X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Fkaro%2Ftx6%2Flowlevel_init.S;h=027db9aa9e25031013e1cc1f24cbdd3692ec4e42;hp=ffdc5e05ced1967f74a59d4929d53c633f9d4afd;hb=5991b7ed19f0a899c6eb97533ca0c8bd9a6fcd81;hpb=0a58072f2c7f304e9cb3914425eb2af8fe597ab9 diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S index ffdc5e05ce..027db9aa9e 100644 --- a/board/karo/tx6/lowlevel_init.S +++ b/board/karo/tx6/lowlevel_init.S @@ -1,5 +1,7 @@ #include +#include #include +#include #include #include @@ -44,6 +46,20 @@ .endm #define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val) +#if PHYS_SDRAM_1_WIDTH == 16 +#define MXC_DCD_ITEM_16(addr, val) mxc_dcd_item (addr), (val) +#define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask) +#else +#define MXC_DCD_ITEM_16(addr, val) +#define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) +#endif +#if PHYS_SDRAM_1_WIDTH > 16 +#define MXC_DCD_ITEM_32(addr, val) mxc_dcd_item (addr), (val) +#define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask) +#else +#define MXC_DCD_ITEM_32(addr, val) +#define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) +#endif #if PHYS_SDRAM_1_WIDTH == 64 #define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item (addr), (val) #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask) @@ -73,6 +89,8 @@ dcd_start: .error "DCD too large!" .endif dcd_end: + .section ".pad" + .section ".text" .endm #define MXC_DCD_CMD_WRT(type, flags) \ @@ -299,11 +317,14 @@ CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 ((PHYS_SDRAM_1_WIDTH / 32) << 16) | \ ((-1) << (32 - BANK_ADDR_BITS))) +#define MDMISC_WALAT(n) (((n) & 3) << 16) +#define MDMISC_RALAT(n) (((n) & 7) << 6) + #define MDMISC_VAL ((ADDR_MIRROR << 19) | \ - (WALAT << 16) | \ + MDMISC_WALAT(WALAT) | \ (BI_ON << 12) | \ (0x3 << 9) | \ - (RALAT << 6) | \ + MDMISC_RALAT(RALAT) | \ (DDR_TYPE << 3)) #define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0)) @@ -315,6 +336,7 @@ CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 (tODTLon << 12) | \ (tODTLoff << 4)) + .section ".ivt" ivt_header: .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40) app_start_addr: @@ -327,30 +349,31 @@ boot_data_ptr: self_ptr: .word ivt_header app_code_csf: +#ifdef CONFIG_SECURE_BOOT + .word __csf_data +#else .word 0x0 +#endif .word 0x0 boot_data: - .long _start + .long CONFIG_SYS_TEXT_BASE image_len: - .long CONFIG_U_BOOT_IMG_SIZE + .long __uboot_img_len plugin: .word 0 ivt_end: #define DCD_VERSION 0x40 -#define CLKCTL_CCGR0 0x68 -#define CLKCTL_CCGR1 0x6c -#define CLKCTL_CCGR2 0x70 -#define CLKCTL_CCGR3 0x74 -#define CLKCTL_CCGR4 0x78 -#define CLKCTL_CCGR5 0x7c -#define CLKCTL_CCGR6 0x80 -#define CLKCTL_CCGR7 0x84 -#define CLKCTL_CMEOR 0x88 - -#define DDR_SEL_VAL 3 -#define DSE_VAL 6 +#define DDR_SEL_VAL 3 /* DDR3 */ +#if PHYS_SDRAM_1_WIDTH == 16 +#define DSE1_VAL 6 /* Drive Strength for DATA lines */ +#define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */ +#else +#define DSE1_VAL 6 /* Drive Strength for DATA lines */ +#define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */ +#endif #define ODT_VAL 2 +#define DDR_PKE_VAL 0 #define DDR_SEL_SHIFT 18 #define DDR_MODE_SHIFT 17 @@ -362,17 +385,19 @@ ivt_end: #define PUS_SHIFT 14 #define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT) -#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT) -#define DSE_MASK (DSE_VAL << DSE_SHIFT) +#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT) /* differential input mode */ +#define DSE1_MASK (DSE1_VAL << DSE_SHIFT) +#define DSE2_MASK (DSE2_VAL << DSE_SHIFT) #define ODT_MASK (ODT_VAL << ODT_SHIFT) +#define DDR_PKE_MASK (DDR_PKE_VAL << PKE_SHIFT) -#define DQM_MASK (DDR_MODE_MASK | DSE_MASK) -#define SDQS_MASK DSE_MASK -#define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) -#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK) +#define DQM_MASK (DDR_MODE_MASK | DSE2_MASK) +#define SDQS_MASK DSE2_MASK +#define SDODT_MASK (DSE2_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) +#define SDCLK_MASK (DDR_MODE_MASK | DSE2_MASK) #define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) -#define DDR_ADDR_MASK 0 -#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK) +#define DDR_ADDR_MASK (ODT_MASK | DDR_MODE_MASK) +#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE2_MASK) #define MMDC1_MDCTL 0x021b0000 #define MMDC1_MDPDC 0x021b0004 @@ -386,7 +411,9 @@ ivt_end: #define MMDC1_MDRWD 0x021b002c #define MMDC1_MDOR 0x021b0030 #define MMDC1_MDASP 0x021b0040 + #define MMDC1_MAPSR 0x021b0404 + #define MMDC1_MPZQHWCTRL 0x021b0800 #define MMDC1_MPWLGCR 0x021b0808 #define MMDC1_MPWLDECTRL0 0x021b080c @@ -419,6 +446,7 @@ ivt_end: #if PHYS_SDRAM_1_WIDTH == 64 #define MMDC2_MDPDC 0x021b4004 + #define MMDC2_MPWLGCR 0x021b4808 #define MMDC2_MPWLDECTRL0 0x021b480c #define MMDC2_MPWLDECTRL1 0x021b4810 @@ -455,15 +483,21 @@ ivt_end: #define MMDC2_MPSWDRDR5 0x021b48ac #define MMDC2_MPSWDRDR6 0x021b48b0 #define MMDC2_MPSWDRDR7 0x021b48b4 +#define MMDC2_MPMUR0 0x021b48b8 #endif -#ifdef CONFIG_MX6Q +#ifdef CONFIG_SOC_MX6Q #define IOMUXC_GPR1 0x020e0004 +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x020e00a0 +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e00a4 +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e00c4 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO16 0x020e0248 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e024c #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e02a8 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x020e02ac #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x020e02c0 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x020e02c4 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 0x020e02c8 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e02d4 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e02d8 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e02dc @@ -480,6 +514,10 @@ ivt_end: #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0310 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e0314 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e0318 + +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 0x020e03b4 +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e03b8 +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e03d8 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x020e050c #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x020e0510 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x020e0514 @@ -524,6 +562,9 @@ ivt_end: #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020e05bc #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x020e05c0 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020e05c4 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO16 0x020e0618 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO17 0x020e061c +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 0x020e06b0 #define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020e0748 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750 @@ -548,17 +589,27 @@ ivt_end: #define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x020e07a0 #define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x020e07a4 #define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x020e07a8 + #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e091c #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920 + +#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0898 +#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e089c +#define TX6_I2C1_SEL_INP_VAL 1 #endif -#ifdef CONFIG_MX6DL +#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S) #define IOMUXC_GPR1 0x020e0004 +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x020e0154 +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e0158 +#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e0174 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO16 0x020e0214 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e0218 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e0330 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x020e032c #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x020e0314 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x020e0318 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 0x020e031c #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e0270 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e026c #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e02a8 @@ -575,6 +626,10 @@ ivt_end: #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0298 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e029c #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e02a0 + +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 0x020e0524 +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e0528 +#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e0544 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x020e04d0 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x020e0484 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x020e0480 @@ -619,11 +674,14 @@ ivt_end: #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020e0488 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x020e04d8 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020e048c +#define IOMUXC_SW_PAD_CTL_PAD_GPIO16 0x020e05e4 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO17 0x020e05e8 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 0x020e0704 #define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020e0748 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e0754 -#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0754 +#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0758 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e075c #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e0760 #define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0784 @@ -635,17 +693,41 @@ ivt_end: #define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x020e07a0 #define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x020e07a4 #define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x020e07a8 + #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e08f8 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e08fc + +#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0868 +#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e086c +#define TX6_I2C1_SEL_INP_VAL 1 #endif dcd_hdr: MXC_DCD_START MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) + /* setup I2C pads for PMIC */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21, 0x00000016) + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28, 0x00000011) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21, 0x0000f079) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28, 0x0000f079) + MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21, TX6_I2C1_SEL_INP_VAL) + MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28, TX6_I2C1_SEL_INP_VAL) + + /* ENET_REF_CLK */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO16, 0x00000012) + /* ETN PHY nRST */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2, 0x00000015) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2, 0x000030b0) + /* ETN PHY Power */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20, 0x00000015) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20, 0x000030b0) /* RESET_OUT GPIO_7_12 */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_GPIO17, 0x000030b0) - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* CS2CDR default: 0x007236c1 */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x007236c1 */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */ MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */ @@ -657,13 +739,16 @@ dcd_hdr: MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */ + MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */ + MXC_DCD_ITEM(0x020c80b0, 0x00065b9a) + MXC_DCD_ITEM(0x020c80c0, 0x000f4240) /* IOMUX: */ MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */ /* UART1 pad config */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7, 0x00000001) /* UART1 TXD */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6, 0x00000001) /* UART1 RXD */ -#ifdef CONFIG_MX6Q +#ifdef CONFIG_SOC_MX6Q MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003) /* UART1 RXD INPUT_SEL */ #else MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000002) /* UART1 RXD INPUT_SEL */ @@ -695,8 +780,8 @@ dcd_hdr: /* DRAM_DQM[0..7] */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK) @@ -739,24 +824,24 @@ dcd_hdr: MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK) /* DRAM_B[0..7]DS */ - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE_MASK) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE_MASK) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK) - MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE_MASK) - MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE_MASK) - MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE_MASK) - MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE1_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE1_MASK) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE1_MASK) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE1_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE1_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE1_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE1_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE1_MASK) /* ADDDS */ - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE2_MASK) /* DDRMODE_CTL */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK) /* DDRPKE */ - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, 0x00000000) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, DDR_PKE_MASK) /* DDRMODE */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK) /* CTLDS */ - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE2_MASK) /* DDR_TYPE */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK) /* DDRPK */ @@ -764,7 +849,7 @@ dcd_hdr: /* DDRHYS */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000) -#ifdef CONFIG_MX6Q +#ifdef CONFIG_SOC_MX6Q /* TERM_CTL[0..7] */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK) @@ -779,8 +864,8 @@ dcd_hdr: /* MPRDDQBY[0..7]DL */ MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333) MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333) - MXC_DCD_ITEM(MMDC1_MPRDDQBY2DL, 0x33333333) - MXC_DCD_ITEM(MMDC1_MPRDDQBY3DL, 0x33333333) + MXC_DCD_ITEM_32(MMDC1_MPRDDQBY2DL, 0x33333333) + MXC_DCD_ITEM_32(MMDC1_MPRDDQBY3DL, 0x33333333) MXC_DCD_ITEM_64(MMDC2_MPRDDQBY0DL, 0x33333333) MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333) MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333) @@ -797,7 +882,11 @@ dcd_hdr: /* MDCTL */ MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL) - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000) +#if BANK_ADDR_BITS > 1 + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, (3 << 30)) +#else + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, (1 << 30)) +#endif MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL) @@ -807,7 +896,6 @@ dcd_hdr: MXC_DCD_ITEM(MMDC1_MDOR, MDOR_VAL) MXC_DCD_ITEM(MMDC1_MDOTC, MDOTC_VAL) MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_0) - MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_0) MXC_DCD_ITEM(MMDC1_MDASP, (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1) /* CS0 MRS: */ @@ -831,7 +919,7 @@ dcd_hdr: /* DDR3 calibration */ MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */ - MXC_DCD_ITEM(MMDC1_MAPSR, 0x00001007) + MXC_DCD_ITEM(MMDC1_MAPSR, 1) /* ZQ calibration */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */ @@ -853,11 +941,18 @@ dcd_hdr: #define WL_DLY_DQS6 (WL_DLY_DQS_VAL + 0) #define WL_DLY_DQS7 (WL_DLY_DQS_VAL + 0) /* Write leveling */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) + MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_RALAT(~0) | MDMISC_WALAT(~0)) /* increase WALAT/RALAT to max. */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) + MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0)) - MXC_DCD_ITEM(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0)) + MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0)) MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0)) MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0)) +#if PHYS_SDRAM_1_WIDTH > 16 +#define DO_DDR_CALIB +#endif /* DQS gating calibration */ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */ #if BANK_ADDR_BITS > 1 @@ -865,52 +960,63 @@ dcd_hdr: #endif MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000) - MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */ MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */ MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */ MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */ - MXC_DCD_ITEM(MMDC1_MPMUR0, 0x00000800) - MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */ - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000) - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) - MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */ - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000) - MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) - MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */ - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10001000) +#define MPMUR_FRC_MSR (1 << 11) + MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR) + MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR) +#ifdef DO_DDR_CALIB + MXC_DCD_ITEM(MMDC1_MPDGCTRL0, (1 << 30) | (1 << 28) | (0 << 23)) /* choose 32 wait cycles and start DQS calib. */ + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_ANY_CLR, MMDC1_MPDGCTRL0, 0x10001000) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) - +#else /* DO_DDR_CALIB */ + MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x41e20160) + MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x014d014f) + MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x014f0150) + MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x0144014a) + MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR) + MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR) +#endif /* DO_DDR_CALIB */ + MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL) /* DRAM_SDQS[0..7] pad config */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK) - +#ifdef DO_DDR_CALIB /* Read delay calibration */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */ MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */ - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f) + MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000013) + MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f) MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) - +#else /* DO_DDR_CALIB */ + MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x4a4f4e4c) + MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x4e50504a) +#endif /* DO_DDR_CALIB */ +#ifdef DO_DDR_CALIB + /* Write delay calibration */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */ - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f) + MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000013) + MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f) #if PHYS_SDRAM_1_WIDTH == 64 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) @@ -919,16 +1025,20 @@ dcd_hdr: MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000001f) #endif MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) - +#else /* DO_DDR_CALIB */ + MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x3f3f3f3f) + MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x3f3f3f3f) + MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR) + MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR) +#endif /* DO_DDR_CALIB */ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ #if BANK_ADDR_BITS > 1 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */ #endif MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b) MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */ - MXC_DCD_ITEM(MMDC1_MAPSR, 0x00001006) + MXC_DCD_ITEM(MMDC1_MAPSR, (16 << 8)) MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1) - MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_1) /* MDSCR: Normal operation */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)