X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Fkaro%2Ftx6%2Flowlevel_init.S;h=39d15ef4c7d057340dd6f5304203458f2a215c57;hp=cca946953965285b7f7eddc107e17e38df46983a;hb=508361f6a6f5faad602de2104718c3f3f70b7145;hpb=d899a6d9a42d3a7682df803c41d4a3c865f78e20;ds=sidebyside

diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S
index cca9469539..39d15ef4c7 100644
--- a/board/karo/tx6/lowlevel_init.S
+++ b/board/karo/tx6/lowlevel_init.S
@@ -28,13 +28,14 @@
 	(((l) >> 8) & 0x0000FF00) |	\
 	(((l) >> 24) & 0x000000FF))
 
-#define CHECK_DCD_ADDR(a)	(			\
+#define CHECK_DCD_ADDR(a)	(					\
 	((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ ||	\
-	((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ ||	\
+	((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ ||		\
 	((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ ||	\
-	((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ ||	\
-	((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ ||	\
+	((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ ||		\
+	((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ ||		\
 	((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ ||	\
+	((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ ||	\
 	((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
 
 	.macro	mxc_dcd_item	addr, val
@@ -434,7 +435,11 @@ ivt_end:
 #define MMDC1_MPWRDLST				0x021b0854
 #define MMDC1_MPRDDLHWCTL			0x021b0860
 #define MMDC1_MPWRDLHWCTL			0x021b0864
+#define MMDC1_MPDGHWST0				0x021b087c
+#define MMDC1_MPDGHWST1				0x021b0880
 #define MMDC1_MPPDCMPR2				0x021b0890
+#define MMDC1_MPDGHWST2				0x021b0884
+#define MMDC1_MPDGHWST3				0x021b0888
 #define MMDC1_MPSWDRDR0				0x021b0898
 #define MMDC1_MPSWDRDR1				0x021b089c
 #define MMDC1_MPSWDRDR2				0x021b08a0
@@ -595,9 +600,7 @@ ivt_end:
 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21	0x020e0898
 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28	0x020e089c
 #define TX6_I2C1_SEL_INP_VAL			0
-#endif
-
-#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
+#elif defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
 #define IOMUXC_GPR1				0x020e0004
 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20	0x020e0154
 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21	0x020e0158
@@ -886,10 +889,10 @@ dcd_hdr:
 	MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
 	MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
 
-	MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x43240334)
-	MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x0324031a)
-	MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x43340344)
-	MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x03280276)
+	MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x42300230)
+	MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x02300230)
+	MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x42300230)
+	MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x02300230)
 
 	MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
 	MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
@@ -972,8 +975,6 @@ dcd_hdr:
 #if BANK_ADDR_BITS > 1
 	MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
 #endif
-
-	MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
 	/* DRAM_SDQS[0..7] pad config */
 	MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
 	MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)