X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Fkaro%2Ftx6%2Ftx6qdl.c;h=15340db196a494ab0abf9a036cae419536b0e1d0;hp=02c6c35a160ff72bfea6a6269e0a07d7c457aebd;hb=dbf41276a92b5f806782033b7444be384ce09658;hpb=2e1f2ce3c03166d5fb46c1828c61f30eb8625d62 diff --git a/board/karo/tx6/tx6qdl.c b/board/karo/tx6/tx6qdl.c index 02c6c35a16..15340db196 100644 --- a/board/karo/tx6/tx6qdl.c +++ b/board/karo/tx6/tx6qdl.c @@ -1,25 +1,19 @@ /* - * Copyright (C) 2012 Lothar Waßmann + * Copyright (C) 2012-2015 Lothar Waßmann * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA */ - #include #include #include @@ -30,22 +24,25 @@ #include #include #include -#include -#include +#include #include +#include #include #include -#include +#include #include #include #include #include #include "../common/karo.h" +#include "pmic.h" + +#define __data __attribute__((section(".data"))) #define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6) #define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20) -#define TX6_FEC_INT_GPIO IMX_GPIO_NR(2, 4) +#define TX6_FEC_INT_GPIO IMX_GPIO_NR(7, 1) #define TX6_LED_GPIO IMX_GPIO_NR(2, 20) #define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31) @@ -54,83 +51,96 @@ #define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12) -#define TEMPERATURE_MIN -40 +#ifdef CONFIG_MX6_TEMPERATURE_MIN +#define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN +#else +#define TEMPERATURE_MIN (-40) +#endif +#ifdef CONFIG_MX6_TEMPERATURE_HOT +#define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT +#else #define TEMPERATURE_HOT 80 -#define TEMPERATURE_MAX 125 +#endif DECLARE_GLOBAL_DATA_PTR; -#define MUX_CFG_SION IOMUX_PAD(0, 0, MUX_CONFIG_SION, 0, 0, 0) +#define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0) -static const iomux_v3_cfg_t tx6qdl_pads[] = { - /* NAND flash pads */ - MX6_PAD_NANDF_CLE__RAWNAND_CLE, - MX6_PAD_NANDF_ALE__RAWNAND_ALE, - MX6_PAD_NANDF_WP_B__RAWNAND_RESETN, - MX6_PAD_NANDF_RB0__RAWNAND_READY0, - MX6_PAD_NANDF_CS0__RAWNAND_CE0N, - MX6_PAD_SD4_CMD__RAWNAND_RDN, - MX6_PAD_SD4_CLK__RAWNAND_WRN, - MX6_PAD_NANDF_D0__RAWNAND_D0, - MX6_PAD_NANDF_D1__RAWNAND_D1, - MX6_PAD_NANDF_D2__RAWNAND_D2, - MX6_PAD_NANDF_D3__RAWNAND_D3, - MX6_PAD_NANDF_D4__RAWNAND_D4, - MX6_PAD_NANDF_D5__RAWNAND_D5, - MX6_PAD_NANDF_D6__RAWNAND_D6, - MX6_PAD_NANDF_D7__RAWNAND_D7, +enum { + MX6_PAD_DECL(GARBAGE, 0, 0, 0, 0, 0, 0) +}; +static const iomux_v3_cfg_t const tx6qdl_pads[] = { + MX6_PAD_GARBAGE, +#ifdef CONFIG_TX6_NAND_ + /* NAND flash pads */ + MX6_PAD_NANDF_CLE__NAND_CLE, + MX6_PAD_NANDF_ALE__NAND_ALE, + MX6_PAD_NANDF_WP_B__NAND_RESETN, + MX6_PAD_NANDF_RB0__NAND_READY0, + MX6_PAD_NANDF_CS0__NAND_CE0N, + MX6_PAD_SD4_CMD__NAND_RDN, + MX6_PAD_SD4_CLK__NAND_WRN, + MX6_PAD_NANDF_D0__NAND_D0, + MX6_PAD_NANDF_D1__NAND_D1, + MX6_PAD_NANDF_D2__NAND_D2, + MX6_PAD_NANDF_D3__NAND_D3, + MX6_PAD_NANDF_D4__NAND_D4, + MX6_PAD_NANDF_D5__NAND_D5, + MX6_PAD_NANDF_D6__NAND_D6, + MX6_PAD_NANDF_D7__NAND_D7, +#endif /* RESET_OUT */ - MX6_PAD_GPIO_17__GPIO_7_12, + MX6_PAD_GPIO_17__GPIO7_IO12, /* UART pads */ #if CONFIG_MXC_UART_BASE == UART1_BASE - MX6_PAD_SD3_DAT7__UART1_TXD, - MX6_PAD_SD3_DAT6__UART1_RXD, - MX6_PAD_SD3_DAT1__UART1_RTS, - MX6_PAD_SD3_DAT0__UART1_CTS, + MX6_PAD_SD3_DAT7__UART1_TX_DATA, + MX6_PAD_SD3_DAT6__UART1_RX_DATA, + MX6_PAD_SD3_DAT1__UART1_RTS_B, + MX6_PAD_SD3_DAT0__UART1_CTS_B, #endif #if CONFIG_MXC_UART_BASE == UART2_BASE - MX6_PAD_SD4_DAT4__UART2_RXD, - MX6_PAD_SD4_DAT7__UART2_TXD, - MX6_PAD_SD4_DAT5__UART2_RTS, - MX6_PAD_SD4_DAT6__UART2_CTS, + MX6_PAD_SD4_DAT4__UART2_RX_DATA, + MX6_PAD_SD4_DAT7__UART2_TX_DATA, + MX6_PAD_SD4_DAT5__UART2_RTS_B, + MX6_PAD_SD4_DAT6__UART2_CTS_B, #endif #if CONFIG_MXC_UART_BASE == UART3_BASE - MX6_PAD_EIM_D24__UART3_TXD, - MX6_PAD_EIM_D25__UART3_RXD, - MX6_PAD_SD3_RST__UART3_RTS, - MX6_PAD_SD3_DAT3__UART3_CTS, + MX6_PAD_EIM_D24__UART3_TX_DATA, + MX6_PAD_EIM_D25__UART3_RX_DATA, + MX6_PAD_SD3_RST__UART3_RTS_B, + MX6_PAD_SD3_DAT3__UART3_CTS_B, #endif /* internal I2C */ MX6_PAD_EIM_D28__I2C1_SDA, MX6_PAD_EIM_D21__I2C1_SCL, /* FEC PHY GPIO functions */ - MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */ - MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */ - MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */ + MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */ + MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */ + MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */ }; -static const iomux_v3_cfg_t tx6qdl_fec_pads[] = { +static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = { /* FEC functions */ MX6_PAD_ENET_MDC__ENET_MDC, MX6_PAD_ENET_MDIO__ENET_MDIO, - MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT, + MX6_PAD_GPIO_16__ENET_REF_CLK, MX6_PAD_ENET_RX_ER__ENET_RX_ER, MX6_PAD_ENET_CRS_DV__ENET_RX_EN, - MX6_PAD_ENET_RXD1__ENET_RDATA_1, - MX6_PAD_ENET_RXD0__ENET_RDATA_0, + MX6_PAD_ENET_RXD1__ENET_RX_DATA1, + MX6_PAD_ENET_RXD0__ENET_RX_DATA0, MX6_PAD_ENET_TX_EN__ENET_TX_EN, - MX6_PAD_ENET_TXD1__ENET_TDATA_1, - MX6_PAD_ENET_TXD0__ENET_TDATA_0, + MX6_PAD_ENET_TXD1__ENET_TX_DATA1, + MX6_PAD_ENET_TXD0__ENET_TX_DATA0, }; -static const struct gpio tx6qdl_gpios[] = { - { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", }, - { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, - { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", }, - { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, +static const struct gpio const tx6qdl_gpios[] = { + { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", }, + { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, + { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", }, + { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", }, }; /* @@ -197,10 +207,9 @@ static void print_reset_cause(void) printf("\n"); } -int read_cpu_temperature(void); -int check_cpu_temperature(int boot); +static const char __data *tx6_mod_suffix; -static void print_cpuinfo(void) +static void tx6qdl_print_cpuinfo(void) { u32 cpurev = get_cpu_rev(); char *cpu_str = "?"; @@ -208,15 +217,19 @@ static void print_cpuinfo(void) switch ((cpurev >> 12) & 0xff) { case MXC_CPU_MX6SL: cpu_str = "SL"; + tx6_mod_suffix = "?"; break; case MXC_CPU_MX6DL: cpu_str = "DL"; + tx6_mod_suffix = "U"; break; case MXC_CPU_MX6SOLO: cpu_str = "SOLO"; + tx6_mod_suffix = "S"; break; case MXC_CPU_MX6Q: cpu_str = "Q"; + tx6_mod_suffix = "Q"; break; } @@ -227,75 +240,9 @@ static void print_cpuinfo(void) mxc_get_clock(MXC_ARM_CLK) / 1000000); print_reset_cause(); +#ifdef CONFIG_MX6_TEMPERATURE_HOT check_cpu_temperature(1); -} - -#define LTC3676_DVB2A 0x0C -#define LTC3676_DVB2B 0x0D -#define LTC3676_DVB4A 0x10 -#define LTC3676_DVB4B 0x11 - -#define VDD_SOC_mV (1375 + 50) -#define VDD_CORE_mV (1375 + 50) - -#define mV_to_regval(mV) (((mV) * 360 / 330 - 825 + 1) / 25) -#define regval_to_mV(v) (((v) * 25 + 825) * 330 / 360) - -static int setup_pmic_voltages(void) -{ - int ret; - unsigned char value; - - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - ret = i2c_probe(CONFIG_SYS_I2C_SLAVE); - if (ret != 0) { - printf("Failed to initialize I2C\n"); - return ret; - } - - ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1); - if (ret) { - printf("%s: i2c_read error: %d\n", __func__, ret); - return ret; - } - - /* VDDCORE/VDDSOC default 1.375V is not enough, considering - pfuze tolerance and IR drop and ripple, need increase - to 1.425V for SabreSD */ - - value = 0x39; /* VB default value & PGOOD not forced when slewing */ - ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2B, 1, &value, 1); - if (ret) { - printf("%s: failed to write PMIC DVB2B register: %d\n", - __func__, ret); - return ret; - } - ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4B, 1, &value, 1); - if (ret) { - printf("%s: failed to write PMIC DVB4B register: %d\n", - __func__, ret); - return ret; - } - - value = mV_to_regval(VDD_SOC_mV); - ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2A, 1, &value, 1); - if (ret) { - printf("%s: failed to write PMIC DVB2A register: %d\n", - __func__, ret); - return ret; - } - printf("VDDSOC set to %dmV\n", regval_to_mV(value)); - - value = mV_to_regval(VDD_CORE_mV); - ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4A, 1, &value, 1); - if (ret) { - printf("%s: failed to write PMIC DVB4A register: %d\n", - __func__, ret); - return ret; - } - printf("VDDCORE set to %dmV\n", regval_to_mV(value)); - return 0; +#endif } int board_early_init_f(void) @@ -306,18 +253,32 @@ int board_early_init_f(void) return 0; } +#ifndef CONFIG_MX6_TEMPERATURE_HOT +static bool tx6_temp_check_enabled = true; +#else +#define tx6_temp_check_enabled 0 +#endif + int board_init(void) { int ret; /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000; -#ifdef CONFIG_OF_LIBFDT gd->bd->bi_arch_number = -1; -#else - gd->bd->bi_arch_number = 4429; + + if (ctrlc() || (wrsr & WRSR_TOUT)) { + if (wrsr & WRSR_TOUT) + printf("WDOG RESET detected; Skipping PMIC setup\n"); + else + printf(" detected; safeboot enabled\n"); +#ifndef CONFIG_MX6_TEMPERATURE_HOT + tx6_temp_check_enabled = false; #endif - ret = setup_pmic_voltages(); + return 1; + } + + ret = tx6_pmic_init(); if (ret) { printf("Failed to setup PMIC voltages\n"); hang(); @@ -346,43 +307,73 @@ void dram_init_banksize(void) } #ifdef CONFIG_CMD_MMC +#define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST) + static const iomux_v3_cfg_t mmc0_pads[] = { - MX6_PAD_SD1_CMD__USDHC1_CMD, - MX6_PAD_SD1_CLK__USDHC1_CLK, - MX6_PAD_SD1_DAT0__USDHC1_DAT0, - MX6_PAD_SD1_DAT1__USDHC1_DAT1, - MX6_PAD_SD1_DAT2__USDHC1_DAT2, - MX6_PAD_SD1_DAT3__USDHC1_DAT3, + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL), /* SD1 CD */ - MX6_PAD_SD3_CMD__GPIO_7_2, + MX6_PAD_SD3_CMD__GPIO7_IO02, }; static const iomux_v3_cfg_t mmc1_pads[] = { - MX6_PAD_SD2_CMD__USDHC2_CMD, - MX6_PAD_SD2_CLK__USDHC2_CLK, - MX6_PAD_SD2_DAT0__USDHC2_DAT0, - MX6_PAD_SD2_DAT1__USDHC2_DAT1, - MX6_PAD_SD2_DAT2__USDHC2_DAT2, - MX6_PAD_SD2_DAT3__USDHC2_DAT3, + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL), /* SD2 CD */ - MX6_PAD_SD3_CLK__GPIO_7_3, + MX6_PAD_SD3_CLK__GPIO7_IO03, +}; + +#ifdef CONFIG_TX6_EMMC +static const iomux_v3_cfg_t mmc3_pads[] = { + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL), + /* eMMC RESET */ + MX6_PAD_NANDF_ALE__SD4_RESET, }; +#endif -static struct tx6q_esdhc_cfg { +static struct tx6_esdhc_cfg { const iomux_v3_cfg_t *pads; int num_pads; enum mxc_clock clkid; struct fsl_esdhc_cfg cfg; + int cd_gpio; } tx6qdl_esdhc_cfg[] = { +#ifdef CONFIG_TX6_EMMC + { + .pads = mmc3_pads, + .num_pads = ARRAY_SIZE(mmc3_pads), + .clkid = MXC_ESDHC4_CLK, + .cfg = { + .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR, + .max_bus_width = 4, + }, + .cd_gpio = -EINVAL, + }, +#endif { .pads = mmc0_pads, .num_pads = ARRAY_SIZE(mmc0_pads), .clkid = MXC_ESDHC_CLK, .cfg = { .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR, - .cd_gpio = IMX_GPIO_NR(7, 2), - .wp_gpio = -EINVAL, + .max_bus_width = 4, }, + .cd_gpio = IMX_GPIO_NR(7, 2), }, { .pads = mmc1_pads, @@ -390,29 +381,28 @@ static struct tx6q_esdhc_cfg { .clkid = MXC_ESDHC2_CLK, .cfg = { .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR, - .cd_gpio = IMX_GPIO_NR(7, 3), - .wp_gpio = -EINVAL, + .max_bus_width = 4, }, + .cd_gpio = IMX_GPIO_NR(7, 3), }, }; -static inline struct tx6q_esdhc_cfg *to_tx6q_esdhc_cfg(struct fsl_esdhc_cfg *cfg) +static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg) { - void *p = cfg; - - return p - offsetof(struct tx6q_esdhc_cfg, cfg); + return container_of(cfg, struct tx6_esdhc_cfg, cfg); } int board_mmc_getcd(struct mmc *mmc) { - struct fsl_esdhc_cfg *cfg = mmc->priv; + struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv); if (cfg->cd_gpio < 0) - return cfg->cd_gpio; + return 1; - debug("SD card %d is %spresent\n", - to_tx6q_esdhc_cfg(cfg) - tx6qdl_esdhc_cfg, - gpio_get_value(cfg->cd_gpio) ? "NOT " : ""); + debug("SD card %d is %spresent (GPIO %d)\n", + cfg - tx6qdl_esdhc_cfg, + gpio_get_value(cfg->cd_gpio) ? "NOT " : "", + cfg->cd_gpio); return !gpio_get_value(cfg->cd_gpio); } @@ -422,22 +412,29 @@ int board_mmc_init(bd_t *bis) for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) { struct mmc *mmc; - struct fsl_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i].cfg; - - if (i >= CONFIG_SYS_FSL_ESDHC_NUM) - break; - - cfg->sdhc_clk = mxc_get_clock(tx6qdl_esdhc_cfg[i].clkid); - imx_iomux_v3_setup_multiple_pads(tx6qdl_esdhc_cfg[i].pads, - tx6qdl_esdhc_cfg[i].num_pads); + struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i]; + int ret; + + cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid); + imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads); + + if (cfg->cd_gpio >= 0) { + ret = gpio_request_one(cfg->cd_gpio, + GPIOFLAG_INPUT, "MMC CD"); + if (ret) { + printf("Error %d requesting GPIO%d_%d\n", + ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32); + continue; + } + } debug("%s: Initializing MMC slot %d\n", __func__, i); - fsl_esdhc_initialize(bis, cfg); + fsl_esdhc_initialize(bis, &cfg->cfg); mmc = find_mmc_device(i); if (mmc == NULL) continue; - if (board_mmc_getcd(mmc) > 0) + if (board_mmc_getcd(mmc)) mmc_init(mmc); } return 0; @@ -462,7 +459,8 @@ int board_eth_init(bd_t *bis) /* delay at least 21ms for the PHY internal POR signal to deassert */ udelay(22000); - imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads)); + imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, + ARRAY_SIZE(tx6qdl_fec_pads)); /* Deassert RESET to the external phy */ gpio_set_value(TX6_FEC_RST_GPIO, 1); @@ -473,6 +471,24 @@ int board_eth_init(bd_t *bis) return ret; } + +static void tx6_init_mac(void) +{ + u8 mac[ETH_ALEN]; + + imx_get_mac_from_fuse(-1, mac); + if (!is_valid_ether_addr(mac)) { + printf("No valid MAC address programmed\n"); + return; + } + + printf("MAC addr from fuse: %pM\n", mac); + eth_setenv_enetaddr("ethaddr", mac); +} +#else +static inline void tx6_init_mac(void) +{ +} #endif /* CONFIG_FEC_MXC */ enum { @@ -481,10 +497,13 @@ enum { LED_STATE_ON, }; -static inline int calc_blink_rate(int tmp) +static inline int calc_blink_rate(void) { + if (!tx6_temp_check_enabled) + return CONFIG_SYS_HZ; + return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 - - (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ / + (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ / (TEMPERATURE_HOT - TEMPERATURE_MIN); } @@ -498,10 +517,10 @@ void show_activity(int arg) last = get_timer(0); gpio_set_value(TX6_LED_GPIO, 1); led_state = LED_STATE_ON; - blink_rate = calc_blink_rate(check_cpu_temperature(0)); + blink_rate = calc_blink_rate(); } else { if (get_timer(last) > blink_rate) { - blink_rate = calc_blink_rate(check_cpu_temperature(0)); + blink_rate = calc_blink_rate(); last = get_timer_masked(); if (led_state == LED_STATE_ON) { gpio_set_value(TX6_LED_GPIO, 0); @@ -515,79 +534,52 @@ void show_activity(int arg) static const iomux_v3_cfg_t stk5_pads[] = { /* SW controlled LED on STK5 baseboard */ - MX6_PAD_EIM_A18__GPIO_2_20, - - /* LCD data pins */ - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */ - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */ - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */ - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */ + MX6_PAD_EIM_A18__GPIO2_IO20, /* I2C bus on DIMM pins 40/41 */ MX6_PAD_GPIO_6__I2C3_SDA, MX6_PAD_GPIO_3__I2C3_SCL, /* TSC200x PEN IRQ */ - MX6_PAD_EIM_D26__GPIO_3_26, + MX6_PAD_EIM_D26__GPIO3_IO26, /* EDT-FT5x06 Polytouch panel */ - MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */ - MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */ - MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */ + MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */ + MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */ + MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */ /* USBH1 */ - MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */ - MX6_PAD_EIM_D30__GPIO_3_30, /* OC */ + MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */ + MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */ /* USBOTG */ - MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */ - MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */ - MX6_PAD_GPIO_8__GPIO_1_8, /* OC */ + MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */ + MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */ + MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */ }; static const struct gpio stk5_gpios[] = { - { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, + { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, - { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", }, - { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", }, - { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", }, - { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", }, - { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, + { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", }, + { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", }, + { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", }, + { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", }, + { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, }; #ifdef CONFIG_LCD +static u16 tx6_cmap[256]; vidinfo_t panel_info = { /* set to max. size supported by SoC */ .vl_col = 1920, .vl_row = 1080, - .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .cmap = tx6_cmap, }; static struct fb_videomode tx6_fb_modes[] = { +#ifndef CONFIG_SYS_LVDS_IF { /* Standard VGA timing */ .name = "VGA", @@ -706,6 +698,42 @@ static struct fb_videomode tx6_fb_modes[] = { .lower_margin = 525 - 480 - 35, .sync = FB_SYNC_CLK_LAT_FALL, }, + { + /* Emerging ET070001DM6 800 x 480 display. + * 152.4 mm x 91.44 mm display area. + */ + .name = "ET070001DM6", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .sync = 0, + }, +#else + { + /* HannStar HSD100PXN1 + * 202.7m mm x 152.06 mm display area. + */ + .name = "HSD100PXN1", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = KHZ2PICOS(65000), + .left_margin = 0, + .hsync_len = 0, + .right_margin = 320, + .upper_margin = 0, + .vsync_len = 0, + .lower_margin = 38, + .sync = FB_SYNC_CLK_LAT_FALL, + }, +#endif { /* unnamed entry for assigning parameters parsed from 'video_mode' string */ .refresh = 60, @@ -720,6 +748,12 @@ static struct fb_videomode tx6_fb_modes[] = { }; static int lcd_enabled = 1; +static int lcd_bl_polarity; + +static int lcd_backlight_polarity(void) +{ + return lcd_bl_polarity; +} void lcd_enable(void) { @@ -731,72 +765,96 @@ void lcd_enable(void) lcd_is_enabled = 0; karo_load_splashimage(1); + if (lcd_enabled) { debug("Switching LCD on\n"); gpio_set_value(TX6_LCD_PWR_GPIO, 1); udelay(100); gpio_set_value(TX6_LCD_RST_GPIO, 1); udelay(300000); - gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 0); + gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, + lcd_backlight_polarity()); + } +} + +void lcd_disable(void) +{ + if (lcd_enabled) { + printf("Disabling LCD\n"); + ipuv3_fb_shutdown(); + } +} + +void lcd_panel_disable(void) +{ + if (lcd_enabled) { + debug("Switching LCD off\n"); + gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, + !lcd_backlight_polarity()); + gpio_set_value(TX6_LCD_RST_GPIO, 0); + gpio_set_value(TX6_LCD_PWR_GPIO, 0); } } static const iomux_v3_cfg_t stk5_lcd_pads[] = { /* LCD RESET */ - MX6_PAD_EIM_D29__GPIO_3_29, + MX6_PAD_EIM_D29__GPIO3_IO29, /* LCD POWER_ENABLE */ - MX6_PAD_EIM_EB3__GPIO_2_31, + MX6_PAD_EIM_EB3__GPIO2_IO31, /* LCD Backlight (PWM) */ - MX6_PAD_GPIO_1__GPIO_1_1, + MX6_PAD_GPIO_1__GPIO1_IO01, +#ifndef CONFIG_SYS_LVDS_IF /* Display */ - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */ + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */ + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */ + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */ +#endif }; static const struct gpio stk5_lcd_gpios[] = { - { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, - { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, - { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, + { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", }, + { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", }, + { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, }; void lcd_ctrl_init(void *lcdbase) { int color_depth = 24; - char *vm; + const char *video_mode = karo_get_vmode(getenv("video_mode")); + const char *vm; unsigned long val; int refresh = 60; struct fb_videomode *p = &tx6_fb_modes[0]; struct fb_videomode fb_mode; int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0; - int pix_fmt = 0; - ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3; + int pix_fmt; + int lcd_bus_width; unsigned long di_clk_rate = 65000000; if (!lcd_enabled) { @@ -804,28 +862,34 @@ void lcd_ctrl_init(void *lcdbase) return; } - if (tstc() || (wrsr & WRSR_TOUT)) { + if (had_ctrlc() || (wrsr & WRSR_TOUT)) { debug("Disabling LCD\n"); lcd_enabled = 0; + setenv("splashimage", NULL); return; } karo_fdt_move_fdt(); + lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt); - vm = getenv("video_mode"); - if (vm == NULL) { + if (video_mode == NULL) { debug("Disabling LCD\n"); lcd_enabled = 0; return; } - if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) { + vm = video_mode; + if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) { p = &fb_mode; debug("Using video mode from FDT\n"); vm += strlen(vm); - if (fb_mode.xres < panel_info.vl_col) - panel_info.vl_col = fb_mode.xres; - if (fb_mode.yres < panel_info.vl_row) - panel_info.vl_row = fb_mode.yres; + if (fb_mode.xres > panel_info.vl_col || + fb_mode.yres > panel_info.vl_row) { + printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n", + fb_mode.xres, fb_mode.yres, + panel_info.vl_col, panel_info.vl_row); + lcd_enabled = 0; + return; + } } if (p->name != NULL) debug("Trying compiled-in video modes\n"); @@ -859,8 +923,9 @@ void lcd_ctrl_init(void *lcdbase) yres_set = 1; } else if (!bpp_set) { switch (val) { + case 32: case 24: - if (pix_fmt == IPU_PIX_FMT_LVDS666) + if (is_lvds()) pix_fmt = IPU_PIX_FMT_LVDS888; /* fallthru */ case 16: @@ -869,7 +934,7 @@ void lcd_ctrl_init(void *lcdbase) break; case 18: - if (pix_fmt == IPU_PIX_FMT_LVDS666) { + if (is_lvds()) { color_depth = val; break; } @@ -902,19 +967,6 @@ void lcd_ctrl_init(void *lcdbase) break; default: - if (!pix_fmt) { - char *tmp; - - if (strncmp(vm, "LVDS", 4) == 0) { - pix_fmt = IPU_PIX_FMT_LVDS666; - di_clk_parent = DI_PCLK_LDB; - } else { - pix_fmt = IPU_PIX_FMT_RGB24; - } - tmp = strchr(vm, ':'); - if (tmp) - vm = tmp; - } if (*vm != '\0') vm++; } @@ -929,37 +981,105 @@ void lcd_ctrl_init(void *lcdbase) printf("\n"); return; } + if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) { + printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n", + p->xres, p->yres, panel_info.vl_col, panel_info.vl_row); + lcd_enabled = 0; + return; + } + panel_info.vl_col = p->xres; + panel_info.vl_row = p->yres; + + switch (color_depth) { + case 8: + panel_info.vl_bpix = LCD_COLOR8; + break; + case 16: + panel_info.vl_bpix = LCD_COLOR16; + break; + default: + panel_info.vl_bpix = LCD_COLOR32; + } p->pixclock = KHZ2PICOS(refresh * (p->xres + p->left_margin + p->right_margin + p->hsync_len) * - (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) - / 1000); + (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) / + 1000); debug("Pixel clock set to %lu.%03lu MHz\n", - PICOS2KHZ(p->pixclock) / 1000, - PICOS2KHZ(p->pixclock) % 1000); + PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000); + + if (p != &fb_mode) { + int ret; + + debug("Creating new display-timing node from '%s'\n", + video_mode); + ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p); + if (ret) + printf("Failed to create new display-timing node from '%s': %d\n", + video_mode, ret); + } gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios)); imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads)); - debug("Initializing FB driver\n"); - if (!pix_fmt) - pix_fmt = IPU_PIX_FMT_RGB24; - else if (pix_fmt == IPU_PIX_FMT_LVDS666) { - writel(0x01, IOMUXC_BASE_ADDR + 8); - } else if (pix_fmt == IPU_PIX_FMT_LVDS888) { - writel(0x21, IOMUXC_BASE_ADDR + 8); - } - if (pix_fmt != IPU_PIX_FMT_RGB24) { - struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - /* enable LDB & DI0 clock */ - writel(readl(&ccm_regs->CCGR3) | (3 << 12) | (3 << 2), - &ccm_regs->CCGR3); + lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24); + switch (lcd_bus_width) { + case 24: + pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24; + break; + + case 18: + pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666; + break; + + case 16: + if (!is_lvds()) { + pix_fmt = IPU_PIX_FMT_RGB565; + break; + } + /* fallthru */ + default: + lcd_enabled = 0; + printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD", + lcd_bus_width); + return; } + if (is_lvds()) { + int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0); + int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt); + uint32_t gpr2; + uint32_t gpr3; + + if (lvds_chan_mask == 0) { + printf("No LVDS channel active\n"); + lcd_enabled = 0; + return; + } + gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8); + if (lcd_bus_width == 24) + gpr2 |= (1 << 5) | (1 << 7); + gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0; + gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0; + debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8); + writel(gpr2, IOMUXC_BASE_ADDR + 8); + + gpr3 = readl(IOMUXC_BASE_ADDR + 0xc); + gpr3 &= ~((3 << 8) | (3 << 6)); + writel(gpr3, IOMUXC_BASE_ADDR + 0xc); + } if (karo_load_splashimage(0) == 0) { + int ret; + debug("Initializing LCD controller\n"); - ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1); + ret = ipuv3_fb_init(p, 0, pix_fmt, + is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3, + di_clk_rate, -1); + if (ret) { + printf("Failed to initialize FB driver: %d\n", ret); + lcd_enabled = 0; + } } else { debug("Skipping initialization of LCD controller\n"); } @@ -983,46 +1103,30 @@ static void stk5v5_board_init(void) { stk5_board_init(); - gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH, + gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH, "Flexcan Transceiver"); - imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21); + imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21); } static void tx6qdl_set_cpu_clock(void) { unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0); - if (tstc() || (wrsr & WRSR_TOUT)) - return; - if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000) return; + if (had_ctrlc() || (wrsr & WRSR_TOUT)) { + printf("%s detected; skipping cpu clock change\n", + (wrsr & WRSR_TOUT) ? "WDOG RESET" : ""); + return; + } if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) { cpu_clk = mxc_get_clock(MXC_ARM_CLK); printf("CPU clock set to %lu.%03lu MHz\n", cpu_clk / 1000000, cpu_clk / 1000 % 1000); } else { - printf("Failed to set CPU clock to %lu MHz\n", cpu_clk); - } -} - -static void tx6_init_mac(void) -{ - u8 mac[ETH_ALEN]; - char mac_str[ETH_ALEN * 3] = ""; - - imx_get_mac_from_fuse(-1, mac); - if (!is_valid_ether_addr(mac)) { - printf("No valid MAC address programmed\n"); - return; + printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk); } - - snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - setenv("ethaddr", mac_str); - printf("MAC addr from fuse: %02x:%02x:%02x:%02x:%02x:%02x\n", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); } int board_late_init(void) @@ -1030,8 +1134,19 @@ int board_late_init(void) int ret = 0; const char *baseboard; + env_cleanup(); + + if (tx6_temp_check_enabled) + check_cpu_temperature(1); + tx6qdl_set_cpu_clock(); - karo_fdt_move_fdt(); + + if (had_ctrlc()) + setenv_ulong("safeboot", 1); + else if (wrsr & WRSR_TOUT) + setenv_ulong("wdreset", 1); + else + karo_fdt_move_fdt(); baseboard = getenv("baseboard"); if (!baseboard) @@ -1044,6 +1159,13 @@ int board_late_init(void) strcmp(baseboard, "stk5-v3") == 0) { stk5v3_board_init(); } else if (strcmp(baseboard, "stk5-v5") == 0) { + const char *otg_mode = getenv("otg_mode"); + + if (otg_mode && strcmp(otg_mode, "host") == 0) { + printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n", + otg_mode, baseboard); + setenv("otg_mode", "none"); + } stk5v5_board_init(); } else { printf("WARNING: Unsupported STK5 board rev.: %s\n", @@ -1059,20 +1181,89 @@ exit: tx6_init_mac(); gpio_set_value(TX6_RESET_OUT_GPIO, 1); + clear_ctrlc(); return ret; } +#ifdef CONFIG_TX6_NAND +#define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1) +#else +#ifdef CONFIG_MMC_BOOT_SIZE +#define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 4096 + 2) +#else +#define TX6_FLASH_SZ 2 +#endif +#endif /* CONFIG_TX6_NAND */ + +#define TX6_DDR_SZ (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1) + +static char tx6_mem_table[] = { + '4', /* 256MiB SDRAM 16bit; 128MiB NAND */ + '1', /* 512MiB SDRAM 32bit; 128MiB NAND */ + '0', /* 1GiB SDRAM 64bit; 128MiB NAND */ + '?', /* 256MiB SDRAM 16bit; 256MiB NAND */ + '?', /* 512MiB SDRAM 32bit; 256MiB NAND */ + '2', /* 1GiB SDRAM 64bit; 256MiB NAND */ + '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */ + '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */ + '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */ + '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */ + '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */ + '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */ +}; + +static inline char tx6_mem_suffix(void) +{ + size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ; + + debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n", + TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx); + + if (mem_idx >= ARRAY_SIZE(tx6_mem_table)) + return '?'; + + return tx6_mem_table[mem_idx]; +}; + +static struct { + uchar addr; + uchar rev; +} tx6_mod_revs[] = { + { 0x3c, 1, }, + { 0x32, 2, }, + { 0x33, 3, }, +}; + +static int tx6_get_mod_rev(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) { + int ret = i2c_probe(tx6_mod_revs[i].addr); + if (ret == 0) { + debug("I2C probe succeeded for addr %02x\n", tx6_mod_revs[i].addr); + return tx6_mod_revs[i].rev; + } + debug("I2C probe returned %d for addr %02x\n", ret, + tx6_mod_revs[i].addr); + } + return 0; +} + int checkboard(void) { u32 cpurev = get_cpu_rev(); int cpu_variant = (cpurev >> 12) & 0xff; - print_cpuinfo(); + tx6qdl_print_cpuinfo(); - printf("Board: Ka-Ro TX6%c-%dxx%d\n", - cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U', + i2c_init(CONFIG_SYS_I2C_SPEED, 0 /* unused */); + + printf("Board: Ka-Ro TX6%s-%d%d%d%c\n", + tx6_mod_suffix, cpu_variant == MXC_CPU_MX6Q ? 1 : 8, - 1 - PHYS_SDRAM_1_WIDTH / 64); + is_lvds(), tx6_get_mod_rev(), + tx6_mem_suffix()); return 0; } @@ -1080,8 +1271,8 @@ int checkboard(void) #ifdef CONFIG_SERIAL_TAG void get_board_serial(struct tag_serialnr *serialnr) { - struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; - struct fuse_bank0_regs *fuse = (void *)iim->bank[0].fuse_regs; + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs; serialnr->low = readl(&fuse->cfg0); serialnr->high = readl(&fuse->cfg1); @@ -1092,33 +1283,44 @@ void get_board_serial(struct tag_serialnr *serialnr) #ifdef CONFIG_FDT_FIXUP_PARTITIONS #include #include -struct node_info nodes[] = { +static struct node_info nodes[] = { { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, }; - #else #define fdt_fixup_mtdparts(b,n,c) do { } while (0) #endif -static void tx6qdl_fixup_flexcan(void *blob) +static const char *tx6_touchpanels[] = { + "ti,tsc2007", + "edt,edt-ft5x06", + "eeti,egalax_ts", +}; + +int ft_board_setup(void *blob, bd_t *bd) { const char *baseboard = getenv("baseboard"); + int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0); + const char *video_mode = karo_get_vmode(getenv("video_mode")); + int ret; - if (baseboard && strcmp(baseboard, "stk5-v5") == 0) - return; - - karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02090000, "transceiver-switch"); - karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02094000, "transceiver-switch"); -} + ret = fdt_increase_size(blob, 4096); + if (ret) { + printf("Failed to increase FDT size: %s\n", fdt_strerror(ret)); + return ret; + } + if (stk5_v5) + karo_fdt_enable_node(blob, "stk5led", 0); -void ft_board_setup(void *blob, bd_t *bd) -{ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); fdt_fixup_ethernet(blob); - karo_fdt_fixup_touchpanel(blob); - karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy"); - tx6qdl_fixup_flexcan(blob); - karo_fdt_update_fb_mode(blob, getenv("video_mode")); + karo_fdt_fixup_touchpanel(blob, tx6_touchpanels, + ARRAY_SIZE(tx6_touchpanels)); + karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply"); + karo_fdt_fixup_flexcan(blob, stk5_v5); + + karo_fdt_update_fb_mode(blob, video_mode); + + return 0; } -#endif +#endif /* CONFIG_OF_BOARD_SETUP */