X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Fkaro%2Ftx6%2Ftx6qdl.c;h=15340db196a494ab0abf9a036cae419536b0e1d0;hp=08dd9dd2a549cc81ddd431120283551591a19d06;hb=dbf41276a92b5f806782033b7444be384ce09658;hpb=dcd0b15449e1811dd1b9f2fda01e29392e494fcb diff --git a/board/karo/tx6/tx6qdl.c b/board/karo/tx6/tx6qdl.c index 08dd9dd2a5..15340db196 100644 --- a/board/karo/tx6/tx6qdl.c +++ b/board/karo/tx6/tx6qdl.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012,2013 Lothar Waßmann + * Copyright (C) 2012-2015 Lothar Waßmann * * See file CREDITS for list of people who contributed to this * project. @@ -14,7 +14,6 @@ * GNU General Public License for more details. * */ - #include #include #include @@ -37,10 +36,13 @@ #include #include "../common/karo.h" +#include "pmic.h" + +#define __data __attribute__((section(".data"))) #define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6) #define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20) -#define TX6_FEC_INT_GPIO IMX_GPIO_NR(2, 4) +#define TX6_FEC_INT_GPIO IMX_GPIO_NR(7, 1) #define TX6_LED_GPIO IMX_GPIO_NR(2, 20) #define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31) @@ -49,83 +51,96 @@ #define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12) -#define TEMPERATURE_MIN -40 +#ifdef CONFIG_MX6_TEMPERATURE_MIN +#define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN +#else +#define TEMPERATURE_MIN (-40) +#endif +#ifdef CONFIG_MX6_TEMPERATURE_HOT +#define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT +#else #define TEMPERATURE_HOT 80 -#define TEMPERATURE_MAX 125 +#endif DECLARE_GLOBAL_DATA_PTR; #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0) -static const iomux_v3_cfg_t tx6qdl_pads[] = { - /* NAND flash pads */ - MX6_PAD_NANDF_CLE__RAWNAND_CLE, - MX6_PAD_NANDF_ALE__RAWNAND_ALE, - MX6_PAD_NANDF_WP_B__RAWNAND_RESETN, - MX6_PAD_NANDF_RB0__RAWNAND_READY0, - MX6_PAD_NANDF_CS0__RAWNAND_CE0N, - MX6_PAD_SD4_CMD__RAWNAND_RDN, - MX6_PAD_SD4_CLK__RAWNAND_WRN, - MX6_PAD_NANDF_D0__RAWNAND_D0, - MX6_PAD_NANDF_D1__RAWNAND_D1, - MX6_PAD_NANDF_D2__RAWNAND_D2, - MX6_PAD_NANDF_D3__RAWNAND_D3, - MX6_PAD_NANDF_D4__RAWNAND_D4, - MX6_PAD_NANDF_D5__RAWNAND_D5, - MX6_PAD_NANDF_D6__RAWNAND_D6, - MX6_PAD_NANDF_D7__RAWNAND_D7, +enum { + MX6_PAD_DECL(GARBAGE, 0, 0, 0, 0, 0, 0) +}; +static const iomux_v3_cfg_t const tx6qdl_pads[] = { + MX6_PAD_GARBAGE, +#ifdef CONFIG_TX6_NAND_ + /* NAND flash pads */ + MX6_PAD_NANDF_CLE__NAND_CLE, + MX6_PAD_NANDF_ALE__NAND_ALE, + MX6_PAD_NANDF_WP_B__NAND_RESETN, + MX6_PAD_NANDF_RB0__NAND_READY0, + MX6_PAD_NANDF_CS0__NAND_CE0N, + MX6_PAD_SD4_CMD__NAND_RDN, + MX6_PAD_SD4_CLK__NAND_WRN, + MX6_PAD_NANDF_D0__NAND_D0, + MX6_PAD_NANDF_D1__NAND_D1, + MX6_PAD_NANDF_D2__NAND_D2, + MX6_PAD_NANDF_D3__NAND_D3, + MX6_PAD_NANDF_D4__NAND_D4, + MX6_PAD_NANDF_D5__NAND_D5, + MX6_PAD_NANDF_D6__NAND_D6, + MX6_PAD_NANDF_D7__NAND_D7, +#endif /* RESET_OUT */ - MX6_PAD_GPIO_17__GPIO_7_12, + MX6_PAD_GPIO_17__GPIO7_IO12, /* UART pads */ #if CONFIG_MXC_UART_BASE == UART1_BASE - MX6_PAD_SD3_DAT7__UART1_TXD, - MX6_PAD_SD3_DAT6__UART1_RXD, - MX6_PAD_SD3_DAT1__UART1_RTS, - MX6_PAD_SD3_DAT0__UART1_CTS, + MX6_PAD_SD3_DAT7__UART1_TX_DATA, + MX6_PAD_SD3_DAT6__UART1_RX_DATA, + MX6_PAD_SD3_DAT1__UART1_RTS_B, + MX6_PAD_SD3_DAT0__UART1_CTS_B, #endif #if CONFIG_MXC_UART_BASE == UART2_BASE - MX6_PAD_SD4_DAT4__UART2_RXD, - MX6_PAD_SD4_DAT7__UART2_TXD, - MX6_PAD_SD4_DAT5__UART2_RTS, - MX6_PAD_SD4_DAT6__UART2_CTS, + MX6_PAD_SD4_DAT4__UART2_RX_DATA, + MX6_PAD_SD4_DAT7__UART2_TX_DATA, + MX6_PAD_SD4_DAT5__UART2_RTS_B, + MX6_PAD_SD4_DAT6__UART2_CTS_B, #endif #if CONFIG_MXC_UART_BASE == UART3_BASE - MX6_PAD_EIM_D24__UART3_TXD, - MX6_PAD_EIM_D25__UART3_RXD, - MX6_PAD_SD3_RST__UART3_RTS, - MX6_PAD_SD3_DAT3__UART3_CTS, + MX6_PAD_EIM_D24__UART3_TX_DATA, + MX6_PAD_EIM_D25__UART3_RX_DATA, + MX6_PAD_SD3_RST__UART3_RTS_B, + MX6_PAD_SD3_DAT3__UART3_CTS_B, #endif /* internal I2C */ MX6_PAD_EIM_D28__I2C1_SDA, MX6_PAD_EIM_D21__I2C1_SCL, /* FEC PHY GPIO functions */ - MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */ - MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */ - MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */ + MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */ + MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */ + MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */ }; -static const iomux_v3_cfg_t tx6qdl_fec_pads[] = { +static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = { /* FEC functions */ MX6_PAD_ENET_MDC__ENET_MDC, MX6_PAD_ENET_MDIO__ENET_MDIO, - MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT, + MX6_PAD_GPIO_16__ENET_REF_CLK, MX6_PAD_ENET_RX_ER__ENET_RX_ER, MX6_PAD_ENET_CRS_DV__ENET_RX_EN, - MX6_PAD_ENET_RXD1__ENET_RDATA_1, - MX6_PAD_ENET_RXD0__ENET_RDATA_0, + MX6_PAD_ENET_RXD1__ENET_RX_DATA1, + MX6_PAD_ENET_RXD0__ENET_RX_DATA0, MX6_PAD_ENET_TX_EN__ENET_TX_EN, - MX6_PAD_ENET_TXD1__ENET_TDATA_1, - MX6_PAD_ENET_TXD0__ENET_TDATA_0, + MX6_PAD_ENET_TXD1__ENET_TX_DATA1, + MX6_PAD_ENET_TXD0__ENET_TX_DATA0, }; -static const struct gpio tx6qdl_gpios[] = { - { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", }, - { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, - { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", }, - { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, +static const struct gpio const tx6qdl_gpios[] = { + { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", }, + { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, + { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", }, + { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", }, }; /* @@ -192,8 +207,7 @@ static void print_reset_cause(void) printf("\n"); } -int read_cpu_temperature(void); -int check_cpu_temperature(int boot); +static const char __data *tx6_mod_suffix; static void tx6qdl_print_cpuinfo(void) { @@ -203,15 +217,19 @@ static void tx6qdl_print_cpuinfo(void) switch ((cpurev >> 12) & 0xff) { case MXC_CPU_MX6SL: cpu_str = "SL"; + tx6_mod_suffix = "?"; break; case MXC_CPU_MX6DL: cpu_str = "DL"; + tx6_mod_suffix = "U"; break; case MXC_CPU_MX6SOLO: cpu_str = "SOLO"; + tx6_mod_suffix = "S"; break; case MXC_CPU_MX6Q: cpu_str = "Q"; + tx6_mod_suffix = "Q"; break; } @@ -222,193 +240,9 @@ static void tx6qdl_print_cpuinfo(void) mxc_get_clock(MXC_ARM_CLK) / 1000000); print_reset_cause(); +#ifdef CONFIG_MX6_TEMPERATURE_HOT check_cpu_temperature(1); -} - -#define LTC3676_BUCK1 0x01 -#define LTC3676_BUCK2 0x02 -#define LTC3676_BUCK3 0x03 -#define LTC3676_BUCK4 0x04 -#define LTC3676_DVB1A 0x0A -#define LTC3676_DVB1B 0x0B -#define LTC3676_DVB2A 0x0C -#define LTC3676_DVB2B 0x0D -#define LTC3676_DVB3A 0x0E -#define LTC3676_DVB3B 0x0F -#define LTC3676_DVB4A 0x10 -#define LTC3676_DVB4B 0x11 -#define LTC3676_MSKPG 0x13 -#define LTC3676_CLIRQ 0x1f - -#define LTC3676_BUCK_DVDT_FAST (1 << 0) -#define LTC3676_BUCK_KEEP_ALIVE (1 << 1) -#define LTC3676_BUCK_CLK_RATE_LOW (1 << 2) -#define LTC3676_BUCK_PHASE_SEL (1 << 3) -#define LTC3676_BUCK_ENABLE_300 (1 << 4) -#define LTC3676_BUCK_PULSE_SKIP (0 << 5) -#define LTC3676_BUCK_BURST_MODE (1 << 5) -#define LTC3676_BUCK_CONTINUOUS (2 << 5) -#define LTC3676_BUCK_ENABLE (1 << 7) - -#define LTC3676_PGOOD_MASK (1 << 5) - -#define LTC3676_MSKPG_BUCK1 (1 << 0) -#define LTC3676_MSKPG_BUCK2 (1 << 1) -#define LTC3676_MSKPG_BUCK3 (1 << 2) -#define LTC3676_MSKPG_BUCK4 (1 << 3) -#define LTC3676_MSKPG_LDO2 (1 << 5) -#define LTC3676_MSKPG_LDO3 (1 << 6) -#define LTC3676_MSKPG_LDO4 (1 << 7) - -#define VDD_IO_VAL mV_to_regval(vout_to_vref(3300 * 10, 5)) -#define VDD_IO_VAL_LP mV_to_regval(vout_to_vref(3100 * 10, 5)) -#define VDD_IO_VAL_2 mV_to_regval(vout_to_vref(3300 * 10, 5_2)) -#define VDD_IO_VAL_2_LP mV_to_regval(vout_to_vref(3100 * 10, 5_2)) -#define VDD_SOC_VAL mV_to_regval(vout_to_vref(1425 * 10, 6)) -#define VDD_SOC_VAL_LP mV_to_regval(vout_to_vref(900 * 10, 6)) -#define VDD_DDR_VAL mV_to_regval(vout_to_vref(1500 * 10, 7)) -#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1425 * 10, 8)) -#define VDD_CORE_VAL_LP mV_to_regval(vout_to_vref(900 * 10, 8)) - -/* LDO1 */ -#define R1_1 470 -#define R2_1 150 -/* LDO4 */ -#define R1_4 470 -#define R2_4 150 -/* Buck1 */ -#define R1_5 390 -#define R2_5 110 -#define R1_5_2 470 -#define R2_5_2 150 -/* Buck2 */ -#define R1_6 150 -#define R2_6 180 -/* Buck3 */ -#define R1_7 150 -#define R2_7 140 -/* Buck4 */ -#define R1_8 150 -#define R2_8 180 - -/* calculate voltages in 10mV */ -#define R1(idx) R1_##idx -#define R2(idx) R2_##idx - -#define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx))) -#define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx)) - -#define mV_to_regval(mV) DIV_ROUND(((((mV) < 4125) ? 4125 : (mV)) - 4125), 125) -#define regval_to_mV(v) (((v) * 125 + 4125)) - -static struct ltc3673_regs { - u8 addr; - u8 val; - u8 mask; -} ltc3676_regs[] = { - { LTC3676_MSKPG, ~LTC3676_MSKPG_BUCK1, }, - { LTC3676_DVB2B, VDD_SOC_VAL | LTC3676_PGOOD_MASK, ~0x3f, }, - { LTC3676_DVB3B, VDD_DDR_VAL, ~0x3f, }, - { LTC3676_DVB4B, VDD_CORE_VAL | LTC3676_PGOOD_MASK, ~0x3f, }, - { LTC3676_DVB2A, VDD_SOC_VAL, ~0x3f, }, - { LTC3676_DVB3A, VDD_DDR_VAL, ~0x3f, }, - { LTC3676_DVB4A, VDD_CORE_VAL, ~0x3f, }, - { LTC3676_BUCK1, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, }, - { LTC3676_BUCK2, LTC3676_BUCK_BURST_MODE, }, - { LTC3676_BUCK3, LTC3676_BUCK_BURST_MODE, }, - { LTC3676_BUCK4, LTC3676_BUCK_BURST_MODE, }, - { LTC3676_CLIRQ, 0, }, /* clear interrupt status */ -}; - -static struct ltc3673_regs ltc3676_regs_1[] = { - { LTC3676_DVB1B, VDD_IO_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, }, - { LTC3676_DVB1A, VDD_IO_VAL, ~0x3f, }, -}; - -static struct ltc3673_regs ltc3676_regs_2[] = { - { LTC3676_DVB1B, VDD_IO_VAL_2_LP | LTC3676_PGOOD_MASK, ~0x3f, }, - { LTC3676_DVB1A, VDD_IO_VAL_2, ~0x3f, }, -}; - -static int tx6_rev_2(void) -{ - struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; - struct fuse_bank5_regs *fuse = (void *)ocotp->bank[5].fuse_regs; - u32 pad_settings = readl(&fuse->pad_settings); - - debug("Fuse pad_settings @ %p = %02x\n", - &fuse->pad_settings, pad_settings); - return pad_settings & 1; -} - -static int tx6_ltc3676_setup_regs(struct ltc3673_regs *r, size_t count) -{ - int ret; - int i; - - for (i = 0; i < count; i++, r++) { -#ifdef DEBUG - unsigned char value; - - ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1); - if ((value & ~r->mask) != r->val) { - printf("Changing PMIC reg %02x from %02x to %02x\n", - r->addr, value, r->val); - } - if (ret) { - printf("%s: failed to read PMIC register %02x: %d\n", - __func__, r->addr, ret); - return ret; - } #endif - ret = i2c_write(CONFIG_SYS_I2C_SLAVE, - r->addr, 1, &r->val, 1); - if (ret) { - printf("%s: failed to write PMIC register %02x: %d\n", - __func__, r->addr, ret); - return ret; - } - } - return 0; -} - -static int setup_pmic_voltages(void) -{ - int ret; - unsigned char value; - - ret = i2c_probe(CONFIG_SYS_I2C_SLAVE); - if (ret != 0) { - printf("Failed to initialize I2C\n"); - return ret; - } - - ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1); - if (ret) { - printf("%s: i2c_read error: %d\n", __func__, ret); - return ret; - } - - ret = tx6_ltc3676_setup_regs(ltc3676_regs, ARRAY_SIZE(ltc3676_regs)); - if (ret) - return ret; - - printf("VDDCORE set to %umV\n", - DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 8), 10)); - printf("VDDSOC set to %umV\n", - DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 6), 10)); - - if (tx6_rev_2()) { - ret = tx6_ltc3676_setup_regs(ltc3676_regs_2, - ARRAY_SIZE(ltc3676_regs_2)); - printf("VDDIO set to %umV\n", - DIV_ROUND(vref_to_vout( - regval_to_mV(VDD_IO_VAL_2), 5_2), 10)); - } else { - ret = tx6_ltc3676_setup_regs(ltc3676_regs_1, - ARRAY_SIZE(ltc3676_regs_1)); - } - return ret; } int board_early_init_f(void) @@ -419,6 +253,12 @@ int board_early_init_f(void) return 0; } +#ifndef CONFIG_MX6_TEMPERATURE_HOT +static bool tx6_temp_check_enabled = true; +#else +#define tx6_temp_check_enabled 0 +#endif + int board_init(void) { int ret; @@ -427,12 +267,18 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000; gd->bd->bi_arch_number = -1; - if (ctrlc()) { - printf("CTRL-C detected; Skipping PMIC setup\n"); + if (ctrlc() || (wrsr & WRSR_TOUT)) { + if (wrsr & WRSR_TOUT) + printf("WDOG RESET detected; Skipping PMIC setup\n"); + else + printf(" detected; safeboot enabled\n"); +#ifndef CONFIG_MX6_TEMPERATURE_HOT + tx6_temp_check_enabled = false; +#endif return 1; } - ret = setup_pmic_voltages(); + ret = tx6_pmic_init(); if (ret) { printf("Failed to setup PMIC voltages\n"); hang(); @@ -461,27 +307,44 @@ void dram_init_banksize(void) } #ifdef CONFIG_CMD_MMC +#define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST) + static const iomux_v3_cfg_t mmc0_pads[] = { - MX6_PAD_SD1_CMD__USDHC1_CMD, - MX6_PAD_SD1_CLK__USDHC1_CLK, - MX6_PAD_SD1_DAT0__USDHC1_DAT0, - MX6_PAD_SD1_DAT1__USDHC1_DAT1, - MX6_PAD_SD1_DAT2__USDHC1_DAT2, - MX6_PAD_SD1_DAT3__USDHC1_DAT3, + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL), /* SD1 CD */ - MX6_PAD_SD3_CMD__GPIO_7_2, + MX6_PAD_SD3_CMD__GPIO7_IO02, }; static const iomux_v3_cfg_t mmc1_pads[] = { - MX6_PAD_SD2_CMD__USDHC2_CMD, - MX6_PAD_SD2_CLK__USDHC2_CLK, - MX6_PAD_SD2_DAT0__USDHC2_DAT0, - MX6_PAD_SD2_DAT1__USDHC2_DAT1, - MX6_PAD_SD2_DAT2__USDHC2_DAT2, - MX6_PAD_SD2_DAT3__USDHC2_DAT3, + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL), /* SD2 CD */ - MX6_PAD_SD3_CLK__GPIO_7_3, + MX6_PAD_SD3_CLK__GPIO7_IO03, +}; + +#ifdef CONFIG_TX6_EMMC +static const iomux_v3_cfg_t mmc3_pads[] = { + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL), + /* eMMC RESET */ + MX6_PAD_NANDF_ALE__SD4_RESET, }; +#endif static struct tx6_esdhc_cfg { const iomux_v3_cfg_t *pads; @@ -490,6 +353,18 @@ static struct tx6_esdhc_cfg { struct fsl_esdhc_cfg cfg; int cd_gpio; } tx6qdl_esdhc_cfg[] = { +#ifdef CONFIG_TX6_EMMC + { + .pads = mmc3_pads, + .num_pads = ARRAY_SIZE(mmc3_pads), + .clkid = MXC_ESDHC4_CLK, + .cfg = { + .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR, + .max_bus_width = 4, + }, + .cd_gpio = -EINVAL, + }, +#endif { .pads = mmc0_pads, .num_pads = ARRAY_SIZE(mmc0_pads), @@ -522,11 +397,12 @@ int board_mmc_getcd(struct mmc *mmc) struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv); if (cfg->cd_gpio < 0) - return cfg->cd_gpio; + return 1; - debug("SD card %d is %spresent\n", + debug("SD card %d is %spresent (GPIO %d)\n", cfg - tx6qdl_esdhc_cfg, - gpio_get_value(cfg->cd_gpio) ? "NOT " : ""); + gpio_get_value(cfg->cd_gpio) ? "NOT " : "", + cfg->cd_gpio); return !gpio_get_value(cfg->cd_gpio); } @@ -542,12 +418,14 @@ int board_mmc_init(bd_t *bis) cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid); imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads); - ret = gpio_request_one(cfg->cd_gpio, - GPIOF_INPUT, "MMC CD"); - if (ret) { - printf("Error %d requesting GPIO%d_%d\n", - ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32); - continue; + if (cfg->cd_gpio >= 0) { + ret = gpio_request_one(cfg->cd_gpio, + GPIOFLAG_INPUT, "MMC CD"); + if (ret) { + printf("Error %d requesting GPIO%d_%d\n", + ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32); + continue; + } } debug("%s: Initializing MMC slot %d\n", __func__, i); @@ -556,7 +434,7 @@ int board_mmc_init(bd_t *bis) mmc = find_mmc_device(i); if (mmc == NULL) continue; - if (board_mmc_getcd(mmc) > 0) + if (board_mmc_getcd(mmc)) mmc_init(mmc); } return 0; @@ -581,7 +459,8 @@ int board_eth_init(bd_t *bis) /* delay at least 21ms for the PHY internal POR signal to deassert */ udelay(22000); - imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads)); + imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, + ARRAY_SIZE(tx6qdl_fec_pads)); /* Deassert RESET to the external phy */ gpio_set_value(TX6_FEC_RST_GPIO, 1); @@ -592,6 +471,24 @@ int board_eth_init(bd_t *bis) return ret; } + +static void tx6_init_mac(void) +{ + u8 mac[ETH_ALEN]; + + imx_get_mac_from_fuse(-1, mac); + if (!is_valid_ether_addr(mac)) { + printf("No valid MAC address programmed\n"); + return; + } + + printf("MAC addr from fuse: %pM\n", mac); + eth_setenv_enetaddr("ethaddr", mac); +} +#else +static inline void tx6_init_mac(void) +{ +} #endif /* CONFIG_FEC_MXC */ enum { @@ -600,10 +497,13 @@ enum { LED_STATE_ON, }; -static inline int calc_blink_rate(int tmp) +static inline int calc_blink_rate(void) { + if (!tx6_temp_check_enabled) + return CONFIG_SYS_HZ; + return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 - - (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ / + (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ / (TEMPERATURE_HOT - TEMPERATURE_MIN); } @@ -617,10 +517,10 @@ void show_activity(int arg) last = get_timer(0); gpio_set_value(TX6_LED_GPIO, 1); led_state = LED_STATE_ON; - blink_rate = calc_blink_rate(check_cpu_temperature(0)); + blink_rate = calc_blink_rate(); } else { if (get_timer(last) > blink_rate) { - blink_rate = calc_blink_rate(check_cpu_temperature(0)); + blink_rate = calc_blink_rate(); last = get_timer_masked(); if (led_state == LED_STATE_ON) { gpio_set_value(TX6_LED_GPIO, 0); @@ -634,67 +534,37 @@ void show_activity(int arg) static const iomux_v3_cfg_t stk5_pads[] = { /* SW controlled LED on STK5 baseboard */ - MX6_PAD_EIM_A18__GPIO_2_20, - - /* LCD data pins */ - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */ - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */ - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */ - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */ + MX6_PAD_EIM_A18__GPIO2_IO20, /* I2C bus on DIMM pins 40/41 */ MX6_PAD_GPIO_6__I2C3_SDA, MX6_PAD_GPIO_3__I2C3_SCL, /* TSC200x PEN IRQ */ - MX6_PAD_EIM_D26__GPIO_3_26, + MX6_PAD_EIM_D26__GPIO3_IO26, /* EDT-FT5x06 Polytouch panel */ - MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */ - MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */ - MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */ + MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */ + MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */ + MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */ /* USBH1 */ - MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */ - MX6_PAD_EIM_D30__GPIO_3_30, /* OC */ + MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */ + MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */ /* USBOTG */ - MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */ - MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */ - MX6_PAD_GPIO_8__GPIO_1_8, /* OC */ + MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */ + MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */ + MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */ }; static const struct gpio stk5_gpios[] = { - { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, + { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, - { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", }, - { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", }, - { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", }, - { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", }, - { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, + { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", }, + { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", }, + { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", }, + { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", }, + { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, }; #ifdef CONFIG_LCD @@ -704,7 +574,7 @@ vidinfo_t panel_info = { .vl_col = 1920, .vl_row = 1080, - .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ .cmap = tx6_cmap, }; @@ -828,6 +698,23 @@ static struct fb_videomode tx6_fb_modes[] = { .lower_margin = 525 - 480 - 35, .sync = FB_SYNC_CLK_LAT_FALL, }, + { + /* Emerging ET070001DM6 800 x 480 display. + * 152.4 mm x 91.44 mm display area. + */ + .name = "ET070001DM6", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .sync = 0, + }, #else { /* HannStar HSD100PXN1 @@ -911,47 +798,49 @@ void lcd_panel_disable(void) static const iomux_v3_cfg_t stk5_lcd_pads[] = { /* LCD RESET */ - MX6_PAD_EIM_D29__GPIO_3_29, + MX6_PAD_EIM_D29__GPIO3_IO29, /* LCD POWER_ENABLE */ - MX6_PAD_EIM_EB3__GPIO_2_31, + MX6_PAD_EIM_EB3__GPIO2_IO31, /* LCD Backlight (PWM) */ - MX6_PAD_GPIO_1__GPIO_1_1, + MX6_PAD_GPIO_1__GPIO1_IO01, +#ifndef CONFIG_SYS_LVDS_IF /* Display */ - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */ + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */ + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */ + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */ +#endif }; static const struct gpio stk5_lcd_gpios[] = { - { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, - { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, - { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, + { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", }, + { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", }, + { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, }; void lcd_ctrl_init(void *lcdbase) @@ -1109,7 +998,7 @@ void lcd_ctrl_init(void *lcdbase) panel_info.vl_bpix = LCD_COLOR16; break; default: - panel_info.vl_bpix = LCD_COLOR24; + panel_info.vl_bpix = LCD_COLOR32; } p->pixclock = KHZ2PICOS(refresh * @@ -1160,6 +1049,7 @@ void lcd_ctrl_init(void *lcdbase) int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0); int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt); uint32_t gpr2; + uint32_t gpr3; if (lvds_chan_mask == 0) { printf("No LVDS channel active\n"); @@ -1174,12 +1064,18 @@ void lcd_ctrl_init(void *lcdbase) gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0; debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8); writel(gpr2, IOMUXC_BASE_ADDR + 8); + + gpr3 = readl(IOMUXC_BASE_ADDR + 0xc); + gpr3 &= ~((3 << 8) | (3 << 6)); + writel(gpr3, IOMUXC_BASE_ADDR + 0xc); } if (karo_load_splashimage(0) == 0) { int ret; debug("Initializing LCD controller\n"); - ret = ipuv3_fb_init(p, 0, pix_fmt, DI_PCLK_PLL3, di_clk_rate, -1); + ret = ipuv3_fb_init(p, 0, pix_fmt, + is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3, + di_clk_rate, -1); if (ret) { printf("Failed to initialize FB driver: %d\n", ret); lcd_enabled = 0; @@ -1207,21 +1103,23 @@ static void stk5v5_board_init(void) { stk5_board_init(); - gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH, + gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH, "Flexcan Transceiver"); - imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21); + imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21); } static void tx6qdl_set_cpu_clock(void) { unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0); - if (had_ctrlc() || (wrsr & WRSR_TOUT)) - return; - if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000) return; + if (had_ctrlc() || (wrsr & WRSR_TOUT)) { + printf("%s detected; skipping cpu clock change\n", + (wrsr & WRSR_TOUT) ? "WDOG RESET" : ""); + return; + } if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) { cpu_clk = mxc_get_clock(MXC_ARM_CLK); printf("CPU clock set to %lu.%03lu MHz\n", @@ -1231,27 +1129,24 @@ static void tx6qdl_set_cpu_clock(void) } } -static void tx6_init_mac(void) -{ - u8 mac[ETH_ALEN]; - - imx_get_mac_from_fuse(-1, mac); - if (!is_valid_ether_addr(mac)) { - printf("No valid MAC address programmed\n"); - return; - } - - printf("MAC addr from fuse: %pM\n", mac); - eth_setenv_enetaddr("ethaddr", mac); -} - int board_late_init(void) { int ret = 0; const char *baseboard; + env_cleanup(); + + if (tx6_temp_check_enabled) + check_cpu_temperature(1); + tx6qdl_set_cpu_clock(); - karo_fdt_move_fdt(); + + if (had_ctrlc()) + setenv_ulong("safeboot", 1); + else if (wrsr & WRSR_TOUT) + setenv_ulong("wdreset", 1); + else + karo_fdt_move_fdt(); baseboard = getenv("baseboard"); if (!baseboard) @@ -1290,6 +1185,71 @@ exit: return ret; } +#ifdef CONFIG_TX6_NAND +#define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1) +#else +#ifdef CONFIG_MMC_BOOT_SIZE +#define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 4096 + 2) +#else +#define TX6_FLASH_SZ 2 +#endif +#endif /* CONFIG_TX6_NAND */ + +#define TX6_DDR_SZ (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1) + +static char tx6_mem_table[] = { + '4', /* 256MiB SDRAM 16bit; 128MiB NAND */ + '1', /* 512MiB SDRAM 32bit; 128MiB NAND */ + '0', /* 1GiB SDRAM 64bit; 128MiB NAND */ + '?', /* 256MiB SDRAM 16bit; 256MiB NAND */ + '?', /* 512MiB SDRAM 32bit; 256MiB NAND */ + '2', /* 1GiB SDRAM 64bit; 256MiB NAND */ + '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */ + '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */ + '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */ + '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */ + '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */ + '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */ +}; + +static inline char tx6_mem_suffix(void) +{ + size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ; + + debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n", + TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx); + + if (mem_idx >= ARRAY_SIZE(tx6_mem_table)) + return '?'; + + return tx6_mem_table[mem_idx]; +}; + +static struct { + uchar addr; + uchar rev; +} tx6_mod_revs[] = { + { 0x3c, 1, }, + { 0x32, 2, }, + { 0x33, 3, }, +}; + +static int tx6_get_mod_rev(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) { + int ret = i2c_probe(tx6_mod_revs[i].addr); + if (ret == 0) { + debug("I2C probe succeeded for addr %02x\n", tx6_mod_revs[i].addr); + return tx6_mod_revs[i].rev; + } + debug("I2C probe returned %d for addr %02x\n", ret, + tx6_mod_revs[i].addr); + } + return 0; +} + int checkboard(void) { u32 cpurev = get_cpu_rev(); @@ -1297,10 +1257,13 @@ int checkboard(void) tx6qdl_print_cpuinfo(); - printf("Board: Ka-Ro TX6%c-%d%d1%d\n", - cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U', + i2c_init(CONFIG_SYS_I2C_SPEED, 0 /* unused */); + + printf("Board: Ka-Ro TX6%s-%d%d%d%c\n", + tx6_mod_suffix, cpu_variant == MXC_CPU_MX6Q ? 1 : 8, - is_lvds(), 1 - PHYS_SDRAM_1_WIDTH / 64); + is_lvds(), tx6_get_mod_rev(), + tx6_mem_suffix()); return 0; } @@ -1333,12 +1296,18 @@ static const char *tx6_touchpanels[] = { "eeti,egalax_ts", }; -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { const char *baseboard = getenv("baseboard"); int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0); const char *video_mode = karo_get_vmode(getenv("video_mode")); + int ret; + ret = fdt_increase_size(blob, 4096); + if (ret) { + printf("Failed to increase FDT size: %s\n", fdt_strerror(ret)); + return ret; + } if (stk5_v5) karo_fdt_enable_node(blob, "stk5led", 0); @@ -1347,9 +1316,11 @@ void ft_board_setup(void *blob, bd_t *bd) karo_fdt_fixup_touchpanel(blob, tx6_touchpanels, ARRAY_SIZE(tx6_touchpanels)); - karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy"); + karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply"); karo_fdt_fixup_flexcan(blob, stk5_v5); karo_fdt_update_fb_mode(blob, video_mode); + + return 0; } #endif /* CONFIG_OF_BOARD_SETUP */