X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Fkaro%2Ftx6%2Ftx6qdl.c;h=1a1e155379e8d9383c1c6e008d27c1ba06f38782;hp=d2d1e8364ffb66236451fb8083f357424373ecba;hb=021edeae96ab10e9793f5c967a7137c367f2fffa;hpb=0bacb4d60fb1d17a66c032eb13ed8d01599bcc37 diff --git a/board/karo/tx6/tx6qdl.c b/board/karo/tx6/tx6qdl.c index d2d1e8364f..1a1e155379 100644 --- a/board/karo/tx6/tx6qdl.c +++ b/board/karo/tx6/tx6qdl.c @@ -64,68 +64,85 @@ char __uboot_img_end[0] __attribute__((section(".__uboot_img_end"))); char __csf_data[0] __attribute__((section(".__csf_data"))); #endif +#define TX6_DEFAULT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST) +#define TX6_FEC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST) +#define TX6_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | \ + PAD_CTL_SRE_FAST) +#define TX6_I2C_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \ + PAD_CTL_HYS | \ + PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_SLOW) + static const iomux_v3_cfg_t const tx6qdl_pads[] = { /* RESET_OUT */ - MX6_PAD_GPIO_17__GPIO7_IO12, + MX6_PAD_GPIO_17__GPIO7_IO12 | TX6_DEFAULT_PAD_CTRL, /* UART pads */ #if CONFIG_MXC_UART_BASE == UART1_BASE - MX6_PAD_SD3_DAT7__UART1_TX_DATA, - MX6_PAD_SD3_DAT6__UART1_RX_DATA, - MX6_PAD_SD3_DAT1__UART1_RTS_B, - MX6_PAD_SD3_DAT0__UART1_CTS_B, + MX6_PAD_SD3_DAT7__UART1_TX_DATA | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_SD3_DAT6__UART1_RX_DATA | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_SD3_DAT1__UART1_RTS_B | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_SD3_DAT0__UART1_CTS_B | TX6_DEFAULT_PAD_CTRL, #endif #if CONFIG_MXC_UART_BASE == UART2_BASE - MX6_PAD_SD4_DAT4__UART2_RX_DATA, - MX6_PAD_SD4_DAT7__UART2_TX_DATA, - MX6_PAD_SD4_DAT5__UART2_RTS_B, - MX6_PAD_SD4_DAT6__UART2_CTS_B, + MX6_PAD_SD4_DAT4__UART2_RX_DATA | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_SD4_DAT7__UART2_TX_DATA | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_SD4_DAT5__UART2_RTS_B | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_SD4_DAT6__UART2_CTS_B | TX6_DEFAULT_PAD_CTRL, #endif #if CONFIG_MXC_UART_BASE == UART3_BASE - MX6_PAD_EIM_D24__UART3_TX_DATA, - MX6_PAD_EIM_D25__UART3_RX_DATA, - MX6_PAD_SD3_RST__UART3_RTS_B, - MX6_PAD_SD3_DAT3__UART3_CTS_B, + MX6_PAD_EIM_D24__UART3_TX_DATA | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_EIM_D25__UART3_RX_DATA | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_SD3_RST__UART3_RTS_B | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_SD3_DAT3__UART3_CTS_B | TX6_DEFAULT_PAD_CTRL, #endif /* internal I2C */ - MX6_PAD_EIM_D28__I2C1_SDA, - MX6_PAD_EIM_D21__I2C1_SCL, + MX6_PAD_EIM_D28__I2C1_SDA | TX6_DEFAULT_PAD_CTRL, + MX6_PAD_EIM_D21__I2C1_SCL | TX6_DEFAULT_PAD_CTRL, /* FEC PHY GPIO functions */ - MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */ - MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */ - MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */ + MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION | + TX6_DEFAULT_PAD_CTRL, /* PHY POWER */ + MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION | + TX6_DEFAULT_PAD_CTRL, /* PHY RESET */ + MX6_PAD_SD3_DAT4__GPIO7_IO01 | TX6_DEFAULT_PAD_CTRL, /* PHY INT */ }; static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = { /* FEC functions */ - MX6_PAD_ENET_MDC__ENET_MDC, - MX6_PAD_ENET_MDIO__ENET_MDIO, - MX6_PAD_GPIO_16__ENET_REF_CLK, - MX6_PAD_ENET_RX_ER__ENET_RX_ER, - MX6_PAD_ENET_CRS_DV__ENET_RX_EN, - MX6_PAD_ENET_RXD1__ENET_RX_DATA1, - MX6_PAD_ENET_RXD0__ENET_RX_DATA0, - MX6_PAD_ENET_TX_EN__ENET_TX_EN, - MX6_PAD_ENET_TXD1__ENET_TX_DATA1, - MX6_PAD_ENET_TXD0__ENET_TX_DATA0, + MX6_PAD_ENET_MDC__ENET_MDC | TX6_FEC_PAD_CTRL, + MX6_PAD_ENET_MDIO__ENET_MDIO | TX6_FEC_PAD_CTRL, + MX6_PAD_GPIO_16__ENET_REF_CLK | TX6_FEC_PAD_CTRL, + MX6_PAD_ENET_RX_ER__ENET_RX_ER | TX6_FEC_PAD_CTRL, + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | TX6_FEC_PAD_CTRL, + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | TX6_FEC_PAD_CTRL, + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | TX6_FEC_PAD_CTRL, + MX6_PAD_ENET_TX_EN__ENET_TX_EN | TX6_FEC_PAD_CTRL, + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | TX6_FEC_PAD_CTRL, + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | TX6_FEC_PAD_CTRL, }; -#define TX6_I2C_GPIO_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ - PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_34ohm | \ - PAD_CTL_SRE_FAST) - static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = { /* internal I2C */ - MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL), - MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL), + MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | + TX6_GPIO_PAD_CTRL, + MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | + TX6_GPIO_PAD_CTRL, }; static const iomux_v3_cfg_t const tx6_i2c_pads[] = { /* internal I2C */ - MX6_PAD_EIM_D28__I2C1_SDA, - MX6_PAD_EIM_D21__I2C1_SCL, + MX6_PAD_EIM_D28__I2C1_SDA | TX6_I2C_PAD_CTRL, + MX6_PAD_EIM_D21__I2C1_SCL | TX6_I2C_PAD_CTRL, }; static const struct gpio const tx6qdl_gpios[] = { @@ -413,20 +430,65 @@ static char tx6_mem_table[] = { '3', /* TX6U-8033 1GiB SDRAM 64bit; 4GiB eMMC */ '?', /* N/A 256MiB SDRAM 16bit; 8GiB eMMC */ '?', /* N/A 512MiB SDRAM 32bit; 8GiB eMMC */ -#if defined(CONFIG_TX6_REV) && CONFIG_TX6_REV == 2 - '0', /* TX6Q-1020 (legacy) 1GiB SDRAM 64bit; 8GiB eMMC */ -#else '6', /* TX6Q-1036 1GiB SDRAM 64bit; 8GiB eMMC */ -#endif }; +#ifdef CONFIG_RN5T567 +/* PMIC settings */ +#define VDD_RTC_VAL rn5t_mV_to_regval_rtc(3000) +#define VDD_CORE_VAL rn5t_mV_to_regval(1400) /* DCDC1 */ +#define VDD_CORE_VAL_LP rn5t_mV_to_regval(900) +#define VDD_SOC_VAL rn5t_mV_to_regval(1400) /* DCDC2 */ +#define VDD_SOC_VAL_LP rn5t_mV_to_regval(1400) +#define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 */ +#define VDD_DDR_VAL_LP rn5t_mV_to_regval(1350) +#define VDD_HIGH_VAL rn5t_mV_to_regval(3000) /* DCDC4 */ +#define VDD_HIGH_VAL_LP rn5t_mV_to_regval(3000) +#define VDD_IO_INT_VAL rn5t_mV_to_regval2(3300) /* LDO1 */ +#define VDD_IO_INT_VAL_LP rn5t_mV_to_regval2(3300) +#define VDD_IO_EXT_VAL rn5t_mV_to_regval2(3300) /* LDO2 */ +#define VDD_IO_EXT_VAL_LP rn5t_mV_to_regval2(3300) + +static struct pmic_regs rn5t567_regs[] = { + { RN5T567_NOETIMSET, 0x5, }, + { RN5T567_DC1DAC, VDD_CORE_VAL, }, + { RN5T567_DC2DAC, VDD_SOC_VAL, }, + { RN5T567_DC3DAC, VDD_DDR_VAL, }, + { RN5T567_DC4DAC, VDD_HIGH_VAL, }, + { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, }, + { RN5T567_DC2DAC_SLP, VDD_SOC_VAL_LP, }, + { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, }, + { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, }, + { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), }, + { RN5T567_DC2CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), }, + { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), }, + { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), }, + { RN5T567_LDORTC1DAC, VDD_RTC_VAL, }, + { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, }, + { RN5T567_LDO1DAC, VDD_IO_INT_VAL, }, + { RN5T567_LDO2DAC, VDD_IO_EXT_VAL, }, + { RN5T567_LDOEN1, 0x03, ~0x1f, }, + { RN5T567_LDOEN2, 0x10, ~0x30, }, + { RN5T567_LDODIS, 0x1c, ~0x1f, }, + { RN5T567_INTPOL, 0, }, + { RN5T567_INTEN, 0x3, }, + { RN5T567_IREN, 0xf, }, + { RN5T567_EN_GPIR, 0, }, +}; +#endif + static struct { uchar addr; uchar rev; + struct pmic_regs *regs; + size_t num_regs; } tx6_mod_revs[] = { - { 0x3c, 1, }, - { 0x32, 2, }, - { 0x33, 3, }, +#ifdef CONFIG_LTC3676 + { 0x3c, 1, NULL, 0, }, +#endif +#ifdef CONFIG_RN5T567 + { 0x33, 3, rn5t567_regs, ARRAY_SIZE(rn5t567_regs), }, +#endif }; static inline char tx6_mem_suffix(void) @@ -512,7 +574,8 @@ int board_init(void) return 0; } - ret = tx6_pmic_init(pmic_addr, NULL, 0); + ret = tx6_pmic_init(pmic_addr, tx6_mod_revs[pmic_id].regs, + tx6_mod_revs[pmic_id].num_regs); if (ret) { printf("Failed to setup PMIC voltages: %d\n", ret); hang(); @@ -545,43 +608,42 @@ void dram_init_banksize(void) } #ifdef CONFIG_FSL_ESDHC -#define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST) +#define SD_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST) static const iomux_v3_cfg_t mmc0_pads[] = { - MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | SD_PAD_CTRL, + MX6_PAD_SD1_CLK__SD1_CLK | SD_PAD_CTRL, + MX6_PAD_SD1_DAT0__SD1_DATA0 | SD_PAD_CTRL, + MX6_PAD_SD1_DAT1__SD1_DATA1 | SD_PAD_CTRL, + MX6_PAD_SD1_DAT2__SD1_DATA2 | SD_PAD_CTRL, + MX6_PAD_SD1_DAT3__SD1_DATA3 | SD_PAD_CTRL, /* SD1 CD */ - MX6_PAD_SD3_CMD__GPIO7_IO02, + MX6_PAD_SD3_CMD__GPIO7_IO02 | TX6_GPIO_PAD_CTRL, }; static const iomux_v3_cfg_t mmc1_pads[] = { - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | SD_PAD_CTRL, + MX6_PAD_SD2_CLK__SD2_CLK | SD_PAD_CTRL, + MX6_PAD_SD2_DAT0__SD2_DATA0 | SD_PAD_CTRL, + MX6_PAD_SD2_DAT1__SD2_DATA1 | SD_PAD_CTRL, + MX6_PAD_SD2_DAT2__SD2_DATA2 | SD_PAD_CTRL, + MX6_PAD_SD2_DAT3__SD2_DATA3 | SD_PAD_CTRL, /* SD2 CD */ - MX6_PAD_SD3_CLK__GPIO7_IO03, + MX6_PAD_SD3_CLK__GPIO7_IO03 | TX6_GPIO_PAD_CTRL, }; #ifdef CONFIG_TX6_EMMC static const iomux_v3_cfg_t mmc3_pads[] = { - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | SD_PAD_CTRL, + MX6_PAD_SD4_CLK__SD4_CLK | SD_PAD_CTRL, + MX6_PAD_SD4_DAT0__SD4_DATA0 | SD_PAD_CTRL, + MX6_PAD_SD4_DAT1__SD4_DATA1 | SD_PAD_CTRL, + MX6_PAD_SD4_DAT2__SD4_DATA2 | SD_PAD_CTRL, + MX6_PAD_SD4_DAT3__SD4_DATA3 | SD_PAD_CTRL, /* eMMC RESET */ - MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | - PAD_CTL_DSE_40ohm), + MX6_PAD_NANDF_ALE__SD4_RESET | SD_PAD_CTRL, }; #endif @@ -772,27 +834,27 @@ void show_activity(int arg) static const iomux_v3_cfg_t stk5_pads[] = { /* SW controlled LED on STK5 baseboard */ - MX6_PAD_EIM_A18__GPIO2_IO20, + MX6_PAD_EIM_A18__GPIO2_IO20 | TX6_GPIO_PAD_CTRL, /* I2C bus on DIMM pins 40/41 */ - MX6_PAD_GPIO_6__I2C3_SDA, - MX6_PAD_GPIO_3__I2C3_SCL, + MX6_PAD_GPIO_6__I2C3_SDA | TX6_I2C_PAD_CTRL, + MX6_PAD_GPIO_3__I2C3_SCL | TX6_I2C_PAD_CTRL, /* TSC200x PEN IRQ */ - MX6_PAD_EIM_D26__GPIO3_IO26, + MX6_PAD_EIM_D26__GPIO3_IO26 | TX6_GPIO_PAD_CTRL, /* EDT-FT5x06 Polytouch panel */ - MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */ - MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */ - MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */ + MX6_PAD_NANDF_CS2__GPIO6_IO15 | TX6_GPIO_PAD_CTRL, /* IRQ */ + MX6_PAD_EIM_A16__GPIO2_IO22 | TX6_GPIO_PAD_CTRL, /* RESET */ + MX6_PAD_EIM_A17__GPIO2_IO21 | TX6_GPIO_PAD_CTRL, /* WAKE */ /* USBH1 */ - MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */ - MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */ + MX6_PAD_EIM_D31__GPIO3_IO31 | TX6_GPIO_PAD_CTRL, /* VBUSEN */ + MX6_PAD_EIM_D30__GPIO3_IO30 | TX6_GPIO_PAD_CTRL, /* OC */ /* USBOTG */ - MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */ - MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */ - MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */ + MX6_PAD_EIM_D23__GPIO3_IO23 | TX6_GPIO_PAD_CTRL, /* USBOTG ID */ + MX6_PAD_GPIO_7__GPIO1_IO07 | TX6_GPIO_PAD_CTRL, /* VBUSEN */ + MX6_PAD_GPIO_8__GPIO1_IO08 | TX6_GPIO_PAD_CTRL, /* OC */ }; static const struct gpio stk5_gpios[] = { @@ -1033,42 +1095,42 @@ void lcd_panel_disable(void) static const iomux_v3_cfg_t stk5_lcd_pads[] = { /* LCD RESET */ - MX6_PAD_EIM_D29__GPIO3_IO29, + MX6_PAD_EIM_D29__GPIO3_IO29 | TX6_GPIO_PAD_CTRL, /* LCD POWER_ENABLE */ - MX6_PAD_EIM_EB3__GPIO2_IO31, + MX6_PAD_EIM_EB3__GPIO2_IO31 | TX6_GPIO_PAD_CTRL, /* LCD Backlight (PWM) */ - MX6_PAD_GPIO_1__GPIO1_IO01, + MX6_PAD_GPIO_1__GPIO1_IO01 | TX6_GPIO_PAD_CTRL, #ifndef CONFIG_SYS_LVDS_IF /* Display */ - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */ - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */ - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */ - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */ + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | TX6_GPIO_PAD_CTRL, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | TX6_GPIO_PAD_CTRL, /* HSYNC */ + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | TX6_GPIO_PAD_CTRL, /* VSYNC */ + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | TX6_GPIO_PAD_CTRL, /* OE_ACD */ + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | TX6_GPIO_PAD_CTRL, /* LSCLK */ #endif }; @@ -1095,7 +1157,6 @@ void lcd_ctrl_init(void *lcdbase) if (!lcd_enabled) { debug("LCD disabled\n"); goto disable; - return; } if (had_ctrlc() || (wrsr & WRSR_TOUT)) { @@ -1103,7 +1164,6 @@ void lcd_ctrl_init(void *lcdbase) lcd_enabled = 0; setenv("splashimage", NULL); goto disable; - return; } karo_fdt_move_fdt(); @@ -1113,7 +1173,6 @@ void lcd_ctrl_init(void *lcdbase) debug("Disabling LCD\n"); lcd_enabled = 0; goto disable; - return; } vm = video_mode; if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) { @@ -1127,7 +1186,6 @@ void lcd_ctrl_init(void *lcdbase) panel_info.vl_col, panel_info.vl_row); lcd_enabled = 0; goto disable; - return; } } if (p->name != NULL) @@ -1219,14 +1277,12 @@ void lcd_ctrl_init(void *lcdbase) } printf("\n"); goto disable; - return; } if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) { printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n", p->xres, p->yres, panel_info.vl_col, panel_info.vl_row); lcd_enabled = 0; goto disable; - return; } panel_info.vl_col = p->xres; panel_info.vl_row = p->yres; @@ -1285,7 +1341,6 @@ void lcd_ctrl_init(void *lcdbase) printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD", lcd_bus_width); goto disable; - return; } if (is_lvds()) { int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0); @@ -1297,7 +1352,6 @@ void lcd_ctrl_init(void *lcdbase) printf("No LVDS channel active\n"); lcd_enabled = 0; goto disable; - return; } gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8); @@ -1368,7 +1422,8 @@ static void stk5v5_board_init(void) return; } - imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21); + imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21 | + TX6_GPIO_PAD_CTRL); } static void tx6qdl_set_cpu_clock(void)