X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Fkaro%2Ftx6%2Ftx6qdl.c;h=7b2cd5371fe3288c98195808d042e127f8bc01f9;hp=f0076e6ccdeee20342e6c73112534ec5077ab2e6;hb=8b40542f7f38a329ee9c35c6dbc2cfdcb9ff60e2;hpb=6ddef5f3686db2caf55c74648891a27be9e23b76

diff --git a/board/karo/tx6/tx6qdl.c b/board/karo/tx6/tx6qdl.c
index f0076e6ccd..7b2cd5371f 100644
--- a/board/karo/tx6/tx6qdl.c
+++ b/board/karo/tx6/tx6qdl.c
@@ -64,68 +64,85 @@ char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
 char __csf_data[0] __attribute__((section(".__csf_data")));
 #endif
 
+#define TX6_DEFAULT_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |	\
+					PAD_CTL_SPEED_MED |		\
+					PAD_CTL_DSE_40ohm |		\
+					PAD_CTL_SRE_FAST)
+#define TX6_FEC_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |	\
+					PAD_CTL_SPEED_MED |		\
+					PAD_CTL_DSE_40ohm |		\
+					PAD_CTL_SRE_FAST)
+#define TX6_GPIO_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |	\
+					PAD_CTL_SPEED_MED |		\
+					PAD_CTL_DSE_34ohm |		\
+					PAD_CTL_SRE_FAST)
+#define TX6_I2C_PAD_CTRL	MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |	\
+					PAD_CTL_HYS |			\
+					PAD_CTL_SPEED_LOW |		\
+					PAD_CTL_DSE_40ohm |		\
+					PAD_CTL_SRE_SLOW)
+
 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
 	/* RESET_OUT */
-	MX6_PAD_GPIO_17__GPIO7_IO12,
+	MX6_PAD_GPIO_17__GPIO7_IO12 | TX6_DEFAULT_PAD_CTRL,
 
 	/* UART pads */
 #if CONFIG_MXC_UART_BASE == UART1_BASE
-	MX6_PAD_SD3_DAT7__UART1_TX_DATA,
-	MX6_PAD_SD3_DAT6__UART1_RX_DATA,
-	MX6_PAD_SD3_DAT1__UART1_RTS_B,
-	MX6_PAD_SD3_DAT0__UART1_CTS_B,
+	MX6_PAD_SD3_DAT7__UART1_TX_DATA | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_SD3_DAT6__UART1_RX_DATA | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_SD3_DAT1__UART1_RTS_B | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_SD3_DAT0__UART1_CTS_B | TX6_DEFAULT_PAD_CTRL,
 #endif
 #if CONFIG_MXC_UART_BASE == UART2_BASE
-	MX6_PAD_SD4_DAT4__UART2_RX_DATA,
-	MX6_PAD_SD4_DAT7__UART2_TX_DATA,
-	MX6_PAD_SD4_DAT5__UART2_RTS_B,
-	MX6_PAD_SD4_DAT6__UART2_CTS_B,
+	MX6_PAD_SD4_DAT4__UART2_RX_DATA | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_SD4_DAT7__UART2_TX_DATA | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_SD4_DAT5__UART2_RTS_B | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_SD4_DAT6__UART2_CTS_B | TX6_DEFAULT_PAD_CTRL,
 #endif
 #if CONFIG_MXC_UART_BASE == UART3_BASE
-	MX6_PAD_EIM_D24__UART3_TX_DATA,
-	MX6_PAD_EIM_D25__UART3_RX_DATA,
-	MX6_PAD_SD3_RST__UART3_RTS_B,
-	MX6_PAD_SD3_DAT3__UART3_CTS_B,
+	MX6_PAD_EIM_D24__UART3_TX_DATA | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_EIM_D25__UART3_RX_DATA | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_SD3_RST__UART3_RTS_B | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_SD3_DAT3__UART3_CTS_B | TX6_DEFAULT_PAD_CTRL,
 #endif
 	/* internal I2C */
-	MX6_PAD_EIM_D28__I2C1_SDA,
-	MX6_PAD_EIM_D21__I2C1_SCL,
+	MX6_PAD_EIM_D28__I2C1_SDA | TX6_DEFAULT_PAD_CTRL,
+	MX6_PAD_EIM_D21__I2C1_SCL | TX6_DEFAULT_PAD_CTRL,
 
 	/* FEC PHY GPIO functions */
-	MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
-	MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
-	MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
+	MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION |
+			TX6_DEFAULT_PAD_CTRL, /* PHY POWER */
+	MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION |
+			TX6_DEFAULT_PAD_CTRL, /* PHY RESET */
+	MX6_PAD_SD3_DAT4__GPIO7_IO01 | TX6_DEFAULT_PAD_CTRL, /* PHY INT */
 };
 
 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
 	/* FEC functions */
-	MX6_PAD_ENET_MDC__ENET_MDC,
-	MX6_PAD_ENET_MDIO__ENET_MDIO,
-	MX6_PAD_GPIO_16__ENET_REF_CLK,
-	MX6_PAD_ENET_RX_ER__ENET_RX_ER,
-	MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
-	MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
-	MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
-	MX6_PAD_ENET_TX_EN__ENET_TX_EN,
-	MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
-	MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
+	MX6_PAD_ENET_MDC__ENET_MDC | TX6_FEC_PAD_CTRL,
+	MX6_PAD_ENET_MDIO__ENET_MDIO | TX6_FEC_PAD_CTRL,
+	MX6_PAD_GPIO_16__ENET_REF_CLK | TX6_FEC_PAD_CTRL,
+	MX6_PAD_ENET_RX_ER__ENET_RX_ER | TX6_FEC_PAD_CTRL,
+	MX6_PAD_ENET_CRS_DV__ENET_RX_EN | TX6_FEC_PAD_CTRL,
+	MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | TX6_FEC_PAD_CTRL,
+	MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | TX6_FEC_PAD_CTRL,
+	MX6_PAD_ENET_TX_EN__ENET_TX_EN | TX6_FEC_PAD_CTRL,
+	MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | TX6_FEC_PAD_CTRL,
+	MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | TX6_FEC_PAD_CTRL,
 };
 
-#define TX6_I2C_GPIO_PAD_CTRL	(PAD_CTL_PUS_22K_UP |	\
-				PAD_CTL_SPEED_MED |	\
-				PAD_CTL_DSE_34ohm |	\
-				PAD_CTL_SRE_FAST)
-
 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
 	/* internal I2C */
-	MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
-	MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
+	MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION |
+			TX6_GPIO_PAD_CTRL,
+	MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION |
+			TX6_GPIO_PAD_CTRL,
 };
 
 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
 	/* internal I2C */
-	MX6_PAD_EIM_D28__I2C1_SDA,
-	MX6_PAD_EIM_D21__I2C1_SCL,
+	MX6_PAD_EIM_D28__I2C1_SDA | TX6_I2C_PAD_CTRL,
+	MX6_PAD_EIM_D21__I2C1_SCL | TX6_I2C_PAD_CTRL,
 };
 
 static const struct gpio const tx6qdl_gpios[] = {
@@ -141,90 +158,88 @@ static const struct gpio const tx6qdl_gpios[] = {
 
 static int pmic_addr __data;
 
-#if defined(CONFIG_SOC_MX6Q)
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21	0x020e00a4
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28	0x020e00c4
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21	0x020e03b8
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28	0x020e03d8
-#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21	0x020e0898
-#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28	0x020e089c
-#define I2C1_SEL_INPUT_VAL			0
-#endif
-#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21	0x020e0158
-#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28	0x020e0174
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21	0x020e0528
-#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28	0x020e0544
-#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21	0x020e0868
-#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28	0x020e086c
-#define I2C1_SEL_INPUT_VAL			1
-#endif
+#if defined(TX6_I2C1_SCL_GPIO) && defined(TX6_I2C1_SDA_GPIO)
+#define SCL_BANK	(TX6_I2C1_SCL_GPIO / 32)
+#define SDA_BANK	(TX6_I2C1_SDA_GPIO / 32)
+#define SCL_BIT		(1 << (TX6_I2C1_SCL_GPIO % 32))
+#define SDA_BIT		(1 << (TX6_I2C1_SDA_GPIO % 32))
 
-#define GPIO_DR 0
-#define GPIO_DIR 4
-#define GPIO_PSR 8
+static void * const gpio_ports[] = {
+	(void *)GPIO1_BASE_ADDR,
+	(void *)GPIO2_BASE_ADDR,
+	(void *)GPIO3_BASE_ADDR,
+	(void *)GPIO4_BASE_ADDR,
+	(void *)GPIO5_BASE_ADDR,
+	(void *)GPIO6_BASE_ADDR,
+	(void *)GPIO7_BASE_ADDR,
+};
 
 static void tx6_i2c_recover(void)
 {
 	int i;
 	int bad = 0;
-#define SCL_BIT		(1 << (TX6_I2C1_SCL_GPIO % 32))
-#define SDA_BIT		(1 << (TX6_I2C1_SDA_GPIO % 32))
+	struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
+	struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
 
-	if ((readl(GPIO3_BASE_ADDR + GPIO_PSR) &
-			(SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
+	if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
+	    (readl(&sda_regs->gpio_psr) & SDA_BIT))
 		return;
 
 	debug("Clearing I2C bus\n");
-	if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SCL_BIT)) {
+	if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
 		printf("I2C SCL stuck LOW\n");
 		bad++;
 
-		writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
-			GPIO3_BASE_ADDR + GPIO_DR);
-		writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
-			GPIO3_BASE_ADDR + GPIO_DIR);
+		setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
+		setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
+
+		imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
+						 ARRAY_SIZE(tx6_i2c_gpio_pads));
 	}
-	if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)) {
+	if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
 		printf("I2C SDA stuck LOW\n");
-		bad++;
 
-		writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) & ~SDA_BIT,
-			GPIO3_BASE_ADDR + GPIO_DIR);
-		writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
-			GPIO3_BASE_ADDR + GPIO_DR);
-		writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
-			GPIO3_BASE_ADDR + GPIO_DIR);
+		clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
+		setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
+		setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
+
+		if (!bad++)
+			imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
+							 ARRAY_SIZE(tx6_i2c_gpio_pads));
 
-		imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
-						ARRAY_SIZE(tx6_i2c_gpio_pads));
 		udelay(10);
 
 		for (i = 0; i < 18; i++) {
-			u32 reg = readl(GPIO3_BASE_ADDR + GPIO_DR) ^ SCL_BIT;
-
-			debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
-			writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
-			udelay(10);
-			if (reg & SCL_BIT &&
-				readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)
+			u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
+
+			debug("%sing SCL\n",
+			      (reg & SCL_BIT) ? "Sett" : "Clear");
+			writel(reg, &scl_regs->gpio_dr);
+			udelay(5);
+			if (reg & SCL_BIT) {
+				if (readl(&sda_regs->gpio_psr) & SDA_BIT)
+					break;
+				if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
+					break;
 				break;
+			}
 		}
 	}
 	if (bad) {
-		u32 reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
+		bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
+		bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
 
-		if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
+		if (scl && sda) {
 			printf("I2C bus recovery succeeded\n");
 		} else {
-			printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
-				SCL_BIT | SDA_BIT);
+			printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
+			       scl, sda);
 		}
+		imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
+						 ARRAY_SIZE(tx6_i2c_pads));
 	}
-	debug("Setting up I2C Pads\n");
-	imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
-					ARRAY_SIZE(tx6_i2c_pads));
 }
+#endif
 
 /* placed in section '.data' to prevent overwriting relocation info
  * overlayed with bss
@@ -345,23 +360,21 @@ int checkboard(void)
 	u32 cpurev = get_cpu_rev();
 	char *cpu_str = "?";
 
-	switch ((cpurev >> 12) & 0xff) {
-	case MXC_CPU_MX6SL:
+	if (is_cpu_type(MXC_CPU_MX6SL)) {
 		cpu_str = "SL";
 		tx6_mod_suffix = "?";
-		break;
-	case MXC_CPU_MX6DL:
+	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
 		cpu_str = "DL";
 		tx6_mod_suffix = "U";
-		break;
-	case MXC_CPU_MX6SOLO:
+	} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 		cpu_str = "SOLO";
 		tx6_mod_suffix = "S";
-		break;
-	case MXC_CPU_MX6Q:
+	} else if (is_cpu_type(MXC_CPU_MX6Q)) {
 		cpu_str = "Q";
 		tx6_mod_suffix = "Q";
-		break;
+	} else if (is_cpu_type(MXC_CPU_MX6QP)) {
+		cpu_str = "QP";
+		tx6_mod_suffix = "QP";
 	}
 
 	printf("CPU:         Freescale i.MX6%s rev%d.%d at %d MHz\n",
@@ -404,27 +417,76 @@ static bool tx6_temp_check_enabled = true;
 #define TX6_DDR_SZ	(ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
 
 static char tx6_mem_table[] = {
-	'4', /* 256MiB SDRAM 16bit; 128MiB NAND */
-	'1', /* 512MiB SDRAM 32bit; 128MiB NAND */
-	'0', /* 1GiB SDRAM 64bit; 128MiB NAND */
-	'?', /* 256MiB SDRAM 16bit; 256MiB NAND */
-	'?', /* 512MiB SDRAM 32bit; 256MiB NAND */
-	'2', /* 1GiB SDRAM 64bit; 256MiB NAND */
-	'?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
-	'5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
-	'3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
-	'?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
-	'?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
-	'0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
+	'4', /* TX6S-8034 256MiB SDRAM 16bit; 128MiB NAND */
+	'1', /* TX6U-8011 512MiB SDRAM 32bit; 128MiB NAND */
+	'0', /* TX6Q-1030/TX6U-8030 1GiB SDRAM 64bit; 128MiB NAND */
+	'?', /* N/A 256MiB SDRAM 16bit; 256MiB NAND */
+	'?', /* N/A 512MiB SDRAM 32bit; 256MiB NAND */
+	'2', /* TX6U-8012 1GiB SDRAM 64bit; 256MiB NAND */
+	'?', /* N/A 256MiB SDRAM 16bit; 4GiB eMMC */
+	'5', /* TX6S-8035 512MiB SDRAM 32bit; 4GiB eMMC */
+	'3', /* TX6U-8033 1GiB SDRAM 64bit; 4GiB eMMC */
+	'?', /* N/A 256MiB SDRAM 16bit; 8GiB eMMC */
+	'?', /* N/A 512MiB SDRAM 32bit; 8GiB eMMC */
+	'6', /* TX6Q-1036 1GiB SDRAM 64bit; 8GiB eMMC */
 };
 
+#ifdef CONFIG_RN5T567
+/* PMIC settings */
+#define VDD_RTC_VAL		rn5t_mV_to_regval_rtc(3000)
+#define VDD_CORE_VAL		rn5t_mV_to_regval(1400)		/* DCDC1 */
+#define VDD_CORE_VAL_LP		rn5t_mV_to_regval(900)
+#define VDD_SOC_VAL		rn5t_mV_to_regval(1400)		/* DCDC2 */
+#define VDD_SOC_VAL_LP		rn5t_mV_to_regval(1400)
+#define VDD_DDR_VAL		rn5t_mV_to_regval(1350)		/* DCDC3 */
+#define VDD_DDR_VAL_LP		rn5t_mV_to_regval(1350)
+#define VDD_HIGH_VAL		rn5t_mV_to_regval(3000)		/* DCDC4 */
+#define VDD_HIGH_VAL_LP		rn5t_mV_to_regval(3000)
+#define VDD_IO_INT_VAL		rn5t_mV_to_regval2(3300)	/* LDO1 */
+#define VDD_IO_INT_VAL_LP	rn5t_mV_to_regval2(3300)
+#define VDD_IO_EXT_VAL		rn5t_mV_to_regval2(3300)	/* LDO2 */
+#define VDD_IO_EXT_VAL_LP	rn5t_mV_to_regval2(3300)
+
+static struct pmic_regs rn5t567_regs[] = {
+	{ RN5T567_NOETIMSET, 0x5, },
+	{ RN5T567_DC1DAC, VDD_CORE_VAL, },
+	{ RN5T567_DC2DAC, VDD_SOC_VAL, },
+	{ RN5T567_DC3DAC, VDD_DDR_VAL, },
+	{ RN5T567_DC4DAC, VDD_HIGH_VAL, },
+	{ RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
+	{ RN5T567_DC2DAC_SLP, VDD_SOC_VAL_LP, },
+	{ RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
+	{ RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
+	{ RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
+	{ RN5T567_DC2CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
+	{ RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
+	{ RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
+	{ RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
+	{ RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
+	{ RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
+	{ RN5T567_LDO2DAC, VDD_IO_EXT_VAL, },
+	{ RN5T567_LDOEN1, 0x03, ~0x1f, },
+	{ RN5T567_LDOEN2, 0x10, ~0x30, },
+	{ RN5T567_LDODIS, 0x1c, ~0x1f, },
+	{ RN5T567_INTPOL, 0, },
+	{ RN5T567_INTEN, 0x3, },
+	{ RN5T567_IREN, 0xf, },
+	{ RN5T567_EN_GPIR, 0, },
+};
+#endif
+
 static struct {
 	uchar addr;
 	uchar rev;
+	struct pmic_regs *regs;
+	size_t num_regs;
 } tx6_mod_revs[] = {
-	{ 0x3c, 1, },
-	{ 0x32, 2, },
-	{ 0x33, 3, },
+#ifdef CONFIG_LTC3676
+	{ 0x3c, 1, NULL, 0, },
+#endif
+#ifdef CONFIG_RN5T567
+	{ 0x33, 3, rn5t567_regs, ARRAY_SIZE(rn5t567_regs), },
+#endif
 };
 
 static inline char tx6_mem_suffix(void)
@@ -436,7 +498,10 @@ static inline char tx6_mem_suffix(void)
 
 	if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
 		return '?';
-
+	if (CONFIG_SYS_SDRAM_CHIP_SIZE > 512)
+		return '7';
+	if (mem_idx == 8)
+		return is_cpu_type(MXC_CPU_MX6Q) ? '6' : '3';
 	return tx6_mem_table[mem_idx];
 };
 
@@ -467,11 +532,19 @@ static int tx6_pmic_probe(void)
 	return -EINVAL;
 }
 
+static int tx6_mipi(void)
+{
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank4_regs *fuse = (void *)ocotp->bank[4].fuse_regs;
+	u32 gp1 = readl(&fuse->gp1);
+
+	debug("Fuse gp1 @ %p = %08x\n", &fuse->gp1, gp1);
+	return gp1 & 1;
+}
+
 int board_init(void)
 {
 	int ret;
-	u32 cpurev = get_cpu_rev();
-	int cpu_variant = (cpurev >> 12) & 0xff;
 	int pmic_id;
 
 	debug("%s@%d: \n", __func__, __LINE__);
@@ -482,8 +555,8 @@ int board_init(void)
 
 	printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
 		tx6_mod_suffix,
-		cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
-		is_lvds(), tx6_get_mod_rev(pmic_id),
+		is_cpu_type(MXC_CPU_MX6Q) ? 1 : 8,
+		tx6_mipi() ? 2 : is_lvds(), tx6_get_mod_rev(pmic_id),
 		tx6_mem_suffix());
 
 	get_hab_status();
@@ -509,7 +582,8 @@ int board_init(void)
 		return 0;
 	}
 
-	ret = tx6_pmic_init(pmic_addr, NULL, 0);
+	ret = tx6_pmic_init(pmic_addr, tx6_mod_revs[pmic_id].regs,
+			tx6_mod_revs[pmic_id].num_regs);
 	if (ret) {
 		printf("Failed to setup PMIC voltages: %d\n", ret);
 		hang();
@@ -529,8 +603,8 @@ int dram_init(void)
 
 void dram_init_banksize(void)
 {
-	debug("%s@%d: \n", __func__, __LINE__);
-
+	debug("%s@%d: chip_size=%u (%u bit bus width)\n", __func__, __LINE__,
+		CONFIG_SYS_SDRAM_CHIP_SIZE, CONFIG_SYS_SDRAM_BUS_WIDTH);
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 			PHYS_SDRAM_1_SIZE);
@@ -542,43 +616,42 @@ void dram_init_banksize(void)
 }
 
 #ifdef	CONFIG_FSL_ESDHC
-#define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP |		\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |		\
-	PAD_CTL_SRE_FAST)
+#define SD_PAD_CTRL		MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |	\
+				PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+				PAD_CTL_SRE_FAST)
 
 static const iomux_v3_cfg_t mmc0_pads[] = {
-	MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
+	MX6_PAD_SD1_CMD__SD1_CMD | SD_PAD_CTRL,
+	MX6_PAD_SD1_CLK__SD1_CLK | SD_PAD_CTRL,
+	MX6_PAD_SD1_DAT0__SD1_DATA0 | SD_PAD_CTRL,
+	MX6_PAD_SD1_DAT1__SD1_DATA1 | SD_PAD_CTRL,
+	MX6_PAD_SD1_DAT2__SD1_DATA2 | SD_PAD_CTRL,
+	MX6_PAD_SD1_DAT3__SD1_DATA3 | SD_PAD_CTRL,
 	/* SD1 CD */
-	MX6_PAD_SD3_CMD__GPIO7_IO02,
+	MX6_PAD_SD3_CMD__GPIO7_IO02 | TX6_GPIO_PAD_CTRL,
 };
 
 static const iomux_v3_cfg_t mmc1_pads[] = {
-	MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
+	MX6_PAD_SD2_CMD__SD2_CMD | SD_PAD_CTRL,
+	MX6_PAD_SD2_CLK__SD2_CLK | SD_PAD_CTRL,
+	MX6_PAD_SD2_DAT0__SD2_DATA0 | SD_PAD_CTRL,
+	MX6_PAD_SD2_DAT1__SD2_DATA1 | SD_PAD_CTRL,
+	MX6_PAD_SD2_DAT2__SD2_DATA2 | SD_PAD_CTRL,
+	MX6_PAD_SD2_DAT3__SD2_DATA3 | SD_PAD_CTRL,
 	/* SD2 CD */
-	MX6_PAD_SD3_CLK__GPIO7_IO03,
+	MX6_PAD_SD3_CLK__GPIO7_IO03 | TX6_GPIO_PAD_CTRL,
 };
 
 #ifdef CONFIG_TX6_EMMC
 static const iomux_v3_cfg_t mmc3_pads[] = {
-	MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
-	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
+	MX6_PAD_SD4_CMD__SD4_CMD | SD_PAD_CTRL,
+	MX6_PAD_SD4_CLK__SD4_CLK | SD_PAD_CTRL,
+	MX6_PAD_SD4_DAT0__SD4_DATA0 | SD_PAD_CTRL,
+	MX6_PAD_SD4_DAT1__SD4_DATA1 | SD_PAD_CTRL,
+	MX6_PAD_SD4_DAT2__SD4_DATA2 | SD_PAD_CTRL,
+	MX6_PAD_SD4_DAT3__SD4_DATA3 | SD_PAD_CTRL,
 	/* eMMC RESET */
-	MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
-						PAD_CTL_DSE_40ohm),
+	MX6_PAD_NANDF_ALE__SD4_RESET | SD_PAD_CTRL,
 };
 #endif
 
@@ -769,27 +842,27 @@ void show_activity(int arg)
 
 static const iomux_v3_cfg_t stk5_pads[] = {
 	/* SW controlled LED on STK5 baseboard */
-	MX6_PAD_EIM_A18__GPIO2_IO20,
+	MX6_PAD_EIM_A18__GPIO2_IO20 | TX6_GPIO_PAD_CTRL,
 
 	/* I2C bus on DIMM pins 40/41 */
-	MX6_PAD_GPIO_6__I2C3_SDA,
-	MX6_PAD_GPIO_3__I2C3_SCL,
+	MX6_PAD_GPIO_6__I2C3_SDA | TX6_I2C_PAD_CTRL,
+	MX6_PAD_GPIO_3__I2C3_SCL | TX6_I2C_PAD_CTRL,
 
 	/* TSC200x PEN IRQ */
-	MX6_PAD_EIM_D26__GPIO3_IO26,
+	MX6_PAD_EIM_D26__GPIO3_IO26 | TX6_GPIO_PAD_CTRL,
 
 	/* EDT-FT5x06 Polytouch panel */
-	MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
-	MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
-	MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
+	MX6_PAD_NANDF_CS2__GPIO6_IO15 | TX6_GPIO_PAD_CTRL, /* IRQ */
+	MX6_PAD_EIM_A16__GPIO2_IO22 | TX6_GPIO_PAD_CTRL, /* RESET */
+	MX6_PAD_EIM_A17__GPIO2_IO21 | TX6_GPIO_PAD_CTRL, /* WAKE */
 
 	/* USBH1 */
-	MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
-	MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
+	MX6_PAD_EIM_D31__GPIO3_IO31 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
+	MX6_PAD_EIM_D30__GPIO3_IO30 | TX6_GPIO_PAD_CTRL, /* OC */
 	/* USBOTG */
-	MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
-	MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
-	MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
+	MX6_PAD_EIM_D23__GPIO3_IO23 | TX6_GPIO_PAD_CTRL, /* USBOTG ID */
+	MX6_PAD_GPIO_7__GPIO1_IO07 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
+	MX6_PAD_GPIO_8__GPIO1_IO08 | TX6_GPIO_PAD_CTRL, /* OC */
 };
 
 static const struct gpio stk5_gpios[] = {
@@ -803,18 +876,15 @@ static const struct gpio stk5_gpios[] = {
 };
 
 #ifdef CONFIG_LCD
-static u16 tx6_cmap[256];
 vidinfo_t panel_info = {
 	/* set to max. size supported by SoC */
 	.vl_col = 1920,
 	.vl_row = 1080,
 
 	.vl_bpix = LCD_COLOR32,	   /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
-	.cmap = tx6_cmap,
 };
 
 static struct fb_videomode tx6_fb_modes[] = {
-#ifndef CONFIG_SYS_LVDS_IF
 	{
 		/* Standard VGA timing */
 		.name		= "VGA",
@@ -848,6 +918,24 @@ static struct fb_videomode tx6_fb_modes[] = {
 		.lower_margin	= 10,
 		.sync		= FB_SYNC_CLK_LAT_FALL,
 	},
+	{
+		/* Emerging ETM0700G0DH6 800 x 480 display.
+		 * 152.4 mm x 91.44 mm display area.
+		 */
+		.name		= "ET0700",
+		.refresh	= 60,
+		.xres		= 800,
+		.yres		= 480,
+		.pixclock	= KHZ2PICOS(33260),
+		.left_margin	= 88,
+		.hsync_len	= 128,
+		.right_margin	= 40,
+		.upper_margin	= 33,
+		.vsync_len	= 2,
+		.lower_margin	= 10,
+		.sync		= FB_SYNC_CLK_LAT_FALL,
+	},
+#ifndef CONFIG_SYS_LVDS_IF
 	{
 		/* Emerging ET0350G0DH6 320 x 240 display.
 		 * 70.08 mm x 52.56 mm display area.
@@ -857,10 +945,10 @@ static struct fb_videomode tx6_fb_modes[] = {
 		.xres		= 320,
 		.yres		= 240,
 		.pixclock	= KHZ2PICOS(6500),
-		.left_margin	= 68 - 34,
+		.left_margin	= 34,
 		.hsync_len	= 34,
 		.right_margin	= 20,
-		.upper_margin	= 18 - 3,
+		.upper_margin	= 15,
 		.vsync_len	= 3,
 		.lower_margin	= 4,
 		.sync		= FB_SYNC_CLK_LAT_FALL,
@@ -890,12 +978,12 @@ static struct fb_videomode tx6_fb_modes[] = {
 		.xres		= 800,
 		.yres		= 480,
 		.pixclock	= KHZ2PICOS(33260),
-		.left_margin	= 216 - 128,
+		.left_margin	= 88,
 		.hsync_len	= 128,
-		.right_margin	= 1056 - 800 - 216,
-		.upper_margin	= 35 - 2,
+		.right_margin	= 40,
+		.upper_margin	= 33,
 		.vsync_len	= 2,
-		.lower_margin	= 525 - 480 - 35,
+		.lower_margin	= 10,
 		.sync		= FB_SYNC_CLK_LAT_FALL,
 	},
 	{
@@ -915,40 +1003,6 @@ static struct fb_videomode tx6_fb_modes[] = {
 		.lower_margin	= 4, /* 4.5 according to datasheet */
 		.sync		= FB_SYNC_CLK_LAT_FALL,
 	},
-	{
-		/* Emerging ET0700G0DH6 800 x 480 display.
-		 * 152.4 mm x 91.44 mm display area.
-		 */
-		.name		= "ET0700",
-		.refresh	= 60,
-		.xres		= 800,
-		.yres		= 480,
-		.pixclock	= KHZ2PICOS(33260),
-		.left_margin	= 216 - 128,
-		.hsync_len	= 128,
-		.right_margin	= 1056 - 800 - 216,
-		.upper_margin	= 35 - 2,
-		.vsync_len	= 2,
-		.lower_margin	= 525 - 480 - 35,
-		.sync		= FB_SYNC_CLK_LAT_FALL,
-	},
-	{
-		/* Emerging ET070001DM6 800 x 480 display.
-		 * 152.4 mm x 91.44 mm display area.
-		 */
-		.name		= "ET070001DM6",
-		.refresh	= 60,
-		.xres		= 800,
-		.yres		= 480,
-		.pixclock	= KHZ2PICOS(33260),
-		.left_margin	= 216 - 128,
-		.hsync_len	= 128,
-		.right_margin	= 1056 - 800 - 216,
-		.upper_margin	= 35 - 2,
-		.vsync_len	= 2,
-		.lower_margin	= 525 - 480 - 35,
-		.sync		= 0,
-	},
 #else
 	{
 		/* HannStar HSD100PXN1
@@ -1032,42 +1086,42 @@ void lcd_panel_disable(void)
 
 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 	/* LCD RESET */
-	MX6_PAD_EIM_D29__GPIO3_IO29,
+	MX6_PAD_EIM_D29__GPIO3_IO29 | TX6_GPIO_PAD_CTRL,
 	/* LCD POWER_ENABLE */
-	MX6_PAD_EIM_EB3__GPIO2_IO31,
+	MX6_PAD_EIM_EB3__GPIO2_IO31 | TX6_GPIO_PAD_CTRL,
 	/* LCD Backlight (PWM) */
-	MX6_PAD_GPIO_1__GPIO1_IO01,
+	MX6_PAD_GPIO_1__GPIO1_IO01 | TX6_GPIO_PAD_CTRL,
 
 #ifndef CONFIG_SYS_LVDS_IF
 	/* Display */
-	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
-	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
-	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
-	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
-	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
-	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
-	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
-	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
-	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
-	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
-	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
-	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
-	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
-	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
-	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
-	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
-	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
-	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
-	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
-	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
-	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
-	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
-	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
-	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
-	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
-	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
-	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
-	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
+	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | TX6_GPIO_PAD_CTRL,
+	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | TX6_GPIO_PAD_CTRL, /* HSYNC */
+	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | TX6_GPIO_PAD_CTRL, /* VSYNC */
+	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | TX6_GPIO_PAD_CTRL, /* OE_ACD */
+	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | TX6_GPIO_PAD_CTRL, /* LSCLK */
 #endif
 };
 
@@ -1093,14 +1147,14 @@ void lcd_ctrl_init(void *lcdbase)
 
 	if (!lcd_enabled) {
 		debug("LCD disabled\n");
-		return;
+		goto disable;
 	}
 
 	if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
 		debug("Disabling LCD\n");
 		lcd_enabled = 0;
 		setenv("splashimage", NULL);
-		return;
+		goto disable;
 	}
 
 	karo_fdt_move_fdt();
@@ -1109,7 +1163,7 @@ void lcd_ctrl_init(void *lcdbase)
 	if (video_mode == NULL) {
 		debug("Disabling LCD\n");
 		lcd_enabled = 0;
-		return;
+		goto disable;
 	}
 	vm = video_mode;
 	if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
@@ -1122,7 +1176,7 @@ void lcd_ctrl_init(void *lcdbase)
 				fb_mode.xres, fb_mode.yres,
 				panel_info.vl_col, panel_info.vl_row);
 			lcd_enabled = 0;
-			return;
+			goto disable;
 		}
 	}
 	if (p->name != NULL)
@@ -1213,13 +1267,13 @@ void lcd_ctrl_init(void *lcdbase)
 			printf(" %s", p->name);
 		}
 		printf("\n");
-		return;
+		goto disable;
 	}
 	if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 		printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
 			p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
 		lcd_enabled = 0;
-		return;
+		goto disable;
 	}
 	panel_info.vl_col = p->xres;
 	panel_info.vl_row = p->yres;
@@ -1277,7 +1331,7 @@ void lcd_ctrl_init(void *lcdbase)
 		lcd_enabled = 0;
 		printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
 			lcd_bus_width);
-		return;
+		goto disable;
 	}
 	if (is_lvds()) {
 		int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
@@ -1288,7 +1342,7 @@ void lcd_ctrl_init(void *lcdbase)
 		if (lvds_chan_mask == 0) {
 			printf("No LVDS channel active\n");
 			lcd_enabled = 0;
-			return;
+			goto disable;
 		}
 
 		gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
@@ -1317,6 +1371,13 @@ void lcd_ctrl_init(void *lcdbase)
 	} else {
 		debug("Skipping initialization of LCD controller\n");
 	}
+	return;
+
+disable:
+	lcd_enabled = 0;
+	panel_info.vl_col = 0;
+	panel_info.vl_row = 0;
+
 }
 #else
 #define lcd_enabled 0
@@ -1352,7 +1413,8 @@ static void stk5v5_board_init(void)
 		return;
 	}
 
-	imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
+	imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21 |
+			TX6_GPIO_PAD_CTRL);
 }
 
 static void tx6qdl_set_cpu_clock(void)
@@ -1484,8 +1546,12 @@ int ft_board_setup(void *blob, bd_t *bd)
 	karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
 	karo_fdt_fixup_flexcan(blob, stk5_v5);
 
-	karo_fdt_update_fb_mode(blob, video_mode);
-
+#ifdef CONFIG_SYS_LVDS_IF
+	karo_fdt_update_fb_mode(blob, video_mode, "/lvds0-panel");
+	karo_fdt_update_fb_mode(blob, video_mode, "/lvds1-panel");
+#else
+	karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
+#endif
 	return 0;
 }
 #endif /* CONFIG_OF_BOARD_SETUP */