X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Fkaro%2Ftx6%2Ftx6ul.c;h=0722b1e5c6756df596659f18b15c34c8d29c7c36;hp=42f8eafc3f99bff77e6ae6426f01d41dc93d73ac;hb=ebddc2e8fca7c1a3e05e6b0764a99fdb89638fc3;hpb=001bd08c07559603eade16459d72c17d5e4d5034 diff --git a/board/karo/tx6/tx6ul.c b/board/karo/tx6/tx6ul.c index 42f8eafc3f..0722b1e5c6 100644 --- a/board/karo/tx6/tx6ul.c +++ b/board/karo/tx6/tx6ul.c @@ -34,14 +34,20 @@ #define TX6UL_FEC_RST_GPIO IMX_GPIO_NR(5, 6) #define TX6UL_FEC_PWR_GPIO IMX_GPIO_NR(5, 7) #define TX6UL_FEC_INT_GPIO IMX_GPIO_NR(5, 5) + +#define TX6UL_FEC2_RST_GPIO IMX_GPIO_NR(4, 28) +#define TX6UL_FEC2_INT_GPIO IMX_GPIO_NR(4, 27) + #define TX6UL_LED_GPIO IMX_GPIO_NR(5, 9) #define TX6UL_LCD_PWR_GPIO IMX_GPIO_NR(5, 4) #define TX6UL_LCD_RST_GPIO IMX_GPIO_NR(3, 4) #define TX6UL_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(4, 16) +#ifdef CONFIG_SYS_I2C_SOFT #define TX6UL_I2C1_SCL_GPIO CONFIG_SOFT_I2C_GPIO_SCL #define TX6UL_I2C1_SDA_GPIO CONFIG_SOFT_I2C_GPIO_SDA +#endif #define TX6UL_SD1_CD_GPIO IMX_GPIO_NR(4, 14) @@ -65,166 +71,195 @@ char __uboot_img_end[0] __attribute__((section(".__uboot_img_end"))); char __csf_data[0] __attribute__((section(".__csf_data"))); #endif +#define TX6UL_DEFAULT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST) +#define TX6UL_I2C_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \ + PAD_CTL_ODE | \ + PAD_CTL_HYS | \ + PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_34ohm | \ + PAD_CTL_SRE_FAST) +#define TX6UL_ENET_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_120ohm | \ + PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SRE_FAST) +#define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_60ohm | \ + PAD_CTL_SRE_SLOW) +#define TX6UL_GPIO_IN_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | \ + PAD_CTL_PUS_47K_UP) + + static const iomux_v3_cfg_t const tx6ul_pads[] = { /* UART pads */ #if CONFIG_MXC_UART_BASE == UART1_BASE - MX6_PAD_UART1_TX_DATA__UART1_DCE_TX, - MX6_PAD_UART1_RX_DATA__UART1_DCE_RX, - MX6_PAD_UART1_RTS_B__UART1_DCE_RTS, - MX6_PAD_UART1_CTS_B__UART1_DCE_CTS, + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL, #endif #if CONFIG_MXC_UART_BASE == UART2_BASE - MX6_PAD_UART2_TX_DATA__UART2_DCE_TX, - MX6_PAD_UART2_RX_DATA__UART2_DCE_RX, - MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS, - MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS, + MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL, #endif #if CONFIG_MXC_UART_BASE == UART5_BASE - MX6_PAD_GPIO1_IO04__UART5_DCE_TX, - MX6_PAD_GPIO1_IO05__UART5_DCE_RX, - MX6_PAD_GPIO1_IO08__UART5_DCE_RTS, - MX6_PAD_GPIO1_IO09__UART5_DCE_CTS, + MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL, + MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL, #endif - /* internal I2C */ - MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION | - MUX_PAD_CTRL(PAD_CTL_DSE_240ohm), /* I2C SCL */ - MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION | - MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS | - PAD_CTL_ODE), /* I2C SDA */ - /* FEC PHY GPIO functions */ - MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */ - MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */ - MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | - PAD_CTL_DSE_40ohm), /* PHY INT */ + MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */ + MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */ + MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */ }; -#define TX6_ENET_PAD_CTRL (PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_48ohm | \ - PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SRE_FAST) -#define TX6_GPIO_OUT_PAD_CTRL (PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_60ohm | \ - PAD_CTL_SRE_SLOW) -#define TX6_GPIO_IN_PAD_CTRL (PAD_CTL_SPEED_LOW | \ - PAD_CTL_PUS_47K_UP) - static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = { /* FEC functions */ - MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm | - PAD_CTL_SPEED_MED), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm | + PAD_CTL_SPEED_LOW), MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | - PAD_CTL_DSE_48ohm | - PAD_CTL_SPEED_MED), - MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION | - MUX_PAD_CTRL(PAD_CTL_SPEED_MED | - PAD_CTL_DSE_40ohm | - PAD_CTL_SRE_FAST), - MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - - MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION | - MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH | - PAD_CTL_DSE_48ohm | - PAD_CTL_SRE_FAST), - MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), - MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL), + PAD_CTL_DSE_120ohm | + PAD_CTL_SPEED_LOW), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | + PAD_CTL_DSE_80ohm | + PAD_CTL_SRE_SLOW), + + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL, }; -#define TX6_I2C_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ - PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_34ohm | \ - PAD_CTL_SRE_FAST) +static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = { + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | + PAD_CTL_DSE_80ohm | + PAD_CTL_SRE_SLOW), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL, + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL, +}; -static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = { +static const iomux_v3_cfg_t const tx6ul_i2c_pads[] = { /* internal I2C */ - MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL), - MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL), + MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION | + TX6UL_I2C_PAD_CTRL, /* I2C SCL */ + MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION | + TX6UL_I2C_PAD_CTRL, /* I2C SDA */ }; static const struct gpio const tx6ul_gpios[] = { +#ifdef CONFIG_SYS_I2C_SOFT /* These two entries are used to forcefully reinitialize the I2C bus */ { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", }, { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", }, - +#endif { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", }, { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", }, }; +static const struct gpio const tx6ul_fec2_gpios[] = { + { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", }, + { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", }, +}; + #define GPIO_DR 0 #define GPIO_DIR 4 #define GPIO_PSR 8 -static void tx6_i2c_recover(void) +/* run with default environment */ +#if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO) +#define SCL_BANK (TX6UL_I2C1_SCL_GPIO / 32) +#define SDA_BANK (TX6UL_I2C1_SDA_GPIO / 32) +#define SCL_BIT (1 << (TX6UL_I2C1_SCL_GPIO % 32)) +#define SDA_BIT (1 << (TX6UL_I2C1_SDA_GPIO % 32)) + +static void * const gpio_ports[] = { + (void *)GPIO1_BASE_ADDR, + (void *)GPIO2_BASE_ADDR, + (void *)GPIO3_BASE_ADDR, + (void *)GPIO4_BASE_ADDR, + (void *)GPIO5_BASE_ADDR, +}; + +static void tx6ul_i2c_recover(void) { int i; int bad = 0; -#define SCL_BIT (1 << (TX6UL_I2C1_SCL_GPIO % 32)) -#define SDA_BIT (1 << (TX6UL_I2C1_SDA_GPIO % 32)) -#define I2C_GPIO_BASE (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000) + struct gpio_regs *scl_regs = gpio_ports[SCL_BANK]; + struct gpio_regs *sda_regs = gpio_ports[SDA_BANK]; - if ((readl(I2C_GPIO_BASE + GPIO_PSR) & - (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) + if ((readl(&scl_regs->gpio_psr) & SCL_BIT) && + (readl(&sda_regs->gpio_psr) & SDA_BIT)) return; debug("Clearing I2C bus\n"); - if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) { + if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) { printf("I2C SCL stuck LOW\n"); bad++; - writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT, - I2C_GPIO_BASE + GPIO_DR); - writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT, - I2C_GPIO_BASE + GPIO_DIR); + setbits_le32(&scl_regs->gpio_dr, SCL_BIT); + setbits_le32(&scl_regs->gpio_dir, SCL_BIT); + + imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | + MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL); } - if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) { + if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) { printf("I2C SDA stuck LOW\n"); bad++; - writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT, - I2C_GPIO_BASE + GPIO_DIR); - writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT, - I2C_GPIO_BASE + GPIO_DR); - writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT, - I2C_GPIO_BASE + GPIO_DIR); + clrbits_le32(&sda_regs->gpio_dir, SDA_BIT); + setbits_le32(&scl_regs->gpio_dr, SCL_BIT); + setbits_le32(&scl_regs->gpio_dir, SCL_BIT); - imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads, - ARRAY_SIZE(tx6_i2c_gpio_pads)); - udelay(10); + udelay(5); for (i = 0; i < 18; i++) { - u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT; + u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT; debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear"); - writel(reg, I2C_GPIO_BASE + GPIO_DR); - udelay(10); - if (reg & SCL_BIT && - readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT) + writel(reg, &scl_regs->gpio_dr); + udelay(5); + if (reg & SCL_BIT) { + if (readl(&sda_regs->gpio_psr) & SDA_BIT) + break; + if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) + break; break; + } } } if (bad) { - u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR); + bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT); + bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT); - if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) { + if (scl && sda) { printf("I2C bus recovery succeeded\n"); } else { - printf("I2C bus recovery FAILED: %08x:%08x\n", reg, - SCL_BIT | SDA_BIT); + printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n", + scl, sda); } + imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads, + ARRAY_SIZE(tx6ul_i2c_pads)); } } +#else +static inline void tx6ul_i2c_recover(void) +{ +} +#endif /* placed in section '.data' to prevent overwriting relocation info * overlayed with bss @@ -343,23 +378,18 @@ int checkboard(void) u32 cpurev = get_cpu_rev(); char *cpu_str = "?"; - switch ((cpurev >> 12) & 0xff) { - case MXC_CPU_MX6SL: + if (is_cpu_type(MXC_CPU_MX6SL)) cpu_str = "SL"; - break; - case MXC_CPU_MX6DL: + else if (is_cpu_type(MXC_CPU_MX6DL)) cpu_str = "DL"; - break; - case MXC_CPU_MX6SOLO: + else if (is_cpu_type(MXC_CPU_MX6SOLO)) cpu_str = "SOLO"; - break; - case MXC_CPU_MX6Q: + else if (is_cpu_type(MXC_CPU_MX6Q)) cpu_str = "Q"; - break; - case MXC_CPU_MX6UL: + else if (is_cpu_type(MXC_CPU_MX6UL)) cpu_str = "UL"; - break; - } + else if (is_cpu_type(MXC_CPU_MX6ULL)) + cpu_str = "ULL"; printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n", cpu_str, @@ -372,7 +402,7 @@ int checkboard(void) #ifdef CONFIG_MX6_TEMPERATURE_HOT check_cpu_temperature(1); #endif - tx6_i2c_recover(); + tx6ul_i2c_recover(); return 0; } @@ -383,65 +413,86 @@ int board_early_init_f(void) } #ifndef CONFIG_MX6_TEMPERATURE_HOT -static bool tx6_temp_check_enabled = true; +static bool tx6ul_temp_check_enabled = true; #else -#define tx6_temp_check_enabled 0 +#define tx6ul_temp_check_enabled 0 #endif static inline u8 tx6ul_mem_suffix(void) { -#ifdef CONFIG_TX6_NAND - return '0'; -#else - return '1'; -#endif + return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 + + IS_ENABLED(CONFIG_TX6_EMMC); } +#ifdef CONFIG_RN5T567 /* PMIC settings */ #define VDD_RTC_VAL rn5t_mV_to_regval_rtc(3000) #define VDD_CORE_VAL rn5t_mV_to_regval(1300) /* DCDC1 */ #define VDD_CORE_VAL_LP rn5t_mV_to_regval(900) #define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 */ #define VDD_DDR_VAL_LP rn5t_mV_to_regval(1350) -#define VDD_HIGH_VAL rn5t_mV_to_regval(3300) /* DCDC4 */ -#define VDD_HIGH_VAL_LP rn5t_mV_to_regval(3300) -#define VDD_CSI_VAL rn5t_mV_to_regval2(3300) /* LDO4 */ -#define VDD_CSI_VAL_LP rn5t_mV_to_regval2(3300) +#define VDD_IO_EXT_VAL rn5t_mV_to_regval(3300) /* DCDC4 */ +#define VDD_IO_EXT_VAL_LP rn5t_mV_to_regval(3300) +#define VDD_IO_INT_VAL rn5t_mV_to_regval2(3300) /* LDO1 */ +#define VDD_IO_INT_VAL_LP rn5t_mV_to_regval2(3300) +#define VDD_ADC_VAL rn5t_mV_to_regval2(3300) /* LDO2 */ +#define VDD_ADC_VAL_LP rn5t_mV_to_regval2(3300) +#define VDD_PMIC_VAL rn5t_mV_to_regval2(2500) /* LDO3 */ +#define VDD_PMIC_VAL_LP rn5t_mV_to_regval2(2500) +#define VDD_CSI_VAL rn5t_mV_to_regval2(1800) /* LDO4 */ +#define VDD_CSI_VAL_LP rn5t_mV_to_regval2(1800) static struct pmic_regs rn5t567_regs[] = { { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, }, - { RN5T567_DC2CTL, DC2_DC2DIS, }, { RN5T567_DC1DAC, VDD_CORE_VAL, }, { RN5T567_DC3DAC, VDD_DDR_VAL, }, - { RN5T567_DC4DAC, VDD_HIGH_VAL, }, + { RN5T567_DC4DAC, VDD_IO_EXT_VAL, }, { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, }, { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, }, - { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, }, - { RN5T567_LDOEN1, 0x01f, ~0x1f, }, - { RN5T567_LDOEN2, 0x10, ~0x30, }, - { RN5T567_LDODIS, 0x00, }, - { RN5T567_LDO4DAC, VDD_CSI_VAL, }, + { RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, }, + { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), }, + { RN5T567_DC2CTL, DCnCTL_DCnDIS, }, + { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), }, + { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), }, { RN5T567_LDORTC1DAC, VDD_RTC_VAL, }, { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, }, + { RN5T567_LDO1DAC, VDD_IO_INT_VAL, }, + { RN5T567_LDO2DAC, VDD_ADC_VAL, }, + { RN5T567_LDO3DAC, VDD_PMIC_VAL, }, + { RN5T567_LDO4DAC, VDD_CSI_VAL, }, + { RN5T567_LDOEN1, 0x0f, ~0x1f, }, + { RN5T567_LDOEN2, 0x10, ~0x30, }, + { RN5T567_LDODIS, 0x10, ~0x1f, }, + { RN5T567_INTPOL, 0, }, + { RN5T567_INTEN, 0x3, }, + { RN5T567_IREN, 0xf, }, + { RN5T567_EN_GPIR, 0, }, }; -static int pmic_addr __maybe_unused = 0x33; +static int pmic_addr = 0x33; +#endif int board_init(void) { int ret; + u32 cpurev = get_cpu_rev(); + char f = '?'; - debug("%s@%d: \n", __func__, __LINE__); + if (is_cpu_type(MXC_CPU_MX6UL)) + f = ((cpurev & 0xf0) > 0x10) ? '5' : '0'; + else if (is_cpu_type(MXC_CPU_MX6ULL)) + f = '8'; - printf("Board: Ka-Ro TXUL-001%c\n", - tx6ul_mem_suffix()); + debug("%s@%d: cpurev=%08x\n", __func__, __LINE__, cpurev); + + printf("Board: Ka-Ro TXUL-%c01%c\n", f, tx6ul_mem_suffix()); get_hab_status(); ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios)); - if (ret < 0) { + if (ret < 0) printf("Failed to request tx6ul_gpios: %d\n", ret); - } + imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads)); /* Address of boot parameters */ @@ -454,7 +505,7 @@ int board_init(void) else printf(" detected; safeboot enabled\n"); #ifndef CONFIG_MX6_TEMPERATURE_HOT - tx6_temp_check_enabled = false; + tx6ul_temp_check_enabled = false; #endif return 0; } @@ -473,7 +524,7 @@ int dram_init(void) /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS); + PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS); return 0; } @@ -483,46 +534,46 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); + PHYS_SDRAM_1_SIZE); #if CONFIG_NR_DRAM_BANKS > 1 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, - PHYS_SDRAM_2_SIZE); + PHYS_SDRAM_2_SIZE); #endif } #ifdef CONFIG_FSL_ESDHC -#define TX6_SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST) +#define TX6UL_SD_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST) static const iomux_v3_cfg_t mmc0_pads[] = { - MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL, + MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL, + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL, + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL, + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL, + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL, /* SD1 CD */ - MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), + MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL, }; #ifdef CONFIG_TX6_EMMC static const iomux_v3_cfg_t mmc1_pads[] = { - MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), - MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL, + MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL, + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL, + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL, + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL, + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL, /* eMMC RESET */ MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | - PAD_CTL_DSE_40ohm), + PAD_CTL_DSE_40ohm), }; #endif -static struct tx6_esdhc_cfg { +static struct tx6ul_esdhc_cfg { const iomux_v3_cfg_t *pads; int num_pads; enum mxc_clock clkid; @@ -553,22 +604,22 @@ static struct tx6_esdhc_cfg { }, }; -static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg) +static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg) { - return container_of(cfg, struct tx6_esdhc_cfg, cfg); + return container_of(cfg, struct tx6ul_esdhc_cfg, cfg); } int board_mmc_getcd(struct mmc *mmc) { - struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv); + struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv); if (cfg->cd_gpio < 0) return 1; debug("SD card %d is %spresent (GPIO %d)\n", - cfg - tx6ul_esdhc_cfg, - gpio_get_value(cfg->cd_gpio) ? "NOT " : "", - cfg->cd_gpio); + cfg - tx6ul_esdhc_cfg, + gpio_get_value(cfg->cd_gpio) ? "NOT " : "", + cfg->cd_gpio); return !gpio_get_value(cfg->cd_gpio); } @@ -578,9 +629,15 @@ int board_mmc_init(bd_t *bis) debug("%s@%d: \n", __func__, __LINE__); +#ifndef CONFIG_ENV_IS_IN_MMC + if (!(gd->flags & GD_FLG_ENV_READY)) { + printf("deferred ..."); + return 0; + } +#endif for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) { struct mmc *mmc; - struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i]; + struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i]; int ret; cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid); @@ -588,10 +645,11 @@ int board_mmc_init(bd_t *bis) if (cfg->cd_gpio >= 0) { ret = gpio_request_one(cfg->cd_gpio, - GPIOFLAG_INPUT, "MMC CD"); + GPIOFLAG_INPUT, "MMC CD"); if (ret) { printf("Error %d requesting GPIO%d_%d\n", - ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32); + ret, cfg->cd_gpio / 32, + cfg->cd_gpio % 32); continue; } } @@ -607,77 +665,18 @@ int board_mmc_init(bd_t *bis) } return 0; } -#endif /* CONFIG_CMD_MMC */ - -#ifdef CONFIG_FEC_MXC - -#ifndef ETH_ALEN -#define ETH_ALEN 6 -#endif - -int board_eth_init(bd_t *bis) -{ - int ret; - - debug("%s@%d: \n", __func__, __LINE__); - - /* delay at least 21ms for the PHY internal POR signal to deassert */ - udelay(22000); - - imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads, - ARRAY_SIZE(tx6ul_enet1_pads)); - - /* Deassert RESET to the external phy */ - gpio_set_value(TX6UL_FEC_RST_GPIO, 1); - - if (getenv("ethaddr")) { - ret = fecmxc_initialize_multi(bis, 0, -1, ENET_BASE_ADDR); - if (ret) { - printf("failed to initialize FEC0: %d\n", ret); - return ret; - } - } - if (getenv("eth1addr")) { - ret = fecmxc_initialize_multi(bis, 1, -1, ENET2_BASE_ADDR); - if (ret) { - printf("failed to initialize FEC1: %d\n", ret); - return ret; - } - } - return 0; -} - -static void tx6_init_mac(void) -{ - u8 mac[ETH_ALEN]; - - imx_get_mac_from_fuse(0, mac); - if (!is_valid_ethaddr(mac)) { - printf("No valid MAC address programmed\n"); - return; - } - - printf("MAC addr from fuse: %pM\n", mac); - eth_setenv_enetaddr("ethaddr", mac); - - imx_get_mac_from_fuse(1, mac); - eth_setenv_enetaddr("eth1addr", mac); -} -#else -static inline void tx6_init_mac(void) -{ -} -#endif /* CONFIG_FEC_MXC */ +#endif /* CONFIG_FSL_ESDHC */ enum { LED_STATE_INIT = -1, LED_STATE_OFF, LED_STATE_ON, + LED_STATE_ERR, }; static inline int calc_blink_rate(void) { - if (!tx6_temp_check_enabled) + if (!tx6ul_temp_check_enabled) return CONFIG_SYS_HZ; return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 - @@ -690,13 +689,24 @@ void show_activity(int arg) static int led_state = LED_STATE_INIT; static int blink_rate; static ulong last; + int ret; + + switch (led_state) { + case LED_STATE_ERR: + return; - if (led_state == LED_STATE_INIT) { + case LED_STATE_INIT: last = get_timer(0); - gpio_set_value(TX6UL_LED_GPIO, 1); - led_state = LED_STATE_ON; + ret = gpio_set_value(TX6UL_LED_GPIO, 1); + if (ret) + led_state = LED_STATE_ERR; + else + led_state = LED_STATE_ON; blink_rate = calc_blink_rate(); - } else { + break; + + case LED_STATE_ON: + case LED_STATE_OFF: if (get_timer(last) > blink_rate) { blink_rate = calc_blink_rate(); last = get_timer_masked(); @@ -707,43 +717,114 @@ void show_activity(int arg) } led_state = 1 - led_state; } + break; } } +static const iomux_v3_cfg_t stk5_jtag_pads[] = { + MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL, + MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL, + MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL, + MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL, + MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL, + MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL, +}; + static const iomux_v3_cfg_t stk5_pads[] = { /* SW controlled LED on STK5 baseboard */ MX6_PAD_SNVS_TAMPER9__GPIO5_IO09, /* I2C bus on DIMM pins 40/41 */ - MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL), - MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL), + MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL, + MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL, /* TSC200x PEN IRQ */ - MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), -#if 0 + MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL, + /* EDT-FT5x06 Polytouch panel */ - MX6_PAD_NAND_CS2__GPIO6_IO15 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */ - MX6_PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */ - MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */ + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */ + MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */ + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */ /* USBH1 */ - MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */ - MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */ + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */ + MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */ + /* USBOTG */ - MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* USBOTG ID */ - MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */ - MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */ -#endif + MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */ + MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */ }; static const struct gpio stk5_gpios[] = { { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, - { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", }, - { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", }, - { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", }, - { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", }, - { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, + { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", }, + { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", }, +}; + +static const iomux_v3_cfg_t tx_tester_pads[] = { + /* SW controlled LEDs on TX-TESTER-V5 baseboard */ + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04, /* red LED */ + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09, /* yellow LED */ + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08, /* green LED */ + + MX6_PAD_LCD_DATA04__GPIO3_IO09, /* IO_RESET */ + + /* I2C bus on DIMM pins 40/41 */ + MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL, + MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL, + + /* USBH1 */ + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */ + MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */ + + /* USBOTG */ + MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */ + MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */ + + MX6_PAD_LCD_DATA08__GPIO3_IO13 | TX6UL_GPIO_OUT_PAD_CTRL, + MX6_PAD_LCD_DATA09__GPIO3_IO14 | TX6UL_GPIO_OUT_PAD_CTRL, + MX6_PAD_LCD_DATA10__GPIO3_IO15 | TX6UL_GPIO_OUT_PAD_CTRL, + + /* USBH_VBUSEN */ + MX6_PAD_LCD_DATA11__GPIO3_IO16 | TX6UL_GPIO_OUT_PAD_CTRL, + + /* + * no drive capability for DUT_ETN_LINKLED, DUT_ETN_ACTLED + * to not interfere whith the DUT ETN PHY strap pins + */ + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02, MUX_PAD_CTRL(PAD_CTL_HYS | + PAD_CTL_DSE_DISABLE | + PAD_CTL_SPEED_LOW), + MX6_PAD_SNVS_TAMPER3__GPIO5_IO03, MUX_PAD_CTRL(PAD_CTL_HYS | + PAD_CTL_DSE_DISABLE | + PAD_CTL_SPEED_LOW), +}; + +static const struct gpio tx_tester_gpios[] = { + { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LEDGE#", }, + { IMX_GPIO_NR(5, 4), GPIOFLAG_OUTPUT_INIT_LOW, "LEDRT#", }, + { IMX_GPIO_NR(5, 8), GPIOFLAG_OUTPUT_INIT_LOW, "LEDGN#", }, + + { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_HIGH, "PMIC PWR_ON", }, + + { IMX_GPIO_NR(3, 5), GPIOFLAG_INPUT, "TSTART#", }, + { IMX_GPIO_NR(3, 6), GPIOFLAG_INPUT, "STARTED", }, + { IMX_GPIO_NR(3, 7), GPIOFLAG_INPUT, "TSTOP#", }, + { IMX_GPIO_NR(3, 8), GPIOFLAG_OUTPUT_INIT_LOW, "STOP#", }, + + { IMX_GPIO_NR(3, 10), GPIOFLAG_INPUT, "DUT_PGOOD", }, + + { IMX_GPIO_NR(3, 11), GPIOFLAG_OUTPUT_INIT_HIGH, "VBACKUP_OFF", }, + { IMX_GPIO_NR(3, 12), GPIOFLAG_OUTPUT_INIT_LOW, "VBACKUP_LOAD", }, + + { IMX_GPIO_NR(1, 10), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD1", }, + { IMX_GPIO_NR(3, 30), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD2", }, + { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD3", }, + + { IMX_GPIO_NR(3, 13), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD1", }, + { IMX_GPIO_NR(3, 14), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD2", }, + { IMX_GPIO_NR(3, 15), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD3", }, }; #ifdef CONFIG_LCD @@ -755,7 +836,7 @@ vidinfo_t panel_info = { .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ }; -static struct fb_videomode tx6_fb_modes[] = { +static struct fb_videomode tx6ul_fb_modes[] = { #ifndef CONFIG_SYS_LVDS_IF { /* Standard VGA timing */ @@ -931,47 +1012,14 @@ static int lcd_backlight_polarity(void) return lcd_bl_polarity; } -void lcd_enable(void) -{ - /* HACK ALERT: - * global variable from common/lcd.c - * Set to 0 here to prevent messages from going to LCD - * rather than serial console - */ - lcd_is_enabled = 0; - - if (lcd_enabled) { - karo_load_splashimage(1); - - debug("Switching LCD on\n"); - gpio_set_value(TX6UL_LCD_PWR_GPIO, 1); - udelay(100); - gpio_set_value(TX6UL_LCD_RST_GPIO, 1); - udelay(300000); - gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO, - lcd_backlight_polarity()); - } -} - -void lcd_disable(void) -{ - if (lcd_enabled) { - printf("Disabling LCD\n"); - panel_info.vl_row = 0; - lcd_enabled = 0; - } -} - static const iomux_v3_cfg_t stk5_lcd_pads[] = { -#if 1 +#ifdef CONFIG_LCD /* LCD RESET */ - MX6_PAD_LCD_RESET__LCDIF_RESET, + MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL, /* LCD POWER_ENABLE */ - MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL, /* LCD Backlight (PWM) */ - MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), -#endif -#ifdef CONFIG_LCD + MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL, /* Display */ MX6_PAD_LCD_DATA00__LCDIF_DATA00, MX6_PAD_LCD_DATA01__LCDIF_DATA01, @@ -1010,6 +1058,38 @@ static const struct gpio stk5_lcd_gpios[] = { { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, }; +/* run with valid env from NAND/eMMC */ +void lcd_enable(void) +{ + /* HACK ALERT: + * global variable from common/lcd.c + * Set to 0 here to prevent messages from going to LCD + * rather than serial console + */ + lcd_is_enabled = 0; + + if (lcd_enabled) { + karo_load_splashimage(1); + + debug("Switching LCD on\n"); + gpio_set_value(TX6UL_LCD_PWR_GPIO, 1); + udelay(100); + gpio_set_value(TX6UL_LCD_RST_GPIO, 1); + udelay(300000); + gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO, + lcd_backlight_polarity()); + } +} + +static void lcd_disable(void) +{ + if (lcd_enabled) { + printf("Disabling LCD\n"); + panel_info.vl_row = 0; + lcd_enabled = 0; + } +} + void lcd_ctrl_init(void *lcdbase) { int color_depth = 24; @@ -1017,7 +1097,7 @@ void lcd_ctrl_init(void *lcdbase) const char *vm; unsigned long val; int refresh = 60; - struct fb_videomode *p = &tx6_fb_modes[0]; + struct fb_videomode *p = &tx6ul_fb_modes[0]; struct fb_videomode fb_mode; int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0; @@ -1047,8 +1127,8 @@ void lcd_ctrl_init(void *lcdbase) if (fb_mode.xres > panel_info.vl_col || fb_mode.yres > panel_info.vl_row) { printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n", - fb_mode.xres, fb_mode.yres, - panel_info.vl_col, panel_info.vl_row); + fb_mode.xres, fb_mode.yres, + panel_info.vl_col, panel_info.vl_row); lcd_enabled = 0; return; } @@ -1095,7 +1175,8 @@ void lcd_ctrl_init(void *lcdbase) default: printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n", - end - vm, vm, color_depth); + end - vm, vm, + color_depth); } bpp_set = 1; } else if (!refresh_set) { @@ -1129,7 +1210,7 @@ void lcd_ctrl_init(void *lcdbase) printf("Invalid video mode: %s\n", getenv("video_mode")); lcd_enabled = 0; printf("Supported video modes are:"); - for (p = &tx6_fb_modes[0]; p->name != NULL; p++) { + for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) { printf(" %s", p->name); } printf("\n"); @@ -1137,7 +1218,7 @@ void lcd_ctrl_init(void *lcdbase) } if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) { printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n", - p->xres, p->yres, panel_info.vl_col, panel_info.vl_row); + p->xres, p->yres, panel_info.vl_col, panel_info.vl_row); lcd_enabled = 0; return; } @@ -1160,35 +1241,35 @@ void lcd_ctrl_init(void *lcdbase) (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) / 1000); debug("Pixel clock set to %lu.%03lu MHz\n", - PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000); + PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000); if (p != &fb_mode) { int ret; debug("Creating new display-timing node from '%s'\n", - video_mode); + video_mode); ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p); if (ret) printf("Failed to create new display-timing node from '%s': %d\n", - video_mode, ret); + video_mode, ret); } gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios)); imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads, - ARRAY_SIZE(stk5_lcd_pads)); + ARRAY_SIZE(stk5_lcd_pads)); debug("video format: %ux%u-%u@%u\n", p->xres, p->yres, - color_depth, refresh); + color_depth, refresh); if (karo_load_splashimage(0) == 0) { char vmode[128]; /* setup env variable for mxsfb display driver */ snprintf(vmode, sizeof(vmode), - "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d", - p->xres, p->yres, p->left_margin, p->right_margin, - p->upper_margin, p->lower_margin, p->hsync_len, - p->vsync_len, p->sync, p->pixclock, color_depth); + "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d", + p->xres, p->yres, p->left_margin, p->right_margin, + p->upper_margin, p->lower_margin, p->hsync_len, + p->vsync_len, p->sync, p->pixclock, color_depth); setenv("videomode", vmode); debug("Initializing LCD controller\n"); @@ -1203,6 +1284,20 @@ void lcd_ctrl_init(void *lcdbase) #define lcd_enabled 0 #endif /* CONFIG_LCD */ +#ifndef CONFIG_ENV_IS_IN_MMC +static void tx6ul_mmc_init(void) +{ + puts("MMC: "); + if (board_mmc_init(gd->bd) < 0) + cpu_mmc_init(gd->bd); + print_mmc_devices(','); +} +#else +static inline void tx6ul_mmc_init(void) +{ +} +#endif + static void stk5_board_init(void) { int ret; @@ -1212,15 +1307,22 @@ static void stk5_board_init(void) printf("Failed to request stk5_gpios: %d\n", ret); return; } + imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads)); -debug("%s@%d: \n", __func__, __LINE__); + if (getenv_yesno("jtag_enable") != 0) { + /* true if unset or set to one of: 'yYtT1' */ + imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads)); + } + + debug("%s@%d: \n", __func__, __LINE__); } static void stk5v3_board_init(void) { -debug("%s@%d: \n", __func__, __LINE__); + debug("%s@%d: \n", __func__, __LINE__); stk5_board_init(); -debug("%s@%d: \n", __func__, __LINE__); + debug("%s@%d: \n", __func__, __LINE__); + tx6ul_mmc_init(); } static void stk5v5_board_init(void) @@ -1228,16 +1330,45 @@ static void stk5v5_board_init(void) int ret; stk5_board_init(); + tx6ul_mmc_init(); ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH, - "Flexcan Transceiver"); + "Flexcan Transceiver"); if (ret) { printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret); return; } imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 | - MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL)); + TX6UL_GPIO_OUT_PAD_CTRL); +} + +static void tx_tester_board_init(void) +{ + int ret; + + setenv("video_mode", NULL); + setenv("touchpanel", NULL); + if (getenv("eth1addr") && !getenv("ethprime")) + setenv("ethprime", "FEC1"); + + ret = gpio_request_array(tx_tester_gpios, ARRAY_SIZE(tx_tester_gpios)); + if (ret) { + printf("Failed to request TX-Tester GPIOs: %d\n", ret); + return; + } + imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads)); + + if (wrsr & WRSR_TOUT) + gpio_set_value(IMX_GPIO_NR(5, 4), 1); + + if (getenv_yesno("jtag_enable") != 0) { + /* true if unset or set to one of: 'yYtT1' */ + imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, + ARRAY_SIZE(stk5_jtag_pads)); + } + + gpio_set_value(IMX_GPIO_NR(3, 8), 1); } static void tx6ul_set_cpu_clock(void) @@ -1249,13 +1380,13 @@ static void tx6ul_set_cpu_clock(void) if (had_ctrlc() || (wrsr & WRSR_TOUT)) { printf("%s detected; skipping cpu clock change\n", - (wrsr & WRSR_TOUT) ? "WDOG RESET" : ""); + (wrsr & WRSR_TOUT) ? "WDOG RESET" : ""); return; } if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) { cpu_clk = mxc_get_clock(MXC_ARM_CLK); printf("CPU clock set to %lu.%03lu MHz\n", - cpu_clk / 1000000, cpu_clk / 1000 % 1000); + cpu_clk / 1000000, cpu_clk / 1000 % 1000); } else { printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk); } @@ -1263,14 +1394,13 @@ static void tx6ul_set_cpu_clock(void) int board_late_init(void) { - int ret = 0; const char *baseboard; debug("%s@%d: \n", __func__, __LINE__); env_cleanup(); - if (tx6_temp_check_enabled) + if (tx6ul_temp_check_enabled) check_cpu_temperature(1); tx6ul_set_cpu_clock(); @@ -1297,7 +1427,7 @@ int board_late_init(void) if (otg_mode && strcmp(otg_mode, "host") == 0) { printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n", - otg_mode, baseboard); + otg_mode, baseboard); setenv("otg_mode", "none"); } stk5v5_board_init(); @@ -1305,21 +1435,166 @@ int board_late_init(void) printf("WARNING: Unsupported STK5 board rev.: %s\n", baseboard + 4); } + } else if (strncmp(baseboard, "ulmb-", 5) == 0) { + const char *otg_mode = getenv("otg_mode"); + + if (otg_mode && strcmp(otg_mode, "host") == 0) { + printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n", + otg_mode, baseboard); + setenv("otg_mode", "none"); + } + stk5_board_init(); + } else if (strncmp(baseboard, "tx-tester-", 10) == 0) { + const char *otg_mode = getenv("otg_mode"); + + if (!otg_mode || strcmp(otg_mode, "none") != 0) + setenv("otg_mode", "device"); + tx_tester_board_init(); } else { printf("WARNING: Unsupported baseboard: '%s'\n", baseboard); - ret = -EINVAL; + printf("Reboot with pressed to fix this\n"); + if (!had_ctrlc()) + return -EINVAL; } exit: -debug("%s@%d: \n", __func__, __LINE__); - tx6_init_mac(); -debug("%s@%d: \n", __func__, __LINE__); + debug("%s@%d: \n", __func__, __LINE__); clear_ctrlc(); - return ret; + return 0; +} + +#ifdef CONFIG_FEC_MXC + +#ifndef ETH_ALEN +#define ETH_ALEN 6 +#endif + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + unsigned int mac0, mac1, mac2; + unsigned int __maybe_unused fuse3_override, fuse4_override; + + memset(mac, 0, 6); + + switch (dev_id) { + case 0: + if (fuse_read(4, 2, &mac0)) { + printf("Failed to read MAC0 fuse\n"); + return; + } + if (fuse_read(4, 3, &mac1)) { + printf("Failed to read MAC1 fuse\n"); + return; + } + mac[0] = mac1 >> 8; + mac[1] = mac1; + mac[2] = mac0 >> 24; + mac[3] = mac0 >> 16; + mac[4] = mac0 >> 8; + mac[5] = mac0; + break; + + case 1: + if (fuse_read(4, 3, &mac1)) { + printf("Failed to read MAC1 fuse\n"); + return; + } + debug("read %08x from fuse 3\n", mac1); + if (fuse_read(4, 4, &mac2)) { + printf("Failed to read MAC2 fuse\n"); + return; + } + debug("read %08x from fuse 4\n", mac2); + mac[0] = mac2 >> 24; + mac[1] = mac2 >> 16; + mac[2] = mac2 >> 8; + mac[3] = mac2; + mac[4] = mac1 >> 24; + mac[5] = mac1 >> 16; + break; + + default: + return; + } + debug("%s@%d: Done %d %pM\n", __func__, __LINE__, dev_id, mac); +} + +static void tx6ul_init_mac(void) +{ + u8 mac[ETH_ALEN]; + const char *baseboard = getenv("baseboard"); + + imx_get_mac_from_fuse(0, mac); + if (!is_valid_ethaddr(mac)) { + printf("No valid MAC address programmed\n"); + return; + } + printf("MAC addr from fuse: %pM\n", mac); + if (!getenv("ethaddr")) + eth_setenv_enetaddr("ethaddr", mac); + + if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) { + setenv("eth1addr", NULL); + return; + } + if (getenv("eth1addr")) + return; + imx_get_mac_from_fuse(1, mac); + if (is_valid_ethaddr(mac)) + eth_setenv_enetaddr("eth1addr", mac); } +int board_eth_init(bd_t *bis) +{ + int ret; + + tx6ul_init_mac(); + + /* delay at least 21ms for the PHY internal POR signal to deassert */ + udelay(22000); + + imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads, + ARRAY_SIZE(tx6ul_enet1_pads)); + + /* Deassert RESET to the external phys */ + gpio_set_value(TX6UL_FEC_RST_GPIO, 1); + + if (getenv("ethaddr")) { + ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR); + if (ret) { + printf("failed to initialize FEC0: %d\n", ret); + return ret; + } + } + if (getenv("eth1addr")) { + ret = gpio_request_array(tx6ul_fec2_gpios, + ARRAY_SIZE(tx6ul_fec2_gpios)); + if (ret < 0) { + printf("Failed to request tx6ul_fec2_gpios: %d\n", ret); + } + imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads, + ARRAY_SIZE(tx6ul_enet2_pads)); + + writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */ + + /* Minimum PHY reset duration */ + udelay(100); + gpio_set_value(TX6UL_FEC2_RST_GPIO, 1); + /* Wait for PHY internal POR to finish */ + udelay(22000); + + ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR); + if (ret) { + printf("failed to initialize FEC1: %d\n", ret); + return ret; + } + } + return 0; +} +#endif /* CONFIG_FEC_MXC */ + #ifdef CONFIG_SERIAL_TAG void get_board_serial(struct tag_serialnr *serialnr) { @@ -1342,7 +1617,7 @@ static struct node_info nodes[] = { #define fdt_fixup_mtdparts(b,n,c) do { } while (0) #endif -static const char *tx6_touchpanels[] = { +static const char *tx6ul_touchpanels[] = { "ti,tsc2007", "edt,edt-ft5x06", "eeti,egalax_ts", @@ -1365,12 +1640,12 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); - karo_fdt_fixup_touchpanel(blob, tx6_touchpanels, - ARRAY_SIZE(tx6_touchpanels)); + karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels, + ARRAY_SIZE(tx6ul_touchpanels)); karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply"); karo_fdt_fixup_flexcan(blob, stk5_v5); - karo_fdt_update_fb_mode(blob, video_mode); + karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel"); return 0; }