X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=board%2Fkaro%2Ftx6%2Ftx6ul.c;h=ceabaa2a5a9bbc3cedead84a18040b0f4b97f784;hp=a2dbf236319f3c070a08d74544e7b2d03a9f50fe;hb=1895d9be35cfc80bdf777b48520250c7030f9c85;hpb=2196e85bcf694759bdc1110f0fbe7733a04e2f7f diff --git a/board/karo/tx6/tx6ul.c b/board/karo/tx6/tx6ul.c index a2dbf23631..ceabaa2a5a 100644 --- a/board/karo/tx6/tx6ul.c +++ b/board/karo/tx6/tx6ul.c @@ -76,12 +76,13 @@ char __csf_data[0] __attribute__((section(".__csf_data"))); PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST) #define TX6UL_I2C_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \ + PAD_CTL_ODE | \ PAD_CTL_HYS | \ PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_34ohm | \ PAD_CTL_SRE_FAST) #define TX6UL_ENET_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_48ohm | \ + PAD_CTL_DSE_120ohm | \ PAD_CTL_PUS_100K_UP | \ PAD_CTL_SRE_FAST) #define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | \ @@ -91,7 +92,7 @@ char __csf_data[0] __attribute__((section(".__csf_data"))); PAD_CTL_PUS_47K_UP) -static const iomux_v3_cfg_t const tx6ul_pads[] = { +static const iomux_v3_cfg_t tx6ul_pads[] = { /* UART pads */ #if CONFIG_MXC_UART_BASE == UART1_BASE MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL, @@ -117,15 +118,17 @@ static const iomux_v3_cfg_t const tx6ul_pads[] = { MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */ }; -static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = { +static const iomux_v3_cfg_t tx6ul_enet1_pads[] = { /* FEC functions */ - MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm | - PAD_CTL_SPEED_MED), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm | + PAD_CTL_SPEED_LOW), MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | - PAD_CTL_DSE_48ohm | PAD_CTL_SPEED_MED), - MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION | - MUX_PAD_CTRL(PAD_CTL_SPEED_MED | - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST), + PAD_CTL_DSE_120ohm | + PAD_CTL_SPEED_LOW), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | + PAD_CTL_DSE_80ohm | + PAD_CTL_SRE_SLOW), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL, MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL, MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL, @@ -135,10 +138,10 @@ static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = { MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL, }; -static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = { - MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION | - MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH | - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST), +static const iomux_v3_cfg_t tx6ul_enet2_pads[] = { + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | + PAD_CTL_DSE_80ohm | + PAD_CTL_SRE_SLOW), MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL, MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL, MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL, @@ -148,17 +151,15 @@ static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = { MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL, }; -static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = { +static const iomux_v3_cfg_t tx6ul_i2c_pads[] = { /* internal I2C */ MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION | - MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS | - PAD_CTL_ODE), /* I2C SCL */ + TX6UL_I2C_PAD_CTRL, /* I2C SCL */ MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION | - MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS | - PAD_CTL_ODE), /* I2C SDA */ + TX6UL_I2C_PAD_CTRL, /* I2C SDA */ }; -static const struct gpio const tx6ul_gpios[] = { +static const struct gpio tx6ul_gpios[] = { #ifdef CONFIG_SYS_I2C_SOFT /* These two entries are used to forcefully reinitialize the I2C bus */ { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", }, @@ -169,7 +170,7 @@ static const struct gpio const tx6ul_gpios[] = { { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", }, }; -static const struct gpio const tx6ul_fec2_gpios[] = { +static const struct gpio tx6ul_fec2_gpios[] = { { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", }, { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", }, }; @@ -180,67 +181,82 @@ static const struct gpio const tx6ul_fec2_gpios[] = { /* run with default environment */ #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO) -static void tx6_i2c_recover(void) +#define SCL_BANK (TX6UL_I2C1_SCL_GPIO / 32) +#define SDA_BANK (TX6UL_I2C1_SDA_GPIO / 32) +#define SCL_BIT (1 << (TX6UL_I2C1_SCL_GPIO % 32)) +#define SDA_BIT (1 << (TX6UL_I2C1_SDA_GPIO % 32)) + +static void * const gpio_ports[] = { + (void *)GPIO1_BASE_ADDR, + (void *)GPIO2_BASE_ADDR, + (void *)GPIO3_BASE_ADDR, + (void *)GPIO4_BASE_ADDR, + (void *)GPIO5_BASE_ADDR, +}; + +static void tx6ul_i2c_recover(void) { int i; int bad = 0; -#define SCL_BIT (1 << (TX6UL_I2C1_SCL_GPIO % 32)) -#define SDA_BIT (1 << (TX6UL_I2C1_SDA_GPIO % 32)) -#define I2C_GPIO_BASE (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000) + struct gpio_regs *scl_regs = gpio_ports[SCL_BANK]; + struct gpio_regs *sda_regs = gpio_ports[SDA_BANK]; - if ((readl(I2C_GPIO_BASE + GPIO_PSR) & - (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) + if ((readl(&scl_regs->gpio_psr) & SCL_BIT) && + (readl(&sda_regs->gpio_psr) & SDA_BIT)) return; debug("Clearing I2C bus\n"); - if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) { + if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) { printf("I2C SCL stuck LOW\n"); bad++; - writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT, - I2C_GPIO_BASE + GPIO_DR); - writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT, - I2C_GPIO_BASE + GPIO_DIR); + setbits_le32(&scl_regs->gpio_dr, SCL_BIT); + setbits_le32(&scl_regs->gpio_dir, SCL_BIT); + + imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | + MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL); } - if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) { + if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) { printf("I2C SDA stuck LOW\n"); bad++; - writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT, - I2C_GPIO_BASE + GPIO_DIR); - writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT, - I2C_GPIO_BASE + GPIO_DR); - writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT, - I2C_GPIO_BASE + GPIO_DIR); + clrbits_le32(&sda_regs->gpio_dir, SDA_BIT); + setbits_le32(&scl_regs->gpio_dr, SCL_BIT); + setbits_le32(&scl_regs->gpio_dir, SCL_BIT); - imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads, - ARRAY_SIZE(tx6_i2c_gpio_pads)); - udelay(10); + udelay(5); for (i = 0; i < 18; i++) { - u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT; + u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT; debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear"); - writel(reg, I2C_GPIO_BASE + GPIO_DR); - udelay(10); - if (reg & SCL_BIT && - readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT) + writel(reg, &scl_regs->gpio_dr); + udelay(5); + if (reg & SCL_BIT) { + if (readl(&sda_regs->gpio_psr) & SDA_BIT) + break; + if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) + break; break; + } } } if (bad) { - u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR); + bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT); + bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT); - if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) { + if (scl && sda) { printf("I2C bus recovery succeeded\n"); } else { - printf("I2C bus recovery FAILED: %08x:%08x\n", reg, - SCL_BIT | SDA_BIT); + printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n", + scl, sda); } + imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads, + ARRAY_SIZE(tx6ul_i2c_pads)); } } #else -static inline void tx6_i2c_recover(void) +static inline void tx6ul_i2c_recover(void) { } #endif @@ -372,6 +388,8 @@ int checkboard(void) cpu_str = "Q"; else if (is_cpu_type(MXC_CPU_MX6UL)) cpu_str = "UL"; + else if (is_cpu_type(MXC_CPU_MX6ULL)) + cpu_str = "ULL"; printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n", cpu_str, @@ -384,7 +402,7 @@ int checkboard(void) #ifdef CONFIG_MX6_TEMPERATURE_HOT check_cpu_temperature(1); #endif - tx6_i2c_recover(); + tx6ul_i2c_recover(); return 0; } @@ -395,18 +413,20 @@ int board_early_init_f(void) } #ifndef CONFIG_MX6_TEMPERATURE_HOT -static bool tx6_temp_check_enabled = true; +static bool tx6ul_temp_check_enabled = true; #else -#define tx6_temp_check_enabled 0 +#define tx6ul_temp_check_enabled 0 +#endif + +#ifndef CONFIG_SYS_NAND_BLOCKS +#define CONFIG_SYS_NAND_BLOCKS 0 #endif static inline u8 tx6ul_mem_suffix(void) { -#ifdef CONFIG_TX6_NAND - return '0'; -#else - return '1'; -#endif + return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 + + IS_ENABLED(CONFIG_TX6_EMMC) + + CONFIG_SYS_NAND_BLOCKS / 2048 * 4; } #ifdef CONFIG_RN5T567 @@ -414,43 +434,90 @@ static inline u8 tx6ul_mem_suffix(void) #define VDD_RTC_VAL rn5t_mV_to_regval_rtc(3000) #define VDD_CORE_VAL rn5t_mV_to_regval(1300) /* DCDC1 */ #define VDD_CORE_VAL_LP rn5t_mV_to_regval(900) -#define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 */ +#define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 SDRAM 1.35V */ #define VDD_DDR_VAL_LP rn5t_mV_to_regval(1350) -#define VDD_HIGH_VAL rn5t_mV_to_regval(3300) /* DCDC4 */ -#define VDD_HIGH_VAL_LP rn5t_mV_to_regval(3300) -#define VDD_CSI_VAL rn5t_mV_to_regval2(3300) /* LDO4 */ +#define VDD_IO_EXT_VAL rn5t_mV_to_regval(3300) /* DCDC4 eMMC/NAND,VDDIO_EXT 3.0V */ +#define VDD_IO_EXT_VAL_LP rn5t_mV_to_regval(3300) +#define VDD_IO_INT_VAL rn5t_mV_to_regval2(3300) /* LDO1 ENET,GPIO,LCD,SD1,UART,3.3V */ +#define VDD_IO_INT_VAL_LP rn5t_mV_to_regval2(3300) +#define VDD_ADC_VAL rn5t_mV_to_regval2(3300) /* LDO2 ADC */ +#define VDD_ADC_VAL_LP rn5t_mV_to_regval2(3300) +#define VDD_PMIC_VAL rn5t_mV_to_regval2(2500) /* LDO3 PMIC */ +#define VDD_PMIC_VAL_LP rn5t_mV_to_regval2(2500) +#define VDD_CSI_VAL rn5t_mV_to_regval2(3300) /* LDO4 CSI */ #define VDD_CSI_VAL_LP rn5t_mV_to_regval2(3300) +#define VDD_LDO5_VAL rn5t_mV_to_regval2(1200) /* LDO5 1.2V */ +#define LDOEN1_LDO1EN (1 << 0) +#define LDOEN1_LDO2EN (1 << 1) +#define LDOEN1_LDO3EN (1 << 2) +#define LDOEN1_LDO4EN (1 << 3) +#define LDOEN1_LDO5EN (1 << 4) +#define LDOEN1_VAL (LDOEN1_LDO1EN | LDOEN1_LDO2EN | LDOEN1_LDO3EN | LDOEN1_LDO4EN) +#define LDOEN1_MASK 0x1f +#define LDOEN2_LDORTC1EN (1 << 4) +#define LDOEN2_LDORTC2EN (1 << 5) +#define LDOEN2_VAL LDOEN2_LDORTC1EN +#define LDOEN2_MASK 0x30 static struct pmic_regs rn5t567_regs[] = { { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, }, - { RN5T567_DC2CTL, DC2_DC2DIS, }, + { RN5T567_SLPCNT, 0, }, + { RN5T567_REPCNT, (3 << 4) | (0 << 1), }, { RN5T567_DC1DAC, VDD_CORE_VAL, }, { RN5T567_DC3DAC, VDD_DDR_VAL, }, - { RN5T567_DC4DAC, VDD_HIGH_VAL, }, + { RN5T567_DC4DAC, VDD_IO_EXT_VAL, }, { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, }, { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, }, - { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, }, - { RN5T567_LDOEN1, 0x01f, ~0x1f, }, - { RN5T567_LDOEN2, 0x10, ~0x30, }, - { RN5T567_LDODIS, 0x00, }, - { RN5T567_LDO4DAC, VDD_CSI_VAL, }, + { RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, }, + { RN5T567_DC1CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), }, + { RN5T567_DC2CTL, DCnCTL_DIS, }, + { RN5T567_DC3CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), }, + { RN5T567_DC4CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), }, + { RN5T567_DC1CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, }, + { RN5T567_DC2CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, }, + { RN5T567_DC3CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, }, + { RN5T567_DC4CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, }, { RN5T567_LDORTC1DAC, VDD_RTC_VAL, }, { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, }, + { RN5T567_LDO1DAC, VDD_IO_INT_VAL, }, + { RN5T567_LDO2DAC, VDD_ADC_VAL, }, + { RN5T567_LDO3DAC, VDD_PMIC_VAL, }, + { RN5T567_LDO4DAC, VDD_CSI_VAL, }, + { RN5T567_LDO1DAC_SLP, VDD_IO_INT_VAL_LP, }, + { RN5T567_LDO2DAC_SLP, VDD_ADC_VAL_LP, }, + { RN5T567_LDO3DAC_SLP, VDD_PMIC_VAL_LP, }, + { RN5T567_LDO4DAC_SLP, VDD_CSI_VAL_LP, }, + { RN5T567_LDO5DAC, VDD_LDO5_VAL, }, + { RN5T567_LDO1DAC_SLP, VDD_IO_INT_VAL_LP, }, + { RN5T567_LDO2DAC_SLP, VDD_ADC_VAL_LP, }, + { RN5T567_LDO3DAC_SLP, VDD_PMIC_VAL_LP, }, + { RN5T567_LDO4DAC_SLP, VDD_CSI_VAL_LP, }, + { RN5T567_LDOEN1, LDOEN1_VAL, ~LDOEN1_MASK, }, + { RN5T567_LDOEN2, LDOEN2_VAL, ~LDOEN2_MASK, }, + { RN5T567_LDODIS, 0x1f, ~0x1f, }, + { RN5T567_INTPOL, 0, }, + { RN5T567_INTEN, 0x3, }, + { RN5T567_DCIREN, 0xf, }, + { RN5T567_EN_GPIR, 0, }, }; -static int pmic_addr __maybe_unused = 0x33; +static int pmic_addr = 0x33; #endif int board_init(void) { int ret; u32 cpurev = get_cpu_rev(); + char f = '?'; - debug("%s@%d: \n", __func__, __LINE__); + if (is_cpu_type(MXC_CPU_MX6UL)) + f = ((cpurev & 0xff) > 0x10) ? '5' : '0'; + else if (is_cpu_type(MXC_CPU_MX6ULL)) + f = '8'; + + debug("%s@%d: cpurev=%08x\n", __func__, __LINE__, cpurev); - printf("Board: Ka-Ro TXUL-%c01%c\n", - ((cpurev &0xff) > 0x10) ? '5' : '0', - tx6ul_mem_suffix()); + printf("Board: Ka-Ro TXUL-%c01%c\n", f, tx6ul_mem_suffix()); get_hab_status(); @@ -470,7 +537,7 @@ int board_init(void) else printf(" detected; safeboot enabled\n"); #ifndef CONFIG_MX6_TEMPERATURE_HOT - tx6_temp_check_enabled = false; + tx6ul_temp_check_enabled = false; #endif return 0; } @@ -489,7 +556,7 @@ int dram_init(void) /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS); + PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS); return 0; } @@ -499,16 +566,16 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); + PHYS_SDRAM_1_SIZE); #if CONFIG_NR_DRAM_BANKS > 1 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, - PHYS_SDRAM_2_SIZE); + PHYS_SDRAM_2_SIZE); #endif } #ifdef CONFIG_FSL_ESDHC -#define TX6UL_SD_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | \ +#define TX6UL_SD_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST) @@ -534,11 +601,11 @@ static const iomux_v3_cfg_t mmc1_pads[] = { MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL, /* eMMC RESET */ MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | - PAD_CTL_DSE_40ohm), + PAD_CTL_DSE_40ohm), }; #endif -static struct tx6_esdhc_cfg { +static struct tx6ul_esdhc_cfg { const iomux_v3_cfg_t *pads; int num_pads; enum mxc_clock clkid; @@ -569,22 +636,22 @@ static struct tx6_esdhc_cfg { }, }; -static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg) +static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg) { - return container_of(cfg, struct tx6_esdhc_cfg, cfg); + return container_of(cfg, struct tx6ul_esdhc_cfg, cfg); } int board_mmc_getcd(struct mmc *mmc) { - struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv); + struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv); if (cfg->cd_gpio < 0) return 1; debug("SD card %d is %spresent (GPIO %d)\n", - cfg - tx6ul_esdhc_cfg, - gpio_get_value(cfg->cd_gpio) ? "NOT " : "", - cfg->cd_gpio); + cfg - tx6ul_esdhc_cfg, + gpio_get_value(cfg->cd_gpio) ? "NOT " : "", + cfg->cd_gpio); return !gpio_get_value(cfg->cd_gpio); } @@ -602,7 +669,7 @@ int board_mmc_init(bd_t *bis) #endif for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) { struct mmc *mmc; - struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i]; + struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i]; int ret; cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid); @@ -610,10 +677,11 @@ int board_mmc_init(bd_t *bis) if (cfg->cd_gpio >= 0) { ret = gpio_request_one(cfg->cd_gpio, - GPIOFLAG_INPUT, "MMC CD"); + GPIOFLAG_INPUT, "MMC CD"); if (ret) { printf("Error %d requesting GPIO%d_%d\n", - ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32); + ret, cfg->cd_gpio / 32, + cfg->cd_gpio % 32); continue; } } @@ -640,7 +708,7 @@ enum { static inline int calc_blink_rate(void) { - if (!tx6_temp_check_enabled) + if (!tx6ul_temp_check_enabled) return CONFIG_SYS_HZ; return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 - @@ -726,6 +794,71 @@ static const struct gpio stk5_gpios[] = { { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", }, }; +static const iomux_v3_cfg_t tx_tester_pads[] = { + /* SW controlled LEDs on TX-TESTER-V5 baseboard */ + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04, /* red LED */ + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09, /* yellow LED */ + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08, /* green LED */ + + MX6_PAD_LCD_DATA04__GPIO3_IO09, /* IO_RESET */ + + /* I2C bus on DIMM pins 40/41 */ + MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL, + MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL, + + /* USBH1 */ + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */ + MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */ + + /* USBOTG */ + MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */ + MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */ + + MX6_PAD_LCD_DATA08__GPIO3_IO13 | TX6UL_GPIO_OUT_PAD_CTRL, + MX6_PAD_LCD_DATA09__GPIO3_IO14 | TX6UL_GPIO_OUT_PAD_CTRL, + MX6_PAD_LCD_DATA10__GPIO3_IO15 | TX6UL_GPIO_OUT_PAD_CTRL, + + /* USBH_VBUSEN */ + MX6_PAD_LCD_DATA11__GPIO3_IO16 | TX6UL_GPIO_OUT_PAD_CTRL, + + /* + * no drive capability for DUT_ETN_LINKLED, DUT_ETN_ACTLED + * to not interfere whith the DUT ETN PHY strap pins + */ + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02, MUX_PAD_CTRL(PAD_CTL_HYS | + PAD_CTL_DSE_DISABLE | + PAD_CTL_SPEED_LOW), + MX6_PAD_SNVS_TAMPER3__GPIO5_IO03, MUX_PAD_CTRL(PAD_CTL_HYS | + PAD_CTL_DSE_DISABLE | + PAD_CTL_SPEED_LOW), +}; + +static const struct gpio tx_tester_gpios[] = { + { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LEDGE#", }, + { IMX_GPIO_NR(5, 4), GPIOFLAG_OUTPUT_INIT_LOW, "LEDRT#", }, + { IMX_GPIO_NR(5, 8), GPIOFLAG_OUTPUT_INIT_LOW, "LEDGN#", }, + + { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_HIGH, "PMIC PWR_ON", }, + + { IMX_GPIO_NR(3, 5), GPIOFLAG_INPUT, "TSTART#", }, + { IMX_GPIO_NR(3, 6), GPIOFLAG_INPUT, "STARTED", }, + { IMX_GPIO_NR(3, 7), GPIOFLAG_INPUT, "TSTOP#", }, + { IMX_GPIO_NR(3, 8), GPIOFLAG_OUTPUT_INIT_LOW, "STOP#", }, + + { IMX_GPIO_NR(3, 10), GPIOFLAG_INPUT, "DUT_PGOOD", }, + + { IMX_GPIO_NR(3, 11), GPIOFLAG_OUTPUT_INIT_HIGH, "VBACKUP_OFF", }, + { IMX_GPIO_NR(3, 12), GPIOFLAG_OUTPUT_INIT_LOW, "VBACKUP_LOAD", }, + + { IMX_GPIO_NR(1, 10), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD1", }, + { IMX_GPIO_NR(3, 30), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD2", }, + { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD3", }, + + { IMX_GPIO_NR(3, 13), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD1", }, + { IMX_GPIO_NR(3, 14), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD2", }, + { IMX_GPIO_NR(3, 15), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD3", }, +}; + #ifdef CONFIG_LCD vidinfo_t panel_info = { /* set to max. size supported by SoC */ @@ -735,7 +868,7 @@ vidinfo_t panel_info = { .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ }; -static struct fb_videomode tx6_fb_modes[] = { +static struct fb_videomode tx6ul_fb_modes[] = { #ifndef CONFIG_SYS_LVDS_IF { /* Standard VGA timing */ @@ -976,7 +1109,7 @@ void lcd_enable(void) gpio_set_value(TX6UL_LCD_RST_GPIO, 1); udelay(300000); gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO, - lcd_backlight_polarity()); + lcd_backlight_polarity()); } } @@ -996,7 +1129,7 @@ void lcd_ctrl_init(void *lcdbase) const char *vm; unsigned long val; int refresh = 60; - struct fb_videomode *p = &tx6_fb_modes[0]; + struct fb_videomode *p = &tx6ul_fb_modes[0]; struct fb_videomode fb_mode; int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0; @@ -1026,8 +1159,8 @@ void lcd_ctrl_init(void *lcdbase) if (fb_mode.xres > panel_info.vl_col || fb_mode.yres > panel_info.vl_row) { printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n", - fb_mode.xres, fb_mode.yres, - panel_info.vl_col, panel_info.vl_row); + fb_mode.xres, fb_mode.yres, + panel_info.vl_col, panel_info.vl_row); lcd_enabled = 0; return; } @@ -1074,7 +1207,8 @@ void lcd_ctrl_init(void *lcdbase) default: printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n", - end - vm, vm, color_depth); + end - vm, vm, + color_depth); } bpp_set = 1; } else if (!refresh_set) { @@ -1108,7 +1242,7 @@ void lcd_ctrl_init(void *lcdbase) printf("Invalid video mode: %s\n", getenv("video_mode")); lcd_enabled = 0; printf("Supported video modes are:"); - for (p = &tx6_fb_modes[0]; p->name != NULL; p++) { + for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) { printf(" %s", p->name); } printf("\n"); @@ -1116,7 +1250,7 @@ void lcd_ctrl_init(void *lcdbase) } if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) { printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n", - p->xres, p->yres, panel_info.vl_col, panel_info.vl_row); + p->xres, p->yres, panel_info.vl_col, panel_info.vl_row); lcd_enabled = 0; return; } @@ -1134,40 +1268,43 @@ void lcd_ctrl_init(void *lcdbase) panel_info.vl_bpix = LCD_COLOR32; } - p->pixclock = KHZ2PICOS(refresh * - (p->xres + p->left_margin + p->right_margin + p->hsync_len) * - (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) / - 1000); + if (refresh_set || p->pixclock == 0) + p->pixclock = KHZ2PICOS(refresh * + (p->xres + p->left_margin + + p->right_margin + p->hsync_len) * + (p->yres + p->upper_margin + + p->lower_margin + p->vsync_len) / + 1000); debug("Pixel clock set to %lu.%03lu MHz\n", - PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000); + PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000); if (p != &fb_mode) { int ret; debug("Creating new display-timing node from '%s'\n", - video_mode); + video_mode); ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p); if (ret) printf("Failed to create new display-timing node from '%s': %d\n", - video_mode, ret); + video_mode, ret); } gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios)); imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads, - ARRAY_SIZE(stk5_lcd_pads)); + ARRAY_SIZE(stk5_lcd_pads)); debug("video format: %ux%u-%u@%u\n", p->xres, p->yres, - color_depth, refresh); + color_depth, refresh); if (karo_load_splashimage(0) == 0) { char vmode[128]; /* setup env variable for mxsfb display driver */ snprintf(vmode, sizeof(vmode), - "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d", - p->xres, p->yres, p->left_margin, p->right_margin, - p->upper_margin, p->lower_margin, p->hsync_len, - p->vsync_len, p->sync, p->pixclock, color_depth); + "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d", + p->xres, p->yres, p->left_margin, p->right_margin, + p->upper_margin, p->lower_margin, p->hsync_len, + p->vsync_len, p->sync, p->pixclock, color_depth); setenv("videomode", vmode); debug("Initializing LCD controller\n"); @@ -1183,7 +1320,7 @@ void lcd_ctrl_init(void *lcdbase) #endif /* CONFIG_LCD */ #ifndef CONFIG_ENV_IS_IN_MMC -static void tx6_mmc_init(void) +static void tx6ul_mmc_init(void) { puts("MMC: "); if (board_mmc_init(gd->bd) < 0) @@ -1191,7 +1328,7 @@ static void tx6_mmc_init(void) print_mmc_devices(','); } #else -static inline void tx6_mmc_init(void) +static inline void tx6ul_mmc_init(void) { } #endif @@ -1205,11 +1342,13 @@ static void stk5_board_init(void) printf("Failed to request stk5_gpios: %d\n", ret); return; } + imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads)); if (getenv_yesno("jtag_enable") != 0) { /* true if unset or set to one of: 'yYtT1' */ imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads)); } + debug("%s@%d: \n", __func__, __LINE__); } @@ -1218,7 +1357,7 @@ static void stk5v3_board_init(void) debug("%s@%d: \n", __func__, __LINE__); stk5_board_init(); debug("%s@%d: \n", __func__, __LINE__); - tx6_mmc_init(); + tx6ul_mmc_init(); } static void stk5v5_board_init(void) @@ -1226,17 +1365,46 @@ static void stk5v5_board_init(void) int ret; stk5_board_init(); - tx6_mmc_init(); + tx6ul_mmc_init(); ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH, - "Flexcan Transceiver"); + "Flexcan Transceiver"); if (ret) { printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret); return; } imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 | - TX6UL_GPIO_OUT_PAD_CTRL); + TX6UL_GPIO_OUT_PAD_CTRL); +} + +static void tx_tester_board_init(void) +{ + int ret; + + setenv("video_mode", NULL); + setenv("touchpanel", NULL); + if (getenv("eth1addr") && !getenv("ethprime")) + setenv("ethprime", "FEC1"); + + ret = gpio_request_array(tx_tester_gpios, ARRAY_SIZE(tx_tester_gpios)); + if (ret) { + printf("Failed to request TX-Tester GPIOs: %d\n", ret); + return; + } + imx_iomux_v3_setup_multiple_pads(tx_tester_pads, + ARRAY_SIZE(tx_tester_pads)); + + if (wrsr & WRSR_TOUT) + gpio_set_value(IMX_GPIO_NR(5, 4), 1); + + if (getenv_yesno("jtag_enable") != 0) { + /* true if unset or set to one of: 'yYtT1' */ + imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, + ARRAY_SIZE(stk5_jtag_pads)); + } + + gpio_set_value(IMX_GPIO_NR(3, 8), 1); } static void tx6ul_set_cpu_clock(void) @@ -1248,13 +1416,13 @@ static void tx6ul_set_cpu_clock(void) if (had_ctrlc() || (wrsr & WRSR_TOUT)) { printf("%s detected; skipping cpu clock change\n", - (wrsr & WRSR_TOUT) ? "WDOG RESET" : ""); + (wrsr & WRSR_TOUT) ? "WDOG RESET" : ""); return; } if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) { cpu_clk = mxc_get_clock(MXC_ARM_CLK); printf("CPU clock set to %lu.%03lu MHz\n", - cpu_clk / 1000000, cpu_clk / 1000 % 1000); + cpu_clk / 1000000, cpu_clk / 1000 % 1000); } else { printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk); } @@ -1268,7 +1436,7 @@ int board_late_init(void) env_cleanup(); - if (tx6_temp_check_enabled) + if (tx6ul_temp_check_enabled) check_cpu_temperature(1); tx6ul_set_cpu_clock(); @@ -1295,7 +1463,7 @@ int board_late_init(void) if (otg_mode && strcmp(otg_mode, "host") == 0) { printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n", - otg_mode, baseboard); + otg_mode, baseboard); setenv("otg_mode", "none"); } stk5v5_board_init(); @@ -1308,13 +1476,20 @@ int board_late_init(void) if (otg_mode && strcmp(otg_mode, "host") == 0) { printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n", - otg_mode, baseboard); + otg_mode, baseboard); setenv("otg_mode", "none"); } stk5_board_init(); + } else if (strncmp(baseboard, "tx-tester-", 10) == 0) { + const char *otg_mode = getenv("otg_mode"); + + if (!otg_mode || strcmp(otg_mode, "none") != 0) + setenv("otg_mode", "device"); + tx_tester_board_init(); } else { printf("WARNING: Unsupported baseboard: '%s'\n", baseboard); + printf("Reboot with pressed to fix this\n"); if (!had_ctrlc()) return -EINVAL; } @@ -1332,7 +1507,57 @@ exit: #define ETH_ALEN 6 #endif -static void tx6_init_mac(void) +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + unsigned int mac0, mac1, mac2; + unsigned int __maybe_unused fuse3_override, fuse4_override; + + memset(mac, 0, 6); + + switch (dev_id) { + case 0: + if (fuse_read(4, 2, &mac0)) { + printf("Failed to read MAC0 fuse\n"); + return; + } + if (fuse_read(4, 3, &mac1)) { + printf("Failed to read MAC1 fuse\n"); + return; + } + mac[0] = mac1 >> 8; + mac[1] = mac1; + mac[2] = mac0 >> 24; + mac[3] = mac0 >> 16; + mac[4] = mac0 >> 8; + mac[5] = mac0; + break; + + case 1: + if (fuse_read(4, 3, &mac1)) { + printf("Failed to read MAC1 fuse\n"); + return; + } + debug("read %08x from fuse 3\n", mac1); + if (fuse_read(4, 4, &mac2)) { + printf("Failed to read MAC2 fuse\n"); + return; + } + debug("read %08x from fuse 4\n", mac2); + mac[0] = mac2 >> 24; + mac[1] = mac2 >> 16; + mac[2] = mac2 >> 8; + mac[3] = mac2; + mac[4] = mac1 >> 24; + mac[5] = mac1 >> 16; + break; + + default: + return; + } + debug("%s@%d: Done %d %pM\n", __func__, __LINE__, dev_id, mac); +} + +static void tx6ul_init_mac(void) { u8 mac[ETH_ALEN]; const char *baseboard = getenv("baseboard"); @@ -1353,20 +1578,21 @@ static void tx6_init_mac(void) if (getenv("eth1addr")) return; imx_get_mac_from_fuse(1, mac); - eth_setenv_enetaddr("eth1addr", mac); + if (is_valid_ethaddr(mac)) + eth_setenv_enetaddr("eth1addr", mac); } int board_eth_init(bd_t *bis) { int ret; - tx6_init_mac(); + tx6ul_init_mac(); /* delay at least 21ms for the PHY internal POR signal to deassert */ udelay(22000); imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads, - ARRAY_SIZE(tx6ul_enet1_pads)); + ARRAY_SIZE(tx6ul_enet1_pads)); /* Deassert RESET to the external phys */ gpio_set_value(TX6UL_FEC_RST_GPIO, 1); @@ -1380,12 +1606,12 @@ int board_eth_init(bd_t *bis) } if (getenv("eth1addr")) { ret = gpio_request_array(tx6ul_fec2_gpios, - ARRAY_SIZE(tx6ul_fec2_gpios)); + ARRAY_SIZE(tx6ul_fec2_gpios)); if (ret < 0) { printf("Failed to request tx6ul_fec2_gpios: %d\n", ret); } imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads, - ARRAY_SIZE(tx6ul_enet2_pads)); + ARRAY_SIZE(tx6ul_enet2_pads)); writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */ @@ -1427,7 +1653,7 @@ static struct node_info nodes[] = { #define fdt_fixup_mtdparts(b,n,c) do { } while (0) #endif -static const char *tx6_touchpanels[] = { +static const char *tx6ul_touchpanels[] = { "ti,tsc2007", "edt,edt-ft5x06", "eeti,egalax_ts", @@ -1450,12 +1676,12 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); - karo_fdt_fixup_touchpanel(blob, tx6_touchpanels, - ARRAY_SIZE(tx6_touchpanels)); + karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels, + ARRAY_SIZE(tx6ul_touchpanels)); karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply"); karo_fdt_fixup_flexcan(blob, stk5_v5); - karo_fdt_update_fb_mode(blob, video_mode); + karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel"); return 0; }