X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=include%2Fddr_spd.h;h=15a3e8d35181ddf71a765d32391f55610e7958bd;hp=f5809e5e1bfcaa7e1d4526237f0c976e95f3d30d;hb=c34c0246a3600dc4712247b267f71576234e403b;hpb=93e1459641e758d2b096d3f1b39414a39bb314f8

diff --git a/include/ddr_spd.h b/include/ddr_spd.h
index f5809e5e1b..15a3e8d351 100644
--- a/include/ddr_spd.h
+++ b/include/ddr_spd.h
@@ -126,8 +126,8 @@ typedef struct ddr2_spd_eeprom_s {
 	unsigned char tdqsq;       /* 44 Max DQS to DQ skew (tDQSQ max) */
 	unsigned char tqhs;        /* 45 Max Read DataHold skew (tQHS) */
 	unsigned char pll_relock;  /* 46 PLL Relock time */
-	unsigned char Tcasemax;    /* 47 Tcasemax */
-	unsigned char psiTAdram;   /* 48 Thermal Resistance of DRAM Package from
+	unsigned char t_casemax;    /* 47 Tcasemax */
+	unsigned char psi_ta_dram;  /* 48 Thermal Resistance of DRAM Package from
 					 Top (Case) to Ambient (Psi T-A DRAM) */
 	unsigned char dt0_mode;    /* 49 DRAM Case Temperature Rise from Ambient
 					 due to Activate-Precharge/Mode Bits
@@ -153,9 +153,9 @@ typedef struct ddr2_spd_eeprom_s {
 	unsigned char dt7;         /* 57 DRAM Case Temperature Rise from Ambient
 					 due to Bank Interleave Reads with
 					 Auto-Precharge (DT7) */
-	unsigned char psiTApll;    /* 58 Thermal Resistance of PLL Package form
+	unsigned char psi_ta_pll;  /* 58 Thermal Resistance of PLL Package form
 					 Top (Case) to Ambient (Psi T-A PLL) */
-	unsigned char psiTAreg;    /* 59 Thermal Reisitance of Register Package
+	unsigned char psi_ta_reg;    /* 59 Thermal Reisitance of Register Package
 					 from Top (Case) to Ambient
 					 (Psi T-A Register) */
 	unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient
@@ -191,41 +191,41 @@ typedef struct ddr3_spd_eeprom_s {
 					     Dividend / Divisor */
 	unsigned char mtb_dividend;    /* 10 Medium Timebase (MTB) Dividend */
 	unsigned char mtb_divisor;     /* 11 Medium Timebase (MTB) Divisor */
-	unsigned char tCK_min;         /* 12 SDRAM Minimum Cycle Time */
+	unsigned char tck_min;         /* 12 SDRAM Minimum Cycle Time */
 	unsigned char res_13;          /* 13 Reserved */
 	unsigned char caslat_lsb;      /* 14 CAS Latencies Supported,
 					     Least Significant Byte */
 	unsigned char caslat_msb;      /* 15 CAS Latencies Supported,
 					     Most Significant Byte */
-	unsigned char tAA_min;         /* 16 Min CAS Latency Time */
-	unsigned char tWR_min;         /* 17 Min Write REcovery Time */
-	unsigned char tRCD_min;        /* 18 Min RAS# to CAS# Delay Time */
-	unsigned char tRRD_min;        /* 19 Min Row Active to
+	unsigned char taa_min;         /* 16 Min CAS Latency Time */
+	unsigned char twr_min;         /* 17 Min Write REcovery Time */
+	unsigned char trcd_min;        /* 18 Min RAS# to CAS# Delay Time */
+	unsigned char trrd_min;        /* 19 Min Row Active to
 					     Row Active Delay Time */
-	unsigned char tRP_min;         /* 20 Min Row Precharge Delay Time */
-	unsigned char tRAS_tRC_ext;    /* 21 Upper Nibbles for tRAS and tRC */
-	unsigned char tRAS_min_lsb;    /* 22 Min Active to Precharge
+	unsigned char trp_min;         /* 20 Min Row Precharge Delay Time */
+	unsigned char tras_trc_ext;    /* 21 Upper Nibbles for tRAS and tRC */
+	unsigned char tras_min_lsb;    /* 22 Min Active to Precharge
 					     Delay Time */
-	unsigned char tRC_min_lsb;     /* 23 Min Active to Active/Refresh
+	unsigned char trc_min_lsb;     /* 23 Min Active to Active/Refresh
 					     Delay Time, LSB */
-	unsigned char tRFC_min_lsb;    /* 24 Min Refresh Recovery Delay Time */
-	unsigned char tRFC_min_msb;    /* 25 Min Refresh Recovery Delay Time */
-	unsigned char tWTR_min;        /* 26 Min Internal Write to
+	unsigned char trfc_min_lsb;    /* 24 Min Refresh Recovery Delay Time */
+	unsigned char trfc_min_msb;    /* 25 Min Refresh Recovery Delay Time */
+	unsigned char twtr_min;        /* 26 Min Internal Write to
 					     Read Command Delay Time */
-	unsigned char tRTP_min;        /* 27 Min Internal Read to Precharge
+	unsigned char trtp_min;        /* 27 Min Internal Read to Precharge
 					     Command Delay Time */
-	unsigned char tFAW_msb;        /* 28 Upper Nibble for tFAW */
-	unsigned char tFAW_min;        /* 29 Min Four Activate Window
+	unsigned char tfaw_msb;        /* 28 Upper Nibble for tFAW */
+	unsigned char tfaw_min;        /* 29 Min Four Activate Window
 					     Delay Time*/
 	unsigned char opt_features;    /* 30 SDRAM Optional Features */
 	unsigned char therm_ref_opt;   /* 31 SDRAM Thermal and Refresh Opts */
 	unsigned char therm_sensor;    /* 32 Module Thermal Sensor */
 	unsigned char device_type;     /* 33 SDRAM device type */
-	int8_t fine_tCK_min;	       /* 34 Fine offset for tCKmin */
-	int8_t fine_tAA_min;	       /* 35 Fine offset for tAAmin */
-	int8_t fine_tRCD_min;	       /* 36 Fine offset for tRCDmin */
-	int8_t fine_tRP_min;	       /* 37 Fine offset for tRPmin */
-	int8_t fine_tRC_min;	       /* 38 Fine offset for tRCmin */
+	int8_t fine_tck_min;	       /* 34 Fine offset for tCKmin */
+	int8_t fine_taa_min;	       /* 35 Fine offset for tAAmin */
+	int8_t fine_trcd_min;	       /* 36 Fine offset for tRCDmin */
+	int8_t fine_trp_min;	       /* 37 Fine offset for tRPmin */
+	int8_t fine_trc_min;	       /* 38 Fine offset for tRCmin */
 	unsigned char res_39_59[21];   /* 39-59 Reserved, General Section */
 
 	/* Module-Specific Section: Bytes 60-116 */