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keystone2: ddr: add DDR3 PHY configs updated for PG 2.0
authorHao Zhang <hzhang@ti.com>
Wed, 9 Jul 2014 16:48:41 +0000 (19:48 +0300)
committerTom Rini <trini@ti.com>
Fri, 25 Jul 2014 20:26:09 +0000 (16:26 -0400)
commit101eec50f021a354487a511dc1f72691404b2b48
tree3ce38417d6fa5b3131307167e075c18b8f47aa41tree | snapshot
parent0b868589563ab96384b9a817bc5b82d93c573ea5commit | diff
keystone2: ddr: add DDR3 PHY configs updated for PG 2.0

Add DDR3 PHY configs updated for PG 2.0
Also add DDR3A PHY reset before init for PG2.0 SoCs.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
arch/arm/cpu/armv7/keystone/ddr3.c diff | blob | history
arch/arm/include/asm/arch-keystone/ddr3.h diff | blob | history
arch/arm/include/asm/arch-keystone/hardware.h diff | blob | history
board/ti/k2hk_evm/ddr3.c diff | blob | history
UBoot for KaRo TX COM modules