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(parent: 14ca3de) | patch
OMAP3: Add optimal SDRC autorefresh control values
authorTom Rini <trini@ti.com>
Fri, 18 Nov 2011 12:48:04 +0000 (12:48 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Tue, 6 Dec 2011 22:59:38 +0000 (23:59 +0100)
commit1be1433b834aaf7aef7c92275f92d4729f6bd62e
tree6f21533bfe62196777c60c117daf2dd4ed75f342tree | snapshot
parent14ca3dee80718b5f8fd06e39e78a4e7757826bbfcommit | diff
OMAP3: Add optimal SDRC autorefresh control values

This adds the optimal SDRC autorefresh control register values for
100Mhz, 133MHz, 165MHz and 200MHz clocks.  We switch to using this
to provide the default 165MHz value.

Signed-off-by: Tom Rini <trini@ti.com>
arch/arm/include/asm/arch-omap3/mem.h diff | blob | history
UBoot for KaRo TX COM modules