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ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock
authorAngela Stegmaier <angelabaker@ti.com>
Mon, 16 Feb 2015 04:45:55 +0000 (10:15 +0530)
committerLothar Waßmann <LW@KARO-electronics.de>
Tue, 1 Sep 2015 11:52:19 +0000 (13:52 +0200)
commit4c9631a34b0ccf48327935e177d3db760fd3a875
treef843f3b55e0b5cd2da33a948cef22f5a24fd7782tree | snapshot
parent7fbdfeffa826f94faeaca6acd25429f8e3700970commit | diff
ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock

DDR3 timing and latency paramenters were not configured
correctly for 666MHz. Fixing the timing and latency values
according to Data sheet.
This fixes the random crashes seen on DRA72-evm.

Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arch/arm/cpu/armv7/omap5/sdram.c diff | blob | history
UBoot for KaRo TX COM modules