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(parent: 4a5d889) | patch
MIPS: refactor L1 cache config reads to a macro
authorPaul Burton <paul.burton@imgtec.com>
Thu, 29 Jan 2015 01:27:59 +0000 (01:27 +0000)
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Thu, 29 Jan 2015 11:55:01 +0000 (12:55 +0100)
commit536cb7ce1aca10c326ac864b3e1d05ab57b3ec7e
treeb0550850214891149050109b60ff9b0ed1839353tree | snapshot
parent4a5d8898bca3e442b61e34b811aec8332752efd3commit | diff
MIPS: refactor L1 cache config reads to a macro

Reduce duplication between reading the configuration of the L1 dcache &
icache by performing both using a macro which calculates the appropriate
line & cache sizes from the coprocessor 0 Config1 register.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
arch/mips/lib/cache_init.S diff | blob | history
UBoot for KaRo TX COM modules