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(parent: 99dbd4e) | patch
PPC4xx: Denali core: Fix incorrect DDR row bits
authorMike Nuss <mike@terascala.com>
Mon, 5 Oct 2009 16:33:28 +0000 (12:33 -0400)
committerStefan Roese <sr@denx.de>
Wed, 7 Oct 2009 07:10:11 +0000 (09:10 +0200)
commit54f5f056aa1daa3e39bad1c5c3fb43a72cdb9e84
tree049354d5e1f2fac5642865ee2078e6b8d29b4449tree | snapshot
parent99dbd4efd6d5ecc37d7e8f28b20d9be8c83055c7commit | diff
PPC4xx: Denali core: Fix incorrect DDR row bits

The SPD detection code for the Denali memory controller used on some
ppc4xx
processors incorrectly encodes DDR0_42. With certain memory
configurations,
this can cause the bootwrapper to incorrectly calculate the installed
memory
size, because the number of row bits is wrong. This patch fixes that
encoding.

Signed-off-by: Mike Nuss <mike@terascala.com>
Signed-off-by: Stefan Roese <sr@denx.de>
cpu/ppc4xx/denali_spd_ddr2.c diff | blob | history
UBoot for KaRo TX COM modules