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(parent: 92d119d) | patch
ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE
authorAlexander Stein <alexanders83@web.de>
Fri, 24 Jul 2015 07:22:11 +0000 (09:22 +0200)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 06:25:46 +0000 (08:25 +0200)
commit5a3fd5ffa4ed5f3851e824a6d276cfaf1b5458ba
treee5085ffa3562b42b74216b5463c4a8ff788f6d8dtree | snapshot
parent92d119d341e8782d28704acb85800494d440353fcommit | diff
ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE

The cacheline is always 32 bytes for arm1176 CPUs, so define it at board
config level for cache handling code.
The ARM Cortex-A7 has a dcache line size of 64 bytes.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
include/configs/rpi.h diff | blob | history
include/configs/rpi_2.h diff | blob | history
UBoot for KaRo TX COM modules