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ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1
authorMarek Vasut <marex@denx.de>
Tue, 21 Jul 2015 03:00:42 +0000 (05:00 +0200)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 06:17:33 +0000 (08:17 +0200)
commit6c546599f0c216d613e7fb090d5a454d8db7217d
treeb32cdd8ea87e7dfbce6a3f9ab48c137d1009cc91tree | snapshot
parent28dfaea5b680166f5b87fc5d9ebe02bd1da0d71acommit | diff
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1

Fix data types and constify where applicable, fix broken multiline
debug strings and fix comments. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
drivers/ddr/altera/sequencer.c diff | blob | history
UBoot for KaRo TX COM modules