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MIPS: mips32/cache.S: remove superfluous register assignment
authorGabor Juhos <juhosg@openwrt.org>
Wed, 12 Jun 2013 16:02:46 +0000 (18:02 +0200)
committerTom Rini <trini@ti.com>
Wed, 24 Jul 2013 13:51:05 +0000 (09:51 -0400)
commitda84f33b046fe99c5fbb6f7d8f8b03c7333b260d
treecae25d170f59261651ca5ff9f2b6aeb2501f94d2tree | snapshot
parentb1a14c471cb4ea633746e7249e468a86a69f2495commit | diff
MIPS: mips32/cache.S: remove superfluous register assignment

The t4 register already holds the cache
line size, and the value of the register
is not changed in mips_init_icache.

Get the cache line size value from t4 for
mips_init_dcache as well and remove the
superfluous assignment of t5 register.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
arch/mips/cpu/mips32/cache.S diff | blob | history
UBoot for KaRo TX COM modules