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(parent: 8c36c16) | patch
armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085A
authorNikhil Badola <nikhil.badola@freescale.com>
Fri, 26 Jun 2015 11:29:21 +0000 (16:59 +0530)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 06:00:48 +0000 (08:00 +0200)
commite8c986c025faa89b6876411b88c80d94f2643be7
tree9167b6d29e22d071fae76da1066fd2d687828101tree | snapshot
parent8c36c1678ae82ef469b26153c3c32efbfed0273acommit | diff
armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085A

Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by
USB XHCI stack for alignment

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
arch/arm/include/asm/arch-fsl-lsch3/config.h diff | blob | history
UBoot for KaRo TX COM modules