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fpga: zynqpl: Add dcache flush support
authorJagannadha Sutradharudu Teki <jagannadha.sutradharudu-teki@xilinx.com>
Fri, 20 Sep 2013 13:09:47 +0000 (18:39 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Wed, 6 Nov 2013 08:15:12 +0000 (09:15 +0100)
commitec4b73f09c384007b274b38052149025e080b138
tree873b53a50014c59368f2c438917bec1a317212c4tree | snapshot
parente5a9a4076f1fb9fb9ce53c2aec32422073bbc66acommit | diff
fpga: zynqpl: Add dcache flush support

Buffers must be cache and dma aligned.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/fpga/zynqpl.c diff | blob | history
UBoot for KaRo TX COM modules