karo: tx53: configure SDRAM size via boards.cfg

diff --git a/board/karo/tx53/lowlevel_init.S b/board/karo/tx53/lowlevel_init.S
index b530fdb91d50c80952c69d837d79fd5a46cd5483..15f2245c41b77ea65e894e08f1829a4932fcae91 100644 (file)
--- a/board/karo/tx53/lowlevel_init.S
+++ b/board/karo/tx53/lowlevel_init.S
@@ -8,13 +8,7 @@
 #define LED_MUX_MODE           0x11
 
 #define SDRAM_CLK              CONFIG_SYS_SDRAM_CLK
 #define LED_MUX_MODE           0x11
 
 #define SDRAM_CLK              CONFIG_SYS_SDRAM_CLK

-
-#ifdef PHYS_SDRAM_2_SIZE
-#define SDRAM_SIZE             (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
-#else
-#define SDRAM_SIZE             PHYS_SDRAM_1_SIZE
-#endif
-
+#define SDRAM_SIZE             (CONFIG_SYS_SDRAM_SIZE / SZ_1M)

 
 #define REG_CCGR0              0x68
 #define REG_CCGR1              0x6c
 
 #define REG_CCGR0              0x68
 #define REG_CCGR1              0x6c


@@ -150,11 +144,7 @@ dcd_end:
 #define ESDOR_CLK_PERIOD_ns            (1000000000 / CKIL_FREQ_Hz / 2) /* base clock for ESDOR values */
 
 /* DDR3 SDRAM */
 #define ESDOR_CLK_PERIOD_ns            (1000000000 / CKIL_FREQ_Hz / 2) /* base clock for ESDOR values */
 
 /* DDR3 SDRAM */

-#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
-#define BANK_ADDR_BITS                 2
-#else
-#define BANK_ADDR_BITS                 1
-#endif
+#define BANK_ADDR_BITS                 CONFIG_NR_DRAM_BANKS

 #define SDRAM_BURST_LENGTH             8
 #define RALAT                          5
 #define WALAT                          0
 #define SDRAM_BURST_LENGTH             8
 #define RALAT                          5
 #define WALAT                          0

diff --git a/board/karo/tx53/tx53.c b/board/karo/tx53/tx53.c
index f67f770ae9b6d8f006409ab5cabf9683dcf7d199..50314f6fecd38205c677ba03913c549797c52c20 100644 (file)
--- a/board/karo/tx53/tx53.c
+++ b/board/karo/tx53/tx53.c
@@ -502,9 +502,13 @@ int dram_init(void)
 {
        int ret;
 
 {
        int ret;
 

-       /* dram_init must store complete ramsize in gd->ram_size */
-       gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-                               PHYS_SDRAM_1_SIZE);
+       /*
+        * U-Boot doesn't support RAM banks with intervening holes,
+        * so let U-Boot only know about the first bank for its
+        * internal data structures. The size reported to Linux is
+        * determined from the individual bank sizes.
+        */
+       gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, SZ_1G);

 
        ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
                CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 
        ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
                CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);


@@ -521,14 +525,24 @@ int dram_init(void)
 
 void dram_init_banksize(void)
 {
 
 void dram_init_banksize(void)
 {

+       long total_size = gd->ram_size;
+

        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;

-       gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
-                       PHYS_SDRAM_1_SIZE);
+       gd->bd->bi_dram[0].size = gd->ram_size;
+

 #if CONFIG_NR_DRAM_BANKS > 1
 #if CONFIG_NR_DRAM_BANKS > 1

-       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-       gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
-                       PHYS_SDRAM_2_SIZE);
+       gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, SZ_1G);
+
+       if (gd->bd->bi_dram[1].size) {
+               debug("Found %luMiB SDRAM in bank 2\n",
+                       gd->bd->bi_dram[1].size / SZ_1M);
+               gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+               total_size += gd->bd->bi_dram[1].size;
+       }

 #endif
 #endif

+       if (total_size != CONFIG_SYS_SDRAM_SIZE)
+               printf("WARNING: SDRAM size mismatch: %uMiB configured; %luMiB detected\n",
+                       CONFIG_SYS_SDRAM_SIZE / SZ_1M, total_size / SZ_1M);

 }
 
 #ifdef CONFIG_CMD_MMC
 }
 
 #ifdef CONFIG_CMD_MMC


@@ -1352,10 +1366,12 @@ exit:
 int checkboard(void)
 {
        tx53_print_cpuinfo();
 int checkboard(void)
 {
        tx53_print_cpuinfo();

-
-       printf("Board: Ka-Ro TX53-x%d3%s\n",
-               is_lvds(), TX53_MOD_SUFFIX);
-
+#if CONFIG_SYS_SDRAM_SIZE < SZ_1G
+       printf("Board: Ka-Ro TX53-8%d3%c\n",
+               is_lvds(), '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
+#else
+       printf("Board: Ka-Ro TX53-1%d31\n", is_lvds() + 2);
+#endif

        return 0;
 }
 
        return 0;
 }
 

diff --git a/include/configs/tx53.h b/include/configs/tx53.h
index 2588e8d63d40fc4aa87f6f5ca718fc3e54bb0d06..098b46d29f6469bb57b7f9246b2460c02a57ef2d 100644 (file)
--- a/include/configs/tx53.h
+++ b/include/configs/tx53.h
@@ -43,14 +43,15 @@
 /*
  * Memory configuration options
  */
 /*
  * Memory configuration options
  */

+#ifndef CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_SDRAM_SIZE          (SZ_512M * CONFIG_NR_DRAM_BANKS)
+#endif
+

 #define PHYS_SDRAM_1                   0x70000000      /* Base address of bank 1 */
 #define PHYS_SDRAM_1                   0x70000000      /* Base address of bank 1 */

-#define PHYS_SDRAM_1_SIZE              SZ_512M
+#define PHYS_SDRAM_1_SIZE              (CONFIG_SYS_SDRAM_SIZE / CONFIG_NR_DRAM_BANKS)

 #if CONFIG_NR_DRAM_BANKS > 1
 #define PHYS_SDRAM_2                   0xb0000000      /* Base address of bank 2 */
 #if CONFIG_NR_DRAM_BANKS > 1
 #define PHYS_SDRAM_2                   0xb0000000      /* Base address of bank 2 */

-#define PHYS_SDRAM_2_SIZE              SZ_512M
-#define TX53_MOD_SUFFIX                        "1"
-#else
-#define TX53_MOD_SUFFIX                        "0"
+#define PHYS_SDRAM_2_SIZE              PHYS_SDRAM_1_SIZE

 #endif
 #define CONFIG_STACKSIZE               SZ_128K
 #define CONFIG_SYS_MALLOC_LEN          SZ_8M
 #endif
 #define CONFIG_STACKSIZE               SZ_128K
 #define CONFIG_SYS_MALLOC_LEN          SZ_8M