# quilt's files
patches
series
+.pc
# gdb files
.gdb_history
else
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL)$(EXTRAVERSION)
endif
-TIMESTAMP_FILE = $(obj)include/generated/timestamp_autogenerated.h
-VERSION_FILE = $(obj)include/generated/version_autogenerated.h
HOSTARCH := $(shell uname -m | \
sed -e s/i.86/x86/ \
ifneq ($(BUILD_DIR),)
saved-output := $(BUILD_DIR)
-# Attempt to create a output directory.
+# Attempt to create an output directory.
$(shell [ -d ${BUILD_DIR} ] || mkdir -p ${BUILD_DIR})
# Verify if it was successful.
endif
export obj src
+TIMESTAMP_FILE = $(obj)include/generated/timestamp_autogenerated.h
+VERSION_FILE = $(obj)include/generated/version_autogenerated.h
+
# Make sure CDPATH settings don't interfere
unexport CDPATH
# Specify the target for use in elftosb call
ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
-$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
- elftosb -zf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
+$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin elftosb
+ cd $(OBJTREE); \
+ $(TOPDIR)/$(SUBDIR_TOOLS)/elftosb/bld/linux/elftosb -zdf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
-o $(obj)u-boot.sb
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
updater:
$(MAKE) -C tools/updater all
+elftosb:
+ $(MAKE) -C $(SUBDIR_TOOLS)/elftosb all
# Explicitly make _depend in subdirs containing multiple targets to prevent
# parallel sub-makes creating .depend files simultaneously.
ALL-$(CONFIG_SYS_THUMB_BUILD) += checkthumb
endif
-# Try if EABI is supported, else fall back to old API,
+# Try if EABI is supported, else fall back to old ABI,
# i. e. for example:
# - with ELDK 4.2 (EABI supported), use:
# -mabi=aapcs-linux
#include <common.h>
#include <command.h>
+#include <lcd.h>
#include <asm/system.h>
static void cache_flush(void);
disable_interrupts ();
+#ifdef CONFIG_LCD
+ {
+ /* switch off LCD panel */
+ lcd_panel_disable();
+ /* disable LCD controller */
+ lcd_disable();
+ }
+#endif
/* turn off I/D-cache */
icache_disable();
#endif
}
+#define MX28_HW_DIGCTL_MICROSECONDS (void *)0x8001c0c0
+
int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
int timeout)
{
- while (--timeout) {
- if ((readl(®->reg) & mask) == mask)
- break;
+ uint32_t start = readl(MX28_HW_DIGCTL_MICROSECONDS);
+
+ /* Wait for at least one microsecond for the bit mask to be set */
+ while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= 1 || --timeout) {
+ if ((readl(®->reg) & mask) == mask) {
+ while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= 1)
+ ;
+ return 0;
+ }
udelay(1);
}
int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
int timeout)
{
- while (--timeout) {
- if ((readl(®->reg) & mask) == 0)
- break;
+ uint32_t start = readl(MX28_HW_DIGCTL_MICROSECONDS);
+
+ /* Wait for at least one microsecond for the bit mask to be cleared */
+ while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= 1 || --timeout) {
+ if ((readl(®->reg) & mask) == 0) {
+ while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= 1)
+ ;
+ return 0;
+ }
udelay(1);
}
/* Clear SFTRST */
writel(MXS_BLOCK_SFTRST, ®->reg_clr);
- if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) {
+ printf("TIMEOUT waiting for SFTRST[%p] to clear: %08x\n",
+ reg, readl(®->reg));
return 1;
+ }
/* Clear CLKGATE */
writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
writel(MXS_BLOCK_SFTRST, ®->reg_set);
/* Wait for CLKGATE being set */
- if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+ if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) {
+ printf("TIMEOUT waiting for CLKGATE[%p] to set: %08x\n",
+ reg, readl(®->reg));
return 1;
+ }
/* Clear SFTRST */
writel(MXS_BLOCK_SFTRST, ®->reg_clr);
- if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) {
+ printf("TIMEOUT waiting for SFTRST[%p] to clear: %08x\n",
+ reg, readl(®->reg));
return 1;
+ }
/* Clear CLKGATE */
writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
- if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) {
+ printf("TIMEOUT waiting for CLKGATE[%p] to clear: %08x\n",
+ reg, readl(®->reg));
return 1;
+ }
return 0;
}
}
#endif
+#ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
return 0;
}
+#endif
#if defined(CONFIG_DISPLAY_CPUINFO)
static const char *get_cpu_type(void)
udelay(10);
+ /*
+ * Enable pad output; must be done BEFORE enabling PLL
+ * according to i.MX28 Ref. Manual Rev. 1, 2010 p. 883
+ */
+ setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
+
/* Gate on ENET PLL */
writel(CLKCTRL_PLL2CTRL0_CLKGATE,
&clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
- /* Enable pad output */
- setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
-
return 0;
}
#endif
* takes a few seconds to roll. The boot doesn't take that long, so to keep the
* code simple, it doesn't take rolling into consideration.
*/
+/*
+ * There's nothing to be taken into consideration for the rollover.
+ * Two's complement arithmetic used correctly does all the magic automagically.
+ */
void early_delay(int delay)
{
struct mxs_digctl_regs *digctl_regs =
(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
+ u32 start = readl(&digctl_regs->hw_digctl_microseconds);
- uint32_t st = readl(&digctl_regs->hw_digctl_microseconds);
- st += delay;
- while (st > readl(&digctl_regs->hw_digctl_microseconds))
- ;
+ while (readl(&digctl_regs->hw_digctl_microseconds) - start < delay);
}
#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
mxs_power_wait_pswitch();
}
-/* Support aparatus */
+/* Support apparatus */
inline void board_init_f(unsigned long bootflag)
{
for (;;)
;
}
+#ifndef CONFIG_SPL_SERIAL_SUPPORT
+void serial_putc(const char c) {}
+void serial_puts(const char *s) {}
+#endif
void hang(void) __attribute__ ((noreturn));
void hang(void)
{
+ serial_puts("ERROR: please reset the target\n");
for (;;)
;
}
writeb(CLKCTRL_FRAC_CLKGATE,
&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]);
- early_delay(11000);
/* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */
writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
(1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
&clkctrl_regs->hw_clkctrl_emi);
+ while (readl(&clkctrl_regs->hw_clkctrl_emi) & CLKCTRL_EMI_BUSY_REF_EMI)
+ ;
/* Unbypass EMI */
writel(CLKCTRL_CLKSEQ_BYPASS_EMI,
&clkctrl_regs->hw_clkctrl_clkseq_clr);
-
- early_delay(10000);
}
static void mxs_mem_setup_cpu_and_hbus(void)
&clkctrl_regs->hw_clkctrl_clkseq_set);
/* HBUS = 151MHz */
- writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
- writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
- &clkctrl_regs->hw_clkctrl_hbus_clr);
-
- early_delay(10000);
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_hbus,
+ CLKCTRL_HBUS_DIV_MASK,
+ 3 << CLKCTRL_HBUS_DIV_OFFSET);
+ while (readl(&clkctrl_regs->hw_clkctrl_hbus) & CLKCTRL_HBUS_ASM_BUSY)
+ ;
/* CPU clock divider = 1 */
clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu,
- CLKCTRL_CPU_DIV_CPU_MASK, 1);
+ CLKCTRL_CPU_DIV_CPU_MASK,
+ 1 << CLKCTRL_CPU_DIV_CPU_OFFSET);
+ while (readl(&clkctrl_regs->hw_clkctrl_cpu) & CLKCTRL_CPU_BUSY_REF_CPU)
+ ;
/* Disable CPU bypass */
writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
&clkctrl_regs->hw_clkctrl_clkseq_clr);
-
- early_delay(15000);
}
-static void mxs_mem_setup_vdda(void)
+static void __attribute__((naked)) data_abort_memdetect_handler(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
- writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
- (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
- POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
- &power_regs->hw_power_vddactrl);
+ asm volatile("subs pc, r14, #4");
}
uint32_t mxs_mem_get_size(void)
{
uint32_t sz, da;
uint32_t *vt = (uint32_t *)0x20;
- /* The following is "subs pc, r14, #4", used as return from DABT. */
- const uint32_t data_abort_memdetect_handler = 0xe25ef004;
/* Replace the DABT handler. */
da = vt[4];
- vt[4] = data_abort_memdetect_handler;
+ vt[4] = (uint32_t)data_abort_memdetect_handler;
sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
writel(CLKCTRL_PLL0CTRL0_POWER,
&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
- early_delay(11000);
+ /* enabling the PLL requires a 10µs delay before use as clk source */
+ early_delay(11);
mxs_mem_init_clock();
- mxs_mem_setup_vdda();
-
/*
* Configure the DRAM registers
*/
while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
;
- early_delay(10000);
-
mxs_mem_setup_cpu_and_hbus();
}
#include "mxs_init.h"
+#ifdef CONFIG_SYS_SPL_VDDD_VAL
+#define VDDD_VAL CONFIG_SYS_SPL_VDDD_VAL
+#else
+#define VDDD_VAL 1350
+#endif
+#ifdef CONFIG_SYS_SPL_VDDIO_VAL
+#define VDDIO_VAL CONFIG_SYS_SPL_VDDIO_VAL
+#else
+#define VDDIO_VAL 3300
+#endif
+#ifdef CONFIG_SYS_SPL_VDDA_VAL
+#define VDDA_VAL CONFIG_SYS_SPL_VDDA_VAL
+#else
+#define VDDA_VAL 1800
+#endif
+#ifdef CONFIG_SYS_SPL_VDDMEM_VAL
+#define VDDMEM_VAL CONFIG_SYS_SPL_VDDMEM_VAL
+#else
+#define VDDMEM_VAL 1500
+#endif
+
+#ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
+#define VDDD_BO_VAL CONFIG_SYS_SPL_VDDD_BO_VAL
+#else
+#define VDDD_BO_VAL 150
+#endif
+#ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
+#define VDDIO_BO_VAL CONFIG_SYS_SPL_VDDIO_BO_VAL
+#else
+#define VDDIO_BO_VAL 150
+#endif
+#ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
+#define VDDA_BO_VAL CONFIG_SYS_SPL_VDDA_BO_VAL
+#else
+#define VDDA_BO_VAL 175
+#endif
+#ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
+#define VDDMEM_BO_VAL CONFIG_SYS_SPL_VDDMEM_BO_VAL
+#else
+#define VDDMEM_BO_VAL 25
+#endif
+
+#ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
+#if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
+#error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
+#endif
+#define BATT_BO_VAL (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
+#else
+/* Brownout default at 3V */
+#define BATT_BO_VAL ((3000 - 2400) / 40)
+#endif
+
+#ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
+static const int fixed_batt_supply = 1;
+#else
+static const int fixed_batt_supply;
+#endif
+
+static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
+
static void mxs_power_clock2xtal(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
static void mxs_power_set_linreg(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/* Set linear regulator 25mV below switching converter */
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
static int mxs_get_batt_volt(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t volt = readl(&power_regs->hw_power_battmonitor);
+
volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
volt *= 8;
static int mxs_is_batt_good(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t volt = mxs_get_batt_volt();
if ((volt >= 2400) && (volt <= 4300))
static void mxs_power_setup_5v_detect(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/* Start 5V detection */
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_VBUSVALID_TRSH_MASK,
static void mxs_src_power_init(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/* Improve efficieny and reduce transient ripple */
writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
- setbits_le32(&power_regs->hw_power_battmonitor,
+ if (!fixed_batt_supply) {
+ /* FIXME: This requires the LRADC to be set up! */
+ setbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_EN_BATADJ);
+ } else {
+ clrbits_le32(&power_regs->hw_power_battmonitor,
+ POWER_BATTMONITOR_EN_BATADJ);
+ }
/* Increase the RCSCALE level for quick DCDC response to dynamic load */
clrsetbits_le32(&power_regs->hw_power_loopctrl,
clrsetbits_le32(&power_regs->hw_power_minpwr,
POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
- /* 5V to battery handoff ... FIXME */
- setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
- early_delay(30);
- clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+ if (!fixed_batt_supply) {
+ /* 5V to battery handoff ... FIXME */
+ setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+ early_delay(30);
+ clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+ }
}
static void mxs_power_init_4p2_params(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/* Setup 4P2 parameters */
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
static void mxs_enable_4p2_dcdc_input(int xfer)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
uint32_t prev_5v_brnout, prev_5v_droop;
static void mxs_power_init_4p2_regulator(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, tmp2;
setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
static void mxs_power_init_dcdc_4p2_source(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
if (!(readl(&power_regs->hw_power_dcdc4p2) &
POWER_DCDC4P2_ENABLE_DCDC)) {
hang();
static void mxs_power_enable_4p2(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t vdddctrl, vddactrl, vddioctrl;
uint32_t tmp;
static void mxs_boot_valid_5v(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/*
* Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
* disconnect event. FIXME
static void mxs_powerdown(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
&power_regs->hw_power_reset);
static void mxs_batt_boot(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
static void mxs_handle_5v_conflict(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
setbits_le32(&power_regs->hw_power_vddioctrl,
static void mxs_5v_boot(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/*
* NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
* but their implementation always returns 1 so we omit it here.
mxs_handle_5v_conflict();
}
-static void mxs_init_batt_bo(void)
+static void mxs_fixed_batt_boot(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
+ writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
+
+ setbits_le32(&power_regs->hw_power_5vctrl,
+ POWER_5VCTRL_PWDN_5VBRNOUT |
+ POWER_5VCTRL_ENABLE_DCDC |
+ POWER_5VCTRL_ILIMIT_EQ_ZERO |
+ POWER_5VCTRL_PWDN_5VBRNOUT |
+ POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
+
+ writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
+
+ clrbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_DISABLE_FET |
+ POWER_VDDDCTRL_ENABLE_LINREG |
+ POWER_VDDDCTRL_DISABLE_STEPPING);
+
+ clrbits_le32(&power_regs->hw_power_vddactrl,
+ POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
+ POWER_VDDACTRL_DISABLE_STEPPING);
+
+ clrbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_DISABLE_FET |
+ POWER_VDDIOCTRL_DISABLE_STEPPING);
- /* Brownout at 3V */
+ /* Stop 5V detection */
+ writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
+ &power_regs->hw_power_5vctrl_clr);
+}
+
+static void mxs_init_batt_bo(void)
+{
clrsetbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
- 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
+ BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
static void mxs_switch_vddd_to_dcdc_source(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
static void mxs_power_configure_power_source(void)
{
- int batt_ready, batt_good;
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
struct mxs_lradc_regs *lradc_regs =
(struct mxs_lradc_regs *)MXS_LRADC_BASE;
mxs_src_power_init();
- if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
- batt_ready = mxs_is_batt_ready();
- if (batt_ready) {
- /* 5V source detected, good battery detected. */
- mxs_batt_boot();
- } else {
- batt_good = mxs_is_batt_good();
- if (!batt_good) {
- /* 5V source detected, bad battery detected. */
- writel(LRADC_CONVERSION_AUTOMATIC,
- &lradc_regs->hw_lradc_conversion_clr);
- clrbits_le32(&power_regs->hw_power_battmonitor,
- POWER_BATTMONITOR_BATT_VAL_MASK);
+ if (!fixed_batt_supply) {
+ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ if (mxs_is_batt_ready()) {
+ /* 5V source detected, good battery detected. */
+ mxs_batt_boot();
+ } else {
+ if (!mxs_is_batt_good()) {
+ /* 5V source detected, bad battery detected. */
+ writel(LRADC_CONVERSION_AUTOMATIC,
+ &lradc_regs->hw_lradc_conversion_clr);
+ clrbits_le32(&power_regs->hw_power_battmonitor,
+ POWER_BATTMONITOR_BATT_VAL_MASK);
+ }
+ mxs_5v_boot();
}
- mxs_5v_boot();
+ } else {
+ /* 5V not detected, booting from battery. */
+ mxs_batt_boot();
}
} else {
- /* 5V not detected, booting from battery. */
- mxs_batt_boot();
+ mxs_fixed_batt_boot();
}
mxs_power_clock2pll();
static void mxs_enable_output_rail_protection(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
static int mxs_get_vddio_power_source_off(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
- if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
+ !(readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
+
tmp = readl(&power_regs->hw_power_vddioctrl);
if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
}
return 0;
-
}
static int mxs_get_vddd_power_source_off(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
tmp = readl(&power_regs->hw_power_vdddctrl);
return 0;
}
+static int mxs_get_vdda_power_source_off(void)
+{
+ uint32_t tmp;
+
+ tmp = readl(&power_regs->hw_power_vddactrl);
+ if (tmp & POWER_VDDACTRL_DISABLE_FET) {
+ if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
+ POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
+ return 1;
+ }
+ }
+
+ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ if (!(readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_ENABLE_DCDC)) {
+ return 1;
+ }
+ }
+
+ if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
+ if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
+ POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
struct mxs_vddx_cfg {
uint32_t *reg;
uint8_t step_mV;
uint16_t lowest_mV;
+ uint16_t highest_mV;
int (*powered_by_linreg)(void);
uint32_t trg_mask;
uint32_t bo_irq;
hw_power_vddioctrl),
.step_mV = 50,
.lowest_mV = 2800,
+ .highest_mV = 3600,
.powered_by_linreg = mxs_get_vddio_power_source_off,
.trg_mask = POWER_VDDIOCTRL_TRG_MASK,
.bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
hw_power_vdddctrl),
.step_mV = 25,
.lowest_mV = 800,
+ .highest_mV = 1575,
.powered_by_linreg = mxs_get_vddd_power_source_off,
.trg_mask = POWER_VDDDCTRL_TRG_MASK,
.bo_irq = POWER_CTRL_VDDD_BO_IRQ,
.bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
};
+static const struct mxs_vddx_cfg mxs_vdda_cfg = {
+ .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
+ hw_power_vddactrl),
+ .step_mV = 50,
+ .lowest_mV = 2800,
+ .highest_mV = 3600,
+ .powered_by_linreg = mxs_get_vdda_power_source_off,
+ .trg_mask = POWER_VDDACTRL_TRG_MASK,
+ .bo_irq = POWER_CTRL_VDDA_BO_IRQ,
+ .bo_enirq = POWER_CTRL_ENIRQ_VDDA_BO,
+ .bo_offset_mask = POWER_VDDACTRL_BO_OFFSET_MASK,
+ .bo_offset_offset = POWER_VDDACTRL_BO_OFFSET_OFFSET,
+};
+
+static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
+ .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
+ hw_power_vddmemctrl),
+ .step_mV = 25,
+ .lowest_mV = 1100,
+ .highest_mV = 1750,
+ .bo_offset_mask = POWER_VDDMEMCTRL_BO_OFFSET_MASK,
+ .bo_offset_offset = POWER_VDDMEMCTRL_BO_OFFSET_OFFSET,
+};
+
static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
uint32_t new_target, uint32_t new_brownout)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t cur_target, diff, bo_int = 0;
- uint32_t powered_by_linreg = 0;
- int adjust_up, tmp;
+ int powered_by_linreg = 0;
+ int adjust_up;
+
+ if (new_target < cfg->lowest_mV)
+ new_target = cfg->lowest_mV;
+ if (new_target > cfg->highest_mV)
+ new_target = cfg->highest_mV;
new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
cur_target += cfg->lowest_mV;
adjust_up = new_target > cur_target;
- powered_by_linreg = cfg->powered_by_linreg();
+ if (cfg->powered_by_linreg)
+ powered_by_linreg = cfg->powered_by_linreg();
if (adjust_up) {
if (powered_by_linreg) {
if (powered_by_linreg ||
(readl(&power_regs->hw_power_sts) &
- POWER_STS_VDD5V_GT_VDDIO))
+ POWER_STS_VDD5V_GT_VDDIO)) {
early_delay(500);
- else {
- for (;;) {
- tmp = readl(&power_regs->hw_power_sts);
- if (tmp & POWER_STS_DC_OK)
- break;
+ } else {
+ while (!(readl(&power_regs->hw_power_sts) &
+ POWER_STS_DC_OK)) {
+
}
}
void mxs_power_init(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
mxs_power_clock2xtal();
mxs_power_clear_auto_restart();
mxs_power_set_linreg();
- mxs_power_setup_5v_detect();
- mxs_setup_batt_detect();
+ if (!fixed_batt_supply) {
+ mxs_power_setup_5v_detect();
+ mxs_setup_batt_detect();
+ }
mxs_power_configure_power_source();
mxs_enable_output_rail_protection();
- mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
- mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
-
+ mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
+ mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
+ mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
+#if VDDMEM_VAL > 0
+ mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
+
+ setbits_le32(&power_regs->hw_power_vddmemctrl,
+ POWER_VDDMEMCTRL_ENABLE_LINREG);
+ early_delay(500);
+ clrbits_le32(&power_regs->hw_power_vddmemctrl,
+ POWER_VDDMEMCTRL_ENABLE_ILIMIT);
+#else
+ clrbits_le32(&power_regs->hw_power_vddmemctrl,
+ POWER_VDDMEMCTRL_ENABLE_LINREG);
+#endif
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
-
- writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
-
- early_delay(1000);
+ if (!fixed_batt_supply)
+ writel(POWER_5VCTRL_PWDN_5VBRNOUT,
+ &power_regs->hw_power_5vctrl_set);
}
#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
void mxs_power_wait_pswitch(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
;
}
DECLARE_GLOBAL_DATA_PTR;
-#define timestamp (gd->arch.tbl)
-#define lastdec (gd->arch.lastinc)
+/* Enable this to verify that the code can correctly
+ * handle the timer rollover
+ */
+/* #define DEBUG_TIMER_WRAP */
+
+#ifdef DEBUG_TIMER_WRAP
+/*
+ * Let the timer wrap 15 seconds after start to catch misbehaving
+ * timer related code early
+ */
+#define TIMER_START (-time_to_tick(15 * CONFIG_SYS_HZ))
+#else
+#define TIMER_START 0UL
+#endif
/*
* This driver uses 1kHz clock source.
*/
-#define MX28_INCREMENTER_HZ 1000
+#define MXS_INCREMENTER_HZ 1000
static inline unsigned long tick_to_time(unsigned long tick)
{
- return tick / (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ);
+ return tick / (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ);
}
static inline unsigned long time_to_tick(unsigned long time)
{
- return time * (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ);
-}
-
-/* Calculate how many ticks happen in "us" microseconds */
-static inline unsigned long us_to_tick(unsigned long us)
-{
- return (us * MX28_INCREMENTER_HZ) / 1000000;
+ return time * (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ);
}
int timer_init(void)
TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL,
&timrot_regs->hw_timrot_timctrl0);
- /* Set fixed_count to maximal value */
+#ifndef DEBUG_TIMER_WRAP
+ /* Set fixed_count to maximum value */
writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
-
+#else
+ /* Set fixed_count so that the counter will wrap after 20 seconds */
+ writel(20 * MXS_INCREMENTER_HZ,
+ &timrot_regs->hw_timrot_fixed_count0);
+ gd->arch.lastinc = TIMER_LOAD_VAL - 20 * MXS_INCREMENTER_HZ;
+#endif
+#ifdef DEBUG_TIMER_WRAP
+ /* Make the usec counter roll over 30 seconds after startup */
+ writel(-30000000, MXS_HW_DIGCTL_MICROSECONDS);
+#endif
+ writel(TIMROT_TIMCTRLn_UPDATE,
+ &timrot_regs->hw_timrot_timctrl0_clr);
+#ifdef DEBUG_TIMER_WRAP
+ /* Set fixed_count to maximal value for subsequent loads */
+ writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
+#endif
+ gd->arch.timer_rate_hz = MXS_INCREMENTER_HZ;
+ gd->arch.tbl = TIMER_START;
+ gd->arch.tbu = 0;
return 0;
}
+/* Note: This function works correctly for TIMER_LOAD_VAL == 0xffffffff!
+ * The rollover is handled automagically due to the properties of
+ * two's complement arithmetic.
+ * For any other value of TIMER_LOAD_VAL the calculations would have
+ * to be done modulus(TIMER_LOAD_VAL + 1).
+ */
unsigned long long get_ticks(void)
{
struct mxs_timrot_regs *timrot_regs =
(struct mxs_timrot_regs *)MXS_TIMROT_BASE;
-
- /* Current tick value */
- uint32_t now = readl(&timrot_regs->hw_timrot_running_count0);
-
- if (lastdec >= now) {
- /*
- * normal mode (non roll)
- * move stamp forward with absolut diff ticks
- */
- timestamp += (lastdec - now);
- } else {
- /* we have rollover of decrementer */
- timestamp += (TIMER_LOAD_VAL - now) + lastdec;
-
- }
- lastdec = now;
-
- return timestamp;
+ /* The timer is counting down, so subtract the register value from
+ * the counter period length to get an incrementing timestamp
+ */
+ unsigned long now = -readl(&timrot_regs->hw_timrot_running_count0);
+ ulong inc = now - gd->arch.lastinc;
+
+ gd->arch.tbl += inc;
+ gd->arch.lastinc = now;
+ /* Since the get_timer() function only uses a 32bit value
+ * it doesn't make sense to return a real 64 bit value here.
+ */
+ return gd->arch.tbl;
}
ulong get_timer_masked(void)
ulong get_timer(ulong base)
{
- return get_timer_masked() - base;
+ /* NOTE: time_to_tick(base) is required to correctly handle rollover! */
+ return tick_to_time(get_ticks() - time_to_tick(base));
}
/* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */
-#define MX28_HW_DIGCTL_MICROSECONDS 0x8001c0c0
+#define MXS_HW_DIGCTL_MICROSECONDS 0x8001c0c0
void __udelay(unsigned long usec)
{
- uint32_t old, new, incr;
- uint32_t counter = 0;
-
- old = readl(MX28_HW_DIGCTL_MICROSECONDS);
-
- while (counter < usec) {
- new = readl(MX28_HW_DIGCTL_MICROSECONDS);
-
- /* Check if the timer wrapped. */
- if (new < old) {
- incr = 0xffffffff - old;
- incr += new;
- } else {
- incr = new - old;
- }
-
- /*
- * Check if we are close to the maximum time and the counter
- * would wrap if incremented. If that's the case, break out
- * from the loop as the requested delay time passed.
+ uint32_t start = readl(MXS_HW_DIGCTL_MICROSECONDS);
+
+ while (readl(MXS_HW_DIGCTL_MICROSECONDS) - start <= usec)
+ /* use '<=' to guarantee a delay of _at least_
+ * the given number of microseconds.
+ * No need for fancy rollover checks
+ * Two's complement arithmetic applied correctly
+ * does everything that's needed automagically!
*/
- if (counter + incr < counter)
- break;
-
- counter += incr;
- old = new;
- }
+ ;
}
ulong get_tbclk(void)
{
- return MX28_INCREMENTER_HZ;
+ return gd->arch.timer_rate_hz;
}
sources {
- u_boot_spl="spl/u-boot-spl.bin";
- u_boot="u-boot.bin";
+ u_boot_spl="spl/u-boot-spl";
+ u_boot="u-boot";
}
section (0) {
- load u_boot_spl > 0x0000;
- load ivt (entry = 0x0014) > 0x8000;
+ load u_boot_spl;
+ load ivt (entry = u_boot_spl:reset) > 0x8000;
hab call 0x8000;
- load u_boot > 0x40000100;
- load ivt (entry = 0x40000100) > 0x8000;
+ load u_boot;
+ load ivt (entry = u_boot:reset) > 0x8000;
hab call 0x8000;
}
COBJS += board.o
COBJS += mux.o
COBJS-$(CONFIG_NAND_OMAP_GPMC) += elm.o
+COBJS-$(CONFIG_NAND_AM33XX) += elm.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
-#include <cpsw.h>
+//#include <cpsw.h>
#include <asm/errno.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+ static int trg __attribute__((section(".data")));
+
+ switch (trg) {
+ case 0:
+ case 1:
+ if (readl(&wdtimer->wdtwwps) & (1 << 4))
+ return;
+ writel(trg ? 0x5555 : 0xaaaa, &wdtimer->wdtwspr);
+ break;
+ case 2:
+ if (readl(&wdtimer->wdtwwps) & (1 << 2))
+ return;
+ /* 10 sec timeout */
+ writel(-32768 * 10, &wdtimer->wdtwldr);
+
+ if (readl(&wdtimer->wdtwwps) & (1 << 0))
+ return;
+ /* prescaler = 1 */
+ writel(0, &wdtimer->wdtwclr);
+ break;
+
+ case 3:
+ case 4:
+ /* enable watchdog */
+ if (readl(&wdtimer->wdtwwps) & (1 << 4))
+ return;
+ writel((trg & 1) ? 0xBBBB : 0x4444, &wdtimer->wdtwspr);
+ break;
+
+ default:
+ /* retrigger watchdog */
+ if (readl(&wdtimer->wdtwwps) & (1 << 3))
+ return;
+
+ writel(trg, &wdtimer->wdtwtgr);
+ trg ^= 0x2;
+ return;
+ }
+ trg++;
+}
+#endif
+
#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
int cpu_mmc_init(bd_t *bis)
{
#define CLK_DIV_MASK 0x1f
#define CLK_DIV2_MASK 0x7f
#define CLK_SEL_SHIFT 0x8
+#define CLK_MODE_MASK 0x7
#define CLK_MODE_SEL 0x7
-#define CLK_MODE_MASK 0xfffffff8
-#define CLK_DIV_SEL 0xFFFFFFE0
-#define CPGMAC0_IDLE 0x30000
-#define DPLL_CLKDCOLDO_GATE_CTRL 0x300
+#define DPLL_CLKDCOLDO_GATE_CTRL 0x300
+
const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
+#ifdef CONFIG_SPL_BUILD
+#define enable_clk(reg, val) __enable_clk(#reg, ®, val)
+
+static void __enable_clk(const char *name, const void *reg, u32 mask)
+{
+ unsigned long timeout = 10000000;
+
+ writel(mask, reg);
+ while (readl(reg) != mask)
+ /* poor man's timeout, since timers not initialized */
+ if (timeout-- == 0)
+ /* no error message, since console not yet available */
+ break;
+}
+
static void enable_interface_clocks(void)
{
/* Enable all the Interconnect Modules */
- writel(PRCM_MOD_EN, &cmper->l3clkctrl);
- while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
- ;
-
- writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
- while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
- ;
-
- writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
- while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
- ;
-
- writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
- while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
- ;
-
- writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
- while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
- ;
-
- writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
- while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
- ;
-
- writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
- while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
- ;
+ enable_clk(cmper->l3clkctrl, PRCM_MOD_EN);
+ enable_clk(cmper->l4lsclkctrl, PRCM_MOD_EN);
+ enable_clk(cmper->l4fwclkctrl, PRCM_MOD_EN);
+ enable_clk(cmwkup->wkl4wkclkctrl, PRCM_MOD_EN);
+ enable_clk(cmper->l3instrclkctrl, PRCM_MOD_EN);
+ enable_clk(cmper->l4hsclkctrl, PRCM_MOD_EN);
+#ifdef CONFIG_HW_WATCHDOG
+ enable_clk(cmwkup->wdtimer1ctrl, PRCM_MOD_EN);
+#endif
+ /* GPIO0 */
+ enable_clk(cmwkup->wkgpio0clkctrl, PRCM_MOD_EN);
}
/*
static void enable_per_clocks(void)
{
/* Enable the control module though RBL would have done it*/
- writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
- while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
- ;
-
- /* Enable the module clock */
- writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
- while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
- ;
-
+ enable_clk(cmwkup->wkctrlclkctrl, PRCM_MOD_EN);
+ /* Enable the timer2 clock */
+ enable_clk(cmper->timer2clkctrl, PRCM_MOD_EN);
/* Select the Master osc 24 MHZ as Timer2 clock source */
writel(0x1, &cmdpll->clktimer2clk);
+#ifdef CONFIG_SYS_NS16550_COM1
/* UART0 */
- writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
- while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
- ;
-
- /* UART1 */
-#ifdef CONFIG_SERIAL2
- writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
- while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
- ;
-#endif /* CONFIG_SERIAL2 */
-
- /* UART2 */
-#ifdef CONFIG_SERIAL3
- writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
- while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
- ;
-#endif /* CONFIG_SERIAL3 */
-
- /* UART3 */
-#ifdef CONFIG_SERIAL4
- writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
- while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
- ;
-#endif /* CONFIG_SERIAL4 */
-
- /* UART4 */
-#ifdef CONFIG_SERIAL5
- writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
- while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
- ;
-#endif /* CONFIG_SERIAL5 */
-
- /* UART5 */
-#ifdef CONFIG_SERIAL6
- writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
- while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
- ;
-#endif /* CONFIG_SERIAL6 */
-
+ enable_clk(cmwkup->wkup_uart0ctrl, PRCM_MOD_EN);
+#endif
+#ifdef CONFIG_SYS_NS16550_COM2
+ enable_clk(cmper->uart1clkctrl, PRCM_MOD_EN);
+#endif
+#ifdef CONFIG_SYS_NS16550_COM3
+ enable_clk(cmper->uart2clkctrl, PRCM_MOD_EN);
+#endif
+#ifdef CONFIG_SYS_NS16550_COM4
+ enable_clk(cmper->uart3clkctrl, PRCM_MOD_EN);
+#endif
+#ifdef CONFIG_SYS_NS16550_COM5
+ enable_clk(cmper->uart4clkctrl, PRCM_MOD_EN);
+#endif
+#ifdef CONFIG_SYS_NS16550_COM6
+ enable_clk(cmper->uart5clkctrl, PRCM_MOD_EN);
+#endif
/* GPMC */
- writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
- while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
- ;
+ enable_clk(cmper->gpmcclkctrl, PRCM_MOD_EN);
/* ELM */
- writel(PRCM_MOD_EN, &cmper->elmclkctrl);
- while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
- ;
+ enable_clk(cmper->elmclkctrl, PRCM_MOD_EN);
- /* MMC0*/
- writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
- while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
- ;
+ /* Ethernet */
+ enable_clk(cmper->cpswclkstctrl, PRCM_MOD_EN);
+ enable_clk(cmper->cpgmac0clkctrl, PRCM_MOD_EN);
+
+ /* MMC */
+#ifndef CONFIG_OMAP_MMC_DEV_0
+ enable_clk(cmper->mmc0clkctrl, PRCM_MOD_EN);
+#endif
+#ifdef CONFIG_OMAP_MMC_DEV_1
+ enable_clk(cmper->mmc1clkctrl, PRCM_MOD_EN);
+#endif
+ /* LCD */
+ enable_clk(cmper->lcdclkctrl, PRCM_MOD_EN);
/* i2c0 */
- writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
- while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
- ;
+ enable_clk(cmwkup->wkup_i2c0ctrl, PRCM_MOD_EN);
- /* gpio1 module */
- writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
- while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
- ;
-
- /* gpio2 module */
- writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
- while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
- ;
-
- /* gpio3 module */
- writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
- while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
- ;
+ /* GPIO1-3 */
+ enable_clk(cmper->gpio1clkctrl, PRCM_MOD_EN);
+ enable_clk(cmper->gpio2clkctrl, PRCM_MOD_EN);
+ enable_clk(cmper->gpio3clkctrl, PRCM_MOD_EN);
/* i2c1 */
- writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
- while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
- ;
-
- /* Ethernet */
- writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
- while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
- ;
+ enable_clk(cmper->i2c1clkctrl, PRCM_MOD_EN);
/* spi0 */
- writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
- while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
- ;
+ enable_clk(cmper->spi0clkctrl, PRCM_MOD_EN);
- /* RTC */
- writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
- while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
- ;
+ /* rtc */
+ enable_clk(cmrtc->rtcclkctrl, PRCM_MOD_EN);
- /* MUSB */
- writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
- while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
- ;
+ /* usb0 */
+ enable_clk(cmper->usb0clkctrl, PRCM_MOD_EN);
}
static void mpu_pll_config(void)
while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
;
- clksel = clksel & (~CLK_SEL_MASK);
- clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
+ clksel &= ~CLK_SEL_MASK;
+ clksel |= (MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N;
writel(clksel, &cmwkup->clkseldpllmpu);
- div_m2 = div_m2 & ~CLK_DIV_MASK;
- div_m2 = div_m2 | MPUPLL_M2;
+ div_m2 &= ~CLK_DIV_MASK;
+ div_m2 |= MPUPLL_M2;
writel(div_m2, &cmwkup->divm2dpllmpu);
- clkmode = clkmode | CLK_MODE_SEL;
+ clkmode &= ~CLK_MODE_MASK;
+ clkmode |= CLK_MODE_SEL;
writel(clkmode, &cmwkup->clkmoddpllmpu);
while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
;
- clksel = clksel & (~CLK_SEL_MASK);
- clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
+ clksel &= ~CLK_SEL_MASK;
+ clksel |= ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
writel(clksel, &cmwkup->clkseldpllcore);
- div_m4 = div_m4 & ~CLK_DIV_MASK;
- div_m4 = div_m4 | COREPLL_M4;
+ div_m4 &= ~CLK_DIV_MASK;
+ div_m4 |= COREPLL_M4;
writel(div_m4, &cmwkup->divm4dpllcore);
- div_m5 = div_m5 & ~CLK_DIV_MASK;
- div_m5 = div_m5 | COREPLL_M5;
+ div_m5 &= ~CLK_DIV_MASK;
+ div_m5 |= COREPLL_M5;
writel(div_m5, &cmwkup->divm5dpllcore);
- div_m6 = div_m6 & ~CLK_DIV_MASK;
- div_m6 = div_m6 | COREPLL_M6;
+ div_m6 &= ~CLK_DIV_MASK;
+ div_m6 |= COREPLL_M6;
writel(div_m6, &cmwkup->divm6dpllcore);
- clkmode = clkmode | CLK_MODE_SEL;
+ clkmode &= ~CLK_MODE_MASK;
+ clkmode |= CLK_MODE_SEL;
writel(clkmode, &cmwkup->clkmoddpllcore);
while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
;
- clksel = clksel & (~CLK_SEL_MASK);
- clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
+ clksel &= ~CLK_SEL_MASK;
+ clksel |= (PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N;
writel(clksel, &cmwkup->clkseldpllper);
- div_m2 = div_m2 & ~CLK_DIV2_MASK;
- div_m2 = div_m2 | PERPLL_M2;
+ div_m2 &= ~CLK_DIV2_MASK;
+ div_m2 |= PERPLL_M2;
writel(div_m2, &cmwkup->divm2dpllper);
- clkmode = clkmode | CLK_MODE_SEL;
+ clkmode &= ~CLK_MODE_MASK;
+ clkmode |= CLK_MODE_SEL;
writel(clkmode, &cmwkup->clkmoddpllper);
while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
}
+static void disp_pll_config(void)
+{
+ u32 clkmode, clksel, div_m2;
+
+ clkmode = readl(&cmwkup->clkmoddplldisp);
+ clksel = readl(&cmwkup->clkseldplldisp);
+ div_m2 = readl(&cmwkup->divm2dplldisp);
+
+ /* Set the PLL to bypass Mode */
+ writel(PLL_BYPASS_MODE, &cmwkup->clkmoddplldisp);
+
+ while (!(readl(&cmwkup->idlestdplldisp) & ST_MN_BYPASS))
+ ;
+
+ clksel &= ~CLK_SEL_MASK;
+ clksel |= (DISPPLL_M << CLK_SEL_SHIFT) | DISPPLL_N;
+ writel(clksel, &cmwkup->clkseldplldisp);
+
+ div_m2 &= ~CLK_DIV2_MASK;
+ div_m2 |= DISPPLL_M2;
+ writel(div_m2, &cmwkup->divm2dplldisp);
+
+ clkmode &= ~CLK_MODE_MASK;
+ clkmode |= CLK_MODE_SEL;
+ writel(clkmode, &cmwkup->clkmoddplldisp);
+
+ while (!(readl(&cmwkup->idlestdplldisp) & ST_DPLL_CLK))
+ ;
+}
+
void ddr_pll_config(unsigned int ddrpll_m)
{
u32 clkmode, clksel, div_m2;
div_m2 = readl(&cmwkup->divm2dpllddr);
/* Set the PLL to bypass Mode */
- clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
+ clkmode &= ~CLK_MODE_MASK;
+ clkmode |= PLL_BYPASS_MODE;
writel(clkmode, &cmwkup->clkmoddpllddr);
/* Wait till bypass mode is enabled */
- while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
- != ST_MN_BYPASS)
+ while (!(readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS))
;
- clksel = clksel & (~CLK_SEL_MASK);
- clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
+ clksel &= ~CLK_SEL_MASK;
+ clksel |= (ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N;
writel(clksel, &cmwkup->clkseldpllddr);
- div_m2 = div_m2 & CLK_DIV_SEL;
- div_m2 = div_m2 | DDRPLL_M2;
+ div_m2 &= ~CLK_DIV_MASK;
+ div_m2 |= DDRPLL_M2;
writel(div_m2, &cmwkup->divm2dpllddr);
- clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
+ clkmode &= ~CLK_MODE_MASK;
+ clkmode |= CLK_MODE_SEL;
writel(clkmode, &cmwkup->clkmoddpllddr);
/* Wait till dpll is locked */
mpu_pll_config();
core_pll_config();
per_pll_config();
+ disp_pll_config();
/* Enable the required interconnect clocks */
enable_interface_clocks();
/* Enable the required peripherals */
enable_per_clocks();
}
+#endif
+
+#define M(mn) (((mn) & CLK_SEL_MASK) >> CLK_SEL_SHIFT)
+#define N(mn) ((mn) & CLK_DIV2_MASK)
+
+unsigned long __clk_get_rate(u32 m_n, u32 div_m2)
+{
+ unsigned long rate;
+
+ div_m2 &= CLK_DIV_MASK;
+ debug("M=%u N=%u M2=%u\n", M(m_n), N(m_n), div_m2);
+ rate = V_OSCK / 1000 * M(m_n) / (N(m_n) + 1) / div_m2;
+ debug("CLK = %lu.%03luMHz\n", rate / 1000, rate % 1000);
+ return rate * 1000;
+}
+
+unsigned long lcdc_clk_rate(void)
+{
+ return clk_get_rate(cmwkup, disp);
+}
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/cpu.h>
-#include <asm/arch/omap_gpmc.h>
-#include <asm/arch/elm.h>
+#include <asm/arch/nand.h>
-#define ELM_DEFAULT_POLY (0)
+#define ELM_DEFAULT_POLY 0
-struct elm *elm_cfg;
+/* make sure this variable does not end up in bss
+ * because that would corrupt the relocation section
+ * that is overlayed with the bss section
+ */
+static struct elm *elm_cfg __attribute__((section(".data")));
/**
* elm_load_syndromes - Load BCH syndromes based on nibble selection
*/
static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly)
{
- u32 *ptr;
u32 val;
+ struct syndrome *sf = &elm_cfg->syndrome_fragments[poly];
/* reg 0 */
- ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[0];
val = syndrome[0] | (syndrome[1] << 8) | (syndrome[2] << 16) |
(syndrome[3] << 24);
- writel(val, ptr);
+ writel(val, &sf->syndrome_fragment_x[0]);
+
/* reg 1 */
- ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[1];
val = syndrome[4] | (syndrome[5] << 8) | (syndrome[6] << 16) |
(syndrome[7] << 24);
- writel(val, ptr);
+ writel(val, &sf->syndrome_fragment_x[1]);
/* BCH 8-bit with 26 nibbles (4*8=32) */
if (nibbles > 13) {
/* reg 2 */
- ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2];
val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) |
(syndrome[11] << 24);
- writel(val, ptr);
+ writel(val, &sf->syndrome_fragment_x[2]);
+
/* reg 3 */
- ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[3];
- val = syndrome[12] | (syndrome[13] << 8) |
- (syndrome[14] << 16) | (syndrome[15] << 24);
- writel(val, ptr);
+ val = syndrome[12] | (syndrome[13] << 8) | (syndrome[14] << 16) |
+ (syndrome[15] << 24);
+ writel(val, &sf->syndrome_fragment_x[3]);
}
/* BCH 16-bit with 52 nibbles (7*8=56) */
if (nibbles > 26) {
/* reg 4 */
- ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4];
- val = syndrome[16] | (syndrome[17] << 8) |
- (syndrome[18] << 16) | (syndrome[19] << 24);
- writel(val, ptr);
+ val = syndrome[16] | (syndrome[17] << 8) | (syndrome[18] << 16) |
+ (syndrome[19] << 24);
+ writel(val, &sf->syndrome_fragment_x[4]);
/* reg 5 */
- ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[5];
- val = syndrome[20] | (syndrome[21] << 8) |
- (syndrome[22] << 16) | (syndrome[23] << 24);
- writel(val, ptr);
+ val = syndrome[20] | (syndrome[21] << 8) | (syndrome[22] << 16) |
+ (syndrome[23] << 24);
+ writel(val, &sf->syndrome_fragment_x[5]);
/* reg 6 */
- ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6];
- val = syndrome[24] | (syndrome[25] << 8) |
- (syndrome[26] << 16) | (syndrome[27] << 24);
- writel(val, ptr);
+ val = syndrome[24] | (syndrome[25] << 8) | (syndrome[26] << 16) |
+ (syndrome[27] << 24);
+ writel(val, &sf->syndrome_fragment_x[6]);
}
}
/**
- * elm_check_errors - Check for BCH errors and return error locations
+ * elm_check_error - Check for BCH errors and return error locations
* @syndrome: BCH syndrome
* @nibbles:
* @error_count: Returns number of errrors in the syndrome
/* start processing */
writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6])
| ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID),
- &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]);
+ &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]);
/* wait for processing to complete */
- while ((readl(&elm_cfg->irqstatus) & (0x1 << poly)) != 0x1)
- ;
+ while (!(readl(&elm_cfg->irqstatus) & (0x1 << poly)));
/* clear status */
- writel((readl(&elm_cfg->irqstatus) | (0x1 << poly)),
- &elm_cfg->irqstatus);
+ writel((readl(&elm_cfg->irqstatus) & ~(0x1 << poly)),
+ &elm_cfg->irqstatus);
/* check if correctable */
location_status = readl(&elm_cfg->error_location[poly].location_status);
/* get error count */
*error_count = readl(&elm_cfg->error_location[poly].location_status) &
- ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK;
+ ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK;
- for (i = 0; i < *error_count; i++) {
+ for (i = 0; i < *error_count; i++)
error_locations[i] =
readl(&elm_cfg->error_location[poly].error_location_x[i]);
- }
return 0;
}
u32 get_device_type(void)
{
int mode;
- mode = readl(&cstat->statusreg) & (DEVICE_MASK);
+ mode = readl(&cstat->statusreg) & DEVICE_MASK;
return mode >>= 8;
}
u32 get_sysboot_value(void)
{
int mode;
- mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
+ mode = readl(&cstat->statusreg) & SYSBOOT_MASK;
return mode;
}
#ifdef CONFIG_DISPLAY_CPUINFO
+#define SYSBOOT_FREQ_SHIFT 22
+#define SYSBOOT_FREQ_MASK (3 << SYSBOOT_FREQ_SHIFT)
+
+static unsigned long bootfreqs[] = {
+ 19200000,
+ 24000000,
+ 25000000,
+ 26000000,
+};
+
+static u32 get_sysboot_freq(void)
+{
+ int mode;
+ mode = readl(&cstat->statusreg) & SYSBOOT_FREQ_MASK;
+ return bootfreqs[mode >> SYSBOOT_FREQ_SHIFT];
+}
+
/**
* Print CPU information
*/
int print_cpuinfo(void)
{
char *cpu_s, *sec_s;
- int arm_freq, ddr_freq;
+ unsigned long clk;
+ const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
switch (get_cpu_type()) {
- case AM335X:
+ case AM335X_ID:
cpu_s = "AM335X";
break;
default:
cpu_s = "Unknown cpu type";
- break;
}
switch (get_device_type()) {
sec_s = "?";
}
- printf("AM%s-%s rev %d\n",
+ printf("%s-%s rev %d\n",
cpu_s, sec_s, get_cpu_rev());
- /* TODO: Print ARM and DDR frequencies */
+ clk = get_sysboot_freq();
+ printf("OSC clk: %4lu.%03lu MHz\n",
+ clk / 1000000, clk / 1000 % 1000);
+ clk = clk_get_rate(cmwkup, mpu);
+ printf("MPU clk: %4lu.%03lu MHz\n",
+ clk / 1000000, clk / 1000 % 1000);
+ clk = clk_get_rate(cmwkup, ddr);
+ printf("DDR clk: %4lu.%03lu MHz\n",
+ clk / 1000000, clk / 1000 % 1000);
+ clk = clk_get_rate(cmwkup, per);
+ printf("PER clk: %4lu.%03lu MHz\n",
+ clk / 1000000, clk / 1000 % 1000);
+#ifdef CONFIG_LCD
+ clk = clk_get_rate(cmwkup, disp);
+ printf("LCD clk: %4lu.%03lu MHz\n",
+ clk / 1000000, clk / 1000 % 1000);
+#endif
return 0;
}
/* Invalidate TLB */
static void v7_inval_tlb(void)
{
- /* Invalidate entire unified TLB */
- asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
- /* Invalidate entire data TLB */
- asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0));
- /* Invalidate entire instruction TLB */
- asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
- /* Full system DSB - make sure that the invalidation is complete */
- CP15DSB;
- /* Full system ISB - make sure the instruction stream sees it */
- CP15ISB;
+ asm volatile (
+ /* Invalidate entire unified TLB */
+ "mcr p15, 0, %0, c8, c7, 0\n"
+ /* Invalidate entire data TLB */
+ "mcr p15, 0, %0, c8, c6, 0\n"
+ /* Invalidate entire instruction TLB */
+ "mcr p15, 0, %0, c8, c5, 0\n"
+ /* Full system DSB - make sure that the invalidation is complete */
+ "mcr p15, 0, %0, c7, c10, 4\n"
+ /* Full system ISB - make sure the instruction stream sees it */
+ "mcr p15, 0, %0, c7, c5, 4\n"
+ : : "r" (0));
}
void invalidate_dcache_all(void)
* Invalidate all instruction caches to PoU.
* Also flushes branch target cache.
*/
- asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
-
- /* Invalidate entire branch predictor array */
- asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
-
- /* Full system DSB - make sure that the invalidation is complete */
- CP15DSB;
-
- /* ISB - make sure the instruction stream sees it */
- CP15ISB;
+ asm volatile (
+ "mcr p15, 0, %0, c7, c5, 0\n"
+ /* Invalidate entire branch predictor array */
+ "mcr p15, 0, %0, c7, c5, 6\n"
+ /* Full system DSB - make sure that the invalidation is complete */
+ "mcr p15, 0, %0, c7, c10, 4\n"
+ /* ISB - make sure the instruction stream sees it */
+ "mcr p15, 0, %0, c7, c5, 4\n"
+ : : "r" (0));
}
#else
void invalidate_icache_all(void)
#include <common.h>
#include <command.h>
+#include <lcd.h>
#include <asm/system.h>
#include <asm/cache.h>
#include <asm/armv7.h>
*/
#ifndef CONFIG_SPL_BUILD
disable_interrupts();
-#endif
+#ifdef CONFIG_LCD
+ {
+ /* switch off LCD panel */
+ lcd_panel_disable();
+ /* disable LCD controller */
+ lcd_disable();
+ }
+#endif /* CONFIG_LCD */
+#endif /* CONFIG_SPL_BUILD */
/*
* Turn off I-cache and invalidate it
LIB = $(obj)lib$(SOC).o
-COBJS = soc.o clock.o iomux.o
+COBJS = soc.o clock.o
+ifneq ($(CONFIG_SYS_MX5_IOMUX_V3),)
+ COBJS += iomux-v3.o
+else
+ COBJS += iomux.o
+endif
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+int clk_enable(struct clk *clk)
+{
+ int ret = 0;
+
+ if (!clk)
+ return 0;
+ if (clk->usecount++ == 0) {
+ ret = clk->enable(clk);
+ if (ret)
+ clk->usecount--;
+ }
+ return ret;
+}
+
+void clk_disable(struct clk *clk)
+{
+ if (!clk)
+ return;
+
+ if (!(--clk->usecount)) {
+ if (clk->disable)
+ clk->disable(clk);
+ }
+ if (clk->usecount < 0) {
+ printf("%s: clk %p underflow\n", __func__, clk);
+ hang();
+ }
+}
+
void set_usboh3_clk(void)
{
clrsetbits_le32(&mxc_ccm->cscmr1,
MXC_CCM_CCGR2_USBOH3_60M(cg));
}
+void ipu_clk_enable(void)
+{
+ /* IPU root clock derived from AXI B */
+ clrsetbits_le32(&mxc_ccm->cbcmr, MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK,
+ MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(1));
+
+ setbits_le32(&mxc_ccm->CCGR5,
+ MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK));
+
+ /* Handshake with IPU when certain clock rates are changed. */
+ clrbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK);
+
+ /* Handshake with IPU when LPM is entered as its enabled. */
+ clrbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS);
+}
+
+void ipu_clk_disable(void)
+{
+ clrbits_le32(&mxc_ccm->CCGR5,
+ MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK));
+
+ /* Handshake with IPU when certain clock rates are changed. */
+ setbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK);
+
+ /* Handshake with IPU when LPM is entered as its enabled. */
+ setbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS);
+}
+
#ifdef CONFIG_I2C_MXC
/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
{ \
- writel(0x1232, &pll->ctrl); \
- writel(0x2, &pll->config); \
- writel((((pd) - 1) << 0) | ((fi) << 4), \
- &pll->op); \
- writel(fn, &(pll->mfn)); \
- writel((fd) - 1, &pll->mfd); \
- writel((((pd) - 1) << 0) | ((fi) << 4), \
- &pll->hfs_op); \
- writel(fn, &pll->hfs_mfn); \
- writel((fd) - 1, &pll->hfs_mfd); \
- writel(0x1232, &pll->ctrl); \
- while (!readl(&pll->ctrl) & 0x1) \
+ __raw_writel(0x1232, &pll->ctrl); \
+ __raw_writel(0x2, &pll->config); \
+ __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
+ &pll->op); \
+ __raw_writel(fn, &(pll->mfn)); \
+ __raw_writel((fd) - 1, &pll->mfd); \
+ __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
+ &pll->hfs_op); \
+ __raw_writel(fn, &pll->hfs_mfn); \
+ __raw_writel((fd) - 1, &pll->hfs_mfd); \
+ __raw_writel(0x1232, &pll->ctrl); \
+ while (!__raw_readl(&pll->ctrl) & 0x1) \
;\
}
static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
{
- u32 ccsr = readl(&mxc_ccm->ccsr);
+ u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
struct mxc_pll_reg *pll = mxc_plls[index];
switch (index) {
case PLL1_CLOCK:
/* Switch ARM to PLL2 clock */
- writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
- &mxc_ccm->ccsr);
+ __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
- writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
- &mxc_ccm->ccsr);
+ __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
break;
case PLL2_CLOCK:
/* Switch to pll2 bypass clock */
- writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
- &mxc_ccm->ccsr);
+ __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
- writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
- &mxc_ccm->ccsr);
+ __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
break;
case PLL3_CLOCK:
/* Switch to pll3 bypass clock */
- writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
- &mxc_ccm->ccsr);
+ __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
- writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
- &mxc_ccm->ccsr);
+ __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
break;
#ifdef CONFIG_MX53
case PLL4_CLOCK:
/* Switch to pll4 bypass clock */
- writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
- &mxc_ccm->ccsr);
+ __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
- writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
- &mxc_ccm->ccsr);
+ __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
break;
#endif
default:
/* The case that periph uses PLL1 is not considered here */
ret = calc_pll_params(ref, freq, &pll_param);
if (ret != 0) {
- printf("Error:Can't find pll parameters: %d\n", ret);
+ printf("Error: Can't find pll parameters for %u.%03uMHz ref %u.%03uMHz\n",
+ freq / 1000000, freq / 1000 % 1000,
+ ref / 1000000, ref / 1000 % 1000);
return ret;
}
--- /dev/null
+/*
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ * <armlinux@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-v3.h>
+#include <asm/arch/sys_proto.h>
+
+static void __iomem *base = (void __iomem *)IOMUXC_BASE_ADDR;
+
+/*
+ * configures a single pad in the iomuxer
+ */
+int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
+{
+ u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
+ u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+ u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
+ u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
+ u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
+ u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+
+ if (mux_ctrl_ofs)
+ __raw_writel(mux_mode, base + mux_ctrl_ofs);
+
+ if (sel_input_ofs)
+ __raw_writel(sel_input, base + sel_input_ofs);
+
+ if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
+ __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
+
+ return 0;
+}
+
+int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list, unsigned count)
+{
+ const iomux_v3_cfg_t *p = pad_list;
+ int i;
+ int ret;
+
+ for (i = 0; i < count; i++) {
+ ret = mxc_iomux_v3_setup_pad(*p);
+ if (ret)
+ return ret;
+ p++;
+ }
+ return 0;
+}
setup_pll PLL1_BASE_ADDR, 864
setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
#else
+#if !defined(CONFIG_SYS_CPU_CLK) || CONFIG_SYS_CPU_CLK == 800
setup_pll PLL1_BASE_ADDR, 800
+#elif CONFIG_SYS_CPU_CLK == 600
+ setup_pll PLL1_BASE_ADDR, 600
+#else
+#error Unsupported CONFIG_SYS_CPU_CLK value
+#endif
#endif
setup_pll PLL3_BASE_ADDR, 665
setup_pll PLL2_BASE_ADDR, 665
/* Switch peripheral to PLL2 */
- ldr r0, =CCM_BASE_ADDR
ldr r1, =0x19239145
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
setup_pll PLL2_BASE_ADDR, 400
/* Switch peripheral to PLL2 */
- ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00808145
orr r1, r1, #(2 << 10)
orr r1, r1, #(0 << 16)
/*change uart clk parent to pll2*/
ldr r1, [r0, #CLKCTL_CSCMR1]
- and r1, r1, #0xfcffffff
- orr r1, r1, #0x01000000
+ bic r1, #(0x3 << 24)
+ orr r1, r1, #(0x1 << 24)
str r1, [r0, #CLKCTL_CSCMR1]
/* make sure change is effective */
/* make uart div=6 */
ldr r1, [r0, #CLKCTL_CSCDR1]
- and r1, r1, #0xffffffc0
+ bic r1, #(0x3f << 0)
orr r1, r1, #0x0a
str r1, [r0, #CLKCTL_CSCDR1]
+ /* make sure divider effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
/* Restore the default values in the Gate registers */
ldr r1, =0xFFFFFFFF
W_DP_665: .word DP_OP_665
.word DP_MFD_665
.word DP_MFN_665
+W_DP_600: .word DP_OP_600
+ .word DP_MFD_600
+ .word DP_MFN_600
#endif
W_DP_216: .word DP_OP_216
.word DP_MFD_216
#error "CPU_TYPE not defined"
#endif
+#ifdef CONFIG_HW_WATCHDOG
+#define wdog_base ((void *)WDOG1_BASE_ADDR)
+#define WDOG_WCR 0x00
+#define WCR_WDE (1 << 2)
+#define WDOG_WSR 0x02
+
+void hw_watchdog_reset(void)
+{
+ if (readw(wdog_base + WDOG_WCR) & WCR_WDE) {
+ static u16 toggle = 0xaaaa;
+
+ writew(toggle, wdog_base + WDOG_WSR);
+ toggle ^= 0xffff;
+ }
+}
+#endif
+
u32 get_cpu_rev(void)
{
#ifdef CONFIG_MX51
#endif
#if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+static void __imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
int i;
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
for (i = 0; i < 6; i++)
mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
}
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+ __attribute__((weak, alias("__imx_get_mac_from_fuse")));
+
#endif
void set_chipselect_size(int const cs_size)
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+//#define DEBUG
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
enum pll_clocks {
- PLL_SYS, /* System PLL */
- PLL_BUS, /* System Bus PLL*/
- PLL_USBOTG, /* OTG USB PLL */
- PLL_ENET, /* ENET PLL */
+ PLL_ARM, /* PLL1: ARM PLL */
+ PLL_BUS, /* PLL2: System Bus PLL*/
+ PLL_USBOTG, /* PLL3: OTG USB PLL */
+ PLL_AUDIO, /* PLL4: Audio PLL */
+ PLL_VIDEO, /* PLL5: Video PLL */
+ PLL_ENET, /* PLL6: ENET PLL */
+ PLL_USB2, /* PLL7: USB2 PLL */
+ PLL_MLB, /* PLL8: MLB PLL */
};
-struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
+struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
+
+int clk_enable(struct clk *clk)
+{
+ int ret = 0;
+
+ if (!clk)
+ return 0;
+ if (clk->usecount == 0) {
+debug("%s: Enabling %s clock\n", __func__, clk->name);
+ ret = clk->enable(clk);
+ if (ret)
+ return ret;
+ clk->usecount++;
+ }
+ assert(clk->usecount > 0);
+ return ret;
+}
+
+void clk_disable(struct clk *clk)
+{
+ if (!clk)
+ return;
+
+ assert(clk->usecount > 0);
+ if (!(--clk->usecount)) {
+ if (clk->disable) {
+debug("%s: Disabling %s clock\n", __func__, clk->name);
+ clk->disable(clk);
+ }
+ }
+}
void enable_usboh3_clk(unsigned char enable)
{
u32 div;
switch (pll) {
- case PLL_SYS:
- div = __raw_readl(&imx_ccm->analog_pll_sys);
- div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
-
- return infreq * (div >> 1);
+ case PLL_ARM:
+ div = __raw_readl(&anatop->pll_arm);
+ if (div & BM_ANADIG_PLL_ARM_BYPASS)
+ /* Assume the bypass clock is always derived from OSC */
+ return infreq;
+ div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
+
+ return infreq * div / 2;
case PLL_BUS:
- div = __raw_readl(&imx_ccm->analog_pll_528);
- div &= BM_ANADIG_PLL_528_DIV_SELECT;
+ div = __raw_readl(&anatop->pll_528);
+ if (div & BM_ANADIG_PLL_SYS_BYPASS)
+ return infreq;
+ div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
- return infreq * (20 + (div << 1));
+ return infreq * (20 + div * 2);
case PLL_USBOTG:
- div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
+ div = __raw_readl(&anatop->usb1_pll_480_ctrl);
+ if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
+ return infreq;
div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
- return infreq * (20 + (div << 1));
+ return infreq * (20 + div * 2);
+ case PLL_AUDIO:
+ div = __raw_readl(&anatop->pll_audio);
+ if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
+ return infreq;
+ div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
+
+ return infreq * div;
+ case PLL_VIDEO:
+ div = __raw_readl(&anatop->pll_video);
+ if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
+ return infreq;
+ div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+
+ return infreq * div;
case PLL_ENET:
- div = __raw_readl(&imx_ccm->analog_pll_enet);
+ div = __raw_readl(&anatop->pll_enet);
+ if (div & BM_ANADIG_PLL_ENET_BYPASS)
+ return infreq;
div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
- return (div == 3 ? 125000000 : 25000000 * (div << 1));
- default:
+ return (div == 3 ? 125000000 : 25000000 * div * 2);
+ case PLL_USB2:
+ div = __raw_readl(&anatop->usb2_pll_480_ctrl);
+ if (div & BM_ANADIG_USB2_PLL_480_CTRL_BYPASS)
+ return infreq;
+ div &= BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT;
+
+ return infreq * (20 + div * 2);
+ case PLL_MLB:
+ div = __raw_readl(&anatop->pll_mlb);
+ if (div & BM_ANADIG_PLL_MLB_BYPASS)
+ return infreq;
+ /* unknown external clock provided on MLB_CLK pin */
return 0;
}
- /* NOTREACHED */
+ return 0;
}
static u32 get_mcu_main_clk(void)
reg = __raw_readl(&imx_ccm->cacrr);
reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
- freq = decode_pll(PLL_SYS, MXC_HCLK);
+ freq = decode_pll(PLL_ARM, MXC_HCLK);
return freq / (reg + 1);
}
case 2:
freq = MXC_HCLK;
break;
- default:
- break;
}
} else {
reg = __raw_readl(&imx_ccm->cbcmr);
case 3:
freq = PLL2_PFD2_DIV_FREQ;
break;
- default:
- break;
}
}
return root_freq / (emi_slow_pof + 1);
}
+static u32 get_nfc_clk(void)
+{
+ u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
+ u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
+ u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
+ int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
+ u32 root_freq;
+
+ switch (nfc_clk_sel) {
+ case 0:
+ root_freq = PLL2_PFD0_FREQ;
+ break;
+ case 1:
+ root_freq = decode_pll(PLL_BUS, MXC_HCLK);
+ break;
+ case 2:
+ root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ break;
+ case 3:
+ root_freq = PLL2_PFD2_FREQ;
+ break;
+ }
+
+ return root_freq / (pred + 1) / (podf + 1);
+}
+
static u32 get_mmdc_ch0_clk(void)
{
u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
int enable_sata_clock(void)
{
- u32 reg = 0;
+ u32 reg;
s32 timeout = 100000;
- struct mxc_ccm_reg *const imx_ccm
- = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
/* Enable sata clock */
reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
writel(reg, &imx_ccm->CCGR5);
/* Enable PLLs */
- reg = readl(&imx_ccm->analog_pll_enet);
- reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
- writel(reg, &imx_ccm->analog_pll_enet);
- reg |= BM_ANADIG_PLL_SYS_ENABLE;
+ reg = readl(&anatop->pll_enet);
+ reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
+ writel(reg, &anatop->pll_enet);
+ reg |= BM_ANADIG_PLL_ENET_ENABLE;
while (timeout--) {
- if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
+ if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
break;
}
if (timeout <= 0)
return -EIO;
- reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
- writel(reg, &imx_ccm->analog_pll_enet);
+ reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
+ writel(reg, &anatop->pll_enet);
reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
- writel(reg, &imx_ccm->analog_pll_enet);
+ writel(reg, &anatop->pll_enet);
return 0 ;
}
+void ipu_clk_enable(void)
+{
+ u32 reg = readl(&imx_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_CG0_MASK;
+ writel(reg, &imx_ccm->CCGR3);
+}
+
+void ipu_clk_disable(void)
+{
+ u32 reg = readl(&imx_ccm->CCGR3);
+ reg &= ~MXC_CCM_CCGR3_CG0_MASK;
+ writel(reg, &imx_ccm->CCGR3);
+}
+
+void ocotp_clk_enable(void)
+{
+ u32 reg = readl(&imx_ccm->CCGR2);
+ reg |= MXC_CCM_CCGR2_CG6_MASK;
+ writel(reg, &imx_ccm->CCGR2);
+}
+
+void ocotp_clk_disable(void)
+{
+ u32 reg = readl(&imx_ccm->CCGR2);
+ reg &= ~MXC_CCM_CCGR2_CG6_MASK;
+ writel(reg, &imx_ccm->CCGR2);
+}
+
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
return get_usdhc_clk(3);
case MXC_SATA_CLK:
return get_ahb_clk();
- default:
- break;
+ case MXC_NFC_CLK:
+ return get_nfc_clk();
}
return -1;
}
+static inline int gcd(int m, int n)
+{
+ int t;
+ while (m > 0) {
+ if (n > m) {
+ t = m;
+ m = n;
+ n = t;
+ } /* swap */
+ m -= n;
+ }
+ return n;
+}
+
+/* Config CPU clock */
+static int config_core_clk(u32 ref, u32 freq)
+{
+ int d;
+ int div = 0;
+ int mul = 0;
+ int min_err = ~0 >> 1;
+ u32 reg;
+
+ if (freq / ref > 108 || freq / ref * 8 < 54) {
+ return -EINVAL;
+ }
+
+ for (d = 1; d < 8; d++) {
+ int m = (freq + (ref - 1)) / ref;
+ unsigned long f;
+ int err;
+
+ if (m > 108 || m < 54)
+ return -EINVAL;
+
+ f = ref * m / d;
+ while (f > freq) {
+ if (--m < 54)
+ return -EINVAL;
+ f = ref * m / d;
+ }
+ err = freq - f;
+ if (err == 0)
+ break;
+ if (err < 0)
+ return -EINVAL;
+ if (err < min_err) {
+ mul = m;
+ div = d;
+ }
+ }
+ printf("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
+ mul, div, freq / 1000000, freq / 1000 % 1000,
+ ref * mul / div / 1000000, ref * mul / div / 1000 % 1000);
+
+ reg = readl(&anatop->pll_arm);
+ printf("anadig_pll_arm=%08x -> %08x\n",
+ reg, (reg & ~0x7f) | mul);
+#if 0
+ writel(div - 1, &imx_ccm->caccr);
+ reg &= 0x7f;
+ writel(reg | mul, &anatop->pll_arm);
+#endif
+ return 0;
+}
+
/*
- * Dump some core clockes.
+ * This function assumes the expected core clock has to be changed by
+ * modifying the PLL. This is NOT true always but for most of the times,
+ * it is. So it assumes the PLL output freq is the same as the expected
+ * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
+ * In the latter case, it will try to increase the presc value until
+ * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
+ * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
+ * on the targeted PLL and reference input clock to the PLL. Lastly,
+ * it sets the register based on these values along with the dividers.
+ * Note 1) There is no value checking for the passed-in divider values
+ * so the caller has to make sure those values are sensible.
+ * 2) Also adjust the NFC divider such that the NFC clock doesn't
+ * exceed NFC_CLK_MAX.
+ * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
+ * 177MHz for higher voltage, this function fixes the max to 133MHz.
+ * 4) This function should not have allowed diag_printf() calls since
+ * the serial driver has been stoped. But leave then here to allow
+ * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
*/
+int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
+{
+ freq *= 1000000;
+
+ switch (clk) {
+ case MXC_ARM_CLK:
+ if (config_core_clk(ref, freq))
+ return -EINVAL;
+ break;
+#if 0
+ case MXC_PER_CLK:
+ if (config_periph_clk(ref, freq))
+ return -EINVAL;
+ break;
+ case MXC_DDR_CLK:
+ if (config_ddr_clk(freq))
+ return -EINVAL;
+ break;
+ case MXC_NFC_CLK:
+ if (config_nfc_clk(freq))
+ return -EINVAL;
+ break;
+#endif
+ default:
+ printf("Warning: Unsupported or invalid clock type: %d\n",
+ clk);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/*
+ * Dump some core clocks.
+ */
+#define print_pll(pll) printf("%-12s %4d.%03d MHz\n", #pll, \
+ decode_pll(pll, MXC_HCLK) / 1000000, \
+ decode_pll(pll, MXC_HCLK) / 1000 % 1000)
+
+#define MXC_IPG_PER_CLK MXC_IPG_PERCLK
+#define print_clk(clk) printf("%-12s %4d.%03d MHz\n", #clk, \
+ mxc_get_clock(MXC_##clk##_CLK) / 1000000, \
+ mxc_get_clock(MXC_##clk##_CLK) / 1000 % 1000)
+
int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- u32 freq;
- freq = decode_pll(PLL_SYS, MXC_HCLK);
- printf("PLL_SYS %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_BUS, MXC_HCLK);
- printf("PLL_BUS %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_USBOTG, MXC_HCLK);
- printf("PLL_OTG %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_ENET, MXC_HCLK);
- printf("PLL_NET %8d MHz\n", freq / 1000000);
+ print_pll(PLL_ARM);
+ print_pll(PLL_BUS);
+ print_pll(PLL_USBOTG);
+ print_pll(PLL_AUDIO);
+ print_pll(PLL_VIDEO);
+ print_pll(PLL_ENET);
+ print_pll(PLL_USB2);
printf("\n");
- printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
- printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
-#ifdef CONFIG_MXC_SPI
- printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
-#endif
- printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
- printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
- printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
- printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
- printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
- printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
- printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
- printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
- printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
+ print_clk(IPG);
+ print_clk(UART);
+ print_clk(CSPI);
+ print_clk(AHB);
+ print_clk(AXI);
+ print_clk(DDR);
+ print_clk(ESDHC);
+ print_clk(ESDHC2);
+ print_clk(ESDHC3);
+ print_clk(ESDHC4);
+ print_clk(EMI_SLOW);
+ print_clk(NFC);
+ print_clk(IPG_PER);
+ print_clk(ARM);
return 0;
}
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/regs-ocotp.h>
#include <asm/arch/clock.h>
+#include <asm/arch/dma.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
+#ifdef CONFIG_VIDEO_IPUV3
+#include <ipu.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TEMPERATURE_MIN -40
+#define TEMPERATURE_HOT 80
+#define TEMPERATURE_MAX 125
+#define REG_VALUE_TO_CEL(ratio, raw) ((raw_n40c - raw) * 100 / ratio - 40)
+
+#define __data __attribute__((section(".data")))
struct scu_regs {
u32 ctrl;
u32 fpga_rev;
};
+#ifdef CONFIG_HW_WATCHDOG
+#define wdog_base ((void *)WDOG1_BASE_ADDR)
+#define WDOG_WCR 0x00
+#define WCR_WDE (1 << 2)
+#define WDOG_WSR 0x02
+
+void hw_watchdog_reset(void)
+{
+ if (readw(wdog_base + WDOG_WCR) & WCR_WDE) {
+ static u16 toggle = 0xaaaa;
+ static int first = 1;
+
+ if (first) {
+ printf("Watchdog active\n");
+ first = 0;
+ }
+ writew(toggle, wdog_base + WDOG_WSR);
+ toggle ^= 0xffff;
+ }
+}
+#endif
+
u32 get_cpu_rev(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
* Possible values are from 0.725V to 1.450V in steps of
* 0.025V (25mV).
*/
-void set_vddsoc(u32 mv)
+static void set_vddsoc(u32 mv)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
u32 val, reg = readl(&anatop->reg_core);
writel(reg, &anatop->reg_core);
}
+static u32 __data thermal_calib;
+
+int read_cpu_temperature(void)
+{
+ unsigned int reg, tmp, i;
+ unsigned int raw_25c, raw_hot, hot_temp, raw_n40c, ratio;
+ int temperature;
+ struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
+ struct mx6_ocotp_regs *const ocotp_regs = (void *)OCOTP_BASE_ADDR;
+
+ if (!thermal_calib) {
+ ocotp_clk_enable();
+ writel(1, &ocotp_regs->hw_ocotp_read_ctrl);
+ thermal_calib = readl(&ocotp_regs->hw_ocotp_ana1);
+ writel(0, &ocotp_regs->hw_ocotp_read_ctrl);
+ ocotp_clk_disable();
+ }
+
+ if (thermal_calib == 0 || thermal_calib == 0xffffffff)
+ return TEMPERATURE_MIN;
+
+ /* Fuse data layout:
+ * [31:20] sensor value @ 25C
+ * [19:8] sensor value of hot
+ * [7:0] hot temperature value */
+ raw_25c = thermal_calib >> 20;
+ raw_hot = (thermal_calib & 0xfff00) >> 8;
+ hot_temp = thermal_calib & 0xff;
+
+ ratio = ((raw_25c - raw_hot) * 100) / (hot_temp - 25);
+ raw_n40c = raw_25c + (13 * ratio) / 20;
+
+ /* now we only using single measure, every time we measure
+ the temperature, we will power on/down the anadig module*/
+ writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
+ writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
+
+ /* write measure freq */
+ reg = readl(&anatop->tempsense1);
+ reg &= ~BM_ANADIG_TEMPSENSE1_MEASURE_FREQ;
+ reg |= 327;
+ writel(reg, &anatop->tempsense1);
+
+ writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
+ writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
+ writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
+
+ tmp = 0;
+ /* read five times of temperature values to get average*/
+ for (i = 0; i < 5; i++) {
+ while ((readl(&anatop->tempsense0) &
+ BM_ANADIG_TEMPSENSE0_FINISHED) == 0)
+ udelay(10000);
+ reg = readl(&anatop->tempsense0);
+ tmp += (reg & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) >>
+ BP_ANADIG_TEMPSENSE0_TEMP_VALUE;
+ writel(BM_ANADIG_TEMPSENSE0_FINISHED,
+ &anatop->tempsense0_clr);
+ }
+
+ tmp = tmp / 5;
+ if (tmp <= raw_n40c)
+ temperature = REG_VALUE_TO_CEL(ratio, tmp);
+ else
+ temperature = TEMPERATURE_MIN;
+
+ /* power down anatop thermal sensor */
+ writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
+ writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
+
+ return temperature;
+}
+
+int check_cpu_temperature(int boot)
+{
+ static int __data max_temp;
+ int boot_limit = TEMPERATURE_HOT;
+ int tmp = read_cpu_temperature();
+
+debug("max_temp[%p]=%d diff=%d\n", &max_temp, max_temp, tmp - max_temp);
+
+ if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) {
+ printf("Temperature: can't get valid data!\n");
+ return tmp;
+ }
+
+ while (tmp >= boot_limit) {
+ if (boot) {
+ printf("CPU is %d C, too hot to boot, waiting...\n",
+ tmp);
+ udelay(5000000);
+ tmp = read_cpu_temperature();
+ boot_limit = TEMPERATURE_HOT - 1;
+ } else {
+ printf("CPU is %d C, too hot, resetting...\n",
+ tmp);
+ udelay(1000000);
+ reset_cpu(0);
+ }
+ }
+
+ if (boot) {
+ printf("Temperature: %d C, calibration data 0x%x\n",
+ tmp, thermal_calib);
+ } else if (tmp > max_temp) {
+ if (tmp > TEMPERATURE_HOT - 5)
+ printf("WARNING: CPU temperature %d C\n", tmp);
+ max_temp = tmp;
+ }
+ return tmp;
+}
+
int arch_cpu_init(void)
{
init_aips();
set_vddsoc(1200); /* Set VDDSOC to 1.2V */
+#ifdef CONFIG_VIDEO_IPUV3
+ gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
+#endif
+#ifdef CONFIG_APBH_DMA
+ /* Timer is required for Initializing APBH DMA */
+ timer_init();
+ mxs_dma_init();
+#endif
return 0;
}
u32 value = readl(&fuse->mac_addr_high);
mac[0] = (value >> 8);
- mac[1] = value ;
+ mac[1] = value;
value = readl(&fuse->mac_addr_low);
- mac[2] = value >> 24 ;
- mac[3] = value >> 16 ;
- mac[4] = value >> 8 ;
- mac[5] = value ;
-
+ mac[2] = value >> 24;
+ mac[3] = value >> 16;
+ mac[4] = value >> 8;
+ mac[5] = value;
}
#endif
{"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
{NULL, 0},
};
+#define RESET_MAX_TIMEOUT 1000000
+#define MXS_BLOCK_SFTRST (1 << 31)
+#define MXS_BLOCK_CLKGATE (1 << 30)
+#include <div64.h>
+
+static const int scale = 1;
+
+int mxs_wait_mask_set(struct mx6_register_32 *mx6_reg, uint32_t mask, unsigned long timeout)
+{
+ unsigned long loops = 0;
+
+ timeout /= scale;
+ if (timeout == 0)
+ timeout++;
+
+ /* Wait for at least one microsecond for the bit mask to be set */
+ while ((readl(&mx6_reg->reg) & mask) != mask) {
+ if ((loops += scale) >= timeout) {
+ printf("MASK %08x in %p not set after %lu ticks\n",
+ mask, &mx6_reg->reg, loops * scale);
+ return 1;
+ }
+ udelay(scale);
+ }
+ if (loops == 0)
+ udelay(1);
+
+ return 0;
+}
+
+int mxs_wait_mask_clr(struct mx6_register_32 *mx6_reg, uint32_t mask, unsigned long timeout)
+{
+ unsigned long loops = 0;
+
+ timeout /= scale;
+ if (timeout == 0)
+ timeout++;
+
+ /* Wait for at least one microsecond for the bit mask to be cleared */
+ while ((readl(&mx6_reg->reg) & mask) != 0) {
+ if ((loops += scale) >= timeout) {
+ printf("MASK %08x in %p not cleared after %lu ticks\n",
+ mask, &mx6_reg->reg, loops * scale);
+ return 1;
+ }
+ udelay(scale);
+ }
+ if (loops == 0)
+ udelay(1);
+
+ return 0;
+}
+
+int mxs_reset_block(struct mx6_register_32 *mx6_reg)
+{
+ /* Clear SFTRST */
+ writel(MXS_BLOCK_SFTRST, &mx6_reg->reg_clr);
+
+ if (mxs_wait_mask_clr(mx6_reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) {
+ printf("TIMEOUT waiting for SFTRST[%p] to clear: %08x\n",
+ &mx6_reg->reg, readl(&mx6_reg->reg));
+ return 1;
+ }
+
+ /* Clear CLKGATE */
+ writel(MXS_BLOCK_CLKGATE, &mx6_reg->reg_clr);
+
+ /* Set SFTRST */
+ writel(MXS_BLOCK_SFTRST, &mx6_reg->reg_set);
+
+ /* Wait for CLKGATE being set */
+ if (mxs_wait_mask_set(mx6_reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) {
+ printf("TIMEOUT waiting for CLKGATE[%p] to set: %08x\n",
+ &mx6_reg->reg, readl(&mx6_reg->reg));
+ return 0;
+ }
+
+ /* Clear SFTRST */
+ writel(MXS_BLOCK_SFTRST, &mx6_reg->reg_clr);
+
+ if (mxs_wait_mask_clr(mx6_reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) {
+ printf("TIMEOUT waiting for SFTRST[%p] to clear: %08x\n",
+ &mx6_reg->reg, readl(&mx6_reg->reg));
+ return 1;
+ }
+
+ /* Clear CLKGATE */
+ writel(MXS_BLOCK_CLKGATE, &mx6_reg->reg_clr);
+
+ if (mxs_wait_mask_clr(mx6_reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) {
+ printf("TIMEOUT waiting for CLKGATE[%p] to clear: %08x\n",
+ &mx6_reg->reg, readl(&mx6_reg->reg));
+ return 1;
+ }
+
+ return 0;
+}
* We would not typically need to save these parameters in regular
* U-Boot. This is needed only in SPL at the moment.
*/
-u32 omap_bootmode = MMCSD_MODE_FAT;
+u32 omap_bootmode __attribute__ ((section(".data"))) = MMCSD_MODE_UNDEFINED;
u32 spl_boot_device(void)
{
- return (u32) (boot_params.omap_bootdevice);
+ return boot_params.omap_bootdevice;
}
u32 spl_boot_mode(void)
*/
ldr r2, =NON_SECURE_SRAM_START
cmp r2, r0
- bgt 1f
+ bge 1f
ldr r2, =NON_SECURE_SRAM_END
cmp r2, r0
blt 1f
str r0, [r1]
#ifdef CONFIG_SPL_BUILD
/* Store the boot device in spl_boot_device */
- ldrb r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device
+ ldrb r2, [r0, #BOOT_DEVICE_OFFSET] @ r2 <- value of boot device
and r2, #BOOT_DEVICE_MASK
- ldr r3, =boot_params
- strb r2, [r3, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r1
+ strb r2, [r1, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r2
/* boot mode is passed only for devices that can raw/fat mode */
cmp r2, #BOOT_DEVICE_XIP
ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode
ldr r3, =omap_bootmode
str r2, [r3]
-#endif
2:
+#endif
ldrb r2, [r0, #CH_FLAGS_OFFSET]
- ldr r3, =boot_params
- strb r2, [r3, #CH_FLAGS_OFFSET]
+ strb r2, [r1, #CH_FLAGS_OFFSET]
1:
bx lr
ENDPROC(save_boot_params)
PUSH {r4-r11, lr} @ save registers - ROM code may pollute
@ our registers
LDR r12, =0x102 @ Set PL310 control register - value in R0
+ smc #0
.word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5
@ call ROM Code API to set control register
POP {r4-r11, pc}
*/
#include <common.h>
+#include <div64.h>
#include <asm/io.h>
+#include <asm/arch/cpu.h>
DECLARE_GLOBAL_DATA_PTR;
* Nothing really to do with interrupts, just starts up a counter.
*/
+#if CONFIG_SYS_PTV > 7
+#error Invalid CONFIG_SYS_PTV value
+#elif CONFIG_SYS_PTV >= 0
#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV))
-#define TIMER_OVERFLOW_VAL 0xffffffff
+#define TCLR_VAL ((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST)
+#else
+#define TIMER_CLOCK V_SCLK
+#define TCLR_VAL (TCLR_AR | TCLR_ST)
+#endif
#define TIMER_LOAD_VAL 0
+#if TIMER_CLOCK < CONFIG_SYS_HZ
+#error TIMER_CLOCK must be > CONFIG_SYS_HZ
+#endif
+
+/*
+ * Start timer so that it will overflow 15 sec after boot,
+ * to catch misbehaving timer code early on!
+*/
+#define TIMER_START (-time_to_tick(15 * CONFIG_SYS_HZ))
+
+static inline unsigned long tick_to_time(unsigned long tick)
+{
+ return tick / (TIMER_CLOCK / CONFIG_SYS_HZ);
+}
+
+static inline unsigned long time_to_tick(unsigned long time)
+{
+ return time * (TIMER_CLOCK / CONFIG_SYS_HZ);
+}
+
+static inline unsigned long us_to_ticks(unsigned long usec)
+{
+ return usec * (TIMER_CLOCK / CONFIG_SYS_HZ / 1000);
+}
+
int timer_init(void)
{
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+ /* Reset the Timer */
+ writel(0x2, &timer_base->tscir);
+
+ /* Wait until the reset is done */
+ while (readl(&timer_base->tiocp_cfg) & 1)
+ ;
+
+ /* preload the counter to make overflow occur early */
+ writel(TIMER_START, &timer_base->tldr);
+ writel(~0, &timer_base->ttgr);
+
/* start the counter ticking up, reload value on overflow */
writel(TIMER_LOAD_VAL, &timer_base->tldr);
/* enable timer */
- writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
- &timer_base->tclr);
-
- /* reset time, capture current incrementer value time */
- gd->arch.lastinc = readl(&timer_base->tcrr) /
- (TIMER_CLOCK / CONFIG_SYS_HZ);
- gd->arch.tbl = 0; /* start "advancing" time stamp from 0 */
-
+ writel(TCLR_VAL, &timer_base->tclr);
+#endif
+#ifndef CONFIG_SPL_BUILD
+ gd->arch.lastinc = -30 * TIMER_CLOCK;
+ gd->arch.tbl = TIMER_START;
+ gd->arch.timer_rate_hz = TIMER_CLOCK;
+#endif
return 0;
}
*/
ulong get_timer(ulong base)
{
- return get_timer_masked() - base;
+ return tick_to_time(get_ticks() - time_to_tick(base));
}
/* delay x useconds */
void __udelay(unsigned long usec)
{
- long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
- unsigned long now, last = readl(&timer_base->tcrr);
-
- while (tmo > 0) {
- now = readl(&timer_base->tcrr);
- if (last > now) /* count up timer overflow */
- tmo -= TIMER_OVERFLOW_VAL - last + now + 1;
- else
- tmo -= now - last;
- last = now;
- }
+ unsigned long start = readl(&timer_base->tcrr);
+ unsigned long ticks = us_to_ticks(usec);
+
+ if (usec == 0)
+ return;
+
+ if (ticks == 0)
+ ticks++;
+
+ while (readl(&timer_base->tcrr) - start < ticks)
+ /* NOP */ ;
}
ulong get_timer_masked(void)
{
/* current tick value */
- ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-
- if (now >= gd->arch.lastinc) { /* normal mode (non roll) */
- /* move stamp fordward with absoulte diff ticks */
- gd->arch.tbl += (now - gd->arch.lastinc);
- } else { /* we have rollover of incrementer */
- gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK /
- CONFIG_SYS_HZ)) - gd->arch.lastinc) + now;
- }
- gd->arch.lastinc = now;
- return gd->arch.tbl;
+ return tick_to_time(get_ticks());
}
/*
*/
unsigned long long get_ticks(void)
{
- return get_timer(0);
+ ulong now = readl(&timer_base->tcrr);
+ ulong inc = now - gd->arch.lastinc;
+
+ gd->arch.tbl += inc;
+ gd->arch.lastinc = now;
+ return gd->arch.tbl;
}
/*
*/
ulong get_tbclk(void)
{
- return CONFIG_SYS_HZ;
+ return gd->arch.timer_rate_hz;
}
.globl _TEXT_BASE
_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
+ .word _start
/*
* These are defined in the board-specific linker script.
mov r6, r2 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _image_copy_end_ofs
/*
* fix .rel.dyn relocations
*/
- ldr r0, _TEXT_BASE /* r0 <- Text base */
+ adr r0, _start /* r0 <- beginning of code */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
+ mov r4, r0
fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ cmp r0, r4
+ blo skipfix
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r7, r1, #0xff
add r1, r1, r9
fixnext:
str r1, [r0]
+skipfix:
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
blo fixloop
--- /dev/null
+/*
+ * Device Tree Source for AM33XX SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "ti,am33xx";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ };
+
+ cpus {
+ cpu@0 {
+ compatible = "arm,cortex-a8";
+ };
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is uses for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap3-mpu";
+ ti,hwmods = "mpu";
+ };
+ };
+
+ /*
+ * XXX: Use a flat representation of the AM33XX interconnect.
+ * The real AM33XX interconnect network is quite complex.Since
+ * that will not bring real advantage to represent that in DT
+ * for the moment, just use a fake OCP bus entry to represent
+ * the whole bus hierarchy.
+ */
+ ocp {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main";
+
+ intc: interrupt-controller@48200000 {
+ compatible = "ti,omap2-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ ti,intc-size = <128>;
+ reg = <0x48200000 0x1000>;
+ };
+
+ gpio0: gpio@44e07000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio1";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio1: gpio@4804C000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio2: gpio@481AC000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio3";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio3: gpio@481AE000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ uart0: serial@44E09000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart1";
+ clock-frequency = <48000000>;
+ };
+
+ uart1: serial@48022000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart2";
+ clock-frequency = <48000000>;
+ };
+
+ uart2: serial@48024000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart3";
+ clock-frequency = <48000000>;
+ };
+
+ uart3: serial@481A6000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ };
+
+ uart4: serial@481A8000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart5";
+ clock-frequency = <48000000>;
+ };
+
+ uart5: serial@481AA000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart6";
+ clock-frequency = <48000000>;
+ };
+
+ i2c0: i2c@44E0B000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c1";
+ };
+
+ i2c1: i2c@4802A000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c2";
+ };
+
+ i2c2: i2c@4819C000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c3";
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&icoll>;
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ saif0 = &saif0;
+ saif1 = &saif1;
+ serial0 = &auart0;
+ serial1 = &auart1;
+ serial2 = &auart2;
+ serial3 = &auart3;
+ serial4 = &auart4;
+ };
+
+ cpus {
+ cpu@0 {
+ compatible = "arm,arm926ejs";
+ };
+ };
+
+ apb@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80000000 0x80000>;
+ ranges;
+
+ apbh@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80000000 0x3c900>;
+ ranges;
+
+ icoll: interrupt-controller@80000000 {
+ compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x80000000 0x2000>;
+ };
+
+ hsadc@80002000 {
+ reg = <0x80002000 0x2000>;
+ interrupts = <13 87>;
+ status = "disabled";
+ };
+
+ dma-apbh@80004000 {
+ compatible = "fsl,imx28-dma-apbh";
+ reg = <0x80004000 0x2000>;
+ };
+
+ perfmon@80006000 {
+ reg = <0x80006000 0x800>;
+ interrupts = <27>;
+ status = "disabled";
+ };
+
+ gpmi-nand@8000c000 {
+ compatible = "fsl,imx28-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
+ reg-names = "gpmi-nand", "bch";
+ interrupts = <88>, <41>;
+ interrupt-names = "gpmi-dma", "bch";
+ fsl,gpmi-dma-channel = <4>;
+ status = "disabled";
+ };
+
+ ssp0: ssp@80010000 {
+ reg = <0x80010000 0x2000>;
+ interrupts = <96 82>;
+ fsl,ssp-dma-channel = <0>;
+ status = "disabled";
+ };
+
+ ssp1: ssp@80012000 {
+ reg = <0x80012000 0x2000>;
+ interrupts = <97 83>;
+ fsl,ssp-dma-channel = <1>;
+ status = "disabled";
+ };
+
+ ssp2: ssp@80014000 {
+ reg = <0x80014000 0x2000>;
+ interrupts = <98 84>;
+ fsl,ssp-dma-channel = <2>;
+ status = "disabled";
+ };
+
+ ssp3: ssp@80016000 {
+ reg = <0x80016000 0x2000>;
+ interrupts = <99 85>;
+ fsl,ssp-dma-channel = <3>;
+ status = "disabled";
+ };
+
+ pinctrl@80018000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx28-pinctrl", "simple-bus";
+ reg = <0x80018000 0x2000>;
+
+ gpio0: gpio@0 {
+ compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ interrupts = <127>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@1 {
+ compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ interrupts = <126>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2 {
+ compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ interrupts = <125>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@3 {
+ compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ interrupts = <124>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@4 {
+ compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ interrupts = <123>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ duart_pins_a: duart@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x3102 /* MX28_PAD_PWM0__DUART_RX */
+ 0x3112 /* MX28_PAD_PWM1__DUART_TX */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ duart_pins_b: duart@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
+ 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ duart_4pins_a: duart-4pins@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
+ 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
+ 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
+ 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ gpmi_pins_a: gpmi-nand@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
+ 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
+ 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
+ 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
+ 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
+ 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
+ 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
+ 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
+ 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
+ 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
+ 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
+ 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
+ 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
+ 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
+ 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ gpmi_status_cfg: gpmi-status-cfg {
+ fsl,pinmux-ids = <
+ 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
+ 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
+ 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
+ >;
+ fsl,drive-strength = <2>;
+ };
+
+ auart0_pins_a: auart0@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
+ 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
+ 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
+ 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ auart0_2pins_a: auart0-2pins@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
+ 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ auart1_pins_a: auart1@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
+ 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
+ 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
+ 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ auart1_2pins_a: auart1-2pins@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
+ 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ auart2_2pins_a: auart2-2pins@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
+ 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ auart3_pins_a: auart3@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
+ 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
+ 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
+ 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ auart3_2pins_a: auart3-2pins@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
+ 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ mac0_pins_a: mac0@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
+ 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
+ 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
+ 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
+ 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
+ 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
+ 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
+ 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
+ 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
+ >;
+ fsl,drive-strength = <1>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <1>;
+ };
+
+ mac1_pins_a: mac1@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
+ 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
+ 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
+ 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
+ 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
+ 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
+ >;
+ fsl,drive-strength = <1>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <1>;
+ };
+
+ mmc0_8bit_pins_a: mmc0-8bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
+ 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
+ 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
+ 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
+ 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
+ 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
+ 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
+ 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
+ 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
+ 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
+ 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
+ >;
+ fsl,drive-strength = <1>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <1>;
+ };
+
+ mmc0_4bit_pins_a: mmc0-4bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
+ 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
+ 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
+ 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
+ 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
+ 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
+ 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
+ >;
+ fsl,drive-strength = <1>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <1>;
+ };
+
+ mmc0_cd_cfg: mmc0-cd-cfg {
+ fsl,pinmux-ids = <
+ 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
+ >;
+ fsl,pull-up = <0>;
+ };
+
+ mmc0_sck_cfg: mmc0-sck-cfg {
+ fsl,pinmux-ids = <
+ 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
+ >;
+ fsl,drive-strength = <2>;
+ fsl,pull-up = <0>;
+ };
+
+ i2c0_pins_a: i2c0@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
+ 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
+ >;
+ fsl,drive-strength = <1>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <1>;
+ };
+
+ i2c0_pins_b: i2c0@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
+ 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
+ >;
+ fsl,drive-strength = <1>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <1>;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
+ 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
+ >;
+ fsl,drive-strength = <1>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <1>;
+ };
+
+ saif0_pins_a: saif0@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
+ 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
+ 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
+ 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
+ >;
+ fsl,drive-strength = <2>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <1>;
+ };
+
+ saif1_pins_a: saif1@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
+ >;
+ fsl,drive-strength = <2>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <1>;
+ };
+
+ pwm0_pins_a: pwm0@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x3100 /* MX28_PAD_PWM0__PWM_0 */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ pwm2_pins_a: pwm2@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x3120 /* MX28_PAD_PWM2__PWM_2 */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ pwm4_pins_a: pwm4@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ lcdif_24bit_pins_a: lcdif-24bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
+ 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
+ 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
+ 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
+ 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
+ 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
+ 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
+ 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
+ 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
+ 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
+ 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
+ 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
+ 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
+ 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
+ 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
+ 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
+ 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
+ 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
+ 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
+ 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
+ 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
+ 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
+ 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
+ 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ can0_pins_a: can0@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
+ 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ can1_pins_a: can1@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
+ 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ spi2_pins_a: spi2@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
+ 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
+ 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
+ 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
+ >;
+ fsl,drive-strength = <1>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <1>;
+ };
+
+ usbphy0_pins_a: usbphy0@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
+ >;
+ fsl,drive-strength = <2>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ usbphy0_pins_b: usbphy0@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
+ >;
+ fsl,drive-strength = <2>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ usbphy1_pins_a: usbphy1@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
+ >;
+ fsl,drive-strength = <2>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+ };
+
+ digctl@8001c000 {
+ reg = <0x8001c000 0x2000>;
+ interrupts = <89>;
+ status = "disabled";
+ };
+
+ etm@80022000 {
+ reg = <0x80022000 0x2000>;
+ status = "disabled";
+ };
+
+ dma-apbx@80024000 {
+ compatible = "fsl,imx28-dma-apbx";
+ reg = <0x80024000 0x2000>;
+ };
+
+ dcp@80028000 {
+ reg = <0x80028000 0x2000>;
+ interrupts = <52 53 54>;
+ status = "disabled";
+ };
+
+ pxp@8002a000 {
+ reg = <0x8002a000 0x2000>;
+ interrupts = <39>;
+ status = "disabled";
+ };
+
+ ocotp@8002c000 {
+ reg = <0x8002c000 0x2000>;
+ status = "disabled";
+ };
+
+ axi-ahb@8002e000 {
+ reg = <0x8002e000 0x2000>;
+ status = "disabled";
+ };
+
+ lcdif@80030000 {
+ compatible = "fsl,imx28-lcdif";
+ reg = <0x80030000 0x2000>;
+ interrupts = <38 86>;
+ status = "disabled";
+ };
+
+ can0: can@80032000 {
+ compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
+ reg = <0x80032000 0x2000>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ can1: can@80034000 {
+ compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
+ reg = <0x80034000 0x2000>;
+ interrupts = <9>;
+ status = "disabled";
+ };
+
+ simdbg@8003c000 {
+ reg = <0x8003c000 0x200>;
+ status = "disabled";
+ };
+
+ simgpmisel@8003c200 {
+ reg = <0x8003c200 0x100>;
+ status = "disabled";
+ };
+
+ simsspsel@8003c300 {
+ reg = <0x8003c300 0x100>;
+ status = "disabled";
+ };
+
+ simmemsel@8003c400 {
+ reg = <0x8003c400 0x100>;
+ status = "disabled";
+ };
+
+ gpiomon@8003c500 {
+ reg = <0x8003c500 0x100>;
+ status = "disabled";
+ };
+
+ simenet@8003c700 {
+ reg = <0x8003c700 0x100>;
+ status = "disabled";
+ };
+
+ armjtag@8003c800 {
+ reg = <0x8003c800 0x100>;
+ status = "disabled";
+ };
+ };
+
+ apbx@80040000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80040000 0x40000>;
+ ranges;
+
+ clkctl@80040000 {
+ reg = <0x80040000 0x2000>;
+ status = "disabled";
+ };
+
+ saif0: saif@80042000 {
+ compatible = "fsl,imx28-saif";
+ reg = <0x80042000 0x2000>;
+ interrupts = <59 80>;
+ fsl,saif-dma-channel = <4>;
+ status = "disabled";
+ };
+
+ power@80044000 {
+ reg = <0x80044000 0x2000>;
+ status = "disabled";
+ };
+
+ saif1: saif@80046000 {
+ compatible = "fsl,imx28-saif";
+ reg = <0x80046000 0x2000>;
+ interrupts = <58 81>;
+ fsl,saif-dma-channel = <5>;
+ status = "disabled";
+ };
+
+ lradc@80050000 {
+ compatible = "fsl,imx28-lradc";
+ reg = <0x80050000 0x2000>;
+ interrupts = <10 14 15 16 17 18 19
+ 20 21 22 23 24 25>;
+ status = "disabled";
+ };
+
+ spdif@80054000 {
+ reg = <0x80054000 0x2000>;
+ interrupts = <45 66>;
+ status = "disabled";
+ };
+
+ rtc@80056000 {
+ compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
+ reg = <0x80056000 0x2000>;
+ interrupts = <29>;
+ };
+
+ i2c0: i2c@80058000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx28-i2c";
+ reg = <0x80058000 0x2000>;
+ interrupts = <111 68>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@8005a000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx28-i2c";
+ reg = <0x8005a000 0x2000>;
+ interrupts = <110 69>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ pwm: pwm@80064000 {
+ compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
+ reg = <0x80064000 0x2000>;
+ #pwm-cells = <2>;
+ fsl,pwm-number = <8>;
+ status = "disabled";
+ };
+
+ timrot@80068000 {
+ reg = <0x80068000 0x2000>;
+ status = "disabled";
+ };
+
+ auart0: serial@8006a000 {
+ compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+ reg = <0x8006a000 0x2000>;
+ interrupts = <112 70 71>;
+ status = "disabled";
+ };
+
+ auart1: serial@8006c000 {
+ compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+ reg = <0x8006c000 0x2000>;
+ interrupts = <113 72 73>;
+ status = "disabled";
+ };
+
+ auart2: serial@8006e000 {
+ compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+ reg = <0x8006e000 0x2000>;
+ interrupts = <114 74 75>;
+ status = "disabled";
+ };
+
+ auart3: serial@80070000 {
+ compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+ reg = <0x80070000 0x2000>;
+ interrupts = <115 76 77>;
+ status = "disabled";
+ };
+
+ auart4: serial@80072000 {
+ compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+ reg = <0x80072000 0x2000>;
+ interrupts = <116 78 79>;
+ status = "disabled";
+ };
+
+ duart: serial@80074000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x80074000 0x1000>;
+ interrupts = <47>;
+ status = "disabled";
+ };
+
+ usbphy0: usbphy@8007c000 {
+ compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
+ reg = <0x8007c000 0x2000>;
+ status = "disabled";
+ };
+
+ usbphy1: usbphy@8007e000 {
+ compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
+ reg = <0x8007e000 0x2000>;
+ status = "disabled";
+ };
+ };
+ };
+
+ ahb@80080000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80080000 0x80000>;
+ ranges;
+
+ usb0: usb@80080000 {
+ compatible = "fsl,imx28-usb", "fsl,imx27-usb";
+ reg = <0x80080000 0x10000>;
+ interrupts = <93>;
+ fsl,usbphy = <&usbphy0>;
+ status = "disabled";
+ };
+
+ usb1: usb@80090000 {
+ compatible = "fsl,imx28-usb", "fsl,imx27-usb";
+ reg = <0x80090000 0x10000>;
+ interrupts = <92>;
+ fsl,usbphy = <&usbphy1>;
+ status = "disabled";
+ };
+
+ dflpt@800c0000 {
+ reg = <0x800c0000 0x10000>;
+ status = "disabled";
+ };
+
+ mac0: ethernet@800f0000 {
+ compatible = "fsl,imx28-fec";
+ reg = <0x800f0000 0x4000>;
+ interrupts = <101>;
+ status = "disabled";
+ };
+
+ mac1: ethernet@800f4000 {
+ compatible = "fsl,imx28-fec";
+ reg = <0x800f4000 0x4000>;
+ interrupts = <102>;
+ status = "disabled";
+ };
+
+ switch@800f8000 {
+ reg = <0x800f8000 0x8000>;
+ status = "disabled";
+ };
+
+ };
+};
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ ethernet0 = &fec0;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ };
+
+ tzic: tz-interrupt-controller@e0000000 {
+ compatible = "fsl,imx51-tzic", "fsl,tzic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xe0000000 0x4000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ckil {
+ compatible = "fsl,imx-ckil", "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ ckih1 {
+ compatible = "fsl,imx-ckih1", "fixed-clock";
+ clock-frequency = <22579200>;
+ };
+
+ ckih2 {
+ compatible = "fsl,imx-ckih2", "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ osc {
+ compatible = "fsl,imx-osc", "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&tzic>;
+ ranges;
+
+ ahb: ahb@40000000 {
+ compatible = "fsl,ahb-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40000000 0x60000000>;
+ ranges;
+
+ ipu@5e000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx-ipuv3";
+ reg = <0x5e000000 0x02000000>;
+ interrupts = <10 11>;
+ status = "disabled";
+ };
+ };
+
+ aips@70000000 { /* AIPS1 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x70000000 0x10000000>;
+ ranges;
+
+ spba@70000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x70000000 0x40000>;
+ ranges;
+
+ esdhc@70004000 { /* ESDHC1 */
+ compatible = "fsl,imx51-esdhc";
+ reg = <0x70004000 0x4000>;
+ interrupts = <1>;
+ status = "disabled";
+ };
+
+ esdhc@70008000 { /* ESDHC2 */
+ compatible = "fsl,imx51-esdhc";
+ reg = <0x70008000 0x4000>;
+ interrupts = <2>;
+ status = "disabled";
+ };
+
+ uart3: serial@7000c000 {
+ compatible = "fsl,imx51-uart", "fsl,imx21-uart";
+ reg = <0x7000c000 0x4000>;
+ interrupts = <33>;
+ status = "disabled";
+ };
+
+ ecspi@70010000 { /* ECSPI1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx51-ecspi";
+ reg = <0x70010000 0x4000>;
+ interrupts = <36>;
+ status = "disabled";
+ };
+
+ ssi2: ssi@70014000 {
+ compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
+ reg = <0x70014000 0x4000>;
+ interrupts = <30>;
+ fsl,fifo-depth = <15>;
+ fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
+ status = "disabled";
+ };
+
+ esdhc@70020000 { /* ESDHC3 */
+ compatible = "fsl,imx51-esdhc";
+ reg = <0x70020000 0x4000>;
+ interrupts = <3>;
+ status = "disabled";
+ };
+
+ esdhc@70024000 { /* ESDHC4 */
+ compatible = "fsl,imx51-esdhc";
+ reg = <0x70024000 0x4000>;
+ interrupts = <4>;
+ status = "disabled";
+ };
+ };
+
+ usb@73f80000 {
+ compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+ reg = <0x73f80000 0x0200>;
+ interrupts = <18>;
+ status = "disabled";
+ };
+
+ usb@73f80200 {
+ compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+ reg = <0x73f80200 0x0200>;
+ interrupts = <14>;
+ status = "disabled";
+ };
+
+ usb@73f80400 {
+ compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+ reg = <0x73f80400 0x0200>;
+ interrupts = <16>;
+ status = "disabled";
+ };
+
+ usb@73f80600 {
+ compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+ reg = <0x73f80600 0x0200>;
+ interrupts = <17>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@73f84000 {
+ compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
+ reg = <0x73f84000 0x4000>;
+ interrupts = <50 51>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@73f88000 {
+ compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
+ reg = <0x73f88000 0x4000>;
+ interrupts = <52 53>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@73f8c000 {
+ compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
+ reg = <0x73f8c000 0x4000>;
+ interrupts = <54 55>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@73f90000 {
+ compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
+ reg = <0x73f90000 0x4000>;
+ interrupts = <56 57>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ keypad@73f94000 {
+ compatible = "fsl,imx-keypad";
+ reg = <0x73f94000 0x4000>;
+ interrupts = <60>;
+ status = "disabled";
+ };
+
+ wdog@73f98000 { /* WDOG1 */
+ compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
+ reg = <0x73f98000 0x4000>;
+ interrupts = <58>;
+ status = "disabled";
+ };
+
+ wdog@73f9c000 { /* WDOG2 */
+ compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
+ reg = <0x73f9c000 0x4000>;
+ interrupts = <59>;
+ status = "disabled";
+ };
+
+ iomuxc@73fa8000 {
+ compatible = "fsl,imx51-iomuxc";
+ reg = <0x73fa8000 0x4000>;
+
+ audmux {
+ pinctrl_audmux_1: audmuxgrp-1 {
+ fsl,pins = <
+ 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
+ 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
+ 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
+ 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
+ >;
+ };
+ };
+
+ fec {
+ pinctrl_fec_1: fecgrp-1 {
+ fsl,pins = <
+ 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
+ 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
+ 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
+ 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
+ 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
+ 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
+ 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
+ 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
+ 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
+ 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
+ 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
+ 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
+ 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
+ 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
+ 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
+ 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
+ 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
+ >;
+ };
+ };
+
+ ecspi1 {
+ pinctrl_ecspi1_1: ecspi1grp-1 {
+ fsl,pins = <
+ 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
+ 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
+ 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
+ >;
+ };
+ };
+
+ esdhc1 {
+ pinctrl_esdhc1_1: esdhc1grp-1 {
+ fsl,pins = <
+ 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
+ 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
+ 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
+ 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
+ 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
+ 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
+ >;
+ };
+ };
+
+ esdhc2 {
+ pinctrl_esdhc2_1: esdhc2grp-1 {
+ fsl,pins = <
+ 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
+ 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
+ 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
+ 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
+ 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
+ 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
+ >;
+ };
+ };
+
+ i2c2 {
+ pinctrl_i2c2_1: i2c2grp-1 {
+ fsl,pins = <
+ 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
+ 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
+ >;
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1_1: uart1grp-1 {
+ fsl,pins = <
+ 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
+ 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
+ 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
+ 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
+ >;
+ };
+ };
+
+ uart2 {
+ pinctrl_uart2_1: uart2grp-1 {
+ fsl,pins = <
+ 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
+ 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
+ >;
+ };
+ };
+
+ uart3 {
+ pinctrl_uart3_1: uart3grp-1 {
+ fsl,pins = <
+ 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
+ 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
+ 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
+ 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
+ >;
+ };
+ };
+ };
+
+ pwm@73fb4000 {
+ compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
+ reg = <0x73fb4000 0x4000>;
+ interrupts = <61>;
+ status = "disabled";
+ };
+
+ pwm@73fb8000 {
+ compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
+ reg = <0x73fb8000 0x4000>;
+ interrupts = <94>;
+ status = "disabled";
+ };
+
+ uart1: serial@73fbc000 {
+ compatible = "fsl,imx51-uart", "fsl,imx21-uart";
+ reg = <0x73fbc000 0x4000>;
+ interrupts = <31>;
+ status = "disabled";
+ };
+
+ uart2: serial@73fc0000 {
+ compatible = "fsl,imx51-uart", "fsl,imx21-uart";
+ reg = <0x73fc0000 0x4000>;
+ interrupts = <32>;
+ status = "disabled";
+ };
+ };
+
+ aips@80000000 { /* AIPS2 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80000000 0x10000000>;
+ ranges;
+
+ ecspi@83fac000 { /* ECSPI2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx51-ecspi";
+ reg = <0x83fac000 0x4000>;
+ interrupts = <37>;
+ status = "disabled";
+ };
+
+ sdma@83fb0000 {
+ compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
+ reg = <0x83fb0000 0x4000>;
+ interrupts = <6>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
+ };
+
+ cspi@83fc0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
+ reg = <0x83fc0000 0x4000>;
+ interrupts = <38>;
+ status = "disabled";
+ };
+
+ i2c@83fc4000 { /* I2C2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
+ reg = <0x83fc4000 0x4000>;
+ interrupts = <63>;
+ status = "disabled";
+ };
+
+ i2c@83fc8000 { /* I2C1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
+ reg = <0x83fc8000 0x4000>;
+ interrupts = <62>;
+ status = "disabled";
+ };
+
+ ssi1: ssi@83fcc000 {
+ compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
+ reg = <0x83fcc000 0x4000>;
+ interrupts = <29>;
+ fsl,fifo-depth = <15>;
+ fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
+ status = "disabled";
+ };
+
+ audmux@83fd0000 {
+ compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
+ reg = <0x83fd0000 0x4000>;
+ ssi-ports = <0 1 2>;
+ ext-ports = <3 4 5 6>;
+ status = "disabled";
+ };
+
+ nand@83fdb000 {
+ compatible = "fsl,imx51-nand";
+ reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ ssi3: ssi@83fe8000 {
+ compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
+ reg = <0x83fe8000 0x4000>;
+ interrupts = <96>;
+ fsl,fifo-depth = <15>;
+ fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
+ status = "disabled";
+ };
+
+ fec0: ethernet@83fec000 {
+ compatible = "fsl,imx51-fec", "fsl,imx27-fec";
+ reg = <0x83fec000 0x4000>;
+ interrupts = <87>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ gpio5 = &gpio5;
+ gpio6 = &gpio6;
+ gpio7 = &gpio7;
+ };
+
+ tzic: tz-interrupt-controller@0fffc000 {
+ compatible = "fsl,imx53-tzic", "fsl,tzic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x0fffc000 0x4000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ckil {
+ compatible = "fsl,imx-ckil", "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ ckih1 {
+ compatible = "fsl,imx-ckih1", "fixed-clock";
+ clock-frequency = <22579200>;
+ };
+
+ ckih2 {
+ compatible = "fsl,imx-ckih2", "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ osc {
+ compatible = "fsl,imx-osc", "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&tzic>;
+ ranges;
+
+ extmc@00000000 {
+ compatible = "fsl,extmc", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x00000000 0x40000000>;
+ ranges;
+
+ sata@10000000 {
+ compatible = "fsl,imx53-sata", "fsl,imx-ahci";
+ reg = <0x10000000 0x00004000>;
+ interrupts = <28>;
+ status = "disabled";
+ };
+
+ ipu@1e000000 {
+ compatible = "fsl,imx-ipuv3";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1e000000 0x02000000>;
+ interrupts = <10 11>;
+ status = "disabled";
+ };
+ };
+
+ aips@50000000 { /* AIPS1 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x50000000 0x10000000>;
+ ranges;
+
+ spba@50000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x50000000 0x40000>;
+ ranges;
+
+ esdhc@50004000 { /* ESDHC1 */
+ compatible = "fsl,imx53-esdhc";
+ reg = <0x50004000 0x4000>;
+ interrupts = <1>;
+ status = "disabled";
+ };
+
+ esdhc@50008000 { /* ESDHC2 */
+ compatible = "fsl,imx53-esdhc";
+ reg = <0x50008000 0x4000>;
+ interrupts = <2>;
+ status = "disabled";
+ };
+
+ uart3: uart@5000c000 {
+ compatible = "fsl,imx53-uart", "fsl,imx21-uart";
+ reg = <0x5000c000 0x4000>;
+ interrupts = <33>;
+ status = "disabled";
+ };
+
+ ecspi@50010000 { /* ECSPI1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
+ reg = <0x50010000 0x4000>;
+ interrupts = <36>;
+ status = "disabled";
+ };
+
+ ssi2: ssi@50014000 {
+ compatible = "fsl,imx-ssi";
+ reg = <0x50014000 0x4000>;
+ interrupts = <30>;
+ status = "disabled";
+ };
+
+ esdhc@50020000 { /* ESDHC3 */
+ compatible = "fsl,imx53-esdhc";
+ reg = <0x50020000 0x4000>;
+ interrupts = <3>;
+ status = "disabled";
+ };
+
+ esdhc@50024000 { /* ESDHC4 */
+ compatible = "fsl,imx53-esdhc";
+ reg = <0x50024000 0x4000>;
+ interrupts = <4>;
+ status = "disabled";
+ };
+ };
+
+ imxotg@53f80000 {
+ compatible = "fsl,imx-otg";
+ reg = <0x53f80000 0x200>;
+ interrupts = <18>;
+ status = "disabled";
+
+ phy-mode = "utmi-wide";
+ host-device-name = "mxc-ehci";
+ host-device-id = <0>;
+ gadget-device-name = "fsl-usb2-udc";
+ };
+
+ imxotg@53f80200 {
+ compatible = "fsl,imx-otg";
+ reg = <0x53f80200 0x200>;
+ interrupts = <14>;
+ status = "disabled";
+
+ phy-mode = "utmi-wide";
+ host-device-name = "mxc-ehci";
+ host-device-id = <1>;
+ };
+
+ mxc-ehci@53f80400 {
+ compatible = "fsl,mxc-ehci";
+ reg = <0x53f80400 0x200>;
+ interrupts = <16>;
+ status = "disabled";
+ };
+
+ mxc-ehci@53f80600 {
+ compatible = "fsl,mxc-ehci";
+ reg = <0x53f80600 0x200>;
+ interrupts = <17>;
+ status = "disabled";
+ };
+
+ imx-usb-phy@53f80800 {
+ compatible = "fsl,imx53-usb-phy", "fsl,imx-usb-phy";
+ reg = <0x53f80800 0x200>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@53f84000 {
+ compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+ reg = <0x53f84000 0x4000>;
+ interrupts = <50 51>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio2: gpio@53f88000 {
+ compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+ reg = <0x53f88000 0x4000>;
+ interrupts = <52 53>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio3: gpio@53f8c000 {
+ compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+ reg = <0x53f8c000 0x4000>;
+ interrupts = <54 55>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio4: gpio@53f90000 {
+ compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+ reg = <0x53f90000 0x4000>;
+ interrupts = <56 57>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ keypad@53f94000 {
+ compatible = "fsl,imx-keypad";
+ reg = <0x53f94000 0x4000>;
+ interrupts = <60>;
+ status = "disabled";
+ };
+
+ wdog@53f98000 { /* WDOG1 */
+ compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
+ reg = <0x53f98000 0x4000>;
+ interrupts = <58>;
+ status = "disabled";
+ };
+
+ wdog@53f9c000 { /* WDOG2 */
+ compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
+ reg = <0x53f9c000 0x4000>;
+ interrupts = <59>;
+ status = "disabled";
+ };
+
+ iomuxc@53fa8000 {
+ compatible = "fsl,imx53-iomuxc";
+ reg = <0x53fa8000 0x4000>;
+
+ audmux {
+ pinctrl_audmux_1: audmuxgrp-1 {
+ fsl,pins = <
+ 10 0x80 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
+ 17 0x80 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
+ 23 0x80 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
+ 30 0x80 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
+ >;
+ };
+ };
+
+ fec {
+ pinctrl_fec_1: fecgrp-1 {
+ fsl,pins = <
+ 820 0x80 /* MX53_PAD_FEC_MDC__FEC_MDC */
+ 779 0x80 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
+ 786 0x80 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
+ 791 0x80 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
+ 796 0x80 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
+ 799 0x80 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
+ 804 0x80 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
+ 808 0x80 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
+ 811 0x80 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
+ 816 0x80 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
+ >;
+ };
+ };
+
+ ecspi1 {
+ pinctrl_ecspi1_1: ecspi1grp-1 {
+ fsl,pins = <
+ 433 0x80 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
+ 439 0x80 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
+ 445 0x80 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
+ >;
+ };
+ };
+
+ esdhc1 {
+ pinctrl_esdhc1_1: esdhc1grp-1 {
+ fsl,pins = <
+ 995 0x1d4 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
+ 1000 0x1d4 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
+ 1010 0x1d4 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
+ 1024 0x1c4 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
+ 1005 0x1d4 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
+ 1018 0x1d4 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
+ >;
+ };
+
+ pinctrl_esdhc1_2: esdhc1grp-2 {
+ fsl,pins = <
+ 995 0x1d4 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
+ 1000 0x1d4 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
+ 1010 0x1d4 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
+ 1024 0x1c4 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
+ 941 0x1d4 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
+ 948 0x1d4 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
+ 955 0x1d4 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
+ 962 0x1d4 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
+ 1005 0x1d4 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
+ 1018 0x1d4 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
+ >;
+ };
+ };
+
+ esdhc2 {
+ pinctrl_esdhc2_1: esdhc2grp-1 {
+ fsl,pins = <
+ 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
+ 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
+ 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
+ 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
+ 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
+ 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
+ >;
+ };
+ };
+
+ esdhc3 {
+ pinctrl_esdhc3_1: esdhc3grp-1 {
+ fsl,pins = <
+ 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
+ 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
+ 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
+ 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
+ 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
+ 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
+ 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
+ 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
+ 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
+ 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
+ >;
+ };
+ };
+
+ i2c1 {
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ 333 0xc0 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
+ 341 0xc0 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
+ >;
+ };
+
+ pinctrl_i2c1_2: i2c1grp-2 {
+ fsl,pins = <
+ 529 0xc0 /* MX53_PAD_EIM_D28__I2C1_SDA */
+ 469 0xc0 /* MX53_PAD_EIM_D21__I2C1_SCL */
+ >;
+ };
+ };
+
+ i2c2 {
+ pinctrl_i2c2_1: i2c2grp-1 {
+ fsl,pins = <
+ 61 0xc0 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
+ 53 0xc0 /* MX53_PAD_KEY_COL3__I2C2_SCL */
+ >;
+ };
+ };
+
+ i2c3 {
+ pinctrl_i2c3_1: i2c3grp-1 {
+ fsl,pins = <
+ 1102 0xc0 /* MX53_PAD_GPIO_6__I2C3_SDA */
+ 1094 0xc0 /* MX53_PAD_GPIO_3__I2C3_SCL */
+ >;
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1_1: uart1grp-1 {
+ fsl,pins = <
+ 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
+ 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
+ >;
+ };
+
+ pinctrl_uart1_2: uart1grp-2 {
+ fsl,pins = <
+ 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
+ 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
+ >;
+ };
+ };
+
+ uart2 {
+ pinctrl_uart2_1: uart2grp-1 {
+ fsl,pins = <
+ 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
+ 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
+ >;
+ };
+ };
+
+ uart3 {
+ pinctrl_uart3_1: uart3grp-1 {
+ fsl,pins = <
+ 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
+ 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
+ 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
+ 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
+ >;
+ };
+ };
+ };
+ pwm@53fb4000 {
+ compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
+ reg = <0x53fb4000 0x4000>;
+ interrupts = <61>;
+ status = "disabled";
+ };
+
+ pwm@53fb8000 {
+ compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
+ reg = <0x53fb8000 0x4000>;
+ interrupts = <94>;
+ status = "disabled";
+ };
+
+ uart1: uart@53fbc000 {
+ compatible = "fsl,imx53-uart", "fsl,imx21-uart";
+ reg = <0x53fbc000 0x4000>;
+ interrupts = <31>;
+ status = "disabled";
+ };
+
+ uart2: uart@53fc0000 {
+ compatible = "fsl,imx53-uart", "fsl,imx21-uart";
+ reg = <0x53fc0000 0x4000>;
+ interrupts = <32>;
+ status = "disabled";
+ };
+
+ can1: flexcan@53fc8000 {
+ compatible = "fsl,p1010-flexcan";
+ reg = <0x53fc8000 0x4000>;
+ interrupts = <82>;
+ status = "disabled";
+ };
+
+ can2: flexcan@53fcc000 {
+ compatible = "fsl,p1010-flexcan";
+ reg = <0x53fcc000 0x4000>;
+ interrupts = <83>;
+ status = "disabled";
+ };
+
+ gpio5: gpio@53fdc000 {
+ compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+ reg = <0x53fdc000 0x4000>;
+ interrupts = <103 104>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio6: gpio@53fe0000 {
+ compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+ reg = <0x53fe0000 0x4000>;
+ interrupts = <105 106>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio7: gpio@53fe4000 {
+ compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+ reg = <0x53fe4000 0x4000>;
+ interrupts = <107 108>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ i2c@53fec000 { /* I2C3 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
+ reg = <0x53fec000 0x4000>;
+ interrupts = <64>;
+ status = "disabled";
+ };
+
+ uart4: uart@53ff0000 {
+ compatible = "fsl,imx53-uart", "fsl,imx21-uart";
+ reg = <0x53ff0000 0x4000>;
+ interrupts = <13>;
+ status = "disabled";
+ };
+ };
+
+ aips@60000000 { /* AIPS2 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x60000000 0x10000000>;
+ ranges;
+
+ uart5: uart@63f90000 {
+ compatible = "fsl,imx53-uart", "fsl,imx21-uart";
+ reg = <0x63f90000 0x4000>;
+ interrupts = <86>;
+ status = "disabled";
+ };
+
+ ecspi@63fac000 { /* ECSPI2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
+ reg = <0x63fac000 0x4000>;
+ interrupts = <37>;
+ status = "disabled";
+ };
+
+ sdma@63fb0000 {
+ compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
+ reg = <0x63fb0000 0x4000>;
+ interrupts = <6>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
+ };
+
+ cspi@63fc0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
+ reg = <0x63fc0000 0x4000>;
+ interrupts = <38>;
+ status = "disabled";
+ };
+
+ i2c@63fc4000 { /* I2C2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
+ reg = <0x63fc4000 0x4000>;
+ interrupts = <63>;
+ status = "disabled";
+ };
+
+ i2c@63fc8000 { /* I2C1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
+ reg = <0x63fc8000 0x4000>;
+ interrupts = <62>;
+ status = "disabled";
+ };
+
+ ssi1: ssi@63fcc000 {
+ compatible = "fsl,imx-ssi";
+ reg = <0x63fcc000 0x4000>;
+ interrupts = <29>;
+ status = "disabled";
+ };
+
+ audmux@63fd0000 {
+ compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
+ reg = <0x63fd0000 0x4000>;
+ status = "disabled";
+ };
+
+ nand@63fdb000 {
+ compatible = "fsl,imx53-nand", "mxc_nand";
+ reg = <0xf7ff0000 0x10000>, <0x63fdb000 0x4000>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ ssi3: ssi@63fe8000 {
+ compatible = "fsl,imx-ssi";
+ reg = <0x63fe8000 0x4000>;
+ interrupts = <96>;
+ status = "disabled";
+ };
+
+ ethernet@63fec000 {
+ compatible = "fsl,imx53-fec", "fsl,imx25-fec";
+ reg = <0x63fec000 0x4000>;
+ interrupts = <87>;
+ status = "disabled";
+ };
+ };
+ };
+};
--- /dev/null
+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/include/ "imx6qdl.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ operating-points = <
+ /* kHz uV */
+ 1200000 1275000
+ 996000 1250000
+ 792000 1150000
+ 396000 950000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clks 104>, <&clks 6>, <&clks 16>,
+ <&clks 17>, <&clks 170>;
+ clock-names = "arm", "pll2_pfd2_396m", "step",
+ "pll1_sw", "pll1_sys";
+ arm-supply = <®_arm>;
+ pu-supply = <®_pu>;
+ soc-supply = <®_soc>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a9";
+ reg = <2>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a9";
+ reg = <3>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ soc {
+ aips-bus@02000000 { /* AIPS1 */
+ spba-bus@02000000 {
+ ecspi5: ecspi@02018000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02018000 0x4000>;
+ interrupts = <0 35 0x04>;
+ clocks = <&clks 116>, <&clks 116>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+ };
+
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,imx6q-iomuxc";
+ reg = <0x020e0000 0x4000>;
+
+ /* shared pinctrl settings */
+ audmux {
+ pinctrl_audmux_1: audmux-1 {
+ fsl,pins = <
+ 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
+ 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
+ 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
+ 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+ >;
+ };
+ };
+
+ ecspi1 {
+ pinctrl_ecspi1_1: ecspi1grp-1 {
+ fsl,pins = <
+ 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
+ 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
+ 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+ >;
+ };
+ };
+
+ enet {
+ pinctrl_enet_1: enetgrp-1 {
+ fsl,pins = <
+ 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
+ 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
+ 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
+ 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+ 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+ 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+ 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+ 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+ 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
+ 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
+ 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+ 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+ 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+ 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+ 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+ 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
+ >;
+ };
+
+ pinctrl_enet_2: enetgrp-2 {
+ fsl,pins = <
+ 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
+ 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
+ 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
+ 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+ 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+ 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+ 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+ 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+ 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
+ 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
+ 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+ 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+ 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+ 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+ 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+ >;
+ };
+ };
+
+ gpmi-nand {
+ pinctrl_gpmi_nand_1: gpmi-nand-1 {
+ fsl,pins = <
+ 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
+ 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
+ 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
+ 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
+ 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
+ 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
+ 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
+ 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
+ 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
+ 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
+ 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
+ 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
+ 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
+ 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
+ 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
+ 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
+ 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
+ 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
+ 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+ >;
+ };
+ };
+
+ i2c1 {
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
+ 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
+ >;
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1_1: uart1grp-1 {
+ fsl,pins = <
+ 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
+ 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
+ >;
+ };
+ pinctrl_uart1_2: uart1-grp-2 {
+ fsl,pins = <
+ 120 0x1b0b1 /* MX6Q_PAD_EIM_D19__UART1_CTS */
+ 128 0x1b0b1 /* MX6Q_PAD_EIM_D20__UART1_RTS */
+ >;
+ };
+
+ pinctrl_uart1_3: uart1grp-3 {
+ fsl,pins = <
+ 1242 0x1b0b1 /* MX6Q_PAD_SD3_DAT7__UART1_TXD */
+ 1250 0x1b0b1 /* MX6Q_PAD_SD3_DAT6__UART1_RXD */
+ >;
+ };
+ pinctrl_uart1_4: uart1-grp-4 {
+ fsl,pins = <
+ 1290 0x1b0b1 /* MX6Q_PAD_SD3_DAT0__UART1_CTS */
+ 1298 0x1b0b1 /* MX6Q_PAD_SD3_DAT1__UART1_RTS */
+ >;
+ };
+ };
+
+ uart2 {
+ pinctrl_uart2_1: uart2grp-1 {
+ fsl,pins = <
+ 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
+ 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
+ >;
+ };
+ pinctrl_uart2_2: uart2grp-2 {
+ fsl,pins = <
+ 199 0x1b0b1 /* MX6Q_PAD_EIM_D28__UART2_CTS */
+ 206 0x1b0b1 /* MX6Q_PAD_EIM_D29__UART2_RTS */
+ >;
+ };
+
+ pinctrl_uart2_3: uart2grp-3 {
+ fsl,pins = <
+ 1258 0x1b0b1 /* MX6Q_PAD_SD3_DAT5__UART2_TXD */
+ 1266 0x1b0b1 /* MX6Q_PAD_SD3_DAT6__UART2_RXD */
+ >;
+ };
+ pinctrl_uart2_4: uart2grp-4 {
+ fsl,pins = <
+ 1274 0x1b0b1 /* MX6Q_PAD_SD3_CMD__UART2_CTS */
+ 1282 0x1b0b1 /* MX6Q_PAD_SD3_CLK__UART2_RTS */
+ >;
+ };
+
+ pinctrl_uart2_5: uart2grp-5 {
+ fsl,pins = <
+ 1518 0x1b0b1 /* MX6Q_PAD_SD4_DAT7__UART2_TXD */
+ 1494 0x1b0b1 /* MX6Q_PAD_SD4_DAT4__UART2_RXD */
+ >;
+ };
+ pinctrl_uart2_6: uart2grp-6 {
+ fsl,pins = <
+ 1510 0x1b0b1 /* MX6Q_PAD_SD4_DAT6__UART2_CTS */
+ 1502 0x1b0b1 /* MX6Q_PAD_SD4_DAT5__UART2_RTS */
+ >;
+ };
+
+ pinctrl_uart2_7: uart2grp-7 {
+ fsl,pins = <
+ 1019 0x1b0b1 /* MX6Q_PAD_GPIO_7__UART2_TXD */
+ 1027 0x1b0b1 /* MX6Q_PAD_GPIO_8__UART2_RXD */
+ >;
+ };
+ };
+
+ uart3 {
+ pinctrl_uart3_1: uart3grp-1 {
+ fsl,pins = <
+ 165 0x1b0b1 /* MX6Q_PAD_EIM_D24__UART3_TXD */
+ 173 0x1b0b1 /* MX6Q_PAD_EIM_D25__UART3_RXD */
+ >;
+ };
+ pinctrl_uart3_2: uart3grp-2 {
+ fsl,pins = <
+ 149 0x1b0b1 /* MX6Q_PAD_EIM_D23__UART3_CTS */
+ 157 0x1b0b1 /* MX6Q_PAD_EIM_EB3__UART3_RTS */
+ >;
+ };
+
+ pinctrl_uart3_3: uart3grp-3 {
+ fsl,pins = <
+ 1388 0x1b0b1 /* MX6Q_PAD_SD4_CMD__UART3_TXD */
+ 1394 0x1b0b1 /* MX6Q_PAD_SD4_CLK__UART3_RXD */
+ >;
+ };
+ pinctrl_uart3_4: uart3grp-4 {
+ fsl,pins = <
+ 1313 0x1b0b1 /* MX6Q_PAD_SD3_DAT3__UART3_CTS */
+ 1321 0x1b0b1 /* MX6Q_PAD_SD3_RST__UART3_RTS */
+ >;
+ };
+
+ pinctrl_uart3_5: uart3grp-5 {
+ fsl,pins = <
+ 214 0x1b0b1 /* MX6Q_PAD_EIM_D30__UART3_CTS */
+ 222 0x1b0b1 /* MX6Q_PAD_EIM_D31__UART3_RTS */
+ >;
+ };
+ };
+
+ uart4 {
+ pinctrl_uart4_1: uart4grp-1 {
+ fsl,pins = <
+ 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
+ 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
+ >;
+ };
+ };
+
+ usbotg {
+ pinctrl_usbotg_1: usbotggrp-1 {
+ fsl,pins = <
+ 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
+ >;
+ };
+ };
+
+ usdhc1 {
+ pinctrl_usdhc1_1: usdhc1grp-1 {
+ fsl,pins = <
+ 1548 0x17059 /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */
+ 1562 0x10059 /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */
+ 1532 0x17059 /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */
+ 1524 0x17059 /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */
+ 1554 0x17059 /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */
+ 1540 0x17059 /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */
+ 1398 0x17059 /* MX6Q_PAD_NANDF_D0__USDHC1_DAT4 */
+ 1406 0x17059 /* MX6Q_PAD_NANDF_D1__USDHC1_DAT5 */
+ 1414 0x17059 /* MX6Q_PAD_NANDF_D2__USDHC1_DAT6 */
+ 1422 0x17059 /* MX6Q_PAD_NANDF_D3__USDHC1_DAT7 */
+ >;
+ };
+
+ pinctrl_usdhc1_2: usdhc1grp-2 {
+ fsl,pins = <
+ 1548 0x17059 /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */
+ 1562 0x10059 /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */
+ 1532 0x17059 /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */
+ 1524 0x17059 /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */
+ 1554 0x17059 /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */
+ 1540 0x17059 /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */
+ >;
+ };
+ };
+
+ usdhc2 {
+ pinctrl_usdhc2_1: usdhc2grp-1 {
+ fsl,pins = <
+ 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
+ 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
+ 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
+ 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
+ 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
+ 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
+ 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
+ 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
+ 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
+ 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
+ >;
+ };
+
+ pinctrl_usdhc2_2: usdhc2grp-2 {
+ fsl,pins = <
+ 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
+ 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
+ 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
+ 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
+ 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
+ 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
+ >;
+ };
+ };
+
+ usdhc3 {
+ pinctrl_usdhc3_1: usdhc3grp-1 {
+ fsl,pins = <
+ 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
+ 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
+ 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
+ 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
+ 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
+ 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
+ 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
+ 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
+ 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
+ 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+ >;
+ };
+
+ pinctrl_usdhc3_2: usdhc3grp-2 {
+ fsl,pins = <
+ 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
+ 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
+ 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
+ 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
+ 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
+ 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
+ >;
+ };
+ };
+
+ usdhc4 {
+ pinctrl_usdhc4_1: usdhc4grp-1 {
+ fsl,pins = <
+ 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+ 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
+ 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+ 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+ 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+ 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+ 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
+ 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
+ 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
+ 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+ >;
+ };
+
+ pinctrl_usdhc4_2: usdhc4grp-2 {
+ fsl,pins = <
+ 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+ 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
+ 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+ 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+ 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+ 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+ >;
+ };
+ };
+ };
+ };
+
+ ipu2: ipu@02800000 {
+ #crtc-cells = <1>;
+ compatible = "fsl,imx6q-ipu";
+ reg = <0x02800000 0x400000>;
+ interrupts = <0 8 0x4 0 7 0x4>;
+ clocks = <&clks 133>, <&clks 134>, <&clks 137>;
+ clock-names = "bus", "di0", "di1";
+ };
+ };
+};
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
-#include <ipu_pixfmt.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
}
}
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
#if defined(CONFIG_MX53)
#define MEMCTL_BASE ESDCTL_BASE_ADDR;
#else
return get_periph_clk() / (ahb_podf + 1);
}
-
-#if defined(CONFIG_VIDEO_IPUV3)
-void arch_preboot_os(void)
-{
- /* disable video before launching O/S */
- ipuv3_fb_shutdown();
-}
-#endif
if (sel_input_ofs)
__raw_writel(sel_input, base + sel_input_ofs);
- if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
+ if ((pad & PAD_CTRL_VALID) && pad_ctrl_ofs)
__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
return 0;
int ret;
for (i = 0; i < count; i++) {
+#if 0
+ u32 mux_ctrl_ofs = (*p & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
+ u32 mux_mode = (*p & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+ u32 sel_input_ofs =
+ (*p & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
+ u32 sel_input =
+ (*p & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
+ u32 pad_ctrl_ofs =
+ (*p & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
+ u32 pad_ctrl = (*p & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+
+ printf("PAD[%2d]=%016llx mux[%03x]=%02x pad[%03x]=%05x%c inp[%03x]=%d\n",
+ i, *p, mux_ctrl_ofs, mux_mode, pad_ctrl_ofs, pad_ctrl,
+ *p & PAD_CTRL_VALID ? ' ' : '!', sel_input_ofs, sel_input);
+#endif
ret = imx_iomux_v3_setup_pad(*p);
if (ret)
return ret;
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#define DEBUG_TIMER_WRAP
+
/* General purpose timers registers */
struct mxc_gpt {
unsigned int control;
/* General purpose timers bitfields */
#define GPTCR_SWR (1 << 15) /* Software reset */
#define GPTCR_FRR (1 << 9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
+#define GPTCR_CLKSOURCE_IPG (1 << 6) /* Clock source */
+#define GPTCR_CLKSOURCE_CKIH (2 << 6)
+#define GPTCR_CLKSOURCE_32kHz (4 << 6)
+#ifdef CONFIG_MX6Q
+#define GPTCR_CLKSOURCE_OSC_DIV_8 (5 << 6)
+#define GPTCR_CLKSOURCE_OSC (7 << 6)
+#else
+#define GPTCR_CLKSOURCE_OSC (5 << 6)
+#endif
+#define GPTCR_CLKSOURCE_MASK (7 << 6)
#define GPTCR_TEN 1 /* Timer enable */
+#if 1
+#define GPT_CLKSOURCE GPTCR_CLKSOURCE_OSC
+#define GPT_REFCLK 24000000
+#define GPT_PRESCALER 24
+#else
+#define GPT_CLKSOURCE GPTCR_CLKSOURCE_32kHz
+#define GPT_REFCLK 32768
+#define GPT_PRESCALER 1
+#endif
+#define GPT_CLK (GPT_REFCLK / GPT_PRESCALER)
+
+#ifdef DEBUG_TIMER_WRAP
+/*
+ * Let the timer wrap 30 seconds after start to catch misbehaving
+ * timer related code early
+ */
+#define TIMER_START (-time_to_tick(30 * CONFIG_SYS_HZ))
+#else
+#define TIMER_START 0UL
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
-#define timestamp (gd->arch.tbl)
-#define lastinc (gd->arch.lastinc)
+static inline unsigned long tick_to_time(unsigned long tick)
+{
+ unsigned long long t = (unsigned long long)tick * CONFIG_SYS_HZ;
+ do_div(t, GPT_CLK);
+ return t;
+}
-static inline unsigned long long tick_to_time(unsigned long long tick)
+static inline unsigned long time_to_tick(unsigned long time)
{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, MXC_CLK32);
+ unsigned long long ticks = (unsigned long long)time;
- return tick;
+ ticks *= GPT_CLK;
+ do_div(ticks, CONFIG_SYS_HZ);
+ return ticks;
}
-static inline unsigned long long us_to_tick(unsigned long long usec)
+static inline unsigned long us_to_tick(unsigned long usec)
{
- usec = usec * MXC_CLK32 + 999999;
- do_div(usec, 1000000);
+ unsigned long long ticks = (unsigned long long)usec;
- return usec;
+ ticks *= GPT_CLK;
+ do_div(ticks, 1000 * CONFIG_SYS_HZ);
+ return ticks;
}
int timer_init(void)
for (i = 0; i < 100; i++)
__raw_writel(0, &cur_gpt->control);
- __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
+ __raw_writel(GPT_PRESCALER - 1, &cur_gpt->prescaler);
/* Freerun Mode, PERCLK1 input */
i = __raw_readl(&cur_gpt->control);
- __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
+ i &= ~GPTCR_CLKSOURCE_MASK;
+ __raw_writel(i | GPT_CLKSOURCE | GPTCR_TEN, &cur_gpt->control);
val = __raw_readl(&cur_gpt->counter);
- lastinc = val / (MXC_CLK32 / CONFIG_SYS_HZ);
- timestamp = 0;
+ gd->arch.lastinc = val;
+ gd->arch.tbu = 0;
+ gd->arch.tbl = TIMER_START;
+ gd->arch.timer_rate_hz = GPT_CLK;
return 0;
}
unsigned long long get_ticks(void)
{
ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */
+ ulong inc = now - gd->arch.lastinc;
- if (now >= lastinc) {
- /*
- * normal mode (non roll)
- * move stamp forward with absolut diff ticks
- */
- timestamp += (now - lastinc);
- } else {
- /* we have rollover of incrementer */
- timestamp += (0xFFFFFFFF - lastinc) + now;
- }
- lastinc = now;
- return timestamp;
+ gd->arch.tbl += inc;
+ gd->arch.lastinc = now;
+ return gd->arch.tbl;
}
ulong get_timer_masked(void)
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
+ /*
+ * LW: get_ticks() returns a long long with the top 32 bits always ZERO!
+ * Thus the calculation above is not true.
+ * A 64bit timer value would only make sense if it was
+ * consistently used throughout the code. Thus also the parameter
+ * to get_timer() and its return value would need to be 64bit wide!
+ */
return tick_to_time(get_ticks());
}
ulong get_timer(ulong base)
{
- return get_timer_masked() - base;
+ return tick_to_time(get_ticks() - time_to_tick(base));
}
+#include <asm/gpio.h>
+
/* delay x useconds AND preserve advance timstamp value */
void __udelay(unsigned long usec)
{
- unsigned long long tmp;
- ulong tmo;
+ unsigned long start = __raw_readl(&cur_gpt->counter);
+ unsigned long ticks;
+
+ if (usec == 0)
+ return;
- tmo = us_to_tick(usec);
- tmp = get_ticks() + tmo; /* get current timestamp */
+ ticks = us_to_tick(usec);
+ if (ticks == 0)
+ ticks++;
- while (get_ticks() < tmp) /* loop till event */
- /*NOP*/;
+ while (__raw_readl(&cur_gpt->counter) - start < ticks)
+ /* loop till event */;
}
/*
*/
ulong get_tbclk(void)
{
- return MXC_CLK32;
+ return gd->arch.timer_rate_hz;
}
#define OSC (V_OSCK/1000000)
+#ifndef CONFIG_SYS_MPU_CLK
/* MAIN PLL Fdll = 550 MHZ, */
#define MPUPLL_M 550
-#define MPUPLL_N (OSC-1)
+#else
+#define MPUPLL_M CONFIG_SYS_MPU_CLK
+#endif
+#define MPUPLL_N (OSC - 1)
#define MPUPLL_M2 1
/* Core PLL Fdll = 1 GHZ, */
#define COREPLL_M 1000
-#define COREPLL_N (OSC-1)
+#define COREPLL_N (OSC - 1)
#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
* For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
*/
#define PERPLL_M 960
-#define PERPLL_N (OSC-1)
+#define PERPLL_N (OSC - 1)
#define PERPLL_M2 5
/* DDR Freq is 266 MHZ for now */
/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
+#ifndef CONFIG_SYS_DDR_CLK
#define DDRPLL_M 266
-#define DDRPLL_N (OSC-1)
+#else
+#define DDRPLL_M CONFIG_SYS_DDR_CLK
+#endif
+#define DDRPLL_N (OSC - 1)
#define DDRPLL_M2 1
+#define DISPPLL_M 200
+#define DISPPLL_N (OSC - 1)
+#define DISPPLL_M2 1
+
extern void pll_init(void);
extern void enable_emif_clocks(void);
#include <asm/arch/hardware.h>
-#define BIT(x) (1 << x)
-#define CL_BIT(x) (0 << x)
+#define BIT(x) (1 << (x))
+#define CL_BIT(x) (0 << (x))
/* Timer register bits */
#define TCLR_ST BIT(0) /* Start=1 Stop=0 */
#define TCLR_AR BIT(1) /* Auto reload */
#define TCLR_PRE BIT(5) /* Pre-scaler enable */
-#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
+#define TCLR_PTV_SHIFT 2 /* Pre-scaler shift value */
#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
/* device type */
#define GP_DEVICE 0x3
/* cpu-id for AM33XX family */
-#define AM335X 0xB944
+#define AM335X_ID 0xB944
#define DEVICE_ID 0x44E10600
/* This gives the status of the boot mode pins on the evm */
-#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
- | BIT(3) | BIT(4))
+#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2) | \
+ BIT(3) | BIT(4))
/* Reset control */
-#ifdef CONFIG_AM33XX
#define PRM_RSTCTRL 0x44E00F00
#define PRM_RSTST 0x44E00F08
-#endif
#define PRM_RSTCTRL_RESET 0x01
#define PRM_RSTST_WARM_RESET_MASK 0x232
unsigned int idlestdpllddr; /* offset 0x34 */
unsigned int resv5[2];
unsigned int clkseldpllddr; /* offset 0x40 */
- unsigned int resv6[4];
+ unsigned int autoidledplldisp; /* offset 0x44 */
+ unsigned int idlestdplldisp; /* offset 0x48 */
+ unsigned int resv6[2];
unsigned int clkseldplldisp; /* offset 0x54 */
unsigned int resv7[1];
unsigned int idlestdpllcore; /* offset 0x5c */
unsigned int resv11[1];
unsigned int wkup_uart0ctrl; /* offset 0xB4 */
unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
- unsigned int resv12[7];
+ unsigned int resv12[6];
+ unsigned int wdtimer1ctrl;
unsigned int divm6dpllcore; /* offset 0xD8 */
};
unsigned int resv1;
unsigned int cpgmac0clkctrl; /* offset 0x14 */
unsigned int lcdclkctrl; /* offset 0x18 */
- unsigned int usb0clkctrl; /* offset 0x1C */
+ unsigned int usb0clkctrl; /* offset 0x1c */
unsigned int resv2;
unsigned int tptc0clkctrl; /* offset 0x24 */
unsigned int emifclkctrl; /* offset 0x28 */
unsigned int resv4[4];
unsigned int miisel; /* offset 0x50 */
};
+
+void init_timer(void);
+
+#define clk_get_rate(c,p) \
+ __clk_get_rate(readl(&(c)->clkseldpll##p), \
+ readl(&(c)->divm2dpll##p))
+
+unsigned long __clk_get_rate(u32 m_n, u32 div_m2);
+
+unsigned long lcdc_clk_rate(void);
+
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
+/* Ethernet MAC ID from EFuse */
+#define MAC_ID0_LO (CTRL_BASE + 0x630)
+#define MAC_ID0_HI (CTRL_BASE + 0x634)
+#define MAC_ID1_LO (CTRL_BASE + 0x638)
+#define MAC_ID1_HI (CTRL_BASE + 0x63c)
+#define MAC_MII_SEL (CTRL_BASE + 0x650)
+
#endif /* _AM33XX_CPU_H */
--- /dev/null
+/*
+ * Porting to u-boot:
+ *
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2008-2009 MontaVista Software Inc.
+ * Copyright (C) 2008-2009 Texas Instruments Inc
+ *
+ * Based on the LCD driver for TI Avalanche processors written by
+ * Ajay Singh and Shalom Hai.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef DA8XX_FB_H
+#define DA8XX_FB_H
+
+enum panel_type {
+ QVGA = 0
+};
+
+enum panel_shade {
+ MONOCHROME = 0,
+ COLOR_ACTIVE,
+ COLOR_PASSIVE,
+};
+
+enum raster_load_mode {
+ LOAD_DATA = 1,
+ LOAD_PALETTE,
+};
+
+struct display_panel {
+ enum panel_type panel_type; /* QVGA */
+ int max_bpp;
+ int min_bpp;
+ enum panel_shade panel_shade;
+};
+
+struct da8xx_panel {
+ const char name[25]; /* Full name <vendor>_<model> */
+ unsigned short width;
+ unsigned short height;
+ int hfp; /* Horizontal front porch */
+ int hbp; /* Horizontal back porch */
+ int hsw; /* Horizontal Sync Pulse Width */
+ int vfp; /* Vertical front porch */
+ int vbp; /* Vertical back porch */
+ int vsw; /* Vertical Sync Pulse Width */
+ unsigned int pxl_clk; /* Pixel clock */
+ unsigned char invert_pxl_clk; /* Invert Pixel clock */
+};
+
+struct da8xx_lcdc_platform_data {
+ const char manu_name[10];
+ void *controller_data;
+ const char type[25];
+ void (*panel_power_ctrl)(int);
+};
+
+struct lcd_ctrl_config {
+ const struct display_panel *p_disp_panel;
+
+ /* AC Bias Pin Frequency */
+ int ac_bias;
+
+ /* AC Bias Pin Transitions per Interrupt */
+ int ac_bias_intrpt;
+
+ /* DMA burst size */
+ int dma_burst_sz;
+
+ /* Bits per pixel */
+ int bpp;
+
+ /* FIFO DMA Request Delay */
+ int fdd;
+
+ /* TFT Alternative Signal Mapping (Only for active) */
+ unsigned char tft_alt_mode;
+
+ /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
+ unsigned char stn_565_mode;
+
+ /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
+ unsigned char mono_8bit_mode;
+
+ /* Invert line clock */
+ unsigned char invert_line_clock;
+
+ /* Invert frame clock */
+ unsigned char invert_frm_clock;
+
+ /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
+ unsigned char sync_edge;
+
+ /* Horizontal and Vertical Sync: Control: 0=ignore */
+ unsigned char sync_ctrl;
+
+ /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
+ unsigned char raster_order;
+};
+
+struct lcd_sync_arg {
+ int back_porch;
+ int front_porch;
+ int pulse_width;
+};
+
+void da8xx_fb_disable(void);
+void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel);
+
+#endif /* ifndef DA8XX_FB_H */
--- /dev/null
+/*
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on ddr_defs.h Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ *
+ */
+
+#ifndef _DDR3_DEFS_H
+#define _DDR3_DEFS_H
+
+#include <asm/arch/hardware.h>
+
+
+#endif /* _DDR_DEFS_H */
+
#define AM33XX_GPIO2_BASE 0x481AC000
#define AM33XX_GPIO3_BASE 0x481AE000
+#define AM33XX_GPIO_NR(bank, pin) (((bank) << 5) | (pin))
+
#endif /* _GPIO_AM33xx_H */
#include <asm/arch/omap.h>
/* Module base addresses */
+#define LOW_LEVEL_SRAM_STACK 0x4030B7FC
#define UART0_BASE 0x44E09000
/* DM Timer base addresses */
#define DM_TIMER6_BASE 0x48048000
#define DM_TIMER7_BASE 0x4804A000
-/* GPIO Base address */
-#define GPIO0_BASE 0x48032000
-#define GPIO1_BASE 0x4804C000
-#define GPIO2_BASE 0x481AC000
-
/* BCH Error Location Module */
#define ELM_BASE 0x48080000
/*
* OMAP HSMMC register definitions
*/
-#define OMAP_HSMMC1_BASE 0x48060100
-#define OMAP_HSMMC2_BASE 0x481D8100
+#define OMAP_HSMMC1_BASE 0x48060000
+#define OMAP_HSMMC2_BASE 0x481D8000
+#define OMAP_HSMMC3_BASE 0x47810000
typedef struct hsmmc {
- unsigned char res1[0x10];
- unsigned int sysconfig; /* 0x10 */
- unsigned int sysstatus; /* 0x14 */
- unsigned char res2[0x14];
- unsigned int con; /* 0x2C */
- unsigned char res3[0xD4];
- unsigned int blk; /* 0x104 */
- unsigned int arg; /* 0x108 */
- unsigned int cmd; /* 0x10C */
- unsigned int rsp10; /* 0x110 */
- unsigned int rsp32; /* 0x114 */
- unsigned int rsp54; /* 0x118 */
- unsigned int rsp76; /* 0x11C */
- unsigned int data; /* 0x120 */
- unsigned int pstate; /* 0x124 */
- unsigned int hctl; /* 0x128 */
- unsigned int sysctl; /* 0x12C */
- unsigned int stat; /* 0x130 */
- unsigned int ie; /* 0x134 */
- unsigned char res4[0x8];
- unsigned int capa; /* 0x140 */
+ unsigned int res1[0x110 / 4];
+ unsigned int sysconfig; /* 0x110 */
+ unsigned int sysstatus; /* 0x114 */
+ unsigned int res2[0x14 / 4];
+ unsigned int con; /* 0x12C */
+ unsigned int res3[0xD4 / 4];
+ unsigned int blk; /* 0x204 */
+ unsigned int arg; /* 0x208 */
+ unsigned int cmd; /* 0x20C */
+ unsigned int rsp10; /* 0x210 */
+ unsigned int rsp32; /* 0x214 */
+ unsigned int rsp54; /* 0x218 */
+ unsigned int rsp76; /* 0x21C */
+ unsigned int data; /* 0x220 */
+ unsigned int pstate; /* 0x224 */
+ unsigned int hctl; /* 0x228 */
+ unsigned int sysctl; /* 0x22C */
+ unsigned int stat; /* 0x230 */
+ unsigned int ie; /* 0x234 */
+ unsigned int res4[2];
+ unsigned int capa; /* 0x240 */
} hsmmc_t;
/*
#define BCE_DISABLE (0x0 << 1)
#define BCE_ENABLE (0x1 << 1)
#define ACEN_DISABLE (0x0 << 2)
-#define DDIR_OFFSET (4)
+#define DDIR_OFFSET 4
#define DDIR_MASK (0x1 << 4)
#define DDIR_WRITE (0x0 << 4)
#define DDIR_READ (0x1 << 4)
#define MSBS_SGLEBLK (0x0 << 5)
#define MSBS_MULTIBLK (0x1 << 5)
-#define RSP_TYPE_OFFSET (16)
+#define RSP_TYPE_OFFSET 16
#define RSP_TYPE_MASK (0x3 << 16)
#define RSP_TYPE_NORSP (0x0 << 16)
#define RSP_TYPE_LGHT136 (0x1 << 16)
#define CCCE_CHECK (0x1 << 19)
#define CICE_NOCHECK (0x0 << 20)
#define CICE_CHECK (0x1 << 20)
-#define DP_OFFSET (21)
+#define DP_OFFSET 21
#define DP_MASK (0x1 << 21)
#define DP_NO_DATA (0x0 << 21)
#define DP_DATA (0x1 << 21)
#define CMD_TYPE_NORMAL (0x0 << 22)
-#define INDEX_OFFSET (24)
+#define INDEX_OFFSET 24
#define INDEX_MASK (0x3f << 24)
-#define INDEX(i) (i << 24)
+#define INDEX(i) ((i) << 24)
#define DATI_MASK (0x1 << 1)
#define CMDI_MASK (0x1 << 0)
#define DTW_1_BITMODE (0x0 << 1)
#define DTW_4_BITMODE (0x1 << 1)
-#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
+#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
#define SDBP_PWROFF (0x0 << 8)
#define SDBP_PWRON (0x1 << 8)
#define SDVS_1V8 (0x5 << 9)
#define CEN_MASK (0x1 << 2)
#define CEN_DISABLE (0x0 << 2)
#define CEN_ENABLE (0x1 << 2)
-#define CLKD_OFFSET (6)
+#define CLKD_OFFSET 6
#define CLKD_MASK (0x3FF << 6)
#define DTO_MASK (0xF << 16)
#define DTO_15THDTO (0xE << 16)
#define MMC_CLOCK_REFERENCE 96 /* MHz */
#define mmc_reg_out(addr, mask, val)\
- writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+ writel((readl(addr) & (~(mask))) | ((val) & (mask)), addr)
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
--- /dev/null
+/*
+ * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Derived from work done by Rohit Choraria <rohitkc@ti.com> for omap3
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_OMAP_GPMC_H
+#define __ASM_ARCH_OMAP_GPMC_H
+
+#include <linux/mtd/nand.h>
+
+#define GPMC_BUF_EMPTY 0
+#define GPMC_BUF_FULL 1
+
+#define ECCCLEAR (0x1 << 8)
+#define ECCRESULTREG1 (0x1 << 0)
+#define ECCSIZE512BYTE 0xFF
+#define ECCSIZE1 (ECCSIZE512BYTE << 22)
+#define ECCSIZE0 (ECCSIZE512BYTE << 12)
+#define ECCSIZE0SEL (0x000 << 0)
+
+/* Generic ECC Layouts */
+/* Large Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT { \
+ .eccbytes = 4 * 13, \
+ .eccpos = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, \
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, \
+ 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, \
+ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, \
+ }, \
+ .oobfree = { \
+ { .offset = 58, .length = 6, }, \
+ }, \
+}
+#endif
+
+/* Large Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT { \
+ .eccbytes = 4 * 3, \
+ .eccpos = { 2, 3, 4, \
+ 5, 6, 7, \
+ 8, 9, 10, \
+ 11, 12, 13, \
+ }, \
+ .oobfree = { \
+ { .offset = 14, .length = 50, }, \
+ }, \
+}
+#endif
+
+/* NAND device layout in synch with the kernel */
+#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT_KERNEL { \
+ .eccbytes = 4 * 3, \
+ .eccpos = { 40, 41, 42, \
+ 43, 44, 45, \
+ 46, 47, 48, \
+ 49, 50, 51, \
+ }, \
+ .oobfree = { \
+ { .offset = 2, .length = 38, }, \
+ }, \
+}
+#endif
+
+/* Small Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT { \
+ .eccbytes = 3, \
+ .eccpos = { 1, 2, 3, }, \
+ .oobfree = { \
+ { .offset = 4, .length = 12, }, \
+ }, \
+}
+#endif
+
+/* Small Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT { \
+ .eccbytes = 3, \
+ .eccpos = { 2, 3, 4, }, \
+ .oobfree = { \
+ { .offset = 58, .length = 6, }, \
+ }, \
+}
+#endif
+
+#define GPMC_NAND_HW_BCH4_ECC_LAYOUT { \
+ .eccbytes = 4 * 8, \
+ .eccpos = { 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ }, \
+ .oobfree = { \
+ { .offset = 34, .length = 30, }, \
+ }, \
+}
+
+#define GPMC_NAND_HW_BCH8_ECC_LAYOUT { \
+ .eccbytes = 4 * 14, \
+ .eccpos = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
+ 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, \
+ 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, \
+ }, \
+ .oobfree = { \
+ { .offset = 58, .length = 6, }, \
+ } \
+}
+
+#define GPMC_NAND_HW_BCH16_ECC_LAYOUT { \
+ .eccbytes = 4 * 26, \
+ .eccpos = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, \
+ 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
+ 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, \
+ 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, \
+ 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, \
+ 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
+ 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, \
+ 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, \
+ }, \
+ .oobfree = { \
+ { .offset = 106, .length = 8, }, \
+ }, \
+}
+
+/*
+ * ELM Module Registers
+ */
+
+/* ELM registers bit fields */
+#define ELM_SYSCONFIG_SOFTRESET_MASK (0x2)
+#define ELM_SYSCONFIG_SOFTRESET (0x2)
+#define ELM_SYSSTATUS_RESETDONE_MASK (0x1)
+#define ELM_SYSSTATUS_RESETDONE (0x1)
+#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK (0x3)
+#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK (0x7FF0000)
+#define ELM_LOCATION_CONFIG_ECC_SIZE_POS (16)
+#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID (0x00010000)
+#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100)
+#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F)
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+
+enum bch_level {
+ BCH_4_BIT = 0,
+ BCH_8_BIT,
+ BCH_16_BIT
+};
+
+
+/* BCH syndrome registers */
+struct syndrome {
+ u32 syndrome_fragment_x[7]; /* 0x400, 0x404.... 0x418 */
+ u8 res1[36]; /* 0x41c */
+};
+
+/* BCH error status & location register */
+struct location {
+ u32 location_status; /* 0x800 */
+ u8 res1[124]; /* 0x804 */
+ u32 error_location_x[16]; /* 0x880.... */
+ u8 res2[64]; /* 0x8c0 */
+};
+
+/* BCH ELM register map - do not try to allocate memmory for this structure.
+ * We have used plenty of reserved variables to fill the slots in the ELM
+ * register memory map.
+ * Directly initialize the struct pointer to ELM base address.
+ */
+struct elm {
+ u32 rev; /* 0x000 */
+ u8 res1[12]; /* 0x004 */
+ u32 sysconfig; /* 0x010 */
+ u32 sysstatus; /* 0x014 */
+ u32 irqstatus; /* 0x018 */
+ u32 irqenable; /* 0x01c */
+ u32 location_config; /* 0x020 */
+ u8 res2[92]; /* 0x024 */
+ u32 page_ctrl; /* 0x080 */
+ u8 res3[892]; /* 0x084 */
+ struct syndrome syndrome_fragments[8]; /* 0x400 */
+ u8 res4[512]; /* 0x600 */
+ struct location error_location[8]; /* 0x800 */
+};
+
+int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
+ u32 *error_locations);
+int elm_config(enum bch_level level);
+void elm_reset(void);
+void elm_init(void);
+void am33xx_nand_switch_ecc(nand_ecc_modes_t hardware, int32_t mode);
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+
+#endif /* __ASM_ARCH_OMAP_GPMC_H */
#ifndef __ASSEMBLY__
struct exynos4_sysreg {
- unsigned char res1[0x210];
+ unsigned int res1[0x210 / 4];
unsigned int display_ctrl;
unsigned int display_ctrl2;
unsigned int camera_control;
};
struct exynos5_sysreg {
- unsigned char res1[0x214];
+ unsigned int res1[0x214 / 4];
unsigned int disp1blk_cfg;
unsigned int disp2blk_cfg;
unsigned int hdcp_e_fuse;
unsigned int reserved;
unsigned int ispblk_cfg;
unsigned int usb20phy_cfg;
- unsigned char res2[0x29c];
+ unsigned int res2[0x29c / 4];
unsigned int mipi_dphy;
unsigned int dptx_dphy;
unsigned int phyclk_sel;
--- /dev/null
+/*
+ * Freescale i.MX28 LCDIF Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_LCDIF_H__
+#define __MX28_REGS_LCDIF_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mx28_lcdif_regs {
+ mx28_reg_32(hw_lcdif_ctrl) /* 0x00 */
+ mx28_reg_32(hw_lcdif_ctrl1) /* 0x10 */
+ mx28_reg_32(hw_lcdif_ctrl2) /* 0x20 */
+ mx28_reg_32(hw_lcdif_transfer_count) /* 0x30 */
+ mx28_reg_32(hw_lcdif_cur_buf) /* 0x40 */
+ mx28_reg_32(hw_lcdif_next_buf) /* 0x50 */
+ mx28_reg_32(hw_lcdif_timing) /* 0x60 */
+ mx28_reg_32(hw_lcdif_vdctrl0) /* 0x70 */
+ mx28_reg_32(hw_lcdif_vdctrl1) /* 0x80 */
+ mx28_reg_32(hw_lcdif_vdctrl2) /* 0x90 */
+ mx28_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */
+ mx28_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */
+ mx28_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */
+ mx28_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */
+ mx28_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */
+ mx28_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */
+ mx28_reg_32(hw_lcdif_dvictrl4) /* 0x100 */
+ mx28_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */
+ mx28_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */
+ mx28_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
+ mx28_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
+ mx28_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
+ mx28_reg_32(hw_lcdif_csc_offset) /* 0x160 */
+ mx28_reg_32(hw_lcdif_csc_limit) /* 0x170 */
+ mx28_reg_32(hw_lcdif_data) /* 0x180 */
+ mx28_reg_32(hw_lcdif_bm_error_stat) /* 0x190 */
+ mx28_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
+ mx28_reg_32(hw_lcdif_lcdif_stat) /* 0x1b0 */
+ mx28_reg_32(hw_lcdif_version) /* 0x1c0 */
+ mx28_reg_32(hw_lcdif_debug0) /* 0x1d0 */
+ mx28_reg_32(hw_lcdif_debug1) /* 0x1e0 */
+ mx28_reg_32(hw_lcdif_debug2) /* 0x1f0 */
+};
+#endif
+
+#define LCDIF_CTRL_SFTRST (1 << 31)
+#define LCDIF_CTRL_CLKGATE (1 << 30)
+#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29)
+#define LCDIF_CTRL_READ_WRITEB (1 << 28)
+#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27)
+#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26)
+#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21)
+#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21
+#define LCDIF_CTRL_DVI_MODE (1 << 20)
+#define LCDIF_CTRL_BYPASS_COUNT (1 << 19)
+#define LCDIF_CTRL_VSYNC_MODE (1 << 18)
+#define LCDIF_CTRL_DOTCLK_MODE (1 << 17)
+#define LCDIF_CTRL_DATA_SELECT (1 << 16)
+#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14)
+#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14
+#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12)
+#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10)
+#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8
+#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8)
+#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7)
+#define LCDIF_CTRL_LCDIF_MASTER (1 << 5)
+#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3)
+#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2)
+#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1)
+#define LCDIF_CTRL_RUN (1 << 0)
+
+#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27)
+#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26)
+#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25)
+#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24)
+#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23)
+#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22)
+#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21)
+#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20)
+#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16)
+#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16
+#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(n) (((n) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET) & \
+ LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
+#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15)
+#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14)
+#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
+#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12)
+#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11)
+#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10)
+#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
+#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8)
+#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2)
+#define LCDIF_CTRL1_MODE86 (1 << 1)
+#define LCDIF_CTRL1_RESET (1 << 0)
+
+#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21)
+#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12)
+#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10)
+#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9)
+#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8)
+#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4)
+#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4
+#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1)
+#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1
+
+#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16)
+#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16
+#define LCDIF_TRANSFER_COUNT_V_COUNT(n) (((n) << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) & \
+ LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
+#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0)
+#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0
+#define LCDIF_TRANSFER_COUNT_H_COUNT(n) (((n) << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET) & \
+ LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
+
+#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff
+#define LCDIF_CUR_BUF_ADDR_OFFSET 0
+
+#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff
+#define LCDIF_NEXT_BUF_ADDR_OFFSET 0
+
+#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24)
+#define LCDIF_TIMING_CMD_HOLD_OFFSET 24
+#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16)
+#define LCDIF_TIMING_CMD_SETUP_OFFSET 16
+#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8)
+#define LCDIF_TIMING_DATA_HOLD_OFFSET 8
+#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0)
+#define LCDIF_TIMING_DATA_SETUP_OFFSET 0
+
+#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29)
+#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28)
+#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27)
+#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26)
+#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25)
+#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24)
+#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)
+#define LCDIF_VDCTRL0_HALF_LINE (1 << 19)
+#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18)
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(n) (((n) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET) & \
+ LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
+
+#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
+#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
+#define LCDIF_VDCTRL1_VSYNC_PERIOD(n) (((n) << LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET) & \
+ LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
+
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(n) (((n) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) & \
+ LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
+#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
+#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
+#define LCDIF_VDCTRL2_HSYNC_PERIOD(n) (((n) << LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET) & \
+ LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
+
+#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
+#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28)
+#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16)
+#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16
+#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(n) (((n) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) & \
+ LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
+
+#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0)
+#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0
+#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(n) (((n) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET) & \
+ LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
+
+#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29)
+#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29
+#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(n) (((n) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) & \
+ LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
+#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
+#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
+#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
+#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(n) (((n) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET) & \
+ LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
+
+#endif /* __MX28_REGS_LCDIF_H__ */
--- /dev/null
+/*
+ * Freescale i.MX28 LRADC Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_LRADC_H__
+#define __MX28_REGS_LRADC_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mx28_lradc_regs {
+ mx28_reg_32(hw_lradc_ctrl0);
+ mx28_reg_32(hw_lradc_ctrl1);
+ mx28_reg_32(hw_lradc_ctrl2);
+ mx28_reg_32(hw_lradc_ctrl3);
+ mx28_reg_32(hw_lradc_status);
+ mx28_reg_32(hw_lradc_ch0);
+ mx28_reg_32(hw_lradc_ch1);
+ mx28_reg_32(hw_lradc_ch2);
+ mx28_reg_32(hw_lradc_ch3);
+ mx28_reg_32(hw_lradc_ch4);
+ mx28_reg_32(hw_lradc_ch5);
+ mx28_reg_32(hw_lradc_ch6);
+ mx28_reg_32(hw_lradc_ch7);
+ mx28_reg_32(hw_lradc_delay0);
+ mx28_reg_32(hw_lradc_delay1);
+ mx28_reg_32(hw_lradc_delay2);
+ mx28_reg_32(hw_lradc_delay3);
+ mx28_reg_32(hw_lradc_debug0);
+ mx28_reg_32(hw_lradc_debug1);
+ mx28_reg_32(hw_lradc_conversion);
+ mx28_reg_32(hw_lradc_ctrl4);
+ mx28_reg_32(hw_lradc_treshold0);
+ mx28_reg_32(hw_lradc_treshold1);
+ mx28_reg_32(hw_lradc_version);
+};
+#endif
+
+#define LRADC_CTRL0_SFTRST (1 << 31)
+#define LRADC_CTRL0_CLKGATE (1 << 30)
+#define LRADC_CTRL0_ONCHIP_GROUNDREF (1 << 26)
+#define LRADC_CTRL0_BUTTON1_DETECT_ENABLE (1 << 25)
+#define LRADC_CTRL0_BUTTON0_DETECT_ENABLE (1 << 24)
+#define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23)
+#define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22)
+#define LRADC_CTRL0_YNLRSW (1 << 21)
+#define LRADC_CTRL0_YPLLSW_MASK (0x3 << 19)
+#define LRADC_CTRL0_YPLLSW_OFFSET 19
+#define LRADC_CTRL0_XNURSW_MASK (0x3 << 17)
+#define LRADC_CTRL0_XNURSW_OFFSET 17
+#define LRADC_CTRL0_XPULSW (1 << 16)
+#define LRADC_CTRL0_SCHEDULE_MASK 0xff
+#define LRADC_CTRL0_SCHEDULE_OFFSET 0
+
+#define LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN (1 << 28)
+#define LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN (1 << 27)
+#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN (1 << 26)
+#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN (1 << 25)
+#define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24)
+#define LRADC_CTRL1_LRADC7_IRQ_EN (1 << 23)
+#define LRADC_CTRL1_LRADC6_IRQ_EN (1 << 22)
+#define LRADC_CTRL1_LRADC5_IRQ_EN (1 << 21)
+#define LRADC_CTRL1_LRADC4_IRQ_EN (1 << 20)
+#define LRADC_CTRL1_LRADC3_IRQ_EN (1 << 19)
+#define LRADC_CTRL1_LRADC2_IRQ_EN (1 << 18)
+#define LRADC_CTRL1_LRADC1_IRQ_EN (1 << 17)
+#define LRADC_CTRL1_LRADC0_IRQ_EN (1 << 16)
+#define LRADC_CTRL1_BUTTON1_DETECT_IRQ (1 << 12)
+#define LRADC_CTRL1_BUTTON0_DETECT_IRQ (1 << 11)
+#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ (1 << 10)
+#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ (1 << 9)
+#define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8)
+#define LRADC_CTRL1_LRADC7_IRQ (1 << 7)
+#define LRADC_CTRL1_LRADC6_IRQ (1 << 6)
+#define LRADC_CTRL1_LRADC5_IRQ (1 << 5)
+#define LRADC_CTRL1_LRADC4_IRQ (1 << 4)
+#define LRADC_CTRL1_LRADC3_IRQ (1 << 3)
+#define LRADC_CTRL1_LRADC2_IRQ (1 << 2)
+#define LRADC_CTRL1_LRADC1_IRQ (1 << 1)
+#define LRADC_CTRL1_LRADC0_IRQ (1 << 0)
+
+#define LRADC_CTRL2_DIVIDE_BY_TWO_MASK (0xff << 24)
+#define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24
+#define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15)
+#define LRADC_CTRL2_VTHSENSE_MASK (0x3 << 13)
+#define LRADC_CTRL2_VTHSENSE_OFFSET 13
+#define LRADC_CTRL2_DISABLE_MUXAMP_BYPASS (1 << 12)
+#define LRADC_CTRL2_TEMP_SENSOR_IENABLE1 (1 << 9)
+#define LRADC_CTRL2_TEMP_SENSOR_IENABLE0 (1 << 8)
+#define LRADC_CTRL2_TEMP_ISRC1_MASK (0xf << 4)
+#define LRADC_CTRL2_TEMP_ISRC1_OFFSET 4
+#define LRADC_CTRL2_TEMP_ISRC1_300 (0xf << 4)
+#define LRADC_CTRL2_TEMP_ISRC1_280 (0xe << 4)
+#define LRADC_CTRL2_TEMP_ISRC1_260 (0xd << 4)
+#define LRADC_CTRL2_TEMP_ISRC1_240 (0xc << 4)
+#define LRADC_CTRL2_TEMP_ISRC1_220 (0xb << 4)
+#define LRADC_CTRL2_TEMP_ISRC1_200 (0xa << 4)
+#define LRADC_CTRL2_TEMP_ISRC1_180 (0x9 << 4)
+#define LRADC_CTRL2_TEMP_ISRC1_160 (0x8 << 4)
+#define LRADC_CTRL2_TEMP_ISRC1_140 (0x7 << 4)
+#define LRADC_CTRL2_TEMP_ISRC1_120 (0x6 << 4)
+#define LRADC_CTRL2_TEMP_ISRC1_100 (0x5 << 4)
+#define LRADC_CTRL2_TEMP_ISRC1_80 (0x4 << 4)
+#define LRADC_CTRL2_TEMP_ISRC1_60 (0x3 << 4)
+#define LRADC_CTRL2_TEMP_ISRC1_40 (0x2 << 4)
+#define LRADC_CTRL2_TEMP_ISRC1_20 (0x1 << 4)
+#define LRADC_CTRL2_TEMP_ISRC1_ZERO (0x0 << 4)
+#define LRADC_CTRL2_TEMP_ISRC0_MASK (0xf << 0)
+#define LRADC_CTRL2_TEMP_ISRC0_OFFSET 0
+#define LRADC_CTRL2_TEMP_ISRC0_300 (0xf << 0)
+#define LRADC_CTRL2_TEMP_ISRC0_280 (0xe << 0)
+#define LRADC_CTRL2_TEMP_ISRC0_260 (0xd << 0)
+#define LRADC_CTRL2_TEMP_ISRC0_240 (0xc << 0)
+#define LRADC_CTRL2_TEMP_ISRC0_220 (0xb << 0)
+#define LRADC_CTRL2_TEMP_ISRC0_200 (0xa << 0)
+#define LRADC_CTRL2_TEMP_ISRC0_180 (0x9 << 0)
+#define LRADC_CTRL2_TEMP_ISRC0_160 (0x8 << 0)
+#define LRADC_CTRL2_TEMP_ISRC0_140 (0x7 << 0)
+#define LRADC_CTRL2_TEMP_ISRC0_120 (0x6 << 0)
+#define LRADC_CTRL2_TEMP_ISRC0_100 (0x5 << 0)
+#define LRADC_CTRL2_TEMP_ISRC0_80 (0x4 << 0)
+#define LRADC_CTRL2_TEMP_ISRC0_60 (0x3 << 0)
+#define LRADC_CTRL2_TEMP_ISRC0_40 (0x2 << 0)
+#define LRADC_CTRL2_TEMP_ISRC0_20 (0x1 << 0)
+#define LRADC_CTRL2_TEMP_ISRC0_ZERO (0x0 << 0)
+
+#define LRADC_CTRL3_DISCARD_MASK (0x3 << 24)
+#define LRADC_CTRL3_DISCARD_OFFSET 24
+#define LRADC_CTRL3_DISCARD_1_SAMPLE (0x1 << 24)
+#define LRADC_CTRL3_DISCARD_2_SAMPLES (0x2 << 24)
+#define LRADC_CTRL3_DISCARD_3_SAMPLES (0x3 << 24)
+#define LRADC_CTRL3_FORCE_ANALOG_PWUP (1 << 23)
+#define LRADC_CTRL3_FORCE_ANALOG_PWDN (1 << 22)
+#define LRADC_CTRL3_CYCLE_TIME_MASK (0x3 << 8)
+#define LRADC_CTRL3_CYCLE_TIME_OFFSET 8
+#define LRADC_CTRL3_CYCLE_TIME_6MHZ (0x0 << 8)
+#define LRADC_CTRL3_CYCLE_TIME_4MHZ (0x1 << 8)
+#define LRADC_CTRL3_CYCLE_TIME_3MHZ (0x2 << 8)
+#define LRADC_CTRL3_CYCLE_TIME_2MHZ (0x3 << 8)
+#define LRADC_CTRL3_HIGH_TIME_MASK (0x3 << 4)
+#define LRADC_CTRL3_HIGH_TIME_OFFSET 4
+#define LRADC_CTRL3_HIGH_TIME_42NS (0x0 << 4)
+#define LRADC_CTRL3_HIGH_TIME_83NS (0x1 << 4)
+#define LRADC_CTRL3_HIGH_TIME_125NS (0x2 << 4)
+#define LRADC_CTRL3_HIGH_TIME_250NS (0x3 << 4)
+#define LRADC_CTRL3_DELAY_CLOCK (1 << 1)
+#define LRADC_CTRL3_INVERT_CLOCK (1 << 0)
+
+#define LRADC_STATUS_BUTTON1_PRESENT (1 << 28)
+#define LRADC_STATUS_BUTTON0_PRESENT (1 << 27)
+#define LRADC_STATUS_TEMP1_PRESENT (1 << 26)
+#define LRADC_STATUS_TEMP0_PRESENT (1 << 25)
+#define LRADC_STATUS_TOUCH_PANEL_PRESENT (1 << 24)
+#define LRADC_STATUS_CHANNEL7_PRESENT (1 << 23)
+#define LRADC_STATUS_CHANNEL6_PRESENT (1 << 22)
+#define LRADC_STATUS_CHANNEL5_PRESENT (1 << 21)
+#define LRADC_STATUS_CHANNEL4_PRESENT (1 << 20)
+#define LRADC_STATUS_CHANNEL3_PRESENT (1 << 19)
+#define LRADC_STATUS_CHANNEL2_PRESENT (1 << 18)
+#define LRADC_STATUS_CHANNEL1_PRESENT (1 << 17)
+#define LRADC_STATUS_CHANNEL0_PRESENT (1 << 16)
+#define LRADC_STATUS_BUTTON1_DETECT_RAW (1 << 2)
+#define LRADC_STATUS_BUTTON0_DETECT_RAW (1 << 1)
+#define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0)
+
+#define LRADC_CH_TOGGLE (1 << 31)
+#define LRADC_CH7_TESTMODE_TOGGLE (1 << 30)
+#define LRADC_CH_ACCUMULATE (1 << 29)
+#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
+#define LRADC_CH_NUM_SAMPLES_OFFSET 24
+#define LRADC_CH_VALUE_MASK 0x3ffff
+#define LRADC_CH_VALUE_OFFSET 0
+
+#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24)
+#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
+#define LRADC_DELAY_KICK (1 << 20)
+#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
+#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
+#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
+#define LRADC_DELAY_LOOP_COUNT_OFFSET 11
+#define LRADC_DELAY_DELAY_MASK 0x7ff
+#define LRADC_DELAY_DELAY_OFFSET 0
+
+#define LRADC_DEBUG0_READONLY_MASK (0xffff << 16)
+#define LRADC_DEBUG0_READONLY_OFFSET 16
+#define LRADC_DEBUG0_STATE_MASK (0xfff << 0)
+#define LRADC_DEBUG0_STATE_OFFSET 0
+
+#define LRADC_DEBUG1_REQUEST_MASK (0xff << 16)
+#define LRADC_DEBUG1_REQUEST_OFFSET 16
+#define LRADC_DEBUG1_TESTMODE_COUNT_MASK (0x1f << 8)
+#define LRADC_DEBUG1_TESTMODE_COUNT_OFFSET 8
+#define LRADC_DEBUG1_TESTMODE6 (1 << 2)
+#define LRADC_DEBUG1_TESTMODE5 (1 << 1)
+#define LRADC_DEBUG1_TESTMODE (1 << 0)
+
+#define LRADC_CONVERSION_AUTOMATIC (1 << 20)
+#define LRADC_CONVERSION_SCALE_FACTOR_MASK (0x3 << 16)
+#define LRADC_CONVERSION_SCALE_FACTOR_OFFSET 16
+#define LRADC_CONVERSION_SCALE_FACTOR_NIMH (0x0 << 16)
+#define LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH (0x1 << 16)
+#define LRADC_CONVERSION_SCALE_FACTOR_LI_ION (0x2 << 16)
+#define LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION (0x3 << 16)
+#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK 0x3ff
+#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET 0
+
+#define LRADC_CTRL4_LRADC7SELECT_MASK (0xf << 28)
+#define LRADC_CTRL4_LRADC7SELECT_OFFSET 28
+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL0 (0x0 << 28)
+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL1 (0x1 << 28)
+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL2 (0x2 << 28)
+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL3 (0x3 << 28)
+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL4 (0x4 << 28)
+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL5 (0x5 << 28)
+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL6 (0x6 << 28)
+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL7 (0x7 << 28)
+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL8 (0x8 << 28)
+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL9 (0x9 << 28)
+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL10 (0xa << 28)
+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL11 (0xb << 28)
+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL12 (0xc << 28)
+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL13 (0xd << 28)
+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL14 (0xe << 28)
+#define LRADC_CTRL4_LRADC7SELECT_CHANNEL15 (0xf << 28)
+#define LRADC_CTRL4_LRADC6SELECT_MASK (0xf << 24)
+#define LRADC_CTRL4_LRADC6SELECT_OFFSET 24
+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL0 (0x0 << 24)
+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL1 (0x1 << 24)
+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL2 (0x2 << 24)
+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL3 (0x3 << 24)
+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL4 (0x4 << 24)
+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL5 (0x5 << 24)
+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL6 (0x6 << 24)
+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL7 (0x7 << 24)
+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL8 (0x8 << 24)
+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL9 (0x9 << 24)
+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL10 (0xa << 24)
+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL11 (0xb << 24)
+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL12 (0xc << 24)
+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL13 (0xd << 24)
+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL14 (0xe << 24)
+#define LRADC_CTRL4_LRADC6SELECT_CHANNEL15 (0xf << 24)
+#define LRADC_CTRL4_LRADC5SELECT_MASK (0xf << 20)
+#define LRADC_CTRL4_LRADC5SELECT_OFFSET 20
+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL0 (0x0 << 20)
+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL1 (0x1 << 20)
+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL2 (0x2 << 20)
+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL3 (0x3 << 20)
+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL4 (0x4 << 20)
+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL5 (0x5 << 20)
+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL6 (0x6 << 20)
+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL7 (0x7 << 20)
+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL8 (0x8 << 20)
+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL9 (0x9 << 20)
+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL10 (0xa << 20)
+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL11 (0xb << 20)
+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL12 (0xc << 20)
+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL13 (0xd << 20)
+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL14 (0xe << 20)
+#define LRADC_CTRL4_LRADC5SELECT_CHANNEL15 (0xf << 20)
+#define LRADC_CTRL4_LRADC4SELECT_MASK (0xf << 16)
+#define LRADC_CTRL4_LRADC4SELECT_OFFSET 16
+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL0 (0x0 << 16)
+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL1 (0x1 << 16)
+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL2 (0x2 << 16)
+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL3 (0x3 << 16)
+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL4 (0x4 << 16)
+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL5 (0x5 << 16)
+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL6 (0x6 << 16)
+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL7 (0x7 << 16)
+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL8 (0x8 << 16)
+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL9 (0x9 << 16)
+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL10 (0xa << 16)
+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL11 (0xb << 16)
+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL12 (0xc << 16)
+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL13 (0xd << 16)
+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL14 (0xe << 16)
+#define LRADC_CTRL4_LRADC4SELECT_CHANNEL15 (0xf << 16)
+#define LRADC_CTRL4_LRADC3SELECT_MASK (0xf << 12)
+#define LRADC_CTRL4_LRADC3SELECT_OFFSET 12
+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL0 (0x0 << 12)
+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL1 (0x1 << 12)
+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL2 (0x2 << 12)
+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL3 (0x3 << 12)
+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL4 (0x4 << 12)
+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL5 (0x5 << 12)
+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL6 (0x6 << 12)
+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL7 (0x7 << 12)
+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL8 (0x8 << 12)
+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL9 (0x9 << 12)
+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL10 (0xa << 12)
+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL11 (0xb << 12)
+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL12 (0xc << 12)
+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL13 (0xd << 12)
+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL14 (0xe << 12)
+#define LRADC_CTRL4_LRADC3SELECT_CHANNEL15 (0xf << 12)
+#define LRADC_CTRL4_LRADC2SELECT_MASK (0xf << 8)
+#define LRADC_CTRL4_LRADC2SELECT_OFFSET 8
+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL0 (0x0 << 8)
+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL1 (0x1 << 8)
+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL2 (0x2 << 8)
+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL3 (0x3 << 8)
+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL4 (0x4 << 8)
+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL5 (0x5 << 8)
+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL6 (0x6 << 8)
+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL7 (0x7 << 8)
+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL8 (0x8 << 8)
+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL9 (0x9 << 8)
+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL10 (0xa << 8)
+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL11 (0xb << 8)
+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL12 (0xc << 8)
+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL13 (0xd << 8)
+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL14 (0xe << 8)
+#define LRADC_CTRL4_LRADC2SELECT_CHANNEL15 (0xf << 8)
+#define LRADC_CTRL4_LRADC1SELECT_MASK (0xf << 4)
+#define LRADC_CTRL4_LRADC1SELECT_OFFSET 4
+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL0 (0x0 << 4)
+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL1 (0x1 << 4)
+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL2 (0x2 << 4)
+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL3 (0x3 << 4)
+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL4 (0x4 << 4)
+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL5 (0x5 << 4)
+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL6 (0x6 << 4)
+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL7 (0x7 << 4)
+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL8 (0x8 << 4)
+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL9 (0x9 << 4)
+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL10 (0xa << 4)
+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL11 (0xb << 4)
+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL12 (0xc << 4)
+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL13 (0xd << 4)
+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL14 (0xe << 4)
+#define LRADC_CTRL4_LRADC1SELECT_CHANNEL15 (0xf << 4)
+#define LRADC_CTRL4_LRADC0SELECT_MASK 0xf
+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL0 (0x0 << 0)
+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL1 (0x1 << 0)
+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL2 (0x2 << 0)
+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL3 (0x3 << 0)
+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL4 (0x4 << 0)
+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL5 (0x5 << 0)
+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL6 (0x6 << 0)
+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL7 (0x7 << 0)
+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL8 (0x8 << 0)
+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL9 (0x9 << 0)
+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL10 (0xa << 0)
+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL11 (0xb << 0)
+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL12 (0xc << 0)
+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL13 (0xd << 0)
+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL14 (0xe << 0)
+#define LRADC_CTRL4_LRADC0SELECT_CHANNEL15 (0xf << 0)
+
+#define LRADC_THRESHOLD_ENABLE (1 << 24)
+#define LRADC_THRESHOLD_BATTCHRG_DISABLE (1 << 23)
+#define LRADC_THRESHOLD_CHANNEL_SEL_MASK (0x7 << 20)
+#define LRADC_THRESHOLD_CHANNEL_SEL_OFFSET 20
+#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0 (0x0 << 20)
+#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1 (0x1 << 20)
+#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2 (0x2 << 20)
+#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3 (0x3 << 20)
+#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4 (0x4 << 20)
+#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5 (0x5 << 20)
+#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6 (0x6 << 20)
+#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7 (0x7 << 20)
+#define LRADC_THRESHOLD_SETTING_MASK (0x3 << 18)
+#define LRADC_THRESHOLD_SETTING_OFFSET 18
+#define LRADC_THRESHOLD_SETTING_NO_COMPARE (0x0 << 18)
+#define LRADC_THRESHOLD_SETTING_DETECT_LOW (0x1 << 18)
+#define LRADC_THRESHOLD_SETTING_DETECT_HIGH (0x2 << 18)
+#define LRADC_THRESHOLD_SETTING_RESERVED (0x3 << 18)
+#define LRADC_THRESHOLD_VALUE_MASK 0x3ffff
+#define LRADC_THRESHOLD_VALUE_OFFSET 0
+
+#define LRADC_VERSION_MAJOR_MASK (0xff << 24)
+#define LRADC_VERSION_MAJOR_OFFSET 24
+#define LRADC_VERSION_MINOR_MASK (0xff << 16)
+#define LRADC_VERSION_MINOR_OFFSET 16
+#define LRADC_VERSION_STEP_MASK 0xffff
+#define LRADC_VERSION_STEP_OFFSET 0
+
+#endif /* __MX28_REGS_LRADC_H__ */
MXC_I2C_CLK,
};
+
+struct clk {
+ const char *name;
+ int id;
+ /* Source clock this clk depends on */
+ struct clk *parent;
+ /* Secondary clock to enable/disable with this clock */
+ struct clk *secondary;
+ /* Current clock rate */
+ unsigned long rate;
+ /* Reference count of clock enable/disable */
+ __s8 usecount;
+ /* Register bit position for clock's enable/disable control. */
+ u8 enable_shift;
+ /* Register address for clock's enable/disable control. */
+ void *enable_reg;
+ u32 flags;
+ /*
+ * Function ptr to recalculate the clock's rate based on parent
+ * clock's rate
+ */
+ void (*recalc) (struct clk *);
+ /*
+ * Function ptr to set the clock to a new rate. The rate must match a
+ * supported rate returned from round_rate. Leave blank if clock is not
+ * programmable
+ */
+ int (*set_rate) (struct clk *, unsigned long);
+ /*
+ * Function ptr to round the requested clock rate to the nearest
+ * supported rate that is less than or equal to the requested rate.
+ */
+ unsigned long (*round_rate) (struct clk *, unsigned long);
+ /*
+ * Function ptr to enable the clock. Leave blank if clock can not
+ * be gated.
+ */
+ int (*enable) (struct clk *);
+ /*
+ * Function ptr to disable the clock. Leave blank if clock can not
+ * be gated.
+ */
+ void (*disable) (struct clk *);
+ /* Function ptr to set the parent clock of the clock. */
+ int (*set_parent) (struct clk *, struct clk *);
+};
+
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
-int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
+int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk);
void set_usb_phy_clk(void);
void enable_usb_phy1_clk(unsigned char enable);
void enable_usb_phy2_clk(unsigned char enable);
void enable_usboh3_clk(unsigned char enable);
void mxc_set_sata_internal_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
+void ipu_clk_enable(void);
+void ipu_clk_disable(void);
#endif /* __ASM_ARCH_CLOCK_H */
#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7)
/* Define the bits in register CCDR */
-#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
+#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 21)
/* Define the bits in register CCGRx */
#define MXC_CCM_CCGR_CG_MASK 0x3
#endif
/* Define the bits in register CLPCR */
-#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
+#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
#define MXC_DPLLC_CTL_HFSM (1 << 7)
#define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12)
#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
-#define IPU_SOC_BASE_ADDR 0x40000000
-#define IPU_SOC_OFFSET 0x1E000000
+#define IPU_CTRL_BASE_ADDR 0x40000000
#define SPBA0_BASE_ADDR 0x70000000
#define AIPS1_BASE_ADDR 0x73F00000
#define AIPS2_BASE_ADDR 0x83F00000
#define NFC_BASE_ADDR_AXI 0xCFFF0000
#define CS1_BASE_ADDR 0xB8000000
#elif defined(CONFIG_MX53)
-#define IPU_SOC_BASE_ADDR 0x18000000
-#define IPU_SOC_OFFSET 0x06000000
+#define IPU_CTRL_BASE_ADDR 0x00000000
#define SPBA0_BASE_ADDR 0x50000000
#define AIPS1_BASE_ADDR 0x53F00000
#define AIPS2_BASE_ADDR 0x63F00000
#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
#define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
+#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
#if defined(CONFIG_MX53)
-#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
-#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
-#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
+#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
+#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
+#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
+#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
-#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
#endif
/*
* AIPS 2
#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
-#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
+#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
#if defined(CONFIG_MX53)
-#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
+#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
#endif
/*
*/
#define WBED 1
+/*
+ * WEIM WCR
+ */
+#define BCM 1
+#define GBCD(x) (((x) & 0x3) << 1)
+#define INTEN (1 << 4)
+#define INTPOL (1 << 5)
+#define WDOG_EN (1 << 8)
+#define WDOG_LIMIT(x) (((x) & 0x3) << 9)
+
#define CS0_128 0
#define CS0_64M_CS1_64M 1
#define CS0_64M_CS1_32M_CS2_32M 2
/*
* Number of GPIO pins per port
*/
-#define GPIO_NUM_PIN 32
+#define GPIO_NUM_PIN 32
#define IIM_SREV 0x24
#define ROM_SI_REV 0x48
#define DP_MFD_665 (96 - 1)
#define DP_MFN_665 89
+#define DP_OP_600 ((6 << 4) + ((1 - 1) << 0))
+#define DP_MFD_600 (4 - 1)
+#define DP_MFN_600 1
+
#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
#define DP_MFD_532 (24 - 1)
#define DP_MFN_532 13
+#define DP_OP_455 ((9 << 4) + ((2 - 1) << 0))
+#define DP_MFD_455 (48 - 1)
+#define DP_MFN_455 23
+
#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
#define DP_MFD_400 (3 - 1)
#define DP_MFN_400 1
-#define DP_OP_455 ((9 << 4) + ((2 - 1) << 0))
-#define DP_MFD_455 (48 - 1)
-#define DP_MFN_455 23
+#define DP_OP_333 ((6 << 4) + ((2 - 1) << 0))
+#define DP_MFD_333 (16 - 1)
+#define DP_MFN_333 15
#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
#define DP_MFD_216 (4 - 1)
#define DP_MFN_216 3
-#define CHIP_REV_1_0 0x10
-#define CHIP_REV_1_1 0x11
-#define CHIP_REV_2_0 0x20
-#define CHIP_REV_2_5 0x25
-#define CHIP_REV_3_0 0x30
+#define CHIP_REV_1_0 0x10
+#define CHIP_REV_1_1 0x11
+#define CHIP_REV_2_0 0x20
+#define CHIP_REV_2_5 0x25
+#define CHIP_REV_3_0 0x30
-#define BOARD_REV_1_0 0x0
-#define BOARD_REV_2_0 0x1
+#define BOARD_REV_1_0 0x0
+#define BOARD_REV_2_0 0x1
#define BOARD_VER_OFFSET 0x8
-#define IMX_IIM_BASE (IIM_BASE_ADDR)
+#define IMX_IIM_BASE IIM_BASE_ADDR
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
struct iim_regs {
u32 stat;
u32 statm;
- u32 err;
+ u32 err;
u32 emask;
u32 fctl;
u32 ua;
--- /dev/null
+/*
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMX_IIM_H__
+#define __IMX_IIM_H__
+
+/* IIM Status & Error Register bits */
+#define IIM_STAT_BUSY (1 << 7)
+#define IIM_STAT_PRGD (1 << 1)
+#define IIM_STAT_SNSD (1 << 0)
+
+#define IIM_ERR_PRGE (1 << 7)
+#define IIM_ERR_WPE (1 << 6)
+#define IIM_ERR_OPE (1 << 5)
+#define IIM_ERR_RPE (1 << 4)
+#define IIM_ERR_WLRE (1 << 3)
+#define IIM_ERR_SNSE (1 << 2)
+#define IIM_ERR_PARITYE (1 << 1)
+
+#define IIM_PROD_REV_SH 3
+#define IIM_PROD_REV_LEN 5
+#define IIM_SREV_REV_SH 4
+#define IIM_SREV_REV_LEN 4
+#define PROD_SIGNATURE_MX51 0x1
+
+#define IIM_ERR_SHIFT 8
+#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
+#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
+
+#define IIM_BANK_AREA_0_OFFSET 0x800
+#define IIM_BANK_AREA_1_OFFSET 0xc00
+#define IIM_BANK_AREA_2_OFFSET 0x1000
+#define IIM_BANK_AREA_3_OFFSET 0x1400
+
+int iim_read(int bank, char row);
+int iim_blow(int bank, int row, int val);
+int iim_blow_func(char *func_name, char *func_val);
+
+#endif
#define __NA_ 0x000
+#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
+#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
+
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
* See also iomux-v3.h
*/
-/* PAD MUX ALT INPSE PATH PADCTRL */
-enum {
- MX51_PAD_EIM_D16__USBH2_DATA0 = IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D17__USBH2_DATA1 = IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D18__USBH2_DATA2 = IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D19__USBH2_DATA3 = IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D20__USBH2_DATA4 = IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D27__GPIO2_9 = IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_EIM_A24__USBH2_CLK = IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_A25__USBH2_DIR = IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_A26__GPIO2_20 = IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_CS0__GPIO2_25 = IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_EIM_CS2__SD1_CD = IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL),
- MX51_PAD_EIM_CS3__GPIO2_28 = IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_EIM_CS4__GPIO2_29 = IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_NANDF_WE_B__PATA_DIOW = IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_RE_B__PATA_DIOR = IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_ALE__PATA_BUFFER_EN = IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_CLE__PATA_RESET_B = IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_WP_B__PATA_DMACK = IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_RB0__PATA_DMARQ = IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_RB1__PATA_IORDY = IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_GPIO_NAND__PATA_INTRQ = IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_CS2__PATA_CS_0 = IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_CS3__PATA_CS_1 = IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_CS4__PATA_DA_0 = IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_CS5__PATA_DA_1 = IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_CS6__PATA_DA_2 = IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_D15__PATA_DATA15 = IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_D14__PATA_DATA14 = IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_D13__PATA_DATA13 = IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_D12__PATA_DATA12 = IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_D11__PATA_DATA11 = IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_D10__PATA_DATA10 = IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_D9__PATA_DATA9 = IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_D8__PATA_DATA8 = IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_D7__PATA_DATA7 = IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_D6__PATA_DATA6 = IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_D5__PATA_DATA5 = IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_D4__PATA_DATA4 = IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_D3__PATA_DATA3 = IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_D2__PATA_DATA2 = IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_D1__PATA_DATA1 = IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_NANDF_D0__PATA_DATA0 = IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
- MX51_PAD_CSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
- MX51_PAD_CSPI1_SS0__GPIO4_24 = IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_CSPI1_SS1__GPIO4_25 = IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
- MX51_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL),
- MX51_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL),
- MX51_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL),
- MX51_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL),
- MX51_PAD_USBH1_CLK__USBH1_CLK = IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DIR__USBH1_DIR = IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_STP__USBH1_STP = IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_STP__GPIO1_27 = IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_USBH1_NXT__USBH1_NXT = IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA0__USBH1_DATA0 = IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA1__USBH1_DATA1 = IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA2__USBH1_DATA2 = IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA3__USBH1_DATA3 = IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA4__USBH1_DATA4 = IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA5__USBH1_DATA5 = IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA6__USBH1_DATA6 = IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA7__USBH1_DATA7 = IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
- MX51_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
- MX51_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
- MX51_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
- MX51_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
- MX51_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
- MX51_PAD_GPIO1_0__SD1_CD = IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
- MX51_PAD_GPIO1_1__SD1_WP = IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
- MX51_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
- MX51_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
- MX51_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
- MX51_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
- MX51_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
- MX51_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
- MX51_PAD_GPIO1_3__GPIO1_3 = IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_GPIO1_5__GPIO1_5 = IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_GPIO1_6__GPIO1_6 = IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_GPIO1_7__SD2_WP = IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
- MX51_PAD_GPIO1_8__SD2_CD = IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
-};
+/* PAD MUX ALT INPSE PATH PADCTRL */
+#define MX51_PAD_EIM_D16__AUD4_RXFS IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__AUD5_TXD IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__GPIO2_0 IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D16__UART2_CTS IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D16__USBH2_DATA0 IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__AUD5_RXD IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__GPIO2_1 IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__UART2_RXD IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D17__UART3_CTS IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D17__USBH2_DATA1 IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__AUD5_TXC IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__GPIO2_2 IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__UART2_TXD IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D18__UART3_RTS IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D18__USBH2_DATA2 IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__AUD4_RXC IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__AUD5_TXFS IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__GPIO2_3 IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D19__UART2_RTS IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D19__USBH2_DATA3 IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__AUD4_TXD IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__USBH2_DATA4 IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__AUD4_RXD IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__USBH2_DATA5 IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__AUD4_TXC IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__GPIO2_6 IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__USBH2_DATA6 IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__AUD4_TXFS IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__GPIO2_7 IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__SPDIF_OUT1 IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__USBH2_DATA7 IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__AUD6_RXFS IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__GPIO2_8 IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__I2C2_SDA IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D24__USBOTG_DATA0 IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D25__KEY_COL6 IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D27__I2C2_SCL IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL)
+#define MX51_PAD_EIM_D27__USBOTG_DATA3 IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D28__AUD6_TXD IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D28__KEY_ROW4 IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D28__USBOTG_DATA4 IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__AUD6_RXD IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__KEY_ROW5 IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__USBOTG_DATA5 IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__AUD6_TXC IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__KEY_ROW6 IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__USBOTG_DATA6 IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__AUD6_TXFS IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__KEY_ROW7 IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__USBOTG_DATA7 IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__GPIO2_10 IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__GPIO2_11 IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__BOOT_LPB0 IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__GPIO2_12 IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__BOOT_LPB1 IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__GPIO2_13 IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__GPIO2_15 IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__BOOT_HPN_EN IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__GPIO2_17 IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__GPIO2_18 IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__USBH2_CLK IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__DISP1_PIN4 IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__GPIO2_19 IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__USBH2_DIR IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__CSI1_DATA_EN IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__DISP2_EXT_CLK IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__GPIO2_20 IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__USBH2_STP IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__CSI2_DATA_EN IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__DISP1_PIN1 IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__GPIO2_21 IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__USBH2_NXT IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__AUD5_RXFS IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__CSI1_D2 IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__FEC_MDIO (IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, 0) | \
+ MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS))
+#define MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__AUD5_RXC IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__CSI1_D3 IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS0__GPIO2_25 IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS1__GPIO2_26 IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__AUD5_TXD IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__CSI1_D4 IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__USBOTG_STP IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__AUD5_RXD IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__CSI1_D5 IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__USBOTG_NXT IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__AUD5_TXC IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__CSI1_D6 IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2)
+#define MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__USBOTG_CLK IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__AUD5_TXFS IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__CSI1_D7 IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2)
+#define MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__USBOTG_DIR IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__SD3_DATA0 IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__GPIO3_4 IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__PATA_DIOR IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__SD3_DATA1 IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__GPIO3_5 IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__GPIO3_6 IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__PATA_RESET_B IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__GPIO3_7 IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__PATA_DMACK IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__SD3_DATA2 IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__GPIO3_8 IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__PATA_DMARQ IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__SD3_DATA3 IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__CSPI_MOSI IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__ECSPI2_RDY IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2)
+#define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2)
+#define MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS1__GPIO3_17 IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__CSPI_SCLK IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
+#define MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__PATA_DA_0 IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__SD4_DAT1 IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__USBH3_STP IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__PATA_DA_1 IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__SD4_DAT2 IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__USBH3_DIR IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__CSPI_SS3 IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__PATA_DA_2 IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__SD4_DAT3 IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__SD3_CLK IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
+#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4)
+#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__PATA_DATA15 IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__SD3_DAT7 IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__ECSPI2_SS3 IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__GPIO3_26 IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__PATA_DATA14 IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__SD3_DAT6 IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__ECSPI2_SS2 IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__GPIO3_27 IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__PATA_DATA13 IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__SD3_DAT5 IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__ECSPI2_SS1 IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__GPIO3_28 IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__PATA_DATA12 IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__SD3_DAT4 IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__PATA_DATA11 IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__SD3_DATA3 IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__PATA_DATA10 IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__SD3_DATA2 IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16c, 2, 0x958, 0, MX51_PAD_CTRL_4)
+#define MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__PATA_DATA9 IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__SD3_DATA1 IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__PATA_DATA8 IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__SD3_DATA0 IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__GPIO4_1 IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__PATA_DATA7 IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__USBH3_DATA0 IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__GPIO4_2 IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__PATA_DATA6 IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__SD4_LCTL IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__USBH3_DATA1 IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__GPIO4_3 IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__PATA_DATA5 IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__SD4_WP IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__USBH3_DATA2 IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__GPIO4_4 IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__PATA_DATA4 IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__SD4_CD IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__USBH3_DATA3 IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__GPIO4_5 IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__PATA_DATA3 IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__SD4_DAT4 IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__USBH3_DATA4 IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__GPIO4_6 IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__PATA_DATA2 IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__SD4_DAT5 IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__USBH3_DATA5 IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__GPIO4_7 IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__PATA_DATA1 IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__SD4_DAT6 IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__USBH3_DATA6 IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__GPIO4_8 IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__PATA_DATA0 IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__SD4_DAT7 IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__USBH3_DATA7 IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D8__GPIO3_12 IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_VSYNC__GPIO3_14 IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_HSYNC__GPIO3_15 IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D12__GPIO4_9 IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D18__GPIO4_11 IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D19__GPIO4_12 IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_VSYNC__GPIO4_13 IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_HSYNC__GPIO4_14 IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__GPIO4_16 IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__GPIO4_17 IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__UART3_RXD IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__AUD3_TXC IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__GPIO4_21 IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__UART3_TXD IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__GPIO4_22 IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__I2C1_SDA IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__AUD4_RXD IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__GPIO4_23 IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__AUD4_TXC IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__AUD4_TXD IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__AUD4_TXFS IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__GPIO4_26 IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__GPIO4_27 IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__I2C1_SCL IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_UART1_RXD__GPIO4_28 IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART1_TXD__GPIO4_29 IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART1_RTS__GPIO4_30 IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART1_CTS__GPIO4_31 IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__FIRI_TXD IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__GPIO1_20 IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__CSI1_D1 IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__GPIO1_23 IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__UART1_DSR IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__GPIO1_24 IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__SPDIF_OUT IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL0__PLL1_BYP IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL1__PLL2_BYP IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL2__PLL3_BYP IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__SPDIF_OUT1 IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__UART1_RI IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__UART1_DCD IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__CSPI_SCLK IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__GPIO1_25 IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__I2C2_SCL IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__CSPI_MOSI IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__GPIO1_26 IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__I2C2_SDA IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__CSPI_RDY IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__GPIO1_27 IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__UART3_RXD IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__CSPI_MISO IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__GPIO1_28 IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__UART3_TXD IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__GPIO1_11 IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__UART2_CTS IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__GPIO1_12 IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__CSPI_SS0 IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__GPIO1_15 IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__CSPI_SS1 IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__GPIO1_16 IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__CSPI_SS3 IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__GPIO1_17 IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__GPIO1_18 IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__GPIO3_0 IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__GPIO3_1 IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__GPIO3_2 IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__DISP1_SER_DIO IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__FEC_TX_ER IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN4__FEC_CRS IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4)
+#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__AUD6_TXFS IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4)
+#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__AUD6_RXFS IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5)
+#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
+#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
+#define MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
+#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(__NA_, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__I2C1_SDA IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
+#define MX51_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA0__SD1_DAT4 IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
+#define MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL)
#endif /* __IOMUX_MX51_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc..
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARCH_IOMUX_MX53_H__
+#define __ASM_ARCH_IOMUX_MX53_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+#define PAD_CTL_DVS (1 << 13)
+#define PAD_CTL_INPUT_DDR (1 << 9)
+#define PAD_CTL_HYS (1 << 8)
+
+#define PAD_CTL_PKE (1 << 7)
+#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
+#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
+
+#define PAD_CTL_ODE (1 << 3)
+
+#define PAD_CTL_DSE_LOW (0 << 1)
+#define PAD_CTL_DSE_MED (1 << 1)
+#define PAD_CTL_DSE_HIGH (2 << 1)
+#define PAD_CTL_DSE_MAX (3 << 1)
+
+#define PAD_CTL_SRE_FAST (1 << 0)
+#define PAD_CTL_SRE_SLOW (0 << 0)
+
+/* These 2 defines are for pins that may not have a mux register, but could
+ * have a pad setting register, and vice-versa. */
+#define __NA_ 0x00
+
+#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_SRE_FAST)
+
+
+#define MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__GPIO4_7 IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__FEC_TX_ER IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__GPIO4_8 IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__FEC_RX_CLK IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__GPIO4_9 IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__FEC_COL IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__GPIO4_10 IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__FEC_MDIO IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__GPIO4_11 IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__FEC_MDC IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__GPIO4_12 IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__USBOH3_H2_DP IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x03C, 4 | MUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__FEC_CRS IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__GPIO4_13 IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x040, 4 | MUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__GPIO4_14 IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__IPU_SISG_4 IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__GPIO4_15 IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__IPU_SISG_5 IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__GPIO4_17 IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__GPIO4_18 IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__GPIO4_19 IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__GPIO4_20 IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__ESDHC1_WP IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__GPIO4_21 IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__CSPI_SCLK IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__GPIO4_22 IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__CSPI_MOSI IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \
+ IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__GPIO4_23 IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__CSPI_MISO IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__GPIO4_24 IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__CSPI_SS0 IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__GPIO4_25 IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__CSPI_SS1 IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__GPIO4_26 IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__CSPI_SS2 IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__GPIO4_27 IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__CSPI_SS3 IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__GPIO4_28 IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__CSPI_RDY IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__GPIO4_29 IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__GPIO4_30 IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__GPIO4_31 IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
+ IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__GPIO5_5 IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
+ IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__GPIO5_6 IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
+ IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__GPIO5_7 IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
+ IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__GPIO5_8 IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
+ IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__GPIO5_9 IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \
+ IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__GPIO5_10 IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 \
+ IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__GPIO5_11 IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 \
+ IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__GPIO5_12 IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 \
+ IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__GPIO5_13 IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 \
+ IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__GPIO5_14 IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \
+ IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__GPIO5_15 IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__GPIO5_16 IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__GPIO5_17 IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__GPIO5_19 IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_VSYNC__GPIO5_21 IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__GPIO5_22 IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__GPIO5_23 IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__GPIO5_24 IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__GPIO5_25 IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__GPIO5_26 IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x40C, 0x0E0, 5 | MUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__GPIO5_27 IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x410, 0x0E4, 5 | MUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__GPIO5_28 IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__GPIO5_29 IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__GPIO5_30 IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__GPIO5_31 IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__GPIO6_0 IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__GPIO6_1 IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__GPIO6_2 IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__GPIO6_3 IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__GPIO6_4 IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__GPIO6_5 IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__GPIO5_2 IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__CSPI_SS1 IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__USBPHY1_BISTOK IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__GPIO2_30 IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, 5 | MUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__GPIO3_16 IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5 | MUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__GPIO3_17 IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5 | MUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__GPIO3_18 IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5 | MUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__GPIO3_19 IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__GPIO3_20 IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__CSPI_SS0 IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__GPIO3_21 IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__CSPI_SCLK IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5 | MUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__GPIO3_22 IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__CSPI_MISO IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__GPIO3_23 IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__GPIO2_31 IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__GPIO3_24 IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__CSPI_SS2 IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__GPIO3_25 IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__UART3_RXD_MUX IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__CSPI_SS3 IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__GPIO3_26 IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D26__FIRI_RXD IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__IPU_SISG_2 IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__GPIO3_27 IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__UART2_RXD_MUX IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D27__FIRI_TXD IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__IPU_SISG_3 IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__GPIO3_28 IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | MUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__GPIO3_29 IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__CSPI_SS0 IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__GPIO3_30 IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__GPIO3_31 IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__GPIO5_4 IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__IPU_SISG_2 IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__USBPHY2_BVALID IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__GPIO6_6 IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__IPU_SISG_3 IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__GPIO2_17 IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__GPIO2_18 IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__GPIO2_19 IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__GPIO2_20 IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__GPIO2_21 IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__GPIO2_22 IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS0__GPIO2_23 IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS1__GPIO2_24 IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__EMI_WEIM_OE IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__GPIO2_25 IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__USBPHY2_IDDIG IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__EMI_WEIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__GPIO2_26 IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__GPIO2_27 IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__GPIO2_28 IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__GPIO2_29 IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__GPIO3_0 IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__GPIO3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__GPIO3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__GPIO3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__GPIO3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 7 | MUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__GPIO3_7 IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__GPIO3_8 IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__GPIO3_9 IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__GPIO3_10 IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA11__GPIO3_11 IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA12__GPIO3_12 IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA13__GPIO3_13 IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA14__GPIO3_14 IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA15__GPIO3_15 IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WE_B__GPIO6_12 IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RE_B__GPIO6_13 IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_WAIT__GPIO5_0 IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_10__GPIO4_0 IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_10__OSC32k_32K_OUT IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_11__GPIO4_1 IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_12__GPIO4_2 IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_13__GPIO4_3 IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_14__GPIO4_4 IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CLE__GPIO6_7 IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_ALE__GPIO6_8 IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WP_B__GPIO6_9 IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RB0__GPIO6_10 IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS0__GPIO6_11 IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS1__GPIO6_14 IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS1__MLB_MLBCLK IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__GPIO6_15 IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__IPU_SISG_0 IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__MLB_MLBSIG IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__GPIO6_16 IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__IPU_SISG_1 IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__MLB_MLBDAT IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__GPIO1_22 IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__ESAI1_SCKR IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__FEC_COL IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__GPIO1_23 IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__GPIO1_24 IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_CRS_DV__GPIO1_25 IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__GPIO1_26 IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__ESAI1_FST IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__MLB_MLBSIG IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD0__GPIO1_27 IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD0__ESAI1_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TX_EN__GPIO1_28 IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__GPIO1_29 IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__MLB_MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD0__GPIO1_30 IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__GPIO1_31 IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__MLB_MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOW__PATA_DIOW IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOW__GPIO6_17 IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMACK__PATA_DMACK IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMACK__GPIO6_18 IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__PATA_INTRQ IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__GPIO7_2 IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOR__PATA_DIOR IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOR__GPIO7_3 IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DIOR__CAN1_RXCAN IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__GPIO7_4 IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__PATA_IORDY IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__GPIO7_5 IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__ESDHC3_CLK IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__UART1_RTS IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__CAN2_RXCAN IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_0__PATA_DA_0 IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_0__GPIO7_6 IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_0__ESDHC3_RST IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_0__OWIRE_LINE IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__PATA_DA_1 IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__GPIO7_7 IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__ESDHC4_CMD IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__PATA_DA_2 IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__GPIO7_8 IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__ESDHC4_CLK IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_0__PATA_CS_0 IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_0__GPIO7_9 IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_1__PATA_CS_1 IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_1__GPIO7_10 IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__PATA_DATA_0 IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__GPIO2_0 IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__PATA_DATA_1 IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__GPIO2_1 IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__PATA_DATA_2 IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__GPIO2_2 IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__PATA_DATA_3 IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__GPIO2_3 IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__PATA_DATA_4 IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__GPIO2_4 IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__PATA_DATA_5 IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__GPIO2_5 IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__PATA_DATA_8 IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__GPIO2_8 IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__PATA_DATA_9 IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__GPIO2_9 IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__PATA_DATA_10 IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__GPIO2_10 IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__PATA_DATA_11 IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__GPIO2_11 IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__PATA_DATA_12 IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__GPIO2_12 IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__PATA_DATA_13 IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__GPIO2_13 IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__PATA_DATA_14 IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__GPIO2_14 IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__PATA_DATA_15 IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__GPIO2_15 IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__GPIO1_16 IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__GPIO1_17 IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__CSPI_SS0 IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x674, 0x2EC, 0 | MUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__GPIO1_18 IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__GPIO1_19 IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__PWM2_PWMO IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__CSPI_SS1 IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__GPIO1_20 IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__GPIO1_21 IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__PWM1_PWMO IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__CSPI_SS2 IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__GPIO1_10 IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__GPIO1_11 IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__SCC_RANDOM IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__GPIO1_12 IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__KPP_COL_6 IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__SJC_DONE IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__GPIO1_13 IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__KPP_ROW_6 IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__CSPI_SS1 IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__SJC_FAIL IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__GPIO1_14 IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__KPP_COL_7 IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__CSPI_SS0 IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__GPIO1_15 IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__KPP_ROW_7 IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__GPIO1_0 IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__CSU_TD IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__GPIO1_1 IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__ESDHC1_CD IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__GPIO1_9 IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__ESDHC1_WP IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__SCC_FAIL_STATE IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__GPIO1_3 IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, 2 | MUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__GPIO1_6 IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6B4, 0x324, 2 | MUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__ESDHC2_LCTL IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__GPIO1_2 IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__ESDHC2_WP IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__GPIO1_4 IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__ESDHC2_CD IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__GPIO1_5 IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6 | MUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__CCM_PLL1_BYP IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__GPIO1_7 IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_GPIO_7__FIRI_RXD IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__CCM_PLL2_BYP IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL)
+#define MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__CCM_PLL3_BYP IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__GPIO7_11 IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, 6 | MUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__GPIO7_12 IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__IPU_SNOOP2 IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__GPIO7_13 IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__OWIRE_LINE IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__ESDHC1_LCTL IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL)
+
+#endif /* __ASM_ARCH_IOMUX_MX53_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ * <armlinux@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __MACH_IOMUX_V3_H__
+#define __MACH_IOMUX_V3_H__
+
+#include <linux/compiler.h>
+
+/*
+ * build IOMUX_PAD structure
+ *
+ * This iomux scheme is based around pads, which are the physical balls
+ * on the processor.
+ *
+ * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
+ * things like driving strength and pullup/pulldown.
+ * - Each pad can have but not necessarily does have an output routing register
+ * (IOMUXC_SW_MUX_CTL_PAD_x).
+ * - Each pad can have but not necessarily does have an input routing register
+ * (IOMUXC_x_SELECT_INPUT)
+ *
+ * The three register sets do not have a fixed offset to each other,
+ * hence we order this table by pad control registers (which all pads
+ * have) and put the optional i/o routing registers into additional
+ * fields.
+ *
+ * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named
+ * GPIO_<unit>_<num>
+ *
+ * IOMUX/PAD Bit field definitions
+ *
+ * MUX_CTRL_OFS: 0..11 (12)
+ * PAD_CTRL_OFS: 12..23 (12)
+ * SEL_INPUT_OFS: 24..35 (12)
+ * MUX_MODE + SION: 36..40 (5)
+ * PAD_CTRL + NO_PAD_CTRL: 41..57 (17)
+ * SEL_INP: 58..61 (4)
+ * reserved: 63 (1)
+*/
+
+typedef u64 iomux_v3_cfg_t;
+
+#define MUX_CTRL_OFS_SHIFT 0
+#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
+#define MUX_PAD_CTRL_OFS_SHIFT 12
+#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT)
+#define MUX_SEL_INPUT_OFS_SHIFT 24
+#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT)
+
+#define MUX_MODE_SHIFT 36
+#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
+#define MUX_PAD_CTRL_SHIFT 41
+#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT)
+#define MUX_SEL_INPUT_SHIFT 58
+#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
+
+#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+
+#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \
+ _sel_input, _pad_ctrl) \
+ (((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
+ ((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) | \
+ ((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
+ ((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
+ ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
+ ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT))
+
+#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad))
+/*
+ * Use to set PAD control
+ */
+
+#define NO_PAD_CTRL (1 << 16)
+#define PAD_CTL_DVS (1 << 13)
+#define PAD_CTL_HYS (1 << 8)
+
+#define PAD_CTL_PKE (1 << 7)
+#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
+#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
+
+#define PAD_CTL_ODE (1 << 3)
+
+#define PAD_CTL_DSE_LOW (0 << 1)
+#define PAD_CTL_DSE_MED (1 << 1)
+#define PAD_CTL_DSE_HIGH (2 << 1)
+#define PAD_CTL_DSE_MAX (3 << 1)
+
+#define PAD_CTL_SRE_FAST (1 << 0)
+#define PAD_CTL_SRE_SLOW (0 << 0)
+
+#define IOMUX_CONFIG_SION (0x1 << 4)
+
+/*
+ * sets up a single pad in the iomuxer
+ */
+int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
+
+/*
+ * sets up mutliple pads
+ * convenient way to call the above function with tables
+ */
+int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list, unsigned count);
+
+#endif /* __MACH_IOMUX_V3_H__*/
+
#define MUX_IO_P 29
#define MUX_IO_I 24
-#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
- GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
+#define IOMUX_TO_GPIO(pin) ((((unsigned int)(pin) >> MUX_IO_P) * \
+ GPIO_NUM_PIN) + (((pin) >> MUX_IO_I) & \
((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
((mi) << MUX_I) | \
- ((pi - PAD_I_START) << PAD_I) | \
+ (((pi) - PAD_I_START) << PAD_I) | \
((ga) << GPIO_I))
#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
_MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
-#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
-#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
+#define PIN_TO_IOMUX_MUX(pin) (((pin) >> MUX_I) & PIN_TO_MUX_MASK)
+#define PIN_TO_IOMUX_PAD(pin) (((pin) >> PAD_I) & PIN_TO_PAD_MASK)
+#define PIN_TO_ALT_GPIO(pin) (((pin) >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
/*
unsigned imx_ddr_size(void);
void sdelay(unsigned long);
void set_chipselect_size(int const);
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
/*
* Initializes on-chip ethernet controllers.
MXC_I2C_CLK,
};
+
+struct clk {
+ const char *name;
+ int id;
+ /* Source clock this clk depends on */
+ struct clk *parent;
+ /* Secondary clock to enable/disable with this clock */
+ struct clk *secondary;
+ /* Current clock rate */
+ unsigned long rate;
+ /* Reference count of clock enable/disable */
+ __s8 usecount;
+ /* Register bit position for clock's enable/disable control. */
+ u8 enable_shift;
+ /* Register address for clock's enable/disable control. */
+ void *enable_reg;
+ u32 flags;
+ /*
+ * Function ptr to recalculate the clock's rate based on parent
+ * clock's rate
+ */
+ void (*recalc) (struct clk *);
+ /*
+ * Function ptr to set the clock to a new rate. The rate must match a
+ * supported rate returned from round_rate. Leave blank if clock is not
+ * programmable
+ */
+ int (*set_rate) (struct clk *, unsigned long);
+ /*
+ * Function ptr to round the requested clock rate to the nearest
+ * supported rate that is less than or equal to the requested rate.
+ */
+ unsigned long (*round_rate) (struct clk *, unsigned long);
+ /*
+ * Function ptr to enable the clock. Leave blank if clock can not
+ * be gated.
+ */
+ int (*enable) (struct clk *);
+ /*
+ * Function ptr to disable the clock. Leave blank if clock can not
+ * be gated.
+ */
+ void (*disable) (struct clk *);
+ /* Function ptr to set the parent clock of the clock. */
+ int (*set_parent) (struct clk *, struct clk *);
+};
+
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
+int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk);
void enable_usboh3_clk(unsigned char enable);
int enable_sata_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
+void ipu_clk_enable(void);
+void ipu_clk_disable(void);
+void ocotp_clk_enable(void);
+void ocotp_clk_disable(void);
#endif /* __ASM_ARCH_CLOCK_H */
u32 cs1cdr;
u32 cs2cdr;
u32 cdcdr; /* 0x0030 */
- u32 chsccdr;
+ u32 chscdr;
u32 cscdr2;
u32 cscdr3;
u32 cscdr4; /* 0x0040 */
u32 CCGR6; /* 0x0080 */
u32 CCGR7;
u32 cmeor;
- u32 resv[0xfdd];
- u32 analog_pll_sys; /* 0x4000 */
- u32 analog_pll_sys_set;
- u32 analog_pll_sys_clr;
- u32 analog_pll_sys_tog;
- u32 analog_usb1_pll_480_ctrl; /* 0x4010 */
- u32 analog_usb1_pll_480_ctrl_set;
- u32 analog_usb1_pll_480_ctrl_clr;
- u32 analog_usb1_pll_480_ctrl_tog;
- u32 analog_reserved0[4];
- u32 analog_pll_528; /* 0x4030 */
- u32 analog_pll_528_set;
- u32 analog_pll_528_clr;
- u32 analog_pll_528_tog;
- u32 analog_pll_528_ss; /* 0x4040 */
- u32 analog_reserved1[3];
- u32 analog_pll_528_num; /* 0x4050 */
- u32 analog_reserved2[3];
- u32 analog_pll_528_denom; /* 0x4060 */
- u32 analog_reserved3[3];
- u32 analog_pll_audio; /* 0x4070 */
- u32 analog_pll_audio_set;
- u32 analog_pll_audio_clr;
- u32 analog_pll_audio_tog;
- u32 analog_pll_audio_num; /* 0x4080*/
- u32 analog_reserved4[3];
- u32 analog_pll_audio_denom; /* 0x4090 */
- u32 analog_reserved5[3];
- u32 analog_pll_video; /* 0x40a0 */
- u32 analog_pll_video_set;
- u32 analog_pll_video_clr;
- u32 analog_pll_video_tog;
- u32 analog_pll_video_num; /* 0x40b0 */
- u32 analog_reserved6[3];
- u32 analog_pll_vedio_denon; /* 0x40c0 */
- u32 analog_reserved7[7];
- u32 analog_pll_enet; /* 0x40e0 */
- u32 analog_pll_enet_set;
- u32 analog_pll_enet_clr;
- u32 analog_pll_enet_tog;
- u32 analog_pfd_480; /* 0x40f0 */
- u32 analog_pfd_480_set;
- u32 analog_pfd_480_clr;
- u32 analog_pfd_480_tog;
- u32 analog_pfd_528; /* 0x4100 */
- u32 analog_pfd_528_set;
- u32 analog_pfd_528_clr;
- u32 analog_pfd_528_tog;
};
/* Define the bits in register CCR */
#define MXC_CCM_CCR_RBC_EN (1 << 27)
-#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
+#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << CCR_REG_BYPASS_CNT_OFFSET)
#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
-#define MXC_CCM_CCR_WB_COUNT_MASK 0x7
+#define MXC_CCM_CCR_WB_COUNT_MASK (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
#define MXC_CCM_CCR_COSC_EN (1 << 12)
-#define MXC_CCM_CCR_OSCNT_MASK 0xFF
+#define MXC_CCM_CCR_OSCNT_MASK (0xFF << MXC_CCM_CCR_OSCNT_OFFSET)
#define MXC_CCM_CCR_OSCNT_OFFSET 0
/* Define the bits in register CCDR */
/* Define the bits in register CACRR */
#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
-#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
+#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7 << MXC_CCM_CACRR_ARM_PODF_OFFSET)
/* Define the bits in register CBCDR */
-#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
+#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET)
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
-#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
-#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET)
#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
-#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET)
#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
-#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
+#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << MXC_CCM_CBCDR_IPG_PODF_OFFSET)
#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
#define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
-#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
+#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET)
#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
-#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET)
#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
/* Define the bits in register CBCMR */
-#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
-#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
+#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
-#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET)
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
-#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
-#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
+#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
-#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET)
#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
-#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
-#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
/* Define the bits in register CSCMR1 */
-#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
-#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
+#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET)
#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
-#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET)
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
-#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
+#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET)
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
-#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
+#define MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET 0
+#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET)
/* Define the bits in register CSCMR2 */
-#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET)
#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
/* Define the bits in register CSCDR1 */
-#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
+#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
-#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
+#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET)
#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
-#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET)
#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
-#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET)
#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
-#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
+#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET)
#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
/* Define the bits in register CS1CDR */
-#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET)
#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
-#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
+#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET)
#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
-#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET)
#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET)
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET)
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
/* Define the bits in register CS2CDR */
-#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
-#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
-#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
+#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
-#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
+#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET)
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET)
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
/* Define the bits in register CDCDR */
-#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
+#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET)
#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19
-#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET)
#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
-#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET)
#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
/* Define the bits in register CHSCCDR */
-#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI1_PRE_CLK_SEL_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
-#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
-#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
-#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI0_PRE_CLK_SEL_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
-#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
-#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
-#define CHSCCDR_CLK_SEL_LDB_DI0 3
-#define CHSCCDR_PODF_DIVIDE_BY_3 2
-#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
-
/* Define the bits in register CSCDR2 */
-#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
+#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
-#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
-#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
-#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
-#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
-#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
-#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
-#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
-#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
-#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
-#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
+#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI1_PRE_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
+#define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET)
+#define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET 12
+#define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET 9
+#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI0_PRE_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
+#define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET)
+#define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET 3
+#define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET 0
/* Define the bits in register CSCDR3 */
-#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET)
#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
-#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET)
#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
-#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
+#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET)
#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
-#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
+#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET)
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
/* Define the bits in register CDHIPR */
#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
-#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1
+#define MXC_CCM_CDHIPR_AXI_PODF_BUSY (1 << 0)
/* Define the bits in register CLPCR */
#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17)
#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
-#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
+#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET)
#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
#define MXC_CCM_CLPCR_VSTBY (1 << 8)
#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
#define MXC_CCM_CLPCR_SBYOS (1 << 6)
#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET)
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
-#define MXC_CCM_CLPCR_LPM_MASK 0x3
+#define MXC_CCM_CLPCR_LPM_MASK (0x3 << MXC_CCM_CLPCR_LPM_OFFSET)
#define MXC_CCM_CLPCR_LPM_OFFSET 0
/* Define the bits in register CISR */
#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
#define MXC_CCM_CISR_COSC_READY (1 << 6)
-#define MXC_CCM_CISR_LRF_PLL 1
+#define MXC_CCM_CISR_LRF_PLL (1 << 0)
/* Define the bits in register CIMR */
#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22)
#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
-#define MXC_CCM_CIMR_MASK_LRF_PLL 1
+#define MXC_CCM_CIMR_MASK_LRF_PLL (1 << 0)
/* Define the bits in register CCOSR */
#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
-#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
+#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET)
#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
-#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
+#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET)
#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
-#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
+#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET)
#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
-#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
+#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF << MXC_CCM_CCOSR_CKOL_SEL_OFFSET)
#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
/* Define the bits in registers CGPR */
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
-#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
+#define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1 << 0)
/* Define the bits in registers CCGRx */
#define MXC_CCM_CCGR_CG_MASK 3
-#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
-#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
-#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
-#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
-#define MXC_CCM_CCGR0_APBHDMA HCLK_OFFSET 4
-#define MXC_CCM_CCGR0_AMASK (3<<MXC_CCM_CCGR0_APBHDMA)
-#define MXC_CCM_CCGR0_ASRC_OFFSET 6
-#define MXC_CCM_CCGR0_ASRC_MASK (3<<MXC_CCM_CCGR0_ASRC_OFFSET)
-#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
-#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3<<MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
-#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
-#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
-#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
-#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
-#define MXC_CCM_CCGR0_CAN1_OFFSET 14
-#define MXC_CCM_CCGR0_CAN1_MASK (3<<MXC_CCM_CCGR0_CAN1_OFFSET)
-#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
-#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
-#define MXC_CCM_CCGR0_CAN2_OFFSET 18
-#define MXC_CCM_CCGR0_CAN2_MASK (3<<MXC_CCM_CCGR0_CAN2_OFFSET)
-#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
-#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
-#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
-#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3<<MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
-#define MXC_CCM_CCGR0_DCIC1_OFFSET 24
-#define MXC_CCM_CCGR0_DCIC1_MASK (3<<MXC_CCM_CCGR0_DCIC1_OFFSET)
-#define MXC_CCM_CCGR0_DCIC2_OFFSET 26
-#define MXC_CCM_CCGR0_DCIC2_MASK (3<<MXC_CCM_CCGR0_DCIC2_OFFSET)
-#define MXC_CCM_CCGR0_DTCP_OFFSET 28
-#define MXC_CCM_CCGR0_DTCP_MASK (3<<MXC_CCM_CCGR0_DTCP_OFFSET)
-
-#define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
-#define MXC_CCM_CCGR1_ECSPI1S_MASK (3<<MXC_CCM_CCGR1_ECSPI1S_OFFSET)
-#define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
-#define MXC_CCM_CCGR1_ECSPI2S_MASK (3<<MXC_CCM_CCGR1_ECSPI2S_OFFSET)
-#define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
-#define MXC_CCM_CCGR1_ECSPI3S_MASK (3<<MXC_CCM_CCGR1_ECSPI3S_OFFSET)
-#define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
-#define MXC_CCM_CCGR1_ECSPI4S_MASK (3<<MXC_CCM_CCGR1_ECSPI4S_OFFSET)
-#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
-#define MXC_CCM_CCGR1_ECSPI5S_MASK (3<<MXC_CCM_CCGR1_ECSPI5S_OFFSET)
-#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
-#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3<<MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
-#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
-#define MXC_CCM_CCGR1_EPIT1S_MASK (3<<MXC_CCM_CCGR1_EPIT1S_OFFSET)
-#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
-#define MXC_CCM_CCGR1_EPIT2S_MASK (3<<MXC_CCM_CCGR1_EPIT2S_OFFSET)
-#define MXC_CCM_CCGR1_ESAIS_OFFSET 16
-#define MXC_CCM_CCGR1_ESAIS_MASK (3<<MXC_CCM_CCGR1_ESAIS_OFFSET)
-#define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
-#define MXC_CCM_CCGR1_GPT_BUS_MASK (3<<MXC_CCM_CCGR1_GPT_BUS_OFFSET)
-#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
-#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3<<MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
-#define MXC_CCM_CCGR1_GPU2D_OFFSET 24
-#define MXC_CCM_CCGR1_GPU2D_MASK (3<<MXC_CCM_CCGR1_GPU2D_OFFSET)
-#define MXC_CCM_CCGR1_GPU3D_OFFSET 26
-#define MXC_CCM_CCGR1_GPU3D_MASK (3<<MXC_CCM_CCGR1_GPU3D_OFFSET)
-
-#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
-#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
-#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
-#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
-#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
-#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
-#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
-#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
-#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
-#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
-#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
-#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3<<MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
-#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
-#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3<<MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
-#define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
-#define MXC_CCM_CCGR2_IPMUX1_MASK (3<<MXC_CCM_CCGR2_IPMUX1_OFFSET)
-#define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
-#define MXC_CCM_CCGR2_IPMUX2_MASK (3<<MXC_CCM_CCGR2_IPMUX2_OFFSET)
-#define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
-#define MXC_CCM_CCGR2_IPMUX3_MASK (3<<MXC_CCM_CCGR2_IPMUX3_OFFSET)
-#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
-#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
-#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
-#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
-#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
-#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3<<MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
-
-#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
-#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
-#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
-#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
-#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
-#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
-#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
-#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
-#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
-#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
-#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
-#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
-#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
-#define MXC_CCM_CCGR3_LDB_DI0_MASK (3<<MXC_CCM_CCGR3_LDB_DI0_OFFSET)
-#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
-#define MXC_CCM_CCGR3_LDB_DI1_MASK (3<<MXC_CCM_CCGR3_LDB_DI1_OFFSET)
-#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
-#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3<<MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
-#define MXC_CCM_CCGR3_MLB_OFFSET 18
-#define MXC_CCM_CCGR3_MLB_MASK (3<<MXC_CCM_CCGR3_MLB_OFFSET)
-#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
-#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
-#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
-#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
-#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
-#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
-#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
-#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
-#define MXC_CCM_CCGR3_OCRAM_OFFSET 28
-#define MXC_CCM_CCGR3_OCRAM_MASK (3<<MXC_CCM_CCGR3_OCRAM_OFFSET)
-#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
-#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3<<MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
-
-#define MXC_CCM_CCGR4_PCIE_OFFSET 0
-#define MXC_CCM_CCGR4_PCIE_MASK (3<<MXC_CCM_CCGR4_PCIE_OFFSET)
-#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
-#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
-#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
-#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
-#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
-#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
-#define MXC_CCM_CCGR4_PWM1_OFFSET 16
-#define MXC_CCM_CCGR4_PWM1_MASK (3<<MXC_CCM_CCGR4_PWM1_OFFSET)
-#define MXC_CCM_CCGR4_PWM2_OFFSET 18
-#define MXC_CCM_CCGR4_PWM2_MASK (3<<MXC_CCM_CCGR4_PWM2_OFFSET)
-#define MXC_CCM_CCGR4_PWM3_OFFSET 20
-#define MXC_CCM_CCGR4_PWM3_MASK (3<<MXC_CCM_CCGR4_PWM3_OFFSET)
-#define MXC_CCM_CCGR4_PWM4_OFFSET 22
-#define MXC_CCM_CCGR4_PWM4_MASK (3<<MXC_CCM_CCGR4_PWM4_OFFSET)
-#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
-#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
-
-#define MXC_CCM_CCGR5_ROM_OFFSET 0
-#define MXC_CCM_CCGR5_ROM_MASK (3<<MXC_CCM_CCGR5_ROM_OFFSET)
-#define MXC_CCM_CCGR5_SATA_OFFSET 4
-#define MXC_CCM_CCGR5_SATA_MASK (3<<MXC_CCM_CCGR5_SATA_OFFSET)
-#define MXC_CCM_CCGR5_SDMA_OFFSET 6
-#define MXC_CCM_CCGR5_SDMA_MASK (3<<MXC_CCM_CCGR5_SDMA_OFFSET)
-#define MXC_CCM_CCGR5_SPBA_OFFSET 12
-#define MXC_CCM_CCGR5_SPBA_MASK (3<<MXC_CCM_CCGR5_SPBA_OFFSET)
-#define MXC_CCM_CCGR5_SPDIF_OFFSET 14
-#define MXC_CCM_CCGR5_SPDIF_MASK (3<<MXC_CCM_CCGR5_SPDIF_OFFSET)
-#define MXC_CCM_CCGR5_SSI1_OFFSET 18
-#define MXC_CCM_CCGR5_SSI1_MASK (3<<MXC_CCM_CCGR5_SSI1_OFFSET)
-#define MXC_CCM_CCGR5_SSI2_OFFSET 20
-#define MXC_CCM_CCGR5_SSI2_MASK (3<<MXC_CCM_CCGR5_SSI2_OFFSET)
-#define MXC_CCM_CCGR5_SSI3_OFFSET 22
-#define MXC_CCM_CCGR5_SSI3_MASK (3<<MXC_CCM_CCGR5_SSI3_OFFSET)
-#define MXC_CCM_CCGR5_UART_OFFSET 24
-#define MXC_CCM_CCGR5_UART_MASK (3<<MXC_CCM_CCGR5_UART_OFFSET)
-#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
-#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3<<MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
-
-#define MXC_CCM_CCGR6_USBOH3_OFFSET 0
-#define MXC_CCM_CCGR6_USBOH3_MASK (3<<MXC_CCM_CCGR6_USBOH3_OFFSET)
-#define MXC_CCM_CCGR6_USDHC1_OFFSET 2
-#define MXC_CCM_CCGR6_USDHC1_MASK (3<<MXC_CCM_CCGR6_USDHC1_OFFSET)
-#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
-#define MXC_CCM_CCGR6_USDHC2_MASK (3<<MXC_CCM_CCGR6_USDHC2_OFFSET)
-#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
-#define MXC_CCM_CCGR6_USDHC3_MASK (3<<MXC_CCM_CCGR6_USDHC3_OFFSET)
-#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
-#define MXC_CCM_CCGR6_USDHC4_MASK (3<<MXC_CCM_CCGR6_USDHC4_OFFSET)
-#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
-#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3<<MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
-#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
-#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3<<MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
-
-#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
-#define BP_ANADIG_PLL_SYS_RSVD0 20
-#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
-#define BF_ANADIG_PLL_SYS_RSVD0(v) \
- (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
-#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
-#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
-#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
-#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
-#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
-#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
-#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
-#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
-#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
-#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
-#define BP_ANADIG_PLL_SYS_DIV_SELECT 0
-#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
-#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
- (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
-
-#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
-#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
-#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
-#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
- (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
-#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
-#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
-#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
-#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
-#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
-#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
-#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
-#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
-#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
-#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
-#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
-#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
-#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
- (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
-#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
-#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
-#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
- (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
-
-#define BM_ANADIG_PLL_528_LOCK 0x80000000
-#define BP_ANADIG_PLL_528_RSVD1 19
-#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
-#define BF_ANADIG_PLL_528_RSVD1(v) \
- (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
-#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
-#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
-#define BM_ANADIG_PLL_528_BYPASS 0x00010000
-#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_528_ENABLE 0x00002000
-#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
-#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
-#define BM_ANADIG_PLL_528_HALF_CP 0x00000200
-#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
-#define BM_ANADIG_PLL_528_HALF_LF 0x00000080
-#define BP_ANADIG_PLL_528_RSVD0 1
-#define BM_ANADIG_PLL_528_RSVD0 0x0000007E
-#define BF_ANADIG_PLL_528_RSVD0(v) \
- (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
-#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
-
-#define BP_ANADIG_PLL_528_SS_STOP 16
-#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
-#define BF_ANADIG_PLL_528_SS_STOP(v) \
- (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
-#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
-#define BP_ANADIG_PLL_528_SS_STEP 0
-#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
-#define BF_ANADIG_PLL_528_SS_STEP(v) \
- (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
-
-#define BP_ANADIG_PLL_528_NUM_RSVD0 30
-#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
-#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
-#define BP_ANADIG_PLL_528_NUM_A 0
-#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
-#define BF_ANADIG_PLL_528_NUM_A(v) \
- (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
-
-#define BP_ANADIG_PLL_528_DENOM_RSVD0 30
-#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
-#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
-#define BP_ANADIG_PLL_528_DENOM_B 0
-#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
-#define BF_ANADIG_PLL_528_DENOM_B(v) \
- (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
-
-#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
-#define BP_ANADIG_PLL_AUDIO_RSVD0 22
-#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
-#define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
- (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
-#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
-#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
-#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
-#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
- (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
-#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
-#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
-#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
-#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
-#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
-#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
-#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
-#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
-#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
-#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
-#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
-#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
- (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
-
-#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
-#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
-#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
-#define BP_ANADIG_PLL_AUDIO_NUM_A 0
-#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
-#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
- (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
-
-#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
-#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
-#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
-#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
-#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
-#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
- (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
-
-#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
-#define BP_ANADIG_PLL_VIDEO_RSVD0 22
-#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
-#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
- (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
-#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
-#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
-#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
-#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
- (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
-#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
-#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
-#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
-#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
-#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
-#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
-#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
-#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
-#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
-#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
-#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
-#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
- (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
-
-#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
-#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
-#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
-#define BP_ANADIG_PLL_VIDEO_NUM_A 0
-#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
-#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
- (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
-
-#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
-#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
-#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
- (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
-#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
-#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
-#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
- (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
-
-#define BM_ANADIG_PLL_ENET_LOCK 0x80000000
-#define BP_ANADIG_PLL_ENET_RSVD1 21
-#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
-#define BF_ANADIG_PLL_ENET_RSVD1(v) \
- (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
-#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
-#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
-#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
-#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
-#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
-#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
-#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
-#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
- (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
-#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
-#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
-#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
-#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
-#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
-#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
-#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
-#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
-#define BP_ANADIG_PLL_ENET_RSVD0 2
-#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
-#define BF_ANADIG_PLL_ENET_RSVD0(v) \
- (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
-#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
-#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
-#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
- (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
-
-#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
-#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
-#define BP_ANADIG_PFD_480_PFD3_FRAC 24
-#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
-#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
- (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
+#define MXC_CCM_CCGR0_CG14_OFFSET 28
+#define MXC_CCM_CCGR0_CG14_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG14_OFFSET)
+#define MXC_CCM_CCGR0_CG13_OFFSET 26
+#define MXC_CCM_CCGR0_CG13_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG13_OFFSET)
+#define MXC_CCM_CCGR0_CG12_OFFSET 24
+#define MXC_CCM_CCGR0_CG12_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG12_OFFSET)
+#define MXC_CCM_CCGR0_CG11_OFFSET 22
+#define MXC_CCM_CCGR0_CG11_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG11_OFFSET)
+#define MXC_CCM_CCGR0_CG10_OFFSET 20
+#define MXC_CCM_CCGR0_CG10_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG10_OFFSET)
+#define MXC_CCM_CCGR0_CG9_OFFSET 18
+#define MXC_CCM_CCGR0_CG9_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG9_OFFSET)
+#define MXC_CCM_CCGR0_CG8_OFFSET 16
+#define MXC_CCM_CCGR0_CG8_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG8_OFFSET)
+#define MXC_CCM_CCGR0_CG7_OFFSET 14
+#define MXC_CCM_CCGR0_CG6_OFFSET 12
+#define MXC_CCM_CCGR0_CG5_OFFSET 10
+#define MXC_CCM_CCGR0_CG5_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG5_OFFSET)
+#define MXC_CCM_CCGR0_CG4_OFFSET 8
+#define MXC_CCM_CCGR0_CG4_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG4_OFFSET)
+#define MXC_CCM_CCGR0_CG3_OFFSET 6
+#define MXC_CCM_CCGR0_CG3_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG3_OFFSET)
+#define MXC_CCM_CCGR0_CG2_OFFSET 4
+#define MXC_CCM_CCGR0_CG2_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG2_OFFSET)
+#define MXC_CCM_CCGR0_CG1_OFFSET 2
+#define MXC_CCM_CCGR0_CG1_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG1_OFFSET)
+#define MXC_CCM_CCGR0_CG0_OFFSET 0
+#define MXC_CCM_CCGR0_CG0_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET)
+
+#define MXC_CCM_CCGR0_DTCP_OFFSET MXC_CCM_CCGR0_CG14_OFFSET
+#define MXC_CCM_CCGR0_DCIC2_OFFSET MXC_CCM_CCGR0_CG13_OFFSET
+#define MXC_CCM_CCGR0_DCIC1_OFFSET MXC_CCM_CCGR0_CG12_OFFSET
+#define MXC_CCM_CCGR0_ARM_DBG_OFFSET MXC_CCM_CCGR0_CG11_OFFSET
+#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET MXC_CCM_CCGR0_CG10_OFFSET
+#define MXC_CCM_CCGR0_CAN2_OFFSET MXC_CCM_CCGR0_CG9_OFFSET
+#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET MXC_CCM_CCGR0_CG8_OFFSET
+#define MXC_CCM_CCGR0_CAN1_OFFSET MXC_CCM_CCGR0_CG7_OFFSET
+#define MXC_CCM_CCGR0_CAAM_IPG_OFFSET MXC_CCM_CCGR0_CG6_OFFSET
+#define MXC_CCM_CCGR0_CAAM_ACLK_OFFSET MXC_CCM_CCGR0_CG5_OFFSET
+#define MXC_CCM_CCGR0_CAAM_SEC_MEM_OFFSET MXC_CCM_CCGR0_CG4_OFFSET
+#define MXC_CCM_CCGR0_ASRC_OFFSET MXC_CCM_CCGR0_CG3_OFFSET
+#define MXC_CCM_CCGR0_APBHDMA_OFFSET MXC_CCM_CCGR0_CG2_OFFSET
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET MXC_CCM_CCGR0_CG1_OFFSET
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET MXC_CCM_CCGR0_CG0_OFFSET
+
+#define MXC_CCM_CCGR1_CG15_OFFSET 30
+#define MXC_CCM_CCGR1_CG14_OFFSET 28
+#define MXC_CCM_CCGR1_CG13_OFFSET 26
+#define MXC_CCM_CCGR1_CG12_OFFSET 24
+#define MXC_CCM_CCGR1_CG11_OFFSET 22
+#define MXC_CCM_CCGR1_CG10_OFFSET 20
+#define MXC_CCM_CCGR1_CG9_OFFSET 18
+#define MXC_CCM_CCGR1_CG8_OFFSET 16
+#define MXC_CCM_CCGR1_CG7_OFFSET 14
+#define MXC_CCM_CCGR1_CG6_OFFSET 12
+#define MXC_CCM_CCGR1_CG5_OFFSET 10
+#define MXC_CCM_CCGR1_CG4_OFFSET 8
+#define MXC_CCM_CCGR1_CG3_OFFSET 6
+#define MXC_CCM_CCGR1_CG2_OFFSET 4
+#define MXC_CCM_CCGR1_CG1_OFFSET 2
+#define MXC_CCM_CCGR1_CG0_OFFSET 0
+
+#define MXC_CCM_CCGR1_GPU3D_OFFSET MXC_CCM_CCGR1_CG13_OFFSET
+#define MXC_CCM_CCGR1_GPU2D_OFFSET MXC_CCM_CCGR1_CG12_OFFSET
+#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET MXC_CCM_CCGR1_CG11_OFFSET
+#define MXC_CCM_CCGR1_GPT_OFFSET MXC_CCM_CCGR1_CG10_OFFSET
+#define MXC_CCM_CCGR1_ESAI_OFFSET MXC_CCM_CCGR1_CG8_OFFSET
+#define MXC_CCM_CCGR1_EPIT2_OFFSET MXC_CCM_CCGR1_CG7_OFFSET
+#define MXC_CCM_CCGR1_EPIT1_OFFSET MXC_CCM_CCGR1_CG6_OFFSET
+#define MXC_CCM_CCGR1_ENET_OFFSET MXC_CCM_CCGR1_CG5_OFFSET
+#define MXC_CCM_CCGR1_ECSPI5_OFFSET MXC_CCM_CCGR1_CG4_OFFSET
+#define MXC_CCM_CCGR1_ECSPI4_OFFSET MXC_CCM_CCGR1_CG3_OFFSET
+#define MXC_CCM_CCGR1_ECSPI3_OFFSET MXC_CCM_CCGR1_CG2_OFFSET
+#define MXC_CCM_CCGR1_ECSPI2_OFFSET MXC_CCM_CCGR1_CG1_OFFSET
+#define MXC_CCM_CCGR1_ECSPI1_OFFSET MXC_CCM_CCGR1_CG0_OFFSET
+
+#define MXC_CCM_CCGR2_CG13_OFFSET 26
+#define MXC_CCM_CCGR2_CG12_OFFSET 24
+#define MXC_CCM_CCGR2_CG11_OFFSET 22
+#define MXC_CCM_CCGR2_CG10_OFFSET 20
+#define MXC_CCM_CCGR2_CG9_OFFSET 18
+#define MXC_CCM_CCGR2_CG8_OFFSET 16
+#define MXC_CCM_CCGR2_CG7_OFFSET 14
+#define MXC_CCM_CCGR2_CG6_OFFSET 12
+#define MXC_CCM_CCGR2_CG6_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR2_CG6_OFFSET)
+#define MXC_CCM_CCGR2_CG5_OFFSET 10
+#define MXC_CCM_CCGR2_CG4_OFFSET 8
+#define MXC_CCM_CCGR2_CG3_OFFSET 6
+#define MXC_CCM_CCGR2_CG2_OFFSET 4
+#define MXC_CCM_CCGR2_CG1_OFFSET 2
+#define MXC_CCM_CCGR2_CG0_OFFSET 0
+
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_OFFSET MXC_CCM_CCGR2_CG13_OFFSET
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_TZASC2_OFFSET MXC_CCM_CCGR2_CG12_OFFSET
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1__OFFSET MXC_CCM_CCGR2_CG11_OFFSET
+#define MXC_CCM_CCGR2_IPMUX3_OFFSET MXC_CCM_CCGR2_CG10_OFFSET
+#define MXC_CCM_CCGR2_IPMUX2_OFFSET MXC_CCM_CCGR2_CG9_OFFSET
+#define MXC_CCM_CCGR2_IPMUX1_OFFSET MXC_CCM_CCGR2_CG8_OFFSET
+#define MXC_CCM_CCGR2_IOMUX_IPT_OFFSET MXC_CCM_CCGR2_CG7_OFFSET
+#define MXC_CCM_CCGR2_OCOTP_OFFSET MXC_CCM_CCGR2_CG6_OFFSET
+#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET MXC_CCM_CCGR2_CG5_OFFSET
+#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET MXC_CCM_CCGR2_CG4_OFFSET
+#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET MXC_CCM_CCGR2_CG3_OFFSET
+#define MXC_CCM_CCGR2_HDMI_TX_ISFR_OFFSET MXC_CCM_CCGR2_CG2_OFFSET
+#define MXC_CCM_CCGR2_HDMI_TX_IAHB_OFFSET MXC_CCM_CCGR2_CG0_OFFSET
+
+#define MXC_CCM_CCGR3_CG15_OFFSET 30
+#define MXC_CCM_CCGR3_CG14_OFFSET 28
+#define MXC_CCM_CCGR3_CG13_OFFSET 26
+#define MXC_CCM_CCGR3_CG12_OFFSET 24
+#define MXC_CCM_CCGR3_CG11_OFFSET 22
+#define MXC_CCM_CCGR3_CG10_OFFSET 20
+#define MXC_CCM_CCGR3_CG9_OFFSET 18
+#define MXC_CCM_CCGR3_CG8_OFFSET 16
+#define MXC_CCM_CCGR3_CG7_OFFSET 14
+#define MXC_CCM_CCGR3_CG6_OFFSET 12
+#define MXC_CCM_CCGR3_CG5_OFFSET 10
+#define MXC_CCM_CCGR3_CG4_OFFSET 8
+#define MXC_CCM_CCGR3_CG3_OFFSET 6
+#define MXC_CCM_CCGR3_CG2_OFFSET 4
+#define MXC_CCM_CCGR3_CG1_OFFSET 2
+#define MXC_CCM_CCGR3_CG0_OFFSET 0
+#define MXC_CCM_CCGR3_CG0_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR3_CG0_OFFSET)
+
+#define MXC_CCM_CCGR3_OPENVGAXI_OFFSET MXC_CCM_CCGR3_CG15_OFFSET
+#define MXC_CCM_CCGR3_OCRAM_OFFSET MXC_CCM_CCGR3_CG14_OFFSET
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_P1_OFFSET MXC_CCM_CCGR3_CG13_OFFSET
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_P0_OFFSET MXC_CCM_CCGR3_CG12_OFFSET
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_P1_OFFSET MXC_CCM_CCGR3_CG11_OFFSET
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_P0_OFFSET MXC_CCM_CCGR3_CG10_OFFSET
+#define MXC_CCM_CCGR3_MLB_OFFSET MXC_CCM_CCGR3_CG9_OFFSET
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET MXC_CCM_CCGR3_CG8_OFFSET
+#define MXC_CCM_CCGR3_LDB_DI1_OFFSET MXC_CCM_CCGR3_CG7_OFFSET
+#define MXC_CCM_CCGR3_LDB_DI0_OFFSET MXC_CCM_CCGR3_CG6_OFFSET
+#define MXC_CCM_CCGR3_IPU2_DI1_OFFSET MXC_CCM_CCGR3_CG5_OFFSET
+#define MXC_CCM_CCGR3_IPU2_DI0_OFFSET MXC_CCM_CCGR3_CG4_OFFSET
+#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET MXC_CCM_CCGR3_CG3_OFFSET
+#define MXC_CCM_CCGR3_IPU1_DI1_OFFSET MXC_CCM_CCGR3_CG2_OFFSET
+#define MXC_CCM_CCGR3_IPU1_DI0_OFFSET MXC_CCM_CCGR3_CG1_OFFSET
+#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET MXC_CCM_CCGR3_CG0_OFFSET
+
+#define MXC_CCM_CCGR4_CG15_OFFSET 30
+#define MXC_CCM_CCGR4_CG14_OFFSET 28
+#define MXC_CCM_CCGR4_CG13_OFFSET 26
+#define MXC_CCM_CCGR4_CG12_OFFSET 24
+#define MXC_CCM_CCGR4_CG11_OFFSET 22
+#define MXC_CCM_CCGR4_CG10_OFFSET 20
+#define MXC_CCM_CCGR4_CG9_OFFSET 18
+#define MXC_CCM_CCGR4_CG8_OFFSET 16
+#define MXC_CCM_CCGR4_CG7_OFFSET 14
+#define MXC_CCM_CCGR4_CG6_OFFSET 12
+#define MXC_CCM_CCGR4_CG5_OFFSET 10
+#define MXC_CCM_CCGR4_CG4_OFFSET 8
+#define MXC_CCM_CCGR4_CG3_OFFSET 6
+#define MXC_CCM_CCGR4_CG2_OFFSET 4
+#define MXC_CCM_CCGR4_CG1_OFFSET 2
+#define MXC_CCM_CCGR4_CG0_OFFSET 0
+
+#if 0
+#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG15_OFFSET
+#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG14_OFFSET
+#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG13_OFFSET
+#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG12_OFFSET
+#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG11_OFFSET
+#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG10_OFFSET
+#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG9_OFFSET
+#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG8_OFFSET
+#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG7_OFFSET
+#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG6_OFFSET
+#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG5_OFFSET
+#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG4_OFFSET
+#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG3_OFFSET
+#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG2_OFFSET
+#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG1_OFFSET
+#define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG0_OFFSET
+#endif
+
+#define MXC_CCM_CCGR5_CG15_OFFSET 30
+#define MXC_CCM_CCGR5_CG14_OFFSET 28
+#define MXC_CCM_CCGR5_CG14_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG14_OFFSET)
+#define MXC_CCM_CCGR5_CG13_OFFSET 26
+#define MXC_CCM_CCGR5_CG13_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG13_OFFSET)
+#define MXC_CCM_CCGR5_CG12_OFFSET 24
+#define MXC_CCM_CCGR5_CG12_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG12_OFFSET)
+#define MXC_CCM_CCGR5_CG11_OFFSET 22
+#define MXC_CCM_CCGR5_CG11_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG11_OFFSET)
+#define MXC_CCM_CCGR5_CG10_OFFSET 20
+#define MXC_CCM_CCGR5_CG10_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG10_OFFSET)
+#define MXC_CCM_CCGR5_CG9_OFFSET 18
+#define MXC_CCM_CCGR5_CG9_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG9_OFFSET)
+#define MXC_CCM_CCGR5_CG8_OFFSET 16
+#define MXC_CCM_CCGR5_CG8_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG8_OFFSET)
+#define MXC_CCM_CCGR5_CG7_OFFSET 14
+#define MXC_CCM_CCGR5_CG7_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG7_OFFSET)
+#define MXC_CCM_CCGR5_CG6_OFFSET 12
+#define MXC_CCM_CCGR5_CG6_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG6_OFFSET)
+#define MXC_CCM_CCGR5_CG5_OFFSET 10
+#define MXC_CCM_CCGR5_CG4_OFFSET 8
+#define MXC_CCM_CCGR5_CG3_OFFSET 6
+#define MXC_CCM_CCGR5_CG2_OFFSET 4
+#define MXC_CCM_CCGR5_CG2_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG2_OFFSET)
+#define MXC_CCM_CCGR5_CG1_OFFSET 2
+#define MXC_CCM_CCGR5_CG0_OFFSET 0
+
+#if 0
+#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG15_OFFSET
+#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG14_OFFSET
+#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG13_OFFSET
+#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG12_OFFSET
+#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG11_OFFSET
+#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG10_OFFSET
+#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG9_OFFSET
+#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG8_OFFSET
+#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG7_OFFSET
+#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG6_OFFSET
+#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG5_OFFSET
+#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG4_OFFSET
+#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG3_OFFSET
+#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG1_OFFSET
+#define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG0_OFFSET
+#endif
+#define MXC_CCM_CCGR5_SATA_MASK MXC_CCM_CCGR5_CG2_MASK
+
+#define MXC_CCM_CCGR6_CG15_OFFSET 30
+#define MXC_CCM_CCGR6_CG14_OFFSET 28
+#define MXC_CCM_CCGR6_CG14_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG14_OFFSET)
+#define MXC_CCM_CCGR6_CG13_OFFSET 26
+#define MXC_CCM_CCGR6_CG13_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG13_OFFSET)
+#define MXC_CCM_CCGR6_CG12_OFFSET 24
+#define MXC_CCM_CCGR6_CG12_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG12_OFFSET)
+#define MXC_CCM_CCGR6_CG11_OFFSET 22
+#define MXC_CCM_CCGR6_CG11_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG11_OFFSET)
+#define MXC_CCM_CCGR6_CG10_OFFSET 20
+#define MXC_CCM_CCGR6_CG10_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG10_OFFSET)
+#define MXC_CCM_CCGR6_CG9_OFFSET 18
+#define MXC_CCM_CCGR6_CG9_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG9_OFFSET)
+#define MXC_CCM_CCGR6_CG8_OFFSET 16
+#define MXC_CCM_CCGR6_CG8_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG8_OFFSET)
+#define MXC_CCM_CCGR6_CG7_OFFSET 14
+#define MXC_CCM_CCGR6_CG7_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG7_OFFSET)
+#define MXC_CCM_CCGR6_CG6_OFFSET 12
+#define MXC_CCM_CCGR6_CG6_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG6_OFFSET)
+#define MXC_CCM_CCGR6_CG5_OFFSET 10
+#define MXC_CCM_CCGR6_CG4_OFFSET 8
+#define MXC_CCM_CCGR6_CG3_OFFSET 6
+#define MXC_CCM_CCGR6_CG2_OFFSET 4
+#define MXC_CCM_CCGR6_CG2_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG2_OFFSET)
+#define MXC_CCM_CCGR6_CG1_OFFSET 2
+#define MXC_CCM_CCGR6_CG1_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG1_OFFSET)
+#define MXC_CCM_CCGR6_CG0_OFFSET 0
+#define MXC_CCM_CCGR6_CG0_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG0_OFFSET)
+
+#if 0
+#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG15_OFFSET
+#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG14_OFFSET
+#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG13_OFFSET
+#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG12_OFFSET
+#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG11_OFFSET
+#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG10_OFFSET
+#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG9_OFFSET
+#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG8_OFFSET
+#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG7_OFFSET
+#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG6_OFFSET
+#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG5_OFFSET
+#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG4_OFFSET
+#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG3_OFFSET
+#define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG2_OFFSET
+#endif
+#define MXC_CCM_CCGR6_USDHC1_MASK MXC_CCM_CCGR6_CG1_MASK
+#define MXC_CCM_CCGR6_USBOH3_MASK MXC_CCM_CCGR6_CG0_MASK
+
+#define MXC_CCM_CCGR7_CG15_OFFSET 30
+#define MXC_CCM_CCGR7_CG14_OFFSET 28
+#define MXC_CCM_CCGR7_CG14_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG14_OFFSET)
+#define MXC_CCM_CCGR7_CG13_OFFSET 26
+#define MXC_CCM_CCGR7_CG13_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG13_OFFSET)
+#define MXC_CCM_CCGR7_CG12_OFFSET 24
+#define MXC_CCM_CCGR7_CG12_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG12_OFFSET)
+#define MXC_CCM_CCGR7_CG11_OFFSET 22
+#define MXC_CCM_CCGR7_CG11_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG11_OFFSET)
+#define MXC_CCM_CCGR7_CG10_OFFSET 20
+#define MXC_CCM_CCGR7_CG10_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG10_OFFSET)
+#define MXC_CCM_CCGR7_CG9_OFFSET 18
+#define MXC_CCM_CCGR7_CG9_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG9_OFFSET)
+#define MXC_CCM_CCGR7_CG8_OFFSET 16
+#define MXC_CCM_CCGR7_CG8_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG8_OFFSET)
+#define MXC_CCM_CCGR7_CG7_OFFSET 14
+#define MXC_CCM_CCGR7_CG7_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG7_OFFSET)
+#define MXC_CCM_CCGR7_CG6_OFFSET 12
+#define MXC_CCM_CCGR7_CG6_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG6_OFFSET)
+#define MXC_CCM_CCGR7_CG5_OFFSET 10
+#define MXC_CCM_CCGR7_CG4_OFFSET 8
+#define MXC_CCM_CCGR7_CG3_OFFSET 6
+#define MXC_CCM_CCGR7_CG2_OFFSET 4
+#define MXC_CCM_CCGR7_CG2_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG2_OFFSET)
+#define MXC_CCM_CCGR7_CG1_OFFSET 2
+#define MXC_CCM_CCGR7_CG0_OFFSET 0
+
+#if 0
+#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG15_OFFSET
+#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG14_OFFSET
+#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG13_OFFSET
+#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG12_OFFSET
+#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG11_OFFSET
+#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG10_OFFSET
+#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG9_OFFSET
+#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG8_OFFSET
+#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG7_OFFSET
+#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG6_OFFSET
+#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG5_OFFSET
+#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG4_OFFSET
+#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG3_OFFSET
+#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG2_OFFSET
+#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG1_OFFSET
+#define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG0_OFFSET
+#endif
+
+struct anatop_regs {
+ mx6_reg_32(pll_arm); /* 0x000 */
+ mx6_reg_32(usb1_pll_480_ctrl); /* 0x010 */
+ mx6_reg_32(usb2_pll_480_ctrl); /* 0x020 */
+ mx6_reg_32(pll_528); /* 0x030 */
+ reg_32(pll_528_ss); /* 0x040 */
+ reg_32(pll_528_num); /* 0x050 */
+ reg_32(pll_528_denom); /* 0x060 */
+ mx6_reg_32(pll_audio); /* 0x070 */
+ reg_32(pll_audio_num); /* 0x080 */
+ reg_32(pll_audio_denom); /* 0x090 */
+ mx6_reg_32(pll_video); /* 0x0a0 */
+ reg_32(pll_video_num); /* 0x0b0 */
+ reg_32(pll_video_denom); /* 0x0c0 */
+ mx6_reg_32(pll_mlb); /* 0x0d0 */
+ mx6_reg_32(pll_enet); /* 0x0e0 */
+ mx6_reg_32(pfd_480); /* 0x0f0 */
+ mx6_reg_32(pfd_528); /* 0x100 */
+ mx6_reg_32(reg_1p1); /* 0x110 */
+ mx6_reg_32(reg_3p0); /* 0x120 */
+ mx6_reg_32(reg_2p5); /* 0x130 */
+ mx6_reg_32(reg_core); /* 0x140 */
+ mx6_reg_32(ana_misc0); /* 0x150 */
+ mx6_reg_32(ana_misc1); /* 0x160 */
+ mx6_reg_32(ana_misc2); /* 0x170 */
+ mx6_reg_32(tempsense0); /* 0x180 */
+ mx6_reg_32(tempsense1); /* 0x190 */
+ mx6_reg_32(usb1_vbus_detect); /* 0x1a0 */
+ mx6_reg_32(usb1_chrg_detect); /* 0x1b0 */
+ mx6_reg_32(usb1_vbus_det_stat); /* 0x1c0 */
+ mx6_reg_32(usb1_chrg_det_stat); /* 0x1d0 */
+ mx6_reg_32(usb1_loopback); /* 0x1e0 */
+ mx6_reg_32(usb1_misc); /* 0x1f0 */
+ mx6_reg_32(usb2_vbus_detect); /* 0x200 */
+ mx6_reg_32(usb2_chrg_detect); /* 0x210 */
+ mx6_reg_32(usb2_vbus_det_stat); /* 0x220 */
+ mx6_reg_32(usb2_chrg_det_stat); /* 0x230 */
+ mx6_reg_32(usb2_loopback); /* 0x240 */
+ mx6_reg_32(usb2_misc); /* 0x250 */
+ reg_32(digprog); /* 0x260 */
+ reg_32(rsrvd); /* 0x270 */
+ reg_32(digprog_sololite); /* 0x280 */
+};
+
+#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
+#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD0_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
+#define ANATOP_PFD_480_PFD0_STABLE_MASK (1 << ANATOP_PFD_480_PFD0_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
+#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1 << ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
+#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
+#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD1_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
+#define ANATOP_PFD_480_PFD1_STABLE_MASK (1 << ANATOP_PFD_480_PFD1_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
+#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
+#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
+#define ANATOP_PFD_480_PFD2_FRAC_MASK (1 << ANATOP_PFD_480_PFD2_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
+#define ANATOP_PFD_480_PFD2_STABLE_MASK (1 << ANATOP_PFD_480_PFD2_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
+#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
+#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
+#define ANATOP_PFD_480_PFD3_FRAC_MASK (1 << ANATOP_PFD_480_PFD3_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
+#define ANATOP_PFD_480_PFD3_STABLE_MASK (1 << ANATOP_PFD_480_PFD3_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
+
+#define BM_ANADIG_PLL_ARM_LOCK (1 << 31)
+#define BM_ANADIG_PLL_ARM_PLL_SEL (1 << 19)
+#define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL (1 << 18)
+#define BM_ANADIG_PLL_ARM_LVDS_SEL (1 << 17)
+#define BM_ANADIG_PLL_ARM_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(0)
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(1)
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(2)
+#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(3)
+#define BM_ANADIG_PLL_ARM_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_ARM_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_ARM_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_ARM_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_ARM_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_ARM_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_ARM_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_ARM_DIV_SELECT 0
+#define BM_ANADIG_PLL_ARM_DIV_SELECT (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT)
+#define BF_ANADIG_PLL_ARM_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \
+ BM_ANADIG_PLL_ARM_DIV_SELECT)
+
+#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK (1 << 31)
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS (1 << 16)
+#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) & \
+ BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(0)
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(1)
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(2)
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(3)
+#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE (1 << 13)
+#define BM_ANADIG_USB1_PLL_480_CTRL_POWER (1 << 12)
+#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP (1 << 9)
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF (1 << 7)
+#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
+#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
+#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
+#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
+ (((v) << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0) & \
+ BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
+#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
+#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
+#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) & \
+ BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
+
+#define BM_ANADIG_USB2_PLL_480_CTRL_LOCK (1 << 31)
+#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS (1 << 16)
+#define BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 14
+#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC) & \
+ BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(0)
+#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(1)
+#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(2)
+#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__XOR BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(3)
+#define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE (1 << 13)
+#define BM_ANADIG_USB2_PLL_480_CTRL_POWER (1 << 12)
+#define BM_ANADIG_USB2_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_CP (1 << 9)
+#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_LF (1 << 7)
+#define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
+#define BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0 2
+#define BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
+#define BF_ANADIG_USB2_PLL_480_CTRL_CONTROL0(v) \
+ (((v) << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0) & \
+ BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
+#define BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0
+#define BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
+#define BF_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT) & \
+ BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
+
+#define BM_ANADIG_PLL_SYS_LOCK (1 << 31)
+#define BM_ANADIG_PLL_SYS_PLL_SEL (1 << 19)
+#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL (1 << 18)
+#define BM_ANADIG_PLL_SYS_LVDS_SEL (1 << 17)
+#define BM_ANADIG_PLL_SYS_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_SYS_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_SYS_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_SYS_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_SYS_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_SYS_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_SYS_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_SYS_DIV_SELECT 0
+#define BM_ANADIG_PLL_SYS_DIV_SELECT (0x7F << BP_ANADIG_PLL_SYS_DIV_SELECT)
+#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_SYS_DIV_SELECT) & BM_ANADIG_PLL_SYS_DIV_SELECT)
+
+#define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
+#define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
+#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
+#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
+#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
+#define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
+#define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
+#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_AUDIO_NUM_A 0
+#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & BM_ANADIG_PLL_AUDIO_NUM_A)
+
+#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
+#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
+ (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & BM_ANADIG_PLL_AUDIO_DENOM_B)
+
+#define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
+#define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
+#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
+#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
+#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
+#define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
+#define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
+#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_VIDEO_NUM_A 0
+#define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
+#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & BM_ANADIG_PLL_VIDEO_NUM_A)
+
+#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
+#define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
+#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
+ (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & BM_ANADIG_PLL_VIDEO_DENOM_B)
+
+#define BM_ANADIG_PLL_MLB_LOCK (1 << 31)
+#define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG 26
+#define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \
+ (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG 23
+#define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \
+ (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG 20
+#define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \
+ (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
+#define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG 17
+#define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
+#define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \
+ (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
+#define BM_ANADIG_PLL_MLB_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_MLB_PHASE_SEL 12
+#define BM_ANADIG_PLL_MLB_PHASE_SEL (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
+#define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \
+ (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & BM_ANADIG_PLL_MLB_PHASE_SEL)
+#define BM_ANADIG_PLL_MLB_HOLD_RING_OFF (1 << 11)
+
+#define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
+#define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
+#define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
+#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
+#define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
+#define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
+#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
+#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
+ (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
+#define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
+#define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
+#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
+#define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
+#define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
+#define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
+#define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
+#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
+#define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
+#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
+ (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & BM_ANADIG_PLL_ENET_DIV_SELECT)
+
+#define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
+#define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
+#define BP_ANADIG_PFD_480_PFD3_FRAC 24
+#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
+#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
+ (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & BM_ANADIG_PFD_480_PFD3_FRAC)
#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
-#define BP_ANADIG_PFD_480_PFD2_FRAC 16
+#define BP_ANADIG_PFD_480_PFD2_FRAC 16
#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
-#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
- (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
-#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
-#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
-#define BP_ANADIG_PFD_480_PFD1_FRAC 8
+#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
+ (((v) << BP_ANADIG_PFD_480_PFD2_FRAC) & BM_ANADIG_PFD_480_PFD2_FRAC)
+#define BM_ANADIG_PFD_480_PFD1_CLKGATE (1 << 15)
+#define BM_ANADIG_PFD_480_PFD1_STABLE (1 << 14)
+#define BP_ANADIG_PFD_480_PFD1_FRAC 8
#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
-#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
- (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
-#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
-#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
-#define BP_ANADIG_PFD_480_PFD0_FRAC 0
+#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
+ (((v) << BP_ANADIG_PFD_480_PFD1_FRAC) & BM_ANADIG_PFD_480_PFD1_FRAC)
+#define BM_ANADIG_PFD_480_PFD0_CLKGATE (1 << 7)
+#define BM_ANADIG_PFD_480_PFD0_STABLE (1 << 6)
+#define BP_ANADIG_PFD_480_PFD0_FRAC 0
#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
-#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
- (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
+#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
+ (((v) << BP_ANADIG_PFD_480_PFD0_FRAC) & BM_ANADIG_PFD_480_PFD0_FRAC)
-#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
+#define BM_ANADIG_PFD_528_PFD3_CLKGATE (1 << 31)
#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
-#define BP_ANADIG_PFD_528_PFD3_FRAC 24
+#define BP_ANADIG_PFD_528_PFD3_FRAC 24
#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
-#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
+#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
(((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
-#define BP_ANADIG_PFD_528_PFD2_FRAC 16
+#define BP_ANADIG_PFD_528_PFD2_FRAC 16
#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
-#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
+#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
(((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
-#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
-#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
-#define BP_ANADIG_PFD_528_PFD1_FRAC 8
+#define BM_ANADIG_PFD_528_PFD1_CLKGATE (1 << 15)
+#define BM_ANADIG_PFD_528_PFD1_STABLE (1 << 14)
+#define BP_ANADIG_PFD_528_PFD1_FRAC 8
#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
-#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
+#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
(((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
-#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
-#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
-#define BP_ANADIG_PFD_528_PFD0_FRAC 0
+#define BM_ANADIG_PFD_528_PFD0_CLKGATE (1 << 7)
+#define BM_ANADIG_PFD_528_PFD0_STABLE (1 << 6)
+#define BP_ANADIG_PFD_528_PFD0_FRAC 0
#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
-#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
+#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
+#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26
+#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY)
+#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
+#define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL (1 << 25)
+#define BP_ANADIG_ANA_MISC0_ANAMUX 21
+#define BM_ANADIG_ANA_MISC0_ANAMUX (0xf << BP_ANADIG_ANA_MISC0_ANAMUX)
+#define BF_ANADIG_ANA_MISC0_ANAMUX(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & BM_ANADIG_ANA_MISC0_ANAMUX)
+#define BM_ANADIG_ANA_MISC0_ANAMUX_EN (1 << 20)
+#define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18
+#define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH (0x3 << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
+#define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
+#define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN (1 << 17)
+#define BM_ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16)
+#define BP_ANADIG_ANA_MISC0_OSC_I 14
+#define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000
+#define BF_ANADIG_ANA_MISC0_OSC_I(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & BM_ANADIG_ANA_MISC0_OSC_I)
+#define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN (1 << 13)
+#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12)
+#define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8
+#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 0x00000300
+#define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) \
+ (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7)
+#define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ (0x7 << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
+#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \
+ (((v) << BM_ANADIG_ANA_MISC0_REFTOP_VBGUP) & BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
+#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3)
+#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2)
+#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1)
+#define BM_ANADIG_ANA_MISC0_REFTOP_PWD (1 << 0)
+
+#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO (1 << 31)
+#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO 0x40000000
+#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO 0x20000000
+#define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN (1 << 13)
+#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
+#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN (1 << 11)
+#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
+#define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5
+#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 0x000003E0
+#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \
+ (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
+#define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0
+#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0x0000001F
+#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \
+ (((v) << 0) & BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
+
+#define BP_ANADIG_ANA_MISC2_CONTROL3 30
+#define BM_ANADIG_ANA_MISC2_CONTROL3 0xC0000000
+#define BF_ANADIG_ANA_MISC2_CONTROL3(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & BM_ANADIG_ANA_MISC2_CONTROL3)
+#define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28
+#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME 0x30000000
+#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
+#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26
+#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME 0x0C000000
+#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
+#define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24
+#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME 0x03000000
+#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
+#define BM_ANADIG_ANA_MISC2_CONTROL2 0x00800000
+#define BM_ANADIG_ANA_MISC2_REG2_OK 0x00400000
+#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO (1 << 21)
+#define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS (1 << 19)
+#define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16
+#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET 0x00070000
+#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
+#define BM_ANADIG_ANA_MISC2_CONTROL1 (1 << 15)
+#define BM_ANADIG_ANA_MISC2_REG1_OK (1 << 14)
+#define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO (1 << 13)
+#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS (1 << 11)
+#define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8
+#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET 0x00000700
+#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
+#define BM_ANADIG_ANA_MISC2_CONTROL0 (1 << 7)
+#define BM_ANADIG_ANA_MISC2_REG0_OK (1 << 6)
+#define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO (1 << 5)
+#define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS (1 << 3)
+#define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0
+#define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
+#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \
+ (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
+
+#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20
+#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE)
+#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \
+ (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
+#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8
+#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE)
+#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \
+ (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
+#define BM_ANADIG_TEMPSENSE0_TEST (1 << 6)
+#define BP_ANADIG_TEMPSENSE0_VBGADJ 3
+#define BM_ANADIG_TEMPSENSE0_VBGADJ (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ)
+#define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \
+ (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & BM_ANADIG_TEMPSENSE0_VBGADJ)
+#define BM_ANADIG_TEMPSENSE0_FINISHED (1 << 2)
+#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP (1 << 1)
+#define BM_ANADIG_TEMPSENSE0_POWER_DOWN (1 << 0)
+
+#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0
+#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ)
+#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \
+ (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
+
#define PLL2_PFD0_FREQ 352000000
#define PLL2_PFD1_FREQ 594000000
#define PLL2_PFD2_FREQ 400000000
--- /dev/null
+/*
+ * Freescale i.MX28 APBH DMA
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __DMA_H__
+#define __DMA_H__
+
+#include <linux/list.h>
+
+#ifndef CONFIG_ARCH_DMA_PIO_WORDS
+#define DMA_PIO_WORDS 15
+#else
+#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS
+#endif
+
+#define MXS_DMA_ALIGNMENT 32
+
+/*
+ * MXS DMA channels
+ */
+enum {
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP,
+ MXS_MAX_DMA_CHANNELS
+};
+
+/*
+ * MXS DMA hardware command.
+ *
+ * This structure describes the in-memory layout of an entire DMA command,
+ * including space for the maximum number of PIO accesses. See the appropriate
+ * reference manual for a detailed description of what these fields mean to the
+ * DMA hardware.
+ */
+#define MXS_DMA_DESC_COMMAND_MASK 0x3
+#define MXS_DMA_DESC_COMMAND_OFFSET 0
+#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
+#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
+#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
+#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
+#define MXS_DMA_DESC_CHAIN (1 << 2)
+#define MXS_DMA_DESC_IRQ (1 << 3)
+#define MXS_DMA_DESC_NAND_LOCK (1 << 4)
+#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
+#define MXS_DMA_DESC_DEC_SEM (1 << 6)
+#define MXS_DMA_DESC_WAIT4END (1 << 7)
+#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
+#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << MXS_DMA_DESC_PIO_WORDS_OFFSET)
+#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
+#define MXS_DMA_DESC_BYTES_MASK (0xffff << MXS_DMA_DESC_BYTES_OFFSET)
+#define MXS_DMA_DESC_BYTES_OFFSET 16
+
+struct mxs_dma_cmd {
+ unsigned long next;
+ unsigned long data;
+ union {
+ dma_addr_t address;
+ unsigned long alternate;
+ };
+ unsigned long pio_words[DMA_PIO_WORDS];
+};
+
+/*
+ * MXS DMA command descriptor.
+ *
+ * This structure incorporates an MXS DMA hardware command structure, along
+ * with metadata.
+ */
+#define MXS_DMA_DESC_FIRST (1 << 0)
+#define MXS_DMA_DESC_LAST (1 << 1)
+#define MXS_DMA_DESC_READY (1 << 31)
+
+struct mxs_dma_desc {
+ struct mxs_dma_cmd cmd;
+ unsigned int flags;
+ dma_addr_t address;
+ void *buffer;
+ struct list_head node;
+};
+
+/**
+ * MXS DMA channel
+ *
+ * This structure represents a single DMA channel. The MXS platform code
+ * maintains an array of these structures to represent every DMA channel in the
+ * system (see mxs_dma_channels).
+ */
+#define MXS_DMA_FLAGS_BUSY (1 << 0)
+#define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
+#define MXS_DMA_FLAGS_VALID (1 << 31)
+
+struct mxs_dma_chan {
+ const char *name;
+ unsigned long dev;
+ struct mxs_dma_device *dma;
+ unsigned int flags;
+ unsigned int active_num;
+ unsigned int pending_num;
+ struct list_head active;
+ struct list_head done;
+};
+
+struct mxs_dma_desc *mxs_dma_desc_alloc(void);
+void mxs_dma_desc_free(struct mxs_dma_desc *);
+int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
+
+int mxs_dma_go(int chan);
+void mxs_dma_init(void);
+int mxs_dma_init_channel(int chan);
+int mxs_dma_release(int chan);
+
+#endif /* __DMA_H__ */
#define CONFIG_SYS_CACHELINE_SIZE 32
-#define ROMCP_ARB_BASE_ADDR 0x00000000
-#define ROMCP_ARB_END_ADDR 0x000FFFFF
-#define CAAM_ARB_BASE_ADDR 0x00100000
-#define CAAM_ARB_END_ADDR 0x00103FFF
-#define APBH_DMA_ARB_BASE_ADDR 0x00110000
-#define APBH_DMA_ARB_END_ADDR 0x00117FFF
-#define HDMI_ARB_BASE_ADDR 0x00120000
-#define HDMI_ARB_END_ADDR 0x00128FFF
-#define GPU_3D_ARB_BASE_ADDR 0x00130000
-#define GPU_3D_ARB_END_ADDR 0x00133FFF
-#define GPU_2D_ARB_BASE_ADDR 0x00134000
-#define GPU_2D_ARB_END_ADDR 0x00137FFF
-#define DTCP_ARB_BASE_ADDR 0x00138000
-#define DTCP_ARB_END_ADDR 0x0013BFFF
+#define ROMCP_ARB_BASE_ADDR 0x00000000
+#define ROMCP_ARB_END_ADDR 0x000FFFFF
+#define CAAM_ARB_BASE_ADDR 0x00100000
+#define CAAM_ARB_END_ADDR 0x00103FFF
+#define APBH_DMA_ARB_BASE_ADDR 0x00110000
+#define APBH_DMA_ARB_END_ADDR 0x00117FFF
+#define HDMI_ARB_BASE_ADDR 0x00120000
+#define HDMI_ARB_END_ADDR 0x00128FFF
+#define GPU_3D_ARB_BASE_ADDR 0x00130000
+#define GPU_3D_ARB_END_ADDR 0x00133FFF
+#define GPU_2D_ARB_BASE_ADDR 0x00134000
+#define GPU_2D_ARB_END_ADDR 0x00137FFF
+#define DTCP_ARB_BASE_ADDR 0x00138000
+#define DTCP_ARB_END_ADDR 0x0013BFFF
/* GPV - PL301 configuration ports */
#define GPV2_BASE_ADDR 0x00200000
#define GPV3_BASE_ADDR 0x00300000
#define GPV4_BASE_ADDR 0x00800000
#define IRAM_BASE_ADDR 0x00900000
-#define SCU_BASE_ADDR 0x00A00000
-#define IC_INTERFACES_BASE_ADDR 0x00A00100
-#define GLOBAL_TIMER_BASE_ADDR 0x00A00200
-#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
-#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
-#define GPV0_BASE_ADDR 0x00B00000
-#define GPV1_BASE_ADDR 0x00C00000
-#define PCIE_ARB_BASE_ADDR 0x01000000
-#define PCIE_ARB_END_ADDR 0x01FFFFFF
-
-#define AIPS1_ARB_BASE_ADDR 0x02000000
-#define AIPS1_ARB_END_ADDR 0x020FFFFF
-#define AIPS2_ARB_BASE_ADDR 0x02100000
-#define AIPS2_ARB_END_ADDR 0x021FFFFF
-#define SATA_ARB_BASE_ADDR 0x02200000
-#define SATA_ARB_END_ADDR 0x02203FFF
-#define OPENVG_ARB_BASE_ADDR 0x02204000
-#define OPENVG_ARB_END_ADDR 0x02207FFF
-#define HSI_ARB_BASE_ADDR 0x02208000
-#define HSI_ARB_END_ADDR 0x0220BFFF
-#define IPU1_ARB_BASE_ADDR 0x02400000
-#define IPU1_ARB_END_ADDR 0x027FFFFF
-#define IPU2_ARB_BASE_ADDR 0x02800000
-#define IPU2_ARB_END_ADDR 0x02BFFFFF
-#define WEIM_ARB_BASE_ADDR 0x08000000
-#define WEIM_ARB_END_ADDR 0x0FFFFFFF
-
-#define MMDC0_ARB_BASE_ADDR 0x10000000
-#define MMDC0_ARB_END_ADDR 0x7FFFFFFF
-#define MMDC1_ARB_BASE_ADDR 0x80000000
-#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
-
-#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
-#define IPU_SOC_OFFSET 0x00200000
+#define SCU_BASE_ADDR 0x00A00000
+#define IC_INTERFACES_BASE_ADDR 0x00A00100
+#define GLOBAL_TIMER_BASE_ADDR 0x00A00200
+#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
+#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
+#define GPV0_BASE_ADDR 0x00B00000
+#define GPV1_BASE_ADDR 0x00C00000
+#define PCIE_ARB_BASE_ADDR 0x01000000
+#define PCIE_ARB_END_ADDR 0x01FFFFFF
+
+#define AIPS1_ARB_BASE_ADDR 0x02000000
+#define AIPS1_ARB_END_ADDR 0x020FFFFF
+#define AIPS2_ARB_BASE_ADDR 0x02100000
+#define AIPS2_ARB_END_ADDR 0x021FFFFF
+#define SATA_ARB_BASE_ADDR 0x02200000
+#define SATA_ARB_END_ADDR 0x02203FFF
+#define OPENVG_ARB_BASE_ADDR 0x02204000
+#define OPENVG_ARB_END_ADDR 0x02207FFF
+#define HSI_ARB_BASE_ADDR 0x02208000
+#define HSI_ARB_END_ADDR 0x0220BFFF
+#define IPU1_ARB_BASE_ADDR 0x02400000
+#define IPU_CTRL_BASE_ADDR IPU1_ARB_BASE_ADDR
+#define IPU1_ARB_END_ADDR 0x027FFFFF
+#define IPU2_ARB_BASE_ADDR 0x02800000
+#define IPU2_ARB_END_ADDR 0x02BFFFFF
+#define WEIM_ARB_BASE_ADDR 0x08000000
+#define WEIM_ARB_END_ADDR 0x0FFFFFFF
+
+#define MMDC0_ARB_BASE_ADDR 0x10000000
+#define MMDC0_ARB_END_ADDR 0x7FFFFFFF
+#define MMDC1_ARB_BASE_ADDR 0x80000000
+#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
/* Defines for Blocks connected via AIPS (SkyBlue) */
-#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
-#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
-#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
-#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
-
-#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
-#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
-#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
-#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
-#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
-#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
-#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
-#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
-#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
-#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
-#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
-#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
-#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
-#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
-#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
-
-#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
-#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
-#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
-#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
-#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
-#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
-#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
-#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
-#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
-#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
-#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
-#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
-#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
-#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
-#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
-#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
-#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
-#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
-#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
-#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
-#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
-#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
-#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
-#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
-#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
-#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
-#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
-#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
-#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
-#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
+#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
+#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
+#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
+
+#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
+#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
+#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
+#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
+#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
+#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
+#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
+#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
+#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
+#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
+#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
+#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
+
+#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
+#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
+#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
+#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
+#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
+#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
+#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
+#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
+#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
+#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
+#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
+#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
+#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
+#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
+#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
+#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
+#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
+#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
+#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
+#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
+#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
+#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
+#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
+#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
+#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
+#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
+#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
+#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
+#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
+#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
-#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
-#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
-#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
+#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
+#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
+#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
-#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
-#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
-#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
-#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
-#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
-#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
-#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
-#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
-#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
-#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
-#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
-#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
-#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
-#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
-#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
-#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
-#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
+#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
+#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
+#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
+#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
+#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
+#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
+#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
+#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
+#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
+#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
+#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
+#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
+#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
+#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
+#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
+#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
-#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
-#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
-#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
-#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
-#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
-#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
-#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
-#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
-#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
-#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
+#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
+#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
+#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
+#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
+#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
+#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
+#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
-#define CHIP_REV_1_0 0x10
-#define IRAM_SIZE 0x00040000
-#define IMX_IIM_BASE OCOTP_BASE_ADDR
+#define CHIP_REV_1_0 0x10
+#define IRAM_SIZE 0x00040000
+#define IMX_IIM_BASE OCOTP_BASE_ADDR
#define FEC_QUIRK_ENET_MAC
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
-extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+#define __reg_32(name) \
+ uint32_t name; \
+ uint32_t reserved_##name[3]
+
+#define __mx6_reg_32(name) \
+ uint32_t name; \
+ uint32_t name##_set; \
+ uint32_t name##_clr; \
+ uint32_t name##_tog
+
+struct register_32 {
+ __reg_32(reg);
+};
+
+struct mx6_register_32 {
+ __mx6_reg_32(reg);
+};
+
+#define reg_32(name) \
+ struct { __reg_32(name); }; \
+
+#define mx6_reg_32(name) \
+ union { \
+ struct { __mx6_reg_32(name); }; \
+ struct mx6_register_32 name##_reg; \
+ }
/* System Reset Controller (SRC) */
struct src {
u32 reserved1[2];
u32 sisr;
u32 simr;
- u32 sbmr2;
- u32 gpr1;
- u32 gpr2;
- u32 gpr3;
- u32 gpr4;
- u32 gpr5;
- u32 gpr6;
- u32 gpr7;
- u32 gpr8;
- u32 gpr9;
- u32 gpr10;
-};
-
-/* OCOTP Registers */
-struct ocotp_regs {
- u32 reserved[0x198];
- u32 gp1; /* 0x660 */
+ u32 sbmr2;
+ u32 gpr1;
+ u32 gpr2;
+ u32 gpr3;
+ u32 gpr4;
+ u32 gpr5;
+ u32 gpr6;
+ u32 gpr7;
+ u32 gpr8;
+ u32 gpr9;
+ u32 gpr10;
};
/* GPR3 bitfields */
struct iim_regs {
u32 ctrl;
u32 ctrl_set;
- u32 ctrl_clr;
+ u32 ctrl_clr;
u32 ctrl_tog;
u32 timing;
- u32 rsvd0[3];
- u32 data;
- u32 rsvd1[3];
- u32 read_ctrl;
- u32 rsvd2[3];
- u32 fuse_data;
- u32 rsvd3[3];
- u32 sticky;
- u32 rsvd4[3];
- u32 scs;
- u32 scs_set;
- u32 scs_clr;
- u32 scs_tog;
- u32 crc_addr;
- u32 rsvd5[3];
- u32 crc_value;
- u32 rsvd6[3];
- u32 version;
- u32 rsvd7[0xdb];
+ u32 rsvd0[3];
+ u32 data;
+ u32 rsvd1[3];
+ u32 read_ctrl;
+ u32 rsvd2[3];
+ u32 fuse_data;
+ u32 rsvd3[3];
+ u32 sticky;
+ u32 rsvd4[3];
+ u32 scs;
+ u32 scs_set;
+ u32 scs_clr;
+ u32 scs_tog;
+ u32 crc_addr;
+ u32 rsvd5[3];
+ u32 crc_value;
+ u32 rsvd6[3];
+ u32 version;
+ u32 rsvd7[0xdb];
struct fuse_bank {
u32 fuse_regs[0x20];
struct fuse_bank4_regs {
u32 sjc_resp_low;
- u32 rsvd0[3];
- u32 sjc_resp_high;
- u32 rsvd1[3];
+ u32 rsvd0[3];
+ u32 sjc_resp_high;
+ u32 rsvd1[3];
u32 mac_addr_low;
- u32 rsvd2[3];
- u32 mac_addr_high;
+ u32 rsvd2[3];
+ u32 mac_addr_high;
u32 rsvd3[0x13];
};
u32 opacr4;
};
-struct anatop_regs {
- u32 pll_sys; /* 0x000 */
- u32 pll_sys_set; /* 0x004 */
- u32 pll_sys_clr; /* 0x008 */
- u32 pll_sys_tog; /* 0x00c */
- u32 usb1_pll_480_ctrl; /* 0x010 */
- u32 usb1_pll_480_ctrl_set; /* 0x014 */
- u32 usb1_pll_480_ctrl_clr; /* 0x018 */
- u32 usb1_pll_480_ctrl_tog; /* 0x01c */
- u32 usb2_pll_480_ctrl; /* 0x020 */
- u32 usb2_pll_480_ctrl_set; /* 0x024 */
- u32 usb2_pll_480_ctrl_clr; /* 0x028 */
- u32 usb2_pll_480_ctrl_tog; /* 0x02c */
- u32 pll_528; /* 0x030 */
- u32 pll_528_set; /* 0x034 */
- u32 pll_528_clr; /* 0x038 */
- u32 pll_528_tog; /* 0x03c */
- u32 pll_528_ss; /* 0x040 */
- u32 rsvd0[3];
- u32 pll_528_num; /* 0x050 */
- u32 rsvd1[3];
- u32 pll_528_denom; /* 0x060 */
- u32 rsvd2[3];
- u32 pll_audio; /* 0x070 */
- u32 pll_audio_set; /* 0x074 */
- u32 pll_audio_clr; /* 0x078 */
- u32 pll_audio_tog; /* 0x07c */
- u32 pll_audio_num; /* 0x080 */
- u32 rsvd3[3];
- u32 pll_audio_denom; /* 0x090 */
- u32 rsvd4[3];
- u32 pll_video; /* 0x0a0 */
- u32 pll_video_set; /* 0x0a4 */
- u32 pll_video_clr; /* 0x0a8 */
- u32 pll_video_tog; /* 0x0ac */
- u32 pll_video_num; /* 0x0b0 */
- u32 rsvd5[3];
- u32 pll_video_denom; /* 0x0c0 */
- u32 rsvd6[3];
- u32 pll_mlb; /* 0x0d0 */
- u32 pll_mlb_set; /* 0x0d4 */
- u32 pll_mlb_clr; /* 0x0d8 */
- u32 pll_mlb_tog; /* 0x0dc */
- u32 pll_enet; /* 0x0e0 */
- u32 pll_enet_set; /* 0x0e4 */
- u32 pll_enet_clr; /* 0x0e8 */
- u32 pll_enet_tog; /* 0x0ec */
- u32 pfd_480; /* 0x0f0 */
- u32 pfd_480_set; /* 0x0f4 */
- u32 pfd_480_clr; /* 0x0f8 */
- u32 pfd_480_tog; /* 0x0fc */
- u32 pfd_528; /* 0x100 */
- u32 pfd_528_set; /* 0x104 */
- u32 pfd_528_clr; /* 0x108 */
- u32 pfd_528_tog; /* 0x10c */
- u32 reg_1p1; /* 0x110 */
- u32 reg_1p1_set; /* 0x114 */
- u32 reg_1p1_clr; /* 0x118 */
- u32 reg_1p1_tog; /* 0x11c */
- u32 reg_3p0; /* 0x120 */
- u32 reg_3p0_set; /* 0x124 */
- u32 reg_3p0_clr; /* 0x128 */
- u32 reg_3p0_tog; /* 0x12c */
- u32 reg_2p5; /* 0x130 */
- u32 reg_2p5_set; /* 0x134 */
- u32 reg_2p5_clr; /* 0x138 */
- u32 reg_2p5_tog; /* 0x13c */
- u32 reg_core; /* 0x140 */
- u32 reg_core_set; /* 0x144 */
- u32 reg_core_clr; /* 0x148 */
- u32 reg_core_tog; /* 0x14c */
- u32 ana_misc0; /* 0x150 */
- u32 ana_misc0_set; /* 0x154 */
- u32 ana_misc0_clr; /* 0x158 */
- u32 ana_misc0_tog; /* 0x15c */
- u32 ana_misc1; /* 0x160 */
- u32 ana_misc1_set; /* 0x164 */
- u32 ana_misc1_clr; /* 0x168 */
- u32 ana_misc1_tog; /* 0x16c */
- u32 ana_misc2; /* 0x170 */
- u32 ana_misc2_set; /* 0x174 */
- u32 ana_misc2_clr; /* 0x178 */
- u32 ana_misc2_tog; /* 0x17c */
- u32 tempsense0; /* 0x180 */
- u32 tempsense0_set; /* 0x184 */
- u32 tempsense0_clr; /* 0x188 */
- u32 tempsense0_tog; /* 0x18c */
- u32 tempsense1; /* 0x190 */
- u32 tempsense1_set; /* 0x194 */
- u32 tempsense1_clr; /* 0x198 */
- u32 tempsense1_tog; /* 0x19c */
- u32 usb1_vbus_detect; /* 0x1a0 */
- u32 usb1_vbus_detect_set; /* 0x1a4 */
- u32 usb1_vbus_detect_clr; /* 0x1a8 */
- u32 usb1_vbus_detect_tog; /* 0x1ac */
- u32 usb1_chrg_detect; /* 0x1b0 */
- u32 usb1_chrg_detect_set; /* 0x1b4 */
- u32 usb1_chrg_detect_clr; /* 0x1b8 */
- u32 usb1_chrg_detect_tog; /* 0x1bc */
- u32 usb1_vbus_det_stat; /* 0x1c0 */
- u32 usb1_vbus_det_stat_set; /* 0x1c4 */
- u32 usb1_vbus_det_stat_clr; /* 0x1c8 */
- u32 usb1_vbus_det_stat_tog; /* 0x1cc */
- u32 usb1_chrg_det_stat; /* 0x1d0 */
- u32 usb1_chrg_det_stat_set; /* 0x1d4 */
- u32 usb1_chrg_det_stat_clr; /* 0x1d8 */
- u32 usb1_chrg_det_stat_tog; /* 0x1dc */
- u32 usb1_loopback; /* 0x1e0 */
- u32 usb1_loopback_set; /* 0x1e4 */
- u32 usb1_loopback_clr; /* 0x1e8 */
- u32 usb1_loopback_tog; /* 0x1ec */
- u32 usb1_misc; /* 0x1f0 */
- u32 usb1_misc_set; /* 0x1f4 */
- u32 usb1_misc_clr; /* 0x1f8 */
- u32 usb1_misc_tog; /* 0x1fc */
- u32 usb2_vbus_detect; /* 0x200 */
- u32 usb2_vbus_detect_set; /* 0x204 */
- u32 usb2_vbus_detect_clr; /* 0x208 */
- u32 usb2_vbus_detect_tog; /* 0x20c */
- u32 usb2_chrg_detect; /* 0x210 */
- u32 usb2_chrg_detect_set; /* 0x214 */
- u32 usb2_chrg_detect_clr; /* 0x218 */
- u32 usb2_chrg_detect_tog; /* 0x21c */
- u32 usb2_vbus_det_stat; /* 0x220 */
- u32 usb2_vbus_det_stat_set; /* 0x224 */
- u32 usb2_vbus_det_stat_clr; /* 0x228 */
- u32 usb2_vbus_det_stat_tog; /* 0x22c */
- u32 usb2_chrg_det_stat; /* 0x230 */
- u32 usb2_chrg_det_stat_set; /* 0x234 */
- u32 usb2_chrg_det_stat_clr; /* 0x238 */
- u32 usb2_chrg_det_stat_tog; /* 0x23c */
- u32 usb2_loopback; /* 0x240 */
- u32 usb2_loopback_set; /* 0x244 */
- u32 usb2_loopback_clr; /* 0x248 */
- u32 usb2_loopback_tog; /* 0x24c */
- u32 usb2_misc; /* 0x250 */
- u32 usb2_misc_set; /* 0x254 */
- u32 usb2_misc_clr; /* 0x258 */
- u32 usb2_misc_tog; /* 0x25c */
- u32 digprog; /* 0x260 */
- u32 reserved1[7];
- u32 digprog_sololite; /* 0x280 */
-};
-
-#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
-#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
-#define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
-#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
-#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
-#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
-#define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
-#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
-#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
-#define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
-#define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
-#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
-#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
-#define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
-#define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
-
struct iomuxc_base_regs {
- u32 gpr[14]; /* 0x000 */
- u32 obsrv[5]; /* 0x038 */
- u32 swmux_ctl[197]; /* 0x04c */
- u32 swpad_ctl[250]; /* 0x360 */
- u32 swgrp[26]; /* 0x748 */
- u32 daisy[104]; /* 0x7b0..94c */
+ u32 gpr[14]; /* 0x000 */
+ u32 obsrv[5]; /* 0x038 */
+ u32 swmux_ctl[197]; /* 0x04c */
+ u32 swpad_ctl[250]; /* 0x360 */
+ u32 swgrp[26]; /* 0x748 */
+ u32 daisy[104]; /* 0x7b0..94c */
};
#endif /* __ASSEMBLER__*/
+
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Auto Generate file, please don't edit it
+ *
+ */
+
+#ifndef __MACH_IOMUX_MX6Q_H__
+#define __MACH_IOMUX_MX6Q_H__
+
+#include <asm/arch/iomux-v3.h>
+
+/*
+ * Use to set PAD control
+ */
+#define MX6_PAD_CTL_HYS (1 << 16)
+
+#define MX6_PAD_CTL_PUS_100K_DOWN (MX6_PAD_CTL_PULL | (0 << 14))
+#define MX6_PAD_CTL_PUS_47K_UP (MX6_PAD_CTL_PULL | (1 << 14))
+#define MX6_PAD_CTL_PUS_100K_UP (MX6_PAD_CTL_PULL | (2 << 14))
+#define MX6_PAD_CTL_PUS_22K_UP (MX6_PAD_CTL_PULL | (3 << 14))
+
+#define MX6_PAD_CTL_PULL (MX6_PAD_CTL_PKE | MX6_PAD_CTL_PUE)
+#define MX6_PAD_CTL_PUE (1 << 13)
+#define MX6_PAD_CTL_PKE (1 << 12)
+#define MX6_PAD_CTL_ODE (1 << 11)
+
+#define MX6_PAD_CTL_SPEED_LOW (1 << 6)
+#define MX6_PAD_CTL_SPEED_MED (2 << 6)
+#define MX6_PAD_CTL_SPEED_HIGH (3 << 6)
+
+#define MX6_PAD_CTL_DSE_DISABLE (0 << 3)
+#define MX6_PAD_CTL_DSE_240ohm (1 << 3)
+#define MX6_PAD_CTL_DSE_120ohm (2 << 3)
+#define MX6_PAD_CTL_DSE_80ohm (3 << 3)
+#define MX6_PAD_CTL_DSE_60ohm (4 << 3)
+#define MX6_PAD_CTL_DSE_48ohm (5 << 3)
+#define MX6_PAD_CTL_DSE_40ohm (6 << 3)
+#define MX6_PAD_CTL_DSE_34ohm (7 << 3)
+
+#define MX6_PAD_CTL_SRE_FAST (1 << 0)
+#define MX6_PAD_CTL_SRE_SLOW (0 << 0)
+
+#define MX6Q_UART_PAD_CTRL (MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS)
+
+#define MX6Q_ECSPI_PAD_CTRL (MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_SPEED_MED | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS)
+
+#define MX6Q_USDHC_PAD_CTRL (MX6_PAD_CTL_PUS_47K_UP | MX6_PAD_CTL_SPEED_MED | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_HYS)
+
+#define MX6Q_ENET_PAD_CTRL (MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS)
+
+#define MX6Q_I2C_PAD_CTRL (MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS | \
+ MX6_PAD_CTL_ODE | MX6_PAD_CTL_SRE_FAST)
+
+#define MX6Q_PWM_PAD_CTRL (MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_SPEED_MED | \
+ MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS | \
+ MX6_PAD_CTL_SRE_FAST)
+
+#define MX6Q_HIGH_DRV MX6_PAD_CTL_DSE_120ohm
+
+#define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \
+ IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \
+ IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 \
+ IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS \
+ IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__KPP_COL_7 \
+ IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__GPIO_1_14 \
+ IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__CCM_WAIT \
+ IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 \
+ IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 \
+ IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 \
+ IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 \
+ IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD \
+ IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__KPP_ROW_6 \
+ IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__GPIO_1_13 \
+ IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__CCM_STOP \
+ IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 \
+ IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 \
+ IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__ECSPI5_MISO \
+ IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \
+ IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__KPP_ROW_7 \
+ IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__GPIO_1_15 \
+ IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT \
+ IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 \
+ IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA \
+ IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC \
+ IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK \
+ IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__GPIO_6_19 \
+ IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 \
+ IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT \
+ IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY \
+ IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 \
+ IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD0__GPIO_6_20 \
+ IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 \
+ IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG \
+ IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 \
+ IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD1__GPIO_6_21 \
+ IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 \
+ IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP \
+ IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA \
+ IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 \
+ IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD2__GPIO_6_22 \
+ IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 \
+ IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP \
+ IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE \
+ IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 \
+ IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD3__GPIO_6_23 \
+ IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 \
+ IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA \
+ IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL \
+ IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0)
+#define _MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 \
+ IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 \
+ IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY \
+ IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 \
+ IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0)
+#define _MX6Q_PAD_RGMII_RD0__GPIO_6_25 \
+ IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 \
+ IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE \
+ IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL \
+ IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 \
+ IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 \
+ IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT \
+ IOMUX_PAD(0x0388, 0x0074, 0x17, 0x083C, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG \
+ IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 \
+ IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0)
+#define _MX6Q_PAD_RGMII_RD1__GPIO_6_27 \
+ IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 \
+ IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD1__SJC_FAIL \
+ IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA \
+ IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 \
+ IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0)
+#define _MX6Q_PAD_RGMII_RD2__GPIO_6_28 \
+ IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 \
+ IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE \
+ IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 \
+ IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0)
+#define _MX6Q_PAD_RGMII_RD3__GPIO_6_29 \
+ IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 \
+ IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE \
+ IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC \
+ IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0)
+#define _MX6Q_PAD_RGMII_RXC__GPIO_6_30 \
+ IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 \
+ IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 \
+ IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__ECSPI4_SS1 \
+ IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__ECSPI2_RDY \
+ IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 \
+ IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS \
+ IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__GPIO_5_2 \
+ IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE \
+ IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0)
+#define _MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 \
+ IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 \
+ IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__ECSPI1_SS0 \
+ IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK \
+ IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 \
+ IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL \
+ IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__GPIO_2_30 \
+ IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__I2C2_SCL \
+ IOMUX_PAD(0x03A0, 0x008C, 6 | IOMUX_CONFIG_SION, 0x08A0, 0, 0)
+#define _MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \
+ IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 \
+ IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D16__ECSPI1_SCLK \
+ IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0)
+#define _MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 \
+ IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 \
+ IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0)
+#define _MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA \
+ IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0)
+#define _MX6Q_PAD_EIM_D16__GPIO_3_16 \
+ IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D16__I2C2_SDA \
+ IOMUX_PAD(0x03A4, 0x0090, 6 | IOMUX_CONFIG_SION, 0x08A4, 0, 0)
+
+#define _MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \
+ IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D17__ECSPI1_MISO \
+ IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0)
+#define _MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 \
+ IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK \
+ IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0)
+#define _MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT \
+ IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D17__GPIO_3_17 \
+ IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D17__I2C3_SCL \
+ IOMUX_PAD(0x03A8, 0x0094, 6 | IOMUX_CONFIG_SION, 0x08A8, 0, 0)
+#define _MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \
+ IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 \
+ IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D18__ECSPI1_MOSI \
+ IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0)
+#define _MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 \
+ IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 \
+ IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0)
+#define _MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS \
+ IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D18__GPIO_3_18 \
+ IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D18__I2C3_SDA \
+ IOMUX_PAD(0x03AC, 0x0098, 6 | IOMUX_CONFIG_SION, 0x08AC, 0, 0)
+#define _MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \
+ IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 \
+ IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__ECSPI1_SS1 \
+ IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0)
+#define _MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 \
+ IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 \
+ IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0)
+#define _MX6Q_PAD_EIM_D19__UART1_CTS \
+ IOMUX_PAD(0x03B0, 0x009C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__UART1_RTS \
+ IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0)
+#define _MX6Q_PAD_EIM_D19__GPIO_3_19 \
+ IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__EPIT1_EPITO \
+ IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP \
+ IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 \
+ IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D20__ECSPI4_SS0 \
+ IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0)
+#define _MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 \
+ IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 \
+ IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0)
+#define _MX6Q_PAD_EIM_D20__UART1_CTS \
+ IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D20__UART1_RTS \
+ IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0)
+#define _MX6Q_PAD_EIM_D20__GPIO_3_20 \
+ IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D20__EPIT2_EPITO \
+ IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 \
+ IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D21__ECSPI4_SCLK \
+ IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 \
+ IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 \
+ IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0)
+#define _MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC \
+ IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0)
+#define _MX6Q_PAD_EIM_D21__GPIO_3_21 \
+ IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D21__I2C1_SCL \
+ IOMUX_PAD(0x03B8, 0x00A4, 6 | IOMUX_CONFIG_SION, 0x0898, 0, 0)
+#define _MX6Q_PAD_EIM_D21__SPDIF_IN1 \
+ IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0)
+
+#define _MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 \
+ IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__ECSPI4_MISO \
+ IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 \
+ IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 \
+ IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0)
+#define _MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR \
+ IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__GPIO_3_22 \
+ IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__SPDIF_OUT1 \
+ IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE \
+ IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 \
+ IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS \
+ IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__UART3_CTS \
+ IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__UART3_RTS \
+ IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0)
+#define _MX6Q_PAD_EIM_D23__UART1_DCD \
+ IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN \
+ IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0)
+#define _MX6Q_PAD_EIM_D23__GPIO_3_23 \
+ IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 \
+ IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 \
+ IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 \
+ IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__ECSPI4_RDY \
+ IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__UART3_CTS \
+ IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__UART3_RTS \
+ IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0)
+#define _MX6Q_PAD_EIM_EB3__UART1_RI \
+ IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC \
+ IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__GPIO_2_31 \
+ IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 \
+ IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 \
+ IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 \
+ IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__ECSPI4_SS2 \
+ IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__UART3_TXD \
+ IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__UART3_RXD \
+ IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0)
+#define _MX6Q_PAD_EIM_D24__ECSPI1_SS2 \
+ IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0)
+#define _MX6Q_PAD_EIM_D24__ECSPI2_SS2 \
+ IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__GPIO_3_24 \
+ IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS \
+ IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0)
+#define _MX6Q_PAD_EIM_D24__UART1_DTR \
+ IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 \
+ IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__ECSPI4_SS3 \
+ IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__UART3_TXD \
+ IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__UART3_RXD \
+ IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0)
+#define _MX6Q_PAD_EIM_D25__ECSPI1_SS3 \
+ IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0)
+#define _MX6Q_PAD_EIM_D25__ECSPI2_SS3 \
+ IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__GPIO_3_25 \
+ IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC \
+ IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0)
+#define _MX6Q_PAD_EIM_D25__UART1_DSR \
+ IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 \
+ IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 \
+ IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 \
+ IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 \
+ IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0)
+#define _MX6Q_PAD_EIM_D26__UART2_TXD \
+ IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__UART2_RXD \
+ IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0)
+#define _MX6Q_PAD_EIM_D26__GPIO_3_26 \
+ IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU1_SISG_2 \
+ IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 \
+ IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 \
+ IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 \
+ IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 \
+ IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 \
+ IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0)
+#define _MX6Q_PAD_EIM_D27__UART2_TXD \
+ IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__UART2_RXD \
+ IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0)
+#define _MX6Q_PAD_EIM_D27__GPIO_3_27 \
+ IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU1_SISG_3 \
+ IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 \
+ IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \
+ IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__I2C1_SDA \
+ IOMUX_PAD(0x03D8, 0x00C4, 1 | IOMUX_CONFIG_SION, 0x089C, 0, 0)
+#define _MX6Q_PAD_EIM_D28__ECSPI4_MOSI \
+ IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \
+ IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0)
+#define _MX6Q_PAD_EIM_D28__UART2_CTS \
+ IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__UART2_RTS \
+ IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0)
+#define _MX6Q_PAD_EIM_D28__GPIO_3_28 \
+ IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG \
+ IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 \
+ IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 \
+ IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 \
+ IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D29__ECSPI4_SS0 \
+ IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0)
+#define _MX6Q_PAD_EIM_D29__UART2_CTS \
+ IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D29__UART2_RTS \
+ IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0)
+#define _MX6Q_PAD_EIM_D29__GPIO_3_29 \
+ IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC \
+ IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0)
+#define _MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 \
+ IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 \
+ IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 \
+ IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 \
+ IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 \
+ IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__UART3_CTS \
+ IOMUX_PAD(0x03E0, 0x00CC, 4, 0x0000, 2, 0)
+#define _MX6Q_PAD_EIM_D30__UART3_RTS \
+ IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0)
+#define _MX6Q_PAD_EIM_D30__GPIO_3_30 \
+ IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC \
+ IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0)
+#define _MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 \
+ IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 \
+ IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 \
+ IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 \
+ IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 \
+ IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__UART3_CTS \
+ IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__UART3_RTS \
+ IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0)
+#define _MX6Q_PAD_EIM_D31__GPIO_3_31 \
+ IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR \
+ IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 \
+ IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 \
+ IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 \
+ IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 \
+ IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0)
+#define _MX6Q_PAD_EIM_A24__IPU2_SISG_2 \
+ IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__IPU1_SISG_2 \
+ IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__GPIO_5_4 \
+ IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 \
+ IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 \
+ IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 \
+ IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 \
+ IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 \
+ IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0)
+#define _MX6Q_PAD_EIM_A23__IPU2_SISG_3 \
+ IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__IPU1_SISG_3 \
+ IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__GPIO_6_6 \
+ IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 \
+ IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 \
+ IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 \
+ IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 \
+ IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 \
+ IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0)
+#define _MX6Q_PAD_EIM_A22__GPIO_2_16 \
+ IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 \
+ IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 \
+ IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 \
+ IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 \
+ IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 \
+ IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0)
+#define _MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 \
+ IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__GPIO_2_17 \
+ IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 \
+ IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 \
+ IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 \
+ IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 \
+ IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 \
+ IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0)
+#define _MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 \
+ IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__GPIO_2_18 \
+ IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 \
+ IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 \
+ IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 \
+ IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 \
+ IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 \
+ IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0)
+#define _MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 \
+ IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__GPIO_2_19 \
+ IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 \
+ IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 \
+ IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 \
+ IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 \
+ IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 \
+ IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0)
+#define _MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 \
+ IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__GPIO_2_20 \
+ IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 \
+ IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 \
+ IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 \
+ IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 \
+ IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 \
+ IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0)
+#define _MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 \
+ IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__GPIO_2_21 \
+ IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 \
+ IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 \
+ IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 \
+ IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK \
+ IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK \
+ IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0)
+#define _MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 \
+ IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__GPIO_2_22 \
+ IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 \
+ IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 \
+ IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 \
+ IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 \
+ IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__ECSPI2_SCLK \
+ IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 \
+ IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__GPIO_2_23 \
+ IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 \
+ IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 \
+ IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 \
+ IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__ECSPI2_MOSI \
+ IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 \
+ IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__GPIO_2_24 \
+ IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 \
+ IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_OE__WEIM_WEIM_OE \
+ IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 \
+ IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_OE__ECSPI2_MISO \
+ IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0)
+#define _MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 \
+ IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_OE__GPIO_2_25 \
+ IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 \
+ IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_RW__WEIM_WEIM_RW \
+ IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 \
+ IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__ECSPI2_SS0 \
+ IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0)
+#define _MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 \
+ IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__GPIO_2_26 \
+ IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 \
+ IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 \
+ IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA \
+ IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 \
+ IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__ECSPI2_SS1 \
+ IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__GPIO_2_27 \
+ IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 \
+ IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 \
+ IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 \
+ IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 \
+ IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 \
+ IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0)
+#define _MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 \
+ IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY \
+ IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__GPIO_2_28 \
+ IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 \
+ IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 \
+ IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 \
+ IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 \
+ IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 \
+ IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0)
+#define _MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 \
+ IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__GPIO_2_29 \
+ IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 \
+ IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 \
+ IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 \
+ IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 \
+ IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 \
+ IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 \
+ IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__GPIO_3_0 \
+ IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 \
+ IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 \
+ IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 \
+ IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 \
+ IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 \
+ IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 \
+ IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \
+ IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__GPIO_3_1 \
+ IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 \
+ IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 \
+ IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 \
+ IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 \
+ IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 \
+ IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 \
+ IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE \
+ IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__GPIO_3_2 \
+ IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 \
+ IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 \
+ IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 \
+ IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 \
+ IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 \
+ IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 \
+ IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ \
+ IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__GPIO_3_3 \
+ IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 \
+ IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 \
+ IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 \
+ IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 \
+ IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 \
+ IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 \
+ IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN \
+ IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__GPIO_3_4 \
+ IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 \
+ IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 \
+ IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 \
+ IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 \
+ IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 \
+ IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 \
+ IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP \
+ IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__GPIO_3_5 \
+ IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 \
+ IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 \
+ IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 \
+ IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 \
+ IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 \
+ IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 \
+ IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN \
+ IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__GPIO_3_6 \
+ IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 \
+ IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 \
+ IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 \
+ IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 \
+ IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 \
+ IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 \
+ IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__GPIO_3_7 \
+ IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 \
+ IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 \
+ IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 \
+ IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 \
+ IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 \
+ IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 \
+ IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__GPIO_3_8 \
+ IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 \
+ IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 \
+ IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 \
+ IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 \
+ IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 \
+ IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 \
+ IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__GPIO_3_9 \
+ IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 \
+ IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 \
+ IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 \
+ IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 \
+ IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN \
+ IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0)
+#define _MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 \
+ IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__GPIO_3_10 \
+ IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 \
+ IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 \
+ IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 \
+ IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 \
+ IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC \
+ IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0)
+#define _MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 \
+ IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 \
+ IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__GPIO_3_11 \
+ IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 \
+ IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 \
+ IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 \
+ IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 \
+ IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC \
+ IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0)
+#define _MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 \
+ IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 \
+ IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__GPIO_3_12 \
+ IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 \
+ IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 \
+ IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 \
+ IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS \
+ IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK \
+ IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0)
+#define _MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 \
+ IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 \
+ IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__GPIO_3_13 \
+ IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 \
+ IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 \
+ IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 \
+ IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS \
+ IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK \
+ IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 \
+ IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 \
+ IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__GPIO_3_14 \
+ IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 \
+ IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 \
+ IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 \
+ IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 \
+ IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 \
+ IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 \
+ IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__GPIO_3_15 \
+ IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 \
+ IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 \
+ IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT \
+ IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B \
+ IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_WAIT__GPIO_5_0 \
+ IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 \
+ IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 \
+ IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK \
+ IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 \
+ IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_BCLK__GPIO_6_31 \
+ IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 \
+ IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \
+ IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK \
+ IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 \
+ IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 \
+ IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 \
+ IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 \
+ IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 \
+ IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 \
+ IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC \
+ IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 \
+ IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 \
+ IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__GPIO_4_17 \
+ IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 \
+ IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 \
+ IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 \
+ IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD \
+ IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 \
+ IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 \
+ IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__GPIO_4_18 \
+ IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 \
+ IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 \
+ IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 \
+ IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 \
+ IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS \
+ IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 \
+ IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 \
+ IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__GPIO_4_19 \
+ IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 \
+ IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 \
+ IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 \
+ IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 \
+ IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD \
+ IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__USDHC1_WP \
+ IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD \
+ IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__GPIO_4_20 \
+ IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 \
+ IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 \
+ IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 \
+ IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 \
+ IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK \
+ IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 \
+ IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN \
+ IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__GPIO_4_21 \
+ IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 \
+ IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 \
+ IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 \
+ IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI \
+ IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 \
+ IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \
+ IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__GPIO_4_22 \
+ IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 \
+ IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 \
+ IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 \
+ IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 \
+ IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO \
+ IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 \
+ IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE \
+ IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__GPIO_4_23 \
+ IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 \
+ IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 \
+ IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 \
+ IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 \
+ IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 \
+ IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 \
+ IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR \
+ IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__GPIO_4_24 \
+ IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 \
+ IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 \
+ IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 \
+ IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 \
+ IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 \
+ IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 \
+ IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB \
+ IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__GPIO_4_25 \
+ IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 \
+ IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 \
+ IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 \
+ IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 \
+ IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 \
+ IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS \
+ IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS \
+ IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__GPIO_4_26 \
+ IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 \
+ IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 \
+ IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 \
+ IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 \
+ IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 \
+ IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC \
+ IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE \
+ IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__GPIO_4_27 \
+ IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 \
+ IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 \
+ IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 \
+ IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 \
+ IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY \
+ IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 \
+ IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 \
+ IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__GPIO_4_28 \
+ IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 \
+ IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 \
+ IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 \
+ IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 \
+ IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__PWM1_PWMO \
+ IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B \
+ IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 \
+ IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__GPIO_4_29 \
+ IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 \
+ IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 \
+ IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 \
+ IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 \
+ IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__PWM2_PWMO \
+ IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B \
+ IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 \
+ IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__GPIO_4_30 \
+ IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 \
+ IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 \
+ IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 \
+ IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 \
+ IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 \
+ IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \
+ IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__GPIO_4_31 \
+ IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 \
+ IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 \
+ IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 \
+ IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 \
+ IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 \
+ IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \
+ IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__GPIO_5_5 \
+ IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 \
+ IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 \
+ IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 \
+ IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 \
+ IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \
+ IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__GPIO_5_6 \
+ IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 \
+ IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 \
+ IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 \
+ IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 \
+ IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS \
+ IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \
+ IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__GPIO_5_7 \
+ IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 \
+ IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 \
+ IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 \
+ IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 \
+ IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC \
+ IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \
+ IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT14__GPIO_5_8 \
+ IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 \
+ IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 \
+ IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 \
+ IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 \
+ IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 \
+ IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \
+ IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__GPIO_5_9 \
+ IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 \
+ IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 \
+ IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 \
+ IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 \
+ IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI \
+ IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC \
+ IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 \
+ IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__GPIO_5_10 \
+ IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 \
+ IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 \
+ IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 \
+ IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 \
+ IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO \
+ IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD \
+ IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 \
+ IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__GPIO_5_11 \
+ IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 \
+ IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 \
+ IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 \
+ IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 \
+ IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 \
+ IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS \
+ IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS \
+ IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__GPIO_5_12 \
+ IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 \
+ IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 \
+ IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 \
+ IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 \
+ IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK \
+ IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD \
+ IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC \
+ IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__GPIO_5_13 \
+ IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 \
+ IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 \
+ IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 \
+ IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 \
+ IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK \
+ IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC \
+ IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \
+ IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__GPIO_5_14 \
+ IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 \
+ IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 \
+ IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 \
+ IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 \
+ IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI \
+ IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD \
+ IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 \
+ IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__GPIO_5_15 \
+ IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 \
+ IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 \
+ IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 \
+ IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 \
+ IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO \
+ IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS \
+ IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 \
+ IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__GPIO_5_16 \
+ IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 \
+ IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 \
+ IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 \
+ IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 \
+ IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 \
+ IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD \
+ IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0)
+#define _MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 \
+ IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__GPIO_5_17 \
+ IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 \
+ IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 \
+ IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_MDIO__ENET_MDIO \
+ IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \
+ IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \
+ IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT \
+ IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__GPIO_1_22 \
+ IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK \
+ IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK \
+ IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR \
+ IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 \
+ IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 \
+ IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK \
+ IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH \
+ IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_RX_ER__ENET_RX_ER \
+ IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR \
+ IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 \
+ IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0)
+#define _MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT \
+ IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__GPIO_1_24 \
+ IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__PHY_TDI \
+ IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD \
+ IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN \
+ IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT \
+ IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK \
+ IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 \
+ IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__PHY_TDO \
+ IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD \
+ IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_RXD1__MLB_MLBSIG \
+ IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 \
+ IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0)
+#define _MX6Q_PAD_ENET_RXD1__ESAI1_FST \
+ IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT \
+ IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__GPIO_1_26 \
+ IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__PHY_TCK \
+ IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \
+ IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT \
+ IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 \
+ IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0)
+#define _MX6Q_PAD_ENET_RXD0__ESAI1_HCKT \
+ IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 \
+ IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__GPIO_1_27 \
+ IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__PHY_TMS \
+ IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \
+ IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_TX_EN__ENET_TX_EN \
+ IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 \
+ IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__GPIO_1_28 \
+ IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI \
+ IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH \
+ IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_TXD1__MLB_MLBCLK \
+ IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 \
+ IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 \
+ IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN \
+ IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__GPIO_1_29 \
+ IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO \
+ IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD \
+ IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 \
+ IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 \
+ IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__GPIO_1_30 \
+ IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK \
+ IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD \
+ IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_ENET_MDC__MLB_MLBDAT \
+ IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__ENET_MDC \
+ IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \
+ IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \
+ IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__GPIO_1_31 \
+ IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__SATA_PHY_TMS \
+ IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \
+ IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 \
+ IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 \
+ IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 \
+ IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 \
+ IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \
+ IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \
+ IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \
+ IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \
+ IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 \
+ IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 \
+ IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 \
+ IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 \
+ IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 \
+ IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 \
+ IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 \
+ IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 \
+ IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 \
+ IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 \
+ IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 \
+ IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 \
+ IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 \
+ IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 \
+ IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 \
+ IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 \
+ IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS \
+ IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \
+ IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \
+ IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS \
+ IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET \
+ IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \
+ IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \
+ IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \
+ IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \
+ IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \
+ IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 \
+ IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \
+ IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \
+ IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \
+ IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \
+ IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \
+ IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \
+ IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \
+ IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \
+ IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 \
+ IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 \
+ IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 \
+ IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 \
+ IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL0__ECSPI1_SCLK \
+ IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0)
+#define _MX6Q_PAD_KEY_COL0__ENET_RDATA_3 \
+ IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0)
+#define _MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC \
+ IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0)
+#define _MX6Q_PAD_KEY_COL0__KPP_COL_0 \
+ IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__UART4_TXD \
+ IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__UART4_RXD \
+ IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__GPIO_4_6 \
+ IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT \
+ IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST \
+ IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI \
+ IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0)
+#define _MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 \
+ IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD \
+ IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0)
+#define _MX6Q_PAD_KEY_ROW0__KPP_ROW_0 \
+ IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__UART4_TXD \
+ IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__UART4_RXD \
+ IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0)
+#define _MX6Q_PAD_KEY_ROW0__GPIO_4_7 \
+ IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT \
+ IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 \
+ IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL1__ECSPI1_MISO \
+ IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0)
+#define _MX6Q_PAD_KEY_COL1__ENET_MDIO \
+ IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0)
+#define _MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS \
+ IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0)
+#define _MX6Q_PAD_KEY_COL1__KPP_COL_1 \
+ IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__UART5_TXD \
+ IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__UART5_RXD \
+ IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__GPIO_4_8 \
+ IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__USDHC1_VSELECT \
+ IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 \
+ IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 \
+ IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0)
+#define _MX6Q_PAD_KEY_ROW1__ENET_COL \
+ IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD \
+ IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0)
+#define _MX6Q_PAD_KEY_ROW1__KPP_ROW_1 \
+ IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__UART5_TXD \
+ IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__UART5_RXD \
+ IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0)
+#define _MX6Q_PAD_KEY_ROW1__GPIO_4_9 \
+ IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT \
+ IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 \
+ IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL2__ECSPI1_SS1 \
+ IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0)
+#define _MX6Q_PAD_KEY_COL2__ENET_RDATA_2 \
+ IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0)
+#define _MX6Q_PAD_KEY_COL2__CAN1_TXCAN \
+ IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__KPP_COL_2 \
+ IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__ENET_MDC \
+ IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__GPIO_4_10 \
+ IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP \
+ IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 \
+ IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 \
+ IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0)
+#define _MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 \
+ IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__CAN1_RXCAN \
+ IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__KPP_ROW_2 \
+ IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT \
+ IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__GPIO_4_11 \
+ IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE \
+ IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0)
+#define _MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 \
+ IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL3__ECSPI1_SS3 \
+ IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0)
+#define _MX6Q_PAD_KEY_COL3__ENET_CRS \
+ IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL \
+ IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0)
+#define _MX6Q_PAD_KEY_COL3__KPP_COL_3 \
+ IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL3__I2C2_SCL \
+ IOMUX_PAD(0x05E0, 0x0210, 4 | IOMUX_CONFIG_SION, 0x08A0, 1, 0)
+#define _MX6Q_PAD_KEY_COL3__GPIO_4_12 \
+ IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL3__SPDIF_IN1 \
+ IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0)
+#define _MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 \
+ IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT \
+ IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK \
+ IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA \
+ IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0)
+#define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \
+ IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__I2C2_SDA \
+ IOMUX_PAD(0x05E4, 0x0214, 4 | IOMUX_CONFIG_SION, 0x08A4, 1, 0)
+#define _MX6Q_PAD_KEY_ROW3__GPIO_4_13 \
+ IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \
+ IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 \
+ IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_COL4__CAN2_TXCAN \
+ IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__IPU1_SISG_4 \
+ IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC \
+ IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0)
+#define _MX6Q_PAD_KEY_COL4__KPP_COL_4 \
+ IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__UART5_CTS \
+ IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__UART5_RTS \
+ IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__GPIO_4_14 \
+ IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 \
+ IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 \
+ IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_KEY_ROW4__CAN2_RXCAN \
+ IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 \
+ IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR \
+ IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__KPP_ROW_4 \
+ IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__UART5_CTS \
+ IOMUX_PAD(0x05EC, 0x021C, 4, 0x0000, 1, 0)
+#define _MX6Q_PAD_KEY_ROW4__UART5_RTS \
+ IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0)
+#define _MX6Q_PAD_KEY_ROW4__GPIO_4_15 \
+ IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 \
+ IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 \
+ IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_0__CCM_CLKO \
+ IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_0__KPP_COL_5 \
+ IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0)
+#define _MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK \
+ IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0)
+#define _MX6Q_PAD_GPIO_0__EPIT1_EPITO \
+ IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_0__GPIO_1_0 \
+ IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR \
+ IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 \
+ IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_1__ESAI1_SCKR \
+ IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0)
+#define _MX6Q_PAD_GPIO_1__WDOG2_WDOG_B \
+ IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_1__KPP_ROW_5 \
+ IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0)
+#define _MX6Q_PAD_GPIO_1__PWM2_PWMO \
+ IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_1__GPIO_1_1 \
+ IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_1__USDHC1_CD \
+ IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_1__SRC_TESTER_ACK \
+ IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_9__ESAI1_FSR \
+ IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0)
+#define _MX6Q_PAD_GPIO_9__WDOG1_WDOG_B \
+ IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_9__KPP_COL_6 \
+ IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0)
+#define _MX6Q_PAD_GPIO_9__CCM_REF_EN_B \
+ IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_9__PWM1_PWMO \
+ IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_9__GPIO_1_9 \
+ IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_9__USDHC1_WP \
+ IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0)
+#define _MX6Q_PAD_GPIO_9__SRC_EARLY_RST \
+ IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_3__ESAI1_HCKR \
+ IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0)
+#define _MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \
+ IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_3__I2C3_SCL \
+ IOMUX_PAD(0x05FC, 0x022C, 2 | IOMUX_CONFIG_SION, 0x08A8, 1, 0)
+#define _MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \
+ IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_3__CCM_CLKO2 \
+ IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_3__GPIO_1_3 \
+ IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC \
+ IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0)
+#define _MX6Q_PAD_GPIO_3__MLB_MLBCLK \
+ IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0)
+
+#define _MX6Q_PAD_GPIO_6__ESAI1_SCKT \
+ IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0)
+#define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
+ IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__I2C3_SDA \
+ IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0)
+#define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \
+ IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \
+ IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__GPIO_1_6 \
+ IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__USDHC2_LCTL \
+ IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_6__MLB_MLBSIG \
+ IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0)
+
+#define _MX6Q_PAD_GPIO_2__ESAI1_FST \
+ IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0)
+#define _MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 \
+ IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__KPP_ROW_6 \
+ IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0)
+#define _MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 \
+ IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 \
+ IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__GPIO_1_2 \
+ IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__USDHC2_WP \
+ IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_2__MLB_MLBDAT \
+ IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0)
+
+#define _MX6Q_PAD_GPIO_4__ESAI1_HCKT \
+ IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0)
+#define _MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 \
+ IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__KPP_COL_7 \
+ IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0)
+#define _MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 \
+ IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 \
+ IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__GPIO_1_4 \
+ IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__USDHC2_CD \
+ IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \
+ IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 \
+ IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0)
+#define _MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 \
+ IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_5__KPP_ROW_7 \
+ IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0)
+#define _MX6Q_PAD_GPIO_5__CCM_CLKO \
+ IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 \
+ IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_5__GPIO_1_5 \
+ IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_5__I2C3_SCL \
+ IOMUX_PAD(0x060C, 0x023C, 6 | IOMUX_CONFIG_SION, 0x08A8, 2, 0)
+#define _MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \
+ IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 \
+ IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0)
+#define _MX6Q_PAD_GPIO_7__ECSPI5_RDY \
+ IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__EPIT1_EPITO \
+ IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__CAN1_TXCAN \
+ IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__UART2_TXD \
+ IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__UART2_RXD \
+ IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0)
+#define _MX6Q_PAD_GPIO_7__GPIO_1_7 \
+ IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__SPDIF_PLOCK \
+ IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE \
+ IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 \
+ IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0)
+#define _MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT \
+ IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__EPIT2_EPITO \
+ IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__CAN1_RXCAN \
+ IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0)
+#define _MX6Q_PAD_GPIO_8__UART2_TXD \
+ IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__UART2_RXD \
+ IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0)
+#define _MX6Q_PAD_GPIO_8__GPIO_1_8 \
+ IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__SPDIF_SRCLK \
+ IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP \
+ IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 \
+ IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0)
+#define _MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN \
+ IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT \
+ IOMUX_PAD(0x0618, 0x0248, 0x12, 0x083C, 1, 0)
+#define _MX6Q_PAD_GPIO_16__USDHC1_LCTL \
+ IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_16__SPDIF_IN1 \
+ IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0)
+#define _MX6Q_PAD_GPIO_16__GPIO_7_11 \
+ IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_16__I2C3_SDA \
+ IOMUX_PAD(0x0618, 0x0248, 6 | IOMUX_CONFIG_SION, 0x08AC, 2, 0)
+#define _MX6Q_PAD_GPIO_16__SJC_DE_B \
+ IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_17__ESAI1_TX0 \
+ IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0)
+#define _MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN \
+ IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_17__CCM_PMIC_RDY \
+ IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0)
+#define _MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 \
+ IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0)
+#define _MX6Q_PAD_GPIO_17__SPDIF_OUT1 \
+ IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_17__GPIO_7_12 \
+ IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_17__SJC_JTAG_ACT \
+ IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_18__ESAI1_TX1 \
+ IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0)
+#define _MX6Q_PAD_GPIO_18__ENET_RX_CLK \
+ IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0)
+#define _MX6Q_PAD_GPIO_18__USDHC3_VSELECT \
+ IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 \
+ IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0)
+#define _MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK \
+ IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0)
+#define _MX6Q_PAD_GPIO_18__GPIO_7_13 \
+ IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL \
+ IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST \
+ IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_GPIO_19__KPP_COL_5 \
+ IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0)
+#define _MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT \
+ IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__SPDIF_OUT1 \
+ IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__CCM_CLKO \
+ IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__ECSPI1_RDY \
+ IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__GPIO_4_5 \
+ IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__ENET_TX_ER \
+ IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_GPIO_19__SRC_INT_BOOT \
+ IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK \
+ IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 \
+ IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 \
+ IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 \
+ IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 \
+ IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO \
+ IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC \
+ IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 \
+ IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__CCM_CLKO \
+ IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 \
+ IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__GPIO_5_19 \
+ IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 \
+ IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL \
+ IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN \
+ IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 \
+ IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 \
+ IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 \
+ IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 \
+ IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 \
+ IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK \
+ IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC \
+ IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 \
+ IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 \
+ IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 \
+ IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 \
+ IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 \
+ IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 \
+ IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 \
+ IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 \
+ IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK \
+ IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT4__KPP_COL_5 \
+ IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC \
+ IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__GPIO_5_22 \
+ IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 \
+ IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 \
+ IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 \
+ IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 \
+ IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI \
+ IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 \
+ IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD \
+ IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__GPIO_5_23 \
+ IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 \
+ IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 \
+ IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 \
+ IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 \
+ IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO \
+ IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT6__KPP_COL_6 \
+ IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS \
+ IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__GPIO_5_24 \
+ IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 \
+ IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 \
+ IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 \
+ IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 \
+ IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 \
+ IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 \
+ IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD \
+ IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__GPIO_5_25 \
+ IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 \
+ IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 \
+ IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 \
+ IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 \
+ IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK \
+ IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \
+ IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT8__I2C1_SDA \
+ IOMUX_PAD(0x0648, 0x0278, 4 | IOMUX_CONFIG_SION, 0x089C, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \
+ IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \
+ IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 \
+ IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 \
+ IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 \
+ IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI \
+ IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \
+ IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT9__I2C1_SCL \
+ IOMUX_PAD(0x064C, 0x027C, 4 | IOMUX_CONFIG_SION, 0x0898, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \
+ IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \
+ IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 \
+ IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 \
+ IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC \
+ IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO \
+ IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT10__UART1_TXD \
+ IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__UART1_RXD \
+ IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 \
+ IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__GPIO_5_28 \
+ IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 \
+ IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 \
+ IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 \
+ IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS \
+ IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 \
+ IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT11__UART1_TXD \
+ IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__UART1_RXD \
+ IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 \
+ IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__GPIO_5_29 \
+ IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 \
+ IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 \
+ IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 \
+ IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 \
+ IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 \
+ IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__UART4_TXD \
+ IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__UART4_RXD \
+ IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 \
+ IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__GPIO_5_30 \
+ IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 \
+ IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 \
+ IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 \
+ IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 \
+ IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 \
+ IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__UART4_TXD \
+ IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__UART4_RXD \
+ IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 \
+ IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__GPIO_5_31 \
+ IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 \
+ IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 \
+ IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 \
+ IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 \
+ IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 \
+ IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__UART5_TXD \
+ IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__UART5_RXD \
+ IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 \
+ IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__GPIO_6_0 \
+ IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 \
+ IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 \
+ IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 \
+ IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 \
+ IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 \
+ IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__UART5_TXD \
+ IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__UART5_RXD \
+ IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 \
+ IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__GPIO_6_1 \
+ IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 \
+ IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 \
+ IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 \
+ IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 \
+ IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 \
+ IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__UART4_CTS \
+ IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__UART4_RTS \
+ IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 \
+ IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__GPIO_6_2 \
+ IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 \
+ IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 \
+ IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 \
+ IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 \
+ IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 \
+ IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__UART4_CTS \
+ IOMUX_PAD(0x066C, 0x029C, 3, 0x0000, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT17__UART4_RTS \
+ IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0)
+#define _MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 \
+ IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__GPIO_6_3 \
+ IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 \
+ IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 \
+ IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 \
+ IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 \
+ IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 \
+ IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__UART5_CTS \
+ IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__UART5_RTS \
+ IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0)
+#define _MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 \
+ IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__GPIO_6_4 \
+ IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 \
+ IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 \
+ IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 \
+ IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 \
+ IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 \
+ IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__UART5_CTS \
+ IOMUX_PAD(0x0674, 0x02A4, 3, 0x0000, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT19__UART5_RTS \
+ IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0)
+#define _MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 \
+ IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__GPIO_6_5 \
+ IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 \
+ IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 \
+ IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TMS__SJC_TMS \
+ IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_MOD__SJC_MOD \
+ IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB \
+ IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TDI__SJC_TDI \
+ IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TCK__SJC_TCK \
+ IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_JTAG_TDO__SJC_TDO \
+ IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_POR_B__SRC_POR_B \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_RESET_IN_B__SRC_RESET_B \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_TEST_MODE__TCU_TEST_MODE \
+ IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 \
+ IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__UART1_TXD \
+ IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__UART1_RXD \
+ IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0)
+#define _MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 \
+ IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 \
+ IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 \
+ IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__GPIO_6_17 \
+ IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 \
+ IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \
+ IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 \
+ IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__UART1_TXD \
+ IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__UART1_RXD \
+ IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0)
+#define _MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 \
+ IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 \
+ IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 \
+ IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__GPIO_6_18 \
+ IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 \
+ IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 \
+ IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 \
+ IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__UART2_TXD \
+ IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__UART2_RXD \
+ IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0)
+#define _MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 \
+ IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 \
+ IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 \
+ IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__GPIO_7_0 \
+ IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 \
+ IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 \
+ IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 \
+ IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__UART2_TXD \
+ IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__UART2_RXD \
+ IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0)
+#define _MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 \
+ IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 \
+ IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 \
+ IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__GPIO_7_1 \
+ IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 \
+ IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 \
+ IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_CMD__USDHC3_CMD \
+ IOMUX_PAD(0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__UART2_CTS \
+ IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0000, 2, 0)
+#define _MX6Q_PAD_SD3_CMD__UART2_RTS \
+ IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0)
+#define _MX6Q_PAD_SD3_CMD__CAN1_TXCAN \
+ IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 \
+ IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 \
+ IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__GPIO_7_2 \
+ IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 \
+ IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 \
+ IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_CLK__USDHC3_CLK \
+ IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__UART2_CTS \
+ IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__UART2_RTS \
+ IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0)
+#define _MX6Q_PAD_SD3_CLK__CAN1_RXCAN \
+ IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0)
+#define _MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 \
+ IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 \
+ IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__GPIO_7_3 \
+ IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 \
+ IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 \
+ IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 \
+ IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__UART1_CTS \
+ IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__UART1_RTS \
+ IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0)
+#define _MX6Q_PAD_SD3_DAT0__CAN2_TXCAN \
+ IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 \
+ IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 \
+ IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__GPIO_7_4 \
+ IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 \
+ IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 \
+ IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 \
+ IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__UART1_CTS \
+ IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__UART1_RTS \
+ IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0)
+#define _MX6Q_PAD_SD3_DAT1__CAN2_RXCAN \
+ IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0)
+#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 \
+ IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 \
+ IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__GPIO_7_5 \
+ IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 \
+ IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 \
+ IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 \
+ IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 \
+ IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 \
+ IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 \
+ IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__GPIO_7_6 \
+ IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 \
+ IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 \
+ IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 \
+ IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__UART3_CTS \
+ IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 4, 0)
+#define _MX6Q_PAD_SD3_DAT3__UART3_RTS \
+ IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0)
+#define _MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 \
+ IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 \
+ IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 \
+ IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__GPIO_7_7 \
+ IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 \
+ IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 \
+ IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD3_RST__USDHC3_RST \
+ IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__UART3_CTS \
+ IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__UART3_RTS \
+ IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0)
+#define _MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 \
+ IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 \
+ IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 \
+ IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__GPIO_7_8 \
+ IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 \
+ IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 \
+ IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CLE__RAWNAND_CLE \
+ IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 \
+ IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 \
+ IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 \
+ IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 \
+ IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__GPIO_6_7 \
+ IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 \
+ IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 \
+ IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_ALE__RAWNAND_ALE \
+ IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__USDHC4_RST \
+ IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 \
+ IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 \
+ IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 \
+ IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__GPIO_6_8 \
+ IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 \
+ IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 \
+ IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN \
+ IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 \
+ IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 \
+ IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 \
+ IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 \
+ IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__GPIO_6_9 \
+ IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 \
+ IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 \
+ IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 \
+ IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 \
+ IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 \
+ IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 \
+ IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 \
+ IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__GPIO_6_10 \
+ IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 \
+ IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 \
+ IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N \
+ IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 \
+ IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 \
+ IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS0__GPIO_6_11 \
+ IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 \
+ IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N \
+ IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT \
+ IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT \
+ IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 \
+ IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__GPIO_6_14 \
+ IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT \
+ IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N \
+ IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 \
+ IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__ESAI1_TX0 \
+ IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0)
+#define _MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE \
+ IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__CCM_CLKO2 \
+ IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__GPIO_6_15 \
+ IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 \
+ IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N \
+ IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 \
+ IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__ESAI1_TX1 \
+ IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0)
+#define _MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 \
+ IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 \
+ IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__GPIO_6_16 \
+ IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 \
+ IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_CS3__TPSMP_CLK \
+ IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_CMD__USDHC4_CMD \
+ IOMUX_PAD(0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__RAWNAND_RDN \
+ IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__UART3_TXD \
+ IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__UART3_RXD \
+ IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0)
+#define _MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 \
+ IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__GPIO_7_9 \
+ IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR \
+ IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_CLK__USDHC4_CLK \
+ IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CLK__RAWNAND_WRN \
+ IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CLK__UART3_TXD \
+ IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CLK__UART3_RXD \
+ IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0)
+#define _MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 \
+ IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_CLK__GPIO_7_10 \
+ IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D0__RAWNAND_D0 \
+ IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__USDHC1_DAT4 \
+ IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 \
+ IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 \
+ IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 \
+ IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__GPIO_2_0 \
+ IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 \
+ IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 \
+ IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D1__RAWNAND_D1 \
+ IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__USDHC1_DAT5 \
+ IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 \
+ IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 \
+ IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 \
+ IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__GPIO_2_1 \
+ IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 \
+ IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 \
+ IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D2__RAWNAND_D2 \
+ IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__USDHC1_DAT6 \
+ IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 \
+ IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 \
+ IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 \
+ IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__GPIO_2_2 \
+ IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 \
+ IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 \
+ IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D3__RAWNAND_D3 \
+ IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__USDHC1_DAT7 \
+ IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 \
+ IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 \
+ IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 \
+ IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__GPIO_2_3 \
+ IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 \
+ IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 \
+ IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D4__RAWNAND_D4 \
+ IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__USDHC2_DAT4 \
+ IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 \
+ IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 \
+ IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 \
+ IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__GPIO_2_4 \
+ IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 \
+ IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 \
+ IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D5__RAWNAND_D5 \
+ IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__USDHC2_DAT5 \
+ IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 \
+ IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 \
+ IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 \
+ IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__GPIO_2_5 \
+ IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 \
+ IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 \
+ IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D6__RAWNAND_D6 \
+ IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__USDHC2_DAT6 \
+ IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 \
+ IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 \
+ IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 \
+ IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__GPIO_2_6 \
+ IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 \
+ IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 \
+ IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_NANDF_D7__RAWNAND_D7 \
+ IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__USDHC2_DAT7 \
+ IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 \
+ IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 \
+ IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 \
+ IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__GPIO_2_7 \
+ IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 \
+ IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 \
+ IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT0__RAWNAND_D8 \
+ IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 \
+ IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__RAWNAND_DQS \
+ IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 \
+ IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 \
+ IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__GPIO_2_8 \
+ IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 \
+ IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 \
+ IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT1__RAWNAND_D9 \
+ IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 \
+ IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__PWM3_PWMO \
+ IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 \
+ IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 \
+ IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__GPIO_2_9 \
+ IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 \
+ IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 \
+ IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT2__RAWNAND_D10 \
+ IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 \
+ IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__PWM4_PWMO \
+ IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 \
+ IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 \
+ IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__GPIO_2_10 \
+ IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 \
+ IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 \
+ IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT3__RAWNAND_D11 \
+ IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 \
+ IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 \
+ IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 \
+ IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__GPIO_2_11 \
+ IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 \
+ IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 \
+ IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT4__RAWNAND_D12 \
+ IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 \
+ IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__UART2_TXD \
+ IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__UART2_RXD \
+ IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0)
+#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 \
+ IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 \
+ IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__GPIO_2_12 \
+ IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 \
+ IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 \
+ IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT5__RAWNAND_D13 \
+ IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 \
+ IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__UART2_CTS \
+ IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__UART2_RTS \
+ IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0)
+#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 \
+ IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 \
+ IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__GPIO_2_13 \
+ IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 \
+ IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 \
+ IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT6__RAWNAND_D14 \
+ IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 \
+ IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__UART2_CTS \
+ IOMUX_PAD(0x071C, 0x0334, 2, 0x0000, 5, 0)
+#define _MX6Q_PAD_SD4_DAT6__UART2_RTS \
+ IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0)
+#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 \
+ IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 \
+ IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__GPIO_2_14 \
+ IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 \
+ IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 \
+ IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD4_DAT7__RAWNAND_D15 \
+ IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 \
+ IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__UART2_TXD \
+ IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__UART2_RXD \
+ IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0)
+#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 \
+ IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 \
+ IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__GPIO_2_15 \
+ IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 \
+ IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 \
+ IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 \
+ IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 \
+ IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0)
+#define _MX6Q_PAD_SD1_DAT1__PWM3_PWMO \
+ IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 \
+ IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 \
+ IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__GPIO_1_17 \
+ IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 \
+ IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 \
+ IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 \
+ IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__ECSPI5_MISO \
+ IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0)
+#define _MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS \
+ IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 \
+ IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 \
+ IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__GPIO_1_16 \
+ IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 \
+ IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 \
+ IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 \
+ IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 \
+ IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 \
+ IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__PWM1_PWMO \
+ IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B \
+ IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__GPIO_1_21 \
+ IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB \
+ IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 \
+ IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_CMD__USDHC1_CMD \
+ IOMUX_PAD(0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__ECSPI5_MOSI \
+ IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__PWM4_PWMO \
+ IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 \
+ IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__GPIO_1_18 \
+ IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 \
+ IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 \
+ IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 \
+ IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0)
+#define _MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 \
+ IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__PWM2_PWMO \
+ IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B \
+ IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__GPIO_1_19 \
+ IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB \
+ IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 \
+ IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD1_CLK__USDHC1_CLK \
+ IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__ECSPI5_SCLK \
+ IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT \
+ IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__GPT_CLKIN \
+ IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__GPIO_1_20 \
+ IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__PHY_DTB_0 \
+ IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 \
+ IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_CLK__USDHC2_CLK \
+ IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CLK__ECSPI5_SCLK \
+ IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0)
+#define _MX6Q_PAD_SD2_CLK__KPP_COL_5 \
+ IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0)
+#define _MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \
+ IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0)
+#define _MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 \
+ IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CLK__GPIO_1_10 \
+ IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CLK__PHY_DTB_1 \
+ IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 \
+ IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_CMD__USDHC2_CMD \
+ IOMUX_PAD(0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CMD__ECSPI5_MOSI \
+ IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0)
+#define _MX6Q_PAD_SD2_CMD__KPP_ROW_5 \
+ IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0)
+#define _MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC \
+ IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0)
+#define _MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 \
+ IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_CMD__GPIO_1_11 \
+ IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0)
+
+#define _MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 \
+ IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 \
+ IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__KPP_COL_6 \
+ IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0)
+#define _MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC \
+ IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0)
+#define _MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 \
+ IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__GPIO_1_12 \
+ IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__SJC_DONE \
+ IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0)
+#define _MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \
+ IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0)
+
+#define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 (_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0)
+#define MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 (_MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2)
+#define MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS (_MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS)
+#define MX6Q_PAD_SD2_DAT1__KPP_COL_7 (_MX6Q_PAD_SD2_DAT1__KPP_COL_7)
+#define MX6Q_PAD_SD2_DAT1__GPIO_1_14 (_MX6Q_PAD_SD2_DAT1__GPIO_1_14)
+#define MX6Q_PAD_SD2_DAT1__CCM_WAIT (_MX6Q_PAD_SD2_DAT1__CCM_WAIT)
+#define MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 (_MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0)
+
+#define MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 (_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 (_MX6Q_PAD_SD2_DAT2__ECSPI5_SS1)
+#define MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 (_MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3)
+#define MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD (_MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD)
+#define MX6Q_PAD_SD2_DAT2__KPP_ROW_6 (_MX6Q_PAD_SD2_DAT2__KPP_ROW_6)
+#define MX6Q_PAD_SD2_DAT2__GPIO_1_13 (_MX6Q_PAD_SD2_DAT2__GPIO_1_13)
+#define MX6Q_PAD_SD2_DAT2__CCM_STOP (_MX6Q_PAD_SD2_DAT2__CCM_STOP)
+#define MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 (_MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1)
+
+#define MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 (_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO (_MX6Q_PAD_SD2_DAT0__ECSPI5_MISO)
+#define MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD (_MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD)
+#define MX6Q_PAD_SD2_DAT0__KPP_ROW_7 (_MX6Q_PAD_SD2_DAT0__KPP_ROW_7)
+#define MX6Q_PAD_SD2_DAT0__GPIO_1_15 (_MX6Q_PAD_SD2_DAT0__GPIO_1_15)
+#define MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT (_MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT)
+#define MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 (_MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2)
+
+#define MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA (_MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA)
+#define MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC (_MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK (_MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK)
+#define MX6Q_PAD_RGMII_TXC__GPIO_6_19 (_MX6Q_PAD_RGMII_TXC__GPIO_6_19)
+#define MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 (_MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0)
+#define MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT (_MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT)
+
+#define MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY (_MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY)
+#define MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 (_MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD0__GPIO_6_20 (_MX6Q_PAD_RGMII_TD0__GPIO_6_20)
+#define MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 (_MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1)
+
+#define MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG (_MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG)
+#define MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 (_MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD1__GPIO_6_21 (_MX6Q_PAD_RGMII_TD1__GPIO_6_21)
+#define MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 (_MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2)
+#define MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP (_MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP)
+
+#define MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA (_MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA)
+#define MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 (_MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD2__GPIO_6_22 (_MX6Q_PAD_RGMII_TD2__GPIO_6_22)
+#define MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 (_MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3)
+#define MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP (_MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP)
+
+#define MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE (_MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE)
+#define MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 (_MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TD3__GPIO_6_23 (_MX6Q_PAD_RGMII_TD3__GPIO_6_23)
+#define MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 (_MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4)
+
+#define MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA (_MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA)
+#define MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL (_MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 (_MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24)
+#define MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 (_MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5)
+
+#define MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY (_MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY)
+#define MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 (_MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD0__GPIO_6_25 (_MX6Q_PAD_RGMII_RD0__GPIO_6_25)
+#define MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 (_MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6)
+
+#define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE)
+#define MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL (_MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 (_MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26)
+#define MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 (_MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7)
+#define MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT (_MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT)
+
+#define MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG (_MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG)
+#define MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 (_MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD1__GPIO_6_27 (_MX6Q_PAD_RGMII_RD1__GPIO_6_27)
+#define MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 (_MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8)
+#define MX6Q_PAD_RGMII_RD1__SJC_FAIL (_MX6Q_PAD_RGMII_RD1__SJC_FAIL)
+
+#define MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA (_MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA)
+#define MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 (_MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD2__GPIO_6_28 (_MX6Q_PAD_RGMII_RD2__GPIO_6_28)
+#define MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 (_MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9)
+
+#define MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE (_MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE)
+#define MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 (_MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RD3__GPIO_6_29 (_MX6Q_PAD_RGMII_RD3__GPIO_6_29)
+#define MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 (_MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10)
+
+#define MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE (_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE)
+#define MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC (_MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_RGMII_RXC__GPIO_6_30 (_MX6Q_PAD_RGMII_RXC__GPIO_6_30)
+#define MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 (_MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11)
+
+#define MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 (_MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25)
+#define MX6Q_PAD_EIM_A25__ECSPI4_SS1 (_MX6Q_PAD_EIM_A25__ECSPI4_SS1)
+#define MX6Q_PAD_EIM_A25__ECSPI2_RDY (_MX6Q_PAD_EIM_A25__ECSPI2_RDY)
+#define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 (_MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12)
+#define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS (_MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS)
+#define MX6Q_PAD_EIM_A25__GPIO_5_2 (_MX6Q_PAD_EIM_A25__GPIO_5_2)
+#define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE (_MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE)
+#define MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 (_MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0)
+
+#define MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 (_MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2)
+#define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 (_MX6Q_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK (_MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK)
+#define MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 (_MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19)
+#define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL (_MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL)
+#define MX6Q_PAD_EIM_EB2__GPIO_2_30 (_MX6Q_PAD_EIM_EB2__GPIO_2_30)
+#define MX6Q_PAD_EIM_EB2__I2C2_SCL (_MX6Q_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 (_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30)
+
+#define MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16)
+#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 (_MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5)
+#define MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 (_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18)
+#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA (_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA)
+#define MX6Q_PAD_EIM_D16__GPIO_3_16 (_MX6Q_PAD_EIM_D16__GPIO_3_16)
+#define MX6Q_PAD_EIM_D16__I2C2_SDA (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17)
+#define MX6Q_PAD_EIM_D17__ECSPI1_MISO (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 (_MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6)
+#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK (_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK)
+#define MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT (_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT)
+#define MX6Q_PAD_EIM_D17__GPIO_3_17 (_MX6Q_PAD_EIM_D17__GPIO_3_17)
+#define MX6Q_PAD_EIM_D17__I2C3_SCL (_MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 (_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1)
+
+#define MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18)
+#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 (_MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7)
+#define MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 (_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17)
+#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS (_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS)
+#define MX6Q_PAD_EIM_D18__GPIO_3_18 (_MX6Q_PAD_EIM_D18__GPIO_3_18)
+#define MX6Q_PAD_EIM_D18__I2C3_SDA (_MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 (_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2)
+
+#define MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19)
+#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 (_MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8)
+#define MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 (_MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16)
+#define MX6Q_PAD_EIM_D19__UART1_CTS (_MX6Q_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__GPIO_3_19 (_MX6Q_PAD_EIM_D19__GPIO_3_19)
+#define MX6Q_PAD_EIM_D19__EPIT1_EPITO (_MX6Q_PAD_EIM_D19__EPIT1_EPITO)
+#define MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP (_MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP)
+
+#define MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 (_MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20)
+#define MX6Q_PAD_EIM_D20__ECSPI4_SS0 (_MX6Q_PAD_EIM_D20__ECSPI4_SS0)
+#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 (_MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16)
+#define MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 (_MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15)
+#define MX6Q_PAD_EIM_D20__UART1_CTS (_MX6Q_PAD_EIM_D20__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D20__UART1_RTS (_MX6Q_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D20__GPIO_3_20 (_MX6Q_PAD_EIM_D20__GPIO_3_20)
+#define MX6Q_PAD_EIM_D20__EPIT2_EPITO (_MX6Q_PAD_EIM_D20__EPIT2_EPITO)
+
+#define MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 (_MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21)
+#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK (_MX6Q_PAD_EIM_D21__ECSPI4_SCLK)
+#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 (_MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17)
+#define MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 (_MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11)
+#define MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC (_MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC)
+#define MX6Q_PAD_EIM_D21__GPIO_3_21 (_MX6Q_PAD_EIM_D21__GPIO_3_21)
+#define MX6Q_PAD_EIM_D21__I2C1_SCL (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_EIM_D21__SPDIF_IN1 (_MX6Q_PAD_EIM_D21__SPDIF_IN1)
+
+#define MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 (_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22)
+#define MX6Q_PAD_EIM_D22__ECSPI4_MISO (_MX6Q_PAD_EIM_D22__ECSPI4_MISO)
+#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 (_MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1)
+#define MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 (_MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10)
+#define MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR (_MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR)
+#define MX6Q_PAD_EIM_D22__GPIO_3_22 (_MX6Q_PAD_EIM_D22__GPIO_3_22)
+#define MX6Q_PAD_EIM_D22__SPDIF_OUT1 (_MX6Q_PAD_EIM_D22__SPDIF_OUT1)
+#define MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE (_MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE)
+
+#define MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 (_MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23)
+#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS (_MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS)
+#define MX6Q_PAD_EIM_D23__UART3_CTS (_MX6Q_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D23__UART1_DCD (_MX6Q_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN (_MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN)
+#define MX6Q_PAD_EIM_D23__GPIO_3_23 (_MX6Q_PAD_EIM_D23__GPIO_3_23)
+#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2)
+#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 (_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14)
+
+#define MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 (_MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3)
+#define MX6Q_PAD_EIM_EB3__ECSPI4_RDY (_MX6Q_PAD_EIM_EB3__ECSPI4_RDY)
+#define MX6Q_PAD_EIM_EB3__UART3_CTS (_MX6Q_PAD_EIM_EB3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__UART3_RTS (_MX6Q_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__UART1_RI (_MX6Q_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC (_MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC)
+#define MX6Q_PAD_EIM_EB3__GPIO_2_31 (_MX6Q_PAD_EIM_EB3__GPIO_2_31)
+#define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 (_MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3)
+#define MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 (_MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31)
+
+#define MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 (_MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24)
+#define MX6Q_PAD_EIM_D24__ECSPI4_SS2 (_MX6Q_PAD_EIM_D24__ECSPI4_SS2)
+#define MX6Q_PAD_EIM_D24__UART3_TXD (_MX6Q_PAD_EIM_D24__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D24__UART3_RXD (_MX6Q_PAD_EIM_D24__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D24__ECSPI1_SS2 (_MX6Q_PAD_EIM_D24__ECSPI1_SS2)
+#define MX6Q_PAD_EIM_D24__ECSPI2_SS2 (_MX6Q_PAD_EIM_D24__ECSPI2_SS2)
+#define MX6Q_PAD_EIM_D24__GPIO_3_24 (_MX6Q_PAD_EIM_D24__GPIO_3_24)
+#define MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS (_MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS)
+#define MX6Q_PAD_EIM_D24__UART1_DTR (_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 (_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25)
+#define MX6Q_PAD_EIM_D25__ECSPI4_SS3 (_MX6Q_PAD_EIM_D25__ECSPI4_SS3)
+#define MX6Q_PAD_EIM_D25__UART3_TXD (_MX6Q_PAD_EIM_D25__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__UART3_RXD (_MX6Q_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D25__ECSPI1_SS3 (_MX6Q_PAD_EIM_D25__ECSPI1_SS3)
+#define MX6Q_PAD_EIM_D25__ECSPI2_SS3 (_MX6Q_PAD_EIM_D25__ECSPI2_SS3)
+#define MX6Q_PAD_EIM_D25__GPIO_3_25 (_MX6Q_PAD_EIM_D25__GPIO_3_25)
+#define MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC (_MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC)
+#define MX6Q_PAD_EIM_D25__UART1_DSR (_MX6Q_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+
+#define MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 (_MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26)
+#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 (_MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11)
+#define MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 (_MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1)
+#define MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 (_MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14)
+#define MX6Q_PAD_EIM_D26__UART2_TXD (_MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__UART2_RXD (_MX6Q_PAD_EIM_D26__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D26__GPIO_3_26 (_MX6Q_PAD_EIM_D26__GPIO_3_26)
+#define MX6Q_PAD_EIM_D26__IPU1_SISG_2 (_MX6Q_PAD_EIM_D26__IPU1_SISG_2)
+#define MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 (_MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22)
+
+#define MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 (_MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27)
+#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 (_MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13)
+#define MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 (_MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0)
+#define MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 (_MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13)
+#define MX6Q_PAD_EIM_D27__UART2_TXD (_MX6Q_PAD_EIM_D27__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__UART2_RXD (_MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D27__GPIO_3_27 (_MX6Q_PAD_EIM_D27__GPIO_3_27)
+#define MX6Q_PAD_EIM_D27__IPU1_SISG_3 (_MX6Q_PAD_EIM_D27__IPU1_SISG_3)
+#define MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 (_MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23)
+
+#define MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28)
+#define MX6Q_PAD_EIM_D28__I2C1_SDA (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI (_MX6Q_PAD_EIM_D28__ECSPI4_MOSI)
+#define MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 (_MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12)
+#define MX6Q_PAD_EIM_D28__UART2_CTS (_MX6Q_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D28__GPIO_3_28 (_MX6Q_PAD_EIM_D28__GPIO_3_28)
+#define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG (_MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG)
+#define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 (_MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13)
+
+#define MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 (_MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29)
+#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 (_MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15)
+#define MX6Q_PAD_EIM_D29__ECSPI4_SS0 (_MX6Q_PAD_EIM_D29__ECSPI4_SS0)
+#define MX6Q_PAD_EIM_D29__UART2_CTS (_MX6Q_PAD_EIM_D29__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D29__UART2_RTS (_MX6Q_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D29__GPIO_3_29 (_MX6Q_PAD_EIM_D29__GPIO_3_29)
+#define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC (_MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC)
+#define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 (_MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14)
+
+#define MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 (_MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30)
+#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 (_MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21)
+#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 (_MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11)
+#define MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 (_MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3)
+#define MX6Q_PAD_EIM_D30__UART3_CTS (_MX6Q_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D30__GPIO_3_30 (_MX6Q_PAD_EIM_D30__GPIO_3_30)
+#define MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC (_MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC)
+#define MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 (_MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0)
+
+#define MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 (_MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31)
+#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 (_MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20)
+#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 (_MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12)
+#define MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 (_MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2)
+#define MX6Q_PAD_EIM_D31__UART3_CTS (_MX6Q_PAD_EIM_D31__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__UART3_RTS (_MX6Q_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_EIM_D31__GPIO_3_31 (_MX6Q_PAD_EIM_D31__GPIO_3_31)
+#define MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR (_MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR)
+#define MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 (_MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1)
+
+#define MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 (_MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24)
+#define MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 (_MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19)
+#define MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 (_MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19)
+#define MX6Q_PAD_EIM_A24__IPU2_SISG_2 (_MX6Q_PAD_EIM_A24__IPU2_SISG_2)
+#define MX6Q_PAD_EIM_A24__IPU1_SISG_2 (_MX6Q_PAD_EIM_A24__IPU1_SISG_2)
+#define MX6Q_PAD_EIM_A24__GPIO_5_4 (_MX6Q_PAD_EIM_A24__GPIO_5_4)
+#define MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 (_MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2)
+#define MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 (_MX6Q_PAD_EIM_A24__SRC_BT_CFG_24)
+
+#define MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 (_MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23)
+#define MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 (_MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18)
+#define MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 (_MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18)
+#define MX6Q_PAD_EIM_A23__IPU2_SISG_3 (_MX6Q_PAD_EIM_A23__IPU2_SISG_3)
+#define MX6Q_PAD_EIM_A23__IPU1_SISG_3 (_MX6Q_PAD_EIM_A23__IPU1_SISG_3)
+#define MX6Q_PAD_EIM_A23__GPIO_6_6 (_MX6Q_PAD_EIM_A23__GPIO_6_6)
+#define MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 (_MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3)
+#define MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 (_MX6Q_PAD_EIM_A23__SRC_BT_CFG_23)
+
+#define MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 (_MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22)
+#define MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 (_MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17)
+#define MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 (_MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17)
+#define MX6Q_PAD_EIM_A22__GPIO_2_16 (_MX6Q_PAD_EIM_A22__GPIO_2_16)
+#define MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 (_MX6Q_PAD_EIM_A22__TPSMP_HDATA_0)
+#define MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 (_MX6Q_PAD_EIM_A22__SRC_BT_CFG_22)
+
+#define MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 (_MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21)
+#define MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 (_MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16)
+#define MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 (_MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16)
+#define MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 (_MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18)
+#define MX6Q_PAD_EIM_A21__GPIO_2_17 (_MX6Q_PAD_EIM_A21__GPIO_2_17)
+#define MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 (_MX6Q_PAD_EIM_A21__TPSMP_HDATA_1)
+#define MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 (_MX6Q_PAD_EIM_A21__SRC_BT_CFG_21)
+
+#define MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 (_MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20)
+#define MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 (_MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15)
+#define MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 (_MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15)
+#define MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 (_MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19)
+#define MX6Q_PAD_EIM_A20__GPIO_2_18 (_MX6Q_PAD_EIM_A20__GPIO_2_18)
+#define MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 (_MX6Q_PAD_EIM_A20__TPSMP_HDATA_2)
+#define MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 (_MX6Q_PAD_EIM_A20__SRC_BT_CFG_20)
+
+#define MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 (_MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19)
+#define MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 (_MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14)
+#define MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 (_MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14)
+#define MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 (_MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20)
+#define MX6Q_PAD_EIM_A19__GPIO_2_19 (_MX6Q_PAD_EIM_A19__GPIO_2_19)
+#define MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 (_MX6Q_PAD_EIM_A19__TPSMP_HDATA_3)
+#define MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 (_MX6Q_PAD_EIM_A19__SRC_BT_CFG_19)
+
+#define MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 (_MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18)
+#define MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 (_MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13)
+#define MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 (_MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13)
+#define MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 (_MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21)
+#define MX6Q_PAD_EIM_A18__GPIO_2_20 (_MX6Q_PAD_EIM_A18__GPIO_2_20)
+#define MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 (_MX6Q_PAD_EIM_A18__TPSMP_HDATA_4)
+#define MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 (_MX6Q_PAD_EIM_A18__SRC_BT_CFG_18)
+
+#define MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 (_MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17)
+#define MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 (_MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12)
+#define MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 (_MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12)
+#define MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 (_MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22)
+#define MX6Q_PAD_EIM_A17__GPIO_2_21 (_MX6Q_PAD_EIM_A17__GPIO_2_21)
+#define MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 (_MX6Q_PAD_EIM_A17__TPSMP_HDATA_5)
+#define MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 (_MX6Q_PAD_EIM_A17__SRC_BT_CFG_17)
+
+#define MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 (_MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16)
+#define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK (_MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK)
+#define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK (_MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK)
+#define MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 (_MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23)
+#define MX6Q_PAD_EIM_A16__GPIO_2_22 (_MX6Q_PAD_EIM_A16__GPIO_2_22)
+#define MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 (_MX6Q_PAD_EIM_A16__TPSMP_HDATA_6)
+#define MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 (_MX6Q_PAD_EIM_A16__SRC_BT_CFG_16)
+
+#define MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 (_MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0)
+#define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 (_MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5)
+#define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK (_MX6Q_PAD_EIM_CS0__ECSPI2_SCLK)
+#define MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 (_MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24)
+#define MX6Q_PAD_EIM_CS0__GPIO_2_23 (_MX6Q_PAD_EIM_CS0__GPIO_2_23)
+#define MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 (_MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7)
+
+#define MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 (_MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1)
+#define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 (_MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6)
+#define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI (_MX6Q_PAD_EIM_CS1__ECSPI2_MOSI)
+#define MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 (_MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25)
+#define MX6Q_PAD_EIM_CS1__GPIO_2_24 (_MX6Q_PAD_EIM_CS1__GPIO_2_24)
+#define MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 (_MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8)
+
+#define MX6Q_PAD_EIM_OE__WEIM_WEIM_OE (_MX6Q_PAD_EIM_OE__WEIM_WEIM_OE)
+#define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 (_MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7)
+#define MX6Q_PAD_EIM_OE__ECSPI2_MISO (_MX6Q_PAD_EIM_OE__ECSPI2_MISO)
+#define MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 (_MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26)
+#define MX6Q_PAD_EIM_OE__GPIO_2_25 (_MX6Q_PAD_EIM_OE__GPIO_2_25)
+#define MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 (_MX6Q_PAD_EIM_OE__TPSMP_HDATA_9)
+
+#define MX6Q_PAD_EIM_RW__WEIM_WEIM_RW (_MX6Q_PAD_EIM_RW__WEIM_WEIM_RW)
+#define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 (_MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8)
+#define MX6Q_PAD_EIM_RW__ECSPI2_SS0 (_MX6Q_PAD_EIM_RW__ECSPI2_SS0)
+#define MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 (_MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27)
+#define MX6Q_PAD_EIM_RW__GPIO_2_26 (_MX6Q_PAD_EIM_RW__GPIO_2_26)
+#define MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 (_MX6Q_PAD_EIM_RW__TPSMP_HDATA_10)
+#define MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 (_MX6Q_PAD_EIM_RW__SRC_BT_CFG_29)
+
+#define MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA (_MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA)
+#define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 (_MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17)
+#define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 (_MX6Q_PAD_EIM_LBA__ECSPI2_SS1)
+#define MX6Q_PAD_EIM_LBA__GPIO_2_27 (_MX6Q_PAD_EIM_LBA__GPIO_2_27)
+#define MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 (_MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11)
+#define MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 (_MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26)
+
+#define MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 (_MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0)
+#define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 (_MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11)
+#define MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 (_MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11)
+#define MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 (_MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0)
+#define MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY (_MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY)
+#define MX6Q_PAD_EIM_EB0__GPIO_2_28 (_MX6Q_PAD_EIM_EB0__GPIO_2_28)
+#define MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 (_MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12)
+#define MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 (_MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27)
+
+#define MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 (_MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1)
+#define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 (_MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10)
+#define MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 (_MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10)
+#define MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 (_MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1)
+#define MX6Q_PAD_EIM_EB1__GPIO_2_29 (_MX6Q_PAD_EIM_EB1__GPIO_2_29)
+#define MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 (_MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13)
+#define MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 (_MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28)
+
+#define MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 (_MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0)
+#define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 (_MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9)
+#define MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 (_MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9)
+#define MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 (_MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2)
+#define MX6Q_PAD_EIM_DA0__GPIO_3_0 (_MX6Q_PAD_EIM_DA0__GPIO_3_0)
+#define MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 (_MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14)
+#define MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 (_MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0)
+
+#define MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 (_MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1)
+#define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 (_MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8)
+#define MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 (_MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8)
+#define MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 (_MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3)
+#define MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE (_MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE)
+#define MX6Q_PAD_EIM_DA1__GPIO_3_1 (_MX6Q_PAD_EIM_DA1__GPIO_3_1)
+#define MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 (_MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15)
+#define MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 (_MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1)
+
+#define MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 (_MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2)
+#define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 (_MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7)
+#define MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 (_MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7)
+#define MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 (_MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4)
+#define MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE (_MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE)
+#define MX6Q_PAD_EIM_DA2__GPIO_3_2 (_MX6Q_PAD_EIM_DA2__GPIO_3_2)
+#define MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 (_MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16)
+#define MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 (_MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2)
+
+#define MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 (_MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3)
+#define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 (_MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6)
+#define MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 (_MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6)
+#define MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 (_MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5)
+#define MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ (_MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ)
+#define MX6Q_PAD_EIM_DA3__GPIO_3_3 (_MX6Q_PAD_EIM_DA3__GPIO_3_3)
+#define MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 (_MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17)
+#define MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 (_MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3)
+
+#define MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 (_MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4)
+#define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 (_MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5)
+#define MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 (_MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5)
+#define MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 (_MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6)
+#define MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN (_MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN)
+#define MX6Q_PAD_EIM_DA4__GPIO_3_4 (_MX6Q_PAD_EIM_DA4__GPIO_3_4)
+#define MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 (_MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18)
+#define MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 (_MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4)
+
+#define MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 (_MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5)
+#define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 (_MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4)
+#define MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 (_MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4)
+#define MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 (_MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7)
+#define MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP (_MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP)
+#define MX6Q_PAD_EIM_DA5__GPIO_3_5 (_MX6Q_PAD_EIM_DA5__GPIO_3_5)
+#define MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 (_MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19)
+#define MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 (_MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5)
+
+#define MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 (_MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6)
+#define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 (_MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3)
+#define MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 (_MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3)
+#define MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 (_MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8)
+#define MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN (_MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN)
+#define MX6Q_PAD_EIM_DA6__GPIO_3_6 (_MX6Q_PAD_EIM_DA6__GPIO_3_6)
+#define MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 (_MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20)
+#define MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 (_MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6)
+
+#define MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 (_MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7)
+#define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 (_MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2)
+#define MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 (_MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2)
+#define MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 (_MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9)
+#define MX6Q_PAD_EIM_DA7__GPIO_3_7 (_MX6Q_PAD_EIM_DA7__GPIO_3_7)
+#define MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 (_MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21)
+#define MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 (_MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7)
+
+#define MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 (_MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8)
+#define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 (_MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1)
+#define MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 (_MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1)
+#define MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 (_MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10)
+#define MX6Q_PAD_EIM_DA8__GPIO_3_8 (_MX6Q_PAD_EIM_DA8__GPIO_3_8)
+#define MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 (_MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22)
+#define MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 (_MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8)
+
+#define MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 (_MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9)
+#define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 (_MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0)
+#define MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 (_MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0)
+#define MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 (_MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11)
+#define MX6Q_PAD_EIM_DA9__GPIO_3_9 (_MX6Q_PAD_EIM_DA9__GPIO_3_9)
+#define MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 (_MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23)
+#define MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 (_MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9)
+
+#define MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 (_MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10)
+#define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 (_MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15)
+#define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN (_MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN)
+#define MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 (_MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12)
+#define MX6Q_PAD_EIM_DA10__GPIO_3_10 (_MX6Q_PAD_EIM_DA10__GPIO_3_10)
+#define MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 (_MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24)
+#define MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 (_MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10)
+
+#define MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 (_MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11)
+#define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 (_MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2)
+#define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC (_MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC)
+#define MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 (_MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13)
+#define MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 (_MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6)
+#define MX6Q_PAD_EIM_DA11__GPIO_3_11 (_MX6Q_PAD_EIM_DA11__GPIO_3_11)
+#define MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 (_MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25)
+#define MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 (_MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11)
+
+#define MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 (_MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12)
+#define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 (_MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3)
+#define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC (_MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC)
+#define MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 (_MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14)
+#define MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 (_MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3)
+#define MX6Q_PAD_EIM_DA12__GPIO_3_12 (_MX6Q_PAD_EIM_DA12__GPIO_3_12)
+#define MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 (_MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26)
+#define MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 (_MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12)
+
+#define MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 (_MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13)
+#define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS (_MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS)
+#define MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK (_MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK)
+#define MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 (_MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15)
+#define MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 (_MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4)
+#define MX6Q_PAD_EIM_DA13__GPIO_3_13 (_MX6Q_PAD_EIM_DA13__GPIO_3_13)
+#define MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 (_MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27)
+#define MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 (_MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13)
+
+#define MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 (_MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14)
+#define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS (_MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS)
+#define MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK (_MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK)
+#define MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 (_MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16)
+#define MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 (_MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5)
+#define MX6Q_PAD_EIM_DA14__GPIO_3_14 (_MX6Q_PAD_EIM_DA14__GPIO_3_14)
+#define MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 (_MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28)
+#define MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 (_MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14)
+
+#define MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 (_MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15)
+#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1)
+#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 (_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4)
+#define MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 (_MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17)
+#define MX6Q_PAD_EIM_DA15__GPIO_3_15 (_MX6Q_PAD_EIM_DA15__GPIO_3_15)
+#define MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 (_MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29)
+#define MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 (_MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15)
+
+#define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT)
+#define MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B (_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B)
+#define MX6Q_PAD_EIM_WAIT__GPIO_5_0 (_MX6Q_PAD_EIM_WAIT__GPIO_5_0)
+#define MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 (_MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30)
+#define MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 (_MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25)
+
+#define MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK (_MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK)
+#define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 (_MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16)
+#define MX6Q_PAD_EIM_BCLK__GPIO_6_31 (_MX6Q_PAD_EIM_BCLK__GPIO_6_31)
+#define MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 (_MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31)
+
+#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK (_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK)
+#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK (_MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK)
+#define MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 (_MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28)
+#define MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 (_MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0)
+#define MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 (_MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16)
+#define MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 (_MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0)
+
+#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 (_MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15)
+#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 (_MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15)
+#define MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC (_MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC)
+#define MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 (_MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29)
+#define MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 (_MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1)
+#define MX6Q_PAD_DI0_PIN15__GPIO_4_17 (_MX6Q_PAD_DI0_PIN15__GPIO_4_17)
+#define MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 (_MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1)
+
+#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 (_MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2)
+#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 (_MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2)
+#define MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD (_MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD)
+#define MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 (_MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30)
+#define MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 (_MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2)
+#define MX6Q_PAD_DI0_PIN2__GPIO_4_18 (_MX6Q_PAD_DI0_PIN2__GPIO_4_18)
+#define MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 (_MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2)
+#define MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 (_MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9)
+
+#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 (_MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3)
+#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 (_MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3)
+#define MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS (_MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS)
+#define MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 (_MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31)
+#define MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 (_MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3)
+#define MX6Q_PAD_DI0_PIN3__GPIO_4_19 (_MX6Q_PAD_DI0_PIN3__GPIO_4_19)
+#define MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 (_MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3)
+#define MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 (_MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10)
+
+#define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 (_MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4)
+#define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 (_MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4)
+#define MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD (_MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD)
+#define MX6Q_PAD_DI0_PIN4__USDHC1_WP (_MX6Q_PAD_DI0_PIN4__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD (_MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD)
+#define MX6Q_PAD_DI0_PIN4__GPIO_4_20 (_MX6Q_PAD_DI0_PIN4__GPIO_4_20)
+#define MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 (_MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4)
+#define MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 (_MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11)
+
+#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 (_MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0)
+#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 (_MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0)
+#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK (_MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK)
+#define MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 (_MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN (_MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN)
+#define MX6Q_PAD_DISP0_DAT0__GPIO_4_21 (_MX6Q_PAD_DISP0_DAT0__GPIO_4_21)
+#define MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 (_MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5)
+
+#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 (_MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1)
+#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 (_MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1)
+#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI (_MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI)
+#define MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 (_MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL (_MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL)
+#define MX6Q_PAD_DISP0_DAT1__GPIO_4_22 (_MX6Q_PAD_DISP0_DAT1__GPIO_4_22)
+#define MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 (_MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6)
+#define MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 (_MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12)
+
+#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 (_MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2)
+#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 (_MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2)
+#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO (_MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO)
+#define MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 (_MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE (_MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE)
+#define MX6Q_PAD_DISP0_DAT2__GPIO_4_23 (_MX6Q_PAD_DISP0_DAT2__GPIO_4_23)
+#define MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 (_MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7)
+#define MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 (_MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13)
+
+#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 (_MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3)
+#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 (_MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3)
+#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 (_MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0)
+#define MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 (_MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR (_MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR)
+#define MX6Q_PAD_DISP0_DAT3__GPIO_4_24 (_MX6Q_PAD_DISP0_DAT3__GPIO_4_24)
+#define MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 (_MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8)
+#define MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 (_MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14)
+
+#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 (_MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4)
+#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 (_MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4)
+#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 (_MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1)
+#define MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 (_MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB (_MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB)
+#define MX6Q_PAD_DISP0_DAT4__GPIO_4_25 (_MX6Q_PAD_DISP0_DAT4__GPIO_4_25)
+#define MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 (_MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9)
+#define MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 (_MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15)
+
+#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 (_MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5)
+#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 (_MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5)
+#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 (_MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2)
+#define MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS (_MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS)
+#define MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS (_MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS)
+#define MX6Q_PAD_DISP0_DAT5__GPIO_4_26 (_MX6Q_PAD_DISP0_DAT5__GPIO_4_26)
+#define MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 (_MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10)
+#define MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 (_MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16)
+
+#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 (_MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6)
+#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 (_MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6)
+#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 (_MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3)
+#define MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC (_MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC)
+#define MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE (_MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE)
+#define MX6Q_PAD_DISP0_DAT6__GPIO_4_27 (_MX6Q_PAD_DISP0_DAT6__GPIO_4_27)
+#define MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 (_MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11)
+#define MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 (_MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17)
+
+#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 (_MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7)
+#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 (_MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7)
+#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY (_MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY)
+#define MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 (_MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 (_MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0)
+#define MX6Q_PAD_DISP0_DAT7__GPIO_4_28 (_MX6Q_PAD_DISP0_DAT7__GPIO_4_28)
+#define MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 (_MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12)
+#define MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 (_MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18)
+
+#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 (_MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8)
+#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 (_MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8)
+#define MX6Q_PAD_DISP0_DAT8__PWM1_PWMO (_MX6Q_PAD_DISP0_DAT8__PWM1_PWMO)
+#define MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B (_MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B)
+#define MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 (_MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1)
+#define MX6Q_PAD_DISP0_DAT8__GPIO_4_29 (_MX6Q_PAD_DISP0_DAT8__GPIO_4_29)
+#define MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 (_MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13)
+#define MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 (_MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19)
+
+#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 (_MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9)
+#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 (_MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9)
+#define MX6Q_PAD_DISP0_DAT9__PWM2_PWMO (_MX6Q_PAD_DISP0_DAT9__PWM2_PWMO)
+#define MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B (_MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B)
+#define MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 (_MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2)
+#define MX6Q_PAD_DISP0_DAT9__GPIO_4_30 (_MX6Q_PAD_DISP0_DAT9__GPIO_4_30)
+#define MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 (_MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14)
+#define MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 (_MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20)
+
+#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 (_MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10)
+#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 (_MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10)
+#define MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 (_MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 (_MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3)
+#define MX6Q_PAD_DISP0_DAT10__GPIO_4_31 (_MX6Q_PAD_DISP0_DAT10__GPIO_4_31)
+#define MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 (_MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15)
+#define MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 (_MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21)
+
+#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 (_MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11)
+#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 (_MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11)
+#define MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 (_MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 (_MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4)
+#define MX6Q_PAD_DISP0_DAT11__GPIO_5_5 (_MX6Q_PAD_DISP0_DAT11__GPIO_5_5)
+#define MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 (_MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16)
+#define MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 (_MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22)
+
+#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 (_MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12)
+#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 (_MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12)
+#define MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 (_MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5)
+#define MX6Q_PAD_DISP0_DAT12__GPIO_5_6 (_MX6Q_PAD_DISP0_DAT12__GPIO_5_6)
+#define MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 (_MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17)
+#define MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 (_MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23)
+
+#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 (_MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13)
+#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 (_MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13)
+#define MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS (_MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS)
+#define MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 (_MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0)
+#define MX6Q_PAD_DISP0_DAT13__GPIO_5_7 (_MX6Q_PAD_DISP0_DAT13__GPIO_5_7)
+#define MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 (_MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18)
+#define MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 (_MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24)
+
+#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 (_MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14)
+#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 (_MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14)
+#define MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC (_MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC)
+#define MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 (_MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1)
+#define MX6Q_PAD_DISP0_DAT14__GPIO_5_8 (_MX6Q_PAD_DISP0_DAT14__GPIO_5_8)
+#define MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 (_MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19)
+
+#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 (_MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15)
+#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 (_MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15)
+#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 (_MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1)
+#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 (_MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1)
+#define MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 (_MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2)
+#define MX6Q_PAD_DISP0_DAT15__GPIO_5_9 (_MX6Q_PAD_DISP0_DAT15__GPIO_5_9)
+#define MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 (_MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20)
+#define MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 (_MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25)
+
+#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 (_MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16)
+#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 (_MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16)
+#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI (_MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI)
+#define MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC (_MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC)
+#define MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 (_MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0)
+#define MX6Q_PAD_DISP0_DAT16__GPIO_5_10 (_MX6Q_PAD_DISP0_DAT16__GPIO_5_10)
+#define MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 (_MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21)
+#define MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 (_MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26)
+
+#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 (_MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17)
+#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 (_MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17)
+#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO (_MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO)
+#define MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD (_MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD)
+#define MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 (_MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1)
+#define MX6Q_PAD_DISP0_DAT17__GPIO_5_11 (_MX6Q_PAD_DISP0_DAT17__GPIO_5_11)
+#define MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 (_MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22)
+#define MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 (_MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27)
+
+#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 (_MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18)
+#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 (_MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18)
+#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 (_MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0)
+#define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS)
+#define MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS (_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS)
+#define MX6Q_PAD_DISP0_DAT18__GPIO_5_12 (_MX6Q_PAD_DISP0_DAT18__GPIO_5_12)
+#define MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 (_MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23)
+#define MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 (_MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2)
+
+#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 (_MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19)
+#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 (_MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19)
+#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK (_MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK)
+#define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD)
+#define MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC (_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC)
+#define MX6Q_PAD_DISP0_DAT19__GPIO_5_13 (_MX6Q_PAD_DISP0_DAT19__GPIO_5_13)
+#define MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 (_MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24)
+#define MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 (_MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3)
+
+#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 (_MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20)
+#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 (_MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20)
+#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK (_MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK)
+#define MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC (_MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC)
+#define MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 (_MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7)
+#define MX6Q_PAD_DISP0_DAT20__GPIO_5_14 (_MX6Q_PAD_DISP0_DAT20__GPIO_5_14)
+#define MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 (_MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25)
+#define MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 (_MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28)
+
+#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 (_MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21)
+#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 (_MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21)
+#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI (_MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI)
+#define MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD (_MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD)
+#define MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 (_MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0)
+#define MX6Q_PAD_DISP0_DAT21__GPIO_5_15 (_MX6Q_PAD_DISP0_DAT21__GPIO_5_15)
+#define MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 (_MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26)
+#define MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 (_MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29)
+
+#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 (_MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22)
+#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 (_MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22)
+#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO (_MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO)
+#define MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS (_MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS)
+#define MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 (_MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1)
+#define MX6Q_PAD_DISP0_DAT22__GPIO_5_16 (_MX6Q_PAD_DISP0_DAT22__GPIO_5_16)
+#define MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 (_MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27)
+#define MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 (_MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30)
+
+#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 (_MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23)
+#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 (_MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23)
+#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 (_MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0)
+#define MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD (_MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD)
+#define MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 (_MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2)
+#define MX6Q_PAD_DISP0_DAT23__GPIO_5_17 (_MX6Q_PAD_DISP0_DAT23__GPIO_5_17)
+#define MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 (_MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28)
+#define MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 (_MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31)
+
+#define MX6Q_PAD_ENET_MDIO__ENET_MDIO (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDIO__ESAI1_SCKR (_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR)
+#define MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 (_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3)
+#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT (_MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT)
+#define MX6Q_PAD_ENET_MDIO__GPIO_1_22 (_MX6Q_PAD_ENET_MDIO__GPIO_1_22)
+#define MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK (_MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK)
+
+#define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK (_MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR (_MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR)
+#define MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 (_MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4)
+#define MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 (_MX6Q_PAD_ENET_REF_CLK__GPIO_1_23)
+#define MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK (_MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK)
+#define MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH (_MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH)
+
+#define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER (_MX6Q_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR (_MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR)
+#define MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 (_MX6Q_PAD_ENET_RX_ER__SPDIF_IN1)
+#define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT (_MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT)
+#define MX6Q_PAD_ENET_RX_ER__GPIO_1_24 (_MX6Q_PAD_ENET_RX_ER__GPIO_1_24)
+#define MX6Q_PAD_ENET_RX_ER__PHY_TDI (_MX6Q_PAD_ENET_RX_ER__PHY_TDI)
+#define MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD (_MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD)
+
+#define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN (_MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT (_MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT)
+#define MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK (_MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK)
+#define MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 (_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25)
+#define MX6Q_PAD_ENET_CRS_DV__PHY_TDO (_MX6Q_PAD_ENET_CRS_DV__PHY_TDO)
+#define MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD (_MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD)
+
+#define MX6Q_PAD_ENET_RXD1__MLB_MLBSIG (_MX6Q_PAD_ENET_RXD1__MLB_MLBSIG)
+#define MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 (_MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD1__ESAI1_FST (_MX6Q_PAD_ENET_RXD1__ESAI1_FST)
+#define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT (_MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT)
+#define MX6Q_PAD_ENET_RXD1__GPIO_1_26 (_MX6Q_PAD_ENET_RXD1__GPIO_1_26)
+#define MX6Q_PAD_ENET_RXD1__PHY_TCK (_MX6Q_PAD_ENET_RXD1__PHY_TCK)
+#define MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET (_MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET)
+
+#define MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT (_MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT)
+#define MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 (_MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_ENET_RXD0__ESAI1_HCKT (_MX6Q_PAD_ENET_RXD0__ESAI1_HCKT)
+#define MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 (_MX6Q_PAD_ENET_RXD0__SPDIF_OUT1)
+#define MX6Q_PAD_ENET_RXD0__GPIO_1_27 (_MX6Q_PAD_ENET_RXD0__GPIO_1_27)
+#define MX6Q_PAD_ENET_RXD0__PHY_TMS (_MX6Q_PAD_ENET_RXD0__PHY_TMS)
+#define MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV (_MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV)
+
+#define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN (_MX6Q_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 (_MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2)
+#define MX6Q_PAD_ENET_TX_EN__GPIO_1_28 (_MX6Q_PAD_ENET_TX_EN__GPIO_1_28)
+#define MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI (_MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI)
+#define MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH (_MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH)
+
+#define MX6Q_PAD_ENET_TXD1__MLB_MLBCLK (_MX6Q_PAD_ENET_TXD1__MLB_MLBCLK)
+#define MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 (_MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 (_MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3)
+#define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN (_MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN)
+#define MX6Q_PAD_ENET_TXD1__GPIO_1_29 (_MX6Q_PAD_ENET_TXD1__GPIO_1_29)
+#define MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO (_MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO)
+#define MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD (_MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD)
+
+#define MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 (_MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 (_MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1)
+#define MX6Q_PAD_ENET_TXD0__GPIO_1_30 (_MX6Q_PAD_ENET_TXD0__GPIO_1_30)
+#define MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK (_MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK)
+#define MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD (_MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD)
+
+#define MX6Q_PAD_ENET_MDC__MLB_MLBDAT (_MX6Q_PAD_ENET_MDC__MLB_MLBDAT)
+#define MX6Q_PAD_ENET_MDC__ENET_MDC (_MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 (_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0)
+#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN (_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN)
+#define MX6Q_PAD_ENET_MDC__GPIO_1_31 (_MX6Q_PAD_ENET_MDC__GPIO_1_31)
+#define MX6Q_PAD_ENET_MDC__SATA_PHY_TMS (_MX6Q_PAD_ENET_MDC__SATA_PHY_TMS)
+#define MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET (_MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET)
+
+#define MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 (_MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40)
+#define MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 (_MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41)
+#define MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 (_MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42)
+#define MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 (_MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43)
+#define MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 (_MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44)
+#define MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 (_MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45)
+#define MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 (_MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46)
+#define MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 (_MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47)
+
+#define MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 (_MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5)
+#define MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 (_MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5)
+
+#define MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 (_MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32)
+#define MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 (_MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33)
+#define MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 (_MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34)
+#define MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 (_MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35)
+#define MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 (_MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36)
+#define MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 (_MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37)
+#define MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 (_MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38)
+#define MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 (_MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39)
+#define MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 (_MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4)
+#define MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 (_MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4)
+#define MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 (_MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24)
+#define MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 (_MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25)
+#define MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 (_MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26)
+#define MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 (_MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27)
+#define MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 (_MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28)
+#define MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 (_MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29)
+#define MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 (_MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3)
+#define MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 (_MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30)
+#define MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 (_MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31)
+#define MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 (_MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3)
+#define MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 (_MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16)
+#define MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 (_MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17)
+#define MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 (_MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18)
+#define MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 (_MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19)
+#define MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 (_MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20)
+#define MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 (_MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21)
+#define MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 (_MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22)
+#define MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 (_MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2)
+#define MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 (_MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23)
+#define MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 (_MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2)
+#define MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 (_MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0)
+#define MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 (_MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1)
+#define MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 (_MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2)
+#define MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 (_MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3)
+#define MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 (_MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4)
+#define MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 (_MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5)
+#define MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 (_MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6)
+#define MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 (_MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7)
+#define MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 (_MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8)
+#define MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 (_MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9)
+#define MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 (_MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10)
+#define MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 (_MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11)
+#define MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 (_MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12)
+#define MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 (_MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13)
+#define MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 (_MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14)
+#define MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 (_MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15)
+#define MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS (_MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS)
+#define MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 (_MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0)
+#define MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 (_MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1)
+#define MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS (_MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS)
+#define MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET (_MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET)
+#define MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 (_MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0)
+#define MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 (_MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1)
+#define MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 (_MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0)
+#define MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 (_MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2)
+#define MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 (_MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0)
+#define MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 (_MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1)
+#define MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 (_MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1)
+#define MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 (_MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0)
+#define MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 (_MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1)
+#define MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE (_MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE)
+#define MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 (_MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0)
+#define MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 (_MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1)
+#define MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 (_MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2)
+#define MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 (_MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3)
+#define MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 (_MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4)
+#define MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 (_MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5)
+#define MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 (_MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0)
+#define MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 (_MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6)
+#define MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 (_MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7)
+#define MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 (_MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0)
+#define MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 (_MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8)
+#define MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 (_MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9)
+#define MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 (_MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10)
+#define MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 (_MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11)
+#define MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 (_MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12)
+#define MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 (_MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13)
+#define MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 (_MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14)
+#define MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 (_MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1)
+#define MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 (_MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15)
+#define MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 (_MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1)
+#define MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 (_MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48)
+#define MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 (_MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49)
+#define MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 (_MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50)
+#define MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 (_MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51)
+#define MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 (_MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52)
+#define MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 (_MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53)
+#define MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 (_MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54)
+#define MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 (_MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55)
+#define MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 (_MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6)
+#define MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 (_MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6)
+#define MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 (_MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56)
+#define MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 (_MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7)
+#define MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 (_MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57)
+#define MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 (_MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58)
+#define MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 (_MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59)
+#define MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 (_MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60)
+#define MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 (_MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7)
+#define MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 (_MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61)
+#define MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 (_MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62)
+#define MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 (_MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63)
+
+#define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK (_MX6Q_PAD_KEY_COL0__ECSPI1_SCLK)
+#define MX6Q_PAD_KEY_COL0__ENET_RDATA_3 (_MX6Q_PAD_KEY_COL0__ENET_RDATA_3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC (_MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC)
+#define MX6Q_PAD_KEY_COL0__KPP_COL_0 (_MX6Q_PAD_KEY_COL0__KPP_COL_0)
+#define MX6Q_PAD_KEY_COL0__UART4_TXD (_MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__UART4_RXD (_MX6Q_PAD_KEY_COL0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL0__GPIO_4_6 (_MX6Q_PAD_KEY_COL0__GPIO_4_6)
+#define MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT (_MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT)
+#define MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST (_MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST)
+
+#define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI (_MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI)
+#define MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 (_MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD (_MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD)
+#define MX6Q_PAD_KEY_ROW0__KPP_ROW_0 (_MX6Q_PAD_KEY_ROW0__KPP_ROW_0)
+#define MX6Q_PAD_KEY_ROW0__UART4_TXD (_MX6Q_PAD_KEY_ROW0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__UART4_RXD (_MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW0__GPIO_4_7 (_MX6Q_PAD_KEY_ROW0__GPIO_4_7)
+#define MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT (_MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT)
+#define MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 (_MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0)
+
+#define MX6Q_PAD_KEY_COL1__ECSPI1_MISO (_MX6Q_PAD_KEY_COL1__ECSPI1_MISO)
+#define MX6Q_PAD_KEY_COL1__ENET_MDIO (_MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS (_MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS)
+#define MX6Q_PAD_KEY_COL1__KPP_COL_1 (_MX6Q_PAD_KEY_COL1__KPP_COL_1)
+#define MX6Q_PAD_KEY_COL1__UART5_TXD (_MX6Q_PAD_KEY_COL1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__UART5_RXD (_MX6Q_PAD_KEY_COL1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__GPIO_4_8 (_MX6Q_PAD_KEY_COL1__GPIO_4_8)
+#define MX6Q_PAD_KEY_COL1__USDHC1_VSELECT (_MX6Q_PAD_KEY_COL1__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 (_MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1)
+
+#define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 (_MX6Q_PAD_KEY_ROW1__ECSPI1_SS0)
+#define MX6Q_PAD_KEY_ROW1__ENET_COL (_MX6Q_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD (_MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD)
+#define MX6Q_PAD_KEY_ROW1__KPP_ROW_1 (_MX6Q_PAD_KEY_ROW1__KPP_ROW_1)
+#define MX6Q_PAD_KEY_ROW1__UART5_TXD (_MX6Q_PAD_KEY_ROW1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__UART5_RXD (_MX6Q_PAD_KEY_ROW1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__GPIO_4_9 (_MX6Q_PAD_KEY_ROW1__GPIO_4_9)
+#define MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT (_MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 (_MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2)
+
+#define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 (_MX6Q_PAD_KEY_COL2__ECSPI1_SS1)
+#define MX6Q_PAD_KEY_COL2__ENET_RDATA_2 (_MX6Q_PAD_KEY_COL2__ENET_RDATA_2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL2__CAN1_TXCAN (_MX6Q_PAD_KEY_COL2__CAN1_TXCAN)
+#define MX6Q_PAD_KEY_COL2__KPP_COL_2 (_MX6Q_PAD_KEY_COL2__KPP_COL_2)
+#define MX6Q_PAD_KEY_COL2__ENET_MDC (_MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL2__GPIO_4_10 (_MX6Q_PAD_KEY_COL2__GPIO_4_10)
+#define MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP (_MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP)
+#define MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 (_MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3)
+
+#define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 (_MX6Q_PAD_KEY_ROW2__ECSPI1_SS2)
+#define MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 (_MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW2__CAN1_RXCAN (_MX6Q_PAD_KEY_ROW2__CAN1_RXCAN)
+#define MX6Q_PAD_KEY_ROW2__KPP_ROW_2 (_MX6Q_PAD_KEY_ROW2__KPP_ROW_2)
+#define MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT (_MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW2__GPIO_4_11 (_MX6Q_PAD_KEY_ROW2__GPIO_4_11)
+#define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE (_MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE)
+#define MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 (_MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4)
+
+#define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 (_MX6Q_PAD_KEY_COL3__ECSPI1_SS3)
+#define MX6Q_PAD_KEY_COL3__ENET_CRS (_MX6Q_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL (_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL)
+#define MX6Q_PAD_KEY_COL3__KPP_COL_3 (_MX6Q_PAD_KEY_COL3__KPP_COL_3)
+#define MX6Q_PAD_KEY_COL3__I2C2_SCL (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL3__GPIO_4_12 (_MX6Q_PAD_KEY_COL3__GPIO_4_12)
+#define MX6Q_PAD_KEY_COL3__SPDIF_IN1 (_MX6Q_PAD_KEY_COL3__SPDIF_IN1)
+#define MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 (_MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5)
+
+#define MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT (_MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT)
+#define MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK (_MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK)
+#define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA (_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA)
+#define MX6Q_PAD_KEY_ROW3__KPP_ROW_3 (_MX6Q_PAD_KEY_ROW3__KPP_ROW_3)
+#define MX6Q_PAD_KEY_ROW3__I2C2_SDA (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW3__GPIO_4_13 (_MX6Q_PAD_KEY_ROW3__GPIO_4_13)
+#define MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT (_MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 (_MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6)
+
+#define MX6Q_PAD_KEY_COL4__CAN2_TXCAN (_MX6Q_PAD_KEY_COL4__CAN2_TXCAN)
+#define MX6Q_PAD_KEY_COL4__IPU1_SISG_4 (_MX6Q_PAD_KEY_COL4__IPU1_SISG_4)
+#define MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC (_MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC)
+#define MX6Q_PAD_KEY_COL4__KPP_COL_4 (_MX6Q_PAD_KEY_COL4__KPP_COL_4)
+#define MX6Q_PAD_KEY_COL4__UART5_CTS (_MX6Q_PAD_KEY_COL4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__UART5_RTS (_MX6Q_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_COL4__GPIO_4_14 (_MX6Q_PAD_KEY_COL4__GPIO_4_14)
+#define MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 (_MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49)
+#define MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 (_MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7)
+
+#define MX6Q_PAD_KEY_ROW4__CAN2_RXCAN (_MX6Q_PAD_KEY_ROW4__CAN2_RXCAN)
+#define MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 (_MX6Q_PAD_KEY_ROW4__IPU1_SISG_5)
+#define MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR (_MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR)
+#define MX6Q_PAD_KEY_ROW4__KPP_ROW_4 (_MX6Q_PAD_KEY_ROW4__KPP_ROW_4)
+#define MX6Q_PAD_KEY_ROW4__UART5_CTS (_MX6Q_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_KEY_ROW4__GPIO_4_15 (_MX6Q_PAD_KEY_ROW4__GPIO_4_15)
+#define MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 (_MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50)
+#define MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 (_MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8)
+
+#define MX6Q_PAD_GPIO_0__CCM_CLKO (_MX6Q_PAD_GPIO_0__CCM_CLKO)
+#define MX6Q_PAD_GPIO_0__KPP_COL_5 (_MX6Q_PAD_GPIO_0__KPP_COL_5)
+#define MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK (_MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK)
+#define MX6Q_PAD_GPIO_0__EPIT1_EPITO (_MX6Q_PAD_GPIO_0__EPIT1_EPITO)
+#define MX6Q_PAD_GPIO_0__GPIO_1_0 (_MX6Q_PAD_GPIO_0__GPIO_1_0)
+#define MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR (_MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR)
+#define MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 (_MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5)
+
+#define MX6Q_PAD_GPIO_1__ESAI1_SCKR (_MX6Q_PAD_GPIO_1__ESAI1_SCKR)
+#define MX6Q_PAD_GPIO_1__WDOG2_WDOG_B (_MX6Q_PAD_GPIO_1__WDOG2_WDOG_B)
+#define MX6Q_PAD_GPIO_1__KPP_ROW_5 (_MX6Q_PAD_GPIO_1__KPP_ROW_5)
+#define MX6Q_PAD_GPIO_1__PWM2_PWMO (_MX6Q_PAD_GPIO_1__PWM2_PWMO)
+#define MX6Q_PAD_GPIO_1__GPIO_1_1 (_MX6Q_PAD_GPIO_1__GPIO_1_1)
+#define MX6Q_PAD_GPIO_1__USDHC1_CD (_MX6Q_PAD_GPIO_1__USDHC1_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_1__SRC_TESTER_ACK (_MX6Q_PAD_GPIO_1__SRC_TESTER_ACK)
+
+#define MX6Q_PAD_GPIO_9__ESAI1_FSR (_MX6Q_PAD_GPIO_9__ESAI1_FSR)
+#define MX6Q_PAD_GPIO_9__WDOG1_WDOG_B (_MX6Q_PAD_GPIO_9__WDOG1_WDOG_B)
+#define MX6Q_PAD_GPIO_9__KPP_COL_6 (_MX6Q_PAD_GPIO_9__KPP_COL_6)
+#define MX6Q_PAD_GPIO_9__CCM_REF_EN_B (_MX6Q_PAD_GPIO_9__CCM_REF_EN_B)
+#define MX6Q_PAD_GPIO_9__PWM1_PWMO (_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(MX6Q_PWM_PAD_CTRL))
+#define MX6Q_PAD_GPIO_9__GPIO_1_9 (_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
+#define MX6Q_PAD_GPIO_9__USDHC1_WP (_MX6Q_PAD_GPIO_9__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_9__SRC_EARLY_RST (_MX6Q_PAD_GPIO_9__SRC_EARLY_RST)
+
+#define MX6Q_PAD_GPIO_3__ESAI1_HCKR (_MX6Q_PAD_GPIO_3__ESAI1_HCKR)
+#define MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 (_MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0)
+#define MX6Q_PAD_GPIO_3__I2C3_SCL (_MX6Q_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT (_MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT)
+#define MX6Q_PAD_GPIO_3__CCM_CLKO2 (_MX6Q_PAD_GPIO_3__CCM_CLKO2)
+#define MX6Q_PAD_GPIO_3__GPIO_1_3 (_MX6Q_PAD_GPIO_3__GPIO_1_3)
+#define MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC (_MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC)
+#define MX6Q_PAD_GPIO_3__MLB_MLBCLK (_MX6Q_PAD_GPIO_3__MLB_MLBCLK)
+
+#define MX6Q_PAD_GPIO_6__ESAI1_SCKT (_MX6Q_PAD_GPIO_6__ESAI1_SCKT)
+#define MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 (_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1)
+#define MX6Q_PAD_GPIO_6__I2C3_SDA (_MX6Q_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 (_MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0)
+#define MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB (_MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB)
+#define MX6Q_PAD_GPIO_6__GPIO_1_6 (_MX6Q_PAD_GPIO_6__GPIO_1_6)
+#define MX6Q_PAD_GPIO_6__USDHC2_LCTL (_MX6Q_PAD_GPIO_6__USDHC2_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_6__MLB_MLBSIG (_MX6Q_PAD_GPIO_6__MLB_MLBSIG)
+
+#define MX6Q_PAD_GPIO_2__ESAI1_FST (_MX6Q_PAD_GPIO_2__ESAI1_FST)
+#define MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 (_MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2)
+#define MX6Q_PAD_GPIO_2__KPP_ROW_6 (_MX6Q_PAD_GPIO_2__KPP_ROW_6)
+#define MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 (_MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1)
+#define MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 (_MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0)
+#define MX6Q_PAD_GPIO_2__GPIO_1_2 (_MX6Q_PAD_GPIO_2__GPIO_1_2)
+#define MX6Q_PAD_GPIO_2__USDHC2_WP (_MX6Q_PAD_GPIO_2__USDHC2_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_2__MLB_MLBDAT (_MX6Q_PAD_GPIO_2__MLB_MLBDAT)
+
+#define MX6Q_PAD_GPIO_4__ESAI1_HCKT (_MX6Q_PAD_GPIO_4__ESAI1_HCKT)
+#define MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 (_MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3)
+#define MX6Q_PAD_GPIO_4__KPP_COL_7 (_MX6Q_PAD_GPIO_4__KPP_COL_7)
+#define MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 (_MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2)
+#define MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 (_MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1)
+#define MX6Q_PAD_GPIO_4__GPIO_1_4 (_MX6Q_PAD_GPIO_4__GPIO_1_4)
+#define MX6Q_PAD_GPIO_4__USDHC2_CD (_MX6Q_PAD_GPIO_4__USDHC2_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED (_MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED)
+
+#define MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 (_MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3)
+#define MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 (_MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4)
+#define MX6Q_PAD_GPIO_5__KPP_ROW_7 (_MX6Q_PAD_GPIO_5__KPP_ROW_7)
+#define MX6Q_PAD_GPIO_5__CCM_CLKO (_MX6Q_PAD_GPIO_5__CCM_CLKO)
+#define MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 (_MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2)
+#define MX6Q_PAD_GPIO_5__GPIO_1_5 (_MX6Q_PAD_GPIO_5__GPIO_1_5)
+#define MX6Q_PAD_GPIO_5__I2C3_SCL (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_GPIO_5__CHEETAH_EVENTI (_MX6Q_PAD_GPIO_5__CHEETAH_EVENTI)
+
+#define MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 (_MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1)
+#define MX6Q_PAD_GPIO_7__ECSPI5_RDY (_MX6Q_PAD_GPIO_7__ECSPI5_RDY)
+#define MX6Q_PAD_GPIO_7__EPIT1_EPITO (_MX6Q_PAD_GPIO_7__EPIT1_EPITO)
+#define MX6Q_PAD_GPIO_7__CAN1_TXCAN (_MX6Q_PAD_GPIO_7__CAN1_TXCAN)
+#define MX6Q_PAD_GPIO_7__UART2_TXD (_MX6Q_PAD_GPIO_7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__UART2_RXD (_MX6Q_PAD_GPIO_7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_GPIO_7__GPIO_1_7 (_MX6Q_PAD_GPIO_7__GPIO_1_7)
+#define MX6Q_PAD_GPIO_7__SPDIF_PLOCK (_MX6Q_PAD_GPIO_7__SPDIF_PLOCK)
+#define MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE (_MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE)
+
+#define MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 (_MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0)
+#define MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT (_MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT)
+#define MX6Q_PAD_GPIO_8__EPIT2_EPITO (_MX6Q_PAD_GPIO_8__EPIT2_EPITO)
+#define MX6Q_PAD_GPIO_8__CAN1_RXCAN (_MX6Q_PAD_GPIO_8__CAN1_RXCAN)
+#define MX6Q_PAD_GPIO_8__UART2_TXD (_MX6Q_PAD_GPIO_8__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__UART2_RXD (_MX6Q_PAD_GPIO_8__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_GPIO_8__GPIO_1_8 (_MX6Q_PAD_GPIO_8__GPIO_1_8)
+#define MX6Q_PAD_GPIO_8__SPDIF_SRCLK (_MX6Q_PAD_GPIO_8__SPDIF_SRCLK)
+#define MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP (_MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP)
+
+#define MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 (_MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2)
+#define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN (_MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN)
+#define MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT (_MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT)
+#define MX6Q_PAD_GPIO_16__USDHC1_LCTL (_MX6Q_PAD_GPIO_16__USDHC1_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_16__SPDIF_IN1 (_MX6Q_PAD_GPIO_16__SPDIF_IN1)
+#define MX6Q_PAD_GPIO_16__GPIO_7_11 (_MX6Q_PAD_GPIO_16__GPIO_7_11)
+#define MX6Q_PAD_GPIO_16__I2C3_SDA (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_GPIO_16__SJC_DE_B (_MX6Q_PAD_GPIO_16__SJC_DE_B)
+
+#define MX6Q_PAD_GPIO_17__ESAI1_TX0 (_MX6Q_PAD_GPIO_17__ESAI1_TX0)
+#define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN (_MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN)
+#define MX6Q_PAD_GPIO_17__CCM_PMIC_RDY (_MX6Q_PAD_GPIO_17__CCM_PMIC_RDY)
+#define MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 (_MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0)
+#define MX6Q_PAD_GPIO_17__SPDIF_OUT1 (_MX6Q_PAD_GPIO_17__SPDIF_OUT1)
+#define MX6Q_PAD_GPIO_17__GPIO_7_12 (_MX6Q_PAD_GPIO_17__GPIO_7_12)
+#define MX6Q_PAD_GPIO_17__SJC_JTAG_ACT (_MX6Q_PAD_GPIO_17__SJC_JTAG_ACT)
+
+#define MX6Q_PAD_GPIO_18__ESAI1_TX1 (_MX6Q_PAD_GPIO_18__ESAI1_TX1)
+#define MX6Q_PAD_GPIO_18__ENET_RX_CLK (_MX6Q_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_GPIO_18__USDHC3_VSELECT (_MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 (_MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1)
+#define MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK (_MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK)
+#define MX6Q_PAD_GPIO_18__GPIO_7_13 (_MX6Q_PAD_GPIO_18__GPIO_7_13)
+#define MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL (_MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL)
+#define MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST (_MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST)
+
+#define MX6Q_PAD_GPIO_19__KPP_COL_5 (_MX6Q_PAD_GPIO_19__KPP_COL_5)
+#define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT (_MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT)
+#define MX6Q_PAD_GPIO_19__SPDIF_OUT1 (_MX6Q_PAD_GPIO_19__SPDIF_OUT1)
+#define MX6Q_PAD_GPIO_19__CCM_CLKO (_MX6Q_PAD_GPIO_19__CCM_CLKO)
+#define MX6Q_PAD_GPIO_19__ECSPI1_RDY (_MX6Q_PAD_GPIO_19__ECSPI1_RDY)
+#define MX6Q_PAD_GPIO_19__GPIO_4_5 (_MX6Q_PAD_GPIO_19__GPIO_4_5)
+#define MX6Q_PAD_GPIO_19__ENET_TX_ER (_MX6Q_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
+#define MX6Q_PAD_GPIO_19__SRC_INT_BOOT (_MX6Q_PAD_GPIO_19__SRC_INT_BOOT)
+
+#define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK (_MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK)
+#define MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 (_MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12)
+#define MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 (_MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0)
+#define MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 (_MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18)
+#define MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 (_MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29)
+#define MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO (_MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO)
+
+#define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC (_MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC)
+#define MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 (_MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13)
+#define MX6Q_PAD_CSI0_MCLK__CCM_CLKO (_MX6Q_PAD_CSI0_MCLK__CCM_CLKO)
+#define MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 (_MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1)
+#define MX6Q_PAD_CSI0_MCLK__GPIO_5_19 (_MX6Q_PAD_CSI0_MCLK__GPIO_5_19)
+#define MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 (_MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30)
+#define MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL (_MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL)
+
+#define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN (_MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN)
+#define MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 (_MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0)
+#define MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 (_MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14)
+#define MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 (_MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2)
+#define MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 (_MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20)
+#define MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 (_MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31)
+#define MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK (_MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK)
+
+#define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC (_MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC)
+#define MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 (_MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1)
+#define MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 (_MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15)
+#define MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 (_MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3)
+#define MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 (_MX6Q_PAD_CSI0_VSYNC__GPIO_5_21)
+#define MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 (_MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32)
+#define MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 (_MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0)
+
+#define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 (_MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4)
+#define MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 (_MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2)
+#define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK (_MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK)
+#define MX6Q_PAD_CSI0_DAT4__KPP_COL_5 (_MX6Q_PAD_CSI0_DAT4__KPP_COL_5)
+#define MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC (_MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC)
+#define MX6Q_PAD_CSI0_DAT4__GPIO_5_22 (_MX6Q_PAD_CSI0_DAT4__GPIO_5_22)
+#define MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 (_MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43)
+#define MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 (_MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1)
+
+#define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 (_MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5)
+#define MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 (_MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3)
+#define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI (_MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI)
+#define MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 (_MX6Q_PAD_CSI0_DAT5__KPP_ROW_5)
+#define MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD (_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD)
+#define MX6Q_PAD_CSI0_DAT5__GPIO_5_23 (_MX6Q_PAD_CSI0_DAT5__GPIO_5_23)
+#define MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 (_MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44)
+#define MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 (_MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2)
+
+#define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 (_MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6)
+#define MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 (_MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4)
+#define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO (_MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO)
+#define MX6Q_PAD_CSI0_DAT6__KPP_COL_6 (_MX6Q_PAD_CSI0_DAT6__KPP_COL_6)
+#define MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS (_MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS)
+#define MX6Q_PAD_CSI0_DAT6__GPIO_5_24 (_MX6Q_PAD_CSI0_DAT6__GPIO_5_24)
+#define MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 (_MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45)
+#define MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 (_MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3)
+
+#define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 (_MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7)
+#define MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 (_MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5)
+#define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 (_MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0)
+#define MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 (_MX6Q_PAD_CSI0_DAT7__KPP_ROW_6)
+#define MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD (_MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD)
+#define MX6Q_PAD_CSI0_DAT7__GPIO_5_25 (_MX6Q_PAD_CSI0_DAT7__GPIO_5_25)
+#define MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 (_MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46)
+#define MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 (_MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4)
+
+#define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 (_MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8)
+#define MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 (_MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6)
+#define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK (_MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK)
+#define MX6Q_PAD_CSI0_DAT8__KPP_COL_7 (_MX6Q_PAD_CSI0_DAT8__KPP_COL_7)
+#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA (_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT8__GPIO_5_26 (_MX6Q_PAD_CSI0_DAT8__GPIO_5_26)
+#define MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 (_MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47)
+#define MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 (_MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5)
+
+#define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 (_MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9)
+#define MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 (_MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7)
+#define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI (_MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI)
+#define MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 (_MX6Q_PAD_CSI0_DAT9__KPP_ROW_7)
+#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL (_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT9__GPIO_5_27 (_MX6Q_PAD_CSI0_DAT9__GPIO_5_27)
+#define MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 (_MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48)
+#define MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 (_MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6)
+
+#define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 (_MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10)
+#define MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC (_MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC)
+#define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO (_MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO)
+#define MX6Q_PAD_CSI0_DAT10__UART1_TXD (_MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__UART1_RXD (_MX6Q_PAD_CSI0_DAT10__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 (_MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4)
+#define MX6Q_PAD_CSI0_DAT10__GPIO_5_28 (_MX6Q_PAD_CSI0_DAT10__GPIO_5_28)
+#define MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 (_MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33)
+#define MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 (_MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7)
+
+#define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 (_MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11)
+#define MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS (_MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS)
+#define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 (_MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0)
+#define MX6Q_PAD_CSI0_DAT11__UART1_TXD (_MX6Q_PAD_CSI0_DAT11__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__UART1_RXD (_MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 (_MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5)
+#define MX6Q_PAD_CSI0_DAT11__GPIO_5_29 (_MX6Q_PAD_CSI0_DAT11__GPIO_5_29)
+#define MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 (_MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34)
+#define MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 (_MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8)
+
+#define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 (_MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12)
+#define MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 (_MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8)
+#define MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 (_MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16)
+#define MX6Q_PAD_CSI0_DAT12__UART4_TXD (_MX6Q_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__UART4_RXD (_MX6Q_PAD_CSI0_DAT12__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 (_MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6)
+#define MX6Q_PAD_CSI0_DAT12__GPIO_5_30 (_MX6Q_PAD_CSI0_DAT12__GPIO_5_30)
+#define MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 (_MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35)
+#define MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 (_MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9)
+
+#define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 (_MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13)
+#define MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 (_MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9)
+#define MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 (_MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17)
+#define MX6Q_PAD_CSI0_DAT13__UART4_TXD (_MX6Q_PAD_CSI0_DAT13__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__UART4_RXD (_MX6Q_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 (_MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7)
+#define MX6Q_PAD_CSI0_DAT13__GPIO_5_31 (_MX6Q_PAD_CSI0_DAT13__GPIO_5_31)
+#define MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 (_MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36)
+#define MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 (_MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10)
+
+#define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 (_MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14)
+#define MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 (_MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10)
+#define MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 (_MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18)
+#define MX6Q_PAD_CSI0_DAT14__UART5_TXD (_MX6Q_PAD_CSI0_DAT14__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__UART5_RXD (_MX6Q_PAD_CSI0_DAT14__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 (_MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8)
+#define MX6Q_PAD_CSI0_DAT14__GPIO_6_0 (_MX6Q_PAD_CSI0_DAT14__GPIO_6_0)
+#define MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 (_MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37)
+#define MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 (_MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11)
+
+#define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 (_MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15)
+#define MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 (_MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11)
+#define MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 (_MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19)
+#define MX6Q_PAD_CSI0_DAT15__UART5_TXD (_MX6Q_PAD_CSI0_DAT15__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__UART5_RXD (_MX6Q_PAD_CSI0_DAT15__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 (_MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9)
+#define MX6Q_PAD_CSI0_DAT15__GPIO_6_1 (_MX6Q_PAD_CSI0_DAT15__GPIO_6_1)
+#define MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 (_MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38)
+#define MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 (_MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12)
+
+#define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 (_MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16)
+#define MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 (_MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12)
+#define MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 (_MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20)
+#define MX6Q_PAD_CSI0_DAT16__UART4_CTS (_MX6Q_PAD_CSI0_DAT16__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__UART4_RTS (_MX6Q_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 (_MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10)
+#define MX6Q_PAD_CSI0_DAT16__GPIO_6_2 (_MX6Q_PAD_CSI0_DAT16__GPIO_6_2)
+#define MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 (_MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39)
+#define MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 (_MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13)
+
+#define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 (_MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17)
+#define MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 (_MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13)
+#define MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 (_MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21)
+#define MX6Q_PAD_CSI0_DAT17__UART4_CTS (_MX6Q_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 (_MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11)
+#define MX6Q_PAD_CSI0_DAT17__GPIO_6_3 (_MX6Q_PAD_CSI0_DAT17__GPIO_6_3)
+#define MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 (_MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40)
+#define MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 (_MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14)
+
+#define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 (_MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18)
+#define MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 (_MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14)
+#define MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 (_MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22)
+#define MX6Q_PAD_CSI0_DAT18__UART5_CTS (_MX6Q_PAD_CSI0_DAT18__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__UART5_RTS (_MX6Q_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 (_MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12)
+#define MX6Q_PAD_CSI0_DAT18__GPIO_6_4 (_MX6Q_PAD_CSI0_DAT18__GPIO_6_4)
+#define MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 (_MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41)
+#define MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 (_MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15)
+
+#define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 (_MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19)
+#define MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 (_MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15)
+#define MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 (_MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23)
+#define MX6Q_PAD_CSI0_DAT19__UART5_CTS (_MX6Q_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 (_MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13)
+#define MX6Q_PAD_CSI0_DAT19__GPIO_6_5 (_MX6Q_PAD_CSI0_DAT19__GPIO_6_5)
+#define MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 (_MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42)
+#define MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 (_MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9)
+
+#define MX6Q_PAD_JTAG_TMS__SJC_TMS (_MX6Q_PAD_JTAG_TMS__SJC_TMS)
+
+#define MX6Q_PAD_JTAG_MOD__SJC_MOD (_MX6Q_PAD_JTAG_MOD__SJC_MOD)
+
+#define MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB (_MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB)
+
+#define MX6Q_PAD_JTAG_TDI__SJC_TDI (_MX6Q_PAD_JTAG_TDI__SJC_TDI)
+
+#define MX6Q_PAD_JTAG_TCK__SJC_TCK (_MX6Q_PAD_JTAG_TCK__SJC_TCK)
+
+#define MX6Q_PAD_JTAG_TDO__SJC_TDO (_MX6Q_PAD_JTAG_TDO__SJC_TDO)
+
+#define MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 (_MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3)
+
+#define MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 (_MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2)
+
+#define MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK (_MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK)
+
+#define MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 (_MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1)
+
+#define MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 (_MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0)
+
+#define MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 (_MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3)
+
+#define MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK (_MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK)
+
+#define MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 (_MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2)
+
+#define MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 (_MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1)
+
+#define MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 (_MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0)
+
+#define MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 (_MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1)
+
+#define MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM (_MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM)
+
+#define MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ (_MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ)
+
+#define MX6Q_PAD_POR_B__SRC_POR_B (_MX6Q_PAD_POR_B__SRC_POR_B)
+
+#define MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 (_MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1)
+
+#define MX6Q_PAD_RESET_IN_B__SRC_RESET_B (_MX6Q_PAD_RESET_IN_B__SRC_RESET_B)
+
+#define MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 (_MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0)
+
+#define MX6Q_PAD_TEST_MODE__TCU_TEST_MODE (_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE)
+
+#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 (_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__UART1_TXD (_MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__UART1_RXD (_MX6Q_PAD_SD3_DAT7__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 (_MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24)
+#define MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0)
+#define MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 (_MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0)
+#define MX6Q_PAD_SD3_DAT7__GPIO_6_17 (_MX6Q_PAD_SD3_DAT7__GPIO_6_17)
+#define MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 (_MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12)
+#define MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV (_MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV)
+
+#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 (_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__UART1_TXD (_MX6Q_PAD_SD3_DAT6__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__UART1_RXD (_MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 (_MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25)
+#define MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1)
+#define MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 (_MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1)
+#define MX6Q_PAD_SD3_DAT6__GPIO_6_18 (_MX6Q_PAD_SD3_DAT6__GPIO_6_18)
+#define MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 (_MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13)
+#define MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 (_MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10)
+
+#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 (_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__UART2_TXD (_MX6Q_PAD_SD3_DAT5__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__UART2_RXD (_MX6Q_PAD_SD3_DAT5__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 (_MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26)
+#define MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2)
+#define MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 (_MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2)
+#define MX6Q_PAD_SD3_DAT5__GPIO_7_0 (_MX6Q_PAD_SD3_DAT5__GPIO_7_0)
+#define MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 (_MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14)
+#define MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 (_MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11)
+
+#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 (_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__UART2_TXD (_MX6Q_PAD_SD3_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__UART2_RXD (_MX6Q_PAD_SD3_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 (_MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27)
+#define MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3)
+#define MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 (_MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3)
+#define MX6Q_PAD_SD3_DAT4__GPIO_7_1 (_MX6Q_PAD_SD3_DAT4__GPIO_7_1)
+#define MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 (_MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15)
+#define MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 (_MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12)
+
+#define MX6Q_PAD_SD3_CMD__USDHC3_CMD (_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_CMD__UART2_CTS (_MX6Q_PAD_SD3_CMD__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_CMD__CAN1_TXCAN (_MX6Q_PAD_SD3_CMD__CAN1_TXCAN)
+#define MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 (_MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4)
+#define MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 (_MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4)
+#define MX6Q_PAD_SD3_CMD__GPIO_7_2 (_MX6Q_PAD_SD3_CMD__GPIO_7_2)
+#define MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 (_MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16)
+#define MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 (_MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13)
+
+#define MX6Q_PAD_SD3_CLK__USDHC3_CLK (_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__UART2_CTS (_MX6Q_PAD_SD3_CLK__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__UART2_RTS (_MX6Q_PAD_SD3_CLK__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_CLK__CAN1_RXCAN (_MX6Q_PAD_SD3_CLK__CAN1_RXCAN)
+#define MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 (_MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5)
+#define MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 (_MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5)
+#define MX6Q_PAD_SD3_CLK__GPIO_7_3 (_MX6Q_PAD_SD3_CLK__GPIO_7_3)
+#define MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 (_MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17)
+#define MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 (_MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14)
+
+#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 (_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__UART1_CTS (_MX6Q_PAD_SD3_DAT0__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT0__CAN2_TXCAN (_MX6Q_PAD_SD3_DAT0__CAN2_TXCAN)
+#define MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6)
+#define MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 (_MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6)
+#define MX6Q_PAD_SD3_DAT0__GPIO_7_4 (_MX6Q_PAD_SD3_DAT0__GPIO_7_4)
+#define MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 (_MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18)
+#define MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 (_MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15)
+
+#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 (_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__UART1_CTS (_MX6Q_PAD_SD3_DAT1__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__UART1_RTS (_MX6Q_PAD_SD3_DAT1__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT1__CAN2_RXCAN (_MX6Q_PAD_SD3_DAT1__CAN2_RXCAN)
+#define MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7)
+#define MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 (_MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7)
+#define MX6Q_PAD_SD3_DAT1__GPIO_7_5 (_MX6Q_PAD_SD3_DAT1__GPIO_7_5)
+#define MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 (_MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19)
+#define MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 (_MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0)
+
+#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 (_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 (_MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28)
+#define MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8)
+#define MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 (_MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8)
+#define MX6Q_PAD_SD3_DAT2__GPIO_7_6 (_MX6Q_PAD_SD3_DAT2__GPIO_7_6)
+#define MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 (_MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20)
+#define MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 (_MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1)
+
+#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 (_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT3__UART3_CTS (_MX6Q_PAD_SD3_DAT3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 (_MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29)
+#define MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9)
+#define MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 (_MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9)
+#define MX6Q_PAD_SD3_DAT3__GPIO_7_7 (_MX6Q_PAD_SD3_DAT3__GPIO_7_7)
+#define MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 (_MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21)
+#define MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 (_MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2)
+
+#define MX6Q_PAD_SD3_RST__USDHC3_RST (_MX6Q_PAD_SD3_RST__USDHC3_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__UART3_CTS (_MX6Q_PAD_SD3_RST__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__UART3_RTS (_MX6Q_PAD_SD3_RST__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 (_MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30)
+#define MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 (_MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10)
+#define MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 (_MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10)
+#define MX6Q_PAD_SD3_RST__GPIO_7_8 (_MX6Q_PAD_SD3_RST__GPIO_7_8)
+#define MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 (_MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22)
+#define MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 (_MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3)
+
+#define MX6Q_PAD_NANDF_CLE__RAWNAND_CLE (_MX6Q_PAD_NANDF_CLE__RAWNAND_CLE)
+#define MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 (_MX6Q_PAD_NANDF_CLE__IPU2_SISG_4)
+#define MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 (_MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31)
+#define MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 (_MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11)
+#define MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 (_MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11)
+#define MX6Q_PAD_NANDF_CLE__GPIO_6_7 (_MX6Q_PAD_NANDF_CLE__GPIO_6_7)
+#define MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 (_MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23)
+#define MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 (_MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0)
+
+#define MX6Q_PAD_NANDF_ALE__RAWNAND_ALE (_MX6Q_PAD_NANDF_ALE__RAWNAND_ALE)
+#define MX6Q_PAD_NANDF_ALE__USDHC4_RST (_MX6Q_PAD_NANDF_ALE__USDHC4_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 (_MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0)
+#define MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 (_MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12)
+#define MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 (_MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12)
+#define MX6Q_PAD_NANDF_ALE__GPIO_6_8 (_MX6Q_PAD_NANDF_ALE__GPIO_6_8)
+#define MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 (_MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24)
+#define MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 (_MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1)
+
+#define MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN (_MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN)
+#define MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 (_MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5)
+#define MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 (_MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1)
+#define MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13)
+#define MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 (_MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13)
+#define MX6Q_PAD_NANDF_WP_B__GPIO_6_9 (_MX6Q_PAD_NANDF_WP_B__GPIO_6_9)
+#define MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 (_MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32)
+#define MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 (_MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0)
+
+#define MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 (_MX6Q_PAD_NANDF_RB0__RAWNAND_READY0)
+#define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 (_MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1)
+#define MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 (_MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2)
+#define MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 (_MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14)
+#define MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 (_MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14)
+#define MX6Q_PAD_NANDF_RB0__GPIO_6_10 (_MX6Q_PAD_NANDF_RB0__GPIO_6_10)
+#define MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 (_MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33)
+#define MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 (_MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1)
+
+#define MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N (_MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N)
+#define MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 (_MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15)
+#define MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 (_MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15)
+#define MX6Q_PAD_NANDF_CS0__GPIO_6_11 (_MX6Q_PAD_NANDF_CS0__GPIO_6_11)
+#define MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 (_MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2)
+
+#define MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N (_MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N)
+#define MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT (_MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT (_MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 (_MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3)
+#define MX6Q_PAD_NANDF_CS1__GPIO_6_14 (_MX6Q_PAD_NANDF_CS1__GPIO_6_14)
+#define MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT (_MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT)
+
+#define MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N (_MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N)
+#define MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 (_MX6Q_PAD_NANDF_CS2__IPU1_SISG_0)
+#define MX6Q_PAD_NANDF_CS2__ESAI1_TX0 (_MX6Q_PAD_NANDF_CS2__ESAI1_TX0)
+#define MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE (_MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE)
+#define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 (_MX6Q_PAD_NANDF_CS2__CCM_CLKO2)
+#define MX6Q_PAD_NANDF_CS2__GPIO_6_15 (_MX6Q_PAD_NANDF_CS2__GPIO_6_15)
+#define MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 (_MX6Q_PAD_NANDF_CS2__IPU2_SISG_0)
+
+#define MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N (_MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N)
+#define MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 (_MX6Q_PAD_NANDF_CS3__IPU1_SISG_1)
+#define MX6Q_PAD_NANDF_CS3__ESAI1_TX1 (_MX6Q_PAD_NANDF_CS3__ESAI1_TX1)
+#define MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 (_MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26)
+#define MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 (_MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4)
+#define MX6Q_PAD_NANDF_CS3__GPIO_6_16 (_MX6Q_PAD_NANDF_CS3__GPIO_6_16)
+#define MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 (_MX6Q_PAD_NANDF_CS3__IPU2_SISG_1)
+#define MX6Q_PAD_NANDF_CS3__TPSMP_CLK (_MX6Q_PAD_NANDF_CS3__TPSMP_CLK)
+
+#define MX6Q_PAD_SD4_CMD__USDHC4_CMD (_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_CMD__RAWNAND_RDN (_MX6Q_PAD_SD4_CMD__RAWNAND_RDN)
+#define MX6Q_PAD_SD4_CMD__UART3_TXD (_MX6Q_PAD_SD4_CMD__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_CMD__UART3_RXD (_MX6Q_PAD_SD4_CMD__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 (_MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5)
+#define MX6Q_PAD_SD4_CMD__GPIO_7_9 (_MX6Q_PAD_SD4_CMD__GPIO_7_9)
+#define MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR (_MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR)
+
+#define MX6Q_PAD_SD4_CLK__USDHC4_CLK (_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_CLK__RAWNAND_WRN (_MX6Q_PAD_SD4_CLK__RAWNAND_WRN)
+#define MX6Q_PAD_SD4_CLK__UART3_TXD (_MX6Q_PAD_SD4_CLK__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_CLK__UART3_RXD (_MX6Q_PAD_SD4_CLK__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 (_MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6)
+#define MX6Q_PAD_SD4_CLK__GPIO_7_10 (_MX6Q_PAD_SD4_CLK__GPIO_7_10)
+
+#define MX6Q_PAD_NANDF_D0__RAWNAND_D0 (_MX6Q_PAD_NANDF_D0__RAWNAND_D0)
+#define MX6Q_PAD_NANDF_D0__USDHC1_DAT4 (_MX6Q_PAD_NANDF_D0__USDHC1_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 (_MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0)
+#define MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 (_MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16)
+#define MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 (_MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16)
+#define MX6Q_PAD_NANDF_D0__GPIO_2_0 (_MX6Q_PAD_NANDF_D0__GPIO_2_0)
+#define MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 (_MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0)
+#define MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 (_MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0)
+
+#define MX6Q_PAD_NANDF_D1__RAWNAND_D1 (_MX6Q_PAD_NANDF_D1__RAWNAND_D1)
+#define MX6Q_PAD_NANDF_D1__USDHC1_DAT5 (_MX6Q_PAD_NANDF_D1__USDHC1_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 (_MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1)
+#define MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 (_MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17)
+#define MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 (_MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17)
+#define MX6Q_PAD_NANDF_D1__GPIO_2_1 (_MX6Q_PAD_NANDF_D1__GPIO_2_1)
+#define MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 (_MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1)
+#define MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 (_MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1)
+
+#define MX6Q_PAD_NANDF_D2__RAWNAND_D2 (_MX6Q_PAD_NANDF_D2__RAWNAND_D2)
+#define MX6Q_PAD_NANDF_D2__USDHC1_DAT6 (_MX6Q_PAD_NANDF_D2__USDHC1_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 (_MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2)
+#define MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 (_MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18)
+#define MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 (_MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18)
+#define MX6Q_PAD_NANDF_D2__GPIO_2_2 (_MX6Q_PAD_NANDF_D2__GPIO_2_2)
+#define MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 (_MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2)
+#define MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 (_MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2)
+
+#define MX6Q_PAD_NANDF_D3__RAWNAND_D3 (_MX6Q_PAD_NANDF_D3__RAWNAND_D3)
+#define MX6Q_PAD_NANDF_D3__USDHC1_DAT7 (_MX6Q_PAD_NANDF_D3__USDHC1_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 (_MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3)
+#define MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 (_MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19)
+#define MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 (_MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19)
+#define MX6Q_PAD_NANDF_D3__GPIO_2_3 (_MX6Q_PAD_NANDF_D3__GPIO_2_3)
+#define MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 (_MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3)
+#define MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 (_MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3)
+
+#define MX6Q_PAD_NANDF_D4__RAWNAND_D4 (_MX6Q_PAD_NANDF_D4__RAWNAND_D4)
+#define MX6Q_PAD_NANDF_D4__USDHC2_DAT4 (_MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 (_MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4)
+#define MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 (_MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20)
+#define MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 (_MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20)
+#define MX6Q_PAD_NANDF_D4__GPIO_2_4 (_MX6Q_PAD_NANDF_D4__GPIO_2_4)
+#define MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 (_MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4)
+#define MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 (_MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4)
+
+#define MX6Q_PAD_NANDF_D5__RAWNAND_D5 (_MX6Q_PAD_NANDF_D5__RAWNAND_D5)
+#define MX6Q_PAD_NANDF_D5__USDHC2_DAT5 (_MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 (_MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5)
+#define MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 (_MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21)
+#define MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 (_MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21)
+#define MX6Q_PAD_NANDF_D5__GPIO_2_5 (_MX6Q_PAD_NANDF_D5__GPIO_2_5)
+#define MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 (_MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5)
+#define MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 (_MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5)
+
+#define MX6Q_PAD_NANDF_D6__RAWNAND_D6 (_MX6Q_PAD_NANDF_D6__RAWNAND_D6)
+#define MX6Q_PAD_NANDF_D6__USDHC2_DAT6 (_MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 (_MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6)
+#define MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 (_MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22)
+#define MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 (_MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22)
+#define MX6Q_PAD_NANDF_D6__GPIO_2_6 (_MX6Q_PAD_NANDF_D6__GPIO_2_6)
+#define MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 (_MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6)
+#define MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 (_MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6)
+
+#define MX6Q_PAD_NANDF_D7__RAWNAND_D7 (_MX6Q_PAD_NANDF_D7__RAWNAND_D7)
+#define MX6Q_PAD_NANDF_D7__USDHC2_DAT7 (_MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 (_MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7)
+#define MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 (_MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23)
+#define MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 (_MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23)
+#define MX6Q_PAD_NANDF_D7__GPIO_2_7 (_MX6Q_PAD_NANDF_D7__GPIO_2_7)
+#define MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 (_MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7)
+#define MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 (_MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7)
+
+#define MX6Q_PAD_SD4_DAT0__RAWNAND_D8 (_MX6Q_PAD_SD4_DAT0__RAWNAND_D8)
+#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 (_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT0__RAWNAND_DQS (_MX6Q_PAD_SD4_DAT0__RAWNAND_DQS)
+#define MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 (_MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24)
+#define MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 (_MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24)
+#define MX6Q_PAD_SD4_DAT0__GPIO_2_8 (_MX6Q_PAD_SD4_DAT0__GPIO_2_8)
+#define MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 (_MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8)
+#define MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 (_MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8)
+
+#define MX6Q_PAD_SD4_DAT1__RAWNAND_D9 (_MX6Q_PAD_SD4_DAT1__RAWNAND_D9)
+#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 (_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT1__PWM3_PWMO (_MX6Q_PAD_SD4_DAT1__PWM3_PWMO)
+#define MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 (_MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25)
+#define MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 (_MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25)
+#define MX6Q_PAD_SD4_DAT1__GPIO_2_9 (_MX6Q_PAD_SD4_DAT1__GPIO_2_9)
+#define MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 (_MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9)
+#define MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 (_MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9)
+
+#define MX6Q_PAD_SD4_DAT2__RAWNAND_D10 (_MX6Q_PAD_SD4_DAT2__RAWNAND_D10)
+#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 (_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT2__PWM4_PWMO (_MX6Q_PAD_SD4_DAT2__PWM4_PWMO)
+#define MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 (_MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26)
+#define MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 (_MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26)
+#define MX6Q_PAD_SD4_DAT2__GPIO_2_10 (_MX6Q_PAD_SD4_DAT2__GPIO_2_10)
+#define MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 (_MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10)
+#define MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 (_MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10)
+
+#define MX6Q_PAD_SD4_DAT3__RAWNAND_D11 (_MX6Q_PAD_SD4_DAT3__RAWNAND_D11)
+#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 (_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 (_MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27)
+#define MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 (_MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27)
+#define MX6Q_PAD_SD4_DAT3__GPIO_2_11 (_MX6Q_PAD_SD4_DAT3__GPIO_2_11)
+#define MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 (_MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11)
+#define MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 (_MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11)
+
+#define MX6Q_PAD_SD4_DAT4__RAWNAND_D12 (_MX6Q_PAD_SD4_DAT4__RAWNAND_D12)
+#define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 (_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__UART2_TXD (_MX6Q_PAD_SD4_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__UART2_RXD (_MX6Q_PAD_SD4_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 (_MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28)
+#define MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 (_MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28)
+#define MX6Q_PAD_SD4_DAT4__GPIO_2_12 (_MX6Q_PAD_SD4_DAT4__GPIO_2_12)
+#define MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 (_MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12)
+#define MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 (_MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12)
+
+#define MX6Q_PAD_SD4_DAT5__RAWNAND_D13 (_MX6Q_PAD_SD4_DAT5__RAWNAND_D13)
+#define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 (_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__UART2_CTS (_MX6Q_PAD_SD4_DAT5__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__UART2_RTS (_MX6Q_PAD_SD4_DAT5__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 (_MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29)
+#define MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 (_MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29)
+#define MX6Q_PAD_SD4_DAT5__GPIO_2_13 (_MX6Q_PAD_SD4_DAT5__GPIO_2_13)
+#define MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 (_MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13)
+#define MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 (_MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13)
+
+#define MX6Q_PAD_SD4_DAT6__RAWNAND_D14 (_MX6Q_PAD_SD4_DAT6__RAWNAND_D14)
+#define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 (_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT6__UART2_CTS (_MX6Q_PAD_SD4_DAT6__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 (_MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30)
+#define MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 (_MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30)
+#define MX6Q_PAD_SD4_DAT6__GPIO_2_14 (_MX6Q_PAD_SD4_DAT6__GPIO_2_14)
+#define MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 (_MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14)
+#define MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 (_MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14)
+
+#define MX6Q_PAD_SD4_DAT7__RAWNAND_D15 (_MX6Q_PAD_SD4_DAT7__RAWNAND_D15)
+#define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 (_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__UART2_TXD (_MX6Q_PAD_SD4_DAT7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__UART2_RXD (_MX6Q_PAD_SD4_DAT7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
+#define MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 (_MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31)
+#define MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 (_MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31)
+#define MX6Q_PAD_SD4_DAT7__GPIO_2_15 (_MX6Q_PAD_SD4_DAT7__GPIO_2_15)
+#define MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 (_MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15)
+#define MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 (_MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15)
+
+#define MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 (_MX6Q_PAD_SD1_DAT1__ECSPI5_SS0)
+#define MX6Q_PAD_SD1_DAT1__PWM3_PWMO (_MX6Q_PAD_SD1_DAT1__PWM3_PWMO)
+#define MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 (_MX6Q_PAD_SD1_DAT1__GPT_CAPIN2)
+#define MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 (_MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7)
+#define MX6Q_PAD_SD1_DAT1__GPIO_1_17 (_MX6Q_PAD_SD1_DAT1__GPIO_1_17)
+#define MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 (_MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0)
+#define MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 (_MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8)
+
+#define MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO (_MX6Q_PAD_SD1_DAT0__ECSPI5_MISO)
+#define MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS (_MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS)
+#define MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 (_MX6Q_PAD_SD1_DAT0__GPT_CAPIN1)
+#define MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 (_MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8)
+#define MX6Q_PAD_SD1_DAT0__GPIO_1_16 (_MX6Q_PAD_SD1_DAT0__GPIO_1_16)
+#define MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 (_MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1)
+#define MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 (_MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7)
+
+#define MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 (_MX6Q_PAD_SD1_DAT3__ECSPI5_SS2)
+#define MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 (_MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3)
+#define MX6Q_PAD_SD1_DAT3__PWM1_PWMO (_MX6Q_PAD_SD1_DAT3__PWM1_PWMO)
+#define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B)
+#define MX6Q_PAD_SD1_DAT3__GPIO_1_21 (_MX6Q_PAD_SD1_DAT3__GPIO_1_21)
+#define MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB (_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB)
+#define MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 (_MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6)
+
+#define MX6Q_PAD_SD1_CMD__USDHC1_CMD (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI (_MX6Q_PAD_SD1_CMD__ECSPI5_MOSI)
+#define MX6Q_PAD_SD1_CMD__PWM4_PWMO (_MX6Q_PAD_SD1_CMD__PWM4_PWMO)
+#define MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 (_MX6Q_PAD_SD1_CMD__GPT_CMPOUT1)
+#define MX6Q_PAD_SD1_CMD__GPIO_1_18 (_MX6Q_PAD_SD1_CMD__GPIO_1_18)
+#define MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 (_MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5)
+
+#define MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 (_MX6Q_PAD_SD1_DAT2__ECSPI5_SS1)
+#define MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 (_MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2)
+#define MX6Q_PAD_SD1_DAT2__PWM2_PWMO (_MX6Q_PAD_SD1_DAT2__PWM2_PWMO)
+#define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B)
+#define MX6Q_PAD_SD1_DAT2__GPIO_1_19 (_MX6Q_PAD_SD1_DAT2__GPIO_1_19)
+#define MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB (_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB)
+#define MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 (_MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4)
+
+#define MX6Q_PAD_SD1_CLK__USDHC1_CLK (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK (_MX6Q_PAD_SD1_CLK__ECSPI5_SCLK)
+#define MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT (_MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT)
+#define MX6Q_PAD_SD1_CLK__GPT_CLKIN (_MX6Q_PAD_SD1_CLK__GPT_CLKIN)
+#define MX6Q_PAD_SD1_CLK__GPIO_1_20 (_MX6Q_PAD_SD1_CLK__GPIO_1_20)
+#define MX6Q_PAD_SD1_CLK__PHY_DTB_0 (_MX6Q_PAD_SD1_CLK__PHY_DTB_0)
+#define MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 (_MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0)
+
+#define MX6Q_PAD_SD2_CLK__USDHC2_CLK (_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK (_MX6Q_PAD_SD2_CLK__ECSPI5_SCLK)
+#define MX6Q_PAD_SD2_CLK__KPP_COL_5 (_MX6Q_PAD_SD2_CLK__KPP_COL_5)
+#define MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS (_MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS)
+#define MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 (_MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9)
+#define MX6Q_PAD_SD2_CLK__GPIO_1_10 (_MX6Q_PAD_SD2_CLK__GPIO_1_10)
+#define MX6Q_PAD_SD2_CLK__PHY_DTB_1 (_MX6Q_PAD_SD2_CLK__PHY_DTB_1)
+#define MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 (_MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1)
+
+#define MX6Q_PAD_SD2_CMD__USDHC2_CMD (_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI (_MX6Q_PAD_SD2_CMD__ECSPI5_MOSI)
+#define MX6Q_PAD_SD2_CMD__KPP_ROW_5 (_MX6Q_PAD_SD2_CMD__KPP_ROW_5)
+#define MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC (_MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC)
+#define MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 (_MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10)
+#define MX6Q_PAD_SD2_CMD__GPIO_1_11 (_MX6Q_PAD_SD2_CMD__GPIO_1_11)
+
+#define MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 (_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 (_MX6Q_PAD_SD2_DAT3__ECSPI5_SS3)
+#define MX6Q_PAD_SD2_DAT3__KPP_COL_6 (_MX6Q_PAD_SD2_DAT3__KPP_COL_6)
+#define MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC (_MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC)
+#define MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 (_MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11)
+#define MX6Q_PAD_SD2_DAT3__GPIO_1_12 (_MX6Q_PAD_SD2_DAT3__GPIO_1_12)
+#define MX6Q_PAD_SD2_DAT3__SJC_DONE (_MX6Q_PAD_SD2_DAT3__SJC_DONE)
+#define MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 (_MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3)
+
+#endif
--- /dev/null
+/*
+ * Based on Linux i.MX iomux-v3.h file:
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ * <armlinux@phytec.de>
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __MACH_IOMUX_V3_H__
+#define __MACH_IOMUX_V3_H__
+
+/*
+ * build IOMUX_PAD structure
+ *
+ * This iomux scheme is based around pads, which are the physical balls
+ * on the processor.
+ *
+ * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
+ * things like driving strength and pullup/pulldown.
+ * - Each pad can have but not necessarily does have an output routing register
+ * (IOMUXC_SW_MUX_CTL_PAD_x).
+ * - Each pad can have but not necessarily does have an input routing register
+ * (IOMUXC_x_SELECT_INPUT)
+ *
+ * The three register sets do not have a fixed offset to each other,
+ * hence we order this table by pad control registers (which all pads
+ * have) and put the optional i/o routing registers into additional
+ * fields.
+ *
+ * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ *
+ * IOMUX/PAD Bit field definitions
+ *
+ * MUX_CTRL_OFS: 0..11 (12)
+ * PAD_CTRL_OFS: 12..23 (12)
+ * SEL_INPUT_OFS: 24..35 (12)
+ * MUX_MODE + SION: 36..40 (5)
+ * PAD_CTRL + PAD_CTRL_VALID: 41..58 (18)
+ * SEL_INP: 59..61 (3)
+ * reserved: 62..63 (2)
+*/
+
+typedef u64 iomux_v3_cfg_t;
+
+#define MUX_CTRL_OFS_SHIFT 0
+#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
+#define MUX_PAD_CTRL_OFS_SHIFT 12
+#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
+ MUX_PAD_CTRL_OFS_SHIFT)
+#define MUX_SEL_INPUT_OFS_SHIFT 24
+#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
+ MUX_SEL_INPUT_OFS_SHIFT)
+
+#define MUX_MODE_SHIFT 36
+#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
+#define MUX_PAD_CTRL_SHIFT 41
+#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT)
+#define MUX_SEL_INPUT_SHIFT 59
+#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0x7 << MUX_SEL_INPUT_SHIFT)
+
+#define MUX_PAD_CTRL(x) (((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) | \
+ PAD_CTRL_VALID)
+
+#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
+ sel_input, pad_ctrl) \
+ (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
+ ((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
+ ((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
+ ((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
+ ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
+ ((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
+
+#define NO_MUX_I 0
+#define NO_PAD_I 0
+
+#define PAD_CTRL_VALID ((iomux_v3_cfg_t)1 << (MUX_PAD_CTRL_SHIFT + 17))
+
+#define GPIO_PIN_MASK 0xf
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
+
+#define IOMUX_CONFIG_SION (0x1 << 4)
+
+int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
+int imx_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list, unsigned count);
+
+/*
+ * IOMUXC_GPR13 bit fields
+ */
+#define IOMUXC_GPR13_SDMA_STOP_REQ (1 << 30)
+#define IOMUXC_GPR13_CAN2_STOP_REQ (1 << 29)
+#define IOMUXC_GPR13_CAN1_STOP_REQ (1 << 28)
+#define IOMUXC_GPR13_ENET_STOP_REQ (1 << 27)
+#define IOMUXC_GPR13_SATA_PHY_8_MASK (7 << 24)
+#define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f << 19)
+#define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16
+#define IOMUXC_GPR13_SATA_PHY_6_MASK (7 << IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+#define IOMUXC_GPR13_SATA_SPEED_MASK (1 << 15)
+#define IOMUXC_GPR13_SATA_PHY_5_MASK (1 << 14)
+#define IOMUXC_GPR13_SATA_PHY_4_MASK (7 << 11)
+#define IOMUXC_GPR13_SATA_PHY_3_MASK (0x1f << 7)
+#define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f << 2)
+#define IOMUXC_GPR13_SATA_PHY_1_MASK (3 << 0)
+
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0b000 << 24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (0b001 << 24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (0b010 << 24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (0b011 << 24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (0b100 << 24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (0b101 << 24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (0b110 << 24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (0b111 << 24)
+
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000 << 19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000 << 19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010 << 19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010 << 19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010 << 19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010 << 19)
+
+#define IOMUXC_GPR13_SATA_SPEED_1P5G (0 << 15)
+#define IOMUXC_GPR13_SATA_SPEED_3G (1 << 15)
+
+#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED (0 << 14)
+#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED (1 << 14)
+
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16 (0 << 11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16 (1 << 11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 (2 << 11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16 (3 << 11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4 << 11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5 << 11)
+
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0b0000 << 7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (0b0001 << 7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (0b0010 << 7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (0b0011 << 7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (0b0100 << 7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (0b0101 << 7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (0b0110 << 7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (0b0111 << 7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (0b1000 << 7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (0b1001 << 7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0b1010 << 7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0b1011 << 7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0b1100 << 7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0b1101 << 7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0b1110 << 7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0b1111 << 7)
+
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0b00000 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (0b00001 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (0b00010 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (0b00011 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (0b00100 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (0b00101 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (0b00110 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (0b00111 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (0b01000 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (0b01001 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0b01010 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0b01011 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0b01100 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0b01101 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0b01110 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0b01111 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0b10000 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0b10001 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0b10010 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0b10011 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0b10100 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0b10101 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0b10110 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0b10111 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0b11000 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0b11001 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0b11010 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0b11011 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0b11100 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0b11101 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0b11110 << 2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0b11111 << 2)
+
+#define IOMUXC_GPR13_SATA_PHY_1_FAST 0
+#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1
+#define IOMUXC_GPR13_SATA_PHY_1_SLOW 2
+
+#define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \
+ |IOMUXC_GPR13_SATA_PHY_7_MASK \
+ |IOMUXC_GPR13_SATA_PHY_6_MASK \
+ |IOMUXC_GPR13_SATA_SPEED_MASK \
+ |IOMUXC_GPR13_SATA_PHY_5_MASK \
+ |IOMUXC_GPR13_SATA_PHY_4_MASK \
+ |IOMUXC_GPR13_SATA_PHY_3_MASK \
+ |IOMUXC_GPR13_SATA_PHY_2_MASK \
+ |IOMUXC_GPR13_SATA_PHY_1_MASK)
+
+#endif /* __MACH_IOMUX_V3_H__*/
+++ /dev/null
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Auto Generate file, please don't edit it
- *
- */
-
-#ifndef __ASM_ARCH_MX6_MX6X_PINS_H__
-#define __ASM_ARCH_MX6_MX6X_PINS_H__
-
-#include <asm/imx-common/iomux-v3.h>
-
-/* Use to set PAD control */
-#define PAD_CTL_HYS (1 << 16)
-#define PAD_CTL_PUS_100K_DOWN (0 << 14)
-#define PAD_CTL_PUS_47K_UP (1 << 14)
-#define PAD_CTL_PUS_100K_UP (2 << 14)
-#define PAD_CTL_PUS_22K_UP (3 << 14)
-
-#define PAD_CTL_PUE (1 << 13)
-#define PAD_CTL_PKE (1 << 12)
-#define PAD_CTL_ODE (1 << 11)
-#define PAD_CTL_SPEED_LOW (1 << 6)
-#define PAD_CTL_SPEED_MED (2 << 6)
-#define PAD_CTL_SPEED_HIGH (3 << 6)
-#define PAD_CTL_DSE_DISABLE (0 << 3)
-#define PAD_CTL_DSE_240ohm (1 << 3)
-#define PAD_CTL_DSE_120ohm (2 << 3)
-#define PAD_CTL_DSE_80ohm (3 << 3)
-#define PAD_CTL_DSE_60ohm (4 << 3)
-#define PAD_CTL_DSE_48ohm (5 << 3)
-#define PAD_CTL_DSE_40ohm (6 << 3)
-#define PAD_CTL_DSE_34ohm (7 << 3)
-#define PAD_CTL_SRE_FAST (1 << 0)
-#define PAD_CTL_SRE_SLOW (0 << 0)
-
-#define NO_MUX_I 0
-#define NO_PAD_I 0
-
-enum {
- MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0),
- MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 = IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0),
- MX6Q_PAD_SD2_DAT1__KPP_COL_7 = IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0),
- MX6Q_PAD_SD2_DAT1__GPIO_1_14 = IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT1__CCM_WAIT = IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 = IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0),
- MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 = IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0),
- MX6Q_PAD_SD2_DAT2__KPP_ROW_6 = IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0),
- MX6Q_PAD_SD2_DAT2__GPIO_1_13 = IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT2__CCM_STOP = IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 = IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0),
- MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0),
- MX6Q_PAD_SD2_DAT0__KPP_ROW_7 = IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0),
- MX6Q_PAD_SD2_DAT0__GPIO_1_15 = IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT = IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT0__TESTO_2 = IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA = IOMUX_PAD(0x036C, 0x0058, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0),
- MX6Q_PAD_RGMII_TXC__GPIO_6_19 = IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 = IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT = IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY = IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD0__GPIO_6_20 = IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 = IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG = IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD1__GPIO_6_21 = IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 = IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP = IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA = IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD2__GPIO_6_22 = IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 = IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP = IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK = IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD3__GPIO_6_23 = IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 = IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA = IOMUX_PAD(0x0380, 0x006C, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0),
- MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 = IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY = IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0),
- MX6Q_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 = IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE = IOMUX_PAD(0x0388, 0x0074, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 = IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 = IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT = IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0),
- MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL = IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0),
- MX6Q_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 = IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD1__SJC_FAIL = IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA = IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0),
- MX6Q_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 = IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK = IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0),
- MX6Q_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 = IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE = IOMUX_PAD(0x0398, 0x0084, 0, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0),
- MX6Q_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0),
- MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 = IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__ECSPI4_SS1 = IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 = IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__GPIO_5_2 = IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0),
- MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 = IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 = IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0),
- MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0),
- MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 = IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0),
- MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL = IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0),
- MX6Q_PAD_EIM_EB2__GPIO_2_30 = IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x03A0, 0x008C, 22, 0x08A0, 0, 0),
- MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 = IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 = IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0),
- MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 = IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 = IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0),
- MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA = IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0),
- MX6Q_PAD_EIM_D16__GPIO_3_16 = IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0090, 22, 0x08A4, 0, 0),
- MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 = IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0),
- MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 = IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0),
- MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D17__GPIO_3_17 = IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x03A8, 0x0094, 22, 0x08A8, 0, 0),
- MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 = IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0),
- MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 = IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 = IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0),
- MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D18__GPIO_3_18 = IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x03AC, 0x0098, 22, 0x08AC, 0, 0),
- MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 = IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0),
- MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 = IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 = IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0),
- MX6Q_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0),
- MX6Q_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D19__PL301MX6QPER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0),
- MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0),
- MX6Q_PAD_EIM_D20__UART1_CTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0),
- MX6Q_PAD_EIM_D20__GPIO_3_20 = IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D21__ECSPI4_SCLK = IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 = IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 = IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0),
- MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0),
- MX6Q_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x03B8, 0x00A4, 22, 0x0898, 0, 0),
- MX6Q_PAD_EIM_D21__SPDIF_IN1 = IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0),
- MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__ECSPI4_MISO = IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 = IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 = IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0),
- MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D22__PL301MX6QPER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0),
- MX6Q_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0),
- MX6Q_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 = IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 = IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__ECSPI4_RDY = IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__UART3_CTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0),
- MX6Q_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC = IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0),
- MX6Q_PAD_EIM_EB3__GPIO_2_31 = IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 = IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 = IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__ECSPI4_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__UART3_TXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__UART3_TXD_RXD = IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0),
- MX6Q_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0),
- MX6Q_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__GPIO_3_24 = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0),
- MX6Q_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D25__ECSPI4_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0),
- MX6Q_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0),
- MX6Q_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D25__GPIO_3_25 = IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0),
- MX6Q_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 = IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 = IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 = IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0),
- MX6Q_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__UART2_TXD_RXD = IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0),
- MX6Q_PAD_EIM_D26__GPIO_3_26 = IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__IPU1_SISG_2 = IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 = IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 = IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 = IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 = IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0),
- MX6Q_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0),
- MX6Q_PAD_EIM_D27__GPIO_3_27 = IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__IPU1_SISG_3 = IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 = IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x03D8, 0x00C4, 17, 0x089C, 0, 0),
- MX6Q_PAD_EIM_D28__ECSPI4_MOSI = IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 = IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0),
- MX6Q_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0),
- MX6Q_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG = IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 = IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 = IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D29__ECSPI4_SS0 = IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0),
- MX6Q_PAD_EIM_D29__UART2_CTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0),
- MX6Q_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC = IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0),
- MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 = IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 = IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 = IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 = IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0),
- MX6Q_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0),
- MX6Q_PAD_EIM_D30__PL301MX6QPER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 = IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__UART3_CTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0),
- MX6Q_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_D31__PL301MX6QPER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 = IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0),
- MX6Q_PAD_EIM_A24__IPU2_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__PL301MX6QPER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 = IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0),
- MX6Q_PAD_EIM_A23__IPU2_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__PL301MX6QPER1_HPROT_3 = IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 = IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 = IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0),
- MX6Q_PAD_EIM_A22__GPIO_2_16 = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0),
- MX6Q_PAD_EIM_A21__RESERVED_RESERVED = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 = IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__GPIO_2_17 = IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 = IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 = IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 = IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 = IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0),
- MX6Q_PAD_EIM_A20__RESERVED_RESERVED = IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 = IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__GPIO_2_18 = IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 = IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 = IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 = IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 = IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0),
- MX6Q_PAD_EIM_A19__RESERVED_RESERVED = IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 = IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__GPIO_2_19 = IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 = IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 = IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 = IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 = IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0),
- MX6Q_PAD_EIM_A18__RESERVED_RESERVED = IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 = IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__GPIO_2_20 = IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 = IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 = IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 = IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 = IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0),
- MX6Q_PAD_EIM_A17__RESERVED_RESERVED = IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 = IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__GPIO_2_21 = IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 = IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 = IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK = IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK = IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0),
- MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 = IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__GPIO_2_22 = IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 = IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 = IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 = IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0),
- MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 = IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS0__GPIO_2_23 = IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 = IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 = IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0),
- MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 = IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS1__GPIO_2_24 = IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 = IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_OE__WEIM_WEIM_OE = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 = IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0),
- MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 = IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_OE__GPIO_2_25 = IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 = IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__WEIM_WEIM_RW = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 = IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0),
- MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 = IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__GPIO_2_26 = IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 = IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 = IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 = IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0),
- MX6Q_PAD_EIM_LBA__GPIO_2_27 = IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 = IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 = IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 = IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 = IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0),
- MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 = IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY = IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0),
- MX6Q_PAD_EIM_EB0__GPIO_2_28 = IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 = IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 = IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 = IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 = IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 = IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0),
- MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 = IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__GPIO_2_29 = IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 = IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 = IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 = IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 = IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 = IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__GPIO_3_0 = IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 = IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 = IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 = IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 = IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 = IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 = IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE = IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__GPIO_3_1 = IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 = IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 = IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 = IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 = IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 = IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 = IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE = IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__GPIO_3_2 = IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 = IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 = IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 = IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 = IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 = IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 = IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ = IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__GPIO_3_3 = IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 = IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 = IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 = IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 = IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 = IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 = IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN = IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__GPIO_3_4 = IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 = IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 = IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 = IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 = IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 = IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 = IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP = IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__GPIO_3_5 = IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 = IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 = IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 = IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 = IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 = IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 = IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN = IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__GPIO_3_6 = IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 = IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 = IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 = IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 = IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 = IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 = IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__GPIO_3_7 = IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 = IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 = IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 = IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 = IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 = IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 = IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__GPIO_3_8 = IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 = IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 = IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 = IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 = IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 = IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 = IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 = IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 = IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 = IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 = IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN = IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0),
- MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 = IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__GPIO_3_10 = IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 = IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 = IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 = IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 = IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC = IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0),
- MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 = IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 = IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__GPIO_3_11 = IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 = IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 = IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 = IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 = IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC = IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0),
- MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 = IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 = IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__GPIO_3_12 = IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 = IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 = IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 = IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS = IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0),
- MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 = IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 = IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__GPIO_3_13 = IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 = IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 = IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 = IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS = IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 = IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 = IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__GPIO_3_14 = IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 = IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 = IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 = IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 = IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 = IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 = IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__GPIO_3_15 = IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 = IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 = IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT = IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B = IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_WAIT__GPIO_5_0 = IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 = IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0),
- MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 = IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0),
- MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK = IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0),
- MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0),
- MX6Q_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0),
- MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0),
- MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0),
- MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0),
- MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0),
- MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 = IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 = IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 = IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 = IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0),
- MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0),
- MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL = IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS = IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT = IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 = IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 = IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 = IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0),
- MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0),
- MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0),
- MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0),
- MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 = IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0),
- MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0),
- MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0),
- MX6Q_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0),
- MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0),
- MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0),
- MX6Q_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0),
- MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0),
- MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0),
- MX6Q_PAD_DISP0_DAT18__GPIO_5_12 = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0),
- MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0),
- MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0),
- MX6Q_PAD_DISP0_DAT19__GPIO_5_13 = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0),
- MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0),
- MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 = IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0),
- MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0),
- MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 = IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0),
- MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0),
- MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 = IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
- MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0),
- MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0),
- MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 = IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0),
- MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 = IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED = IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0),
- MX6Q_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0),
- MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 = IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT = IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDIO__GPIO_1_22 = IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK = IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED = IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 = IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 = IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK = IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH = IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RX_ER__ENET_RX_ER = IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0),
- MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 = IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0),
- MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT = IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RX_ER__GPIO_1_24 = IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RX_ER__PHY_TDI = IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD = IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED = IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN = IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0),
- MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0),
- MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK = IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0),
- MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 = IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_CRS_DV__PHY_TDO = IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD = IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD1__MLB_MLBSIG = IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0),
- MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 = IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0),
- MX6Q_PAD_ENET_RXD1__ESAI1_FST = IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0),
- MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT = IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD1__GPIO_1_26 = IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD1__PHY_TCK = IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON = IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT = IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 = IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0),
- MX6Q_PAD_ENET_RXD0__ESAI1_HCKT = IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0),
- MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 = IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD0__PHY_TMS = IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV = IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED = IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TX_EN__ENET_TX_EN = IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0),
- MX6Q_PAD_ENET_TX_EN__GPIO_1_28 = IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI = IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH = IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD1__MLB_MLBCLK = IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0),
- MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 = IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0),
- MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN = IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD1__GPIO_1_29 = IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO = IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD = IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED = IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 = IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0),
- MX6Q_PAD_ENET_TXD0__GPIO_1_30 = IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK = IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD = IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDC__MLB_MLBDAT = IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0),
- MX6Q_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0),
- MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN = IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDC__GPIO_1_31 = IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDC__SATA_PHY_TMS = IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0),
- MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON = IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 = IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 = IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 = IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 = IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 = IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 = IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 = IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 = IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 = IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 = IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 = IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 = IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 = IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 = IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 = IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 = IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 = IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 = IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 = IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 = IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 = IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 = IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 = IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS = IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 = IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 = IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS = IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET = IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 = IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 = IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 = IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 = IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 = IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 = IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 = IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 = IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 = IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE = IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 = IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 = IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 = IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 = IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 = IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 = IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 = IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 = IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0),
- MX6Q_PAD_KEY_COL0__ENET_RDATA_3 = IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0),
- MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0),
- MX6Q_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL0__UART4_TXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL0__UART4_TXD_RXD = IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0),
- MX6Q_PAD_KEY_COL0__GPIO_4_6 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT = IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0),
- MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0),
- MX6Q_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0),
- MX6Q_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 = IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0),
- MX6Q_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0),
- MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0),
- MX6Q_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL1__UART5_TXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL1__UART5_TXD_RXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0),
- MX6Q_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 = IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0),
- MX6Q_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0),
- MX6Q_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0),
- MX6Q_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 = IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0),
- MX6Q_PAD_KEY_COL2__ENET_RDATA_2 = IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0),
- MX6Q_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP = IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 = IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0),
- MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0),
- MX6Q_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0),
- MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 = IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0),
- MX6Q_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0),
- MX6Q_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20, 0x08A0, 1, 0),
- MX6Q_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0),
- MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 = IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0),
- MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0),
- MX6Q_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20, 0x08A4, 1, 0),
- MX6Q_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 = IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0),
- MX6Q_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__UART5_CTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0),
- MX6Q_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 = IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 = IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0),
- MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0),
- MX6Q_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0),
- MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 = IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0),
- MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0),
- MX6Q_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_0__GPIO_1_0 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 = IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0),
- MX6Q_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0),
- MX6Q_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_1__GPIO_1_1 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_1__USDHC1_CD = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0),
- MX6Q_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0),
- MX6Q_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_9__GPIO_1_9 = IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_9__USDHC1_WP = IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0),
- MX6Q_PAD_GPIO_9__SRC_EARLY_RST = IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0),
- MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 = IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x05FC, 0x022C, 18, 0x08A8, 1, 0),
- MX6Q_PAD_GPIO_3__ANATOP_24M_OUT = IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_3__GPIO_1_3 = IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0),
- MX6Q_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0),
- MX6Q_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0),
- MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 = IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x0600, 0x0230, 18, 0x08AC, 1, 0),
- MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_6__GPIO_1_6 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_6__USDHC2_LCTL = IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0),
- MX6Q_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0),
- MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 = IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0),
- MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_2__USDHC2_WP = IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0),
- MX6Q_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0),
- MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 = IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0),
- MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_4__GPIO_1_4 = IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_4__USDHC2_CD = IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA = IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0),
- MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 = IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0),
- MX6Q_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x060C, 0x023C, 22, 0x08A8, 2, 0),
- MX6Q_PAD_GPIO_5__CHEETAH_EVENTI = IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0),
- MX6Q_PAD_GPIO_7__ECSPI5_RDY = IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__UART2_TXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__UART2_TXD_RXD = IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0),
- MX6Q_PAD_GPIO_7__GPIO_1_7 = IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE = IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0),
- MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT = IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0),
- MX6Q_PAD_GPIO_8__UART2_RXD = IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0),
- MX6Q_PAD_GPIO_8__GPIO_1_8 = IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK = IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0),
- MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN = IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT = IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0),
- MX6Q_PAD_GPIO_16__USDHC1_LCTL = IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0),
- MX6Q_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x0618, 0x0248, 22, 0x08AC, 2, 0),
- MX6Q_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0),
- MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN = IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_17__CCM_PMIC_RDY = IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0),
- MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0),
- MX6Q_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0),
- MX6Q_PAD_GPIO_18__ENET_RX_CLK = IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0),
- MX6Q_PAD_GPIO_18__USDHC3_VSELECT = IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0),
- MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0),
- MX6Q_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 = IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0),
- MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT = IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__ENET_TX_ER = IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0),
- MX6Q_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK = IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 = IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 = IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 = IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO = IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC = IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 = IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__CCM_CLKO = IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__GPIO_5_19 = IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 = IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL = IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN = IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 = IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 = IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 = IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 = IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK = IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC = IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 = IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 = IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 = IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 = IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 = IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 = IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 = IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0),
- MX6Q_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0),
- MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__GPIO_5_22 = IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 = IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 = IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 = IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 = IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0),
- MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0),
- MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__GPIO_5_23 = IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 = IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 = IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 = IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 = IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0),
- MX6Q_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0),
- MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__GPIO_5_24 = IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 = IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 = IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 = IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 = IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0),
- MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0),
- MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__GPIO_5_25 = IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 = IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 = IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 = IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 = IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0),
- MX6Q_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0),
- MX6Q_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x0648, 0x0278, 20, 0x089C, 1, 0),
- MX6Q_PAD_CSI0_DAT8__GPIO_5_26 = IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 = IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 = IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 = IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 = IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0),
- MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0),
- MX6Q_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x064C, 0x027C, 20, 0x0898, 1, 0),
- MX6Q_PAD_CSI0_DAT9__GPIO_5_27 = IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 = IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 = IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 = IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0),
- MX6Q_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__UART1_TXD_RXD = IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0),
- MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__GPIO_5_28 = IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 = IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 = IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 = IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0),
- MX6Q_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0),
- MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__GPIO_5_29 = IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 = IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 = IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 = IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 = IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 = IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__UART4_TXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__UART4_TXD_RXD = IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0),
- MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__GPIO_5_30 = IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 = IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 = IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 = IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 = IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 = IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__UART4_RXD = IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0),
- MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__GPIO_5_31 = IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 = IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 = IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 = IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 = IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 = IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__UART5_TXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__UART5_TXD_RXD = IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0),
- MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__GPIO_6_0 = IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 = IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 = IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 = IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 = IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 = IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__UART5_RXD = IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0),
- MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__GPIO_6_1 = IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 = IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 = IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 = IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 = IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 = IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__UART4_CTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0),
- MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__GPIO_6_2 = IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 = IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 = IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 = IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 = IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 = IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0),
- MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__GPIO_6_3 = IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 = IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 = IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 = IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 = IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 = IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__UART5_CTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0),
- MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__GPIO_6_4 = IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 = IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 = IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 = IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 = IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 = IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0),
- MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__GPIO_6_5 = IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 = IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0),
- MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 = IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB = IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_POR_B__SRC_POR_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_RESET_IN_B__SRC_RESET_B = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 = IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__UART1_TXD_RXD = IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0),
- MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 = IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 = IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__GPIO_6_17 = IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 = IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV = IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 = IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0),
- MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 = IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__GPIO_6_18 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 = IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 = IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 = IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__UART2_TXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__UART2_TXD_RXD = IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0),
- MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 = IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 = IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 = IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 = IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 = IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__UART2_RXD = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0),
- MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 = IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 = IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__GPIO_7_1 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 = IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 = IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06A0, 0x02B8, 16, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__UART2_CTS = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0),
- MX6Q_PAD_SD3_CMD__CAN1_TXCAN = IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 = IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__GPIO_7_2 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 = IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 = IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__UART2_CTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__UART2_RTS = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0),
- MX6Q_PAD_SD3_CLK__CAN1_RXCAN = IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0),
- MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 = IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__GPIO_7_3 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 = IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 = IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__UART1_CTS = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0),
- MX6Q_PAD_SD3_DAT0__CAN2_TXCAN = IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 = IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__GPIO_7_4 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 = IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 = IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__UART1_CTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__UART1_RTS = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0),
- MX6Q_PAD_SD3_DAT1__CAN2_RXCAN = IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0),
- MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 = IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__GPIO_7_5 = IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 = IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 = IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 = IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 = IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__GPIO_7_6 = IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 = IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 = IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__UART3_CTS = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0),
- MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 = IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 = IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__GPIO_7_7 = IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 = IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 = IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__USDHC3_RST = IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__UART3_CTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__UART3_RTS = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0),
- MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 = IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 = IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__GPIO_7_8 = IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 = IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 = IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__RAWNAND_CLE = IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 = IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 = IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__GPIO_6_7 = IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 = IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 = IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__RAWNAND_ALE = IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__USDHC4_RST = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 = IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 = IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__GPIO_6_8 = IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 = IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 = IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 = IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 = IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 = IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__GPIO_6_9 = IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 = IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 = IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 = IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 = IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 = IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__GPIO_6_10 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 = IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 = IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 = IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS0__GPIO_6_11 = IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 = IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 = IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT = IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0),
- MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE = IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS2__CCM_CLKO2 = IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0),
- MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 = IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 = IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 = IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_CS3__TPSMP_CLK = IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CMD__RAWNAND_RDN = IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CMD__UART3_TXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CMD__UART3_TXD_RXD = IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0),
- MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 = IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CMD__GPIO_7_9 = IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR = IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CLK__RAWNAND_WRN = IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CLK__UART3_RXD = IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0),
- MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 = IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_CLK__GPIO_7_10 = IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D0__RAWNAND_D0 = IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D0__USDHC1_DAT4 = IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 = IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 = IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D0__GPIO_2_0 = IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 = IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D1__RAWNAND_D1 = IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D1__USDHC1_DAT5 = IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 = IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 = IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 = IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D2__RAWNAND_D2 = IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D2__USDHC1_DAT6 = IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 = IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 = IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 = IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D3__RAWNAND_D3 = IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D3__USDHC1_DAT7 = IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 = IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 = IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 = IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D4__RAWNAND_D4 = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D4__USDHC2_DAT4 = IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 = IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 = IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 = IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D5__RAWNAND_D5 = IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D5__USDHC2_DAT5 = IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 = IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 = IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D5__GPIO_2_5 = IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 = IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D6__RAWNAND_D6 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D6__USDHC2_DAT6 = IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 = IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 = IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 = IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D7__RAWNAND_D7 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D7__USDHC2_DAT7 = IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 = IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 = IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D7__GPIO_2_7 = IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0),
- MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 = IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT0__RAWNAND_D8 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT0__RAWNAND_DQS = IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 = IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT0__GPIO_2_8 = IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 = IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT1__RAWNAND_D9 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT1__PWM3_PWMO = IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 = IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT1__GPIO_2_9 = IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 = IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT2__RAWNAND_D10 = IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT2__PWM4_PWMO = IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 = IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT2__GPIO_2_10 = IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 = IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT3__RAWNAND_D11 = IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 = IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT3__GPIO_2_11 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 = IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT4__RAWNAND_D12 = IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 = IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT4__UART2_RXD = IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0),
- MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 = IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT4__GPIO_2_12 = IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 = IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT5__RAWNAND_D13 = IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT5__UART2_CTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT5__UART2_RTS = IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0),
- MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 = IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT5__GPIO_2_13 = IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 = IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT6__RAWNAND_D14 = IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 = IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT6__UART2_CTS = IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0),
- MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 = IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT6__GPIO_2_14 = IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 = IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__RAWNAND_D15 = IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 = IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__UART2_TXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__UART2_TXD_RXD = IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0),
- MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__GPIO_2_15 = IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 = IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0),
- MX6Q_PAD_SD1_DAT1__PWM3_PWMO = IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 = IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 = IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT1__GPIO_1_17 = IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 = IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 = IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT0__ECSPI5_MISO = IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0),
- MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS = IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 = IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 = IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT0__GPIO_1_16 = IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 = IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 = IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 = IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT3__PWM1_PWMO = IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B = IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 = IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0730, 0x0348, 16, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0),
- MX6Q_PAD_SD1_CMD__PWM4_PWMO = IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 = IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0),
- MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 = IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT2__PWM2_PWMO = IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B = IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT2__GPIO_1_19 = IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 = IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CLK__ECSPI5_SCLK = IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0),
- MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT = IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CLK__GPIO_1_20 = IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CLK__PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 = IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD2_CLK__ECSPI5_SCLK = IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0),
- MX6Q_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0),
- MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0),
- MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 = IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD2_CLK__GPIO_1_10 = IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD2_CLK__PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 = IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0),
- MX6Q_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0740, 0x0358, 16, 0x0000, 0, 0),
- MX6Q_PAD_SD2_CMD__ECSPI5_MOSI = IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0),
- MX6Q_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0),
- MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0),
- MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 = IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD2_CMD__GPIO_1_11 = IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 = IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT3__KPP_COL_6 = IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0),
- MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0),
- MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 = IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT3__GPIO_1_12 = IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT3__SJC_DONE = IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0),
- MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 = IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0),
-};
-
-#endif /* __ASM_ARCH_MX6_MX6X_PINS_H__ */
--- /dev/null
+/*
+ * Freescale i.MX6Q APBH Register Definitions
+ *
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on: arch/arm/include/arch-mx28/apbh-regs.h by Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __REGS_APBH_H__
+#define __REGS_APBH_H__
+
+#include <asm/arch/imx-regs.h>
+
+#define MXS_APBH_BASE 0x00110000
+
+#ifndef __ASSEMBLY__
+struct apbh_regs {
+ mx6_reg_32(hw_apbh_ctrl0); /* 0x000 */
+ mx6_reg_32(hw_apbh_ctrl1); /* 0x010 */
+ mx6_reg_32(hw_apbh_ctrl2); /* 0x020 */
+ mx6_reg_32(hw_apbh_channel_ctrl); /* 0x030 */
+ reg_32(hw_apbh_devsel); /* 0x040 */
+ reg_32(hw_apbh_dma_burst_size); /* 0x050 */
+ reg_32(hw_apbh_debug); /* 0x060 */
+
+ reg_32(reserved[9]); /* 0x064-0x0fc */
+
+ union {
+ struct {
+ reg_32(hw_apbh_ch_curcmdar);
+ reg_32(hw_apbh_ch_nxtcmdar);
+ reg_32(hw_apbh_ch_cmd);
+ reg_32(hw_apbh_ch_bar);
+ reg_32(hw_apbh_ch_sema);
+ reg_32(hw_apbh_ch_debug1);
+ reg_32(hw_apbh_ch_debug2);
+ } ch[16];
+ struct {
+ reg_32(hw_apbh_ch0_curcmdar); /* 0x100 */
+ reg_32(hw_apbh_ch0_nxtcmdar); /* 0x110 */
+ reg_32(hw_apbh_ch0_cmd); /* 0x120 */
+ reg_32(hw_apbh_ch0_bar); /* 0x130 */
+ reg_32(hw_apbh_ch0_sema); /* 0x140 */
+ reg_32(hw_apbh_ch0_debug1); /* 0x150 */
+ reg_32(hw_apbh_ch0_debug2); /* 0x160 */
+ reg_32(hw_apbh_ch1_curcmdar); /* 0x170 */
+ reg_32(hw_apbh_ch1_nxtcmdar); /* 0x180 */
+ reg_32(hw_apbh_ch1_cmd); /* 0x190 */
+ reg_32(hw_apbh_ch1_bar); /* 0x1a0 */
+ reg_32(hw_apbh_ch1_sema); /* 0x1b0 */
+ reg_32(hw_apbh_ch1_debug1); /* 0x1c0 */
+ reg_32(hw_apbh_ch1_debug2); /* 0x1d0 */
+ reg_32(hw_apbh_ch2_curcmdar); /* 0x1e0 */
+ reg_32(hw_apbh_ch2_nxtcmdar); /* 0x1f0 */
+ reg_32(hw_apbh_ch2_cmd); /* 0x200 */
+ reg_32(hw_apbh_ch2_bar); /* 0x210 */
+ reg_32(hw_apbh_ch2_sema); /* 0x220 */
+ reg_32(hw_apbh_ch2_debug1); /* 0x230 */
+ reg_32(hw_apbh_ch2_debug2); /* 0x240 */
+ reg_32(hw_apbh_ch3_curcmdar); /* 0x250 */
+ reg_32(hw_apbh_ch3_nxtcmdar); /* 0x260 */
+ reg_32(hw_apbh_ch3_cmd); /* 0x270 */
+ reg_32(hw_apbh_ch3_bar); /* 0x280 */
+ reg_32(hw_apbh_ch3_sema); /* 0x290 */
+ reg_32(hw_apbh_ch3_debug1); /* 0x2a0 */
+ reg_32(hw_apbh_ch3_debug2); /* 0x2b0 */
+ reg_32(hw_apbh_ch4_curcmdar); /* 0x2c0 */
+ reg_32(hw_apbh_ch4_nxtcmdar); /* 0x2d0 */
+ reg_32(hw_apbh_ch4_cmd); /* 0x2e0 */
+ reg_32(hw_apbh_ch4_bar); /* 0x2f0 */
+ reg_32(hw_apbh_ch4_sema); /* 0x300 */
+ reg_32(hw_apbh_ch4_debug1); /* 0x310 */
+ reg_32(hw_apbh_ch4_debug2); /* 0x320 */
+ reg_32(hw_apbh_ch5_curcmdar); /* 0x330 */
+ reg_32(hw_apbh_ch5_nxtcmdar); /* 0x340 */
+ reg_32(hw_apbh_ch5_cmd); /* 0x350 */
+ reg_32(hw_apbh_ch5_bar); /* 0x360 */
+ reg_32(hw_apbh_ch5_sema); /* 0x370 */
+ reg_32(hw_apbh_ch5_debug1); /* 0x380 */
+ reg_32(hw_apbh_ch5_debug2); /* 0x390 */
+ reg_32(hw_apbh_ch6_curcmdar); /* 0x3a0 */
+ reg_32(hw_apbh_ch6_nxtcmdar); /* 0x3b0 */
+ reg_32(hw_apbh_ch6_cmd); /* 0x3c0 */
+ reg_32(hw_apbh_ch6_bar); /* 0x3d0 */
+ reg_32(hw_apbh_ch6_sema); /* 0x3e0 */
+ reg_32(hw_apbh_ch6_debug1); /* 0x3f0 */
+ reg_32(hw_apbh_ch6_debug2); /* 0x400 */
+ reg_32(hw_apbh_ch7_curcmdar); /* 0x410 */
+ reg_32(hw_apbh_ch7_nxtcmdar); /* 0x420 */
+ reg_32(hw_apbh_ch7_cmd); /* 0x430 */
+ reg_32(hw_apbh_ch7_bar); /* 0x440 */
+ reg_32(hw_apbh_ch7_sema); /* 0x450 */
+ reg_32(hw_apbh_ch7_debug1); /* 0x460 */
+ reg_32(hw_apbh_ch7_debug2); /* 0x470 */
+ reg_32(hw_apbh_ch8_curcmdar); /* 0x480 */
+ reg_32(hw_apbh_ch8_nxtcmdar); /* 0x490 */
+ reg_32(hw_apbh_ch8_cmd); /* 0x4a0 */
+ reg_32(hw_apbh_ch8_bar); /* 0x4b0 */
+ reg_32(hw_apbh_ch8_sema); /* 0x4c0 */
+ reg_32(hw_apbh_ch8_debug1); /* 0x4d0 */
+ reg_32(hw_apbh_ch8_debug2); /* 0x4e0 */
+ reg_32(hw_apbh_ch9_curcmdar); /* 0x4f0 */
+ reg_32(hw_apbh_ch9_nxtcmdar); /* 0x500 */
+ reg_32(hw_apbh_ch9_cmd); /* 0x510 */
+ reg_32(hw_apbh_ch9_bar); /* 0x520 */
+ reg_32(hw_apbh_ch9_sema); /* 0x530 */
+ reg_32(hw_apbh_ch9_debug1); /* 0x540 */
+ reg_32(hw_apbh_ch9_debug2); /* 0x550 */
+ reg_32(hw_apbh_ch10_curcmdar); /* 0x560 */
+ reg_32(hw_apbh_ch10_nxtcmdar); /* 0x570 */
+ reg_32(hw_apbh_ch10_cmd); /* 0x580 */
+ reg_32(hw_apbh_ch10_bar); /* 0x590 */
+ reg_32(hw_apbh_ch10_sema); /* 0x5a0 */
+ reg_32(hw_apbh_ch10_debug1); /* 0x5b0 */
+ reg_32(hw_apbh_ch10_debug2); /* 0x5c0 */
+ reg_32(hw_apbh_ch11_curcmdar); /* 0x5d0 */
+ reg_32(hw_apbh_ch11_nxtcmdar); /* 0x5e0 */
+ reg_32(hw_apbh_ch11_cmd); /* 0x5f0 */
+ reg_32(hw_apbh_ch11_bar); /* 0x600 */
+ reg_32(hw_apbh_ch11_sema); /* 0x610 */
+ reg_32(hw_apbh_ch11_debug1); /* 0x620 */
+ reg_32(hw_apbh_ch11_debug2); /* 0x630 */
+ reg_32(hw_apbh_ch12_curcmdar); /* 0x640 */
+ reg_32(hw_apbh_ch12_nxtcmdar); /* 0x650 */
+ reg_32(hw_apbh_ch12_cmd); /* 0x660 */
+ reg_32(hw_apbh_ch12_bar); /* 0x670 */
+ reg_32(hw_apbh_ch12_sema); /* 0x680 */
+ reg_32(hw_apbh_ch12_debug1); /* 0x690 */
+ reg_32(hw_apbh_ch12_debug2); /* 0x6a0 */
+ reg_32(hw_apbh_ch13_curcmdar); /* 0x6b0 */
+ reg_32(hw_apbh_ch13_nxtcmdar); /* 0x6c0 */
+ reg_32(hw_apbh_ch13_cmd); /* 0x6d0 */
+ reg_32(hw_apbh_ch13_bar); /* 0x6e0 */
+ reg_32(hw_apbh_ch13_sema); /* 0x6f0 */
+ reg_32(hw_apbh_ch13_debug1); /* 0x700 */
+ reg_32(hw_apbh_ch13_debug2); /* 0x710 */
+ reg_32(hw_apbh_ch14_curcmdar); /* 0x720 */
+ reg_32(hw_apbh_ch14_nxtcmdar); /* 0x730 */
+ reg_32(hw_apbh_ch14_cmd); /* 0x740 */
+ reg_32(hw_apbh_ch14_bar); /* 0x750 */
+ reg_32(hw_apbh_ch14_sema); /* 0x760 */
+ reg_32(hw_apbh_ch14_debug1); /* 0x770 */
+ reg_32(hw_apbh_ch14_debug2); /* 0x780 */
+ reg_32(hw_apbh_ch15_curcmdar); /* 0x790 */
+ reg_32(hw_apbh_ch15_nxtcmdar); /* 0x7a0 */
+ reg_32(hw_apbh_ch15_cmd); /* 0x7b0 */
+ reg_32(hw_apbh_ch15_bar); /* 0x7c0 */
+ reg_32(hw_apbh_ch15_sema); /* 0x7d0 */
+ reg_32(hw_apbh_ch15_debug1); /* 0x7e0 */
+ reg_32(hw_apbh_ch15_debug2); /* 0x7f0 */
+ };
+ };
+ mx6_reg_32(hw_apbh_version); /* 0x800 */
+};
+#endif
+
+#define APBH_CTRL0_SFTRST (1 << 31)
+#define APBH_CTRL0_CLKGATE (1 << 30)
+#define APBH_CTRL0_AHB_BURST8_EN (1 << 29)
+#define APBH_CTRL0_APB_BURST_EN (1 << 28)
+#define APBH_CTRL0_RSVD0_MASK (0xfff << 16)
+#define APBH_CTRL0_RSVD0_OFFSET 16
+#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff
+#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
+#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
+#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
+
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16)
+#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16
+#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0)
+
+#define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31)
+#define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30)
+#define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29)
+#define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28)
+#define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27)
+#define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26)
+#define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25)
+#define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24)
+#define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23)
+#define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22)
+#define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21)
+#define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20)
+#define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19)
+#define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18)
+#define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17)
+#define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16)
+#define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15)
+#define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14)
+#define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13)
+#define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12)
+#define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11)
+#define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10)
+#define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9)
+#define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8)
+#define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7)
+#define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6)
+#define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5)
+#define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4)
+#define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3)
+#define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2)
+#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1)
+#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0)
+
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16)
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
+
+#define APBH_DEVSEL_CH15_MASK (0x3 << 30)
+#define APBH_DEVSEL_CH15_OFFSET 30
+#define APBH_DEVSEL_CH14_MASK (0x3 << 28)
+#define APBH_DEVSEL_CH14_OFFSET 28
+#define APBH_DEVSEL_CH13_MASK (0x3 << 26)
+#define APBH_DEVSEL_CH13_OFFSET 26
+#define APBH_DEVSEL_CH12_MASK (0x3 << 24)
+#define APBH_DEVSEL_CH12_OFFSET 24
+#define APBH_DEVSEL_CH11_MASK (0x3 << 22)
+#define APBH_DEVSEL_CH11_OFFSET 22
+#define APBH_DEVSEL_CH10_MASK (0x3 << 20)
+#define APBH_DEVSEL_CH10_OFFSET 20
+#define APBH_DEVSEL_CH9_MASK (0x3 << 18)
+#define APBH_DEVSEL_CH9_OFFSET 18
+#define APBH_DEVSEL_CH8_MASK (0x3 << 16)
+#define APBH_DEVSEL_CH8_OFFSET 16
+#define APBH_DEVSEL_CH7_MASK (0x3 << 14)
+#define APBH_DEVSEL_CH7_OFFSET 14
+#define APBH_DEVSEL_CH6_MASK (0x3 << 12)
+#define APBH_DEVSEL_CH6_OFFSET 12
+#define APBH_DEVSEL_CH5_MASK (0x3 << 10)
+#define APBH_DEVSEL_CH5_OFFSET 10
+#define APBH_DEVSEL_CH4_MASK (0x3 << 8)
+#define APBH_DEVSEL_CH4_OFFSET 8
+#define APBH_DEVSEL_CH3_MASK (0x3 << 6)
+#define APBH_DEVSEL_CH3_OFFSET 6
+#define APBH_DEVSEL_CH2_MASK (0x3 << 4)
+#define APBH_DEVSEL_CH2_OFFSET 4
+#define APBH_DEVSEL_CH1_MASK (0x3 << 2)
+#define APBH_DEVSEL_CH1_OFFSET 2
+#define APBH_DEVSEL_CH0_MASK (0x3 << 0)
+#define APBH_DEVSEL_CH0_OFFSET 0
+
+#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30)
+#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30
+#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28)
+#define APBH_DMA_BURST_SIZE_CH14_OFFSET 28
+#define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26)
+#define APBH_DMA_BURST_SIZE_CH13_OFFSET 26
+#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24)
+#define APBH_DMA_BURST_SIZE_CH12_OFFSET 24
+#define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22)
+#define APBH_DMA_BURST_SIZE_CH11_OFFSET 22
+#define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20)
+#define APBH_DMA_BURST_SIZE_CH10_OFFSET 20
+#define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18)
+#define APBH_DMA_BURST_SIZE_CH9_OFFSET 18
+#define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16)
+#define APBH_DMA_BURST_SIZE_CH8_OFFSET 16
+#define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16)
+#define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16)
+#define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16)
+#define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14)
+#define APBH_DMA_BURST_SIZE_CH7_OFFSET 14
+#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12)
+#define APBH_DMA_BURST_SIZE_CH6_OFFSET 12
+#define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10)
+#define APBH_DMA_BURST_SIZE_CH5_OFFSET 10
+#define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8)
+#define APBH_DMA_BURST_SIZE_CH4_OFFSET 8
+#define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6)
+#define APBH_DMA_BURST_SIZE_CH3_OFFSET 6
+#define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6)
+#define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6)
+#define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6)
+
+#define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4)
+#define APBH_DMA_BURST_SIZE_CH2_OFFSET 4
+#define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4)
+#define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4)
+#define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4)
+#define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2)
+#define APBH_DMA_BURST_SIZE_CH1_OFFSET 2
+#define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2)
+#define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2)
+#define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2)
+
+#define APBH_DMA_BURST_SIZE_CH0_MASK 0x3
+#define APBH_DMA_BURST_SIZE_CH0_OFFSET 0
+#define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0
+#define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1
+#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2
+
+#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0)
+
+#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff
+#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0
+
+#define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff
+#define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0
+
+#define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16)
+#define APBH_CHn_CMD_XFER_COUNT_OFFSET 16
+#define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12)
+#define APBH_CHn_CMD_CMDWORDS_OFFSET 12
+#define APBH_CHn_CMD_HALTONTERMINATE (1 << 8)
+#define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7)
+#define APBH_CHn_CMD_SEMAPHORE (1 << 6)
+#define APBH_CHn_CMD_NANDWAIT4READY (1 << 5)
+#define APBH_CHn_CMD_NANDLOCK (1 << 4)
+#define APBH_CHn_CMD_IRQONCMPLT (1 << 3)
+#define APBH_CHn_CMD_CHAIN (1 << 2)
+#define APBH_CHn_CMD_COMMAND_MASK 0x3
+#define APBH_CHn_CMD_COMMAND_OFFSET 0
+#define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0
+#define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1
+#define APBH_CHn_CMD_COMMAND_DMA_READ 0x2
+#define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3
+
+#define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff
+#define APBH_CHn_BAR_ADDRESS_OFFSET 0
+
+#define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24)
+#define APBH_CHn_SEMA_RSVD2_OFFSET 24
+#define APBH_CHn_SEMA_PHORE_MASK (0xff << 16)
+#define APBH_CHn_SEMA_PHORE_OFFSET 16
+#define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8)
+#define APBH_CHn_SEMA_RSVD1_OFFSET 8
+#define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0)
+#define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0
+
+#define APBH_CHn_DEBUG1_REQ (1 << 31)
+#define APBH_CHn_DEBUG1_BURST (1 << 30)
+#define APBH_CHn_DEBUG1_KICK (1 << 29)
+#define APBH_CHn_DEBUG1_END (1 << 28)
+#define APBH_CHn_DEBUG1_SENSE (1 << 27)
+#define APBH_CHn_DEBUG1_READY (1 << 26)
+#define APBH_CHn_DEBUG1_LOCK (1 << 25)
+#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24)
+#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23)
+#define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22)
+#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21)
+#define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20)
+#define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5)
+#define APBH_CHn_DEBUG1_RSVD1_OFFSET 5
+#define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f
+#define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0
+#define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00
+#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01
+#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02
+#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03
+#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04
+#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05
+#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06
+#define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07
+#define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08
+#define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09
+#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c
+#define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d
+#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e
+#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f
+#define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14
+#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15
+#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c
+#define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d
+#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e
+#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f
+
+#define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16)
+#define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16
+#define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff
+#define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0
+
+#define APBH_VERSION_MAJOR_MASK (0xff << 24)
+#define APBH_VERSION_MAJOR_OFFSET 24
+#define APBH_VERSION_MINOR_MASK (0xff << 16)
+#define APBH_VERSION_MINOR_OFFSET 16
+#define APBH_VERSION_STEP_MASK 0xffff
+#define APBH_VERSION_STEP_OFFSET 0
+
+#endif /* __REGS_APBH_H__ */
--- /dev/null
+/*
+ * Freescale i.MX6 BCH Register Definitions
+ *
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on: mx28/regs-bch.h
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX6_REGS_BCH_H__
+#define __MX6_REGS_BCH_H__
+
+//#include <asm/arch/regs-common.h>
+
+#define GPMI_BASE_ADDRESS 0x00112000
+#define BCH_BASE_ADDRESS 0x00114000
+
+#ifndef __ASSEMBLY__
+struct bch_regs {
+ mx6_reg_32(hw_bch_ctrl); /* 0x000 */
+ mx6_reg_32(hw_bch_status0); /* 0x010 */
+ mx6_reg_32(hw_bch_mode); /* 0x020 */
+ reg_32(hw_bch_encodeptr); /* 0x030 */
+ reg_32(hw_bch_dataptr); /* 0x040 */
+ reg_32(hw_bch_metaptr); /* 0x050 */
+ reg_32(reserved); /* 0x060 */
+ mx6_reg_32(hw_bch_layoutselect); /* 0x070 */
+ reg_32(hw_bch_flash0layout0); /* 0x080 */
+ reg_32(hw_bch_flash0layout1); /* 0x090 */
+ reg_32(hw_bch_flash1layout0); /* 0x0a0 */
+ reg_32(hw_bch_flash1layout1); /* 0x0b0 */
+ reg_32(hw_bch_flash2layout0); /* 0x0c0 */
+ reg_32(hw_bch_flash2layout1); /* 0x0d0 */
+ reg_32(hw_bch_flash3layout0); /* 0x0e0 */
+ reg_32(hw_bch_flash3layout1); /* 0x0f0 */
+ reg_32(hw_bch_debug0); /* 0x100 */
+ reg_32(hw_bch_dbgkesread); /* 0x110 */
+ reg_32(hw_bch_dbgcsferead); /* 0x120 */
+ reg_32(hw_bch_dbgsyndegread); /* 0x130 */
+ reg_32(hw_bch_dbgahbmread); /* 0x140 */
+ reg_32(hw_bch_blockname); /* 0x150 */
+ reg_32(hw_bch_version); /* 0x160 */
+};
+#endif
+
+#define BCH_CTRL_SFTRST (1 << 31)
+#define BCH_CTRL_CLKGATE (1 << 30)
+#define BCH_CTRL_DEBUGSYNDROME (1 << 22)
+#define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18)
+#define BCH_CTRL_M2M_LAYOUT_OFFSET 18
+#define BCH_CTRL_M2M_ENCODE (1 << 17)
+#define BCH_CTRL_M2M_ENABLE (1 << 16)
+#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10)
+#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8)
+#define BCH_CTRL_BM_ERROR_IRQ (1 << 3)
+#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2)
+#define BCH_CTRL_COMPLETE_IRQ (1 << 0)
+
+#define BCH_STATUS0_HANDLE_MASK (0xfff << 20)
+#define BCH_STATUS0_HANDLE_OFFSET 20
+#define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16)
+#define BCH_STATUS0_COMPLETED_CE_OFFSET 16
+#define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8)
+#define BCH_STATUS0_STATUS_BLK0_OFFSET 8
+#define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8)
+#define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8)
+#define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8)
+#define BCH_STATUS0_ALLONES (1 << 4)
+#define BCH_STATUS0_CORRECTED (1 << 3)
+#define BCH_STATUS0_UNCORRECTABLE (1 << 2)
+
+#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff
+#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0
+
+#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff
+#define BCH_ENCODEPTR_ADDR_OFFSET 0
+
+#define BCH_DATAPTR_ADDR_MASK 0xffffffff
+#define BCH_DATAPTR_ADDR_OFFSET 0
+
+#define BCH_METAPTR_ADDR_MASK 0xffffffff
+#define BCH_METAPTR_ADDR_OFFSET 0
+
+#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS15_SELECT_OFFSET)
+#define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30
+#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS14_SELECT_OFFSET)
+#define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28
+#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS13_SELECT_OFFSET)
+#define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26
+#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS12_SELECT_OFFSET)
+#define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24
+#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS11_SELECT_OFFSET)
+#define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22
+#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS10_SELECT_OFFSET)
+#define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20
+#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS9_SELECT_OFFSET)
+#define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18
+#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS8_SELECT_OFFSET)
+#define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16
+#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS7_SELECT_OFFSET)
+#define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14
+#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS6_SELECT_OFFSET)
+#define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12
+#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS5_SELECT_OFFSET)
+#define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10
+#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS4_SELECT_OFFSET)
+#define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8
+#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS3_SELECT_OFFSET)
+#define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6
+#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS2_SELECT_OFFSET)
+#define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4
+#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS1_SELECT_OFFSET)
+#define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2
+#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << BCH_LAYOUTSELECT_CS0_SELECT_OFFSET)
+#define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0
+
+#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET)
+#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
+#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << BCH_FLASHLAYOUT0_META_SIZE_OFFSET)
+#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
+#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
+#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << BCH_FLASHLAYOUT0_ECC0_OFFSET)
+#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10)
+#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0x3ff
+#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0
+
+#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET)
+#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
+#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
+#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << BCH_FLASHLAYOUT1_ECCN_OFFSET)
+#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10)
+#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0x3ff
+#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0
+
+#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27)
+#define BCH_DEBUG0_RSVD1_OFFSET 27
+#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26)
+#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25)
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16)
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16)
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16)
+#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15)
+#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14)
+#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13)
+#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12)
+#define BCH_DEBUG0_KES_STANDALONE (1 << 11)
+#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10)
+#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9)
+#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8)
+#define BCH_DEBUG0_RSVD0_MASK (0x3 << 6)
+#define BCH_DEBUG0_RSVD0_OFFSET 6
+#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f
+#define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0
+
+#define BCH_DBGKESREAD_VALUES_MASK 0xffffffff
+#define BCH_DBGKESREAD_VALUES_OFFSET 0
+
+#define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff
+#define BCH_DBGCSFEREAD_VALUES_OFFSET 0
+
+#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff
+#define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0
+
+#define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff
+#define BCH_DBGAHBMREAD_VALUES_OFFSET 0
+
+#define BCH_BLOCKNAME_NAME_MASK 0xffffffff
+#define BCH_BLOCKNAME_NAME_OFFSET 0
+
+#define BCH_VERSION_MAJOR_MASK (0xff << 24)
+#define BCH_VERSION_MAJOR_OFFSET 24
+#define BCH_VERSION_MINOR_MASK (0xff << 16)
+#define BCH_VERSION_MINOR_OFFSET 16
+#define BCH_VERSION_STEP_MASK 0xffff
+#define BCH_VERSION_STEP_OFFSET 0
+
+#endif /* __MX6_REGS_BCH_H__ */
--- /dev/null
+/*
+ * Freescale i.MX6Q GPMI Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX6Q_REGS_GPMI_H__
+#define __MX6Q_REGS_GPMI_H__
+
+#define MXS_GPMI_BASE 0x00112000
+
+#ifndef __ASSEMBLY__
+struct gpmi_regs {
+ mx6_reg_32(hw_gpmi_ctrl0); /* 0x000 */
+ reg_32(hw_gpmi_compare); /* 0x010 */
+ mx6_reg_32(hw_gpmi_eccctrl); /* 0x020 */
+ reg_32(hw_gpmi_ecccount); /* 0x030 */
+ reg_32(hw_gpmi_payload); /* 0x040 */
+ reg_32(hw_gpmi_auxiliary); /* 0x050 */
+ mx6_reg_32(hw_gpmi_ctrl1); /* 0x060 */
+ reg_32(hw_gpmi_timing0); /* 0x070 */
+ reg_32(hw_gpmi_timing1); /* 0x080 */
+ reg_32(hw_gpmi_timing2); /* 0x090 */
+ reg_32(hw_gpmi_data); /* 0x0a0 */
+ reg_32(hw_gpmi_stat); /* 0x0b0 */
+ reg_32(hw_gpmi_debug); /* 0x0c0 */
+ reg_32(hw_gpmi_version); /* 0x0d0 */
+ reg_32(hw_gpmi_debug2); /* 0x0e0 */
+ reg_32(hw_gpmi_debug3); /* 0x0f0 */
+ reg_32(hw_gpmi_rd_ddr_dll_ctrl); /* 0x100 */
+ reg_32(hw_gpmi_wr_ddr_dll_ctrl); /* 0x110 */
+ reg_32(hw_gpmi_rd_ddr_dll_sts); /* 0x120 */
+ reg_32(hw_gpmi_wr_ddr_dll_sts); /* 0x130 */
+
+};
+#endif
+
+#define GPMI_CTRL0_SFTRST (1 << 31)
+#define GPMI_CTRL0_CLKGATE (1 << 30)
+#define GPMI_CTRL0_RUN (1 << 29)
+#define GPMI_CTRL0_DEV_IRQ_EN (1 << 28)
+#define GPMI_CTRL0_LOCK_CS (1 << 27)
+#define GPMI_CTRL0_UDMA (1 << 26)
+#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24)
+#define GPMI_CTRL0_COMMAND_MODE_OFFSET 24
+#define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24)
+#define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24)
+#define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24)
+#define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24)
+#define GPMI_CTRL0_WORD_LENGTH (1 << 23)
+#define GPMI_CTRL0_CS_MASK (0x7 << 20)
+#define GPMI_CTRL0_CS_OFFSET 20
+#define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17)
+#define GPMI_CTRL0_ADDRESS_OFFSET 17
+#define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17)
+#define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17)
+#define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17)
+#define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16)
+#define GPMI_CTRL0_XFER_COUNT_MASK 0xffff
+#define GPMI_CTRL0_XFER_COUNT_OFFSET 0
+
+#define GPMI_COMPARE_MASK_MASK (0xffff << 16)
+#define GPMI_COMPARE_MASK_OFFSET 16
+#define GPMI_COMPARE_REFERENCE_MASK 0xffff
+#define GPMI_COMPARE_REFERENCE_OFFSET 0
+
+#define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16)
+#define GPMI_ECCCTRL_HANDLE_OFFSET 16
+#define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13)
+#define GPMI_ECCCTRL_ECC_CMD_OFFSET 13
+#define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13)
+#define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13)
+#define GPMI_ECCCTRL_ENABLE_ECC (1 << 12)
+#define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff
+#define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0
+#define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100
+#define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff
+
+#define GPMI_ECCCOUNT_COUNT_MASK 0xffff
+#define GPMI_ECCCOUNT_COUNT_OFFSET 0
+
+#define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2)
+#define GPMI_PAYLOAD_ADDRESS_OFFSET 2
+
+#define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2)
+#define GPMI_AUXILIARY_ADDRESS_OFFSET 2
+
+#define GPMI_CTRL1_DECOUPLE_CS (1 << 24)
+#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22)
+#define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22
+#define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20)
+#define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19)
+#define GPMI_CTRL1_BCH_MODE (1 << 18)
+#define GPMI_CTRL1_DLL_ENABLE (1 << 17)
+#define GPMI_CTRL1_HALF_PERIOD (1 << 16)
+#define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12)
+#define GPMI_CTRL1_RDN_DELAY_OFFSET 12
+#define GPMI_CTRL1_DMA2ECC_MODE (1 << 11)
+#define GPMI_CTRL1_DEV_IRQ (1 << 10)
+#define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9)
+#define GPMI_CTRL1_BURST_EN (1 << 8)
+#define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7)
+#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4)
+#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4
+#define GPMI_CTRL1_DEV_RESET (1 << 3)
+#define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2)
+#define GPMI_CTRL1_CAMERA_MODE (1 << 1)
+#define GPMI_CTRL1_GPMI_MODE (1 << 0)
+
+#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16)
+#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16
+#define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8)
+#define GPMI_TIMING0_DATA_HOLD_OFFSET 8
+#define GPMI_TIMING0_DATA_SETUP_MASK 0xff
+#define GPMI_TIMING0_DATA_SETUP_OFFSET 0
+
+#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16)
+#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16
+
+#define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24)
+#define GPMI_TIMING2_UDMA_TRP_OFFSET 24
+#define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16)
+#define GPMI_TIMING2_UDMA_ENV_OFFSET 16
+#define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8)
+#define GPMI_TIMING2_UDMA_HOLD_OFFSET 8
+#define GPMI_TIMING2_UDMA_SETUP_MASK 0xff
+#define GPMI_TIMING2_UDMA_SETUP_OFFSET 0
+
+#define GPMI_DATA_DATA_MASK 0xffffffff
+#define GPMI_DATA_DATA_OFFSET 0
+
+#define GPMI_STAT_READY_BUSY_MASK (0xff << 24)
+#define GPMI_STAT_READY_BUSY_OFFSET 24
+#define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16)
+#define GPMI_STAT_RDY_TIMEOUT_OFFSET 16
+#define GPMI_STAT_DEV7_ERROR (1 << 15)
+#define GPMI_STAT_DEV6_ERROR (1 << 14)
+#define GPMI_STAT_DEV5_ERROR (1 << 13)
+#define GPMI_STAT_DEV4_ERROR (1 << 12)
+#define GPMI_STAT_DEV3_ERROR (1 << 11)
+#define GPMI_STAT_DEV2_ERROR (1 << 10)
+#define GPMI_STAT_DEV1_ERROR (1 << 9)
+#define GPMI_STAT_DEV0_ERROR (1 << 8)
+#define GPMI_STAT_ATA_IRQ (1 << 4)
+#define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3)
+#define GPMI_STAT_FIFO_EMPTY (1 << 2)
+#define GPMI_STAT_FIFO_FULL (1 << 1)
+#define GPMI_STAT_PRESENT (1 << 0)
+
+#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24)
+#define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24
+#define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16)
+#define GPMI_DEBUG_DMA_SENSE_OFFSET 16
+#define GPMI_DEBUG_DMAREQ_MASK (0xff << 8)
+#define GPMI_DEBUG_DMAREQ_OFFSET 8
+#define GPMI_DEBUG_CMD_END_MASK 0xff
+#define GPMI_DEBUG_CMD_END_OFFSET 0
+
+#define GPMI_VERSION_MAJOR_MASK (0xff << 24)
+#define GPMI_VERSION_MAJOR_OFFSET 24
+#define GPMI_VERSION_MINOR_MASK (0xff << 16)
+#define GPMI_VERSION_MINOR_OFFSET 16
+#define GPMI_VERSION_STEP_MASK 0xffff
+#define GPMI_VERSION_STEP_OFFSET 0
+
+#define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24)
+#define GPMI_DEBUG2_UDMA_STATE_OFFSET 24
+#define GPMI_DEBUG2_BUSY (1 << 23)
+#define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20)
+#define GPMI_DEBUG2_PIN_STATE_OFFSET 20
+#define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20)
+#define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20)
+#define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16)
+#define GPMI_DEBUG2_MAIN_STATE_OFFSET 16
+#define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16)
+#define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16)
+#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12)
+#define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12
+#define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11)
+#define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10)
+#define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9)
+#define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8)
+#define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7)
+#define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6)
+#define GPMI_DEBUG2_RDN_TAP_MASK 0x3f
+#define GPMI_DEBUG2_RDN_TAP_OFFSET 0
+
+#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16)
+#define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16
+#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff
+#define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0
+
+#endif /* __MX6Q_REGS_GPMI_H__ */
--- /dev/null
+/*
+ * Freescale i.MX6 OCOTP Register Definitions
+ *
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX6_REGS_OCOTP_H__
+#define __MX6_REGS_OCOTP_H__
+
+#ifndef __ASSEMBLY__
+#define mx6_ocotp_reg_32(r) mx6_reg_32(hw_ocotp_##r)
+#define ocotp_reg_32(r) reg_32(hw_ocotp_##r)
+
+struct mx6_ocotp_regs {
+ mx6_ocotp_reg_32(ctrl); /* 0x000 */
+ ocotp_reg_32(timing); /* 0x010 */
+ ocotp_reg_32(data); /* 0x020 */
+ ocotp_reg_32(read_ctrl); /* 0x030 */
+ ocotp_reg_32(read_fuse_data); /* 0x040 */
+ ocotp_reg_32(sw_sticky); /* 0x050 */
+ mx6_ocotp_reg_32(scs); /* 0x060 */
+ reg_32(rsrvd1); /* 0x070 */
+ reg_32(rsrvd2); /* 0x080 */
+ ocotp_reg_32(version); /* 0x090 */
+
+ reg_32(rsrvd3[54]); /* 0x0a0 - 0x3ff */
+
+ /* bank 0 */
+ ocotp_reg_32(lock); /* 0x400 */
+ ocotp_reg_32(cfg0); /* 0x410 */
+ ocotp_reg_32(cfg1); /* 0x420 */
+ ocotp_reg_32(cfg2); /* 0x430 */
+ ocotp_reg_32(cfg3); /* 0x440 */
+ ocotp_reg_32(cfg4); /* 0x450 */
+ ocotp_reg_32(cfg5); /* 0x460 */
+ ocotp_reg_32(cfg6); /* 0x470 */
+
+ /* bank 1 */
+ ocotp_reg_32(mem0); /* 0x480 */
+ ocotp_reg_32(mem1); /* 0x490 */
+ ocotp_reg_32(mem2); /* 0x4a0 */
+ ocotp_reg_32(mem3); /* 0x4b0 */
+ ocotp_reg_32(mem4); /* 0x4c0 */
+ ocotp_reg_32(ana0); /* 0x4d0 */
+ ocotp_reg_32(ana1); /* 0x4e0 */
+ ocotp_reg_32(ana2); /* 0x4f0 */
+
+ /* bank 2 */
+ reg_32(rsrvd4[8]); /* 0x500 - 0x57f */
+
+ /* bank 3 */
+ ocotp_reg_32(srk0); /* 0x580 */
+ ocotp_reg_32(srk1); /* 0x590 */
+ ocotp_reg_32(srk2); /* 0x5a0 */
+ ocotp_reg_32(srk3); /* 0x5b0 */
+ ocotp_reg_32(srk4); /* 0x5c0 */
+ ocotp_reg_32(srk5); /* 0x5d0 */
+ ocotp_reg_32(srk6); /* 0x5e0 */
+ ocotp_reg_32(srk7); /* 0x5f0 */
+
+ /* bank 4 */
+ ocotp_reg_32(hsjc_resp0); /* 0x600 */
+ ocotp_reg_32(hsjc_resp1); /* 0x610 */
+ ocotp_reg_32(mac0); /* 0x620 */
+ ocotp_reg_32(mac1); /* 0x630 */
+ reg_32(rsrvd5[2]); /* 0x640 - 0x65f */
+ ocotp_reg_32(gp1); /* 0x660 */
+ ocotp_reg_32(gp2); /* 0x670 */
+
+ /* bank 5 */
+ reg_32(rsrvd6[5]); /* 0x680 - 0x6cf */
+ ocotp_reg_32(misc_conf); /* 0x6d0 */
+ ocotp_reg_32(field_return); /* 0x6e0 */
+ ocotp_reg_32(srk_revoke); /* 0x6f0 */
+};
+
+#endif
+
+#define OCOTP_CTRL_BUSY (1 << 8)
+#define OCOTP_CTRL_ERROR (1 << 9)
+#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 10)
+
+#define OCOTP_RD_CTRL_READ_FUSE (1 << 0)
+
+#define OCOTP_VERSION_MAJOR_MASK (0xff << 24)
+#define OCOTP_VERSION_MAJOR_OFFSET 24
+#define OCOTP_VERSION_MINOR_MASK (0xff << 16)
+#define OCOTP_VERSION_MINOR_OFFSET 16
+#define OCOTP_VERSION_STEP_MASK 0xffff
+#define OCOTP_VERSION_STEP_OFFSET 0
+
+#endif /* __MX6_REGS_OCOTP_H__ */
const char *get_imx_type(u32 imxtype);
unsigned imx_ddr_size(void);
-void set_vddsoc(u32 mv);
+
+struct mx6_register_32;
+
+int mxs_reset_block(struct mx6_register_32 *reg);
+int mxs_wait_mask_set(struct mx6_register_32 *reg,
+ uint32_t mask,
+ unsigned long timeout);
+int mxs_wait_mask_clr(struct mx6_register_32 *reg,
+ uint32_t mask,
+ unsigned long timeout);
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
/*
* Initializes on-chip ethernet controllers.
--- /dev/null
+/*
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * LCD driver for i.MX28
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MXSFB_H
+#define __MXSFB_H
+
+#include <linux/list.h>
+#include <linux/fb.h>
+
+#define fourcc(a, b, c, d) (((__u32)(a) << 0) | \
+ ((__u32)(b) << 8) | \
+ ((__u32)(c) << 16) | \
+ ((__u32)(d) << 24))
+
+/*
+ * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
+ * the same used by V4L2 API.
+ */
+
+#define PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*< 8 RGB-3-3-2 */
+#define PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*< 16 RGB-5-5-5 */
+#define PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*< 1 6 RGB-5-6-5 */
+#define PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*< 18 RGB-6-6-6 */
+#define PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*< 18 BGR-6-6-6 */
+#define PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*< 24 BGR-8-8-8 */
+#define PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*< 24 RGB-8-8-8 */
+
+#define PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*< 8 Greyscale */
+
+#define FB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6)
+#define FB_SYNC_DOTCLK_FALLING_ACT (1 << 7) /* falling/negative edge sampling */
+
+extern int mxsfb_init(struct fb_videomode *mode, uint32_t pixfmt, int bpp);
+extern void mxsfb_disable(void);
+
+#endif /* __MXSFB_H */
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mxs_apbh_regs {
+struct apbh_regs {
mxs_reg_32(hw_apbh_ctrl0)
mxs_reg_32(hw_apbh_ctrl1)
mxs_reg_32(hw_apbh_ctrl2)
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mxs_bch_regs {
+struct bch_regs {
mxs_reg_32(hw_bch_ctrl)
mxs_reg_32(hw_bch_status0)
mxs_reg_32(hw_bch_mode)
};
#endif
+#define BCH_BASE_ADDRESS MXS_BCH_BASE
+
#define BCH_CTRL_SFTRST (1 << 31)
#define BCH_CTRL_CLKGATE (1 << 30)
#define BCH_CTRL_DEBUGSYNDROME (1 << 22)
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mxs_gpmi_regs {
+struct gpmi_regs {
mxs_reg_32(hw_gpmi_ctrl0)
mxs_reg_32(hw_gpmi_compare)
mxs_reg_32(hw_gpmi_eccctrl)
};
#endif
+#define GPMI_BASE_ADDRESS MXS_GPMI_BASE
+
#define GPMI_CTRL0_SFTRST (1 << 31)
#define GPMI_CTRL0_CLKGATE (1 << 30)
#define GPMI_CTRL0_RUN (1 << 29)
#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20)
#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16)
#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16
+#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(n) (((n) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET) & \
+ LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15)
#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14)
#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16)
#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16
+#define LCDIF_TRANSFER_COUNT_V_COUNT(n) (((n) << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) & \
+ LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0)
#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0
+#define LCDIF_TRANSFER_COUNT_H_COUNT(n) (((n) << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET) & \
+ LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff
#define LCDIF_CUR_BUF_ADDR_OFFSET 0
#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18)
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(n) (((n) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET) & \
+ LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
+#define LCDIF_VDCTRL1_VSYNC_PERIOD(n) (((n) << LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET) & \
+ LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(n) (((n) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) & \
+ LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
+#define LCDIF_VDCTRL2_HSYNC_PERIOD(n) (((n) << LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET) & \
+ LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28)
#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16)
#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16
+#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(n) (((n) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) & \
+ LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0)
#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0
+#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(n) (((n) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET) & \
+ LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29)
#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29
+#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(n) (((n) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) & \
+ LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
+#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(n) (((n) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET) & \
+ LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
#endif /* __MX28_REGS_LCDIF_H__ */
#ifndef __SYS_PROTO_H__
#define __SYS_PROTO_H__
+struct mxs_register_32;
+
int mxs_reset_block(struct mxs_register_32 *reg);
int mxs_wait_mask_set(struct mxs_register_32 *reg,
uint32_t mask,
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int));
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+
#ifdef CONFIG_SPL_BUILD
#include <asm/arch/iomux-mx28.h>
void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _GP_PADCTRL_H_
+#define _GP_PADCTRL_H_
+
+/* APB_MISC_PP registers */
+struct apb_misc_pp_ctlr {
+ u32 reserved0[2];
+ u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */
+};
+
+/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */
+#define RAM_CODE_SHIFT 4
+#define RAM_CODE_MASK (0xf << RAM_CODE_SHIFT)
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ARCH_EMC_H_
+#define _ARCH_EMC_H_
+
+#include <asm/types.h>
+
+#define TEGRA_EMC_NUM_REGS 46
+
+/* EMC Registers */
+struct emc_ctlr {
+ u32 cfg; /* 0x00: EMC_CFG */
+ u32 reserved0[3]; /* 0x04 ~ 0x0C */
+ u32 adr_cfg; /* 0x10: EMC_ADR_CFG */
+ u32 adr_cfg1; /* 0x14: EMC_ADR_CFG_1 */
+ u32 reserved1[2]; /* 0x18 ~ 0x18 */
+ u32 refresh_ctrl; /* 0x20: EMC_REFCTRL */
+ u32 pin; /* 0x24: EMC_PIN */
+ u32 timing_ctrl; /* 0x28: EMC_TIMING_CONTROL */
+ u32 rc; /* 0x2C: EMC_RC */
+ u32 rfc; /* 0x30: EMC_RFC */
+ u32 ras; /* 0x34: EMC_RAS */
+ u32 rp; /* 0x38: EMC_RP */
+ u32 r2w; /* 0x3C: EMC_R2W */
+ u32 w2r; /* 0x40: EMC_W2R */
+ u32 r2p; /* 0x44: EMC_R2P */
+ u32 w2p; /* 0x48: EMC_W2P */
+ u32 rd_rcd; /* 0x4C: EMC_RD_RCD */
+ u32 wd_rcd; /* 0x50: EMC_WD_RCD */
+ u32 rrd; /* 0x54: EMC_RRD */
+ u32 rext; /* 0x58: EMC_REXT */
+ u32 wdv; /* 0x5C: EMC_WDV */
+ u32 quse; /* 0x60: EMC_QUSE */
+ u32 qrst; /* 0x64: EMC_QRST */
+ u32 qsafe; /* 0x68: EMC_QSAFE */
+ u32 rdv; /* 0x6C: EMC_RDV */
+ u32 refresh; /* 0x70: EMC_REFRESH */
+ u32 burst_refresh_num; /* 0x74: EMC_BURST_REFRESH_NUM */
+ u32 pdex2wr; /* 0x78: EMC_PDEX2WR */
+ u32 pdex2rd; /* 0x7c: EMC_PDEX2RD */
+ u32 pchg2pden; /* 0x80: EMC_PCHG2PDEN */
+ u32 act2pden; /* 0x84: EMC_ACT2PDEN */
+ u32 ar2pden; /* 0x88: EMC_AR2PDEN */
+ u32 rw2pden; /* 0x8C: EMC_RW2PDEN */
+ u32 txsr; /* 0x90: EMC_TXSR */
+ u32 tcke; /* 0x94: EMC_TCKE */
+ u32 tfaw; /* 0x98: EMC_TFAW */
+ u32 trpab; /* 0x9C: EMC_TRPAB */
+ u32 tclkstable; /* 0xA0: EMC_TCLKSTABLE */
+ u32 tclkstop; /* 0xA4: EMC_TCLKSTOP */
+ u32 trefbw; /* 0xA8: EMC_TREFBW */
+ u32 quse_extra; /* 0xAC: EMC_QUSE_EXTRA */
+ u32 odt_write; /* 0xB0: EMC_ODT_WRITE */
+ u32 odt_read; /* 0xB4: EMC_ODT_READ */
+ u32 reserved2[5]; /* 0xB8 ~ 0xC8 */
+ u32 mrs; /* 0xCC: EMC_MRS */
+ u32 emrs; /* 0xD0: EMC_EMRS */
+ u32 ref; /* 0xD4: EMC_REF */
+ u32 pre; /* 0xD8: EMC_PRE */
+ u32 nop; /* 0xDC: EMC_NOP */
+ u32 self_ref; /* 0xE0: EMC_SELF_REF */
+ u32 dpd; /* 0xE4: EMC_DPD */
+ u32 mrw; /* 0xE8: EMC_MRW */
+ u32 mrr; /* 0xEC: EMC_MRR */
+ u32 reserved3; /* 0xF0: */
+ u32 fbio_cfg1; /* 0xF4: EMC_FBIO_CFG1 */
+ u32 fbio_dqsib_dly; /* 0xF8: EMC_FBIO_DQSIB_DLY */
+ u32 fbio_dqsib_dly_msb; /* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */
+ u32 fbio_spare; /* 0x100: SBIO_SPARE */
+ /* There are more registers ... */
+};
+
+/**
+ * Set up the EMC for the given rate. The timing parameters are retrieved
+ * from the device tree "nvidia,tegra20-emc" node and its
+ * "nvidia,tegra20-emc-table" sub-nodes.
+ *
+ * @param blob Device tree blob
+ * @param rate Clock speed of memory controller in Hz (=2x memory bus rate)
+ * @return 0 if ok, else -ve error code (look in emc.c to decode it)
+ */
+int tegra_set_emc(const void *blob, unsigned rate);
+
+/**
+ * Get a pointer to the EMC controller from the device tree.
+ *
+ * @param blob Device tree blob
+ * @return pointer to EMC controller
+ */
+struct emc_ctlr *emc_get_controller(const void *blob);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010, 2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _FLOW_H_
+#define _FLOW_H_
+
+struct flow_ctlr {
+ u32 halt_cpu_events;
+ u32 halt_cop_events;
+ u32 cpu_csr;
+ u32 cop_csr;
+ u32 halt_cpu1_events;
+ u32 cpu1_csr;
+};
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _FUSE_H_
+#define _FUSE_H_
+
+/* FUSE registers */
+struct fuse_regs {
+ u32 reserved0[64]; /* 0x00 - 0xFC: */
+ u32 production_mode; /* 0x100: FUSE_PRODUCTION_MODE */
+ u32 reserved1[3]; /* 0x104 - 0x10c: */
+ u32 sku_info; /* 0x110 */
+ u32 reserved2[13]; /* 0x114 - 0x144: */
+ u32 fa; /* 0x148: FUSE_FA */
+ u32 reserved3[21]; /* 0x14C - 0x19C: */
+ u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */
+};
+
+#endif /* ifndef _FUSE_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _GP_PADCTRL_H_
+#define _GP_PADCTRL_H_
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+ u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
+ u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
+ u32 reserved0[22]; /* 0x08 - 0x5C: */
+ u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
+ u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+ u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+ u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
+ u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+ u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+ u32 cdevcfg1; /* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */
+ u32 cdevcfg2; /* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */
+ u32 csuscfg; /* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */
+ u32 dap1cfg; /* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */
+ u32 dap2cfg; /* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */
+ u32 dap3cfg; /* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */
+ u32 dap4cfg; /* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */
+ u32 dbgcfg; /* 0x94: APB_MISC_GP_DBGCFGPADCTRL */
+ u32 lcdcfg1; /* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */
+ u32 lcdcfg2; /* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */
+ u32 sdmmc2_cfg; /* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */
+ u32 sdmmc3_cfg; /* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */
+ u32 spicfg; /* 0xA8: APB_MISC_GP_SPICFGPADCTRL */
+ u32 uaacfg; /* 0xAC: APB_MISC_GP_UAACFGPADCTRL */
+ u32 uabcfg; /* 0xB0: APB_MISC_GP_UABCFGPADCTRL */
+ u32 uart2cfg; /* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */
+ u32 uart3cfg; /* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */
+ u32 vicfg1; /* 0xBC: APB_MISC_GP_VICFG1PADCTRL */
+ u32 vicfg2; /* 0xC0: APB_MISC_GP_VICFG2PADCTRL */
+ u32 xm2cfga; /* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */
+ u32 xm2cfgc; /* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */
+ u32 xm2cfgd; /* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */
+ u32 xm2clkcfg; /* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */
+ u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */
+};
+
+/* bit fields definitions for APB_MISC_GP_HIDREV register */
+#define HIDREV_CHIPID_SHIFT 8
+#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
+#define HIDREV_MAJORPREV_SHIFT 4
+#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
+
+/* CHIPID field returned from APB_MISC_GP_HIDREV register */
+#define CHIPID_TEGRA2 0x20
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ARCH_PMU_H_
+#define _ARCH_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif /* _ARCH_PMU_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2010, 2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SDRAM_PARAM_H_
+#define _SDRAM_PARAM_H_
+
+/*
+ * Defines the number of 32-bit words provided in each set of SDRAM parameters
+ * for arbitration configuration data.
+ */
+#define BCT_SDRAM_ARB_CONFIG_WORDS 27
+
+enum memory_type {
+ MEMORY_TYPE_NONE = 0,
+ MEMORY_TYPE_DDR,
+ MEMORY_TYPE_LPDDR,
+ MEMORY_TYPE_DDR2,
+ MEMORY_TYPE_LPDDR2,
+ MEMORY_TYPE_NUM,
+ MEMORY_TYPE_FORCE32 = 0x7FFFFFFF
+};
+
+/* Defines the SDRAM parameter structure */
+struct sdram_params {
+ enum memory_type memory_type;
+ u32 pllm_charge_pump_setup_control;
+ u32 pllm_loop_filter_setup_control;
+ u32 pllm_input_divider;
+ u32 pllm_feedback_divider;
+ u32 pllm_post_divider;
+ u32 pllm_stable_time;
+ u32 emc_clock_divider;
+ u32 emc_auto_cal_interval;
+ u32 emc_auto_cal_config;
+ u32 emc_auto_cal_wait;
+ u32 emc_pin_program_wait;
+ u32 emc_rc;
+ u32 emc_rfc;
+ u32 emc_ras;
+ u32 emc_rp;
+ u32 emc_r2w;
+ u32 emc_w2r;
+ u32 emc_r2p;
+ u32 emc_w2p;
+ u32 emc_rd_rcd;
+ u32 emc_wr_rcd;
+ u32 emc_rrd;
+ u32 emc_rext;
+ u32 emc_wdv;
+ u32 emc_quse;
+ u32 emc_qrst;
+ u32 emc_qsafe;
+ u32 emc_rdv;
+ u32 emc_refresh;
+ u32 emc_burst_refresh_num;
+ u32 emc_pdex2wr;
+ u32 emc_pdex2rd;
+ u32 emc_pchg2pden;
+ u32 emc_act2pden;
+ u32 emc_ar2pden;
+ u32 emc_rw2pden;
+ u32 emc_txsr;
+ u32 emc_tcke;
+ u32 emc_tfaw;
+ u32 emc_trpab;
+ u32 emc_tclkstable;
+ u32 emc_tclkstop;
+ u32 emc_trefbw;
+ u32 emc_quseextra;
+ u32 emc_fbioc_fg1;
+ u32 emc_fbio_dqsib_dly;
+ u32 emc_fbio_dqsib_dly_msb;
+ u32 emc_fbio_quse_dly;
+ u32 emc_fbio_quse_dly_msb;
+ u32 emc_fbio_cfg5;
+ u32 emc_fbio_cfg6;
+ u32 emc_fbio_spare;
+ u32 emc_mrs;
+ u32 emc_emrs;
+ u32 emc_mrw1;
+ u32 emc_mrw2;
+ u32 emc_mrw3;
+ u32 emc_mrw_reset_command;
+ u32 emc_mrw_reset_init_wait;
+ u32 emc_adr_cfg;
+ u32 emc_adr_cfg1;
+ u32 emc_emem_cfg;
+ u32 emc_low_latency_config;
+ u32 emc_cfg;
+ u32 emc_cfg2;
+ u32 emc_dbg;
+ u32 ahb_arbitration_xbar_ctrl;
+ u32 emc_cfg_dig_dll;
+ u32 emc_dll_xform_dqs;
+ u32 emc_dll_xform_quse;
+ u32 warm_boot_wait;
+ u32 emc_ctt_term_ctrl;
+ u32 emc_odt_write;
+ u32 emc_odt_read;
+ u32 emc_zcal_ref_cnt;
+ u32 emc_zcal_wait_cnt;
+ u32 emc_zcal_mrw_cmd;
+ u32 emc_mrs_reset_dll;
+ u32 emc_mrw_zq_init_dev0;
+ u32 emc_mrw_zq_init_dev1;
+ u32 emc_mrw_zq_init_wait;
+ u32 emc_mrs_reset_dll_wait;
+ u32 emc_emrs_emr2;
+ u32 emc_emrs_emr3;
+ u32 emc_emrs_ddr2_dll_enable;
+ u32 emc_mrs_ddr2_dll_reset;
+ u32 emc_emrs_ddr2_ocd_calib;
+ u32 emc_edr2_wait;
+ u32 emc_cfg_clktrim0;
+ u32 emc_cfg_clktrim1;
+ u32 emc_cfg_clktrim2;
+ u32 pmc_ddr_pwr;
+ u32 apb_misc_gp_xm2cfga_padctrl;
+ u32 apb_misc_gp_xm2cfgc_padctrl;
+ u32 apb_misc_gp_xm2cfgc_padctrl2;
+ u32 apb_misc_gp_xm2cfgd_padctrl;
+ u32 apb_misc_gp_xm2cfgd_padctrl2;
+ u32 apb_misc_gp_xm2clkcfg_padctrl;
+ u32 apb_misc_gp_xm2comp_padctrl;
+ u32 apb_misc_gp_xm2vttgen_padctrl;
+ u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS];
+};
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010, 2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _WARM_BOOT_H_
+#define _WARM_BOOT_H_
+
+#define STRAP_OPT_A_RAM_CODE_SHIFT 4
+#define STRAP_OPT_A_RAM_CODE_MASK (0xf << STRAP_OPT_A_RAM_CODE_SHIFT)
+
+/* Defines the supported operating modes */
+enum fuse_operating_mode {
+ MODE_PRODUCTION = 3,
+ MODE_UNDEFINED,
+};
+
+/* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */
+enum {
+ HASH_LENGTH = 4
+};
+
+/* Defines the storage for a hash value (128 bits) */
+struct hash {
+ u32 hash[HASH_LENGTH];
+};
+
+/*
+ * Defines the code header information for the boot rom.
+ *
+ * The code immediately follows the code header.
+ *
+ * Note that the code header needs to be 16 bytes aligned to preserve
+ * the alignment of relevant data for hash and decryption computations without
+ * requiring extra copies to temporary memory areas.
+ */
+struct wb_header {
+ u32 length_insecure; /* length of the code header */
+ u32 reserved[3];
+ struct hash hash; /* hash of header+code, starts next field*/
+ struct hash random_aes_block; /* a data block to aid security. */
+ u32 length_secure; /* length of the code header */
+ u32 destination; /* destination address to put the wb code */
+ u32 entry_point; /* execution address of the wb code */
+ u32 code_length; /* length of the code */
+};
+
+/*
+ * The warm boot code needs direct access to these registers since it runs in
+ * SRAM and cannot call other U-Boot code.
+ */
+union osc_ctrl_reg {
+ struct {
+ u32 xoe:1;
+ u32 xobp:1;
+ u32 reserved0:2;
+ u32 xofs:6;
+ u32 reserved1:2;
+ u32 xods:5;
+ u32 reserved2:3;
+ u32 oscfi_spare:8;
+ u32 pll_ref_div:2;
+ u32 osc_freq:2;
+ };
+ u32 word;
+};
+
+union pllx_base_reg {
+ struct {
+ u32 divm:5;
+ u32 reserved0:3;
+ u32 divn:10;
+ u32 reserved1:2;
+ u32 divp:3;
+ u32 reserved2:4;
+ u32 lock:1;
+ u32 reserved3:1;
+ u32 ref_dis:1;
+ u32 enable:1;
+ u32 bypass:1;
+ };
+ u32 word;
+};
+
+union pllx_misc_reg {
+ struct {
+ u32 vcocon:4;
+ u32 lfcon:4;
+ u32 cpcon:4;
+ u32 lock_sel:6;
+ u32 reserved0:1;
+ u32 lock_enable:1;
+ u32 reserved1:1;
+ u32 dccon:1;
+ u32 pts:2;
+ u32 reserved2:6;
+ u32 out1_div_byp:1;
+ u32 out1_inv_clk:1;
+ };
+ u32 word;
+};
+
+/*
+ * TODO: This register is not documented in the TRM yet. We could move this
+ * into the EMC and give it a proper interface, but not while it is
+ * undocumented.
+ */
+union scratch3_reg {
+ struct {
+ u32 pllx_base_divm:5;
+ u32 pllx_base_divn:10;
+ u32 pllx_base_divp:3;
+ u32 pllx_misc_lfcon:4;
+ u32 pllx_misc_cpcon:4;
+ };
+ u32 word;
+};
+
+
+/**
+ * Save warmboot memory settings for a later resume
+ *
+ * @return 0 if ok, -1 on error
+ */
+int warmboot_save_sdram_params(void);
+
+int warmboot_prepare_code(u32 seg_address, u32 seg_length);
+int sign_data_block(u8 *source, u32 length, u8 *signature);
+void wb_start(void); /* Start of WB assembly code */
+void wb_end(void); /* End of WB assembly code */
+
+#endif
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
+#ifdef CONFIG_VIDEO_IPUV3
+ unsigned int ipu_hw_rev;
+#endif
#ifdef CONFIG_AT91FAMILY
/* "static data" needed by at91's clock.c */
unsigned long cpu_clk_rate_hz;
* MA 02110-1301, USA.
*/
-#ifndef __MACH_IOMUX_V3_H__
-#define __MACH_IOMUX_V3_H__
+#ifndef __ASM_ARCH_IOMUX_V3_H__
+#define __ASM_ARCH_IOMUX_V3_H__
/*
* build IOMUX_PAD structure
* PAD_CTRL_OFS: 12..23 (12)
* SEL_INPUT_OFS: 24..35 (12)
* MUX_MODE + SION: 36..40 (5)
- * PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
+ * PAD_CTRL + PAD_CTRL_VALID: 41..58 (18)
* SEL_INP: 59..62 (4)
* reserved: 63 (1)
*/
#define MUX_SEL_INPUT_SHIFT 59
#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
-#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+#define MUX_PAD_CTRL(x) (((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) | \
+ PAD_CTRL_VALID)
#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
sel_input, pad_ctrl) \
#define NO_PAD_CTRL (1 << 17)
#define GPIO_PIN_MASK 0x1f
+#define PAD_CTRL_VALID ((iomux_v3_cfg_t)1 << (MUX_PAD_CTRL_SHIFT + 17))
#define GPIO_PORT_SHIFT 5
#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
#define MUX_CONFIG_SION (0x1 << 4)
+
int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count);
-#endif /* __MACH_IOMUX_V3_H__*/
+#endif /* __ASM_ARCH_IOMUX_V3_H__*/
static inline unsigned int get_cr(void)
{
unsigned int val;
- asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
+ asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
return val;
}
* has the disadvantage that you either get nothing, or everything.
* On PowerPC, you might see "DRAM: " before the system hangs - which
* gives a simple yet clear indication which part of the
- * initialization if failing.
+ * initialization is failing.
*/
static int display_dram_config(void)
{
gd->relocaddr = addr;
gd->start_addr_sp = addr_sp;
gd->reloc_off = addr - _TEXT_BASE;
+
debug("relocation Offset is: %08lx\n", gd->reloc_off);
if (new_fdt) {
memcpy(new_fdt, gd->fdt_blob, fdt_size);
debug("monitor flash len: %08lX\n", monitor_flash_len);
board_init(); /* Setup chipselects */
/*
- * TODO: printing of the clock inforamtion of the board is now
+ * TODO: printing of the clock information of the board is now
* implemented as part of bdinfo command. Currently only support for
* davinci SOC's is added. Remove this check once all the board
* implement this.
void arm_init_before_mmu(void)
__attribute__((weak, alias("__arm_init_before_mmu")));
-static void cp_delay (void)
-{
- volatile int i;
-
- /* copro seems to need some delay between reading and writing */
- for (i = 0; i < 100; i++)
- nop();
- asm volatile("" : : : "memory");
-}
-
void set_section_dcache(int section, enum dcache_option option)
{
u32 *page_table = (u32 *)gd->arch.tlb_addr;
/* to activate the MMU we need to set up virtual memory: use 1M areas */
static inline void mmu_setup(void)
{
+ u32 *page_table = (u32 *)gd->arch.tlb_addr;
int i;
u32 reg;
dram_bank_mmu_setup(i);
}
- /* Copy the page table address to cp15 */
- asm volatile("mcr p15, 0, %0, c2, c0, 0"
- : : "r" (gd->arch.tlb_addr) : "memory");
- /* Set the access control to all-supervisor */
- asm volatile("mcr p15, 0, %0, c3, c0, 0"
- : : "r" (~0));
+ asm volatile(
+ /* Copy the page table address to cp15 */
+ "mcr p15, 0, %0, c2, c0, 0\n"
+ /* Set the access control to all-supervisor */
+ "mcr p15, 0, %1, c3, c0, 0\n"
+ :
+ : "r"(page_table), "r"(~0)
+ );
/* and enable the mmu */
reg = get_cr(); /* get control reg. */
- cp_delay();
set_cr(reg | CR_M);
}
if ((cache_bit == CR_C) && !mmu_enabled())
mmu_setup();
reg = get_cr(); /* get control reg. */
- cp_delay();
set_cr(reg | cache_bit);
}
uint32_t reg;
reg = get_cr();
- cp_delay();
if (cache_bit == CR_C) {
/* if cache isn;t enabled no need to disable */
cache_bit |= CR_M;
}
reg = get_cr();
- cp_delay();
if (cache_bit == (CR_C | CR_M))
flush_dcache_all();
set_cr(reg & ~cache_bit);
arm1136_cache_flush();
#endif
#ifdef CONFIG_ARM926EJS
- /* test and clean, page 2-23 of arm926ejs manual */
- asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
- /* disable write buffer as well (page 2-22) */
- asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+ asm(
+ /* test and clean, page 2-23 of arm926ejs manual */
+ "0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n"
+ /* flush write buffer as well (page 2-22) */
+ "mcr p15, 0, %0, c7, c10, 4" : : "r"(0) : "memory"
+ );
#endif
return;
}
{
mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
}
+
+static uint32_t dram_vals[] = {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a,
+ 0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000,
+ 0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
+ 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 0x02030202,
+ 0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303,
+ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100,
+ 0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000612, 0x01000F02, 0x06120612, 0x00000200,
+ 0x00020007, 0xf5014b27, 0xf5014b27, 0xf5014b27, 0xf5014b27,
+ 0x07000300, 0x07000300, 0x07000300, 0x07000300, 0x00000006,
+ 0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201,
+ 0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04,
+ 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00010000, 0x00020304, 0x00000004,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303,
+ 0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200,
+ 0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001
+};
+
+void mx28_ddr2_setup(void)
+{
+ int i;
+
+ serial_puts("\n");
+ for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
+ writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+}
--- /dev/null
+#
+# (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# version 2 as published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
+
+LIB = $(obj)lib$(VENDOR).o
+
+ifeq ($(CONFIG_SPL_BUILD),)
+ COBJS-$(CONFIG_OF_BOARD_SETUP) += fdt.o
+ COBJS-$(CONFIG_SPLASH_SCREEN) += splashimage.o
+endif
+
+COBJS := $(COBJS-y)
+SOBJS :=
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+all: $(LIB)
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+*/
+
+#include <common.h>
+#include <errno.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <nand.h>
+#include <jffs2/load_kernel.h>
+
+#include "karo.h"
+
+#ifdef CONFIG_MAX_DTB_SIZE
+#define MAX_DTB_SIZE CONFIG_MAX_DTB_SIZE
+#else
+#define MAX_DTB_SIZE SZ_64K
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void karo_set_fdtsize(void *fdt)
+{
+ char fdt_size[9];
+ size_t fdtsize = getenv_ulong("fdtsize", 16, 0);
+
+ if (fdtsize == fdt_totalsize(fdt)) {
+ return;
+ }
+ debug("FDT size changed from %u to %u\n",
+ fdtsize, fdt_totalsize(fdt));
+
+ snprintf(fdt_size, sizeof(fdt_size), "%08x", fdt_totalsize(fdt));
+ setenv("fdtsize", fdt_size);
+}
+
+void karo_fdt_move_fdt(void)
+{
+ void *fdt;
+ unsigned long fdt_addr = getenv_ulong("fdtaddr", 16, 0);
+
+ if (!fdt_addr) {
+ fdt_addr = CONFIG_SYS_FDT_ADDR;
+ printf("fdtaddr is not set; using default: %08lx\n",
+ fdt_addr);
+ }
+
+ fdt = karo_fdt_load_dtb();
+ if (fdt == NULL) {
+ fdt = (void *)gd->fdt_blob;
+ if (fdt == NULL) {
+ printf("Compiled in FDT not found\n");
+ return;
+ }
+ debug("Checking FDT header @ %p\n", fdt);
+ if (fdt_check_header(fdt)) {
+ printf("ERROR: No valid DTB found at %p\n", fdt);
+ return;
+ }
+ printf("No DTB in flash; using default DTB\n");
+ debug("Moving FDT from %p..%p to %08lx..%08lx\n",
+ fdt, fdt + fdt_totalsize(fdt) - 1,
+ fdt_addr, fdt_addr + fdt_totalsize(fdt) - 1);
+ memmove((void *)fdt_addr, fdt, fdt_totalsize(fdt));
+ }
+ set_working_fdt_addr((void *)fdt_addr);
+ karo_set_fdtsize(fdt);
+}
+
+void karo_fdt_remove_node(void *blob, const char *node)
+{
+ debug("Removing node '%s' from DT\n", node);
+ int off = fdt_path_offset(blob, node);
+ int ret;
+
+ if (off < 0) {
+ printf("Could not find node '%s': %d\n", node, off);
+ } else {
+ ret = fdt_del_node(blob, off);
+ if (ret)
+ printf("Failed to remove node '%s': %d\n",
+ node, ret);
+ }
+ karo_set_fdtsize(blob);
+}
+
+void karo_fdt_enable_node(void *blob, const char *node, int enable)
+{
+ int off = fdt_path_offset(blob, node);
+
+ debug("%sabling node '%s'\n", enable ? "En" : "Dis", node);
+ if (off < 0) {
+ printf("Could not find node '%s': %d\n", node, off);
+ return;
+ }
+ fdt_set_node_status(blob, off,
+ enable ? FDT_STATUS_OKAY : FDT_STATUS_DISABLED, 0);
+
+ karo_set_fdtsize(blob);
+}
+
+static const char *karo_touchpanels[] = {
+ "ti,tsc2007",
+ "edt,edt-ft5x06",
+};
+
+static void fdt_del_tp_node(void *blob, const char *name)
+{
+ int offs = fdt_node_offset_by_compatible(blob, -1, name);
+ uint32_t ph1 = 0, ph2 = 0;
+ const uint32_t *prop;
+
+ if (offs < 0) {
+ debug("node '%s' not found: %d\n", name, offs);
+ return;
+ }
+
+ prop = fdt_getprop(blob, offs, "reset-switch", NULL);
+ if (prop)
+ ph1 = fdt32_to_cpu(*prop);
+
+ prop = fdt_getprop(blob, offs, "wake-switch", NULL);
+ if (prop)
+ ph2 = fdt32_to_cpu(*prop);
+
+ debug("Removing node '%s' from DT\n", name);
+ fdt_del_node(blob, offs);
+
+ if (ph1) {
+ offs = fdt_node_offset_by_phandle(blob, ph1);
+ if (offs > 0) {
+ debug("Removing node %08x @ %08x\n", ph1, offs);
+ fdt_del_node(blob, offs);
+ }
+ }
+ if (ph2) {
+ offs = fdt_node_offset_by_phandle(blob, ph2);
+ if (offs > 0) {
+ debug("Removing node %08x @ %08x\n", ph2, offs);
+ fdt_del_node(blob, offs);
+ }
+ }
+}
+
+void karo_fdt_fixup_touchpanel(void *blob)
+{
+ int i;
+ const char *model = getenv("touchpanel");
+
+ for (i = 0; i < ARRAY_SIZE(karo_touchpanels); i++) {
+ const char *tp = karo_touchpanels[i];
+
+ if (model != NULL && strcmp(model, tp) == 0)
+ continue;
+
+ tp = strchr(tp, ',');
+ if (tp != NULL && *tp != '\0' && strcmp(model, tp + 1) == 0)
+ continue;
+
+ fdt_del_tp_node(blob, karo_touchpanels[i]);
+ karo_set_fdtsize(blob);
+ }
+}
+
+void karo_fdt_fixup_usb_otg(void *blob, const char *compat, phys_addr_t offs)
+{
+ const char *otg_mode = getenv("otg_mode");
+ int off;
+
+ debug("OTG mode is '%s'\n", otg_mode ? otg_mode : "<UNSET>");
+
+ off = fdt_node_offset_by_compat_reg(blob, compat, offs);
+ if (off < 0) {
+ printf("Failed to find node %s@%08lx\n", compat, offs);
+ return;
+ }
+
+ if (!otg_mode || strcmp(otg_mode, "device") != 0) {
+ printf("Deleting property gadget-device-name from node %s@%08lx\n",
+ compat, offs);
+ fdt_delprop(blob, off, "gadget-device-name");
+ }
+ if (!otg_mode || strcmp(otg_mode, "host") != 0) {
+ printf("Deleting property host-device-name from node %s@%08lx\n",
+ compat, offs);
+ fdt_delprop(blob, off, "host-device-name");
+ }
+ karo_set_fdtsize(blob);
+}
+
+void karo_fdt_del_prop(void *blob, const char *compat, phys_addr_t offs,
+ const char *prop)
+{
+ int ret;
+ int offset;
+ const uint32_t *phandle;
+ uint32_t ph = 0;
+
+ offset = fdt_node_offset_by_compat_reg(blob, compat, offs);
+ if (offset <= 0)
+ return;
+
+ phandle = fdt_getprop(blob, offset, prop, NULL);
+ if (phandle) {
+ ph = fdt32_to_cpu(*phandle);
+ }
+
+ debug("Removing property '%s' from node %s@%08lx\n", prop, compat, offs);
+ ret = fdt_delprop(blob, offset, prop);
+ if (ret == 0)
+ karo_set_fdtsize(blob);
+
+ if (!ph)
+ return;
+
+ offset = fdt_node_offset_by_phandle(blob, ph);
+ if (offset <= 0)
+ return;
+
+ debug("Removing node @ %08x\n", offset);
+ fdt_del_node(blob, offset);
+ karo_set_fdtsize(blob);
+}
+
+static int karo_load_part(const char *part, void *addr, size_t len)
+{
+ int ret;
+ struct mtd_device *dev;
+ struct part_info *part_info;
+ u8 part_num;
+
+ debug("Initializing mtd_parts\n");
+ ret = mtdparts_init();
+ if (ret)
+ return ret;
+
+ debug("Trying to find NAND partition '%s'\n", part);
+ ret = find_dev_and_part(part, &dev, &part_num,
+ &part_info);
+ if (ret) {
+ printf("Failed to find flash partition '%s': %d\n",
+ part, ret);
+
+ return ret;
+ }
+ debug("Found partition '%s': offset=%08x size=%08x\n",
+ part, part_info->offset, part_info->size);
+ if (part_info->size < len) {
+ printf("Warning: partition '%s' smaller than requested size: %u; truncating data to %u byte\n",
+ part, len, part_info->size);
+ len = part_info->size;
+ }
+ debug("Reading NAND partition '%s' to %p\n", part, addr);
+ ret = nand_read_skip_bad(&nand_info[0], part_info->offset, &len, addr);
+ if (ret) {
+ printf("Failed to load partition '%s' to %p\n", part, addr);
+ return ret;
+ }
+ debug("Read %u byte from partition '%s' @ offset %08x\n",
+ len, part, part_info->offset);
+ return 0;
+}
+
+void *karo_fdt_load_dtb(void)
+{
+ int ret;
+ void *fdt = (void *)getenv_ulong("fdtaddr", 16, 0);
+
+ if (tstc() || !fdt) {
+ debug("aborting DTB load\n");
+ return NULL;
+ }
+
+ /* clear FDT header in memory */
+ memset(fdt, 0, 4);
+
+ ret = karo_load_part("dtb", fdt, MAX_DTB_SIZE);
+ if (ret) {
+ printf("Failed to load dtb from flash: %d\n", ret);
+ return NULL;
+ }
+
+ if (fdt_check_header(fdt)) {
+ debug("No valid DTB in flash\n");
+ return NULL;
+ }
+ debug("Using DTB from flash\n");
+ karo_set_fdtsize(fdt);
+ return fdt;
+}
--- /dev/null
+/*
+ * (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+*/
+
+void karo_fdt_remove_node(void *blob, const char *node);
+void karo_fdt_move_fdt(void);
+void karo_fdt_fixup_touchpanel(void *blob);
+void karo_fdt_fixup_usb_otg(void *blob, const char *compat, phys_addr_t offs);
+void karo_fdt_del_prop(void *blob, const char *compat, phys_addr_t offs,
+ const char *prop);
+void karo_fdt_enable_node(void *blob, const char *node, int enable);
+void *karo_fdt_load_dtb(void);
+
+int karo_load_splashimage(int mode);
--- /dev/null
+/*
+ * (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <lcd.h>
+#include <nand.h>
+#include <jffs2/load_kernel.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int karo_load_part(const char *part, void *addr, size_t len)
+{
+ int ret;
+ struct mtd_device *dev;
+ struct part_info *part_info;
+ u8 part_num;
+
+ debug("Initializing mtd_parts\n");
+ ret = mtdparts_init();
+ if (ret)
+ return ret;
+
+ debug("Trying to find NAND partition '%s'\n", part);
+ ret = find_dev_and_part(part, &dev, &part_num,
+ &part_info);
+ if (ret) {
+ printf("Failed to find flash partition '%s': %d\n",
+ part, ret);
+
+ return ret;
+ }
+ debug("Found partition '%s': offset=%08x size=%08x\n",
+ part, part_info->offset, part_info->size);
+ if (part_info->size < len) {
+ printf("Warning: partition '%s' smaller than requested size: %u; truncating data to %u byte\n",
+ part, len, part_info->size);
+ len = part_info->size;
+ }
+ debug("Reading NAND partition '%s' to %p\n", part, addr);
+ ret = nand_read_skip_bad(&nand_info[0], part_info->offset, &len, addr);
+ if (ret) {
+ printf("Failed to load partition '%s' to %p\n", part, addr);
+ return ret;
+ }
+ debug("Read %u byte from partition '%s' @ offset %08x\n",
+ len, part, part_info->offset);
+ return 0;
+}
+
+static ulong calc_fbsize(void)
+{
+ return panel_info.vl_row * panel_info.vl_col *
+ NBITS(panel_info.vl_bpix) / 8;
+}
+
+int karo_load_splashimage(int mode)
+{
+ int ret;
+ int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
+ unsigned long la = gd->fb_base;
+ char *splashimage = getenv("splashimage");
+ ulong fbsize = calc_fbsize();
+ char *end;
+
+ if (!la || !splashimage)
+ return 0;
+
+ if ((simple_strtoul(splashimage, &end, 16) != 0) &&
+ *end == '\0') {
+ if (mode)
+ return 0;
+ la = simple_strtoul(splashimage, NULL, 16);
+ splashimage = "logo.bmp";
+ } else if (!mode) {
+ return 0;
+ }
+
+ if (tstc())
+ return -ENODEV;
+
+ ret = karo_load_part(splashimage, (void *)la, fbsize);
+ if (ret) {
+ printf("Failed to load logo from '%s': %d\n", splashimage, ret);
+ return ret;
+ }
+ return 0;
+}
+
+static int erase_flash(loff_t offs, size_t len)
+{
+ nand_erase_options_t nand_erase_options;
+
+ memset(&nand_erase_options, 0, sizeof(nand_erase_options));
+ nand_erase_options.length = len;
+ nand_erase_options.offset = offs;
+
+ return nand_erase_opts(&nand_info[0], &nand_erase_options);
+}
+
+int do_fbdump(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int ret;
+ size_t fbsize = calc_fbsize();
+ const char *part = "logo";
+ struct mtd_device *dev;
+ struct part_info *part_info;
+ u8 part_num;
+ u_char *addr = (u_char *)gd->fb_base;
+
+ if (argc > 2)
+ return CMD_RET_USAGE;
+
+ if (argc == 2)
+ part = argv[1];
+
+ if (!addr) {
+ printf("fb address unknown\n");
+ return CMD_RET_FAILURE;
+ }
+
+ debug("Initializing mtd_parts\n");
+ ret = mtdparts_init();
+ if (ret)
+ return ret;
+
+ debug("Trying to find NAND partition '%s'\n", part);
+ ret = find_dev_and_part(part, &dev, &part_num,
+ &part_info);
+ if (ret) {
+ printf("Failed to find flash partition '%s': %d\n",
+ part, ret);
+
+ return ret;
+ }
+ debug("Found partition '%s': offset=%08x size=%08x\n",
+ part, part_info->offset, part_info->size);
+ if (part_info->size < fbsize) {
+ printf("Error: partition '%s' smaller than frame buffer size: %u\n",
+ part, fbsize);
+ return CMD_RET_FAILURE;
+ }
+ debug("Writing framebuffer %p to NAND partition '%s'\n",
+ addr, part);
+
+ ret = erase_flash(part_info->offset, fbsize);
+ if (ret) {
+ printf("Failed to erase partition '%s'\n", part);
+ return CMD_RET_FAILURE;
+ }
+
+ ret = nand_write_skip_bad(&nand_info[0], part_info->offset,
+ &fbsize, addr, WITH_DROP_FFS);
+ if (ret) {
+ printf("Failed to write partition '%s'\n", part);
+ return ret;
+ }
+ debug("Wrote %u byte from %p to partition '%s' @ offset %08x\n",
+ fbsize, addr, part, part_info->offset);
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(fbdump, 2, 0, do_fbdump, "dump framebuffer contents to flash",
+ "[partition name]\n"
+ " default partition name: 'logo'\n");
--- /dev/null
+/*
+ * Copyright 2012 <LW@KARO-electronics.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "Ka-Ro electronics TX28 module";
+ compatible = "karo,tx28", "fsl,imx28";
+
+ aliases {
+ usbphy0 = &usbphy0;
+ usbphy1 = &usbphy1;
+ usbotg = &usb0;
+ usbh1 = &usb1;
+ can1 = &can1;
+ ethernet0 = &mac0;
+ ethernet1 = &mac1;
+ ds1339 = &ds1339;
+ pca9554 = &pca9554;
+ stk5led = &stk5_led;
+ };
+
+ memory {
+ reg = <0 0>;
+ };
+
+ apb@80000000 {
+ apbh@80000000 {
+ ssp0: ssp@80010000 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_4bit_pins_a
+ &mmc0_cd_cfg
+ &mmc0_sck_cfg>;
+ bus-width = <4>;
+ status = "okay";
+ };
+
+ pinctrl@80018000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_a>;
+
+ hog_pins_a: hog-gpios@1 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x31b3 /* MX28_PAD_SPDIF__GPIO_3_27 */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ hog_pins_stk_v3_led: hog-gpios@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ mac0_pins_gpio: mac0-gpio-mode@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ 0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */
+ 0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */
+ 0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */
+ 0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */
+ 0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */
+ 0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */
+ 0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */
+ 0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */
+ 0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+
+ lcdif_pins_tx28: lcdif-tx28@0 {
+ fsl,pinmux-ids = <
+ 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
+ 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
+ 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
+ 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
+ >;
+ fsl,drive-strength = <0>;
+ fsl,voltage = <1>;
+ fsl,pull-up = <0>;
+ };
+ };
+
+ lcdif@80030000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdif_24bit_pins_a
+ &lcdif_pins_tx28>;
+ };
+
+ can0: can@80032000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0_pins_a>;
+ transceiver-switch = <&flexcan_transceiver>;
+ };
+
+ can1: can@80034000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&can1_pins_a>;
+ transceiver-switch = <&flexcan_transceiver>;
+ };
+ };
+
+ apbx@80040000 {
+ saif0: saif@80042000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif0_pins_a>;
+ };
+
+ saif1: saif@80046000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif1_pins_a>;
+ fsl,saif-master = <&saif0>;
+ };
+
+ lradc@80050000 {
+ status = "okay";
+ };
+
+ i2c0: i2c@80058000 {
+ status = "okay";
+
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+
+ ds1339: rtc@68 {
+ compatible = "maxim,ds1339";
+ reg = <0x68>;
+ };
+
+ pca9554: pca953x@20 {
+ compatible = "nxp,pca953x";
+ reg = <0x20>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <20>;
+ };
+
+ codec: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+
+ touchscreen: tsc2007@48 {
+ compatible = "ti,tsc2007";
+ reg = <0x48>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <20 0>;
+ pendown-gpio = <&gpio3 20 1>;
+ model = "2007";
+ x-plate-ohms = <660>;
+ };
+
+ polytouch: edt-ft5x06@ {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <5>;
+ reset-switch = <&edt_ft5x06_reset>;
+ wake-switch = <&edt_ft5x06_wake>;
+ };
+ };
+
+ pwm: pwm@80064000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins_a>;
+ };
+
+ auart1: serial@8006c000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart1_pins_a>;
+ };
+
+ auart3: serial@80070000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart3_pins_a>;
+ };
+
+ duart: serial@80074000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_4pins_a>;
+ };
+
+ usbphy0: usbphy@8007c000 {
+ status = "okay";
+ };
+
+ usbphy1: usbphy@8007e000 {
+ status = "okay";
+ };
+ };
+ };
+
+ ahb@80080000 {
+ usb0: usb@80080000 {
+ status = "okay";
+
+ vbus-supply = <®_usb0_vbus>;
+ pinctrl-names = "default";
+ };
+
+ usb1: usb@80090000 {
+ status = "okay";
+
+ vbus-supply = <®_usb1_vbus>;
+ pinctrl-names = "default";
+ };
+
+ gpmi-nand@8000c000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpmi_pins_a>;
+ };
+
+ mac0: ethernet@800f0000 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac0_pins_a>;
+ status = "okay";
+ mac-address = [000000000000]; /* will be set bootloader */
+ };
+
+ mac1: ethernet@800f4000 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mac1_pins_a>;
+ status = "okay";
+ mac-address = [000000000000]; /* will be set by bootloader */
+ };
+ };
+
+ stk5_led: leds {
+ compatible = "gpio-leds";
+
+ user {
+ label = "Heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_stk_v3_led>;
+ gpios = <&gpio4 10 0>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 5000000>;
+ brightness-levels = <100 95 90 85 80 75 70 65 60 55
+ 50 45 40 35 30 25 20 15 10 5 0>;
+ default-brightness-level = <20>;
+ };
+
+ gpio-switch {
+ compatible = "gpio-switches", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flexcan_transceiver: gpio-switch@0 {
+ label = "flexcan transceiver switch";
+ gpios = <&gpio1 0 1>;
+ gpio-shared;
+ };
+
+ lcd_power: gpio-switch@1 {
+ compatible = "linux,gpio-switch";
+ gpios = <&gpio1 31 0>;
+ label = "LCD Power Enable";
+ init-state = <0>;
+ };
+
+ lcd_reset: gpio-switch@2 {
+ compatible = "linux,gpio-switch";
+ gpios = <&gpio3 30 1>;
+ label = "LCD Reset";
+ init-state = <1>;
+ };
+
+ edt_ft5x06_reset: gpio-switch@3 {
+ compatible = "linux,gpio-switch";
+ gpios = <&gpio2 6 1>;
+ label = "EDT-FT5x06 RESET";
+ };
+
+ edt_ft5x06_wake: gpio-switch@4 {
+ compatible = "linux,gpio-switch";
+ gpios = <&gpio4 9 0>;
+ label = "EDT-FT5x06 WAKE";
+ init-state = <1>;
+ };
+
+ usbotg_vbus: gpio-switch@5 {
+ compatible = "linux,gpio-switch";
+ gpios = <&gpio0 18 0>;
+ label = "USBOTG VBUS";
+ };
+
+ usbh1_vbus: gpio-switch@6 {
+ compatible = "linux,gpio-switch";
+ gpios = <&gpio3 27 0>;
+ label = "USBH1 VBUS";
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+
+ reg_2p5v: 2p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb0_vbus: usb0_vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio0 18 1>;
+ };
+
+ reg_usb1_vbus: usb1_vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 27 1>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "Ka-Ro electronics TX48 module";
+ compatible = "karo,tx48", "ti,am33xx";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ ocp {
+ i2c@44E0B000 {
+ rtc1: ds1339@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ trickle-charge = <0xa5>;
+ };
+
+ pmic: lt3589@48 {
+ compatible = "lt,lt3589";
+ reg = <0x48>;
+ };
+
+ codec: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+
+ touchscreen: tsc2007@48 {
+ compatible = "ti,tsc2007";
+ reg = <0x48>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <16 0>;
+ pendown-gpio = <&gpio3 16 1>;
+ model = "2007";
+ x-plate-ohms = <660>;
+ };
+
+ polytouch: edt-ft5x06@38 {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <17>;
+ reset-switch = <&edt_ft5x06_reset>;
+ wake-switch = <&edt_ft5x06_wake>;
+ };
+ };
+ };
+
+ gpio-switch {
+ compatible = "gpio-switch";
+
+ can_xcvr_enable: can-xcvr-enable {
+ gpio = <&gpio0 22 1>;
+ label = "Flexcan Transceiver Enable";
+ gpio-shared;
+ };
+
+ lcd_power: lcd-power {
+ compatible = "linux,gpio-switch";
+ gpio = <&gpio1 22 0>;
+ label = "LCD Power Enable";
+ };
+
+ lcd_reset: lcd-reset {
+ compatible = "linux,gpio-switch";
+ gpio = <&gpio1 19 1>;
+ label = "LCD Reset";
+ init-state = <1>;
+ };
+
+ edt_ft5x06_reset: edt-ft5x06-reset {
+ compatible = "linux,gpio-switch";
+ gpio = <&gpio1 18 1>;
+ label = "EDT-FT5x06 RESET";
+ };
+
+ edt_ft5x06_wake: edt-ft5x06-wake {
+ compatible = "linux,gpio-switch";
+ gpio = <&gpio1 27 0>;
+ label = "EDT-FT5x06 WAKE";
+ init-state = <1>;
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+
+ reg_2p5v: 2p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2012 <LW@KARO-electronics.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "Ka-Ro electronics TX51 module";
+ compatible = "karo,tx51", "fsl,imx51";
+
+ chosen {
+ bootargs = "init=/linuxrc console=ttymxc0,115200 root=/dev/mtdblock1 ro debug panic=1";
+ };
+
+ aliases {
+ usbh1 = &usbh1;
+ usbotg = &usbotg;
+ usbphy = &usbphy;
+ };
+
+ clocks {
+ ckih1 {
+ clock-frequency = <0>;
+ };
+ };
+
+ soc {
+ ahb: ahb@40000000 {
+ ipu: ipu@5e000000 {
+ status = "okay";
+ };
+ };
+
+ aips1: aips@70000000 { /* AIPS1 */
+ spba@70000000 {
+ mmc0: esdhc@70004000 { /* ESDHC1 */
+ cd-gpios = <&gpio3 8 0>;
+ fsl,wp-controller;
+ status = "okay";
+ };
+
+ mmc1: esdhc@70008000 { /* ESDHC2 */
+ cd-gpios = <&gpio3 6 0>;
+ status = "okay";
+ };
+
+ uart@7000c000 {
+ status = "okay";
+ fsl,uart-has-rtscts;
+ };
+
+ spi0: ecspi@70010000 { /* ECSPI1 */
+ fsl,spi-num-chipselects = <2>;
+ cs-gpios = <&gpio4 24 0 &gpio4 25 0>;
+ status = "okay";
+
+ spidev0: spi@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <250000000>;
+ };
+ };
+ };
+
+ usbotg: imxotg@73f80000 {
+ status = "okay";
+
+ ignore-overcurrent;
+ enable-wakeup;
+ phy-mode = "utmi-wide";
+ };
+
+ usbh1: imxotg@73f80200 {
+ status = "okay";
+
+ phy-mode = "ulpi";
+ ignore-overcurrent;
+ enable-wakeup;
+ itc-no-threshold;
+ };
+
+ usbphy: imx-usb-phy@73f80800 {
+ status = "okay";
+
+ device-ports = <&usbotg>;
+ host-ports = <&usbotg &usbh1>;
+ };
+
+ keypad@73f94000 {
+ status = "okay";
+ /* sample keymap */
+ linux,keymap = < 0x00000074 /* row 0, col 0, KEY_POWER */
+ 0x00010052 /* row 0, col 1, KEY_KP0 */
+ 0x0002004f /* row 0, col 2, KEY_KP1 */
+ 0x00030050 /* row 0, col 3, KEY_KP2 */
+ 0x00040051 /* row 0, col 4, KEY_KP3 */
+ 0x0100004b /* row 1, col 0, KEY_KP4 */
+ 0x0101004c /* row 1, col 1, KEY_KP5 */
+ 0x0102004d /* row 1, col 2, KEY_KP6 */
+ 0x01030047 /* row 1, col 3, KEY_KP7 */
+ 0x01040048 /* row 1, col 4, KEY_KP8 */
+ 0x02000049 /* row 2, col 0, KEY_KP9 */
+ >;
+ };
+
+ wdog@73f98000 { /* WDOG1 */
+ status = "okay";
+ };
+
+ iomuxc@73fa8000 {
+ compatible = "fsl,imx51-iomuxc-tx51";
+ reg = <0x73fa8000 0x4000>;
+ };
+
+ pwm1: pwm@73fb4000 {
+ status = "okay";
+ };
+
+ uart@73fbc000 {
+ status = "okay";
+ fsl,uart-has-rtscts;
+ };
+
+ uart@73fc0000 {
+ status = "okay";
+ fsl,uart-has-rtscts;
+ };
+ };
+
+ aips2: aips@80000000 { /* AIPS2 */
+
+ sdma@83fb0000 {
+ fsl,sdma-ram-script-name = "sdma-imx51.bin";
+ };
+
+ i2c@83fc4000 { /* I2C2 */
+ status = "okay";
+
+ codec: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+
+ touchscreen: tsc2007@48 {
+ compatible = "ti,tsc2007";
+ reg = <0x48>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <3 0>;
+ pendown-gpio = <&gpio3 3 1>;
+ model = "2007";
+ x-plate-ohms = <660>;
+ };
+
+ polytouch: edt-ft5x06@38 {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <5>;
+ reset-switch = <&edt_ft5x06_reset>;
+ wake-switch = <&edt_ft5x06_wake>;
+ };
+ };
+
+ ssi@83fcc000 {
+ status = "okay";
+ rx-dma = <28>;
+ tx-dma = <29>;
+ i2s-sync-mode;
+ };
+
+ ssi@70014000 {
+ status = "okay";
+ };
+
+ audmux@83fd0000 {
+ status = "okay";
+ };
+
+ sound-card@0 {
+ compatible = "fsl,imx-sgtl5000";
+ status = "okay";
+ /* '1' based port numbers according to datasheet names */
+ ssi-port = <1>;
+ audmux-port = <3>;
+ sysclk = <26000000>;
+ };
+
+ nand@83fdb000 {
+ status = "okay";
+
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ };
+
+ ethernet@83fec000 {
+ phy-mode = "mii";
+/*
+ phy-reset-gpios = <&gpio2 14 0>;
+*/
+ status = "okay";
+ phy-handle = <&phy0>;
+ mac-address = [000000000000];
+
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <&gpio3>;
+ interrupts = <18>;
+ device_type = "ethernet-phy";
+ };
+ };
+ };
+ };
+
+ i2c-gpio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ gpios = <&gpio4 17 0
+ &gpio4 16 0>;
+ clock-frequency = <400000>;
+
+ rtc1: ds1339@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+ };
+
+ gpio-switch {
+ compatible = "gpio-switches", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ lcd_power: gpio-switch@1 {
+ compatible = "linux,gpio-switch";
+ gpio = <&gpio4 14 0>;
+ label = "LCD Power Enable";
+ init-state = <0>;
+ };
+
+ lcd_reset: gpio-switch@2 {
+ compatible = "linux,gpio-switch";
+ gpio = <&gpio4 13 1>;
+ label = "LCD Reset";
+ init-state = <1>;
+ };
+
+ edt_ft5x06_reset: gpio-switch@3 {
+ compatible = "linux,gpio-switch";
+ gpio = <&gpio4 15 1>;
+ label = "EDT-FT5x06 RESET";
+ };
+
+ edt_ft5x06_wake: gpio-switch@4 {
+ compatible = "linux,gpio-switch";
+ gpio = <&gpio4 9 0>;
+ label = "EDT-FT5x06 WAKE";
+ init-state = <1>;
+ };
+
+ usbotg_vbus: gpio-switch@5 {
+ compatible = "linux,gpio-switch";
+ gpio = <&gpio1 8 0>;
+ label = "USBOTG VBUS";
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ user {
+ label = "Heartbeat";
+ gpios = <&gpio4 10 0>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ lcd {
+ compatible = "of-gpio-lcd";
+ parent = <&ipu>;
+
+ power-switch = <&gpio4 14 0>;
+ reset-switch = <&gpio4 13 1>;
+ };
+
+ backlight: pwm-backlight {
+ compatible = "pwm-backlight";
+
+ pwm = <&pwm1>;
+ inverted;
+ max-brightness = <100>;
+ dft-brightness = <50>;
+ pwm-period-ns = <1000000>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+
+ reg_2p5v: 2p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2012 <LW@KARO-electronics.de>
+ * based on imx53-qsb.dts
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#undef linux
+
+/dts-v1/;
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "Ka-Ro electronics TX53 module";
+ compatible = "karo,tx53", "fsl,imx53";
+
+ chosen {
+ bootargs = "init=/linuxrc console=ttymxc0,115200 root=/dev/mtdblock3 rootfstype=jffs2 ro debug panic=1";
+ };
+
+ aliases {
+ ipu = &ipu;
+ };
+
+ clocks {
+ ckih1 {
+ clock-frequency = <0>;
+ };
+ };
+
+ soc {
+ extmc: extmc@00000000 {
+ sata: sata@10000000 {
+ status = "okay";
+ };
+
+ ipu: ipu@1e000000 {
+ status = "okay";
+ };
+ };
+
+ aips1: aips@50000000 { /* AIPS1 */
+ spba@50000000 {
+ mmc0: esdhc@50004000 { /* ESDHC1 */
+ status = "okay";
+ cd-gpios = <&gpio3 24 0>;
+ fsl,wp-controller;
+ };
+
+ mmc1: esdhc@50008000 { /* ESDHC2 */
+ status = "okay";
+ cd-gpios = <&gpio3 25 0>;
+ fsl,wp-controller;
+ };
+
+ uart3: uart@5000c000 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_1>;
+ fsl,uart-has-rtscts;
+ };
+
+ spi0: ecspi@50010000 { /* ECSPI1 */
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &pinctrl_ecspi1_1
+ &pinctrl_cspi1_cs
+ >;
+
+ fsl,spi-num-chipselects = <2>;
+ cs-gpios = <&gpio2 30 0 &gpio3 19 0>;
+
+ spidev0: spi@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <54000000>;
+ };
+ };
+ };
+
+ usbotg: imxotg@53f80000 {
+ status = "okay";
+
+ ignore-overcurrent;
+ enable-wakeup;
+ vbus-gpio = <&usbotg_vbus>;
+ };
+
+ usbh1: imxotg@53f80200 {
+ status = "okay";
+
+ ignore-overcurrent;
+ enable-wakeup;
+ vbus-gpio = <&usbh1_vbus>;
+ };
+
+ usbphy: imx-usb-phy@53f80800 {
+ status = "okay";
+
+ device-ports = <&usbotg>;
+ host-ports = <&usbotg &usbh1>;
+ };
+
+ keypad@53f94000 {
+ status = "okay";
+ /* sample keymap */
+ /* row/col 0,1 are mapped to KPP row/col 6,7 */
+ linux,keymap = < 0x06060074 /* row 6, col 6, KEY_POWER */
+ 0x06070052 /* row 6, col 7, KEY_KP0 */
+ 0x0602004f /* row 6, col 2, KEY_KP1 */
+ 0x06030050 /* row 6, col 3, KEY_KP2 */
+ 0x07060051 /* row 7, col 6, KEY_KP3 */
+ 0x0707004b /* row 7, col 7, KEY_KP4 */
+ 0x0702004c /* row 7, col 2, KEY_KP5 */
+ 0x0703004d /* row 7, col 3, KEY_KP6 */
+ 0x02060047 /* row 2, col 6, KEY_KP7 */
+ 0x02070048 /* row 2, col 7, KEY_KP8 */
+ 0x02020049 /* row 2, col 2, KEY_KP9 */
+ >;
+ };
+
+ wdog@53f98000 { /* WDOG1 */
+ status = "okay";
+ };
+
+ iomuxc@53fa8000 {
+ compatible = "fsl,imx53-iomuxc-tx53";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tsc2007_pd>;
+
+ pincontroller {
+ pinctrl_stk5_led: stk5-led-gpios {
+ fsl,pins = <
+ 589 0xc0 /* MX53_PAD_EIM_A18__GPIO2_20 */
+ >;
+ };
+
+ pinctrl_ds1339_int: ds1339-gpios {
+ fsl,pins = <
+ 104 0xe0 /* MX53_PAD_DI0_PIN4__GPIO4_20 */
+ >;
+ };
+
+ pinctrl_cspi1_cs: cspi1-cs-gpios {
+ fsl,pins = <
+ 424 0xe0 /* MX53_PAD_EIM_EB2__GPIO2_30 */
+ 449 0xe0 /* MX53_PAD_EIM_D19__GPIO3_19 */
+ >;
+ };
+
+ pinctrl_esdhc1_cd: esdhc1-cd-gpios {
+ fsl,pins = <
+ 493 0x1f0 /* MX53_PAD_EIM_D24__GPIO3_24 */
+ >;
+ };
+
+ pinctrl_esdhc2_cd: esdhc2-cd-gpios {
+ fsl,pins = <
+ 501 0x1f0 /* MX53_PAD_EIM_D25__GPIO3_25 */
+ >;
+ };
+
+ pinctrl_tsc2007_pd: pendown-gpios {
+ fsl,pins = <
+ 517 0x1f0 /* MX53_PAD_EIM_D27__GPIO3_27 */
+ >;
+ };
+ };
+ };
+
+ pwm2: pwm@53fb8000 {
+ status = "okay";
+ };
+
+ uart1: uart@53fbc000 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_2>;
+ fsl,uart-has-rtscts;
+ };
+
+ uart2: uart@53fc0000 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_1>;
+ fsl,uart-has-rtscts;
+ };
+
+ can1: flexcan@53fc8000 {
+ status = "okay";
+ transceiver-switch = <&flexcan_transceiver>;
+ };
+
+ can2: flexcan@53fcc000 {
+ status = "okay";
+ transceiver-switch = <&flexcan_transceiver>;
+ };
+
+ i2c@53fec000 { /* I2C3 */
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3_1>;
+
+ sgtl5000: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_3p3v>;
+ clock-frequency = <26000000>;
+ };
+
+ touchscreen: tsc2007@48 {
+ compatible = "ti,tsc2007";
+ reg = <0x48>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <26 0>;
+ pendown-gpio = <&gpio3 26 1>;
+ model = "2007";
+ x-plate-ohms = <660>;
+ };
+
+ polytouch: edt-ft5x06@ {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <15 0>;
+ reset-switch = <&edt_ft5x06_reset>;
+ wake-switch = <&edt_ft5x06_wake>;
+ };
+ };
+ };
+
+ aips2: aips@60000000 { /* AIPS2 */
+
+ sdma@63fb0000 {
+ fsl,sdma-ram-script-name = "sdma-imx53.bin";
+ };
+
+ i2c@63fc8000 { /* I2C1 */
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &pinctrl_i2c1_2
+ &pinctrl_ds1339_int
+ >;
+
+ rtc1: ds1339@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ trickle-charge = <0xa5>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <20 0>;
+ };
+
+ pmic: lt3589@48 {
+ compatible = "lt,lt3589";
+ reg = <0x48>;
+ };
+ };
+
+ ssi@63fcc000 {
+ status = "okay";
+ rx-dma = <28>;
+ tx-dma = <29>;
+ i2s-sync-mode;
+ };
+
+ ssi@50014000 {
+ status = "okay";
+ };
+
+ audmux@63fd0000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux_1>;
+ };
+
+ nand@63fdb000 {
+ status = "okay";
+
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ };
+
+ ethernet@63fec000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec_1>;
+
+ phy-mode = "rmii";
+ phy-reset-gpios = <&gpio7 6 0>;
+ phy-handle = <&phy0>;
+ mac-address = [000000000000];
+
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <&gpio2>;
+ interrupts = <4>;
+ device_type = "ethernet-phy";
+ };
+ };
+ };
+ };
+
+ sound {
+ compatible = "fsl,imx-sgtl5000";
+ status = "okay";
+ /* '1' based port numbers according to datasheet names */
+ ssi-port = <1>;
+ audmux-port = <5>;
+ sysclk = <26000000>;
+ };
+
+ gpio-switch {
+ compatible = "gpio-switches", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flexcan_transceiver: gpio-switch@0 {
+ compatible = "linux,gpio-switch";
+ gpio = <&gpio4 21 1>;
+ label = "Flexcan Transceiver Enable";
+ gpio-shared;
+ init-state = <0>;
+ };
+
+ lcd_power: gpio-switch@1 {
+ compatible = "linux,gpio-switch";
+ gpio = <&gpio2 31 0>;
+ label = "LCD Power Enable";
+ init-state = <0>;
+ };
+
+ lcd_reset: gpio-switch@2 {
+ compatible = "linux,gpio-switch";
+ gpio = <&gpio3 29 1>;
+ label = "LCD Reset";
+ init-state = <1>;
+ };
+
+ edt_ft5x06_reset: gpio-switch@3 {
+ compatible = "linux,gpio-switch";
+ gpio = <&gpio2 22 1>;
+ label = "EDT-FT5x06 RESET";
+ };
+
+ edt_ft5x06_wake: gpio-switch@4 {
+ compatible = "linux,gpio-switch";
+ gpio = <&gpio2 21 0>;
+ label = "EDT-FT5x06 WAKE";
+ init-state = <1>;
+ };
+
+ usbotg_vbus: gpio-switch@5 {
+ compatible = "linux,gpio-switch";
+ gpio = <&gpio1 7 0>;
+ label = "USBOTG VBUS";
+ };
+
+ usbh1_vbus: gpio-switch@6 {
+ compatible = "linux,gpio-switch";
+ gpio = <&gpio3 31 0>;
+ label = "USBH1 VBUS";
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_stk5_led>;
+
+ user {
+ label = "Heartbeat";
+ gpios = <&gpio2 20 0>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ lcd {
+ compatible = "of-gpio-lcd";
+ parent = <&ipu>;
+
+ power-switch = <&lcd_power>;
+/*
+ reset-switch = <&lcd_reset>;
+ reset-delay-us = <300>;
+*/
+ };
+
+ backlight: pwm-backlight {
+ compatible = "pwm-backlight";
+
+ pwm = <&pwm2>;
+ inverted;
+ max-brightness = <100>;
+ dft-brightness = <50>;
+ pwm-period-ns = <1000000>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+
+ reg_2p5v: 2p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "Ka-Ro TX6Q module";
+ compatible = "karo,imx6q-tx6q", "fsl,imx6q";
+
+ memory {
+ reg = <0 0>; /* filled in by U-Boot */
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_3 &pinctrl_uart1_4>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_5 &pinctrl_uart2_6>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_4>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet_1>;
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1_2>;
+ cd-gpios = <&gpio7 2 0>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_2>;
+ cd-gpios = <&gpio7 3 0>;
+ status = "okay";
+};
--- /dev/null
+#
+# (C) Copyright 2009 DENX Software Engineering
+# Author: John Rigby <jcrigby@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := tx28.o
+ifeq ($(CONFIG_SPL_BUILD),y)
+ COBJS += spl_boot.o
+else
+ifeq ($(CONFIG_CMD_ROMUPDATE),y)
+ COBJS += flash.o
+endif
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+$(obj)u-boot.db: u-boot.db.in
+ sed "s:@@BUILD_DIR@@:${BUILD_DIR:-.}/:" $< > $@
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+# stack is allocated below CONFIG_SYS_TEXT_BASE
+CONFIG_SYS_TEXT_BASE := 0x40100000
+CONFIG_SPL_TEXT_BASE := 0x00000000
+
+LOGO_BMP = logos/karo.bmp
+
+PLATFORM_CPPFLAGS += -Werror
+ifneq ($(CONFIG_SPL_BUILD),y)
+ ALL-y += $(obj)u-boot.sb
+endif
--- /dev/null
+#include <common.h>
+#include <malloc.h>
+#include <nand.h>
+#include <errno.h>
+
+#include <linux/err.h>
+
+#include <asm/io.h>
+#include <asm/sizes.h>
+#include <asm/arch/regs-base.h>
+#include <asm/arch/regs-gpmi.h>
+#include <asm/arch/regs-bch.h>
+
+#define FCB_START_BLOCK 0
+#define NUM_FCB_BLOCKS 1
+#define MAX_FCB_BLOCKS 32768
+
+struct mx28_nand_timing {
+ u8 data_setup;
+ u8 data_hold;
+ u8 address_setup;
+ u8 dsample_time;
+ u8 nand_timing_state;
+ u8 tREA;
+ u8 tRLOH;
+ u8 tRHOH;
+};
+
+struct mx28_fcb {
+ u32 checksum;
+ u32 fingerprint;
+ u32 version;
+ struct mx28_nand_timing timing;
+ u32 page_data_size;
+ u32 total_page_size;
+ u32 sectors_per_block;
+ u32 number_of_nands; /* not used by ROM code */
+ u32 total_internal_die; /* not used by ROM code */
+ u32 cell_type; /* not used by ROM code */
+ u32 ecc_blockn_type;
+ u32 ecc_block0_size;
+ u32 ecc_blockn_size;
+ u32 ecc_block0_type;
+ u32 metadata_size;
+ u32 ecc_blocks_per_page;
+ u32 rsrvd[6]; /* not used by ROM code */
+ u32 bch_mode;
+ u32 boot_patch;
+ u32 patch_sectors;
+ u32 fw1_start_page;
+ u32 fw2_start_page;
+ u32 fw1_sectors;
+ u32 fw2_sectors;
+ u32 dbbt_search_area;
+ u32 bb_mark_byte;
+ u32 bb_mark_startbit;
+ u32 bb_mark_phys_offset;
+};
+
+struct mx28_dbbt_header {
+ u32 checksum;
+ u32 fingerprint;
+ u32 version;
+ u32 number_bb;
+ u32 number_pages;
+ u8 spare[492];
+};
+
+struct mx28_dbbt {
+ u32 nand_number;
+ u32 number_bb;
+ u32 bb_num[2040 / 4];
+};
+
+#define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET)
+
+static nand_info_t *mtd = &nand_info[0];
+
+extern void *_start;
+
+#define BIT(v,n) (((v) >> (n)) & 0x1)
+
+static u8 calculate_parity_13_8(u8 d)
+{
+ u8 p = 0;
+
+ p |= (BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 3) ^ BIT(d, 2)) << 0;
+ p |= (BIT(d, 7) ^ BIT(d, 5) ^ BIT(d, 4) ^ BIT(d, 2) ^ BIT(d, 1)) << 1;
+ p |= (BIT(d, 7) ^ BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 1) ^ BIT(d, 0)) << 2;
+ p |= (BIT(d, 7) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 0)) << 3;
+ p |= (BIT(d, 6) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 2) ^ BIT(d, 1) ^ BIT(d, 0)) << 4;
+ return p;
+}
+
+static void encode_hamming_13_8(void *_src, void *_ecc, size_t size)
+{
+ int i;
+ u8 *src = _src;
+ u8 *ecc = _ecc;
+
+ for (i = 0; i < size; i++)
+ ecc[i] = calculate_parity_13_8(src[i]);
+}
+
+static u32 calc_chksum(void *buf, size_t size)
+{
+ u32 chksum = 0;
+ u8 *bp = buf;
+ size_t i;
+
+ for (i = 0; i < size; i++) {
+ chksum += bp[i];
+ }
+ return ~chksum;
+}
+
+/*
+ Physical organisation of data in NAND flash:
+ metadata
+ payload chunk 0 (may be empty)
+ ecc for metadata + payload chunk 0
+ payload chunk 1
+ ecc for payload chunk 1
+...
+ payload chunk n
+ ecc for payload chunk n
+ */
+
+static int calc_bb_offset(nand_info_t *mtd, struct mx28_fcb *fcb)
+{
+ int bb_mark_offset;
+ int chunk_data_size = fcb->ecc_blockn_size * 8;
+ int chunk_ecc_size = (fcb->ecc_blockn_type << 1) * 13;
+ int chunk_total_size = chunk_data_size + chunk_ecc_size;
+ int bb_mark_chunk, bb_mark_chunk_offs;
+
+ bb_mark_offset = (mtd->writesize - fcb->metadata_size) * 8;
+ if (fcb->ecc_block0_size == 0)
+ bb_mark_offset -= (fcb->ecc_block0_type << 1) * 13;
+
+ bb_mark_chunk = bb_mark_offset / chunk_total_size;
+ bb_mark_chunk_offs = bb_mark_offset - (bb_mark_chunk * chunk_total_size);
+ if (bb_mark_chunk_offs > chunk_data_size) {
+ printf("Unsupported ECC layout; BB mark resides in ECC data: %u\n",
+ bb_mark_chunk_offs);
+ return -EINVAL;
+ }
+ bb_mark_offset -= bb_mark_chunk * chunk_ecc_size;
+ return bb_mark_offset;
+}
+
+static struct mx28_fcb *create_fcb(void *buf, int fw1_start_block,
+ int fw2_start_block, size_t fw_size)
+{
+ struct gpmi_regs *gpmi_base = (void *)GPMI_BASE_ADDRESS;
+ struct bch_regs *bch_base = (void *)BCH_BASE_ADDRESS;
+ u32 fl0, fl1;
+ u32 t0, t1;
+ int metadata_size;
+ int bb_mark_bit_offs;
+ struct mx28_fcb *fcb;
+ int fcb_offs;
+
+ if (gpmi_base == NULL || bch_base == NULL) {
+ return ERR_PTR(-ENOMEM);
+ }
+
+ fl0 = readl(&bch_base->hw_bch_flash0layout0);
+ fl1 = readl(&bch_base->hw_bch_flash0layout1);
+ t0 = readl(&gpmi_base->hw_gpmi_timing0);
+ t1 = readl(&gpmi_base->hw_gpmi_timing1);
+
+ metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
+
+ fcb = buf + ALIGN(metadata_size, 4);
+ fcb_offs = (void *)fcb - buf;
+
+ memset(buf, 0xff, fcb_offs);
+ memset(fcb, 0x00, sizeof(*fcb));
+ memset(fcb + 1, 0xff, mtd->erasesize - fcb_offs - sizeof(*fcb));
+
+ strncpy((char *)&fcb->fingerprint, "FCB ", 4);
+ fcb->version = cpu_to_be32(1);
+
+ fcb->timing.data_setup = BF_VAL(t0, GPMI_TIMING0_DATA_SETUP);
+ fcb->timing.data_hold = BF_VAL(t0, GPMI_TIMING0_DATA_HOLD);
+ fcb->timing.address_setup = BF_VAL(t0, GPMI_TIMING0_ADDRESS_SETUP);
+
+ fcb->page_data_size = mtd->writesize;
+ fcb->total_page_size = mtd->writesize + mtd->oobsize;
+ fcb->sectors_per_block = mtd->erasesize / mtd->writesize;
+
+ fcb->ecc_block0_type = BF_VAL(fl0, BCH_FLASHLAYOUT0_ECC0);
+ fcb->ecc_block0_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_DATA0_SIZE);
+ fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASHLAYOUT1_ECCN);
+ fcb->ecc_blockn_size = BF_VAL(fl1, BCH_FLASHLAYOUT1_DATAN_SIZE);
+
+ fcb->metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
+ fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASHLAYOUT0_NBLOCKS);
+ fcb->bch_mode = readl(&bch_base->hw_bch_mode);
+/*
+ fcb->boot_patch = 0;
+ fcb->patch_sectors = 0;
+*/
+ fcb->fw1_start_page = fw1_start_block * mtd->erasesize / mtd->writesize;
+ fcb->fw1_sectors = DIV_ROUND_UP(fw_size, mtd->writesize);
+
+ if (fw2_start_block != 0 && fw2_start_block < mtd->size / mtd->erasesize) {
+ fcb->fw2_start_page = fw2_start_block * mtd->erasesize / mtd->writesize;
+ fcb->fw2_sectors = fcb->fw1_sectors;
+ }
+
+ fcb->dbbt_search_area = 1;
+
+ bb_mark_bit_offs = calc_bb_offset(mtd, fcb);
+ if (bb_mark_bit_offs < 0)
+ return ERR_PTR(bb_mark_bit_offs);
+ fcb->bb_mark_byte = bb_mark_bit_offs / 8;
+ fcb->bb_mark_startbit = bb_mark_bit_offs % 8;
+ fcb->bb_mark_phys_offset = mtd->writesize;
+
+ fcb->checksum = calc_chksum(&fcb->fingerprint, 512 - 4);
+ return fcb;
+}
+
+static int find_fcb(void *ref, int page)
+{
+ int ret = 0;
+ struct nand_chip *chip = mtd->priv;
+ void *buf = malloc(mtd->erasesize);
+
+ if (buf == NULL) {
+ return -ENOMEM;
+ }
+ chip->select_chip(mtd, 0);
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+ ret = chip->ecc.read_page_raw(mtd, chip, buf, page);
+ if (ret) {
+ printf("Failed to read FCB from page %u: %d\n", page, ret);
+ return ret;
+ }
+ chip->select_chip(mtd, -1);
+ if (memcmp(buf, ref, mtd->writesize) == 0) {
+ printf("%s: Found FCB in page %u (%08x)\n", __func__,
+ page, page * mtd->writesize);
+ ret = 1;
+ }
+ free(buf);
+ return ret;
+}
+
+static int write_fcb(void *buf, int block)
+{
+ int ret;
+ struct nand_chip *chip = mtd->priv;
+ int page = block * mtd->erasesize / mtd->writesize;
+
+ ret = find_fcb(buf, page);
+ if (ret > 0) {
+ printf("FCB at block %d is up to date\n", block);
+ return 0;
+ }
+
+ ret = nand_erase(mtd, block * mtd->erasesize, mtd->erasesize);
+ if (ret) {
+ printf("Failed to erase FCB block %u\n", block);
+ return ret;
+ }
+
+ printf("Writing FCB to block %d @ %08x\n", block,
+ block * mtd->erasesize);
+ chip->select_chip(mtd, 0);
+ ret = chip->write_page(mtd, chip, buf, page, 0, 1);
+ if (ret) {
+ printf("Failed to write FCB to block %u: %d\n", block, ret);
+ }
+ chip->select_chip(mtd, -1);
+ return ret;
+}
+
+#define chk_overlap(a,b) \
+ ((a##_start_block <= b##_end_block && \
+ a##_end_block >= b##_start_block) || \
+ (b##_start_block <= a##_end_block && \
+ b##_end_block >= a##_start_block))
+
+#define fail_if_overlap(a,b,m1,m2) do { \
+ if (chk_overlap(a, b)) { \
+ printf("%s blocks %lu..%lu overlap %s in blocks %lu..%lu!\n", \
+ m1, a##_start_block, a##_end_block, \
+ m2, b##_start_block, b##_end_block); \
+ return -EINVAL; \
+ } \
+} while (0)
+
+#ifndef CONFIG_ENV_OFFSET_REDUND
+#define TOTAL_ENV_SIZE CONFIG_ENV_SIZE
+#else
+#define TOTAL_ENV_SIZE (CONFIG_ENV_SIZE * 2)
+#endif
+
+int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int ret;
+ int block;
+ int erase_size = mtd->erasesize;
+ int page_size = mtd->writesize;
+ void *buf;
+ char *load_addr;
+ char *file_size;
+ size_t size = 0;
+ void *addr = NULL;
+ struct mx28_fcb *fcb;
+ unsigned long fcb_start_block = FCB_START_BLOCK;
+ unsigned long num_fcb_blocks = NUM_FCB_BLOCKS;
+ unsigned long fcb_end_block;
+ unsigned long mtd_num_blocks = mtd->size / mtd->erasesize;
+ unsigned long env_start_block = CONFIG_ENV_OFFSET / mtd->erasesize;
+ unsigned long env_end_block = env_start_block +
+ DIV_ROUND_UP(TOTAL_ENV_SIZE, mtd->erasesize) - 1;
+ int optind;
+ int fw1_set = 0;
+ int fw2_set = 0;
+ unsigned long fw1_start_block = 0, fw1_end_block;
+ unsigned long fw2_start_block = 0, fw2_end_block;
+ unsigned long fw_num_blocks;
+ unsigned long extra_blocks = 2;
+ nand_erase_options_t erase_opts = { 0, };
+ int fcb_written = 0;
+
+ load_addr = getenv("fileaddr");
+ file_size = getenv("filesize");
+
+ if (argc < 2 && load_addr == NULL) {
+ printf("Load address not specified\n");
+ return -EINVAL;
+ }
+ if (argc < 3 && file_size == NULL) {
+ printf("Image size not specified\n");
+ return -EINVAL;
+ }
+
+ for (optind = 1; optind < argc; optind++) {
+ if (strcmp(argv[optind], "-b") == 0) {
+ if (optind >= argc - 1) {
+ printf("Option %s requires an argument\n", argv[optind]);
+ return -EINVAL;
+ }
+ optind++;
+ fcb_start_block = simple_strtoul(argv[optind], NULL, 0);
+ if (fcb_start_block >= mtd_num_blocks) {
+ printf("Block number %lu is out of range: 0..%lu\n",
+ fcb_start_block, mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ } else if (strcmp(argv[optind], "-n") == 0) {
+ if (optind >= argc - 1) {
+ printf("Option %s requires an argument\n", argv[optind]);
+ return -EINVAL;
+ }
+ optind++;
+ num_fcb_blocks = simple_strtoul(argv[optind], NULL, 0);
+ if (num_fcb_blocks > MAX_FCB_BLOCKS) {
+ printf("Extraneous number of FCB blocks; max. allowed: %u\n",
+ MAX_FCB_BLOCKS);
+ return -EINVAL;
+ }
+ } else if (strcmp(argv[optind], "-f") == 0) {
+ if (optind >= argc - 1) {
+ printf("Option %s requires an argument\n", argv[optind]);
+ return -EINVAL;
+ }
+ optind++;
+ fw1_start_block = simple_strtoul(argv[optind], NULL, 0);
+ if (fw1_start_block >= mtd_num_blocks) {
+ printf("Block number %lu is out of range: 0..%lu\n",
+ fw1_start_block,
+ mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ fw1_set = 1;
+ } else if (strcmp(argv[optind], "-r") == 0) {
+ if (optind < argc - 1 && argv[optind + 1][0] != '-') {
+ optind++;
+ fw2_start_block = simple_strtoul(argv[optind], NULL, 0);
+ if (fw2_start_block >= mtd_num_blocks) {
+ printf("Block number %lu is out of range: 0..%lu\n",
+ fw2_start_block,
+ mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ }
+ fw2_set = 1;
+ } else if (strcmp(argv[optind], "-e") == 0) {
+ if (optind >= argc - 1) {
+ printf("Option %s requires an argument\n", argv[optind]);
+ return -EINVAL;
+ }
+ optind++;
+ extra_blocks = simple_strtoul(argv[optind], NULL, 0);
+ if (extra_blocks >= mtd_num_blocks) {
+ printf("Extra block count %lu is out of range: 0..%lu\n",
+ extra_blocks,
+ mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ } else if (argv[optind][0] == '-') {
+ printf("Unrecognized option %s\n", argv[optind]);
+ return -EINVAL;
+ }
+ }
+ if (argc > optind) {
+ load_addr = NULL;
+ addr = (void *)simple_strtoul(argv[optind], NULL, 0);
+ optind++;
+ }
+ if (argc > optind) {
+ file_size = NULL;
+ size = simple_strtoul(argv[optind], NULL, 0);
+ optind++;
+ }
+ if (load_addr != NULL) {
+ addr = (void *)simple_strtoul(load_addr, NULL, 16);
+ printf("Using default load address %p\n", addr);
+ }
+ if (file_size != NULL) {
+ size = simple_strtoul(file_size, NULL, 16);
+ printf("Using default file size %08x\n", size);
+ }
+ fcb_end_block = fcb_start_block + num_fcb_blocks - 1;
+ fw_num_blocks = DIV_ROUND_UP(size, mtd->erasesize);
+
+ if (!fw1_set) {
+ fw1_start_block = fcb_end_block + 1;
+ fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1;
+ if (chk_overlap(fw1, env)) {
+ fw1_start_block = env_end_block + 1;
+ fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1;
+ }
+ } else {
+ fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1;
+ }
+
+ if (fw2_set && fw2_start_block == 0) {
+ fw2_start_block = fw1_end_block + 1;
+ fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1;
+ if (chk_overlap(fw2, env)) {
+ fw2_start_block = env_end_block + 1;
+ fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1;
+ }
+ } else {
+ fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1;
+ }
+
+ fail_if_overlap(fcb, env, "FCB", "Environment");
+ fail_if_overlap(fcb, fw1, "FCB", "FW1");
+ fail_if_overlap(fw1, env, "FW1", "Environment");
+ if (fw2_set) {
+ fail_if_overlap(fcb, fw2, "FCB", "FW2");
+ fail_if_overlap(fw2, env, "FW2", "Environment");
+ fail_if_overlap(fw1, fw2, "FW1", "FW2");
+ }
+
+ buf = malloc(erase_size);
+ if (buf == NULL) {
+ printf("Failed to allocate buffer\n");
+ return -ENOMEM;
+ }
+ /* search for first non-bad block in FW1 block range */
+ while (fw1_start_block <= fw1_end_block) {
+ if (!nand_block_isbad(mtd, fw1_start_block * mtd->erasesize))
+ break;
+ fw1_start_block++;
+ }
+ if (fw1_end_block - fw1_start_block + 1 < fw_num_blocks) {
+ printf("Too many bad blocks in FW1 block range: %lu..%lu\n",
+ fw1_end_block + 1 - fw_num_blocks - extra_blocks,
+ fw1_end_block);
+ return -EINVAL;
+ }
+
+ /* search for first non-bad block in FW2 block range */
+ while (fw2_set && fw2_start_block <= fw2_end_block) {
+ if (!nand_block_isbad(mtd, fw2_start_block * mtd->erasesize))
+ break;
+ fw2_start_block++;
+ }
+ if (fw2_end_block - fw2_start_block + 1 < fw_num_blocks) {
+ printf("Too many bad blocks in FW2 area %08lx..%08lx\n",
+ fw2_end_block + 1 - fw_num_blocks - extra_blocks,
+ fw2_end_block);
+ return -EINVAL;
+ }
+
+ fcb = create_fcb(buf, fw1_start_block, fw2_start_block,
+ (fw_num_blocks + extra_blocks) * mtd->erasesize);
+ if (IS_ERR(fcb)) {
+ printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb));
+ return PTR_ERR(fcb);
+ }
+ encode_hamming_13_8(fcb, (void *)fcb + 512, 512);
+
+ for (block = fcb_start_block; block < fcb_start_block + num_fcb_blocks;
+ block++) {
+ if (nand_block_isbad(mtd, block * mtd->erasesize)) {
+ if (block == fcb_start_block)
+ fcb_start_block++;
+ continue;
+ }
+ ret = write_fcb(buf, block);
+ if (ret) {
+ printf("Failed to write FCB to block %u\n", block);
+ return ret;
+ }
+ fcb_written = 1;
+ }
+
+ if (!fcb_written) {
+ printf("Could not write FCB to flash\n");
+ return -EIO;
+ }
+
+ printf("Programming U-Boot image from %p to block %lu\n",
+ addr, fw1_start_block);
+ if (size & (page_size - 1)) {
+ memset(addr + size, 0xff, size & (page_size - 1));
+ size = ALIGN(size, page_size);
+ }
+
+ erase_opts.offset = fcb->fw1_start_page * page_size;
+ erase_opts.length = ALIGN(size, erase_size) +
+ extra_blocks * mtd->erasesize;
+ erase_opts.quiet = 1;
+
+ printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset,
+ erase_opts.offset + erase_opts.length - 1);
+
+ ret = nand_erase_opts(mtd, &erase_opts);
+ if (ret) {
+ printf("Failed to erase flash: %d\n", ret);
+ return ret;
+ }
+ printf("Programming flash @ %08x..%08x from %p\n",
+ fcb->fw1_start_page * page_size,
+ fcb->fw1_start_page * page_size + size, addr);
+ ret = nand_write_skip_bad(mtd, fcb->fw1_start_page * page_size,
+ &size, addr, WITH_DROP_FFS);
+ if (ret) {
+ printf("Failed to program flash: %d\n", ret);
+ return ret;
+ }
+ if (fw2_start_block == 0) {
+ return ret;
+ }
+
+ printf("Programming redundant U-Boot image to block %lu\n",
+ fw2_start_block);
+ erase_opts.offset = fcb->fw2_start_page * page_size;
+ printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset,
+ erase_opts.offset + erase_opts.length - 1);
+
+ ret = nand_erase_opts(mtd, &erase_opts);
+ if (ret) {
+ printf("Failed to erase flash: %d\n", ret);
+ return ret;
+ }
+ printf("Programming flash @ %08x..%08x from %p\n",
+ fcb->fw2_start_page * page_size,
+ fcb->fw2_start_page * page_size + size, addr);
+ ret = nand_write_skip_bad(mtd, fcb->fw2_start_page * page_size,
+ &size, addr, WITH_DROP_FFS);
+ if (ret) {
+ printf("Failed to program flash: %d\n", ret);
+ return ret;
+ }
+ return ret;
+}
+
+U_BOOT_CMD(romupdate, 11, 0, do_update,
+ "Creates an FCB data structure and writes an U-Boot image to flash\n",
+ "[-b #] [-n #] [-f #] [-r [#]] [<address>] [<length>]\n"
+ "\t-b #\tfirst FCB block number (default 0)\n"
+ "\t-n #\ttotal number of FCB blocks (default 1)\n"
+ "\t-f #\twrite bootloader image at block #\n"
+ "\t-r\twrite redundant bootloader image at next free block after first image\n"
+ "\t-r #\twrite redundant bootloader image at block #\n"
+ "\t-e #\tspecify number of redundant blocks per boot loader image\n"
+ "\t<address>\tRAM address of bootloader image (default: ${fileaddr}\n"
+ "\t<length>\tlength of bootloader image in RAM (default: ${filesize}"
+ );
--- /dev/null
+/*
+ * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA)
+#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_GPIO (MXS_PAD_3V3 | MXS_PAD_PULLUP)
+
+static iomux_cfg_t tx28_stk5_pads[] = {
+ /* LED */
+ MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED,
+
+ /* framebuffer */
+ MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_ENABLE__GPIO_1_31 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD,
+
+ /* DUART pads */
+ MX28_PAD_PWM0__GPIO_3_16 | MUX_CONFIG_GPIO,
+ MX28_PAD_PWM1__GPIO_3_17 | MUX_CONFIG_GPIO,
+ MX28_PAD_I2C0_SCL__GPIO_3_24 | MUX_CONFIG_GPIO,
+ MX28_PAD_I2C0_SDA__GPIO_3_25 | MUX_CONFIG_GPIO,
+
+ MX28_PAD_AUART0_RTS__DUART_TX,
+ MX28_PAD_AUART0_CTS__DUART_RX,
+ MX28_PAD_AUART0_TX__DUART_RTS,
+ MX28_PAD_AUART0_RX__DUART_CTS,
+
+ /* EMI */
+ MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+ /* FEC pads */
+ MX28_PAD_PWM4__GPIO_3_29 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RX_EN__GPIO_4_2 | MUX_CONFIG_ENET, /* COL/CRS_DV/MODE2 */
+ MX28_PAD_ENET0_RXD0__GPIO_4_3 | MUX_CONFIG_ENET, /* RXD0/MODE0 */
+ MX28_PAD_ENET0_RXD1__GPIO_4_4 | MUX_CONFIG_ENET, /* RXD1/MODE1 */
+ MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | MUX_CONFIG_ENET, /* nINT/TX_ER/TXD4 */
+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+
+ /* MMC pads */
+ MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | MUX_CONFIG_GPIO,
+ MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0,
+
+ /* GPMI pads */
+ MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDN__GPMI_RDN | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+
+ /* maybe used for EDT-FT5x06 */
+ MX28_PAD_SSP0_DATA5__GPIO_2_5 | MUX_CONFIG_GPIO,
+ MX28_PAD_SSP0_DATA6__GPIO_2_6 | MUX_CONFIG_GPIO,
+ MX28_PAD_ENET0_RXD2__GPIO_4_9 | MUX_CONFIG_GPIO,
+
+ /* unused pads */
+ MX28_PAD_GPMI_RDY1__GPIO_0_21 | MUX_CONFIG_GPIO,
+ MX28_PAD_GPMI_RDY2__GPIO_0_22 | MUX_CONFIG_GPIO,
+ MX28_PAD_GPMI_RDY3__GPIO_0_23 | MUX_CONFIG_GPIO,
+ MX28_PAD_GPMI_CE1N__GPIO_0_17 | MUX_CONFIG_GPIO,
+ MX28_PAD_GPMI_CE2N__GPIO_0_18 | MUX_CONFIG_GPIO,
+ MX28_PAD_GPMI_CE3N__GPIO_0_19 | MUX_CONFIG_GPIO,
+
+ MX28_PAD_SSP0_DATA4__GPIO_2_4 | MUX_CONFIG_GPIO,
+ MX28_PAD_SSP0_DATA7__GPIO_2_7 | MUX_CONFIG_GPIO,
+
+ MX28_PAD_SSP2_SS0__GPIO_2_19 | MUX_CONFIG_GPIO,
+ MX28_PAD_SSP2_SS1__GPIO_2_20 | MUX_CONFIG_GPIO,
+ MX28_PAD_SSP2_SS2__GPIO_2_21 | MUX_CONFIG_GPIO,
+ MX28_PAD_SSP3_SS0__GPIO_2_27 | MUX_CONFIG_GPIO,
+
+ MX28_PAD_ENET0_TXD2__GPIO_4_11 | MUX_CONFIG_GPIO,
+ MX28_PAD_ENET0_TXD3__GPIO_4_12 | MUX_CONFIG_GPIO,
+ MX28_PAD_ENET0_CRS__GPIO_4_15 | MUX_CONFIG_GPIO,
+};
+
+static void tx28_stk5_lcd_init(void)
+{
+ gpio_direction_output(MX28_PAD_PWM0__GPIO_3_16, 1);
+ gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 0);
+ gpio_direction_output(MX28_PAD_LCD_ENABLE__GPIO_1_31, 0);
+}
+
+static void tx28_stk5_led_on(void)
+{
+ gpio_direction_output(MX28_PAD_ENET0_RXD3__GPIO_4_10, 1);
+}
+
+void board_init_ll(void)
+{
+ mxs_common_spl_init(tx28_stk5_pads, ARRAY_SIZE(tx28_stk5_pads));
+ tx28_stk5_lcd_init();
+ tx28_stk5_led_on();
+}
+
+#ifndef CONFIG_TX28_S
+static uint32_t tx28_dram_vals[] = {
+ /* TX28-41x0: NT5TU32M16DG-AC */
+ /* 000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 020 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 030 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 040 */ 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+ /* 050 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x01010101,
+ /* 070 */ 0x000f0f01, 0x0102020a, 0x00000000, 0x00010101,
+ /* 080 */ 0x00000100, 0x00000100, 0x00000000, 0x00000002,
+ /* 090 */ 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
+ /* 0a0 */ 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
+ /* 0b0 */ 0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
+ /* 0c0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+ /* 0d0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+ /* 0e0 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+ /* 0f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 100 */ 0x00000000, 0x00000000, 0x00000612, 0x01000f02,
+ /* 110 */ 0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
+ /* 120 */ 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300,
+ /* 130 */ 0x07400300, 0x07400300, 0x07400300, 0x00000005,
+ /* 140 */ 0x00000000, 0x00000000, 0x01000000, 0x01020408,
+ /* 150 */ 0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
+ /* 160 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
+ /* 170 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
+ /* 180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 280 */ 0x00000000, 0x00000000, 0x00010000, 0x00030404,
+ /* 290 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+ /* 2a0 */ 0x00000000, 0x00000000, 0x00000000, 0x01010000,
+ /* 2b0 */ 0x01000000, 0x03030000, 0x00010303, 0x01020202,
+ /* 2c0 */ 0x00000000, 0x02040303, 0x21002103, 0x00061200,
+ /* 2d0 */ 0x06120612, 0x04420442, 0x04420442, 0x00040004,
+ /* 2e0 */ 0x00040004, 0x00000000, 0x00000000, 0x00000000,
+ /* 2f0 */ 0x00000000, 0x00000000,
+};
+#else
+static uint32_t tx28_dram_vals[] = {
+ /* TX28-40x0: MT47H64M16HR-3 */
+ /* 000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 020 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 030 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 040 */ 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+ /* 050 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x00010101,
+ /* 070 */ 0x000f0f01, 0x0102010a, 0x00000000, 0x00000101,
+ /* 080 */ 0x00000100, 0x00000100, 0x00000000, 0x00000002,
+ /* 090 */ 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
+ /* 0a0 */ 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
+ /* 0b0 */ 0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
+ /* 0c0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+ /* 0d0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+ /* 0e0 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+ /* 0f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 100 */ 0x00000000, 0x00000000, 0x00000612, 0x01000f02,
+ /* 110 */ 0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
+ /* 120 */ 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300,
+ /* 130 */ 0x07400300, 0x07400300, 0x07400300, 0x00000005,
+ /* 140 */ 0x00000000, 0x00000000, 0x01000000, 0x01020408,
+ /* 150 */ 0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
+ /* 160 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
+ /* 170 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
+ /* 180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 280 */ 0x00000000, 0x00000000, 0x00010000, 0x00030404,
+ /* 290 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+ /* 2a0 */ 0x00000000, 0x00000000, 0x00000000, 0x01010000,
+ /* 2b0 */ 0x01000000, 0x03030000, 0x00010303, 0x01020202,
+ /* 2c0 */ 0x00000000, 0x02040303, 0x21002103, 0x00061200,
+ /* 2d0 */ 0x06120612, 0x04420442, 0x04420442, 0x00040004,
+ /* 2e0 */ 0x00040004, 0x00000000, 0x00000000, 0x00000000,
+ /* 2f0 */ 0x00000000, 0x00000000,
+};
+#endif
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ memcpy(dram_vals, tx28_dram_vals, sizeof(tx28_dram_vals));
+}
--- /dev/null
+/*
+ * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <lcd.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <imx_ssp_mmc.h>
+#include <linux/list.h>
+#include <linux/fb.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mxsfb.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#include "../common/karo.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MXS_GPIO_NR(p, o) (((p) << 5) | (o))
+
+#define TX28_LCD_PWR_GPIO MX28_PAD_LCD_ENABLE__GPIO_1_31
+#define TX28_LCD_RST_GPIO MX28_PAD_LCD_RESET__GPIO_3_30
+#define TX28_LCD_BACKLIGHT_GPIO MX28_PAD_PWM0__GPIO_3_16
+
+#define TX28_USBH_VBUSEN_GPIO MX28_PAD_SPDIF__GPIO_3_27
+#define TX28_USBH_OC_GPIO MX28_PAD_JTAG_RTCK__GPIO_4_20
+#define TX28_USBOTG_VBUSEN_GPIO MX28_PAD_GPMI_CE2N__GPIO_0_18
+#define TX28_USBOTG_OC_GPIO MX28_PAD_GPMI_CE3N__GPIO_0_19
+#define TX28_USBOTG_ID_GPIO MX28_PAD_PWM2__GPIO_3_18
+
+#define TX28_LED_GPIO MX28_PAD_ENET0_RXD3__GPIO_4_10
+
+static const struct gpio tx28_gpios[] = {
+ { TX28_USBH_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBH VBUSEN", },
+ { TX28_USBH_OC_GPIO, GPIOF_INPUT, "USBH OC", },
+ { TX28_USBOTG_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUSEN", },
+ { TX28_USBOTG_OC_GPIO, GPIOF_INPUT, "USBOTG OC", },
+ { TX28_USBOTG_ID_GPIO, GPIOF_INPUT, "USBOTG ID", },
+};
+
+static const iomux_cfg_t tx28_pads[] = {
+ /* UART pads */
+#if CONFIG_CONS_INDEX == 0
+ MX28_PAD_AUART0_RX__DUART_CTS,
+ MX28_PAD_AUART0_TX__DUART_RTS,
+ MX28_PAD_AUART0_CTS__DUART_RX,
+ MX28_PAD_AUART0_RTS__DUART_TX,
+#elif CONFIG_CONS_INDEX == 1
+ MX28_PAD_AUART1_RX__AUART1_RX,
+ MX28_PAD_AUART1_TX__AUART1_TX,
+ MX28_PAD_AUART1_CTS__AUART1_CTS,
+ MX28_PAD_AUART1_RTS__AUART1_RTS,
+#elif CONFIG_CONS_INDEX == 2
+ MX28_PAD_AUART3_RX__AUART3_RX,
+ MX28_PAD_AUART3_TX__AUART3_TX,
+ MX28_PAD_AUART3_CTS__AUART3_CTS,
+ MX28_PAD_AUART3_RTS__AUART3_RTS,
+#endif
+ /* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+ /* USBH VBUSEN, OC */
+ MX28_PAD_SPDIF__GPIO_3_27,
+ MX28_PAD_JTAG_RTCK__GPIO_4_20,
+
+ /* USBOTG VBUSEN, OC, ID */
+ MX28_PAD_GPMI_CE2N__GPIO_0_18,
+ MX28_PAD_GPMI_CE3N__GPIO_0_19,
+ MX28_PAD_PWM2__GPIO_3_18,
+};
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mx28_set_ioclk(MXC_IOCLK0, 480000);
+ /* IO1 clock at 480MHz */
+ mx28_set_ioclk(MXC_IOCLK1, 480000);
+
+ /* SSP0 clock at 96MHz */
+ mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
+ /* SSP2 clock at 96MHz */
+ mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
+
+ gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
+ mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads));
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
+ return 0;
+}
+
+int dram_init(void)
+{
+ return mxs_dram_init();
+}
+
+#ifdef CONFIG_CMD_MMC
+static int tx28_mmc_wp(int dev_no)
+{
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ return mxsmmc_initialize(bis, 0, tx28_mmc_wp);
+}
+#endif /* CONFIG_CMD_MMC */
+
+#ifdef CONFIG_FEC_MXC
+#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+
+#ifdef CONFIG_FEC_MXC_MULTI
+#define FEC_MAX_IDX 1
+#else
+#define FEC_MAX_IDX 0
+#endif
+
+static int fec_get_mac_addr(int index)
+{
+ u32 val1, val2;
+ int timeout = 1000;
+ struct mxs_ocotp_regs *ocotp_regs =
+ (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
+ u32 *cust = &ocotp_regs->hw_ocotp_cust0;
+ char mac[6 * 3];
+ char env_name[] = "eth.addr";
+
+ if (index < 0 || index > FEC_MAX_IDX)
+ return -EINVAL;
+
+ /* set this bit to open the OTP banks for reading */
+ writel(OCOTP_CTRL_RD_BANK_OPEN,
+ &ocotp_regs->hw_ocotp_ctrl_set);
+
+ /* wait until OTP contents are readable */
+ while (OCOTP_CTRL_BUSY & readl(&ocotp_regs->hw_ocotp_ctrl)) {
+ if (timeout-- < 0)
+ return -ETIMEDOUT;
+ udelay(100);
+ }
+
+ val1 = readl(&cust[index * 8]);
+ val2 = readl(&cust[index * 8 + 4]);
+ if ((val1 | val2) == 0)
+ return 0;
+ snprintf(mac, sizeof(mac), "%02x:%02x:%02x:%02x:%02x:%02x",
+ (val1 >> 24) & 0xFF, (val1 >> 16) & 0xFF,
+ (val1 >> 8) & 0xFF, (val1 >> 0) & 0xFF,
+ (val2 >> 24) & 0xFF, (val2 >> 16) & 0xFF);
+ if (index == 0)
+ snprintf(env_name, sizeof(env_name), "ethaddr");
+ else
+ snprintf(env_name, sizeof(env_name), "eth%daddr", index);
+
+ setenv(env_name, mac);
+ return 0;
+}
+#endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */
+
+static const iomux_cfg_t tx28_fec_pads[] = {
+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN,
+ MX28_PAD_ENET0_RXD0__ENET0_RXD0,
+ MX28_PAD_ENET0_RXD1__ENET0_RXD1,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+
+ /* Reset the external phy */
+ gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
+
+ /* Power on the external phy */
+ gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1);
+
+ /* Pull strap pins to high */
+ gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1);
+ gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1);
+ gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1);
+ gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5);
+
+ udelay(25000);
+ gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
+ udelay(100);
+
+ mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads));
+
+ ret = cpu_eth_init(bis);
+ if (ret) {
+ printf("cpu_eth_init() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = fec_get_mac_addr(0);
+ if (ret < 0) {
+ printf("Failed to read FEC0 MAC address from OCOTP\n");
+ return ret;
+ }
+#ifdef CONFIG_FEC_MXC_MULTI
+ if (getenv("ethaddr")) {
+ ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC0\n");
+ return ret;
+ }
+ }
+
+ ret = fec_get_mac_addr(1);
+ if (ret < 0) {
+ printf("Failed to read FEC1 MAC address from OCOTP\n");
+ return ret;
+ }
+ if (getenv("eth1addr")) {
+ ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC1\n");
+ return ret;
+ }
+ }
+ return 0;
+#else
+ if (getenv("ethaddr")) {
+ ret = fecmxc_initialize(bis);
+ }
+ return ret;
+#endif
+}
+#endif /* CONFIG_FEC_MXC */
+
+enum {
+ LED_STATE_INIT = -1,
+ LED_STATE_OFF,
+ LED_STATE_ON,
+};
+
+void show_activity(int arg)
+{
+ static int led_state = LED_STATE_INIT;
+ static ulong last;
+
+ if (led_state == LED_STATE_INIT) {
+ last = get_timer(0);
+ gpio_set_value(TX28_LED_GPIO, 1);
+ led_state = LED_STATE_ON;
+ } else {
+ if (get_timer(last) > CONFIG_SYS_HZ) {
+ last = get_timer(0);
+ if (led_state == LED_STATE_ON) {
+ gpio_set_value(TX28_LED_GPIO, 0);
+ } else {
+ gpio_set_value(TX28_LED_GPIO, 1);
+ }
+ led_state = 1 - led_state;
+ }
+ }
+}
+
+static const iomux_cfg_t stk5_pads[] = {
+ /* SW controlled LED on STK5 baseboard */
+ MX28_PAD_ENET0_RXD3__GPIO_4_10,
+};
+
+static const struct gpio stk5_gpios[] = {
+};
+
+#ifdef CONFIG_LCD
+static struct fb_videomode tx28_fb_modes[] = {
+ {
+ /* Standard VGA timing */
+ .name = "VGA",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ {
+ /* Emerging ETV570 640 x 480 display. Syncs low active,
+ * DE high active, 115.2 mm x 86.4 mm display area
+ * VGA compatible timing
+ */
+ .name = "ETV570",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 114,
+ .hsync_len = 30,
+ .right_margin = 16,
+ .upper_margin = 32,
+ .vsync_len = 3,
+ .lower_margin = 10,
+ .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ {
+ /* Emerging ET0350G0DH6 320 x 240 display.
+ * 70.08 mm x 52.56 mm display area.
+ */
+ .name = "ET0350",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6500),
+ .left_margin = 68 - 34,
+ .hsync_len = 34,
+ .right_margin = 20,
+ .upper_margin = 18 - 3,
+ .vsync_len = 3,
+ .lower_margin = 4,
+ .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ {
+ /* Emerging ET0430G0DH6 480 x 272 display.
+ * 95.04 mm x 53.856 mm display area.
+ */
+ .name = "ET0430",
+ .refresh = 60,
+ .xres = 480,
+ .yres = 272,
+ .pixclock = KHZ2PICOS(9000),
+ .left_margin = 2,
+ .hsync_len = 41,
+ .right_margin = 2,
+ .upper_margin = 2,
+ .vsync_len = 10,
+ .lower_margin = 2,
+ .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ {
+ /* Emerging ET0500G0DH6 800 x 480 display.
+ * 109.6 mm x 66.4 mm display area.
+ */
+ .name = "ET0500",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ {
+ /* Emerging ETQ570G0DH6 320 x 240 display.
+ * 115.2 mm x 86.4 mm display area.
+ */
+ .name = "ETQ570",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6400),
+ .left_margin = 38,
+ .hsync_len = 30,
+ .right_margin = 30,
+ .upper_margin = 16, /* 15 according to datasheet */
+ .vsync_len = 3, /* TVP -> 1>x>5 */
+ .lower_margin = 4, /* 4.5 according to datasheet */
+ .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ {
+ /* Emerging ET0700G0DH6 800 x 480 display.
+ * 152.4 mm x 91.44 mm display area.
+ */
+ .name = "ET0700",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 216 - 128,
+ .hsync_len = 128,
+ .right_margin = 1056 - 800 - 216,
+ .upper_margin = 35 - 2,
+ .vsync_len = 2,
+ .lower_margin = 525 - 480 - 35,
+ .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ {
+ /* unnamed entry for assigning parameters parsed from 'video_mode' string */
+ .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+};
+
+static int lcd_enabled = 1;
+
+void lcd_enable(void)
+{
+ /* HACK ALERT:
+ * global variable from common/lcd.c
+ * Set to 0 here to prevent messages from going to LCD
+ * rather than serial console
+ */
+ lcd_is_enabled = 0;
+
+ karo_load_splashimage(1);
+ if (lcd_enabled) {
+ debug("Switching LCD on\n");
+ gpio_set_value(TX28_LCD_PWR_GPIO, 1);
+ udelay(100);
+ gpio_set_value(TX28_LCD_RST_GPIO, 1);
+ udelay(300000);
+ gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 0);
+ }
+}
+
+void lcd_disable(void)
+{
+ mxsfb_disable();
+}
+
+void lcd_panel_disable(void)
+{
+ if (lcd_enabled) {
+ debug("Switching LCD off\n");
+ gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 1);
+ gpio_set_value(TX28_LCD_RST_GPIO, 0);
+ gpio_set_value(TX28_LCD_PWR_GPIO, 0);
+ }
+}
+
+static const iomux_cfg_t stk5_lcd_pads[] = {
+ /* LCD RESET */
+ MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
+ /* LCD POWER_ENABLE */
+ MX28_PAD_LCD_ENABLE__GPIO_1_31 | MXS_PAD_CTRL,
+ /* LCD Backlight (PWM) */
+ MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
+
+ /* Display */
+ MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
+ MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
+ MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
+ MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
+ MX28_PAD_LCD_CS__LCD_CS | MXS_PAD_CTRL,
+ MX28_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL,
+ MX28_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL,
+ MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL,
+};
+
+static const struct gpio stk5_lcd_gpios[] = {
+ { TX28_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
+ { TX28_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
+ { TX28_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+};
+
+extern void video_hw_init(void *lcdbase);
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ int color_depth = 24;
+ char *vm;
+ unsigned long val;
+ int refresh = 60;
+ struct fb_videomode *p = &tx28_fb_modes[0];
+ int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
+
+ if (!lcd_enabled) {
+ debug("LCD disabled\n");
+ return;
+ }
+
+ if (tstc()) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ return;
+ }
+
+ vm = getenv("video_mode");
+ if (vm == NULL) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ return;
+ }
+ while (p->name != NULL) {
+ if (strcmp(p->name, vm) == 0) {
+ printf("Using video mode: '%s'\n", p->name);
+ vm += strlen(vm);
+ break;
+ }
+ p++;
+ }
+
+ while (*vm != '\0') {
+ if (*vm >= '0' && *vm <= '9') {
+ char *end;
+
+ val = simple_strtoul(vm, &end, 0);
+ if (end > vm) {
+ if (!xres_set) {
+ if (val > panel_info.vl_col)
+ val = panel_info.vl_col;
+ p->xres = val;
+ xres_set = 1;
+ } else if (!yres_set) {
+ if (val > panel_info.vl_row)
+ val = panel_info.vl_row;
+ p->yres = val;
+ yres_set = 1;
+ } else if (!bpp_set) {
+ switch (val) {
+ case 8:
+ case 16:
+ case 18:
+ case 24:
+ color_depth = val;
+ break;
+
+ default:
+ printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
+ end - vm, vm, color_depth);
+ }
+ bpp_set = 1;
+ } else if (!refresh_set) {
+ refresh = val;
+ refresh_set = 1;
+ }
+ }
+ vm = end;
+ }
+ switch (*vm) {
+ case '@':
+ bpp_set = 1;
+ /* fallthru */
+ case '-':
+ yres_set = 1;
+ /* fallthru */
+ case 'x':
+ xres_set = 1;
+ /* fallthru */
+ case 'M':
+ case 'R':
+ vm++;
+ break;
+
+ default:
+ if (*vm != '\0')
+ vm++;
+ }
+ }
+ if (p->xres == 0 || p->yres == 0) {
+ printf("Invalid video mode: %s\n", getenv("video_mode"));
+ lcd_enabled = 0;
+ printf("Supported video modes are:");
+ for (p = &tx28_fb_modes[0]; p->name != NULL; p++) {
+ printf(" %s", p->name);
+ }
+ printf("\n");
+ return;
+ }
+ p->pixclock = KHZ2PICOS(refresh *
+ (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
+ (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
+ 1000);
+ debug("Pixel clock set to %lu.%03lu MHz\n",
+ PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
+
+ gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
+ mxs_iomux_setup_multiple_pads(stk5_lcd_pads,
+ ARRAY_SIZE(stk5_lcd_pads));
+
+ debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
+ color_depth, refresh);
+
+ if (karo_load_splashimage(0) == 0) {
+ debug("Initializing LCD controller\n");
+ mxsfb_init(p, PIX_FMT_RGB24, color_depth);
+ video_hw_init(lcdbase);
+ } else {
+ debug("Skipping initialization of LCD controller\n");
+ }
+}
+#else
+#define lcd_enabled 0
+#endif /* CONFIG_LCD */
+
+static void stk5_board_init(void)
+{
+ gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
+ mxs_iomux_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
+}
+
+static void stk5v3_board_init(void)
+{
+ stk5_board_init();
+}
+
+static void stk5v5_board_init(void)
+{
+ stk5_board_init();
+
+ /* init flexcan transceiver enable GPIO */
+ gpio_request_one(MXS_GPIO_NR(0, 1), GPIOF_OUTPUT_INIT_HIGH,
+ "Flexcan Transceiver");
+ mxs_iomux_setup_pad(MX28_PAD_LCD_D00__GPIO_1_0);
+}
+
+int board_late_init(void)
+{
+ const char *baseboard;
+
+ karo_fdt_move_fdt();
+
+ baseboard = getenv("baseboard");
+ if (!baseboard)
+ return 0;
+
+ if (strncmp(baseboard, "stk5", 4) == 0) {
+ printf("Baseboard: %s\n", baseboard);
+ if ((strlen(baseboard) == 4) ||
+ strcmp(baseboard, "stk5-v3") == 0) {
+ stk5v3_board_init();
+ } else if (strcmp(baseboard, "stk5-v5") == 0) {
+ stk5v5_board_init();
+ } else {
+ printf("WARNING: Unsupported STK5 board rev.: %s\n",
+ baseboard + 4);
+ }
+ } else {
+ printf("WARNING: Unsupported baseboard: '%s'\n",
+ baseboard);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: Ka-Ro TX28-4%sxx\n", TX28_MOD_SUFFIX);
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+#include <jffs2/jffs2.h>
+#include <mtd_node.h>
+struct node_info tx28_nand_nodes[] = {
+ { "gpmi-nand", MTD_DEV_TYPE_NAND, },
+};
+#else
+#define fdt_fixup_mtdparts(b,n,c) do { } while (0)
+#endif
+
+static void tx28_fixup_flexcan(void *blob)
+{
+ karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x80032000, "transceiver-switch");
+ karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x80034000, "transceiver-switch");
+}
+
+static void tx28_fixup_fec(void *blob)
+{
+ karo_fdt_remove_node(blob, "ethernet1");
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ const char *baseboard = getenv("baseboard");
+
+#ifdef CONFIG_TX28_S
+ /* TX28-41xx (aka TX28S) has no external RTC
+ * and no I2C GPIO extender
+ */
+ karo_fdt_remove_node(blob, "ds1339");
+ karo_fdt_remove_node(blob, "pca9554");
+#endif
+ if (baseboard != NULL && strcmp(baseboard, "stk5-v5") == 0) {
+ const char *otg_mode = getenv("otg_mode");
+
+ if (otg_mode && strcmp(otg_mode, "host") == 0) {
+ printf("otg_mode=%s incompatible with baseboard %s\n",
+ otg_mode, baseboard);
+ setenv(otg_mode, "none");
+ }
+ karo_fdt_remove_node(blob, "stk5led");
+ } else {
+ tx28_fixup_flexcan(blob);
+ tx28_fixup_fec(blob);
+ }
+
+ if (baseboard != NULL && strcmp(baseboard, "stk5-v3") == 0) {
+ const char *otg_mode = getenv("otg_mode");
+
+ if (otg_mode && strcmp(otg_mode, "device") == 0)
+ karo_fdt_remove_node(blob, "can1");
+ }
+
+ fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes));
+ fdt_fixup_ethernet(blob);
+
+ karo_fdt_fixup_touchpanel(blob);
+ karo_fdt_fixup_usb_otg(blob, "fsl,imx28-usbphy", 0x8007c000);
+}
+#endif
--- /dev/null
+sources {
+ u_boot_spl="@@BUILD_DIR@@spl/u-boot-spl";
+ u_boot="@@BUILD_DIR@@u-boot";
+}
+
+section (0) {
+ load u_boot_spl;
+ load ivt (entry = u_boot_spl:reset) > 0x8000;
+ hab call 0x8000;
+
+ load u_boot;
+ load ivt (entry = u_boot:reset) > 0x8000;
+ hab call 0x8000;
+}
--- /dev/null
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation version 2.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+ifeq ($(CONFIG_SPL_BUILD),)
+ COBJS := tx48.o
+else
+ COBJS := spl.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+CONFIG_SYS_TEXT_BASE = 0x80800000
+ifneq ($(CONFIG_SPL_BUILD),)
+ CONFIG_SPL_TEXT_BASE = 0x402F0400
+endif
+PLATFORM_CPPFLAGS += -Werror
+PLATFORM_CPPFLAGS += -DDEBUG
+
+LOGO_BMP = logos/karo.bmp
--- /dev/null
+/*
+ * board/karo/tx48/spl.c
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <serial.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <nand.h>
+#include <net.h>
+#include <spl.h>
+#include <linux/mtd/nand.h>
+#include <asm/gpio.h>
+#include <asm/cache.h>
+#include <asm/omap_common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/nand.h>
+#include <asm/arch/clock.h>
+#include <video_fb.h>
+#include <asm/arch/da8xx-fb.h>
+
+#define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26)
+#define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8)
+#define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19)
+#define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22)
+#define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14)
+
+#define GMII_SEL (CTRL_BASE + 0x650)
+
+/* UART Defines */
+#define UART_SYSCFG_OFFSET 0x54
+#define UART_SYSSTS_OFFSET 0x58
+
+#define UART_RESET (0x1 << 1)
+#define UART_CLK_RUNNING_MASK 0x1
+#define UART_SMART_IDLE_EN (0x1 << 0x3)
+
+/* Timer Defines */
+#define TSICR_REG 0x54
+#define TIOCP_CFG_REG 0x10
+#define TCLR_REG 0x38
+
+/* RGMII mode define */
+#define RGMII_MODE_ENABLE 0xA
+#define RMII_MODE_ENABLE 0x5
+#define MII_MODE_ENABLE 0x0
+
+#define NO_OF_MAC_ADDR 1
+#define ETH_ALEN 6
+
+#define MUX_CFG(value, offset) { \
+ __raw_writel(value, (CTRL_BASE + (offset))); \
+ }
+
+/* PAD Control Fields */
+#define SLEWCTRL (0x1 << 6)
+#define RXACTIVE (0x1 << 5)
+#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
+#define PULLUDEN (0x0 << 3) /* Pull up enabled */
+#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
+#define MODE(val) (val)
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+ int gpmc_ad0;
+ int gpmc_ad1;
+ int gpmc_ad2;
+ int gpmc_ad3;
+ int gpmc_ad4;
+ int gpmc_ad5;
+ int gpmc_ad6;
+ int gpmc_ad7;
+ int gpmc_ad8;
+ int gpmc_ad9;
+ int gpmc_ad10;
+ int gpmc_ad11;
+ int gpmc_ad12;
+ int gpmc_ad13;
+ int gpmc_ad14;
+ int gpmc_ad15;
+ int gpmc_a0;
+ int gpmc_a1;
+ int gpmc_a2;
+ int gpmc_a3;
+ int gpmc_a4;
+ int gpmc_a5;
+ int gpmc_a6;
+ int gpmc_a7;
+ int gpmc_a8;
+ int gpmc_a9;
+ int gpmc_a10;
+ int gpmc_a11;
+ int gpmc_wait0;
+ int gpmc_wpn;
+ int gpmc_be1n;
+ int gpmc_csn0;
+ int gpmc_csn1;
+ int gpmc_csn2;
+ int gpmc_csn3;
+ int gpmc_clk;
+ int gpmc_advn_ale;
+ int gpmc_oen_ren;
+ int gpmc_wen;
+ int gpmc_be0n_cle;
+ int lcd_data0;
+ int lcd_data1;
+ int lcd_data2;
+ int lcd_data3;
+ int lcd_data4;
+ int lcd_data5;
+ int lcd_data6;
+ int lcd_data7;
+ int lcd_data8;
+ int lcd_data9;
+ int lcd_data10;
+ int lcd_data11;
+ int lcd_data12;
+ int lcd_data13;
+ int lcd_data14;
+ int lcd_data15;
+ int lcd_vsync;
+ int lcd_hsync;
+ int lcd_pclk;
+ int lcd_ac_bias_en;
+ int mmc0_dat3;
+ int mmc0_dat2;
+ int mmc0_dat1;
+ int mmc0_dat0;
+ int mmc0_clk;
+ int mmc0_cmd;
+ int mii1_col;
+ int mii1_crs;
+ int mii1_rxerr;
+ int mii1_txen;
+ int mii1_rxdv;
+ int mii1_txd3;
+ int mii1_txd2;
+ int mii1_txd1;
+ int mii1_txd0;
+ int mii1_txclk;
+ int mii1_rxclk;
+ int mii1_rxd3;
+ int mii1_rxd2;
+ int mii1_rxd1;
+ int mii1_rxd0;
+ int rmii1_refclk;
+ int mdio_data;
+ int mdio_clk;
+ int spi0_sclk;
+ int spi0_d0;
+ int spi0_d1;
+ int spi0_cs0;
+ int spi0_cs1;
+ int ecap0_in_pwm0_out;
+ int uart0_ctsn;
+ int uart0_rtsn;
+ int uart0_rxd;
+ int uart0_txd;
+ int uart1_ctsn;
+ int uart1_rtsn;
+ int uart1_rxd;
+ int uart1_txd;
+ int i2c0_sda;
+ int i2c0_scl;
+ int mcasp0_aclkx;
+ int mcasp0_fsx;
+ int mcasp0_axr0;
+ int mcasp0_ahclkr;
+ int mcasp0_aclkr;
+ int mcasp0_fsr;
+ int mcasp0_axr1;
+ int mcasp0_ahclkx;
+ int xdma_event_intr0;
+ int xdma_event_intr1;
+ int nresetin_out;
+ int porz;
+ int nnmi;
+ int osc0_in;
+ int osc0_out;
+ int rsvd1;
+ int tms;
+ int tdi;
+ int tdo;
+ int tck;
+ int ntrst;
+ int emu0;
+ int emu1;
+ int osc1_in;
+ int osc1_out;
+ int pmic_power_en;
+ int rtc_porz;
+ int rsvd2;
+ int ext_wakeup;
+ int enz_kaldo_1p8v;
+ int usb0_dm;
+ int usb0_dp;
+ int usb0_ce;
+ int usb0_id;
+ int usb0_vbus;
+ int usb0_drvvbus;
+ int usb1_dm;
+ int usb1_dp;
+ int usb1_ce;
+ int usb1_id;
+ int usb1_vbus;
+ int usb1_drvvbus;
+ int ddr_resetn;
+ int ddr_csn0;
+ int ddr_cke;
+ int ddr_ck;
+ int ddr_nck;
+ int ddr_casn;
+ int ddr_rasn;
+ int ddr_wen;
+ int ddr_ba0;
+ int ddr_ba1;
+ int ddr_ba2;
+ int ddr_a0;
+ int ddr_a1;
+ int ddr_a2;
+ int ddr_a3;
+ int ddr_a4;
+ int ddr_a5;
+ int ddr_a6;
+ int ddr_a7;
+ int ddr_a8;
+ int ddr_a9;
+ int ddr_a10;
+ int ddr_a11;
+ int ddr_a12;
+ int ddr_a13;
+ int ddr_a14;
+ int ddr_a15;
+ int ddr_odt;
+ int ddr_d0;
+ int ddr_d1;
+ int ddr_d2;
+ int ddr_d3;
+ int ddr_d4;
+ int ddr_d5;
+ int ddr_d6;
+ int ddr_d7;
+ int ddr_d8;
+ int ddr_d9;
+ int ddr_d10;
+ int ddr_d11;
+ int ddr_d12;
+ int ddr_d13;
+ int ddr_d14;
+ int ddr_d15;
+ int ddr_dqm0;
+ int ddr_dqm1;
+ int ddr_dqs0;
+ int ddr_dqsn0;
+ int ddr_dqs1;
+ int ddr_dqsn1;
+ int ddr_vref;
+ int ddr_vtp;
+ int ddr_strben0;
+ int ddr_strben1;
+ int ain7;
+ int ain6;
+ int ain5;
+ int ain4;
+ int ain3;
+ int ain2;
+ int ain1;
+ int ain0;
+ int vrefp;
+ int vrefn;
+};
+
+struct pin_mux {
+ short reg_offset;
+ uint8_t val;
+};
+
+#define PAD_CTRL_BASE 0x800
+#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
+ (PAD_CTRL_BASE))->x)
+
+static struct pin_mux tx48_pins[] = {
+#ifdef CONFIG_CMD_NAND
+ { OFFSET(gpmc_ad0), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD0 */
+ { OFFSET(gpmc_ad1), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD1 */
+ { OFFSET(gpmc_ad2), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD2 */
+ { OFFSET(gpmc_ad3), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD3 */
+ { OFFSET(gpmc_ad4), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD4 */
+ { OFFSET(gpmc_ad5), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD5 */
+ { OFFSET(gpmc_ad6), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD6 */
+ { OFFSET(gpmc_ad7), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD7 */
+ { OFFSET(gpmc_wait0), MODE(0) | RXACTIVE | PULLUP_EN, }, /* NAND WAIT */
+ { OFFSET(gpmc_wpn), MODE(7) | PULLUP_EN | RXACTIVE, }, /* NAND_WPN */
+ { OFFSET(gpmc_csn0), MODE(0) | PULLUDEN, }, /* NAND_CS0 */
+ { OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN, }, /* NAND_ADV_ALE */
+ { OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN, }, /* NAND_OE */
+ { OFFSET(gpmc_wen), MODE(0) | PULLUDEN, }, /* NAND_WEN */
+ { OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN, }, /* NAND_BE_CLE */
+#endif
+ /* I2C0 */
+ { OFFSET(i2c0_sda), MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, }, /* I2C_DATA */
+ { OFFSET(i2c0_scl), MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, }, /* I2C_SCLK */
+
+#ifndef CONFIG_NO_ETH
+ /* RMII1 */
+ { OFFSET(mii1_crs), MODE(1) | RXACTIVE, }, /* RMII1_CRS */
+ { OFFSET(mii1_rxerr), MODE(1) | RXACTIVE | PULLUDEN, }, /* RMII1_RXERR */
+ { OFFSET(mii1_txen), MODE(1), }, /* RMII1_TXEN */
+ { OFFSET(mii1_txd1), MODE(1), }, /* RMII1_TXD1 */
+ { OFFSET(mii1_txd0), MODE(1), }, /* RMII1_TXD0 */
+ { OFFSET(mii1_rxd1), MODE(1) | RXACTIVE | PULLUP_EN, }, /* RMII1_RXD1 */
+ { OFFSET(mii1_rxd0), MODE(1) | RXACTIVE | PULLUP_EN, }, /* RMII1_RXD0 */
+ { OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN, }, /* MDIO_DATA */
+ { OFFSET(mdio_clk), MODE(0) | PULLUP_EN, }, /* MDIO_CLK */
+ { OFFSET(rmii1_refclk), MODE(0) | RXACTIVE, }, /* RMII1_REFCLK */
+ { OFFSET(emu0), MODE(7) | RXACTIVE}, /* nINT */
+ { OFFSET(emu1), MODE(7), }, /* nRST */
+#endif
+};
+
+static struct gpio tx48_gpios[] = {
+ /* configure this pin early to prevent flicker of the LCD */
+ { TX48_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+};
+
+static struct pin_mux tx48_mmc_pins[] = {
+#ifdef CONFIG_OMAP_HSMMC
+ /* MMC1 */
+ { OFFSET(mii1_rxd2), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT3 */
+ { OFFSET(mii1_rxd3), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT2 */
+ { OFFSET(mii1_rxclk), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT1 */
+ { OFFSET(mii1_txclk), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT0 */
+ { OFFSET(gpmc_csn1), MODE(2) | RXACTIVE | PULLUP_EN, }, /* MMC1_CLK */
+ { OFFSET(gpmc_csn2), MODE(2) | RXACTIVE | PULLUP_EN, }, /* MMC1_CMD */
+ { OFFSET(mcasp0_fsx), MODE(4) | RXACTIVE, }, /* MMC1_CD */
+#endif
+};
+
+/*
+ * Configure the pin mux for the module
+ */
+static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
+ int num_pins)
+{
+ int i;
+
+ for (i = 0; i < num_pins; i++)
+ MUX_CFG(pin_mux[i].val, pin_mux[i].reg_offset);
+}
+
+static struct pin_mux tx48_uart0_pins[] = {
+#ifdef CONFIG_SYS_NS16550_COM1
+ /* UART0 for early boot messages */
+ { OFFSET(uart0_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART0_RXD */
+ { OFFSET(uart0_txd), MODE(0) | PULLUDEN, }, /* UART0_TXD */
+ { OFFSET(uart0_ctsn), MODE(0) | PULLUP_EN | RXACTIVE, },/* UART0_CTS */
+ { OFFSET(uart0_rtsn), MODE(0) | PULLUDEN, }, /* UART0_RTS */
+#endif
+#ifdef CONFIG_SYS_NS16550_COM2
+ /* UART1 */
+ { OFFSET(uart1_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART1_RXD */
+ { OFFSET(uart1_txd), MODE(0) | PULLUDEN, }, /* UART1_TXD */
+ { OFFSET(uart1_ctsn), MODE(0) | PULLUP_EN | RXACTIVE, },/* UART1_CTS */
+ { OFFSET(uart1_rtsn), MODE(0) | PULLUDEN, }, /* UART1_RTS */
+#endif
+#ifdef CONFIG_SYS_NS16550_COM3
+ /* UART5 */
+ { OFFSET(mii1_rxdv), MODE(3) | PULLUP_EN | RXACTIVE, }, /* UART5_RXD */
+ { OFFSET(mii1_col), MODE(3) | PULLUDEN, }, /* UART5_TXD */
+ { OFFSET(mmc0_dat1), MODE(2) | PULLUP_EN | RXACTIVE, }, /* UART5_CTS */
+ { OFFSET(mmc0_dat0), MODE(2) | PULLUDEN, }, /* UART5_RTS */
+#endif
+};
+
+/*
+ * early system init of muxing and clocks.
+ */
+void enable_uart0_pin_mux(void)
+{
+ tx48_set_pin_mux(tx48_uart0_pins, ARRAY_SIZE(tx48_uart0_pins));
+}
+
+void enable_mmc0_pin_mux(void)
+{
+ tx48_set_pin_mux(tx48_mmc_pins, ARRAY_SIZE(tx48_mmc_pins));
+}
+
+static const struct ddr_data tx48_ddr3_data = {
+ .datardsratio0 = MT41J128MJT125_RD_DQS,
+ .datawdsratio0 = MT41J128MJT125_WR_DQS,
+ .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
+ .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control tx48_ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41J128MJT125_RATIO,
+ .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
+ .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41J128MJT125_RATIO,
+ .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
+ .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41J128MJT125_RATIO,
+ .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
+ .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
+};
+
+static struct emif_regs tx48_ddr3_emif_reg_data = {
+ .sdram_config = MT41J128MJT125_EMIF_SDCFG,
+ .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
+ .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
+ .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
+ .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
+ .zq_config = MT41J128MJT125_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
+};
+
+void s_init(void)
+{
+#ifndef CONFIG_HW_WATCHDOG
+ struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+ /* WDT1 is already running when the bootloader gets control
+ * Disable it to avoid "random" resets
+ */
+ writel(0xAAAA, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+ writel(0x5555, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+#endif
+ /* Setup the PLLs and the clocks for the peripherals */
+ pll_init();
+
+ /* UART softreset */
+ u32 regVal;
+ struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+
+ enable_uart0_pin_mux();
+
+ regVal = readl(&uart_base->uartsyscfg);
+ regVal |= UART_RESET;
+ writel(regVal, &uart_base->uartsyscfg);
+ while ((readl(&uart_base->uartsyssts) &
+ UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+ ;
+
+ /* Disable smart idle */
+ regVal = readl(&uart_base->uartsyscfg);
+ regVal |= UART_SMART_IDLE_EN;
+ writel(regVal, &uart_base->uartsyscfg);
+
+ /* Initialize the Timer */
+ timer_init();
+
+ preloader_console_init();
+
+ config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &tx48_ddr3_data,
+ &tx48_ddr3_cmd_ctrl_data, &tx48_ddr3_emif_reg_data);
+
+ /* Enable MMC0 */
+ enable_mmc0_pin_mux();
+
+ gpio_request_array(tx48_gpios, ARRAY_SIZE(tx48_gpios));
+ tx48_set_pin_mux(tx48_pins, ARRAY_SIZE(tx48_pins));
+}
--- /dev/null
+/*
+ * tx48.c
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * based on evm.c
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <serial.h>
+#include <libfdt.h>
+#include <lcd.h>
+#include <fdt_support.h>
+#include <nand.h>
+#include <net.h>
+#include <linux/mtd/nand.h>
+#include <asm/gpio.h>
+#include <asm/cache.h>
+#include <asm/omap_common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/nand.h>
+#include <asm/arch/clock.h>
+#include <video_fb.h>
+#include <asm/arch/da8xx-fb.h>
+
+#include "../common/karo.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26)
+#define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8)
+#define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19)
+#define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22)
+#define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14)
+
+#define GMII_SEL (CTRL_BASE + 0x650)
+
+/* UART Defines */
+#define UART_SYSCFG_OFFSET 0x54
+#define UART_SYSSTS_OFFSET 0x58
+
+#define UART_RESET (0x1 << 1)
+#define UART_CLK_RUNNING_MASK 0x1
+#define UART_SMART_IDLE_EN (0x1 << 0x3)
+
+/* Timer Defines */
+#define TSICR_REG 0x54
+#define TIOCP_CFG_REG 0x10
+#define TCLR_REG 0x38
+
+/* RGMII mode define */
+#define RGMII_MODE_ENABLE 0xA
+#define RMII_MODE_ENABLE 0x5
+#define MII_MODE_ENABLE 0x0
+
+#define NO_OF_MAC_ADDR 1
+#define ETH_ALEN 6
+
+#define MUX_CFG(value, offset) { \
+ __raw_writel(value, (CTRL_BASE + (offset))); \
+ }
+
+/* PAD Control Fields */
+#define SLEWCTRL (0x1 << 6)
+#define RXACTIVE (0x1 << 5)
+#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
+#define PULLUDEN (0x0 << 3) /* Pull up enabled */
+#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
+#define MODE(val) (val)
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+ int gpmc_ad0;
+ int gpmc_ad1;
+ int gpmc_ad2;
+ int gpmc_ad3;
+ int gpmc_ad4;
+ int gpmc_ad5;
+ int gpmc_ad6;
+ int gpmc_ad7;
+ int gpmc_ad8;
+ int gpmc_ad9;
+ int gpmc_ad10;
+ int gpmc_ad11;
+ int gpmc_ad12;
+ int gpmc_ad13;
+ int gpmc_ad14;
+ int gpmc_ad15;
+ int gpmc_a0;
+ int gpmc_a1;
+ int gpmc_a2;
+ int gpmc_a3;
+ int gpmc_a4;
+ int gpmc_a5;
+ int gpmc_a6;
+ int gpmc_a7;
+ int gpmc_a8;
+ int gpmc_a9;
+ int gpmc_a10;
+ int gpmc_a11;
+ int gpmc_wait0;
+ int gpmc_wpn;
+ int gpmc_be1n;
+ int gpmc_csn0;
+ int gpmc_csn1;
+ int gpmc_csn2;
+ int gpmc_csn3;
+ int gpmc_clk;
+ int gpmc_advn_ale;
+ int gpmc_oen_ren;
+ int gpmc_wen;
+ int gpmc_be0n_cle;
+ int lcd_data0;
+ int lcd_data1;
+ int lcd_data2;
+ int lcd_data3;
+ int lcd_data4;
+ int lcd_data5;
+ int lcd_data6;
+ int lcd_data7;
+ int lcd_data8;
+ int lcd_data9;
+ int lcd_data10;
+ int lcd_data11;
+ int lcd_data12;
+ int lcd_data13;
+ int lcd_data14;
+ int lcd_data15;
+ int lcd_vsync;
+ int lcd_hsync;
+ int lcd_pclk;
+ int lcd_ac_bias_en;
+ int mmc0_dat3;
+ int mmc0_dat2;
+ int mmc0_dat1;
+ int mmc0_dat0;
+ int mmc0_clk;
+ int mmc0_cmd;
+ int mii1_col;
+ int mii1_crs;
+ int mii1_rxerr;
+ int mii1_txen;
+ int mii1_rxdv;
+ int mii1_txd3;
+ int mii1_txd2;
+ int mii1_txd1;
+ int mii1_txd0;
+ int mii1_txclk;
+ int mii1_rxclk;
+ int mii1_rxd3;
+ int mii1_rxd2;
+ int mii1_rxd1;
+ int mii1_rxd0;
+ int rmii1_refclk;
+ int mdio_data;
+ int mdio_clk;
+ int spi0_sclk;
+ int spi0_d0;
+ int spi0_d1;
+ int spi0_cs0;
+ int spi0_cs1;
+ int ecap0_in_pwm0_out;
+ int uart0_ctsn;
+ int uart0_rtsn;
+ int uart0_rxd;
+ int uart0_txd;
+ int uart1_ctsn;
+ int uart1_rtsn;
+ int uart1_rxd;
+ int uart1_txd;
+ int i2c0_sda;
+ int i2c0_scl;
+ int mcasp0_aclkx;
+ int mcasp0_fsx;
+ int mcasp0_axr0;
+ int mcasp0_ahclkr;
+ int mcasp0_aclkr;
+ int mcasp0_fsr;
+ int mcasp0_axr1;
+ int mcasp0_ahclkx;
+ int xdma_event_intr0;
+ int xdma_event_intr1;
+ int nresetin_out;
+ int porz;
+ int nnmi;
+ int osc0_in;
+ int osc0_out;
+ int rsvd1;
+ int tms;
+ int tdi;
+ int tdo;
+ int tck;
+ int ntrst;
+ int emu0;
+ int emu1;
+ int osc1_in;
+ int osc1_out;
+ int pmic_power_en;
+ int rtc_porz;
+ int rsvd2;
+ int ext_wakeup;
+ int enz_kaldo_1p8v;
+ int usb0_dm;
+ int usb0_dp;
+ int usb0_ce;
+ int usb0_id;
+ int usb0_vbus;
+ int usb0_drvvbus;
+ int usb1_dm;
+ int usb1_dp;
+ int usb1_ce;
+ int usb1_id;
+ int usb1_vbus;
+ int usb1_drvvbus;
+ int ddr_resetn;
+ int ddr_csn0;
+ int ddr_cke;
+ int ddr_ck;
+ int ddr_nck;
+ int ddr_casn;
+ int ddr_rasn;
+ int ddr_wen;
+ int ddr_ba0;
+ int ddr_ba1;
+ int ddr_ba2;
+ int ddr_a0;
+ int ddr_a1;
+ int ddr_a2;
+ int ddr_a3;
+ int ddr_a4;
+ int ddr_a5;
+ int ddr_a6;
+ int ddr_a7;
+ int ddr_a8;
+ int ddr_a9;
+ int ddr_a10;
+ int ddr_a11;
+ int ddr_a12;
+ int ddr_a13;
+ int ddr_a14;
+ int ddr_a15;
+ int ddr_odt;
+ int ddr_d0;
+ int ddr_d1;
+ int ddr_d2;
+ int ddr_d3;
+ int ddr_d4;
+ int ddr_d5;
+ int ddr_d6;
+ int ddr_d7;
+ int ddr_d8;
+ int ddr_d9;
+ int ddr_d10;
+ int ddr_d11;
+ int ddr_d12;
+ int ddr_d13;
+ int ddr_d14;
+ int ddr_d15;
+ int ddr_dqm0;
+ int ddr_dqm1;
+ int ddr_dqs0;
+ int ddr_dqsn0;
+ int ddr_dqs1;
+ int ddr_dqsn1;
+ int ddr_vref;
+ int ddr_vtp;
+ int ddr_strben0;
+ int ddr_strben1;
+ int ain7;
+ int ain6;
+ int ain5;
+ int ain4;
+ int ain3;
+ int ain2;
+ int ain1;
+ int ain0;
+ int vrefp;
+ int vrefn;
+};
+
+struct pin_mux {
+ short reg_offset;
+ uint8_t val;
+};
+
+#define PAD_CTRL_BASE 0x800
+#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
+ (PAD_CTRL_BASE))->x)
+
+/*
+ * Configure the pin mux for the module
+ */
+static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
+ int num_pins)
+{
+ int i;
+
+ for (i = 0; i < num_pins; i++)
+ MUX_CFG(pin_mux[i].val, pin_mux[i].reg_offset);
+}
+
+#define PRM_RSTST_GLOBAL_COLD_RST (1 << 0)
+#define PRM_RSTST_GLOBAL_WARM_SW_RST (1 << 1)
+#define PRM_RSTST_WDT1_RST (1 << 4)
+#define PRM_RSTST_EXTERNAL_WARM_RST (1 << 5)
+#define PRM_RSTST_ICEPICK_RST (1 << 9)
+
+struct prm_device {
+ unsigned int prmrstctrl; /* offset 0x00 */
+ unsigned int prmrsttime; /* offset 0x04 */
+ unsigned int prmrstst; /* offset 0x08 */
+ /* ... */
+};
+
+static u32 prm_rstst __attribute__((section(".data")));
+
+/*
+ * Basic board specific setup
+ */
+static const struct pin_mux stk5_pads[] = {
+ /* heartbeat LED */
+ { OFFSET(gpmc_a10), MODE(7) | PULLUDEN, },
+ /* LCD RESET */
+ { OFFSET(gpmc_a3), MODE(7) | PULLUDEN, },
+ /* LCD POWER_ENABLE */
+ { OFFSET(gpmc_a6), MODE(7) | PULLUDEN, },
+ /* LCD Backlight (PWM) */
+ { OFFSET(mcasp0_aclkx), MODE(7) | PULLUDEN, },
+};
+
+static const struct pin_mux stk5_lcd_pads[] = {
+ /* LCD data bus */
+ { OFFSET(lcd_data0), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data1), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data2), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data3), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data4), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data5), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data6), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data7), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data8), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data9), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data10), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data11), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data12), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data13), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data14), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_data15), MODE(0) | PULLUDEN, },
+ /* LCD control signals */
+ { OFFSET(lcd_hsync), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_vsync), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_pclk), MODE(0) | PULLUDEN, },
+ { OFFSET(lcd_ac_bias_en), MODE(0) | PULLUDEN, },
+};
+
+static const struct gpio stk5_gpios[] = {
+ { AM33XX_GPIO_NR(1, 26), GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
+};
+
+static const struct gpio stk5_lcd_gpios[] = {
+ { AM33XX_GPIO_NR(1, 19), GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
+ { AM33XX_GPIO_NR(1, 22), GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
+ { AM33XX_GPIO_NR(3, 14), GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+};
+
+static const struct pin_mux stk5v5_pads[] = {
+ /* CAN transceiver control */
+ { OFFSET(gpmc_ad8), MODE(7) | PULLUDEN, },
+};
+
+static const struct gpio stk5v5_gpios[] = {
+ { AM33XX_GPIO_NR(0, 22), GPIOF_OUTPUT_INIT_HIGH, "CAN XCVR", },
+};
+
+#ifdef CONFIG_LCD
+static u16 tx48_cmap[256];
+vidinfo_t panel_info = {
+ /* set to max. size supported by SoC */
+ .vl_col = 1366,
+ .vl_row = 768,
+
+ .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+ .cmap = tx48_cmap,
+};
+
+static struct da8xx_panel tx48_lcd_panel = {
+ .name = "640x480MR@60",
+ .width = 640,
+ .height = 480,
+ .hfp = 12,
+ .hbp = 144,
+ .hsw = 30,
+ .vfp = 10,
+ .vbp = 35,
+ .vsw = 3,
+ .pxl_clk = 25000000,
+ .invert_pxl_clk = 1,
+};
+
+void *lcd_base; /* Start of framebuffer memory */
+void *lcd_console_address; /* Start of console buffer */
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+
+short console_col;
+short console_row;
+
+static int lcd_enabled = 1;
+
+void lcd_initcolregs(void)
+{
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+
+void lcd_enable(void)
+{
+ /* HACK ALERT:
+ * global variable from common/lcd.c
+ * Set to 0 here to prevent messages from going to LCD
+ * rather than serial console
+ */
+ lcd_is_enabled = 0;
+
+ if (lcd_enabled) {
+ karo_load_splashimage(1);
+
+ gpio_set_value(TX48_LCD_PWR_GPIO, 1);
+ gpio_set_value(TX48_LCD_RST_GPIO, 1);
+ udelay(300000);
+ gpio_set_value(TX48_LCD_BACKLIGHT_GPIO, 0);
+ }
+}
+
+void lcd_disable(void)
+{
+ da8xx_fb_disable();
+}
+
+void lcd_panel_disable(void)
+{
+ if (lcd_enabled) {
+ gpio_set_value(TX48_LCD_BACKLIGHT_GPIO, 1);
+ gpio_set_value(TX48_LCD_PWR_GPIO, 0);
+ gpio_set_value(TX48_LCD_RST_GPIO, 0);
+ }
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ int color_depth = 24;
+ char *vm;
+ unsigned long val;
+ struct da8xx_panel *p = &tx48_lcd_panel;
+ int refresh = 60;
+
+ if (!lcd_enabled) {
+ printf("LCD disabled\n");
+ return;
+ }
+
+ if (tstc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
+ lcd_enabled = 0;
+ return;
+ }
+
+ vm = getenv("video_mode");
+ if (vm == NULL) {
+ lcd_enabled = 0;
+ return;
+ }
+
+ strncpy((char *)p->name, vm, sizeof(p->name));
+
+ val = simple_strtoul(vm, &vm, 0);
+ if (val != 0) {
+ if (val > panel_info.vl_col)
+ val = panel_info.vl_col;
+ p->width = val;
+ panel_info.vl_col = val;
+ }
+ if (*vm == 'x') {
+ val = simple_strtoul(vm + 1, &vm, 0);
+ if (val > panel_info.vl_row)
+ val = panel_info.vl_row;
+ p->height = val;
+ panel_info.vl_row = val;
+ }
+ while (*vm != '\0') {
+ switch (*vm) {
+ case 'M':
+ case 'R':
+ vm++;
+ break;
+
+ case '-':
+ color_depth = simple_strtoul(vm + 1, &vm, 10);
+ break;
+
+ case '@':
+ refresh = simple_strtoul(vm + 1, &vm, 10);
+ break;
+
+ default:
+ debug("Ignoring '%c'\n", *vm);
+ vm++;
+ }
+ }
+ switch (color_depth) {
+ case 8:
+ panel_info.vl_bpix = 3;
+ break;
+
+ case 16:
+ panel_info.vl_bpix = 4;
+ break;
+
+ case 24:
+ panel_info.vl_bpix = 5;
+ break;
+
+ default:
+ printf("Invalid color_depth %u from video_mode '%s'; using default: %u\n",
+ color_depth, getenv("video_mode"), 24);
+ }
+ lcd_line_length = NBITS(panel_info.vl_bpix) / 8 * panel_info.vl_col;
+ p->pxl_clk = refresh *
+ (p->width + p->hfp + p->hbp + p->hsw) *
+ (p->height + p->vfp + p->vbp + p->vsw);
+ debug("Pixel clock set to %u.%03uMHz\n",
+ p->pxl_clk / 1000000, p->pxl_clk / 1000 % 1000);
+
+ gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
+ tx48_set_pin_mux(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads));
+ debug("Initializing FB driver\n");
+ da8xx_video_init(&tx48_lcd_panel, color_depth);
+
+ if (karo_load_splashimage(0) == 0) {
+ debug("Initializing LCD controller\n");
+ video_hw_init();
+ } else {
+ debug("Skipping initialization of LCD controller\n");
+ }
+}
+#else
+#define lcd_enabled 0
+#endif /* CONFIG_LCD */
+
+static void stk5_board_init(void)
+{
+ tx48_set_pin_mux(stk5_pads, ARRAY_SIZE(stk5_pads));
+}
+
+static void stk5v3_board_init(void)
+{
+ stk5_board_init();
+}
+
+static void stk5v5_board_init(void)
+{
+ stk5_board_init();
+ tx48_set_pin_mux(stk5v5_pads, ARRAY_SIZE(stk5v5_pads));
+ gpio_request_array(stk5v5_gpios, ARRAY_SIZE(stk5v5_gpios));
+}
+
+/* called with default environment! */
+int board_init(void)
+{
+ /* mach type passed to kernel */
+#ifdef CONFIG_OF_LIBFDT
+ gd->bd->bi_arch_number = -1;
+#endif
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+static void show_reset_cause(u32 prm_rstst)
+{
+ const char *dlm = "";
+
+ printf("RESET cause: ");
+ if (prm_rstst & PRM_RSTST_GLOBAL_COLD_RST) {
+ printf("%sPOR", dlm);
+ dlm = " | ";
+ }
+ if (prm_rstst & PRM_RSTST_GLOBAL_WARM_SW_RST) {
+ printf("%sSW", dlm);
+ dlm = " | ";
+ }
+ if (prm_rstst & PRM_RSTST_WDT1_RST) {
+ printf("%sWATCHDOG", dlm);
+ dlm = " | ";
+ }
+ if (prm_rstst & PRM_RSTST_EXTERNAL_WARM_RST) {
+ printf("%sWARM", dlm);
+ dlm = " | ";
+ }
+ if (prm_rstst & PRM_RSTST_ICEPICK_RST) {
+ printf("%sJTAG", dlm);
+ dlm = " | ";
+ }
+ if (*dlm == '\0')
+ printf("unknown");
+
+ printf(" RESET\n");
+}
+
+/* called with default environment! */
+int checkboard(void)
+{
+ struct prm_device *prmdev = (struct prm_device *)PRM_DEVICE;
+
+ prm_rstst = readl(&prmdev->prmrstst);
+ show_reset_cause(prm_rstst);
+
+#ifdef CONFIG_OF_LIBFDT
+ printf("Board: Ka-Ro TX48-7020 with FDT support\n");
+#else
+ printf("Board: Ka-Ro TX48-7020\n");
+#endif
+ timer_init();
+ return 0;
+}
+
+/* called with environment from NAND or MMC */
+int board_late_init(void)
+{
+ const char *baseboard;
+
+#ifdef CONFIG_OF_BOARD_SETUP
+ karo_fdt_move_fdt();
+#endif
+ baseboard = getenv("baseboard");
+ if (!baseboard)
+ return 0;
+
+ if (strncmp(baseboard, "stk5", 4) == 0) {
+ printf("Baseboard: %s\n", baseboard);
+ if ((strlen(baseboard) == 4) ||
+ strcmp(baseboard, "stk5-v3") == 0) {
+ stk5v3_board_init();
+ } else if (strcmp(baseboard, "stk5-v5") == 0) {
+ stk5v5_board_init();
+ } else {
+ printf("WARNING: Unsupported STK5 board rev.: %s\n",
+ baseboard + 4);
+ }
+ } else {
+ printf("WARNING: Unsupported baseboard: '%s'\n",
+ baseboard);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void tx48_phy_init(char *name, int addr)
+{
+ debug("%s: Resetting ethernet PHY\n", __func__);
+
+ gpio_direction_output(TX48_ETH_PHY_RST_GPIO, 0);
+
+ udelay(100);
+
+ /* Release nRST */
+ gpio_set_value(TX48_ETH_PHY_RST_GPIO, 1);
+
+ /* Wait for PHY internal POR signal to deassert */
+ udelay(25000);
+}
+
+static void cpsw_control(int enabled)
+{
+ /* nothing for now */
+ /* TODO : VTP was here before */
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_id = 0,
+ },
+};
+
+void s_init(void)
+{
+}
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = AM335X_CPSW_MDIO_BASE,
+ .cpsw_base = AM335X_CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = ARRAY_SIZE(cpsw_slaves),
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .mac_control = (1 << 5) /* MIIEN */,
+ .control = cpsw_control,
+ .phy_init = tx48_phy_init,
+ .gigabit_en = 0,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ uint8_t mac_addr[ETH_ALEN];
+ uint32_t mac_hi, mac_lo;
+
+ /* try reading mac address from efuse */
+ mac_lo = __raw_readl(MAC_ID0_LO);
+ mac_hi = __raw_readl(MAC_ID0_HI);
+
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (is_valid_ether_addr(mac_addr)) {
+ debug("MAC addr set to: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac_addr[0], mac_addr[1], mac_addr[2],
+ mac_addr[3], mac_addr[4], mac_addr[5]);
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ } else {
+ printf("ERROR: Did not find a valid mac address in e-fuse\n");
+ }
+
+ __raw_writel(RMII_MODE_ENABLE, MAC_MII_SEL);
+ __raw_writel(0x5D, GMII_SEL);
+ return cpsw_register(&cpsw_data);
+}
+#endif /* CONFIG_DRIVER_TI_CPSW */
+
+#if defined(CONFIG_NAND_AM33XX) && defined(CONFIG_CMD_SWITCH_ECC)
+/******************************************************************************
+ * Command to switch between NAND HW and SW ecc
+ *****************************************************************************/
+static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ int type = 0;
+
+ if (argc < 2)
+ goto usage;
+
+ if (strncmp(argv[1], "hw", 2) == 0) {
+ if (argc == 3)
+ type = simple_strtoul(argv[2], NULL, 10);
+ am33xx_nand_switch_ecc(NAND_ECC_HW, type);
+ }
+ else if (strncmp(argv[1], "sw", 2) == 0)
+ am33xx_nand_switch_ecc(NAND_ECC_SOFT, 0);
+ else
+ goto usage;
+
+ return 0;
+
+usage:
+ printf("Usage: nandecc %s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(
+ nandecc, 3, 1, do_switch_ecc,
+ "Switch NAND ECC calculation algorithm b/w hardware and software",
+ "[sw|hw <hw_type>] \n"
+ " [sw|hw]- Switch b/w hardware(hw) & software(sw) ecc algorithm\n"
+ " hw_type- 0 for Hamming code\n"
+ " 1 for bch4\n"
+ " 2 for bch8\n"
+ " 3 for bch16\n"
+);
+#endif /* CONFIG_NAND_AM33XX && CONFIG_CMD_SWITCH_ECC */
+
+enum {
+ LED_STATE_INIT = -1,
+ LED_STATE_OFF,
+ LED_STATE_ON,
+};
+
+void show_activity(int arg)
+{
+ static int led_state = LED_STATE_INIT;
+ static ulong last;
+
+ if (led_state == LED_STATE_INIT) {
+ last = get_timer(0);
+ gpio_set_value(TX48_LED_GPIO, 1);
+ led_state = LED_STATE_ON;
+ } else {
+ if (get_timer(last) > CONFIG_SYS_HZ) {
+ last = get_timer(0);
+ if (led_state == LED_STATE_ON) {
+ gpio_set_value(TX48_LED_GPIO, 0);
+ } else {
+ gpio_set_value(TX48_LED_GPIO, 1);
+ }
+ led_state = 1 - led_state;
+ }
+ }
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+#include <jffs2/jffs2.h>
+#include <mtd_node.h>
+struct node_info nodes[] = {
+ { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
+};
+
+#else
+#define fdt_fixup_mtdparts(b,n,c) do { } while (0)
+#endif /* CONFIG_FDT_FIXUP_PARTITIONS */
+
+static void tx48_fixup_flexcan(void *blob)
+{
+ const char *baseboard = getenv("baseboard");
+
+ if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
+ return;
+
+ karo_fdt_del_prop(blob, "ti,dcan", 0x481cc000, "can-xcvr-enable");
+ karo_fdt_del_prop(blob, "ti,dcan", 0x481d0000, "can-xcvr-enable");
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ fdt_fixup_ethernet(blob);
+
+ karo_fdt_fixup_touchpanel(blob);
+ tx48_fixup_flexcan(blob);
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
--- /dev/null
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+ .text :
+ {
+ __image_copy_start = .;
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
+ . = ALIGN(4);
+
+ __image_copy_end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ _end = .;
+
+ /*
+ * Deprecated: this MMU section is used by pxa at present but
+ * should not be used by new boards/CPUs.
+ */
+ . = ALIGN(4096);
+ .mmutable : {
+ *(.mmutable)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
--- /dev/null
+#
+# (C) Copyright 2009 DENX Software Engineering
+# Author: John Rigby <jcrigby@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT := $(BOARDDIR)/u-boot.lds
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := tx51.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+# stack is allocated below CONFIG_SYS_TEXT_BASE
+CONFIG_SYS_TEXT_BASE := 0x90100000
+
+PLATFORM_CPPFLAGS += -Werror
+LOGO_BMP = logos/karo.bmp
--- /dev/null
+#include <config.h>
+#include <configs/tx51.h>
+#include <asm/arch/imx-regs.h>
+
+#define DCDGEN(type, addr, data) .long type, addr, data
+
+#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
+
+#ifdef PHYS_SDRAM_2_SIZE
+#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#else
+#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
+#endif
+
+#define REG_ESDCTL0 0x00
+#define REG_ESDCFG0 0x04
+#define REG_ESDCTL1 0x08
+#define REG_ESDCFG1 0x0c
+#define REG_ESDMISC 0x10
+#define REG_ESDSCR 0x14
+#define REG_ESDGPR 0x34
+
+#define REG_CCGR0 0x68
+#define REG_CCGR1 0x6c
+#define REG_CCGR2 0x70
+#define REG_CCGR3 0x74
+#define REG_CCGR4 0x78
+#define REG_CCGR5 0x7c
+#define REG_CCGR6 0x80
+#define REG_CMEOR 0x84
+
+/* SDRAM timing setup */
+#define RALAT 1
+#define LHD 0
+
+#if SDRAM_SIZE <= SZ_128M
+#define RA_BITS (13 - 11) /* row addr bits - 11 */
+#else
+#define RA_BITS (14 - 11) /* row addr bits - 11 */
+#endif
+
+#define CA_BITS (10 - 8) /* 0-2: col addr bits - 8 3: rsrvd */
+#define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
+#define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
+#define SRT 0 /* 0: disabled *: 1: self refr. ... */
+#define PWDT 0 /* 0: disabled 1: precharge pwdn
+ 2: pwdn after 64 clocks 3: pwdn after 128 clocks */
+#define ESDCTL_VAL (0x80000000 | (SREFR << 28) | (RA_BITS << 24) | (CA_BITS << 20) | \
+ (DSIZ << 16) | (SRT << 14) | (PWDT << 12))
+
+#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+
+ .macro CK_VAL, name, clks, offs
+ .iflt \clks - \offs
+ .set \name, 0
+ .else
+ .set \name, \clks - \offs
+ .endif
+ .endm
+
+ .macro NS_VAL, name, ns, offs
+ .iflt \ns - \offs
+ .set \name, 0
+ .else
+ CK_VAL \name, NS_TO_CK(\ns), \offs
+ .endif
+ .endm
+
+#if SDRAM_CLK < 200
+/* MT46H32M32LF-6 */
+NS_VAL tRFC, 125, 10 /* clks - 10 (0..15) */
+NS_VAL tXSR, 138, 25 /* clks - 25 (0..15) */
+NS_VAL tXP, 25, 1 /* clks - 1 (0..7) */
+CK_VAL tWTR, 1, 1 /* clks - 1 (0..1) */
+NS_VAL tRP, 18, 2 /* clks - 2 (0..3) */
+CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
+NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
+NS_VAL tRAS, 42, 1 /* clks - 1 (0..15) */
+NS_VAL tRRD, 12, 1 /* clks - 1 (0..3) */
+NS_VAL tRCD, 18, 1 /* clks - 1 (0..7) */
+NS_VAL tRC, 60, 1 /* 0: 20 *: clks - 1 (0..15) */
+#else
+/* MT46H64M32LF-5 or -6 */
+NS_VAL tRFC, 72, 10 /* clks - 10 (0..15) */
+NS_VAL tXSR, 113, 25 /* clks - 25 (0..15) */
+CK_VAL tXP, 2, 1 /* clks - 1 (0..7) */
+CK_VAL tWTR, 2, 1 /* clks - 1 (0..1) */
+NS_VAL tRP, 18, 2 /* clks - 2 (0..3) */
+CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
+NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
+NS_VAL tRAS, 42, 1 /* clks - 1 (0..15) */
+NS_VAL tRRD, 12, 1 /* clks - 1 (0..3) */
+NS_VAL tRCD, 18, 1 /* clks - 1 (0..7) */
+NS_VAL tRC, 60, 1 /* 0: 20 *: clks - 1 (0..15) */
+#endif
+
+#define ESDCFG_VAL ((tRFC << 28) | (tXSR << 24) | (tXP << 21) | \
+ (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
+ (tRAS << 12) | (tRRD << 10) | (tWR << 7) | \
+ (tRCD << 4) | (tRC << 0))
+
+#define ESDMISC_RALAT(n) (((n) & 0x3) << 7)
+#define ESDMISC_DDR2_EN(n) (((n) & 0x1) << 4)
+#define ESDMISC_DDR_EN(n) (((n) & 0x1) << 3)
+#define ESDMISC_AP(n) (((n) & 0xf) << 16)
+#define ESDMISC_VAL (ESDMISC_AP(10) | ESDMISC_RALAT(RALAT) | \
+ (LHD << 5) | ESDMISC_DDR2_EN(0) | ESDMISC_DDR_EN(0))
+
+ b _start
+ .org 0x400
+app_start_addr:
+ .long _start
+app_code_barker:
+ .long 0xB1
+app_code_csf:
+ .long 0 // 0x97f40000 - 0x1000
+dcd_ptr_ptr:
+ .long dcd_ptr
+super_root_key:
+ .long 0 // hab_super_root_key
+dcd_ptr:
+ .long dcd_data
+app_dest_ptr:
+ .long CONFIG_SYS_TEXT_BASE
+dcd_data:
+ .long 0xB17219E9 // Fixed. can't change.
+dcd_len:
+ .long dcd_end - dcd_start
+dcd_start:
+ DCDGEN(4, CCM_BASE_ADDR + REG_CCGR0, 0xffcffffc);
+ DCDGEN(4, CCM_BASE_ADDR + REG_CCGR1, 0x003fffff);
+ DCDGEN(4, CCM_BASE_ADDR + REG_CCGR2, 0x030c003c);
+ DCDGEN(4, CCM_BASE_ADDR + REG_CCGR3, 0x000000ff);
+ DCDGEN(4, CCM_BASE_ADDR + REG_CCGR4, 0x00000000);
+ DCDGEN(4, CCM_BASE_ADDR + REG_CCGR5, 0x003fc003);
+ DCDGEN(4, CCM_BASE_ADDR + REG_CCGR6, 0x00000000);
+ DCDGEN(4, CCM_BASE_ADDR + REG_CMEOR, 0x00000000);
+
+ DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDCTL0, 0x80000000)
+ DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDSCR, 0x04008008)
+ DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDSCR, 0x00008010)
+ DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDSCR, 0x00008010)
+ DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDSCR, 0x00338018)
+ DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDCTL0, ESDCTL_VAL)
+ DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDCFG0, ESDCFG_VAL)
+#ifdef RAM_BANK1_SIZE
+ DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDCTL1, ESDCTL_VAL)
+ DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDCFG1, ESDCFG_VAL)
+#endif
+ DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDGPR, 0x00020000 | ((RALAT & 0x3) << 29))
+ DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDMISC, ESDMISC_VAL)
+ DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDSCR, 0x00000000)
+
+ /* UART1_RXD */
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x228, 0x00000000)
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x618, 0x000001c1)
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x9e4, 0x00000000)
+
+ /* UART1_TXD */
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x22c, 0x00000000)
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x61c, 0x000000c5)
+
+ /* UART1_RTS */
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x230, 0x00000000)
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x620, 0x000001c1)
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x9e0, 0x00000000)
+
+ /* UART1_CTS */
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x234, 0x00000000)
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x624, 0x000000c5)
+
+ /* STK5 board LED */
+ DCDGEN(4, IOMUXC_BASE_ADDR + 0x1d0, 0x00000013)
+dcd_end:
+ .ifgt dcd_end - dcd_start - 720
+ DCD too large!
+ .endif
+image_len:
+ .long CONFIG_U_BOOT_IMG_SIZE
--- /dev/null
+/*
+ * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <lcd.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <video_fb.h>
+#include <ipu.h>
+#include <mx2fb.h>
+#include <linux/fb.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx51.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+
+#include "../common/karo.h"
+
+//#define IMX_GPIO_NR(b, o) ((((b) - 1) << 5) | (o))
+
+#define TX51_FEC_RST_GPIO IMX_GPIO_NR(2, 14)
+#define TX51_FEC_PWR_GPIO IMX_GPIO_NR(1, 3)
+#define TX51_FEC_INT_GPIO IMX_GPIO_NR(3, 18)
+#define TX51_LED_GPIO IMX_GPIO_NR(4, 10)
+
+#define TX51_LCD_PWR_GPIO IMX_GPIO_NR(4, 14)
+#define TX51_LCD_RST_GPIO IMX_GPIO_NR(4, 13)
+#define TX51_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 2)
+
+#define TX51_RESET_OUT_GPIO IMX_GPIO_NR(2, 15)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IOMUX_SION IOMUX_PAD(0, 0, MUX_CONFIG_SION, 0, 0, 0)
+
+#define FEC_PAD_CTRL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_SRE_FAST)
+#define FEC_PAD_CTRL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
+#define GPIO_PAD_CTRL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
+
+static iomux_v3_cfg_t tx51_pads[] = {
+ /* NAND flash pads are set up in lowlevel_init.S */
+
+ /* RESET_OUT */
+ MX51_PAD_EIM_A21__GPIO2_15 | GPIO_PAD_CTRL,
+
+ /* UART pads */
+#if CONFIG_MXC_UART_BASE == UART1_BASE
+ MX51_PAD_UART1_RXD__UART1_RXD,
+ MX51_PAD_UART1_TXD__UART1_TXD,
+ MX51_PAD_UART1_RTS__UART1_RTS,
+ MX51_PAD_UART1_CTS__UART1_CTS,
+#endif
+#if CONFIG_MXC_UART_BASE == UART2_BASE
+ MX51_PAD_UART2_RXD__UART2_RXD,
+ MX51_PAD_UART2_TXD__UART2_TXD,
+ MX51_PAD_EIM_D26__UART2_RTS,
+ MX51_PAD_EIM_D25__UART2_CTS,
+#endif
+#if CONFIG_MXC_UART_BASE == UART3_BASE
+ MX51_PAD_UART3_RXD__UART3_RXD,
+ MX51_PAD_UART3_TXD__UART3_TXD,
+ MX51_PAD_EIM_D18__UART3_RTS,
+ MX51_PAD_EIM_D17__UART3_CTS,
+#endif
+ /* internal I2C */
+ MX51_PAD_I2C1_DAT__GPIO4_17 | IOMUX_SION,
+ MX51_PAD_I2C1_CLK__GPIO4_16 | IOMUX_SION,
+
+ /* FEC PHY GPIO functions */
+ MX51_PAD_GPIO1_3__GPIO1_3 | GPIO_PAD_CTRL, /* PHY POWER */
+ MX51_PAD_EIM_A20__GPIO2_14 | GPIO_PAD_CTRL, /* PHY RESET */
+ MX51_PAD_NANDF_CS2__GPIO3_18 | GPIO_PAD_CTRL, /* PHY INT */
+
+ /* FEC functions */
+ MX51_PAD_NANDF_CS3__FEC_MDC | FEC_PAD_CTRL,
+ MX51_PAD_EIM_EB2__FEC_MDIO | FEC_PAD_CTRL,
+ MX51_PAD_NANDF_D11__FEC_RX_DV | FEC_PAD_CTRL2,
+ MX51_PAD_EIM_CS4__FEC_RX_ER | FEC_PAD_CTRL2,
+ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | FEC_PAD_CTRL2,
+ MX51_PAD_NANDF_CS7__FEC_TX_EN | FEC_PAD_CTRL,
+ MX51_PAD_NANDF_D8__FEC_TDATA0 | FEC_PAD_CTRL,
+ MX51_PAD_NANDF_CS4__FEC_TDATA1 | FEC_PAD_CTRL,
+ MX51_PAD_NANDF_CS5__FEC_TDATA2 | FEC_PAD_CTRL,
+ MX51_PAD_NANDF_CS6__FEC_TDATA3 | FEC_PAD_CTRL,
+
+ /* strap pins for PHY configuration */
+ MX51_PAD_NANDF_RB3__GPIO3_11 | GPIO_PAD_CTRL, /* RX_CLK/REGOFF */
+ MX51_PAD_NANDF_D9__GPIO3_31 | GPIO_PAD_CTRL, /* RXD0/Mode0 */
+ MX51_PAD_EIM_EB3__GPIO2_23 | GPIO_PAD_CTRL, /* RXD1/Mode1 */
+ MX51_PAD_EIM_CS2__GPIO2_27 | GPIO_PAD_CTRL, /* RXD2/Mode2 */
+ MX51_PAD_EIM_CS3__GPIO2_28 | GPIO_PAD_CTRL, /* RXD3/nINTSEL */
+ MX51_PAD_NANDF_RB2__GPIO3_10 | GPIO_PAD_CTRL, /* COL/RMII/CRSDV */
+ MX51_PAD_EIM_CS5__GPIO2_30 | GPIO_PAD_CTRL, /* CRS/PHYAD4 */
+
+ /* unusable pins on TX51 */
+ MX51_PAD_GPIO1_0__GPIO1_0,
+ MX51_PAD_GPIO1_1__GPIO1_1,
+};
+
+static const struct gpio tx51_gpios[] = {
+ /* RESET_OUT */
+ { TX51_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_LOW, "RESET_OUT", },
+
+ /* FEC PHY control GPIOs */
+ { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */
+ { TX51_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */
+ { TX51_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, /* PHY INT (TX_ER) */
+
+ /* FEC PHY strap pins */
+ { IMX_GPIO_NR(3, 11), GPIOF_OUTPUT_INIT_LOW, "FEC PHY REGOFF", }, /* RX_CLK/REGOFF */
+ { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE0", }, /* RXD0/Mode0 */
+ { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE1", }, /* RXD1/Mode1 */
+ { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE2", }, /* RXD2/Mode2 */
+ { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
+ { IMX_GPIO_NR(3, 10), GPIOF_OUTPUT_INIT_LOW, "FEC PHY RMII", }, /* COL/RMII/CRSDV */
+ { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
+
+ /* module internal I2C bus */
+ { IMX_GPIO_NR(4, 17), GPIOF_INPUT, "I2C1 SDA", },
+ { IMX_GPIO_NR(4, 16), GPIOF_INPUT, "I2C1 SCL", },
+
+ /* Unconnected pins */
+ { IMX_GPIO_NR(1, 0), GPIOF_OUTPUT_INIT_LOW, "N/C", },
+ { IMX_GPIO_NR(1, 1), GPIOF_OUTPUT_INIT_LOW, "N/C", },
+};
+
+/*
+ * Functions
+ */
+#define WRSR_POR (1 << 4)
+#define WRSR_TOUT (1 << 1)
+#define WRSR_SFTW (1 << 0)
+
+/* placed in section '.data' to prevent overwriting relocation info
+ * overlayed with bss
+ */
+static u32 wrsr __attribute__((section(".data")));
+
+static void print_reset_cause(void)
+{
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
+ u32 srsr;
+ char *dlm = "";
+
+ printf("Reset cause: ");
+
+ srsr = readl(&src_regs->srsr);
+ wrsr = readw(wdt_base + 4);
+
+ if (wrsr & WRSR_POR) {
+ printf("%sPOR", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00004) {
+ printf("%sCSU", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00008) {
+ printf("%sIPP USER", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00010) {
+ if (wrsr & WRSR_SFTW) {
+ printf("%sSOFT", dlm);
+ dlm = " | ";
+ }
+ if (wrsr & WRSR_TOUT) {
+ printf("%sWDOG", dlm);
+ dlm = " | ";
+ }
+ }
+ if (srsr & 0x00020) {
+ printf("%sJTAG HIGH-Z", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00040) {
+ printf("%sJTAG SW", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x10000) {
+ printf("%sWARM BOOT", dlm);
+ dlm = " | ";
+ }
+ if (dlm[0] == '\0')
+ printf("unknown");
+
+ printf("\n");
+}
+
+static void print_cpuinfo(void)
+{
+ u32 cpurev;
+
+ cpurev = get_cpu_rev();
+
+ printf("CPU: Freescale i.MX51 rev%d.%d at %d MHz\n",
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+
+ print_reset_cause();
+}
+
+int board_early_init_f(void)
+{
+ struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+
+#ifdef CONFIG_CMD_BOOTCE
+ /* WinCE fails to enable these clocks */
+ writel(readl(&ccm_regs->CCGR2) | 0x0c000000, &ccm_regs->CCGR2); /* usboh3_ipg_ahb */
+ writel(readl(&ccm_regs->CCGR4) | 0x30000000, &ccm_regs->CCGR4); /* srtc */
+ writel(readl(&ccm_regs->CCGR6) | 0x00000300, &ccm_regs->CCGR6); /* emi_garb */
+#endif
+ gpio_request_array(tx51_gpios, ARRAY_SIZE(tx51_gpios));
+ imx_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads));
+
+ writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
+ writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
+
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
+
+ writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
+ writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
+
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
+ return 0;
+}
+
+int dram_init(void)
+{
+ int ret;
+
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+
+ ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
+ CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
+ if (ret)
+ printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
+ CONFIG_SYS_SDRAM_CLK, ret);
+ else
+ debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
+ __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
+ mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
+ CONFIG_SYS_SDRAM_CLK);
+ return ret;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+#if CONFIG_NR_DRAM_BANKS > 1
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
+ PHYS_SDRAM_2_SIZE);
+#endif
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = mmc->priv;
+
+ if (cfg->cd_gpio < 0)
+ return cfg->cd_gpio;
+
+ return !gpio_get_value(cfg->cd_gpio);
+}
+
+static struct fsl_esdhc_cfg esdhc_cfg[] = {
+ {
+ .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
+ .cd_gpio = IMX_GPIO_NR(3, 8),
+ .wp_gpio = -EINVAL,
+ },
+ {
+ .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
+ .cd_gpio = IMX_GPIO_NR(3, 6),
+ .wp_gpio = -EINVAL,
+ },
+};
+
+static const iomux_v3_cfg_t mmc0_pads[] = {
+ MX51_PAD_SD1_CMD__SD1_CMD,
+ MX51_PAD_SD1_CLK__SD1_CLK,
+ MX51_PAD_SD1_DATA0__SD1_DATA0,
+ MX51_PAD_SD1_DATA1__SD1_DATA1,
+ MX51_PAD_SD1_DATA2__SD1_DATA2,
+ MX51_PAD_SD1_DATA3__SD1_DATA3,
+ /* SD1 CD */
+ MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(PAD_CTL_PUE | PAD_CTL_PKE),
+};
+
+static const iomux_v3_cfg_t mmc1_pads[] = {
+ MX51_PAD_SD2_CMD__SD2_CMD,
+ MX51_PAD_SD2_CLK__SD2_CLK,
+ MX51_PAD_SD2_DATA0__SD2_DATA0,
+ MX51_PAD_SD2_DATA1__SD2_DATA1,
+ MX51_PAD_SD2_DATA2__SD2_DATA2,
+ MX51_PAD_SD2_DATA3__SD2_DATA3,
+ /* SD2 CD */
+ MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(PAD_CTL_PUE | PAD_CTL_PKE),
+};
+
+static struct {
+ const iomux_v3_cfg_t *pads;
+ int count;
+} mmc_pad_config[] = {
+ { mmc0_pads, ARRAY_SIZE(mmc0_pads), },
+ { mmc1_pads, ARRAY_SIZE(mmc1_pads), },
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(esdhc_cfg); i++) {
+ struct mmc *mmc;
+ struct fsl_esdhc_cfg *cfg;
+
+ if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
+ break;
+
+ imx_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads,
+ mmc_pad_config[i].count);
+
+ cfg = &esdhc_cfg[i];
+ cfg->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ fsl_esdhc_initialize(bis, cfg);
+
+ mmc = find_mmc_device(i);
+ if (mmc == NULL)
+ continue;
+ if (board_mmc_getcd(mmc) > 0)
+ mmc_init(mmc);
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_MMC */
+
+#ifdef CONFIG_FEC_MXC
+
+#ifndef ETH_ALEN
+#define ETH_ALEN 6
+#endif
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ int i;
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ struct fuse_bank *bank = &iim->bank[1];
+ struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
+
+ if (dev_id > 0)
+ return;
+
+ for (i = 0; i < ETH_ALEN; i++)
+ mac[ETH_ALEN - i - 1] = readl(&fuse->mac_addr[i]);
+}
+
+static iomux_v3_cfg_t tx51_fec_pads[] = {
+ /* reconfigure strap pins for FEC function */
+ MX51_PAD_NANDF_RB3__FEC_RX_CLK | FEC_PAD_CTRL2,
+ MX51_PAD_NANDF_D9__FEC_RDATA0 | FEC_PAD_CTRL2,
+ MX51_PAD_EIM_EB3__FEC_RDATA1 | FEC_PAD_CTRL2,
+ MX51_PAD_EIM_CS2__FEC_RDATA2 | FEC_PAD_CTRL2,
+ MX51_PAD_EIM_CS3__FEC_RDATA3 | FEC_PAD_CTRL2,
+ MX51_PAD_NANDF_RB2__FEC_COL | FEC_PAD_CTRL2,
+ MX51_PAD_EIM_CS5__FEC_CRS | FEC_PAD_CTRL,
+};
+
+/* take bit 4 of PHY address from configured PHY address or
+ * set it to 0 if PHYADDR is -1 (probe for PHY)
+ */
+#define PHYAD4 ((CONFIG_FEC_MXC_PHYADDR >> 4) & !(CONFIG_FEC_MXC_PHYADDR >> 5))
+
+static struct gpio tx51_fec_gpios[] = {
+ { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY POWER", },
+ { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode0", }, /* RXD0/Mode0 */
+ { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode1", }, /* RXD1/Mode1 */
+ { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode2", }, /* RXD2/Mode2 */
+ { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
+#if PHYAD4
+ { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
+#else
+ { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
+#endif
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+ unsigned char mac[ETH_ALEN];
+ char mac_str[ETH_ALEN * 3] = "";
+
+ /* Power up the external phy and assert strap options */
+ gpio_request_array(tx51_fec_gpios, ARRAY_SIZE(tx51_fec_gpios));
+
+ /* delay at least 21ms for the PHY internal POR signal to deassert */
+ udelay(22000);
+
+ /* Deassert RESET to the external phy */
+ gpio_set_value(TX51_FEC_RST_GPIO, 1);
+
+ /* Without this delay the PHY won't work, though nothing in
+ * the datasheets suggests that it should be necessary!
+ */
+ udelay(400);
+ imx_iomux_v3_setup_multiple_pads(tx51_fec_pads,
+ ARRAY_SIZE(tx51_fec_pads));
+
+ ret = cpu_eth_init(bis);
+ if (ret) {
+ printf("cpu_eth_init() failed: %d\n", ret);
+ return ret;
+ }
+
+ imx_get_mac_from_fuse(0, mac);
+ snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ setenv("ethaddr", mac_str);
+
+ return ret;
+}
+#endif /* CONFIG_FEC_MXC */
+
+enum {
+ LED_STATE_INIT = -1,
+ LED_STATE_OFF,
+ LED_STATE_ON,
+};
+
+void show_activity(int arg)
+{
+ static int led_state = LED_STATE_INIT;
+ static ulong last;
+
+ if (led_state == LED_STATE_INIT) {
+ last = get_timer(0);
+ gpio_set_value(TX51_LED_GPIO, 1);
+ led_state = LED_STATE_ON;
+ } else {
+ if (get_timer(last) > CONFIG_SYS_HZ) {
+ last = get_timer(0);
+ if (led_state == LED_STATE_ON) {
+ gpio_set_value(TX51_LED_GPIO, 0);
+ } else {
+ gpio_set_value(TX51_LED_GPIO, 1);
+ }
+ led_state = 1 - led_state;
+ }
+ }
+}
+
+static const iomux_v3_cfg_t stk5_pads[] = {
+ /* SW controlled LED on STK5 baseboard */
+ MX51_PAD_CSI2_D13__GPIO4_10,
+
+ /* USB PHY reset */
+ MX51_PAD_GPIO1_4__GPIO1_4,
+ /* USBOTG OC */
+ MX51_PAD_GPIO1_6__GPIO1_6,
+ /* USB PHY clock enable */
+ MX51_PAD_GPIO1_7__GPIO1_7,
+ /* USBH1 VBUS enable */
+ MX51_PAD_GPIO1_8__GPIO1_8,
+ /* USBH1 OC */
+ MX51_PAD_GPIO1_9__GPIO1_9,
+};
+
+static const struct gpio stk5_gpios[] = {
+ { TX51_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
+
+ { IMX_GPIO_NR(1, 4), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY clk enable", },
+ { IMX_GPIO_NR(1, 6), GPIOF_INPUT, "USBOTG OC", },
+ { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY reset", },
+ { IMX_GPIO_NR(1, 8), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
+ { IMX_GPIO_NR(1, 9), GPIOF_INPUT, "USBH1 OC", },
+};
+
+#ifdef CONFIG_LCD
+static ushort tx51_cmap[256];
+vidinfo_t panel_info = {
+ /* set to max. size supported by SoC */
+ .vl_col = 1600,
+ .vl_row = 1200,
+
+ .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+ .cmap = tx51_cmap,
+};
+
+static struct fb_videomode tx51_fb_mode = {
+ /* Standard VGA timing */
+ .name = "VGA",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
+static int lcd_enabled = 1;
+
+void lcd_enable(void)
+{
+ /* HACK ALERT:
+ * global variable from common/lcd.c
+ * Set to 0 here to prevent messages from going to LCD
+ * rather than serial console
+ */
+ lcd_is_enabled = 0;
+
+ karo_load_splashimage(1);
+ if (lcd_enabled) {
+ debug("Switching LCD on\n");
+ gpio_set_value(TX51_LCD_PWR_GPIO, 1);
+ udelay(100);
+ gpio_set_value(TX51_LCD_RST_GPIO, 1);
+ udelay(300000);
+ gpio_set_value(TX51_LCD_BACKLIGHT_GPIO, 0);
+ }
+}
+
+static const iomux_v3_cfg_t stk5_lcd_pads[] = {
+ /* LCD RESET */
+ MX51_PAD_CSI2_VSYNC__GPIO4_13,
+ /* LCD POWER_ENABLE */
+ MX51_PAD_CSI2_HSYNC__GPIO4_14,
+ /* LCD Backlight (PWM) */
+ MX51_PAD_GPIO1_2__GPIO1_2,
+
+ /* Display */
+ MX51_PAD_DISP1_DAT0__DISP1_DAT0,
+ MX51_PAD_DISP1_DAT1__DISP1_DAT1,
+ MX51_PAD_DISP1_DAT2__DISP1_DAT2,
+ MX51_PAD_DISP1_DAT3__DISP1_DAT3,
+ MX51_PAD_DISP1_DAT4__DISP1_DAT4,
+ MX51_PAD_DISP1_DAT5__DISP1_DAT5,
+ MX51_PAD_DISP1_DAT6__DISP1_DAT6,
+ MX51_PAD_DISP1_DAT7__DISP1_DAT7,
+ MX51_PAD_DISP1_DAT8__DISP1_DAT8,
+ MX51_PAD_DISP1_DAT9__DISP1_DAT9,
+ MX51_PAD_DISP1_DAT10__DISP1_DAT10,
+ MX51_PAD_DISP1_DAT11__DISP1_DAT11,
+ MX51_PAD_DISP1_DAT12__DISP1_DAT12,
+ MX51_PAD_DISP1_DAT13__DISP1_DAT13,
+ MX51_PAD_DISP1_DAT14__DISP1_DAT14,
+ MX51_PAD_DISP1_DAT15__DISP1_DAT15,
+ MX51_PAD_DISP1_DAT16__DISP1_DAT16,
+ MX51_PAD_DISP1_DAT17__DISP1_DAT17,
+ MX51_PAD_DISP1_DAT18__DISP1_DAT18,
+ MX51_PAD_DISP1_DAT19__DISP1_DAT19,
+ MX51_PAD_DISP1_DAT20__DISP1_DAT20,
+ MX51_PAD_DISP1_DAT21__DISP1_DAT21,
+ MX51_PAD_DISP1_DAT22__DISP1_DAT22,
+ MX51_PAD_DISP1_DAT23__DISP1_DAT23,
+ MX51_PAD_DI1_PIN2__DI1_PIN2, /* HSYNC */
+ MX51_PAD_DI1_PIN3__DI1_PIN3, /* VSYNC */
+};
+
+static const struct gpio stk5_lcd_gpios[] = {
+ { TX51_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
+ { TX51_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
+ { TX51_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+};
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ int color_depth = 24;
+ char *vm;
+ unsigned long val;
+ int refresh = 60;
+ struct fb_videomode *p = &tx51_fb_mode;
+ int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
+ int pix_fmt = 0;
+ ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
+ unsigned long di_clk_rate = 65000000;
+
+ if (!lcd_enabled) {
+ debug("LCD disabled\n");
+ return;
+ }
+
+ if (tstc() || (wrsr & WRSR_TOUT)) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ return;
+ }
+
+ vm = getenv("video_mode");
+ if (vm == NULL) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ return;
+ }
+ while (*vm != '\0') {
+ if (*vm >= '0' && *vm <= '9') {
+ char *end;
+
+ val = simple_strtoul(vm, &end, 0);
+ if (end > vm) {
+ if (!xres_set) {
+ if (val > panel_info.vl_col)
+ val = panel_info.vl_col;
+ p->xres = val;
+ panel_info.vl_col = val;
+ xres_set = 1;
+ } else if (!yres_set) {
+ if (val > panel_info.vl_row)
+ val = panel_info.vl_row;
+ p->yres = val;
+ panel_info.vl_row = val;
+ yres_set = 1;
+ } else if (!bpp_set) {
+ switch (val) {
+ case 8:
+ case 16:
+ case 24:
+ color_depth = val;
+ break;
+
+ default:
+ printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
+ end - vm, vm, color_depth);
+ }
+ bpp_set = 1;
+ } else if (!refresh_set) {
+ refresh = val;
+ refresh_set = 1;
+ }
+ }
+ vm = end;
+ }
+ switch (*vm) {
+ case '@':
+ bpp_set = 1;
+ /* fallthru */
+ case '-':
+ yres_set = 1;
+ /* fallthru */
+ case 'x':
+ xres_set = 1;
+ /* fallthru */
+ case 'M':
+ case 'R':
+ vm++;
+ break;
+
+ default:
+ if (!pix_fmt) {
+ char *tmp;
+
+ pix_fmt = IPU_PIX_FMT_RGB24;
+ tmp = strchr(vm, ':');
+ if (tmp)
+ vm = tmp;
+ }
+ if (*vm != '\0')
+ vm++;
+ }
+ }
+ switch (color_depth) {
+ case 8:
+ panel_info.vl_bpix = 3;
+ break;
+
+ case 16:
+ panel_info.vl_bpix = 4;
+ break;
+
+ case 24:
+ panel_info.vl_bpix = 5;
+ }
+
+ p->pixclock = KHZ2PICOS(refresh *
+ (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
+ (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
+ / 1000);
+ debug("Pixel clock set to %lu.%03lu MHz\n",
+ PICOS2KHZ(p->pixclock) / 1000,
+ PICOS2KHZ(p->pixclock) % 1000);
+
+ gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
+ imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
+ ARRAY_SIZE(stk5_lcd_pads));
+
+ debug("Initializing FB driver\n");
+ if (!pix_fmt)
+ pix_fmt = IPU_PIX_FMT_RGB24;
+
+ if (karo_load_splashimage(0) == 0) {
+ struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+ u32 ccgr4 = readl(&ccm_regs->CCGR4);
+
+ /* MIPI HSC clock is required for initialization */
+ writel(ccgr4 | (3 << 12), &ccm_regs->CCGR4);
+
+ debug("Initializing LCD controller\n");
+ ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
+
+ writel(ccgr4 & ~(3 << 12), &ccm_regs->CCGR4);
+ } else {
+ debug("Skipping initialization of LCD controller\n");
+ }
+}
+#else
+#define lcd_enabled 0
+#endif /* CONFIG_LCD */
+
+static void stk5_board_init(void)
+{
+ gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
+ imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
+}
+
+static void stk5v3_board_init(void)
+{
+ stk5_board_init();
+}
+
+static void tx51_set_cpu_clock(void)
+{
+ unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
+ int ret;
+
+ if (tstc() || (wrsr & WRSR_TOUT))
+ return;
+
+ if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
+ return;
+
+ ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
+ if (ret != 0) {
+ printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
+ return;
+ }
+ printf("CPU clock set to %u.%03u MHz\n",
+ mxc_get_clock(MXC_ARM_CLK) / 1000000,
+ mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
+}
+
+int board_late_init(void)
+{
+ int ret = 0;
+ const char *baseboard;
+
+ tx51_set_cpu_clock();
+ karo_fdt_move_fdt();
+
+ baseboard = getenv("baseboard");
+ if (!baseboard)
+ goto exit;
+
+ if (strncmp(baseboard, "stk5", 4) == 0) {
+ printf("Baseboard: %s\n", baseboard);
+ if ((strlen(baseboard) == 4) ||
+ strcmp(baseboard, "stk5-v3") == 0) {
+ stk5v3_board_init();
+ } else if (strcmp(baseboard, "stk5-v5") == 0) {
+ printf("ERROR: Baseboard '%s' incompatible with TX51 module!\n",
+ baseboard);
+ stk5v3_board_init();
+ } else {
+ printf("WARNING: Unsupported STK5 board rev.: %s\n",
+ baseboard + 4);
+ }
+ } else {
+ printf("WARNING: Unsupported baseboard: '%s'\n",
+ baseboard);
+ ret = -EINVAL;
+ }
+
+exit:
+ gpio_set_value(TX51_RESET_OUT_GPIO, 1);
+ return ret;
+}
+
+int checkboard(void)
+{
+ print_cpuinfo();
+
+ printf("Board: Ka-Ro TX51-%sxx%s\n",
+ TX51_MOD_PREFIX, TX51_MOD_SUFFIX);
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+#include <jffs2/jffs2.h>
+#include <mtd_node.h>
+struct node_info nodes[] = {
+ { "fsl,imx51-nand", MTD_DEV_TYPE_NAND, },
+};
+
+#else
+#define fdt_fixup_mtdparts(b,n,c) do { } while (0)
+#endif
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ fdt_fixup_ethernet(blob);
+
+ karo_fdt_fixup_touchpanel(blob);
+ karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", 0x73f80000);
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ board/karo/tx51/lowlevel_init.o (.text*)
+ __image_copy_start = .;
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
+ . = ALIGN(4);
+
+ __image_copy_end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ _end = .;
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
--- /dev/null
+#
+# (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# version 2 as published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT := $(BOARDDIR)/u-boot.lds
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := tx53.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+# stack is allocated below CONFIG_SYS_TEXT_BASE
+CONFIG_SYS_TEXT_BASE := 0x70100000
+
+PLATFORM_CPPFLAGS += -Werror
+LOGO_BMP = logos/karo.bmp
--- /dev/null
+#include <config.h>
+#include <configs/tx53.h>
+#include <asm/arch/imx-regs.h>
+
+#define DEBUG_LED_BIT 20
+#define LED_GPIO_BASE GPIO2_BASE_ADDR
+#define LED_MUX_OFFSET 0x174
+#define LED_MUX_MODE 0x11
+
+#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
+
+#ifdef PHYS_SDRAM_2_SIZE
+#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#else
+#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
+#endif
+
+#define REG_ESDCTL0 0x00
+#define REG_ESDCFG0 0x04
+#define REG_ESDCTL1 0x08
+#define REG_ESDCFG1 0x0c
+#define REG_ESDMISC 0x10
+#define REG_ESDSCR 0x14
+#define REG_ESDGPR 0x34
+
+#define REG_CCGR0 0x68
+#define REG_CCGR1 0x6c
+#define REG_CCGR2 0x70
+#define REG_CCGR3 0x74
+#define REG_CCGR4 0x78
+#define REG_CCGR5 0x7c
+#define REG_CCGR6 0x80
+#define REG_CCGR7 0x84
+#define REG_CMEOR 0x88
+
+#define CPU_2_BE_32(l) \
+ ((((l) << 24) & 0xFF000000) | \
+ (((l) << 8) & 0x00FF0000) | \
+ (((l) >> 8) & 0x0000FF00) | \
+ (((l) >> 24) & 0x000000FF))
+
+#define MXC_DCD_ITEM(addr, val) \
+ .word CPU_2_BE_32(addr), CPU_2_BE_32(val)
+
+#define MXC_DCD_CMD_SZ_BYTE 1
+#define MXC_DCD_CMD_SZ_SHORT 2
+#define MXC_DCD_CMD_SZ_WORD 4
+#define MXC_DCD_CMD_FLAG_WRITE 0x0
+#define MXC_DCD_CMD_FLAG_CLR 0x1
+#define MXC_DCD_CMD_FLAG_SET 0x3
+#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
+#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
+#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
+
+#define MXC_DCD_CMD_WRT(type, flags, next) \
+ .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
+
+#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
+ .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
+ CPU_2_BE_32(addr), CPU_2_BE_32(mask)
+
+#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
+ .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
+ CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
+
+#define MXC_DCD_CMD_NOP() \
+ .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+
+#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
+#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+
+ .macro CK_VAL, name, clks, offs, max
+ .iflt \clks - \offs
+ .set \name, 0
+ .else
+ .ifle \clks - \offs - \max
+ .set \name, \clks - \offs
+ .endif
+ .endif
+ .endm
+
+ .macro NS_VAL, name, ns, offs, max
+ .iflt \ns - \offs
+ .set \name, 0
+ .else
+ CK_VAL \name, NS_TO_CK(\ns), \offs, \max
+ .endif
+ .endm
+
+ .macro CK_MAX, name, ck1, ck2, offs, max
+ .ifgt \ck1 - \ck2
+ CK_VAL \name, \ck1, \offs, \max
+ .else
+ CK_VAL \name, \ck2, \offs, \max
+ .endif
+ .endm
+
+#define ESDMISC_DDR_TYPE_DDR3 0
+#define ESDMISC_DDR_TYPE_LPDDR2 1
+#define ESDMISC_DDR_TYPE_DDR2 2
+
+#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
+
+#define CKIL_FREQ_Hz 32768
+#define ESDOR_CLK_PERIOD_ns (1000000000 / CKIL_FREQ_Hz / 2) /* base clock for ESDOR values */
+
+/* DDR3 SDRAM */
+#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
+#define BANK_ADDR_BITS 2
+#else
+#define BANK_ADDR_BITS 1
+#endif
+#define SDRAM_BURST_LENGTH 8
+#define RALAT 5
+#define WALAT 1
+#define ADDR_MIRROR 0
+#define DDR_TYPE ESDMISC_DDR_TYPE_DDR3
+
+/* 512/1024MiB SDRAM: NT5CB128M16P-CG */
+/* ESDCFG0 0x0c */
+NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
+CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
+CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
+CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
+NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tCL, 9, 3, 8 /* clks - 3 (0..8) CAS Latency */
+
+/* ESDCFG1 0x10 */
+NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
+NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
+NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tCWL, 5, 2, 6 /* clks - 2 (0..6) */
+
+/* ESDCFG2 0x14 */
+CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
+CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+
+/* ESDOR 0x30 */
+CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
+
+/* ESDOTC 0x08 */
+NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tANPD, tCWL, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tAXPD, tCWL, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tODTLon tCWL - 1, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tODTLoff tCWL - 1, 1, 31 /* clks - 1 (0..31) */
+
+#define tSDE_RST (DIV_ROUND_UP(200000, ESDOR_CLK_PERIOD_ns) + 1)
+
+ /* Add an extra (or two?) ESDOR_CLK_PERIOD_ns according to
+ * erroneous Erratum Engcm12377
+ */
+#define tRST_CKE (DIV_ROUND_UP(500000 + 2 * ESDOR_CLK_PERIOD_ns, ESDOR_CLK_PERIOD_ns) + 1)
+
+#define ROW_ADDR_BITS 14
+#define COL_ADDR_BITS 10
+
+ .iflt tWR - 7
+ .set mrs_val, (0x8080 | \
+ (3 << 4) /* MRS command */ | \
+ ((1 << 8) /* DLL Reset */ | \
+ ((tWR + 1 - 4) << 9) | \
+ (((tCL + 3) - 4) << 4)) << 16)
+ .else
+ .set mrs_val, (0x8080 | \
+ (3 << 4) /* MRS command */ | \
+ ((1 << 8) /* DLL Reset */ | \
+ (((tWR + 1) / 2) << 9) | \
+ (((tCL + 3) - 4) << 4)) << 16)
+ .endif
+#define ESDSCR_MRS_VAL(cs) (mrs_val | ((cs) << 3))
+
+#define ESDCFG0_VAL ( \
+ (tRFC << 24) | \
+ (tXS << 16) | \
+ (tXP << 13) | \
+ (tXPDLL << 9) | \
+ (tFAW << 4) | \
+ (tCL << 0)) \
+
+#define ESDCFG1_VAL ( \
+ (tRCD << 29) | \
+ (tRP << 26) | \
+ (tRC << 21) | \
+ (tRAS << 16) | \
+ (tRPA << 15) | \
+ (tWR << 9) | \
+ (tMRD << 5) | \
+ (tCWL << 0)) \
+
+#define ESDCFG2_VAL ( \
+ (tDLLK << 16) | \
+ (tRTP << 6) | \
+ (tWTR << 3) | \
+ (tRRD << 0))
+
+#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
+#define ESDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
+ ((COL_ADDR_BITS - 9) << 20) | \
+ (BURST_LEN << 19) | \
+ (1 << 16) | /* SDRAM bus width */ \
+ ((-1) << (32 - BANK_ADDR_BITS)))
+
+#define ESDMISC_VAL ((1 << 12) | \
+ (0x3 << 9) | \
+ (RALAT << 6) | \
+ (WALAT << 16) | \
+ (ADDR_MIRROR << 19) | \
+ (DDR_TYPE << 3))
+
+#define ESDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
+
+#define ESDOTC_VAL ((tAOFPD << 27) | \
+ (tAONPD << 24) | \
+ (tANPD << 20) | \
+ (tAXPD << 16) | \
+ (tODTLon << 12) | \
+ (tODTLoff << 4))
+
+fcb_start:
+ b _start
+ .word 0x20424346 /* "FCB " marker */
+ .word 0x01 /* FCB version number */
+ .org 0x68
+ .word 0x0 /* primary image starting page number */
+ .word 0x0 /* secondary image starting page number */
+ .word 0x6b
+ .word 0x6b
+ .word 0x0 /* DBBT start page (0 == NO DBBT) */
+ .word 0 /* Bad block marker offset in main area (unused) */
+ .org 0xac
+ .word 0 /* BI Swap disabled */
+ .word 0 /* Bad Block marker offset in spare area */
+fcb_end:
+
+ .org 0x400
+ivt_header:
+ .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
+app_start_addr:
+ .long _start
+ .long 0x0
+dcd_ptr:
+ .long dcd_hdr
+boot_data_ptr:
+ .word boot_data
+self_ptr:
+ .word ivt_header
+app_code_csf:
+ .word 0x0
+ .word 0x0
+boot_data:
+ .long fcb_start
+image_len:
+ .long CONFIG_U_BOOT_IMG_SIZE
+plugin:
+ .word 0
+ivt_end:
+#define DCD_VERSION 0x40
+
+dcd_hdr:
+ .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
+dcd_start:
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
+ /* disable all irrelevant clocks */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR0, 0xffcf0fff)
+ MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR1, 0x000fffc3)
+ MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR2, 0x033c0000)
+ MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR3, 0x000000ff)
+ MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR4, 0x00000000)
+ MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR5, 0x00fff033)
+ MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR6, 0x0f00030f)
+ MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR7, 0xfff00000)
+ MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CMEOR, 0x00000000)
+
+ MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x340, 0x11) /* GPIO_17 => RESET_OUT */
+
+ MXC_DCD_ITEM(0x63fd800c, 0x00000000) /* M4IF: MUX NFC signals on WEIM */
+#if SDRAM_CLK > 333
+ MXC_DCD_ITEM(0x53fd4014, 0x00888944) /* CBCDR */
+#else
+ MXC_DCD_ITEM(0x53fd4014, 0x00888644) /* CBCDR */
+#endif
+ MXC_DCD_ITEM(0x53fd4018, 0x00016154) /* CBCMR */
+
+ MXC_DCD_ITEM(0x53fd401c, 0xa6a2a020) /* CSCMR1 */
+ MXC_DCD_ITEM(0x53fd4020, 0xb6b12f0a) /* CSCMR2 */
+ MXC_DCD_ITEM(0x53fd4024, 0x00080b18) /* CSCDR1 */
+
+#define DDR_SEL_VAL 2
+#define DSE_VAL 5
+#define ODT_VAL 2
+
+#define DDR_SEL_SHIFT 25
+#define ODT_SHIFT 22
+#define DSE_SHIFT 19
+#define DDR_INPUT_SHIFT 9
+#define HYS_SHIFT 8
+#define PKE_SHIFT 7
+#define PUE_SHIFT 6
+#define PUS_SHIFT 4
+
+#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
+#define DSE_MASK (DSE_VAL << DSE_SHIFT)
+#define ODT_MASK (ODT_VAL << ODT_SHIFT)
+
+#define DQM_VAL DSE_MASK
+#define SDQS_VAL (ODT_MASK | DSE_MASK | (1 << PUE_SHIFT))
+#define SDODT_VAL (DSE_MASK | (0 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define SDCLK_VAL DSE_MASK
+#define SDCKE_VAL ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+
+ MXC_DCD_ITEM(0x53fa8724, DDR_SEL_MASK) /* DDR_TYPE: DDR3 */
+ MXC_DCD_ITEM(0x53fa86f4, 0 << DDR_INPUT_SHIFT) /* DDRMODE_CTL */
+ MXC_DCD_ITEM(0x53fa8714, 0 << DDR_INPUT_SHIFT) /* GRP_DDRMODE */
+ MXC_DCD_ITEM(0x53fa86fc, 1 << PKE_SHIFT) /* GRP_DDRPKE */
+ MXC_DCD_ITEM(0x53fa8710, 0 << HYS_SHIFT) /* GRP_DDRHYS */
+ MXC_DCD_ITEM(0x53fa8708, 1 << PUE_SHIFT) /* GRP_DDRPK */
+
+ MXC_DCD_ITEM(0x53fa8584, DQM_VAL) /* DQM0 */
+ MXC_DCD_ITEM(0x53fa8594, DQM_VAL) /* DQM1 */
+ MXC_DCD_ITEM(0x53fa8560, DQM_VAL) /* DQM2 */
+ MXC_DCD_ITEM(0x53fa8554, DQM_VAL) /* DQM3 */
+
+ MXC_DCD_ITEM(0x53fa857c, SDQS_VAL) /* SDQS0 */
+ MXC_DCD_ITEM(0x53fa8590, SDQS_VAL) /* SDQS1 */
+ MXC_DCD_ITEM(0x53fa8568, SDQS_VAL) /* SDQS2 */
+ MXC_DCD_ITEM(0x53fa8558, SDQS_VAL) /* SDQS3 */
+
+ MXC_DCD_ITEM(0x53fa8580, SDODT_VAL) /* SDODT0 */
+ MXC_DCD_ITEM(0x53fa8578, SDCLK_VAL) /* SDCLK0 */
+
+ MXC_DCD_ITEM(0x53fa8564, SDODT_VAL) /* SDODT1 */
+ MXC_DCD_ITEM(0x53fa8570, SDCLK_VAL) /* SDCLK1 */
+
+ MXC_DCD_ITEM(0x53fa858c, SDCKE_VAL) /* SDCKE0 */
+ MXC_DCD_ITEM(0x53fa855c, SDCKE_VAL) /* SDCKE1 */
+
+ MXC_DCD_ITEM(0x53fa8574, DSE_MASK) /* DRAM_CAS */
+ MXC_DCD_ITEM(0x53fa8588, DSE_MASK) /* DRAM_RAS */
+
+ MXC_DCD_ITEM(0x53fa86f0, DSE_MASK) /* GRP_ADDDS */
+ MXC_DCD_ITEM(0x53fa8720, DSE_MASK) /* GRP_CTLDS */
+ MXC_DCD_ITEM(0x53fa8718, DSE_MASK) /* GRP_B0DS */
+ MXC_DCD_ITEM(0x53fa871c, DSE_MASK) /* GRP_B1DS */
+ MXC_DCD_ITEM(0x53fa8728, DSE_MASK) /* GRP_B2DS */
+ MXC_DCD_ITEM(0x53fa872c, DSE_MASK) /* GRP_B3DS */
+
+ /* calibration defaults */
+ MXC_DCD_ITEM(0x63fd904c, 0x001f001f)
+ MXC_DCD_ITEM(0x63fd9050, 0x001f001f)
+ MXC_DCD_ITEM(0x63fd907c, 0x011e011e)
+ MXC_DCD_ITEM(0x63fd9080, 0x011f0120)
+ MXC_DCD_ITEM(0x63fd9088, 0x3a393d3b)
+ MXC_DCD_ITEM(0x63fd9090, 0x3f3f3f3f)
+
+ MXC_DCD_ITEM(0x63fd9018, ESDMISC_VAL)
+ MXC_DCD_ITEM(0x63fd9000, ESDCTL_VAL)
+ MXC_DCD_ITEM(0x63fd900c, ESDCFG0_VAL)
+ MXC_DCD_ITEM(0x63fd9010, ESDCFG1_VAL)
+ MXC_DCD_ITEM(0x63fd9014, ESDCFG2_VAL)
+
+ MXC_DCD_ITEM(0x63fd902c, 0x000026d2)
+ MXC_DCD_ITEM(0x63fd9030, ESDOR_VAL)
+ MXC_DCD_ITEM(0x63fd9008, ESDOTC_VAL)
+ MXC_DCD_ITEM(0x63fd9004, 0x00030012)
+
+ /* MR0 - CS0 */
+ MXC_DCD_ITEM(0x63fd901c, 0x00008032) /* MRS: MR2 */
+ MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: MR3 */
+ MXC_DCD_ITEM(0x63fd901c, 0x00408031) /* MRS: MR1 */
+ MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0)) /* MRS: MR0 */
+ /* MR0 - CS1 */
+#if BANK_ADDR_BITS > 1
+ MXC_DCD_ITEM(0x63fd901c, 0x0000803a) /* MRS: MR2 */
+ MXC_DCD_ITEM(0x63fd901c, 0x0000803b) /* MRS: MR3 */
+ MXC_DCD_ITEM(0x63fd901c, 0x00408039) /* MRS: MR1 */
+ MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1)) /* MRS: MR0 */
+#endif
+ MXC_DCD_ITEM(0x63fd9020, 0x00005800) /* refresh interval */
+ MXC_DCD_ITEM(0x63fd9058, 0x00011112)
+
+ MXC_DCD_ITEM(0x63fd90d0, 0x00000003) /* select default compare pattern for calibration */
+
+ /* ZQ calibration */
+ MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
+ MXC_DCD_ITEM(0x63fd901c, 0x00008040) /* MRS: ZQ calibration */
+ MXC_DCD_ITEM(0x63fd9040, 0x0539002b) /* Force ZQ calibration */
+zq_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9040, 0x00010000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
+
+ /* Write Leveling */
+ MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
+ MXC_DCD_ITEM(0x63fd901c, 0x00848231) /* MRS: start write leveling */
+ MXC_DCD_ITEM(0x63fd901c, 0x00000000)
+ MXC_DCD_ITEM(0x63fd9048, 0x00000001)
+wl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9048, 0x00000001)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
+ MXC_DCD_ITEM(0x63fd901c, 0x00048031) /* MRS: end write leveling */
+ MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
+
+ /* DQS calibration */
+ MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
+ MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
+ MXC_DCD_ITEM(0x63fd907c, 0x90000000) /* reset RD fifo and start DQS calib. */
+dqs_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd907c, 0x90000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
+ MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
+
+ /* WR DL calibration */
+ MXC_DCD_ITEM(0x63fd901c, 0x00000000)
+ MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
+ MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
+ MXC_DCD_ITEM(0x63fd90a4, 0x00000010)
+wr_dl_calib: /* 6c4 */
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a4, 0x00000010)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
+ MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
+
+ /* RD DL calibration */
+ MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
+ MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
+ MXC_DCD_ITEM(0x63fd90a0, 0x00000010)
+rd_dl_calib: /* 70c */
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a0, 0x00000010)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end)
+ MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
+
+ MXC_DCD_ITEM(0x63fd901c, 0x00000000)
+
+ MXC_DCD_ITEM(0x53fa8004, 0x00194005) @ set LDO to 1.3V
+
+ /* setup NFC pads */
+ /* MUX_SEL */
+ MXC_DCD_ITEM(0x53fa819c, 0x00000000) @ EIM_DA0
+ MXC_DCD_ITEM(0x53fa81a0, 0x00000000) @ EIM_DA1
+ MXC_DCD_ITEM(0x53fa81a4, 0x00000000) @ EIM_DA2
+ MXC_DCD_ITEM(0x53fa81a8, 0x00000000) @ EIM_DA3
+ MXC_DCD_ITEM(0x53fa81ac, 0x00000000) @ EIM_DA4
+ MXC_DCD_ITEM(0x53fa81b0, 0x00000000) @ EIM_DA5
+ MXC_DCD_ITEM(0x53fa81b4, 0x00000000) @ EIM_DA6
+ MXC_DCD_ITEM(0x53fa81b8, 0x00000000) @ EIM_DA7
+ MXC_DCD_ITEM(0x53fa81dc, 0x00000000) @ WE_B
+ MXC_DCD_ITEM(0x53fa81e0, 0x00000000) @ RE_B
+ MXC_DCD_ITEM(0x53fa8228, 0x00000000) @ CLE
+ MXC_DCD_ITEM(0x53fa822c, 0x00000000) @ ALE
+ MXC_DCD_ITEM(0x53fa8230, 0x00000000) @ WP_B
+ MXC_DCD_ITEM(0x53fa8234, 0x00000000) @ RB0
+ MXC_DCD_ITEM(0x53fa8238, 0x00000000) @ CS0
+ /* PAD_CTL */
+ MXC_DCD_ITEM(0x53fa84ec, 0x000000e4) @ EIM_DA0
+ MXC_DCD_ITEM(0x53fa84f0, 0x000000e4) @ EIM_DA1
+ MXC_DCD_ITEM(0x53fa84f4, 0x000000e4) @ EIM_DA2
+ MXC_DCD_ITEM(0x53fa84f8, 0x000000e4) @ EIM_DA3
+ MXC_DCD_ITEM(0x53fa84fc, 0x000000e4) @ EIM_DA4
+ MXC_DCD_ITEM(0x53fa8500, 0x000000e4) @ EIM_DA5
+ MXC_DCD_ITEM(0x53fa8504, 0x000000e4) @ EIM_DA6
+ MXC_DCD_ITEM(0x53fa8508, 0x000000e4) @ EIM_DA7
+ MXC_DCD_ITEM(0x53fa852c, 0x00000004) @ NANDF_WE_B
+ MXC_DCD_ITEM(0x53fa8530, 0x00000004) @ NANDF_RE_B
+ MXC_DCD_ITEM(0x53fa85a0, 0x00000004) @ NANDF_CLE_B
+ MXC_DCD_ITEM(0x53fa85a4, 0x00000004) @ NANDF_ALE_B
+ MXC_DCD_ITEM(0x53fa85a8, 0x000000e4) @ NANDF_WE_B
+ MXC_DCD_ITEM(0x53fa85ac, 0x000000e4) @ NANDF_RB0
+ MXC_DCD_ITEM(0x53fa85b0, 0x00000004) @ NANDF_CS0
+dcd_end:
+ .ifgt dcd_end - dcd_start - 1768
+ DCD too large!
+ .endif
--- /dev/null
+/*
+ * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <lcd.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <video_fb.h>
+#include <ipu.h>
+#include <mx2fb.h>
+#include <linux/fb.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+
+#include "../common/karo.h"
+
+#define TX53_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
+#define TX53_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
+#define TX53_FEC_INT_GPIO IMX_GPIO_NR(2, 4)
+#define TX53_LED_GPIO IMX_GPIO_NR(2, 20)
+
+#define TX53_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
+#define TX53_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
+#define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
+
+#define TX53_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MX53_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
+
+#define TX53_SDHC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
+
+static iomux_v3_cfg_t tx53_pads[] = {
+ /* NAND flash pads are set up in lowlevel_init.S */
+
+ /* RESET_OUT */
+ MX53_PAD_GPIO_17__GPIO7_12,
+
+ /* UART pads */
+#if CONFIG_MXC_UART_BASE == UART1_BASE
+ MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
+ MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
+ MX53_PAD_PATA_IORDY__UART1_RTS,
+ MX53_PAD_PATA_RESET_B__UART1_CTS,
+#endif
+#if CONFIG_MXC_UART_BASE == UART2_BASE
+ MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
+ MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
+ MX53_PAD_PATA_DIOR__UART2_RTS,
+ MX53_PAD_PATA_INTRQ__UART2_CTS,
+#endif
+#if CONFIG_MXC_UART_BASE == UART3_BASE
+ MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
+ MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
+ MX53_PAD_PATA_DA_2__UART3_RTS,
+ MX53_PAD_PATA_DA_1__UART3_CTS,
+#endif
+ /* internal I2C */
+ MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
+ MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
+
+ /* FEC PHY GPIO functions */
+ MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
+ MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
+ MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
+
+ /* FEC functions */
+ MX53_PAD_FEC_MDC__FEC_MDC,
+ MX53_PAD_FEC_MDIO__FEC_MDIO,
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN,
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1,
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0,
+};
+
+static const struct gpio tx53_gpios[] = {
+ { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
+ { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
+ { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
+ { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
+};
+
+/*
+ * Functions
+ */
+/* placed in section '.data' to prevent overwriting relocation info
+ * overlayed with bss
+ */
+static u32 wrsr __attribute__((section(".data")));
+
+#define WRSR_POR (1 << 4)
+#define WRSR_TOUT (1 << 1)
+#define WRSR_SFTW (1 << 0)
+
+static void print_reset_cause(void)
+{
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
+ u32 srsr;
+ char *dlm = "";
+
+ printf("Reset cause: ");
+
+ srsr = readl(&src_regs->srsr);
+ wrsr = readw(wdt_base + 4);
+
+ if (wrsr & WRSR_POR) {
+ printf("%sPOR", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00004) {
+ printf("%sCSU", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00008) {
+ printf("%sIPP USER", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00010) {
+ if (wrsr & WRSR_SFTW) {
+ printf("%sSOFT", dlm);
+ dlm = " | ";
+ }
+ if (wrsr & WRSR_TOUT) {
+ printf("%sWDOG", dlm);
+ dlm = " | ";
+ }
+ }
+ if (srsr & 0x00020) {
+ printf("%sJTAG HIGH-Z", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00040) {
+ printf("%sJTAG SW", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x10000) {
+ printf("%sWARM BOOT", dlm);
+ dlm = " | ";
+ }
+ if (dlm[0] == '\0')
+ printf("unknown");
+
+ printf("\n");
+}
+
+static void print_cpuinfo(void)
+{
+ u32 cpurev;
+
+ cpurev = get_cpu_rev();
+
+ printf("CPU: Freescale i.MX53 rev%d.%d at %d MHz\n",
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+
+ print_reset_cause();
+}
+
+int board_early_init_f(void)
+{
+ gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
+ imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
+
+ writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
+ writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
+
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
+ writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
+
+ writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
+ writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
+
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
+ writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
+ return 0;
+}
+
+int dram_init(void)
+{
+ int ret;
+
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+
+ ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
+ CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
+ if (ret)
+ printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
+ CONFIG_SYS_SDRAM_CLK, ret);
+ else
+ debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
+ __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
+ mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
+ CONFIG_SYS_SDRAM_CLK);
+ return ret;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+#if CONFIG_NR_DRAM_BANKS > 1
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
+ PHYS_SDRAM_2_SIZE);
+#endif
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = mmc->priv;
+
+ if (cfg->cd_gpio < 0)
+ return cfg->cd_gpio;
+
+ return !gpio_get_value(cfg->cd_gpio);
+}
+
+static struct fsl_esdhc_cfg esdhc_cfg[] = {
+ {
+ .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
+ .cd_gpio = IMX_GPIO_NR(3, 24),
+ .wp_gpio = -EINVAL,
+ },
+ {
+ .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
+ .cd_gpio = IMX_GPIO_NR(3, 25),
+ .wp_gpio = -EINVAL,
+ },
+};
+
+static const iomux_v3_cfg_t mmc0_pads[] = {
+ MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
+ /* SD1 CD */
+ MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
+};
+
+static const iomux_v3_cfg_t mmc1_pads[] = {
+ MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
+ MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
+ /* SD2 CD */
+ MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
+};
+
+static struct {
+ const iomux_v3_cfg_t *pads;
+ int count;
+} mmc_pad_config[] = {
+ { mmc0_pads, ARRAY_SIZE(mmc0_pads), },
+ { mmc1_pads, ARRAY_SIZE(mmc1_pads), },
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(esdhc_cfg); i++) {
+ struct mmc *mmc;
+
+ if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
+ break;
+
+ imx_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads,
+ mmc_pad_config[i].count);
+ fsl_esdhc_initialize(bis, &esdhc_cfg[i]);
+
+ mmc = find_mmc_device(i);
+ if (mmc == NULL)
+ continue;
+ if (board_mmc_getcd(mmc) > 0)
+ mmc_init(mmc);
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_MMC */
+
+#ifdef CONFIG_FEC_MXC
+
+#ifndef ETH_ALEN
+#define ETH_ALEN 6
+#endif
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ int i;
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ struct fuse_bank *bank = &iim->bank[1];
+ struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
+
+ if (dev_id > 0)
+ return;
+
+ for (i = 0; i < ETH_ALEN; i++)
+ mac[i] = readl(&fuse->mac_addr[i]);
+}
+
+#define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_SRE_FAST)
+#define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
+#define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+ unsigned char mac[ETH_ALEN];
+ char mac_str[ETH_ALEN * 3] = "";
+
+ /* delay at least 21ms for the PHY internal POR signal to deassert */
+ udelay(22000);
+
+ /* Deassert RESET to the external phy */
+ gpio_set_value(TX53_FEC_RST_GPIO, 1);
+
+ ret = cpu_eth_init(bis);
+ if (ret) {
+ printf("cpu_eth_init() failed: %d\n", ret);
+ return ret;
+ }
+
+ imx_get_mac_from_fuse(0, mac);
+ snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ setenv("ethaddr", mac_str);
+
+ return ret;
+}
+#endif /* CONFIG_FEC_MXC */
+
+enum {
+ LED_STATE_INIT = -1,
+ LED_STATE_OFF,
+ LED_STATE_ON,
+};
+
+void show_activity(int arg)
+{
+ static int led_state = LED_STATE_INIT;
+ static ulong last;
+
+ if (led_state == LED_STATE_INIT) {
+ last = get_timer(0);
+ gpio_set_value(TX53_LED_GPIO, 1);
+ led_state = LED_STATE_ON;
+ } else {
+ if (get_timer(last) > CONFIG_SYS_HZ) {
+ last = get_timer(0);
+ if (led_state == LED_STATE_ON) {
+ gpio_set_value(TX53_LED_GPIO, 0);
+ } else {
+ gpio_set_value(TX53_LED_GPIO, 1);
+ }
+ led_state = 1 - led_state;
+ }
+ }
+}
+
+static const iomux_v3_cfg_t stk5_pads[] = {
+ /* SW controlled LED on STK5 baseboard */
+ MX53_PAD_EIM_A18__GPIO2_20,
+
+ /* I2C bus on DIMM pins 40/41 */
+ MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
+ MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
+
+ /* TSC200x PEN IRQ */
+ MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
+
+ /* EDT-FT5x06 Polytouch panel */
+ MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
+ MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
+ MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
+
+ /* USBH1 */
+ MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
+ MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
+ /* USBOTG */
+ MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
+ MX53_PAD_GPIO_8__GPIO1_8, /* OC */
+
+ /* DS1339 Interrupt */
+ MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
+};
+
+static const struct gpio stk5_gpios[] = {
+ { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
+
+ { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
+ { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
+ { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
+ { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
+};
+
+#ifdef CONFIG_LCD
+static ushort tx53_cmap[256];
+vidinfo_t panel_info = {
+ /* set to max. size supported by SoC */
+ .vl_col = 1600,
+ .vl_row = 1200,
+
+ .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+ .cmap = tx53_cmap,
+};
+
+static struct fb_videomode tx53_fb_mode = {
+ /* Standard VGA timing */
+ .name = "VGA",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
+static int lcd_enabled = 1;
+
+void lcd_enable(void)
+{
+ /* HACK ALERT:
+ * global variable from common/lcd.c
+ * Set to 0 here to prevent messages from going to LCD
+ * rather than serial console
+ */
+ lcd_is_enabled = 0;
+
+ karo_load_splashimage(1);
+ if (lcd_enabled) {
+ debug("Switching LCD on\n");
+ gpio_set_value(TX53_LCD_PWR_GPIO, 1);
+ udelay(100);
+ gpio_set_value(TX53_LCD_RST_GPIO, 1);
+ udelay(300000);
+ gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 0);
+ }
+}
+
+static const iomux_v3_cfg_t stk5_lcd_pads[] = {
+ /* LCD RESET */
+ MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
+ /* LCD POWER_ENABLE */
+ MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
+ /* LCD Backlight (PWM) */
+ MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
+
+ /* Display */
+ MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
+ MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
+ MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
+ MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
+ MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
+ MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
+ MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
+ MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
+ MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
+ MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
+ MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
+ MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
+ MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
+ MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
+ MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
+ MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
+ MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
+ MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
+ MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
+ MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
+ MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
+ MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
+ MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
+ MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
+ MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
+ MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
+ MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
+ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
+
+ /* LVDS option */
+ MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
+ MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
+ MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
+ MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
+ MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
+ MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
+ MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
+ MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
+ MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
+ MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
+};
+
+static const struct gpio stk5_lcd_gpios[] = {
+ { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
+ { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
+ { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+};
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ int color_depth = 24;
+ char *vm;
+ unsigned long val;
+ int refresh = 60;
+ struct fb_videomode *p = &tx53_fb_mode;
+ int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
+ int pix_fmt = 0;
+ ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
+ unsigned long di_clk_rate = 65000000;
+
+ if (!lcd_enabled) {
+ debug("LCD disabled\n");
+ return;
+ }
+
+ if (tstc() || (wrsr & WRSR_TOUT)) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ return;
+ }
+
+ vm = getenv("video_mode");
+ if (vm == NULL) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ return;
+ }
+ while (*vm != '\0') {
+ if (*vm >= '0' && *vm <= '9') {
+ char *end;
+
+ val = simple_strtoul(vm, &end, 0);
+ if (end > vm) {
+ if (!xres_set) {
+ if (val > panel_info.vl_col)
+ val = panel_info.vl_col;
+ p->xres = val;
+ panel_info.vl_col = val;
+ xres_set = 1;
+ } else if (!yres_set) {
+ if (val > panel_info.vl_row)
+ val = panel_info.vl_row;
+ p->yres = val;
+ panel_info.vl_row = val;
+ yres_set = 1;
+ } else if (!bpp_set) {
+ switch (val) {
+ case 24:
+ if (pix_fmt == IPU_PIX_FMT_LVDS666)
+ pix_fmt = IPU_PIX_FMT_LVDS888;
+ /* fallthru */
+ case 16:
+ case 8:
+ color_depth = val;
+ break;
+
+ case 18:
+ if (pix_fmt == IPU_PIX_FMT_LVDS666) {
+ color_depth = val;
+ break;
+ }
+ /* fallthru */
+ default:
+ printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
+ end - vm, vm, color_depth);
+ }
+ bpp_set = 1;
+ } else if (!refresh_set) {
+ refresh = val;
+ refresh_set = 1;
+ }
+ }
+ vm = end;
+ }
+ switch (*vm) {
+ case '@':
+ bpp_set = 1;
+ /* fallthru */
+ case '-':
+ yres_set = 1;
+ /* fallthru */
+ case 'x':
+ xres_set = 1;
+ /* fallthru */
+ case 'M':
+ case 'R':
+ vm++;
+ break;
+
+ default:
+ if (!pix_fmt) {
+ char *tmp;
+
+ if (strncmp(vm, "LVDS", 4) == 0) {
+ pix_fmt = IPU_PIX_FMT_LVDS666;
+ di_clk_parent = DI_PCLK_LDB;
+ } else {
+ pix_fmt = IPU_PIX_FMT_RGB24;
+ }
+ tmp = strchr(vm, ':');
+ if (tmp)
+ vm = tmp;
+ }
+ if (*vm != '\0')
+ vm++;
+ }
+ }
+ switch (color_depth) {
+ case 8:
+ panel_info.vl_bpix = 3;
+ break;
+
+ case 16:
+ panel_info.vl_bpix = 4;
+ break;
+
+ case 18:
+ case 24:
+ panel_info.vl_bpix = 5;
+ }
+
+ p->pixclock = KHZ2PICOS(refresh *
+ (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
+ (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
+ / 1000);
+ debug("Pixel clock set to %lu.%03lu MHz\n",
+ PICOS2KHZ(p->pixclock) / 1000,
+ PICOS2KHZ(p->pixclock) % 1000);
+
+ gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
+ imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
+ ARRAY_SIZE(stk5_lcd_pads));
+
+ debug("Initializing FB driver\n");
+ if (!pix_fmt)
+ pix_fmt = IPU_PIX_FMT_RGB24;
+ else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
+ writel(0x01, IOMUXC_BASE_ADDR + 8);
+ } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
+ writel(0x21, IOMUXC_BASE_ADDR + 8);
+ }
+ if (pix_fmt != IPU_PIX_FMT_RGB24) {
+ struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ /* enable LDB & DI0 clock */
+ writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10),
+ &ccm_regs->CCGR6);
+ }
+
+ if (karo_load_splashimage(0) == 0) {
+ ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
+
+ debug("Initializing LCD controller\n");
+// video_hw_init();
+ } else {
+ debug("Skipping initialization of LCD controller\n");
+ }
+}
+#else
+#define lcd_enabled 0
+#endif /* CONFIG_LCD */
+
+static void stk5_board_init(void)
+{
+ gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
+ imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
+}
+
+static void stk5v3_board_init(void)
+{
+ stk5_board_init();
+}
+
+static void stk5v5_board_init(void)
+{
+ stk5_board_init();
+
+ gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
+ "Flexcan Transceiver");
+ imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
+}
+
+static void tx53_set_cpu_clock(void)
+{
+ unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
+ int ret;
+
+ if (tstc() || (wrsr & WRSR_TOUT))
+ return;
+
+ if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
+ return;
+
+ ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
+ if (ret != 0) {
+ printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
+ return;
+ }
+ printf("CPU clock set to %u.%03u MHz\n",
+ mxc_get_clock(MXC_ARM_CLK) / 1000000,
+ mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
+}
+
+int board_late_init(void)
+{
+ int ret = 0;
+ const char *baseboard;
+
+ tx53_set_cpu_clock();
+ karo_fdt_move_fdt();
+
+ baseboard = getenv("baseboard");
+ if (!baseboard)
+ goto exit;
+
+ if (strncmp(baseboard, "stk5", 4) == 0) {
+ printf("Baseboard: %s\n", baseboard);
+ if ((strlen(baseboard) == 4) ||
+ strcmp(baseboard, "stk5-v3") == 0) {
+ stk5v3_board_init();
+ } else if (strcmp(baseboard, "stk5-v5") == 0) {
+ stk5v5_board_init();
+ } else {
+ printf("WARNING: Unsupported STK5 board rev.: %s\n",
+ baseboard + 4);
+ }
+ } else {
+ printf("WARNING: Unsupported baseboard: '%s'\n",
+ baseboard);
+ ret = -EINVAL;
+ }
+
+exit:
+ gpio_set_value(TX53_RESET_OUT_GPIO, 1);
+ return ret;
+}
+
+int checkboard(void)
+{
+ print_cpuinfo();
+
+ printf("Board: Ka-Ro TX53-xx3%s\n",
+ TX53_MOD_SUFFIX);
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+#include <jffs2/jffs2.h>
+#include <mtd_node.h>
+struct node_info nodes[] = {
+ { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
+};
+
+#else
+#define fdt_fixup_mtdparts(b,n,c) do { } while (0)
+#endif
+
+static void tx53_fixup_flexcan(void *blob)
+{
+ const char *baseboard = getenv("baseboard");
+
+ if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
+ return;
+
+ karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fc8000, "transceiver-switch");
+ karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fcc000, "transceiver-switch");
+}
+
+#ifdef CONFIG_SYS_TX53_HWREV_2
+void tx53_fixup_rtc(void *blob)
+{
+ karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
+ karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
+}
+#else
+static inline void tx53_fixup_rtc(void *blob)
+{
+}
+#endif
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ fdt_fixup_ethernet(blob);
+
+ karo_fdt_enable_node(blob, "ipu", getenv("video_mode") != NULL);
+ karo_fdt_fixup_touchpanel(blob);
+ karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", 0x53f80000);
+ tx53_fixup_flexcan(blob);
+ tx53_fixup_rtc(blob);
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ board/karo/tx53/lowlevel_init.o (.text*)
+ __image_copy_start = .;
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
+ . = ALIGN(4);
+
+ __image_copy_end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ _end = .;
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
--- /dev/null
+#
+# (C) Copyright 2009 DENX Software Engineering
+# Author: John Rigby <jcrigby@gmail.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := tx6q.o
+SOBJS := lowlevel_init.o
+ifeq ($(CONFIG_SPL_BUILD),y)
+ COBJS += spl_boot.o
+else
+ifeq ($(CONFIG_CMD_ROMUPDATE),y)
+ COBJS += flash.o
+endif
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+# stack is allocated below CONFIG_SYS_TEXT_BASE
+CONFIG_SYS_TEXT_BASE := 0x27800000
+#CONFIG_SYS_TEXT_BASE := 0x17800000
+#CONFIG_SPL_TEXT_BASE := 0x00000000
+
+LOGO_BMP = logos/karo.bmp
+#PLATFORM_CPPFLAGS += -DDEBUG
+PLATFORM_CPPFLAGS += -Wno-unused-but-set-variable
+
+PLATFORM_CPPFLAGS += -Werror
+#ifneq ($(CONFIG_SPL_BUILD),y)
+# ALL-y += $(obj)u-boot.sb
+#endif
--- /dev/null
+/*
+ * Table 8-35. Valid DCD Address Ranges
+ * Address range Start address Last Address
+ * IRAM Free Space 0x00907000 0x00937FF0
+ * CCM register set 0x020C4000 0x020C7FFF
+ * ANADIG registers 0x020C8000 0x020C8FFF
+ * IOMUX Control (IOMUXC) registers 0x020E0000 0x020E3FFF
+ * MMDC register set 0x021B0000 0x021B7FFF
+ * EIM 0x08000000 0x0FFEFFFF
+ * DDR 0x10000000 0xFFFFFFFF
+ */
+
+#define CPU_2_BE_32(l) \
+ ((((l) << 24) & 0xFF000000) | \
+ (((l) << 8) & 0x00FF0000) | \
+ (((l) >> 8) & 0x0000FF00) | \
+ (((l) >> 24) & 0x000000FF))
+
+#define CHECK_DCD_ADDR(a) ((((a) >= 0x00907000) && ((a) <= 0x00937FF0)) || \
+ (((a) >= 0x020C4000) && ((a) < 0x020C8000)) || \
+ (((a) >= 0x020C8000) && ((a) < 0x020C9000)) || \
+ (((a) >= 0x020E0000) && ((a) < 0x020E4000)) || \
+ (((a) >= 0x021B0000) && ((a) < 0x021B8000)) || \
+ (((a) >= 0x08000000) && ((a) < 0x0FFF0000)) || \
+ (((a) >= 0x10000000)))
+
+#define __MXC_DCD_ITEM(addr, val) \
+ CPU_2_BE_32(addr), CPU_2_BE_32(val)
+
+#define MXC_DCD_ITEM(addr, val) (CHECK_DCD_ADDR(addr) ? __MXC_DCD_ITEM(addr, val) : bad_dcd_address)
+
+#define MXC_DCD_CMD_WRT(type, flags, next) \
+ CPU_2_BE_32((0xcc << 24) | ((next) << 8) | ((flags) << 3) | (type))
+
+unsigned long dcd_start[] = {
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end)
+
+ /* RESET_OUT GPIO_7_12 */
+ MXC_DCD_ITEM(0x20e024c, 0x00000005),
+#if 1
+ /* STK5 LED GPIO */
+ MXC_DCD_ITEM(0x020e00ec, (1 << 20)),
+#endif
+ MXC_DCD_ITEM(0x020c402c, 0x01e436c1), /* CSC2CDR default: 0x007236c1 */
+ MXC_DCD_ITEM(0x020c80e0, 0x00002001), /* ENET PLL */
+ MXC_DCD_ITEM(0x020e0004, 0x48640005), /* default: 0x48400005 ENET_CLK output */
+#if 1
+ /* enable all relevant clocks... */
+ MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f), /* default: 0xf0c03f0f APBH-DMA */
+ MXC_DCD_ITEM(0x020c406c, 0xf0fc0c00), /* default: 0xf0fc0000 */
+ MXC_DCD_ITEM(0x020c4070, 0xfc3ff00c), /* default: 0xfc3ff00c */
+ MXC_DCD_ITEM(0x020c4074, 0x3ff00000), /* default: 0x3ff00000 */
+ MXC_DCD_ITEM(0x020c4078, 0xff00ff00), /* default: 0x0000ff00 GPMI BCH */
+ MXC_DCD_ITEM(0x020c407c, 0xff033f0f), /* default: 0xf0033f0f UART1 */
+ MXC_DCD_ITEM(0x020c4080, 0xffff03c3), /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
+
+// MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f), /* default: 0xf0c03f0f */
+// MXC_DCD_ITEM(0x020c406c, 0xf0fc0000),
+// MXC_DCD_ITEM(0x020c4070, 0xfc3ff00c),
+// MXC_DCD_ITEM(0x020c4074, 0x3ff00000),
+// MXC_DCD_ITEM(0x020c4078, 0x0000ff00),
+// /* enable UART clocks */
+// MXC_DCD_ITEM(0x020c407c, 0xff033f0f), /* default: 0xf0033f0f */
+// MXC_DCD_ITEM(0x020c4080, 0xffff00c3), /* default: 0xffff0003 */
+#else
+ /* enable all clocks... */
+ MXC_DCD_ITEM(0x020c4068, 0xffffffff),
+ MXC_DCD_ITEM(0x020c406c, 0xffffffff),
+ MXC_DCD_ITEM(0x020c4070, 0xffffffff),
+ MXC_DCD_ITEM(0x020c4074, 0xffffffff),
+ MXC_DCD_ITEM(0x020c4078, 0xffffffff),
+ MXC_DCD_ITEM(0x020c407c, 0xffffffff),
+ MXC_DCD_ITEM(0x020c4080, 0xffffffff),
+#endif
+ /* UART1 pad config */
+ MXC_DCD_ITEM(0x020e02a8, 0x00000001), /* UART1 TXD */
+ MXC_DCD_ITEM(0x020e02ac, 0x00000001), /* UART1 RXD */
+ MXC_DCD_ITEM(0x020e0920, 0x00000003), /* UART1 RXD INPUT_SEL */
+ MXC_DCD_ITEM(0x020e02c0, 0x00000001), /* UART1 CTS */
+ MXC_DCD_ITEM(0x020e02c4, 0x00000001), /* UART1 RTS */
+ MXC_DCD_ITEM(0x020e091c, 0x00000003), /* UART1 RTS INPUT_SEL */
+
+ /* NAND */
+ MXC_DCD_ITEM(0x020e02d4, 0x00000000), /* NANDF_CLE: NANDF_CLE */
+ MXC_DCD_ITEM(0x020e02d8, 0x00000000), /* NANDF_ALE: NANDF_ALE */
+ MXC_DCD_ITEM(0x020e02dc, 0x00000000), /* NANDF_WP_B: NANDF_WPn */
+ MXC_DCD_ITEM(0x020e02e0, 0x00000000), /* NANDF_RB0: NANDF_READY0 */
+ MXC_DCD_ITEM(0x020e02e4, 0x00000000), /* NANDF_CS0: NANDF_CS0 */
+ MXC_DCD_ITEM(0x020e02f4, 0x00000001), /* SD4_CMD: NANDF_RDn */
+ MXC_DCD_ITEM(0x020e02f8, 0x00000001), /* SD4_CLK: NANDF_WRn */
+
+ MXC_DCD_ITEM(0x020e02fc, 0x00000000), /* NANDF_D0: NANDF_D0 */
+ MXC_DCD_ITEM(0x020e0300, 0x00000000), /* NANDF_D1: NANDF_D1 */
+ MXC_DCD_ITEM(0x020e0304, 0x00000000), /* NANDF_D2: NANDF_D2 */
+ MXC_DCD_ITEM(0x020e0308, 0x00000000), /* NANDF_D3: NANDF_D3 */
+ MXC_DCD_ITEM(0x020e030c, 0x00000000), /* NANDF_D4: NANDF_D4 */
+ MXC_DCD_ITEM(0x020e0310, 0x00000000), /* NANDF_D5: NANDF_D5 */
+ MXC_DCD_ITEM(0x020e0314, 0x00000000), /* NANDF_D6: NANDF_D6 */
+ MXC_DCD_ITEM(0x020e0318, 0x00000000), /* NANDF_D7: NANDF_D7 */
+
+ /* ext. mem CS */
+ MXC_DCD_ITEM(0x020e02ec, 0x00000000), /* NANDF_CS2: NANDF_CS2 */
+
+ MXC_DCD_ITEM(0x020e05a8, 0x00000030),
+ MXC_DCD_ITEM(0x020e05b0, 0x00000030),
+ MXC_DCD_ITEM(0x020e0524, 0x00000030),
+ MXC_DCD_ITEM(0x020e051c, 0x00000030),
+ MXC_DCD_ITEM(0x020e0518, 0x00000030),
+ MXC_DCD_ITEM(0x020e050c, 0x00000030),
+ MXC_DCD_ITEM(0x020e05b8, 0x00000030),
+ MXC_DCD_ITEM(0x020e05c0, 0x00000030),
+ MXC_DCD_ITEM(0x020e05ac, 0x00020030),
+ MXC_DCD_ITEM(0x020e05b4, 0x00020030),
+ MXC_DCD_ITEM(0x020e0528, 0x00020030),
+ MXC_DCD_ITEM(0x020e0520, 0x00020030),
+ MXC_DCD_ITEM(0x020e0514, 0x00020030),
+ MXC_DCD_ITEM(0x020e0510, 0x00020030),
+ MXC_DCD_ITEM(0x020e05bc, 0x00020030),
+ MXC_DCD_ITEM(0x020e05c4, 0x00020030),
+ MXC_DCD_ITEM(0x020e056c, 0x00020030),
+ MXC_DCD_ITEM(0x020e0578, 0x00020030),
+ MXC_DCD_ITEM(0x020e0588, 0x00020030),
+ MXC_DCD_ITEM(0x020e0594, 0x00020030),
+ MXC_DCD_ITEM(0x020e057c, 0x00020030),
+ MXC_DCD_ITEM(0x020e0590, 0x00003000),
+ MXC_DCD_ITEM(0x020e0598, 0x00003000),
+ MXC_DCD_ITEM(0x020e058c, 0x00000000),
+ MXC_DCD_ITEM(0x020e059c, 0x00003030),
+ MXC_DCD_ITEM(0x020e05a0, 0x00003030),
+ MXC_DCD_ITEM(0x020e0784, 0x00000030),
+ MXC_DCD_ITEM(0x020e0788, 0x00000030),
+ MXC_DCD_ITEM(0x020e0794, 0x00000030),
+ MXC_DCD_ITEM(0x020e079c, 0x00000030),
+ MXC_DCD_ITEM(0x020e07a0, 0x00000030),
+ MXC_DCD_ITEM(0x020e07a4, 0x00000030),
+ MXC_DCD_ITEM(0x020e07a8, 0x00000030),
+ MXC_DCD_ITEM(0x020e0748, 0x00000030),
+ MXC_DCD_ITEM(0x020e074c, 0x00000030),
+ MXC_DCD_ITEM(0x020e0750, 0x00020000),
+ MXC_DCD_ITEM(0x020e0758, 0x00000000),
+ MXC_DCD_ITEM(0x020e0774, 0x00020000),
+ MXC_DCD_ITEM(0x020e078c, 0x00000030),
+ MXC_DCD_ITEM(0x020e0798, 0x000c0000),
+ MXC_DCD_ITEM(0x021b081c, 0x33333333),
+ MXC_DCD_ITEM(0x021b0820, 0x33333333),
+ MXC_DCD_ITEM(0x021b0824, 0x33333333),
+ MXC_DCD_ITEM(0x021b0828, 0x33333333),
+ MXC_DCD_ITEM(0x021b481c, 0x33333333),
+ MXC_DCD_ITEM(0x021b4820, 0x33333333),
+ MXC_DCD_ITEM(0x021b4824, 0x33333333),
+ MXC_DCD_ITEM(0x021b4828, 0x33333333),
+ MXC_DCD_ITEM(0x021b0018, 0x00081740),
+ MXC_DCD_ITEM(0x021b001c, 0x00008000),
+ MXC_DCD_ITEM(0x021b000c, 0x555a7975),
+ MXC_DCD_ITEM(0x021b0010, 0xff538e64),
+ MXC_DCD_ITEM(0x021b0014, 0x01ff00db),
+ MXC_DCD_ITEM(0x021b002c, 0x000026d2),
+ MXC_DCD_ITEM(0x021b0030, 0x005b0e21),
+ MXC_DCD_ITEM(0x021b0008, 0x09444040),
+ MXC_DCD_ITEM(0x021b0004, 0x00025576),
+ MXC_DCD_ITEM(0x021b0040, 0x00000027),
+ MXC_DCD_ITEM(0x021b0000, 0x831a0000),
+ MXC_DCD_ITEM(0x021b001c, 0x04088032),
+ MXC_DCD_ITEM(0x021b001c, 0x0408803a),
+ MXC_DCD_ITEM(0x021b001c, 0x00008033),
+ MXC_DCD_ITEM(0x021b001c, 0x0000803b),
+ MXC_DCD_ITEM(0x021b001c, 0x00428031),
+ MXC_DCD_ITEM(0x021b001c, 0x00428039),
+ MXC_DCD_ITEM(0x021b001c, 0x09408030),
+ MXC_DCD_ITEM(0x021b001c, 0x09408038),
+ MXC_DCD_ITEM(0x021b001c, 0x04008040),
+ MXC_DCD_ITEM(0x021b001c, 0x04008048),
+ MXC_DCD_ITEM(0x021b0800, 0xa1380003),
+ MXC_DCD_ITEM(0x021b4800, 0xa1380003),
+ MXC_DCD_ITEM(0x021b0020, 0x00005800),
+ MXC_DCD_ITEM(0x021b0818, 0x00000007),
+ MXC_DCD_ITEM(0x021b4818, 0x00000007),
+ MXC_DCD_ITEM(0x021b083c, 0x434b0350),
+ MXC_DCD_ITEM(0x021b0840, 0x034c0359),
+ MXC_DCD_ITEM(0x021b483c, 0x434b0350),
+ MXC_DCD_ITEM(0x021b4840, 0x03650348),
+ MXC_DCD_ITEM(0x021b0848, 0x4436383b),
+ MXC_DCD_ITEM(0x021b4848, 0x39393341),
+ MXC_DCD_ITEM(0x021b0850, 0x35373933),
+ MXC_DCD_ITEM(0x021b4850, 0x48254a36),
+ MXC_DCD_ITEM(0x021b080c, 0x001f001f),
+ MXC_DCD_ITEM(0x021b0810, 0x001f001f),
+ MXC_DCD_ITEM(0x021b480c, 0x00440044),
+ MXC_DCD_ITEM(0x021b4810, 0x00440044),
+ MXC_DCD_ITEM(0x021b08b8, 0x00000800),
+ MXC_DCD_ITEM(0x021b48b8, 0x00000800),
+ MXC_DCD_ITEM(0x021b001c, 0x00000000),
+ MXC_DCD_ITEM(0x021b0404, 0x00011006),
+ dcd_end:
+};
--- /dev/null
+#include <common.h>
+#include <malloc.h>
+#include <nand.h>
+#include <errno.h>
+
+#include <linux/err.h>
+
+#include <asm/io.h>
+#include <asm/sizes.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/regs-gpmi.h>
+#include <asm/arch/regs-bch.h>
+
+#define FCB_START_BLOCK 0
+#define NUM_FCB_BLOCKS 1
+#define MAX_FCB_BLOCKS 32768
+
+#if CONFIG_SYS_NAND_U_BOOT_OFFS < 0x20000
+#error CONFIG_SYS_NAND_U_BOOT_OFFS must be >= 128kIB
+#endif
+
+struct mx6_nand_timing {
+ u8 data_setup;
+ u8 data_hold;
+ u8 address_setup;
+ u8 dsample_time;
+ u8 nand_timing_state;
+ u8 tREA;
+ u8 tRLOH;
+ u8 tRHOH;
+};
+
+struct mx6_fcb {
+ u32 checksum;
+ u32 fingerprint;
+ u32 version;
+ struct mx6_nand_timing timing;
+ u32 page_data_size;
+ u32 total_page_size;
+ u32 sectors_per_block;
+ u32 number_of_nands; /* not used by ROM code */
+ u32 total_internal_die; /* not used by ROM code */
+ u32 cell_type; /* not used by ROM code */
+ u32 ecc_blockn_type;
+ u32 ecc_block0_size;
+ u32 ecc_blockn_size;
+ u32 ecc_block0_type;
+ u32 metadata_size;
+ u32 ecc_blocks_per_page;
+ u32 rsrvd1[6]; /* not used by ROM code */
+ u32 bch_mode; /* erase_threshold */
+ u32 rsrvd2[2];
+ u32 fw1_start_page;
+ u32 fw2_start_page;
+ u32 fw1_sectors;
+ u32 fw2_sectors;
+ u32 dbbt_search_area;
+ u32 bb_mark_byte;
+ u32 bb_mark_startbit;
+ u32 bb_mark_phys_offset;
+ u32 bch_type;
+ u32 rsrvd3[8]; /* Toggle NAND timing parameters */
+ u32 disbbm;
+ u32 bb_mark_spare_offset;
+ u32 rsrvd4[9]; /* ONFI NAND parameters */
+ u32 disbb_search;
+};
+
+struct mx6_dbbt_header {
+ u32 checksum;
+ u32 fingerprint;
+ u32 version;
+ u32 number_bb;
+ u32 number_pages;
+ u8 spare[492];
+};
+
+struct mx6_dbbt {
+ u32 nand_number;
+ u32 number_bb;
+ u32 bb_num[2040 / 4];
+};
+
+#define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET)
+
+static nand_info_t *mtd = &nand_info[0];
+
+extern void *_start;
+
+#define BIT(v,n) (((v) >> (n)) & 0x1)
+
+static inline void memdump(const void *addr, size_t len)
+{
+ const char *buf = addr;
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (i % 16 == 0) {
+ if (i > 0)
+ printf("\n");
+ printf("%p:", &buf[i]);
+ }
+ printf(" %02x", buf[i]);
+ }
+ printf("\n");
+}
+
+static u8 calculate_parity_13_8(u8 d)
+{
+ u8 p = 0;
+
+ p |= (BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 3) ^ BIT(d, 2)) << 0;
+ p |= (BIT(d, 7) ^ BIT(d, 5) ^ BIT(d, 4) ^ BIT(d, 2) ^ BIT(d, 1)) << 1;
+ p |= (BIT(d, 7) ^ BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 1) ^ BIT(d, 0)) << 2;
+ p |= (BIT(d, 7) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 0)) << 3;
+ p |= (BIT(d, 6) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 2) ^ BIT(d, 1) ^ BIT(d, 0)) << 4;
+ return p;
+}
+
+static void encode_hamming_13_8(void *_src, void *_ecc, size_t size)
+{
+ int i;
+ u8 *src = _src;
+ u8 *ecc = _ecc;
+
+ for (i = 0; i < size; i++)
+ ecc[i] = calculate_parity_13_8(src[i]);
+}
+
+static u32 calc_chksum(void *buf, size_t size)
+{
+ u32 chksum = 0;
+ u8 *bp = buf;
+ size_t i;
+
+ for (i = 0; i < size; i++) {
+ chksum += bp[i];
+ }
+ return ~chksum;
+}
+
+/*
+ Physical organisation of data in NAND flash:
+ metadata
+ payload chunk 0 (may be empty)
+ ecc for metadata + payload chunk 0
+ payload chunk 1
+ ecc for payload chunk 1
+...
+ payload chunk n
+ ecc for payload chunk n
+ */
+
+static int calc_bb_offset(nand_info_t *mtd, struct mx6_fcb *fcb)
+{
+ int bb_mark_offset;
+ int chunk_data_size = fcb->ecc_blockn_size * 8;
+ int chunk_ecc_size = (fcb->ecc_blockn_type << 1) * 13;
+ int chunk_total_size = chunk_data_size + chunk_ecc_size;
+ int bb_mark_chunk, bb_mark_chunk_offs;
+
+ bb_mark_offset = (mtd->writesize - fcb->metadata_size) * 8;
+ if (fcb->ecc_block0_size == 0)
+ bb_mark_offset -= (fcb->ecc_block0_type << 1) * 13;
+
+ bb_mark_chunk = bb_mark_offset / chunk_total_size;
+ bb_mark_chunk_offs = bb_mark_offset - (bb_mark_chunk * chunk_total_size);
+ if (bb_mark_chunk_offs > chunk_data_size) {
+ printf("Unsupported ECC layout; BB mark resides in ECC data: %u\n",
+ bb_mark_chunk_offs);
+ return -EINVAL;
+ }
+ bb_mark_offset -= bb_mark_chunk * chunk_ecc_size;
+ return bb_mark_offset;
+}
+
+#define pr_fcb_val(p, n) debug("%s=%08x(%d)\n", #n, (p)->n, (p)->n)
+
+static struct mx6_fcb *create_fcb(void *buf, int fw1_start_block,
+ int fw2_start_block, size_t fw_size)
+{
+ struct gpmi_regs *gpmi_base = (struct gpmi_regs *)GPMI_BASE_ADDRESS;
+ struct bch_regs *bch_base = (struct bch_regs *)BCH_BASE_ADDRESS;
+ u32 fl0, fl1;
+ u32 t0;
+ int metadata_size;
+ int bb_mark_bit_offs;
+ struct mx6_fcb *fcb;
+ int fcb_offs;
+
+ if (gpmi_base == NULL || bch_base == NULL) {
+ return ERR_PTR(-ENOMEM);
+ }
+
+ fl0 = readl(&bch_base->hw_bch_flash0layout0);
+ fl1 = readl(&bch_base->hw_bch_flash0layout1);
+ t0 = readl(&gpmi_base->hw_gpmi_timing0);
+// t1 = readl(&gpmi_base->hw_gpmi_timing1);
+
+ metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
+
+ fcb = buf + ALIGN(metadata_size, 4);
+ fcb_offs = (void *)fcb - buf;
+#if 0
+ memset(buf, 0xff, fcb_offs);
+ memset(fcb, 0x00, sizeof(*fcb));
+ memset(fcb + 1, 0xff, mtd->erasesize - fcb_offs - sizeof(*fcb));
+#else
+ memset(buf, 0, fcb_offs);
+ memset(fcb, 0x00, sizeof(*fcb));
+ memset(fcb + 1, 0, mtd->erasesize - fcb_offs - sizeof(*fcb));
+#endif
+ strncpy((char *)&fcb->fingerprint, "FCB ", 4);
+ fcb->version = cpu_to_be32(1);
+#if 1
+ fcb->disbb_search = 1;
+ fcb->disbbm = 1;
+#endif
+ fcb->timing.data_setup = BF_VAL(t0, GPMI_TIMING0_DATA_SETUP);
+ fcb->timing.data_hold = BF_VAL(t0, GPMI_TIMING0_DATA_HOLD);
+ fcb->timing.address_setup = BF_VAL(t0, GPMI_TIMING0_ADDRESS_SETUP);
+#if 0
+ fcb->timing.data_setup = 80;
+ fcb->timing.data_hold = 60;
+ fcb->timing.address_setup = 25;
+ fcb->timing.dsample_time = 6;
+#endif
+ fcb->page_data_size = mtd->writesize;
+ fcb->total_page_size = mtd->writesize + mtd->oobsize;
+ fcb->sectors_per_block = mtd->erasesize / mtd->writesize;
+
+ fcb->ecc_block0_type = BF_VAL(fl0, BCH_FLASHLAYOUT0_ECC0);
+ fcb->ecc_block0_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_DATA0_SIZE) * 4;
+ fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASHLAYOUT1_ECCN);
+ fcb->ecc_blockn_size = BF_VAL(fl1, BCH_FLASHLAYOUT1_DATAN_SIZE) * 4;
+
+ pr_fcb_val(fcb, ecc_block0_type);
+ pr_fcb_val(fcb, ecc_blockn_type);
+ pr_fcb_val(fcb, ecc_block0_size);
+ pr_fcb_val(fcb, ecc_blockn_size);
+
+ fcb->metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
+ fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASHLAYOUT0_NBLOCKS);
+ fcb->bch_mode = readl(&bch_base->hw_bch_mode);
+ fcb->bch_type = 0; /* BCH20 */
+
+ fcb->fw1_start_page = fw1_start_block * mtd->erasesize / mtd->writesize;
+ fcb->fw1_sectors = DIV_ROUND_UP(fw_size, mtd->writesize);
+
+ if (fw2_start_block != 0 && fw2_start_block < mtd->size / mtd->erasesize) {
+ fcb->fw2_start_page = fw2_start_block * mtd->erasesize / mtd->writesize;
+ fcb->fw2_sectors = fcb->fw1_sectors;
+ }
+
+ fcb->dbbt_search_area = 1;
+
+ bb_mark_bit_offs = calc_bb_offset(mtd, fcb);
+ if (bb_mark_bit_offs < 0)
+ return ERR_PTR(bb_mark_bit_offs);
+ fcb->bb_mark_byte = bb_mark_bit_offs / 8;
+ fcb->bb_mark_startbit = bb_mark_bit_offs % 8;
+ fcb->bb_mark_phys_offset = mtd->writesize;
+
+ pr_fcb_val(fcb, bb_mark_byte);
+ pr_fcb_val(fcb, bb_mark_startbit);
+ pr_fcb_val(fcb, bb_mark_phys_offset);
+
+ fcb->checksum = calc_chksum(&fcb->fingerprint, 512 - 4);
+ return fcb;
+}
+
+static inline int find_fcb(void *ref, int page)
+{
+ int ret = 0;
+ struct nand_chip *chip = mtd->priv;
+ void *buf = malloc(mtd->erasesize);
+
+ if (buf == NULL) {
+ return -ENOMEM;
+ }
+ chip->select_chip(mtd, 0);
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+ ret = chip->ecc.read_page_raw(mtd, chip, buf, page);
+ if (ret) {
+ printf("Failed to read FCB from page %u: %d\n", page, ret);
+ return ret;
+ }
+ chip->select_chip(mtd, -1);
+ if (memcmp(buf, ref, mtd->writesize) == 0) {
+ debug("Found FCB in page %u (%08x)\n",
+ page, page * mtd->writesize);
+ ret = 1;
+ }
+ free(buf);
+ return ret;
+}
+
+static int write_fcb(void *buf, int block)
+{
+ int ret;
+ struct nand_chip *chip = mtd->priv;
+ int page = block * mtd->erasesize / mtd->writesize;
+
+ ret = find_fcb(buf, page);
+ if (ret > 0) {
+ printf("FCB at block %d is up to date\n", block);
+ return 0;
+ }
+
+ ret = nand_erase(mtd, block * mtd->erasesize, mtd->erasesize);
+ if (ret) {
+ printf("Failed to erase FCB block %u\n", block);
+ return ret;
+ }
+
+ printf("Writing FCB to block %d @ %08x\n", block,
+ block * mtd->erasesize);
+ chip->select_chip(mtd, 0);
+ ret = chip->write_page(mtd, chip, buf, page, 0, 1);
+ if (ret) {
+ printf("Failed to write FCB to block %u: %d\n", block, ret);
+ }
+ chip->select_chip(mtd, -1);
+
+ return ret;
+}
+
+struct mx6_ivt {
+ u32 magic;
+ u32 entry;
+ u32 rsrvd1;
+ void *dcd;
+ void *boot_data;
+ void *self;
+ void *csf;
+ u32 rsrvd2;
+};
+
+struct mx6_boot_data {
+ u32 start;
+ u32 length;
+ u32 plugin;
+};
+
+static int find_ivt(void *buf)
+{
+ struct mx6_ivt *ivt_hdr = buf + 0x400;
+
+ if ((ivt_hdr->magic & 0xff0000ff) != 0x400000d1)
+ return 0;
+
+ return 1;
+}
+
+static inline void *reloc(void *dst, void *base, void *ptr)
+{
+ return dst + (ptr - base);
+}
+
+static int patch_ivt(void *buf, size_t fsize)
+{
+ struct mx6_ivt *ivt_hdr = buf + 0x400;
+ struct mx6_boot_data *boot_data;
+
+ if (!find_ivt(buf)) {
+ printf("No IVT found in image at %p\n", buf);
+ return -EINVAL;
+ }
+ boot_data = reloc(ivt_hdr, ivt_hdr->self, ivt_hdr->boot_data);
+ boot_data->length = fsize;
+
+ return 0;
+}
+
+#define chk_overlap(a,b) \
+ ((a##_start_block <= b##_end_block && \
+ a##_end_block >= b##_start_block) || \
+ (b##_start_block <= a##_end_block && \
+ b##_end_block >= a##_start_block))
+
+#define fail_if_overlap(a,b,m1,m2) do { \
+ if (chk_overlap(a, b)) { \
+ printf("%s blocks %lu..%lu overlap %s in blocks %lu..%lu!\n", \
+ m1, a##_start_block, a##_end_block, \
+ m2, b##_start_block, b##_end_block); \
+ /*return -EINVAL;*/ \
+ } \
+} while (0)
+
+#ifndef CONFIG_ENV_OFFSET_REDUND
+#define TOTAL_ENV_SIZE CONFIG_ENV_RANGE
+#else
+#define TOTAL_ENV_SIZE (CONFIG_ENV_RANGE * 2)
+#endif
+
+#define pr_fcb_offset(n) printf("%s: %04x (%d)\n", #n, \
+ offsetof(struct mx6_fcb, n), offsetof(struct mx6_fcb, n))
+
+int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int ret;
+ int block;
+ int erase_size = mtd->erasesize;
+ int page_size = mtd->writesize;
+ void *buf;
+ char *load_addr;
+ char *file_size;
+ size_t size = 0;
+ void *addr = NULL;
+ struct mx6_fcb *fcb;
+ unsigned long fcb_start_block = FCB_START_BLOCK;
+ unsigned long num_fcb_blocks = NUM_FCB_BLOCKS;
+ unsigned long fcb_end_block;
+ unsigned long mtd_num_blocks = mtd->size / mtd->erasesize;
+ unsigned long env_start_block = CONFIG_ENV_OFFSET / mtd->erasesize;
+ unsigned long env_end_block = env_start_block +
+ DIV_ROUND_UP(TOTAL_ENV_SIZE, mtd->erasesize) - 1;
+ int optind;
+ int fw1_set = 0;
+ int fw2_set = 0;
+ unsigned long fw1_start_block = 0, fw1_end_block;
+ unsigned long fw2_start_block = 0, fw2_end_block;
+ unsigned long fw_num_blocks;
+ unsigned long extra_blocks = 2;
+ nand_erase_options_t erase_opts = { 0, };
+ int fcb_written = 0;
+
+ load_addr = getenv("fileaddr");
+ file_size = getenv("filesize");
+
+ if (argc < 2 && load_addr == NULL) {
+ printf("Load address not specified\n");
+ return -EINVAL;
+ }
+ if (argc < 3 && file_size == NULL) {
+ printf("Image size not specified\n");
+ return -EINVAL;
+ }
+
+ for (optind = 1; optind < argc; optind++) {
+ if (strcmp(argv[optind], "-b") == 0) {
+ if (optind >= argc - 1) {
+ printf("Option %s requires an argument\n",
+ argv[optind]);
+ return -EINVAL;
+ }
+ optind++;
+ fcb_start_block = simple_strtoul(argv[optind], NULL, 0);
+ if (fcb_start_block >= mtd_num_blocks) {
+ printf("Block number %lu is out of range: 0..%lu\n",
+ fcb_start_block, mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ } else if (strcmp(argv[optind], "-n") == 0) {
+ if (optind >= argc - 1) {
+ printf("Option %s requires an argument\n",
+ argv[optind]);
+ return -EINVAL;
+ }
+ optind++;
+ num_fcb_blocks = simple_strtoul(argv[optind], NULL, 0);
+ if (num_fcb_blocks == 0) {
+ printf("Number of FCB blocks must be non-zero\n");
+ return -EINVAL;
+ } else if (num_fcb_blocks > MAX_FCB_BLOCKS) {
+ printf("Extraneous number of FCB blocks; max. allowed: %u\n",
+ MAX_FCB_BLOCKS);
+ return -EINVAL;
+ }
+ } else if (strcmp(argv[optind], "-f") == 0) {
+ if (optind >= argc - 1) {
+ printf("Option %s requires an argument\n",
+ argv[optind]);
+ return -EINVAL;
+ }
+ optind++;
+ fw1_start_block = simple_strtoul(argv[optind], NULL, 0);
+ if (fw1_start_block >= mtd_num_blocks) {
+ printf("Block number %lu is out of range: 0..%lu\n",
+ fw1_start_block, mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ fw1_set = 1;
+ } else if (strcmp(argv[optind], "-r") == 0) {
+ if (optind < argc - 1 && argv[optind + 1][0] != '-') {
+ optind++;
+ fw2_start_block = simple_strtoul(argv[optind],
+ NULL, 0);
+ if (fw2_start_block >= mtd_num_blocks) {
+ printf("Block number %lu is out of range: 0..%lu\n",
+ fw2_start_block,
+ mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ }
+ fw2_set = 1;
+ } else if (strcmp(argv[optind], "-e") == 0) {
+ if (optind >= argc - 1) {
+ printf("Option %s requires an argument\n",
+ argv[optind]);
+ return -EINVAL;
+ }
+ optind++;
+ extra_blocks = simple_strtoul(argv[optind], NULL, 0);
+ if (extra_blocks >= mtd_num_blocks) {
+ printf("Extra block count %lu is out of range: 0..%lu\n",
+ extra_blocks,
+ mtd_num_blocks - 1);
+ return -EINVAL;
+ }
+ } else if (argv[optind][0] == '-') {
+ printf("Unrecognized option %s\n", argv[optind]);
+ return -EINVAL;
+ } else {
+ break;
+ }
+ }
+
+ if (argc > optind) {
+ load_addr = NULL;
+ addr = (void *)simple_strtoul(argv[optind], NULL, 16);
+ optind++;
+ }
+ if (argc > optind) {
+ file_size = NULL;
+ size = simple_strtoul(argv[optind], NULL, 16);
+ optind++;
+ }
+ if (load_addr != NULL) {
+ addr = (void *)simple_strtoul(load_addr, NULL, 16);
+ printf("Using default load address %p\n", addr);
+ }
+ if (file_size != NULL) {
+ size = simple_strtoul(file_size, NULL, 16);
+ printf("Using default file size %08x\n", size);
+ }
+ fcb_end_block = fcb_start_block + num_fcb_blocks - 1;
+ fw_num_blocks = DIV_ROUND_UP(size, mtd->erasesize);
+
+ if (!fw1_set) {
+ fw1_start_block = fcb_end_block + CONFIG_SYS_NAND_U_BOOT_OFFS / mtd->erasesize;
+ fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1;
+ if (chk_overlap(fw1, env)) {
+ fw1_start_block = env_end_block + 1;
+ fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1;
+ }
+ } else {
+ fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1;
+ }
+
+ if (fw2_set && fw2_start_block == 0) {
+ fw2_start_block = fw1_end_block + 1;
+ fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1;
+ if (chk_overlap(fw2, env)) {
+ fw2_start_block = env_end_block + 1;
+ fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1;
+ }
+ } else {
+ fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1;
+ }
+
+ fail_if_overlap(fcb, env, "FCB", "Environment");
+ fail_if_overlap(fcb, fw1, "FCB", "FW1");
+ fail_if_overlap(fw1, env, "FW1", "Environment");
+ if (fw2_set) {
+ fail_if_overlap(fcb, fw2, "FCB", "FW2");
+ fail_if_overlap(fw2, env, "FW2", "Environment");
+ fail_if_overlap(fw1, fw2, "FW1", "FW2");
+ }
+
+ buf = malloc(erase_size);
+ if (buf == NULL) {
+ printf("Failed to allocate buffer\n");
+ return -ENOMEM;
+ }
+
+ /* search for first non-bad block in FW1 block range */
+ while (fw1_start_block <= fw1_end_block) {
+ if (!nand_block_isbad(mtd, fw1_start_block * mtd->erasesize))
+ break;
+ fw1_start_block++;
+ }
+ if (fw1_end_block - fw1_start_block + 1 < fw_num_blocks) {
+ printf("Too many bad blocks in FW1 block range: %lu..%lu\n",
+ fw1_end_block + 1 - fw_num_blocks - extra_blocks,
+ fw1_end_block);
+ return -EINVAL;
+ }
+
+ /* search for first non-bad block in FW2 block range */
+ while (fw2_set && fw2_start_block <= fw2_end_block) {
+ if (!nand_block_isbad(mtd, fw2_start_block * mtd->erasesize))
+ break;
+ fw2_start_block++;
+ }
+ if (fw2_end_block - fw2_start_block + 1 < fw_num_blocks) {
+ printf("Too many bad blocks in FW2 area %08lx..%08lx\n",
+ fw2_end_block + 1 - fw_num_blocks - extra_blocks,
+ fw2_end_block);
+ return -EINVAL;
+ }
+
+ fcb = create_fcb(buf, fw1_start_block, fw2_start_block,
+ ALIGN(size, mtd->writesize));
+ if (IS_ERR(fcb)) {
+ printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb));
+ return PTR_ERR(fcb);
+ }
+ encode_hamming_13_8(fcb, (void *)fcb + 512, 512);
+
+ for (block = fcb_start_block; block <= fcb_end_block; block++) {
+ if (nand_block_isbad(mtd, block * mtd->erasesize)) {
+ if (block == fcb_start_block)
+ fcb_start_block++;
+ continue;
+ }
+ ret = write_fcb(buf, block);
+ if (ret) {
+ printf("Failed to write FCB to block %u\n", block);
+ return ret;
+ }
+ fcb_written = 1;
+ }
+
+ if (!fcb_written) {
+ printf("Could not write FCB to flash\n");
+ return -EIO;
+ }
+
+ ret = patch_ivt(addr, size);
+ if (ret) {
+ return ret;
+ }
+
+ printf("Programming U-Boot image from %p to block %lu\n",
+ addr, fw1_start_block);
+ if (size & (page_size - 1)) {
+ memset(addr + size, 0xff, size & (page_size - 1));
+ size = ALIGN(size, page_size);
+ }
+
+ erase_opts.offset = fcb->fw1_start_page * page_size;
+ erase_opts.length = ALIGN(size, erase_size) +
+ extra_blocks * mtd->erasesize;
+ erase_opts.quiet = 1;
+
+ printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset,
+ erase_opts.offset + erase_opts.length - 1);
+
+ ret = nand_erase_opts(mtd, &erase_opts);
+ if (ret) {
+ printf("Failed to erase flash: %d\n", ret);
+ return ret;
+ }
+ printf("Programming flash @ %08x..%08x from %p\n",
+ fcb->fw1_start_page * page_size,
+ fcb->fw1_start_page * page_size + size, addr);
+ ret = nand_write_skip_bad(mtd, fcb->fw1_start_page * page_size,
+ &size, addr, WITH_DROP_FFS);
+ if (ret) {
+ printf("Failed to program flash: %d\n", ret);
+ return ret;
+ }
+ if (fw2_start_block == 0) {
+ return ret;
+ }
+
+ printf("Programming redundant U-Boot image to block %lu\n",
+ fw2_start_block);
+ erase_opts.offset = fcb->fw2_start_page * page_size;
+ printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset,
+ erase_opts.offset + erase_opts.length - 1);
+
+ ret = nand_erase_opts(mtd, &erase_opts);
+ if (ret) {
+ printf("Failed to erase flash: %d\n", ret);
+ return ret;
+ }
+ printf("Programming flash @ %08x..%08x from %p\n",
+ fcb->fw2_start_page * page_size,
+ fcb->fw2_start_page * page_size + size, addr);
+ ret = nand_write_skip_bad(mtd, fcb->fw2_start_page * page_size,
+ &size, addr, WITH_DROP_FFS);
+ if (ret) {
+ printf("Failed to program flash: %d\n", ret);
+ return ret;
+ }
+ return ret;
+}
+
+U_BOOT_CMD(romupdate, 11, 0, do_update,
+ "Creates an FCB data structure and writes an U-Boot image to flash\n",
+ "[-b #] [-n #] [-f #] [-r [#]] [<address>] [<length>]\n"
+ "\t-b #\tfirst FCB block number (default 0)\n"
+ "\t-n #\ttotal number of FCB blocks (default 1)\n"
+ "\t-f #\twrite bootloader image at block #\n"
+ "\t-r\twrite redundant bootloader image at next free block after first image\n"
+ "\t-r #\twrite redundant bootloader image at block #\n"
+ "\t-e #\tspecify number of redundant blocks per boot loader image\n"
+ "\t<address>\tRAM address of bootloader image (default: ${fileaddr}\n"
+ "\t<length>\tlength of bootloader image in RAM (default: ${filesize}"
+ );
--- /dev/null
+#include <config.h>
+#include <configs/tx6q.h>
+#include <asm/arch/imx-regs.h>
+
+#define DEBUG_LED_BIT 20
+#define LED_GPIO_BASE GPIO2_BASE_ADDR
+#define LED_MUX_OFFSET 0x0ec
+#define LED_MUX_MODE 0x15
+
+#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
+
+#ifdef PHYS_SDRAM_2_SIZE
+#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#else
+#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
+#endif
+
+#define CPU_2_BE_32(l) \
+ ((((l) << 24) & 0xFF000000) | \
+ (((l) << 8) & 0x00FF0000) | \
+ (((l) >> 8) & 0x0000FF00) | \
+ (((l) >> 24) & 0x000000FF))
+
+#define MXC_DCD_ITEM(addr, val) .word CPU_2_BE_32(addr), CPU_2_BE_32(val)
+
+#define CHECK_DCD_ADDR(a) ((((a) >= 0x00907000) && ((a) <= 0x00937FF0)) || \
+ (((a) >= 0x020C4000) && ((a) < 0x020C8000)) || \
+ (((a) >= 0x020C8000) && ((a) < 0x020C9000)) || \
+ (((a) >= 0x020E0000) && ((a) < 0x020E4000)) || \
+ (((a) >= 0x021B0000) && ((a) < 0x021B8000)) || \
+ (((a) >= 0x08000000) && ((a) < 0x0FFF0000)) || \
+ (((a) >= 0x10000000)))
+
+#define MXC_DCD_CMD_SZ_BYTE 1
+#define MXC_DCD_CMD_SZ_SHORT 2
+#define MXC_DCD_CMD_SZ_WORD 4
+#define MXC_DCD_CMD_FLAG_WRITE 0x0
+#define MXC_DCD_CMD_FLAG_CLR 0x1
+#define MXC_DCD_CMD_FLAG_SET 0x3
+#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
+#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
+#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
+
+#define MXC_DCD_CMD_WRT(type, flags, next) \
+ .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
+
+#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
+ .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
+ CPU_2_BE_32(addr), CPU_2_BE_32(mask)
+
+#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
+ .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
+ CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
+
+#define MXC_DCD_CMD_NOP \
+ .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+
+#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
+#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+
+ .macro CK_VAL, name, clks, offs, max
+ .iflt \clks - \offs
+ .set \name, 0
+ .else
+ .ifle \clks - \offs - \max
+ .set \name, \clks - \offs
+ .endif
+ .endif
+ .endm
+
+ .macro NS_VAL, name, ns, offs, max
+ .iflt \ns - \offs
+ .set \name, 0
+ .else
+ CK_VAL \name, NS_TO_CK(\ns), \offs, \max
+ .endif
+ .endm
+
+ .macro CK_MAX, name, ck1, ck2, offs, max
+ .ifgt \ck1 - \ck2
+ CK_VAL \name, \ck1, \offs, \max
+ .else
+ CK_VAL \name, \ck2, \offs, \max
+ .endif
+ .endm
+
+#define MDMISC_DDR_TYPE_DDR3 0
+#define MDMISC_DDR_TYPE_LPDDR2 1
+#define MDMISC_DDR_TYPE_DDR2 2
+
+#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
+
+#define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */
+
+/* DDR3 SDRAM */
+#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
+#define BANK_ADDR_BITS 2
+#else
+#define BANK_ADDR_BITS 1
+#endif
+#define SDRAM_BURST_LENGTH 8
+#define RALAT 5
+#define WALAT 0
+#define BI_ON 1
+#define ADDR_MIRROR 1
+#define DDR_TYPE MDMISC_DDR_TYPE_DDR3
+
+/* 512/1024MiB SDRAM: NT5CB128M16P-CG */
+/* MDCFG0 0x0c */
+NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
+CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
+CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
+CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
+NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */
+
+/* MDCFG1 0x10 */
+NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
+NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
+NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */
+
+/* MDCFG2 0x14 */
+CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
+CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+
+/* MDOR 0x30 */
+CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
+#define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
+#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
+
+/* MDOTC 0x08 */
+NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */
+
+/* MDPDC 0x04 */
+CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7
+CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
+CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
+
+#define PRCT 0
+#define PWDT 5
+#define SLOW_PD 0
+#define BOTH_CS_PD 1
+
+#define MDPDC_VAL_0 ( \
+ (PRCT << 28) | \
+ (PRCT << 24) | \
+ (tCKE << 16) | \
+ (SLOW_PD << 7) | \
+ (BOTH_CS_PD << 6) | \
+ (tCKSRX << 3) | \
+ (tCKSRE << 0) \
+ )
+
+#define MDPDC_VAL_1 (MDPDC_VAL_0 | \
+ (PWDT << 12) | \
+ (PWDT << 8) \
+ )
+
+#define ROW_ADDR_BITS 14
+#define COL_ADDR_BITS 10
+
+ .iflt tWR - 7
+ .set mr0_val, ((1 << 8) /* DLL Reset */ | \
+ ((tWR + 1 - 4) << 9) | \
+ (((tCL + 3) - 4) << 4))
+ .else
+ .set mr0_val, ((1 << 8) /* DLL Reset */ | \
+ (((tWR + 1) / 2) << 9) | \
+ (((tCL + 3) - 4) << 4))
+ .endif
+#define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
+ (1 << 15) /* CON REQ */ | \
+ (3 << 4) /* MRS command */ | \
+ ((cs) << 3) | \
+ ((mr) << 0))
+
+#define mr1_val 0x0040
+#define mr2_val 0x0408
+
+#define MDCFG0_VAL ( \
+ (tRFC << 24) | \
+ (tXS << 16) | \
+ (tXP << 13) | \
+ (tXPDLL << 9) | \
+ (tFAW << 4) | \
+ (tCL << 0)) \
+
+#define MDCFG1_VAL ( \
+ (tRCD << 29) | \
+ (tRP << 26) | \
+ (tRC << 21) | \
+ (tRAS << 16) | \
+ (tRPA << 15) | \
+ (tWR << 9) | \
+ (tMRD << 5) | \
+ (tCWL << 0)) \
+
+#define MDCFG2_VAL ( \
+ (tDLLK << 16) | \
+ (tRTP << 6) | \
+ (tWTR << 3) | \
+ (tRRD << 0))
+
+#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
+#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
+ ((COL_ADDR_BITS - 9) << 20) | \
+ (BURST_LEN << 19) | \
+ (2 << 16) | /* SDRAM bus width */ \
+ ((-1) << (32 - BANK_ADDR_BITS)))
+
+#define MDMISC_VAL ((ADDR_MIRROR << 19) | \
+ (WALAT << 16) | \
+ (BI_ON << 12) | \
+ (0x3 << 9) | \
+ (RALAT << 6) | \
+ (DDR_TYPE << 3))
+
+#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
+
+#define MDOTC_VAL ((tAOFPD << 27) | \
+ (tAONPD << 24) | \
+ (tANPD << 20) | \
+ (tAXPD << 16) | \
+ (tODTLon << 12) | \
+ (tODTLoff << 4))
+
+fcb_start:
+ b _start
+ .org 0x400
+ivt_header:
+ .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
+app_start_addr:
+ .long _start
+ .long 0x0
+dcd_ptr:
+ .long dcd_hdr
+boot_data_ptr:
+ .word boot_data
+self_ptr:
+ .word ivt_header
+app_code_csf:
+ .word 0x0
+ .word 0x0
+boot_data:
+ .long fcb_start
+image_len:
+ .long CONFIG_U_BOOT_IMG_SIZE
+plugin:
+ .word 0
+ivt_end:
+#define DCD_VERSION 0x40
+
+#define CLKCTL_CCGR0 0x68
+#define CLKCTL_CCGR1 0x6c
+#define CLKCTL_CCGR2 0x70
+#define CLKCTL_CCGR3 0x74
+#define CLKCTL_CCGR4 0x78
+#define CLKCTL_CCGR5 0x7c
+#define CLKCTL_CCGR6 0x80
+#define CLKCTL_CCGR7 0x84
+#define CLKCTL_CMEOR 0x88
+
+#define DDR_SEL_VAL 3
+#define DSE_VAL 6
+#define ODT_VAL 2
+
+#define DDR_SEL_SHIFT 18
+#define DDR_MODE_SHIFT 17
+#define ODT_SHIFT 8
+#define DSE_SHIFT 3
+#define HYS_SHIFT 16
+#define PKE_SHIFT 12
+#define PUE_SHIFT 13
+#define PUS_SHIFT 14
+
+#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
+#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT)
+#define DSE_MASK (DSE_VAL << DSE_SHIFT)
+#define ODT_MASK (ODT_VAL << ODT_SHIFT)
+
+#define DQM_MASK (DDR_MODE_MASK | DSE_MASK)
+#define SDQS_MASK DSE_MASK
+#define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK)
+#define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define DDR_ADDR_MASK 0
+#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK)
+
+dcd_hdr:
+ .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
+dcd_start:
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset)
+ /* RESET_OUT GPIO_7_12 */
+ MXC_DCD_ITEM(0x020e024c, 0x00000005)
+
+ MXC_DCD_ITEM(0x020c402c, 0x01e436c1) /* CSC2CDR default: 0x007236c1 */
+ MXC_DCD_ITEM(0x020c80e0, 0x00002001) /* ENET PLL */
+
+ /* enable all relevant clocks... */
+ MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
+ MXC_DCD_ITEM(0x020c406c, 0xf0fc0c00) /* default: 0xf0fc0000 */
+ MXC_DCD_ITEM(0x020c4070, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
+ MXC_DCD_ITEM(0x020c4074, 0x3ff00000) /* default: 0x3ff00000 */
+ MXC_DCD_ITEM(0x020c4078, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
+ MXC_DCD_ITEM(0x020c407c, 0xff033f0f) /* default: 0xf0033f0f UART1 */
+ MXC_DCD_ITEM(0x020c4080, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
+
+ /* IOMUX: */
+ MXC_DCD_ITEM(0x020e0004, 0x48640005) /* default: 0x48400005 ENET_CLK output */
+ /* UART1 pad config */
+ MXC_DCD_ITEM(0x020e02a8, 0x00000001) /* UART1 TXD */
+ MXC_DCD_ITEM(0x020e02ac, 0x00000001) /* UART1 RXD */
+ MXC_DCD_ITEM(0x020e0920, 0x00000003) /* UART1 RXD INPUT_SEL */
+ MXC_DCD_ITEM(0x020e02c0, 0x00000001) /* UART1 CTS */
+ MXC_DCD_ITEM(0x020e02c4, 0x00000001) /* UART1 RTS */
+ MXC_DCD_ITEM(0x020e091c, 0x00000003) /* UART1 RTS INPUT_SEL */
+#if 0
+ /* NAND */
+ MXC_DCD_ITEM(0x020e02d4, 0x00000000) /* NANDF_CLE: NANDF_CLE */
+ MXC_DCD_ITEM(0x020e02d8, 0x00000000) /* NANDF_ALE: NANDF_ALE */
+ MXC_DCD_ITEM(0x020e02dc, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
+ MXC_DCD_ITEM(0x020e02e0, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
+ MXC_DCD_ITEM(0x020e02e4, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
+ MXC_DCD_ITEM(0x020e02f4, 0x00000001) /* SD4_CMD: NANDF_RDn */
+ MXC_DCD_ITEM(0x020e02f8, 0x00000001) /* SD4_CLK: NANDF_WRn */
+ MXC_DCD_ITEM(0x020e02fc, 0x00000000) /* NANDF_D0: NANDF_D0 */
+ MXC_DCD_ITEM(0x020e0300, 0x00000000) /* NANDF_D1: NANDF_D1 */
+ MXC_DCD_ITEM(0x020e0304, 0x00000000) /* NANDF_D2: NANDF_D2 */
+ MXC_DCD_ITEM(0x020e0308, 0x00000000) /* NANDF_D3: NANDF_D3 */
+ MXC_DCD_ITEM(0x020e030c, 0x00000000) /* NANDF_D4: NANDF_D4 */
+ MXC_DCD_ITEM(0x020e0310, 0x00000000) /* NANDF_D5: NANDF_D5 */
+ MXC_DCD_ITEM(0x020e0314, 0x00000000) /* NANDF_D6: NANDF_D6 */
+ MXC_DCD_ITEM(0x020e0318, 0x00000000) /* NANDF_D7: NANDF_D7 */
+#endif
+ /* ext. mem CS */
+ MXC_DCD_ITEM(0x020e02ec, 0x00000000) /* NANDF_CS2: NANDF_CS2 */
+ /* DRAM_DQM[0..7] */
+ MXC_DCD_ITEM(0x020e05ac, DQM_MASK)
+ MXC_DCD_ITEM(0x020e05b4, DQM_MASK)
+ MXC_DCD_ITEM(0x020e0528, DQM_MASK)
+ MXC_DCD_ITEM(0x020e0520, DQM_MASK)
+ MXC_DCD_ITEM(0x020e0514, DQM_MASK)
+ MXC_DCD_ITEM(0x020e0510, DQM_MASK)
+ MXC_DCD_ITEM(0x020e05bc, DQM_MASK)
+ MXC_DCD_ITEM(0x020e05c4, DQM_MASK)
+ /* DRAM_A[0..15] */
+ MXC_DCD_ITEM(0x020e052c, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0530, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0534, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0538, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e053c, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0540, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0544, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0548, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e054c, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0550, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0554, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0558, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e055c, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0560, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0564, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0568, DDR_ADDR_MASK)
+ /* DRAM_CAS */
+ MXC_DCD_ITEM(0x020e056c, DDR_CTRL_MASK)
+ /* DRAM_RAS */
+ MXC_DCD_ITEM(0x020e0578, DDR_CTRL_MASK)
+ /* DRAM_SDCLK[0..1] */
+ MXC_DCD_ITEM(0x020e0588, SDCLK_MASK)
+ MXC_DCD_ITEM(0x020e0594, SDCLK_MASK)
+ /* DRAM_RESET */
+ MXC_DCD_ITEM(0x020e057c, DDR_CTRL_MASK)
+ /* DRAM_SDCKE[0..1] */
+ MXC_DCD_ITEM(0x020e0590, SDCKE_MASK)
+ MXC_DCD_ITEM(0x020e0598, SDCKE_MASK)
+ /* DRAM_SDBA[0..2] */
+ MXC_DCD_ITEM(0x020e0580, 0x00000000)
+ MXC_DCD_ITEM(0x020e0584, 0x00000000)
+ MXC_DCD_ITEM(0x020e058c, 0x00000000)
+ /* DRAM_SDODT[0..1] */
+ MXC_DCD_ITEM(0x020e059c, SDODT_MASK)
+ MXC_DCD_ITEM(0x020e05a0, SDODT_MASK)
+ /* DRAM_B[0..7]DS */
+ MXC_DCD_ITEM(0x020e0784, DSE_MASK)
+ MXC_DCD_ITEM(0x020e0788, DSE_MASK)
+ MXC_DCD_ITEM(0x020e0794, DSE_MASK)
+ MXC_DCD_ITEM(0x020e079c, DSE_MASK)
+ MXC_DCD_ITEM(0x020e07a0, DSE_MASK)
+ MXC_DCD_ITEM(0x020e07a4, DSE_MASK)
+ MXC_DCD_ITEM(0x020e07a8, DSE_MASK)
+ MXC_DCD_ITEM(0x020e0748, DSE_MASK)
+ /* ADDDS */
+ MXC_DCD_ITEM(0x020e074c, DSE_MASK)
+ /* DDRMODE_CTL */
+ MXC_DCD_ITEM(0x020e0750, DDR_MODE_MASK)
+ /* DDRPKE */
+ MXC_DCD_ITEM(0x020e0758, 0x00000000)
+ /* DDRMODE */
+ MXC_DCD_ITEM(0x020e0774, DDR_MODE_MASK)
+ /* CTLDS */
+ MXC_DCD_ITEM(0x020e078c, DSE_MASK)
+ /* DDR_TYPE */
+ MXC_DCD_ITEM(0x020e0798, DDR_SEL_MASK)
+ /* DDRPK */
+ MXC_DCD_ITEM(0x020e0768, 1 << PUE_SHIFT)
+ /* DDRHYS */
+ MXC_DCD_ITEM(0x020e0770, 0x00000000)
+ /* TERM_CTL[0..7] */
+ MXC_DCD_ITEM(0x020e0754, ODT_MASK)
+ MXC_DCD_ITEM(0x020e075c, ODT_MASK)
+ MXC_DCD_ITEM(0x020e0760, ODT_MASK)
+ MXC_DCD_ITEM(0x020e0764, ODT_MASK)
+ MXC_DCD_ITEM(0x020e076c, ODT_MASK)
+ MXC_DCD_ITEM(0x020e0778, ODT_MASK)
+ MXC_DCD_ITEM(0x020e077c, ODT_MASK)
+ MXC_DCD_ITEM(0x020e0780, ODT_MASK)
+
+ /* SDRAM initialization */
+ /* MPRDDQBY[0..7]DL */
+ MXC_DCD_ITEM(0x021b081c, 0x33333333)
+ MXC_DCD_ITEM(0x021b481c, 0x33333333)
+ MXC_DCD_ITEM(0x021b0820, 0x33333333)
+ MXC_DCD_ITEM(0x021b4820, 0x33333333)
+ MXC_DCD_ITEM(0x021b0824, 0x33333333)
+ MXC_DCD_ITEM(0x021b4824, 0x33333333)
+ MXC_DCD_ITEM(0x021b0828, 0x33333333)
+ MXC_DCD_ITEM(0x021b4828, 0x33333333)
+ /* MDMISC */
+ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | 2) /* reset MMDC FSM */
+ddr_reset:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0018, 0x00000002)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack)
+
+ /* MSDSCR Conf Req */
+ MXC_DCD_ITEM(0x021b001c, 0x00008000)
+con_ack:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b001c, 0x00004000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib)
+ /* MDCTL */
+ MXC_DCD_ITEM(0x021b0000, MDCTL_VAL)
+ddr_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b0018, 0x40000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
+
+ MXC_DCD_ITEM(0x021b000c, MDCFG0_VAL)
+ MXC_DCD_ITEM(0x021b0010, MDCFG1_VAL)
+ MXC_DCD_ITEM(0x021b0014, MDCFG2_VAL)
+ MXC_DCD_ITEM(0x021b002c, 0x000026d2) /* MDRWD */
+ MXC_DCD_ITEM(0x021b0030, MDOR_VAL)
+ MXC_DCD_ITEM(0x021b0008, MDOTC_VAL)
+ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_0)
+ MXC_DCD_ITEM(0x021b0040, 0x00000027) /* MDASP */
+
+ /* CS0 MRS: */
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 0, mr0_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 2, mr2_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0))
+#if BANK_ADDR_BITS > 1
+ /* CS1 MRS: MR2 */
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 0, mr0_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 1, mr1_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 2, mr2_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
+#endif
+ MXC_DCD_ITEM(0x021b0020, 0x0000c000) /* disable refresh */
+
+ MXC_DCD_ITEM(0x021b0818, 0x00011112) /* MPODTCTRL */
+ MXC_DCD_ITEM(0x021b4818, 0x00011112)
+
+ /* DDR3 calibration */
+ MXC_DCD_ITEM(0x021b0890, 0x00000003) /* select default compare pattern for DQ calibration */
+ MXC_DCD_ITEM(0x021b0404, 0x00011007)
+
+ /* ZQ calibration */
+ MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */
+ MXC_DCD_ITEM(0x021b001c, 0x04008040) /* MRS: ZQ calibration */
+
+ MXC_DCD_ITEM(0x021b4800, 0xa138002b)
+ MXC_DCD_ITEM(0x021b0800, 0xa139002b)
+zq_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0800, 0x00010000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
+
+ /* Write leveling */
+ MXC_DCD_ITEM(0x021b4800, 0xa1380000)
+ MXC_DCD_ITEM(0x021b0800, 0xa1380000)
+
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
+ MXC_DCD_ITEM(0x021b001c, 0x00808231) /* MRS: start write leveling */
+
+ MXC_DCD_ITEM(0x021b0808, 0x00000001) /* initiate Write leveling */
+wl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000001)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000f00)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000001)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000f00)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset)
+
+ MXC_DCD_ITEM(0x021b0800, 0xa138002b)
+ MXC_DCD_ITEM(0x021b4800, 0xa138002b)
+
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
+
+ /* DQS gating calibration */
+ MXC_DCD_ITEM(0x020e05a8, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
+ MXC_DCD_ITEM(0x020e05b0, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e0524, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e051c, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e0518, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e050c, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e05b8, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e05c0, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | (7 << 6) | (3 << 16)) /* RALAT/WALAT max. */
+
+ MXC_DCD_ITEM(0x021b001c, 0x00008020) /* issue one refresh cycle */
+ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
+
+ MXC_DCD_ITEM(0x021b0848, 0x40404040) /* DQ RD Delay default values */
+ MXC_DCD_ITEM(0x021b4848, 0x40404040)
+ MXC_DCD_ITEM(0x021b0850, 0x40404040) /* DQ WR Delay default values */
+ MXC_DCD_ITEM(0x021b4850, 0x40404040)
+ MXC_DCD_ITEM(0x021b48b8, 0x00000800)
+ MXC_DCD_ITEM(0x021b08b8, 0x00000800)
+
+ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue fifo reset */
+dqs_fifo_reset:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2)
+ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue 2nd fifo reset */
+dqs_fifo_reset2:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
+ MXC_DCD_ITEM(0x021b083c, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
+dqs_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x10000000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x00001000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x10000000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x00001000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
+
+ /* DRAM_SDQS[0..7] pad config */
+ MXC_DCD_ITEM(0x020e05a8, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e05b0, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e0524, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e051c, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e0518, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e050c, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e05b8, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e05c0, SDQS_MASK)
+
+ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL)
+
+ /* Read delay calibration */
+ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
+ MXC_DCD_ITEM(0x021b0860, 0x00000030) /* MPRDDLHWCTL: HW_RD_DL_EN */
+rd_dl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x0000000f)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x0000000f)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
+
+ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
+ MXC_DCD_ITEM(0x021b0864, 0x00000030) /* start WR DL calibration */
+wr_dl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x0000000f)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x0000000f)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr)
+
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
+ MXC_DCD_ITEM(0x021b0020, 0x00005800) /* MDREF */
+ MXC_DCD_ITEM(0x021b0404, 0x00011006) /* MAPSR */
+ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_1)
+
+ /* MDSCR: Normal operation */
+ MXC_DCD_ITEM(0x021b001c, 0x00000000)
+con_ack_clr:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b001c, 0x00004000)
+dcd_end:
+ .ifgt dcd_end - dcd_start - 1768
+ DCD too large!
+ .endif
--- /dev/null
+#include <config.h>
+#include <configs/tx6q.h>
+#include <asm/arch/imx-regs.h>
+
+#define DEBUG_LED_BIT 20
+#define LED_GPIO_BASE GPIO2_BASE_ADDR
+#define LED_MUX_OFFSET 0x0ec
+#define LED_MUX_MODE 0x15
+
+#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
+
+#ifdef PHYS_SDRAM_2_SIZE
+#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#else
+#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
+#endif
+
+#define CPU_2_BE_32(l) \
+ ((((l) << 24) & 0xFF000000) | \
+ (((l) << 8) & 0x00FF0000) | \
+ (((l) >> 8) & 0x0000FF00) | \
+ (((l) >> 24) & 0x000000FF))
+
+#define MXC_DCD_ITEM(addr, val) .word CPU_2_BE_32(addr), CPU_2_BE_32(val)
+
+#define CHECK_DCD_ADDR(a) ((((a) >= 0x00907000) && ((a) <= 0x00937FF0)) || \
+ (((a) >= 0x020C4000) && ((a) < 0x020C8000)) || \
+ (((a) >= 0x020C8000) && ((a) < 0x020C9000)) || \
+ (((a) >= 0x020E0000) && ((a) < 0x020E4000)) || \
+ (((a) >= 0x021B0000) && ((a) < 0x021B8000)) || \
+ (((a) >= 0x08000000) && ((a) < 0x0FFF0000)) || \
+ (((a) >= 0x10000000)))
+
+#define MXC_DCD_CMD_SZ_BYTE 1
+#define MXC_DCD_CMD_SZ_SHORT 2
+#define MXC_DCD_CMD_SZ_WORD 4
+#define MXC_DCD_CMD_FLAG_WRITE 0x0
+#define MXC_DCD_CMD_FLAG_CLR 0x1
+#define MXC_DCD_CMD_FLAG_SET 0x3
+#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
+#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
+#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
+
+#define MXC_DCD_CMD_WRT(type, flags, next) \
+ .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
+
+#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
+ .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
+ CPU_2_BE_32(addr), CPU_2_BE_32(mask)
+
+#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
+ .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
+ CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
+
+#define MXC_DCD_CMD_NOP \
+ .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+
+#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
+#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+
+ .macro CK_VAL, name, clks, offs, max
+ .iflt \clks - \offs
+ .set \name, 0
+ .else
+ .ifle \clks - \offs - \max
+ .set \name, \clks - \offs
+ .endif
+ .endif
+ .endm
+
+ .macro NS_VAL, name, ns, offs, max
+ .iflt \ns - \offs
+ .set \name, 0
+ .else
+ CK_VAL \name, NS_TO_CK(\ns), \offs, \max
+ .endif
+ .endm
+
+ .macro CK_MAX, name, ck1, ck2, offs, max
+ .ifgt \ck1 - \ck2
+ CK_VAL \name, \ck1, \offs, \max
+ .else
+ CK_VAL \name, \ck2, \offs, \max
+ .endif
+ .endm
+
+#define MDMISC_DDR_TYPE_DDR3 0
+#define MDMISC_DDR_TYPE_LPDDR2 1
+#define MDMISC_DDR_TYPE_DDR2 2
+
+#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
+
+#define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */
+
+/* DDR3 SDRAM */
+#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
+#define BANK_ADDR_BITS 2
+#else
+#define BANK_ADDR_BITS 1
+#endif
+#define SDRAM_BURST_LENGTH 8
+#define RALAT 5
+#define WALAT 0
+#define BI_ON 1
+#define ADDR_MIRROR 1
+#define DDR_TYPE MDMISC_DDR_TYPE_DDR3
+
+/* 512/1024MiB SDRAM: NT5CB128M16P-CG */
+/* MDCFG0 0x0c */
+NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
+CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
+CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
+CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
+NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */
+
+/* MDCFG1 0x10 */
+NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
+NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
+NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */
+
+/* MDCFG2 0x14 */
+CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
+CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+
+/* MDOR 0x30 */
+CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
+#define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
+#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
+
+/* MDOTC 0x08 */
+NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */
+
+/* MDPDC 0x04 */
+CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7
+CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
+CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
+
+#define PRCT 0
+#define PWDT 5
+#define SLOW_PD 0
+#define BOTH_CS_PD 1
+
+#define MDPDC_VAL_0 ( \
+ (PRCT << 28) | \
+ (PRCT << 24) | \
+ (tCKE << 16) | \
+ (SLOW_PD << 7) | \
+ (BOTH_CS_PD << 6) | \
+ (tCKSRX << 3) | \
+ (tCKSRE << 0) \
+ )
+
+#define MDPDC_VAL_1 (MDPDC_VAL_0 | \
+ (PWDT << 12) | \
+ (PWDT << 8) \
+ )
+
+#define ROW_ADDR_BITS 14
+#define COL_ADDR_BITS 10
+
+ .iflt tWR - 7
+ .set mr0_val, ((1 << 8) /* DLL Reset */ | \
+ ((tWR + 1 - 4) << 9) | \
+ (((tCL + 3) - 4) << 4))
+ .else
+ .set mr0_val, ((1 << 8) /* DLL Reset */ | \
+ (((tWR + 1) / 2) << 9) | \
+ (((tCL + 3) - 4) << 4))
+ .endif
+#define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
+ (1 << 15) /* CON REQ */ | \
+ (3 << 4) /* MRS command */ | \
+ ((cs) << 3) | \
+ ((mr) << 0))
+
+#define mr1_val 0x0040
+#define mr2_val 0x0408
+
+#define MDCFG0_VAL ( \
+ (tRFC << 24) | \
+ (tXS << 16) | \
+ (tXP << 13) | \
+ (tXPDLL << 9) | \
+ (tFAW << 4) | \
+ (tCL << 0)) \
+
+#define MDCFG1_VAL ( \
+ (tRCD << 29) | \
+ (tRP << 26) | \
+ (tRC << 21) | \
+ (tRAS << 16) | \
+ (tRPA << 15) | \
+ (tWR << 9) | \
+ (tMRD << 5) | \
+ (tCWL << 0)) \
+
+#define MDCFG2_VAL ( \
+ (tDLLK << 16) | \
+ (tRTP << 6) | \
+ (tWTR << 3) | \
+ (tRRD << 0))
+
+#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
+#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
+ ((COL_ADDR_BITS - 9) << 20) | \
+ (BURST_LEN << 19) | \
+ (2 << 16) | /* SDRAM bus width */ \
+ ((-1) << (32 - BANK_ADDR_BITS)))
+
+#define MDMISC_VAL ((ADDR_MIRROR << 19) | \
+ (WALAT << 16) | \
+ (BI_ON << 12) | \
+ (0x3 << 9) | \
+ (RALAT << 6) | \
+ (DDR_TYPE << 3))
+
+#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
+
+#define MDOTC_VAL ((tAOFPD << 27) | \
+ (tAONPD << 24) | \
+ (tANPD << 20) | \
+ (tAXPD << 16) | \
+ (tODTLon << 12) | \
+ (tODTLoff << 4))
+
+fcb_start:
+ b _start
+ .org 0x400
+ivt_header:
+ .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
+app_start_addr:
+ .long _start
+ .long 0x0
+dcd_ptr:
+ .long dcd_hdr
+boot_data_ptr:
+ .word boot_data
+self_ptr:
+ .word ivt_header
+app_code_csf:
+ .word 0x0
+ .word 0x0
+boot_data:
+ .long fcb_start
+image_len:
+ .long CONFIG_U_BOOT_IMG_SIZE
+plugin:
+ .word 0
+ivt_end:
+#define DCD_VERSION 0x40
+
+#define CLKCTL_CCGR0 0x68
+#define CLKCTL_CCGR1 0x6c
+#define CLKCTL_CCGR2 0x70
+#define CLKCTL_CCGR3 0x74
+#define CLKCTL_CCGR4 0x78
+#define CLKCTL_CCGR5 0x7c
+#define CLKCTL_CCGR6 0x80
+#define CLKCTL_CCGR7 0x84
+#define CLKCTL_CMEOR 0x88
+
+#define DDR_SEL_VAL 3
+#define DSE_VAL 6
+#define ODT_VAL 2
+
+#define DDR_SEL_SHIFT 18
+#define DDR_MODE_SHIFT 17
+#define ODT_SHIFT 8
+#define DSE_SHIFT 3
+#define HYS_SHIFT 16
+#define PKE_SHIFT 12
+#define PUE_SHIFT 13
+#define PUS_SHIFT 14
+
+#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
+#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT)
+#define DSE_MASK (DSE_VAL << DSE_SHIFT)
+#define ODT_MASK (ODT_VAL << ODT_SHIFT)
+
+#define DQM_MASK (DDR_MODE_MASK | DSE_MASK)
+#define SDQS_MASK DSE_MASK
+#define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK)
+#define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define DDR_ADDR_MASK 0
+#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK)
+
+dcd_hdr:
+ .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
+dcd_start:
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset)
+ /* RESET_OUT GPIO_7_12 */
+ MXC_DCD_ITEM(0x020e024c, 0x00000005)
+
+ MXC_DCD_ITEM(0x020c402c, 0x01e436c1) /* CSC2CDR default: 0x007236c1 */
+ MXC_DCD_ITEM(0x020c80e0, 0x00002001) /* ENET PLL */
+
+ /* enable all relevant clocks... */
+ MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
+ MXC_DCD_ITEM(0x020c406c, 0xf0fc0c00) /* default: 0xf0fc0000 */
+ MXC_DCD_ITEM(0x020c4070, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
+ MXC_DCD_ITEM(0x020c4074, 0x3ff00000) /* default: 0x3ff00000 */
+ MXC_DCD_ITEM(0x020c4078, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
+ MXC_DCD_ITEM(0x020c407c, 0xff033f0f) /* default: 0xf0033f0f UART1 */
+ MXC_DCD_ITEM(0x020c4080, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
+
+ /* IOMUX: */
+ MXC_DCD_ITEM(0x020e0004, 0x48640005) /* default: 0x48400005 ENET_CLK output */
+ /* UART1 pad config */
+ MXC_DCD_ITEM(0x020e02a8, 0x00000001) /* UART1 TXD */
+ MXC_DCD_ITEM(0x020e02ac, 0x00000001) /* UART1 RXD */
+ MXC_DCD_ITEM(0x020e0920, 0x00000003) /* UART1 RXD INPUT_SEL */
+ MXC_DCD_ITEM(0x020e02c0, 0x00000001) /* UART1 CTS */
+ MXC_DCD_ITEM(0x020e02c4, 0x00000001) /* UART1 RTS */
+ MXC_DCD_ITEM(0x020e091c, 0x00000003) /* UART1 RTS INPUT_SEL */
+#if 0
+ /* NAND */
+ MXC_DCD_ITEM(0x020e02d4, 0x00000000) /* NANDF_CLE: NANDF_CLE */
+ MXC_DCD_ITEM(0x020e02d8, 0x00000000) /* NANDF_ALE: NANDF_ALE */
+ MXC_DCD_ITEM(0x020e02dc, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
+ MXC_DCD_ITEM(0x020e02e0, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
+ MXC_DCD_ITEM(0x020e02e4, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
+ MXC_DCD_ITEM(0x020e02f4, 0x00000001) /* SD4_CMD: NANDF_RDn */
+ MXC_DCD_ITEM(0x020e02f8, 0x00000001) /* SD4_CLK: NANDF_WRn */
+ MXC_DCD_ITEM(0x020e02fc, 0x00000000) /* NANDF_D0: NANDF_D0 */
+ MXC_DCD_ITEM(0x020e0300, 0x00000000) /* NANDF_D1: NANDF_D1 */
+ MXC_DCD_ITEM(0x020e0304, 0x00000000) /* NANDF_D2: NANDF_D2 */
+ MXC_DCD_ITEM(0x020e0308, 0x00000000) /* NANDF_D3: NANDF_D3 */
+ MXC_DCD_ITEM(0x020e030c, 0x00000000) /* NANDF_D4: NANDF_D4 */
+ MXC_DCD_ITEM(0x020e0310, 0x00000000) /* NANDF_D5: NANDF_D5 */
+ MXC_DCD_ITEM(0x020e0314, 0x00000000) /* NANDF_D6: NANDF_D6 */
+ MXC_DCD_ITEM(0x020e0318, 0x00000000) /* NANDF_D7: NANDF_D7 */
+#endif
+ /* ext. mem CS */
+ MXC_DCD_ITEM(0x020e02ec, 0x00000000) /* NANDF_CS2: NANDF_CS2 */
+ /* DRAM_DQM[0..7] */
+ MXC_DCD_ITEM(0x020e05ac, DQM_MASK)
+ MXC_DCD_ITEM(0x020e05b4, DQM_MASK)
+ MXC_DCD_ITEM(0x020e0528, DQM_MASK)
+ MXC_DCD_ITEM(0x020e0520, DQM_MASK)
+ MXC_DCD_ITEM(0x020e0514, DQM_MASK)
+ MXC_DCD_ITEM(0x020e0510, DQM_MASK)
+ MXC_DCD_ITEM(0x020e05bc, DQM_MASK)
+ MXC_DCD_ITEM(0x020e05c4, DQM_MASK)
+ /* DRAM_A[0..15] */
+ MXC_DCD_ITEM(0x020e052c, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0530, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0534, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0538, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e053c, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0540, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0544, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0548, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e054c, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0550, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0554, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0558, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e055c, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0560, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0564, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0568, DDR_ADDR_MASK)
+ /* DRAM_CAS */
+ MXC_DCD_ITEM(0x020e056c, DDR_CTRL_MASK)
+ /* DRAM_RAS */
+ MXC_DCD_ITEM(0x020e0578, DDR_CTRL_MASK)
+ /* DRAM_SDCLK[0..1] */
+ MXC_DCD_ITEM(0x020e0588, SDCLK_MASK)
+ MXC_DCD_ITEM(0x020e0594, SDCLK_MASK)
+ /* DRAM_RESET */
+ MXC_DCD_ITEM(0x020e057c, DDR_CTRL_MASK)
+ /* DRAM_SDCKE[0..1] */
+ MXC_DCD_ITEM(0x020e0590, SDCKE_MASK)
+ MXC_DCD_ITEM(0x020e0598, SDCKE_MASK)
+ /* DRAM_SDBA[0..2] */
+ MXC_DCD_ITEM(0x020e0580, 0x00000000)
+ MXC_DCD_ITEM(0x020e0584, 0x00000000)
+ MXC_DCD_ITEM(0x020e058c, 0x00000000)
+ /* DRAM_SDODT[0..1] */
+ MXC_DCD_ITEM(0x020e059c, SDODT_MASK)
+ MXC_DCD_ITEM(0x020e05a0, SDODT_MASK)
+ /* DRAM_B[0..7]DS */
+ MXC_DCD_ITEM(0x020e0784, DSE_MASK)
+ MXC_DCD_ITEM(0x020e0788, DSE_MASK)
+ MXC_DCD_ITEM(0x020e0794, DSE_MASK)
+ MXC_DCD_ITEM(0x020e079c, DSE_MASK)
+ MXC_DCD_ITEM(0x020e07a0, DSE_MASK)
+ MXC_DCD_ITEM(0x020e07a4, DSE_MASK)
+ MXC_DCD_ITEM(0x020e07a8, DSE_MASK)
+ MXC_DCD_ITEM(0x020e0748, DSE_MASK)
+ /* ADDDS */
+ MXC_DCD_ITEM(0x020e074c, DSE_MASK)
+ /* DDRMODE_CTL */
+ MXC_DCD_ITEM(0x020e0750, DDR_MODE_MASK)
+ /* DDRPKE */
+ MXC_DCD_ITEM(0x020e0758, 0x00000000)
+ /* DDRMODE */
+ MXC_DCD_ITEM(0x020e0774, DDR_MODE_MASK)
+ /* CTLDS */
+ MXC_DCD_ITEM(0x020e078c, DSE_MASK)
+ /* DDR_TYPE */
+ MXC_DCD_ITEM(0x020e0798, DDR_SEL_MASK)
+ /* DDRPK */
+ MXC_DCD_ITEM(0x020e0768, 1 << PUE_SHIFT)
+ /* DDRHYS */
+ MXC_DCD_ITEM(0x020e0770, 0x00000000)
+ /* TERM_CTL[0..7] */
+ MXC_DCD_ITEM(0x020e0754, ODT_MASK)
+ MXC_DCD_ITEM(0x020e075c, ODT_MASK)
+ MXC_DCD_ITEM(0x020e0760, ODT_MASK)
+ MXC_DCD_ITEM(0x020e0764, ODT_MASK)
+ MXC_DCD_ITEM(0x020e076c, ODT_MASK)
+ MXC_DCD_ITEM(0x020e0778, ODT_MASK)
+ MXC_DCD_ITEM(0x020e077c, ODT_MASK)
+ MXC_DCD_ITEM(0x020e0780, ODT_MASK)
+
+ /* SDRAM initialization */
+ /* MPRDDQBY[0..7]DL */
+ MXC_DCD_ITEM(0x021b081c, 0x33333333)
+ MXC_DCD_ITEM(0x021b481c, 0x33333333)
+ MXC_DCD_ITEM(0x021b0820, 0x33333333)
+ MXC_DCD_ITEM(0x021b4820, 0x33333333)
+ MXC_DCD_ITEM(0x021b0824, 0x33333333)
+ MXC_DCD_ITEM(0x021b4824, 0x33333333)
+ MXC_DCD_ITEM(0x021b0828, 0x33333333)
+ MXC_DCD_ITEM(0x021b4828, 0x33333333)
+ /* MDMISC */
+ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | 2) /* reset MMDC FSM */
+ddr_reset:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0018, 0x00000002)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack)
+
+ /* MSDSCR Conf Req */
+ MXC_DCD_ITEM(0x021b001c, 0x00008000)
+con_ack:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b001c, 0x00004000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib)
+ /* MDCTL */
+ MXC_DCD_ITEM(0x021b0000, MDCTL_VAL)
+ddr_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b0018, 0x40000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
+
+ MXC_DCD_ITEM(0x021b000c, MDCFG0_VAL)
+ MXC_DCD_ITEM(0x021b0010, MDCFG1_VAL)
+ MXC_DCD_ITEM(0x021b0014, MDCFG2_VAL)
+ MXC_DCD_ITEM(0x021b002c, 0x000026d2) /* MDRWD */
+ MXC_DCD_ITEM(0x021b0030, MDOR_VAL)
+ MXC_DCD_ITEM(0x021b0008, MDOTC_VAL)
+ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_0)
+ MXC_DCD_ITEM(0x021b0040, 0x00000027) /* MDASP */
+
+ /* CS0 MRS: */
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 0, mr0_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 2, mr2_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0))
+#if BANK_ADDR_BITS > 1
+ /* CS1 MRS: MR2 */
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 0, mr0_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 1, mr1_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 2, mr2_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
+#endif
+ MXC_DCD_ITEM(0x021b0020, 0x0000c000) /* disable refresh */
+
+ MXC_DCD_ITEM(0x021b0818, 0x00011112) /* MPODTCTRL */
+ MXC_DCD_ITEM(0x021b4818, 0x00011112)
+
+ /* DDR3 calibration */
+ MXC_DCD_ITEM(0x021b0890, 0x00000003) /* select default compare pattern for DQ calibration */
+ MXC_DCD_ITEM(0x021b0404, 0x00011007)
+
+ /* ZQ calibration */
+ MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */
+ MXC_DCD_ITEM(0x021b001c, 0x04008040) /* MRS: ZQ calibration */
+
+ MXC_DCD_ITEM(0x021b4800, 0xa138002b)
+ MXC_DCD_ITEM(0x021b0800, 0xa139002b)
+zq_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0800, 0x00010000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
+
+ /* Write leveling */
+ MXC_DCD_ITEM(0x021b4800, 0xa1380000)
+ MXC_DCD_ITEM(0x021b0800, 0xa1380000)
+
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
+ MXC_DCD_ITEM(0x021b001c, 0x00808231) /* MRS: start write leveling */
+
+ MXC_DCD_ITEM(0x021b0808, 0x00000001) /* initiate Write leveling */
+wl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000001)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000f00)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000001)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000f00)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset)
+
+ MXC_DCD_ITEM(0x021b0800, 0xa138002b)
+ MXC_DCD_ITEM(0x021b4800, 0xa138002b)
+
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
+
+ /* DQS gating calibration */
+ MXC_DCD_ITEM(0x020e05a8, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
+ MXC_DCD_ITEM(0x020e05b0, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e0524, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e051c, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e0518, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e050c, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e05b8, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e05c0, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | (7 << 6) | (3 << 16)) /* RALAT/WALAT max. */
+
+ MXC_DCD_ITEM(0x021b001c, 0x00008020) /* issue one refresh cycle */
+ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
+
+ MXC_DCD_ITEM(0x021b0848, 0x40404040) /* DQ RD Delay default values */
+ MXC_DCD_ITEM(0x021b4848, 0x40404040)
+ MXC_DCD_ITEM(0x021b0850, 0x40404040) /* DQ WR Delay default values */
+ MXC_DCD_ITEM(0x021b4850, 0x40404040)
+ MXC_DCD_ITEM(0x021b48b8, 0x00000800)
+ MXC_DCD_ITEM(0x021b08b8, 0x00000800)
+
+ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue fifo reset */
+dqs_fifo_reset:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2)
+ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue 2nd fifo reset */
+dqs_fifo_reset2:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
+ MXC_DCD_ITEM(0x021b083c, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
+dqs_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x10000000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x00001000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x10000000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x00001000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_fifo_reset1)
+
+ /* DRAM_SDQS[0..7] pad config */
+ MXC_DCD_ITEM(0x020e05a8, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e05b0, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e0524, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e051c, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e0518, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e050c, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e05b8, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e05c0, SDQS_MASK)
+
+ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL)
+rd_dl_fifo_reset1:
+ /* Read delay calibration */
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET, rd_dl_fifo_reset2)
+ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue fifo reset */
+rd_dl_fifo_reset2:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET, rd_dl_fifo_reset3)
+ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue 2nd fifo reset */
+rd_dl_fifo_reset3:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
+
+ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
+ MXC_DCD_ITEM(0x021b0860, 0x00000030) /* MPRDDLHWCTL: HW_RD_DL_EN */
+rd_dl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x0000000f)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x0000000f)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_fifo_reset1)
+
+ /* Write Delay calibration */
+wr_dl_fifo_reset1:
+ /* Read delay calibration */
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET, wr_dl_fifo_reset2)
+ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue fifo reset */
+wr_dl_fifo_reset2:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET, wr_dl_fifo_reset3)
+ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue 2nd fifo reset */
+wr_dl_fifo_reset3:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
+
+ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
+ MXC_DCD_ITEM(0x021b0864, 0x00000030) /* start WR DL calibration */
+wr_dl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x0000000f)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x0000000f)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr)
+
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
+ MXC_DCD_ITEM(0x021b0020, 0x00005800) /* MDREF */
+ MXC_DCD_ITEM(0x021b0404, 0x00011006) /* MAPSR */
+ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_1)
+
+ /* MDSCR: Normal operation */
+ MXC_DCD_ITEM(0x021b001c, 0x00000000)
+con_ack_clr:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b001c, 0x00004000)
+dcd_end:
+ .ifgt dcd_end - dcd_start - 1768
+ DCD too large!
+ .endif
+dcd_size:
+ .word (1768 - (dcd_end - dcd_start)) / (3 * 4)
--- /dev/null
+#include <config.h>
+#include <configs/tx6q.h>
+#include <asm/arch/imx-regs.h>
+
+#define DEBUG_LED_BIT 20
+#define LED_GPIO_BASE GPIO2_BASE_ADDR
+#define LED_MUX_OFFSET 0x0ec
+#define LED_MUX_MODE 0x15
+
+#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
+
+#ifdef PHYS_SDRAM_2_SIZE
+#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#else
+#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
+#endif
+
+#define CPU_2_BE_32(l) \
+ ((((l) << 24) & 0xFF000000) | \
+ (((l) << 8) & 0x00FF0000) | \
+ (((l) >> 8) & 0x0000FF00) | \
+ (((l) >> 24) & 0x000000FF))
+
+#define MXC_DCD_ITEM(addr, val) .word CPU_2_BE_32(addr), CPU_2_BE_32(val)
+
+#define CHECK_DCD_ADDR(a) ((((a) >= 0x00907000) && ((a) <= 0x00937FF0)) || \
+ (((a) >= 0x020C4000) && ((a) < 0x020C8000)) || \
+ (((a) >= 0x020C8000) && ((a) < 0x020C9000)) || \
+ (((a) >= 0x020E0000) && ((a) < 0x020E4000)) || \
+ (((a) >= 0x021B0000) && ((a) < 0x021B8000)) || \
+ (((a) >= 0x08000000) && ((a) < 0x0FFF0000)) || \
+ (((a) >= 0x10000000)))
+
+#define MXC_DCD_CMD_SZ_BYTE 1
+#define MXC_DCD_CMD_SZ_SHORT 2
+#define MXC_DCD_CMD_SZ_WORD 4
+#define MXC_DCD_CMD_FLAG_WRITE 0x0
+#define MXC_DCD_CMD_FLAG_CLR 0x1
+#define MXC_DCD_CMD_FLAG_SET 0x3
+#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
+#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
+#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
+
+#define MXC_DCD_CMD_WRT(type, flags, next) \
+ .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
+
+#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
+ .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
+ CPU_2_BE_32(addr), CPU_2_BE_32(mask)
+
+#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
+ .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
+ CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
+
+#define MXC_DCD_CMD_NOP \
+ .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+
+#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
+#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+
+ .macro CK_VAL, name, clks, offs, max
+ .iflt \clks - \offs
+ .set \name, 0
+ .else
+ .ifle \clks - \offs - \max
+ .set \name, \clks - \offs
+ .endif
+ .endif
+ .endm
+
+ .macro NS_VAL, name, ns, offs, max
+ .iflt \ns - \offs
+ .set \name, 0
+ .else
+ CK_VAL \name, NS_TO_CK(\ns), \offs, \max
+ .endif
+ .endm
+
+ .macro CK_MAX, name, ck1, ck2, offs, max
+ .ifgt \ck1 - \ck2
+ CK_VAL \name, \ck1, \offs, \max
+ .else
+ CK_VAL \name, \ck2, \offs, \max
+ .endif
+ .endm
+
+#define MDMISC_DDR_TYPE_DDR3 0
+#define MDMISC_DDR_TYPE_LPDDR2 1
+#define MDMISC_DDR_TYPE_DDR2 2
+
+#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
+
+#define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */
+
+/* DDR3 SDRAM */
+#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
+#define BANK_ADDR_BITS 2
+#else
+#define BANK_ADDR_BITS 1
+#endif
+#define SDRAM_BURST_LENGTH 8
+#define RALAT 5
+#define WALAT 0
+#define BI_ON 1
+#define ADDR_MIRROR 1
+#define DDR_TYPE MDMISC_DDR_TYPE_DDR3
+
+/* 512/1024MiB SDRAM: NT5CB128M16P-CG */
+/* MDCFG0 0x0c */
+NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
+CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
+CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
+CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
+NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */
+
+/* MDCFG1 0x10 */
+NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
+NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
+NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */
+
+/* MDCFG2 0x14 */
+CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
+CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+
+/* MDOR 0x30 */
+CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
+#define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
+#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
+
+/* MDOTC 0x08 */
+NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */
+
+/* MDPDC 0x04 */
+CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7
+CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
+CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
+
+#define PRCT 0
+#define PWDT 5
+#define SLOW_PD 0
+#define BOTH_CS_PD 1
+
+#define MDPDC_VAL_0 ( \
+ (PRCT << 28) | \
+ (PRCT << 24) | \
+ (tCKE << 16) | \
+ (SLOW_PD << 7) | \
+ (BOTH_CS_PD << 6) | \
+ (tCKSRX << 3) | \
+ (tCKSRE << 0) \
+ )
+
+#define MDPDC_VAL_1 (MDPDC_VAL_0 | \
+ (PWDT << 12) | \
+ (PWDT << 8) \
+ )
+
+#define ROW_ADDR_BITS 14
+#define COL_ADDR_BITS 10
+
+ .iflt tWR - 7
+ .set mr0_val, ((1 << 8) /* DLL Reset */ | \
+ ((tWR + 1 - 4) << 9) | \
+ (((tCL + 3) - 4) << 4))
+ .else
+ .set mr0_val, ((1 << 8) /* DLL Reset */ | \
+ (((tWR + 1) / 2) << 9) | \
+ (((tCL + 3) - 4) << 4))
+ .endif
+#define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
+ (1 << 15) /* CON REQ */ | \
+ (3 << 4) /* MRS command */ | \
+ ((cs) << 3) | \
+ ((mr) << 0))
+
+#define mr1_val 0x0040
+#define mr2_val 0x0408
+
+#define MDCFG0_VAL ( \
+ (tRFC << 24) | \
+ (tXS << 16) | \
+ (tXP << 13) | \
+ (tXPDLL << 9) | \
+ (tFAW << 4) | \
+ (tCL << 0)) \
+
+#define MDCFG1_VAL ( \
+ (tRCD << 29) | \
+ (tRP << 26) | \
+ (tRC << 21) | \
+ (tRAS << 16) | \
+ (tRPA << 15) | \
+ (tWR << 9) | \
+ (tMRD << 5) | \
+ (tCWL << 0)) \
+
+#define MDCFG2_VAL ( \
+ (tDLLK << 16) | \
+ (tRTP << 6) | \
+ (tWTR << 3) | \
+ (tRRD << 0))
+
+#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
+#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
+ ((COL_ADDR_BITS - 9) << 20) | \
+ (BURST_LEN << 19) | \
+ (2 << 16) | /* SDRAM bus width */ \
+ ((-1) << (32 - BANK_ADDR_BITS)))
+
+#define MDMISC_VAL ((ADDR_MIRROR << 19) | \
+ (WALAT << 16) | \
+ (BI_ON << 12) | \
+ (0x3 << 9) | \
+ (RALAT << 6) | \
+ (DDR_TYPE << 3))
+
+#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
+
+#define MDOTC_VAL ((tAOFPD << 27) | \
+ (tAONPD << 24) | \
+ (tANPD << 20) | \
+ (tAXPD << 16) | \
+ (tODTLon << 12) | \
+ (tODTLoff << 4))
+
+fcb_start:
+ b _start
+ .org 0x400
+ivt_header:
+ .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
+app_start_addr:
+ .long _start
+ .long 0x0
+dcd_ptr:
+ .long dcd_hdr
+boot_data_ptr:
+ .word boot_data
+self_ptr:
+ .word ivt_header
+app_code_csf:
+ .word 0x0
+ .word 0x0
+boot_data:
+ .long fcb_start
+image_len:
+ .long CONFIG_U_BOOT_IMG_SIZE
+plugin:
+ .word 0
+ivt_end:
+#define DCD_VERSION 0x40
+
+#define CLKCTL_CCGR0 0x68
+#define CLKCTL_CCGR1 0x6c
+#define CLKCTL_CCGR2 0x70
+#define CLKCTL_CCGR3 0x74
+#define CLKCTL_CCGR4 0x78
+#define CLKCTL_CCGR5 0x7c
+#define CLKCTL_CCGR6 0x80
+#define CLKCTL_CCGR7 0x84
+#define CLKCTL_CMEOR 0x88
+
+#define DDR_SEL_VAL 3
+#define DSE_VAL 6
+#define ODT_VAL 2
+
+#define DDR_SEL_SHIFT 18
+#define DDR_MODE_SHIFT 17
+#define ODT_SHIFT 8
+#define DSE_SHIFT 3
+#define HYS_SHIFT 16
+#define PKE_SHIFT 12
+#define PUE_SHIFT 13
+#define PUS_SHIFT 14
+
+#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
+#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT)
+#define DSE_MASK (DSE_VAL << DSE_SHIFT)
+#define ODT_MASK (ODT_VAL << ODT_SHIFT)
+
+#define DQM_MASK (DDR_MODE_MASK | DSE_MASK)
+#define SDQS_MASK DSE_MASK
+#define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK)
+#define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define DDR_ADDR_MASK 0
+#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK)
+
+dcd_hdr:
+ .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
+dcd_start:
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset)
+ /* RESET_OUT GPIO_7_12 */
+ MXC_DCD_ITEM(0x020e024c, 0x00000005)
+
+ MXC_DCD_ITEM(0x020c402c, 0x01e436c1) /* CSC2CDR default: 0x007236c1 */
+ MXC_DCD_ITEM(0x020c80e0, 0x00002001) /* ENET PLL */
+
+ /* enable all relevant clocks... */
+ MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
+ MXC_DCD_ITEM(0x020c406c, 0xf0fc0c00) /* default: 0xf0fc0000 */
+ MXC_DCD_ITEM(0x020c4070, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
+ MXC_DCD_ITEM(0x020c4074, 0x3ff00000) /* default: 0x3ff00000 */
+ MXC_DCD_ITEM(0x020c4078, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
+ MXC_DCD_ITEM(0x020c407c, 0xff033f0f) /* default: 0xf0033f0f UART1 */
+ MXC_DCD_ITEM(0x020c4080, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
+
+ /* IOMUX: */
+ MXC_DCD_ITEM(0x020e0004, 0x48640005) /* default: 0x48400005 ENET_CLK output */
+ /* UART1 pad config */
+ MXC_DCD_ITEM(0x020e02a8, 0x00000001) /* UART1 TXD */
+ MXC_DCD_ITEM(0x020e02ac, 0x00000001) /* UART1 RXD */
+ MXC_DCD_ITEM(0x020e0920, 0x00000003) /* UART1 RXD INPUT_SEL */
+ MXC_DCD_ITEM(0x020e02c0, 0x00000001) /* UART1 CTS */
+ MXC_DCD_ITEM(0x020e02c4, 0x00000001) /* UART1 RTS */
+ MXC_DCD_ITEM(0x020e091c, 0x00000003) /* UART1 RTS INPUT_SEL */
+#if 0
+ /* NAND */
+ MXC_DCD_ITEM(0x020e02d4, 0x00000000) /* NANDF_CLE: NANDF_CLE */
+ MXC_DCD_ITEM(0x020e02d8, 0x00000000) /* NANDF_ALE: NANDF_ALE */
+ MXC_DCD_ITEM(0x020e02dc, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
+ MXC_DCD_ITEM(0x020e02e0, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
+ MXC_DCD_ITEM(0x020e02e4, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
+ MXC_DCD_ITEM(0x020e02f4, 0x00000001) /* SD4_CMD: NANDF_RDn */
+ MXC_DCD_ITEM(0x020e02f8, 0x00000001) /* SD4_CLK: NANDF_WRn */
+ MXC_DCD_ITEM(0x020e02fc, 0x00000000) /* NANDF_D0: NANDF_D0 */
+ MXC_DCD_ITEM(0x020e0300, 0x00000000) /* NANDF_D1: NANDF_D1 */
+ MXC_DCD_ITEM(0x020e0304, 0x00000000) /* NANDF_D2: NANDF_D2 */
+ MXC_DCD_ITEM(0x020e0308, 0x00000000) /* NANDF_D3: NANDF_D3 */
+ MXC_DCD_ITEM(0x020e030c, 0x00000000) /* NANDF_D4: NANDF_D4 */
+ MXC_DCD_ITEM(0x020e0310, 0x00000000) /* NANDF_D5: NANDF_D5 */
+ MXC_DCD_ITEM(0x020e0314, 0x00000000) /* NANDF_D6: NANDF_D6 */
+ MXC_DCD_ITEM(0x020e0318, 0x00000000) /* NANDF_D7: NANDF_D7 */
+#endif
+ /* ext. mem CS */
+ MXC_DCD_ITEM(0x020e02ec, 0x00000000) /* NANDF_CS2: NANDF_CS2 */
+ /* DRAM_DQM[0..7] */
+ MXC_DCD_ITEM(0x020e05ac, DQM_MASK)
+ MXC_DCD_ITEM(0x020e05b4, DQM_MASK)
+ MXC_DCD_ITEM(0x020e0528, DQM_MASK)
+ MXC_DCD_ITEM(0x020e0520, DQM_MASK)
+ MXC_DCD_ITEM(0x020e0514, DQM_MASK)
+ MXC_DCD_ITEM(0x020e0510, DQM_MASK)
+ MXC_DCD_ITEM(0x020e05bc, DQM_MASK)
+ MXC_DCD_ITEM(0x020e05c4, DQM_MASK)
+ /* DRAM_A[0..15] */
+ MXC_DCD_ITEM(0x020e052c, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0530, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0534, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0538, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e053c, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0540, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0544, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0548, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e054c, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0550, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0554, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0558, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e055c, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0560, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0564, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0568, DDR_ADDR_MASK)
+ /* DRAM_CAS */
+ MXC_DCD_ITEM(0x020e056c, DDR_CTRL_MASK)
+ /* DRAM_RAS */
+ MXC_DCD_ITEM(0x020e0578, DDR_CTRL_MASK)
+ /* DRAM_SDCLK[0..1] */
+ MXC_DCD_ITEM(0x020e0588, SDCLK_MASK)
+ MXC_DCD_ITEM(0x020e0594, SDCLK_MASK)
+ /* DRAM_RESET */
+ MXC_DCD_ITEM(0x020e057c, DDR_CTRL_MASK)
+ /* DRAM_SDCKE[0..1] */
+ MXC_DCD_ITEM(0x020e0590, SDCKE_MASK)
+ MXC_DCD_ITEM(0x020e0598, SDCKE_MASK)
+ /* DRAM_SDBA[0..2] */
+ MXC_DCD_ITEM(0x020e0580, 0x00000000)
+ MXC_DCD_ITEM(0x020e0584, 0x00000000)
+ MXC_DCD_ITEM(0x020e058c, 0x00000000)
+ /* DRAM_SDODT[0..1] */
+ MXC_DCD_ITEM(0x020e059c, SDODT_MASK)
+ MXC_DCD_ITEM(0x020e05a0, SDODT_MASK)
+ /* DRAM_B[0..7]DS */
+ MXC_DCD_ITEM(0x020e0784, DSE_MASK)
+ MXC_DCD_ITEM(0x020e0788, DSE_MASK)
+ MXC_DCD_ITEM(0x020e0794, DSE_MASK)
+ MXC_DCD_ITEM(0x020e079c, DSE_MASK)
+ MXC_DCD_ITEM(0x020e07a0, DSE_MASK)
+ MXC_DCD_ITEM(0x020e07a4, DSE_MASK)
+ MXC_DCD_ITEM(0x020e07a8, DSE_MASK)
+ MXC_DCD_ITEM(0x020e0748, DSE_MASK)
+ /* ADDDS */
+ MXC_DCD_ITEM(0x020e074c, DSE_MASK)
+ /* DDRMODE_CTL */
+ MXC_DCD_ITEM(0x020e0750, DDR_MODE_MASK)
+ /* DDRPKE */
+ MXC_DCD_ITEM(0x020e0758, 0x00000000)
+ /* DDRMODE */
+ MXC_DCD_ITEM(0x020e0774, DDR_MODE_MASK)
+ /* CTLDS */
+ MXC_DCD_ITEM(0x020e078c, DSE_MASK)
+ /* DDR_TYPE */
+ MXC_DCD_ITEM(0x020e0798, DDR_SEL_MASK)
+ /* DDRPK */
+ MXC_DCD_ITEM(0x020e0768, 1 << PUE_SHIFT)
+ /* DDRHYS */
+ MXC_DCD_ITEM(0x020e0770, 0x00000000)
+ /* TERM_CTL[0..7] */
+ MXC_DCD_ITEM(0x020e0754, ODT_MASK)
+ MXC_DCD_ITEM(0x020e075c, ODT_MASK)
+ MXC_DCD_ITEM(0x020e0760, ODT_MASK)
+ MXC_DCD_ITEM(0x020e0764, ODT_MASK)
+ MXC_DCD_ITEM(0x020e076c, ODT_MASK)
+ MXC_DCD_ITEM(0x020e0778, ODT_MASK)
+ MXC_DCD_ITEM(0x020e077c, ODT_MASK)
+ MXC_DCD_ITEM(0x020e0780, ODT_MASK)
+
+ /* SDRAM initialization */
+ /* MPRDDQBY[0..7]DL */
+ MXC_DCD_ITEM(0x021b081c, 0x33333333)
+ MXC_DCD_ITEM(0x021b481c, 0x33333333)
+ MXC_DCD_ITEM(0x021b0820, 0x33333333)
+ MXC_DCD_ITEM(0x021b4820, 0x33333333)
+ MXC_DCD_ITEM(0x021b0824, 0x33333333)
+ MXC_DCD_ITEM(0x021b4824, 0x33333333)
+ MXC_DCD_ITEM(0x021b0828, 0x33333333)
+ MXC_DCD_ITEM(0x021b4828, 0x33333333)
+ /* MDMISC */
+ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | 2) /* reset MMDC FSM */
+ddr_reset:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0018, 0x00000002)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack)
+
+ /* MSDSCR Conf Req */
+ MXC_DCD_ITEM(0x021b001c, 0x00008000)
+con_ack:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b001c, 0x00004000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib)
+ /* MDCTL */
+ MXC_DCD_ITEM(0x021b0000, MDCTL_VAL)
+ddr_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b0018, 0x40000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
+
+ MXC_DCD_ITEM(0x021b000c, MDCFG0_VAL)
+ MXC_DCD_ITEM(0x021b0010, MDCFG1_VAL)
+ MXC_DCD_ITEM(0x021b0014, MDCFG2_VAL)
+ MXC_DCD_ITEM(0x021b002c, 0x000026d2) /* MDRWD */
+ MXC_DCD_ITEM(0x021b0030, MDOR_VAL)
+ MXC_DCD_ITEM(0x021b0008, MDOTC_VAL)
+ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_0)
+ MXC_DCD_ITEM(0x021b0040, 0x00000027) /* MDASP */
+
+ /* CS0 MRS: */
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 0, mr0_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 2, mr2_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0))
+#if BANK_ADDR_BITS > 1
+ /* CS1 MRS: MR2 */
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 0, mr0_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 1, mr1_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 2, mr2_val))
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
+#endif
+ MXC_DCD_ITEM(0x021b0020, 0x0000c000) /* disable refresh */
+
+ MXC_DCD_ITEM(0x021b0818, 0x00011112) /* MPODTCTRL */
+ MXC_DCD_ITEM(0x021b4818, 0x00011112)
+
+ /* DDR3 calibration */
+ MXC_DCD_ITEM(0x021b0890, 0x00000003) /* select default compare pattern for DQ calibration */
+ MXC_DCD_ITEM(0x021b0404, 0x00011007)
+
+ /* ZQ calibration */
+ MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */
+ MXC_DCD_ITEM(0x021b001c, 0x04008040) /* MRS: ZQ calibration */
+
+ MXC_DCD_ITEM(0x021b4800, 0xa138002b)
+ MXC_DCD_ITEM(0x021b0800, 0xa139002b)
+zq_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0800, 0x00010000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
+
+ /* Write leveling */
+ MXC_DCD_ITEM(0x021b4800, 0xa1380000)
+ MXC_DCD_ITEM(0x021b0800, 0xa1380000)
+
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
+ MXC_DCD_ITEM(0x021b001c, 0x00808231) /* MRS: start write leveling */
+
+ MXC_DCD_ITEM(0x021b0808, 0x00000001) /* initiate Write leveling */
+wl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000001)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000f00)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000001)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000f00)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset)
+
+ MXC_DCD_ITEM(0x021b0800, 0xa138002b)
+ MXC_DCD_ITEM(0x021b4800, 0xa138002b)
+
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
+
+ /* DQS gating calibration */
+ MXC_DCD_ITEM(0x020e05a8, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
+ MXC_DCD_ITEM(0x020e05b0, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e0524, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e051c, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e0518, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e050c, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e05b8, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x020e05c0, SDQS_MASK | 0x7000)
+ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | (7 << 6) | (3 << 16)) /* RALAT/WALAT max. */
+
+ MXC_DCD_ITEM(0x021b001c, 0x00008020) /* issue one refresh cycle */
+ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
+
+ MXC_DCD_ITEM(0x021b0848, 0x40404040) /* DQ RD Delay default values */
+ MXC_DCD_ITEM(0x021b4848, 0x40404040)
+ MXC_DCD_ITEM(0x021b0850, 0x40404040) /* DQ WR Delay default values */
+ MXC_DCD_ITEM(0x021b4850, 0x40404040)
+ MXC_DCD_ITEM(0x021b48b8, 0x00000800)
+ MXC_DCD_ITEM(0x021b08b8, 0x00000800)
+
+ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue fifo reset */
+dqs_fifo_reset:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2)
+ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue 2nd fifo reset */
+dqs_fifo_reset2:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
+ MXC_DCD_ITEM(0x021b083c, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
+dqs_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x10000000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x00001000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x10000000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x00001000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_fifo_reset1)
+
+ /* DRAM_SDQS[0..7] pad config */
+ MXC_DCD_ITEM(0x020e05a8, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e05b0, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e0524, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e051c, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e0518, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e050c, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e05b8, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e05c0, SDQS_MASK)
+
+ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL)
+rd_dl_fifo_reset1:
+ /* Read delay calibration */
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET, rd_dl_fifo_reset2)
+ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue fifo reset */
+rd_dl_fifo_reset2:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET, rd_dl_fifo_reset3)
+ MXC_DCD_ITEM(0x021b083c, 0x80000000) /* issue 2nd fifo reset */
+rd_dl_fifo_reset3:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x80000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
+
+ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
+ MXC_DCD_ITEM(0x021b0860, 0x00000030) /* MPRDDLHWCTL: HW_RD_DL_EN */
+rd_dl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x0000000f)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x0000000f)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
+
+ /* Write Delay calibration */
+ MXC_DCD_ITEM(0x021b001c, 0x04008050) /* precharge all to bank 0 */
+ MXC_DCD_ITEM(0x021b0864, 0x00000030) /* start WR DL calibration */
+wr_dl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x0000000f)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x0000000f)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr)
+
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
+ MXC_DCD_ITEM(0x021b0020, 0x00005800) /* MDREF */
+ MXC_DCD_ITEM(0x021b0404, 0x00011006) /* MAPSR */
+ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_1)
+
+ /* MDSCR: Normal operation */
+ MXC_DCD_ITEM(0x021b001c, 0x00000000)
+con_ack_clr:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b001c, 0x00004000)
+dcd_end:
+ .ifgt dcd_end - dcd_start - 1768
+ DCD too large!
+ .endif
+dcd_size:
+ .word (1768 - (dcd_end - dcd_start)) / (3 * 4)
--- /dev/null
+#include <config.h>
+#include <configs/tx6q.h>
+#include <asm/arch/imx-regs.h>
+
+#define DEBUG_LED_BIT 20
+#define LED_GPIO_BASE GPIO2_BASE_ADDR
+#define LED_MUX_OFFSET 0x0ec
+#define LED_MUX_MODE 0x15
+
+#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
+
+#ifdef PHYS_SDRAM_2_SIZE
+#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#else
+#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
+#endif
+
+#if 1
+#define CPU_2_BE_32(l) \
+ ((((l) << 24) & 0xFF000000) | \
+ (((l) << 8) & 0x00FF0000) | \
+ (((l) >> 8) & 0x0000FF00) | \
+ (((l) >> 24) & 0x000000FF))
+#else
+#define CPU_2_BE_32(l) (l)
+#endif
+
+#define MXC_DCD_ITEM(addr, val) .word CPU_2_BE_32(addr), CPU_2_BE_32(val)
+
+#define CHECK_DCD_ADDR(a) ((((a) >= 0x00907000) && ((a) <= 0x00937FF0)) || \
+ (((a) >= 0x020C4000) && ((a) < 0x020C8000)) || \
+ (((a) >= 0x020C8000) && ((a) < 0x020C9000)) || \
+ (((a) >= 0x020E0000) && ((a) < 0x020E4000)) || \
+ (((a) >= 0x021B0000) && ((a) < 0x021B8000)) || \
+ (((a) >= 0x08000000) && ((a) < 0x0FFF0000)) || \
+ (((a) >= 0x10000000)))
+
+#define MXC_DCD_CMD_SZ_BYTE 1
+#define MXC_DCD_CMD_SZ_SHORT 2
+#define MXC_DCD_CMD_SZ_WORD 4
+#define MXC_DCD_CMD_FLAG_WRITE 0x0
+#define MXC_DCD_CMD_FLAG_CLR 0x1
+#define MXC_DCD_CMD_FLAG_SET 0x3
+#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
+#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
+#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
+
+#define MXC_DCD_CMD_WRT(type, flags, next) \
+ .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
+
+#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
+ .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
+ CPU_2_BE_32(addr), CPU_2_BE_32(mask)
+
+#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
+ .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
+ CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
+
+#define MXC_DCD_CMD_NOP \
+ .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+
+#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
+#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+
+ .macro CK_VAL, name, clks, offs, max
+ .iflt \clks - \offs
+ .set \name, 0
+ .else
+ .ifle \clks - \offs - \max
+ .set \name, \clks - \offs
+ .endif
+ .endif
+ .endm
+
+ .macro NS_VAL, name, ns, offs, max
+ .iflt \ns - \offs
+ .set \name, 0
+ .else
+ CK_VAL \name, NS_TO_CK(\ns), \offs, \max
+ .endif
+ .endm
+
+ .macro CK_MAX, name, ck1, ck2, offs, max
+ .ifgt \ck1 - \ck2
+ CK_VAL \name, \ck1, \offs, \max
+ .else
+ CK_VAL \name, \ck2, \offs, \max
+ .endif
+ .endm
+
+#define MDMISC_DDR_TYPE_DDR3 0
+#define MDMISC_DDR_TYPE_LPDDR2 1
+#define MDMISC_DDR_TYPE_DDR2 2
+
+#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
+
+#define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */
+
+/* DDR3 SDRAM */
+#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
+#define BANK_ADDR_BITS 2
+#else
+#define BANK_ADDR_BITS 1
+#endif
+#define SDRAM_BURST_LENGTH 8
+#define RALAT 5
+#define WALAT 0
+#define BI_ON 1
+#define ADDR_MIRROR 1
+#define DDR_TYPE MDMISC_DDR_TYPE_DDR3
+
+/* 512/1024MiB SDRAM: NT5CB128M16P-CG */
+/* MDCFG0 0x0c */
+NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
+CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
+CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
+CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
+NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tCL, 8, 3, 8 /* clks - 3 (0..8) CAS Latency */
+
+/* MDCFG1 0x10 */
+NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
+NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
+NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tCWL, 6, 2, 6 /* clks - 2 (0..6) */
+
+/* MDCFG2 0x14 */
+CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
+CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
+
+/* MDOR 0x30 */
+CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
+#define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
+#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
+
+/* MDOTC 0x08 */
+NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */
+NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tODTLon tCWL, 1, 7 /* clks - 1 (0..7) */
+CK_VAL tODTLoff tCWL, 1, 31 /* clks - 1 (0..31) */
+
+/* MDPDC 0x04 */
+CK_MAX tCKE, NS_TO_CK(6), 3, 1, 7
+CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
+CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
+
+#define PRCT 0
+#define PWDT 5
+#define SLOW_PD 0
+#define BOTH_CS_PD 1
+
+#define MDPDC_VAL_0 ( \
+ (tCKE << 16) | \
+ (tCKSRX << 3) | \
+ (tCKSRE << 0) \
+ )
+
+#define MDPDC_VAL_1 (MDPDC_VAL_0 | \
+ (PRCT << 28) | \
+ (PRCT << 24) | \
+ (PWDT << 12) | \
+ (PWDT << 8) | \
+ (BOTH_CS_PD << 6) | \
+ (SLOW_PD << 7) \
+ )
+
+#define ROW_ADDR_BITS 14
+#define COL_ADDR_BITS 10
+
+ .iflt tWR - 7
+ .set mrs_val, ((1 << 15) /* CON REQ */ | \
+ (3 << 4) /* MRS command */ | \
+ ((1 << 8) /* DLL Reset */ | \
+ ((tWR + 1 - 4) << 9) | \
+ (((tCL + 3) - 4) << 4)) << 16)
+ .else
+ .set mrs_val, ((1 << 15) /* CON REQ */ | \
+ (3 << 4) /* MRS command */ | \
+ ((1 << 8) /* DLL Reset */ | \
+ (((tWR + 1) / 2) << 9) | \
+ (((tCL + 3) - 4) << 4)) << 16)
+ .endif
+#define MDSCR_MRS_VAL(cs) (mrs_val | ((cs) << 3))
+
+#define MDCFG0_VAL ( \
+ (tRFC << 24) | \
+ (tXS << 16) | \
+ (tXP << 13) | \
+ (tXPDLL << 9) | \
+ (tFAW << 4) | \
+ (tCL << 0)) \
+
+#define MDCFG1_VAL ( \
+ (tRCD << 29) | \
+ (tRP << 26) | \
+ (tRC << 21) | \
+ (tRAS << 16) | \
+ (tRPA << 15) | \
+ (tWR << 9) | \
+ (tMRD << 5) | \
+ (tCWL << 0)) \
+
+#define MDCFG2_VAL ( \
+ (tDLLK << 16) | \
+ (tRTP << 6) | \
+ (tWTR << 3) | \
+ (tRRD << 0))
+
+#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
+#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
+ ((COL_ADDR_BITS - 9) << 20) | \
+ (BURST_LEN << 19) | \
+ (2 << 16) | /* SDRAM bus width */ \
+ ((-1) << (32 - BANK_ADDR_BITS)))
+
+#define MDMISC_VAL ((ADDR_MIRROR << 19) | \
+ (WALAT << 16) | \
+ (BI_ON << 12) | \
+ (0x3 << 9) | \
+ (RALAT << 6) | \
+ (DDR_TYPE << 3))
+
+#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
+
+#define MDOTC_VAL ((tAOFPD << 27) | \
+ (tAONPD << 24) | \
+ (tANPD << 20) | \
+ (tAXPD << 16) | \
+ (tODTLon << 12) | \
+ (tODTLoff << 4))
+
+fcb_start:
+ b _start
+ .org 0x400
+ivt_header:
+ .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
+app_start_addr:
+ .long _start
+ .long 0x0
+dcd_ptr:
+ .long dcd_hdr
+boot_data_ptr:
+ .word boot_data
+self_ptr:
+ .word ivt_header
+app_code_csf:
+ .word 0x0
+ .word 0x0
+boot_data:
+ .long fcb_start
+image_len:
+ .long CONFIG_U_BOOT_IMG_SIZE
+plugin:
+ .word 0
+ivt_end:
+#define DCD_VERSION 0x40
+
+#define CLKCTL_CCGR0 0x68
+#define CLKCTL_CCGR1 0x6c
+#define CLKCTL_CCGR2 0x70
+#define CLKCTL_CCGR3 0x74
+#define CLKCTL_CCGR4 0x78
+#define CLKCTL_CCGR5 0x7c
+#define CLKCTL_CCGR6 0x80
+#define CLKCTL_CCGR7 0x84
+#define CLKCTL_CMEOR 0x88
+
+#define DDR_SEL_VAL 3
+#define DSE_VAL 6
+#define ODT_VAL 2
+
+#define DDR_SEL_SHIFT 18
+#define DDR_MODE_SHIFT 17
+#define ODT_SHIFT 8
+#define DSE_SHIFT 3
+#define HYS_SHIFT 16
+#define PKE_SHIFT 12
+#define PUE_SHIFT 13
+#define PUS_SHIFT 14
+
+#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
+#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT)
+#define DSE_MASK (DSE_VAL << DSE_SHIFT)
+#define ODT_MASK (ODT_VAL << ODT_SHIFT)
+
+#define DQM_MASK (DDR_MODE_MASK | DSE_MASK)
+#define SDQS_MASK DSE_MASK
+#define SDODT_MASK (DSE_MASK | (0 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK)
+#define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
+#define DDR_ADDR_MASK DDR_MODE_MASK
+#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK)
+
+dcd_hdr:
+ .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
+dcd_start:
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack)
+ /* RESET_OUT GPIO_7_12 */
+ MXC_DCD_ITEM(0x020e024c, 0x00000005)
+#if 0
+ /* STK5 LED GPIO */
+ MXC_DCD_ITEM(0x020e00ec, (1 << 20))
+#endif
+ MXC_DCD_ITEM(0x020c402c, 0x01e436c1) /* CSC2CDR default: 0x007236c1 */
+ MXC_DCD_ITEM(0x020c80e0, 0x00002001) /* ENET PLL */
+
+ /* enable all relevant clocks... */
+ MXC_DCD_ITEM(0x020c4068, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
+ MXC_DCD_ITEM(0x020c406c, 0xf0fc0c00) /* default: 0xf0fc0000 */
+ MXC_DCD_ITEM(0x020c4070, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
+ MXC_DCD_ITEM(0x020c4074, 0x3ff00000) /* default: 0x3ff00000 */
+ MXC_DCD_ITEM(0x020c4078, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
+ MXC_DCD_ITEM(0x020c407c, 0xff033f0f) /* default: 0xf0033f0f UART1 */
+ MXC_DCD_ITEM(0x020c4080, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
+
+ /* IOMUX: */
+ MXC_DCD_ITEM(0x020e0004, 0x48640005) /* default: 0x48400005 ENET_CLK output */
+ /* UART1 pad config */
+ MXC_DCD_ITEM(0x020e02a8, 0x00000001) /* UART1 TXD */
+ MXC_DCD_ITEM(0x020e02ac, 0x00000001) /* UART1 RXD */
+ MXC_DCD_ITEM(0x020e0920, 0x00000003) /* UART1 RXD INPUT_SEL */
+ MXC_DCD_ITEM(0x020e02c0, 0x00000001) /* UART1 CTS */
+ MXC_DCD_ITEM(0x020e02c4, 0x00000001) /* UART1 RTS */
+ MXC_DCD_ITEM(0x020e091c, 0x00000003) /* UART1 RTS INPUT_SEL */
+ /* NAND */
+ MXC_DCD_ITEM(0x020e02d4, 0x00000000) /* NANDF_CLE: NANDF_CLE */
+ MXC_DCD_ITEM(0x020e02d8, 0x00000000) /* NANDF_ALE: NANDF_ALE */
+ MXC_DCD_ITEM(0x020e02dc, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
+ MXC_DCD_ITEM(0x020e02e0, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
+ MXC_DCD_ITEM(0x020e02e4, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
+ MXC_DCD_ITEM(0x020e02f4, 0x00000001) /* SD4_CMD: NANDF_RDn */
+ MXC_DCD_ITEM(0x020e02f8, 0x00000001) /* SD4_CLK: NANDF_WRn */
+ MXC_DCD_ITEM(0x020e02fc, 0x00000000) /* NANDF_D0: NANDF_D0 */
+ MXC_DCD_ITEM(0x020e0300, 0x00000000) /* NANDF_D1: NANDF_D1 */
+ MXC_DCD_ITEM(0x020e0304, 0x00000000) /* NANDF_D2: NANDF_D2 */
+ MXC_DCD_ITEM(0x020e0308, 0x00000000) /* NANDF_D3: NANDF_D3 */
+ MXC_DCD_ITEM(0x020e030c, 0x00000000) /* NANDF_D4: NANDF_D4 */
+ MXC_DCD_ITEM(0x020e0310, 0x00000000) /* NANDF_D5: NANDF_D5 */
+ MXC_DCD_ITEM(0x020e0314, 0x00000000) /* NANDF_D6: NANDF_D6 */
+ MXC_DCD_ITEM(0x020e0318, 0x00000000) /* NANDF_D7: NANDF_D7 */
+ /* ext. mem CS */
+ MXC_DCD_ITEM(0x020e02ec, 0x00000000) /* NANDF_CS2: NANDF_CS2 */
+ /* DRAM_SDQS[0..7] */
+ MXC_DCD_ITEM(0x020e05a8, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e05b0, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e0524, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e051c, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e0518, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e050c, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e05b8, SDQS_MASK)
+ MXC_DCD_ITEM(0x020e05c0, SDQS_MASK)
+ /* DRAM_DQM[0..7] */
+ MXC_DCD_ITEM(0x020e05ac, DQM_MASK)
+ MXC_DCD_ITEM(0x020e05b4, DQM_MASK)
+ MXC_DCD_ITEM(0x020e0528, DQM_MASK)
+ MXC_DCD_ITEM(0x020e0520, DQM_MASK)
+ MXC_DCD_ITEM(0x020e0514, DQM_MASK)
+ MXC_DCD_ITEM(0x020e0510, DQM_MASK)
+ MXC_DCD_ITEM(0x020e05bc, DQM_MASK)
+ MXC_DCD_ITEM(0x020e05c4, DQM_MASK)
+ /* DRAM_A[0..15] */
+ MXC_DCD_ITEM(0x020e052c, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0530, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0534, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0538, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e053c, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0540, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0544, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0548, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e054c, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0550, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0554, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0558, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e055c, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0560, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0564, DDR_ADDR_MASK)
+ MXC_DCD_ITEM(0x020e0568, DDR_ADDR_MASK)
+ /* DRAM_CAS */
+ MXC_DCD_ITEM(0x020e056c, DDR_CTRL_MASK)
+ /* DRAM_RAS */
+ MXC_DCD_ITEM(0x020e0578, DDR_CTRL_MASK)
+ /* DRAM_SDCLK[0..1] */
+ MXC_DCD_ITEM(0x020e0588, SDCLK_MASK)
+ MXC_DCD_ITEM(0x020e0594, SDCLK_MASK)
+ /* DRAM_RESET */
+ MXC_DCD_ITEM(0x020e057c, DDR_CTRL_MASK)
+ /* DRAM_SDCKE[0..1] */
+ MXC_DCD_ITEM(0x020e0590, SDCKE_MASK)
+ MXC_DCD_ITEM(0x020e0598, SDCKE_MASK)
+ /* DRAM_SDBA[0..2] */
+ MXC_DCD_ITEM(0x020e0580, 0x00000000)
+ MXC_DCD_ITEM(0x020e0584, 0x00000000)
+ MXC_DCD_ITEM(0x020e058c, 0x00000000)
+ /* DRAM_SDODT[0..1] */
+ MXC_DCD_ITEM(0x020e059c, SDODT_MASK)
+ MXC_DCD_ITEM(0x020e05a0, SDODT_MASK)
+ /* DRAM_B[0..7]DS */
+ MXC_DCD_ITEM(0x020e0784, DSE_MASK)
+ MXC_DCD_ITEM(0x020e0788, DSE_MASK)
+ MXC_DCD_ITEM(0x020e0794, DSE_MASK)
+ MXC_DCD_ITEM(0x020e079c, DSE_MASK)
+ MXC_DCD_ITEM(0x020e07a0, DSE_MASK)
+ MXC_DCD_ITEM(0x020e07a4, DSE_MASK)
+ MXC_DCD_ITEM(0x020e07a8, DSE_MASK)
+ MXC_DCD_ITEM(0x020e0748, DSE_MASK)
+ /* ADDDS */
+ MXC_DCD_ITEM(0x020e074c, DSE_MASK)
+ /* DDRMODE_CTL */
+ MXC_DCD_ITEM(0x020e0750, DDR_MODE_MASK)
+ /* DDRPKE */
+ MXC_DCD_ITEM(0x020e0758, 0x00000000)
+ /* DDRMODE */
+ MXC_DCD_ITEM(0x020e0774, DDR_MODE_MASK)
+ /* CTLDS */
+ MXC_DCD_ITEM(0x020e078c, DSE_MASK)
+ /* DDR_TYPE */
+ MXC_DCD_ITEM(0x020e0798, DDR_SEL_MASK)
+ /* DDRPK */
+ MXC_DCD_ITEM(0x020e0768, 1 << PUE_SHIFT)
+ /* DDRHYS */
+ MXC_DCD_ITEM(0x020e0770, 0x00000000)
+ /* TERM_CTL[0..7] */
+#if 0
+ MXC_DCD_ITEM(0x020e0754, ODT_MASK)
+ MXC_DCD_ITEM(0x020e075c, ODT_MASK)
+ MXC_DCD_ITEM(0x020e0760, ODT_MASK)
+ MXC_DCD_ITEM(0x020e0764, ODT_MASK)
+ MXC_DCD_ITEM(0x020e076c, ODT_MASK)
+ MXC_DCD_ITEM(0x020e0778, ODT_MASK)
+ MXC_DCD_ITEM(0x020e077c, ODT_MASK)
+ MXC_DCD_ITEM(0x020e0780, ODT_MASK)
+#endif
+ /* SDRAM initialization */
+#if 1
+ /* MPRDDQBY[0..7]DL */
+ MXC_DCD_ITEM(0x021b081c, 0x33333333)
+ MXC_DCD_ITEM(0x021b481c, 0x33333333)
+ MXC_DCD_ITEM(0x021b0820, 0x33333333)
+ MXC_DCD_ITEM(0x021b4820, 0x33333333)
+ MXC_DCD_ITEM(0x021b0824, 0x33333333)
+ MXC_DCD_ITEM(0x021b4824, 0x33333333)
+ MXC_DCD_ITEM(0x021b0828, 0x33333333)
+ MXC_DCD_ITEM(0x021b4828, 0x33333333)
+#endif
+MDMISC: /* MDMISC */
+ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL) ;@ 0x00081740
+MSDSCR: /* MSDSCR Conf Req */
+ MXC_DCD_ITEM(0x021b001c, 0x00008000)
+con_ack:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x021b001c, 0x00004000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
+MDCFG0: /* MDCFG0 */
+ MXC_DCD_ITEM(0x021b000c, MDCFG0_VAL) ;@ 0x555a7975
+MDCFG1: /* MDCFG1 */
+ MXC_DCD_ITEM(0x021b0010, MDCFG1_VAL) ;@ 0xff538e64
+MDCFG2: /* MDCFG2 */
+ MXC_DCD_ITEM(0x021b0014, MDCFG2_VAL) ;@ 0x01ff00db
+MDRWD: /* MDRWD */
+ MXC_DCD_ITEM(0x021b002c, 0x000026d2)
+MDOR: /* MDOR */
+ MXC_DCD_ITEM(0x021b0030, MDOR_VAL) ;@ 0x005b0e21
+MDOTC: /* MDOTC */
+ MXC_DCD_ITEM(0x021b0008, MDOTC_VAL) ;@ 0x09444040
+MDPDC: /* MDPDC */
+ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_1) ;@ 0x00025576
+ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_0) ;@ 0x00025576
+MDASP: /* MDASP */
+ MXC_DCD_ITEM(0x021b0040, 0x00000027)
+MDCTL: /* MDCTL */
+ MXC_DCD_ITEM(0x021b0000, MDCTL_VAL);@ 0x831a0000
+ddr_calib:
+ /* CS0 MRS: */
+MR2: /* MR2 */
+ MXC_DCD_ITEM(0x021b001c, 0x04088032)
+MR3: /* MR3 */
+ MXC_DCD_ITEM(0x021b001c, 0x00008033)
+MR1: /* MR1 */
+ MXC_DCD_ITEM(0x021b001c, 0x00048031)
+MR0: /* MR0 */
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(0)) ;@ 0x09408030
+#if BANK_ADDR_BITS > 1
+ /* CS1 MRS: MR2 */
+ MXC_DCD_ITEM(0x021b001c, 0x0408803a)
+ MXC_DCD_ITEM(0x021b001c, 0x0000803b)
+ MXC_DCD_ITEM(0x021b001c, 0x00408039)
+ MXC_DCD_ITEM(0x021b001c, MDSCR_MRS_VAL(1)) ;@ 0x09408038
+#endif
+MDREF: /* MDREF */
+ MXC_DCD_ITEM(0x021b0020, 0x00005800)
+MPODTCTRL: /* MPODTCTRL */
+#if 0
+ MXC_DCD_ITEM(0x021b0818, 0x00011112) ;@ 0x00000007
+ MXC_DCD_ITEM(0x021b4818, 0x00011112) ;@ 0x00000007
+#else
+ MXC_DCD_ITEM(0x021b0818, 0x00000007)
+ MXC_DCD_ITEM(0x021b4818, 0x00000007)
+#endif
+ MXC_DCD_ITEM(0x021b0890, 0x00000003) /* select default compare pattern for DQ calibration */
+
+ /* ZQ calibration */
+ MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */
+ MXC_DCD_ITEM(0x021b001c, 0x00008040) /* MRS: ZQ calibration */
+
+ MXC_DCD_ITEM(0x021b0800, 0xa1390003)
+zq_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0800, 0x00010000)
+#if 1
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
+ MXC_DCD_ITEM(0x021b001c, 0x00048033) /* MRS: select MPR */
+ MXC_DCD_ITEM(0x021b001c, 0x00c08231) /* MRS: start write leveling */
+
+ MXC_DCD_ITEM(0x021b001c, 0x00000000)
+ MXC_DCD_ITEM(0x021b0808, 0x00000001) /* initiate Write leveling */
+ MXC_DCD_ITEM(0x021b4808, 0x00000001)
+wl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00000001)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0808, 0x00f00000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00000001)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4808, 0x00f00000)
+#endif
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
+ MXC_DCD_ITEM(0x021b001c, 0x00048031) /* MRS: end write leveling */
+ MXC_DCD_ITEM(0x021b001c, 0x00008033) /* MRS: select normal data path */
+
+ /* DQS gating calibration */
+ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL | (3 << 16) | (3 << 9)) ;@ 0x00081740
+#if 1
+ MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */
+ MXC_DCD_ITEM(0x021b001c, 0x00048033) /* MRS: select MPR */
+#if 1
+ MXC_DCD_ITEM(0x021b0848, 0x47424140) /* DQ Delay default values */
+ MXC_DCD_ITEM(0x021b4848, 0x41414047)
+#endif
+ MXC_DCD_ITEM(0x021b083c, 0x90000000) /* reset RD fifo and start DQS calib. */
+ MXC_DCD_ITEM(0x021b483c, 0x90000000)
+dqs_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b083c, 0x90000000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b483c, 0x90000000)
+#endif
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
+ MXC_DCD_ITEM(0x021b001c, 0x00008033) /* MRS: select normal data path */
+
+ MXC_DCD_ITEM(0x021b001c, 0x00000000)
+ MXC_DCD_ITEM(0x021b0018, MDMISC_VAL) ;@ 0x00081740
+
+ /* Read delay calibration */
+ MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */
+ MXC_DCD_ITEM(0x021b001c, 0x00048033) /* MRS: select MPR */
+#define DO_CALIB
+#ifdef DO_CALIB
+ MXC_DCD_ITEM(0x021b0860, 0x00000010) /* MPRDDLHWCTL: HW_RD_DL_EN */
+ MXC_DCD_ITEM(0x021b4860, 0x00000010)
+#endif
+rd_dl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0860, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4860, 0x00000010)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
+ MXC_DCD_ITEM(0x021b001c, 0x00008033) /* MRS: select normal data path */
+
+ /* Write Delay calibration */
+ MXC_DCD_ITEM(0x021b001c, 0x04008010) /* precharge all */
+ MXC_DCD_ITEM(0x021b001c, 0x00048033) /* MRS: select MPR */
+#ifdef DO_CALIB
+ MXC_DCD_ITEM(0x021b0864, 0x00000010)
+ MXC_DCD_ITEM(0x021b4864, 0x00000010)
+#endif
+wr_dl_calib:
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b0864, 0x00000010)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x021b4864, 0x00000010)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end)
+ MXC_DCD_ITEM(0x021b001c, 0x00008033) /* MRS: select normal data path */
+
+ /* MDSCR: Normal operation */
+ MXC_DCD_ITEM(0x021b001c, 0x00000000)
+#if 0
+ MXC_DCD_ITEM(0x021b0868, 0x00000000)
+ MXC_DCD_ITEM(0x021b086c, 0x00000000)
+ MXC_DCD_ITEM(0x021b4868, 0x00000000)
+ MXC_DCD_ITEM(0x021b486c, 0x00000000)
+@ MXC_DCD_ITEM(0x021b0844, 0x1f251f21)
+ MXC_DCD_ITEM(0x021b0898, 0x4ffa481a)
+ MXC_DCD_ITEM(0x021b089c, 0x4ffa481a)
+ MXC_DCD_ITEM(0x021b4898, 0x4ffa481a)
+ MXC_DCD_ITEM(0x021b489c, 0x4ffa481a)
+#endif
+MAPSR: /* MAPSR */
+ MXC_DCD_ITEM(0x021b0404, 0x00011006)
+ MXC_DCD_ITEM(0x021b0004, MDPDC_VAL_1) ;@ 0x00025576
+#if 1
+ MXC_DCD_ITEM(0x021b083c, 0x034b0350) /* DG_DL_ABS_OFFS[0..1] */
+ MXC_DCD_ITEM(0x021b483c, 0x034b0350)
+ MXC_DCD_ITEM(0x021b0840, 0x034c0359) /* DG_DL_ABS_OFFS[2..3] */
+ MXC_DCD_ITEM(0x021b4840, 0x03650348)
+#endif
+#if 0
+bogus_ram_access:
+ MXC_DCD_ITEM(0x12345678, 0x12345678)
+#endif
+dcd_end:
+ .ifgt dcd_end - dcd_start - 1768
+ DCD too large!
+ .endif
--- /dev/null
+#define MMDC_MDCTL 0x0000
+#define MMDC_MDPDC 0x0004
+#define MMDC_MDOTC 0x0008
+#define MMDC_MDCFG0 0x000C
+#define MMDC_MDCFG1 0x0010
+#define MMDC_MDCFG2 0x0014
+#define MMDC_MDMISC 0x0018
+#define MMDC_MDSCR 0x001C
+#define MMDC_MDREF 0x0020
+#define MMDC_MDRWD 0x002C
+#define MMDC_MDOR 0x0030
+#define MMDC_MDMRR 0x0034
+#define MMDC_MDCFG3LP 0x0038
+#define MMDC_MDMR4 0x003C
+#define MMDC_MDASP 0x0040
+#define MMDC_MAARCR 0x0400
+#define MMDC_MAPSR 0x0404
+#define MMDC_MAEXIDR0 0x0408
+#define MMDC_MAEXIDR1 0x040C
+#define MMDC_MADPCR0 0x0410
+#define MMDC_MADPCR1 0x0414
+#define MMDC_MADPSR0 0x0418
+#define MMDC_MADPSR1 0x041C
+#define MMDC_MADPSR2 0x0420
+#define MMDC_MADPSR3 0x0424
+#define MMDC_MADPSR4 0x0428
+#define MMDC_MADPSR5 0x042C
+#define MMDC_MASBS0 0x0430
+#define MMDC_MASBS1 0x0434
+#define MMDC_MAGENP 0x0440
+#define MMDC_MPZQHWCTRL 0x0800
+#define MMDC_MPZQSWCTRL 0x0804
+#define MMDC_MPWLGCR 0x0808
+#define MMDC_MPWLDECTRL0 0x080C
+#define MMDC_MPWLDECTRL1 0x0810
+#define MMDC_MPWLDLST 0x0814
+#define MMDC_MPODTCTRL 0x0818
+#define MMDC_MPRDDQBY0DL 0x081C
+#define MMDC_MPRDDQBY1DL 0x0820
+#define MMDC_MPRDDQBY2DL 0x0824
+#define MMDC_MPRDDQBY3DL 0x0828
+#define MMDC_MPWRDQBY0DL 0x082C
+#define MMDC_MPWRDQBY1DL 0x0830
+#define MMDC_MPWRDQBY2DL 0x0834
+#define MMDC_MPWRDQBY3DL 0x0838
+#define MMDC_MPDGCTRL0 0x083C
+#define MMDC_MPDGCTRL1 0x0840
+#define MMDC_MPDGDLST0 0x0844
+#define MMDC_MPRDDLCTL 0x0848
+#define MMDC_MPRDDLST 0x084C
+#define MMDC_MPWRDLCTL 0x0850
+#define MMDC_MPWRDLST 0x0854
+#define MMDC_MPSDCTRL 0x0858
+#define MMDC_MPZQLP2CTL 0x085C
+#define MMDC_MPRDDLHWCTL 0x0860
+#define MMDC_MPWRDLHWCTL 0x0864
+#define MMDC_MPRDDLHWST0 0x0868
+#define MMDC_MPRDDLHWST1 0x086C
+#define MMDC_MPWRDLHWST0 0x0870
+#define MMDC_MPWRDLHWST1 0x0874
+#define MMDC_MPWLHWERR 0x0878
+#define MMDC_MPDGHWST0 0x087C
+#define MMDC_MPDGHWST1 0x0880
+#define MMDC_MPDGHWST2 0x0884
+#define MMDC_MPDGHWST3 0x0888
+#define MMDC_MPPDCMPR1 0x088C
+#define MMDC_MPPDCMPR2 0x0890
+#define MMDC_MPSWDAR0 0x0894
+#define MMDC_MPSWDRDR0 0x0898
+#define MMDC_MPSWDRDR1 0x089C
+#define MMDC_MPSWDRDR2 0x08A0
+#define MMDC_MPSWDRDR3 0x08A4
+#define MMDC_MPSWDRDR4 0x08A8
+#define MMDC_MPSWDRDR5 0x08AC
+#define MMDC_MPSWDRDR6 0x08B0
+#define MMDC_MPSWDRDR7 0x08B4
+#define MMDC_MPMUR0 0x08B8
+#define MMDC_MPWRCADL 0x08BC
+#define MMDC_MPDCCR 0x08C0
--- /dev/null
+/*
+ * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx6.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_LED MX6_PAD_CTL_DSE_80ohm
+#define MUX_CONFIG_LCD (MX6_PAD_CTL_SPEED_HIGH | MX6_PAD_CTL_SRE_FAST | \
+ MX6_PAD_CTL_DSE_80ohm)
+#define MUX_CONFIG_TSC (MX6_PAD_CTL_SRE_FAST | MX6_PAD_CTL_DSE_80ohm | \
+ MX6_PAD_CTL_PUS_47K_UP)
+#define MUX_CONFIG_GPMI MX6_PAD_CTL_DSE_80ohm
+#define MUX_CONFIG_EMI MX6Q_HIGH_DRV
+#define MUX_CONFIG_GPIO MX6_PAD_CTL_PUS_47K_UP
+
+static iomux_v3_cfg_t tx6q_stk5_pads[] = {
+ /* LED */
+ MX6Q_PAD_EIM_A18__GPIO_2_20,
+
+ /* framebuffer */
+ MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
+ MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
+ MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
+ MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
+ MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
+ MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
+ MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
+ MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
+ MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
+ MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
+ MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
+ MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
+ MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
+ MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
+ MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
+ MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
+ MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
+ MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
+ MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
+ MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
+ MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
+ MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
+ MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
+ MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
+ MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* LCD VSYNC */
+ MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* LCD HSYNC */
+ MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LCD DOTCLK */
+ MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* LCD OE/ACD */
+
+ /* UART1 pads */
+ MX6Q_PAD_SD3_DAT7__UART1_TXD,
+ MX6Q_PAD_SD3_DAT6__UART1_RXD,
+ MX6Q_PAD_SD3_DAT1__UART1_RTS,
+ MX6Q_PAD_SD3_DAT0__UART1_CTS,
+
+ /* EMI */
+ MX6_PAD_EMI_D00__EMI_DATA0,
+ MX6_PAD_EMI_D01__EMI_DATA1,
+ MX6_PAD_EMI_D02__EMI_DATA2,
+ MX6_PAD_EMI_D03__EMI_DATA3,
+ MX6_PAD_EMI_D04__EMI_DATA4,
+ MX6_PAD_EMI_D05__EMI_DATA5,
+ MX6_PAD_EMI_D06__EMI_DATA6,
+ MX6_PAD_EMI_D07__EMI_DATA7,
+ MX6_PAD_EMI_D08__EMI_DATA8,
+ MX6_PAD_EMI_D09__EMI_DATA9,
+ MX6_PAD_EMI_D10__EMI_DATA10,
+ MX6_PAD_EMI_D11__EMI_DATA11,
+ MX6_PAD_EMI_D12__EMI_DATA12,
+ MX6_PAD_EMI_D13__EMI_DATA13,
+ MX6_PAD_EMI_D14__EMI_DATA14,
+ MX6_PAD_EMI_D15__EMI_DATA15,
+ MX6_PAD_EMI_ODT0__EMI_ODT0,
+ MX6_PAD_EMI_DQM0__EMI_DQM0,
+ MX6_PAD_EMI_ODT1__EMI_ODT1,
+ MX6_PAD_EMI_DQM1__EMI_DQM1,
+ MX6_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK,
+ MX6_PAD_EMI_CLK__EMI_CLK,
+ MX6_PAD_EMI_DQS0__EMI_DQS0,
+ MX6_PAD_EMI_DQS1__EMI_DQS1,
+ MX6_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN,
+
+ MX6_PAD_EMI_A00__EMI_ADDR0,
+ MX6_PAD_EMI_A01__EMI_ADDR1,
+ MX6_PAD_EMI_A02__EMI_ADDR2,
+ MX6_PAD_EMI_A03__EMI_ADDR3,
+ MX6_PAD_EMI_A04__EMI_ADDR4,
+ MX6_PAD_EMI_A05__EMI_ADDR5,
+ MX6_PAD_EMI_A06__EMI_ADDR6,
+ MX6_PAD_EMI_A07__EMI_ADDR7,
+ MX6_PAD_EMI_A08__EMI_ADDR8,
+ MX6_PAD_EMI_A09__EMI_ADDR9,
+ MX6_PAD_EMI_A10__EMI_ADDR10,
+ MX6_PAD_EMI_A11__EMI_ADDR11,
+ MX6_PAD_EMI_A12__EMI_ADDR12,
+ MX6_PAD_EMI_A13__EMI_ADDR13,
+ MX6_PAD_EMI_A14__EMI_ADDR14,
+ MX6_PAD_EMI_BA0__EMI_BA0,
+ MX6_PAD_EMI_BA1__EMI_BA1,
+ MX6_PAD_EMI_BA2__EMI_BA2,
+ MX6_PAD_EMI_CASN__EMI_CASN,
+ MX6_PAD_EMI_RASN__EMI_RASN,
+ MX6_PAD_EMI_WEN__EMI_WEN,
+ MX6_PAD_EMI_CE0N__EMI_CE0N,
+ MX6_PAD_EMI_CE1N__EMI_CE1N,
+ MX6_PAD_EMI_CKE__EMI_CKE,
+
+ /* FEC pads */
+ MX6_PAD_PWM4__GPIO_3_29,
+ MX6_PAD_ENET0_RX_CLK__GPIO_4_13,
+ MX6_PAD_ENET0_MDC__ENET0_MDC,
+ MX6_PAD_ENET0_MDIO__ENET0_MDIO,
+ MX6_PAD_ENET0_RX_EN__GPIO_4_2, /* COL/CRS_DV/MODE2 */
+ MX6_PAD_ENET0_RXD0__GPIO_4_3, /* RXD0/MODE0 */
+ MX6_PAD_ENET0_RXD1__GPIO_4_4, /* RXD1/MODE1 */
+ MX6_PAD_ENET0_TX_CLK__GPIO_4_5, /* nINT/TX_ER/TXD4 */
+ MX6_PAD_ENET0_TX_EN__ENET0_TX_EN,
+ MX6_PAD_ENET0_TXD0__ENET0_TXD0,
+ MX6_PAD_ENET0_TXD1__ENET0_TXD1,
+ MX6_PAD_ENET_CLK__CLKCTRL_ENET,
+
+ /* MMC pads */
+ MX6_PAD_SSP0_DATA0__SSP0_D0,
+ MX6_PAD_SSP0_DATA1__SSP0_D1,
+ MX6_PAD_SSP0_DATA2__SSP0_D2,
+ MX6_PAD_SSP0_DATA3__SSP0_D3,
+ MX6_PAD_SSP0_CMD__SSP0_CMD,
+ MX6_PAD_SSP0_DETECT__SSP0_CARD_DETECT,
+ MX6_PAD_SSP0_SCK__SSP0_SCK,
+
+ /* GPMI pads */
+ MX6_PAD_GPMI_D00__GPMI_D0,
+ MX6_PAD_GPMI_D01__GPMI_D1,
+ MX6_PAD_GPMI_D02__GPMI_D2,
+ MX6_PAD_GPMI_D03__GPMI_D3,
+ MX6_PAD_GPMI_D04__GPMI_D4,
+ MX6_PAD_GPMI_D05__GPMI_D5,
+ MX6_PAD_GPMI_D06__GPMI_D6,
+ MX6_PAD_GPMI_D07__GPMI_D7,
+ MX6_PAD_GPMI_CE0N__GPMI_CE0N,
+ MX6_PAD_GPMI_RDY0__GPMI_READY0,
+ MX6_PAD_GPMI_RDN__GPMI_RDN,
+ MX6_PAD_GPMI_WRN__GPMI_WRN,
+ MX6_PAD_GPMI_ALE__GPMI_ALE,
+ MX6_PAD_GPMI_CLE__GPMI_CLE,
+ MX6_PAD_GPMI_RESETN__GPMI_RESETN,
+
+ /* maybe used for EDT-FT5x06 */
+ MX6_PAD_SSP0_DATA5__GPIO_2_5,
+ MX6_PAD_SSP0_DATA6__GPIO_2_6,
+ MX6_PAD_ENET0_RXD2__GPIO_4_9,
+
+ /* unused pads */
+ MX6_PAD_GPMI_RDY1__GPIO_0_21,
+ MX6_PAD_GPMI_RDY2__GPIO_0_22,
+ MX6_PAD_GPMI_RDY3__GPIO_0_23,
+ MX6_PAD_GPMI_CE1N__GPIO_0_17,
+ MX6_PAD_GPMI_CE2N__GPIO_0_18,
+ MX6_PAD_GPMI_CE3N__GPIO_0_19,
+
+ MX6_PAD_SSP0_DATA4__GPIO_2_4,
+ MX6_PAD_SSP0_DATA7__GPIO_2_7,
+
+ MX6_PAD_SSP2_SS0__GPIO_2_19,
+ MX6_PAD_SSP2_SS1__GPIO_2_20,
+ MX6_PAD_SSP2_SS2__GPIO_2_21,
+ MX6_PAD_SSP3_SS0__GPIO_2_27,
+
+ MX6_PAD_ENET0_TXD2__GPIO_4_11,
+ MX6_PAD_ENET0_TXD3__GPIO_4_12,
+ MX6_PAD_ENET0_CRS__GPIO_4_15,
+};
+
+static void tx6q_stk5_lcd_init(void)
+{
+ gpio_direction_output(MX6_PAD_PWM0__GPIO_3_16, 1);
+ gpio_direction_output(MX6_PAD_LCD_RESET__GPIO_3_30, 0);
+ gpio_direction_output(MX6_PAD_LCD_ENABLE__GPIO_1_31, 0);
+}
+
+static void tx6q_stk5_led_on(void)
+{
+ gpio_direction_output(MX6Q_PAD_EIM_A18__GPIO_2_20, 1);
+}
+
+void board_init_ll(void)
+{
+ mx6_common_spl_init(tx6q_stk5_pads, ARRAY_SIZE(tx6q_stk5_pads));
+ tx6q_stk5_lcd_init();
+ tx6q_stk5_led_on();
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+//#define DEBUG
+//#define TIMER_TEST
+
+#include <common.h>
+#include <errno.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <lcd.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <video_fb.h>
+#include <ipu.h>
+#include <mx2fb.h>
+#include <linux/fb.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx6.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+
+#include "../common/karo.h"
+
+#define TX6Q_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
+#define TX6Q_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
+#define TX6Q_FEC_INT_GPIO IMX_GPIO_NR(2, 4)
+#define TX6Q_LED_GPIO IMX_GPIO_NR(2, 20)
+
+#define TX6Q_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
+#define TX6Q_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
+#define TX6Q_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
+
+#define TX6Q_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
+
+#define TEMPERATURE_MIN -40
+#define TEMPERATURE_HOT 80
+#define TEMPERATURE_MAX 125
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
+
+static const iomux_v3_cfg_t tx6q_pads[] = {
+ /* NAND flash pads */
+ MX6Q_PAD_NANDF_CLE__RAWNAND_CLE,
+ MX6Q_PAD_NANDF_ALE__RAWNAND_ALE,
+ MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN,
+ MX6Q_PAD_NANDF_RB0__RAWNAND_READY0,
+ MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N,
+ MX6Q_PAD_SD4_CMD__RAWNAND_RDN,
+ MX6Q_PAD_SD4_CLK__RAWNAND_WRN,
+ MX6Q_PAD_NANDF_D0__RAWNAND_D0,
+ MX6Q_PAD_NANDF_D1__RAWNAND_D1,
+ MX6Q_PAD_NANDF_D2__RAWNAND_D2,
+ MX6Q_PAD_NANDF_D3__RAWNAND_D3,
+ MX6Q_PAD_NANDF_D4__RAWNAND_D4,
+ MX6Q_PAD_NANDF_D5__RAWNAND_D5,
+ MX6Q_PAD_NANDF_D6__RAWNAND_D6,
+ MX6Q_PAD_NANDF_D7__RAWNAND_D7,
+
+ /* RESET_OUT */
+ MX6Q_PAD_GPIO_17__GPIO_7_12,
+
+ /* UART pads */
+#if CONFIG_MXC_UART_BASE == UART1_BASE
+ MX6Q_PAD_SD3_DAT7__UART1_TXD,
+ MX6Q_PAD_SD3_DAT6__UART1_RXD,
+ MX6Q_PAD_SD3_DAT1__UART1_RTS,
+ MX6Q_PAD_SD3_DAT0__UART1_CTS,
+#endif
+#if CONFIG_MXC_UART_BASE == UART2_BASE
+ MX6Q_PAD_SD4_DAT4__UART2_RXD,
+ MX6Q_PAD_SD4_DAT7__UART2_TXD,
+ MX6Q_PAD_SD4_DAT5__UART2_RTS,
+ MX6Q_PAD_SD4_DAT6__UART2_CTS,
+#endif
+#if CONFIG_MXC_UART_BASE == UART3_BASE
+ MX6Q_PAD_EIM_D24__UART3_TXD,
+ MX6Q_PAD_EIM_D25__UART3_RXD,
+ MX6Q_PAD_SD3_RST__UART3_RTS,
+ MX6Q_PAD_SD3_DAT3__UART3_CTS,
+#endif
+ /* internal I2C */
+ MX6Q_PAD_EIM_D28__I2C1_SDA,
+ MX6Q_PAD_EIM_D21__I2C1_SCL,
+
+ /* FEC PHY GPIO functions */
+ MX6Q_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
+ MX6Q_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
+ MX6Q_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
+};
+
+static const iomux_v3_cfg_t tx6q_fec_pads[] = {
+ /* FEC functions */
+ MX6Q_PAD_ENET_MDC__ENET_MDC,
+ MX6Q_PAD_ENET_MDIO__ENET_MDIO,
+ MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
+ MX6Q_PAD_ENET_RX_ER__ENET_RX_ER,
+ MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN,
+ MX6Q_PAD_ENET_RXD1__ENET_RDATA_1,
+ MX6Q_PAD_ENET_RXD0__ENET_RDATA_0,
+ MX6Q_PAD_ENET_TX_EN__ENET_TX_EN,
+ MX6Q_PAD_ENET_TXD1__ENET_TDATA_1,
+ MX6Q_PAD_ENET_TXD0__ENET_TDATA_0,
+};
+
+static const struct gpio tx6q_gpios[] = {
+ { TX6Q_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
+ { TX6Q_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
+ { TX6Q_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
+ { TX6Q_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
+};
+
+/*
+ * Functions
+ */
+/* placed in section '.data' to prevent overwriting relocation info
+ * overlayed with bss
+ */
+static u32 wrsr __attribute__((section(".data")));
+
+#define WRSR_POR (1 << 4)
+#define WRSR_TOUT (1 << 1)
+#define WRSR_SFTW (1 << 0)
+
+static void print_reset_cause(void)
+{
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
+ u32 srsr;
+ char *dlm = "";
+
+ printf("Reset cause: ");
+
+ srsr = readl(&src_regs->srsr);
+ wrsr = readw(wdt_base + 4);
+
+ if (wrsr & WRSR_POR) {
+ printf("%sPOR", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00004) {
+ printf("%sCSU", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00008) {
+ printf("%sIPP USER", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00010) {
+ if (wrsr & WRSR_SFTW) {
+ printf("%sSOFT", dlm);
+ dlm = " | ";
+ }
+ if (wrsr & WRSR_TOUT) {
+ printf("%sWDOG", dlm);
+ dlm = " | ";
+ }
+ }
+ if (srsr & 0x00020) {
+ printf("%sJTAG HIGH-Z", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x00040) {
+ printf("%sJTAG SW", dlm);
+ dlm = " | ";
+ }
+ if (srsr & 0x10000) {
+ printf("%sWARM BOOT", dlm);
+ dlm = " | ";
+ }
+ if (dlm[0] == '\0')
+ printf("unknown");
+
+ printf("\n");
+}
+
+int read_cpu_temperature(void);
+int check_cpu_temperature(int boot);
+
+static void print_cpuinfo(void)
+{
+ u32 cpurev;
+
+ cpurev = get_cpu_rev();
+
+ printf("CPU: Freescale i.MX6Q rev%d.%d at %d MHz\n",
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+
+ print_reset_cause();
+ check_cpu_temperature(1);
+}
+
+#define LTC3676_DVB2A 0x0C
+#define LTC3676_DVB2B 0x0D
+#define LTC3676_DVB4A 0x10
+#define LTC3676_DVB4B 0x11
+
+#define VDD_SOC_mV (1375 + 50)
+#define VDD_CORE_mV (1375 + 50)
+
+#define mV_to_regval(mV) (((mV) * 360 / 330 - 825 + 1) / 25)
+#define regval_to_mV(v) (((v) * 25 + 825) * 330 / 360)
+
+static int setup_pmic_voltages(void)
+{
+ int ret;
+ unsigned char value;
+
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
+ if (ret != 0) {
+ printf("Failed to initialize I2C\n");
+ return ret;
+ }
+
+ ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
+ if (ret) {
+ printf("%s: i2c_read error: %d\n", __func__, ret);
+ return ret;
+ }
+
+ /* VDDCORE/VDDSOC default 1.375V is not enough, considering
+ pfuze tolerance and IR drop and ripple, need increase
+ to 1.425V for SabreSD */
+
+ value = 0x39; /* VB default value & PGOOD not forced when slewing */
+ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2B, 1, &value, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC DVB2B register: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4B, 1, &value, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC DVB4B register: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ value = mV_to_regval(VDD_SOC_mV);
+ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2A, 1, &value, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC DVB2A register: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ printf("VDDSOC set to %dmV\n", regval_to_mV(value));
+
+ value = mV_to_regval(VDD_CORE_mV);
+ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4A, 1, &value, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC DVB4A register: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ printf("VDDCORE set to %dmV\n", regval_to_mV(value));
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+#if 0
+ writel(0xffffffff, 0x020c4068); /* CCGR0 */
+ writel(0xffffffff, 0x020c406c); /* CCGR1 */
+ writel(0xffffffff, 0x020c4070); /* CCGR2 */
+ writel(0xffffffff, 0x020c4074); /* CCGR3 */
+ writel(0xffffffff, 0x020c4078); /* CCGR4 */
+ writel(0xffffffff, 0x020c407c); /* CCGR5 */
+ writel(0xffffffff, 0x020c4080); /* CCGR6 */
+ writel(0xffffffff, 0x020c4084); /* CCGR7 */
+#endif
+#if 0
+ writel(0x00000000, 0x020e02d4); /* NANDF_CLE: NANDF_CLE */
+ writel(0x00000000, 0x020e02d8); /* NANDF_ALE: NANDF_ALE */
+ writel(0x00000000, 0x020e02dc); /* NANDF_WP_B: NANDF_WPn */
+ writel(0x00000000, 0x020e02e0); /* NANDF_RB0: NANDF_READY0 */
+ writel(0x00000000, 0x020e02e4); /* NANDF_CS0: NANDF_CS0 */
+ writel(0x00000001, 0x020e02f4); /* SD4_CMD: NANDF_RDn */
+ writel(0x00000001, 0x020e02f8); /* SD4_CLK: NANDF_WRn */
+
+ writel(0x00000000, 0x020e02fc); /* NANDF_D0: NANDF_D0 */
+ writel(0x00000000, 0x020e0300); /* NANDF_D1: NANDF_D1 */
+ writel(0x00000000, 0x020e0304); /* NANDF_D2: NANDF_D2 */
+ writel(0x00000000, 0x020e0308); /* NANDF_D3: NANDF_D3 */
+ writel(0x00000000, 0x020e030c); /* NANDF_D4: NANDF_D4 */
+ writel(0x00000000, 0x020e0310); /* NANDF_D5: NANDF_D5 */
+ writel(0x00000000, 0x020e0314); /* NANDF_D6: NANDF_D6 */
+ writel(0x00000000, 0x020e0318); /* NANDF_D7: NANDF_D7 */
+#endif
+ gpio_request_array(tx6q_gpios, ARRAY_SIZE(tx6q_gpios));
+ imx_iomux_v3_setup_multiple_pads(tx6q_pads, ARRAY_SIZE(tx6q_pads));
+
+#if 0
+ int ret;
+ ret = setup_pmic_voltages();
+ if (ret) {
+ printf("Failed to setup PMIC voltages\n");
+// hang();
+ }
+#endif
+ return 0;
+}
+
+int board_init(void)
+{
+ int ret;
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
+#if 1
+ gd->bd->bi_arch_number = 4429;
+#endif
+ ret = setup_pmic_voltages();
+ if (ret) {
+ printf("Failed to setup PMIC voltages\n");
+// hang();
+ }
+ return 0;
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+#if CONFIG_NR_DRAM_BANKS > 1
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
+ PHYS_SDRAM_2_SIZE);
+#endif
+}
+
+#ifdef CONFIG_CMD_MMC
+static const iomux_v3_cfg_t mmc0_pads[] = {
+ MX6Q_PAD_SD1_CMD__USDHC1_CMD,
+ MX6Q_PAD_SD1_CLK__USDHC1_CLK,
+ MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
+ MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
+ MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
+ MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
+ /* SD1 CD */
+ MX6Q_PAD_SD3_CMD__GPIO_7_2,
+};
+
+static const iomux_v3_cfg_t mmc1_pads[] = {
+ MX6Q_PAD_SD2_CMD__USDHC2_CMD,
+ MX6Q_PAD_SD2_CLK__USDHC2_CLK,
+ MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
+ MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
+ MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
+ MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
+ /* SD2 CD */
+ MX6Q_PAD_SD3_CLK__GPIO_7_3,
+};
+
+static struct tx6q_esdhc_cfg {
+ const iomux_v3_cfg_t *pads;
+ int num_pads;
+ enum mxc_clock clkid;
+ struct fsl_esdhc_cfg cfg;
+} tx6q_esdhc_cfg[] = {
+ {
+ .pads = mmc0_pads,
+ .num_pads = ARRAY_SIZE(mmc0_pads),
+ .clkid = MXC_ESDHC_CLK,
+ .cfg = {
+ .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
+ .cd_gpio = IMX_GPIO_NR(7, 2),
+ .wp_gpio = -EINVAL,
+ },
+ },
+ {
+ .pads = mmc1_pads,
+ .num_pads = ARRAY_SIZE(mmc1_pads),
+ .clkid = MXC_ESDHC2_CLK,
+ .cfg = {
+ .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
+ .cd_gpio = IMX_GPIO_NR(7, 3),
+ .wp_gpio = -EINVAL,
+ },
+ },
+};
+
+static inline struct tx6q_esdhc_cfg *to_tx6q_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
+{
+ void *p = cfg;
+
+ return p - offsetof(struct tx6q_esdhc_cfg, cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = mmc->priv;
+
+ if (cfg->cd_gpio < 0)
+ return cfg->cd_gpio;
+
+ debug("SD card %d is %spresent\n",
+ to_tx6q_esdhc_cfg(cfg) - tx6q_esdhc_cfg, gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
+ return !gpio_get_value(cfg->cd_gpio);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(tx6q_esdhc_cfg); i++) {
+ struct mmc *mmc;
+ struct fsl_esdhc_cfg *cfg = &tx6q_esdhc_cfg[i].cfg;
+
+ if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
+ break;
+
+ cfg->sdhc_clk = mxc_get_clock(tx6q_esdhc_cfg[i].clkid);
+ imx_iomux_v3_setup_multiple_pads(tx6q_esdhc_cfg[i].pads,
+ tx6q_esdhc_cfg[i].num_pads);
+
+ debug("%s: Initializing MMC slot %d\n", __func__, i);
+ fsl_esdhc_initialize(bis, cfg);
+
+ mmc = find_mmc_device(i);
+ if (mmc == NULL)
+ continue;
+ if (board_mmc_getcd(mmc) > 0)
+ mmc_init(mmc);
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_MMC */
+
+#ifdef CONFIG_FEC_MXC
+
+#define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_SRE_FAST)
+#define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
+#define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
+
+#ifndef ETH_ALEN
+#define ETH_ALEN 6
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+#if 0
+ unsigned char mac[ETH_ALEN];
+ char mac_str[ETH_ALEN * 3] = "";
+#endif
+ /* delay at least 21ms for the PHY internal POR signal to deassert */
+ udelay(22000);
+
+ imx_iomux_v3_setup_multiple_pads(tx6q_fec_pads, ARRAY_SIZE(tx6q_fec_pads));
+#if 0
+ printf("RXD0(MODE0)=%d\n", gpio_get_value(IMX_GPIO_NR(1, 27)));
+ printf("RXD1(MODE1)=%d\n", gpio_get_value(IMX_GPIO_NR(1, 26)));
+ printf("CRS_DV(MODE2)=%d\n", gpio_get_value(IMX_GPIO_NR(1, 25)));
+
+ printf("RX_ER(PHYAD0)=%d\n", gpio_get_value(IMX_GPIO_NR(1, 24)));
+
+ printf("GPIO7[6](FEC RESET)=%d\n", gpio_get_value(IMX_GPIO_NR(7, 6)));
+ printf("GPIO3[20](FEC PWR)=%d\n", gpio_get_value(IMX_GPIO_NR(3, 20)));
+#endif
+
+ /* Deassert RESET to the external phy */
+ gpio_set_value(TX6Q_FEC_RST_GPIO, 1);
+
+ ret = cpu_eth_init(bis);
+ if (ret) {
+ printf("cpu_eth_init() failed: %d\n", ret);
+ return ret;
+ }
+#if 0
+ imx_get_mac_from_fuse(-1, mac);
+ snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ setenv("ethaddr", mac_str);
+#endif
+ return ret;
+}
+#endif /* CONFIG_FEC_MXC */
+
+enum {
+ LED_STATE_INIT = -1,
+ LED_STATE_OFF,
+ LED_STATE_ON,
+};
+
+static inline int calc_blink_rate(int tmp)
+{
+ return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
+ (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
+ (TEMPERATURE_HOT - TEMPERATURE_MIN);
+}
+
+void show_activity(int arg)
+{
+ static int led_state = LED_STATE_INIT;
+ static int blink_rate;
+ static ulong last;
+
+ if (led_state == LED_STATE_INIT) {
+ last = get_timer(0);
+ gpio_set_value(TX6Q_LED_GPIO, 1);
+ led_state = LED_STATE_ON;
+ blink_rate = calc_blink_rate(check_cpu_temperature(0));
+ } else {
+ if (get_timer(last) > blink_rate) {
+ blink_rate = calc_blink_rate(check_cpu_temperature(0));
+ last = get_timer_masked();
+ if (led_state == LED_STATE_ON) {
+ gpio_set_value(TX6Q_LED_GPIO, 0);
+ } else {
+ gpio_set_value(TX6Q_LED_GPIO, 1);
+ }
+ led_state = 1 - led_state;
+ }
+ }
+}
+
+static const iomux_v3_cfg_t stk5_pads[] = {
+ /* SW controlled LED on STK5 baseboard */
+ MX6Q_PAD_EIM_A18__GPIO_2_20,
+
+ /* LCD data pins */
+ MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
+ MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
+ MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
+ MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
+ MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
+ MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
+ MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
+ MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
+ MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
+ MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
+ MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
+ MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
+ MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
+ MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
+ MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
+ MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
+ MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
+ MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
+ MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
+ MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
+ MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
+ MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
+ MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
+ MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
+ MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
+ MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
+ MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
+ MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
+
+ /* I2C bus on DIMM pins 40/41 */
+ MX6Q_PAD_GPIO_6__I2C3_SDA,
+ MX6Q_PAD_GPIO_3__I2C3_SCL,
+
+ /* TSC200x PEN IRQ */
+ MX6Q_PAD_EIM_D26__GPIO_3_26,
+
+ /* EDT-FT5x06 Polytouch panel */
+ MX6Q_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
+ MX6Q_PAD_EIM_A16__GPIO_2_22, /* RESET */
+ MX6Q_PAD_EIM_A17__GPIO_2_21, /* WAKE */
+
+ /* USBH1 */
+ MX6Q_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
+ MX6Q_PAD_EIM_D30__GPIO_3_30, /* OC */
+ /* USBOTG */
+ MX6Q_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
+ MX6Q_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
+ MX6Q_PAD_GPIO_8__GPIO_1_8, /* OC */
+
+ /* DEBUG */
+ MX6Q_PAD_GPIO_0__CCM_CLKO,
+ MX6Q_PAD_NANDF_CS2__CCM_CLKO2,
+};
+
+static const struct gpio stk5_gpios[] = {
+ { TX6Q_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
+
+ { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
+ { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
+ { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
+ { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
+ { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
+};
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ /* set to max. size supported by SoC */
+ .vl_col = 1920,
+ .vl_row = 1080,
+
+ .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+};
+
+static struct fb_videomode tx6q_fb_mode = {
+ /* Standard VGA timing */
+ .name = "VGA",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(25175),
+ .left_margin = 48,
+ .hsync_len = 96,
+ .right_margin = 16,
+ .upper_margin = 31,
+ .vsync_len = 2,
+ .lower_margin = 12,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
+static int lcd_enabled = 1;
+
+void lcd_enable(void)
+{
+ /* HACK ALERT:
+ * global variable from common/lcd.c
+ * Set to 0 here to prevent messages from going to LCD
+ * rather than serial console
+ */
+ lcd_is_enabled = 0;
+
+ karo_load_splashimage(1);
+ if (lcd_enabled) {
+ debug("Switching LCD on\n");
+ gpio_set_value(TX6Q_LCD_PWR_GPIO, 1);
+ udelay(100);
+ gpio_set_value(TX6Q_LCD_RST_GPIO, 1);
+ udelay(300000);
+ gpio_set_value(TX6Q_LCD_BACKLIGHT_GPIO, 0);
+ }
+}
+
+static const iomux_v3_cfg_t stk5_lcd_pads[] = {
+ /* LCD RESET */
+ MX6Q_PAD_EIM_D29__GPIO_3_29,
+ /* LCD POWER_ENABLE */
+ MX6Q_PAD_EIM_EB3__GPIO_2_31,
+ /* LCD Backlight (PWM) */
+ MX6Q_PAD_GPIO_1__GPIO_1_1,
+
+ /* Display */
+ MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+ MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,
+ MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,
+ MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,
+ MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
+ MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
+ MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
+ MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
+ MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
+ MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
+ MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
+ MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
+ MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
+ MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
+ MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
+ MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
+ MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
+ MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
+ MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
+ MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
+ MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
+ MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
+ MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
+ MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
+ MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
+ MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
+ MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
+ MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
+
+ /* LVDS option */
+ MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
+ MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
+ MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
+ MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
+ MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
+ MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
+ MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
+ MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
+ MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
+ MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
+};
+
+static const struct gpio stk5_lcd_gpios[] = {
+ { TX6Q_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
+ { TX6Q_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
+ { TX6Q_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+};
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ int color_depth = 24;
+ char *vm;
+ unsigned long val;
+ int refresh = 60;
+ struct fb_videomode *p = &tx6q_fb_mode;
+ int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
+ int pix_fmt = 0;
+ ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
+ unsigned long di_clk_rate = 65000000;
+
+ if (!lcd_enabled) {
+ debug("LCD disabled\n");
+ return;
+ }
+
+ if (tstc() || (wrsr & WRSR_TOUT)) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ return;
+ }
+
+ vm = getenv("video_mode");
+ if (vm == NULL) {
+ debug("Disabling LCD\n");
+ lcd_enabled = 0;
+ return;
+ }
+ while (*vm != '\0') {
+ if (*vm >= '0' && *vm <= '9') {
+ char *end;
+
+ val = simple_strtoul(vm, &end, 0);
+ if (end > vm) {
+ if (!xres_set) {
+ if (val > panel_info.vl_col)
+ val = panel_info.vl_col;
+ p->xres = val;
+ panel_info.vl_col = val;
+ xres_set = 1;
+ } else if (!yres_set) {
+ if (val > panel_info.vl_row)
+ val = panel_info.vl_row;
+ p->yres = val;
+ panel_info.vl_row = val;
+ yres_set = 1;
+ } else if (!bpp_set) {
+ switch (val) {
+ case 24:
+ if (pix_fmt == IPU_PIX_FMT_LVDS666)
+ pix_fmt = IPU_PIX_FMT_LVDS888;
+ /* fallthru */
+ case 16:
+ case 8:
+ color_depth = val;
+ break;
+
+ case 18:
+ if (pix_fmt == IPU_PIX_FMT_LVDS666) {
+ color_depth = val;
+ break;
+ }
+ /* fallthru */
+ default:
+ printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
+ end - vm, vm, color_depth);
+ }
+ bpp_set = 1;
+ } else if (!refresh_set) {
+ refresh = val;
+ refresh_set = 1;
+ }
+ }
+ vm = end;
+ }
+ switch (*vm) {
+ case '@':
+ bpp_set = 1;
+ /* fallthru */
+ case '-':
+ yres_set = 1;
+ /* fallthru */
+ case 'x':
+ xres_set = 1;
+ /* fallthru */
+ case 'M':
+ case 'R':
+ vm++;
+ break;
+
+ default:
+ if (!pix_fmt) {
+ char *tmp;
+
+ if (strncmp(vm, "LVDS", 4) == 0) {
+ pix_fmt = IPU_PIX_FMT_LVDS666;
+ di_clk_parent = DI_PCLK_LDB;
+ } else {
+ pix_fmt = IPU_PIX_FMT_RGB24;
+ }
+ tmp = strchr(vm, ':');
+ if (tmp)
+ vm = tmp;
+ }
+ if (*vm != '\0')
+ vm++;
+ }
+ }
+ switch (color_depth) {
+ case 8:
+ panel_info.vl_bpix = 3;
+ break;
+
+ case 16:
+ panel_info.vl_bpix = 4;
+ break;
+
+ case 18:
+ case 24:
+ panel_info.vl_bpix = 5;
+ }
+
+ p->pixclock = KHZ2PICOS(refresh *
+ (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
+ (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
+ / 1000);
+ debug("Pixel clock set to %lu.%03lu MHz\n",
+ PICOS2KHZ(p->pixclock) / 1000,
+ PICOS2KHZ(p->pixclock) % 1000);
+
+ gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
+ imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
+ ARRAY_SIZE(stk5_lcd_pads));
+
+ debug("Initializing FB driver\n");
+ if (!pix_fmt)
+ pix_fmt = IPU_PIX_FMT_RGB24;
+ else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
+ writel(0x01, IOMUXC_BASE_ADDR + 8);
+ } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
+ writel(0x21, IOMUXC_BASE_ADDR + 8);
+ }
+ if (pix_fmt != IPU_PIX_FMT_RGB24) {
+ struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ /* enable LDB & DI0 clock */
+ writel(readl(&ccm_regs->CCGR3) | (3 << 12) | (3 << 2),
+ &ccm_regs->CCGR3);
+ }
+
+ if (karo_load_splashimage(0) == 0) {
+ debug("Initializing LCD controller\n");
+ ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
+ } else {
+ debug("Skipping initialization of LCD controller\n");
+ }
+}
+#else
+#define lcd_enabled 0
+#endif /* CONFIG_LCD */
+
+static void stk5_board_init(void)
+{
+ gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
+ imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
+}
+
+static void stk5v3_board_init(void)
+{
+ stk5_board_init();
+}
+
+static void stk5v5_board_init(void)
+{
+ stk5_board_init();
+
+ gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
+ "Flexcan Transceiver");
+ imx_iomux_v3_setup_pad(MX6Q_PAD_DISP0_DAT0__GPIO_4_21);
+}
+
+static void tx6q_set_cpu_clock(void)
+{
+ unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
+
+ if (tstc() || (wrsr & WRSR_TOUT))
+ return;
+
+ if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
+ return;
+
+ mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK);
+
+ printf("CPU clock set to %u.%03u MHz\n",
+ mxc_get_clock(MXC_ARM_CLK) / 1000000,
+ mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
+}
+
+static void tx6_init_mac(void)
+{
+ u8 mac[ETH_ALEN];
+ char mac_str[ETH_ALEN * 3] = "";
+
+ imx_get_mac_from_fuse(-1, mac);
+ if (!is_valid_ether_addr(mac)) {
+ printf("No valid MAC address programmed\n");
+ return;
+ }
+
+ snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ setenv("ethaddr", mac_str);
+ printf("MAC addr from fuse: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+}
+
+int board_late_init(void)
+{
+ int ret = 0;
+ const char *baseboard;
+
+ tx6q_set_cpu_clock();
+ karo_fdt_move_fdt();
+
+ baseboard = getenv("baseboard");
+ if (!baseboard)
+ goto exit;
+
+ printf("Baseboard: %s\n", baseboard);
+
+ if (strncmp(baseboard, "stk5", 4) == 0) {
+ if ((strlen(baseboard) == 4) ||
+ strcmp(baseboard, "stk5-v3") == 0) {
+ stk5v3_board_init();
+ } else if (strcmp(baseboard, "stk5-v5") == 0) {
+ stk5v5_board_init();
+ } else {
+ printf("WARNING: Unsupported STK5 board rev.: %s\n",
+ baseboard + 4);
+ }
+ } else {
+ printf("WARNING: Unsupported baseboard: '%s'\n",
+ baseboard);
+ ret = -EINVAL;
+ }
+
+exit:
+ tx6_init_mac();
+
+ gpio_set_value(TX6Q_RESET_OUT_GPIO, 1);
+ return ret;
+}
+
+#define iomux_field(v,f) (((iomux_v3_cfg_t)(v) << f##_SHIFT) & f##_MASK)
+
+#define chk_iomux_field(f1,f2) ({ \
+ iomux_v3_cfg_t __c = iomux_field(~0, f1); \
+ if (__c & f2##_MASK) { \
+ printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \
+ #f1, f1##_MASK, \
+ #f2, f2##_MASK); \
+ } \
+ (__c & f2##_MASK) != 0; \
+})
+
+#define chk_iomux_bit(f1,f2) ({ \
+ iomux_v3_cfg_t __c = iomux_field(~0, f1); \
+ if (__c & f2) { \
+ printf("%18s[%016llx] overlaps with:\n%18s[%016llx]\n", \
+ #f1, f1##_MASK, \
+ #f2, (iomux_v3_cfg_t)f2); \
+ } \
+ (__c & f2) != 0; \
+})
+
+int checkboard(void)
+{
+ print_cpuinfo();
+
+ printf("Board: Ka-Ro TX6Q\n");
+
+#ifdef TIMER_TEST
+ {
+ struct mxc_gpt {
+ unsigned int control;
+ unsigned int prescaler;
+ unsigned int status;
+ unsigned int nouse[6];
+ unsigned int counter;
+ };
+ const int us_delay = 10;
+ unsigned long start = get_timer(0);
+ unsigned long last = gd->arch.tbl;
+ unsigned long loop = 0;
+ unsigned long cnt = 0;
+ static struct mxc_gpt *timer_base = (struct mxc_gpt *)GPT1_BASE_ADDR;
+
+ printf("GPT prescaler=%u\n", readl(&timer_base->prescaler) + 1);
+ printf("clock tick rate: %lu.%03lukHz\n",
+ gd->arch.timer_rate_hz / 1000, gd->arch.timer_rate_hz % 1000);
+ printf("ticks/us=%lu\n", gd->arch.timer_rate_hz / CONFIG_SYS_HZ / 1000);
+
+ while (!tstc()) {
+ unsigned long elapsed = get_timer(start);
+ unsigned long diff = gd->arch.tbl - last;
+
+ loop++;
+ last = gd->arch.tbl;
+
+ printf("loop %4lu: t=%08lx diff=%08lx steps=%6lu elapsed time: %4lu",
+ loop, gd->arch.tbl, diff, cnt, elapsed / CONFIG_SYS_HZ);
+ cnt = 0;
+ while (get_timer(elapsed + start) < CONFIG_SYS_HZ) {
+ cnt++;
+ udelay(us_delay);
+ }
+ printf(" counter=%08x udelay(%u)=%lu.%03luus\n",
+ readl(&timer_base->counter), us_delay,
+ 1000000000 / cnt / 1000, 1000000000 / cnt % 1000);
+ }
+ }
+#endif
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+#include <jffs2/jffs2.h>
+#include <mtd_node.h>
+struct node_info nodes[] = {
+ { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
+};
+
+#else
+#define fdt_fixup_mtdparts(b,n,c) do { } while (0)
+#endif
+
+static void tx6q_fixup_flexcan(void *blob)
+{
+ const char *baseboard = getenv("baseboard");
+
+ if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
+ return;
+
+ karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02090000, "transceiver-switch");
+ karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02094000, "transceiver-switch");
+}
+
+void tx6q_fixup_rtc(void *blob)
+{
+ karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
+ karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ fdt_fixup_ethernet(blob);
+
+ karo_fdt_fixup_touchpanel(blob);
+ karo_fdt_fixup_usb_otg(blob, "", 0);
+ tx6q_fixup_flexcan(blob);
+ tx6q_fixup_rtc(blob);
+}
+#endif
--- /dev/null
+sources {
+ u_boot_spl="@@BUILD_DIR@@spl/u-boot-spl";
+ u_boot="@@BUILD_DIR@@u-boot";
+}
+
+section (0) {
+ load u_boot_spl;
+ load ivt (entry = u_boot_spl:reset) > 0x8000;
+ hab call 0x8000;
+
+ load u_boot;
+ load ivt (entry = u_boot:reset) > 0x8000;
+ hab call 0x8000;
+}
--- /dev/null
+/*
+ * (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ board/karo/tx6q/lowlevel_init.o (.text*)
+ __image_copy_start = .;
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
+ . = ALIGN(4);
+
+ __image_copy_end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ _end = .;
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
-#include <cpsw.h>
+//#include <cpsw.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
jadecpu arm arm926ejs jadecpu syteco mb86r0x
mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg
tx25 arm arm926ejs tx25 karo mx25
+tx28-40xx arm arm926ejs tx28 karo mxs tx28:TX28
+tx28-41xx arm arm926ejs tx28 karo mxs tx28:TX28_S
zmx25 arm arm926ejs zmx25 syteco mx25
imx27lite arm arm926ejs imx27lite logicpd mx27
magnesium arm arm926ejs imx27lite logicpd mx27
am335x_evm_uart3 arm armv7 am335x ti am33xx am335x_evm:SERIAL4,CONS_INDEX=4
am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=5
am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6
+tx48 arm armv7 tx48 karo am33xx tx48:SYS_MPU_CLK=500,SYS_DDR_CLK=266
+tx48-dt arm armv7 tx48 karo am33xx tx48:OF_LIBFDT,SYS_MPU_CLK=720,SYS_DDR_CLK=444
highbank arm armv7 highbank - highbank
mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg
ima3-mx53 arm armv7 ima3-mx53 esg mx5 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg
vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
+tx51-6xx0 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=600,NR_DRAM_BANKS=1,SYS_SDRAM_CLK=166
+tx51-6xx1 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=600,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=200
+tx51-6xx2 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=600,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=166
+tx51-8xx0 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=1,SYS_SDRAM_CLK=166
+tx51-8xx1 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=200
+tx51-8xx2 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=166
+tx53-xx20 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=1,SYS_TX53_HWREV_2
+tx53-xx21 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=2,SYS_TX53_HWREV_2
+tx53-xx30 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=1
+tx53-xx31 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=2
+tx6q arm armv7 tx6q karo mx6
mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
COBJS-$(CONFIG_CMD_BDI) += cmd_bdinfo.o
COBJS-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o
COBJS-$(CONFIG_CMD_BMP) += cmd_bmp.o
+COBJS-$(CONFIG_CMD_BOOTCE) += cmd_bootce.o
COBJS-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o
COBJS-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o
COBJS-$(CONFIG_CMD_CACHE) += cmd_cache.o
COBJS-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o
COBJS-$(CONFIG_CMD_GETTIME) += cmd_gettime.o
COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o
+COBJS-$(CONFIG_CMD_IIM) += cmd_iim.o
COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o
COBJS-$(CONFIG_CMD_HASH) += cmd_hash.o
COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o
COBJS-$(CONFIG_CMD_ONENAND) += cmd_onenand.o
COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o
COBJS-$(CONFIG_CMD_PART) += cmd_part.o
+COBJS-$(CONFIG_CMD_PATA) += cmd_pata.o
ifdef CONFIG_PCI
COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o
endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on: code from RedBoot (C) Uwe Steinkohl <US@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+//#define DEBUG
+//#define TEST_LAUNCH
+//#define DDEBUG
+#ifdef DDEBUG
+#define _debug printf
+#else
+#define _debug debug
+#endif
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <wince.h>
+#include <asm/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define WINCE_VRAM_BASE 0x80000000
+#define CE_FIX_ADDRESS(a) ((void *)((a) - WINCE_VRAM_BASE + CONFIG_SYS_SDRAM_BASE))
+
+#ifndef INT_MAX
+#define INT_MAX ((int)(~0 >> 1))
+#endif
+
+/* Bin image parse states */
+#define CE_PS_RTI_ADDR 0
+#define CE_PS_RTI_LEN 1
+#define CE_PS_E_ADDR 2
+#define CE_PS_E_LEN 3
+#define CE_PS_E_CHKSUM 4
+#define CE_PS_E_DATA 5
+
+#define CE_MIN(a, b) (((a) < (b)) ? (a) : (b))
+#define CE_MAX(a, b) (((a) > (b)) ? (a) : (b))
+
+#define _STRMAC(s) #s
+#define STRMAC(s) _STRMAC(s)
+
+static ce_bin __attribute__ ((aligned (32))) g_bin;
+static ce_net __attribute__ ((aligned (32))) g_net;
+static IPaddr_t server_ip;
+
+static void ce_init_bin(ce_bin *bin, unsigned char *dataBuffer)
+{
+ memset(bin, 0, sizeof(*bin));
+
+debug("%s@%d: \n", __func__, __LINE__);
+ bin->data = dataBuffer;
+ bin->parseState = CE_PS_RTI_ADDR;
+ bin->parsePtr = (unsigned char *)bin;
+debug("%s@%d: \n", __func__, __LINE__);
+}
+
+static int ce_is_bin_image(void *image, int imglen)
+{
+ if (imglen < CE_BIN_SIGN_LEN) {
+ return 0;
+ }
+
+ return memcmp(image, CE_BIN_SIGN, CE_BIN_SIGN_LEN) == 0;
+}
+
+static const struct ce_magic {
+ char magic[8];
+ size_t size;
+ ce_std_driver_globals drv_glb;
+} ce_magic_template = {
+ .magic = "KARO_CE6",
+ .size = sizeof(ce_std_driver_globals),
+ .drv_glb = {
+ .header = {
+ .signature = STD_DRV_GLB_SIGNATURE,
+ .oalVersion = 1,
+ .bspVersion = 2,
+ },
+ },
+};
+
+#ifdef DEBUG
+static void __attribute__((unused)) ce_dump_block(void *ptr, int length)
+{
+ char *p = ptr;
+ int i;
+ int j;
+
+ for (i = 0; i < length; i++) {
+ if (!(i % 16)) {
+ printf("\n%p: ", ptr + i);
+ }
+
+ printf("%02x ", p[i]);
+ if (!((i + 1) % 16)){
+ printf(" ");
+ for (j = i - 15; j <= i; j++){
+ if((p[j] > 0x1f) && (p[j] < 0x7f)) {
+ printf("%c", p[j]);
+ } else {
+ printf(".");
+ }
+ }
+ }
+ }
+ printf("\n");
+}
+#else
+static inline void ce_dump_block(void *ptr, int length)
+{
+}
+#endif
+
+static void ce_setup_std_drv_globals(ce_std_driver_globals *std_drv_glb)
+{
+ char *mtdparts = getenv("mtdparts");
+ size_t max_len = ALIGN((unsigned long)std_drv_glb, SZ_4K) -
+ (unsigned long)&std_drv_glb->mtdparts;
+
+ if (eth_get_dev()) {
+ memcpy(&std_drv_glb->kitl.mac, eth_get_dev()->enetaddr,
+ sizeof(std_drv_glb->kitl.mac));
+ }
+ snprintf(std_drv_glb->deviceId, sizeof(std_drv_glb->deviceId),
+ "Triton%02X", eth_get_dev()->enetaddr[5]);
+
+ NetCopyIP(&std_drv_glb->kitl.ipAddress, &NetOurIP);
+ std_drv_glb->kitl.ipMask = getenv_IPaddr("netmask");
+ std_drv_glb->kitl.ipRoute = getenv_IPaddr("gatewayip");
+
+ if (mtdparts) {
+ strncpy(std_drv_glb->mtdparts, mtdparts, max_len);
+ std_drv_glb->mtdparts[max_len - 1] = '\0';
+ } else {
+ printf("Failed to get mtdparts environment variable\n");
+ }
+}
+
+static void ce_prepare_run_bin(ce_bin *bin)
+{
+ ce_driver_globals *drv_glb;
+ struct ce_magic *ce_magic = (void *)CONFIG_SYS_SDRAM_BASE + 0x160;
+ ce_std_driver_globals *std_drv_glb = &ce_magic->drv_glb;
+
+ /* Clear os RAM area (if needed) */
+ if (bin->edbgConfig.flags & EDBG_FL_CLEANBOOT) {
+ debug("cleaning memory from %p to %p\n",
+ bin->eRamStart, bin->eRamStart + bin->eRamLen);
+
+ printf("Preparing clean boot ... ");
+ memset(bin->eRamStart, 0, bin->eRamLen);
+ printf("ok\n");
+ }
+
+ /* Prepare driver globals (if needed) */
+ if (bin->eDrvGlb) {
+ debug("Copying CE MAGIC from %p to %p..%p\n",
+ &ce_magic_template, ce_magic,
+ (void *)ce_magic + sizeof(*ce_magic) - 1);
+ memcpy(ce_magic, &ce_magic_template, sizeof(*ce_magic));
+
+ ce_setup_std_drv_globals(std_drv_glb);
+ ce_magic->size = sizeof(*std_drv_glb) +
+ strlen(std_drv_glb->mtdparts) + 1;
+ ce_dump_block(ce_magic, offsetof(struct ce_magic, drv_glb) +
+ ce_magic->size);
+
+ drv_glb = bin->eDrvGlb;
+ memset(drv_glb, 0, sizeof(*drv_glb));
+
+ drv_glb->signature = DRV_GLB_SIGNATURE;
+
+ /* Local ethernet MAC address */
+ memcpy(drv_glb->macAddr, std_drv_glb->kitl.mac,
+ sizeof(drv_glb->macAddr));
+ debug("got MAC address %02x:%02x:%02x:%02x:%02x:%02x from environment\n",
+ drv_glb->macAddr[0], drv_glb->macAddr[1],
+ drv_glb->macAddr[2], drv_glb->macAddr[3],
+ drv_glb->macAddr[4], drv_glb->macAddr[5]);
+
+ /* Local IP address */
+ drv_glb->ipAddr = getenv_IPaddr("ipaddr");
+
+ /* Subnet mask */
+ drv_glb->ipMask = getenv_IPaddr("netmask");
+
+ /* Gateway config */
+ drv_glb->ipGate = getenv_IPaddr("gatewayip");
+#ifdef DEBUG
+ debug("got IP address %pI4 from environment\n", &drv_glb->ipAddr);
+ debug("got IP mask %pI4 from environment\n", &drv_glb->ipMask);
+ debug("got gateway address %pI4 from environment\n", &drv_glb->ipGate);
+#endif
+ /* EDBG services config */
+ memcpy(&drv_glb->edbgConfig, &bin->edbgConfig,
+ sizeof(bin->edbgConfig));
+ }
+
+ /*
+ * Make sure, all the above makes it into SDRAM because
+ * WinCE switches the cache & MMU off, obviously without
+ * flushing it first!
+ */
+ flush_dcache_all();
+}
+
+static int ce_lookup_ep_bin(ce_bin *bin)
+{
+ ce_rom_hdr *header;
+ ce_toc_entry *tentry;
+ e32_rom *e32;
+ unsigned int i;
+ uint32_t *sig = (uint32_t *)(bin->rtiPhysAddr + ROM_SIGNATURE_OFFSET);
+
+ debug("Looking for TOC signature at %p\n", sig);
+
+ /* Check image Table Of Contents (TOC) signature */
+ if (*sig != ROM_SIGNATURE) {
+ printf("Error: Did not find image TOC signature!\n");
+ printf("Expected %08x at address %p; found %08x instead\n",
+ ROM_SIGNATURE, sig, *sig);
+ return 0;
+ }
+
+ /* Lookup entry point */
+ header = CE_FIX_ADDRESS(*(unsigned int *)(bin->rtiPhysAddr +
+ ROM_SIGNATURE_OFFSET +
+ sizeof(unsigned int)));
+ tentry = (ce_toc_entry *)(header + 1);
+
+ for (i = 0; i < header->nummods; i++) {
+ // Look for 'nk.exe' module
+ if (strcmp(CE_FIX_ADDRESS(tentry[i].fileName), "nk.exe") == 0) {
+ // Save entry point and RAM addresses
+
+ e32 = CE_FIX_ADDRESS(tentry[i].e32Offset);
+
+ bin->eEntryPoint = CE_FIX_ADDRESS(tentry[i].loadOffset) +
+ e32->e32_entryrva;
+ bin->eRamStart = CE_FIX_ADDRESS(header->ramStart);
+ bin->eRamLen = header->ramEnd - header->ramStart;
+ // Save driver_globals address
+ // Must follow RAM section in CE config.bib file
+ //
+ // eg.
+ //
+ // RAM 80900000 03200000 RAM
+ // DRV_GLB 83B00000 00001000 RESERVED
+ //
+ bin->eDrvGlb = CE_FIX_ADDRESS(header->ramEnd);
+ return 1;
+ }
+ }
+
+ // Error: Did not find 'nk.exe' module
+ return 0;
+}
+
+static int ce_parse_bin(ce_bin *bin)
+{
+ unsigned char *pbData = g_net.data + 4;//bin->data;
+ int len = bin->dataLen;
+ int copyLen;
+
+ debug("starting ce image parsing:\n\tbin->binLen: 0x%08X\n", bin->binLen);
+ debug("\tlen=%d\n", len);
+ debug("\tparse_state=%d\n", bin->parseState);
+
+ if (len) {
+ ce_dump_block(pbData, len);
+#if 0
+if (bin->binLen > 1024)
+ return CE_PR_EOF;
+#endif
+ if (bin->binLen == 0) {
+ // Check for the .BIN signature first
+ if (!ce_is_bin_image(pbData, len)) {
+ printf("Error: Invalid or corrupted .BIN image!\n");
+ return CE_PR_ERROR;
+ }
+
+ printf("Loading Windows CE .BIN image ...\n");
+ // Skip signature
+ len -= CE_BIN_SIGN_LEN;
+ pbData += CE_BIN_SIGN_LEN;
+ }
+
+ while (len) {
+ switch (bin->parseState) {
+ case CE_PS_RTI_ADDR:
+ case CE_PS_RTI_LEN:
+ case CE_PS_E_ADDR:
+ case CE_PS_E_LEN:
+ case CE_PS_E_CHKSUM:
+ copyLen = CE_MIN(sizeof(unsigned int) - bin->parseLen, len);
+ memcpy(&bin->parsePtr[bin->parseLen], pbData, copyLen);
+
+ bin->parseLen += copyLen;
+ len -= copyLen;
+ pbData += copyLen;
+
+ if (bin->parseLen == sizeof(unsigned int)) {
+ if (bin->parseState == CE_PS_RTI_ADDR)
+ bin->rtiPhysAddr = CE_FIX_ADDRESS(bin->rtiPhysAddr);
+ else if (bin->parseState == CE_PS_E_ADDR &&
+ bin->ePhysAddr)
+ bin->ePhysAddr = CE_FIX_ADDRESS(bin->ePhysAddr);
+
+ bin->parseState++;
+ bin->parseLen = 0;
+ bin->parsePtr += sizeof(unsigned int);
+
+ if (bin->parseState == CE_PS_E_DATA) {
+ if (bin->ePhysAddr) {
+ bin->parsePtr = bin->ePhysAddr;
+ bin->parseChkSum = 0;
+ } else {
+ /* EOF */
+ len = 0;
+ bin->endOfBin = 1;
+ }
+ }
+ }
+ break;
+
+ case CE_PS_E_DATA:
+ debug("ePhysAddr=%p physlen=%08x parselen=%08x\n",
+ bin->ePhysAddr, bin->ePhysLen, bin->parseLen);
+ if (bin->ePhysAddr) {
+ copyLen = CE_MIN(bin->ePhysLen - bin->parseLen, len);
+ bin->parseLen += copyLen;
+ len -= copyLen;
+
+ while (copyLen--) {
+ bin->parseChkSum += *pbData;
+ *bin->parsePtr++ = *pbData++;
+ }
+
+ if (bin->parseLen == bin->ePhysLen) {
+ printf("Section [%02d]: address %p, size 0x%08X, checksum %s\n",
+ bin->section,
+ bin->ePhysAddr,
+ bin->ePhysLen,
+ (bin->eChkSum == bin->parseChkSum) ? "ok" : "fail");
+
+ if (bin->eChkSum != bin->parseChkSum) {
+ printf("Error: Checksum error, corrupted .BIN file!\n");
+ printf("checksum calculated: 0x%08x from file: 0x%08x\n",
+ bin->parseChkSum, bin->eChkSum);
+ bin->binLen = 0;
+ return CE_PR_ERROR;
+ }
+
+ bin->section++;
+ bin->parseState = CE_PS_E_ADDR;
+ bin->parseLen = 0;
+ bin->parsePtr = (unsigned char *)&bin->ePhysAddr;
+ }
+ } else {
+ bin->parseLen = 0;
+ bin->endOfBin = 1;
+ len = 0;
+ }
+ break;
+ }
+ }
+ }
+
+ if (bin->endOfBin) {
+ if (!ce_lookup_ep_bin(bin)) {
+ printf("Error: entry point not found!\n");
+ bin->binLen = 0;
+ return CE_PR_ERROR;
+ }
+
+ printf("Entry point: %p, address range: %p-%p\n",
+ bin->eEntryPoint,
+ bin->rtiPhysAddr,
+ bin->rtiPhysAddr + bin->rtiPhysLen);
+
+ return CE_PR_EOF;
+ }
+
+ /* Need more data */
+ bin->binLen += bin->dataLen;
+ return CE_PR_MORE;
+}
+
+static int ce_bin_load(void *image, int imglen)
+{
+ ce_init_bin(&g_bin, image);
+ g_bin.dataLen = imglen;
+ if (ce_parse_bin(&g_bin) == CE_PR_EOF) {
+ ce_prepare_run_bin(&g_bin);
+ return 1;
+ }
+
+ return 0;
+}
+
+static void ce_run_bin(void (*entry)(void))
+{
+ printf("Launching Windows CE ...\n");
+#ifdef TEST_LAUNCH
+return;
+#endif
+ entry();
+}
+
+static int do_bootce(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ void *addr;
+ size_t image_size;
+ char *s;
+
+ if (argc > 1) {
+ addr = (void *)simple_strtoul(argv[1], NULL, 16);
+ image_size = INT_MAX; /* actually we do not know the image size */
+ } else if (getenv("fileaddr") != NULL) {
+ addr = (void *)getenv_ulong("fileaddr", 16, 0);
+ image_size = getenv_ulong("filesize", 16, INT_MAX);
+ } else {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ printf ("## Booting Windows CE Image from address %p ...\n", addr);
+
+ /* check if there is a valid windows CE image */
+ if (ce_is_bin_image(addr, image_size)) {
+ if (!ce_bin_load(addr, image_size)) {
+ /* Ops! Corrupted .BIN image! */
+ /* Handle error here ... */
+ printf("corrupted .BIN image !!!\n");
+ return 1;
+ }
+ if ((s = getenv("autostart")) != NULL) {
+ if (*s != 'y') {
+ /*
+ * just use bootce to load the image to SDRAM;
+ * Do not start it automatically.
+ */
+ setenv_addr("fileaddr",
+ g_bin.eEntryPoint);
+ return 0;
+ }
+ }
+ ce_run_bin(g_bin.eEntryPoint); /* start the image */
+ } else {
+ printf("Image does not seem to be a valid Windows CE image!\n");
+ return 1;
+ }
+ return 1; /* never reached - just to keep compiler happy */
+}
+
+U_BOOT_CMD(
+ bootce, 2, 0, do_bootce,
+ "bootce\t- Boot a Windows CE image from memory \n",
+ "[args..]\n"
+ "\taddr\t\t-boot image from address addr\n"
+);
+
+static int ce_send_write_ack(ce_net *net)
+{
+ int ret;
+ unsigned short wdata[2];
+ int retries = 0;
+
+ wdata[0] = htons(EDBG_CMD_WRITE_ACK);
+ wdata[1] = htons(net->blockNum);
+ net->dataLen = sizeof(wdata);
+ memcpy(net->data, wdata, net->dataLen);
+
+ do {
+ ret = bootme_send_frame(net->data, net->dataLen);
+ if (ret) {
+ printf("Failed to send write ack %d; retries=%d\n",
+ ret, retries);
+ }
+debug("*");
+ } while (ret != 0 && retries-- > 0);
+ return ret;
+}
+
+static enum bootme_state ce_process_download(ce_net *net, ce_bin *bin)
+{
+ int ret = net->state;
+
+ if (net->dataLen >= 4) {
+ unsigned short command;
+ unsigned short blknum;
+
+ memcpy(&command, net->data, sizeof(command));
+ command = ntohs(command);
+ debug("command found: 0x%04X\n", command);
+
+ if (net->state == BOOTME_DOWNLOAD) {
+ unsigned short nxt = net->blockNum + 1;
+
+ memcpy(&blknum, &net->data[2], sizeof(blknum));
+ blknum = ntohs(blknum);
+ if (blknum == nxt) {
+ net->blockNum = blknum;
+debug("#");
+ } else {
+ int rc = ce_send_write_ack(net);
+
+ printf("Dropping out of sequence packet with ID %d (expected %d)\n",
+ blknum, nxt);
+ if (rc != 0)
+ return rc;
+
+ return ret;
+ }
+ }
+
+ switch (command) {
+ case EDBG_CMD_WRITE_REQ:
+ if (net->state == BOOTME_INIT) {
+ // Check file name for WRITE request
+ // CE EShell uses "boot.bin" file name
+#if 0
+ printf(">>>>>>>> First Frame, IP: %s, port: %d\n",
+ inet_ntoa((in_addr_t *)&net->srvAddrRecv),
+ ntohs(net->srvAddrRecv.sin_port));
+#endif
+ if (strncmp((char *)&net->data[2],
+ "boot.bin", 8) == 0) {
+ // Some diag output
+ if (net->verbose) {
+ printf("Locked Down download link, IP: %pI4\n",
+ &NetServerIP);
+ printf("Sending BOOTME request [%d] to %pI4\n",
+ net->seqNum, &NetServerIP);
+ }
+
+ // Lock down EShell download link
+// net->link = 1;
+ ret = BOOTME_DOWNLOAD;
+ } else {
+ // Unknown link
+ printf("Unknown link\n");
+ }
+
+ if (ret == BOOTME_DOWNLOAD) {
+ int rc = ce_send_write_ack(net);
+ if (rc != 0)
+ return rc;
+ }
+ }
+ break;
+
+ case EDBG_CMD_WRITE:
+ /* Fixup data len */
+ bin->dataLen = net->dataLen - 4;
+ ret = ce_parse_bin(bin);
+ if (ret != CE_PR_ERROR) {
+ int rc = ce_send_write_ack(net);
+ if (rc)
+ return rc;
+ if (ret == CE_PR_EOF)
+ ret = BOOTME_DONE;
+ } else {
+ ret = BOOTME_ERROR;
+ }
+ break;
+
+ case EDBG_CMD_READ_REQ:
+ printf("Ignoring EDBG_CMD_READ_REQ\n");
+ /* Read requests are not supported
+ * Do nothing ...
+ */
+ break;
+
+ case EDBG_CMD_ERROR:
+ printf("Error: unknown error on the host side\n");
+
+ bin->binLen = 0;
+ ret = BOOTME_ERROR;
+ break;
+
+ default:
+ printf("unknown command 0x%04X\n", command);
+ net->state = BOOTME_ERROR;
+ }
+ }
+ return ret;
+}
+
+static enum bootme_state ce_process_edbg(ce_net *net, ce_bin *bin)
+{
+ enum bootme_state ret = net->state;
+ eth_dbg_hdr header;
+
+debug("%s: received packet of %u byte @ %p\n", __func__, net->dataLen, net->data);
+ if (net->dataLen < sizeof(header)) {
+ /* Bad packet */
+ printf("Invalid packet size %u\n", net->dataLen);
+ net->dataLen = 0;
+ return ret;
+ }
+debug("%s@%d: Copying header from %p..%p to %p\n", __func__, __LINE__,
+ net->data, net->data + sizeof(header) - 1, &header);
+ memcpy(&header, net->data, sizeof(header));
+ if (header.id != EDBG_ID) {
+ /* Bad packet */
+ printf("Bad EDBG ID %08x\n", header.id);
+ net->dataLen = 0;
+ return ret;
+ }
+
+debug("%s@%d\n", __func__, __LINE__);
+ if (header.service != EDBG_SVC_ADMIN) {
+ /* Unknown service */
+ printf("Bad EDBG service %02x\n", header.service);
+ net->dataLen = 0;
+ return ret;
+ }
+
+debug("%s@%d\n", __func__, __LINE__);
+ if (net->state == BOOTME_INIT) {
+ /* Some diag output */
+ if (net->verbose) {
+ printf("Locked Down EDBG service link, IP: %pI4\n",
+ &NetServerIP);
+ }
+
+ /* Lock down EDBG link */
+// net->link = 1;
+ net->state = BOOTME_DEBUG;
+ }
+
+debug("%s@%d\n", __func__, __LINE__);
+ switch (header.cmd) {
+ case EDBG_CMD_JUMPIMG:
+debug("%s@%d\n", __func__, __LINE__);
+ net->gotJumpingRequest = 1;
+
+ if (net->verbose) {
+ printf("Received JUMPING command\n");
+ }
+ /* Just pass through and copy CONFIG structure */
+ case EDBG_CMD_OS_CONFIG:
+debug("%s@%d\n", __func__, __LINE__);
+ /* Copy config structure */
+ memcpy(&bin->edbgConfig, header.data,
+ sizeof(edbg_os_config_data));
+ if (net->verbose) {
+ printf("Received CONFIG command\n");
+ if (bin->edbgConfig.flags & EDBG_FL_DBGMSG) {
+ printf("--> Enabling DBGMSG service, IP: %d.%d.%d.%d, port: %d\n",
+ (bin->edbgConfig.dbgMsgIPAddr >> 0) & 0xFF,
+ (bin->edbgConfig.dbgMsgIPAddr >> 8) & 0xFF,
+ (bin->edbgConfig.dbgMsgIPAddr >> 16) & 0xFF,
+ (bin->edbgConfig.dbgMsgIPAddr >> 24) & 0xFF,
+ ntohs(bin->edbgConfig.dbgMsgPort));
+ }
+
+ if (bin->edbgConfig.flags & EDBG_FL_PPSH) {
+ printf("--> Enabling PPSH service, IP: %d.%d.%d.%d, port: %d\n",
+ (bin->edbgConfig.ppshIPAddr >> 0) & 0xFF,
+ (bin->edbgConfig.ppshIPAddr >> 8) & 0xFF,
+ (bin->edbgConfig.ppshIPAddr >> 16) & 0xFF,
+ (bin->edbgConfig.ppshIPAddr >> 24) & 0xFF,
+ ntohs(bin->edbgConfig.ppshPort));
+ }
+
+ if (bin->edbgConfig.flags & EDBG_FL_KDBG) {
+ printf("--> Enabling KDBG service, IP: %d.%d.%d.%d, port: %d\n",
+ (bin->edbgConfig.kdbgIPAddr >> 0) & 0xFF,
+ (bin->edbgConfig.kdbgIPAddr >> 8) & 0xFF,
+ (bin->edbgConfig.kdbgIPAddr >> 16) & 0xFF,
+ (bin->edbgConfig.kdbgIPAddr >> 24) & 0xFF,
+ ntohs(bin->edbgConfig.kdbgPort));
+ }
+
+ if (bin->edbgConfig.flags & EDBG_FL_CLEANBOOT) {
+ printf("--> Force clean boot\n");
+ }
+ }
+ ret = BOOTME_DEBUG;
+ break;
+
+ default:
+ if (net->verbose) {
+ printf("Received unknown command: %08X\n", header.cmd);
+ }
+ return BOOTME_ERROR;
+ }
+
+ /* Respond with ack */
+ header.flags = EDBG_FL_FROM_DEV | EDBG_FL_ACK;
+ net->dataLen = EDBG_DATA_OFFSET;
+debug("%s@%d: sending packet %p len %u\n", __func__, __LINE__,
+ net->data, net->dataLen);
+ bootme_send_frame(net->data, net->dataLen);
+ return ret;
+}
+
+static enum bootme_state ce_edbg_handler(const void *buf, size_t len)
+{
+ enum bootme_state ret;
+
+ if (len == 0) {
+ _debug("%s: EOF\n", __func__);
+ return BOOTME_DONE;
+ }
+#if 0
+ if (len > sizeof(g_net.data)) {
+ debug("Dropping oversized packet of %u bytes (max. size %u)\n",
+ len, sizeof(g_net.data));
+ return g_net.state;
+ }
+ debug("Copying network packet of %u bytes from %p to %p\n",
+ len, buf, g_net.data);
+ memcpy(g_net.data, buf, len);
+ g_net.dataLen = len;
+#else
+ g_net.data = (void *)buf;
+ g_net.dataLen = len;
+#endif
+ ret = ce_process_edbg(&g_net, &g_bin);
+ return ret;
+}
+
+static void ce_init_edbg_link(ce_net *net)
+{
+ /* Initialize EDBG link for commands */
+ net->state = BOOTME_INIT;
+}
+
+static enum bootme_state ce_download_handler(const void *buf, size_t len)
+{
+#if 0
+ if (len > sizeof(g_net.data)) {
+ debug("Dropping oversized packet of %u bytes (max. size %u)\n",
+ len, sizeof(g_net.data));
+ return g_net.state;
+ }
+ debug("Copying network packet of %u bytes from %p to %p\n",
+ len, buf, g_net.data);
+ memcpy(g_net.data, buf, len);
+ g_net.dataLen = len;
+#else
+ g_net.data = (void *)buf;
+ g_net.dataLen = len;
+#endif
+ g_net.state = ce_process_download(&g_net, &g_bin);
+ return g_net.state;
+}
+
+static int ce_send_bootme(ce_net *net)
+{
+ eth_dbg_hdr *header;
+ edbg_bootme_data *data;
+ unsigned char txbuf[PKTSIZE_ALIGN];
+#ifdef DEBUG_
+ int i;
+ unsigned char *pkt;
+#endif
+ /* Fill out BOOTME packet */
+net->data = txbuf;
+assert(net->data != NULL);
+ memset(net->data, 0, PKTSIZE);
+ header = (eth_dbg_hdr *)net->data;
+ data = (edbg_bootme_data *)header->data;
+
+ header->id = EDBG_ID;
+ header->service = EDBG_SVC_ADMIN;
+ header->flags = EDBG_FL_FROM_DEV;
+ header->seqNum = net->seqNum++;
+ header->cmd = EDBG_CMD_BOOTME;
+
+ data->versionMajor = 0;
+ data->versionMinor = 0;
+ data->cpuId = EDBG_CPU_TYPE_ARM;
+ data->bootmeVer = EDBG_CURRENT_BOOTME_VERSION;
+ data->bootFlags = 0;
+ data->downloadPort = 0;
+ data->svcPort = 0;
+
+ /* MAC address from environment*/
+ if (!eth_getenv_enetaddr("ethaddr", data->macAddr)) {
+ printf("'ethaddr' is not set or invalid\n");
+ memset(data->macAddr, 0, sizeof(data->macAddr));
+ }
+
+ /* IP address from active config */
+ NetCopyIP(&data->ipAddr, &NetOurIP);
+
+ // Device name string (NULL terminated). Should include
+ // platform and number based on Ether address (e.g. Odo42, CEPCLS2346, etc)
+
+ // We will use lower MAC address segment to create device name
+ // eg. MAC '00-0C-C6-69-09-05', device name 'Triton05'
+
+ strncpy(data->platformId, "Triton", sizeof(data->platformId));
+ snprintf(data->deviceName, sizeof(data->deviceName), "%s%02X",
+ data->platformId, data->macAddr[5]);
+
+#ifdef DEBUG_
+ printf("header->id: %08X\r\n", header->id);
+ printf("header->service: %08X\r\n", header->service);
+ printf("header->flags: %08X\r\n", header->flags);
+ printf("header->seqNum: %08X\r\n", header->seqNum);
+ printf("header->cmd: %08X\r\n\r\n", header->cmd);
+
+ printf("data->versionMajor: %08X\r\n", data->versionMajor);
+ printf("data->versionMinor: %08X\r\n", data->versionMinor);
+ printf("data->cpuId: %08X\r\n", data->cpuId);
+ printf("data->bootmeVer: %08X\r\n", data->bootmeVer);
+ printf("data->bootFlags: %08X\r\n", data->bootFlags);
+ printf("data->svcPort: %08X\r\n\r\n", ntohs(data->svcPort));
+
+ printf("data->macAddr: %02X-%02X-%02X-%02X-%02X-%02X\r\n",
+ data->macAddr[0], data->macAddr[1],
+ data->macAddr[2], data->macAddr[3],
+ data->macAddr[4], data->macAddr[5]);
+
+ printf("data->ipAddr: %d.%d.%d.%d\r\n",
+ (data->ipAddr >> 0) & 0xFF,
+ (data->ipAddr >> 8) & 0xFF,
+ (data->ipAddr >> 16) & 0xFF,
+ (data->ipAddr >> 24) & 0xFF);
+
+ printf("data->platformId: %s\r\n", data->platformId);
+
+ printf("data->deviceName: %s\r\n", data->deviceName);
+#endif
+ // Some diag output ...
+ if (net->verbose) {
+ printf("Sending BOOTME request [%d] to %pI4\n", net->seqNum,
+ &server_ip);
+ }
+
+ net->dataLen = BOOTME_PKT_SIZE;
+// net->status = CE_PR_MORE;
+ net->state = BOOTME_INIT;
+#ifdef DEBUG_
+ debug("Start of buffer: %p\n", net->data);
+ debug("Start of ethernet buffer: %p\n", net->data);
+ debug("Start of CE header: %p\n", header);
+ debug("Start of CE data: %p\n", data);
+
+ pkt = net->data;
+ debug("packet to send (ceconnect): \n");
+ for (i = 0; i < net->dataLen; i++) {
+ debug("0x%02X ", pkt[i]);
+ if (!((i + 1) % 16))
+ debug("\n");
+ }
+ debug("\n");
+#endif
+ return BootMeRequest(server_ip, net->data, net->dataLen, 1);
+}
+
+static inline int ce_init_download_link(ce_net *net, ce_bin *bin, int verbose)
+{
+ if (!eth_get_dev()) {
+ printf("No network interface available\n");
+ return -ENODEV;
+ }
+ printf("Using device '%s'\n", eth_get_name());
+
+ /* Initialize EDBG link for download */
+ memset(net, 0, sizeof(*net));
+
+ net->verbose = verbose;
+
+ ce_init_bin(bin, NULL);//&net->data[4]);
+ return 0;
+}
+
+#define UINT_MAX ~0UL
+
+static inline int ce_download_file(ce_net *net, ulong timeout)
+{
+ ulong start = get_timer_masked();
+
+ while (net->state == BOOTME_INIT) {
+ int ret;
+
+ if (timeout && get_timer(start) > timeout) {
+ printf("CELOAD - Canceled, timeout\n");
+ return 1;
+ }
+
+ if (ctrlc()) {
+ printf("CELOAD - canceled by user\n");
+ return 1;
+ }
+
+ if (ce_send_bootme(&g_net)) {
+ printf("CELOAD - error while sending BOOTME request\n");
+ return 1;
+ }
+ if (net->verbose) {
+ if (timeout) {
+ printf("Waiting for connection, timeout %lu sec\n",
+ DIV_ROUND_UP(timeout - get_timer(start),
+ CONFIG_SYS_HZ));
+ } else {
+ printf("Waiting for connection, enter ^C to abort\n");
+ }
+ }
+
+ ret = BootMeDownload(ce_download_handler);
+ printf("BootMeDownload() returned %d\n", ret);
+ if (ret == BOOTME_ERROR) {
+ printf("CELOAD - aborted\n");
+ return 1;
+ }
+ }
+ return 0;
+}
+
+static void ce_disconnect(void)
+{
+ net_set_udp_handler(NULL);
+ eth_halt();
+}
+
+static int do_ceconnect(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int verbose = 0;
+ ulong timeout = 0;
+ int ret = 1;
+ int i;
+
+ server_ip = 0;
+
+ for (i = 1; i < argc; i++){
+ if (*argv[i] != '-')
+ break;
+ if (argv[i][1] == 'v') {
+ verbose = 1;
+ } else if (argv[i][1] == 't') {
+ i++;
+ if (argc > i) {
+ timeout = simple_strtoul(argv[i],
+ NULL, 10);
+ if (timeout >= UINT_MAX / CONFIG_SYS_HZ) {
+ printf("Timeout value %lu out of range (max.: %lu)\n",
+ timeout, UINT_MAX / CONFIG_SYS_HZ - 1);
+ return 1;
+ }
+ timeout *= CONFIG_SYS_HZ;
+ } else {
+ printf("Option requires an argument - t\n");
+ return 1;
+ }
+ } else if (argv[i][1] == 'h') {
+ i++;
+ if (argc > i) {
+ server_ip = string_to_ip(argv[i]);
+ printf("Using server %pI4\n", &server_ip);
+ } else {
+ printf("Option requires an argument - t\n");
+ return 1;
+ }
+ }
+ }
+#ifndef TEST_LAUNCH
+ if (ce_init_download_link(&g_net, &g_bin, verbose) != 0)
+ goto err;
+
+ if (ce_download_file(&g_net, timeout))
+ goto err;
+#else
+g_bin.binLen = 1;
+#endif
+ if (g_bin.binLen) {
+ // Try to receive edbg commands from host
+_debug("%s@%d: \n", __func__, __LINE__);
+ ce_init_edbg_link(&g_net);
+_debug("%s@%d: \n", __func__, __LINE__);
+ if (verbose)
+ printf("Waiting for EDBG commands ...\n");
+
+_debug("%s@%d: \n", __func__, __LINE__);
+ ret = BootMeDebugStart(ce_edbg_handler);
+_debug("%s@%d: ret=%d\n", __func__, __LINE__, ret);
+ if (ret != BOOTME_DONE)
+ goto err;
+_debug("%s@%d: \n", __func__, __LINE__);
+
+ // Prepare WinCE image for execution
+ ce_prepare_run_bin(&g_bin);
+_debug("%s@%d: \n", __func__, __LINE__);
+
+ // Launch WinCE, if necessary
+ if (g_net.gotJumpingRequest)
+ ce_run_bin(g_bin.eEntryPoint);
+_debug("%s@%d: \n", __func__, __LINE__);
+ }
+ ret = 0;
+err:
+ ce_disconnect();
+ return ret;
+}
+
+U_BOOT_CMD(
+ ceconnect, 4, 1, do_ceconnect,
+ "ceconnect - Set up a connection to the CE host PC over TCP/IP and download the run-time image\n",
+ "ceconnect [-v] [-t <timeout>]\n"
+ " -v verbose operation\n"
+ " -t <timeout> - max wait time (#sec) for the connection\n"
+);
"fdt rsvmem delete <index> - Delete a mem reserves\n"
"fdt chosen [<start> <end>] - Add/update the /chosen branch in the tree\n"
" <start>/<end> - initrd start/end addr\n"
- "NOTE: Dereference aliases by omiting the leading '/', "
+ "NOTE: Dereference aliases by omitting the leading '/', "
"e.g. fdt print ethernet0.";
#endif
--- /dev/null
+/*
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright 2007, Freescale Semiconductor, Inc
+ * Andy Fleming
+ *
+ * Based vaguely on the pxa mmc code:
+ * (C) Copyright 2003
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * Adapted for U-Boot version 2012-04-01 by Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/arch/imx_iim.h>
+
+int do_iimops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int bank = 0,
+ row = 0,
+ val = 0;
+
+ if (argc < 3 || argc > 5)
+ goto err_rtn;
+
+ if (strcmp(argv[1], "read") == 0) {
+ if (strcmp(argv[2], "fecmac") == 0) {
+ if (3 == argc)
+ iim_blow_func(argv[2], NULL);
+ else
+ goto err_rtn;
+ } else {
+ if (4 == argc) {
+ bank = simple_strtoul(argv[2], NULL, 16);
+ row = simple_strtoul(argv[3], NULL, 16);
+
+ iim_read(bank, row);
+ } else
+ goto err_rtn;
+ }
+ } else if (strcmp(argv[1], "blow") == 0) {
+ if (strcmp(argv[2], "fecmac") == 0) {
+ if (4 == argc)
+ iim_blow_func(argv[2], argv[3]);
+ else
+ goto err_rtn;
+ } else {
+ if (5 == argc) {
+ bank = simple_strtoul(argv[2], NULL, 16);
+ row = simple_strtoul(argv[3], NULL, 16);
+ val = simple_strtoul(argv[4], NULL, 16);
+
+ iim_blow(bank, row, val);
+ } else
+ goto err_rtn;
+ }
+ } else
+ goto err_rtn;
+
+ return 0;
+err_rtn:
+ printf("Invalid parameters!\n");
+ printf("It is too dangeous for you to use iim command.\n");
+ return 1;
+}
+
+U_BOOT_CMD(
+ iim, 5, 1, do_iimops,
+ "IIM sub system",
+ "Warning: all numbers in parameter are in hex format!\n"
+ "iim read <bank> <row> - Read some fuses\n"
+ "iim read fecmac - Read FEC Mac address\n"
+ "iim blow <bank> <row> <value> - Blow some fuses\n"
+ "iim blow fecmac <0x##:0x##:0x##:0x##:0x##:0x##>"
+ "- Blow FEC Mac address");
+
/* Only "dump" is repeatable. */
if (repeat && strcmp(cmd, "dump"))
- return 0;
+ return CMD_RET_FAILURE;
if (strcmp(cmd, "info") == 0) {
if (nand_info[i].name)
nand_print_and_set_info(i);
}
- return 0;
+ return CMD_RET_SUCCESS;
}
if (strcmp(cmd, "device") == 0) {
puts("no devices available\n");
else
nand_print_and_set_info(dev);
- return 0;
+ return CMD_RET_SUCCESS;
}
dev = (int)simple_strtoul(argv[2], NULL, 10);
set_dev(dev);
- return 0;
+ return CMD_RET_SUCCESS;
}
#ifdef CONFIG_ENV_OFFSET_OOB
/* this command operates only on the first nand device */
if (strcmp(cmd, "env.oob") == 0)
- return do_nand_env_oob(cmdtp, argc - 1, argv + 1);
+ return do_nand_env_oob(cmdtp, argc - 1, argv + 1) ?
+ CMD_RET_FAILURE : CMD_RET_SUCCESS;;
#endif
/* The following commands operate on the current device, unless
if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
!nand_info[dev].name) {
puts("\nno devices available\n");
- return 1;
+ return CMD_RET_FAILURE;
}
nand = &nand_info[dev];
for (off = 0; off < nand->size; off += nand->erasesize)
if (nand_block_isbad(nand, off))
printf(" %08llx\n", (unsigned long long)off);
- return 0;
+ return CMD_RET_SUCCESS;
}
/*
printf("\nNAND %s: ", cmd);
/* skip first two or three arguments, look for offset and size */
if (arg_off_size(argc - o, argv + o, &dev, &off, &size) != 0)
- return 1;
+ return CMD_RET_FAILURE;
nand = &nand_info[dev];
opts.scrub = 1;
else {
puts("scrub aborted\n");
- return -1;
+ return CMD_RET_FAILURE;
}
} else {
puts("scrub aborted\n");
- return -1;
+ return CMD_RET_FAILURE;
}
}
ret = nand_erase_opts(nand, &opts);
printf("%s\n", ret ? "ERROR" : "OK");
- return ret == 0 ? 0 : 1;
+ return ret == 0 ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
}
if (strncmp(cmd, "dump", 4) == 0) {
off = (int)simple_strtoul(argv[2], NULL, 16);
ret = nand_dump(nand, off, !strcmp(&cmd[4], ".oob"), repeat);
- return ret == 0 ? 1 : 0;
+ return ret == 0 ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
}
if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) {
read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
printf("\nNAND %s: ", read ? "read" : "write");
+ if (arg_off_size(argc - 3, argv + 3, &dev, &off, &size) != 0)
+ return CMD_RET_FAILURE;
nand = &nand_info[dev];
} else if (!strcmp(s, ".trimffs")) {
if (read) {
printf("Unknown nand command suffix '%s'\n", s);
- return 1;
+ return CMD_RET_FAILURE;
}
ret = nand_write_skip_bad(nand, off, &rwsize,
(u_char *)addr,
} else if (!strcmp(s, ".yaffs")) {
if (read) {
printf("Unknown nand command suffix '%s'.\n", s);
- return 1;
+ return CMD_RET_FAILURE;
}
ret = nand_write_skip_bad(nand, off, &rwsize,
(u_char *)addr,
ret = raw_access(nand, addr, off, pagecount, read);
} else {
printf("Unknown nand command suffix '%s'.\n", s);
- return 1;
+ return CMD_RET_FAILURE;
}
printf(" %zu bytes %s: %s\n", rwsize,
read ? "read" : "written", ret ? "ERROR" : "OK");
- return ret == 0 ? 0 : 1;
+ return ret == 0 ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
}
#ifdef CONFIG_CMD_NAND_TORTURE
--argc;
++argv;
}
- return ret;
+ return ret == 0 ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
}
if (strcmp(cmd, "biterr") == 0) {
/* todo */
- return 1;
+ return CMD_RET_FAILURE;
}
#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
puts("NAND flash successfully locked\n");
} else {
puts("Error locking NAND flash\n");
- return 1;
+ return CMD_RET_FAILURE;
}
}
- return 0;
+ return CMD_RET_SUCCESS;
}
if (strncmp(cmd, "unlock", 5) == 0) {
allexcept = 1;
if (arg_off_size(argc - 2, argv + 2, &dev, &off, &size) < 0)
- return 1;
+ return CMD_RET_FAILURE;
if (!nand_unlock(&nand_info[dev], off, size, allexcept)) {
puts("NAND flash successfully unlocked\n");
} else {
puts("Error unlocking NAND flash, "
"write and erase will probably fail\n");
- return 1;
+ return CMD_RET_FAILURE;
}
- return 0;
+ return CMD_RET_SUCCESS;
}
#endif
--- /dev/null
+/*
+ * Copyright (C) 2000-2005, DENX Software Engineering
+ * Wolfgang Denk <wd@denx.de>
+ * Copyright (C) Procsys. All rights reserved.
+ * Mushtaq Khan <mushtaq_k@procsys.com>
+ * <mushtaqk_921@yahoo.co.in>
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Terry Lv <r65388@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <part.h>
+#include <ata.h>
+#include <pata.h>
+
+int pata_curr_device = -1;
+block_dev_desc_t pata_dev_desc[CONFIG_SYS_ATA_MAX_DEVICE];
+
+int pata_initialize(void)
+{
+ int rc;
+ int i;
+
+ for (i = 0; i < CONFIG_SYS_ATA_MAX_DEVICE; i++) {
+ memset(&pata_dev_desc[i], 0, sizeof(struct block_dev_desc));
+ pata_dev_desc[i].if_type = IF_TYPE_ATAPI;
+ pata_dev_desc[i].dev = i;
+ pata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+ pata_dev_desc[i].type = DEV_TYPE_HARDDISK;
+ pata_dev_desc[i].lba = 0;
+ pata_dev_desc[i].blksz = 512;
+ pata_dev_desc[i].block_read = pata_read;
+ pata_dev_desc[i].block_write = pata_write;
+
+ rc = init_pata(i);
+ rc = scan_pata(i);
+ if ((pata_dev_desc[i].lba > 0) && (pata_dev_desc[i].blksz > 0))
+ init_part(&pata_dev_desc[i]);
+ }
+ pata_curr_device = 0;
+ return rc;
+}
+
+block_dev_desc_t *pata_get_dev(int dev)
+{
+ return (dev < CONFIG_SYS_ATA_MAX_DEVICE) ? &pata_dev_desc[dev] : NULL;
+}
+
+int do_pata(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int rc = 0;
+
+ if (argc == 2 && strcmp(argv[1], "init") == 0)
+ return pata_initialize();
+
+ /* If the user has not yet run `pata init`, do it now */
+ if (pata_curr_device == -1)
+ if (pata_initialize())
+ return 1;
+
+ switch (argc) {
+ case 0:
+ case 1:
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ case 2:
+ if (strncmp(argv[1], "inf", 3) == 0) {
+ int i;
+ putc('\n');
+ for (i = 0; i < CONFIG_SYS_ATA_MAX_DEVICE; ++i) {
+ if (pata_dev_desc[i].type == DEV_TYPE_UNKNOWN)
+ continue;
+ printf("PATA device %d: ", i);
+ dev_print(&pata_dev_desc[i]);
+ }
+ return 0;
+ } else if (strncmp(argv[1], "dev", 3) == 0) {
+ if ((pata_curr_device < 0) || \
+ (pata_curr_device >= CONFIG_SYS_ATA_MAX_DEVICE)) {
+ puts("\nno PATA devices available\n");
+ return 1;
+ }
+ printf("\nPATA device %d: ", pata_curr_device);
+ dev_print(&pata_dev_desc[pata_curr_device]);
+ return 0;
+ } else if (strncmp(argv[1], "part", 4) == 0) {
+ int dev, ok;
+
+ for (ok = 0, dev = 0; dev < CONFIG_SYS_ATA_MAX_DEVICE; ++dev) {
+ if (pata_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
+ ++ok;
+ if (dev)
+ putc('\n');
+ print_part(&pata_dev_desc[dev]);
+ }
+ }
+ if (!ok) {
+ puts("\nno PATA devices available\n");
+ rc++;
+ }
+ return rc;
+ }
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ case 3:
+ if (strncmp(argv[1], "dev", 3) == 0) {
+ int dev = (int)simple_strtoul(argv[2], NULL, 10);
+
+ printf("\nPATA device %d: ", dev);
+ if (dev >= CONFIG_SYS_ATA_MAX_DEVICE) {
+ puts("unknown device\n");
+ return 1;
+ }
+ dev_print(&pata_dev_desc[dev]);
+
+ if (pata_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
+ return 1;
+
+ pata_curr_device = dev;
+
+ puts("... is now current device\n");
+
+ return 0;
+ } else if (strncmp(argv[1], "part", 4) == 0) {
+ int dev = (int)simple_strtoul(argv[2], NULL, 10);
+
+ if (pata_dev_desc[dev].part_type != PART_TYPE_UNKNOWN) {
+ print_part(&pata_dev_desc[dev]);
+ } else {
+ printf("\nPATA device %d not available\n", dev);
+ rc = 1;
+ }
+ return rc;
+ }
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+
+ default: /* at least 4 args */
+ if (strcmp(argv[1], "read") == 0) {
+ ulong addr = simple_strtoul(argv[2], NULL, 16);
+ ulong cnt = simple_strtoul(argv[4], NULL, 16);
+ ulong n;
+ lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
+
+ printf("\nPATA read: device %d block # %ld, count %ld ... ",
+ pata_curr_device, blk, cnt);
+
+ n = pata_read(pata_curr_device, blk, cnt, (u32 *)addr);
+
+ /* flush cache after read */
+ flush_cache(addr, cnt * pata_dev_desc[pata_curr_device].blksz);
+
+ printf("%ld blocks read: %s\n",
+ n, (n == cnt) ? "OK" : "ERROR");
+ return (n == cnt) ? 0 : 1;
+ } else if (strcmp(argv[1], "write") == 0) {
+ ulong addr = simple_strtoul(argv[2], NULL, 16);
+ ulong cnt = simple_strtoul(argv[4], NULL, 16);
+ ulong n;
+
+ lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
+
+ printf("\nPATA write: device %d block # %ld, count %ld ... ",
+ pata_curr_device, blk, cnt);
+
+ n = pata_write(pata_curr_device, blk, cnt, (u32 *)addr);
+
+ printf("%ld blocks written: %s\n",
+ n, (n == cnt) ? "OK" : "ERROR");
+ return (n == cnt) ? 0 : 1;
+ } else {
+ printf("Usage:\n%s\n", cmdtp->usage);
+ rc = 1;
+ }
+
+ return rc;
+ }
+}
+
+U_BOOT_CMD(
+ pata, 5, 1, do_pata,
+ "pata - PATA sub system\n",
+ "pata info - show available PATA devices\n"
+ "pata device [dev] - show or set current device\n"
+ "pata part [dev] - print partition table\n"
+ "pata read addr blk# cnt\n"
+ "pata write addr blk# cnt\n");
/*
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Terry Lv <r65388@freescale.com>
+ *
* Copyright (C) 2000-2005, DENX Software Engineering
* Wolfgang Denk <wd@denx.de>
* Copyright (C) Procsys. All rights reserved.
env_t *env_ptr = &environment;
#elif defined(CONFIG_NAND_ENV_DST)
env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST;
-#else /* ! ENV_IS_EMBEDDED */
-env_t *env_ptr;
#endif /* ENV_IS_EMBEDDED */
DECLARE_GLOBAL_DATA_PTR;
gd->env_valid = 1;
}
+#ifdef CONFIG_NAND_ENV_DST
free(env_ptr);
+#endif
if (gd->env_valid == 1)
ep = tmp_env1;
goto bail;
bus = &of_busses[0];
- /* Cound address cells & copy address locally */
+ /* Count address cells & copy address locally */
bus->count_cells(blob, parent, &na, &ns);
if (!OF_CHECK_COUNTS(na, ns)) {
printf("%s: Bad cell count for %s\n", __FUNCTION__,
#ifdef CONFIG_LCD_LOGO
# include <bmp_logo.h> /* Get logo data, width and height */
# include <bmp_logo_data.h>
-# if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET) && (LCD_BPP != LCD_COLOR16)
+# if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET) && (LCD_BPP < LCD_COLOR16)
# error Default Color Map overlaps with Logo Color Map
# endif
#endif
static void lcd_drawchars(ushort x, ushort y, uchar *str, int count)
{
- uchar *dest;
+ void *dest;
ushort row;
#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
ushort off = x * (1 << LCD_BPP) % 8;
#endif
- dest = (uchar *)(lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8);
+ dest = lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8;
for (row = 0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) {
uchar *s = str;
int i;
-#if LCD_BPP == LCD_COLOR16
- ushort *d = (ushort *)dest;
+#if LCD_BPP == LCD_COLOR24
+ ulong *d = dest;
+#elif LCD_BPP == LCD_COLOR16
+ ushort *d = dest;
#else
uchar *d = dest;
#endif
*d++ = rest | (sym >> off);
rest = sym << (8-off);
-#elif LCD_BPP == LCD_COLOR8
- for (c = 0; c < 8; ++c) {
- *d++ = (bits & 0x80) ?
- lcd_color_fg : lcd_color_bg;
- bits <<= 1;
- }
-#elif LCD_BPP == LCD_COLOR16
+#else
for (c = 0; c < 8; ++c) {
*d++ = (bits & 0x80) ?
lcd_color_fg : lcd_color_bg;
CONSOLE_COLOR_BLUE, CONSOLE_COLOR_MAGENTA, CONSOLE_COLOR_CYAN,
};
+#if LCD_BPP == LCD_COLOR8
+typedef uchar pix_t;
+#elif LCD_BPP == LCD_COLOR16
+typedef ushort pix_t;
+#elif LCD_BPP == LCD_COLOR24
+typedef ulong pix_t;
+#else
+#error Unsupported pixelformat
+#endif
+
static void test_pattern(void)
{
ushort v_max = panel_info.vl_row;
ushort v_step = (v_max + N_BLK_VERT - 1) / N_BLK_VERT;
ushort h_step = (h_max + N_BLK_HOR - 1) / N_BLK_HOR;
ushort v, h;
- uchar *pix = (uchar *)lcd_base;
+ pix_t *pix = lcd_base;
printf("[LCD] Test Pattern: %d x %d [%d x %d]\n",
h_max, v_max, h_step, v_step);
return *line_length * panel_info.vl_row;
}
-int drv_lcd_init (void)
+int drv_lcd_init(void)
{
struct stdio_dev lcddev;
int rc;
- lcd_base = (void *)(gd->fb_base);
+ lcd_base = (void *)gd->fb_base;
lcd_get_size(&lcd_line_length);
lcd_line_length*panel_info.vl_row);
#endif
/* Paint the logo and retrieve LCD base address */
- debug("[LCD] Drawing the logo...\n");
- lcd_console_address = lcd_logo ();
+ debug("[LCD] Drawing the logo @ %p...\n", lcd_base);
+ lcd_console_address = lcd_logo();
console_col = 0;
console_row = 0;
static int lcd_init(void *lcdbase)
{
/* Initialize the lcd controller */
- debug("[LCD] Initializing LCD frambuffer at %p\n", lcdbase);
+ debug("[LCD] Initializing %ux%ux%u LCD framebuffer at %p\n",
+ panel_info.vl_col, panel_info.vl_row, NBITS(panel_info.vl_bpix),
+ lcdbase);
lcd_ctrl_init(lcdbase);
lcd_is_enabled = 1;
lcd_clear();
- lcd_enable ();
+ lcd_enable();
/* Initialize the console */
console_col = 0;
/*----------------------------------------------------------------------*/
-static int lcd_getbgcolor(void)
+static inline int lcd_getbgcolor(void)
{
return lcd_color_bg;
}
struct pxafb_info *fbi = &panel_info.pxa;
return (ushort *)fbi->palette;
#elif defined(CONFIG_MPC823)
- immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
cpm8xx_t *cp = &(immr->im_cpm);
return (ushort *)&(cp->lcd_cmap[255 * sizeof(ushort)]);
#elif defined(CONFIG_ATMEL_LCD)
uchar *fb;
ushort *fb16;
#if defined(CONFIG_MPC823)
- immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
cpm8xx_t *cp = &(immr->im_cpm);
#endif
bmap += BMP_LOGO_WIDTH;
fb += panel_info.vl_col;
}
- }
- else { /* true color mode */
+ } else if (NBITS(panel_info.vl_bpix) == 16) {
u16 col16;
fb16 = (ushort *)(lcd_base + y * lcd_line_length + x);
for (i = 0; i < BMP_LOGO_HEIGHT; ++i) {
bmap += BMP_LOGO_WIDTH;
fb16 += panel_info.vl_col;
}
+ } else { /* true color mode */
+ u16 col16;
+ u32 *fb32 = lcd_base + y * lcd_line_length + x;
+
+ for (i = 0; i < BMP_LOGO_HEIGHT; i++) {
+ for (j = 0; j < BMP_LOGO_WIDTH; j++) {
+ col16 = bmp_logo_palette[bmap[j] - 16];
+ fb32[j] =
+ ((col16 & 0x000F) << 4) |
+ ((col16 & 0x00F0) << 8) |
+ ((col16 & 0x0F00) << 12);
+ }
+ bmap += BMP_LOGO_WIDTH;
+ fb32 += panel_info.vl_col;
+ }
}
WATCHDOG_RESET();
bmp_image_t *bmp=(bmp_image_t *)bmp_image;
uchar *bmap;
ushort padded_width;
- unsigned long width, height, byte_width;
+ unsigned long width, height;
unsigned long pwidth = panel_info.vl_col;
- unsigned colors, bpix, bmp_bpix;
+ unsigned long long colors;
+ unsigned bpix, bmp_bpix;
if (!bmp || !((bmp->header.signature[0] == 'B') &&
(bmp->header.signature[1] == 'M'))) {
width = le32_to_cpu(bmp->header.width);
height = le32_to_cpu(bmp->header.height);
bmp_bpix = le16_to_cpu(bmp->header.bit_count);
- colors = 1 << bmp_bpix;
+ colors = 1ULL << bmp_bpix;
bpix = NBITS(panel_info.vl_bpix);
return 1;
}
- /* We support displaying 8bpp BMPs on 16bpp LCDs */
- if (bpix != bmp_bpix && !(bmp_bpix == 8 && bpix == 16)) {
+ /* We support displaying 8bpp BMPs on 16bpp or 32bpp LCDs */
+ if (bpix != bmp_bpix && (bmp_bpix != 8 || (bpix != 16 && bpix != 32))) {
printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
bpix,
le16_to_cpu(bmp->header.bit_count));
return 1;
}
- debug("Display-bmp: %d x %d with %d colors\n",
- (int)width, (int)height, (int)colors);
+ debug("Display-bmp: %lu x %lu with %llu colors\n",
+ width, height, colors);
#if !defined(CONFIG_MCC200)
/* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
*/
#if defined(CONFIG_MCC200)
if (bpix == 1) {
- width = ((width + 7) & ~7) >> 3;
- x = ((x + 7) & ~7) >> 3;
- pwidth= ((pwidth + 7) & ~7) >> 3;
+ width = ALIGN(width, 8) >> 3;
+ x = ALIGN(x, 8) >> 3;
+ pwidth= ALIGN(pwidth, 8) >> 3;
}
#endif
- padded_width = (width&0x3) ? ((width&~0x3)+4) : (width);
+ padded_width = ALIGN(width, 4);
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
splash_align_axis(&x, pwidth, width);
splash_align_axis(&y, panel_info.vl_row, height);
#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
+ bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset);
if ((x + width) > pwidth)
- width = pwidth - x;
- if ((y + height) > panel_info.vl_row)
+ width = max(pwidth - x, pwidth);
+ if ((y + height) > panel_info.vl_row) {
height = panel_info.vl_row - y;
+ bmap += (panel_info.vl_row - y) * padded_width;
+ }
bmap = (uchar *)bmp + le32_to_cpu(bmp->header.data_offset);
fb = (uchar *) (lcd_base +
}
#endif
- if (bpix != 16)
- byte_width = width;
- else
- byte_width = width * 2;
-
for (i = 0; i < height; ++i) {
WATCHDOG_RESET();
for (j = 0; j < width; j++) {
- if (bpix != 16) {
- FB_PUT_BYTE(fb, bmap);
- } else {
+ if (bpix == 32) {
+ int i = *bmap++;
+
+ fb[3] = 0; /* T */
+ fb[0] = bmp->color_table[i].blue;
+ fb[1] = bmp->color_table[i].green;
+ fb[2] = bmp->color_table[i].red;
+ fb += sizeof(uint32_t) / sizeof(*fb);
+ } else if (bpix == 16) {
*(uint16_t *)fb = cmap_base[*(bmap++)];
fb += sizeof(uint16_t) / sizeof(*fb);
+ } else {
+ FB_PUT_BYTE(fb, bmap);
}
}
- bmap += (padded_width - width);
- fb -= (byte_width + lcd_line_length);
+ bmap += padded_width - width;
+ fb -= width + lcd_line_length;
}
break;
fb_put_word(&fb, &bmap);
bmap += (padded_width - width) * 2;
- fb -= (width * 2 + lcd_line_length);
+ fb -= width * 2 + lcd_line_length;
}
break;
#endif /* CONFIG_BMP_16BPP */
-
-#if defined(CONFIG_BMP_32BPP)
case 32:
for (i = 0; i < height; ++i) {
+ WATCHDOG_RESET();
for (j = 0; j < width; j++) {
- *(fb++) = *(bmap++);
- *(fb++) = *(bmap++);
- *(fb++) = *(bmap++);
- *(fb++) = *(bmap++);
+ fb[3] = *bmap++; /* T */
+ fb[0] = *bmap++; /* B */
+ fb[1] = *bmap++; /* G */
+ fb[2] = *bmap++; /* R */
+ fb += 4;
}
- fb -= (lcd_line_length + width * (bpix / 8));
+ bmap += (padded_width - width) * 4;
+ fb -= width * 4 + lcd_line_length;
}
break;
-#endif /* CONFIG_BMP_32BPP */
- default:
- break;
};
- lcd_sync();
return 0;
}
#endif
if (do_splash && (s = getenv("splashimage")) != NULL) {
int x = 0, y = 0;
+ char *end;
+
do_splash = 0;
- addr = simple_strtoul (s, NULL, 16);
+ addr = simple_strtoul (s, &end, 16);
+ if (addr == 0 || *end != '\0')
+ return lcd_base;
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
s = getenv("splashpos");
if (s != NULL) {
#endif /* CONFIG_LCD_INFO */
#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
- return (void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length);
+ return lcd_base + BMP_LOGO_HEIGHT * lcd_line_length;
#else
- return (void *)lcd_base;
+ return lcd_base;
#endif /* CONFIG_LCD_LOGO && !CONFIG_LCD_INFO_BELOW_LOGO */
}
else
rc = run_command(lastcommand, flag);
- if (rc <= 0) {
+ if (rc || len < 0) {
/* invalid command or not repeatable, forget it */
- lastcommand[0] = 0;
+ lastcommand[0] = '\0';
}
}
#endif /*CONFIG_SYS_HUSH_PARSER*/
if (prompt)
puts (prompt);
+#ifdef CONFIG_SHOW_ACTIVITY
+ while (!tstc()) {
+ extern void show_activity(int arg);
+ show_activity(0);
+ WATCHDOG_RESET();
+ }
+#endif
rc = cread_line(prompt, p, &len, timeout);
return rc < 0 ? rc : len;
continue;
}
- if (cmd_process(flag, argc, argv, &repeatable, NULL))
+ if (cmd_process(flag, argc, argv, &repeatable, NULL) != CMD_RET_SUCCESS)
rc = -1;
/* Did the user stop this? */
#include <asm/io.h>
#include <nand.h>
-void spl_nand_load_image(void)
+int spl_nand_load_image(void)
{
+ int ret;
struct image_header *header;
int *src __attribute__((unused));
int *dst __attribute__((unused));
nand_init();
/*use CONFIG_SYS_TEXT_BASE as temporary storage area */
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+ header = (struct image_header *)CONFIG_SYS_TEXT_BASE;
#ifdef CONFIG_SPL_OS_BOOT
if (!spl_start_uboot()) {
/*
nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
spl_image.size, (void *)spl_image.load_addr);
nand_deselect();
- return;
+ return 0;
} else {
- puts("The Expected Linux image was not "
- "found. Please check your NAND "
+ printf("The Expected Linux image was not"
+ "found. Please check your NAND"
"configuration.\n");
- puts("Trying to start u-boot now...\n");
+ printf("Trying to start u-boot now...\n");
}
}
#endif
#endif
#endif
/* Load u-boot */
- nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
- spl_parse_image_header(header);
- nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- spl_image.size, (void *)spl_image.load_addr);
+ ret = nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
+ if (ret == 0) {
+ spl_parse_image_header(header);
+ ret = nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ spl_image.size, (void *)spl_image.load_addr);
+ }
nand_deselect();
+ return ret;
}
#include <common.h>
#include <spl.h>
#include <xyzModem.h>
+#include <watchdog.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
ulong store_addr = ~0;
ulong addr = 0;
+loop:
info.mode = xyzModem_ymodem;
ret = xyzModem_stream_open(&info, &err);
-
- if (!ret) {
- while ((res =
- xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
+ if (ret == 0) {
+ while ((res = xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
+ WATCHDOG_RESET();
if (addr == 0)
spl_parse_image_header((struct image_header *)buf);
store_addr = addr + spl_image.load_addr;
size += res;
addr += res;
- memcpy((char *)(store_addr), buf, res);
+ memcpy((char *)store_addr, buf, res);
}
} else {
- printf("spl: ymodem err - %s\n", xyzModem_error(err));
- hang();
+ WATCHDOG_RESET();
+ printf("Retrying...\n");
+ goto loop;
}
xyzModem_stream_close(&err);
#define BSP 0x08
#define NAK 0x15
#define CAN 0x18
-#define EOF 0x1A /* ^Z for DOS officionados */
+#define EOF 0x1A /* ^Z for DOS aficionados */
#define USE_YMODEM_LENGTH
static int
zm_dprintf (char *fmt, ...)
{
- int cur_console;
+ int cur_console __attribute__((unused));
va_list args;
va_start (args, fmt);
#ifdef REDBOOT
CYGACC_CALL_IF_SET_CONSOLE_COMM (cur_console);
#endif
+ return 0;
}
-static void
+static inline void
zm_flush (void)
{
}
return len;
}
-static void
+static inline void
zm_flush (void)
{
#ifdef REDBOOT
static unsigned char zm_buf[2048];
static unsigned char *zm_bp;
-static void
+static inline void
zm_new (void)
{
zm_bp = zm_buf;
}
-static void
+static inline void
zm_save (unsigned char c)
{
*zm_bp++ = c;
}
-static void
+static inline void
zm_dump (int line)
{
zm_dprintf ("Packet at line: %d\n", line);
CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \
-isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS)
-ifdef BUILD_TAG
-CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes \
- -DBUILD_TAG='"$(BUILD_TAG)"'
-else
-CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes
-endif
-
CFLAGS_SSP := $(call cc-option,-fno-stack-protector)
-CFLAGS += $(CFLAGS_SSP)
+
# Some toolchains enable security related warning flags by default,
# but they don't make much sense in the u-boot world, so disable them.
CFLAGS_WARN := $(call cc-option,-Wno-format-nonliteral) \
$(call cc-option,-Wno-format-security)
-CFLAGS += $(CFLAGS_WARN)
+
+CFLAGS := $(CFLAGS_SSP) $(CFLAGS_WARN) $(CPPFLAGS) -Wall -Wstrict-prototypes
+ifdef BUILD_TAG
+ CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"'
+endif
# Report stack usage if supported
CFLAGS_STACK := $(call cc-option,-fstack-usage)
#if defined(CONFIG_CMD_IDE)
{ .name = "ide", .get_dev = ide_get_dev, },
#endif
+#if defined(CONFIG_CMD_PATA)
+ { .name = "pata", .get_dev = pata_get_dev, },
+#endif
#if defined(CONFIG_CMD_SATA)
{.name = "sata", .get_dev = sata_get_dev, },
#endif
--- /dev/null
+ Building & Flashing U-Boot for TX28
+ ===================================
+
+Building U-Boot
+---------------
+
+Unpacking the source
+--------------------
+mkdir u-boot
+cd u-boot
+tar -xjf /cdrom/U-Boot/u-boot-src.tar.bz2
+
+Compiling U-Boot
+----------------
+export ARCH=arm
+export CROSS_COMPILE=arm-926ejs-linux-gnueabi-
+make tx28_config
+make
+
+
+Flashing U-Boot Image
+---------------------
+Load the U-Boot image with sbloader (either the Windows version or the
+Linux version) and use the builtin 'romupdate' command to program the
+image into the flash.
+
+Put the u-boot.sb file in the TFTP server data directory (usually
+/tftpboot).
+
+Load the U-Boot image:
+Enter the following commands at the U-Boot prompt
+set autostart no
+set autoload yes
+set bootfile u-boot.sb
+bootp
+romupdate
+
+Power down the module, make sure the BOOT_MODE jumper (ST3) is removed
+and re-apply power to start from flash.
--- /dev/null
+ Managing the device tree data in U-Boot
+ =======================================
+
+The 'fdt' command can be used to manipulate the device tree (DT) data
+that is passed from U-Boot to Linux.
+
+- 'fdt boardsetup' will trim out some device nodes according to
+ environment settings:
+
+Environment setting removed nodes
+---------------------------------------------
+otg_mode=host usbh1
+otg_mode=device usbotg
+otg_mode=<UNSET> <both of the above> + usbphy
+
+touchpanel=edt-ft5x06 ti,tsc2007
+touchpanel=tsc2007 edt,edt-ft5x06
+touchpanel=<UNSET> <both of the above>
+
+Note: This command is automatically executed when booting Linux via
+ 'run bootm_cmd'.
+
+- 'fdt rm' and 'fdt add' can be used to remove/create additional nodes.
+
+The whole DT data can be saved to and reloaded from the flash partition
+'dtb' (or any other partition):
+ nand erase.part dtb
+ nand write.jffs2 ${fdtaddr} dtb ${fdtsize}
+
+If a DT is loaded from flash which should not be further manipulated
+upon booting Linux, the string 'fdt boardsetup;' should be removed
+from the 'bootm_cmd' environment variable.
+
+Loading the DT data:
+ nand read ${fdtaddr} dtb
--- /dev/null
+ U-Boot for TX28
+ ===============
+
+Building U-Boot
+---------------
+
+Note: There are currently two variants of the TX28 module, that
+ require slightly different U-Boot configurations. They are
+ distinguished through the last digit of the module name. Replace
+ the '?' in the following description with the corresponding
+ number from your TX28 module.
+ E.g. TX28-4031 => 'make tx28-40xx_config'
+
+Unpacking the source
+--------------------
+mkdir u-boot
+cd u-boot
+tar -xjf /cdrom/U-Boot/u-boot-src.tar.bz2
+
+Alternatively you can access the current source via the git repository:
+git://git.kernelconcepts.de/karo-tx-uboot.git master
+
+
+Compiling U-Boot
+----------------
+export ARCH=arm
+export CROSS_COMPILE=arm-cortexa8-linux-gnueabi-
+make tx28-4?xx_config (see above Note!)
+make
+
+
+Flashing U-Boot Image
+---------------------
+If you want to replace a working U-Boot with a new version, you can
+load the new U-Boot image via TFTP and program it like any other flash
+partition with:
+nand erase.part u-boot;nand write.trimffs ${fileaddr} u-boot ${filesize}
+
+If you want to revive a bricked module, U-Boot can be downloaded via
+USB with the 'sbloader' tool in recovery boot mode (Jumper ST3
+on Starterkit-5 baseboard closed). See TX28-U-Boot.pdf for details.
+
+
+U-Boot Features
+---------------
+
+Environment variables:
+
+cpu_clk <CPU freq [MHz]>
+touchpanel {tsc2007|edt-ft5x06}
+otg_mode [host|device|none]
+video_mode <video mode as understood by Linux fb_find_mode() function>
+ e.g.: VGA-1:640x480MR-24@60
+baseboard {stk5-v3|stk5-v5} selects type of baseboard
+splashimage either: memory address (e.g. ${loadaddr}) of a BMP file
+ to be displayed instead of the built-in logo. Since NAND
+ flash is not accessible in a memory mapped fashion,
+ U-Boot will try to load the contents of the flash
+ partition 'logo.bmp' to the address given with
+ 'splashimage'.
+
+ or: the name of an MTD partition, that contains a raw
+ dump of the frame buffer contents which will be loaded
+ to the framebuffer.
+
+splashpos (when 'splashimage' contains a memory address) the
+ position ('x,y') on the screen at which the BMP image
+ will be displayed.
+ Setting splashpos to 'm,m' will center the image on the
+ screen.
+
+Note: Some variables (like 'cpu_clk' or 'splashimage') may render the
+ board unbootable if incorrectly set. Therefore these variables
+ will not be evaluated in case the board has been reset through a
+ watchdog reset or a character is available on the serial console
+ during startup to give the user a chance to recover from this
+ situation.
--- /dev/null
+ U-Boot for TX48
+ ===============
+
+Building U-Boot
+---------------
+
+Unpacking the source
+--------------------
+mkdir u-boot
+cd u-boot
+tar -xjf /cdrom/U-Boot/u-boot-src.tar.bz2
+
+Alternatively you can access the current source via the git repository:
+git://git.kernelconcepts.de/karo-tx-uboot.git master
+
+
+Compiling U-Boot
+----------------
+export ARCH=arm
+export CROSS_COMPILE=arm-cortexa8-linux-gnueabi-
+make tx48_config
+make
+
+
+Flashing U-Boot Image
+---------------------
+If you want to replace a working U-Boot with a new version, you can
+load the new U-Boot image via TFTP and program it like any other flash
+partition with:
+nand erase.part u-boot;nand write.trimffs ${fileaddr} u-boot ${filesize}
+
+If you want to revive a bricked module, U-Boot can be downloaded via
+xmodem protocol over the serial port in recovery boot mode (Jumper ST3
+on Starterkit-5 baseboard closed). See TX48-U-Boot.pdf for details.
+
+
+U-Boot Features
+---------------
+
+Environment variables:
+
+cpu_clk <CPU freq [MHz]>
+touchpanel {tsc2007|edt-ft5x06}
+otg_mode [host|device|none]
+video_mode <video mode as understood by Linux fb_find_mode() function>
+ e.g.: 640x480MR-24@60
+baseboard {stk5-v3|stk5-v5} selects type of baseboard
+splashimage either: memory address (e.g. ${loadaddr}) of a BMP file
+ to be displayed instead of the built-in logo. Since NAND
+ flash is not accessible in a memory mapped fashion,
+ U-Boot will try to load the contents of the flash
+ partition 'logo.bmp' to the address given with
+ 'splashimage'.
+
+ or: the name of an MTD partition, that contains a raw
+ dump of the frame buffer contents which will be loaded
+ to the framebuffer.
+
+splashpos (when 'splashimage' contains a memory address) the
+ position ('x,y') on the screen at which the BMP image
+ will be displayed.
+ Setting splashpos to 'm,m' will center the image on the
+ screen.
+
+Note: Some variables (like 'cpu_clk' or 'splashimage') may render the
+ board unbootable if incorrectly set. Therefore these variables
+ will not be evaluated in case the board has been reset through a
+ watchdog reset or a character is available on the serial console
+ during startup to give the user a chance to recover from this
+ situation.
--- /dev/null
+ U-Boot for TX51
+ ===============
+
+Building U-Boot
+---------------
+
+Note: There are currently six variants of the TX51 module, that
+ require slightly different U-Boot configurations. They are
+ distinguished through the first and last digit of the module
+ name suffix. Replace the '?' in the following description with
+ the corresponding numbers from your TX51 module.
+ E.g. TX51-8021 => 'make tx51-8xx1_config'
+
+Unpacking the source
+--------------------
+mkdir u-boot
+cd u-boot
+tar -xjf /cdrom/U-Boot/u-boot-src.tar.bz2
+
+Alternatively you can access the current source via the git repository:
+git://git.kernelconcepts.de/karo-tx-uboot.git master
+
+
+Compiling U-Boot
+----------------
+export ARCH=arm
+export CROSS_COMPILE=arm-cortexa8-linux-gnueabi-
+make tx51-?xx?_config (see above Note!)
+make
+
+
+Flashing U-Boot Image
+---------------------
+If you want to replace a working U-Boot with a new version, you can
+load the new U-Boot image via TFTP and program it like any other flash
+partition with:
+nand erase.part u-boot;nand write ${fileaddr} u-boot ${filesize}
+
+If you want to revive a bricked module, you can use one of the
+flashtools provided with the BSP to reprogram the flash.
+
+
+U-Boot Features
+---------------
+
+Environment variables:
+
+cpu_clk <CPU freq [MHz]>
+touchpanel {tsc2007|edt-ft5x06}
+otg_mode [host|device|none]
+video_mode <video mode as understood by Linux fb_find_mode() function>
+ e.g.: VGA-1:640x480MR-24@60
+baseboard {stk5-v3|stk5-v5} selects type of baseboard
+ 'stk5-v5' setting disables USB Host mode on USBOTG port.
+ strings not starting in 'stk5' prevent the STK5 specific
+ pad initialization to be done.
+splashimage either: memory address (e.g. ${loadaddr}) of a BMP file
+ to be displayed instead of the built-in logo. Since NAND
+ flash is not accessible in a memory mapped fashion,
+ U-Boot will try to load the contents of the flash
+ partition 'logo.bmp' to the address given with
+ 'splashimage'.
+
+ or: the name of an MTD partition, that contains a raw
+ dump of the frame buffer contents which will be loaded
+ to the framebuffer.
+
+splashpos (when 'splashimage' contains a memory address) the
+ position ('x,y') on the screen at which the BMP image
+ will be displayed.
+ Setting splashpos to 'm,m' will center the image on the
+ screen.
+
+Note: Some variables (like 'cpu_clk' or 'splashimage') may render the
+ board unbootable if incorrectly set. Therefore these variables
+ will not be evaluated in case the board has been reset through a
+ watchdog reset or a character is available on the serial console
+ during startup to give the user a chance to recover from this
+ situation.
--- /dev/null
+ U-Boot for TX53
+ ===============
+
+Building U-Boot
+---------------
+
+Note: There are currently two variants of the TX53 module, that
+ require slightly different U-Boot configurations. They are
+ distinguished through the last digit of the module name. Replace
+ the '?' in the following description with the corresponding
+ number from your TX51 module.
+ E.g. TX53-8031 => 'make tx53-xx31_config'
+
+Unpacking the source
+--------------------
+mkdir u-boot
+cd u-boot
+tar -xjf /cdrom/U-Boot/u-boot-src.tar.bz2
+
+Alternatively you can access the current source via the git repository:
+git://git.kernelconcepts.de/karo-tx-uboot.git master
+
+
+Compiling U-Boot
+----------------
+export ARCH=arm
+export CROSS_COMPILE=arm-cortexa8-linux-gnueabi-
+make tx53-xx3?_config (see above Note!)
+make
+
+
+Flashing U-Boot Image
+---------------------
+If you want to replace a working U-Boot with a new version, you can
+load the new U-Boot image via TFTP and program it like any other flash
+partition with:
+nand erase.part u-boot;nand write ${fileaddr} u-boot ${filesize}
+
+If you want to revive a bricked module, you can use one of the
+flashtools provided with the BSP to reprogram the flash.
+
+
+U-Boot Features
+---------------
+
+Environment variables:
+
+cpu_clk <CPU freq [MHz]>
+touchpanel {tsc2007|edt-ft5x06}
+otg_mode [host|device|none]
+video_mode <video mode as understood by Linux fb_find_mode() function>
+ e.g.: VGA-1:640x480MR-24@60
+baseboard {stk5-v3|stk5-v5} selects type of baseboard
+ 'stk5-v5' setting enables CAN transceiver switch on GPIO4_21 and
+ disables USB Host mode on USBOTG port.
+ strings not starting in 'stk5' prevent the STK5 specific
+ pad initialization to be done.
+splashimage either: memory address (e.g. ${loadaddr}) of a BMP file
+ to be displayed instead of the built-in logo. Since NAND
+ flash is not accessible in a memory mapped fashion,
+ U-Boot will try to load the contents of the flash
+ partition 'logo.bmp' to the address given with
+ 'splashimage'.
+
+ or: the name of an MTD partition, that contains a raw
+ dump of the frame buffer contents which will be loaded
+ to the framebuffer.
+
+splashpos (when 'splashimage' contains a memory address) the
+ position ('x,y') on the screen at which the BMP image
+ will be displayed.
+ Setting splashpos to 'm,m' will center the image on the
+ screen.
+
+Note: Some variables (like 'cpu_clk' or 'splashimage') may render the
+ board unbootable if incorrectly set. Therefore these variables
+ will not be evaluated in case the board has been reset through a
+ watchdog reset or a character is available on the serial console
+ during startup to give the user a chance to recover from this
+ situation.
--- /dev/null
+#ifndef _MXC_ATA_H_
+#define _MXC_ATA_H_
+
+/*
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define MXC_ATA_TIMING_REGS 0x00
+#define MXC_ATA_FIFO_FILL 0x20
+#define MXC_ATA_CONTROL 0x24
+#define MXC_ATA_INT_PEND 0x28
+#define MXC_ATA_INT_EN 0x2C
+#define MXC_ATA_INT_CLEAR 0x30
+#define MXC_ATA_FIFO_ALARM 0x34
+#define MXC_ATA_ADMA_ERROR_STATUS 0x38
+#define MXC_ATA_SYS_DMA_BADDR 0x3C
+#define MXC_ATA_ADMA_SYS_ADDR 0x40
+#define MXC_ATA_BLOCK_COUNT 0x48
+#define MXC_ATA_BURST_LENGTH 0x4C
+#define MXC_ATA_SECTOR_SIZE 0x50
+#define MXC_ATA_DRIVE_DATA 0xA0
+#define MXC_ATA_DFTR 0xA4
+#define MXC_ATA_DSCR 0xA8
+#define MXC_ATA_DSNR 0xAC
+#define MXC_ATA_DCLR 0xB0
+#define MXC_ATA_DCHR 0xB4
+#define MXC_ATA_DDHR 0xB8
+#define MXC_ATA_DCDR 0xBC
+#define MXC_ATA_DRIVE_CONTROL 0xD8
+
+/* bits within MXC_ATA_CONTROL */
+#define MXC_ATA_CTRL_DMA_SRST 0x1000
+#define MXC_ATA_CTRL_DMA_64ADMA 0x800
+#define MXC_ATA_CTRL_DMA_32ADMA 0x400
+#define MXC_ATA_CTRL_DMA_STAT_STOP 0x200
+#define MXC_ATA_CTRL_DMA_ENABLE 0x100
+#define MXC_ATA_CTRL_FIFO_RST_B 0x80
+#define MXC_ATA_CTRL_ATA_RST_B 0x40
+#define MXC_ATA_CTRL_FIFO_TX_EN 0x20
+#define MXC_ATA_CTRL_FIFO_RCV_EN 0x10
+#define MXC_ATA_CTRL_DMA_PENDING 0x08
+#define MXC_ATA_CTRL_DMA_ULTRA 0x04
+#define MXC_ATA_CTRL_DMA_WRITE 0x02
+#define MXC_ATA_CTRL_IORDY_EN 0x01
+
+/* bits within the interrupt control registers */
+#define MXC_ATA_INTR_ATA_INTRQ1 0x80
+#define MXC_ATA_INTR_FIFO_UNDERFLOW 0x40
+#define MXC_ATA_INTR_FIFO_OVERFLOW 0x20
+#define MXC_ATA_INTR_CTRL_IDLE 0x10
+#define MXC_ATA_INTR_ATA_INTRQ2 0x08
+#define MXC_ATA_INTR_DMA_ERR 0x04
+#define MXC_ATA_INTR_DMA_TRANS_OVER 0x02
+
+/* ADMA Addr Descriptor Attribute Filed */
+#define MXC_ADMA_DES_ATTR_VALID 0x01
+#define MXC_ADMA_DES_ATTR_END 0x02
+#define MXC_ADMA_DES_ATTR_INT 0x04
+#define MXC_ADMA_DES_ATTR_SET 0x10
+#define MXC_ADMA_DES_ATTR_TRAN 0x20
+#define MXC_ADMA_DES_ATTR_LINK 0x30
+
+#define PIO_XFER_MODE_0 0
+#define PIO_XFER_MODE_1 1
+#define PIO_XFER_MODE_2 2
+#define PIO_XFER_MODE_3 3
+#define PIO_XFER_MODE_4 4
+
+#define ATA_SECTOR_SIZE 512
+#define MAX_SECTORS 256
+
+#endif /* _IMX_ATA_H_ */
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/regs-apbh.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/dma.h>
+#ifdef DEBUG_
+static inline u32 mxs_readl(void *addr,
+ const char *fn, int ln)
+{
+ u32 val = readl(addr);
+ static void *last_addr;
+ static u32 last_val;
+
+ if (addr != last_addr || last_val != val) {
+ printf("%s@%d: Read %08x from %p\n", fn, ln, val, addr);
+ last_addr = addr;
+ last_val = val;
+ }
+ return val;
+}
+
+static inline void mxs_writel(u32 val, void *addr,
+ const char *name, const char *fn, int ln)
+{
+#if 0
+ printf("%s@%d: Writing %08x to %s[%p]...", fn, ln, val, name, addr);
+#else
+ printf("%s@%d: Writing %08x to %p...", fn, ln, val, addr);
+#endif
+ writel(val, addr);
+ printf(" result: %08x\n", readl(addr));
+}
+
+#undef readl
+#define readl(a) mxs_readl(a, __func__, __LINE__)
+
+#undef writel
+#define writel(v, a) mxs_writel(v, a, #a, __func__, __LINE__)
+#endif
+
+#define pr_dma_flag(c,f) do { if ((c) & MXS_DMA_DESC_##f) printf("%s ", #f); } while (0)
+static inline void dump_dma_desc(struct mxs_dma_desc *desc)
+{
+ struct mxs_dma_cmd *cmd = &desc->cmd;
+
+ printf("DMA desc %p:\n", desc);
+ printf("NXT: %08lx\n", cmd->next);
+ printf("CMD: %08lx - ", cmd->data);
+ printf("CNT: %04lx ", (cmd->data & MXS_DMA_DESC_BYTES_MASK) >> MXS_DMA_DESC_BYTES_OFFSET);
+ printf("PIO: %ld ", (cmd->data & MXS_DMA_DESC_PIO_WORDS_MASK) >> MXS_DMA_DESC_PIO_WORDS_OFFSET);
+ pr_dma_flag(cmd->data, HALT_ON_TERMINATE);
+ pr_dma_flag(cmd->data, WAIT4END);
+ pr_dma_flag(cmd->data, DEC_SEM);
+ pr_dma_flag(cmd->data, NAND_WAIT_4_READY);
+ pr_dma_flag(cmd->data, NAND_LOCK);
+ pr_dma_flag(cmd->data, IRQ);
+ pr_dma_flag(cmd->data, CHAIN);
+ printf("\nMOD: ");
+ switch (cmd->data & MXS_DMA_DESC_COMMAND_MASK) {
+ case MXS_DMA_DESC_COMMAND_NO_DMAXFER:
+ printf("NO_DMA\n");
+ break;
+ case MXS_DMA_DESC_COMMAND_DMA_WRITE:
+ printf("WRITE\n");
+ break;
+ case MXS_DMA_DESC_COMMAND_DMA_READ:
+ printf("READ\n");
+ break;
+ case MXS_DMA_DESC_COMMAND_DMA_SENSE:
+ printf("SENSE\n");
+ }
+ if (cmd->data & MXS_DMA_DESC_PIO_WORDS_MASK) {
+ int pio_words = (cmd->data & MXS_DMA_DESC_PIO_WORDS_MASK) >> MXS_DMA_DESC_PIO_WORDS_OFFSET;
+ int i;
+
+ printf("PIO: ");
+ for (i = 0; i < pio_words; i++) {
+ printf("%08lx ", cmd->pio_words[i]);
+ }
+ printf("\n");
+ }
+}
+
static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
+static struct apbh_regs *apbh_regs = (struct apbh_regs *)MXS_APBH_BASE;
/*
* Test is the DMA channel is valid channel
{
struct mxs_dma_chan *pchan;
- if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
+ if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) {
+ printf("Invalid DMA channel %d\n", channel);
return -EINVAL;
+ }
pchan = mxs_dma_channels + channel;
- if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
+ if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) {
+ printf("DMA channel %d not allocated\n", channel);
return -EINVAL;
+ }
return 0;
}
*/
static int mxs_dma_read_semaphore(int channel)
{
- struct mxs_apbh_regs *apbh_regs =
- (struct mxs_apbh_regs *)MXS_APBH_BASE;
uint32_t tmp;
int ret;
*/
static int mxs_dma_enable(int channel)
{
- struct mxs_apbh_regs *apbh_regs =
- (struct mxs_apbh_regs *)MXS_APBH_BASE;
unsigned int sem;
struct mxs_dma_chan *pchan;
struct mxs_dma_desc *pdesc;
pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
if (pdesc == NULL)
- return -EFAULT;
+ return -EINVAL;
if (pchan->flags & MXS_DMA_FLAGS_BUSY) {
if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN))
} else {
pchan->active_num += pchan->pending_num;
pchan->pending_num = 0;
+#if 1
+ writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
+ &apbh_regs->hw_apbh_ctrl0_clr);
+#endif
writel(mxs_dma_cmd_address(pdesc),
&apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
writel(pchan->active_num,
&apbh_regs->ch[channel].hw_apbh_ch_sema);
- writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
- &apbh_regs->hw_apbh_ctrl0_clr);
}
pchan->flags |= MXS_DMA_FLAGS_BUSY;
static int mxs_dma_disable(int channel)
{
struct mxs_dma_chan *pchan;
- struct mxs_apbh_regs *apbh_regs =
- (struct mxs_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(channel);
pchan = mxs_dma_channels + channel;
- if (!(pchan->flags & MXS_DMA_FLAGS_BUSY))
+ if ((pchan->flags & MXS_DMA_FLAGS_BUSY)) {
+ printf("%s: DMA channel %d busy\n", __func__, channel);
return -EINVAL;
-
+ }
+#if 0
writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
&apbh_regs->hw_apbh_ctrl0_set);
-
- pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
+#endif
pchan->active_num = 0;
pchan->pending_num = 0;
list_splice_init(&pchan->active, &pchan->done);
*/
static int mxs_dma_reset(int channel)
{
- struct mxs_apbh_regs *apbh_regs =
- (struct mxs_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(channel);
*/
static int mxs_dma_enable_irq(int channel, int enable)
{
- struct mxs_apbh_regs *apbh_regs =
- (struct mxs_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(channel);
*/
static int mxs_dma_ack_irq(int channel)
{
- struct mxs_apbh_regs *apbh_regs =
- (struct mxs_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(channel);
*/
static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
{
- struct mxs_apbh_regs *apbh_regs =
- (struct mxs_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(chan);
*/
int mxs_dma_go(int chan)
{
- uint32_t timeout = 10000000;
+ uint32_t timeout = 10000;
int ret;
LIST_HEAD(tmp_desc_list);
*/
void mxs_dma_init(void)
{
- struct mxs_apbh_regs *apbh_regs =
- (struct mxs_apbh_regs *)MXS_APBH_BASE;
-
mxs_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
#ifdef CONFIG_APBH_DMA_BURST8
LIB := $(obj)libgpio.o
+COBJS-y += gpiolib.o
+
+COBJS-$(CONFIG_AM33XX_GPIO) += am33xx_gpio.o
COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o
COBJS-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
--- /dev/null
+/*
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <asm/sizes.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio.h>
+
+struct gpio_regs {
+ unsigned int res1[0x134 / 4];
+ unsigned int oe; /* 0x134 */
+ unsigned int datain; /* 0x138 */
+ unsigned int res2[0x54 / 4];
+ unsigned int cleardataout; /* 0x190 */
+ unsigned int setdataout; /* 0x194 */
+};
+
+static const struct gpio_regs *gpio_base[] = {
+ (struct gpio_regs *)AM33XX_GPIO0_BASE,
+ (struct gpio_regs *)AM33XX_GPIO1_BASE,
+ (struct gpio_regs *)AM33XX_GPIO2_BASE,
+ (struct gpio_regs *)AM33XX_GPIO3_BASE,
+};
+
+static unsigned long gpio_map[ARRAY_SIZE(gpio_base)];
+
+#define MAX_GPIO (ARRAY_SIZE(gpio_base) * 32)
+
+int gpio_request(unsigned gpio, const char *name)
+{
+ if (gpio >= MAX_GPIO)
+ return -EINVAL;
+ if (test_and_set_bit(gpio, gpio_map))
+ return -EBUSY;
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ if (gpio >= MAX_GPIO)
+ return -EINVAL;
+
+ if (test_bit(gpio, gpio_map))
+ __clear_bit(gpio, gpio_map);
+ else
+ printf("ERROR: trying to free unclaimed GPIO %u\n", gpio);
+
+ return 0;
+}
+
+int gpio_set_value(unsigned gpio, int val)
+{
+ int bank = gpio / 32;
+ int mask = 1 << (gpio % 32);
+
+ if (bank >= ARRAY_SIZE(gpio_base))
+ return -EINVAL;
+
+ if (val)
+ writel(mask, &gpio_base[bank]->setdataout);
+ else
+ writel(mask, &gpio_base[bank]->cleardataout);
+ return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ int bank = gpio / 32;
+ int mask = 1 << (gpio % 32);
+
+ if (bank >= ARRAY_SIZE(gpio_base))
+ return -EINVAL;
+
+ writel(readl(&gpio_base[bank]->oe) | mask, &gpio_base[bank]->oe);
+ return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int val)
+{
+ int bank = gpio / 32;
+ int mask = 1 << (gpio % 32);
+
+ if (bank >= ARRAY_SIZE(gpio_base))
+ return -EINVAL;
+
+ gpio_set_value(gpio, val);
+ writel(readl(&gpio_base[bank]->oe) & ~mask, &gpio_base[bank]->oe);
+ return 0;
+}
--- /dev/null
+#include <common.h>
+#include <asm-generic/gpio.h>
+
+int gpio_request_one(unsigned int gpio, enum gpio_flags flags,
+ const char *label)
+{
+ int ret;
+
+ ret = gpio_request(gpio, label);
+ if (ret)
+ return ret;
+
+ if (flags == GPIOF_INPUT)
+ gpio_direction_input(gpio);
+ else if (flags == GPIOF_OUTPUT_INIT_LOW)
+ gpio_direction_output(gpio, 0);
+ else if (flags == GPIOF_OUTPUT_INIT_HIGH)
+ gpio_direction_output(gpio, 1);
+
+ return ret;
+}
+
+int gpio_request_array(const struct gpio *gpios, int count)
+{
+ int ret;
+ int i;
+
+ for (i = 0; i < count; i++) {
+ ret = gpio_request_one(gpios[i].gpio, gpios[i].flags,
+ gpios[i].label);
+ if (ret) {
+ printf("Failed to request GPIO%d (%u of %u): %d\n",
+ gpios[i].gpio, i, count, ret);
+ goto error;
+ }
+ }
+ return 0;
+
+error:
+ while (--i >= 0)
+ gpio_free(gpios[i].gpio);
+
+ return ret;
+}
+
+int gpio_free_array(const struct gpio *gpios, int count)
+{
+ int ret = 0;
+ int i;
+
+ for (i = 0; i < count; i++)
+ ret |= gpio_free(gpios[i].gpio);
+
+ return ret;
+}
MXC_GPIO_DIRECTION_OUT,
};
-#define GPIO_TO_PORT(n) (n / 32)
+#define GPIO_TO_PORT(n) ((n) / 32)
/* GPIO port description */
static unsigned long gpio_ports[] = {
defined(CONFIG_MX53) || defined(CONFIG_MX6)
[3] = GPIO4_BASE_ADDR,
#endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
[4] = GPIO5_BASE_ADDR,
[5] = GPIO6_BASE_ADDR,
#endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
[6] = GPIO7_BASE_ADDR,
#endif
};
struct gpio_regs *regs;
u32 l;
- if (port >= ARRAY_SIZE(gpio_ports))
+ if (port >= ARRAY_SIZE(gpio_ports)) {
+ printf("%s: Invalid GPIO %d\n", __func__, gpio);
return -1;
+ }
gpio &= 0x1f;
struct gpio_regs *regs;
u32 l;
- if (port >= ARRAY_SIZE(gpio_ports))
+ if (port >= ARRAY_SIZE(gpio_ports)) {
+ printf("%s: Invalid GPIO %d\n", __func__, gpio);
return -1;
+ }
gpio &= 0x1f;
struct gpio_regs *regs;
u32 val;
- if (port >= ARRAY_SIZE(gpio_ports))
+ if (port >= ARRAY_SIZE(gpio_ports)) {
+ printf("%s: Invalid GPIO %d\n", __func__, gpio);
return -1;
+ }
gpio &= 0x1f;
regs = (struct gpio_regs *)gpio_ports[port];
- val = (readl(®s->gpio_psr) >> gpio) & 0x01;
-
+ if (readl(®s->gpio_dir) & (1 << gpio)) {
+ printf("WARNING: Reading status of output GPIO_%d_%d\n",
+ port - GPIO_TO_PORT(0), gpio);
+ val = (readl(®s->gpio_dr) >> gpio) & 0x01;
+ } else {
+ val = (readl(®s->gpio_psr) >> gpio) & 0x01;
+ }
return val;
}
int gpio_request(unsigned gpio, const char *label)
{
unsigned int port = GPIO_TO_PORT(gpio);
- if (port >= ARRAY_SIZE(gpio_ports))
+ if (port >= ARRAY_SIZE(gpio_ports)) {
+ printf("%s: Invalid GPIO %d\n", __func__, gpio);
return -1;
+ }
return 0;
}
int gpio_free(unsigned gpio)
{
+ unsigned int port = GPIO_TO_PORT(gpio);
+ if (port >= ARRAY_SIZE(gpio_ports)) {
+ printf("%s: Invalid GPIO %d\n", __func__, gpio);
+ return -1;
+ }
return 0;
}
int gpio_direction_output(unsigned gpio, int value)
{
- int ret = mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
+ int ret = gpio_set_value(gpio, value);
if (ret < 0)
return ret;
- return gpio_set_value(gpio, value);
+ return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
}
--- /dev/null
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_keyb.c
+ *
+ * @brief Driver for the Freescale Semiconductor MXC keypad port.
+ *
+ * The keypad driver is designed as a standard Input driver which interacts
+ * with low level keypad port hardware. Upon opening, the Keypad driver
+ * initializes the keypad port. When the keypad interrupt happens the driver
+ * calles keypad polling timer and scans the keypad matrix for key
+ * press/release. If all key press/release happened it comes out of timer and
+ * waits for key press interrupt. The scancode for key press and release events
+ * are passed to Input subsytem.
+ *
+ * @ingroup keypad
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/keypad.h>
+#include <linux/types.h>
+#include <malloc.h>
+
+/*
+ * * Module header file
+ * */
+#include <mxc_keyb.h>
+
+/*!
+ * Comment KPP_DEBUG to disable debug messages
+ */
+
+#undef KPP_DEBUG
+
+#ifdef KPP_DEBUG
+#define KPP_PRINTF(fmt, args...) printf(fmt , ##args)
+
+static void mxc_kpp_dump_regs()
+{
+ unsigned short t1, t2, t3;
+
+ t1 = __raw_readw(KPCR);
+ t2 = __raw_readw(KPSR);
+ t3 = __raw_readw(KDDR);
+ /*
+ KPP_PRINTF("KPCR=0x%04x, KPSR=0x%04x, KDDR=0x%04x\n",
+ t1, t2, t3);
+ */
+}
+#else
+#define KPP_PRINTF(fmt, args...)
+#endif
+
+static u16 mxc_key_mapping[] = CONFIG_MXC_KEYMAPPING;
+
+/*!
+ * This structure holds the keypad private data structure.
+ */
+static struct keypad_priv kpp_dev;
+
+/*! Indicates if the key pad device is enabled. */
+
+/*! This static variable indicates whether a key event is pressed/released. */
+static unsigned short KPress;
+
+/*! cur_rcmap and prev_rcmap array is used to detect key press and release. */
+static unsigned short *cur_rcmap; /* max 64 bits (8x8 matrix) */
+static unsigned short *prev_rcmap;
+
+/*!
+ * Debounce polling period(10ms) in system ticks.
+ */
+static unsigned short KScanRate = (10 * CONFIG_SYS_HZ) / 1000;
+
+/*!
+ * These arrays are used to store press and release scancodes.
+ */
+static short **press_scancode;
+static short **release_scancode;
+
+static const unsigned short *mxckpd_keycodes;
+static unsigned short mxckpd_keycodes_size;
+
+/*!
+ * These functions are used to configure and the GPIO pins for keypad to
+ * activate and deactivate it.
+ */
+extern void setup_mxc_kpd(void);
+
+/*!
+ * This function is called to scan the keypad matrix to find out the key press
+ * and key release events. Make scancode and break scancode are generated for
+ * key press and key release events.
+ *
+ * The following scanning sequence are done for
+ * keypad row and column scanning,
+ * -# Write 1's to KPDR[15:8], setting column data to 1's
+ * -# Configure columns as totem pole outputs(for quick discharging of keypad
+ * capacitance)
+ * -# Configure columns as open-drain
+ * -# Write a single column to 0, others to 1.
+ * -# Sample row inputs and save data. Multiple key presses can be detected on
+ * a single column.
+ * -# Repeat steps the above steps for remaining columns.
+ * -# Return all columns to 0 in preparation for standby mode.
+ * -# Clear KPKD and KPKR status bit(s) by writing to a 1,
+ * Set the KPKR synchronizer chain by writing "1" to KRSS register,
+ * Clear the KPKD synchronizer chain by writing "1" to KDSC register
+ *
+ * @result Number of key pressed/released.
+ */
+static int mxc_kpp_scan_matrix(void)
+{
+ unsigned short reg_val;
+ int col, row;
+ short scancode = 0;
+ int keycnt = 0; /* How many keys are still pressed */
+
+ /*
+ * wmb() linux kernel function which guarantees orderings in write
+ * operations
+ */
+ /* wmb(); */
+
+ /* save cur keypad matrix to prev */
+ memcpy(prev_rcmap, cur_rcmap, kpp_dev.kpp_rows * sizeof(prev_rcmap[0]));
+ memset(cur_rcmap, 0, kpp_dev.kpp_rows * sizeof(cur_rcmap[0]));
+
+ for (col = 0; col < kpp_dev.kpp_cols; col++) { /* Col */
+ /* 2. Write 1.s to KPDR[15:8] setting column data to 1.s */
+ reg_val = __raw_readw(KPDR);
+ reg_val |= 0xff00;
+ __raw_writew(reg_val, KPDR);
+
+ /*
+ * 3. Configure columns as totem pole outputs(for quick
+ * discharging of keypad capacitance)
+ */
+ reg_val = __raw_readw(KPCR);
+ reg_val &= 0x00ff;
+ __raw_writew(reg_val, KPCR);
+
+ udelay(2);
+
+#ifdef KPP_DEBUG
+ mxc_kpp_dump_regs();
+#endif
+
+ /*
+ * 4. Configure columns as open-drain
+ */
+ reg_val = __raw_readw(KPCR);
+ reg_val |= ((1 << kpp_dev.kpp_cols) - 1) << 8;
+ __raw_writew(reg_val, KPCR);
+
+ /*
+ * 5. Write a single column to 0, others to 1.
+ * 6. Sample row inputs and save data. Multiple key presses
+ * can be detected on a single column.
+ * 7. Repeat steps 2 - 6 for remaining columns.
+ */
+
+ /* Col bit starts at 8th bit in KPDR */
+ reg_val = __raw_readw(KPDR);
+ reg_val &= ~(1 << (8 + col));
+ __raw_writew(reg_val, KPDR);
+
+ /* Delay added to avoid propagating the 0 from column to row
+ * when scanning. */
+
+ udelay(5);
+
+#ifdef KPP_DEBUG
+ mxc_kpp_dump_regs();
+#endif
+
+ /* Read row input */
+ reg_val = __raw_readw(KPDR);
+ for (row = 0; row < kpp_dev.kpp_rows; row++) { /* sample row */
+ if (TEST_BIT(reg_val, row) == 0) {
+ cur_rcmap[row] = BITSET(cur_rcmap[row], col);
+ keycnt++;
+ }
+ }
+ }
+
+ /*
+ * 8. Return all columns to 0 in preparation for standby mode.
+ * 9. Clear KPKD and KPKR status bit(s) by writing to a .1.,
+ * set the KPKR synchronizer chain by writing "1" to KRSS register,
+ * clear the KPKD synchronizer chain by writing "1" to KDSC register
+ */
+ reg_val = 0x00;
+ __raw_writew(reg_val, KPDR);
+ reg_val = __raw_readw(KPDR);
+ reg_val = __raw_readw(KPSR);
+ reg_val |= KBD_STAT_KPKD | KBD_STAT_KPKR | KBD_STAT_KRSS |
+ KBD_STAT_KDSC;
+ __raw_writew(reg_val, KPSR);
+
+#ifdef KPP_DEBUG
+ mxc_kpp_dump_regs();
+#endif
+
+ /* Check key press status change */
+
+ /*
+ * prev_rcmap array will contain the previous status of the keypad
+ * matrix. cur_rcmap array will contains the present status of the
+ * keypad matrix. If a bit is set in the array, that (row, col) bit is
+ * pressed, else it is not pressed.
+ *
+ * XORing these two variables will give us the change in bit for
+ * particular row and column. If a bit is set in XOR output, then that
+ * (row, col) has a change of status from the previous state. From
+ * the diff variable the key press and key release of row and column
+ * are found out.
+ *
+ * If the key press is determined then scancode for key pressed
+ * can be generated using the following statement:
+ * scancode = ((row * 8) + col);
+ *
+ * If the key release is determined then scancode for key release
+ * can be generated using the following statement:
+ * scancode = ((row * 8) + col) + MXC_KEYRELEASE;
+ */
+ for (row = 0; row < kpp_dev.kpp_rows; row++) {
+ unsigned char diff;
+
+ /*
+ * Calculate the change in the keypad row status
+ */
+ diff = prev_rcmap[row] ^ cur_rcmap[row];
+
+ for (col = 0; col < kpp_dev.kpp_cols; col++) {
+ if ((diff >> col) & 0x1) {
+ /* There is a status change on col */
+ if ((prev_rcmap[row] & BITSET(0, col)) == 0) {
+ /*
+ * Previous state is 0, so now
+ * a key is pressed
+ */
+ scancode =
+ ((row * kpp_dev.kpp_cols) +
+ col);
+ KPress = 1;
+ kpp_dev.iKeyState = KStateUp;
+
+ KPP_PRINTF("Press (%d, %d) scan=%d "
+ "Kpress=%d\n",
+ row, col, scancode, KPress);
+ press_scancode[row][col] =
+ (short)scancode;
+ } else {
+ /*
+ * Previous state is not 0, so
+ * now a key is released
+ */
+ scancode =
+ (row * kpp_dev.kpp_cols) +
+ col + MXC_KEYRELEASE;
+ KPress = 0;
+ kpp_dev.iKeyState = KStateDown;
+
+ KPP_PRINTF
+ ("Release (%d, %d) scan=%d Kpress=%d\n",
+ row, col, scancode, KPress);
+ release_scancode[row][col] =
+ (short)scancode;
+ keycnt++;
+ }
+ }
+ }
+ }
+
+ return keycnt;
+}
+
+static int mxc_kpp_reset(void)
+{
+ unsigned short reg_val;
+ int i;
+
+ /*
+ * Stop scanning and wait for interrupt.
+ * Enable press interrupt and disable release interrupt.
+ */
+ __raw_writew(0x00FF, KPDR);
+ reg_val = __raw_readw(KPSR);
+ reg_val |= (KBD_STAT_KPKR | KBD_STAT_KPKD);
+ reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC;
+ __raw_writew(reg_val, KPSR);
+ reg_val |= KBD_STAT_KDIE;
+ reg_val &= ~KBD_STAT_KRIE;
+ __raw_writew(reg_val, KPSR);
+
+#ifdef KPP_DEBUG
+ mxc_kpp_dump_regs();
+#endif
+
+ /*
+ * No more keys pressed... make sure unwanted key codes are
+ * not given upstairs
+ */
+ for (i = 0; i < kpp_dev.kpp_rows; i++) {
+ memset(press_scancode[i], -1,
+ sizeof(press_scancode[0][0]) * kpp_dev.kpp_cols);
+ memset(release_scancode[i], -1,
+ sizeof(release_scancode[0][0]) *
+ kpp_dev.kpp_cols);
+ }
+
+ return 0;
+}
+
+int mxc_kpp_getc(struct kpp_key_info *key_info)
+{
+ int col, row;
+ static int key_cnt;
+ unsigned short reg_val;
+ short scancode = 0;
+
+ reg_val = __raw_readw(KPSR);
+
+ if (!key_cnt) {
+ if (reg_val & KBD_STAT_KPKD) {
+ /*
+ * Disable key press(KDIE status bit) interrupt
+ */
+ reg_val &= ~KBD_STAT_KDIE;
+ __raw_writew(reg_val, KPSR);
+
+#ifdef KPP_DEBUG
+ mxc_kpp_dump_regs();
+#endif
+
+ key_cnt = mxc_kpp_scan_matrix();
+ } else {
+ return 0;
+ }
+ }
+
+ /*
+ * This switch case statement is the
+ * implementation of state machine of debounc
+ * logic for key press/release.
+ * The explaination of state machine is as
+ * follows:
+ *
+ * KStateUp State:
+ * This is in intial state of the state machine
+ * this state it checks for any key presses.
+ * The key press can be checked using the
+ * variable KPress. If KPress is set, then key
+ * press is identified and switches the to
+ * KStateFirstDown state for key press to
+ * debounce.
+ *
+ * KStateFirstDown:
+ * After debounce delay(10ms), if the KPress is
+ * still set then pass scancode generated to
+ * input device and change the state to
+ * KStateDown, else key press debounce is not
+ * satisfied so change the state to KStateUp.
+ *
+ * KStateDown:
+ * In this state it checks for any key release.
+ * If KPress variable is cleared, then key
+ * release is indicated and so, switch the
+ * state to KStateFirstUp else to state
+ * KStateDown.
+ *
+ * KStateFirstUp:
+ * After debounce delay(10ms), if the KPress is
+ * still reset then pass the key release
+ * scancode to input device and change
+ * the state to KStateUp else key release is
+ * not satisfied so change the state to
+ * KStateDown.
+ */
+
+ for (row = 0; row < kpp_dev.kpp_rows; row++) {
+ for (col = 0; col < kpp_dev.kpp_cols; col++) {
+ if ((press_scancode[row][col] != -1)) {
+ /* Still Down, so add scancode */
+ scancode =
+ press_scancode[row][col];
+
+ key_info->val = mxckpd_keycodes[scancode];
+ key_info->evt = KDepress;
+
+ KPP_PRINTF("KStateFirstDown: scan=%d val=%d\n",
+ scancode, mxckpd_keycodes[scancode]);
+ kpp_dev.iKeyState = KStateDown;
+ press_scancode[row][col] = -1;
+
+ goto key_detect;
+ }
+ }
+ }
+
+ for (row = 0; row < kpp_dev.kpp_rows; row++) {
+ for (col = 0; col < kpp_dev.kpp_cols; col++) {
+ if ((release_scancode[row][col] != -1)) {
+ scancode =
+ release_scancode[row][col];
+ scancode =
+ scancode - MXC_KEYRELEASE;
+
+ key_info->val = mxckpd_keycodes[scancode];
+ key_info->evt = KRelease;
+
+ KPP_PRINTF("KStateFirstUp: scan=%d val=%d\n",
+ scancode, mxckpd_keycodes[scancode]);
+
+ kpp_dev.iKeyState = KStateUp;
+ release_scancode[row][col] = -1;
+
+ goto key_detect;
+ }
+ }
+ }
+
+ return 0;
+
+key_detect:
+ /* udelay(KScanRate); */
+ key_cnt = mxc_kpp_scan_matrix();
+
+ if (0 == key_cnt)
+ mxc_kpp_reset();
+ return 1;
+}
+
+/*!
+ * This function is called to free the allocated memory for local arrays
+ */
+static void mxc_kpp_free_allocated(void)
+{
+ int i;
+
+ if (press_scancode) {
+ for (i = 0; i < kpp_dev.kpp_rows; i++) {
+ if (press_scancode[i])
+ free(press_scancode[i]);
+ }
+ free(press_scancode);
+ }
+
+ if (release_scancode) {
+ for (i = 0; i < kpp_dev.kpp_rows; i++) {
+ if (release_scancode[i])
+ free(release_scancode[i]);
+ }
+ free(release_scancode);
+ }
+
+ if (cur_rcmap)
+ free(cur_rcmap);
+
+ if (prev_rcmap)
+ free(prev_rcmap);
+}
+
+/*!
+ * This function is called during the driver binding process.
+ *
+ * @param pdev the device structure used to store device specific
+ * information that is used by the suspend, resume and remove
+ * functions.
+ *
+ * @return The function returns 0 on successful registration. Otherwise returns
+ * specific error code.
+ */
+int mxc_kpp_init(void)
+{
+ int i;
+ int retval;
+ unsigned int reg_val;
+
+ kpp_dev.kpp_cols = CONFIG_MXC_KPD_COLMAX;
+ kpp_dev.kpp_rows = CONFIG_MXC_KPD_ROWMAX;
+
+ /* clock and IOMUX configuration for keypad */
+ setup_mxc_kpd();
+
+ /* Configure keypad */
+
+ /* Enable number of rows in keypad (KPCR[7:0])
+ * Configure keypad columns as open-drain (KPCR[15:8])
+ *
+ * Configure the rows/cols in KPP
+ * LSB nibble in KPP is for 8 rows
+ * MSB nibble in KPP is for 8 cols
+ */
+ reg_val = __raw_readw(KPCR);
+ reg_val |= (1 << kpp_dev.kpp_rows) - 1; /* LSB */
+ reg_val |= ((1 << kpp_dev.kpp_cols) - 1) << 8; /* MSB */
+ __raw_writew(reg_val, KPCR);
+
+ /* Write 0's to KPDR[15:8] */
+ reg_val = __raw_readw(KPDR);
+ reg_val &= 0x00ff;
+ __raw_writew(reg_val, KPDR);
+
+ /* Configure columns as output,
+ * rows as input (KDDR[15:0]) */
+ reg_val = __raw_readw(KDDR);
+ reg_val |= 0xff00;
+ reg_val &= 0xff00;
+ __raw_writew(reg_val, KDDR);
+
+ /* Clear the KPKD Status Flag
+ * and Synchronizer chain. */
+ reg_val = __raw_readw(KPSR);
+ reg_val &= ~(KBD_STAT_KPKR | KBD_STAT_KPKD);
+ reg_val |= KBD_STAT_KPKD;
+ reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC;
+ __raw_writew(reg_val, KPSR);
+ /* Set the KDIE control bit, and clear the KRIE
+ * control bit (avoid false release events). */
+ reg_val |= KBD_STAT_KDIE;
+ reg_val &= ~KBD_STAT_KRIE;
+ __raw_writew(reg_val, KPSR);
+
+#ifdef KPP_DEBUG
+ mxc_kpp_dump_regs();
+#endif
+
+ mxckpd_keycodes = mxc_key_mapping;
+ mxckpd_keycodes_size = kpp_dev.kpp_cols * kpp_dev.kpp_rows;
+
+ if ((mxckpd_keycodes == (void *)0)
+ || (mxckpd_keycodes_size == 0)) {
+ retval = -ENODEV;
+ goto err;
+ }
+
+ /* allocate required memory */
+ press_scancode = (short **)malloc(kpp_dev.kpp_rows * sizeof(press_scancode[0]));
+ release_scancode = (short **)malloc(kpp_dev.kpp_rows * sizeof(release_scancode[0]));
+
+ if (!press_scancode || !release_scancode) {
+ retval = -ENOMEM;
+ goto err;
+ }
+
+ for (i = 0; i < kpp_dev.kpp_rows; i++) {
+ press_scancode[i] = (short *)malloc(kpp_dev.kpp_cols
+ * sizeof(press_scancode[0][0]));
+ release_scancode[i] =
+ (short *)malloc(kpp_dev.kpp_cols * sizeof(release_scancode[0][0]));
+
+ if (!press_scancode[i] || !release_scancode[i]) {
+ retval = -ENOMEM;
+ goto err;
+ }
+ }
+
+ cur_rcmap =
+ (unsigned short *)malloc(kpp_dev.kpp_rows * sizeof(cur_rcmap[0]));
+ prev_rcmap =
+ (unsigned short *)malloc(kpp_dev.kpp_rows * sizeof(prev_rcmap[0]));
+
+ if (!cur_rcmap || !prev_rcmap) {
+ retval = -ENOMEM;
+ goto err;
+ }
+
+ for (i = 0; i < kpp_dev.kpp_rows; i++) {
+ memset(press_scancode[i], -1,
+ sizeof(press_scancode[0][0]) * kpp_dev.kpp_cols);
+ memset(release_scancode[i], -1,
+ sizeof(release_scancode[0][0]) * kpp_dev.kpp_cols);
+ }
+ memset(cur_rcmap, 0, kpp_dev.kpp_rows * sizeof(cur_rcmap[0]));
+ memset(prev_rcmap, 0, kpp_dev.kpp_rows * sizeof(prev_rcmap[0]));
+
+ return 0;
+
+err:
+ mxc_kpp_free_allocated();
+ return retval;
+}
+
COBJS-$(CONFIG_ALI152X) += ali512x.o
COBJS-$(CONFIG_DS4510) += ds4510.o
COBJS-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
+COBJS-$(CONFIG_IMX_IIM) += imx_iim.o
COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
COBJS-$(CONFIG_NS87308) += ns87308.o
--- /dev/null
+/*
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Terry Lv
+ *
+ * Copyright 2007, Freescale Semiconductor, Inc
+ * Andy Fleming
+ *
+ * Based vaguely on the pxa mmc code:
+ * (C) Copyright 2003
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * Adapted for U-Boot version 2012-04-01 by Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <net.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/imx_iim.h>
+
+static struct iim_regs *imx_iim = (void *)IMX_IIM_BASE;
+
+/* slen - string length, e.g.: 23 -> slen=2; abcd -> slen=4 */
+/* only convert hex value as string input. so "12" is 0x12. */
+static u32 quick_atoi(char *a, u32 slen)
+{
+ u32 i, num = 0, digit;
+
+ for (i = 0; i < slen; i++) {
+ if (a[i] >= '0' && a[i] <= '9') {
+ digit = a[i] - '0';
+ } else if (a[i] >= 'a' && a[i] <= 'f') {
+ digit = a[i] - 'a' + 10;
+ } else if (a[i] >= 'A' && a[i] <= 'F') {
+ digit = a[i] - 'A' + 10;
+ } else {
+ printf("ERROR: %c\n", a[i]);
+ return -1;
+ }
+ num = (num * 16) + digit;
+ }
+
+ return num;
+}
+
+static void fuse_op_start(void)
+{
+ /* Do not generate interrupt */
+ writel(0, &imx_iim->statm);
+ /* clear the status bits and error bits */
+ writel(0x3, &imx_iim->stat);
+ writel(0xfe, &imx_iim->err);
+}
+
+/*
+ * The action should be either:
+ * POLL_FUSE_PRGD
+ * or:
+ * POLL_FUSE_SNSD
+ */
+static s32 poll_fuse_op_done(s32 action)
+{
+ u32 status, error;
+
+ if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
+ printf("%s(%d) invalid operation\n", __func__, action);
+ return -1;
+ }
+
+ /* Poll busy bit till it is NOT set */
+ while ((readl(&imx_iim->stat) & IIM_STAT_BUSY) != 0)
+ ;
+
+ /* Test for successful write */
+ status = readl(&imx_iim->stat);
+ error = readl(&imx_iim->err);
+
+ if ((status & action) != 0 && \
+ (error & (action >> IIM_ERR_SHIFT)) == 0) {
+ if (error) {
+ printf("Even though the operation"
+ "seems successful...\n");
+ printf("There are some error(s) "
+ "at addr=%p: 0x%x\n",
+ &imx_iim->err, error);
+ }
+ return 0;
+ }
+ printf("%s(%d) failed\n", __func__, action);
+ printf("status address=%p, value=0x%x\n",
+ &imx_iim->stat, status);
+ printf("There are some error(s) at addr=%p: 0x%x\n",
+ &imx_iim->err, error);
+ return -1;
+}
+
+static u32 sense_fuse(s32 bank, s32 row, s32 bit)
+{
+ s32 addr, addr_l, addr_h;
+ void *reg_addr;
+
+ fuse_op_start();
+
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
+
+#ifdef IIM_FUSE_DEBUG
+ printf("%s: addr_h=0x%x, addr_l=0x%x\n",
+ __func__, addr_h, addr_l);
+#endif
+ writel(addr_h, &imx_iim->ua);
+ writel(addr_l, &imx_iim->la);
+
+ /* Start sensing */
+ writel(0x8, &imx_iim->fctl);
+ if (poll_fuse_op_done(POLL_FUSE_SNSD) != 0) {
+ printf("%s(bank: %d, row: %d, bit: %d failed\n",
+ __func__, bank, row, bit);
+ }
+ reg_addr = &imx_iim->sdat;
+
+ return readl(reg_addr);
+}
+
+int iim_read(int bank, char row)
+{
+ u32 fuse_val;
+ s32 err = 0;
+
+ printf("Read fuse at bank:%d row:%d\n", bank, row);
+ fuse_val = sense_fuse(bank, row, 0);
+ printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, fuse_val);
+
+ return err;
+}
+
+/* Blow fuses based on the bank, row and bit positions (all 0-based)
+*/
+static s32 fuse_blow_bit(s32 bank, s32 row, s32 bit)
+{
+ int addr, addr_l, addr_h, ret = -1;
+
+ fuse_op_start();
+
+ /* Disable IIM Program Protect */
+ writel(0xaa, &imx_iim->preg_p);
+
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
+
+#ifdef IIM_FUSE_DEBUG
+ printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l);
+#endif
+
+ writel(addr_h, &imx_iim->ua);
+ writel(addr_l, &imx_iim->la);
+
+ /* Start Programming */
+ writel(0x31, &imx_iim->fctl);
+ if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0)
+ ret = 0;
+
+ /* Enable IIM Program Protect */
+ writel(0x0, &imx_iim->preg_p);
+
+ return ret;
+}
+
+static void fuse_blow_row(s32 bank, s32 row, s32 value)
+{
+ u32 reg, i;
+
+ /* enable fuse blown */
+ reg = readl(CCM_BASE_ADDR + 0x64);
+ reg |= 0x10;
+ writel(reg, CCM_BASE_ADDR + 0x64);
+
+ for (i = 0; i < 8; i++) {
+ if (((value >> i) & 0x1) == 0)
+ continue;
+ if (fuse_blow_bit(bank, row, i) != 0) {
+ printf("fuse_blow_bit(bank: %d, row: %d, "
+ "bit: %d failed\n",
+ bank, row, i);
+ }
+ }
+ reg &= ~0x10;
+ writel(reg, CCM_BASE_ADDR + 0x64);
+}
+
+int iim_blow(int bank, int row, int val)
+{
+ u32 fuse_val, err = 0;
+
+ printf("Blowing fuse at bank:%d row:%d value:%d\n",
+ bank, row, val);
+ fuse_blow_row(bank, row, val);
+ fuse_val = sense_fuse(bank, row, 0);
+ printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, fuse_val);
+
+ return err;
+}
+
+int iim_blow_func(char *func_name, char *func_val)
+{
+ u32 value, i;
+ char *s;
+ char val[3];
+ s32 err = 0;
+
+ if (strcmp(func_name, "scc") == 0) {
+ /* fuse_blow scc
+ C3D153EDFD2EA9982226EF5047D3B9A0B9C7138EA87C028401D28C2C2C0B9AA2 */
+ printf("Ready to burn SCC fuses\n");
+ s = func_val;
+ for (i = 0; ; ++i) {
+ memcpy(val, s, 2);
+ val[2] = '\0';
+ value = quick_atoi(val, 2);
+ /* printf("fuse_blow_row(2, %d, value=0x%x)\n",
+ i, value); */
+ fuse_blow_row(2, i, value);
+
+ if (*(++s) == '\0') {
+ printf("ERROR: Odd string input\n");
+ err = -1;
+ break;
+ }
+ if (*(++s) == '\0') {
+ printf("Successful\n");
+ break;
+ }
+ }
+ } else if (strcmp(func_name, "srk") == 0) {
+ /* fuse_blow srk
+ 418bccd09b53bee1ab59e2662b3c7877bc0094caee201052add49be8780dff95 */
+ printf("Ready to burn SRK key fuses\n");
+ s = func_val;
+ for (i = 0; ; ++i) {
+ memcpy(val, s, 2);
+ val[2] = '\0';
+ value = quick_atoi(val, 2);
+ if (i == 0) {
+ /* 0x41 goes to SRK_HASH[255:248],
+ * bank 1, row 1 */
+ fuse_blow_row(1, 1, value);
+ } else {
+ /* 0x8b in SRK_HASH[247:240] bank 3, row 1 */
+ /* 0xcc in SRK_HASH[239:232] bank 3, row 2 */
+ /* ... */
+ fuse_blow_row(3, i, value);
+
+ if (*(++s) == '\0') {
+ printf("ERROR: Odd string input\n");
+ err = -1;
+ break;
+ }
+ if (*(++s) == '\0') {
+ printf("Successful\n");
+ break;
+ }
+ }
+ }
+ } else if (strcmp(func_name, "fecmac") == 0) {
+ u8 ea[6] = { 0 };
+
+ if (func_val == NULL) {
+ /* Read the Mac address and print it */
+ imx_get_mac_from_fuse(0, ea);
+
+ printf("FEC MAC address: ");
+ printf("0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n\n",
+ ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);
+
+ return 0;
+ }
+
+ eth_parse_enetaddr(func_val, ea);
+ if (!is_valid_ether_addr(ea)) {
+ printf("Error: invalid mac address parameter!\n");
+ err = -1;
+ } else {
+ for (i = 0; i < 6; ++i)
+ fuse_blow_row(1, i + 9, ea[i]);
+ }
+ } else {
+ printf("This command is not supported\n");
+ }
+
+ return err;
+}
+
+
--- /dev/null
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <pmic.h>
+#include <dialog_pmic.h>
+
+int pmic_dialog_init(void)
+{
+ struct pmic *p = get_pmic();
+ static const char name[] = "DIALOG_PMIC";
+
+ p->name = name;
+ p->number_of_regs = DIALOG_NUM_OF_REGS;
+
+ p->interface = PMIC_I2C;
+ p->hw.i2c.addr = CONFIG_SYS_DIALOG_PMIC_I2C_ADDR;
+ p->hw.i2c.tx_num = 1;
+ p->bus = I2C_PMIC;
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pmic.h>
+#include <max8997_pmic.h>
+
+int pmic_init(void)
+{
+ struct pmic *p = get_pmic();
+ static const char name[] = "MAX8997_PMIC";
+
+ puts("Board PMIC init\n");
+
+ p->name = name;
+ p->interface = PMIC_I2C;
+ p->number_of_regs = PMIC_NUM_OF_REGS;
+ p->hw.i2c.addr = MAX8997_I2C_ADDR;
+ p->hw.i2c.tx_num = 1;
+ p->bus = I2C_PMIC;
+
+ return 0;
+}
esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
{
struct fsl_esdhc_cfg *cfg = mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc *regs = cfg->esdhc_base;
uint blocks;
char *buffer;
uint databuf;
uint size;
- uint irqstat;
uint timeout;
+ int wml = esdhc_read32(®s->wml);
if (data->flags & MMC_DATA_READ) {
+ wml &= WML_RD_WML_MASK;
blocks = data->blocks;
buffer = data->dest;
while (blocks) {
timeout = PIO_TIMEOUT;
size = data->blocksize;
- irqstat = esdhc_read32(®s->irqstat);
- while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
- && --timeout);
- if (timeout <= 0) {
- printf("\nData Read Failed in PIO Mode.");
- return;
- }
- while (size && (!(irqstat & IRQSTAT_TC))) {
- udelay(100); /* Wait before last byte transfer complete */
- irqstat = esdhc_read32(®s->irqstat);
- databuf = in_le32(®s->datport);
- *((uint *)buffer) = databuf;
- buffer += 4;
- size -= 4;
+ while (size &&
+ !(esdhc_read32(®s->irqstat) & IRQSTAT_TC)) {
+ int i;
+ u32 prsstat;
+
+ while (!((prsstat = esdhc_read32(®s->prsstat)) &
+ PRSSTAT_BREN) && --timeout)
+ /* NOP */;
+ if (!(prsstat & PRSSTAT_BREN)) {
+ printf("%s: Data Read Failed in PIO Mode\n",
+ __func__);
+ return;
+ }
+ for (i = 0; i < wml && size; i++) {
+ databuf = in_le32(®s->datport);
+ memcpy(buffer, &databuf, sizeof(databuf));
+ buffer += 4;
+ size -= 4;
+ }
}
blocks--;
}
} else {
+ wml = (wml & WML_WR_WML_MASK) >> 16;
blocks = data->blocks;
- buffer = (char *)data->src;
+ buffer = (char *)data->src; /* cast away 'const' */
while (blocks) {
timeout = PIO_TIMEOUT;
size = data->blocksize;
- irqstat = esdhc_read32(®s->irqstat);
- while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
- && --timeout);
- if (timeout <= 0) {
- printf("\nData Write Failed in PIO Mode.");
- return;
- }
- while (size && (!(irqstat & IRQSTAT_TC))) {
- udelay(100); /* Wait before last byte transfer complete */
- databuf = *((uint *)buffer);
- buffer += 4;
- size -= 4;
- irqstat = esdhc_read32(®s->irqstat);
- out_le32(®s->datport, databuf);
+ while (size &&
+ !(esdhc_read32(®s->irqstat) & IRQSTAT_TC)) {
+ int i;
+ u32 prsstat;
+
+ while (!((prsstat = esdhc_read32(®s->prsstat)) &
+ PRSSTAT_BWEN) && --timeout)
+ /* NOP */;
+ if (!(prsstat & PRSSTAT_BWEN)) {
+ printf("%s: Data Write Failed in PIO Mode\n",
+ __func__);
+ return;
+ }
+ for (i = 0; i < wml && size; i++) {
+ memcpy(&databuf, buffer, sizeof(databuf));
+ out_le32(®s->datport, databuf);
+ buffer += 4;
+ size -= 4;
+ }
}
blocks--;
}
static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
{
int timeout;
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_cfg *cfg = mmc->priv;
+ struct fsl_esdhc *regs = cfg->esdhc_base;
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
uint wml_value;
- wml_value = data->blocksize/4;
+ wml_value = data->blocksize / 4;
if (data->flags & MMC_DATA_READ) {
if (wml_value > WML_RD_WML_MAX)
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
esdhc_write32(®s->dsaddr, (u32)data->dest);
} else {
- flush_dcache_range((ulong)data->src,
- (ulong)data->src+data->blocks
- *data->blocksize);
-
if (wml_value > WML_WR_WML_MAX)
wml_value = WML_WR_WML_MAX_VAL;
if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
- printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
- return TIMEOUT;
+ printf("The SD card is locked. Can not write to a locked card.\n");
+ return UNUSABLE_ERR;
}
+ flush_dcache_range((unsigned long)data->src,
+ (unsigned long)data->src + data->blocks * data->blocksize);
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
wml_value << 16);
esdhc_write32(®s->dsaddr, (u32)data->src);
#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
if (!(data->flags & MMC_DATA_READ)) {
if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
- printf("\nThe SD card is locked. "
- "Can not write to a locked card.\n\n");
- return TIMEOUT;
+ printf("The SD card is locked. Can not write to a locked card.\n");
+ return UNUSABLE_ERR;
}
esdhc_write32(®s->dsaddr, (u32)data->src);
- } else
+ } else {
esdhc_write32(®s->dsaddr, (u32)data->dest);
+ }
#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
- esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
+ esdhc_write32(®s->blkattr, (data->blocks << 16) | data->blocksize);
/* Calculate the timeout period for data transactions */
/*
* => timeout + 13 = log2(mmc->tran_speed/4) + 1
* => timeout + 13 = fls(mmc->tran_speed/4)
*/
- timeout = fls(mmc->tran_speed/4);
+ timeout = fls(mmc->tran_speed / 4);
timeout -= 13;
if (timeout > 14)
timeout = 14;
-
- if (timeout < 0)
+ else if (timeout < 0)
timeout = 0;
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
if ((timeout == 4) || (timeout == 8) || (timeout == 12))
timeout++;
#endif
-
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
return 0;
}
-static void check_and_invalidate_dcache_range
- (struct mmc_cmd *cmd,
- struct mmc_data *data) {
- unsigned start = (unsigned)data->dest ;
+static void check_and_invalidate_dcache_range(struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ unsigned start = (unsigned)data->dest;
unsigned size = roundup(ARCH_DMA_MINALIGN,
- data->blocks*data->blocksize);
- unsigned end = start+size ;
+ data->blocks * data->blocksize);
+ unsigned end = start + size;
+
invalidate_dcache_range(start, end);
}
+
/*
* Sends a command out on the bus. Takes the mmc pointer,
* a command pointer, and an optional data pointer.
{
uint xfertyp;
uint irqstat;
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_cfg *cfg = mmc->priv;
+ volatile struct fsl_esdhc *regs = cfg->esdhc_base;
+ unsigned long start;
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
return 0;
#endif
-
esdhc_write32(®s->irqstat, -1);
sync();
+ start = get_timer_masked();
/* Wait for the bus to be idle */
while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
- (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
- ;
+ (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) {
+ if (get_timer(start) > CONFIG_SYS_HZ) {
+ printf("%s: Timeout waiting for bus idle\n", __func__);
+ return TIMEOUT;
+ }
+ }
- while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
- ;
+ start = get_timer_masked();
+ while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) {
+ if (get_timer(start) > CONFIG_SYS_HZ)
+ return TIMEOUT;
+ }
/* Wait at least 8 SD clock cycles before the next command */
/*
int err;
err = esdhc_setup_data(mmc, data);
- if(err)
+ if (err)
return err;
}
esdhc_write32(®s->cmdarg, cmd->cmdarg);
#if defined(CONFIG_FSL_USDHC)
esdhc_write32(®s->mixctrl,
- (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
+ (esdhc_read32(®s->mixctrl) & ~0x7f) | (xfertyp & 0x7F));
esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
#else
esdhc_write32(®s->xfertyp, xfertyp);
/* Mask all irqs */
esdhc_write32(®s->irqsigen, 0);
+ start = get_timer_masked();
/* Wait for the command to complete */
- while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
- ;
+ while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) {
+ if (get_timer(start) > CONFIG_SYS_HZ) {
+ printf("%s: Timeout waiting for cmd completion\n", __func__);
+ return TIMEOUT;
+ }
+ }
if (data && (data->flags & MMC_DATA_READ))
check_and_invalidate_dcache_range(cmd, data);
if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) {
esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
SYSCTL_RSTC);
- while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
- ;
+ start = get_timer_masked();
+ while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) {
+ if (get_timer(start) > CONFIG_SYS_HZ)
+ return TIMEOUT;
+ }
if (data) {
esdhc_write32(®s->sysctl,
esdhc_read32(®s->sysctl) |
SYSCTL_RSTD);
- while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
- ;
+ start = get_timer_masked();
+ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) {
+ if (get_timer(start) > CONFIG_SYS_HZ)
+ return TIMEOUT;
+ }
}
}
#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
esdhc_pio_read_write(mmc, data);
#else
+ unsigned long start = get_timer_masked();
+ unsigned long data_timeout = data->blocks *
+ data->blocksize * 100 / mmc->bus_width /
+ (mmc->tran_speed / CONFIG_SYS_HZ) + CONFIG_SYS_HZ;
+
do {
irqstat = esdhc_read32(®s->irqstat);
- if (irqstat & IRQSTAT_DTOE)
+ if (irqstat & IRQSTAT_DTOE) {
+ printf("MMC/SD data %s timeout\n",
+ data->flags & MMC_DATA_READ ?
+ "read" : "write");
return TIMEOUT;
+ }
- if (irqstat & DATA_ERR)
+ if (irqstat & DATA_ERR) {
+ printf("MMC/SD data error\n");
return COMM_ERR;
+ }
+
+ if (get_timer(start) > data_timeout) {
+ printf("MMC/SD timeout waiting for %s xfer completion\n",
+ data->flags & MMC_DATA_READ ?
+ "read" : "write");
+ return TIMEOUT;
+ }
} while (!(irqstat & IRQSTAT_TC) &&
- (esdhc_read32(®s->prsstat) & PRSSTAT_DLA));
+ (esdhc_read32(®s->prsstat) & PRSSTAT_DLA));
+
+ check_and_invalidate_dcache_range(cmd, data);
#endif
}
- esdhc_write32(®s->irqstat, -1);
+ esdhc_write32(®s->irqstat, irqstat);
return 0;
}
static void set_sysctl(struct mmc *mmc, uint clock)
{
int div, pre_div;
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_cfg *cfg = mmc->priv;
+ volatile struct fsl_esdhc *regs = cfg->esdhc_base;
int sdhc_clk = cfg->sdhc_clk;
uint clk;
static void esdhc_set_ios(struct mmc *mmc)
{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_cfg *cfg = mmc->priv;
+ struct fsl_esdhc *regs = cfg->esdhc_base;
/* Set the clock speed */
set_sysctl(mmc, mmc->clock);
static int esdhc_init(struct mmc *mmc)
{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_cfg *cfg = mmc->priv;
+ struct fsl_esdhc *regs = cfg->esdhc_base;
int timeout = 1000;
/* Reset the entire host controller */
static int esdhc_getcd(struct mmc *mmc)
{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ struct fsl_esdhc_cfg *cfg = mmc->priv;
+ struct fsl_esdhc *regs = cfg->esdhc_base;
int timeout = 1000;
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
u32 caps, voltage_caps;
if (!cfg)
- return -1;
+ return -EINVAL;
- mmc = malloc(sizeof(struct mmc));
+ mmc = kzalloc(sizeof(struct mmc), GFP_KERNEL);
+ if (!mmc)
+ return -ENOMEM;
sprintf(mmc->name, "FSL_SDHC");
- regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ regs = cfg->esdhc_base;
/* First reset the eSDHC controller */
esdhc_reset(regs);
#endif
if ((mmc->voltages & voltage_caps) == 0) {
printf("voltage not supported by controller\n");
- return -1;
+ return -EINVAL;
}
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
mmc->f_min = 400000;
- mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);
+ mmc->f_max = MIN(cfg->sdhc_clk, 52000000);
mmc->b_max = 0;
mmc_register(mmc);
{
struct fsl_esdhc_cfg *cfg;
- cfg = malloc(sizeof(struct fsl_esdhc_cfg));
- memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
- cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+ cfg = kzalloc(sizeof(struct fsl_esdhc_cfg), GFP_KERNEL);
+ if (!cfg)
+ return -ENOMEM;
+ cfg->esdhc_base = (void __iomem *)CONFIG_SYS_FSL_ESDHC_ADDR;
cfg->sdhc_clk = gd->arch.sdhc_clk;
return fsl_esdhc_initialize(bis, cfg);
}
--- /dev/null
+/*
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Terry Lv
+ *
+ * Copyright 2007, Freescale Semiconductor, Inc
+ * Andy Fleming
+ *
+ * Based vaguely on the pxa mmc code:
+ * (C) Copyright 2003
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <asm/arch/regs-ssp.h>
+#include <asm/arch/regs-clkctrl.h>
+#include <imx_ssp_mmc.h>
+
+#undef IMX_SSP_MMC_DEBUG
+
+static inline int ssp_mmc_read(struct mmc *mmc, uint reg)
+{
+ struct imx_ssp_mmc_cfg *cfg = (struct imx_ssp_mmc_cfg *)mmc->priv;
+ return REG_RD(cfg->ssp_mmc_base, reg);
+}
+
+static inline void ssp_mmc_write(struct mmc *mmc, uint reg, uint val)
+{
+ struct imx_ssp_mmc_cfg *cfg = (struct imx_ssp_mmc_cfg *)mmc->priv;
+ REG_WR(cfg->ssp_mmc_base, reg, val);
+}
+
+static inline void mdelay(unsigned long msec)
+{
+ unsigned long i;
+ for (i = 0; i < msec; i++)
+ udelay(1000);
+}
+
+static inline void sdelay(unsigned long sec)
+{
+ unsigned long i;
+ for (i = 0; i < sec; i++)
+ mdelay(1000);
+}
+
+/*
+ * Sends a command out on the bus. Takes the mmc pointer,
+ * a command pointer, and an optional data pointer.
+ */
+static int
+ssp_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+{
+ int i;
+
+#ifdef IMX_SSP_MMC_DEBUG
+ printf("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
+#endif
+
+ /* Check bus busy */
+ i = 0;
+ while (ssp_mmc_read(mmc, HW_SSP_STATUS) & (BM_SSP_STATUS_BUSY |
+ BM_SSP_STATUS_DATA_BUSY | BM_SSP_STATUS_CMD_BUSY)) {
+ mdelay(1);
+ i++;
+ if (i == 1000) {
+ printf("MMC%d: Bus busy timeout!\n",
+ mmc->block_dev.dev);
+ return TIMEOUT;
+ }
+ }
+
+ /* See if card is present */
+ if (ssp_mmc_read(mmc, HW_SSP_STATUS) & BM_SSP_STATUS_CARD_DETECT) {
+ printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
+ return NO_CARD_ERR;
+ }
+
+ /* Clear all control bits except bus width */
+ ssp_mmc_write(mmc, HW_SSP_CTRL0_CLR, 0xff3fffff);
+
+ /* Set up command */
+ if (!(cmd->resp_type & MMC_RSP_CRC))
+ ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_IGNORE_CRC);
+ if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
+ ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_GET_RESP);
+ if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
+ ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_LONG_RESP);
+
+ /* Command index */
+ ssp_mmc_write(mmc, HW_SSP_CMD0,
+ (ssp_mmc_read(mmc, HW_SSP_CMD0) & ~BM_SSP_CMD0_CMD) |
+ (cmd->cmdidx << BP_SSP_CMD0_CMD));
+ /* Command argument */
+ ssp_mmc_write(mmc, HW_SSP_CMD1, cmd->cmdarg);
+
+ /* Set up data */
+ if (data) {
+ /* READ or WRITE */
+ if (data->flags & MMC_DATA_READ) {
+ ssp_mmc_write(mmc, HW_SSP_CTRL0_SET,
+ BM_SSP_CTRL0_READ);
+ } else if (ssp_mmc_is_wp(mmc)) {
+ printf("MMC%d: Can not write a locked card!\n",
+ mmc->block_dev.dev);
+ return UNUSABLE_ERR;
+ }
+ ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_DATA_XFER);
+ ssp_mmc_write(mmc, HW_SSP_BLOCK_SIZE,
+ ((data->blocks - 1) <<
+ BP_SSP_BLOCK_SIZE_BLOCK_COUNT) |
+ ((ffs(data->blocksize) - 1) <<
+ BP_SSP_BLOCK_SIZE_BLOCK_SIZE));
+ ssp_mmc_write(mmc, HW_SSP_XFER_SIZE,
+ data->blocksize * data->blocks);
+ }
+
+ /* Kick off the command */
+ ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_WAIT_FOR_IRQ);
+ ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_ENABLE);
+ ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_RUN);
+
+ /* Wait for the command to complete */
+ i = 0;
+ do {
+ mdelay(10);
+ if (i++ == 100) {
+ printf("MMC%d: Command %d busy\n",
+ mmc->block_dev.dev,
+ cmd->cmdidx);
+ break;
+ }
+ } while (ssp_mmc_read(mmc, HW_SSP_STATUS) &
+ BM_SSP_STATUS_CMD_BUSY);
+
+ /* Check command timeout */
+ if (ssp_mmc_read(mmc, HW_SSP_STATUS) &
+ BM_SSP_STATUS_RESP_TIMEOUT) {
+#ifdef IMX_SSP_MMC_DEBUG
+ printf("MMC%d: Command %d timeout\n", mmc->block_dev.dev,
+ cmd->cmdidx);
+#endif
+ return TIMEOUT;
+ }
+
+ /* Check command errors */
+ if (ssp_mmc_read(mmc, HW_SSP_STATUS) &
+ (BM_SSP_STATUS_RESP_CRC_ERR | BM_SSP_STATUS_RESP_ERR)) {
+ printf("MMC%d: Command %d error (status 0x%08x)!\n",
+ mmc->block_dev.dev, cmd->cmdidx,
+ ssp_mmc_read(mmc, HW_SSP_STATUS));
+ return COMM_ERR;
+ }
+
+ /* Copy response to response buffer */
+ if (cmd->resp_type & MMC_RSP_136) {
+ cmd->response[3] = ssp_mmc_read(mmc, HW_SSP_SDRESP0);
+ cmd->response[2] = ssp_mmc_read(mmc, HW_SSP_SDRESP1);
+ cmd->response[1] = ssp_mmc_read(mmc, HW_SSP_SDRESP2);
+ cmd->response[0] = ssp_mmc_read(mmc, HW_SSP_SDRESP3);
+ } else
+ cmd->response[0] = ssp_mmc_read(mmc, HW_SSP_SDRESP0);
+
+ /* Return if no data to process */
+ if (!data)
+ return 0;
+
+ /* Process the data */
+ u32 xfer_cnt = data->blocksize * data->blocks;
+ u32 *tmp_ptr;
+
+ if (data->flags & MMC_DATA_READ) {
+ tmp_ptr = (u32 *)data->dest;
+ while (xfer_cnt > 0) {
+ if ((ssp_mmc_read(mmc, HW_SSP_STATUS) &
+ BM_SSP_STATUS_FIFO_EMPTY) == 0) {
+ *tmp_ptr++ = ssp_mmc_read(mmc, HW_SSP_DATA);
+ xfer_cnt -= 4;
+ }
+ }
+ } else {
+ tmp_ptr = (u32 *)data->src;
+ while (xfer_cnt > 0) {
+ if ((ssp_mmc_read(mmc, HW_SSP_STATUS) &
+ BM_SSP_STATUS_FIFO_FULL) == 0) {
+ ssp_mmc_write(mmc, HW_SSP_DATA, *tmp_ptr++);
+ xfer_cnt -= 4;
+ }
+ }
+ }
+
+ /* Check data errors */
+ if (ssp_mmc_read(mmc, HW_SSP_STATUS) &
+ (BM_SSP_STATUS_TIMEOUT | BM_SSP_STATUS_DATA_CRC_ERR |
+ BM_SSP_STATUS_FIFO_OVRFLW | BM_SSP_STATUS_FIFO_UNDRFLW)) {
+ printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
+ mmc->block_dev.dev, cmd->cmdidx,
+ ssp_mmc_read(mmc, HW_SSP_STATUS));
+ return COMM_ERR;
+ }
+
+ return 0;
+}
+
+static void set_bit_clock(struct mmc *mmc, u32 clock)
+{
+ const u32 sspclk = 480000 * 18 / 29 / 1; /* 297931 KHz */
+ u32 divide, rate, tgtclk;
+
+ /*
+ * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
+ * CLOCK_DIVIDE has to be an even value from 2 to 254, and
+ * CLOCK_RATE could be any integer from 0 to 255.
+ */
+ clock /= 1000; /* KHz */
+ for (divide = 2; divide < 254; divide += 2) {
+ rate = sspclk / clock / divide;
+ if (rate <= 256)
+ break;
+ }
+
+ tgtclk = sspclk / divide / rate;
+ while (tgtclk > clock) {
+ rate++;
+ tgtclk = sspclk / divide / rate;
+ }
+ if (rate > 256)
+ rate = 256;
+
+ /* Always set timeout the maximum */
+ ssp_mmc_write(mmc, HW_SSP_TIMING, BM_SSP_TIMING_TIMEOUT |
+ divide << BP_SSP_TIMING_CLOCK_DIVIDE |
+ (rate - 1) << BP_SSP_TIMING_CLOCK_RATE);
+
+#ifdef IMX_SSP_MMC_DEBUG
+ printf("MMC%d: Set clock rate to %d KHz (requested %d KHz)\n",
+ mmc->block_dev.dev, tgtclk, clock);
+#endif
+}
+
+static void ssp_mmc_set_ios(struct mmc *mmc)
+{
+ u32 regval;
+
+ /* Set the clock speed */
+ if (mmc->clock)
+ set_bit_clock(mmc, mmc->clock);
+
+ /* Set the bus width */
+ regval = ssp_mmc_read(mmc, HW_SSP_CTRL0);
+ regval &= ~BM_SSP_CTRL0_BUS_WIDTH;
+ switch (mmc->bus_width) {
+ case 1:
+ regval |= (BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT <<
+ BP_SSP_CTRL0_BUS_WIDTH);
+ break;
+ case 4:
+ regval |= (BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT <<
+ BP_SSP_CTRL0_BUS_WIDTH);
+ break;
+ case 8:
+ regval |= (BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT <<
+ BP_SSP_CTRL0_BUS_WIDTH);
+ }
+ ssp_mmc_write(mmc, HW_SSP_CTRL0, regval);
+
+#ifdef IMX_SSP_MMC_DEBUG
+ printf("MMC%d: Set %d bits bus width\n",
+ mmc->block_dev.dev, mmc->bus_width);
+#endif
+}
+
+static int ssp_mmc_init(struct mmc *mmc)
+{
+ struct imx_ssp_mmc_cfg *cfg = (struct imx_ssp_mmc_cfg *)mmc->priv;
+ u32 regval;
+
+ /*
+ * Set up SSPCLK
+ */
+ /* Set REF_IO0 at 297.731 MHz */
+ regval = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0);
+ regval &= ~BM_CLKCTRL_FRAC0_IO0FRAC;
+ REG_WR(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0,
+ regval | (29 << BP_CLKCTRL_FRAC0_IO0FRAC));
+ /* Enable REF_IO0 */
+ REG_CLR(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0,
+ BM_CLKCTRL_FRAC0_CLKGATEIO0);
+
+ /* Source SSPCLK from REF_IO0 */
+ REG_CLR(REGS_CLKCTRL_BASE, HW_CLKCTRL_CLKSEQ,
+ cfg->clkctrl_clkseq_ssp_offset);
+ /* Turn on SSPCLK */
+ REG_WR(REGS_CLKCTRL_BASE, cfg->clkctrl_ssp_offset,
+ REG_RD(REGS_CLKCTRL_BASE, cfg->clkctrl_ssp_offset) &
+ ~BM_CLKCTRL_SSP_CLKGATE);
+ /* Set SSPCLK divide 1 */
+ regval = REG_RD(REGS_CLKCTRL_BASE, cfg->clkctrl_ssp_offset);
+ regval &= ~(BM_CLKCTRL_SSP_DIV_FRAC_EN | BM_CLKCTRL_SSP_DIV);
+ REG_WR(REGS_CLKCTRL_BASE, cfg->clkctrl_ssp_offset,
+ regval | (1 << BP_CLKCTRL_SSP_DIV));
+ /* Wait for new divide ready */
+ do {
+ udelay(10);
+ } while (REG_RD(REGS_CLKCTRL_BASE, cfg->clkctrl_ssp_offset) &
+ BM_CLKCTRL_SSP_BUSY);
+
+ /* Prepare for software reset */
+ ssp_mmc_write(mmc, HW_SSP_CTRL0_CLR, BM_SSP_CTRL0_SFTRST);
+ ssp_mmc_write(mmc, HW_SSP_CTRL0_CLR, BM_SSP_CTRL0_CLKGATE);
+ /* Assert reset */
+ ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_SFTRST);
+ /* Wait for confirmation */
+ while (!(ssp_mmc_read(mmc, HW_SSP_CTRL0) & BM_SSP_CTRL0_CLKGATE))
+ ;
+ /* Done */
+ ssp_mmc_write(mmc, HW_SSP_CTRL0_CLR, BM_SSP_CTRL0_SFTRST);
+ ssp_mmc_write(mmc, HW_SSP_CTRL0_CLR, BM_SSP_CTRL0_CLKGATE);
+
+ /* 8 bits word length in MMC mode */
+ regval = ssp_mmc_read(mmc, HW_SSP_CTRL1);
+ regval &= ~(BM_SSP_CTRL1_SSP_MODE | BM_SSP_CTRL1_WORD_LENGTH);
+ ssp_mmc_write(mmc, HW_SSP_CTRL1, regval |
+ (BV_SSP_CTRL1_SSP_MODE__SD_MMC << BP_SSP_CTRL1_SSP_MODE) |
+ (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS <<
+ BP_SSP_CTRL1_WORD_LENGTH));
+
+ /* Set initial bit clock 400 KHz */
+ set_bit_clock(mmc, 400000);
+
+ /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
+ ssp_mmc_write(mmc, HW_SSP_CMD0_SET, BM_SSP_CMD0_CONT_CLKING_EN);
+ udelay(200);
+ ssp_mmc_write(mmc, HW_SSP_CMD0_CLR, BM_SSP_CMD0_CONT_CLKING_EN);
+
+ return 0;
+}
+
+int imx_ssp_mmc_initialize(bd_t *bis, struct imx_ssp_mmc_cfg *cfg)
+{
+ struct mmc *mmc;
+
+ mmc = malloc(sizeof(struct mmc));
+ sprintf(mmc->name, "IMX_SSP_MMC");
+ mmc->send_cmd = ssp_mmc_send_cmd;
+ mmc->set_ios = ssp_mmc_set_ios;
+ mmc->init = ssp_mmc_init;
+ mmc->priv = cfg;
+
+ mmc->voltages = MMC_VDD_32_33 | MMC_VDD_31_32 | MMC_VDD_30_31 |
+ MMC_VDD_29_30 | MMC_VDD_28_29 | MMC_VDD_27_28;
+
+ mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
+ MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+ /*
+ * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
+ * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
+ * CLOCK_DIVIDE has to be an even value from 2 to 254, and
+ * CLOCK_RATE could be any integer from 0 to 255.
+ */
+ mmc->f_min = 400000;
+ mmc->f_max = 148000000; /* 297.731 MHz / 2 */
+
+ mmc_register(mmc);
+ return 0;
+}
udelay(1000);
} while (!(cmd.response[0] & OCR_BUSY) && timeout--);
- if (timeout <= 0)
+ if (timeout <= 0) {
+debug("%s: timeout\n", __func__);
return UNUSABLE_ERR;
-
+ }
if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
cmd.resp_type = MMC_RSP_R3;
uint32_t reg;
int timeout;
uint32_t ctrl0;
+ const uint32_t busy_stat = SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
+ SSP_STATUS_CMD_BUSY;
int ret;
debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
/* Check bus busy */
timeout = MXSMMC_MAX_TIMEOUT;
- while (--timeout) {
- udelay(1000);
- reg = readl(&ssp_regs->hw_ssp_status);
- if (!(reg &
- (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
- SSP_STATUS_CMD_BUSY))) {
+ while ((reg = readl(&ssp_regs->hw_ssp_status)) & busy_stat) {
+ if (timeout-- <= 0)
break;
- }
+ udelay(1000);
}
-
- if (!timeout) {
+ if (reg & busy_stat && readl(&ssp_regs->hw_ssp_status) & busy_stat) {
printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
return TIMEOUT;
}
if (!(reg & SSP_STATUS_CMD_BUSY))
break;
}
-
- if (!timeout) {
+ if ((reg & SSP_STATUS_CMD_BUSY) &&
+ (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CMD_BUSY)) {
printf("MMC%d: Command %d busy\n",
mmc->block_dev.dev, cmd->cmdidx);
return TIMEOUT;
if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
ret = mxsmmc_send_cmd_pio(priv, data);
if (ret) {
- printf("MMC%d: Data timeout with command %d "
- "(status 0x%08x)!\n",
+ printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n",
mmc->block_dev.dev, cmd->cmdidx, reg);
return ret;
}
struct mxsmmc_priv *priv = NULL;
int ret;
- mmc = malloc(sizeof(struct mmc));
+ mmc = calloc(sizeof(struct mmc), 1);
if (!mmc)
return -ENOMEM;
- priv = malloc(sizeof(struct mxsmmc_priv));
+ priv = calloc(sizeof(struct mxsmmc_priv), 1);
if (!priv) {
free(mmc);
return -ENOMEM;
writel(MMC_CMD0, &mmc_base->cmd);
start = get_timer(0);
while (!(readl(&mmc_base->stat) & CC_MASK)) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for cc!\n", __func__);
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for cc!\n", __func__);
return;
}
}
;
start = get_timer(0);
while (!(readl(&mmc_base->stat) & CC_MASK)) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for cc2!\n", __func__);
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for cc2!\n", __func__);
return;
}
}
&mmc_base->sysconfig);
start = get_timer(0);
while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for cc2!\n", __func__);
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for cc2!\n", __func__);
return TIMEOUT;
}
}
writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
start = get_timer(0);
while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for softresetall!\n",
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for softresetall!\n",
__func__);
return TIMEOUT;
}
(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
start = get_timer(0);
while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for ics!\n", __func__);
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for ics!\n", __func__);
return TIMEOUT;
}
}
static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
- struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
+ struct hsmmc *mmc_base = mmc->priv;
unsigned int flags, mmc_stat;
ulong start;
start = get_timer(0);
while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting on cmd inhibit to clear\n",
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting on cmd inhibit to clear\n",
__func__);
return TIMEOUT;
}
writel(0xFFFFFFFF, &mmc_base->stat);
start = get_timer(0);
while (readl(&mmc_base->stat)) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for STAT (%x) to clear\n",
- __func__, readl(&mmc_base->stat));
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for stat!\n", __func__);
return TIMEOUT;
}
}
start = get_timer(0);
do {
mmc_stat = readl(&mmc_base->stat);
- if (get_timer(0) - start > MAX_RETRY_MS) {
+ if (get_timer(start) > MAX_RETRY_MS) {
printf("%s : timeout: No status update\n", __func__);
return TIMEOUT;
}
ulong start = get_timer(0);
do {
mmc_stat = readl(&mmc_base->stat);
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for status!\n",
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for status!\n",
__func__);
return TIMEOUT;
}
ulong start = get_timer(0);
do {
mmc_stat = readl(&mmc_base->stat);
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for status!\n",
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for status!\n",
__func__);
return TIMEOUT;
}
start = get_timer(0);
while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for ics!\n", __func__);
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for ics!\n", __func__);
return;
}
}
COBJS-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
+COBJS-$(CONFIG_NAND_AM33XX) += am33xx_nand.o
COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o
COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
COBJS-$(CONFIG_NAND_MXS) += mxs_nand.o
COBJS-$(CONFIG_NAND_NDFC) += ndfc.o
COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
+COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_bch_decoder.o omap_gpmc.o omap_bch_soft.o
+COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
--- /dev/null
+/*
+ * (C) Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ * based on ti81xx_nand.c
+ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Derived from work done by Rohit Choraria <rohitkc@ti.com> for omap
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <nand.h>
+
+struct nand_bch_priv {
+ uint8_t type;
+ uint8_t nibbles;
+};
+
+/* bch types */
+#define ECC_BCH4 0
+#define ECC_BCH8 1
+#define ECC_BCH16 2
+
+/* BCH nibbles for diff bch levels */
+#define ECC_BCH4_NIBBLES 13
+#define ECC_BCH8_NIBBLES 26
+#define ECC_BCH16_NIBBLES 52
+
+static uint8_t cs;
+#ifndef CONFIG_SPL_BUILD
+static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT_KERNEL;
+static struct nand_ecclayout hw_bch4_nand_oob = GPMC_NAND_HW_BCH4_ECC_LAYOUT;
+static struct nand_ecclayout hw_bch16_nand_oob = GPMC_NAND_HW_BCH16_ECC_LAYOUT;
+#endif
+static struct nand_ecclayout hw_bch8_nand_oob = GPMC_NAND_HW_BCH8_ECC_LAYOUT;
+
+static struct nand_bch_priv bch_priv = {
+ .type = ECC_BCH8,
+ .nibbles = ECC_BCH8_NIBBLES,
+};
+
+#ifndef CONFIG_SYS_NAND_NO_OOB
+static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
+static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+ NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+ .offs = 58,
+ .len = 4,
+ .veroffs = 62,
+ .maxblocks = 4,
+ .pattern = bbt_pattern,
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+ NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+ .offs = 58,
+ .len = 4,
+ .veroffs = 62,
+ .maxblocks = 4,
+ .pattern = mirror_pattern,
+};
+#endif
+
+/*
+ * am33xx_read_bch8_result - Read BCH result for BCH8 level
+ *
+ * @mtd: MTD device structure
+ * @big_endian: When set read register 3 first
+ * @ecc_code: Read syndrome from BCH result registers
+ */
+static void am33xx_read_bch8_result(struct mtd_info *mtd, int big_endian,
+ uint8_t *ecc_code)
+{
+ uint32_t *ptr;
+ int i = 0, j;
+
+ if (big_endian) {
+ u32 res;
+ ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
+ res = readl(ptr);
+ ecc_code[i++] = res & 0xFF;
+ for (j = 0; j < 3; j++) {
+ u32 res = readl(--ptr);
+
+ ecc_code[i++] = (res >> 24) & 0xFF;
+ ecc_code[i++] = (res >> 16) & 0xFF;
+ ecc_code[i++] = (res >> 8) & 0xFF;
+ ecc_code[i++] = res & 0xFF;
+ }
+ } else {
+ ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0];
+ for (j = 0; j < 3; j++) {
+ u32 res = readl(ptr++);
+
+ ecc_code[i++] = res & 0xFF;
+ ecc_code[i++] = (res >> 8) & 0xFF;
+ ecc_code[i++] = (res >> 16) & 0xFF;
+ ecc_code[i++] = (res >> 24) & 0xFF;
+ }
+ ecc_code[i++] = readl(ptr) & 0xFF;
+ }
+ ecc_code[i] = 0xff;
+}
+
+/*
+ * am33xx_ecc_disable - Disable H/W ECC calculation
+ *
+ * @mtd: MTD device structure
+ *
+ */
+static void am33xx_ecc_disable(struct mtd_info *mtd)
+{
+ writel((readl(&gpmc_cfg->ecc_config) & ~0x1),
+ &gpmc_cfg->ecc_config);
+}
+
+/*
+ * am33xx_nand_hwcontrol - Set the address pointers correctly for the
+ * following address/data/command operation
+ */
+static void am33xx_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
+ uint32_t ctrl)
+{
+ register struct nand_chip *this = mtd->priv;
+
+ debug("nand cmd %08x ctrl %08x\n", cmd, ctrl);
+ /*
+ * Point the IO_ADDR to DATA and ADDRESS registers instead
+ * of chip address
+ */
+ switch (ctrl) {
+ case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
+ this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
+ break;
+ case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
+ this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
+ break;
+ case NAND_CTRL_CHANGE | NAND_NCE:
+ this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+/*
+ * am33xx_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
+ * GPMC controller
+ * @mtd: MTD device structure
+ * @mode: Read/Write mode
+ */
+static void am33xx_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
+{
+ uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
+ uint32_t unused_length = 0;
+ struct nand_bch_priv *bch = chip->priv;
+
+ switch (bch->nibbles) {
+ case ECC_BCH4_NIBBLES:
+ unused_length = 3;
+ break;
+ case ECC_BCH8_NIBBLES:
+ unused_length = 2;
+ break;
+ case ECC_BCH16_NIBBLES:
+ unused_length = 0;
+ }
+
+ /* Clear the ecc result registers, select ecc reg as 1 */
+ writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
+
+ switch (mode) {
+ case NAND_ECC_WRITE:
+ /* eccsize1 config */
+ val = ((unused_length + bch->nibbles) << 22);
+ break;
+
+ case NAND_ECC_READ:
+ default:
+ /* by default eccsize0 selected for ecc1resultsize */
+ /* eccsize0 config */
+ val = (bch->nibbles << 12);
+ /* eccsize1 config */
+ val |= (unused_length << 22);
+ }
+ /* ecc size configuration */
+ writel(val, &gpmc_cfg->ecc_size_config);
+ /* by default 512bytes sector page is selected */
+ /* set bch mode */
+ val = (1 << 16);
+ /* bch4 / bch8 / bch16 */
+ val |= (bch->type << 12);
+ /* set wrap mode to 1 */
+ val |= (1 << 8);
+ val |= (dev_width << 7);
+ val |= (cs << 1);
+ /* enable ecc */
+ /* val |= (1); */ /* should not enable ECC just init i.e. config */
+ writel(val, &gpmc_cfg->ecc_config);
+}
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * am33xx_hwecc_init - Initialize the Hardware ECC for NAND flash in
+ * GPMC controller
+ * @mtd: MTD device structure
+ *
+ */
+static void am33xx_hwecc_init(struct nand_chip *chip)
+{
+ /*
+ * Init ECC Control Register
+ * Clear all ECC | Enable Reg1
+ */
+ writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
+ writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config);
+}
+
+/*
+ * gen_true_ecc - This function will generate true ECC value, which
+ * can be used when correcting data read from NAND flash memory core
+ *
+ * @ecc_buf: buffer to store ecc code
+ *
+ * @return: re-formatted ECC value
+ */
+static uint32_t gen_true_ecc(uint8_t *ecc_buf)
+{
+ return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
+ ((ecc_buf[2] & 0x0F) << 8);
+}
+#endif
+
+/*
+ * am33xx_rotate_ecc_bch - Rotate the syndrome bytes
+ *
+ * @mtd: MTD device structure
+ * @calc_ecc: ECC read from ECC registers
+ * @syndrome: Rotated syndrome will be retuned in this array
+ *
+ */
+static inline void am33xx_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc,
+ uint8_t *syndrome)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ int n_bytes;
+ int i, j;
+
+ switch (bch->type) {
+ case ECC_BCH4:
+ n_bytes = 8;
+ break;
+
+ case ECC_BCH16:
+ n_bytes = 28;
+ break;
+
+ case ECC_BCH8:
+ default:
+ n_bytes = 13;
+ }
+
+ for (i = 0, j = (n_bytes - 1); i < n_bytes; i++, j--)
+ syndrome[i] = calc_ecc[j];
+ syndrome[i] = 0xff;
+}
+
+
+/*
+ * am33xx_fix_errors_bch - Correct bch error in the data
+ *
+ * @mtd: MTD device structure
+ * @data: Data read from flash
+ * @error_count:Number of errors in data
+ * @error_loc: Locations of errors in the data
+ *
+ */
+static void am33xx_fix_errors_bch(struct mtd_info *mtd, uint8_t *data,
+ uint32_t error_count, uint32_t *error_loc)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ int count = 0;
+ uint32_t error_byte_pos;
+ uint32_t error_bit_mask;
+ uint32_t last_bit = (bch->nibbles * 4) - 1;
+
+ /* Flip all bits as specified by the error location array. */
+ /* FOR( each found error location flip the bit ) */
+ for (count = 0; count < error_count; count++) {
+ if (error_loc[count] > last_bit) {
+ /* Remove the ECC spare bits from correction. */
+ error_loc[count] -= (last_bit + 1);
+ /* Offset bit in data region */
+ error_byte_pos = ((512 * 8) - (error_loc[count]) - 1) / 8;
+ /* Error Bit mask */
+ error_bit_mask = 0x1 << (error_loc[count] % 8);
+ /* Toggle the error bit to make the correction. */
+ data[error_byte_pos] ^= error_bit_mask;
+ }
+ }
+}
+
+/*
+ * am33xx_correct_data_bch - Compares the ecc read from nand spare area
+ * with ECC registers values and corrects one bit error if it has occured
+ *
+ * @mtd: MTD device structure
+ * @dat: page data
+ * @read_ecc: ecc read from nand flash (ignored)
+ * @calc_ecc: ecc read from ECC registers
+ *
+ * @return 0 if data is OK or corrected, else returns -1
+ */
+static inline int am33xx_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int page);
+
+static int am33xx_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
+ uint8_t *read_ecc, uint8_t *calc_ecc)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ uint8_t syndrome[28];
+ uint32_t error_count = 0;
+ uint32_t error_loc[8];
+ uint32_t i, ecc_flag;
+
+ ecc_flag = 0;
+ for (i = 0; i < (chip->ecc.bytes - 1); i++)
+ if (read_ecc[i] != 0xff)
+ ecc_flag = 1;
+
+ if (!ecc_flag)
+ return 0;
+
+ elm_reset();
+ elm_config(bch->type);
+
+ /* while reading ECC result we read it in big endian.
+ * Hence while loading to ELM we have rotate to get the right endian.
+ */
+ am33xx_rotate_ecc_bch(mtd, calc_ecc, syndrome);
+
+ /* use elm module to check for errors */
+ if (elm_check_error(syndrome, bch->nibbles, &error_count, error_loc) != 0) {
+ printf("uncorrectable ECC error\n");
+ return -1;
+ }
+
+ /* correct bch error */
+ if (error_count > 0) {
+ am33xx_fix_errors_bch(mtd, dat, error_count, error_loc);
+ }
+
+ return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * am33xx_correct_data - Compares the ecc read from nand spare area with ECC
+ * registers values and corrects one bit error if it has occured
+ * Further details can be had from Am33xx TRM and the following selected links:
+ * http://en.wikipedia.org/wiki/Hamming_code
+ * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
+ *
+ * @mtd: MTD device structure
+ * @dat: page data
+ * @read_ecc: ecc read from nand flash
+ * @calc_ecc: ecc read from ECC registers
+ *
+ * @return 0 if data is OK or corrected, else returns -1
+ */
+static int am33xx_correct_data(struct mtd_info *mtd, uint8_t *dat,
+ uint8_t *read_ecc, uint8_t *calc_ecc)
+{
+ uint32_t orig_ecc, new_ecc, res, hm;
+ uint16_t parity_bits, byte;
+ int bit;
+
+ /* Regenerate the orginal ECC */
+ orig_ecc = gen_true_ecc(read_ecc);
+ new_ecc = gen_true_ecc(calc_ecc);
+ /* Get the XOR of real ecc */
+ res = orig_ecc ^ new_ecc;
+ if (res) {
+ /* Get the hamming width */
+ hm = hweight32(res);
+ /* Single bit errors can be corrected! */
+ if (hm == 12) {
+ /* Correctable data! */
+ parity_bits = res >> 16;
+ bit = (parity_bits & 0x7);
+ byte = (parity_bits >> 3) & 0x1FF;
+ /* Flip the bit to correct */
+ dat[byte] ^= (0x1 << bit);
+ } else if (hm == 1) {
+ printf("am33xx_nand: Error: Corrupted ECC\n");
+ /* ECC itself is corrupted */
+ return 2;
+ } else {
+ /*
+ * hm distance != parity pairs OR one, could mean 2 bit
+ * error OR potentially be on a blank page..
+ * orig_ecc: contains spare area data from nand flash.
+ * new_ecc: generated ecc while reading data area.
+ * Note: if the ecc = 0, all data bits from which it was
+ * generated are 0xFF.
+ * The 3 byte(24 bits) ecc is generated per 512byte
+ * chunk of a page. If orig_ecc(from spare area)
+ * is 0xFF && new_ecc(computed now from data area)=0x0,
+ * this means that data area is 0xFF and spare area is
+ * 0xFF. A sure sign of an erased page!
+ */
+ if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
+ return 0;
+ printf("am33xx_nand: Error: Multibit error detected; hm=%d\n",
+ hm);
+ /* detected 2 bit error */
+ return -1;
+ }
+ }
+ return 0;
+}
+#endif
+
+/*
+ * am33xx_calculate_ecc_bch - Read BCH ECC result
+ *
+ * @mtd: MTD structure
+ * @dat: unused
+ * @ecc_code: ecc_code buffer
+ */
+static int am33xx_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
+ uint8_t *ecc_code)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ int big_endian = 1;
+ int ret = 0;
+
+ if (bch->type == ECC_BCH8)
+ am33xx_read_bch8_result(mtd, big_endian, ecc_code);
+ else /* BCH4 and BCH16 currently not supported */
+ ret = -1;
+
+ /*
+ * Stop reading anymore ECC vals and clear old results
+ * enable will be called if more reads are required
+ */
+ am33xx_ecc_disable(mtd);
+
+ return ret;
+}
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * am33xx_calculate_ecc - Generate non-inverted ECC bytes.
+ *
+ * Using noninverted ECC can be considered ugly since writing a blank
+ * page ie. padding will clear the ECC bytes. This is no problem as
+ * long nobody is trying to write data on the seemingly unused page.
+ * Reading an erased page will produce an ECC mismatch between
+ * generated and read ECC bytes that has to be dealt with separately.
+ * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
+ * is used, the result of read will be 0x0 while the ECC offsets of the
+ * spare area will be 0xFF which will result in an ECC mismatch.
+ * @mtd: MTD structure
+ * @dat: unused
+ * @ecc_code: ecc_code buffer
+ */
+static int am33xx_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
+ uint8_t *ecc_code)
+{
+ u_int32_t val;
+
+ /* Start Reading from HW ECC1_Result = 0x200 */
+ val = readl(&gpmc_cfg->ecc1_result);
+
+ ecc_code[0] = val & 0xFF;
+ ecc_code[1] = (val >> 16) & 0xFF;
+ ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
+
+ /*
+ * Stop reading anymore ECC vals and clear old results
+ * enable will be called if more reads are required
+ */
+ writel(0x000, &gpmc_cfg->ecc_config);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+static void am33xx_spl_nand_command(struct mtd_info *mtd, unsigned int cmd,
+ int col, int page)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ while (!chip->dev_ready(mtd))
+ ;
+
+ /* Emulate NAND_CMD_READOOB */
+ if (cmd == NAND_CMD_READOOB) {
+ col += CONFIG_SYS_NAND_PAGE_SIZE;
+ cmd = NAND_CMD_READ0;
+ }
+
+ /* Shift the offset from byte addressing to word addressing. */
+ if (chip->options & NAND_BUSWIDTH_16)
+ col >>= 1;
+
+ /* Begin command latch cycle */
+ chip->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ /* Set ALE and clear CLE to start address cycle */
+ /* Column address */
+ chip->cmd_ctrl(mtd, col & 0xff,
+ NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
+ chip->cmd_ctrl(mtd, (col >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
+ /* Row address */
+ chip->cmd_ctrl(mtd, page & 0xff, NAND_CTRL_ALE); /* A[19:12] */
+ chip->cmd_ctrl(mtd, (page >> 8) & 0xff,
+ NAND_CTRL_ALE); /* A[27:20] */
+#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
+ /* One more address cycle for devices > 128MiB */
+ chip->cmd_ctrl(mtd, (page >> 16) & 0x0f,
+ NAND_CTRL_ALE); /* A[31:28] */
+#endif
+ chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+ /* Latch in address */
+ chip->cmd_ctrl(mtd, cmd == NAND_CMD_RNDOUT ?
+ NAND_CMD_RNDOUTSTART : NAND_CMD_READSTART,
+ NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+ /*
+ * Wait a while for the data to be ready
+ */
+ while (!chip->dev_ready(mtd))
+ ;
+}
+#endif
+
+/**
+ * am33xx_read_page_bch - hardware ecc based page read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @page: page number to read
+ *
+ */
+static inline int am33xx_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int page)
+{
+ int ret = 0;
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ uint8_t *p = buf;
+ uint8_t *ecc_calc = chip->buffers->ecccalc;
+ uint8_t *ecc_code = chip->buffers->ecccode;
+ uint32_t *eccpos = chip->ecc.layout->eccpos;
+ uint8_t *oob = chip->oob_poi;
+ uint32_t data_pos = 0;
+ uint32_t oob_pos = (eccsize * eccsteps) + eccpos[0];
+
+ chip->cmdfunc(mtd, NAND_CMD_READ0, data_pos, page);
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
+ oob += eccbytes) {
+ chip->ecc.hwctl(mtd, NAND_ECC_READ);
+ /* read data */
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
+ chip->read_buf(mtd, p, eccsize);
+ /* read respective ecc from oob area */
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
+ chip->read_buf(mtd, oob, eccbytes);
+ /* read syndrome */
+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+ data_pos += eccsize;
+ oob_pos += eccbytes;
+ }
+
+ for (i = 0; i < chip->ecc.total; i++) {
+ ecc_code[i] = chip->oob_poi[i];
+ }
+
+ eccsteps = chip->ecc.steps;
+ p = buf;
+
+ for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ int stat;
+
+ stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+ if (stat < 0) {
+ printf("am33xx_nand: uncorrectable ECC error in page %5d\n",
+ page);
+ mtd->ecc_stats.failed++;
+ return -EBADMSG;
+ } else if (stat) {
+ mtd->ecc_stats.corrected += stat;
+ printf("%s: corrected ECC errors: %d\n", __func__, stat);
+ ret += stat;
+ }
+ }
+ return ret;
+}
+
+/*
+ * am33xx_enable_ecc_bch- This function enables the bch h/w ecc functionality
+ * @mtd: MTD device structure
+ * @mode: Read/Write mode
+ *
+ */
+static void am33xx_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ am33xx_hwecc_init_bch(chip, mode);
+ /* enable ecc */
+ writel(readl(&gpmc_cfg->ecc_config) | 0x1, &gpmc_cfg->ecc_config);
+}
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * am33xx_enable_ecc - This function enables the hardware ecc functionality
+ * @mtd: MTD device structure
+ * @mode: Read/Write mode
+ */
+static void am33xx_enable_ecc(struct mtd_info *mtd, int32_t mode)
+{
+ struct nand_chip *chip = mtd->priv;
+ uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
+
+ switch (mode) {
+ case NAND_ECC_READ:
+ case NAND_ECC_WRITE:
+ /* Clear the ecc result registers, select ecc reg as 1 */
+ writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
+
+ /*
+ * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
+ * tell all regs to generate size0 sized regs
+ * we just have a single ECC engine for all CS
+ */
+ writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
+ &gpmc_cfg->ecc_size_config);
+ val = (dev_width << 7) | (cs << 1) | (1 << 0);
+ writel(val, &gpmc_cfg->ecc_config);
+ break;
+ default:
+ printf("Error: Unrecognized Mode[%d]!\n", mode);
+ }
+}
+
+/*
+ * __am33xx_nand_switch_ecc - switch the ECC operation ib/w h/w ecc
+ * (i.e. hamming / bch) and s/w ecc.
+ * The default is to come up on s/w ecc
+ *
+ * @nand: NAND chip datastructure
+ * @hardware: NAND_ECC_HW -switch to h/w ecc
+ * NAND_ECC_SOFT -switch to s/w ecc
+ *
+ * @mode: 0 - hamming code
+ * 1 - bch4
+ * 2 - bch8
+ * 3 - bch16
+ */
+static void __am33xx_nand_switch_ecc(struct nand_chip *nand,
+ nand_ecc_modes_t hardware, int32_t mode)
+{
+ struct nand_bch_priv *bch;
+
+ bch = nand->priv;
+
+ /* Reset ecc interface */
+ nand->ecc.read_page = NULL;
+ nand->ecc.write_page = NULL;
+ nand->ecc.read_oob = NULL;
+ nand->ecc.write_oob = NULL;
+ nand->ecc.hwctl = NULL;
+ nand->ecc.correct = NULL;
+ nand->ecc.calculate = NULL;
+
+ nand->ecc.mode = hardware;
+ /* Setup the ecc configurations again */
+ if (hardware == NAND_ECC_HW) {
+ if (mode) {
+ /* -1 for converting mode to bch type */
+ bch->type = mode - 1;
+ debug("HW ECC BCH");
+ switch (bch->type) {
+ case ECC_BCH4:
+ nand->ecc.bytes = 8;
+ nand->ecc.layout = &hw_bch4_nand_oob;
+ bch->nibbles = ECC_BCH4_NIBBLES;
+ debug("4 not supported\n");
+ return;
+
+ case ECC_BCH16:
+ nand->ecc.bytes = 26;
+ nand->ecc.layout = &hw_bch16_nand_oob;
+ bch->nibbles = ECC_BCH16_NIBBLES;
+ debug("16 not supported\n");
+ return;
+
+ case ECC_BCH8:
+ default:
+ nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
+ nand->ecc.layout = &hw_bch8_nand_oob;
+ bch->nibbles = ECC_BCH8_NIBBLES;
+ debug("8 Selected\n");
+ }
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.size = 512;
+ nand->ecc.read_page = am33xx_read_page_bch;
+ nand->ecc.hwctl = am33xx_enable_ecc_bch;
+ nand->ecc.correct = am33xx_correct_data_bch;
+ nand->ecc.calculate = am33xx_calculate_ecc_bch;
+ am33xx_hwecc_init_bch(nand, NAND_ECC_READ);
+ } else {
+ nand->ecc.layout = &hw_nand_oob;
+ nand->ecc.size = 512;
+ nand->ecc.bytes = 3;
+ nand->ecc.hwctl = am33xx_enable_ecc;
+ nand->ecc.correct = am33xx_correct_data;
+ nand->ecc.calculate = am33xx_calculate_ecc;
+ am33xx_hwecc_init(nand);
+ debug("HW ECC Hamming Code selected\n");
+ }
+ } else if (hardware == NAND_ECC_SOFT) {
+ /* Use mtd default settings */
+ nand->ecc.layout = NULL;
+ debug("SW ECC selected\n");
+ } else {
+ debug("ECC Disabled\n");
+ }
+}
+
+/*
+ * am33xx_nand_switch_ecc - switch the ECC operation ib/w h/w ecc
+ * (i.e. hamming / bch) and s/w ecc.
+ * The default is to come up on s/w ecc
+ *
+ * @hardware - NAND_ECC_HW -switch to h/w ecc
+ * NAND_ECC_SOFT -switch to s/w ecc
+ *
+ * @mode - 0 - hamming code
+ * 1 - bch4
+ * 2 - bch8
+ * 3 - bch16
+ */
+void am33xx_nand_switch_ecc(nand_ecc_modes_t hardware, int32_t mode)
+{
+ struct nand_chip *nand;
+ struct mtd_info *mtd;
+
+ if (nand_curr_device < 0 ||
+ nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE) {
+ printf("Error: Can't switch ecc, no devices available\n");
+ return;
+ }
+
+ mtd = &nand_info[nand_curr_device];
+ nand = mtd->priv;
+
+ __am33xx_nand_switch_ecc(nand, hardware, mode);
+
+ nand->options |= NAND_OWN_BUFFERS;
+ /* Update NAND handling after ECC mode switch */
+ nand_scan_tail(mtd);
+ nand->options &= ~NAND_OWN_BUFFERS;
+}
+
+#else /* CONFIG_SPL_BUILD */
+/* Check wait pin as dev ready indicator */
+static int am33xx_spl_dev_ready(struct mtd_info *mtd)
+{
+ int ret;
+
+// printf("dev status: ");
+ ret = readl(&gpmc_cfg->status) & (1 << 8);
+// printf("%d %08x\n", ret, gpmc_cfg->status);
+ return ret;
+}
+#endif
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific:
+ * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
+ * - cmd_ctrl: hardwarespecific function for accesing control-lines
+ * - waitfunc: hardwarespecific function for accesing device ready/busy line
+ * - ecc.hwctl: function to enable (reset) hardware ecc generator
+ * - ecc.mode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ * read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ * nand_scan about special functionality. See the defines for further
+ * explanation
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+ /* int32_t gpmc_config = 0; */
+ cs = 0;
+
+ /*
+ * xloader/Uboot's gpmc configuration would have configured GPMC for
+ * nand type of memory. The following logic scans and latches on to the
+ * first CS with NAND type memory.
+ * TBD: need to make this logic generic to handle multiple CS NAND
+ * devices.
+ */
+ while (cs < GPMC_MAX_CS) {
+ /* Check if NAND type is set */
+ if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
+ /* Found it!! */
+ debug("Searching for NAND device @ GPMC CS:%d\n", cs);
+ break;
+ }
+ cs++;
+ }
+ if (cs >= GPMC_MAX_CS) {
+ printf("NAND: Unable to find NAND settings in "
+ "GPMC Configuration - quitting\n");
+ return -ENODEV;
+ }
+
+ nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
+ nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
+
+ nand->cmd_ctrl = am33xx_nand_hwcontrol;
+ nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR;
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+#ifdef CONFIG_SYS_NAND_NO_OOB
+ nand->options |= NAND_USE_FLASH_BBT | NAND_USE_FLASH_BBT_NO_OOB;
+#else
+ nand->options |= NAND_USE_FLASH_BBT;
+ nand->bbt_td = &bbt_main_descr;
+ nand->bbt_md = &bbt_mirror_descr;
+#endif /* CONFIG_SYS_NAND_NO_OOB */
+#endif /* CONFIG_SYS_NAND_USE_FLASH_BBT */
+
+ /* If we are 16 bit dev, our gpmc config tells us that */
+ if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) {
+ nand->options |= NAND_BUSWIDTH_16;
+ }
+
+ nand->chip_delay = 100;
+
+ /* required in case of BCH */
+ elm_init();
+
+ /* BCH info that will be correct for SPL or overridden otherwise. */
+ nand->priv = &bch_priv;
+
+ bch_priv.nibbles = ECC_BCH8_NIBBLES;
+ bch_priv.type = ECC_BCH8;
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.layout = &hw_bch8_nand_oob;
+ nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
+ nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
+ nand->ecc.hwctl = am33xx_enable_ecc_bch;
+ nand->ecc.read_page = am33xx_read_page_bch;
+ nand->ecc.correct = am33xx_correct_data_bch;
+ nand->ecc.calculate = am33xx_calculate_ecc_bch;
+
+#ifndef CONFIG_SPL_BUILD
+ nand_curr_device = 0;
+#else
+ nand->cmdfunc = am33xx_spl_nand_command;
+
+ nand->ecc.steps = CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE;
+ nand->ecc.total = CONFIG_SYS_NAND_ECCBYTES * nand->ecc.steps;
+
+ if (nand->options & NAND_BUSWIDTH_16)
+ nand->read_buf = nand_read_buf16;
+ else
+ nand->read_buf = nand_read_buf;
+
+ nand->dev_ready = am33xx_spl_dev_ready;
+#endif /* CONFIG_SPL_BUILD */
+ am33xx_hwecc_init_bch(nand, NAND_ECC_READ);
+
+ return 0;
+}
* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
* Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
*
+ * Copyright 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
*/
#include <common.h>
+#include <malloc.h>
#include <nand.h>
#include <linux/err.h>
#include <asm/io.h>
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
+ defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
#endif
-#include <fsl_nfc.h>
-
-#define DRIVER_NAME "mxc_nand"
-typedef enum {false, true} bool;
+#ifdef DEBUG
+#define pr_debug(fmt...) printk(fmt)
+#else
+#define pr_debug(fmt...) do { } while (0)
+#endif
-struct mxc_nand_host {
- struct mtd_info mtd;
- struct nand_chip *nand;
-
- struct fsl_nfc_regs __iomem *regs;
- int spare_only;
- int status_request;
- int pagesize_2k;
- int clk_act;
- uint16_t col_addr;
- unsigned int page_addr;
-};
+typedef enum _bool { false, true } bool;
static struct mxc_nand_host mxc_host;
static struct mxc_nand_host *host = &mxc_host;
-/* Define delays in microsec for NAND device operations */
-#define TROP_US_DELAY 2000
-/* Macros to get byte and bit positions of ECC */
-#define COLPOS(x) ((x) >> 3)
-#define BITPOS(x) ((x) & 0xf)
-
-/* Define single bit Error positions in Main & Spare area */
-#define MAIN_SINGLEBIT_ERROR 0x4
-#define SPARE_SINGLEBIT_ERROR 0x1
-
-/* OOB placement block for use with hardware ecc generation */
-#if defined(MXC_NFC_V1)
-#ifndef CONFIG_SYS_NAND_LARGEPAGE
-static struct nand_ecclayout nand_hw_eccoob = {
- .eccbytes = 5,
- .eccpos = {6, 7, 8, 9, 10},
- .oobfree = { {0, 5}, {11, 5}, }
-};
-#else
-static struct nand_ecclayout nand_hw_eccoob2k = {
- .eccbytes = 20,
- .eccpos = {
- 6, 7, 8, 9, 10,
- 22, 23, 24, 25, 26,
- 38, 39, 40, 41, 42,
- 54, 55, 56, 57, 58,
- },
- .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
-};
-#endif
-#elif defined(MXC_NFC_V2_1)
-#ifndef CONFIG_SYS_NAND_LARGEPAGE
-static struct nand_ecclayout nand_hw_eccoob = {
- .eccbytes = 9,
- .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
- .oobfree = { {2, 5} }
-};
-#else
-static struct nand_ecclayout nand_hw_eccoob2k = {
- .eccbytes = 36,
- .eccpos = {
- 7, 8, 9, 10, 11, 12, 13, 14, 15,
- 23, 24, 25, 26, 27, 28, 29, 30, 31,
- 39, 40, 41, 42, 43, 44, 45, 46, 47,
- 55, 56, 57, 58, 59, 60, 61, 62, 63,
- },
- .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
-};
-#endif
-#endif
-
#ifdef CONFIG_MX27
static int is_16bit_nand(void)
{
#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
static int is_16bit_nand(void)
{
- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL)
return 1;
else
return 0;
}
+#elif defined(CONFIG_MX51)
+static int is_16bit_nand(void)
+{
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ if (readl(&src->sbmr) & (1 << 2))
+ return 1;
+ else
+ return 0;
+}
+#elif defined(CONFIG_MX53)
+/* BOOT_CFG[1..3][0..7] */
+#define SRC_BOOT_CFG(m, n) (1 << ((m) * 8 + (n)))
+static int is_16bit_nand(void)
+{
+ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ if (readl(&src->sbmr) & SRC_BOOT_CFG(2, 5))
+ return 1;
+ else
+ return 0;
+}
#else
#warning "8/16 bit NAND autodetection not supported"
static int is_16bit_nand(void)
}
#endif
-static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
-{
- uint32_t *d = dest;
-
- size >>= 2;
- while (size--)
- __raw_writel(__raw_readl(source++), d++);
- return dest;
-}
+#define MXC_NAND_TIMEOUT (1 * HZ)
-/*
- * This function polls the NANDFC to wait for the basic operation to
- * complete by checking the INT bit of config2 register.
- */
-static void wait_op_done(struct mxc_nand_host *host, int max_retries,
- uint16_t param)
-{
- uint32_t tmp;
+#define DRIVER_NAME "mxc_nand"
- while (max_retries-- > 0) {
- if (readw(&host->regs->config2) & NFC_INT) {
- tmp = readw(&host->regs->config2);
- tmp &= ~NFC_INT;
- writew(tmp, &host->regs->config2);
- break;
- }
- udelay(1);
- }
- if (max_retries < 0) {
- MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
- __func__, param);
- }
-}
+#ifndef CONFIG_MXC_NAND_REGS_BASE
+#error CONFIG_MXC_NAND_REGS_BASE not defined
+#endif
-/*
- * This function issues the specified command to the NAND device and
- * waits for completion.
- */
-static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
-{
- MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
+#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
+#define nfc_is_v1() 1
+#define nfc_is_v21() 0
+#define nfc_is_v3_2() 0
+#define nfc_is_v3() nfc_is_v3_2()
+#define NFC_VERSION "V1"
+#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
+#define nfc_is_v1() 0
+#define nfc_is_v21() 1
+#define nfc_is_v3_2() 0
+#define nfc_is_v3() nfc_is_v3_2()
+#define NFC_VERSION "V2"
+#elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#define nfc_is_v1() 0
+#define nfc_is_v21() 0
+#define nfc_is_v3_2() 1
+#define nfc_is_v3() nfc_is_v3_2()
+#define NFC_VERSION "V3"
+#ifndef CONFIG_MXC_NAND_IP_BASE
+#error CONFIG_MXC_NAND_IP_BASE not defined
+#endif
+#else
+#error mxc_nand driver not supported on this platform
+#define NFC_VERSION "unknown"
+#endif
- writew(cmd, &host->regs->flash_cmd);
- writew(NFC_CMD, &host->regs->config2);
+#ifndef CONFIG_MXC_NAND_IP_BASE
+#define CONFIG_MXC_NAND_IP_BASE 0
+#endif
- /* Wait for operation to complete */
- wait_op_done(host, TROP_US_DELAY, cmd);
-}
+/* Addresses for NFC registers */
+#define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
+#define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
+#define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
+#define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
+#define NFC_V1_V2_CONFIG (host->regs + 0x0a)
+#define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
+#define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
+#define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
+#define NFC_V1_V2_WRPROT (host->regs + 0x12)
+#define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
+#define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
+#define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
+#define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
+#define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
+#define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
+#define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
+#define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
+#define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
+#define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
+#define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
+#define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
+#define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
+
+#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
+#define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
+#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
+#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
+#define NFC_V1_V2_CONFIG1_BIG (1 << 5)
+#define NFC_V1_V2_CONFIG1_RST (1 << 6)
+#define NFC_V1_V2_CONFIG1_CE (1 << 7)
+#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
+#define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
+#define NFC_V2_CONFIG1_FP_INT (1 << 11)
+
+#define NFC_V1_V2_CONFIG2_INT (1 << 15)
/*
- * This function sends an address (or partial address) to the
- * NAND device. The address is used to select the source/destination for
- * a NAND command.
+ * Operation modes for the NFC. Valid for v1, v2 and v3
+ * type controllers.
*/
-static void send_addr(struct mxc_nand_host *host, uint16_t addr)
-{
- MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
+#define NFC_CMD (1 << 0)
+#define NFC_ADDR (1 << 1)
+#define NFC_INPUT (1 << 2)
+#define NFC_OUTPUT (1 << 3)
+#define NFC_ID (1 << 4)
+#define NFC_STATUS (1 << 5)
+
+#define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
+#define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
+
+#define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
+#define NFC_V3_CONFIG1_SP_EN (1 << 0)
+#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
+
+#define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
+
+#define NFC_V3_LAUNCH (host->regs_axi + 0x40)
+
+#define NFC_V3_WRPROT (host->regs_ip + 0x0)
+#define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
+#define NFC_V3_WRPROT_LOCK (1 << 1)
+#define NFC_V3_WRPROT_UNLOCK (1 << 2)
+#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
+
+#define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
+
+#define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
+#define NFC_V3_CONFIG2_PS_512 (0 << 0)
+#define NFC_V3_CONFIG2_PS_2048 (1 << 0)
+#define NFC_V3_CONFIG2_PS_4096 (2 << 0)
+#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
+#define NFC_V3_CONFIG2_ECC_EN (1 << 3)
+#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
+#define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
+#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
+#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
+#define MX53_CONFIG2_PPB(x) (((x) & 0x3) << 8)
+#define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
+#define NFC_V3_CONFIG2_INT_MSK (1 << 15)
+#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
+#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
+
+#define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
+#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
+#define NFC_V3_CONFIG3_FW8 (1 << 3)
+#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
+#define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
+#define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
+#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
+
+#define NFC_V3_IPC (host->regs_ip + 0x2C)
+#define NFC_V3_IPC_CREQ (1 << 0)
+#define NFC_V3_IPC_CACK (1 << 1)
+#define NFC_V3_IPC_INT (1 << 31)
+
+#define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
- writew(addr, &host->regs->flash_addr);
- writew(NFC_ADDR, &host->regs->config2);
-
- /* Wait for operation to complete */
- wait_op_done(host, TROP_US_DELAY, addr);
-}
+struct mxc_nand_host {
+ struct mtd_info mtd;
+ struct nand_chip nand;
+
+ void *spare0;
+ void *main_area0;
+
+ void __iomem *base;
+ void __iomem *regs;
+ void __iomem *regs_axi;
+ void __iomem *regs_ip;
+ int status_request;
+ int eccsize;
+ int active_cs;
+
+ uint8_t *data_buf;
+ unsigned int buf_start;
+ int spare_len;
+
+ void (*preset)(struct mtd_info *);
+ void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
+ void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
+ void (*send_page)(struct mtd_info *, unsigned int);
+ void (*send_read_id)(struct mxc_nand_host *);
+ uint16_t (*get_dev_status)(struct mxc_nand_host *);
+ int (*check_int)(struct mxc_nand_host *);
+};
-/*
- * This function requests the NANDFC to initiate the transfer
- * of data currently in the NANDFC RAM buffer to the NAND device.
- */
-static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
- int spare_only)
-{
- if (spare_only)
- MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
+/* OOB placement block for use with hardware ecc generation */
+static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
+ .eccbytes = 5,
+ .eccpos = {6, 7, 8, 9, 10},
+ .oobfree = {{0, 5}, {12, 4}, }
+};
- if (is_mxc_nfc_21()) {
- int i;
- /*
- * The controller copies the 64 bytes of spare data from
- * the first 16 bytes of each of the 4 64 byte spare buffers.
- * Copy the contiguous data starting in spare_area[0] to
- * the four spare area buffers.
- */
- for (i = 1; i < 4; i++) {
- void __iomem *src = &host->regs->spare_area[0][i * 16];
- void __iomem *dst = &host->regs->spare_area[i][0];
+static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
+ .eccbytes = 20,
+ .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
+ 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
+ .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
+};
- mxc_nand_memcpy32(dst, src, 16);
- }
+/* OOB description for 512 byte pages with 16 byte OOB */
+static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
+ .eccbytes = 1 * 9,
+ .eccpos = {
+ 7, 8, 9, 10, 11, 12, 13, 14, 15
+ },
+ .oobfree = {
+ {.offset = 0, .length = 5}
}
+};
- writew(buf_id, &host->regs->buf_addr);
+/* OOB description for 2048 byte pages with 64 byte OOB */
+static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
+ .eccbytes = 4 * 9,
+ .eccpos = {
+ 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 23, 24, 25, 26, 27, 28, 29, 30, 31,
+ 39, 40, 41, 42, 43, 44, 45, 46, 47,
+ 55, 56, 57, 58, 59, 60, 61, 62, 63
+ },
+ .oobfree = {
+ {.offset = 2, .length = 4},
+ {.offset = 16, .length = 7},
+ {.offset = 32, .length = 7},
+ {.offset = 48, .length = 7}
+ }
+};
- /* Configure spare or page+spare access */
- if (!host->pagesize_2k) {
- uint16_t config1 = readw(&host->regs->config1);
- if (spare_only)
- config1 |= NFC_SP_EN;
- else
- config1 &= ~NFC_SP_EN;
- writew(config1, &host->regs->config1);
+/* OOB description for 4096 byte pages with 128 byte OOB */
+static struct nand_ecclayout nandv2_hw_eccoob_4k = {
+ .eccbytes = 8 * 9,
+ .eccpos = {
+ 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 23, 24, 25, 26, 27, 28, 29, 30, 31,
+ 39, 40, 41, 42, 43, 44, 45, 46, 47,
+ 55, 56, 57, 58, 59, 60, 61, 62, 63,
+ 71, 72, 73, 74, 75, 76, 77, 78, 79,
+ 87, 88, 89, 90, 91, 92, 93, 94, 95,
+ 103, 104, 105, 106, 107, 108, 109, 110, 111,
+ 119, 120, 121, 122, 123, 124, 125, 126, 127,
+ },
+ .oobfree = {
+ {.offset = 2, .length = 4},
+ {.offset = 16, .length = 7},
+ {.offset = 32, .length = 7},
+ {.offset = 48, .length = 7},
+ {.offset = 64, .length = 7},
+ {.offset = 80, .length = 7},
+ {.offset = 96, .length = 7},
+ {.offset = 112, .length = 7},
}
+};
- writew(NFC_INPUT, &host->regs->config2);
+static int check_int_v3(struct mxc_nand_host *host)
+{
+ uint32_t tmp;
- /* Wait for operation to complete */
- wait_op_done(host, TROP_US_DELAY, spare_only);
+ tmp = readl(NFC_V3_IPC);
+ if (!(tmp & NFC_V3_IPC_INT))
+ return 0;
+
+ tmp &= ~NFC_V3_IPC_INT;
+ writel(tmp, NFC_V3_IPC);
+
+ return 1;
}
-/*
- * Requests NANDFC to initiate the transfer of data from the
- * NAND device into in the NANDFC ram buffer.
- */
-static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
- int spare_only)
+static int check_int_v1_v2(struct mxc_nand_host *host)
{
- MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
-
- writew(buf_id, &host->regs->buf_addr);
+ uint32_t tmp;
- /* Configure spare or page+spare access */
- if (!host->pagesize_2k) {
- uint32_t config1 = readw(&host->regs->config1);
- if (spare_only)
- config1 |= NFC_SP_EN;
- else
- config1 &= ~NFC_SP_EN;
- writew(config1, &host->regs->config1);
- }
+ tmp = readw(NFC_V1_V2_CONFIG2);
+ if (!(tmp & NFC_V1_V2_CONFIG2_INT))
+ return 0;
- writew(NFC_OUTPUT, &host->regs->config2);
+ writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
- /* Wait for operation to complete */
- wait_op_done(host, TROP_US_DELAY, spare_only);
+ return 1;
+}
- if (is_mxc_nfc_21()) {
- int i;
+/* This function polls the NANDFC to wait for the basic operation to
+ * complete by checking the INT bit of config2 register.
+ */
+static void wait_op_done(struct mxc_nand_host *host, bool useirq)
+{
+ int max_retries = 8000;
- /*
- * The controller copies the 64 bytes of spare data to
- * the first 16 bytes of each of the 4 spare buffers.
- * Make the data contiguous starting in spare_area[0].
- */
- for (i = 1; i < 4; i++) {
- void __iomem *src = &host->regs->spare_area[i][0];
- void __iomem *dst = &host->regs->spare_area[0][i * 16];
+ while (max_retries-- > 0) {
+ if (host->check_int(host))
+ break;
- mxc_nand_memcpy32(dst, src, 16);
- }
+ udelay(1);
}
+ if (max_retries < 0)
+ pr_debug("%s: INT not set\n", __func__);
}
-/* Request the NANDFC to perform a read of the NAND device ID. */
-static void send_read_id(struct mxc_nand_host *host)
+static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
{
- uint16_t tmp;
+ /* fill command */
+ writel(cmd, NFC_V3_FLASH_CMD);
- /* NANDFC buffer 0 is used for device ID output */
- writew(0x0, &host->regs->buf_addr);
-
- /* Read ID into main buffer */
- tmp = readw(&host->regs->config1);
- tmp &= ~NFC_SP_EN;
- writew(tmp, &host->regs->config1);
-
- writew(NFC_ID, &host->regs->config2);
+ /* send out command */
+ writel(NFC_CMD, NFC_V3_LAUNCH);
/* Wait for operation to complete */
- wait_op_done(host, TROP_US_DELAY, 0);
+ wait_op_done(host, useirq);
}
-/*
- * This function requests the NANDFC to perform a read of the
- * NAND device status and returns the current status.
- */
-static uint16_t get_dev_status(struct mxc_nand_host *host)
+/* This function issues the specified command to the NAND device and
+ * waits for completion. */
+static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
{
- void __iomem *main_buf = host->regs->main_area[1];
- uint32_t store;
- uint16_t ret, tmp;
- /* Issue status request to NAND device */
-
- /* store the main area1 first word, later do recovery */
- store = readl(main_buf);
- /* NANDFC buffer 1 is used for device status */
- writew(1, &host->regs->buf_addr);
+ pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
- /* Read status into main buffer */
- tmp = readw(&host->regs->config1);
- tmp &= ~NFC_SP_EN;
- writew(tmp, &host->regs->config1);
-
- writew(NFC_STATUS, &host->regs->config2);
+ writew(cmd, NFC_V1_V2_FLASH_CMD);
+ writew(NFC_CMD, NFC_V1_V2_CONFIG2);
/* Wait for operation to complete */
- wait_op_done(host, TROP_US_DELAY, 0);
-
- /*
- * Status is placed in first word of main buffer
- * get status, then recovery area 1 data
- */
- ret = readw(main_buf);
- writel(store, main_buf);
-
- return ret;
+ wait_op_done(host, useirq);
}
-/* This function is used by upper layer to checks if device is ready */
-static int mxc_nand_dev_ready(struct mtd_info *mtd)
+static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
{
- /*
- * NFC handles R/B internally. Therefore, this function
- * always returns status as ready.
- */
- return 1;
-}
+ /* fill address */
+ writel(addr, NFC_V3_FLASH_ADDR0);
-static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
-{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
- uint16_t tmp = readw(&host->regs->config1);
+ /* send out address */
+ writel(NFC_ADDR, NFC_V3_LAUNCH);
- if (on)
- tmp |= NFC_ECC_EN;
- else
- tmp &= ~NFC_ECC_EN;
- writew(tmp, &host->regs->config1);
+ wait_op_done(host, islast);
}
-#ifdef CONFIG_MXC_NAND_HWECC
-static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+/* This function sends an address (or partial address) to the
+ * NAND device. The address is used to select the source/destination for
+ * a NAND command. */
+static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
{
- /*
- * If HW ECC is enabled, we turn it on during init. There is
- * no need to enable again here.
- */
-}
+ pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
-#ifdef MXC_NFC_V2_1
-static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
- struct nand_chip *chip,
- int page, int sndcmd)
-{
- struct mxc_nand_host *host = chip->priv;
- uint8_t *buf = chip->oob_poi;
- int length = mtd->oobsize;
- int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
- uint8_t *bufpoi = buf;
- int i, toread;
-
- MTDDEBUG(MTD_DEBUG_LEVEL0,
- "%s: Reading OOB area of page %u to oob %p\n",
- __FUNCTION__, host->page_addr, buf);
-
- chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
- for (i = 0; i < chip->ecc.steps; i++) {
- toread = min_t(int, length, chip->ecc.prepad);
- if (toread) {
- chip->read_buf(mtd, bufpoi, toread);
- bufpoi += toread;
- length -= toread;
- }
- bufpoi += chip->ecc.bytes;
- host->col_addr += chip->ecc.bytes;
- length -= chip->ecc.bytes;
-
- toread = min_t(int, length, chip->ecc.postpad);
- if (toread) {
- chip->read_buf(mtd, bufpoi, toread);
- bufpoi += toread;
- length -= toread;
- }
- }
- if (length > 0)
- chip->read_buf(mtd, bufpoi, length);
-
- _mxc_nand_enable_hwecc(mtd, 0);
- chip->cmdfunc(mtd, NAND_CMD_READOOB,
- mtd->writesize + chip->ecc.prepad, page);
- bufpoi = buf + chip->ecc.prepad;
- length = mtd->oobsize - chip->ecc.prepad;
- for (i = 0; i < chip->ecc.steps; i++) {
- toread = min_t(int, length, chip->ecc.bytes);
- chip->read_buf(mtd, bufpoi, toread);
- bufpoi += eccpitch;
- length -= eccpitch;
- host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
- }
- _mxc_nand_enable_hwecc(mtd, 1);
- return 1;
+ writew(addr, NFC_V1_V2_FLASH_ADDR);
+ writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
+
+ /* Wait for operation to complete */
+ wait_op_done(host, islast);
}
-static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
- struct nand_chip *chip,
- uint8_t *buf,
- int page)
+static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
{
- struct mxc_nand_host *host = chip->priv;
- int eccsize = chip->ecc.size;
- int eccbytes = chip->ecc.bytes;
- int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
- uint8_t *oob = chip->oob_poi;
- int steps, size;
- int n;
-
- _mxc_nand_enable_hwecc(mtd, 0);
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr);
-
- for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
- host->col_addr = n * eccsize;
- chip->read_buf(mtd, buf, eccsize);
- buf += eccsize;
-
- host->col_addr = mtd->writesize + n * eccpitch;
- if (chip->ecc.prepad) {
- chip->read_buf(mtd, oob, chip->ecc.prepad);
- oob += chip->ecc.prepad;
- }
-
- chip->read_buf(mtd, oob, eccbytes);
- oob += eccbytes;
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+ uint32_t tmp;
- if (chip->ecc.postpad) {
- chip->read_buf(mtd, oob, chip->ecc.postpad);
- oob += chip->ecc.postpad;
- }
- }
+ tmp = readl(NFC_V3_CONFIG1);
+ tmp &= ~(7 << 4);
+ writel(tmp, NFC_V3_CONFIG1);
- size = mtd->oobsize - (oob - chip->oob_poi);
- if (size)
- chip->read_buf(mtd, oob, size);
- _mxc_nand_enable_hwecc(mtd, 1);
+ /* transfer data from NFC ram to nand */
+ writel(ops, NFC_V3_LAUNCH);
- return 0;
+ wait_op_done(host, false);
}
-static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
- struct nand_chip *chip,
- uint8_t *buf,
- int page)
+static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
{
- struct mxc_nand_host *host = chip->priv;
- int n, eccsize = chip->ecc.size;
- int eccbytes = chip->ecc.bytes;
- int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
- int eccsteps = chip->ecc.steps;
- uint8_t *p = buf;
- uint8_t *oob = chip->oob_poi;
-
- MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
- host->page_addr, buf, oob);
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+ int bufs, i;
- /* first read the data area and the available portion of OOB */
- for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
- int stat;
+ if (nfc_is_v1() && mtd->writesize > 512)
+ bufs = 4;
+ else
+ bufs = 1;
- host->col_addr = n * eccsize;
+ for (i = 0; i < bufs; i++) {
- chip->read_buf(mtd, p, eccsize);
+ /* NANDFC buffer 0 is used for page read/write */
+ writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
- host->col_addr = mtd->writesize + n * eccpitch;
+ writew(ops, NFC_V1_V2_CONFIG2);
- if (chip->ecc.prepad) {
- chip->read_buf(mtd, oob, chip->ecc.prepad);
- oob += chip->ecc.prepad;
- }
+ /* Wait for operation to complete */
+ wait_op_done(host, true);
+ }
+}
- stat = chip->ecc.correct(mtd, p, oob, NULL);
+static void send_read_id_v3(struct mxc_nand_host *host)
+{
+ /* Read ID into main buffer */
+ writel(NFC_ID, NFC_V3_LAUNCH);
- if (stat < 0)
- mtd->ecc_stats.failed++;
- else
- mtd->ecc_stats.corrected += stat;
- oob += eccbytes;
+ wait_op_done(host, true);
- if (chip->ecc.postpad) {
- chip->read_buf(mtd, oob, chip->ecc.postpad);
- oob += chip->ecc.postpad;
- }
- }
+ memcpy(host->data_buf, host->main_area0, 16);
- /* Calculate remaining oob bytes */
- n = mtd->oobsize - (oob - chip->oob_poi);
- if (n)
- chip->read_buf(mtd, oob, n);
-
- /* Then switch ECC off and read the OOB area to get the ECC code */
- _mxc_nand_enable_hwecc(mtd, 0);
- chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, host->page_addr);
- eccsteps = chip->ecc.steps;
- oob = chip->oob_poi + chip->ecc.prepad;
- for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
- host->col_addr = mtd->writesize +
- n * eccpitch +
- chip->ecc.prepad;
- chip->read_buf(mtd, oob, eccbytes);
- oob += eccbytes + chip->ecc.postpad;
- }
- _mxc_nand_enable_hwecc(mtd, 1);
- return 0;
+ pr_debug("read ID %02x %02x %02x %02x\n",
+ host->data_buf[0], host->data_buf[1],
+ host->data_buf[2], host->data_buf[3]);
}
-static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
- struct nand_chip *chip, int page)
+/* Request the NANDFC to perform a read of the NAND device ID. */
+static void send_read_id_v1_v2(struct mxc_nand_host *host)
{
- struct mxc_nand_host *host = chip->priv;
- int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
- int length = mtd->oobsize;
- int i, len, status, steps = chip->ecc.steps;
- const uint8_t *bufpoi = chip->oob_poi;
-
- chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
- for (i = 0; i < steps; i++) {
- len = min_t(int, length, eccpitch);
-
- chip->write_buf(mtd, bufpoi, len);
- bufpoi += len;
- length -= len;
- host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
- }
- if (length > 0)
- chip->write_buf(mtd, bufpoi, length);
+ struct nand_chip *this = &host->nand;
- chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
- status = chip->waitfunc(mtd, chip);
- return status & NAND_STATUS_FAIL ? -EIO : 0;
-}
+ /* NANDFC buffer 0 is used for device ID output */
+ writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
-static void mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
- struct nand_chip *chip,
- const uint8_t *buf)
-{
- struct mxc_nand_host *host = chip->priv;
- int eccsize = chip->ecc.size;
- int eccbytes = chip->ecc.bytes;
- int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
- uint8_t *oob = chip->oob_poi;
- int steps, size;
- int n;
-
- for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
- host->col_addr = n * eccsize;
- chip->write_buf(mtd, buf, eccsize);
- buf += eccsize;
-
- host->col_addr = mtd->writesize + n * eccpitch;
-
- if (chip->ecc.prepad) {
- chip->write_buf(mtd, oob, chip->ecc.prepad);
- oob += chip->ecc.prepad;
- }
+ writew(NFC_ID, NFC_V1_V2_CONFIG2);
- host->col_addr += eccbytes;
- oob += eccbytes;
+ /* Wait for operation to complete */
+ wait_op_done(host, true);
- if (chip->ecc.postpad) {
- chip->write_buf(mtd, oob, chip->ecc.postpad);
- oob += chip->ecc.postpad;
- }
- }
+ memcpy(host->data_buf, host->main_area0, 16);
- size = mtd->oobsize - (oob - chip->oob_poi);
- if (size)
- chip->write_buf(mtd, oob, size);
+ if (this->options & NAND_BUSWIDTH_16) {
+ /* compress the ID info */
+ host->data_buf[1] = host->data_buf[2];
+ host->data_buf[2] = host->data_buf[4];
+ host->data_buf[3] = host->data_buf[6];
+ host->data_buf[4] = host->data_buf[8];
+ host->data_buf[5] = host->data_buf[10];
+ }
}
-static void mxc_nand_write_page_syndrome(struct mtd_info *mtd,
- struct nand_chip *chip,
- const uint8_t *buf)
+static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
{
- struct mxc_nand_host *host = chip->priv;
- int i, n, eccsize = chip->ecc.size;
- int eccbytes = chip->ecc.bytes;
- int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
- int eccsteps = chip->ecc.steps;
- const uint8_t *p = buf;
- uint8_t *oob = chip->oob_poi;
+ writel(NFC_STATUS, NFC_V3_LAUNCH);
+ wait_op_done(host, true);
- chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+ return readl(NFC_V3_CONFIG1) >> 16;
+}
- for (i = n = 0;
- eccsteps;
- n++, eccsteps--, i += eccbytes, p += eccsize) {
- host->col_addr = n * eccsize;
+/* This function requests the NANDFC to perform a read of the
+ * NAND device status and returns the current status. */
+static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
+{
+ void __iomem *main_buf = host->main_area0;
+ uint32_t store;
+ uint16_t ret;
- chip->write_buf(mtd, p, eccsize);
+ writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
- host->col_addr = mtd->writesize + n * eccpitch;
+ /*
+ * The device status is stored in main_area0. To
+ * prevent corruption of the buffer save the value
+ * and restore it afterwards.
+ */
+ store = readl(main_buf);
- if (chip->ecc.prepad) {
- chip->write_buf(mtd, oob, chip->ecc.prepad);
- oob += chip->ecc.prepad;
- }
+ writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
+ wait_op_done(host, true);
- chip->write_buf(mtd, oob, eccbytes);
- oob += eccbytes;
+ ret = readw(main_buf);
- if (chip->ecc.postpad) {
- chip->write_buf(mtd, oob, chip->ecc.postpad);
- oob += chip->ecc.postpad;
- }
- }
+ writel(store, main_buf);
- /* Calculate remaining oob bytes */
- i = mtd->oobsize - (oob - chip->oob_poi);
- if (i)
- chip->write_buf(mtd, oob, i);
+ return ret;
}
-static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
- u_char *read_ecc, u_char *calc_ecc)
+/* This functions is used by upper layer to checks if device is ready */
+static int mxc_nand_dev_ready(struct mtd_info *mtd)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
- uint32_t ecc_status = readl(&host->regs->ecc_status_result);
- int subpages = mtd->writesize / nand_chip->subpagesize;
- int pg2blk_shift = nand_chip->phys_erase_shift -
- nand_chip->page_shift;
-
- do {
- if ((ecc_status & 0xf) > 4) {
- static int last_bad = -1;
-
- if (last_bad != host->page_addr >> pg2blk_shift) {
- last_bad = host->page_addr >> pg2blk_shift;
- printk(KERN_DEBUG
- "MXC_NAND: HWECC uncorrectable ECC error"
- " in block %u page %u subpage %d\n",
- last_bad, host->page_addr,
- mtd->writesize / nand_chip->subpagesize
- - subpages);
- }
- return -1;
- }
- ecc_status >>= 4;
- subpages--;
- } while (subpages > 0);
+ /*
+ * NFC handles R/B internally. Therefore, this function
+ * always returns status as ready.
+ */
+ return 1;
+}
- return 0;
+static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+ /*
+ * If HW ECC is enabled, we turn it on during init. There is
+ * no need to enable again here.
+ */
}
-#else
-#define mxc_nand_read_page_syndrome NULL
-#define mxc_nand_read_page_raw_syndrome NULL
-#define mxc_nand_read_oob_syndrome NULL
-#define mxc_nand_write_page_syndrome NULL
-#define mxc_nand_write_page_raw_syndrome NULL
-#define mxc_nand_write_oob_syndrome NULL
-
-static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
+
+static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{
struct nand_chip *nand_chip = mtd->priv;
* additional correction. 2-Bit errors cannot be corrected by
* HW ECC, so we need to return failure
*/
- uint16_t ecc_status = readw(&host->regs->ecc_status_result);
+ uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT);
if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
- MTDDEBUG(MTD_DEBUG_LEVEL0,
- "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
+ printk("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
return -1;
}
return 0;
}
-#endif
+
+static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
+ u_char *read_ecc, u_char *calc_ecc)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+ u32 ecc_stat, err;
+ int no_subpages = 1;
+ int ret = 0;
+ u8 ecc_bit_mask, err_limit;
+
+ ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
+ err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
+
+ no_subpages = mtd->writesize >> 9;
+
+ if (nfc_is_v21())
+ ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
+ else
+ ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT);
+
+ do {
+ err = ecc_stat & ecc_bit_mask;
+ if (err > err_limit) {
+ printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
+ return -1;
+ } else {
+ ret += err;
+ }
+ ecc_stat >>= 4;
+ } while (--no_subpages);
+
+ mtd->ecc_stats.corrected += ret;
+ if (ret)
+ pr_debug("%d Symbol Correctable RS-ECC Errors\n", ret);
+
+ return ret;
+}
static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{
return 0;
}
-#endif
static u_char mxc_nand_read_byte(struct mtd_info *mtd)
{
struct nand_chip *nand_chip = mtd->priv;
struct mxc_nand_host *host = nand_chip->priv;
- uint8_t ret = 0;
- uint16_t col;
- uint16_t __iomem *main_buf =
- (uint16_t __iomem *)host->regs->main_area[0];
- uint16_t __iomem *spare_buf =
- (uint16_t __iomem *)host->regs->spare_area[0];
- union {
- uint16_t word;
- uint8_t bytes[2];
- } nfc_word;
+ uint8_t ret;
/* Check for status request */
if (host->status_request)
- return get_dev_status(host) & 0xFF;
+ return host->get_dev_status(host) & 0xFF;
- /* Get column for 16-bit access */
- col = host->col_addr >> 1;
-
- /* If we are accessing the spare region */
- if (host->spare_only)
- nfc_word.word = readw(&spare_buf[col]);
- else
- nfc_word.word = readw(&main_buf[col]);
-
- /* Pick upper/lower byte of word from RAM buffer */
- ret = nfc_word.bytes[host->col_addr & 0x1];
-
- /* Update saved column address */
- if (nand_chip->options & NAND_BUSWIDTH_16)
- host->col_addr += 2;
- else
- host->col_addr++;
+ ret = *(uint8_t *)(host->data_buf + host->buf_start);
+ host->buf_start++;
return ret;
}
{
struct nand_chip *nand_chip = mtd->priv;
struct mxc_nand_host *host = nand_chip->priv;
- uint16_t col, ret;
- uint16_t __iomem *p;
+ uint16_t ret;
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "mxc_nand_read_word(col = %d)\n", host->col_addr);
-
- col = host->col_addr;
- /* Adjust saved column address */
- if (col < mtd->writesize && host->spare_only)
- col += mtd->writesize;
-
- if (col < mtd->writesize) {
- p = (uint16_t __iomem *)(host->regs->main_area[0] +
- (col >> 1));
- } else {
- p = (uint16_t __iomem *)(host->regs->spare_area[0] +
- ((col - mtd->writesize) >> 1));
- }
-
- if (col & 1) {
- union {
- uint16_t word;
- uint8_t bytes[2];
- } nfc_word[3];
-
- nfc_word[0].word = readw(p);
- nfc_word[1].word = readw(p + 1);
-
- nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
- nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
-
- ret = nfc_word[2].word;
- } else {
- ret = readw(p);
- }
-
- /* Update saved column address */
- host->col_addr = col + 2;
+ ret = *(uint16_t *)(host->data_buf + host->buf_start);
+ host->buf_start += 2;
return ret;
}
-/*
- * Write data of length len to buffer buf. The data to be
+/* Write data of length len to buffer buf. The data to be
* written on NAND Flash is first copied to RAMbuffer. After the Data Input
- * Operation by the NFC, the data is written to NAND Flash
- */
+ * Operation by the NFC, the data is written to NAND Flash */
static void mxc_nand_write_buf(struct mtd_info *mtd,
const u_char *buf, int len)
{
struct nand_chip *nand_chip = mtd->priv;
struct mxc_nand_host *host = nand_chip->priv;
- int n, col, i = 0;
+ u16 col = host->buf_start;
+ int n = mtd->oobsize + mtd->writesize - col;
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
- len);
+ n = min(n, len);
- col = host->col_addr;
+ memcpy(host->data_buf + col, buf, n);
- /* Adjust saved column address */
- if (col < mtd->writesize && host->spare_only)
- col += mtd->writesize;
+ host->buf_start += n;
+}
- n = mtd->writesize + mtd->oobsize - col;
- n = min(len, n);
+/* Read the data buffer from the NAND Flash. To read the data from NAND
+ * Flash first the data output cycle is initiated by the NFC, which copies
+ * the data to RAMbuffer. This data of length len is then copied to buffer buf.
+ */
+static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+ u16 col = host->buf_start;
+ int n = mtd->oobsize + mtd->writesize - col;
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
+ n = min(n, len);
- while (n > 0) {
- void __iomem *p;
+ memcpy(buf, host->data_buf + col, n);
- if (col < mtd->writesize) {
- p = host->regs->main_area[0] + (col & ~3);
- } else {
- p = host->regs->spare_area[0] -
- mtd->writesize + (col & ~3);
- }
+ host->buf_start += n;
+}
- MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
- __LINE__, p);
+/* Used by the upper layer to verify the data in NAND Flash
+ * with the data in the buf. */
+static int mxc_nand_verify_buf(struct mtd_info *mtd,
+ const u_char *buf, int len)
+{
+ return -EFAULT;
+}
- if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
- union {
- uint32_t word;
- uint8_t bytes[4];
- } nfc_word;
+/* This function is used by upper layer for select and
+ * deselect of the NAND chip */
+static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
- nfc_word.word = readl(p);
- nfc_word.bytes[col & 3] = buf[i++];
- n--;
- col++;
+ if (nfc_is_v21()) {
+ host->active_cs = chip;
+ writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
+ }
+}
- writel(nfc_word.word, p);
- } else {
- int m = mtd->writesize - col;
+/*
+ * Function to transfer data to/from spare area.
+ */
+static void copy_spare(struct mtd_info *mtd, bool bfrom)
+{
+ struct nand_chip *this = mtd->priv;
+ struct mxc_nand_host *host = this->priv;
+ u16 i, j;
+ u16 n = mtd->writesize >> 9;
+ u8 *d = host->data_buf + mtd->writesize;
+ u8 *s = host->spare0;
+ u16 t = host->spare_len;
+
+ j = (mtd->oobsize / n >> 1) << 1;
+
+ if (bfrom) {
+ for (i = 0; i < n - 1; i++)
+ memcpy(d + i * j, s + i * t, j);
+
+ /* the last section */
+ memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
+ } else {
+ for (i = 0; i < n - 1; i++)
+ memcpy(&s[i * t], &d[i * j], j);
- if (col >= mtd->writesize)
- m += mtd->oobsize;
+ /* the last section */
+ memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
+ }
+}
- m = min(n, m) & ~3;
+static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
- __func__, __LINE__, n, m, i, col);
+ /* Write out column address, if necessary */
+ if (column != -1) {
+ /*
+ * MXC NANDFC can only perform full page+spare or
+ * spare-only read/write. When the upper layers
+ * perform a read/write buf operation, the saved column
+ * address is used to index into the full page.
+ */
+ host->send_addr(host, 0, page_addr == -1);
+ if (mtd->writesize > 512)
+ /* another col addr cycle for 2k page */
+ host->send_addr(host, 0, false);
+ }
- mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
- col += m;
- i += m;
- n -= m;
+ /* Write out page address, if necessary */
+ if (page_addr != -1) {
+ /* paddr_0 - p_addr_7 */
+ host->send_addr(host, (page_addr & 0xff), false);
+
+ if (mtd->writesize > 512) {
+ if (mtd->size >= 0x10000000) {
+ /* paddr_8 - paddr_15 */
+ host->send_addr(host, (page_addr >> 8) & 0xff, false);
+ host->send_addr(host, (page_addr >> 16) & 0xff, true);
+ } else
+ /* paddr_8 - paddr_15 */
+ host->send_addr(host, (page_addr >> 8) & 0xff, true);
+ } else {
+ /* One more address cycle for higher density devices */
+ if (mtd->size >= 0x4000000) {
+ /* paddr_8 - paddr_15 */
+ host->send_addr(host, (page_addr >> 8) & 0xff, false);
+ host->send_addr(host, (page_addr >> 16) & 0xff, true);
+ } else
+ /* paddr_8 - paddr_15 */
+ host->send_addr(host, (page_addr >> 8) & 0xff, true);
}
}
- /* Update saved column address */
- host->col_addr = col;
}
/*
- * Read the data buffer from the NAND Flash. To read the data from NAND
- * Flash first the data output cycle is initiated by the NFC, which copies
- * the data to RAMbuffer. This data of length len is then copied to buffer buf.
+ * v2 and v3 type controllers can do 4bit or 8bit ecc depending
+ * on how much oob the nand chip has. For 8bit ecc we need at least
+ * 26 bytes of oob data per 512 byte block.
*/
-static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+static int get_eccsize(struct mtd_info *mtd)
{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
- int n, col, i = 0;
+ int oobbytes_per_512 = 0;
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
+ oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
- col = host->col_addr;
+ if (oobbytes_per_512 < 26)
+ return 4;
+ else
+ return 8;
+}
- /* Adjust saved column address */
- if (col < mtd->writesize && host->spare_only)
- col += mtd->writesize;
+static void preset_v1_v2(struct mtd_info *mtd)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct mxc_nand_host *host = nand_chip->priv;
+ uint16_t config1 = 0;
- n = mtd->writesize + mtd->oobsize - col;
- n = min(len, n);
+ if (nand_chip->ecc.mode == NAND_ECC_HW)
+ config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
- while (n > 0) {
- void __iomem *p;
+ if (nfc_is_v21())
+ config1 |= NFC_V2_CONFIG1_FP_INT;
- if (col < mtd->writesize) {
- p = host->regs->main_area[0] + (col & ~3);
- } else {
- p = host->regs->spare_area[0] -
- mtd->writesize + (col & ~3);
- }
+ if (nfc_is_v21() && mtd->writesize) {
+ uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
- if (((col | (int)&buf[i]) & 3) || n < 4) {
- union {
- uint32_t word;
- uint8_t bytes[4];
- } nfc_word;
+ host->eccsize = get_eccsize(mtd);
+ if (host->eccsize == 4)
+ config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
- nfc_word.word = readl(p);
- buf[i++] = nfc_word.bytes[col & 3];
- n--;
- col++;
- } else {
- int m = mtd->writesize - col;
+ config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
+ } else {
+ host->eccsize = 1;
+ }
- if (col >= mtd->writesize)
- m += mtd->oobsize;
+ writew(config1, NFC_V1_V2_CONFIG1);
+ /* preset operation */
- m = min(n, m) & ~3;
- mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
+ /* Unlock the internal RAM Buffer */
+ writew(0x2, NFC_V1_V2_CONFIG);
- col += m;
- i += m;
- n -= m;
- }
- }
- /* Update saved column address */
- host->col_addr = col;
+ /* Blocks to be unlocked */
+ if (nfc_is_v21()) {
+ writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
+ writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
+ writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
+ writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
+ writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
+ writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
+ writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
+ writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
+ } else if (nfc_is_v1()) {
+ writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
+ writew(0x4000, NFC_V1_UNLOCKEND_BLKADDR);
+ } else
+ BUG();
+
+ /* Unlock Block Command for given address range */
+ writew(0x4, NFC_V1_V2_WRPROT);
}
-/*
- * Used by the upper layer to verify the data in NAND Flash
- * with the data in the buf.
- */
-static int mxc_nand_verify_buf(struct mtd_info *mtd,
- const u_char *buf, int len)
+static void preset_v3(struct mtd_info *mtd)
{
- u_char tmp[256];
- uint bsize;
+ struct nand_chip *chip = mtd->priv;
+ struct mxc_nand_host *host = chip->priv;
+ uint32_t config2, config3;
+ int i, addr_phases;
- while (len) {
- bsize = min(len, 256);
- mxc_nand_read_buf(mtd, tmp, bsize);
+ writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
+ writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
+ WARN_ON(!(readl(NFC_V3_IPC) & NFC_V3_IPC_CACK));
- if (memcmp(buf, tmp, bsize))
- return 1;
+ /* Unlock the internal RAM Buffer */
+ writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
+ NFC_V3_WRPROT);
- buf += bsize;
- len -= bsize;
+ /* Blocks to be unlocked */
+ for (i = 0; i < CONFIG_SYS_NAND_MAX_CHIPS; i++)
+ writel(0x0 | (0xffff << 16),
+ NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
+
+ config2 = NFC_V3_CONFIG2_ONE_CYCLE |
+ NFC_V3_CONFIG2_2CMD_PHASES |
+ NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
+ NFC_V3_CONFIG2_ST_CMD(0x70) |
+ NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
+
+ if (chip->ecc.mode == NAND_ECC_HW)
+ config2 |= NFC_V3_CONFIG2_ECC_EN;
+
+ addr_phases = fls(chip->pagemask) >> 3;
+
+ if (mtd->writesize == 2048) {
+ config2 |= NFC_V3_CONFIG2_PS_2048;
+ config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
+ } else if (mtd->writesize == 4096) {
+ config2 |= NFC_V3_CONFIG2_PS_4096;
+ config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
+ } else {
+ config2 |= NFC_V3_CONFIG2_PS_512;
+ config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
}
- return 0;
-}
+ if (mtd->writesize) {
+#if defined CONFIG_MX53
+ config2 |= MX53_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
+#else
+ config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
+#endif
+ host->eccsize = get_eccsize(mtd);
+ if (host->eccsize == 8)
+ config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
+ }
-/*
- * This function is used by upper layer for select and
- * deselect of the NAND chip
- */
-static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
-{
- struct nand_chip *nand_chip = mtd->priv;
- struct mxc_nand_host *host = nand_chip->priv;
+ writel(config2, NFC_V3_CONFIG2);
- switch (chip) {
- case -1:
- /* TODO: Disable the NFC clock */
- if (host->clk_act)
- host->clk_act = 0;
- break;
- case 0:
- /* TODO: Enable the NFC clock */
- if (!host->clk_act)
- host->clk_act = 1;
- break;
+ config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
+ NFC_V3_CONFIG3_NO_SDMA |
+ NFC_V3_CONFIG3_RBB_MODE |
+ NFC_V3_CONFIG3_SBB(6) | /* Reset default */
+ NFC_V3_CONFIG3_ADD_OP(0);
- default:
- break;
- }
+ if (!(chip->options & NAND_BUSWIDTH_16))
+ config3 |= NFC_V3_CONFIG3_FW8;
+
+ writel(config3, NFC_V3_CONFIG3);
+
+ writel(0, NFC_V3_DELAY_LINE);
+ writel(0, NFC_V3_IPC);
}
-/*
- * Used by the upper layer to write command to NAND Flash for
- * different operations to be carried out on NAND Flash
- */
-void mxc_nand_command(struct mtd_info *mtd, unsigned command,
+/* Used by the upper layer to write command to NAND Flash for
+ * different operations to be carried out on NAND Flash */
+static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
int column, int page_addr)
{
struct nand_chip *nand_chip = mtd->priv;
struct mxc_nand_host *host = nand_chip->priv;
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
+ pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
command, column, page_addr);
/* Reset command state information */
/* Command pre-processing step */
switch (command) {
+ case NAND_CMD_RESET:
+ host->preset(mtd);
+ host->send_cmd(host, command, false);
+ break;
case NAND_CMD_STATUS:
- host->col_addr = 0;
+ host->buf_start = 0;
host->status_request = true;
- break;
- case NAND_CMD_READ0:
- host->page_addr = page_addr;
- host->col_addr = column;
- host->spare_only = false;
+ host->send_cmd(host, command, true);
+ mxc_do_addr_cycle(mtd, column, page_addr);
break;
+ case NAND_CMD_READ0:
case NAND_CMD_READOOB:
- host->col_addr = column;
- host->spare_only = true;
- if (host->pagesize_2k)
- command = NAND_CMD_READ0; /* only READ0 is valid */
- break;
+ if (command == NAND_CMD_READ0)
+ host->buf_start = column;
+ else
+ host->buf_start = column + mtd->writesize;
- case NAND_CMD_SEQIN:
- if (column >= mtd->writesize) {
- /*
- * before sending SEQIN command for partial write,
- * we need read one page out. FSL NFC does not support
- * partial write. It always sends out 512+ecc+512+ecc
- * for large page nand flash. But for small page nand
- * flash, it does support SPARE ONLY operation.
- */
- if (host->pagesize_2k) {
- /* call ourself to read a page */
- mxc_nand_command(mtd, NAND_CMD_READ0, 0,
- page_addr);
- }
-
- host->col_addr = column - mtd->writesize;
- host->spare_only = true;
-
- /* Set program pointer to spare region */
- if (!host->pagesize_2k)
- send_cmd(host, NAND_CMD_READOOB);
- } else {
- host->spare_only = false;
- host->col_addr = column;
+ command = NAND_CMD_READ0; /* only READ0 is valid */
- /* Set program pointer to page start */
- if (!host->pagesize_2k)
- send_cmd(host, NAND_CMD_READ0);
- }
- break;
+ host->send_cmd(host, command, false);
+ mxc_do_addr_cycle(mtd, column, page_addr);
- case NAND_CMD_PAGEPROG:
- send_prog_page(host, 0, host->spare_only);
+ if (mtd->writesize > 512)
+ host->send_cmd(host, NAND_CMD_READSTART, true);
- if (host->pagesize_2k && is_mxc_nfc_1()) {
- /* data in 4 areas */
- send_prog_page(host, 1, host->spare_only);
- send_prog_page(host, 2, host->spare_only);
- send_prog_page(host, 3, host->spare_only);
- }
+ host->send_page(mtd, NFC_OUTPUT);
+ memcpy(host->data_buf, host->main_area0, mtd->writesize);
+ copy_spare(mtd, true);
break;
- }
-
- /* Write out the command to the device. */
- send_cmd(host, command);
- /* Write out column address, if necessary */
- if (column != -1) {
- /*
- * MXC NANDFC can only perform full page+spare or
- * spare-only read/write. When the upper layers perform
- * a read/write buffer operation, we will use the saved
- * column address to index into the full page.
- */
- send_addr(host, 0);
- if (host->pagesize_2k)
- /* another col addr cycle for 2k page */
- send_addr(host, 0);
- }
-
- /* Write out page address, if necessary */
- if (page_addr != -1) {
- u32 page_mask = nand_chip->pagemask;
- do {
- send_addr(host, page_addr & 0xFF);
- page_addr >>= 8;
- page_mask >>= 8;
- } while (page_mask);
- }
-
- /* Command post-processing step */
- switch (command) {
-
- case NAND_CMD_RESET:
- break;
+ case NAND_CMD_SEQIN:
+ if (column >= mtd->writesize)
+ /* call ourself to read a page */
+ mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
- case NAND_CMD_READOOB:
- case NAND_CMD_READ0:
- if (host->pagesize_2k) {
- /* send read confirm command */
- send_cmd(host, NAND_CMD_READSTART);
- /* read for each AREA */
- send_read_page(host, 0, host->spare_only);
- if (is_mxc_nfc_1()) {
- send_read_page(host, 1, host->spare_only);
- send_read_page(host, 2, host->spare_only);
- send_read_page(host, 3, host->spare_only);
- }
- } else {
- send_read_page(host, 0, host->spare_only);
- }
- break;
+ host->buf_start = column;
- case NAND_CMD_READID:
- host->col_addr = 0;
- send_read_id(host);
+ host->send_cmd(host, command, false);
+ mxc_do_addr_cycle(mtd, column, page_addr);
break;
case NAND_CMD_PAGEPROG:
+ memcpy(host->main_area0, host->data_buf, mtd->writesize);
+ copy_spare(mtd, false);
+ host->send_page(mtd, NFC_INPUT);
+ host->send_cmd(host, command, true);
+ mxc_do_addr_cycle(mtd, column, page_addr);
break;
- case NAND_CMD_STATUS:
+ case NAND_CMD_READID:
+ host->send_cmd(host, command, true);
+ mxc_do_addr_cycle(mtd, column, page_addr);
+ host->send_read_id(host);
+ host->buf_start = column;
break;
+ case NAND_CMD_ERASE1:
case NAND_CMD_ERASE2:
+ host->send_cmd(host, command, false);
+ mxc_do_addr_cycle(mtd, column, page_addr);
+
break;
}
}
-#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
-
-static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
-static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
+/*
+ * The generic flash bbt decriptors overlap with our ecc
+ * hardware, so define some i.MX specific ones.
+ */
+static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
+static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
static struct nand_bbt_descr bbt_main_descr = {
- .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
- NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
- .offs = 0,
+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_WRITE |
+ NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+ .offs = 0,
.len = 4,
.veroffs = 4,
.maxblocks = 4,
};
static struct nand_bbt_descr bbt_mirror_descr = {
- .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
- NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
- .offs = 0,
+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_WRITE |
+ NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+ .offs = 0,
.len = 4,
.veroffs = 4,
.maxblocks = 4,
.pattern = mirror_pattern,
};
-#endif
-
-int board_nand_init(struct nand_chip *this)
+static void mxc_nand_chip_init(int devno)
{
- struct mtd_info *mtd;
-#ifdef MXC_NFC_V2_1
- uint16_t tmp;
-#endif
-
-#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
- this->options |= NAND_USE_FLASH_BBT;
- this->bbt_td = &bbt_main_descr;
- this->bbt_md = &bbt_mirror_descr;
-#endif
+ int err;
+ struct nand_chip *this;
+ struct mtd_info *mtd = &nand_info[devno];
+ struct nand_ecclayout *oob_smallpage, *oob_largepage;
+
+ /* allocate a minimal buffer for the read_id command */
+ host->data_buf = malloc(16);
+ if (!host->data_buf) {
+ printk("Failed to allocate ID buffer\n");
+ return;
+ }
/* structures must be linked */
- mtd = &host->mtd;
+ this = &host->nand;
+// host->mtd = mtd;
mtd->priv = this;
- host->nand = this;
+ mtd->name = DRIVER_NAME;
- /* 5 us command delay time */
+ /* 50 us command delay time */
this->chip_delay = 5;
this->priv = host;
this->read_buf = mxc_nand_read_buf;
this->verify_buf = mxc_nand_verify_buf;
- host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
- host->clk_act = 1;
+ host->base = (void __iomem *)CONFIG_MXC_NAND_REGS_BASE;
+ if (!host->base) {
+ return;
+ }
-#ifdef CONFIG_MXC_NAND_HWECC
- this->ecc.calculate = mxc_nand_calculate_ecc;
- this->ecc.hwctl = mxc_nand_enable_hwecc;
- this->ecc.correct = mxc_nand_correct_data;
- if (is_mxc_nfc_21()) {
- this->ecc.mode = NAND_ECC_HW_SYNDROME;
- this->ecc.read_page = mxc_nand_read_page_syndrome;
- this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
- this->ecc.read_oob = mxc_nand_read_oob_syndrome;
- this->ecc.write_page = mxc_nand_write_page_syndrome;
- this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
- this->ecc.write_oob = mxc_nand_write_oob_syndrome;
- this->ecc.bytes = 9;
- this->ecc.prepad = 7;
- } else {
- this->ecc.mode = NAND_ECC_HW;
+ host->main_area0 = host->base;
+
+ if (nfc_is_v1() || nfc_is_v21()) {
+ host->preset = preset_v1_v2;
+ host->send_cmd = send_cmd_v1_v2;
+ host->send_addr = send_addr_v1_v2;
+ host->send_page = send_page_v1_v2;
+ host->send_read_id = send_read_id_v1_v2;
+ host->get_dev_status = get_dev_status_v1_v2;
+ host->check_int = check_int_v1_v2;
}
- host->pagesize_2k = 0;
+ if (nfc_is_v21()) {
+ host->regs = host->base + 0x1e00;
+ host->spare0 = host->base + 0x1000;
+ host->spare_len = 64;
+ oob_smallpage = &nandv2_hw_eccoob_smallpage;
+ oob_largepage = &nandv2_hw_eccoob_largepage;
+ this->ecc.bytes = 9;
+ } else if (nfc_is_v1()) {
+ host->regs = host->base + 0xe00;
+ host->spare0 = host->base + 0x800;
+ host->spare_len = 16;
+ oob_smallpage = &nandv1_hw_eccoob_smallpage;
+ oob_largepage = &nandv1_hw_eccoob_largepage;
+ this->ecc.bytes = 3;
+ host->eccsize = 1;
+ } else if (nfc_is_v3_2()) {
+ host->regs_ip = (void __iomem *)CONFIG_MXC_NAND_IP_BASE;
+ host->regs_axi = host->base + 0x1e00;
+ host->spare0 = host->base + 0x1000;
+ host->spare_len = 64;
+ host->preset = preset_v3;
+ host->send_cmd = send_cmd_v3;
+ host->send_addr = send_addr_v3;
+ host->send_page = send_page_v3;
+ host->send_read_id = send_read_id_v3;
+ host->check_int = check_int_v3;
+ host->get_dev_status = get_dev_status_v3;
+ oob_smallpage = &nandv2_hw_eccoob_smallpage;
+ oob_largepage = &nandv2_hw_eccoob_largepage;
+ } else
+ hang();
this->ecc.size = 512;
- _mxc_nand_enable_hwecc(mtd, 1);
+ this->ecc.layout = oob_smallpage;
+
+#ifdef CONFIG_MXC_NAND_HWECC
+ this->ecc.calculate = mxc_nand_calculate_ecc;
+ this->ecc.hwctl = mxc_nand_enable_hwecc;
+ if (nfc_is_v1())
+ this->ecc.correct = mxc_nand_correct_data_v1;
+ else
+ this->ecc.correct = mxc_nand_correct_data_v2_v3;
+ this->ecc.mode = NAND_ECC_HW;
#else
- this->ecc.layout = &nand_soft_eccoob;
this->ecc.mode = NAND_ECC_SOFT;
- _mxc_nand_enable_hwecc(mtd, 0);
#endif
- /* Reset NAND */
- this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
-
- /* NAND bus width determines access functions used by upper layer */
+ /* NAND bus width determines access funtions used by upper layer */
if (is_16bit_nand())
this->options |= NAND_BUSWIDTH_16;
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
- host->pagesize_2k = 1;
- this->ecc.layout = &nand_hw_eccoob2k;
-#else
- host->pagesize_2k = 0;
- this->ecc.layout = &nand_hw_eccoob;
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+ this->options |= NAND_USE_FLASH_BBT;
+ this->bbt_td = &bbt_main_descr;
+ this->bbt_md = &bbt_mirror_descr;
+ this->bbt_td->options |= NAND_BBT_CREATE;
+ this->bbt_md->options |= NAND_BBT_CREATE;
#endif
-#ifdef MXC_NFC_V2_1
- tmp = readw(&host->regs->config1);
- tmp |= NFC_ONE_CYCLE;
- tmp |= NFC_4_8N_ECC;
- writew(tmp, &host->regs->config1);
- if (host->pagesize_2k)
- writew(64/2, &host->regs->spare_area_size);
- else
- writew(16/2, &host->regs->spare_area_size);
-#endif
+ /* first scan to find the device and get the page size */
+ if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
+ return;
+ }
- /*
- * preset operation
- * Unlock the internal RAM Buffer
- */
- writew(0x2, &host->regs->config);
+ host->data_buf = realloc(host->data_buf,
+ mtd->writesize + mtd->oobsize);
+ if (!host->data_buf) {
+ printk("Failed to allocate data buffer of %u byte\n",
+ mtd->writesize + mtd->oobsize);
+ return;
+ }
+ pr_debug("Allocated %u byte data buffer\n",
+ mtd->writesize + mtd->oobsize);
+
+ /* Call preset again, with correct writesize this time */
+ host->preset(mtd);
+
+ if (mtd->writesize == 2048)
+ this->ecc.layout = oob_largepage;
+ if (nfc_is_v21() && mtd->writesize == 4096)
+ this->ecc.layout = &nandv2_hw_eccoob_4k;
+
+ /* second phase scan */
+ err = nand_scan_tail(mtd);
+ if (err) {
+ printk("Nand scan failed: %d\n", err);
+ return;
+ }
- /* Blocks to be unlocked */
- writew(0x0, &host->regs->unlockstart_blkaddr);
- /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
- * unlockend_blkaddr, but the magic 0x4000 does not always work
- * when writing more than some 32 megabytes (on 2k page nands)
- * However 0xFFFF doesn't seem to have this kind
- * of limitation (tried it back and forth several times).
- * The linux kernel driver sets this to 0xFFFF for the v2 controller
- * only, but probably this was not tested there for v1.
- * The very same limitation seems to apply to this kernel driver.
- * This might be NAND chip specific and the i.MX31 datasheet is
- * extremely vague about the semantics of this register.
- */
- writew(0xFFFF, &host->regs->unlockend_blkaddr);
+ err = nand_register(devno);
+ if (err)
+ return;
+}
- /* Unlock Block Command for given address range */
- writew(0x4, &host->regs->wrprot);
+void board_nand_init(void)
+{
+ int i;
- return 0;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ mxc_nand_chip_init(i);
}
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
+//#define DEBUG
#include <common.h>
#include <linux/mtd/mtd.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/regs-bch.h>
+#include <asm/arch/regs-gpmi.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/dma.h>
#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
+#ifndef CONFIG_MX6Q
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
+#else
+#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE (512 / 4)
+#endif
+
#define MXS_NAND_METADATA_SIZE 10
#define MXS_NAND_COMMAND_BUFFER_SIZE 32
+/* BCH timeout in microseconds */
#define MXS_NAND_BCH_TIMEOUT 10000
+static struct bch_regs *bch_regs = (void *)BCH_BASE_ADDRESS;
+static struct gpmi_regs *gpmi_regs = (void *)GPMI_BASE_ADDRESS;
struct mxs_nand_info {
int cur_chip;
uint32_t desc_index;
};
+#ifdef DEBUG
+#define dump_reg(b, r) __dump_reg(&b->r, #r)
+static inline void __dump_reg(void *addr, const char *name)
+{
+ printf("%16s[%p]=%08x\n", name, addr, readl(addr));
+}
+
+#define dump_bch_reg(n) __dump_reg(&bch_regs->hw_bch_##n, #n)
+#define dump_gpmi_reg(n) __dump_reg(&gpmi_regs->hw_gpmi_##n, #n)
+static inline void dump_regs(void)
+{
+ printf("BCH:\n");
+ dump_bch_reg(ctrl);
+ dump_bch_reg(status0);
+ dump_bch_reg(mode);
+ dump_bch_reg(debug0);
+ dump_bch_reg(dbgkesread);
+ dump_bch_reg(dbgcsferead);
+ dump_bch_reg(dbgsyndegread);
+ dump_bch_reg(dbgahbmread);
+ dump_bch_reg(blockname);
+ dump_bch_reg(version);
+
+ printf("\nGPMI:\n");
+ dump_gpmi_reg(ctrl0);
+ dump_gpmi_reg(eccctrl);
+ dump_gpmi_reg(ecccount);
+ dump_gpmi_reg(payload);
+ dump_gpmi_reg(auxiliary);
+ dump_gpmi_reg(ctrl1);
+ dump_gpmi_reg(data);
+ dump_gpmi_reg(stat);
+ dump_gpmi_reg(debug);
+ dump_gpmi_reg(version);
+ dump_gpmi_reg(debug2);
+ dump_gpmi_reg(debug3);
+}
+
+static inline int dbg_addr(void *addr)
+{
+ if (((unsigned long)addr & ~0xfff) == BCH_BASE_ADDRESS)
+ return 1;
+ return 1;
+}
+
+static inline u32 mxs_readl(void *addr,
+ const char *fn, int ln)
+{
+ u32 val = readl(addr);
+ static void *last_addr;
+ static u32 last_val;
+
+ if (!dbg_addr(addr))
+ return val;
+
+ if (addr != last_addr || last_val != val) {
+ printf("%s@%d: Read %08x from %p\n", fn, ln, val, addr);
+ last_addr = addr;
+ last_val = val;
+ }
+ return val;
+}
+
+static inline void mxs_writel(u32 val, void *addr,
+ const char *fn, int ln)
+{
+ if (dbg_addr(addr))
+ printf("%s@%d: Writing %08x to %p...", fn, ln, val, addr);
+ writel(val, addr);
+ if (dbg_addr(addr))
+ printf(" result: %08x\n", readl(addr));
+}
+
+#undef readl
+#define readl(a) mxs_readl(a, __func__, __LINE__)
+
+#undef writel
+#define writel(v, a) mxs_writel(v, a, __func__, __LINE__)
+static inline void memdump(const void *addr, size_t len)
+{
+ const char *buf = addr;
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (i % 16 == 0) {
+ if (i > 0)
+ printf("\n");
+ printf("%p:", &buf[i]);
+ }
+ printf(" %02x", buf[i]);
+ }
+ printf("\n");
+}
+#else
+static inline void memdump(void *addr, size_t len)
+{
+}
+
+static inline void dump_regs(void)
+{
+}
+#endif
+
struct nand_ecclayout fake_ecc_layout;
/*
info->desc_index = 0;
}
-static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
+static uint32_t mxs_nand_ecc_chunk_cnt(struct mtd_info *mtd)
{
- return page_data_size / MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
+ struct nand_chip *nand = mtd->priv;
+ return mtd->writesize / nand->ecc.size;
}
static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
}
+static int mxs_nand_gpmi_init(void)
+{
+ int ret;
+
+ /* Reset the GPMI block. */
+ ret = mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
+ if (ret)
+ return ret;
+
+ /*
+ * Choose NAND mode, set IRQ polarity, disable write protection and
+ * select BCH ECC.
+ */
+ clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
+ GPMI_CTRL1_GPMI_MODE,
+ GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
+ GPMI_CTRL1_BCH_MODE);
+ writel(0x500 << 16, &gpmi_regs->hw_gpmi_timing1);
+ return 0;
+}
+
static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
uint32_t page_oob_size)
{
*/
static int mxs_nand_wait_for_bch_complete(void)
{
- struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
int timeout = MXS_NAND_BCH_TIMEOUT;
int ret;
ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
BCH_CTRL_COMPLETE_IRQ, timeout);
+ if (ret) {
+ debug("%s@%d: %d\n", __func__, __LINE__, ret);
+ mxs_nand_gpmi_init();
+ }
writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
/* Execute the DMA chain. */
ret = mxs_dma_go(channel);
- if (ret)
- printf("MXS NAND: Error sending command\n");
+ if (ret) {
+ int i;
+
+ printf("MXS NAND: Error sending command %08lx\n", d->cmd.pio_words[0]);
+ for (i = 0; i < nand_info->cmd_queue_len; i++) {
+ printf("%02x ", nand_info->cmd_buf[i]);
+ }
+ printf("\n");
+ }
mxs_nand_return_dma_descs(nand_info);
{
struct nand_chip *chip = mtd->priv;
struct mxs_nand_info *nand_info = chip->priv;
- struct mxs_gpmi_regs *gpmi_regs =
- (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
uint32_t tmp;
tmp = readl(&gpmi_regs->hw_gpmi_stat);
uint32_t src;
uint32_t dst;
-
+return;
bit_offset = mxs_nand_mark_bit_offset(mtd);
buf_offset = mxs_nand_mark_byte_offset(mtd);
dst = oob_buf[0];
+ debug("Swapping byte %02x @ %03x.%d with %02x @ %03x\n",
+ src & 0xff, buf_offset, bit_offset, dst & 0xff, 0);
+
oob_buf[0] = src;
data_buf[buf_offset] &= ~(0xff << bit_offset);
return;
}
+ memset(buf, 0xee, length);
+
/* Compile the DMA descriptor - a descriptor that reads data. */
d = mxs_nand_get_dma_desc(nand_info);
d->cmd.data =
length;
mxs_dma_desc_append(channel, d);
-
+#ifndef CONFIG_MX6Q
/*
* A DMA descriptor that waits for the command to end and the chip to
* become ready.
GPMI_CTRL0_ADDRESS_NAND_DATA;
mxs_dma_desc_append(channel, d);
-
+#endif
/* Execute the DMA chain. */
ret = mxs_dma_go(channel);
if (ret) {
- printf("MXS NAND: DMA read error\n");
+ printf("%s: DMA read error\n", __func__);
goto rtn;
}
/* Execute the DMA chain. */
ret = mxs_dma_go(channel);
if (ret)
- printf("MXS NAND: DMA write error\n");
+ printf("%s: DMA write error\n", __func__);
mxs_nand_return_dma_descs(nand_info);
}
return buf;
}
+static void flush_buffers(struct mtd_info *mtd, struct mxs_nand_info *nand_info)
+{
+ flush_dcache_range((unsigned long)nand_info->data_buf,
+ (unsigned long)nand_info->data_buf +
+ mtd->writesize);
+ flush_dcache_range((unsigned long)nand_info->oob_buf,
+ (unsigned long)nand_info->oob_buf +
+ mtd->oobsize);
+}
+
/*
* Read a page from NAND.
*/
d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
+ flush_buffers(mtd, nand_info);
+
mxs_dma_desc_append(channel, d);
/* Compile the DMA descriptor - disable the BCH block. */
/* Execute the DMA chain. */
ret = mxs_dma_go(channel);
if (ret) {
- printf("MXS NAND: DMA read error\n");
+ printf("%s: DMA read error\n", __func__);
goto rtn;
}
/* Loop over status bytes, accumulating ECC status. */
status = nand_info->oob_buf + mxs_nand_aux_status_offset();
- for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) {
+ for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd); i++) {
if (status[i] == 0x00)
continue;
GPMI_ECCCTRL_ENABLE_ECC |
GPMI_ECCCTRL_ECC_CMD_ENCODE |
GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
- d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
+ d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
+ flush_buffers(mtd, nand_info);
+
mxs_dma_desc_append(channel, d);
/* Flush caches */
/* Execute the DMA chain. */
ret = mxs_dma_go(channel);
if (ret) {
- printf("MXS NAND: DMA write error\n");
+ printf("%s: DMA write error\n", __func__);
goto rtn;
}
ret = mxs_nand_wait_for_bch_complete();
if (ret) {
- printf("MXS NAND: BCH write timeout\n");
+ printf("%s: BCH write timeout\n", __func__);
goto rtn;
}
/*
* Nominally, the purpose of this function is to look for or create the bad
* block table. In fact, since the we call this function at the very end of
- * the initialization process started by nand_scan(), and we doesn't have a
+ * the initialization process started by nand_scan(), and we don't have a
* more formal mechanism, we "hook" this function to continue init process.
*
* At this point, the physical NAND Flash chips have been identified and
{
struct nand_chip *nand = mtd->priv;
struct mxs_nand_info *nand_info = nand->priv;
- struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
uint32_t tmp;
/* Configure BCH and set NFC geometry */
- mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
+ if (readl(&bch_regs->hw_bch_ctrl_reg) &
+ (BCH_CTRL_SFTRST | BCH_CTRL_CLKGATE))
+ /* When booting from NAND the BCH engine will already
+ * be operational and obviously does not like being reset here.
+ * There will be occasional read errors upon boot when this
+ * reset is done.
+ */
+ mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
+ readl(&bch_regs->hw_bch_ctrl_reg);
+
+ debug("mtd->writesize=%d\n", mtd->writesize);
+ debug("mtd->oobsize=%d\n", mtd->oobsize);
+ debug("ecc_strength=%d\n", mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize));
/* Configure layout 0 */
- tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
+ tmp = (mxs_nand_ecc_chunk_cnt(mtd) - 1)
<< BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
/* DMA buffers */
buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
if (!buf) {
- printf("MXS NAND: Error allocating DMA buffers\n");
+ printf("%s: Error allocating DMA buffers\n", __func__);
return -ENOMEM;
}
*/
int mxs_nand_init(struct mxs_nand_info *info)
{
- struct mxs_gpmi_regs *gpmi_regs =
- (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
- struct mxs_bch_regs *bch_regs =
- (struct mxs_bch_regs *)MXS_BCH_BASE;
- int i = 0, j;
+ int ret;
+ int i;
info->desc = malloc(sizeof(struct mxs_dma_desc *) *
MXS_NAND_DMA_DESCRIPTOR_COUNT);
- if (!info->desc)
+ if (!info->desc) {
+ printf("MXS NAND: Unable to allocate DMA descriptor table\n");
+ ret = -ENOMEM;
goto err1;
+ }
+
+ mxs_dma_init();
/* Allocate the DMA descriptors. */
for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
info->desc[i] = mxs_dma_desc_alloc();
- if (!info->desc[i])
+ if (!info->desc[i]) {
+ printf("MXS NAND: Unable to allocate DMA descriptors\n");
+ ret = -ENOMEM;
goto err2;
+ }
}
/* Init the DMA controller. */
- for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
- j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
- if (mxs_dma_init_channel(j))
+ for (i = 0; i < CONFIG_SYS_NAND_MAX_CHIPS; i++) {
+ const int chan = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + i;
+
+ ret = mxs_dma_init_channel(chan);
+ if (ret) {
+ printf("Failed to initialize DMA channel %d\n", chan);
goto err3;
+ }
}
- /* Reset the GPMI block. */
- mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
- mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
-
- /*
- * Choose NAND mode, set IRQ polarity, disable write protection and
- * select BCH ECC.
- */
- clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
- GPMI_CTRL1_GPMI_MODE,
- GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
- GPMI_CTRL1_BCH_MODE);
+ ret = mxs_nand_gpmi_init();
+ if (ret)
+ goto err3;
return 0;
err3:
- for (--j; j >= 0; j--)
- mxs_dma_release(j);
+ for (--i; i >= 0; i--)
+ mxs_dma_release(i + MXS_DMA_CHANNEL_AHB_APBH_GPMI0);
+ i = MXS_NAND_DMA_DESCRIPTOR_COUNT - 1;
err2:
free(info->desc);
-err1:
for (--i; i >= 0; i--)
mxs_dma_desc_free(info->desc[i]);
- printf("MXS NAND: Unable to allocate DMA descriptors\n");
- return -ENOMEM;
+err1:
+ return ret;
}
/*!
nand->priv = nand_info;
nand->options |= NAND_NO_SUBPAGE_WRITE;
-
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+ nand->options |= NAND_USE_FLASH_BBT | NAND_USE_FLASH_BBT_NO_OOB;
+#endif
nand->cmd_ctrl = mxs_nand_cmd_ctrl;
nand->dev_ready = mxs_nand_device_ready;
return NULL;
}
-#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
-
/**
* nand_do_write_ops - [Internal] NAND write with ECC
* @mtd: MTD device structure
chip->ecc.steps = mtd->writesize / chip->ecc.size;
if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
printk(KERN_WARNING "Invalid ecc parameters\n");
+ printk(KERN_WARNING "steps=%d size=%d writesize=%d\n",
+ chip->ecc.steps, chip->ecc.size, mtd->writesize);
BUG();
}
chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
mtd->ecc_stats.bbtblocks++;
continue;
}
- MTDDEBUG(MTD_DEBUG_LEVEL0, "nand_read_bbt: " \
- "Bad block at 0x%012llx\n",
- (loff_t)((offs << 2) + (act >> 1))
- << this->bbt_erase_shift);
+ MTDDEBUG(MTD_DEBUG_LEVEL0, "nand_read_bbt: Bad block at 0x%012llx\n",
+ (loff_t)((offs << 2) + (act >> 1)) << this->bbt_erase_shift);
/* Factory marked bad or worn out ? */
if (tmp == 0)
this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06);
if (td->pages[i] == -1)
printk(KERN_WARNING "Bad block table not found for chip %d\n", i);
else
- MTDDEBUG(MTD_DEBUG_LEVEL0, "Bad block table found " \
- "at page %d, version 0x%02X\n", td->pages[i],
- td->version[i]);
+ MTDDEBUG(MTD_DEBUG_LEVEL0,
+ "Bad block table found at page %d, version 0x%02X\n",
+ td->pages[i], td->version[i]);
}
return 0;
}
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
{
- unsigned int block, lastblock;
+ unsigned int block, lastblock, bad = 0;
unsigned int page;
+ const int ppb = CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
+ int maxbad;
+#ifdef CONFIG_SYS_NAND_MAXBAD
+ maxbad = CONFIG_SYS_NAND_MAXBAD;
+#else
+ maxbad = mtd.size;
+#endif
/*
* offs has to be aligned to a page address!
*/
* Skip bad blocks
*/
while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
- nand_read_page(block, page, dst);
+ if (nand_chip.ecc.read_page) {
+ int ret;
+
+ ret = nand_chip.ecc.read_page(&mtd, &nand_chip,
+ dst, block * ppb + page);
+ if (ret) {
+ if (page > 0)
+ dst -= (page - 1) * CONFIG_SYS_NAND_PAGE_SIZE;
+ bad++;
+ lastblock++;
+ break;
+ }
+ } else {
+ nand_read_page(block, page, dst);
+ }
dst += CONFIG_SYS_NAND_PAGE_SIZE;
page++;
}
page = 0;
} else {
+ printf("Skipping bad block %d\n", block);
+ bad++;
lastblock++;
}
+ if (maxbad > 0 && bad > maxbad) {
+ printf("Too many bad blocks encountered\n");
+ return -1;
+ }
+
block++;
}
/* nand_init() - initialize data to make nand usable by SPL */
void nand_init(void)
{
+ static struct nand_buffers ecc_buf;
+
/*
* Init board specific nand support
*/
mtd.priv = &nand_chip;
+ mtd.erasesize = CONFIG_SYS_NAND_BLOCK_SIZE;
+ mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
+ mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
+
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
(void __iomem *)CONFIG_SYS_NAND_BASE;
+ nand_chip.oob_poi = ecc_buf.databuf;
+ nand_chip.buffers = &ecc_buf;
+
board_nand_init(&nand_chip);
#ifdef CONFIG_SPL_NAND_SOFTECC
COBJS-$(CONFIG_SPI_FLASH_WINBOND) += winbond.o
COBJS-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
COBJS-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
+COBJS-$(CONFIG_SPI_FLASH_IMX) += imx_spi_nor.o
+COBJS-$(CONFIG_SPI_FLASH_IMX_SST) += imx_spi_nor_sst.o
+COBJS-$(CONFIG_SPI_FLASH_IMX_ATMEL) += imx_spi_nor_atmel.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <asm/errno.h>
+#include <linux/types.h>
+#include <malloc.h>
+
+#include <imx_spi.h>
+#include <imx_spi_nor.h>
+
+static u8 g_tx_buf[256];
+static u8 g_rx_buf[256];
+
+#define WRITE_ENABLE(a) spi_nor_cmd_1byte(a, WREN)
+#define ENABLE_WRITE_STATUS(a) spi_nor_cmd_1byte(a, EWSR)
+
+struct imx_spi_flash_params {
+ u8 idcode1;
+ u32 block_size;
+ u32 block_count;
+ u32 device_size;
+ const char *name;
+};
+
+struct imx_spi_flash {
+ const struct imx_spi_flash_params *params;
+ struct spi_flash flash;
+};
+
+static inline struct imx_spi_flash *
+to_imx_spi_flash(struct spi_flash *flash)
+{
+ return container_of(flash, struct imx_spi_flash, flash);
+}
+
+static const struct imx_spi_flash_params imx_spi_flash_table[] = {
+ {
+ .idcode1 = 0x27,
+ .block_size = SZ_64K,
+ .block_count = 64,
+ .device_size = SZ_64K * 64,
+ .name = "AT45DB321D - 4MB",
+ },
+};
+
+static s32 spi_nor_flash_query(struct spi_flash *flash, void* data)
+{
+ u8 au8Tmp[4] = { 0 };
+ u8 *pData = (u8 *)data;
+
+ g_tx_buf[3] = JEDEC_ID;
+
+ if (spi_xfer(flash->spi, (4 << 3), g_tx_buf, au8Tmp,
+ SPI_XFER_BEGIN | SPI_XFER_END)) {
+ return -1;
+ }
+
+ printf("JEDEC ID: 0x%02x:0x%02x:0x%02x\n",
+ au8Tmp[2], au8Tmp[1], au8Tmp[0]);
+
+ pData[0] = au8Tmp[2];
+ pData[1] = au8Tmp[1];
+ pData[2] = au8Tmp[0];
+
+ return 0;
+}
+
+static s32 spi_nor_status(struct spi_flash *flash)
+{
+ g_tx_buf[1] = STAT_READ;
+
+ if (spi_xfer(flash->spi, 2 << 3, g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf("Error: %s(): %d\n", __func__, __LINE__);
+ return 0;
+ }
+ return g_rx_buf[0];
+}
+
+#if 0
+/*!
+ * Erase a block_size data from block_addr offset in the flash
+ */
+static int spi_nor_erase_page(struct spi_flash *flash,
+ void *page_addr)
+{
+ u32 addr = (u32)page_addr;
+
+ if ((addr & 512) != 0) {
+ printf("Error - page_addr is not "
+ "512 Bytes aligned: %p\n",
+ page_addr);
+ return -1;
+ }
+
+ /* now do the block erase */
+ if (spi_xfer(flash->spi, 4 << 3, g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ return -1;
+ }
+
+ while (spi_nor_status(flash) & RDSR_BUSY)
+ ;
+
+ return 0;
+}
+#endif
+
+static int spi_nor_flash_read(struct spi_flash *flash, u32 offset,
+ size_t len, void *buf)
+{
+ struct imx_spi_flash *imx_sf = to_imx_spi_flash(flash);
+ u32 *cmd = (u32 *)g_tx_buf;
+ u32 max_rx_sz = (MAX_SPI_BYTES) - 4;
+ u8 *d_buf = (u8 *)buf;
+ u8 *s_buf;
+ s32 s32remain_size = len;
+ int i;
+
+ if (!(flash->spi))
+ return -1;
+
+ printf("Reading SPI NOR flash 0x%x [0x%x bytes] -> ram 0x%p\n",
+ offset, len, buf);
+ debug("%s(from flash=0x%08x to ram=%p len=0x%x)\n",
+ __func__,
+ offset, buf, len);
+
+ if (len == 0)
+ return 0;
+
+ *cmd = (READ << 24) | ((u32)offset & 0x00FFFFFF);
+
+ for (; s32remain_size > 0;
+ s32remain_size -= max_rx_sz, *cmd += max_rx_sz) {
+ debug("Addr:0x%p=>Offset:0x%08x, %d bytes transferred\n",
+ d_buf,
+ (*cmd & 0x00FFFFFF),
+ (len - s32remain_size));
+ debug("%d%% completed\n", ((len - s32remain_size) * 100 / len));
+
+ if (s32remain_size < max_rx_sz) {
+ debug("100%% completed\n");
+
+ if (spi_xfer(flash->spi, (s32remain_size + 4) << 3,
+ g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf("Error: %s(%d): failed\n",
+ __FILE__, __LINE__);
+ return -1;
+ }
+ /* throw away 4 bytes (5th received bytes is real) */
+ s_buf = g_rx_buf + 4;
+
+ /* now adjust the endianness */
+ for (i = s32remain_size; i >= 0; i -= 4, s_buf += 4) {
+ if (i < 4) {
+ if (i == 1) {
+ *d_buf = s_buf[0];
+ } else if (i == 2) {
+ *d_buf++ = s_buf[1];
+ *d_buf++ = s_buf[0];
+ } else if (i == 3) {
+ *d_buf++ = s_buf[2];
+ *d_buf++ = s_buf[1];
+ *d_buf++ = s_buf[0];
+ }
+ printf("SUCCESS\n\n");
+ return 0;
+ }
+ /* copy 4 bytes */
+ *d_buf++ = s_buf[3];
+ *d_buf++ = s_buf[2];
+ *d_buf++ = s_buf[1];
+ *d_buf++ = s_buf[0];
+ }
+ }
+
+ /* now grab max_rx_sz data (+4 is
+ *needed due to 4-throw away bytes */
+ if (spi_xfer(flash->spi, (max_rx_sz + 4) << 3,
+ g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf("Error: %s(%d): failed\n", __FILE__, __LINE__);
+ return -1;
+ }
+ /* throw away 4 bytes (5th received bytes is real) */
+ s_buf = g_rx_buf + 4;
+ /* now adjust the endianness */
+ for (i = 0; i < max_rx_sz; i += 4, s_buf += 4) {
+ *d_buf++ = s_buf[3];
+ *d_buf++ = s_buf[2];
+ *d_buf++ = s_buf[1];
+ *d_buf++ = s_buf[0];
+ }
+
+ if ((s32remain_size % imx_sf->params->block_size) == 0)
+ printf(".");
+ }
+ printf("SUCCESS\n\n");
+
+ return -1;
+}
+
+static int spi_nor_flash_write(struct spi_flash *flash, u32 offset,
+ size_t len, const void *buf)
+{
+ u32 d_addr = offset;
+ u8 *s_buf = (u8 *)buf;
+ unsigned int final_addr = 0;
+ int page_size = 528, trans_bytes = 0, buf_ptr = 0,
+ bytes_sent = 0, byte_sent_per_iter = 0;
+ int page_no = 0, buf_addr = 0, page_off = 0,
+ i = 0, j = 0, k = 0, fifo_size = 32;
+ int remain_len = 0;
+
+ if (!(flash->spi))
+ return -1;
+
+ if (len == 0)
+ return 0;
+
+ printf("Writing SPI NOR flash 0x%x [0x%x bytes] <- ram 0x%p\n",
+ offset, len, buf);
+ debug("%s(flash addr=0x%08x, ram=%p, len=0x%x)\n",
+ __func__, offset, buf, len);
+
+ /* Read the status register to get the Page size */
+ if (spi_nor_status(flash) & STAT_PG_SZ) {
+ page_size = 512;
+ } else {
+ puts("Unsupported Page Size of 528 bytes\n");
+ g_tx_buf[0] = CONFIG_REG4;
+ g_tx_buf[1] = CONFIG_REG3;
+ g_tx_buf[2] = CONFIG_REG2;
+ g_tx_buf[3] = CONFIG_REG1;
+
+ if (spi_xfer(flash->spi, 4 << 3, g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf("Error: %s(): %d", __func__, __LINE__);
+ return -1;
+ }
+
+ while (!(spi_nor_status(flash) & STAT_BUSY))
+ ;
+
+ puts("Reprogrammed the Page Size to 512 bytes\n");
+ puts("Please Power Cycle the board for the change to take effect\n");
+
+ return -1;
+ }
+
+ /* Due to the way CSPI operates send data less
+ that 4 bytes in a different manner */
+ remain_len = len % 4;
+ if (remain_len)
+ len -= remain_len;
+
+ while (1) {
+ page_no = d_addr / page_size;
+ /* Get the offset within the page
+ if address is not page-aligned */
+ page_off = (d_addr % page_size);
+ if (page_off) {
+ if (page_no == 0)
+ buf_addr = d_addr;
+ else
+ buf_addr = page_off;
+
+ trans_bytes = page_size - buf_addr;
+ } else {
+ buf_addr = 0;
+ trans_bytes = page_size;
+ }
+
+ if (len <= 0)
+ break;
+
+ if (trans_bytes > len)
+ trans_bytes = len;
+
+ bytes_sent = trans_bytes;
+ /* Write the data to the SPI-NOR Buffer first */
+ while (trans_bytes > 0) {
+ final_addr = (buf_addr & 0x3FF);
+ g_tx_buf[0] = final_addr;
+ g_tx_buf[1] = final_addr >> 8;
+ g_tx_buf[2] = final_addr >> 16;
+ g_tx_buf[3] = BUF1_WR; /*Opcode */
+
+ /* 4 bytes already used for Opcode & address bytes,
+ check to ensure we do not overflow the SPI TX buffer */
+ if (trans_bytes > (fifo_size - 4))
+ byte_sent_per_iter = fifo_size;
+ else
+ byte_sent_per_iter = trans_bytes + 4;
+
+ for (i = 4; i < byte_sent_per_iter; i += 4) {
+ g_tx_buf[i + 3] = s_buf[buf_ptr++];
+ g_tx_buf[i + 2] = s_buf[buf_ptr++];
+ g_tx_buf[i + 1] = s_buf[buf_ptr++];
+ g_tx_buf[i] = s_buf[buf_ptr++];
+ }
+
+ if (spi_xfer(flash->spi, byte_sent_per_iter << 3,
+ g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf("Error: %s(%d): failed\n",
+ __FILE__, __LINE__);
+ return -1;
+ }
+
+ while (!(spi_nor_status(flash) & STAT_BUSY))
+ ;
+
+ /* Deduct 4 bytes as it is used for Opcode & address bytes */
+ trans_bytes -= (byte_sent_per_iter - 4);
+ /* Update the destination buffer address */
+ buf_addr += (byte_sent_per_iter - 4);
+ }
+
+ /* Send the command to write data from the SPI-NOR Buffer to Flash memory */
+ final_addr = (page_size == 512) ? ((page_no & 0x1FFF) << 9) : \
+ ((page_no & 0x1FFF) << 10);
+
+ /* Specify the Page address in Flash where the data should be written to */
+ g_tx_buf[0] = final_addr;
+ g_tx_buf[1] = final_addr >> 8;
+ g_tx_buf[2] = final_addr >> 16;
+ g_tx_buf[3] = BUF1_TO_MEM; /*Opcode */
+ if (spi_xfer(flash->spi, 4 << 3, g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf("Error: %s(%d): failed\n", __FILE__, __LINE__);
+ return -1;
+ }
+
+ while (!(spi_nor_status(flash) & STAT_BUSY))
+ ;
+
+ d_addr += bytes_sent;
+ len -= bytes_sent;
+ if (d_addr % (page_size * 50) == 0)
+ puts(".");
+ }
+
+ if (remain_len) {
+ buf_ptr += remain_len;
+ /* Write the remaining data bytes first */
+ for (i = 0; i < remain_len; ++i)
+ g_tx_buf[i] = s_buf[buf_ptr--];
+
+ /* Write the address bytes next in the same word
+ as the data byte from the next byte */
+ for (j = i, k = 0; j < 4; j++, k++)
+ g_tx_buf[j] = final_addr >> (k * 8);
+
+ /* Write the remaining address bytes in the next word */
+ j = 0;
+ final_addr = (buf_addr & 0x3FF);
+
+ for (j = 0; k < 3; j++, k++)
+ g_tx_buf[j] = final_addr >> (k * 8);
+
+ /* Finally the Opcode to write the data to the buffer */
+ g_tx_buf[j] = BUF1_WR; /*Opcode */
+
+ if (spi_xfer(flash->spi, (remain_len + 4) << 3,
+ g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf("Error: %s(%d): failed\n", __FILE__, __LINE__);
+ return -1;
+ }
+
+ while (!(spi_nor_status(flash) & STAT_BUSY))
+ ;
+
+ if (page_size == 512)
+ final_addr = (page_no & 0x1FFF) << 9;
+ else
+ final_addr = (page_no & 0x1FFF) << 10;
+
+ g_tx_buf[0] = final_addr;
+ g_tx_buf[1] = final_addr >> 8;
+ g_tx_buf[2] = final_addr >> 16;
+ g_tx_buf[3] = BUF1_TO_MEM; /*Opcode */
+ if (spi_xfer(flash->spi, 4 << 3, g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf("Error: %s(%d): failed\n", __FILE__, __LINE__);
+ return -1;
+ }
+
+ while (!(spi_nor_status(flash) & STAT_BUSY))
+ ;
+ }
+
+ printf("SUCCESS\n\n");
+
+ return 0;
+}
+
+static int spi_nor_flash_erase(struct spi_flash *flash, u32 offset,
+ size_t len)
+{
+ printf("Erase is built in program.\n");
+
+ return 0;
+}
+
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int spi_mode)
+{
+ struct spi_slave *spi = NULL;
+ const struct imx_spi_flash_params *params = NULL;
+ struct imx_spi_flash *imx_sf = NULL;
+ u8 idcode[4] = { 0 };
+ u32 i = 0;
+ s32 ret = 0;
+
+ if (CONFIG_SPI_FLASH_CS != cs) {
+ printf("Invalid cs for SPI NOR.\n");
+ return NULL;
+ }
+
+ spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+
+ if (!spi) {
+ debug("SF: Failed to set up slave\n");
+ return NULL;
+ }
+
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ debug("SF: Failed to claim SPI bus: %d\n", ret);
+ goto err_claim_bus;
+ }
+
+ imx_sf = (struct imx_spi_flash *)malloc(sizeof(struct imx_spi_flash));
+
+ if (!imx_sf) {
+ debug("SF: Failed to allocate memory\n");
+ spi_free_slave(spi);
+ return NULL;
+ }
+
+ imx_sf->flash.spi = spi;
+
+ /* Read the ID codes */
+ ret = spi_nor_flash_query(&(imx_sf->flash), idcode);
+ if (ret)
+ goto err_read_id;
+
+ for (i = 0; i < ARRAY_SIZE(imx_spi_flash_table); ++i) {
+ params = &imx_spi_flash_table[i];
+ if (params->idcode1 == idcode[1])
+ break;
+ }
+
+ if (i == ARRAY_SIZE(imx_spi_flash_table)) {
+ debug("SF: Unsupported DataFlash ID %02x\n",
+ idcode[1]);
+
+ goto err_invalid_dev;
+ }
+
+ imx_sf->params = params;
+
+ imx_sf->flash.name = params->name;
+ imx_sf->flash.size = params->device_size;
+
+ imx_sf->flash.read = spi_nor_flash_read;
+ imx_sf->flash.write = spi_nor_flash_write;
+ imx_sf->flash.erase = spi_nor_flash_erase;
+
+ debug("SF: Detected %s with block size %lu, "
+ "block count %lu, total %u bytes\n",
+ params->name,
+ params->block_size,
+ params->block_count,
+ params->device_size);
+
+ return &(imx_sf->flash);
+
+err_read_id:
+ spi_release_bus(spi);
+err_invalid_dev:
+ if (imx_sf)
+ free(imx_sf);
+err_claim_bus:
+ if (spi)
+ spi_free_slave(spi);
+ return NULL;
+}
+
+void spi_flash_free(struct spi_flash *flash)
+{
+ struct imx_spi_flash *imx_sf = NULL;
+
+ if (!flash)
+ return;
+
+ imx_sf = to_imx_spi_flash(flash);
+
+ if (flash->spi) {
+ spi_free_slave(flash->spi);
+ flash->spi = NULL;
+ }
+
+ free(imx_sf);
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <asm/errno.h>
+#include <linux/types.h>
+#include <malloc.h>
+
+#include <imx_spi.h>
+#include <imx_spi_nor.h>
+
+static u8 g_tx_buf[256];
+static u8 g_rx_buf[256];
+
+#define WRITE_ENABLE(a) spi_nor_cmd_1byte(a, WREN)
+#define WRITE_DISABLE(a) spi_nor_cmd_1byte(a, WRDI)
+#define ENABLE_WRITE_STATUS(a) spi_nor_cmd_1byte(a, EWSR)
+
+struct imx_spi_flash_params {
+ u8 idcode1;
+ u32 block_size;
+ u32 block_count;
+ u32 device_size;
+ const char *name;
+};
+
+struct imx_spi_flash {
+ const struct imx_spi_flash_params *params;
+ struct spi_flash flash;
+};
+
+static inline struct imx_spi_flash *
+to_imx_spi_flash(struct spi_flash *flash)
+{
+ return container_of(flash, struct imx_spi_flash, flash);
+}
+
+static const struct imx_spi_flash_params imx_spi_flash_table[] = {
+ {
+ .idcode1 = 0x25,
+ .block_size = SZ_64K,
+ .block_count = 32,
+ .device_size = SZ_64K * 32,
+ .name = "SST25VF016B - 2MB",
+ },
+};
+
+static s32 spi_nor_flash_query(struct spi_flash *flash, void* data)
+{
+ u8 au8Tmp[4] = { 0 };
+ u8 *pData = (u8 *)data;
+
+ g_tx_buf[3] = JEDEC_ID;
+
+ if (spi_xfer(flash->spi, (4 << 3), g_tx_buf, au8Tmp,
+ SPI_XFER_BEGIN | SPI_XFER_END)) {
+ return -1;
+ }
+
+ printf("JEDEC ID: 0x%02x:0x%02x:0x%02x\n",
+ au8Tmp[2], au8Tmp[1], au8Tmp[0]);
+
+ pData[0] = au8Tmp[2];
+ pData[1] = au8Tmp[1];
+ pData[2] = au8Tmp[0];
+
+ return 0;
+}
+
+static s32 spi_nor_cmd_1byte(struct spi_flash *flash, u8 cmd)
+{
+ g_tx_buf[0] = cmd;
+
+ if (spi_xfer(flash->spi, (1 << 3), g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf("Error: %s(): %d\n", __func__, __LINE__);
+ return -1;
+ }
+ return 0;
+}
+
+static s32 spi_nor_status(struct spi_flash *flash)
+{
+ g_tx_buf[1] = RDSR;
+
+ if (spi_xfer(flash->spi, 2 << 3, g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf("Error: %s(): %d\n", __func__, __LINE__);
+ return 0;
+ }
+ return g_rx_buf[0];
+}
+
+static int spi_nor_program_1byte(struct spi_flash *flash,
+ u8 data, void *addr)
+{
+ u32 addr_val = (u32)addr;
+
+ /* need to do write-enable command */
+ if (WRITE_ENABLE(flash) != 0) {
+ printf("Error : %d\n", __LINE__);
+ return -1;
+ }
+ g_tx_buf[0] = BYTE_PROG; /* need to skip bytes 1, 2, 3 */
+ g_tx_buf[4] = data;
+ g_tx_buf[5] = addr_val & 0xFF;
+ g_tx_buf[6] = (addr_val >> 8) & 0xFF;
+ g_tx_buf[7] = (addr_val >> 16) & 0xFF;
+
+ debug("0x%x: 0x%x\n", *(u32 *)g_tx_buf, *(u32 *)(g_tx_buf + 4));
+ debug("addr=0x%x\n", addr_val);
+
+ if (spi_xfer(flash->spi, 5 << 3, g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf("Error: %s(%d): failed\n", __FILE__, __LINE__);
+ return -1;
+ }
+
+ while (spi_nor_status(flash) & RDSR_BUSY)
+ ;
+
+ return 0;
+}
+
+/*!
+ * Write 'val' to flash WRSR (write status register)
+ */
+static int spi_nor_write_status(struct spi_flash *flash, u8 val)
+{
+ g_tx_buf[0] = val;
+ g_tx_buf[1] = WRSR;
+
+ if (spi_xfer(flash->spi, 2 << 3, g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf("Error: %s(): %d\n", __func__, __LINE__);
+ return -1;
+ }
+ return 0;
+}
+
+/*!
+ * Erase a block_size data from block_addr offset in the flash
+ */
+static int spi_nor_erase_block(struct spi_flash *flash,
+ void *block_addr, u32 block_size)
+{
+ u32 *cmd = (u32 *)g_tx_buf;
+ u32 addr = (u32) block_addr;
+
+ if (block_size != SZ_64K &&
+ block_size != SZ_32K &&
+ block_size != SZ_4K) {
+ printf("Error - block_size is not "
+ "4kB, 32kB or 64kB: 0x%x\n",
+ block_size);
+ return -1;
+ }
+
+ if ((addr & (block_size - 1)) != 0) {
+ printf("Error - block_addr is not "
+ "4kB, 32kB or 64kB aligned: %p\n",
+ block_addr);
+ return -1;
+ }
+
+ if (ENABLE_WRITE_STATUS(flash) != 0 ||
+ spi_nor_write_status(flash, 0) != 0) {
+ printf("Error: %s: %d\n", __func__, __LINE__);
+ return -1;
+ }
+
+ /* need to do write-enable command */
+ if (WRITE_ENABLE(flash) != 0) {
+ printf("Error : %d\n", __LINE__);
+ return -1;
+ }
+
+ if (block_size == SZ_64K)
+ *cmd = (ERASE_64K << 24) | (addr & 0x00FFFFFF);
+ else if (block_size == SZ_32K)
+ *cmd = (ERASE_32K << 24) | (addr & 0x00FFFFFF);
+ else if (block_size == SZ_4K)
+ *cmd = (ERASE_4K << 24) | (addr & 0x00FFFFFF);
+
+ /* now do the block erase */
+ if (spi_xfer(flash->spi, 4 << 3, g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ return -1;
+ }
+
+ while (spi_nor_status(flash) & RDSR_BUSY)
+ ;
+
+ return 0;
+}
+
+static int spi_nor_flash_read(struct spi_flash *flash, u32 offset,
+ size_t len, void *buf)
+{
+ struct imx_spi_flash *imx_sf = to_imx_spi_flash(flash);
+ u32 *cmd = (u32 *)g_tx_buf;
+ u32 max_rx_sz = (MAX_SPI_BYTES) - 4;
+ u8 *d_buf = (u8 *)buf;
+ u8 *s_buf;
+ s32 s32remain_size = len;
+ int i;
+
+ if (!(flash->spi))
+ return -1;
+
+ printf("Reading SPI NOR flash 0x%x [0x%x bytes] -> ram 0x%p\n",
+ offset, len, buf);
+ debug("%s(from flash=0x%08x to ram=%p len=0x%x)\n",
+ __func__,
+ offset, buf, len);
+
+ if (len == 0)
+ return 0;
+
+ *cmd = (READ << 24) | ((u32)offset & 0x00FFFFFF);
+
+ for (; s32remain_size > 0; s32remain_size -= max_rx_sz, *cmd += max_rx_sz) {
+ debug("Addr:0x%p=>Offset:0x%08x, %d bytes transferred\n",
+ d_buf,
+ (*cmd & 0x00FFFFFF),
+ (len - s32remain_size));
+ debug("%d%% completed\n", ((len - s32remain_size) * 100 / len));
+
+ if (s32remain_size < max_rx_sz) {
+ debug("100%% completed\n");
+
+ if (spi_xfer(flash->spi, (s32remain_size + 4) << 3,
+ g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf("Error: %s(%d): failed\n", __FILE__, __LINE__);
+ return -1;
+ }
+ /* throw away 4 bytes (5th received bytes is real) */
+ s_buf = g_rx_buf + 4;
+
+ /* now adjust the endianness */
+ for (i = s32remain_size; i >= 0; i -= 4, s_buf += 4) {
+ if (i < 4) {
+ if (i == 1) {
+ *d_buf = s_buf[0];
+ } else if (i == 2) {
+ *d_buf++ = s_buf[1];
+ *d_buf++ = s_buf[0];
+ } else if (i == 3) {
+ *d_buf++ = s_buf[2];
+ *d_buf++ = s_buf[1];
+ *d_buf++ = s_buf[0];
+ }
+ printf("SUCCESS\n\n");
+ return 0;
+ }
+ /* copy 4 bytes */
+ *d_buf++ = s_buf[3];
+ *d_buf++ = s_buf[2];
+ *d_buf++ = s_buf[1];
+ *d_buf++ = s_buf[0];
+ }
+ }
+
+ /* now grab max_rx_sz data (+4 is
+ *needed due to 4-throw away bytes */
+ if (spi_xfer(flash->spi, (max_rx_sz + 4) << 3,
+ g_tx_buf, g_rx_buf, SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf("Error: %s(%d): failed\n", __FILE__, __LINE__);
+ return -1;
+ }
+ /* throw away 4 bytes (5th received bytes is real) */
+ s_buf = g_rx_buf + 4;
+ /* now adjust the endianness */
+ for (i = 0; i < max_rx_sz; i += 4, s_buf += 4) {
+ *d_buf++ = s_buf[3];
+ *d_buf++ = s_buf[2];
+ *d_buf++ = s_buf[1];
+ *d_buf++ = s_buf[0];
+ }
+
+ if ((s32remain_size % imx_sf->params->block_size) == 0)
+ printf(".");
+ }
+ printf("SUCCESS\n\n");
+
+ return -1;
+}
+
+static int spi_nor_flash_write(struct spi_flash *flash, u32 offset,
+ size_t len, const void *buf)
+{
+ struct imx_spi_flash *imx_sf = to_imx_spi_flash(flash);
+ u32 d_addr = offset;
+ u8 *s_buf = (u8 *)buf;
+ s32 s32remain_size = len;
+
+ if (!(flash->spi))
+ return -1;
+
+ if (len == 0)
+ return 0;
+
+ printf("Writing SPI NOR flash 0x%x [0x%x bytes] <- ram 0x%p\n",
+ offset, len, buf);
+ debug("%s(flash addr=0x%08x, ram=%p, len=0x%x)\n",
+ __func__, offset, buf, len);
+
+ if (ENABLE_WRITE_STATUS(flash) != 0 ||
+ spi_nor_write_status(flash, 0) != 0) {
+ printf("Error: %s: %d\n", __func__, __LINE__);
+ return -1;
+ }
+
+ if ((d_addr & 1) != 0) {
+ /* program 1st byte */
+ if (spi_nor_program_1byte(flash, s_buf[0],
+ (void *)d_addr) != 0) {
+ printf("Error: %s(%d)\n", __func__, __LINE__);
+ return -1;
+ }
+ if (--s32remain_size == 0)
+ return 0;
+ d_addr++;
+ s_buf++;
+ }
+
+ /* need to do write-enable command */
+ if (WRITE_ENABLE(flash) != 0) {
+ printf("Error : %d\n", __LINE__);
+ return -1;
+ }
+
+ /*
+ These two bytes write will be copied to txfifo first with
+ g_tx_buf[1] being shifted out and followed by g_tx_buf[0].
+ The reason for this is we will specify burst len=6. So SPI will
+ do this kind of data movement.
+ */
+ g_tx_buf[0] = d_addr >> 16;
+ g_tx_buf[1] = AAI_PROG; /* need to skip bytes 1, 2 */
+ /* byte shifted order is: 7, 6, 5, 4 */
+ g_tx_buf[4] = s_buf[1];
+ g_tx_buf[5] = s_buf[0];
+ g_tx_buf[6] = d_addr;
+ g_tx_buf[7] = d_addr >> 8;
+ if (spi_xfer(flash->spi, 6 << 3, g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf("Error: %s(%d): failed\n",
+ __FILE__, __LINE__);
+ return -1;
+ }
+
+ while (spi_nor_status(flash) & RDSR_BUSY)
+ ;
+
+ for (d_addr += 2, s_buf += 2, s32remain_size -= 2;
+ s32remain_size > 1;
+ d_addr += 2, s_buf += 2, s32remain_size -= 2) {
+ debug("%d%% transferred\n",
+ ((len - s32remain_size) * 100 / len));
+ /* byte shifted order is: 2,1,0 */
+ g_tx_buf[2] = AAI_PROG;
+ g_tx_buf[1] = s_buf[0];
+ g_tx_buf[0] = s_buf[1];
+
+ if (spi_xfer(flash->spi, 3 << 3, g_tx_buf, g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
+ printf("Error: %s(%d): failed\n",
+ __FILE__, __LINE__);
+ return -1;
+ }
+
+ while (spi_nor_status(flash) & RDSR_BUSY)
+ ;
+
+ if ((s32remain_size % imx_sf->params->block_size) == 0)
+ printf(".");
+ }
+ printf("SUCCESS\n\n");
+ debug("100%% transferred\n");
+
+ WRITE_DISABLE(flash);
+ while (spi_nor_status(flash) & RDSR_BUSY)
+ ;
+
+ if (WRITE_ENABLE(flash) != 0) {
+ printf("Error : %d\n", __LINE__);
+ return -1;
+ }
+
+ if (len == 1) {
+ /* need to do write-enable command */
+ /* only 1 byte left */
+ if (spi_nor_program_1byte(flash, s_buf[0],
+ (void *)d_addr) != 0) {
+ printf("Error: %s(%d)\n",
+ __func__, __LINE__);
+ return -1;
+ }
+ }
+ return 0;
+}
+
+static int spi_nor_flash_erase(struct spi_flash *flash, u32 offset,
+ size_t len)
+{
+ s32 s32remain_size = len;
+
+ if (!(flash->spi))
+ return -1;
+
+ printf("Erasing SPI NOR flash 0x%x [0x%x bytes]\n",
+ offset, len);
+
+ if ((len % SZ_4K) != 0 || len == 0) {
+ printf("Error: size (0x%x) is not integer multiples of 4kB(0x1000)\n",
+ len);
+ return -1;
+ }
+ if ((offset & (SZ_4K - 1)) != 0) {
+ printf("Error - addr is not 4kB(0x1000) aligned: 0x%08x\n",
+ offset);
+ return -1;
+ }
+ for (; s32remain_size > 0; s32remain_size -= SZ_4K, offset += SZ_4K) {
+ debug("Erasing 0x%08x, %d%% erased\n",
+ offset,
+ ((len - s32remain_size) * 100 / len));
+ if (spi_nor_erase_block(flash,
+ (void *)offset, SZ_4K) != 0) {
+ printf("Error: spi_nor_flash_erase(): %d\n", __LINE__);
+ return -1;
+ }
+ printf(".");
+ }
+ printf("SUCCESS\n\n");
+ debug("100%% erased\n");
+ return 0;
+}
+
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int spi_mode)
+{
+ struct spi_slave *spi = NULL;
+ const struct imx_spi_flash_params *params = NULL;
+ struct imx_spi_flash *imx_sf = NULL;
+ u8 idcode[4] = { 0 };
+ u32 i = 0;
+ s32 ret = 0;
+
+ if (CONFIG_SPI_FLASH_CS != cs) {
+ printf("Invalid cs for SPI NOR.\n");
+ return NULL;
+ }
+
+ spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+
+ if (!spi) {
+ debug("SF: Failed to set up slave\n");
+ return NULL;
+ }
+
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ debug("SF: Failed to claim SPI bus: %d\n", ret);
+ goto err_claim_bus;
+ }
+
+ imx_sf = (struct imx_spi_flash *)malloc(sizeof(struct imx_spi_flash));
+
+ if (!imx_sf) {
+ debug("SF: Failed to allocate memory\n");
+ spi_free_slave(spi);
+ return NULL;
+ }
+
+ imx_sf->flash.spi = spi;
+
+ /* Read the ID codes */
+ ret = spi_nor_flash_query(&(imx_sf->flash), idcode);
+ if (ret)
+ goto err_read_id;
+
+ for (i = 0; i < ARRAY_SIZE(imx_spi_flash_table); ++i) {
+ params = &imx_spi_flash_table[i];
+ if (params->idcode1 == idcode[1])
+ break;
+ }
+
+ if (i == ARRAY_SIZE(imx_spi_flash_table)) {
+ debug("SF: Unsupported DataFlash ID %02x\n",
+ idcode[1]);
+
+ goto err_invalid_dev;
+ }
+
+ imx_sf->params = params;
+
+ imx_sf->flash.name = params->name;
+ imx_sf->flash.size = params->device_size;
+
+ imx_sf->flash.read = spi_nor_flash_read;
+ imx_sf->flash.write = spi_nor_flash_write;
+ imx_sf->flash.erase = spi_nor_flash_erase;
+
+ debug("SF: Detected %s with block size %lu, "
+ "block count %lu, total %u bytes\n",
+ params->name,
+ params->block_size,
+ params->block_count,
+ params->device_size);
+
+ return &(imx_sf->flash);
+
+err_read_id:
+ spi_release_bus(spi);
+err_invalid_dev:
+ if (imx_sf)
+ free(imx_sf);
+err_claim_bus:
+ if (spi)
+ spi_free_slave(spi);
+ return NULL;
+}
+
+void spi_flash_free(struct spi_flash *flash)
+{
+ struct imx_spi_flash *imx_sf = NULL;
+
+ if (!flash)
+ return;
+
+ imx_sf = to_imx_spi_flash(flash);
+
+ if (flash->spi) {
+ spi_free_slave(flash->spi);
+ flash->spi = NULL;
+ }
+
+ free(imx_sf);
+}
+
COBJS-$(CONFIG_SMC91111) += smc91111.o
COBJS-$(CONFIG_SMC911X) += smc911x.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
+COBJS-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
COBJS-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
COBJS-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
COBJS-$(CONFIG_FMAN_ENET) += fsl_mdio.o
#include <malloc.h>
#include <net.h>
#include <netdev.h>
-#include <cpsw.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <phy.h>
+#include <asm/arch/cpu.h>
#define BITMASK(bits) (BIT(bits) - 1)
#define PHY_REG_MASK 0x1f
#define USERACCESS_GO BIT(31)
#define USERACCESS_WRITE BIT(30)
#define USERACCESS_ACK BIT(29)
-#define USERACCESS_READ (0)
-#define USERACCESS_DATA (0xffff)
+#define USERACCESS_READ 0
+#define USERACCESS_DATA 0xffff
} user[0];
};
u32 hw_buffer;
u32 hw_len;
u32 hw_mode;
- /* software fields */
- u32 sw_buffer;
- u32 sw_len;
+} __attribute__((aligned(CONFIG_SYS_CACHELINE_SIZE)));
+
+struct cpsw_desc {
+ void *sw_buffer;
+ struct cpsw_desc *next;
+ struct cpdma_desc *dma_desc;
};
struct cpdma_chan {
- struct cpdma_desc *head, *tail;
+ struct cpsw_desc *head, *tail;
void *hdp, *cp, *rxfree;
};
-#define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)
-#define desc_read(desc, fld) __raw_readl(&(desc)->fld)
-#define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld))
+#define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->dma_desc->fld)
+#define desc_read(desc, fld) __raw_readl(&(desc)->dma_desc->fld)
+#define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->dma_desc->fld))
#define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
#define chan_read(chan, fld) __raw_readl((chan)->fld)
#define for_each_slave(slave, priv) \
for (slave = (priv)->slaves; slave != (priv)->slaves + \
- (priv)->data.slaves; slave++)
+ (priv)->data->slaves; slave++)
struct cpsw_priv {
struct eth_device *dev;
- struct cpsw_platform_data data;
+ struct cpsw_platform_data *data;
int host_port;
struct cpsw_regs *regs;
struct cpsw_host_regs *host_port_regs;
void *ale_regs;
- struct cpdma_desc *descs;
- struct cpdma_desc *desc_free;
+ struct cpsw_desc descs[NUM_DESCS];
+ struct cpsw_desc *desc_free;
struct cpdma_chan rx_chan, tx_chan;
struct cpsw_slave *slaves;
u32 ale_entry[ALE_ENTRY_WORDS];
int type, idx;
- for (idx = 0; idx < priv->data.ale_entries; idx++) {
+ for (idx = 0; idx < priv->data->ale_entries; idx++) {
u8 entry_addr[6];
cpsw_ale_read(priv, idx, ale_entry);
u32 ale_entry[ALE_ENTRY_WORDS];
int type, idx;
- for (idx = 0; idx < priv->data.ale_entries; idx++) {
+ for (idx = 0; idx < priv->data->ale_entries; idx++) {
cpsw_ale_read(priv, idx, ale_entry);
type = cpsw_ale_get_entry_type(ale_entry);
if (type == ALE_TYPE_FREE)
u32 ale_entry[ALE_ENTRY_WORDS];
int type, idx;
- for (idx = 0; idx < priv->data.ale_entries; idx++) {
+ for (idx = 0; idx < priv->data->ale_entries; idx++) {
cpsw_ale_read(priv, idx, ale_entry);
type = cpsw_ale_get_entry_type(ale_entry);
if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
/* wait until hardware is ready for another user access */
static inline u32 wait_for_user_access(void)
{
- u32 reg = 0;
int timeout = MDIO_TIMEOUT;
+ u32 reg;
- while (timeout-- &&
- ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO))
- udelay(10);
-
- if (timeout == -1) {
- printf("wait_for_user_access Timeout\n");
- return -ETIMEDOUT;
+ while ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO) {
+ udelay(1);
+ if (--timeout <= 0) {
+ printf("TIMEOUT waiting for USERACCESS_GO\n");
+ return -1;
+ }
}
+
return reg;
}
{
int timeout = MDIO_TIMEOUT;
- while (timeout-- &&
- ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0))
- udelay(10);
-
- if (timeout == -1)
- printf("wait_for_idle Timeout\n");
+ while ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0) {
+ if (--timeout <= 0) {
+ printf("TIMEOUT waiting for state machine idle\n");
+ break;
+ }
+ udelay(1);
+ }
}
static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
/* Set a self-clearing bit in a register, and wait for it to clear */
static inline void setbit_and_wait_for_clear32(void *addr)
{
+ int loops = 0;
+
__raw_writel(CLEAR_BIT, addr);
while (__raw_readl(addr) & CLEAR_BIT)
- ;
+ loops++;
+ debug("%s: reset finished after %u loops\n", __func__, loops);
}
#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
__raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
}
+#define NUM_TRIES 50
+#if 1
+static void cpsw_slave_update_link(struct cpsw_slave *slave,
+ struct cpsw_priv *priv, int *link)
+{
+ struct phy_device *phy = priv->phydev;
+ u32 mac_control = 0;
+ int retries = NUM_TRIES;
+
+ do {
+ phy_startup(phy);
+ *link = phy->link;
+
+ if (*link) { /* link up */
+ mac_control = priv->data->mac_control;
+ if (phy->speed == 1000)
+ mac_control |= GIGABITEN;
+ if (phy->duplex == DUPLEX_FULL)
+ mac_control |= FULLDUPLEXEN;
+ if (phy->speed == 100)
+ mac_control |= MIIEN;
+ } else {
+ udelay(10000);
+ }
+ } while (!*link && retries-- > 0);
+ debug("%s: mac_control: %08x -> %08x after %u loops\n", __func__,
+ slave->mac_control, mac_control, NUM_TRIES - retries);
+
+ if (mac_control == slave->mac_control)
+ return;
+
+ if (mac_control) {
+ printf("link up on port %d, speed %d, %s duplex\n",
+ slave->slave_num, phy->speed,
+ (phy->duplex == DUPLEX_FULL) ? "full" : "half");
+ } else {
+ printf("link down on port %d\n", slave->slave_num);
+ }
+
+ __raw_writel(mac_control, &slave->sliver->mac_control);
+ slave->mac_control = mac_control;
+}
+#else
static void cpsw_slave_update_link(struct cpsw_slave *slave,
struct cpsw_priv *priv, int *link)
{
if (phy->speed == 100)
mac_control |= MIIEN;
}
+ debug("%s: mac_control: %08x -> %08x after %u loops\n", __func__,
+ slave->mac_control, mac_control, NUM_TRIES - retries);
if (mac_control == slave->mac_control)
return;
__raw_writel(mac_control, &slave->sliver->mac_control);
slave->mac_control = mac_control;
}
+#endif
static int cpsw_update_link(struct cpsw_priv *priv)
{
return link;
}
-static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
+static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
{
if (priv->host_port == 0)
return slave_num + 1;
{
u32 slave_port;
+ debug("%s\n", __func__);
setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
/* setup priority mapping */
cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port);
}
-static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
+static void cpdma_desc_get(struct cpsw_desc *desc)
+{
+ invalidate_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
+}
+
+static void cpdma_desc_put(struct cpsw_desc *desc)
+{
+ flush_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
+}
+
+static struct cpsw_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
{
- struct cpdma_desc *desc = priv->desc_free;
+ struct cpsw_desc *desc = priv->desc_free;
- if (desc)
- priv->desc_free = desc_read_ptr(desc, hw_next);
+ if (desc) {
+ cpdma_desc_get(desc);
+ priv->desc_free = desc->next;
+ }
return desc;
}
-static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
+static void cpdma_desc_free(struct cpsw_priv *priv, struct cpsw_desc *desc)
{
if (desc) {
- desc_write(desc, hw_next, priv->desc_free);
+ desc_write(desc, hw_next, priv->desc_free->dma_desc);
+ cpdma_desc_put(desc);
+ desc->next = priv->desc_free;
priv->desc_free = desc;
}
}
static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
void *buffer, int len)
{
- struct cpdma_desc *desc, *prev;
+ struct cpsw_desc *desc, *prev;
u32 mode;
+ if (!buffer) {
+ printf("ERROR: %s() NULL buffer\n", __func__);
+ return -EINVAL;
+ }
+
+ flush_dcache_range((u32)buffer, (u32)buffer + len);
+
desc = cpdma_desc_alloc(priv);
if (!desc)
return -ENOMEM;
+ debug("%s@%d: %cX desc %p DMA %p\n", __func__, __LINE__,
+ chan == &priv->rx_chan ? 'R' : 'T', desc, desc->dma_desc);
if (len < PKT_MIN)
len = PKT_MIN;
mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
+ desc->next = NULL;
desc_write(desc, hw_next, 0);
desc_write(desc, hw_buffer, buffer);
desc_write(desc, hw_len, len);
desc_write(desc, hw_mode, mode | len);
- desc_write(desc, sw_buffer, buffer);
- desc_write(desc, sw_len, len);
+ desc->sw_buffer = buffer;
+
+ cpdma_desc_put(desc);
if (!chan->head) {
/* simple case - first packet enqueued */
chan->head = desc;
chan->tail = desc;
- chan_write(chan, hdp, desc);
+ chan_write(chan, hdp, desc->dma_desc);
goto done;
}
/* not the first packet - enqueue at the tail */
prev = chan->tail;
- desc_write(prev, hw_next, desc);
+
+ prev->next = desc;
+ cpdma_desc_get(prev);
+ desc_write(prev, hw_next, desc->dma_desc);
+ cpdma_desc_put(prev);
+
chan->tail = desc;
/* next check if EOQ has been triggered already */
if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
- chan_write(chan, hdp, desc);
+ chan_write(chan, hdp, desc->dma_desc);
done:
if (chan->rxfree)
chan_write(chan, rxfree, 1);
+ debug("%s@%d\n", __func__, __LINE__);
return 0;
}
static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
void **buffer, int *len)
{
- struct cpdma_desc *desc = chan->head;
+ struct cpsw_desc *desc = chan->head;
u32 status;
if (!desc)
return -ENOENT;
+ cpdma_desc_get(desc);
+
status = desc_read(desc, hw_mode);
+ if (status & CPDMA_DESC_OWNER)
+ return -EBUSY;
if (len)
*len = status & 0x7ff;
if (buffer)
- *buffer = desc_read_ptr(desc, sw_buffer);
-
- if (status & CPDMA_DESC_OWNER) {
- if (chan_read(chan, hdp) == 0) {
- if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
- chan_write(chan, hdp, desc);
- }
+ *buffer = desc->sw_buffer;
+ debug("%s@%d: buffer=%p\n", __func__, __LINE__, desc->sw_buffer);
- return -EBUSY;
- }
-
- chan->head = desc_read_ptr(desc, hw_next);
- chan_write(chan, cp, desc);
+ chan->head = desc->next;
+ chan_write(chan, cp, desc->dma_desc);
cpdma_desc_free(priv, desc);
return 0;
struct cpsw_slave *slave;
int i, ret;
+ debug("%s\n", __func__);
/* soft reset the controller and initialize priv */
setbit_and_wait_for_clear32(&priv->regs->soft_reset);
/* init descriptor pool */
for (i = 0; i < NUM_DESCS; i++) {
+ struct cpsw_desc *next_desc = (i < (NUM_DESCS - 1)) ?
+ &priv->descs[i + 1] : NULL;
+
+ priv->descs[i].next = next_desc;
desc_write(&priv->descs[i], hw_next,
- (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
+ next_desc ? next_desc->dma_desc : 0);
+ cpdma_desc_put(&priv->descs[i]);
}
priv->desc_free = &priv->descs[0];
/* initialize channels */
- if (priv->data.version == CPSW_CTRL_VERSION_2) {
+ if (priv->data->version == CPSW_CTRL_VERSION_2) {
memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
- priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
- priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
- priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
+ priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
+ priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
+ priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
- priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
- priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
+ priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
+ priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
} else {
memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
- priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
- priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
- priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
+ priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
+ priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
+ priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
- priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
- priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
+ priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
+ priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
}
/* clear dma state */
setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
- if (priv->data.version == CPSW_CTRL_VERSION_2) {
- for (i = 0; i < priv->data.channels; i++) {
- __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
- * i);
- __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
- * i);
- __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
- * i);
- __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
- * i);
- __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
- * i);
+ if (priv->data->version == CPSW_CTRL_VERSION_2) {
+ for (i = 0; i < priv->data->channels; i++) {
+ __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 * i);
}
} else {
- for (i = 0; i < priv->data.channels; i++) {
- __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
- * i);
- __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
- * i);
- __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
- * i);
- __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
- * i);
- __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
- * i);
+ for (i = 0; i < priv->data->channels; i++) {
+ __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 * i);
}
}
}
}
- return 0;
+ return ret;
}
static void cpsw_halt(struct eth_device *dev)
/* clear dma state */
setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
- priv->data.control(0);
+ debug("%s\n", __func__);
+ priv->data->control(0);
}
static int cpsw_send(struct eth_device *dev, void *packet, int length)
{
- struct cpsw_priv *priv = dev->priv;
+ struct cpsw_priv *priv = dev->priv;
void *buffer;
int len;
- int timeout = CPDMA_TIMEOUT;
- if (!cpsw_update_link(priv))
- return -EIO;
+ debug("%s@%d: sending packet %p..%p\n", __func__, __LINE__,
+ packet, packet + length - 1);
- flush_dcache_range((unsigned long)packet,
- (unsigned long)packet + length);
+ if (!priv->data->mac_control && !cpsw_update_link(priv)) {
+ printf("%s: Cannot send packet; link is down\n", __func__);
+ return -EIO;
+ }
/* first reap completed packets */
- while (timeout-- &&
- (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0))
- ;
-
- if (timeout == -1) {
- printf("cpdma_process timeout\n");
- return -ETIMEDOUT;
- }
+ while (cpdma_process(priv, &priv->tx_chan, &buffer, &len) == 0)
+ /* NOP */;
return cpdma_submit(priv, &priv->tx_chan, packet, length);
}
void *buffer;
int len;
- cpsw_update_link(priv);
-
- while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) {
- invalidate_dcache_range((unsigned long)buffer,
- (unsigned long)buffer + PKTSIZE_ALIGN);
- NetReceive(buffer, len);
- cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE);
+ while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) == 0) {
+ if (buffer) {
+ NetReceive(buffer, len);
+ cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE);
+ } else {
+ printf("NULL buffer returned from cpdma_process\n");
+ return -EIO;
+ }
}
return 0;
struct cpsw_priv *priv)
{
void *regs = priv->regs;
- struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
+ struct cpsw_slave_data *data = priv->data->slave_data + slave_num;
+
+ debug("%s@%d: slave[%d] %p\n", __func__, __LINE__,
+ slave_num, slave);
slave->slave_num = slave_num;
slave->data = data;
slave->regs = regs + data->slave_reg_ofs;
struct cpsw_slave *slave;
void *regs = (void *)data->cpsw_base;
struct eth_device *dev;
+ int i;
+ int idx = 0;
+
+ debug("%s@%d\n", __func__, __LINE__);
dev = calloc(sizeof(*dev), 1);
if (!dev)
return -ENOMEM;
}
- priv->data = *data;
+ priv->data = data;
priv->dev = dev;
- priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
+ priv->slaves = calloc(sizeof(struct cpsw_slave), data->slaves);
if (!priv->slaves) {
free(dev);
free(priv);
return -ENOMEM;
}
- priv->descs = (void *)CPDMA_RAM_ADDR;
+ for (i = 0; i < NUM_DESCS; i++) {
+ priv->descs[i].dma_desc = memalign(CONFIG_SYS_CACHELINE_SIZE,
+ sizeof(struct cpsw_desc) * NUM_DESCS);
+ if (!priv->descs[i].dma_desc) {
+ while (--i >= 0) {
+ free(priv->descs[i].dma_desc);
+ }
+ free(priv->slaves);
+ free(priv);
+ free(dev);
+ return -ENOMEM;
+ }
+ debug("DMA desc[%d] allocated @ %p desc_size %u\n",
+ i, priv->descs[i].dma_desc,
+ sizeof(*priv->descs[i].dma_desc));
+ }
+
priv->host_port = data->host_port_num;
priv->regs = regs;
priv->host_port_regs = regs + data->host_port_reg_ofs;
priv->dma_regs = regs + data->cpdma_reg_ofs;
priv->ale_regs = regs + data->ale_reg_ofs;
- int idx = 0;
-
for_each_slave(slave, priv) {
cpsw_slave_setup(slave, idx, priv);
idx = idx + 1;
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
-#include "fec_mxc.h"
+#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <linux/compiler.h>
+#include "fec_mxc.h"
+
DECLARE_GLOBAL_DATA_PTR;
/*
uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
};
+static int rx_idx;
+
#ifdef CONFIG_FEC_MXC_SWAP_PACKET
static void swap_packet(uint32_t *packet, int length)
{
{
uint32_t reg; /* convenient holder for the PHY register */
uint32_t phy; /* convenient holder for the PHY */
- uint32_t start;
+ ulong start;
int val;
/*
start = get_timer(0);
while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
+ if (readl(ð->ievent) & FEC_IEVENT_MII)
+ break;
printf("Read MDIO failed...\n");
return -1;
}
* it's now safe to read the PHY's register
*/
val = (unsigned short)readl(ð->mii_data);
- debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
+ debug("%s: phy: %02x reg:%02x val:%#06x\n", __func__, phyAddr,
regAddr, val);
return val;
}
{
uint32_t reg; /* convenient holder for the PHY register */
uint32_t phy; /* convenient holder for the PHY */
- uint32_t start;
+ ulong start;
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
start = get_timer(0);
while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
+ if (readl(ð->ievent) & FEC_IEVENT_MII)
+ break;
printf("Write MDIO failed...\n");
return -1;
}
* clear MII interrupt bit
*/
writel(FEC_IEVENT_MII, ð->ievent);
- debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
+ debug("%s: phy: %02x reg:%02x val:%#06x\n", __func__, phyAddr,
regAddr, data);
return 0;
}
#endif
-static int fec_rx_task_enable(struct fec_priv *fec)
+static inline void fec_rx_task_enable(struct fec_priv *fec)
{
- writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
- return 0;
+ writel(1 << 24, &fec->eth->r_des_active);
}
-static int fec_rx_task_disable(struct fec_priv *fec)
+static inline void fec_rx_task_disable(struct fec_priv *fec)
{
- return 0;
}
-static int fec_tx_task_enable(struct fec_priv *fec)
+static inline void fec_tx_task_enable(struct fec_priv *fec)
{
- writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
- return 0;
+ writel(1 << 24, &fec->eth->x_des_active);
}
-static int fec_tx_task_disable(struct fec_priv *fec)
+static inline void fec_tx_task_disable(struct fec_priv *fec)
{
- return 0;
}
/**
writew(0x0000, &fec->tbd_base[0].status);
writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
fec->tbd_index = 0;
- flush_dcache_range(addr, addr+size);
+ flush_dcache_range(addr, addr + size);
}
/**
struct fec_priv *fec = (struct fec_priv *)dev->priv;
struct phy_device *phydev;
- phydev = phy_connect(fec->bus, fec->phy_id, dev,
- PHY_INTERFACE_MODE_RGMII);
+ if (fec->phy_id < 0) {
+ int phy_id;
+
+ for (phy_id = 0; phy_id < 32; phy_id++) {
+ debug("%s: Probing PHY ID %02x\n", __func__, phy_id);
+ phydev = phy_connect(fec->bus, phy_id, dev,
+ PHY_INTERFACE_MODE_RGMII);
+
+ if (phydev)
+ break;
+ }
+ } else {
+ phydev = phy_connect(fec->bus, fec->phy_id, dev,
+ PHY_INTERFACE_MODE_RGMII);
+ }
if (phydev) {
fec->phydev = phydev;
phy_config(phydev);
*/
static int fec_open(struct eth_device *edev)
{
- struct fec_priv *fec = (struct fec_priv *)edev->priv;
+ struct fec_priv *fec = edev->priv;
int speed;
uint32_t addr, size;
int i;
#ifdef FEC_QUIRK_ENET_MAC
{
u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
- u32 rcr = (readl(&fec->eth->r_cntrl) &
- ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
- FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
+ u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
+
if (speed == _1000BASET)
ecr |= FEC_ECNTRL_SPEED;
else if (speed != _100BASET)
*/
fec_rx_task_enable(fec);
- udelay(100000);
+// udelay(100000);
return 0;
}
static int fec_init(struct eth_device *dev, bd_t* bd)
{
- struct fec_priv *fec = (struct fec_priv *)dev->priv;
- uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
+ struct fec_priv *fec = dev->priv;
+ uint32_t *mib_ptr = (uint32_t *)&fec->eth->rmon_t_drop;
uint32_t size;
int i, ret;
/* clear MIB RAM */
- for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
- writel(0, i);
+ for (i = 0; i <= 0xfc >> 2; i++)
+ writel(0, &mib_ptr[i]);
/* FIFO receive start register */
writel(0x520, &fec->eth->r_fstart);
static void fec_halt(struct eth_device *dev)
{
struct fec_priv *fec = (struct fec_priv *)dev->priv;
- int counter = 0xffff;
+ int counter = 1000;
/*
* issue graceful stop command to the FEC transmitter if necessary
* wait for graceful stop to register
*/
while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
- udelay(1);
+ udelay(100);
/*
* Disable SmartDMA tasks
uint32_t size, end;
uint32_t addr;
int timeout = FEC_XFER_TIMEOUT;
- int ret = 0;
/*
* This routine transmits one frame. This routine only accepts
* 6-byte Ethernet addresses.
*/
- struct fec_priv *fec = (struct fec_priv *)dev->priv;
+ struct fec_priv *fec = dev->priv;
/*
* Check for valid length of data.
* update BD's status now
* This block:
* - is always the last in a chain (means no chain)
- * - should transmitt the CRC
+ * - should transmit the CRC
* - might be the last BD in the list, so the address counter should
* wrap (-> keep the WRAP flag)
*/
* invalidate data cache to see what's really in RAM. Also, we need
* barrier here.
*/
- while (--timeout) {
- if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
- break;
- }
-
- if (!timeout)
- ret = -EINVAL;
-
invalidate_dcache_range(addr, addr + size);
- if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
- ret = -EINVAL;
+ while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
+ if (--timeout < 0)
+ return -ETIMEDOUT;
+ udelay(1);
+ invalidate_dcache_range(addr, addr + size);
+ }
- debug("fec_send: status 0x%x index %d ret %i\n",
+ debug("fec_send: status 0x%04x index %d\n",
readw(&fec->tbd_base[fec->tbd_index].status),
- fec->tbd_index, ret);
+ fec->tbd_index);
/* for next transmission use the other buffer */
if (fec->tbd_index)
fec->tbd_index = 0;
else
fec->tbd_index = 1;
- return ret;
+ return 0;
}
/**
uint16_t bd_status;
uint32_t addr, size, end;
int i;
- uchar buff[FEC_MAX_PKT_SIZE] __aligned(ARCH_DMA_MINALIGN);
/*
* Check if any critical events have happened
*/
ievent = readl(&fec->eth->ievent);
- writel(ievent, &fec->eth->ievent);
- debug("fec_recv: ievent 0x%lx\n", ievent);
+ if (ievent)
+ writel(ievent, &fec->eth->ievent);
+
+ if (ievent)
+ debug("fec_recv: ievent 0x%lx\n", ievent);
if (ievent & FEC_IEVENT_BABR) {
fec_halt(dev);
fec_init(dev, fec->bd);
invalidate_dcache_range(addr, addr + size);
bd_status = readw(&rbd->status);
- debug("fec_recv: status 0x%x\n", bd_status);
-
if (!(bd_status & FEC_RBD_EMPTY)) {
+ debug("fec_recv: status 0x%04x len %u\n", bd_status,
+ readw(&rbd->data_length) - 4);
if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
((readw(&rbd->data_length) - 4) > 14)) {
/*
*/
frame = (struct nbuf *)readl(&rbd->data_pointer);
frame_length = readw(&rbd->data_length) - 4;
+
/*
* Invalidate data cache over the buffer
*/
#ifdef CONFIG_FEC_MXC_SWAP_PACKET
swap_packet((uint32_t *)frame->data, frame_length);
#endif
- memcpy(buff, frame->data, frame_length);
- NetReceive(buff, frame_length);
+ memcpy((void *)NetRxPackets[rx_idx], frame->data, frame_length);
+ NetReceive(NetRxPackets[rx_idx], frame_length);
+ rx_idx = (rx_idx + 1) % PKTBUFSRX;
len = frame_length;
} else {
if (bd_status & FEC_RBD_ERR)
fec_rx_task_enable(fec);
fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
+ debug("fec_recv: stop\n");
}
- debug("fec_recv: stop\n");
return len;
}
int ret = 0;
/* create and fill edev struct */
- edev = (struct eth_device *)malloc(sizeof(struct eth_device));
+ edev = calloc(sizeof(struct eth_device), 1);
if (!edev) {
puts("fec_mxc: not enough malloc memory for eth_device\n");
ret = -ENOMEM;
goto err1;
}
- fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
+ fec = calloc(sizeof(struct fec_priv), 1);
if (!fec) {
puts("fec_mxc: not enough malloc memory for fec_priv\n");
ret = -ENOMEM;
goto err2;
}
- memset(edev, 0, sizeof(*edev));
- memset(fec, 0, sizeof(*fec));
-
edev->priv = fec;
edev->init = fec_init;
edev->send = fec_send;
eth_register(edev);
if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
- debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
+ if (dev_id < 0)
+ debug("got MAC address from fuse: %pM\n", ethaddr);
+ else
+ debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
memcpy(edev->enetaddr, ethaddr, 6);
}
/* Configure phy */
{
int lout = 1;
- debug("eth_init: fec_probe(bd)\n");
+ debug("eth_init: fec_probe(PHY %02x FEC: %08x)\n",
+ CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
return lout;
#ifndef __FEC_MXC_H
#define __FEC_MXC_H
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
-
/**
* Layout description of the FEC
*/
/* If the phy_id is mostly Fs, there is no device there */
if ((phy_id & 0x1fffffff) != 0x1fffffff)
- break;
+ return phy_device_create(bus, addr, phy_id, interface);
}
-
- return phy_device_create(bus, addr, phy_id, interface);
+ return NULL;
}
int phy_reset(struct phy_device *phydev)
#define DRIVERNAME "smc911x"
#if defined (CONFIG_SMC911X_32_BIT) && \
- defined (CONFIG_SMC911X_16_BIT)
+ defined (CONFIG_SMC911X_16_BIT) && \
+ defined(CONFIG_SMC911X_CPLD)
#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
CONFIG_SMC911X_16_BIT shall be set"
#endif
*(volatile u16 *)(dev->iobase + offset) = (u16)val;
*(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
}
+#elif defined(CONFIG_SMC911X_CPLD)
+#include <asm/arch/imx_spi_cpld.h>
+static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
+{
+ return cpld_reg_xfer(offset, 0x0, 1) | \
+ (cpld_reg_xfer(offset + 0x2, 0x0, 1) << 16);
+}
+static void smc911x_reg_write(struct eth_device *dev,
+ u32 offset, u32 val)
+{
+ cpld_reg_xfer(offset, val, 0);
+ cpld_reg_xfer(offset + 0x2, (val >> 16), 0);
+}
#else
#error "SMC911X: undefined bus width"
#endif /* CONFIG_SMC911X_16_BIT */
--- /dev/null
+/*
+ * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+
+#ifdef CONFIG_STMP3XXX_DBGUART
+
+#include "stmp3xxx_dbguart.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Set baud rate. The settings are always 8n1:
+ * 8 data bits, no parity, 1 stop bit
+ */
+void serial_setbrg(void)
+{
+ u32 cr, lcr_h;
+ u32 quot;
+
+ /* Disable everything */
+ cr = REG_RD(DBGUART_BASE + UARTDBGCR);
+ REG_WR(DBGUART_BASE + UARTDBGCR, 0);
+
+ /* Calculate and set baudrate */
+ quot = (CONFIG_DBGUART_CLK * 4) / gd->baudrate;
+ REG_WR(DBGUART_BASE + UARTDBGFBRD, quot & 0x3f);
+ REG_WR(DBGUART_BASE + UARTDBGIBRD, quot >> 6);
+
+ /* Set 8n1 mode, enable FIFOs */
+ lcr_h = WLEN8 | FEN;
+ REG_WR(DBGUART_BASE + UARTDBGLCR_H, lcr_h);
+
+ /* Enable Debug UART */
+ REG_WR(DBGUART_BASE + UARTDBGCR, cr);
+}
+
+int serial_init(void)
+{
+ u32 cr;
+
+ /* Disable UART */
+ REG_WR(DBGUART_BASE + UARTDBGCR, 0);
+
+ /* Mask interrupts */
+ REG_WR(DBGUART_BASE + UARTDBGIMSC, 0);
+
+ /* Set default baudrate */
+ serial_setbrg();
+
+ /* Enable UART */
+ cr = TXE | RXE | UARTEN;
+ REG_WR(DBGUART_BASE + UARTDBGCR, cr);
+
+ return 0;
+}
+
+/* Send a character */
+void serial_putc(const char c)
+{
+ /* Wait for room in TX FIFO */
+ while (REG_RD(DBGUART_BASE + UARTDBGFR) & TXFF)
+ ;
+
+ /* Write the data byte */
+ REG_WR(DBGUART_BASE + UARTDBGDR, c);
+
+ if (c == '\n')
+ serial_putc('\r');
+}
+
+void serial_puts(const char *s)
+{
+ while (*s) {
+ serial_putc(*s++);
+ }
+}
+
+/* Test whether a character is in TX buffer */
+int serial_tstc(void)
+{
+ /* Check if RX FIFO is not empty */
+ return !(REG_RD(DBGUART_BASE + UARTDBGFR) & RXFE);
+}
+
+/* Receive character */
+int serial_getc(void)
+{
+ /* Wait while TX FIFO is empty */
+ while (REG_RD(DBGUART_BASE + UARTDBGFR) & RXFE)
+ ;
+
+ /* Read data byte */
+ return REG_RD(DBGUART_BASE + UARTDBGDR) & 0xff;
+}
+
+#endif /* CONFIG_STMP378X_DBGUART */
--- /dev/null
+/*
+ * Debug UART register definitions
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ */
+
+#ifndef STMP3XXX_DBGUART_H
+#define STMP3XXX_DBGUART_H
+
+#include <asm/arch/dbguart.h>
+
+#define UARTDBGDR 0x00
+#define UARTDBGRSR_ECR 0x04
+#define UARTDBGFR 0x18
+#define UARTDBGILPR 0x20
+#define UARTDBGIBRD 0x24
+#define UARTDBGFBRD 0x28
+#define UARTDBGLCR_H 0x2c
+#define UARTDBGCR 0x30
+#define UARTDBGIFLS 0x34
+#define UARTDBGIMSC 0x38
+#define UARTDBGRIS 0x3c
+#define UARTDBGMIS 0x40
+#define UARTDBGICR 0x44
+#define UARTDBGDMACR 0x48
+
+/* UARTDBGFR - Flag Register bits */
+#define CTS 0x0001
+#define DSR 0x0002
+#define DCD 0x0004
+#define BUSY 0x0008
+#define RXFE 0x0010
+#define TXFF 0x0020
+#define RXFF 0x0040
+#define TXFE 0x0080
+#define RI 0x0100
+
+/* UARTDBGLCR_H - Line Control Register bits */
+#define BRK 0x0001
+#define PEN 0x0002
+#define EPS 0x0004
+#define STP2 0x0008
+#define FEN 0x0010
+#define WLEN5 0x0000
+#define WLEN6 0x0020
+#define WLEN7 0x0040
+#define WLEN8 0x0060
+#define SPS 0x0080
+
+/* UARTDBGCR - Control Register bits */
+#define UARTEN 0x0001
+#define LBE 0x0080
+#define TXE 0x0100
+#define RXE 0x0200
+#define DTR 0x0400
+#define RTS 0x0800
+#define OUT1 0x1000
+#define OUT2 0x2000
+#define RTSEN 0x4000
+#define CTSEN 0x8000
+
+#endif /* STMP3XXX_DBGUART_H */
--- /dev/null
+/*
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <spi.h>
+#include <asm/errno.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <malloc.h>
+
+#include <imx_spi.h>
+
+extern s32 spi_get_cfg(struct imx_spi_dev_t *dev);
+
+static inline struct imx_spi_dev_t *to_imx_spi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct imx_spi_dev_t, slave);
+}
+
+static s32 spi_reset(struct spi_slave *slave)
+{
+ u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
+ s32 div = 0, i, reg_ctrl;
+ struct imx_spi_dev_t *dev = to_imx_spi_slave(slave);
+ struct spi_reg_t *reg = &(dev->reg);
+ int lim = 0;
+ unsigned int baud_rate_div[] = { 4, 8, 16, 32, 64, 128, 256, 512 };
+
+ if (dev->freq == 0) {
+ printf("Error: desired clock is 0\n");
+ return 1;
+ }
+
+ reg_ctrl = readl(dev->base + SPI_CON_REG);
+ /* Reset spi */
+ writel(0, dev->base + SPI_CON_REG);
+ writel((reg_ctrl | SPI_CTRL_EN), dev->base + SPI_CON_REG);
+
+ lim = sizeof(baud_rate_div) / sizeof(unsigned int);
+ if (clk_src > dev->freq) {
+ div = clk_src / dev->freq;
+
+ for (i = 0; i < lim; i++) {
+ if (div <= baud_rate_div[i])
+ break;
+ }
+ }
+ debug("div = %d\n", baud_rate_div[i]);
+
+ reg_ctrl =
+ (reg_ctrl & ~SPI_CTRL_SS_MASK) | (dev->ss << SPI_CTRL_SS_OFF);
+ reg_ctrl = (reg_ctrl & ~SPI_CTRL_DATA_MASK) | (i << SPI_CTRL_DATA_OFF);
+ reg_ctrl |= SPI_CTRL_MODE; /* always set to master mode !!!! */
+ reg_ctrl &= ~SPI_CTRL_EN; /* disable spi */
+
+ /* configuration register setup */
+ reg_ctrl =
+ (reg_ctrl & ~SPI_CTRL_SSPOL) | (dev->ss_pol << SPI_CTRL_SSPOL_OFF);
+ reg_ctrl =
+ (reg_ctrl & ~SPI_CTRL_SSCTL) | (dev->ssctl << SPI_CTRL_SSCTL_OFF);
+ reg_ctrl =
+ (reg_ctrl & ~SPI_CTRL_SCLK_POL) | (dev->
+ sclkpol <<
+ SPI_CTRL_SCLK_POL_OFF);
+ reg_ctrl =
+ (reg_ctrl & ~SPI_CTRL_SCLK_PHA) | (dev->
+ sclkpha <<
+ SPI_CTRL_SCLK_PHA_OFF);
+
+ debug("reg_ctrl = 0x%x\n", reg_ctrl);
+ writel(reg_ctrl, dev->base + SPI_CON_REG);
+ /* save control register */
+ reg->ctrl_reg = reg_ctrl;
+
+ /* clear interrupt reg */
+ writel(0, dev->base + SPI_INT_REG);
+ writel(SPI_INT_STAT_TC, dev->base + SPI_STAT_REG);
+
+ return 0;
+}
+
+void spi_init(void)
+{
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct imx_spi_dev_t *imx_spi_slave = NULL;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ imx_spi_slave =
+ (struct imx_spi_dev_t *)malloc(sizeof(struct imx_spi_dev_t));
+ if (!imx_spi_slave)
+ return NULL;
+
+ imx_spi_slave->slave.bus = bus;
+ imx_spi_slave->slave.cs = cs;
+
+ spi_get_cfg(imx_spi_slave);
+
+ spi_io_init(imx_spi_slave);
+
+ spi_reset(&(imx_spi_slave->slave));
+
+ return &(imx_spi_slave->slave);
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct imx_spi_dev_t *imx_spi_slave;
+
+ if (slave) {
+ imx_spi_slave = to_imx_spi_slave(slave);
+ free(imx_spi_slave);
+ }
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+
+}
+
+/*
+ * SPI transfer:
+ *
+ * See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf
+ * for more informations.
+ */
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ s32 val = SPI_RETRY_TIMES;
+ u32 *p_buf;
+ u32 reg;
+ s32 len = 0, ret_val = 0;
+ s32 burst_bytes = bitlen >> 3;
+ struct imx_spi_dev_t *dev = to_imx_spi_slave(slave);
+ struct spi_reg_t *spi_reg = &(dev->reg);
+
+ if (!slave)
+ return -1;
+
+ if ((bitlen % 8) != 0)
+ burst_bytes++;
+
+ if (burst_bytes > (dev->fifo_sz)) {
+ printf("Error: maximum burst size is 0x%x bytes, asking 0x%x\n",
+ dev->fifo_sz, burst_bytes);
+ return -1;
+ }
+
+ if (flags & SPI_XFER_BEGIN) {
+ spi_cs_activate(slave);
+
+ if (spi_reg->ctrl_reg == 0) {
+ printf
+ ("Error: spi(base=0x%x) has not been initialized\n",
+ dev->base);
+ return -1;
+ }
+
+ spi_reg->ctrl_reg = (spi_reg->ctrl_reg & ~SPI_CTRL_BURST_MASK) |
+ ((bitlen - 1) << SPI_CTRL_BURST_OFF);
+ writel(spi_reg->ctrl_reg | SPI_CTRL_EN,
+ dev->base + SPI_CON_REG);
+ debug("ctrl_reg=0x%x\n", readl(dev->base + SPI_CON_REG));
+
+ /* move data to the tx fifo */
+ if (dout) {
+ for (p_buf = (u32 *) dout, len = burst_bytes; len > 0;
+ p_buf++, len -= 4)
+ writel(*p_buf, dev->base + SPI_TX_DATA);
+ }
+
+ reg = readl(dev->base + SPI_CON_REG);
+ reg |= SPI_CTRL_REG_XCH_BIT; /* set xch bit */
+ debug("control reg = 0x%08x\n", reg);
+ writel(reg, dev->base + SPI_CON_REG);
+
+ /* poll on the TC bit (transfer complete) */
+ while ((val-- > 0) &&
+ (((reg =
+ readl(dev->base + SPI_STAT_REG)) & SPI_INT_STAT_TC) ==
+ 0));
+
+ /* clear the TC bit */
+ writel(reg | SPI_INT_STAT_TC, dev->base + SPI_STAT_REG);
+ if (val <= 0) {
+ printf
+ ("Error: re-tried %d times without response. Give up\n",
+ SPI_RETRY_TIMES);
+ ret_val = -1;
+ goto error;
+ }
+ }
+
+ /* move data in the rx buf */
+ if (flags & SPI_XFER_END) {
+ if (din) {
+ for (p_buf = (u32 *) din, len = burst_bytes; len > 0;
+ p_buf++, len -= 4)
+ *p_buf = readl(dev->base + SPI_RX_DATA);
+ }
+ }
+error:
+ spi_cs_deactivate(slave);
+ return ret_val;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct imx_spi_dev_t *dev = to_imx_spi_slave(slave);
+
+ spi_io_init(dev);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct imx_spi_dev_t *dev = to_imx_spi_slave(slave);
+
+ writel(0, dev->base + SPI_CON_REG);
+}
--- /dev/null
+/*
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <spi.h>
+#include <asm/errno.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <malloc.h>
+
+#include <imx_spi.h>
+
+#ifdef DEBUG
+
+/* -----------------------------------------------
+ * Helper functions to peek into tx and rx buffers
+ * ----------------------------------------------- */
+static const char * const hex_digit = "0123456789ABCDEF";
+
+static char quickhex(int i)
+{
+ return hex_digit[i];
+}
+
+static void memdump(const void *pv, int num)
+{
+
+}
+
+#else /* !DEBUG */
+
+#define memdump(p, n)
+
+#endif /* DEBUG */
+
+extern s32 spi_get_cfg(struct imx_spi_dev_t *dev);
+
+static inline struct imx_spi_dev_t *to_imx_spi_slave(struct spi_slave *slave)
+{
+ return container_of(slave, struct imx_spi_dev_t, slave);
+}
+
+static s32 spi_reset(struct spi_slave *slave)
+{
+ u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
+ s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
+ struct imx_spi_dev_t *dev = to_imx_spi_slave(slave);
+ struct spi_reg_t *reg = &(dev->reg);
+
+ if (dev->freq == 0) {
+ printf("Error: desired clock is 0\n");
+ return 1;
+ }
+
+ reg_ctrl = readl(dev->base + SPI_CON_REG);
+ /* Reset spi */
+ writel(0, dev->base + SPI_CON_REG);
+ writel((reg_ctrl | 0x1), dev->base + SPI_CON_REG);
+
+ /* Control register setup */
+ if (clk_src > dev->freq) {
+ pre_div = clk_src / dev->freq;
+ if (pre_div > 16) {
+ post_div = pre_div / 16;
+ pre_div = 15;
+ }
+ if (post_div != 0) {
+ for (i = 0; i < 16; i++) {
+ if ((1 << i) >= post_div)
+ break;
+ }
+ if (i == 16) {
+ printf("Error: no divider can meet the freq: %d\n",
+ dev->freq);
+ return -1;
+ }
+ post_div = i;
+ }
+ }
+
+ debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
+ reg_ctrl = (reg_ctrl & ~(3 << 18)) | dev->ss << 18;
+ reg_ctrl = (reg_ctrl & ~(0xF << 12)) | pre_div << 12;
+ reg_ctrl = (reg_ctrl & ~(0xF << 8)) | post_div << 8;
+ reg_ctrl |= 1 << (dev->ss + 4); /* always set to master mode !!!! */
+ reg_ctrl &= ~0x1; /* disable spi */
+
+ reg_config = readl(dev->base + SPI_CFG_REG);
+ /* configuration register setup */
+ reg_config = (reg_config & ~(1 << ((dev->ss + 12)))) |
+ (dev->ss_pol << (dev->ss + 12));
+ reg_config = (reg_config & ~(1 << ((dev->ss + 20)))) |
+ (dev->in_sctl << (dev->ss + 20));
+ reg_config = (reg_config & ~(1 << ((dev->ss + 16)))) |
+ (dev->in_dctl << (dev->ss + 16));
+ reg_config = (reg_config & ~(1 << ((dev->ss + 8)))) |
+ (dev->ssctl << (dev->ss + 8));
+ reg_config = (reg_config & ~(1 << ((dev->ss + 4)))) |
+ (dev->sclkpol << (dev->ss + 4));
+ reg_config = (reg_config & ~(1 << ((dev->ss + 0)))) |
+ (dev->sclkpha << (dev->ss + 0));
+
+ debug("reg_ctrl = 0x%x\n", reg_ctrl);
+ writel(reg_ctrl, dev->base + SPI_CON_REG);
+ debug("reg_config = 0x%x\n", reg_config);
+ writel(reg_config, dev->base + SPI_CFG_REG);
+
+ /* save config register and control register */
+ reg->cfg_reg = reg_config;
+ reg->ctrl_reg = reg_ctrl;
+
+ /* clear interrupt reg */
+ writel(0, dev->base + SPI_INT_REG);
+ writel(3 << 6, dev->base + SPI_STAT_REG);
+
+ return 0;
+}
+
+void spi_init(void)
+{
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct imx_spi_dev_t *imx_spi_slave = NULL;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ imx_spi_slave = (struct imx_spi_dev_t *)malloc(sizeof(struct imx_spi_dev_t));
+ if (!imx_spi_slave)
+ return NULL;
+
+ imx_spi_slave->slave.bus = bus;
+ imx_spi_slave->slave.cs = cs;
+
+ spi_get_cfg(imx_spi_slave);
+
+ spi_io_init(imx_spi_slave);
+
+ spi_reset(&(imx_spi_slave->slave));
+
+ return &(imx_spi_slave->slave);
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct imx_spi_dev_t *imx_spi_slave;
+
+ if (slave) {
+ imx_spi_slave = to_imx_spi_slave(slave);
+ free(imx_spi_slave);
+ }
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+
+}
+
+/*
+ * SPI transfer:
+ *
+ * See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf
+ * for more informations.
+ */
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ s32 val = SPI_RETRY_TIMES;
+ u32 *p_buf;
+ u32 reg;
+ s32 len = 0,
+ ret_val = 0;
+ s32 burst_bytes = bitlen >> 3;
+ s32 tmp = 0;
+ struct imx_spi_dev_t *dev = to_imx_spi_slave(slave);
+ struct spi_reg_t *spi_reg = &(dev->reg);
+
+ if (!slave)
+ return -1;
+
+ if (burst_bytes > (MAX_SPI_BYTES)) {
+ printf("Error: maximum burst size is 0x%x bytes, asking 0x%x\n",
+ MAX_SPI_BYTES, burst_bytes);
+ return -1;
+ }
+
+ if (flags & SPI_XFER_BEGIN) {
+ spi_cs_activate(slave);
+
+ if (spi_reg->ctrl_reg == 0) {
+ printf("Error: spi(base=0x%x) has not been initialized yet\n",
+ dev->base);
+ return -1;
+ }
+ spi_reg->ctrl_reg = (spi_reg->ctrl_reg & ~0xFFF00000) | \
+ ((burst_bytes * 8 - 1) << 20);
+
+ writel(spi_reg->ctrl_reg | 0x1, dev->base + SPI_CON_REG);
+ writel(spi_reg->cfg_reg, dev->base + SPI_CFG_REG);
+ debug("ctrl_reg=0x%x, cfg_reg=0x%x\n",
+ readl(dev->base + SPI_CON_REG),
+ readl(dev->base + SPI_CFG_REG));
+
+ /* move data to the tx fifo */
+ if (dout) {
+ for (p_buf = (u32 *)dout, len = burst_bytes; len > 0;
+ p_buf++, len -= 4)
+ writel(*p_buf, dev->base + SPI_TX_DATA);
+ } else {
+ for (len = burst_bytes; len > 0; len -= 4)
+ writel(tmp, dev->base + SPI_TX_DATA);
+ }
+
+ reg = readl(dev->base + SPI_CON_REG);
+ reg |= (1 << 2); /* set xch bit */
+ debug("control reg = 0x%08x\n", reg);
+ writel(reg, dev->base + SPI_CON_REG);
+
+ /* poll on the TC bit (transfer complete) */
+ while ((val-- > 0) &&
+ (readl(dev->base + SPI_STAT_REG) & (1 << 7)) == 0) {
+ udelay(100);
+ }
+
+ /* clear the TC bit */
+ writel(3 << 6, dev->base + SPI_STAT_REG);
+ if (val <= 0) {
+ printf("Error: re-tried %d times without response. Give up\n",
+ SPI_RETRY_TIMES);
+ ret_val = -1;
+ goto error;
+ }
+ }
+
+ /* move data in the rx buf */
+ if (flags & SPI_XFER_END) {
+ if (din) {
+ for (p_buf = (u32 *)din, len = burst_bytes; len > 0;
+ ++p_buf, len -= 4)
+ *p_buf = readl(dev->base + SPI_RX_DATA);
+ } else {
+ for (len = burst_bytes; len > 0; len -= 4)
+ tmp = readl(dev->base + SPI_RX_DATA);
+ }
+
+ spi_cs_deactivate(slave);
+ }
+
+ return ret_val;
+
+error:
+ spi_cs_deactivate(slave);
+ return ret_val;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct imx_spi_dev_t *dev = to_imx_spi_slave(slave);
+
+ spi_io_init(dev);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct imx_spi_dev_t *dev = to_imx_spi_slave(slave);
+
+ writel(0, dev->base + SPI_CON_REG);
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <spi.h>
+#include <asm/errno.h>
+#include <linux/types.h>
+
+#include <imx_spi.h>
+#include <asm/arch/imx_spi_cpld.h>
+
+static struct spi_slave *cpld_slave;
+
+void cpld_reg_write(u32 offset, u32 val)
+{
+ cpld_reg_xfer(offset, val, 0);
+ cpld_reg_xfer(offset + 0x2, (val >> 16), 0);
+}
+
+u32 cpld_reg_read(u32 offset)
+{
+ return cpld_reg_xfer(offset, 0x0, 1) | \
+ (cpld_reg_xfer(offset + 0x2, 0x0, 1) << 16);
+}
+
+/*!
+ * To read/write to a CPLD register.
+ *
+ * @param reg register number inside the CPLD
+ * @param val data to be written to the register; don't care for read
+ * @param read 0 for write; 1 for read
+ *
+ * @return the actual data in the CPLD register
+ */
+unsigned int cpld_reg_xfer(unsigned int reg, unsigned int val,
+ unsigned int read)
+{
+ unsigned int local_val1, local_val2;
+ unsigned int g_tx_buf[2], g_rx_buf[2];
+
+ reg >>= 1;
+
+ local_val1 = (read << 13) | ((reg & 0x0001FFFF) >> 5) | 0x00001000;
+ if (read)
+ local_val2 = (((reg & 0x0000001F) << 27) | 0x0200001f);
+ else
+ local_val2 =
+ (((reg & 0x0000001F) << 27) | ((val & 0x0000FFFF) << 6) |
+ 0x03C00027);
+
+ *g_tx_buf = local_val1;
+ *(g_tx_buf + 1) = local_val2;
+
+ if (read) {
+ if (spi_xfer(cpld_slave, 46, (u8 *) g_tx_buf, (u8 *) g_rx_buf,
+ SPI_XFER_BEGIN | SPI_XFER_END)) {
+ return -1;
+ }
+ } else {
+ if (spi_xfer(cpld_slave, 46, (u8 *) g_tx_buf, (u8 *) g_rx_buf,
+ SPI_XFER_BEGIN)) {
+ return -1;
+ }
+ }
+ return ((*(g_rx_buf + 1)) >> 6) & 0xffff;
+}
+
+struct spi_slave *spi_cpld_probe()
+{
+ u32 reg;
+ cpld_slave = spi_setup_slave(0, 0, 25000000, 0);
+
+ udelay(1000);
+
+ /* Reset interrupt status reg */
+ cpld_reg_write(PBC_INT_REST, 0x1F);
+ cpld_reg_write(PBC_INT_REST, 0);
+ cpld_reg_write(PBC_INT_MASK, 0xFFFF);
+ /* Reset the XUART and Ethernet controllers */
+ reg = cpld_reg_read(PBC_SW_RESET);
+ reg |= 0x9;
+ cpld_reg_write(PBC_SW_RESET, reg);
+ reg &= ~0x9;
+ cpld_reg_write(PBC_SW_RESET, reg);
+
+ return cpld_slave;
+}
+
+void mxc_cpld_spi_init(void)
+{
+ spi_cpld_probe();
+}
+
+void spi_cpld_free(struct spi_slave *slave)
+{
+ if (slave)
+ spi_free_slave(slave);
+}
--- /dev/null
+/*
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <spi.h>
+#include <asm/errno.h>
+#include <linux/types.h>
+
+#include <imx_spi.h>
+
+static u32 pmic_tx, pmic_rx;
+
+/*!
+ * To read/write to a PMIC register. For write, it does another read for the
+ * actual register value.
+ *
+ * @param reg register number inside the PMIC
+ * @param val data to be written to the register; don't care for read
+ * @param write 0 for read; 1 for write
+ *
+ * @return the actual data in the PMIC register
+ */
+u32 pmic_reg(struct spi_slave *slave, u32 reg, u32 val, u32 write)
+{
+ if (!slave)
+ return 0;
+
+ if (reg > 63 || write > 1) {
+ printf("<reg num> = %d is invalide. Should be less then 63\n",
+ reg);
+ return 0;
+ }
+ pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF);
+ debug("reg=0x%x, val=0x%08x\n", reg, pmic_tx);
+
+ if (spi_xfer(slave, 4 << 3, (u8 *)&pmic_tx, (u8 *)&pmic_rx,
+ SPI_XFER_BEGIN | SPI_XFER_END)) {
+ return -1;
+ }
+
+ if (write) {
+ pmic_tx &= ~(1 << 31);
+ if (spi_xfer(slave, 4 << 3, (u8 *)&pmic_tx, (u8 *)&pmic_rx,
+ SPI_XFER_BEGIN | SPI_XFER_END)) {
+ return -1;
+ }
+ }
+
+ return pmic_rx;
+}
+
+void show_pmic_info(struct spi_slave *slave)
+{
+ volatile u32 rev_id;
+
+ if (!slave)
+ return;
+
+ rev_id = pmic_reg(slave, 7, 0, 0);
+ debug("PMIC ID: 0x%08x [Rev: ", rev_id);
+ switch (rev_id & 0x1F) {
+ case 0x1:
+ printf("1.0");
+ break;
+ case 0x9:
+ printf("1.1");
+ break;
+ case 0xA:
+ printf("1.2");
+ break;
+ case 0x10:
+ printf("2.0");
+ break;
+ case 0x11:
+ printf("2.1");
+ break;
+ case 0x18:
+ printf("3.0");
+ break;
+ case 0x19:
+ printf("3.1");
+ break;
+ case 0x1A:
+ printf("3.2");
+ break;
+ case 0x2:
+ printf("3.2A");
+ break;
+ case 0x1B:
+ printf("3.3");
+ break;
+ case 0x1D:
+ printf("3.5");
+ break;
+ default:
+ printf("unknown");
+ break;
+ }
+ printf("]\n");
+}
+
+struct spi_slave *spi_pmic_probe(void)
+{
+ return spi_setup_slave(0, CONFIG_IMX_SPI_PMIC_CS, 2500000, 0);
+}
+
+void spi_pmic_free(struct spi_slave *slave)
+{
+ if (slave)
+ spi_free_slave(slave);
+}
COBJS-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o
COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
+COBJS-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
-COBJS-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
+COBJS-$(CONFIG_VIDEO_MXS) += mxsfb.o
COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
#include <video_fb.h>
#include <linux/list.h>
#include <linux/fb.h>
+#include <lcd.h>
#include <asm/errno.h>
#include <asm/io.h>
-#include <asm/arch/hardware.h>
+#include <asm/arch/cpu.h>
#include "videomodes.h"
#include <asm/arch/da8xx-fb.h>
#define DRIVER_NAME "da8xx_lcdc"
+#define LCD_VERSION_1 1
+#define LCD_VERSION_2 2
+
+#define BIT(x) (1 << (x))
+
/* LCD Status Register */
-#define LCD_END_OF_FRAME1 (1 << 9)
-#define LCD_END_OF_FRAME0 (1 << 8)
-#define LCD_PL_LOAD_DONE (1 << 6)
-#define LCD_FIFO_UNDERFLOW (1 << 5)
-#define LCD_SYNC_LOST (1 << 2)
+#define LCD_END_OF_FRAME1 BIT(9)
+#define LCD_END_OF_FRAME0 BIT(8)
+#define LCD_PL_LOAD_DONE BIT(6)
+#define LCD_FIFO_UNDERFLOW BIT(5)
+#define LCD_SYNC_LOST BIT(2)
/* LCD DMA Control Register */
#define LCD_DMA_BURST_SIZE(x) ((x) << 4)
+#define LCD_DMA_BURST_SIZE_MASK (0x7 << 4)
#define LCD_DMA_BURST_1 0x0
#define LCD_DMA_BURST_2 0x1
#define LCD_DMA_BURST_4 0x2
#define LCD_DMA_BURST_8 0x3
#define LCD_DMA_BURST_16 0x4
-#define LCD_END_OF_FRAME_INT_ENA (1 << 2)
-#define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
+#define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)
+#define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8)
+#define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9)
+#define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
/* LCD Control Register */
#define LCD_CLK_DIVISOR(x) ((x) << 8)
#define PALETTE_ONLY 0x01
#define DATA_ONLY 0x02
-#define LCD_MONO_8BIT_MODE (1 << 9)
-#define LCD_RASTER_ORDER (1 << 8)
-#define LCD_TFT_MODE (1 << 7)
-#define LCD_UNDERFLOW_INT_ENA (1 << 6)
-#define LCD_PL_ENABLE (1 << 4)
-#define LCD_MONOCHROME_MODE (1 << 1)
-#define LCD_RASTER_ENABLE (1 << 0)
-#define LCD_TFT_ALT_ENABLE (1 << 23)
-#define LCD_STN_565_ENABLE (1 << 24)
+#define LCD_MONO_8BIT_MODE BIT(9)
+#define LCD_RASTER_ORDER BIT(8)
+#define LCD_TFT_MODE BIT(7)
+#define LCD_V1_UNDERFLOW_INT_ENA BIT(6)
+#define LCD_V2_UNDERFLOW_INT_ENA BIT(5)
+#define LCD_V1_PL_INT_ENA BIT(4)
+#define LCD_V2_PL_INT_ENA BIT(6)
+#define LCD_MONOCHROME_MODE BIT(1)
+#define LCD_RASTER_ENABLE BIT(0)
+#define LCD_TFT_ALT_ENABLE BIT(23)
+#define LCD_STN_565_ENABLE BIT(24)
+#define LCD_TFT24 BIT(25)
+#define LCD_TFT24_UNPACKED BIT(26)
+#define LCD_V2_DMA_CLK_EN BIT(2)
+#define LCD_V2_LIDD_CLK_EN BIT(1)
+#define LCD_V2_CORE_CLK_EN BIT(0)
+#define LCD_V2_LPP_B10 26
/* LCD Raster Timing 2 Register */
#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
#define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
-#define LCD_SYNC_CTRL (1 << 25)
-#define LCD_SYNC_EDGE (1 << 24)
-#define LCD_INVERT_PIXEL_CLOCK (1 << 22)
-#define LCD_INVERT_LINE_CLOCK (1 << 21)
-#define LCD_INVERT_FRAME_CLOCK (1 << 20)
+#define LCD_SYNC_CTRL BIT(25)
+#define LCD_SYNC_EDGE BIT(24)
+#define LCD_INVERT_PIXEL_CLOCK BIT(22)
+#define LCD_INVERT_LINE_CLOCK BIT(21)
+#define LCD_INVERT_FRAME_CLOCK BIT(20)
+
+/* Clock reset register */
+#define LCD_CLK_MAIN_RESET BIT(3)
/* LCD Block */
struct da8xx_lcd_regs {
- u32 revid;
- u32 ctrl;
- u32 stat;
- u32 lidd_ctrl;
- u32 lidd_cs0_conf;
- u32 lidd_cs0_addr;
- u32 lidd_cs0_data;
- u32 lidd_cs1_conf;
- u32 lidd_cs1_addr;
- u32 lidd_cs1_data;
- u32 raster_ctrl;
- u32 raster_timing_0;
- u32 raster_timing_1;
- u32 raster_timing_2;
- u32 raster_subpanel;
- u32 reserved;
- u32 dma_ctrl;
- u32 dma_frm_buf_base_addr_0;
- u32 dma_frm_buf_ceiling_addr_0;
- u32 dma_frm_buf_base_addr_1;
- u32 dma_frm_buf_ceiling_addr_1;
+ u32 revid; /* 0x00 */
+ u32 ctrl; /* 0x04 */
+ u32 stat; /* 0x08 */
+ u32 lidd_ctrl; /* 0x0c */
+ u32 lidd_cs0_conf; /* 0x10 */
+ u32 lidd_cs0_addr; /* 0x14 */
+ u32 lidd_cs0_data; /* 0x18 */
+ u32 lidd_cs1_conf; /* 0x1c */
+ u32 lidd_cs1_addr; /* 0x20 */
+ u32 lidd_cs1_data; /* 0x24 */
+ u32 raster_ctrl; /* 0x28 */
+ u32 raster_timing_0; /* 0x2c */
+ u32 raster_timing_1; /* 0x30 */
+ u32 raster_timing_2; /* 0x34 */
+ u32 raster_subpanel; /* 0x38 */
+ u32 reserved; /* 0x3c */
+ u32 dma_ctrl; /* 0x40 */
+ u32 dma_frm_buf_base_addr_0; /* 0x44 */
+ u32 dma_frm_buf_ceiling_addr_0; /* 0x48 */
+ u32 dma_frm_buf_base_addr_1; /* 0x4c */
+ u32 dma_frm_buf_ceiling_addr_1; /* 0x50 */
+ u32 rsrvd1; /* 0x54 */
+ u32 raw_stat; /* 0x58 */
+ u32 masked_stat; /* 0x5c */
+ u32 int_enable_set; /* 0x60 */
+ u32 int_enable_clr; /* 0x64 */
+ u32 end_of_int_ind; /* 0x68 */
+ u32 clk_enable; /* 0x6c */
+ u32 clk_reset; /* 0x70 */
};
#define LCD_NUM_BUFFERS 1
#define UPPER_MARGIN 32
#define LOWER_MARGIN 32
-#define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
+DECLARE_GLOBAL_DATA_PTR;
static struct da8xx_lcd_regs *da8xx_fb_reg_base;
-
-DECLARE_GLOBAL_DATA_PTR;
+static unsigned int lcd_revision;
/* graphics setup */
static GraphicDevice gpanel;
static const struct da8xx_panel *lcd_panel;
static struct fb_info *da8xx_fb_info;
static int bits_x_pixel;
+static u32 (*lcdc_irq_handler)(void);
static inline unsigned int lcdc_read(u32 *addr)
{
- return (unsigned int)readl(addr);
+ return readl(addr);
}
static inline void lcdc_write(unsigned int val, u32 *addr)
}
struct da8xx_fb_par {
- u32 p_palette_base;
- unsigned char *v_palette_base;
+ unsigned long p_palette_base;
+ void *v_palette_base;
dma_addr_t vram_phys;
unsigned long vram_size;
void *vram_virt;
int vsync_timeout;
};
-
/* Variable Screen Information */
static struct fb_var_screeninfo da8xx_fb_var = {
.xoffset = 0,
};
static const struct display_panel disp_panel = {
- QVGA,
- 16,
- 16,
- COLOR_ACTIVE,
+ .panel_type = QVGA,
+ .max_bpp = 24,
+ .min_bpp = 16,
+ .panel_shade = COLOR_ACTIVE,
};
static const struct lcd_ctrl_config lcd_cfg = {
.ac_bias = 255,
.ac_bias_intrpt = 0,
.dma_burst_sz = 16,
- .bpp = 16,
+ .bpp = 1 << LCD_BPP,
.fdd = 255,
.tft_alt_mode = 0,
.stn_565_mode = 0,
{
u32 reg;
+ /* Bring LCDC out of reset */
+ if (lcd_revision == LCD_VERSION_2)
+ lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
+
reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
if (!(reg & LCD_RASTER_ENABLE))
lcdc_write(reg | LCD_RASTER_ENABLE,
if (reg & LCD_RASTER_ENABLE)
lcdc_write(reg & ~LCD_RASTER_ENABLE,
&da8xx_fb_reg_base->raster_ctrl);
+ if (lcd_revision == LCD_VERSION_2)
+ /* Write 1 to reset LCDC */
+ lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
}
static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
u32 end;
u32 reg_ras;
u32 reg_dma;
+ u32 reg_int;
/* init reg to clear PLM (loading mode) fields */
reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
end = par->dma_end;
reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
- reg_dma |= LCD_END_OF_FRAME_INT_ENA;
-
+ if (lcd_revision == LCD_VERSION_1) {
+ reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
+ } else {
+ reg_int = lcdc_read(&da8xx_fb_reg_base->int_enable_set) |
+ LCD_V2_END_OF_FRAME0_INT_ENA |
+ LCD_V2_END_OF_FRAME1_INT_ENA;
+ lcdc_write(reg_int,
+ &da8xx_fb_reg_base->int_enable_set);
+ }
#if (LCD_NUM_BUFFERS == 2)
reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
#endif
-
} else if (load_mode == LOAD_PALETTE) {
start = par->p_palette_base;
end = start + par->palette_sz - 1;
reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
- reg_ras |= LCD_PL_ENABLE;
+ if (lcd_revision == LCD_VERSION_1) {
+ reg_ras |= LCD_V1_PL_INT_ENA;
+ } else {
+ reg_int = lcdc_read(&da8xx_fb_reg_base->int_enable_set) |
+ LCD_V2_PL_INT_ENA;
+ lcdc_write(reg_int, &da8xx_fb_reg_base->int_enable_set);
+ }
lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
}
{
u32 reg;
- reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
+ reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
+ reg &= ~LCD_DMA_BURST_SIZE_MASK;
switch (burst_size) {
case 1:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
{
u32 reg;
+ u32 reg_int;
reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
LCD_MONO_8BIT_MODE |
- LCD_MONOCHROME_MODE);
+ LCD_MONOCHROME_MODE |
+ LCD_TFT24 |
+ LCD_TFT24_UNPACKED);
switch (cfg->p_disp_panel->panel_shade) {
case MONOCHROME:
}
/* enable additional interrupts here */
- reg |= LCD_UNDERFLOW_INT_ENA;
+ if (lcd_revision == LCD_VERSION_1) {
+ reg |= LCD_V1_UNDERFLOW_INT_ENA;
+ } else {
+ if (bits_x_pixel >= 24)
+ reg |= LCD_TFT24;
+ if (cfg->bpp == 32)
+ reg |= LCD_TFT24_UNPACKED;
+ reg_int = lcdc_read(&da8xx_fb_reg_base->int_enable_set) |
+ LCD_V2_UNDERFLOW_INT_ENA;
+ lcdc_write(reg_int, &da8xx_fb_reg_base->int_enable_set);
+ }
lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
/* Set the Panel Width */
/* Pixels per line = (PPL + 1)*16 */
- /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
- width &= 0x3f0;
+ /* Pixels per line = (PPL + 1)*16 */
+ if (lcd_revision == LCD_VERSION_1) {
+ /*
+ * 0x3F in bits 4..9 gives max horizontal resolution = 1024
+ * pixels.
+ */
+ width &= 0x3f0;
+ } else {
+ /*
+ * 0x7F in bits 4..10 gives max horizontal resolution = 2048
+ * pixels.
+ */
+ width &= 0x7f0;
+ }
+
reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
reg &= 0xfffffc00;
- reg |= ((width >> 4) - 1) << 4;
+ if (lcd_revision == LCD_VERSION_1) {
+ reg |= ((width >> 4) - 1) << 4;
+ } else {
+ width = (width >> 4) - 1;
+ reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
+ }
lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
/* Set the Panel Height */
+ /* Set bits 9:0 of Lines Per Pixel */
reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
+ /* Set bit 10 of Lines Per Pixel */
+ if (lcd_revision == LCD_VERSION_2) {
+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
+ reg |= ((height - 1) & 0x400) << 16;
+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
+ }
+
/* Set the Raster Order of the Frame Buffer */
reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
if (raster_order)
case 2:
case 4:
case 16:
+ case 24:
par->palette_sz = 16 * 2;
break;
struct fb_info *info)
{
struct da8xx_fb_par *par = info->par;
- unsigned short *palette = (unsigned short *) par->v_palette_base;
+ unsigned short *palette = par->v_palette_base;
u_short pal;
int update_hw = 0;
update_hw = 1;
palette[regno] = pal;
}
- } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
+ } else if ((info->var.bits_per_pixel >= 16) && regno < 16) {
red >>= (16 - info->var.red.length);
red <<= info->var.red.offset;
/* DMA has to be disabled */
lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
+
+ if (lcd_revision == LCD_VERSION_2) {
+ lcdc_write(0, &da8xx_fb_reg_base->int_enable_set);
+ /* Write 1 to reset */
+ lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
+ lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
+ }
}
static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
{
unsigned int lcd_clk, div;
+#ifndef CONFIG_AM33XX
/* Get clock from sysclk2 */
lcd_clk = clk_get(2);
-
- div = lcd_clk / par->pxl_clk;
- debug("LCD Clock: 0x%x Divider: 0x%x PixClk: 0x%x\n",
- lcd_clk, div, par->pxl_clk);
+#else
+ lcd_clk = lcdc_clk_rate();
+#endif
+ /* calculate divisor so that the resulting clock is rounded down */
+ div = (lcd_clk + par->pxl_clk - 1)/ par->pxl_clk;
+ if (div > 255)
+ div = 255;
+ if (div < 2)
+ div = 2;
+
+ debug("LCD Clock: %u.%03uMHz Divider: 0x%08x PixClk requested: %u.%03uMHz actual: %u.%03uMHz\n",
+ lcd_clk / 1000000, lcd_clk / 1000 % 1000, div,
+ par->pxl_clk / 1000000, par->pxl_clk / 1000 % 1000,
+ lcd_clk / div / 1000000, lcd_clk / div / 1000 % 1000);
/* Configure the LCD clock divisor. */
- lcdc_write(LCD_CLK_DIVISOR(div) |
- (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
+ lcdc_write(LCD_CLK_DIVISOR(div) | LCD_RASTER_MODE,
+ &da8xx_fb_reg_base->ctrl);
+
+ if (lcd_revision == LCD_VERSION_2)
+ lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
+ LCD_V2_CORE_CLK_EN, &da8xx_fb_reg_base->clk_enable);
+
}
static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
- /* Configure for disply */
+ /* Configure for display */
ret = lcd_cfg_display(cfg);
if (ret < 0)
return ret;
&da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
}
-static u32 lcdc_irq_handler(void)
+/* IRQ handler for version 2 of LCDC */
+static u32 lcdc_irq_handler_rev02(void)
+{
+ u32 ret = 0;
+ struct da8xx_fb_par *par = da8xx_fb_info->par;
+ u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
+
+ debug("%s: stat=%08x\n", __func__, stat);
+
+ if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
+ debug("LCD_SYNC_LOST\n");
+ lcd_disable_raster();
+ lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
+ lcd_enable_raster();
+ ret = LCD_SYNC_LOST;
+ } else if (stat & LCD_PL_LOAD_DONE) {
+ debug("LCD_PL_LOAD_DONE\n");
+ /*
+ * Must disable raster before changing state of any control bit.
+ * And also must be disabled before clearing the PL loading
+ * interrupt via the following write to the status register. If
+ * this is done after then one gets multiple PL done interrupts.
+ */
+ lcd_disable_raster();
+
+ lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
+
+ /* Disable PL completion inerrupt */
+ lcdc_write(LCD_V2_PL_INT_ENA,
+ &da8xx_fb_reg_base->int_enable_clr);
+
+ /* Setup and start data loading mode */
+ lcd_blit(LOAD_DATA, par);
+ ret = LCD_PL_LOAD_DONE;
+ } else if (stat & (LCD_END_OF_FRAME0 | LCD_END_OF_FRAME1)) {
+ par->vsync_flag = 1;
+ lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
+
+ if (stat & LCD_END_OF_FRAME0) {
+ debug("LCD_END_OF_FRAME0\n");
+
+ lcdc_write(par->dma_start,
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(par->dma_end,
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ }
+ if (stat & LCD_END_OF_FRAME1) {
+ debug("LCD_END_OF_FRAME1\n");
+ lcdc_write(par->dma_start,
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+ lcdc_write(par->dma_end,
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+ par->vsync_flag = 1;
+ }
+ ret = (stat & LCD_END_OF_FRAME0) ?
+ LCD_END_OF_FRAME0 : LCD_END_OF_FRAME1;
+ }
+ lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
+ return ret;
+}
+
+static u32 lcdc_irq_handler_rev01(void)
{
struct da8xx_fb_par *par = da8xx_fb_info->par;
u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
/* Disable PL completion inerrupt */
reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
- reg_ras &= ~LCD_PL_ENABLE;
+ reg_ras &= ~LCD_V1_PL_INT_ENA;
lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
/* Setup and start data loading mode */
lcd_blit(LOAD_DATA, par);
return LCD_PL_LOAD_DONE;
- } else {
+ } else if (stat & (LCD_END_OF_FRAME0 | LCD_END_OF_FRAME1)) {
+ par->vsync_flag = 1;
lcdc_write(stat, &da8xx_fb_reg_base->stat);
- if (stat & LCD_END_OF_FRAME0)
+ if (stat & LCD_END_OF_FRAME0) {
debug("LCD_END_OF_FRAME0\n");
- lcdc_write(par->dma_start,
- &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
- lcdc_write(par->dma_end,
- &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
- par->vsync_flag = 1;
- return LCD_END_OF_FRAME0;
+ lcdc_write(par->dma_start,
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
+ lcdc_write(par->dma_end,
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
+ }
+
+ if (stat & LCD_END_OF_FRAME1) {
+ debug("LCD_END_OF_FRAME1\n");
+ lcdc_write(par->dma_start,
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
+ lcdc_write(par->dma_end,
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
+ }
+
+ return (stat & LCD_END_OF_FRAME0) ?
+ LCD_END_OF_FRAME0 : LCD_END_OF_FRAME1;
}
return stat;
}
static u32 wait_for_event(u32 event)
{
- u32 timeout = 50000;
+ int timeout = 100;
u32 ret;
do {
ret = lcdc_irq_handler();
+ if (ret & event)
+ break;
udelay(1000);
- } while (!(ret & event));
+ } while (--timeout > 0);
if (timeout <= 0) {
printf("%s: event %d not hit\n", __func__, event);
printf("Display not initialized\n");
return NULL;
}
+
gpanel.winSizeX = lcd_panel->width;
gpanel.winSizeY = lcd_panel->height;
gpanel.plnSizeX = lcd_panel->width;
default:
gpanel.gdfBytesPP = 1;
gpanel.gdfIndex = GDF__8BIT_INDEX;
- break;
}
da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE;
- debug("Resolution: %dx%d %x\n",
+ /* Determine LCD IP Version */
+
+ lcd_revision = lcdc_read(&da8xx_fb_reg_base->revid);
+ switch (lcd_revision & 0xfff00000) {
+ case 0x4C100000:
+ lcd_revision = LCD_VERSION_1;
+ break;
+
+ case 0x4F200000:
+ lcd_revision = LCD_VERSION_2;
+ break;
+
+ default:
+ printf("Unknown PID Reg value 0x%08x, defaulting to LCD revision 1\n",
+ lcd_revision);
+ lcd_revision = LCD_VERSION_1;
+ }
+
+ debug("Resolution: %dx%d %d\n",
gpanel.winSizeX,
gpanel.winSizeY,
lcd_cfg.bpp);
size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
da8xx_fb_info = malloc(size);
- debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
+ debug("da8xx_fb_info at %p\n", da8xx_fb_info);
if (!da8xx_fb_info) {
printf("Memory allocation failed for fb_info\n");
par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp;
par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
+#ifdef CONFIG_LCD
+ par->vram_virt = lcd_base;
+#else
par->vram_virt = malloc(par->vram_size);
-
+#endif
par->vram_phys = (dma_addr_t) par->vram_virt;
- debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
- (unsigned int)par->vram_size,
- (unsigned int)par->vram_virt);
+ debug("Requesting 0x%lx bytes for framebuffer at 0x%p\n",
+ par->vram_size, par->vram_virt);
if (!par->vram_virt) {
printf("GLCD: malloc for frame buffer failed\n");
goto err_release_fb;
}
gpanel.frameAdrs = (unsigned int)par->vram_virt;
- da8xx_fb_info->screen_base = (char *) par->vram_virt;
+ da8xx_fb_info->screen_base = par->vram_virt;
da8xx_fb_fix.smem_start = gpanel.frameAdrs;
da8xx_fb_fix.smem_len = par->vram_size;
da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8;
-
+ debug("%s: vram_virt: %p size %ux%u=%lu bpp %u\n", __func__,
+ par->vram_virt, lcd_panel->width, lcd_panel->height,
+ par->vram_size, lcd_cfg.bpp);
par->dma_start = par->vram_phys;
par->dma_end = par->dma_start + lcd_panel->height *
da8xx_fb_fix.line_length - 1;
goto err_release_fb_mem;
}
memset(par->v_palette_base, 0, PALETTE_SIZE);
- par->p_palette_base = (unsigned int)par->v_palette_base;
-
- /* Initialize par */
- da8xx_fb_info->var.bits_per_pixel = lcd_cfg.bpp;
+ par->p_palette_base = (unsigned long)par->v_palette_base;
+ /* Initialize var */
da8xx_fb_var.xres = lcd_panel->width;
da8xx_fb_var.xres_virtual = lcd_panel->width;
da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
+ if (lcd_revision == LCD_VERSION_1)
+ lcdc_irq_handler = lcdc_irq_handler_rev01;
+ else
+ lcdc_irq_handler = lcdc_irq_handler_rev02;
+
/* Clear interrupt */
- memset((void *)par->vram_virt, 0, par->vram_size);
+ memset(par->vram_virt, 0, par->vram_size);
lcd_disable_raster();
lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
- debug("Palette at 0x%x size %d\n", par->p_palette_base,
+ debug("Palette at 0x%08lx size %u\n", par->p_palette_base,
par->palette_sz);
lcdc_dma_start();
/* Wait until DMA is working */
wait_for_event(LCD_END_OF_FRAME0);
- return (void *)&gpanel;
+ return &gpanel;
err_release_fb_mem:
+#ifndef CONFIG_LCD
free(par->vram_virt);
+#endif
err_release_fb:
free(da8xx_fb_info);
return NULL;
}
+void da8xx_fb_disable(void)
+{
+ lcd_reset(da8xx_fb_info->par);
+}
+
void video_set_lut(unsigned int index, /* color number */
unsigned char r, /* red */
unsigned char g, /* green */
unsigned char b /* blue */
)
{
-
- return;
}
void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel)
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de
*
- * Linux IPU driver for MX51:
+ * Linux IPU driver
*
- * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
+ * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
/* #define DEBUG */
#include <common.h>
+#include <ipu.h>
#include <linux/types.h>
#include <linux/err.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
-#include "ipu.h"
-#include "ipu_regs.h"
+#include <asm/arch/clock.h>
-extern struct mxc_ccm_reg *mxc_ccm;
-extern u32 *ipu_cpmem_base;
+#include "ipu_regs.h"
struct ipu_ch_param_word {
uint32_t data[5];
#define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
#define _param_word(base, w) \
- (((struct ipu_ch_param *)(base))->word[(w)].data)
+ (((struct ipu_ch_param *)(base))->word[w].data)
-#define ipu_ch_param_set_field(base, w, bit, size, v) { \
- int i = (bit) / 32; \
- int off = (bit) % 32; \
- _param_word(base, w)[i] |= (v) << off; \
- if (((bit) + (size) - 1) / 32 > i) { \
+#define ipu_ch_param_set_field(base, w, bit, size, v) { \
+ int i = (bit) / 32; \
+ int off = (bit) % 32; \
+ _param_word(base, w)[i] |= (v) << off; \
+ if (((bit) + (size) - 1) / 32 > i) { \
_param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
- } \
+ } \
}
-#define ipu_ch_param_mod_field(base, w, bit, size, v) { \
- int i = (bit) / 32; \
- int off = (bit) % 32; \
- u32 mask = (1UL << size) - 1; \
- u32 temp = _param_word(base, w)[i]; \
- temp &= ~(mask << off); \
- _param_word(base, w)[i] = temp | (v) << off; \
- if (((bit) + (size) - 1) / 32 > i) { \
- temp = _param_word(base, w)[i + 1]; \
- temp &= ~(mask >> (32 - off)); \
- _param_word(base, w)[i + 1] = \
+#define ipu_ch_param_mod_field(base, w, bit, size, v) { \
+ int i = (bit) / 32; \
+ int off = (bit) % 32; \
+ u32 mask = (1UL << size) - 1; \
+ u32 temp = _param_word(base, w)[i]; \
+ temp &= ~(mask << off); \
+ _param_word(base, w)[i] = temp | (v) << off; \
+ if (((bit) + (size) - 1) / 32 > i) { \
+ temp = _param_word(base, w)[i + 1]; \
+ temp &= ~(mask >> (32 - off)); \
+ _param_word(base, w)[i + 1] = \
temp | ((v) >> (off ? (32 - off) : 0)); \
- } \
+ } \
}
-#define ipu_ch_param_read_field(base, w, bit, size) ({ \
- u32 temp2; \
- int i = (bit) / 32; \
- int off = (bit) % 32; \
- u32 mask = (1UL << size) - 1; \
- u32 temp1 = _param_word(base, w)[i]; \
- temp1 = mask & (temp1 >> off); \
- if (((bit)+(size) - 1) / 32 > i) { \
- temp2 = _param_word(base, w)[i + 1]; \
- temp2 &= mask >> (off ? (32 - off) : 0); \
- temp1 |= temp2 << (off ? (32 - off) : 0); \
- } \
- temp1; \
+#define ipu_ch_param_read_field(base, w, bit, size) ({ \
+ u32 temp2; \
+ int i = (bit) / 32; \
+ int off = (bit) % 32; \
+ u32 mask = (1UL << size) - 1; \
+ u32 temp1 = _param_word(base, w)[i]; \
+ temp1 = mask & (temp1 >> off); \
+ if (((bit)+(size) - 1) / 32 > i) { \
+ temp2 = _param_word(base, w)[i + 1]; \
+ temp2 &= mask >> (off ? (32 - off) : 0); \
+ temp1 |= temp2 << (off ? (32 - off) : 0); \
+ } \
+ temp1; \
})
-#define IPU_SW_RST_TOUT_USEC (10000)
-
-void clk_enable(struct clk *clk)
-{
- if (clk) {
- if (clk->usecount++ == 0) {
- clk->enable(clk);
- }
- }
-}
-
-void clk_disable(struct clk *clk)
-{
- if (clk) {
- if (!(--clk->usecount)) {
- if (clk->disable)
- clk->disable(clk);
- }
- }
-}
-
int clk_get_usecount(struct clk *clk)
{
if (clk == NULL)
int clk_set_parent(struct clk *clk, struct clk *parent)
{
+ debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
+ clk ? clk->parent : NULL);
+
+ if (!clk || clk == parent)
+ return 0;
+
+ if (clk->set_parent) {
+ int ret;
+
+ ret = clk->set_parent(clk, parent);
+ if (ret)
+ return ret;
+ }
clk->parent = parent;
- if (clk->set_parent)
- return clk->set_parent(clk, parent);
return 0;
}
static int clk_ipu_enable(struct clk *clk)
{
- u32 reg;
-
- reg = __raw_readl(clk->enable_reg);
- reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift;
- __raw_writel(reg, clk->enable_reg);
-
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
- /* Handshake with IPU when certain clock rates are changed. */
- reg = __raw_readl(&mxc_ccm->ccdr);
- reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
- __raw_writel(reg, &mxc_ccm->ccdr);
-
- /* Handshake with IPU when LPM is entered as its enabled. */
- reg = __raw_readl(&mxc_ccm->clpcr);
- reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
- __raw_writel(reg, &mxc_ccm->clpcr);
-#endif
+ ipu_clk_enable();
return 0;
}
static void clk_ipu_disable(struct clk *clk)
{
- u32 reg;
-
- reg = __raw_readl(clk->enable_reg);
- reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);
- __raw_writel(reg, clk->enable_reg);
-
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
- /*
- * No handshake with IPU whe dividers are changed
- * as its not enabled.
- */
- reg = __raw_readl(&mxc_ccm->ccdr);
- reg |= MXC_CCM_CCDR_IPU_HS_MASK;
- __raw_writel(reg, &mxc_ccm->ccdr);
-
- /* No handshake with IPU when LPM is entered as its not enabled. */
- reg = __raw_readl(&mxc_ccm->clpcr);
- reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
- __raw_writel(reg, &mxc_ccm->clpcr);
-#endif
+ ipu_clk_disable();
}
-
static struct clk ipu_clk = {
.name = "ipu_clk",
- .rate = CONFIG_IPUV3_CLK,
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
- .enable_reg = (u32 *)(CCM_BASE_ADDR +
- offsetof(struct mxc_ccm_reg, CCGR5)),
- .enable_shift = MXC_CCM_CCGR5_IPU_OFFSET,
-#else
- .enable_reg = (u32 *)(CCM_BASE_ADDR +
- offsetof(struct mxc_ccm_reg, CCGR3)),
- .enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET,
+#if defined(CONFIG_IPU_CLKRATE)
+ .rate = CONFIG_IPU_CLKRATE,
#endif
.enable = clk_ipu_enable,
.disable = clk_ipu_disable,
- .usecount = 0,
-};
-
-static struct clk ldb_clk = {
- .name = "ldb_clk",
- .rate = 65000000,
- .usecount = 0,
};
/* Globals */
struct clk *g_ipu_clk;
-struct clk *g_ldb_clk;
-unsigned char g_ipu_clk_enabled;
struct clk *g_di_clk[2];
struct clk *g_pixel_clk[2];
unsigned char g_dc_di_assignment[10];
-uint32_t g_channel_init_mask;
-uint32_t g_channel_enable_mask;
+int g_ipu_clk_enabled;
+u32 *ipu_dc_tmpl_reg;
+static uint32_t g_channel_init_mask;
+static uint32_t g_channel_enable_mask;
static int ipu_dc_use_count;
static int ipu_dp_use_count;
static int ipu_dmfc_use_count;
static int ipu_di_use_count[2];
-u32 *ipu_cpmem_base;
-u32 *ipu_dc_tmpl_reg;
+static u32 *ipu_cpmem_base;
/* Static functions */
unsigned long rate)
{
u32 div, div1;
- u32 tmp;
+ u64 tmp;
/*
* Calculate divider
* Fractional part is 4 bits,
* so simply multiply by 2^4 to get fractional part.
*/
- tmp = (clk->parent->rate * 16);
+ tmp = (u64)clk->parent->rate * 16;
div = tmp / rate;
if (div < 0x10) /* Min DI disp clock divider is 1 */
else
div &= 0xFF8;
}
- return (clk->parent->rate * 16) / div;
+ tmp /= div;
+#if 1
+ debug("%s: requested rate: %lu.%03luMHz parent_rate: %lu.%03luMHz actual rate: %llu.%03lluMHz div: %u.%u\n", __func__,
+ rate / 1000000, rate / 1000 % 1000,
+ clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
+ tmp / 1000000, tmp / 1000 % 1000, div / 16, div % 16);
+#endif
+ return tmp;
}
static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
{
- u32 div = (clk->parent->rate * 16) / rate;
+ u32 div = ((u64)clk->parent->rate * 16) / rate;
+
+ debug("%s: parent_rate: %lu.%03luMHz actual rate: %lu.%03luMHz div: %u.%u\n", __func__,
+ clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
+ rate / 1000000, rate / 1000 % 1000, div / 16, div % 16);
__raw_writel(div, DI_BS_CLKGEN0(clk->id));
/* Setup pixel clock timing */
__raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
- clk->rate = (clk->parent->rate * 16) / div;
+ clk->rate = ((u64)clk->parent->rate * 16) / div;
+ debug("%s: pix_clk=%lu.%03luMHz\n", __func__,
+ clk->rate / 1000000, clk->rate / 1000 % 1000);
return 0;
}
u32 disp_gen = __raw_readl(IPU_DISP_GEN);
disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
__raw_writel(disp_gen, IPU_DISP_GEN);
-
}
static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
{
- u32 di_gen = __raw_readl(DI_GENERAL(clk->id));
+ int ret;
+ u32 di_gen;
+
+ ret = clk_enable(clk);
+ if (ret)
+ return ret;
+
+ di_gen = __raw_readl(DI_GENERAL(clk->id));
if (parent == g_ipu_clk)
di_gen &= ~DI_GEN_DI_CLK_EXT;
- else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk)
+ else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_di_clk[clk->id])
di_gen |= DI_GEN_DI_CLK_EXT;
else
- return -EINVAL;
+ goto err;
+ ret = clk_enable(parent);
+ if (ret)
+ goto err;
__raw_writel(di_gen, DI_GENERAL(clk->id));
ipu_pixel_clk_recalc(clk);
- return 0;
+ clk->disable(clk->parent);
+ clk->parent = parent;
+err:
+ clk_disable(clk);
+ return ret;
}
static struct clk pixel_clk[] = {
{
- .name = "pixel_clk",
- .id = 0,
- .recalc = ipu_pixel_clk_recalc,
- .set_rate = ipu_pixel_clk_set_rate,
- .round_rate = ipu_pixel_clk_round_rate,
- .set_parent = ipu_pixel_clk_set_parent,
- .enable = ipu_pixel_clk_enable,
- .disable = ipu_pixel_clk_disable,
- .usecount = 0,
+ .name = "pixel_clk",
+ .id = 0,
+ .recalc = ipu_pixel_clk_recalc,
+ .set_rate = ipu_pixel_clk_set_rate,
+ .round_rate = ipu_pixel_clk_round_rate,
+ .set_parent = ipu_pixel_clk_set_parent,
+ .enable = ipu_pixel_clk_enable,
+ .disable = ipu_pixel_clk_disable,
},
{
- .name = "pixel_clk",
- .id = 1,
- .recalc = ipu_pixel_clk_recalc,
- .set_rate = ipu_pixel_clk_set_rate,
- .round_rate = ipu_pixel_clk_round_rate,
- .set_parent = ipu_pixel_clk_set_parent,
- .enable = ipu_pixel_clk_enable,
- .disable = ipu_pixel_clk_disable,
- .usecount = 0,
+ .name = "pixel_clk",
+ .id = 1,
+ .recalc = ipu_pixel_clk_recalc,
+ .set_rate = ipu_pixel_clk_set_rate,
+ .round_rate = ipu_pixel_clk_round_rate,
+ .set_parent = ipu_pixel_clk_set_parent,
+ .enable = ipu_pixel_clk_enable,
+ .disable = ipu_pixel_clk_disable,
+ },
+};
+
+static struct clk di_clk[] = {
+ {
+ .name = "ipu_di_clk",
+ .id = 0,
+ },
+ {
+ .name = "ipu_di_clk",
+ .id = 1,
},
};
{
u32 *reg;
u32 value;
- int timeout = IPU_SW_RST_TOUT_USEC;
reg = (u32 *)SRC_BASE_ADDR;
value = __raw_readl(reg);
value = value | SW_IPU_RST;
__raw_writel(value, reg);
-
- while (__raw_readl(reg) & SW_IPU_RST) {
- udelay(1);
- if (!(timeout--)) {
- printf("ipu software reset timeout\n");
- break;
- }
- };
}
/*
*
* @return Returns 0 on success or negative error code on error
*/
-int ipu_probe(void)
+int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val)
{
- unsigned long ipu_base;
-#if defined CONFIG_MX51
- u32 temp;
+ int ret;
+ void *ipu_base;
+ unsigned long start;
+#if defined(CONFIG_MXC_HSC)
+ u32 temp;
u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
__raw_writel(0xF00, reg_hsc_mcd);
- /* CSI mode reserved*/
+ /* CSI mode reserved */
temp = __raw_readl(reg_hsc_mxt_conf);
__raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);
temp = __raw_readl(reg_hsc_mxt_conf);
__raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
#endif
-
- ipu_base = IPU_CTRL_BASE_ADDR;
- ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE);
- ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE);
+ ipu_base = (void *)IPU_CTRL_BASE_ADDR;
+ /* base fixup */
+ if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3H) /* IPUv3H */
+ ipu_base += IPUV3H_REG_BASE;
+ else if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3M) /* IPUv3M */
+ ipu_base += IPUV3M_REG_BASE;
+ else /* IPUv3D, v3E, v3EX */
+ ipu_base += IPUV3DEX_REG_BASE;
+ ipu_cpmem_base = ipu_base + IPU_CPMEM_REG_BASE;
+ ipu_dc_tmpl_reg = ipu_base + IPU_DC_TMPL_REG_BASE;
+
+ printf("IPU HW Rev: %d\n", gd->arch.ipu_hw_rev);
g_pixel_clk[0] = &pixel_clk[0];
g_pixel_clk[1] = &pixel_clk[1];
+ g_di_clk[0] = &di_clk[0];
+ g_di_clk[1] = &di_clk[1];
+ g_di_clk[di]->rate = di_clk_val;
+
g_ipu_clk = &ipu_clk;
debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
- g_ldb_clk = &ldb_clk;
- debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
- ipu_reset();
- clk_set_parent(g_pixel_clk[0], g_ipu_clk);
- clk_set_parent(g_pixel_clk[1], g_ipu_clk);
- clk_enable(g_ipu_clk);
+ ret = clk_enable(g_ipu_clk);
+ if (ret)
+ return ret;
+ ipu_reset();
- g_di_clk[0] = NULL;
- g_di_clk[1] = NULL;
+ if (di_clk_parent == DI_PCLK_LDB) {
+ clk_set_parent(g_pixel_clk[di], g_di_clk[di]);
+ } else {
+ clk_set_parent(g_pixel_clk[0], g_ipu_clk);
+ clk_set_parent(g_pixel_clk[1], g_ipu_clk);
+ }
__raw_writel(0x807FFFFF, IPU_MEM_RST);
- while (__raw_readl(IPU_MEM_RST) & 0x80000000)
- ;
+ start = get_timer_masked();
+ while (__raw_readl(IPU_MEM_RST) & 0x80000000) {
+ if (get_timer(start) > CONFIG_SYS_HZ)
+ return -ETIME;
+ }
ipu_init_dc_mappings();
void ipu_dump_registers(void)
{
- debug("IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF));
- debug("IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF));
- debug("IDMAC_CHA_EN1 = \t0x%08X\n",
+ debug("IPU_CONF 0x%08X\n", __raw_readl(IPU_CONF));
+ debug("IDMAC_CONF 0x%08X\n", __raw_readl(IDMAC_CONF));
+ debug("IDMAC_CHA_EN1 0x%08X\n",
__raw_readl(IDMAC_CHA_EN(0)));
- debug("IDMAC_CHA_EN2 = \t0x%08X\n",
+ debug("IDMAC_CHA_EN2 0x%08X\n",
__raw_readl(IDMAC_CHA_EN(32)));
- debug("IDMAC_CHA_PRI1 = \t0x%08X\n",
+ debug("IDMAC_CHA_PRI1 0x%08X\n",
__raw_readl(IDMAC_CHA_PRI(0)));
- debug("IDMAC_CHA_PRI2 = \t0x%08X\n",
+ debug("IDMAC_CHA_PRI2 0x%08X\n",
__raw_readl(IDMAC_CHA_PRI(32)));
- debug("IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
+ debug("IPU_CHA_DB_MODE_SEL0 0x%08X\n",
__raw_readl(IPU_CHA_DB_MODE_SEL(0)));
- debug("IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
+ debug("IPU_CHA_DB_MODE_SEL1 0x%08X\n",
__raw_readl(IPU_CHA_DB_MODE_SEL(32)));
- debug("DMFC_WR_CHAN = \t0x%08X\n",
+ debug("DMFC_WR_CHAN 0x%08X\n",
__raw_readl(DMFC_WR_CHAN));
- debug("DMFC_WR_CHAN_DEF = \t0x%08X\n",
+ debug("DMFC_WR_CHAN_DEF 0x%08X\n",
__raw_readl(DMFC_WR_CHAN_DEF));
- debug("DMFC_DP_CHAN = \t0x%08X\n",
+ debug("DMFC_DP_CHAN 0x%08X\n",
__raw_readl(DMFC_DP_CHAN));
- debug("DMFC_DP_CHAN_DEF = \t0x%08X\n",
+ debug("DMFC_DP_CHAN_DEF 0x%08X\n",
__raw_readl(DMFC_DP_CHAN_DEF));
- debug("DMFC_IC_CTRL = \t0x%08X\n",
+ debug("DMFC_IC_CTRL 0x%08X\n",
__raw_readl(DMFC_IC_CTRL));
- debug("IPU_FS_PROC_FLOW1 = \t0x%08X\n",
+ debug("IPU_FS_PROC_FLOW1 0x%08X\n",
__raw_readl(IPU_FS_PROC_FLOW1));
- debug("IPU_FS_PROC_FLOW2 = \t0x%08X\n",
+ debug("IPU_FS_PROC_FLOW2 0x%08X\n",
__raw_readl(IPU_FS_PROC_FLOW2));
- debug("IPU_FS_PROC_FLOW3 = \t0x%08X\n",
+ debug("IPU_FS_PROC_FLOW3 0x%08X\n",
__raw_readl(IPU_FS_PROC_FLOW3));
- debug("IPU_FS_DISP_FLOW1 = \t0x%08X\n",
+ debug("IPU_FS_DISP_FLOW1 0x%08X\n",
__raw_readl(IPU_FS_DISP_FLOW1));
}
break;
default:
printf("Missing channel initialization\n");
- break;
}
/* Enable IPU sub module */
if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
idma_is_set(IDMAC_CHA_EN, out_dma)) {
- printf(
- "Channel %d is not disabled, disable first\n",
+ printf("Channel %d is not disabled, disable first\n",
IPU_CHAN_ID(channel));
return;
}
{
#ifdef DEBUG
struct ipu_ch_param *p = ipu_ch_param_addr(ch);
- debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
+ printf("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
p->word[0].data[3], p->word[0].data[4]);
- debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
+ printf("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
p->word[1].data[3], p->word[1].data[4]);
- debug("PFS 0x%x, ",
+ printf("PFS 0x%x, ",
ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));
- debug("BPP 0x%x, ",
+ printf("BPP 0x%x, ",
ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));
- debug("NPB 0x%x\n",
+ printf("NPB 0x%x\n",
ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));
- debug("FW %d, ",
+ printf("FW %d, ",
ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));
- debug("FH %d, ",
+ printf("FH %d, ",
ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));
- debug("Stride %d\n",
+ printf("Stride %d\n",
ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));
- debug("Width0 %d+1, ",
+ printf("Width0 %d+1, ",
ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));
- debug("Width1 %d+1, ",
+ printf("Width1 %d+1, ",
ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));
- debug("Width2 %d+1, ",
+ printf("Width2 %d+1, ",
ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));
- debug("Width3 %d+1, ",
+ printf("Width3 %d+1, ",
ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));
- debug("Offset0 %d, ",
+ printf("Offset0 %d, ",
ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));
- debug("Offset1 %d, ",
+ printf("Offset1 %d, ",
ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));
- debug("Offset2 %d, ",
+ printf("Offset2 %d, ",
ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));
- debug("Offset3 %d\n",
+ printf("Offset3 %d\n",
ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));
#endif
}
{
uint32_t u_offset = 0;
uint32_t v_offset = 0;
- struct ipu_ch_param params;
-
- memset(¶ms, 0, sizeof(params));
- ipu_ch_param_set_field(¶ms, 0, 125, 13, width - 1);
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 125, 13, width - 1);
if ((ch == 8) || (ch == 9) || (ch == 10)) {
- ipu_ch_param_set_field(¶ms, 0, 138, 12, (height / 2) - 1);
- ipu_ch_param_set_field(¶ms, 1, 102, 14, (stride * 2) - 1);
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, (height / 2) - 1);
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, (stride * 2) - 1);
} else {
- ipu_ch_param_set_field(¶ms, 0, 138, 12, height - 1);
- ipu_ch_param_set_field(¶ms, 1, 102, 14, stride - 1);
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, height - 1);
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, stride - 1);
}
- ipu_ch_param_set_field(¶ms, 1, 0, 29, addr0 >> 3);
- ipu_ch_param_set_field(¶ms, 1, 29, 29, addr1 >> 3);
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 0, 29, addr0 >> 3);
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 29, 29, addr1 >> 3);
switch (pixel_fmt) {
case IPU_PIX_FMT_GENERIC:
/*Represents 8-bit Generic data */
- ipu_ch_param_set_field(¶ms, 0, 107, 3, 5); /* bits/pixel */
- ipu_ch_param_set_field(¶ms, 1, 85, 4, 6); /* pix format */
- ipu_ch_param_set_field(¶ms, 1, 78, 7, 63); /* burst size */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 5); /* bits/pixel */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 6); /* pix format */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 63); /* burst size */
break;
case IPU_PIX_FMT_GENERIC_32:
/*Represents 32-bit Generic data */
break;
case IPU_PIX_FMT_RGB565:
- ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */
- ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
- ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3); /* bits/pixel */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); /* burst size */
- ipu_ch_params_set_packing(¶ms, 5, 0, 6, 5, 5, 11, 8, 16);
+ ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 5, 0, 6, 5, 5, 11, 8, 16);
break;
case IPU_PIX_FMT_BGR24:
- ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */
- ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
- ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1); /* bits/pixel */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19); /* burst size */
- ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24);
+ ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
break;
case IPU_PIX_FMT_RGB24:
case IPU_PIX_FMT_YUV444:
- ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */
- ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
- ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1); /* bits/pixel */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19); /* burst size */
- ipu_ch_params_set_packing(¶ms, 8, 16, 8, 8, 8, 0, 8, 24);
+ ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 16, 8, 8, 8, 0, 8, 24);
break;
case IPU_PIX_FMT_BGRA32:
case IPU_PIX_FMT_BGR32:
- ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */
- ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
- ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0); /* bits/pixel */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); /* burst size */
- ipu_ch_params_set_packing(¶ms, 8, 8, 8, 16, 8, 24, 8, 0);
+ ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 8, 8, 16, 8, 24, 8, 0);
break;
case IPU_PIX_FMT_RGBA32:
case IPU_PIX_FMT_RGB32:
- ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */
- ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
- ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0); /* bits/pixel */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); /* burst size */
- ipu_ch_params_set_packing(¶ms, 8, 24, 8, 16, 8, 8, 8, 0);
+ ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 24, 8, 16, 8, 8, 8, 0);
break;
case IPU_PIX_FMT_ABGR32:
- ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */
- ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0); /* bits/pixel */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7); /* pix format */
- ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24);
+ ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
break;
case IPU_PIX_FMT_UYVY:
- ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */
- ipu_ch_param_set_field(¶ms, 1, 85, 4, 0xA); /* pix format */
- ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3); /* bits/pixel */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0xA); /* pix format */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15); /* burst size */
break;
case IPU_PIX_FMT_YUYV:
- ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */
- ipu_ch_param_set_field(¶ms, 1, 85, 4, 0x8); /* pix format */
- ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3); /* bits/pixel */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0x8); /* pix format */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); /* burst size */
break;
case IPU_PIX_FMT_YUV420P2:
case IPU_PIX_FMT_YUV420P:
- ipu_ch_param_set_field(¶ms, 1, 85, 4, 2); /* pix format */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 2); /* pix format */
if (uv_stride < stride / 2)
uv_stride = stride / 2;
v_offset = u_offset + (uv_stride * height / 2);
/* burst size */
if ((ch == 8) || (ch == 9) || (ch == 10)) {
- ipu_ch_param_set_field(¶ms, 1, 78, 7, 15);
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);
uv_stride = uv_stride*2;
} else {
- ipu_ch_param_set_field(¶ms, 1, 78, 7, 31);
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);
}
break;
case IPU_PIX_FMT_YVU422P:
/* BPP & pixel format */
- ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */
- ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1); /* pix format */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); /* burst size */
if (uv_stride < stride / 2)
uv_stride = stride / 2;
break;
case IPU_PIX_FMT_YUV422P:
/* BPP & pixel format */
- ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */
- ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1); /* pix format */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); /* burst size */
if (uv_stride < stride / 2)
uv_stride = stride / 2;
break;
case IPU_PIX_FMT_NV12:
/* BPP & pixel format */
- ipu_ch_param_set_field(¶ms, 1, 85, 4, 4); /* pix format */
- ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 4); /* pix format */
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31); /* burst size */
uv_stride = stride;
u_offset = (u == 0) ? stride * height : u;
break;
default:
- puts("mxc ipu: unimplemented pixel format\n");
- break;
+ printf("mxc ipu: unimplemented pixel format: %08x\n",
+ pixel_fmt);
}
if (uv_stride)
- ipu_ch_param_set_field(¶ms, 1, 128, 14, uv_stride - 1);
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 128, 14, uv_stride - 1);
/* Get the uv offset from user when need cropping */
if (u || v) {
if (v_offset/8 > 0x3fffff)
puts("The value of V offset exceeds IPU limitation\n");
- ipu_ch_param_set_field(¶ms, 0, 46, 22, u_offset / 8);
- ipu_ch_param_set_field(¶ms, 0, 68, 22, v_offset / 8);
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 46, 22, u_offset / 8);
+ ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 68, 22, v_offset / 8);
debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
- memcpy(ipu_ch_param_addr(ch), ¶ms, sizeof(params));
};
/*
stride = width * bytes_per_pixel(pixel_fmt);
if (stride % 4) {
- printf(
- "Stride not 32-bit aligned, stride = %d\n", stride);
+ printf("Stride %d not 32-bit aligned\n", stride);
return -EINVAL;
}
/* Build parameter memory data for DMA channel */
}
if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
- (channel == MEM_FG_SYNC))
+ (channel == MEM_FG_SYNC)) {
+ reg = __raw_readl(IDMAC_WM_EN(in_dma));
+ __raw_writel(reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
+
ipu_dp_dc_enable(channel);
+ }
g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
case IPU_PIX_FMT_YUV420P:
case IPU_PIX_FMT_YUV422P:
return 1;
- break;
case IPU_PIX_FMT_RGB565:
case IPU_PIX_FMT_YUYV:
case IPU_PIX_FMT_UYVY:
return 2;
- break;
case IPU_PIX_FMT_BGR24:
case IPU_PIX_FMT_RGB24:
return 3;
- break;
case IPU_PIX_FMT_GENERIC_32: /*generic data */
case IPU_PIX_FMT_BGR32:
case IPU_PIX_FMT_BGRA32:
case IPU_PIX_FMT_RGBA32:
case IPU_PIX_FMT_ABGR32:
return 4;
- break;
default:
return 1;
- break;
}
return 0;
}
case IPU_PIX_FMT_LVDS666:
case IPU_PIX_FMT_LVDS888:
return RGB;
- break;
default:
return YCbCr;
- break;
}
return RGB;
}
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de
*
- * Linux IPU driver for MX51:
+ * Linux IPU driver
*
- * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
+ * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
/* #define DEBUG */
#include <common.h>
+#include <ipu.h>
#include <linux/types.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-#include "ipu.h"
+
#include "ipu_regs.h"
enum csc_type_t {
#define DC_DISP_ID_SERIAL 2
#define DC_DISP_ID_ASYNC 3
-int dmfc_type_setup;
+static int dmfc_type_setup;
static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23;
-int g_di1_tvout;
+static int g_di1_tvout;
+#if 0
extern struct clk *g_ipu_clk;
-extern struct clk *g_ldb_clk;
extern struct clk *g_di_clk[2];
extern struct clk *g_pixel_clk[2];
extern unsigned char g_ipu_clk_enabled;
extern unsigned char g_dc_di_assignment[];
+#endif
void ipu_dmfc_init(int dmfc_type, int first)
{
/* IPU_PIX_FMT_LVDS666 */
ipu_dc_map_clear(4);
ipu_dc_map_config(4, 0, 5, 0xFC);
- ipu_dc_map_config(4, 1, 13, 0xFC);
- ipu_dc_map_config(4, 2, 21, 0xFC);
+ ipu_dc_map_config(4, 1, 11, 0xFC);
+ ipu_dc_map_config(4, 2, 17, 0xFC);
}
int ipu_pixfmt_to_map(uint32_t fmt)
switch (fmt) {
case IPU_PIX_FMT_GENERIC:
case IPU_PIX_FMT_RGB24:
+ case IPU_PIX_FMT_LVDS888:
return 0;
case IPU_PIX_FMT_RGB666:
return 1;
* fail.
*/
-int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
- uint16_t width, uint16_t height,
- uint32_t pixel_fmt,
- uint16_t h_start_width, uint16_t h_sync_width,
- uint16_t h_end_width, uint16_t v_start_width,
- uint16_t v_sync_width, uint16_t v_end_width,
- uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
+int ipu_init_sync_panel(int disp, uint32_t pixel_clk,
+ uint16_t width, uint16_t height,
+ uint32_t pixel_fmt,
+ uint16_t h_start_width, uint16_t h_sync_width,
+ uint16_t h_end_width, uint16_t v_start_width,
+ uint16_t v_sync_width, uint16_t v_end_width,
+ uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
{
uint32_t reg;
uint32_t di_gen, vsync_cnt;
debug("pixel clk = %d\n", pixel_clk);
if (sig.ext_clk) {
- if (!(g_di1_tvout && (disp == 1))) { /*not round div for tvout*/
+ if (!(g_di1_tvout && (disp == 1))) { /* don't round div for tvout */
/*
* Set the PLL to be an even multiple
* of the pixel clock.
rounded_pixel_clk =
clk_round_rate(g_pixel_clk[disp],
pixel_clk);
- div = clk_get_rate(di_parent) /
- rounded_pixel_clk;
- if (div % 2)
- div++;
- if (clk_get_rate(di_parent) != div *
- rounded_pixel_clk)
- clk_set_rate(di_parent,
- div * rounded_pixel_clk);
- udelay(10000);
- clk_set_rate(g_di_clk[disp],
- 2 * rounded_pixel_clk);
- udelay(10000);
+ if (di_parent != NULL) {
+ div = clk_get_rate(di_parent) /
+ rounded_pixel_clk;
+ if (div % 2)
+ div++;
+ if (clk_get_rate(di_parent) != div *
+ rounded_pixel_clk)
+ clk_set_rate(di_parent,
+ div * rounded_pixel_clk);
+ udelay(10000);
+ clk_set_rate(g_di_clk[disp],
+ 2 * rounded_pixel_clk);
+ udelay(10000);
+ }
}
}
- clk_set_parent(g_pixel_clk[disp], g_ldb_clk);
+ clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]);
} else {
if (clk_get_usecount(g_pixel_clk[disp]) != 0)
clk_set_parent(g_pixel_clk[disp], g_ipu_clk);
div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) /
rounded_pixel_clk;
- ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1);
+ /* Enable for a divide by 2 clock change. */
+ reg = __raw_readl(IPU_PM);
+ reg &= ~(0x7f << 7);
+ reg |= 0x20 << 7;
+ reg &= ~(0x7f << 23);
+ reg |= 0x20 << 23;
+ __raw_writel(reg, IPU_PM);
+
+ di_gen = 0;
+
+ if (pixel_fmt != IPU_PIX_FMT_LVDS666 &&
+ pixel_fmt != IPU_PIX_FMT_LVDS888) {
+ clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
+ udelay(5000);
+ /* Get integer portion of divider */
+ div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) /
+ rounded_pixel_clk;
+ ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1);
+ } else {
+ clk_set_rate(g_pixel_clk[disp], clk_get_rate(g_ipu_clk));
+ div = 1;
+ ipu_di_data_wave_config(disp, SYNC_WAVE, 0, 0);
+ di_gen |= (6 << 24);
+ di_gen |= DI_GEN_DI_CLK_EXT;
+ }
ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
map = ipu_pixfmt_to_map(pixel_fmt);
return -EINVAL;
}
- di_gen = __raw_readl(DI_GENERAL(disp));
-
if (sig.interlaced) {
/* Setup internal HSYNC waveform */
ipu_di_sync_config(
/* set gentime select and tag sel */
reg = __raw_readl(DI_SW_GEN1(disp, 9));
reg &= 0x1FFFFFFF;
- reg |= (3 - 1)<<29 | 0x00008000;
+ reg |= ((3 - 1) << 29) | 0x00008000;
__raw_writel(reg, DI_SW_GEN1(disp, 9));
__raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp));
__raw_writel(0, DI_STP_REP(disp, 7));
__raw_writel(0, DI_STP_REP(disp, 9));
+ h_total = ((width + h_start_width + h_sync_width) / 2) - 2;
+ ipu_di_sync_config(disp, 6, 1, 0, 2, DI_SYNC_CLK, h_total,
+ DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE,
+ DI_SYNC_NONE, 0, 0);
+
/* Init template microcode */
if (disp) {
- ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5);
- ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5);
- ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5);
+ ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5);
+ ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5);
+ ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5);
} else {
- ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5);
- ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5);
- ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5);
+ ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5);
+ ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5);
+ ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5);
}
if (sig.Hsync_pol)
if (sig.clk_pol)
di_gen |= DI_GEN_POL_CLK;
+ /* Set the clock to stop at counter 6. */
+ di_gen |= 0x6000000;
}
__raw_writel(di_gen, DI_GENERAL(disp));
- __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
- 0x00000002, DI_SYNC_AS_GEN(disp));
+ if (sig.interlaced)
+ __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
+ 0x00000002, DI_SYNC_AS_GEN(disp));
+ else
+ __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET),
+ DI_SYNC_AS_GEN(disp));
reg = __raw_readl(DI_POL(disp));
reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
*
* @return Returns 0 on success or negative error code on fail
*/
-int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
+int ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
uint8_t alpha)
{
+ int ret;
uint32_t reg;
unsigned char bg_chan;
else
bg_chan = 0;
- if (!g_ipu_clk_enabled)
- clk_enable(g_ipu_clk);
+ ret = clk_enable(g_ipu_clk);
+ if (ret)
+ return ret;
if (bg_chan) {
reg = __raw_readl(DP_COM_CONF());
reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
__raw_writel(reg, IPU_SRM_PRI2);
- if (!g_ipu_clk_enabled)
- clk_disable(g_ipu_clk);
+ clk_disable(g_ipu_clk);
return 0;
}
*
* @return Returns 0 on success or negative error code on fail
*/
-int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
+int ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
uint32_t color_key)
{
+ int ret;
uint32_t reg;
int y, u, v;
int red, green, blue;
(channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
return -EINVAL;
- if (!g_ipu_clk_enabled)
- clk_enable(g_ipu_clk);
+ ret = clk_enable(g_ipu_clk);
+ if (ret)
+ return ret;
color_key_4rgb = 1;
/* Transform color key from rgb to yuv if CSC is enabled */
reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
__raw_writel(reg, IPU_SRM_PRI2);
- if (!g_ipu_clk_enabled)
- clk_disable(g_ipu_clk);
+ clk_disable(g_ipu_clk);
return 0;
}
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de
*
- * Linux IPU driver for MX51:
+ * Linux IPU driver:
*
- * (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
+ * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#define IPU_DISP0_BASE 0x00000000
#define IPU_MCU_T_DEFAULT 8
-#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25)
+#define IPU_DISP1_BASE (gd->arch.ipu_hw_rev < IPUV3_HW_REV_IPUV3H ? \
+ (IPU_MCU_T_DEFAULT << 25) : \
+ 0x00000000)
+
+#define IPUV3DEX_REG_BASE 0x1E000000
+#define IPUV3M_REG_BASE 0x1E000000
+#define IPUV3H_REG_BASE 0x00200000
+
#define IPU_CM_REG_BASE 0x00000000
#define IPU_STAT_REG_BASE 0x00000200
#define IPU_IDMAC_REG_BASE 0x00008000
#define IPU_SMFC_REG_BASE 0x00050000
#define IPU_DC_REG_BASE 0x00058000
#define IPU_DMFC_REG_BASE 0x00060000
-#define IPU_VDI_REG_BASE 0x00680000
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
-#define IPU_CPMEM_REG_BASE 0x01000000
-#define IPU_LUT_REG_BASE 0x01020000
-#define IPU_SRM_REG_BASE 0x01040000
-#define IPU_TPM_REG_BASE 0x01060000
-#define IPU_DC_TMPL_REG_BASE 0x01080000
-#define IPU_ISP_TBPR_REG_BASE 0x010C0000
-#elif defined(CONFIG_MX6)
-#define IPU_CPMEM_REG_BASE 0x00100000
-#define IPU_LUT_REG_BASE 0x00120000
-#define IPU_SRM_REG_BASE 0x00140000
-#define IPU_TPM_REG_BASE 0x00160000
-#define IPU_DC_TMPL_REG_BASE 0x00180000
-#define IPU_ISP_TBPR_REG_BASE 0x001C0000
-#endif
-
-#define IPU_CTRL_BASE_ADDR (IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET)
+#define IPU_VDI_REG_BASE 0x00068000
+#define IPU_CPMEM_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \
+ 0x00100000 : \
+ 0x01000000)
+#define IPU_LUT_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \
+ 0x00120000 : \
+ 0x01020000)
+#define IPU_SRM_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \
+ 0x00140000 : \
+ 0x01040000)
+#define IPU_TPM_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \
+ 0x00160000 : \
+ 0x01060000)
+#define IPU_DC_TMPL_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \
+ 0x00180000 : \
+ 0x01080000)
+#define IPU_ISP_TBPR_REG_BASE (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \
+ 0x001C0000 : \
+ 0x010C0000)
+
+#define IPU_DISP_REG_BASE_ADDR (gd->arch.ipu_hw_rev >= IPUV3_HW_REV_IPUV3H ? \
+ IPU_CTRL_BASE_ADDR + IPUV3H_REG_BASE : \
+ IPU_CTRL_BASE_ADDR + IPUV3M_REG_BASE)
extern u32 *ipu_dc_tmpl_reg;
+extern struct clk *g_ipu_clk;
+extern struct clk *g_di_clk[2];
+extern struct clk *g_pixel_clk[2];
+
+extern int g_ipu_clk_enabled;
+extern unsigned char g_dc_di_assignment[];
#define DC_EVT_NF 0
#define DC_EVT_NL 1
DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
- DI_GEN_DI_CLK_EXT = 0x100000,
+ DI_GEN_DI_CLK_EXT = 0x00100000,
DI_GEN_POLARITY_1 = 0x00000001,
DI_GEN_POLARITY_2 = 0x00000002,
DI_GEN_POLARITY_3 = 0x00000004,
DI_GEN_POLARITY_6 = 0x00000020,
DI_GEN_POLARITY_7 = 0x00000040,
DI_GEN_POLARITY_8 = 0x00000080,
- DI_GEN_POL_CLK = 0x20000,
+ DI_GEN_POL_CLK = 0x00020000,
DI_POL_DRDY_DATA_POLARITY = 0x00000080,
DI_POL_DRDY_POLARITY_15 = 0x00000010,
u32 stat;
};
-#define IPU_CM_REG ((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \
+#define IPU_CM_REG ((struct ipu_cm *)(IPU_DISP_REG_BASE_ADDR + \
IPU_CM_REG_BASE))
#define IPU_CONF (&IPU_CM_REG->conf)
#define IPU_SRM_PRI1 (&IPU_CM_REG->srm_pri1)
#define IPU_FS_DISP_FLOW1 (&IPU_CM_REG->fs_disp_flow[0])
#define IPU_DISP_GEN (&IPU_CM_REG->disp_gen)
#define IPU_MEM_RST (&IPU_CM_REG->mem_rst)
+#define IPU_PM (&IPU_CM_REG->pm)
#define IPU_GPR (&IPU_CM_REG->gpr)
-#define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32])
+#define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[(ch) / 32])
-#define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \
+#define IPU_STAT ((struct ipu_stat *)(IPU_DISP_REG_BASE_ADDR + \
IPU_STAT_REG_BASE))
-#define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32])
-#define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32])
-#define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32])
+#define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[(ch) / 32])
+#define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[(ch) / 32])
+#define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[(ch) / 32])
#define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1])
-#define IDMAC_REG ((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \
+#define IDMAC_REG ((struct ipu_idmac *)(IPU_DISP_REG_BASE_ADDR + \
IPU_IDMAC_REG_BASE))
#define IDMAC_CONF (&IDMAC_REG->conf)
-#define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[ch / 32])
-#define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[ch / 32])
+#define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[(ch) / 32])
+#define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[(ch) / 32])
+#define IDMAC_WM_EN(ch) (&IDMAC_REG->wm_en[(ch) / 32])
+
+#define DI_REG(di) ((struct ipu_di *)(IPU_DISP_REG_BASE_ADDR + \
+ (((di) == 1) ? IPU_DI1_REG_BASE : \
+ IPU_DI0_REG_BASE)))
-#define DI_REG(di) ((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \
- ((di == 1) ? IPU_DI1_REG_BASE : \
- IPU_DI0_REG_BASE)))
#define DI_GENERAL(di) (&DI_REG(di)->general)
#define DI_BS_CLKGEN0(di) (&DI_REG(di)->bs_clkgen0)
#define DI_BS_CLKGEN1(di) (&DI_REG(di)->bs_clkgen1)
-#define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1])
-#define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1])
-#define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2])
+#define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[(gen) - 1])
+#define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[(gen) - 1])
+#define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[((gen) - 1) / 2])
#define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as)
#define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen])
-#define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set])
+#define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[(gen) + 12 * set])
#define DI_POL(di) (&DI_REG(di)->pol)
#define DI_SCR_CONF(di) (&DI_REG(di)->scr_conf)
-#define DMFC_REG ((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \
+#define DMFC_REG ((struct ipu_dmfc *)(IPU_DISP_REG_BASE_ADDR + \
IPU_DMFC_REG_BASE))
#define DMFC_WR_CHAN (&DMFC_REG->wr_chan)
#define DMFC_WR_CHAN_DEF (&DMFC_REG->wr_chan_def)
#define DMFC_GENERAL1 (&DMFC_REG->general[0])
#define DMFC_IC_CTRL (&DMFC_REG->ic_ctrl)
-
-#define DC_REG ((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \
+#define DC_REG ((struct ipu_dc *)(IPU_DISP_REG_BASE_ADDR + \
IPU_DC_REG_BASE))
-#define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[n / 2])
-#define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[n / 2])
+#define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[(n) / 2])
+#define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[(n) / 2])
+DECLARE_GLOBAL_DATA_PTR;
static inline struct ipu_dc_ch *dc_ch_offset(int ch)
{
printf("%s: invalid channel %d\n", __func__, ch);
return NULL;
}
-
}
-#define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[evt / 2])
+#define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[(evt) / 2])
#define DC_WR_CH_CONF(ch) (&dc_ch_offset(ch)->wr_ch_conf)
#define DC_WR_CH_ADDR(ch) (&dc_ch_offset(ch)->wr_ch_addr)
#define DP_ASYNC0 0x60
#define DP_ASYNC1 0xBC
-#define DP_REG ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \
+#define DP_REG ((struct ipu_dp *)(IPU_DISP_REG_BASE_ADDR + \
IPU_DP_REG_BASE))
#define DP_COM_CONF() (&DP_REG->com_conf_sync)
#define DP_GRAPH_WIND_CTRL() (&DP_REG->graph_wind_ctrl_sync)
#define DP_CSC_1() (&DP_REG->csc_sync[1])
/* DC template opcodes */
-#define WROD(lf) (0x18 | (lf << 1))
+#define WROD(lf) (0x18 | ((lf) << 1))
#endif
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53-EVK Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <asm/arch/mx25-regs.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/errno.h>
+#include <mx2fb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void *lcd_base; /* Start of framebuffer memory */
+void *lcd_console_address; /* Start of console buffer */
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+
+short console_col;
+short console_row;
+
+
+void lcd_initcolregs(void)
+{
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+
+void lcd_enable(void)
+{
+}
+
+void lcd_disable(void)
+{
+}
+
+void lcd_panel_disable(void)
+{
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ u32 ccm_ipg_cg, pcr;
+
+ /* LSSAR */
+ writel(gd->fb_base, LCDC_BASE + 0x00);
+ /* LSR = x << 20 + y */
+ writel(((panel_info.vl_col >> 4) << 20) + panel_info.vl_row,
+ LCDC_BASE + 0x04);
+ /* LVPWR = x_res * 2 / 2 */
+ writel(panel_info.vl_col / 2, LCDC_BASE + 0x08);
+ /* LPCR = To be fixed using Linux BSP Value for now */
+ switch (panel_info.vl_bpix) {
+ /* bpix = 4 (16bpp) */
+ case 4:
+ pcr = LCDC_LPCR | (0x5 << 25);
+ break;
+ default:
+ pcr = LCDC_LPCR;
+ break;
+ }
+
+ pcr |= (panel_info.vl_sync & FB_SYNC_CLK_LAT_FALL) ? 0x00200000 : 0;
+ pcr |= (panel_info.vl_sync & FB_SYNC_DATA_INVERT) ? 0x01000000 : 0;
+ pcr |= (panel_info.vl_sync & FB_SYNC_SHARP_MODE) ? 0x00000040 : 0;
+ pcr |= (panel_info.vl_sync & FB_SYNC_OE_LOW_ACT) ? 0x00100000 : 0;
+
+ pcr |= LCDC_LPCR_PCD;
+
+ writel(pcr, LCDC_BASE + 0x18);
+ /* LHCR = H Pulse width, Right and Left Margins */
+ writel(((panel_info.vl_hsync - 1) << 26) + \
+ ((panel_info.vl_right_margin - 1) << 8) + \
+ (panel_info.vl_left_margin - 3),
+ LCDC_BASE + 0x1c);
+ /* LVCR = V Pulse width, lower and upper margins */
+ writel((panel_info.vl_vsync << 26) + \
+ (panel_info.vl_lower_margin << 8) + \
+ (panel_info.vl_upper_margin),
+ LCDC_BASE + 0x20);
+ /* LSCR */
+ writel(LCDC_LSCR, LCDC_BASE + 0x28);
+ /* LRMCR */
+ writel(LCDC_LRMCR, LCDC_BASE + 0x34);
+ /* LDCR */
+ writel(LCDC_LDCR, LCDC_BASE + 0x30);
+ /* LPCCR = PWM */
+ writel(LCDC_LPCCR, LCDC_BASE + 0x2c);
+
+ /* On and off clock gating */
+ ccm_ipg_cg = readl(CCM_BASE + 0x10);
+
+ writel(ccm_ipg_cg&0xDFFFFFFF, CCM_BASE + 0x10);
+ writel(ccm_ipg_cg|0x20000000, CCM_BASE + 0x10);
+}
+
+ulong calc_fbsize(void)
+{
+ return panel_info.vl_row * panel_info.vl_col * 2 \
+ * NBITS(panel_info.vl_bpix) / 8;
+}
+
+
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+/*
+ * Based on STMP378X LCDIF
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <linux/list.h>
+#include <linux/err.h>
+#include <linux/types.h>
+#include <asm/arch/mx50.h>
+
+#include "mxc_epdc_fb.h"
+
+
+extern int setup_waveform_file();
+extern void epdc_power_on();
+extern void epdc_power_off();
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void *lcd_base; /* Start of framebuffer memory */
+void *lcd_console_address; /* Start of console buffer */
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+
+short console_col;
+short console_row;
+
+void lcd_initcolregs(void)
+{
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+
+#define TEMP_USE_DEFAULT 8
+
+#define UPDATE_MODE_PARTIAL 0x0
+#define UPDATE_MODE_FULL 0x1
+
+#define TRUE 1
+#define FALSE 0
+
+#define msleep(a) udelay(a * 1000)
+
+
+/********************************************************
+ * Start Low-Level EPDC Functions
+ ********************************************************/
+
+static inline void epdc_set_screen_res(u32 width, u32 height)
+{
+ u32 val = (height << EPDC_RES_VERTICAL_OFFSET) | width;
+
+ REG_WR(EPDC_BASE, EPDC_RES, val);
+}
+
+static inline void epdc_set_update_coord(u32 x, u32 y)
+{
+ u32 val = (y << EPDC_UPD_CORD_YCORD_OFFSET) | x;
+
+ REG_WR(EPDC_BASE, EPDC_UPD_CORD, val);
+}
+
+static inline void epdc_set_update_dimensions(u32 width, u32 height)
+{
+ u32 val = (height << EPDC_UPD_SIZE_HEIGHT_OFFSET) | width;
+
+ REG_WR(EPDC_BASE, EPDC_UPD_SIZE, val);
+}
+
+static void epdc_submit_update(u32 lut_num, u32 waveform_mode, u32 update_mode,
+ int use_test_mode, u32 np_val)
+{
+ u32 reg_val = 0;
+
+ if (use_test_mode) {
+ reg_val |=
+ ((np_val << EPDC_UPD_FIXED_FIXNP_OFFSET) &
+ EPDC_UPD_FIXED_FIXNP_MASK) | EPDC_UPD_FIXED_FIXNP_EN;
+
+ REG_WR(EPDC_BASE, EPDC_UPD_FIXED, reg_val);
+
+ reg_val = EPDC_UPD_CTRL_USE_FIXED;
+ } else {
+ REG_WR(EPDC_BASE, EPDC_UPD_FIXED, reg_val);
+ }
+
+ reg_val |=
+ ((lut_num << EPDC_UPD_CTRL_LUT_SEL_OFFSET) &
+ EPDC_UPD_CTRL_LUT_SEL_MASK) |
+ ((waveform_mode << EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET) &
+ EPDC_UPD_CTRL_WAVEFORM_MODE_MASK) |
+ update_mode;
+
+ REG_WR(EPDC_BASE, EPDC_UPD_CTRL, reg_val);
+}
+
+static inline int epdc_is_lut_active(u32 lut_num)
+{
+ u32 val = REG_RD(EPDC_BASE, EPDC_STATUS_LUTS);
+ int is_active = val & (1 << lut_num) ? TRUE : FALSE;
+
+ return is_active;
+}
+
+static void epdc_set_horizontal_timing(u32 horiz_start, u32 horiz_end,
+ u32 hsync_width, u32 hsync_line_length)
+{
+ u32 reg_val =
+ ((hsync_width << EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET) &
+ EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK)
+ | ((hsync_line_length << EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET) &
+ EPDC_TCE_HSCAN1_LINE_SYNC_MASK);
+ REG_WR(EPDC_BASE, EPDC_TCE_HSCAN1, reg_val);
+
+ reg_val =
+ ((horiz_start << EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET) &
+ EPDC_TCE_HSCAN2_LINE_BEGIN_MASK)
+ | ((horiz_end << EPDC_TCE_HSCAN2_LINE_END_OFFSET) &
+ EPDC_TCE_HSCAN2_LINE_END_MASK);
+ REG_WR(EPDC_BASE, EPDC_TCE_HSCAN2, reg_val);
+}
+
+static void epdc_set_vertical_timing(u32 vert_start, u32 vert_end,
+ u32 vsync_width)
+{
+ u32 reg_val =
+ ((vert_start << EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET) &
+ EPDC_TCE_VSCAN_FRAME_BEGIN_MASK)
+ | ((vert_end << EPDC_TCE_VSCAN_FRAME_END_OFFSET) &
+ EPDC_TCE_VSCAN_FRAME_END_MASK)
+ | ((vsync_width << EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET) &
+ EPDC_TCE_VSCAN_FRAME_SYNC_MASK);
+ REG_WR(EPDC_BASE, EPDC_TCE_VSCAN, reg_val);
+}
+
+static void epdc_init_settings(void)
+{
+ u32 reg_val;
+
+ /* EPDC_CTRL */
+ reg_val = REG_RD(EPDC_BASE, EPDC_CTRL);
+ reg_val &= ~EPDC_CTRL_UPD_DATA_SWIZZLE_MASK;
+ reg_val |= EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP;
+ reg_val &= ~EPDC_CTRL_LUT_DATA_SWIZZLE_MASK;
+ reg_val |= EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP;
+ REG_SET(EPDC_BASE, EPDC_CTRL, reg_val);
+
+ /* EPDC_FORMAT - 2bit TFT and 4bit Buf pixel format */
+ reg_val = EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT
+ | EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N
+ | ((0x0 << EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET) &
+ EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK);
+ REG_WR(EPDC_BASE, EPDC_FORMAT, reg_val);
+
+ /* EPDC_FIFOCTRL (disabled) */
+ reg_val =
+ ((100 << EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET) &
+ EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK)
+ | ((200 << EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET) &
+ EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK)
+ | ((100 << EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET) &
+ EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK);
+ REG_WR(EPDC_BASE, EPDC_FIFOCTRL, reg_val);
+
+ /* EPDC_TEMP - Use default temperature */
+ REG_WR(EPDC_BASE, EPDC_TEMP, TEMP_USE_DEFAULT);
+
+ /* EPDC_RES */
+ epdc_set_screen_res(panel_info.vl_col, panel_info.vl_row);
+
+ /*
+ * EPDC_TCE_CTRL
+ * VSCAN_HOLDOFF = 4
+ * VCOM_MODE = MANUAL
+ * VCOM_VAL = 0
+ * DDR_MODE = DISABLED
+ * LVDS_MODE_CE = DISABLED
+ * LVDS_MODE = DISABLED
+ * DUAL_SCAN = DISABLED
+ * SDDO_WIDTH = 8bit
+ * PIXELS_PER_SDCLK = 4
+ */
+ reg_val =
+ ((4 << EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET) &
+ EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK)
+ | EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4;
+ REG_WR(EPDC_BASE, EPDC_TCE_CTRL, reg_val);
+
+ /* EPDC_TCE_HSCAN */
+ epdc_set_horizontal_timing(panel_info.vl_left_margin,
+ panel_info.vl_right_margin,
+ panel_info.vl_hsync,
+ panel_info.vl_hsync);
+
+ /* EPDC_TCE_VSCAN */
+ epdc_set_vertical_timing(panel_info.vl_upper_margin,
+ panel_info.vl_lower_margin,
+ panel_info.vl_vsync);
+
+ /* EPDC_TCE_OE */
+ reg_val =
+ ((10 << EPDC_TCE_OE_SDOED_WIDTH_OFFSET) &
+ EPDC_TCE_OE_SDOED_WIDTH_MASK)
+ | ((20 << EPDC_TCE_OE_SDOED_DLY_OFFSET) &
+ EPDC_TCE_OE_SDOED_DLY_MASK)
+ | ((10 << EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET) &
+ EPDC_TCE_OE_SDOEZ_WIDTH_MASK)
+ | ((20 << EPDC_TCE_OE_SDOEZ_DLY_OFFSET) &
+ EPDC_TCE_OE_SDOEZ_DLY_MASK);
+ REG_WR(EPDC_BASE, EPDC_TCE_OE, reg_val);
+
+ /* EPDC_TCE_TIMING1 */
+ REG_WR(EPDC_BASE, EPDC_TCE_TIMING1, 0x0);
+
+ /* EPDC_TCE_TIMING2 */
+ reg_val =
+ ((480 << EPDC_TCE_TIMING2_GDCLK_HP_OFFSET) &
+ EPDC_TCE_TIMING2_GDCLK_HP_MASK)
+ | ((20 << EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET) &
+ EPDC_TCE_TIMING2_GDSP_OFFSET_MASK);
+ REG_WR(EPDC_BASE, EPDC_TCE_TIMING2, reg_val);
+
+ /* EPDC_TCE_TIMING3 */
+ reg_val =
+ ((0 << EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET) &
+ EPDC_TCE_TIMING3_GDOE_OFFSET_MASK)
+ | ((1 << EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET) &
+ EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK);
+ REG_WR(EPDC_BASE, EPDC_TCE_TIMING3, reg_val);
+
+ /*
+ * EPDC_TCE_SDCFG
+ * SDCLK_HOLD = 1
+ * SDSHR = 1
+ * NUM_CE = 1
+ * SDDO_REFORMAT = FLIP_PIXELS
+ * SDDO_INVERT = DISABLED
+ * PIXELS_PER_CE = display horizontal resolution
+ */
+ reg_val = EPDC_TCE_SDCFG_SDCLK_HOLD | EPDC_TCE_SDCFG_SDSHR
+ | ((1 << EPDC_TCE_SDCFG_NUM_CE_OFFSET) & EPDC_TCE_SDCFG_NUM_CE_MASK)
+ | EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS
+ | ((panel_info.vl_col << EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET) &
+ EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK);
+ REG_WR(EPDC_BASE, EPDC_TCE_SDCFG, reg_val);
+
+ /*
+ * EPDC_TCE_GDCFG
+ * GDRL = 1
+ * GDOE_MODE = 0;
+ * GDSP_MODE = 0;
+ */
+ reg_val = EPDC_TCE_SDCFG_GDRL;
+ REG_WR(EPDC_BASE, EPDC_TCE_GDCFG, reg_val);
+
+ /*
+ * EPDC_TCE_POLARITY
+ * SDCE_POL = ACTIVE LOW
+ * SDLE_POL = ACTIVE HIGH
+ * SDOE_POL = ACTIVE HIGH
+ * GDOE_POL = ACTIVE HIGH
+ * GDSP_POL = ACTIVE LOW
+ */
+ reg_val = EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH
+ | EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH
+ | EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH;
+ REG_WR(EPDC_BASE, EPDC_TCE_POLARITY, reg_val);
+
+ /* EPDC_IRQ_MASK */
+ REG_WR(EPDC_BASE, EPDC_IRQ_MASK,
+ EPDC_IRQ_TCE_UNDERRUN_IRQ);
+
+ /*
+ * EPDC_GPIO
+ * PWRCOM = ?
+ * PWRCTRL = ?
+ * BDR = ?
+ */
+ reg_val = ((0 << EPDC_GPIO_PWRCTRL_OFFSET) & EPDC_GPIO_PWRCTRL_MASK)
+ | ((0 << EPDC_GPIO_BDR_OFFSET) & EPDC_GPIO_BDR_MASK);
+ REG_WR(EPDC_BASE, EPDC_GPIO, reg_val);
+}
+
+static void draw_mode0(void)
+{
+ int i;
+
+ /* Program EPDC update to process buffer */
+ epdc_set_update_coord(0, 0);
+ epdc_set_update_dimensions(panel_info.vl_col, panel_info.vl_row);
+ epdc_submit_update(0, panel_info.epdc_data.wv_modes.mode_init,
+ UPDATE_MODE_FULL, FALSE, 0);
+
+ debug("Mode0 update - Waiting for LUT to complete...\n");
+
+ /* Will timeout after ~4-5 seconds */
+
+ for (i = 0; i < 40; i++) {
+ if (!epdc_is_lut_active(0)) {
+ debug("Mode0 init complete\n");
+ return;
+ }
+ msleep(100);
+ }
+
+ debug("Mode0 init failed!\n");
+
+}
+
+static void draw_splash_screen(void)
+{
+ int i;
+ int lut_num = 0;
+
+ /* Program EPDC update to process buffer */
+ epdc_set_update_coord(0, 0);
+ epdc_set_update_dimensions(panel_info.vl_col, panel_info.vl_row);
+ epdc_submit_update(lut_num, panel_info.epdc_data.wv_modes.mode_gc16,
+ UPDATE_MODE_FULL, FALSE, 0);
+
+ for (i = 0; i < 40; i++) {
+ if (!epdc_is_lut_active(lut_num)) {
+ debug("Splash screen update complete\n");
+ return;
+ }
+ msleep(100);
+ }
+ debug("Splash screen update failed!\n");
+
+}
+
+void lcd_enable(void)
+{
+ int i;
+
+ epdc_power_on();
+
+ /* Draw black border around framebuffer*/
+ memset(lcd_base, 0xFF, panel_info.vl_col * panel_info.vl_row);
+ memset(lcd_base, 0x0, 24 * panel_info.vl_col);
+ for (i = 24; i < (panel_info.vl_row - 24); i++) {
+ memset((u8 *)lcd_base + i * panel_info.vl_col, 0x00, 24);
+ memset((u8 *)lcd_base + i * panel_info.vl_col
+ + panel_info.vl_col - 24, 0x00, 24);
+ }
+ memset((u8 *)lcd_base + panel_info.vl_col * (panel_info.vl_row - 24),
+ 0x00, 24 * panel_info.vl_col);
+
+ /* Draw data to display */
+ draw_mode0();
+
+ draw_splash_screen();
+}
+
+void lcd_disable(void)
+{
+ debug("lcd_disable\n");
+
+ /* Disable clocks to EPDC */
+ REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE);
+}
+
+void lcd_panel_disable(void)
+{
+ epdc_power_off();
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ /*
+ * We rely on lcdbase being a physical address, i.e., either MMU off,
+ * or 1-to-1 mapping. Might want to add some virt2phys here.
+ */
+ if (!lcdbase)
+ return;
+
+ lcd_color_fg = 0xFF;
+ lcd_color_bg = 0xFF;
+
+ /* Reset */
+ REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST);
+ while (!(REG_RD(EPDC_BASE, EPDC_CTRL) & EPDC_CTRL_CLKGATE))
+ ;
+ REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST);
+
+ /* Enable clock gating (clear to enable) */
+ REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE);
+ while (REG_RD(EPDC_BASE, EPDC_CTRL) &
+ (EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE))
+ ;
+
+ debug("resolution %dx%d, bpp %d\n", (int)panel_info.vl_col,
+ (int)panel_info.vl_row, NBITS(panel_info.vl_bpix));
+
+ /* Set framebuffer pointer */
+ REG_WR(EPDC_BASE, EPDC_UPD_ADDR, (u32)lcdbase);
+
+ /* Set Working Buffer pointer */
+ REG_WR(EPDC_BASE, EPDC_WB_ADDR, panel_info.epdc_data.working_buf_addr);
+
+ /* Get waveform data address and offset */
+ if (setup_waveform_file()) {
+ printf("Can't load waveform data!\n");
+ return;
+ }
+
+ /* Set Waveform Buffer pointer */
+ REG_WR(EPDC_BASE, EPDC_WVADDR,
+ panel_info.epdc_data.waveform_buf_addr);
+
+ /* Initialize EPDC, passing pointer to EPDC registers */
+ epdc_init_settings();
+
+ return;
+}
+
+ulong calc_fbsize(void)
+{
+ return panel_info.vl_row * panel_info.vl_col * 2 \
+ * NBITS(panel_info.vl_bpix) / 8;
+}
+
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#ifndef __EPDC_REGS_INCLUDED__
+#define __EPDC_REGS_INCLUDED__
+
+#include <linux/types.h>
+#include <linux/list.h>
+
+/*************************************
+ * Register addresses
+ *************************************/
+#define EPDC_BASE (EPDC_BASE_ADDR)
+
+#define EPDC_CTRL (0x000)
+#define EPDC_CTRL_SET (0x004)
+#define EPDC_CTRL_CLR (0x008)
+#define EPDC_CTRL_TOG (0x00c)
+#define EPDC_WVADDR (0x020)
+#define EPDC_WB_ADDR (0x030)
+#define EPDC_RES (0x040)
+#define EPDC_FORMAT (0x050)
+#define EPDC_FORMAT_SET (0x054)
+#define EPDC_FORMAT_CLR (0x058)
+#define EPDC_FORMAT_TOG (0x05c)
+#define EPDC_FIFOCTRL (0x0a0)
+#define EPDC_FIFOCTRL_SET (0x0a4)
+#define EPDC_FIFOCTRL_CLR (0x0a8)
+#define EPDC_FIFOCTRL_TOG (0x0ac)
+#define EPDC_UPD_ADDR (0x100)
+#define EPDC_UPD_CORD (0x120)
+#define EPDC_UPD_SIZE (0x140)
+#define EPDC_UPD_CTRL (0x160)
+#define EPDC_UPD_FIXED (0x180)
+#define EPDC_TEMP (0x1a0)
+#define EPDC_TCE_CTRL (0x200)
+#define EPDC_TCE_SDCFG (0x220)
+#define EPDC_TCE_GDCFG (0x240)
+#define EPDC_TCE_HSCAN1 (0x260)
+#define EPDC_TCE_HSCAN2 (0x280)
+#define EPDC_TCE_VSCAN (0x2a0)
+#define EPDC_TCE_OE (0x2c0)
+#define EPDC_TCE_POLARITY (0x2e0)
+#define EPDC_TCE_TIMING1 (0x300)
+#define EPDC_TCE_TIMING2 (0x310)
+#define EPDC_TCE_TIMING3 (0x320)
+#define EPDC_IRQ_MASK (0x400)
+#define EPDC_IRQ_MASK_SET (0x404)
+#define EPDC_IRQ_MASK_CLR (0x408)
+#define EPDC_IRQ_MASK_TOG (0x40c)
+#define EPDC_IRQ (0x420)
+#define EPDC_IRQ_SET (0x424)
+#define EPDC_IRQ_CLR (0x428)
+#define EPDC_IRQ_TOG (0x42c)
+#define EPDC_STATUS_LUTS (0x440)
+#define EPDC_STATUS_LUTS_SET (0x444)
+#define EPDC_STATUS_LUTS_CLR (0x448)
+#define EPDC_STATUS_LUTS_TOG (0x44c)
+#define EPDC_STATUS_NEXTLUT (0x460)
+#define EPDC_STATUS_COL (0x480)
+#define EPDC_STATUS (0x4a0)
+#define EPDC_STATUS_SET (0x4a4)
+#define EPDC_STATUS_CLR (0x4a8)
+#define EPDC_STATUS_TOG (0x4ac)
+#define EPDC_DEBUG (0x500)
+#define EPDC_DEBUG_LUT0 (0x540)
+#define EPDC_DEBUG_LUT1 (0x550)
+#define EPDC_DEBUG_LUT2 (0x560)
+#define EPDC_DEBUG_LUT3 (0x570)
+#define EPDC_DEBUG_LUT4 (0x580)
+#define EPDC_DEBUG_LUT5 (0x590)
+#define EPDC_DEBUG_LUT6 (0x5a0)
+#define EPDC_DEBUG_LUT7 (0x5b0)
+#define EPDC_DEBUG_LUT8 (0x5c0)
+#define EPDC_DEBUG_LUT9 (0x5d0)
+#define EPDC_DEBUG_LUT10 (0x5e0)
+#define EPDC_DEBUG_LUT11 (0x5f0)
+#define EPDC_DEBUG_LUT12 (0x600)
+#define EPDC_DEBUG_LUT13 (0x610)
+#define EPDC_DEBUG_LUT14 (0x620)
+#define EPDC_DEBUG_LUT15 (0x630)
+#define EPDC_GPIO (0x700)
+#define EPDC_VERSION (0x7f0)
+
+enum {
+ /* EPDC_CTRL field values */
+ EPDC_CTRL_SFTRST = 0x80000000,
+ EPDC_CTRL_CLKGATE = 0x40000000,
+ EPDC_CTRL_SRAM_POWERDOWN = 0x100,
+ EPDC_CTRL_UPD_DATA_SWIZZLE_MASK = 0xc0,
+ EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP = 0,
+ EPDC_CTRL_UPD_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x40,
+ EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_SWAP = 0x80,
+ EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_BYTE_SWAP = 0xc0,
+ EPDC_CTRL_LUT_DATA_SWIZZLE_MASK = 0x30,
+ EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP = 0,
+ EPDC_CTRL_LUT_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x10,
+ EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_SWAP = 0x20,
+ EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_BYTE_SWAP = 0x30,
+ EPDC_CTRL_BURST_LEN_8_8 = 0x1,
+ EPDC_CTRL_BURST_LEN_8_16 = 0,
+
+ /* EPDC_RES field values */
+ EPDC_RES_VERTICAL_MASK = 0x1fff0000,
+ EPDC_RES_VERTICAL_OFFSET = 16,
+ EPDC_RES_HORIZONTAL_MASK = 0x1fff,
+ EPDC_RES_HORIZONTAL_OFFSET = 0,
+
+ /* EPDC_FORMAT field values */
+ EPDC_FORMAT_BUF_PIXEL_SCALE_ROUND = 0x1000000,
+ EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK = 0xff0000,
+ EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET = 16,
+ EPDC_FORMAT_BUF_PIXEL_FORMAT_P2N = 0x200,
+ EPDC_FORMAT_BUF_PIXEL_FORMAT_P3N = 0x300,
+ EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N = 0x400,
+ EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N = 0x500,
+ EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT = 0x0,
+ EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT_VCOM = 0x1,
+ EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT = 0x2,
+ EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT_VCOM = 0x3,
+
+ /* EPDC_FIFOCTRL field values */
+ EPDC_FIFOCTRL_ENABLE_PRIORITY = 0x80000000,
+ EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK = 0xff0000,
+ EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET = 16,
+ EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK = 0xff00,
+ EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET = 8,
+ EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK = 0xff,
+ EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET = 0,
+
+ /* EPDC_UPD_CORD field values */
+ EPDC_UPD_CORD_YCORD_MASK = 0x1fff0000,
+ EPDC_UPD_CORD_YCORD_OFFSET = 16,
+ EPDC_UPD_CORD_XCORD_MASK = 0x1fff,
+ EPDC_UPD_CORD_XCORD_OFFSET = 0,
+
+ /* EPDC_UPD_SIZE field values */
+ EPDC_UPD_SIZE_HEIGHT_MASK = 0x1fff0000,
+ EPDC_UPD_SIZE_HEIGHT_OFFSET = 16,
+ EPDC_UPD_SIZE_WIDTH_MASK = 0x1fff,
+ EPDC_UPD_SIZE_WIDTH_OFFSET = 0,
+
+ /* EPDC_UPD_CTRL field values */
+ EPDC_UPD_CTRL_USE_FIXED = 0x80000000,
+ EPDC_UPD_CTRL_LUT_SEL_MASK = 0xf0000,
+ EPDC_UPD_CTRL_LUT_SEL_OFFSET = 16,
+ EPDC_UPD_CTRL_WAVEFORM_MODE_MASK = 0xff00,
+ EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET = 8,
+ EPDC_UPD_CTRL_UPDATE_MODE_FULL = 0x1,
+
+ /* EPDC_UPD_FIXED field values */
+ EPDC_UPD_FIXED_FIXNP_EN = 0x80000000,
+ EPDC_UPD_FIXED_FIXCP_EN = 0x40000000,
+ EPDC_UPD_FIXED_FIXNP_MASK = 0xff00,
+ EPDC_UPD_FIXED_FIXNP_OFFSET = 8,
+ EPDC_UPD_FIXED_FIXCP_MASK = 0xff,
+ EPDC_UPD_FIXED_FIXCP_OFFSET = 0,
+
+ /* EPDC_TCE_CTRL field values */
+ EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK = 0x1ff0000,
+ EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET = 16,
+ EPDC_TCE_CTRL_VCOM_VAL_MASK = 0xc00,
+ EPDC_TCE_CTRL_VCOM_VAL_OFFSET = 10,
+ EPDC_TCE_CTRL_VCOM_MODE_AUTO = 0x200,
+ EPDC_TCE_CTRL_VCOM_MODE_MANUAL = 0x000,
+ EPDC_TCE_CTRL_DDR_MODE_ENABLE = 0x100,
+ EPDC_TCE_CTRL_LVDS_MODE_CE_ENABLE = 0x80,
+ EPDC_TCE_CTRL_LVDS_MODE_ENABLE = 0x40,
+ EPDC_TCE_CTRL_SCAN_DIR_1_UP = 0x20,
+ EPDC_TCE_CTRL_SCAN_DIR_0_UP = 0x10,
+ EPDC_TCE_CTRL_DUAL_SCAN_ENABLE = 0x8,
+ EPDC_TCE_CTRL_SDDO_WIDTH_16BIT = 0x4,
+ EPDC_TCE_CTRL_PIXELS_PER_SDCLK_2 = 1,
+ EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4 = 2,
+ EPDC_TCE_CTRL_PIXELS_PER_SDCLK_8 = 3,
+
+ /* EPDC_TCE_SDCFG field values */
+ EPDC_TCE_SDCFG_SDCLK_HOLD = 0x200000,
+ EPDC_TCE_SDCFG_SDSHR = 0x100000,
+ EPDC_TCE_SDCFG_NUM_CE_MASK = 0xf0000,
+ EPDC_TCE_SDCFG_NUM_CE_OFFSET = 16,
+ EPDC_TCE_SDCFG_SDDO_REFORMAT_STANDARD = 0,
+ EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS = 0x4000,
+ EPDC_TCE_SDCFG_SDDO_INVERT_ENABLE = 0x2000,
+ EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK = 0x1fff,
+ EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET = 0,
+
+ /* EPDC_TCE_GDCFG field values */
+ EPDC_TCE_SDCFG_GDRL = 0x10,
+ EPDC_TCE_SDCFG_GDOE_MODE_DELAYED_GDCLK = 0x2,
+ EPDC_TCE_SDCFG_GDSP_MODE_FRAME_SYNC = 0x1,
+ EPDC_TCE_SDCFG_GDSP_MODE_ONE_LINE = 0x0,
+
+ /* EPDC_TCE_HSCAN1 field values */
+ EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK = 0xfff0000,
+ EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET = 16,
+ EPDC_TCE_HSCAN1_LINE_SYNC_MASK = 0xfff,
+ EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET = 0,
+
+ /* EPDC_TCE_HSCAN2 field values */
+ EPDC_TCE_HSCAN2_LINE_END_MASK = 0xfff0000,
+ EPDC_TCE_HSCAN2_LINE_END_OFFSET = 16,
+ EPDC_TCE_HSCAN2_LINE_BEGIN_MASK = 0xfff,
+ EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET = 0,
+
+ /* EPDC_TCE_VSCAN field values */
+ EPDC_TCE_VSCAN_FRAME_END_MASK = 0xff0000,
+ EPDC_TCE_VSCAN_FRAME_END_OFFSET = 16,
+ EPDC_TCE_VSCAN_FRAME_BEGIN_MASK = 0xff00,
+ EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET = 8,
+ EPDC_TCE_VSCAN_FRAME_SYNC_MASK = 0xff,
+ EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET = 0,
+
+ /* EPDC_TCE_OE field values */
+ EPDC_TCE_OE_SDOED_WIDTH_MASK = 0xff000000,
+ EPDC_TCE_OE_SDOED_WIDTH_OFFSET = 24,
+ EPDC_TCE_OE_SDOED_DLY_MASK = 0xff0000,
+ EPDC_TCE_OE_SDOED_DLY_OFFSET = 16,
+ EPDC_TCE_OE_SDOEZ_WIDTH_MASK = 0xff00,
+ EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET = 8,
+ EPDC_TCE_OE_SDOEZ_DLY_MASK = 0xff,
+ EPDC_TCE_OE_SDOEZ_DLY_OFFSET = 0,
+
+ /* EPDC_TCE_POLARITY field values */
+ EPDC_TCE_POLARITY_GDSP_POL_ACTIVE_HIGH = 0x10,
+ EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH = 0x8,
+ EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH = 0x4,
+ EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH = 0x2,
+ EPDC_TCE_POLARITY_SDCE_POL_ACTIVE_HIGH = 0x1,
+
+ /* EPDC_TCE_TIMING1 field values */
+ EPDC_TCE_TIMING1_SDLE_SHIFT_NONE = 0x00,
+ EPDC_TCE_TIMING1_SDLE_SHIFT_1 = 0x10,
+ EPDC_TCE_TIMING1_SDLE_SHIFT_2 = 0x20,
+ EPDC_TCE_TIMING1_SDLE_SHIFT_3 = 0x30,
+ EPDC_TCE_TIMING1_SDCLK_INVERT = 0x8,
+ EPDC_TCE_TIMING1_SDCLK_SHIFT_NONE = 0,
+ EPDC_TCE_TIMING1_SDCLK_SHIFT_1CYCLE = 1,
+ EPDC_TCE_TIMING1_SDCLK_SHIFT_2CYCLES = 2,
+ EPDC_TCE_TIMING1_SDCLK_SHIFT_3CYCLES = 3,
+
+ /* EPDC_TCE_TIMING2 field values */
+ EPDC_TCE_TIMING2_GDCLK_HP_MASK = 0xffff0000,
+ EPDC_TCE_TIMING2_GDCLK_HP_OFFSET = 16,
+ EPDC_TCE_TIMING2_GDSP_OFFSET_MASK = 0xffff,
+ EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET = 0,
+
+ /* EPDC_TCE_TIMING3 field values */
+ EPDC_TCE_TIMING3_GDOE_OFFSET_MASK = 0xffff0000,
+ EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET = 16,
+ EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK = 0xffff,
+ EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET = 0,
+
+ /* EPDC_IRQ_MASK/EPDC_IRQ field values */
+ EPDC_IRQ_WB_CMPLT_IRQ = 0x10000,
+ EPDC_IRQ_LUT_COL_IRQ = 0x20000,
+ EPDC_IRQ_TCE_UNDERRUN_IRQ = 0x40000,
+ EPDC_IRQ_FRAME_END_IRQ = 0x80000,
+ EPDC_IRQ_BUS_ERROR_IRQ = 0x100000,
+ EPDC_IRQ_TCE_IDLE_IRQ = 0x200000,
+
+ /* EPDC_STATUS_NEXTLUT field values */
+ EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID = 0x100,
+ EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK = 0xf,
+ EPDC_STATUS_NEXTLUT_NEXT_LUT_OFFSET = 0,
+
+ /* EPDC_STATUS field values */
+ EPDC_STATUS_LUTS_UNDERRUN = 0x4,
+ EPDC_STATUS_LUTS_BUSY = 0x2,
+ EPDC_STATUS_WB_BUSY = 0x1,
+
+ /* EPDC_DEBUG field values */
+ EPDC_DEBUG_UNDERRUN_RECOVER = 0x2,
+ EPDC_DEBUG_COLLISION_OFF = 0x1,
+
+ /* EPDC_GPIO field values */
+ EPDC_GPIO_PWRCOM = 0x40,
+ EPDC_GPIO_PWRCTRL_MASK = 0x3c,
+ EPDC_GPIO_PWRCTRL_OFFSET = 2,
+ EPDC_GPIO_BDR_MASK = 0x3,
+ EPDC_GPIO_BDR_OFFSET = 0,
+};
+
+#endif
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de
*
- * MX51 Linux framebuffer:
+ * IPUv3 Linux framebuffer:
*
- * (C) Copyright 2004-2010 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
+/* #define DEBUG */
+// #define DEBUG
#include <common.h>
#include <asm/errno.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <asm/io.h>
#include <malloc.h>
+#include <lcd.h>
+#include <ipu.h>
#include <video_fb.h>
#include "videomodes.h"
-#include "ipu.h"
#include "mxcfb.h"
-#include "ipu_regs.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern vidinfo_t panel_info;
+
+void *lcd_base; /* Start of framebuffer memory */
+void *lcd_console_address; /* Start of console buffer */
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+
+short console_col;
+short console_row;
static int mxcfb_map_video_memory(struct fb_info *fbi);
static int mxcfb_unmap_video_memory(struct fb_info *fbi);
-/* graphics setup */
-static GraphicDevice panel;
-static struct fb_videomode const *gmode;
-static uint8_t gdisp;
-static uint32_t gpixfmt;
+void lcd_initcolregs(void)
+{
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+}
-void fb_videomode_to_var(struct fb_var_screeninfo *var,
+void lcd_disable(void)
+{
+}
+
+void lcd_panel_disable(void)
+{
+}
+
+static void fb_videomode_to_var(struct fb_var_screeninfo *var,
const struct fb_videomode *mode)
{
var->xres = mode->xres;
case 16:
pixfmt = IPU_PIX_FMT_RGB565;
break;
+ case 8:
+ pixfmt = IPU_PIX_FMT_GENERIC;
}
return pixfmt;
}
static int setup_disp_channel1(struct fb_info *fbi)
{
ipu_channel_params_t params;
- struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+ struct mxcfb_info *mxc_fbi = fbi->par;
memset(¶ms, 0, sizeof(params));
params.mem_dp_bg_sync.di = mxc_fbi->ipu_di;
static int setup_disp_channel2(struct fb_info *fbi)
{
int retval = 0;
- struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+ struct mxcfb_info *mxc_fbi = fbi->par;
mxc_fbi->cur_ipu_buf = 1;
if (mxc_fbi->alpha_chan_en)
fbi->var.xoffset = fbi->var.yoffset = 0;
- debug("%s: %x %d %d %d %lx %lx\n",
+ debug("%s: ch: %08x xres: %d yres: %d line_length: %d mem: %08lx .. %08lx\n",
__func__,
mxc_fbi->ipu_ch,
fbi->var.xres,
fbi->fix.line_length,
fbi->fix.smem_start,
fbi->fix.smem_start +
- (fbi->fix.line_length * fbi->var.yres));
+ (fbi->fix.line_length * fbi->var.yres) - 1);
retval = ipu_init_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
bpp_to_pixfmt(fbi),
int retval = 0;
u32 mem_len;
ipu_di_signal_cfg_t sig_cfg;
- struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
+ struct mxcfb_info *mxc_fbi = fbi->par;
uint32_t out_pixel_fmt;
ipu_disable_channel(mxc_fbi->ipu_ch);
if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
sig_cfg.clkidle_en = 1;
- debug("pixclock = %ul Hz\n",
- (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
+ debug("pixclock = %lu.%03lu MHz\n",
+ PICOS2KHZ(fbi->var.pixclock) / 1000,
+ PICOS2KHZ(fbi->var.pixclock) % 1000);
- if (ipu_init_sync_panel(mxc_fbi->ipu_di,
+ retval = ipu_init_sync_panel(mxc_fbi->ipu_di,
(PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
fbi->var.xres, fbi->var.yres,
out_pixel_fmt,
fbi->var.upper_margin,
fbi->var.vsync_len,
fbi->var.lower_margin,
- 0, sig_cfg) != 0) {
- puts("mxcfb: Error initializing panel.\n");
- return -EINVAL;
+ 0, sig_cfg);
+ if (retval != 0) {
+ printf("mxc_ipuv3_fb: Error %d initializing panel\n", retval);
+ return retval;
}
retval = setup_disp_channel2(fbi);
fbi->fix.smem_len = fbi->var.yres_virtual *
fbi->fix.line_length;
}
-
- fbi->screen_base = (char *)malloc(fbi->fix.smem_len);
- fbi->fix.smem_start = (unsigned long)fbi->screen_base;
- if (fbi->screen_base == 0) {
+ if (gd->fb_base)
+ fbi->screen_base = (void *)gd->fb_base;
+ else
+ fbi->screen_base = malloc(fbi->fix.smem_len);
+ if (fbi->screen_base == NULL) {
puts("Unable to allocate framebuffer memory\n");
fbi->fix.smem_len = 0;
- fbi->fix.smem_start = 0;
return -EBUSY;
}
+ fbi->fix.smem_start = (unsigned long)fbi->screen_base;
debug("allocated fb @ paddr=0x%08X, size=%d.\n",
(uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
fbi->screen_size = fbi->fix.smem_len;
- /* Clear the screen */
- memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
-
return 0;
}
*/
static struct fb_info *mxcfb_init_fbinfo(void)
{
-#define BYTES_PER_LONG 4
-#define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG))
struct fb_info *fbi;
struct mxcfb_info *mxcfbi;
- char *p;
- int size = sizeof(struct mxcfb_info) + PADDING +
+ void *p;
+ int size = ALIGN(sizeof(struct mxcfb_info), sizeof(long)) +
sizeof(struct fb_info);
- debug("%s: %d %d %d %d\n",
+ debug("%s: %d %d %d\n",
__func__,
- PADDING,
size,
sizeof(struct mxcfb_info),
sizeof(struct fb_info));
memset(p, 0, size);
- fbi = (struct fb_info *)p;
- fbi->par = p + sizeof(struct fb_info) + PADDING;
+ fbi = p;
+ fbi->par = p + ALIGN(sizeof(struct fb_info), sizeof(long));
- mxcfbi = (struct mxcfb_info *)fbi->par;
- debug("Framebuffer structures at: fbi=0x%x mxcfbi=0x%x\n",
- (unsigned int)fbi, (unsigned int)mxcfbi);
+ mxcfbi = fbi->par;
+ debug("Framebuffer structures at: fbi=%p mxcfbi=%p\n",
+ fbi, mxcfbi);
fbi->var.activate = FB_ACTIVATE_NOW;
*
* @return Appropriate error code to the kernel common code
*/
-static int mxcfb_probe(u32 interface_pix_fmt, uint8_t disp,
- struct fb_videomode const *mode)
+static int mxcfb_probe(u32 interface_pix_fmt, struct fb_videomode *mode, int di)
{
struct fb_info *fbi;
struct mxcfb_info *mxcfbi;
- int ret = 0;
/*
* Initialize FB structures
*/
fbi = mxcfb_init_fbinfo();
- if (!fbi) {
- ret = -ENOMEM;
- goto err0;
- }
- mxcfbi = (struct mxcfb_info *)fbi->par;
+ if (!fbi)
+ return -ENOMEM;
+
+ mxcfbi = fbi->par;
if (!g_dp_in_use) {
mxcfbi->ipu_ch = MEM_BG_SYNC;
mxcfbi->blank = FB_BLANK_POWERDOWN;
}
- mxcfbi->ipu_di = disp;
+ mxcfbi->ipu_di = di;
ipu_disp_set_global_alpha(mxcfbi->ipu_ch, 1, 0x80);
ipu_disp_set_color_key(mxcfbi->ipu_ch, 0, 0);
mxcfb_info[mxcfbi->ipu_di] = fbi;
/* Need dummy values until real panel is configured */
+ fbi->var.xres = panel_info.vl_col;
+ fbi->var.yres = panel_info.vl_row;
mxcfbi->ipu_di_pix_fmt = interface_pix_fmt;
fb_videomode_to_var(&fbi->var, mode);
- fbi->var.bits_per_pixel = 16;
+ fbi->var.bits_per_pixel = NBITS(panel_info.vl_bpix);
fbi->fix.line_length = fbi->var.xres * (fbi->var.bits_per_pixel / 8);
fbi->fix.smem_len = fbi->var.yres_virtual * fbi->fix.line_length;
mxcfb_check_var(&fbi->var, fbi);
-
- /* Default Y virtual size is 2x panel size */
- fbi->var.yres_virtual = fbi->var.yres * 2;
-
mxcfb_set_fix(fbi);
- /* alocate fb first */
+ /* allocate fb first */
if (mxcfb_map_video_memory(fbi) < 0)
return -ENOMEM;
mxcfb_set_par(fbi);
- panel.winSizeX = mode->xres;
- panel.winSizeY = mode->yres;
- panel.plnSizeX = mode->xres;
- panel.plnSizeY = mode->yres;
-
- panel.frameAdrs = (u32)fbi->screen_base;
- panel.memSize = fbi->screen_size;
+ lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
- panel.gdfBytesPP = 2;
- panel.gdfIndex = GDF_16BIT_565RGB;
+ debug("MXC IPUV3 configured\n"
+ "XRES = %d YRES = %d BitsXpixel = %d\n",
+ panel_info.vl_col,
+ panel_info.vl_row,
+ panel_info.vl_bpix);
ipu_dump_registers();
return 0;
-
-err0:
- return ret;
}
-void ipuv3_fb_shutdown(void)
+ulong calc_fbsize(void)
{
- int i;
- struct ipu_stat *stat = (struct ipu_stat *)IPU_STAT;
-
- for (i = 0; i < ARRAY_SIZE(mxcfb_info); i++) {
- struct fb_info *fbi = mxcfb_info[i];
- if (fbi) {
- struct mxcfb_info *mxc_fbi = fbi->par;
- ipu_disable_channel(mxc_fbi->ipu_ch);
- ipu_uninit_channel(mxc_fbi->ipu_ch);
- }
- }
- for (i = 0; i < ARRAY_SIZE(stat->int_stat); i++) {
- __raw_writel(__raw_readl(&stat->int_stat[i]),
- &stat->int_stat[i]);
- }
+ return (panel_info.vl_col * panel_info.vl_row *
+ NBITS(panel_info.vl_bpix)) / 8;
}
-void *video_hw_init(void)
+int overwrite_console(void)
{
- int ret;
+ /* Keep stdout / stderr on serial, our LCD is for splashscreen only */
+ return 1;
+}
- ret = ipu_probe();
- if (ret)
- puts("Error initializing IPU\n");
+#if 0
+void lcd_ctrl_init(void *lcdbase)
+{
+ u32 mem_len = panel_info.vl_col *
+ panel_info.vl_row *
+ NBITS(panel_info.vl_bpix) / 8;
- ret = mxcfb_probe(gpixfmt, gdisp, gmode);
- debug("Framebuffer at 0x%x\n", (unsigned int)panel.frameAdrs);
+ /*
+ * We rely on lcdbase being a physical address, i.e., either MMU off,
+ * or 1-to-1 mapping. Might want to add some virt2phys here.
+ */
+ if (!lcdbase)
+ return;
- return (void *)&panel;
+ memset(lcdbase, 0, mem_len);
}
+#endif
-void video_set_lut(unsigned int index, /* color number */
- unsigned char r, /* red */
- unsigned char g, /* green */
- unsigned char b /* blue */
- )
+int ipuv3_fb_init(struct fb_videomode *mode, int di, unsigned int interface_pix_fmt,
+ ipu_di_clk_parent_t di_clk_parent, unsigned long di_clk_val, int bpp)
{
- return;
-}
+ int ret;
-int ipuv3_fb_init(struct fb_videomode const *mode,
- uint8_t disp,
- uint32_t pixfmt)
-{
- gmode = mode;
- gdisp = disp;
- gpixfmt = pixfmt;
+// default_bpp = bpp;
- return 0;
+ ret = ipu_probe(di, di_clk_parent, di_clk_val);
+ if (ret) {
+ printf("Error initializing IPU\n");
+ return ret;
+ }
+
+ debug("Framebuffer at %p\n", lcd_base);
+ ret = mxcfb_probe(interface_pix_fmt, mode, di);
+
+ return ret;
}
--- /dev/null
+/*
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * LCD driver for i.MXS
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <lcd.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mxsfb.h>
+#include <asm/arch/sys_proto.h>
+
+vidinfo_t panel_info = {
+ /* set to max. size supported by SoC */
+ .vl_col = 800,
+ .vl_row = 480,
+
+ .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+};
+
+static int bits_per_pixel;
+static int color_depth;
+static uint32_t pix_fmt;
+static struct fb_var_screeninfo mxsfb_var;
+
+static struct mxs_lcdif_regs *lcd_regs = (void *)MXS_LCDIF_BASE;
+
+void *lcd_base; /* Start of framebuffer memory */
+void *lcd_console_address; /* Start of console buffer */
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+
+short console_col;
+short console_row;
+
+void lcd_initcolregs(void)
+{
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+
+#define fourcc_str(fourcc) ((fourcc) >> 0) & 0xff, \
+ ((fourcc) >> 8) & 0xff, \
+ ((fourcc) >> 16) & 0xff, \
+ ((fourcc) >> 24) & 0xff
+
+#define LCD_CTRL_DEFAULT (LCDIF_CTRL_LCDIF_MASTER | \
+ LCDIF_CTRL_BYPASS_COUNT | \
+ LCDIF_CTRL_DOTCLK_MODE)
+
+#define LCD_CTRL1_DEFAULT 0
+#define LCD_CTRL2_DEFAULT LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2
+
+#define LCD_VDCTRL0_DEFAULT (LCDIF_VDCTRL0_ENABLE_PRESENT | \
+ LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | \
+ LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT)
+#define LCD_VDCTRL1_DEFAULT 0
+#define LCD_VDCTRL2_DEFAULT 0
+#define LCD_VDCTRL3_DEFAULT 0
+#define LCD_VDCTRL4_DEFAULT LCDIF_VDCTRL4_SYNC_SIGNALS_ON
+
+void video_hw_init(void *lcdbase)
+{
+ int ret;
+ unsigned int div = 0, best = 0, pix_clk;
+ u32 frac1;
+ const unsigned long lcd_clk = 480000000;
+ u32 lcd_ctrl = LCD_CTRL_DEFAULT | LCDIF_CTRL_RUN;
+ u32 lcd_ctrl1 = LCD_CTRL1_DEFAULT, lcd_ctrl2 = LCD_CTRL2_DEFAULT;
+ u32 lcd_vdctrl0 = LCD_VDCTRL0_DEFAULT;
+ u32 lcd_vdctrl1 = LCD_VDCTRL1_DEFAULT;
+ u32 lcd_vdctrl2 = LCD_VDCTRL2_DEFAULT;
+ u32 lcd_vdctrl3 = LCD_VDCTRL3_DEFAULT;
+ u32 lcd_vdctrl4 = LCD_VDCTRL4_DEFAULT;
+ struct mxs_clkctrl_regs *clk_regs = (void *)MXS_CLKCTRL_BASE;
+ char buf1[16], buf2[16];
+
+ /* pixel format in memory */
+ switch (color_depth) {
+ case 8:
+ lcd_ctrl |= LCDIF_CTRL_WORD_LENGTH_8BIT;
+ lcd_ctrl1 |= LCDIF_CTRL1_BYTE_PACKING_FORMAT(1);
+ break;
+
+ case 16:
+ lcd_ctrl |= LCDIF_CTRL_WORD_LENGTH_16BIT;
+ lcd_ctrl1 |= LCDIF_CTRL1_BYTE_PACKING_FORMAT(3);
+ break;
+
+ case 18:
+ lcd_ctrl |= LCDIF_CTRL_WORD_LENGTH_18BIT;
+ lcd_ctrl1 |= LCDIF_CTRL1_BYTE_PACKING_FORMAT(7);
+ break;
+
+ case 24:
+ lcd_ctrl |= LCDIF_CTRL_WORD_LENGTH_24BIT;
+ lcd_ctrl1 |= LCDIF_CTRL1_BYTE_PACKING_FORMAT(7);
+ break;
+
+ default:
+ printf("Invalid bpp: %d\n", color_depth);
+ return;
+ }
+
+ /* pixel format on the LCD data pins */
+ switch (pix_fmt) {
+ case PIX_FMT_RGB332:
+ lcd_ctrl |= LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
+ break;
+
+ case PIX_FMT_RGB565:
+ lcd_ctrl |= LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
+ break;
+
+ case PIX_FMT_BGR666:
+ lcd_ctrl |= 1 << LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET;
+ /* fallthru */
+ case PIX_FMT_RGB666:
+ lcd_ctrl |= LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
+ break;
+
+ case PIX_FMT_BGR24:
+ lcd_ctrl |= 1 << LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET;
+ /* fallthru */
+ case PIX_FMT_RGB24:
+ lcd_ctrl |= LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
+ break;
+
+ default:
+ printf("Invalid pixel format: %c%c%c%c\n", fourcc_str(pix_fmt));
+ return;
+ }
+
+ pix_clk = PICOS2KHZ(mxsfb_var.pixclock);
+ debug("designated pix_clk: %sMHz\n", strmhz(buf1, pix_clk * 1000));
+
+ for (frac1 = 18; frac1 < 36; frac1++) {
+ static unsigned int err = ~0;
+ unsigned long clk = lcd_clk / 1000 * 18 / frac1;
+ unsigned int d = (clk + pix_clk - 1) / pix_clk;
+ unsigned int diff = abs(clk / d - pix_clk);
+
+ debug("frac1=%u div=%u lcd_clk=%-8sMHz pix_clk=%-8sMHz diff=%u err=%u\n",
+ frac1, d, strmhz(buf1, clk * 1000), strmhz(buf2, clk * 1000 / d),
+ diff, err);
+
+ if (clk < pix_clk)
+ break;
+ if (d > 255)
+ continue;
+
+ if (diff < err) {
+ best = frac1;
+ div = d;
+ err = diff;
+ if (err == 0)
+ break;
+ }
+ }
+ if (div == 0) {
+ printf("Requested pixel clock %sMHz out of range\n",
+ strmhz(buf1, pix_clk * 1000));
+ return;
+ }
+
+ debug("div=%lu(%u*%u/18) for pixel clock %sMHz with base clock %sMHz\n",
+ lcd_clk / pix_clk / 1000, best, div,
+ strmhz(buf1, lcd_clk / div * 18 / best),
+ strmhz(buf2, lcd_clk));
+
+ frac1 = (readl(&clk_regs->hw_clkctrl_frac1_reg) & ~0xff) | best;
+ writel(frac1, &clk_regs->hw_clkctrl_frac1_reg);
+ writel(1 << 14, &clk_regs->hw_clkctrl_clkseq_clr);
+
+ /* enable LCD clk and fractional divider */
+ writel(div, &clk_regs->hw_clkctrl_lcdif_reg);
+ while (readl(&clk_regs->hw_clkctrl_lcdif_reg) & (1 << 29))
+ ;
+
+ ret = mxs_reset_block(&lcd_regs->hw_lcdif_ctrl_reg);
+ if (ret) {
+ printf("Failed to reset LCD controller: LCDIF_CTRL: %08x CLKCTRL_LCDIF: %08x\n",
+ readl(&lcd_regs->hw_lcdif_ctrl_reg),
+ readl(&clk_regs->hw_clkctrl_lcdif_reg));
+ return;
+ }
+
+ if (mxsfb_var.sync & FB_SYNC_HOR_HIGH_ACT)
+ lcd_vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
+
+ if (mxsfb_var.sync & FB_SYNC_VERT_HIGH_ACT)
+ lcd_vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
+
+ if (mxsfb_var.sync & FB_SYNC_DATA_ENABLE_HIGH_ACT)
+ lcd_vdctrl0 |= LCDIF_VDCTRL0_ENABLE_POL;
+
+ if (mxsfb_var.sync & FB_SYNC_DOTCLK_FALLING_ACT)
+ lcd_vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL;
+
+ lcd_vdctrl0 |= LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(mxsfb_var.vsync_len);
+ lcd_vdctrl1 |= LCDIF_VDCTRL1_VSYNC_PERIOD(mxsfb_var.vsync_len +
+ mxsfb_var.upper_margin +
+ mxsfb_var.lower_margin +
+ mxsfb_var.yres);
+ lcd_vdctrl2 |= LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(mxsfb_var.hsync_len);
+ lcd_vdctrl2 |= LCDIF_VDCTRL2_HSYNC_PERIOD(mxsfb_var.hsync_len +
+ mxsfb_var.left_margin +
+ mxsfb_var.right_margin +
+ mxsfb_var.xres);
+
+ lcd_vdctrl3 |= LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(mxsfb_var.left_margin +
+ mxsfb_var.hsync_len);
+ lcd_vdctrl3 |= LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(mxsfb_var.upper_margin +
+ mxsfb_var.vsync_len);
+
+ lcd_vdctrl4 |= LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(mxsfb_var.xres);
+
+ writel((u32)lcdbase, &lcd_regs->hw_lcdif_next_buf_reg);
+ writel(LCDIF_TRANSFER_COUNT_H_COUNT(mxsfb_var.xres) |
+ LCDIF_TRANSFER_COUNT_V_COUNT(mxsfb_var.yres),
+ &lcd_regs->hw_lcdif_transfer_count_reg);
+
+ writel(lcd_vdctrl0, &lcd_regs->hw_lcdif_vdctrl0_reg);
+ writel(lcd_vdctrl1, &lcd_regs->hw_lcdif_vdctrl1_reg);
+ writel(lcd_vdctrl2, &lcd_regs->hw_lcdif_vdctrl2_reg);
+ writel(lcd_vdctrl3, &lcd_regs->hw_lcdif_vdctrl3_reg);
+ writel(lcd_vdctrl4, &lcd_regs->hw_lcdif_vdctrl4_reg);
+
+ writel(lcd_ctrl1, &lcd_regs->hw_lcdif_ctrl1_reg);
+ writel(lcd_ctrl2, &lcd_regs->hw_lcdif_ctrl2_reg);
+
+ writel(lcd_ctrl, &lcd_regs->hw_lcdif_ctrl_reg);
+
+ debug("mxsfb framebuffer driver initialized\n");
+}
+
+void mxsfb_disable(void)
+{
+ u32 lcd_ctrl = readl(&lcd_regs->hw_lcdif_ctrl_reg);
+
+ writel(lcd_ctrl & ~LCDIF_CTRL_RUN, &lcd_regs->hw_lcdif_ctrl_reg);
+}
+
+int mxsfb_init(struct fb_videomode *mode, uint32_t pixfmt, int bpp)
+{
+ switch (bpp) {
+ case 8:
+ bits_per_pixel = 8;
+ panel_info.vl_bpix = LCD_COLOR8;
+ break;
+
+ case 16:
+ bits_per_pixel = 16;
+ panel_info.vl_bpix = LCD_COLOR16;
+ break;
+
+ case 18:
+ bits_per_pixel = 32;
+ panel_info.vl_bpix = LCD_COLOR24;
+ break;
+
+ case 24:
+ bits_per_pixel = 32;
+ panel_info.vl_bpix = LCD_COLOR24;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ pix_fmt = pixfmt;
+ color_depth = bpp;
+
+ lcd_line_length = bits_per_pixel / 8 * mode->xres;
+
+ mxsfb_var.xres = mode->xres;
+ mxsfb_var.yres = mode->yres;
+ mxsfb_var.xres_virtual = mode->xres;
+ mxsfb_var.yres_virtual = mode->yres;
+ mxsfb_var.pixclock = mode->pixclock;
+ mxsfb_var.left_margin = mode->left_margin;
+ mxsfb_var.right_margin = mode->right_margin;
+ mxsfb_var.upper_margin = mode->upper_margin;
+ mxsfb_var.lower_margin = mode->lower_margin;
+ mxsfb_var.hsync_len = mode->hsync_len;
+ mxsfb_var.vsync_len = mode->vsync_len;
+ mxsfb_var.sync = mode->sync;
+
+ panel_info.vl_col = mode->xres;
+ panel_info.vl_row = mode->yres;
+
+ return 0;
+}
{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
- writew(WCR_WDE, &wdog->wcr);
- writew(0x5555, &wdog->wsr);
- writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
while (1) {
- /*
- * spin for .5 seconds before reset
- */
+ writew(0, &wdog->wcr); /* clear SRS initiating SOFT reset */
}
}
Please define CONFIG_ARCH_DEVICE_TREE))
# We preprocess the device tree file provide a useful define
-DTS_CPPFLAGS := -ansi \
- -DARCH_CPU_DTS=\"$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\" \
+DTS_CPPFLAGS := -DARCH_CPU_DTS=\"$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\" \
-DBOARD_DTS=\"$(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts/$(DEVICE_TREE).dts\"
all: $(obj).depend $(LIB)
$(DT_BIN): $(TOPDIR)/board/$(VENDOR)/dts/$(DEVICE_TREE).dts
rc=$$( \
- cat $< | $(CPP) -P $(DTS_CPPFLAGS) - | \
- { { $(DTC) -R 4 -p 0x1000 -O dtb -o ${DT_BIN} - 2>&1 ; \
+ cat $< | $(CPP) -P -x assembler-with-cpp $(DTS_CPPFLAGS) - | \
+ { { $(DTC) -R 4 -p 0x1000 -O dtb -o ${DT_BIN} - >&2 ; \
echo $$? >&3 ; } | \
grep -v '^DTC: dts->dtb on file' ; \
} 3>&1 1>&2 ) ; \
oformat=`$(call process_lds,cat $(LDSCRIPT),FORMAT)` && \
oarch=`$(call process_lds,cat $(LDSCRIPT),ARCH)` ;\
\
- [ -z $${oformat} ] && \
+ [ -z "$${oformat}" ] && \
oformat=`$(call process_lds,$(GET_LDS),FORMAT)` ;\
- [ -z $${oarch} ] && \
+ [ -z "$${oarch}" ] && \
oarch=`$(call process_lds,$(GET_LDS),ARCH)` ;\
\
- [ -z $${oformat} ] && \
+ [ -z "$${oformat}" ] && \
echo "Cannot read OUTPUT_FORMAT from lds file $(LDSCRIPT)" && \
exit 1 || true ;\
- [ -z $${oarch} ] && \
+ [ -z "$${oarch}" ] && \
echo "Cannot read OUTPUT_ARCH from lds file $(LDSCRIPT)" && \
exit 1 || true ;\
\
/*
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Terry Lv <r65388@freescale.com>
+ *
* Copyright (C) Freescale Semiconductor, Inc. 2006.
* Author: Jason Jin<Jason.jin@freescale.com>
* Zhang Wei<wei.zhang@freescale.com>
#define AHCI_PCI_BAR 0x24
#define AHCI_MAX_SG 56 /* hardware max is 64K */
+#define AHCI_MAX_CMD_SLOT 32
#define AHCI_CMD_SLOT_SZ 32
#define AHCI_MAX_CMD_SLOT 32
#define AHCI_RX_FIS_SZ 256
#define AHCI_CMD_TBL_HDR 0x80
#define AHCI_CMD_TBL_CDB 0x40
-#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
+#define AHCI_CMD_TBL_SZ (AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16))
#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \
AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ)
#define AHCI_CMD_ATAPI (1 << 5)
u32 host_flags;
u32 host_set_flags;
u32 mmio_base;
- u32 pio_mask;
+ u32 pio_mask;
u32 udma_mask;
u32 flags;
u32 cap; /* cache of HOST_CAP register */
--- /dev/null
+/*
+ * fec.h -- Fast Ethernet Controller definitions
+ *
+ * Some definitions copied from commproc.h for MPC8xx:
+ * MPC8xx Communication Processor Module.
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * Add FEC Structure and definitions
+ * Copyright 2004-2010 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef fec_h
+#define fec_h
+
+extern int fec_get_mac_addr(unsigned char *mac);
+
+#include <net.h>
+
+/* Buffer descriptors used FEC.
+*/
+typedef struct cpm_buf_desc {
+ ushort cbd_datlen; /* Data length in buffer */
+ ushort cbd_sc; /* Status and Control */
+ ulong cbd_bufaddr; /* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
+#define BD_SC_WRAP ((ushort)0x2000)/* Last buffer descriptor */
+#define BD_SC_INTRPT ((ushort)0x1000)/* Interrupt on change */
+#define BD_SC_LAST ((ushort)0x0800)/* Last buffer in frame */
+#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
+#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
+#define BD_SC_ID ((ushort)0x0100)/* Rec'd too many idles */
+#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
+#define BD_SC_BR ((ushort)0x0020) /* Break received */
+#define BD_SC_FR ((ushort)0x0010) /* Framing error */
+#define BD_SC_PR ((ushort)0x0008) /* Parity error */
+#define BD_SC_OV ((ushort)0x0002) /* Overrun */
+#define BD_SC_CD ((ushort)0x0001)/* Carrier Detect lost */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+*/
+#define BD_ENET_RX_EMPTY ((ushort)0x8000)
+#define BD_ENET_RX_RO1 ((ushort)0x4000)
+#define BD_ENET_RX_WRAP ((ushort)0x2000)
+#define BD_ENET_RX_INTR ((ushort)0x1000)
+#define BD_ENET_RX_RO2 BD_ENET_RX_INTR
+#define BD_ENET_RX_LAST ((ushort)0x0800)
+#define BD_ENET_RX_FIRST ((ushort)0x0400)
+#define BD_ENET_RX_MISS ((ushort)0x0100)
+#define BD_ENET_RX_BC ((ushort)0x0080)
+#define BD_ENET_RX_MC ((ushort)0x0040)
+#define BD_ENET_RX_LG ((ushort)0x0020)
+#define BD_ENET_RX_NO ((ushort)0x0010)
+#define BD_ENET_RX_SH ((ushort)0x0008)
+#define BD_ENET_RX_CR ((ushort)0x0004)
+#define BD_ENET_RX_OV ((ushort)0x0002)
+#define BD_ENET_RX_CL ((ushort)0x0001)
+#define BD_ENET_RX_TR BD_ENET_RX_CL
+#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+*/
+#define BD_ENET_TX_READY ((ushort)0x8000)
+#define BD_ENET_TX_PAD ((ushort)0x4000)
+#define BD_ENET_TX_TO1 BD_ENET_TX_PAD
+#define BD_ENET_TX_WRAP ((ushort)0x2000)
+#define BD_ENET_TX_INTR ((ushort)0x1000)
+#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
+#define BD_ENET_TX_LAST ((ushort)0x0800)
+#define BD_ENET_TX_TC ((ushort)0x0400)
+#define BD_ENET_TX_DEF ((ushort)0x0200)
+#define BD_ENET_TX_ABC BD_ENET_TX_DEF
+#define BD_ENET_TX_HB ((ushort)0x0100)
+#define BD_ENET_TX_LC ((ushort)0x0080)
+#define BD_ENET_TX_RL ((ushort)0x0040)
+#define BD_ENET_TX_RCMASK ((ushort)0x003c)
+#define BD_ENET_TX_UN ((ushort)0x0002)
+#define BD_ENET_TX_CSL ((ushort)0x0001)
+#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
+
+/*********************************************************************
+* Fast Ethernet Controller (FEC)
+*********************************************************************/
+/* FEC private information */
+struct fec_info_s {
+ int index;
+ volatile void *iobase;
+ int phy_addr;
+ int dup_spd;
+ char *phy_name;
+ int phyname_init;
+ cbd_t *rxbd; /* Rx BD */
+ cbd_t *txbd; /* Tx BD */
+ uint rxIdx;
+ uint txIdx;
+ char *txbuf;
+#ifdef CONFIG_ARCH_MMU
+ char *rxbuf[PKTBUFSRX];
+#endif
+ int initialized;
+ struct fec_info_s *next;
+};
+
+/* Register read/write struct */
+typedef struct fec {
+ u32 resv0;
+ u32 eir;
+ u32 eimr;
+ u32 resv1;
+ u32 rdar;
+ u32 tdar;
+ u32 resv2[0x03];
+ u32 ecr;
+ u32 resv3[0x06];
+ u32 mmfr;
+ u32 mscr;
+ u32 resv4[0x07];
+ u32 mibc;
+ u32 resv5[0x07];
+ u32 rcr;
+ u32 resv6[0x0F];
+ u32 tcr;
+ u32 resv7[0x07];
+ u32 palr;
+ u32 paur;
+ u32 opd;
+ u32 resv8[0x0A];
+ u32 iaur;
+ u32 ialr;
+ u32 gaur;
+ u32 galr;
+ u32 resv9[0x07];
+ u32 tfwr;
+ u32 resv10;
+ u32 frbr;
+ u32 frsr;
+ u32 resv11[0x0B];
+ u32 erdsr;
+ u32 etdsr;
+ u32 emrbr;
+ u32 resv12[93];
+ u32 fec_miigsk_cfgr;
+ u32 fec_reserved13;
+ u32 fec_miigsk_enr;
+} fec_t;
+
+/*********************************************************************
+* Fast Ethernet Controller (FEC)
+*********************************************************************/
+/* Bit definitions and macros for FEC_EIR */
+#define FEC_EIR_CLEAR_ALL (0xFFF80000)
+#define FEC_EIR_HBERR (0x80000000)
+#define FEC_EIR_BABR (0x40000000)
+#define FEC_EIR_BABT (0x20000000)
+#define FEC_EIR_GRA (0x10000000)
+#define FEC_EIR_TXF (0x08000000)
+#define FEC_EIR_TXB (0x04000000)
+#define FEC_EIR_RXF (0x02000000)
+#define FEC_EIR_RXB (0x01000000)
+#define FEC_EIR_MII (0x00800000)
+#define FEC_EIR_EBERR (0x00400000)
+#define FEC_EIR_LC (0x00200000)
+#define FEC_EIR_RL (0x00100000)
+#define FEC_EIR_UN (0x00080000)
+
+/* Bit definitions and macros for FEC_RDAR */
+#define FEC_RDAR_R_DES_ACTIVE (0x01000000)
+
+/* Bit definitions and macros for FEC_TDAR */
+#define FEC_TDAR_X_DES_ACTIVE (0x01000000)
+
+/* Bit definitions and macros for FEC_ECR */
+#define FEC_ECR_ETHER_EN (0x00000002)
+#define FEC_ECR_RESET (0x00000001)
+
+/* Bit definitions and macros for FEC_MMFR */
+#define FEC_MMFR_DATA(x) (((x)&0xFFFF))
+#define FEC_MMFR_ST(x) (((x)&0x03)<<30)
+#define FEC_MMFR_ST_01 (0x40000000)
+#define FEC_MMFR_OP_RD (0x20000000)
+#define FEC_MMFR_OP_WR (0x10000000)
+#define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
+#define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
+#define FEC_MMFR_TA(x) (((x)&0x03)<<16)
+#define FEC_MMFR_TA_10 (0x00020000)
+
+/* Bit definitions and macros for FEC_MSCR */
+#define FEC_MSCR_DIS_PREAMBLE (0x00000080)
+#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
+
+/* Bit definitions and macros for FEC_MIBC */
+#define FEC_MIBC_MIB_DISABLE (0x80000000)
+#define FEC_MIBC_MIB_IDLE (0x40000000)
+
+/* Bit definitions and macros for FEC_RCR */
+#define FEC_RCR_GRS (0x80000000)
+#define FEC_RCR_NO_LGTH_CHECK (0x40000000)
+#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
+#define FEC_RCR_CNTL_FRM_ENA (0x00008000)
+#define FEC_RCR_CRC_FWD (0x00004000)
+#define FEC_RCR_PAUSE_FWD (0x00002000)
+#define FEC_RCR_PAD_EN (0x00001000)
+#define FEC_RCR_RMII_ECHO (0x00000800)
+#define FEC_RCR_RMII_LOOP (0x00000400)
+#define FEC_RCR_RMII_10T (0x00000200)
+#define FEC_RCR_RMII_MODE (0x00000100)
+#define FEC_RCR_SGMII_ENA (0x00000080)
+#define FEC_RCR_RGMII_ENA (0x00000040)
+#define FEC_RCR_FCE (0x00000020)
+#define FEC_RCR_BC_REJ (0x00000010)
+#define FEC_RCR_PROM (0x00000008)
+#define FEC_RCR_MII_MODE (0x00000004)
+#define FEC_RCR_DRT (0x00000002)
+#define FEC_RCR_LOOP (0x00000001)
+
+/* Bit definitions and macros for FEC_TCR */
+#define FEC_TCR_RFC_PAUSE (0x00000010)
+#define FEC_TCR_TFC_PAUSE (0x00000008)
+#define FEC_TCR_FDEN (0x00000004)
+#define FEC_TCR_HBC (0x00000002)
+#define FEC_TCR_GTS (0x00000001)
+
+/* Bit definitions and macros for FEC_PAUR */
+#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
+#define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
+
+/* Bit definitions and macros for FEC_OPD */
+#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
+#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for FEC_TFWR */
+#define FEC_TFWR_X_WMRK(x) ((x)&0x03)
+#define FEC_TFWR_X_WMRK_64 (0x01)
+#define FEC_TFWR_X_WMRK_128 (0x02)
+#define FEC_TFWR_X_WMRK_192 (0x03)
+
+/* Bit definitions and macros for FEC_FRBR */
+#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
+
+/* Bit definitions and macros for FEC_FRSR */
+#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
+
+/* Bit definitions and macros for FEC_ERDSR */
+#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for FEC_ETDSR */
+#define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for FEC_EMRBR */
+#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
+
+#define FEC_RESET_DELAY 100
+#define FEC_RX_TOUT 100
+
+#define FEC_MAX_TIMEOUT 50000
+#define FEC_TIMEOUT_TICKET 2
+
+/*
+ * Functions
+ */
+int mxc_fec_initialize(bd_t *bis);
+
+#endif /* fec_h */
--- /dev/null
+/*
+ * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_MMU_H
+#define __ASM_MMU_H
+
+#include <asm/system.h>
+
+#define MMU_L1_TYPE 0x03 /* Descriptor type */
+#define MMU_L1_TYPE_Fault 0x00 /* Invalid */
+#define MMU_L1_TYPE_Page 0x11 /* Individual page mapping */
+#define MMU_L1_TYPE_Section 0x12 /* Mapping for 1M segment */
+
+#define MMU_L2_TYPE 0x03 /* Descriptor type */
+#define MMU_L2_TYPE_Fault 0x00 /* Invalid data */
+#define MMU_L2_TYPE_Large 0x01 /* Large page (64K) */
+#define MMU_L2_TYPE_Small 0x02 /* Small page (4K) */
+
+#define MMU_Bufferable 0x04 /* Data can use write-buffer */
+#define MMU_Cacheable 0x08 /* Data can use cache */
+
+#define MMU_AP_Limited 0x000 /* Limited access */
+#define MMU_AP_Supervisor 0x400 /* Supervisor RW, User none */
+#define MMU_AP_UserRead 0x800 /* Supervisor RW, User read only */
+#define MMU_AP_Any 0xC00 /* Supervisor RW, User RW */
+
+#define MMU_AP_ap0_Any 0x030
+#define MMU_AP_ap1_Any 0x0C0
+#define MMU_AP_ap2_Any 0x300
+#define MMU_AP_ap3_Any 0xC00
+#define MMU_AP_All (MMU_AP_ap0_Any|MMU_AP_ap1_Any|MMU_AP_ap2_Any|MMU_AP_ap3_Any)
+
+#define MMU_DOMAIN(x) ((x)<<5)
+
+#define MMU_PAGE_SIZE 0x1000
+#define MMU_SECTION_SIZE 0x100000
+
+#define MMU_CP p15 /* Co-processor ID */
+#define MMU_Control c1 /* Control register */
+#define MMU_Base c2 /* Page tables base */
+#define MMU_DomainAccess c3 /* Domain access control */
+#define MMU_FaultStatus c5 /* Fault status register */
+#define MMU_FaultAddress c6 /* Fault Address */
+#define MMU_InvalidateCache c7 /* Invalidate cache data */
+#define MMU_TLB c8 /* Translation Lookaside Buffer */
+
+/* These seem to be 710 specific */
+#define MMU_FlushTLB c5
+#define MMU_FlushIDC c7
+
+#define MMU_Control_M 0x001 /* Enable MMU */
+#define MMU_Control_A 0x002 /* Enable address alignment faults */
+#define MMU_Control_C 0x004 /* Enable cache */
+#define MMU_Control_W 0x008 /* Enable write-buffer */
+#define MMU_Control_P 0x010 /* Compatability: 32 bit code */
+#define MMU_Control_D 0x020 /* Compatability: 32 bit data */
+#define MMU_Control_L 0x040 /* Compatability: */
+#define MMU_Control_B 0x080 /* Enable Big-Endian */
+#define MMU_Control_S 0x100 /* Enable system protection */
+#define MMU_Control_R 0x200 /* Enable ROM protection */
+#define MMU_Control_I 0x1000 /* Enable Instruction cache */
+#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
+#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
+
+/* Extras for some newer versions eg. ARM920 with architecture version 4. */
+#define MMU_Control_F 0x400 /* IMPLEMENTATION DEFINED */
+#define MMU_Control_Z 0x800 /* Enable branch predicion */
+#define MMU_Control_RR 0x4000 /* Select non-random cache replacement */
+
+#ifdef CONFIG_ARCH_MMU
+
+#define MMU_ON() \
+ { \
+ unsigned long cr = 0; \
+ asm volatile ("mrc p15, 0, %0, c1, c0;" : "=r"(cr) : /*:*/); \
+ cr |= (CR_M | CR_A | CR_C | CR_Z); \
+ asm volatile ("mcr p15, 0, %0, c1, c0;" : : "r"(cr) /*:*/); \
+ /* Clean instruction pipeline */ \
+ asm volatile ( \
+ "b skip;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "skip:" \
+ ); \
+ }
+
+#define MMU_OFF() \
+ { \
+ unsigned long cr = 0; \
+ asm volatile ("mrc p15, 0, %0, c1, c0;" : "=r"(cr) /*: :*/); \
+ cr &= (~(CR_M | CR_A | CR_C | CR_I)); \
+ asm volatile ("mcr p15, 0, %0, c1, c0;" : : "r"(cr) /*:*/); \
+ asm volatile ( \
+ "nop;" /* flush i+d-TLBs */ \
+ "nop;" /* flush i+d-TLBs */ \
+ "nop;" /* flush i+d-TLBs */ \
+ ); \
+ }
+
+#else
+
+#define MMU_ON()
+#define MMU_OFF()
+
+#endif
+
+#endif
* an error value of -1.
*/
+enum gpio_flags {
+ GPIOF_INPUT,
+ GPIOF_OUTPUT_INIT_LOW,
+ GPIOF_OUTPUT_INIT_HIGH,
+};
+
+struct gpio {
+ unsigned int gpio;
+ enum gpio_flags flags;
+ const char *label;
+};
+
/**
* Request a gpio. This should be called before any of the other functions
* are used on this gpio.
* @return 0 if ok, -1 on error
*/
int gpio_set_value(unsigned gpio, int value);
+
+/**
+ * Request a GPIO and configure it
+ * @param gpios pointer to array of gpio defs
+ * @param count number of GPIOs to set up
+ */
+int gpio_request_one(unsigned gpio, enum gpio_flags flags, const char *label);
+
+/**
+ * Request a set of GPIOs and configure them
+ * @param gpios pointer to array of gpio defs
+ * @param count number of GPIOs to set up
+ */
+int gpio_request_array(const struct gpio *gpios, int count);
+
+/**
+ * Release a set of GPIOs
+ * @param gpios pointer to array of gpio defs
+ * @param count number of GPIOs to set up
+ */
+int gpio_free_array(const struct gpio *gpios, int count);
+
#endif /* _ASM_GENERIC_GPIO_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * Define this to make U-Boot skip low level initialization when loaded
+ * by initial bootloader. Not required by NAND U-Boot version but IS
+ * required for a NOR version used to burn the real NOR U-Boot into
+ * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
+ * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
+ * NOR U-Boot is loaded directly from Flash so it must perform all the
+ * low level initialization itself. NAND version is loaded by an initial
+ * bootloader (UBL in TI-ese) that performs such an initialization so it's
+ * skipped in NAND version. The third DaVinci boot mode loads a bootloader
+ * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
+ * performing low level init prior to loading. All that means we can NOT use
+ * NAND version to put U-Boot into NOR because it doesn't have NOR support and
+ * we can NOT use NOR version because it performs low level initialization
+ * effectively destroying itself in DDR memory. That's why a separate NOR
+ * version with this define is needed. It is loaded via UART, then one uses
+ * it to somehow download a proper NOR version built WITHOUT this define to
+ * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
+ * NOR support into the initial bootloader so it won't be needed but DaVinci
+ * static RAM might be too small for this (I have something like 2Kbytes left
+ * as of now, without NOR support) so this might've not happened...
+ *
+ */
+
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_MX23 /* MX23 SoC */
+#define CONFIG_MX23_EVK /* MX23 EVK board */
+#define CONFIG_SYS_CLK_FREQ 120000000 /* Arm Clock frequency */
+#define CONFIG_USE_TIMER0 /* use timer 0 */
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest start address */
+#define CONFIG_SYS_MEMTEST_END 0x41000000 /* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+#define PHYS_SDRAM_1 0x40000000 /* mDDR Start */
+#define PHYS_SDRAM_1_SIZE 0x02000000 /* mDDR size 32MB */
+
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CONFIG_STMP3XXX_DBGUART /* 378x debug UART */
+#define CONFIG_DBGUART_CLK 24000000
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*====================*/
+/* SPI Driver info */
+/*====================*/
+#define CONFIG_SSP_CLK 48000000
+#define CONFIG_SPI_CLK 3000000
+#define CONFIG_SPI_SSP1
+#undef CONFIG_SPI_SSP2
+
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#define CONFIG_SYS_NO_FLASH /* Flash is not supported */
+#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
+#define CONFIG_ENV_SIZE 0x20000
+
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.167.10.2
+#define CONFIG_SERVERIP 192.167.10.1
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "MX23 U-Boot > "
+ /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+ /* Print buffer sz */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot Argument Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR 0x40400000
+ /* default Linux kernel load address */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CFG_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR 0x40000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS "console=ttyAM0,115200n8 "\
+ "root=/dev/mtdblock1 rootfstype=jffs2 lcd_panel=lms350"
+#define CONFIG_BOOTCOMMAND "tftpboot ; bootm"
+
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#undef CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_SAVES
+#undef CONFIG_CMD_IMLS
+
+/* Ethernet chip - select an alternative driver */
+#define CONFIG_ENC28J60_ETH
+#define CONFIG_ENC28J60_ETH_SPI_BUS 0
+#define CONFIG_ENC28J60_ETH_SPI_CS 0
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2009-2010 Freescale Semiconductor
+ *
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Kshitij Gupta <kshitij@ti.com>
+ *
+ * Configuration settings for the Freescale i.MX31 PDK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx25.h>
+#include <asm/arch/mx25-regs.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARM926EJS 1 /* This is an arm1136 CPU core */
+#define CONFIG_MX25 1 /* in a mx31 */
+#define CONFIG_MX25_HCLK_FREQ 24000000
+#define CONFIG_MX25_CLK32 32768
+
+#define CONFIG_IMX_CSPI 1
+#define IMX_CSPI_VER_0_7 1
+#define CONFIG_IMX_SPI_CPLD
+
+/* IF iMX25 3DS V-1.0 define it */
+/* #define CONFIG_MX25_3DS_V10 */
+
+#ifdef CONFIG_MX25_3DS_V10
+#define MXC_MEMORY_MDDR
+#endif
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/* No support for NAND boot for i.MX31 PDK yet, so we rely on some other
+ * program to initialize the SDRAM.
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C1_BASE
+#define CONFIG_SYS_I2C_SPEED 40000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+#define CONFIG_MX25_UART 1
+#define CONFIG_MX25_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+/* #define CONFIG_CMD_SPI */
+/* #define CONFIG_CMD_DATE */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MMC
+#define CONFIG_MXC_NAND
+
+
+/*
+ * MMC Configs
+ * */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC 1
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_SYS_FSL_ESDHC_NUM 2
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_IMX_ESDHC_V1
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+#endif
+
+/* Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
+ * that CONFIG_NO_FLASH is undefined).
+ */
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=smc911x-0\0" \
+ "uboot=u-boot.bin\0" \
+ "uboot_addr=0xa0000000\0" \
+ "kernel=uImage\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "load_uboot=tftpboot ${loadaddr} ${uboot}\0" \
+ "splashimage=0x80800000\0"
+
+/*Support LAN9217*/
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_CPLD
+#define CONFIG_SMC911X_BASE 0
+
+#define CONFIG_HAS_ETH1
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#define CONFIG_NET_MULTI
+#define CONFIG_ETHPRIME
+
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_MII_GASKET
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#define CONFIG_IIM_MAC_ADDR_OFFSET 0x68
+
+#define CONFIG_FEC0_IOBASE FEC_BASE
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR 0x1F
+#define CONFIG_FEC0_MIIBASE -1
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "MX25 U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* default load address */
+
+#define CONFIG_SYS_HZ 1000
+
+#define UBOOT_IMAGE_SIZE 0x40000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE
+
+/* iMX25 V-1.0 has 128MB but V-1.1 has only 64MB */
+#ifdef CONFIG_MX25_3DS_V10
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+#else
+#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
+#endif
+
+/* LCD */
+/*
+#define CONFIG_SPLASH_SCREEN
+*/
+
+#ifdef CONFIG_SPLASH_SCREEN
+ #define CONFIG_LCD
+ #define CONFIG_MXC2_LCD 1
+ #undef LCD_TEST_PATTERN
+ #define CONFIG_FB_BASE 0x81400000
+ #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+ #define CONFIG_SPLASH_SCREEN 1
+ #define CONFIG_SPLASH_IS_IN_MMC 1
+ #define LCD_BPP LCD_COLOR16
+ /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
+
+ #define CONFIG_CMD_BMP
+ #define CONFIG_BMP_24BPP 1
+ #define CONFIG_BMP_16BPP 1
+#endif
+
+
+#ifdef CONFIG_SPLASH_IS_IN_MMC
+ #define CONFIG_SPLASH_IMG_MMC_DEV 0
+ #define CONFIG_SPLASH_IMG_OFFSET 0x4c000
+ #define CONFIG_SPLASH_IMG_SIZE 0x19000
+#endif
+
+/* Monitor at beginning of flash */
+/* #define CONFIG_FSL_ENV_IN_MMC */
+#define CONFIG_FSL_ENV_IN_NAND
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET 0x80000
+#elif defined(CONFIG_FSL_ENV_IN_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#else
+ #define CONFIG_ENV_IS_NOWHERE 1
+#endif
+
+#define CONFIG_ENV_SECT_SIZE (256 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH driver setup
+ */
+#define CONFIG_SYS_NO_FLASH
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+
+/*
+ * JFFS2 partitions TODO:
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand0"
+
+#endif /* __CONFIG_H */
+
--- /dev/null
+/*
+ * (C) Copyright 2009-2010 Freescale Semiconductor
+ *
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Kshitij Gupta <kshitij@ti.com>
+ *
+ * Configuration settings for the Freescale i.MX31 PDK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx25.h>
+#include <asm/arch/mx25-regs.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARM926EJS 1 /* This is an arm1136 CPU core */
+#define CONFIG_MX25 1 /* in a mx31 */
+#define CONFIG_MX25_HCLK_FREQ 24000000
+#define CONFIG_MX25_CLK32 32768
+
+#define CONFIG_MFG 1
+#define CONFIG_IMX_CSPI 1
+#define IMX_CSPI_VER_0_7 1
+#define CONFIG_IMX_SPI_CPLD
+
+/* IF iMX25 3DS V-1.0 define it */
+/* #define CONFIG_MX25_3DS_V10 */
+
+#ifdef CONFIG_MX25_3DS_V10
+#define MXC_MEMORY_MDDR
+#endif
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define BOARD_LATE_INIT
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/* No support for NAND boot for i.MX31 PDK yet, so we rely on some other
+ * program to initialize the SDRAM.
+ */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C1_BASE
+#define CONFIG_SYS_I2C_SPEED 40000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+#define CONFIG_MX25_UART 1
+#define CONFIG_MX25_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+/* #define CONFIG_CMD_SPI */
+/* #define CONFIG_CMD_DATE */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MMC
+#define CONFIG_MXC_NAND
+
+/*
+ * MMC Configs
+ * */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC 1
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_SYS_FSL_ESDHC_NUM 2
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_IMX_ESDHC_V1
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+#endif
+
+/* Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
+ * that CONFIG_NO_FLASH is undefined).
+ */
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_LOADADDR 0x80100000 /* loadaddr env var */
+
+#define CONFIG_BOOTAGS "console=ttymxc0,115200 "\
+ "rdinit=/linuxrc"
+#define CONFIG_BOOTCOMMAND "bootm ${loadaddr} 0x80800000"
+#define CONFIG_ENV_IS_EMBEDDED
+
+/*
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=smc911x-0\0" \
+ "uboot=u-boot.bin\0" \
+ "uboot_addr=0xa0000000\0" \
+ "kernel=uImage\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
+ "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
+ "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "load_uboot=tftpboot ${loadaddr} ${uboot}\0"
+*/
+
+/*Support LAN9217*/
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_CPLD
+#define CONFIG_SMC911X_BASE 0
+
+#define CONFIG_HAS_ETH1
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#define CONFIG_NET_MULTI
+#define CONFIG_ETHPRIME
+
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_MII_GASKET
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC0_IOBASE FEC_BASE
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR 0x1F
+#define CONFIG_FEC0_MIIBASE -1
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "MX25 U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* default load address */
+
+#define CONFIG_SYS_HZ 1000
+
+#define UBOOT_IMAGE_SIZE 0x40000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE
+
+/* iMX25 V-1.0 has 128MB but V-1.1 has only 64MB */
+#ifdef CONFIG_MX25_3DS_V10
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+#else
+#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
+#endif
+
+/* Monitor at beginning of flash */
+/* #define CONFIG_FSL_ENV_IN_MMC */
+/*#define CONFIG_FSL_ENV_IN_NAND*/
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+/*
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET 0x80000
+#elif defined(CONFIG_FSL_ENV_IN_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#else
+ #define CONFIG_ENV_IS_NOWHERE 1
+#endif
+*/
+
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_ENV_SECT_SIZE (256 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH driver setup
+ */
+#define CONFIG_SYS_NO_FLASH
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+
+/*
+ * JFFS2 partitions TODO:
+ */
+/*
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand0"
+*/
+#endif /* __CONFIG_H */
+
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __MX28_EVK_H
+#define __MX28_EVK_H
+
+#include <asm/arch/mx28.h>
+
+/*
+ * SoC configurations
+ */
+#define CONFIG_MX28 /* i.MX28 SoC */
+#define CONFIG_MX28_TO1_2
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+/* ROM loads UBOOT into DRAM */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x40000000 /* Base address */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define CONFIG_STACKSIZE 0x00020000 /* 128 KB stack */
+#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Reserved for initial data */
+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start address */
+#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_PROMPT "MX28 U-Boot > "
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttyAM0,115200n8 "
+#define CONFIG_BOOTCOMMAND "run bootcmd_net"
+#define CONFIG_LOADADDR 0x42000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "nfsroot=/home/notroot/nfs/rootfs\0" \
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
+ "fec_mac=${ethaddr}\0" \
+ "bootcmd_net=run bootargs_nfs; dhcp; bootm\0" \
+ "bootargs_mmc=setenv bootargs ${bootargs} root=/dev/mmcblk0p3 " \
+ "rw rootwait ip=dhcp fec_mac=${ethaddr}\0" \
+ "bootcmd_mmc=run bootargs_mmc; " \
+ "mmc read 0 ${loadaddr} 100 3000; bootm\0" \
+
+/*
+ * U-Boot Commands
+ */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_UARTDBG_CLK 24000000
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * FEC Driver
+ */
+#define CONFIG_MXC_FEC
+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#define CONFIG_FEC0_IOBASE REGS_ENET_BASE
+#define CONFIG_FEC0_PHY_ADDR 0
+#define CONFIG_NET_MULTI
+#define CONFIG_ETH_PRIME
+#define CONFIG_RMII
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_IPADDR 192.168.1.103
+#define CONFIG_SERVERIP 192.168.1.101
+#define CONFIG_NETMASK 255.255.255.0
+/* Add for working with "strict" DHCP server */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+/*
+ * MMC Driver
+ */
+#define CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_IMX_SSP_MMC /* MMC driver based on SSP */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_SYS_SSP_MMC_NUM 2
+
+/*
+ * Environments on MMC
+ */
+#define CONFIG_CMD_ENV
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_MMC
+/* Assoiated with the MMC layout defined in mmcops.c */
+#define CONFIG_ENV_OFFSET (0x400) /* 1 KB */
+#define CONFIG_ENV_SIZE (0x20000 - 0x400) /* 127 KB */
+#define CONFIG_DYNAMIC_MMC_DEVNO
+
+/* The global boot mode will be detected by ROM code and
+ * a boot mode value will be stored at fixed address:
+ * TO1.0 addr 0x0001a7f0
+ * TO1.2 addr 0x00019BF0
+ */
+#ifndef MX28_EVK_TO1_0
+ #define GLOBAL_BOOT_MODE_ADDR 0x00019BF0
+#else
+ #define GLOBAL_BOOT_MODE_ADDR 0x0001a7f0
+#endif
+#define BOOT_MODE_SD0 0x9
+#define BOOT_MODE_SD1 0xa
+
+#endif /* __MX28_EVK_H */
--- /dev/null
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Configuration settings for the MX31 3Stack Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx31-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MX31 1 /* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ 26000000
+#define CONFIG_MX31_CLK32 32768
+
+#define CONFIG_MX31_NAND
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MXC_UART 1
+#define CONFIG_SYS_MX31_UART1 1
+
+#define CONFIG_MXC_SPI 1
+
+#define CONFIG_RTC_MC13783 1
+#define CONFIG_MC13783_SPI_BUS 1
+#define CONFIG_MC13783_SPI_CS 0
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_NAND
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "loadaddr=0x80010000\0" \
+ "tftp_server=10.192.225.58\0" \
+ "serverip=10.192.225.211\0" \
+ "nfsroot=/tools/rootfs/rootfs-2.6.24\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot} rw\0" \
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${tftp_server}:${kernel}; bootm\0"
+
+/* configure for smc91xx debug board ethernet */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_16_BIT 1
+#define CONFIG_SMC911X_BASE CS5_BASE
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "MX31 U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ CONFIG_MX31_CLK32
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+/*
+ * TODO: NAND Flash configure
+ */
+
+#define CONFIG_SYS_NO_FLASH
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_OFFSET 0x40000 /* 2nd block */
+#define CONFIG_ENV_SIZE (128*1024)
+/*
+ * JFFS2 partitions TODO:
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand0"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX31ADS Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx35.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MXC 1
+#define CONFIG_MX35 1 /* in a mx31 */
+#define CONFIG_MX35_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant increase
+ * in the final file size: 144260 vs. 109536 Bytes.
+ */
+#if 0
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#endif
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+#define CONFIG_MX35_UART UART1_BASE_ADDR
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+/*#define CONFIG_CMD_SPI*/
+/*#define CONFIG_CMD_DATE*/
+#define CONFIG_CMD_NAND
+#define CONFIG_MXC_NAND
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=smc911x\0" \
+ "uboot_addr=0xa0000000\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "nfsroot=/opt/eldk/arm\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
+ "protect off ${uboot_addr} 0xa003ffff; " \
+ "erase ${uboot_addr} 0xa003ffff; " \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
+ "setenv filesize; saveenv\0"
+
+/*Support LAN9217*/
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_16_BIT 1
+#define CONFIG_SMC911X_BASE CS5_BASE_ADDR
+
+#define CONFIG_HAS_ETH1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_ETHPRIME
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR 0x1F
+#define CONFIG_FEC0_MIIBASE -1
+
+/*
+ * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
+ * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
+ * controller inverted. The controller is capable of detecting and correcting
+ * this, but it needs 4 network packets for that. Which means, at startup, you
+ * will not receive answers to the first 4 packest, unless there have been some
+ * broadcasts on the network, or your board is on a hub. Reducing the ARP
+ * timeout from default 5 seconds to 200ms we speed up the initial TFTP
+ * transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "MX35 U-Boot > "
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 256KiB */
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (2 * 1024 * 1024)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+/*
+ * S29WS256N NOR flash has 4 32KiB small sectors at the beginning and at the
+ * end. The rest of 32MiB is in 128KiB big sectors. U-Boot occupies the low
+ * 4 sectors, if we put environment next to it, we will have to occupy 128KiB
+ * for it. Putting it at the top of flash we use only 32KiB.
+ */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
+
+#if defined(CONFIG_CMD_NAND)
+ #define CONFIG_FSL_ENV_IN_NAND
+#else
+ #define CONFIG_ENV_IS_IN_FLASH 1
+#endif
+
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET (1024 * 1024)
+#elif defined(CONFIG_FSL_ENV_IS_IN_FLASH)
+ #define CONFIG_ENV_IS_IN_FLASH 1
+#endif
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI 1/* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER 1/* Use drivers/cfi_flash.c */
+/* A non-standard buffered write algorithm */
+#define CONFIG_FLASH_SPANSION_S29WS_N 1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION 1/* Use hardware sector protection */
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH driver setup
+ */
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX35 3stack Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx35.h>
+/* for mfg firmware */
+#define CONFIG_MFG
+#define CONFIG_BOOTARGS "console=ttymxc0,115200 rdinit=/linuxrc"
+#define CONFIG_ENV_IS_NOWHERE
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MXC 1
+#define CONFIG_MX35 1 /* in a mx31 */
+#define CONFIG_MX35_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian
+ * and a significant increase
+ * in the final file size: 144260 vs. 109536 Bytes.
+ */
+#if 0
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#endif
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+#define CONFIG_MX35_UART UART1_BASE_ADDR
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+/*#define CONFIG_CMD_SPI*/
+/*#define CONFIG_CMD_DATE*/
+/*#define CONFIG_CMD_NAND*/
+#define CONFIG_CMD_ENV
+/* #define CONFIG_CMD_MMC */
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_LOADADDR 0x80100000 /* loadaddr env var */
+#define CONFIG_BOOTCOMMAND "bootm ${loadaddr} 0x80800000"
+/*Support LAN9217*/
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_16_BIT 1
+#define CONFIG_SMC911X_BASE CS5_BASE_ADDR
+
+#define CONFIG_HAS_ETH1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_ETHPRIME
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR 0x1F
+#define CONFIG_FEC0_MIIBASE -1
+
+/*
+ * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
+ * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
+ * controller inverted. The controller is capable of detecting and correcting
+ * this, but it needs 4 network packets for that. Which means, at startup, you
+ * will not receive answers to the first 4 packest, unless there have been some
+ * broadcasts on the network, or your board is on a hub. Reducing the ARP
+ * timeout from default 5 seconds to 200ms we speed up the initial TFTP
+ * transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "MX35 U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*
+ * MMC Configs
+ * */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC 1
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_SYS_FSL_ESDHC_NUM 2
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+#endif
+
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_CMD_FAT 1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 256KiB */
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+/*
+ * S29WS256N NOR flash has 4 32KiB small sectors at the beginning and at the
+ * end. The rest of 32MiB is in 128KiB big sectors. U-Boot occupies the low
+ * 4 sectors, if we put environment next to it, we will have to occupy 128KiB
+ * for it. Putting it at the top of flash we use only 32KiB.
+ */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
+
+#if defined(CONFIG_CMD_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#elif defined(CONFIG_CMD_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET 0x100000
+#else
+ #define CONFIG_ENV_IS_IN_FLASH 1
+#endif
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI 1/* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER 1/* Use drivers/cfi_flash.c */
+/* A non-standard buffered write algorithm */
+#define CONFIG_FLASH_SPANSION_S29WS_N 1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION 1/* Use hardware sector protection */
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH driver setup
+ */
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX31ADS Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx35.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_MXC 1
+#define CONFIG_MX35 1 /* in a mx31 */
+#define CONFIG_MX35_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant increase
+ * in the final file size: 144260 vs. 109536 Bytes.
+ */
+#if 0
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#endif
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+#define CONFIG_MX35_UART UART1_BASE_ADDR
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+/*#define CONFIG_CMD_SPI*/
+/*#define CONFIG_CMD_DATE*/
+/*#define CONFIG_CMD_NAND*/
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MMC
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=smc911x\0" \
+ "uboot_addr=0xa0000000\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "nfsroot=/opt/eldk/arm\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
+ "protect off ${uboot_addr} 0xa003ffff; " \
+ "erase ${uboot_addr} 0xa003ffff; " \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
+ "setenv filesize; saveenv\0"
+
+/*Support LAN9217*/
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_16_BIT 1
+#define CONFIG_SMC911X_BASE CS5_BASE_ADDR
+
+#define CONFIG_HAS_ETH1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_ETHPRIME
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR 0x1F
+#define CONFIG_FEC0_MIIBASE -1
+
+/*
+ * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
+ * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
+ * controller inverted. The controller is capable of detecting and correcting
+ * this, but it needs 4 network packets for that. Which means, at startup, you
+ * will not receive answers to the first 4 packest, unless there have been some
+ * broadcasts on the network, or your board is on a hub. Reducing the ARP
+ * timeout from default 5 seconds to 200ms we speed up the initial TFTP
+ * transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "MX35 U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*
+ * MMC Configs
+ * */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC 1
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_SYS_FSL_ESDHC_NUM 2
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+#endif
+
+#define CONFIG_FLASH_HEADER 1
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+#define CONFIG_FLASH_HEADER_BARKER 0xB1
+
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_CMD_FAT 1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 256KiB */
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+/*
+ * S29WS256N NOR flash has 4 32KiB small sectors at the beginning and at the
+ * end. The rest of 32MiB is in 128KiB big sectors. U-Boot occupies the low
+ * 4 sectors, if we put environment next to it, we will have to occupy 128KiB
+ * for it. Putting it at the top of flash we use only 32KiB.
+ */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
+
+#if defined(CONFIG_CMD_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#elif defined(CONFIG_CMD_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET 0x100000
+#else
+ #define CONFIG_ENV_IS_IN_FLASH 1
+#endif
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI 1/* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER 1/* Use drivers/cfi_flash.c */
+/* A non-standard buffered write algorithm */
+#define CONFIG_FLASH_SPANSION_S29WS_N 1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION 1/* Use hardware sector protection */
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH driver setup
+ */
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX50-ARM2 Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx50.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_MXC
+#define CONFIG_MX50
+#define CONFIG_MX50_ARM2
+#define CONFIG_FLASH_HEADER
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+
+#define CONFIG_MX50_HCLK_FREQ 24000000
+#define CONFIG_SYS_PLL2_FREQ 400
+#define CONFIG_SYS_AHB_PODF 2
+#define CONFIG_SYS_AXIA_PODF 0
+#define CONFIG_SYS_AXIB_PODF 1
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MX50_UART 1
+#define CONFIG_MX50_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+#define CONFIG_NET_MULTI 1
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_ENV
+
+/*#define CONFIG_CMD */
+#define CONFIG_REF_CLK_FREQ CONFIG_MX50_HCLK_FREQ
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
+#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "nfsroot=/opt/eldk/arm\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \
+ "root=/dev/mmcblk0p2 rootwait\0" \
+ "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \
+ "bootcmd=run bootcmd_net\0" \
+
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "ARM2 U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR -1
+#define CONFIG_FEC0_MIIBASE -1
+
+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_MII_GASKET
+#define CONFIG_DISCOVER_PHY
+
+/*
+#define CONFIG_SPLASH_SCREEN
+*/
+
+/*
+ * SPLASH SCREEN Configs
+ */
+#ifdef CONFIG_SPLASH_SCREEN
+ #define CONFIG_LCD
+ #undef LCD_TEST_PATTERN
+ #define CONFIG_FB_BASE (TEXT_BASE + 0x300000)
+ #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+ /* #define CONFIG_SPLASH_IS_IN_MMC 1 */
+ #define LCD_BPP LCD_MONOCHROME
+ /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
+
+ #define CONFIG_MXC_EPDC 1
+
+ #define CONFIG_WORKING_BUF_ADDR (TEXT_BASE + 0x100000)
+ #define CONFIG_WAVEFORM_BUF_ADDR (TEXT_BASE + 0x200000)
+ #define CONFIG_WAVEFORM_FILE_OFFSET 0x100000
+ #define CONFIG_WAVEFORM_FILE_SIZE 0xB4000
+ #define CONFIG_WAVEFORM_FILE_IN_MMC
+#endif
+
+#ifdef CONFIG_SPLASH_IS_IN_MMC
+ #define CONFIG_SPLASH_IMG_OFFSET 0x4c000
+ #define CONFIG_SPLASH_IMG_SIZE 0x19000
+#endif
+
+/*
+ * I2C Configs
+ */
+#define CONFIG_CMD_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+
+/*
+ * SPI Configs
+ */
+#define CONFIG_FSL_SF 1
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_IMX_ATMEL 1
+#define CONFIG_SPI_FLASH_CS 1
+#define CONFIG_IMX_CSPI
+#define IMX_CSPI_VER_0_7 1
+#define MAX_SPI_BYTES (8 * 4)
+#define CONFIG_IMX_SPI_PMIC
+#define CONFIG_IMX_SPI_PMIC_CS 0
+
+/*
+ * MMC Configs
+ */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC 1
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_SYS_FSL_ESDHC_NUM 3
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+ #define CONFIG_CMD_EXT2 1
+
+ /* detect whether ESDHC1, ESDHC2, or ESDHC3 is boot device */
+ #define CONFIG_DYNAMIC_MMC_DEVNO
+
+ #define CONFIG_BOOT_PARTITION_ACCESS
+ #define CONFIG_EMMC_DDR_MODE
+
+ /* Indicate to esdhc driver which ports support 8-bit data */
+ #define CONFIG_MMC_8BIT_PORTS 0x6 /* ports 1 and 2 */
+
+#endif
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Monitor at beginning of flash */
+#define CONFIG_FSL_ENV_IN_MMC
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET 0x100000
+#elif defined(CONFIG_FSL_ENV_IN_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#elif defined(CONFIG_FSL_ENV_IN_SF)
+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
+ #define CONFIG_ENV_SPI_CS 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#else
+ #define CONFIG_ENV_IS_NOWHERE 1
+#endif
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX50-ARM2 Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx50.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */
+
+#define CONFIG_MXC
+#define CONFIG_MX50
+#define CONFIG_MX50_ARM2
+#define CONFIG_FLASH_HEADER
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+*/
+
+#define CONFIG_MX50_HCLK_FREQ 24000000
+#define CONFIG_SYS_PLL2_FREQ 600
+#define CONFIG_SYS_AHB_PODF 4
+#define CONFIG_SYS_AXIA_PODF 1
+#define CONFIG_SYS_AXIB_PODF 2
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define BOARD_LATE_INIT
+
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (3 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MX50_UART 1
+#define CONFIG_MX50_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#define CONFIG_CMD_BDI /* bdinfo */
+#define CONFIG_CMD_BOOTD /* bootd */
+#define CONFIG_CMD_CONSOLE /* coninfo */
+#define CONFIG_CMD_RUN /* run command in env variable */
+
+/*
+ * SPI Configs
+ * */
+
+/*
+ * MMC Configs
+ * */
+/*
+ * Eth Configs
+ */
+
+
+/* Enable below configure when supporting nand */
+#define CONFIG_CMD_ENV
+
+#define CONFIG_REF_CLK_FREQ CONFIG_MX50_HCLK_FREQ
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
+#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
+
+#define CONFIG_BOOTARGS "console=ttymxc0,115200 "\
+ "rdinit=/linuxrc"
+
+#define CONFIG_BOOTCOMMAND "bootm"
+#define CONFIG_ENV_IS_EMBEDDED
+/*
+ * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under
+ * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
+ * controller inverted. The controller is capable of detecting and correcting
+ * this, but it needs 4 network packets for that. Which means, at startup, you
+ * will not receive answers to the first 4 packest, unless there have been some
+ * broadcasts on the network, or your board is on a hub. Reducing the ARP
+ * timeout from default 5 seconds to 200ms we speed up the initial TFTP
+ * transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_PROMPT "ARM2 U-Boot > "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (6 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+/* TO1 boards */
+/* #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) */
+#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Monitor at beginning of flash */
+/* #define CONFIG_FSL_ENV_IN_SF
+*/
+/* #define CONFIG_FSL_ENV_IN_MMC */
+
+#define CONFIG_ENV_SECT_SIZE (1 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_IS_NOWHERE
+
+/*
+ * JFFS2 partitions
+ */
+/*
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand0"
+*/
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX50-ARM2 Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx50.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_MXC
+#define CONFIG_MX50
+#define CONFIG_MX50_ARM2
+#define CONFIG_LPDDR2
+#define CONFIG_FLASH_HEADER
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+
+#define CONFIG_MX50_HCLK_FREQ 24000000
+#define CONFIG_SYS_PLL2_FREQ 400
+#define CONFIG_SYS_AHB_PODF 2
+#define CONFIG_SYS_AXIA_PODF 0
+#define CONFIG_SYS_AXIB_PODF 1
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MX50_UART 1
+#define CONFIG_MX50_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+#define CONFIG_NET_MULTI 1
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_ENV
+
+/*#define CONFIG_CMD */
+#define CONFIG_REF_CLK_FREQ CONFIG_MX50_HCLK_FREQ
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
+#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "nfsroot=/opt/eldk/arm\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \
+ "root=/dev/mmcblk0p2 rootwait\0" \
+ "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \
+ "bootcmd=run bootcmd_net\0" \
+
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "ARM2 U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR -1
+#define CONFIG_FEC0_MIIBASE -1
+
+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_MII_GASKET
+#define CONFIG_DISCOVER_PHY
+
+/*
+#define CONFIG_SPLASH_SCREEN
+*/
+
+/*
+ * SPLASH SCREEN Configs
+ */
+#ifdef CONFIG_SPLASH_SCREEN
+ #define CONFIG_LCD
+ #undef LCD_TEST_PATTERN
+ #define CONFIG_FB_BASE (TEXT_BASE + 0x300000)
+ #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+ /* #define CONFIG_SPLASH_IS_IN_MMC 1 */
+ #define LCD_BPP LCD_MONOCHROME
+ /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
+
+ #define CONFIG_MXC_EPDC 1
+
+ #define CONFIG_WORKING_BUF_ADDR (TEXT_BASE + 0x100000)
+ #define CONFIG_WAVEFORM_BUF_ADDR (TEXT_BASE + 0x200000)
+ #define CONFIG_WAVEFORM_FILE_OFFSET 0x100000
+ #define CONFIG_WAVEFORM_FILE_SIZE 0xB4000
+ #define CONFIG_WAVEFORM_FILE_IN_MMC
+#endif
+
+#ifdef CONFIG_SPLASH_IS_IN_MMC
+ #define CONFIG_SPLASH_IMG_OFFSET 0x4c000
+ #define CONFIG_SPLASH_IMG_SIZE 0x19000
+#endif
+
+/*
+ * I2C Configs
+ */
+#define CONFIG_CMD_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+
+/*
+ * SPI Configs
+ */
+#define CONFIG_FSL_SF 1
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_IMX_ATMEL 1
+#define CONFIG_SPI_FLASH_CS 1
+#define CONFIG_IMX_CSPI
+#define IMX_CSPI_VER_0_7 1
+#define MAX_SPI_BYTES (8 * 4)
+#define CONFIG_IMX_SPI_PMIC
+#define CONFIG_IMX_SPI_PMIC_CS 0
+
+/*
+ * MMC Configs
+ */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC 1
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_SYS_FSL_ESDHC_NUM 3
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+ #define CONFIG_CMD_EXT2 1
+
+ /* detect whether ESDHC1, ESDHC2, or ESDHC3 is boot device */
+ #define CONFIG_DYNAMIC_MMC_DEVNO
+
+ #define CONFIG_BOOT_PARTITION_ACCESS
+ #define CONFIG_EMMC_DDR_MODE
+
+ /* Indicate to esdhc driver which ports support 8-bit data */
+ #define CONFIG_MMC_8BIT_PORTS 0x6 /* ports 1 and 2 */
+
+
+#endif
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Monitor at beginning of flash */
+#define CONFIG_FSL_ENV_IN_MMC
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET 0x100000
+#elif defined(CONFIG_FSL_ENV_IN_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#elif defined(CONFIG_FSL_ENV_IN_SF)
+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
+ #define CONFIG_ENV_SPI_CS 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#else
+ #define CONFIG_ENV_IS_NOWHERE 1
+#endif
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX50-ARM2 Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx50.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_MFG
+#define CONFIG_MXC
+#define CONFIG_MX50
+#define CONFIG_MX50_ARM2
+#define CONFIG_FLASH_HEADER
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+
+#define CONFIG_MX50_HCLK_FREQ 24000000
+#define CONFIG_SYS_PLL2_FREQ 400
+#define CONFIG_SYS_AHB_PODF 2
+#define CONFIG_SYS_AXIA_PODF 0
+#define CONFIG_SYS_AXIB_PODF 1
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MX50_UART 1
+#define CONFIG_MX50_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+#define CONFIG_NET_MULTI 1
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+/* #define CONFIG_CMD_MMC */
+/* #define CONFIG_CMD_ENV */
+
+/*#define CONFIG_CMD */
+#define CONFIG_REF_CLK_FREQ CONFIG_MX50_HCLK_FREQ
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
+#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
+
+#define CONFIG_BOOTARGS "console=ttymxc0,115200 "\
+ "rdinit=/linuxrc"
+#define CONFIG_BOOTCOMMAND "bootm 0x70800000 0x70B00000"
+#define CONFIG_ENV_IS_EMBEDDED
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "nfsroot=/opt/eldk/arm\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \
+ "root=/dev/mmcblk0p2 rootwait\0" \
+ "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \
+ "bootcmd=run bootcmd_net\0" \
+
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "ARM2 MFG U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR -1
+#define CONFIG_FEC0_MIIBASE -1
+
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_MII_GASKET
+#define CONFIG_DISCOVER_PHY
+
+/*
+ * I2C Configs
+ */
+#define CONFIG_CMD_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+
+/*
+ * SPI Configs
+ */
+#define CONFIG_FSL_SF 1
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_IMX_ATMEL 1
+#define CONFIG_SPI_FLASH_CS 1
+#define CONFIG_IMX_CSPI
+#define IMX_CSPI_VER_0_7 1
+#define MAX_SPI_BYTES (8 * 4)
+#define CONFIG_IMX_SPI_PMIC
+#define CONFIG_IMX_SPI_PMIC_CS 0
+
+/*
+ * MMC Configs
+ */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC 1
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_SYS_FSL_ESDHC_NUM 3
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+ #define CONFIG_CMD_EXT2 1
+
+ /* detect whether ESDHC1 or ESDHC3 is boot device */
+ #define CONFIG_DYNAMIC_MMC_DEVNO
+
+ #define CONFIG_BOOT_PARTITION_ACCESS
+
+#endif
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Monitor at beginning of flash */
+/* #define CONFIG_FSL_ENV_IN_MMC */
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET 0x100000
+#elif defined(CONFIG_FSL_ENV_IN_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#elif defined(CONFIG_FSL_ENV_IN_SF)
+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
+ #define CONFIG_ENV_SPI_CS 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#else
+ #define CONFIG_ENV_IS_NOWHERE 1
+#endif
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX51-3Stack Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx51.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */
+#define CONFIG_SYS_APCS_GNU
+
+#define CONFIG_MXC 1
+#define CONFIG_MX51_3DS 1 /* in a mx51 */
+#define CONFIG_FLASH_HEADER 1
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+#define CONFIG_FLASH_HEADER_BARKER 0xB1
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MX51_UART 1
+#define CONFIG_MX51_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+/* Enable below configure when supporting nand */
+#define CONFIG_CMD_NAND
+#define CONFIG_MXC_NAND
+#define CONFIG_CMD_ENV
+#define CMD_SAVEENV
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_IIM
+
+/*
+ * FUSE Configs
+ * */
+#ifdef CONFIG_CMD_IIM
+ #define CONFIG_IMX_IIM
+ #define IMX_IIM_BASE IIM_BASE_ADDR
+ #define CONFIG_IIM_MAC_BANK 1
+ #define CONFIG_IIM_MAC_ROW 9
+#endif
+
+/*
+ * MMC Configs
+ */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC 1
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+ #define CONFIG_SYS_FSL_ESDHC_NUM 1
+#endif
+
+/*
+ * I2C Configs
+ */
+#define CONFIG_CMD_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+/*
+ * Eth Configs
+ */
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETHPRIME
+#define CONFIG_NET_RETRY_COUNT 100
+#define CONFIG_NET_MULTI
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR 0x1F
+#define CONFIG_FEC0_MIIBASE -1
+
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=smc911x\0" \
+ "uboot_addr=0xa0000000\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "nfsroot=/opt/eldk/arm\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
+ "protect off ${uboot_addr} 0xa003ffff; " \
+ "erase ${uboot_addr} 0xa003ffff; " \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
+ "setenv filesize; saveenv\0"
+
+/*Support LAN9217*/
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_16_BIT 1
+#define CONFIG_SMC911X_BASE mx51_io_base_addr
+
+/*
+ * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under
+ * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
+ * controller inverted. The controller is capable of detecting and correcting
+ * this, but it needs 4 network packets for that. Which means, at startup, you
+ * will not receive answers to the first 4 packest, unless there have been some
+ * broadcasts on the network, or your board is on a hub. Reducing the ARP
+ * timeout from default 5 seconds to 200ms we speed up the initial TFTP
+ * transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "MX51 U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH driver setup
+ */
+#define NAND_MAX_CHIPS 8
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_NAND_FW_16BIT 0 /* 1: 16bit 0: 8bit */
+
+/* Monitor at beginning of flash */
+#define CONFIG_FSL_ENV_IN_NAND
+/* #define CONFIG_FSL_ENV_IN_NAND */
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET 0x100000
+#elif defined(CONFIG_FSL_ENV_IN_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#else
+ #define CONFIG_ENV_IS_NOWHERE 1
+#endif
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand0"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX51-3Stack Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx51.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */
+#define CONFIG_SYS_APCS_GNU
+
+#define CONFIG_MXC 1
+#define CONFIG_MX51_3DS 1 /* in a mx51 */
+#define CONFIG_FLASH_HEADER 1
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+#define CONFIG_FLASH_HEADER_BARKER 0xB1
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 4 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MX51_UART 1
+#define CONFIG_MX51_UART1 1
+
+/*
+ * SPI Configs
+ * */
+/*
+#define CONFIG_FSL_SF 1
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_IMX_ATMEL 1
+#define CONFIG_SPI_FLASH_CS 1
+#define CONFIG_IMX_ECSPI
+#define CONFIG_IMX_SPI_PMIC
+#define CONFIG_IMX_SPI_PMIC_CS 0
+#define IMX_CSPI_VER_2_3 1
+#define MAX_SPI_BYTES (64 * 4)
+*/
+
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=nand0"
+#define MTDPARTS_DEFAULT "mtdparts=nand0:0x700000@0x0(BOOT),0x100000@0x700000(MISC),0x1400000@0x800000(RECOVERY),-@0x1c00000(ROOT)"
+#define MTD_ACTIVE_PART "nand0,3"
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+/*
+ * Android support Configs
+ */
+#include <asm/arch/keypad.h>
+
+#define CONFIG_FSL_ANDROID
+
+#define CONFIG_MXC_KPD
+#define CONFIG_MXC_KEYMAPPING \
+ { \
+ KEY_1, KEY_2, KEY_3, KEY_F1, KEY_UP, KEY_F2, \
+ KEY_4, KEY_5, KEY_6, KEY_LEFT, KEY_SELECT, KEY_RIGHT, \
+ KEY_7, KEY_8, KEY_9, KEY_F3, KEY_DOWN, KEY_F4, \
+ KEY_0, KEY_OK, KEY_ESC, KEY_ENTER, KEY_MENU, KEY_BACK, \
+ }
+#define CONFIG_MXC_KPD_COLMAX 6
+#define CONFIG_MXC_KPD_ROWMAX 4
+#define CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC \
+ "setenv bootargs ${bootargs} root=/dev/mmcblk0p4 ip=off init=/init rootfstype=ext3"
+#define CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC \
+ "run bootargs_base bootargs_android;mmc read 0 ${loadaddr} 0x800 0x1280;bootm"
+#define CONFIG_ANDROID_RECOVERY_BOOTARGS_NAND \
+ "setenv bootargs ${bootargs} ip=off rootfstype=ubifs root=ubi1:recovery init=/init ubi.mtd=3 ubi.mtd=2"
+#define CONFIG_ANDROID_RECOVERY_BOOTCMD_NAND \
+ "run bootargs_base bootargs_android;nand read ${loadaddr} 0x300000 0x250000;bootm"
+#define CONFIG_ANDROID_RECOVERY_CMD_FILE "/recovery/command"
+#define CONFIG_ANDROID_BOOTMOD_DELAY 3
+#define CONFIG_ANDROID_CACHE_PARTITION_MMC 6
+#define CONFIG_ANDROID_UBIFS_PARTITION_NM "ROOT"
+#define CONFIG_ANDROID_CACHE_PARTITION_NAND "cache"
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+/* Enable below configure when supporting nand */
+#define CONFIG_CMD_NAND
+#define CONFIG_MXC_NAND
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_ENV
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
+#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=smc911x\0" \
+ "uboot_addr=0xa0000000\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "rd_loadaddr=0x90B00000\0" \
+ "nfsroot=/opt/eldk/arm\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootargs_android=setenv bootargs ${bootargs} ip=dhcp mem=480M init=/init wvga calibration\0" \
+ "bootcmd=run bootcmd_android\0" \
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "bootcmd_android=run bootargs_base bootargs_android; " \
+ "mmc read 0 ${loadaddr} 0x800 0x1280; " \
+ "mmc read 0 ${rd_loadaddr} 0x2000 0x258; " \
+ "bootm ${loadaddr} ${rd_loadaddr}\0" \
+ "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
+ "protect off ${uboot_addr} 0xa003ffff; " \
+ "erase ${uboot_addr} 0xa003ffff; " \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
+ "setenv filesize; saveenv\0"
+
+/*Support LAN9217*/
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_16_BIT 1
+#define CONFIG_SMC911X_BASE mx51_io_base_addr
+
+/*
+ * MMC Configs
+ * */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC 1
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_SYS_FSL_ESDHC_NUM 2
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+ #define CONFIG_CMD_EXT2 1
+ #define CONFIG_SYS_FSL_ESDHC_NUM 1
+#endif
+
+/*
+ * Eth Configs
+ */
+#define CONFIG_HAS_ETH1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_ETHPRIME
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR 0x1F
+#define CONFIG_FEC0_MIIBASE -1
+
+/*
+ * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under
+ * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
+ * controller inverted. The controller is capable of detecting and correcting
+ * this, but it needs 4 network packets for that. Which means, at startup, you
+ * will not receive answers to the first 4 packest, unless there have been some
+ * broadcasts on the network, or your board is on a hub. Reducing the ARP
+ * timeout from default 5 seconds to 200ms we speed up the initial TFTP
+ * transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "MX51 U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH driver setup
+ */
+#define NAND_MAX_CHIPS 8
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+
+/* Monitor at beginning of flash */
+/* #define CONFIG_FSL_ENV_IN_MMC */
+#define CONFIG_FSL_ENV_IN_NAND
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET 0x100000
+#elif defined(CONFIG_FSL_ENV_IN_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#elif defined(CONFIG_FSL_ENV_IN_SF)
+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
+ #define CONFIG_ENV_SPI_CS 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#else
+ #define CONFIG_ENV_IS_NOWHERE 1
+#endif
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand0"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX51-3Stack Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx51.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */
+
+#define CONFIG_MXC 1
+#define CONFIG_MX51_BBG 1 /* in a mx51 */
+#define CONFIG_FLASH_HEADER 1
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+#define CONFIG_FLASH_HEADER_BARKER 0xB1
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MX51_UART 1
+#define CONFIG_MX51_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_IIM
+#define CONFIG_CMD_I2C
+
+/*
+ * FUSE Configs
+ * */
+#ifdef CONFIG_CMD_IIM
+ #define CONFIG_IMX_IIM
+ #define IMX_IIM_BASE IIM_BASE_ADDR
+ #define CONFIG_IIM_MAC_BANK 1
+ #define CONFIG_IIM_MAC_ROW 9
+#endif
+
+/*
+ * SPI Configs
+ * */
+#ifdef CONFIG_CMD_SF
+ #define CONFIG_FSL_SF 1
+ #define CONFIG_SPI_FLASH_IMX_ATMEL 1
+ #define CONFIG_SPI_FLASH_CS 1
+ #define CONFIG_IMX_ECSPI
+ #define IMX_CSPI_VER_2_3 1
+ #define CONFIG_IMX_SPI_PMIC
+ #define CONFIG_IMX_SPI_PMIC_CS 0
+
+ #define MAX_SPI_BYTES (64 * 4)
+#endif
+
+/*
+ * MMC Configs
+ * */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC 1
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_SYS_FSL_ESDHC_NUM 2
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+ #define CONFIG_DYNAMIC_MMC_DEVNO
+#endif
+
+/*
+ * I2C Configs
+ */
+#ifdef CONFIG_CMD_I2C
+ #define CONFIG_HARD_I2C 1
+ #define CONFIG_I2C_MXC 1
+ #define CONFIG_SYS_I2C_PORT I2C1_BASE_ADDR
+ #define CONFIG_SYS_I2C_SPEED 400000
+ #define CONFIG_SYS_I2C_SLAVE 0xfe
+#endif
+
+/*
+ * Eth Configs
+ */
+#define CONFIG_HAS_ETH1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#define CONFIG_IIM_MAC_ADDR_OFFSET 0x24
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR 0x1F
+#define CONFIG_FEC0_MIIBASE -1
+
+
+
+/* Enable below configure when supporting nand */
+#define CONFIG_CMD_ENV
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "uboot_addr=0xa0000000\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "load_uboot=tftpboot ${loadaddr} ${uboot}\0" \
+
+/*
+ * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under
+ * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
+ * controller inverted. The controller is capable of detecting and correcting
+ * this, but it needs 4 network packets for that. Which means, at startup, you
+ * will not receive answers to the first 4 packest, unless there have been some
+ * broadcasts on the network, or your board is on a hub. Reducing the ARP
+ * timeout from default 5 seconds to 200ms we speed up the initial TFTP
+ * transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "BBG U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Monitor at beginning of flash */
+/* #define CONFIG_FSL_ENV_IN_SF */
+#define CONFIG_FSL_ENV_IN_MMC
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+#if defined(CONFIG_FSL_ENV_IN_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#elif defined(CONFIG_FSL_ENV_IN_SF)
+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
+ #define CONFIG_ENV_SPI_CS 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#else
+ #define CONFIG_ENV_IS_NOWHERE 1
+#endif
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand0"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX51-3Stack Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx51.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */
+#define CONFIG_SYS_APCS_GNU
+
+#define CONFIG_MXC 1
+#define CONFIG_MX51_BBG 1 /* in a mx51 */
+#define CONFIG_FLASH_HEADER 1
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+#define CONFIG_FLASH_HEADER_BARKER 0xB1
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MX51_UART 1
+#define CONFIG_MX51_UART1 1
+
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+#define CONFIG_CMD_I2C
+
+/*
+ * Android support Configs
+ */
+#include <asm/arch/keypad.h>
+
+#define CONFIG_FSL_ANDROID
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+
+#define CONFIG_MXC_KPD
+#define CONFIG_MXC_KEYMAPPING \
+ { \
+ KEY_1, KEY_2, KEY_3, KEY_F1, KEY_UP, KEY_F2, \
+ KEY_4, KEY_5, KEY_6, KEY_LEFT, KEY_SELECT, KEY_RIGHT, \
+ KEY_7, KEY_8, KEY_9, KEY_F3, KEY_DOWN, KEY_F4, \
+ KEY_0, KEY_OK, KEY_ESC, KEY_ENTER, KEY_MENU, KEY_BACK, \
+ }
+ /*
+ { \
+ KEY_3, KEY_2, KEY_0, KEY_OK, KEY_ESC, KEY_ENTER,
+ KEY_F1, KEY_4, KEY_6, KEY_5,
+ KEY_LEFT, KEY_1, KEY_ , KEY_8, KEY_9, KEY_RIGHT,
+ }
+ */
+#define CONFIG_MXC_KPD_COLMAX 6
+#define CONFIG_MXC_KPD_ROWMAX 4
+#define CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC \
+ "setenv bootargs ${bootargs} root=/dev/mmcblk0p4 ip=off init=/init rootfstype=ext3 wvga"
+#define CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC \
+ "run bootargs_base bootargs_android;mmc read 0 ${loadaddr} 0x800 0x1280;bootm"
+#define CONFIG_ANDROID_RECOVERY_CMD_FILE "/recovery/command"
+#define CONFIG_ANDROID_BOOTMOD_DELAY 3
+#define CONFIG_ANDROID_CACHE_PARTITION_MMC 6
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+/* Enable below configure when supporting nand */
+/* #define CONFIG_CMD_NAND */
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_ENV
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
+#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "uboot_addr=0xa0000000\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "rd_loadaddr=0x90B00000\0" \
+ "nfsroot=/opt/eldk/arm\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootargs_android=setenv bootargs ${bootargs} ip=dhcp mem=480M init=/init wvga calibration\0" \
+ "bootcmd=run bootcmd_android\0" \
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "bootcmd_android=run bootargs_base bootargs_android; " \
+ "mmcinit;cp.b 0x100000 ${loadaddr} 0x250000; " \
+ "cp.b 0x400000 ${rd_loadaddr} 0x4B000; " \
+ "bootm ${loadaddr} ${rd_loadaddr}\0" \
+ "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
+ "protect off ${uboot_addr} 0xa003ffff; " \
+ "erase ${uboot_addr} 0xa003ffff; " \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
+ "setenv filesize; saveenv\0"
+
+/*Support LAN9217*/
+/*
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_16_BIT 1
+#define CONFIG_SMC911X_BASE mx51_io_base_addr
+*/
+
+/*
+ * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under
+ * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
+ * controller inverted. The controller is capable of detecting and correcting
+ * this, but it needs 4 network packets for that. Which means, at startup, you
+ * will not receive answers to the first 4 packest, unless there have been some
+ * broadcasts on the network, or your board is on a hub. Reducing the ARP
+ * timeout from default 5 seconds to 200ms we speed up the initial TFTP
+ * transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "BBG U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*
+ * Eth Configs
+ */
+#define CONFIG_HAS_ETH1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR 0x1F
+#define CONFIG_FEC0_MIIBASE -1
+
+/*
+ * SPI Configs
+ * */
+#define CONFIG_FSL_SF 1
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_IMX_ATMEL 1
+#define CONFIG_SPI_FLASH_CS 1
+#define CONFIG_IMX_ECSPI
+#define CONFIG_IMX_SPI_PMIC
+#define CONFIG_IMX_SPI_PMIC_CS 0
+#define IMX_CSPI_VER_2_3 1
+
+#define MAX_SPI_BYTES (64 * 4)
+
+/*
+ * MMC Configs
+ * */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC 1
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_SYS_FSL_ESDHC_NUM 2
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+ #define CONFIG_CMD_EXT2 1
+ #define CONFIG_DYNAMIC_MMC_DEVNO
+#endif
+
+/*
+ * I2C Configs
+ */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C1_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH driver setup
+ */
+#define NAND_MAX_CHIPS 8
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+
+/* Monitor at beginning of flash */
+/* #define CONFIG_FSL_ENV_IN_SF */
+#define CONFIG_FSL_ENV_IN_MMC
+/* #define CONFIG_FSL_ENV_IN_NAND */
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET 0x100000
+#elif defined(CONFIG_FSL_ENV_IN_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#elif defined(CONFIG_FSL_ENV_IN_SF)
+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
+ #define CONFIG_ENV_SPI_CS 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#else
+ #define CONFIG_ENV_IS_NOWHERE 1
+#endif
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand0"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX51-3Stack Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx51.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */
+
+#define CONFIG_MFG 1
+#define CONFIG_MXC 1
+#define CONFIG_MX51_BBG 1 /* in a mx51 */
+#define CONFIG_FLASH_HEADER 1
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+#define CONFIG_FLASH_HEADER_BARKER 0xB1
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define BOARD_LATE_INIT
+
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MX51_UART 1
+#define CONFIG_MX51_UART1 1
+
+/*
+ * SPI Configs
+ * */
+#define CONFIG_FSL_SF 1
+#define CONFIG_SPI_FLASH_IMX_ATMEL 1
+#define CONFIG_SPI_FLASH_CS 1
+#define CONFIG_IMX_ECSPI
+#define CONFIG_IMX_SPI_PMIC
+#define CONFIG_IMX_SPI_PMIC_CS 0
+#define IMX_CSPI_VER_2_3 1
+#define MAX_SPI_BYTES (64 * 4)
+
+/*
+ * MMC Configs
+ * */
+
+/*
+ * Eth Configs
+ */
+#define CONFIG_HAS_ETH1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR 0x1F
+#define CONFIG_FEC0_MIIBASE -1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+
+/*
+ * SPI Configs
+ * */
+
+/*
+ * MMC Configs
+ * */
+/*
+ * Eth Configs
+ */
+#define CONFIG_HAS_ETH1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR 0x1F
+#define CONFIG_FEC0_MIIBASE -1
+
+
+
+/* Enable below configure when supporting nand */
+#define CONFIG_CMD_ENV
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x90100000 /* loadaddr env var */
+
+#define CONFIG_BOOTARGS "console=ttymxc0,115200 "\
+ "rdinit=/linuxrc"
+
+#define CONFIG_BOOTCOMMAND "bootm ${loadaddr} 0x90800000"
+#define CONFIG_ENV_IS_EMBEDDED
+/*
+ * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under
+ * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
+ * controller inverted. The controller is capable of detecting and correcting
+ * this, but it needs 4 network packets for that. Which means, at startup, you
+ * will not receive answers to the first 4 packest, unless there have been some
+ * broadcasts on the network, or your board is on a hub. Reducing the ARP
+ * timeout from default 5 seconds to 200ms we speed up the initial TFTP
+ * transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "BBG U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+/* TO1 boards */
+/* #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) */
+#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Monitor at beginning of flash */
+/* #define CONFIG_FSL_ENV_IN_SF
+*/
+/* #define CONFIG_FSL_ENV_IN_MMC */
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_IS_NOWHERE
+
+/*
+ * JFFS2 partitions
+ */
+/*
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nand0"
+*/
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53-ARM2 Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx53.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU core */
+#define CONFIG_MXC
+#define CONFIG_MX53
+#define CONFIG_MX53_ARM2
+#define CONFIG_FLASH_HEADER
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+
+#define CONFIG_MX53_HCLK_FREQ 24000000
+#define CONFIG_SYS_PLL2_FREQ 400
+#define CONFIG_SYS_AHB_PODF 2
+#define CONFIG_SYS_AXIA_PODF 0
+#define CONFIG_SYS_AXIB_PODF 1
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MX53_UART 1
+#define CONFIG_MX53_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+#define CONFIG_NET_MULTI 1
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_ENV
+
+#define CONFIG_CMD_IIM
+
+#define CONFIG_CMD_CLOCK
+#define CONFIG_REF_CLK_FREQ CONFIG_MX53_HCLK_FREQ
+
+#define CONFIG_CMD_SATA
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
+#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "nfsroot=/opt/eldk/arm\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \
+ "root=/dev/mmcblk0p2 rootwait\0" \
+ "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \
+ "bootcmd=run bootcmd_net\0" \
+
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "ARM2 U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR -1
+#define CONFIG_FEC0_MIIBASE -1
+
+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#define CONFIG_IIM_MAC_ADDR_OFFSET 0x24
+
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_MII_GASKET
+#define CONFIG_DISCOVER_PHY
+
+/*
+ * FUSE Configs
+ * */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_IMX_IIM
+ #define IMX_IIM_BASE IIM_BASE_ADDR
+ #define CONFIG_IIM_MAC_BANK 1
+ #define CONFIG_IIM_MAC_ROW 9
+#endif
+
+/*
+ * I2C Configs
+ */
+#define CONFIG_CMD_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+
+/*
+ * SPI Configs
+ */
+#define CONFIG_FSL_SF 1
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_IMX_ATMEL 1
+#define CONFIG_SPI_FLASH_CS 1
+#define CONFIG_IMX_ECSPI
+#define IMX_CSPI_VER_2_3 1
+#define MAX_SPI_BYTES (64 * 4)
+
+/*
+ * MMC Configs
+ */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC 1
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_SYS_FSL_ESDHC_NUM 2
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+ #define CONFIG_CMD_EXT2 1
+
+ #define CONFIG_BOOT_PARTITION_ACCESS
+#endif
+
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+ #define CONFIG_DWC_AHSATA
+ #define CONFIG_SYS_SATA_MAX_DEVICE 1
+ #define CONFIG_DWC_AHSATA_PORT_ID 0
+ #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
+ #define CONFIG_LBA48
+ #define CONFIG_LIBATA
+#endif
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= \
+ (unsigned long)(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Monitor at beginning of flash */
+#define CONFIG_FSL_ENV_IN_MMC
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET 0x100000
+#elif defined(CONFIG_FSL_ENV_IN_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#elif defined(CONFIG_FSL_ENV_IN_SF)
+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
+ #define CONFIG_ENV_SPI_CS 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#else
+ #define CONFIG_ENV_IS_NOWHERE 1
+#endif
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53-ARM2-DDR3 Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx53.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU core */
+#define CONFIG_MXC
+#define CONFIG_MX53
+#define CONFIG_MX53_ARM2_DDR3
+#define CONFIG_FLASH_HEADER
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+
+#define CONFIG_MX53_HCLK_FREQ 24000000
+#define CONFIG_SYS_PLL2_FREQ 400
+#define CONFIG_SYS_AHB_PODF 2
+#define CONFIG_SYS_AXIA_PODF 0
+#define CONFIG_SYS_AXIB_PODF 1
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MX53_UART 1
+#define CONFIG_MX53_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+#define CONFIG_NET_MULTI 1
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_ENV
+
+#define CONFIG_CMD_IIM
+
+#define CONFIG_CMD_CLOCK
+#define CONFIG_REF_CLK_FREQ CONFIG_MX53_HCLK_FREQ
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
+#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "nfsroot=/opt/eldk/arm\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \
+ "root=/dev/mmcblk0p2 rootwait\0" \
+ "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \
+ "bootcmd=run bootcmd_net\0" \
+
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "ARM2-DDR3 U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR -1
+#define CONFIG_FEC0_MIIBASE -1
+
+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#define CONFIG_IIM_MAC_ADDR_OFFSET 0x24
+
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_MII_GASKET
+#define CONFIG_DISCOVER_PHY
+
+/*
+ * FUSE Configs
+ * */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_IMX_IIM
+ #define IMX_IIM_BASE IIM_BASE_ADDR
+ #define CONFIG_IIM_MAC_BANK 1
+ #define CONFIG_IIM_MAC_ROW 9
+#endif
+
+/*
+ * I2C Configs
+ */
+#define CONFIG_CMD_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+
+/*
+ * SPI Configs
+ */
+#define CONFIG_FSL_SF 1
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_IMX_ATMEL 1
+#define CONFIG_SPI_FLASH_CS 1
+#define CONFIG_IMX_ECSPI
+#define IMX_CSPI_VER_2_3 1
+#define MAX_SPI_BYTES (64 * 4)
+
+/*
+ * MMC Configs
+ */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC 1
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_SYS_FSL_ESDHC_NUM 2
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+ #define CONFIG_CMD_EXT2 1
+#endif
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Monitor at beginning of flash */
+#define CONFIG_FSL_ENV_IN_MMC
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET 0x100000
+#elif defined(CONFIG_FSL_ENV_IN_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#elif defined(CONFIG_FSL_ENV_IN_SF)
+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
+ #define CONFIG_ENV_SPI_CS 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#else
+ #define CONFIG_ENV_IS_NOWHERE 1
+#endif
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53-EVK Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx53.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU core */
+#define CONFIG_MXC
+#define CONFIG_MX53
+#define CONFIG_MX53_EVK
+#define CONFIG_FLASH_HEADER
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+
+#define CONFIG_MX53_HCLK_FREQ 24000000
+#define CONFIG_SYS_PLL2_FREQ 600
+#define CONFIG_SYS_AHB_PODF 4
+#define CONFIG_SYS_AXIA_PODF 1
+#define CONFIG_SYS_AXIB_PODF 2
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MX53_UART 1
+#define CONFIG_MX53_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+#define CONFIG_NET_MULTI 1
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#define CONFIG_CMD_IIM
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_ENV
+
+#define CONFIG_CMD_CLOCK
+#define CONFIG_REF_CLK_FREQ CONFIG_MX53_HCLK_FREQ
+
+#define CONFIG_CMD_SATA
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
+#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "nfsroot=/opt/eldk/arm\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \
+ "root=/dev/mmcblk0p2 rootwait\0" \
+ "bootcmd_mmc=run bootargs_base bootargs_mmc; bootm\0" \
+ "bootcmd=run bootcmd_net\0" \
+
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "EVK U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR -1
+#define CONFIG_FEC0_MIIBASE -1
+
+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#define CONFIG_IIM_MAC_ADDR_OFFSET 0x24
+
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_MII_GASKET
+#define CONFIG_DISCOVER_PHY
+
+/*
+ * FUSE Configs
+ * */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_IMX_IIM
+ #define IMX_IIM_BASE IIM_BASE_ADDR
+ #define CONFIG_IIM_MAC_BANK 1
+ #define CONFIG_IIM_MAC_ROW 9
+#endif
+
+/*
+ * I2C Configs
+ */
+#define CONFIG_CMD_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+
+/*
+ * SPI Configs
+ */
+#define CONFIG_FSL_SF 1
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_IMX_ATMEL 1
+#define CONFIG_SPI_FLASH_CS 1
+#define CONFIG_IMX_ECSPI
+#define IMX_CSPI_VER_2_3 1
+#define MAX_SPI_BYTES (64 * 4)
+
+/*
+ * MMC Configs
+ */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC 1
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_SYS_FSL_ESDHC_NUM 2
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+ #define CONFIG_CMD_EXT2 1
+
+ /* detect whether ESDHC1 or ESDHC3 is boot device */
+ #define CONFIG_DYNAMIC_MMC_DEVNO
+
+ #define CONFIG_BOOT_PARTITION_ACCESS
+#endif
+
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+ #define CONFIG_DWC_AHSATA
+ #define CONFIG_SYS_SATA_MAX_DEVICE 1
+ #define CONFIG_DWC_AHSATA_PORT_ID 0
+ #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
+ #define CONFIG_LBA48
+ #define CONFIG_LIBATA
+#endif
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Monitor at beginning of flash */
+#define CONFIG_FSL_ENV_IN_MMC
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET 0x100000
+#elif defined(CONFIG_FSL_ENV_IN_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#elif defined(CONFIG_FSL_ENV_IN_SF)
+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
+ #define CONFIG_ENV_SPI_CS 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#else
+ #define CONFIG_ENV_IS_NOWHERE 1
+#endif
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53-EVK Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx53.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_MFG 1
+#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU core */
+#define CONFIG_MXC
+#define CONFIG_MX53
+#define CONFIG_MX53_EVK
+#define CONFIG_FLASH_HEADER
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MMU
+
+#define CONFIG_MX53_HCLK_FREQ 24000000
+#define CONFIG_SYS_PLL2_FREQ 600
+#define CONFIG_SYS_AHB_PODF 4
+#define CONFIG_SYS_AXIA_PODF 1
+#define CONFIG_SYS_AXIB_PODF 2
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MX53_UART 1
+#define CONFIG_MX53_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+#define CONFIG_NET_MULTI 1
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_ENV
+
+#define CONFIG_CMD_CLOCK
+#define CONFIG_REF_CLK_FREQ CONFIG_MX53_HCLK_FREQ
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
+#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
+
+#define CONFIG_BOOTARGS "console=ttymxc0,115200 "\
+ "rdinit=/linuxrc"
+#define CONFIG_BOOTCOMMAND "bootm 0x70800000 0x70B00000"
+#define CONFIG_ENV_IS_EMBEDDED
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "EVK MFG U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING 1
+
+#define CONFIG_FEC0_IOBASE FEC_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_PHY_ADDR -1
+#define CONFIG_FEC0_MIIBASE -1
+
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CONFIG_MII_GASKET
+#define CONFIG_DISCOVER_PHY
+
+/*
+ * I2C Configs
+ */
+#define CONFIG_CMD_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+
+/*
+ * SPI Configs
+ */
+#define CONFIG_FSL_SF 1
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_IMX_ATMEL 1
+#define CONFIG_SPI_FLASH_CS 1
+#define CONFIG_IMX_ECSPI
+#define IMX_CSPI_VER_2_3 1
+#define MAX_SPI_BYTES (64 * 4)
+
+/*
+ * MMC Configs
+ */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC 1
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_SYS_FSL_ESDHC_NUM 2
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+ #define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+ #define CONFIG_CMD_EXT2 1
+#endif
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+#define CONFIG_ENV_IS_NOWHERE
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the TRITON320 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
+#define CONFIG_TRITON320 1 /* Zylonite board */
+
+/* #define CONFIG_LCD 1 */
+#ifdef CONFIG_LCD
+#define CONFIG_SHARP_LM8V31
+#endif
+/* #define CONFIG_MMC 1 */
+#define BOARD_LATE_INIT 1
+
+#define CONFIG_SKIP_RELOCATE_UBOOT 1
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
+#define CFG_GBL_DATA_SIZE 512 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0x10000300
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE+0x8000)
+#define CONFIG_DM9000_USE_16BIT
+
+
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 38400
+
+#if 0
+# define CONFIG_COMMANDS CFG_CMD_AUTOSCRIPT \
+ | CFG_CMD_BDI \
+ | CFG_CMD_BOOTD \
+ | CFG_CMD_CONSOLE \
+ | CFG_CMD_ECHO \
+ | CFG_CMD_ENV \
+ | CFG_CMD_IMI \
+ | CFG_CMD_ITEST \
+ | CFG_CMD_LOADB \
+ | CFG_CMD_LOADS \
+ | CFG_CMD_MEMORY \
+ | CFG_CMD_NAND \
+ | CFG_CMD_REGINFO \
+ | CFG_CMD_RUN \
+ & ~(CFG_CMD_JFFS2 | CFG_CMD_FLASH | CFG_CMD_IMLS)
+#endif
+
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL| \
+ CFG_CMD_NAND | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_PING | \
+ CFG_CMD_DHCP) & \
+ ~(CFG_CMD_FLASH | \
+ CFG_CMD_IMLS))
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTCOMMAND "bootm 80000"
+#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rootfstype=jffs2 console=ttyS0,38400"
+#define CONFIG_BOOT_RETRY_TIME -1
+#define CONFIG_BOOT_RETRY_MIN 60
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR " "
+#define CONFIG_AUTOBOOT_STOP_STR "system"
+
+#define CONFIG_ETHADDR ff:ff:ff:ff:ff:ff
+#define CONFIG_NETMASK 255.255.255.255
+#define CONFIG_IPADDR 0.0.0.0
+#define CONFIG_SERVERIP 0.0.0.0
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_TIMESTAMP
+#define CONFIG_USE_MAC_FROM_ENV
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER 1
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CFG_LONGHELP /* undef to save memory */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT "$ " /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_DEVICE_NULLDEV 1
+
+#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */
+
+/* Monahans Core Frequency */
+#define CFG_MONAHANS_RUN_MODE_OSC_RATIO 31 /* valid values: 8, 16, 24, 31 */
+#define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 2 /* valid values: 1, 2 */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* #define CFG_MMC_BASE 0xF0000000 */
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */
+#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+#define CFG_DRAM_BASE PHYS_SDRAM_1
+#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE
+
+
+#define CFG_LOAD_ADDR (PHYS_SDRAM_1 + 0x100000) /* default load address */
+
+#define CFG_SKIP_DRAM_SCRUB
+
+/*
+ * NAND Flash
+ */
+/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
+#define CONFIG_NEW_NAND_CODE
+#define CFG_NAND0_BASE 0x0
+#undef CFG_NAND1_BASE
+
+#define CONFIG_MTD_NAND_ECC_JFFS2 1
+
+#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+
+/* nand timeout values */
+#define CFG_NAND_PROG_ERASE_TO 9000
+#define CFG_NAND_OTHER_TO 2000
+#define CFG_NAND_SENDCMD_RETRY 3
+#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
+
+/* NAND Timing Parameters (in ns) */
+#define NAND_TIMING_tCH 10
+#define NAND_TIMING_tCS 0
+#define NAND_TIMING_tWH 20
+#define NAND_TIMING_tWP 40
+
+#define NAND_TIMING_tRH 20
+#define NAND_TIMING_tRP 40
+
+#define NAND_TIMING_tR 11123
+#define NAND_TIMING_tWHR 100
+#define NAND_TIMING_tAR 10
+
+/* NAND debugging */
+#if 0
+#define CFG_DFC_DEBUG1 /* useful */
+#define CFG_DFC_DEBUG2 /* noisy */
+#define CFG_DFC_DEBUG3 /* extremly noisy */
+#else
+#undef CFG_DFC_DEBUG1 /* useful */
+#undef CFG_DFC_DEBUG2 /* noisy */
+#undef CFG_DFC_DEBUG3 /* extremly noisy */
+#endif
+
+#define CONFIG_MTD_DEBUG 0
+#define CONFIG_MTD_DEBUG_VERBOSE 0
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NO_FLASH 1
+
+#define CFG_ENV_IS_IN_NAND 1
+#define CFG_ENV_OFFSET 0x60000
+#undef CFG_ENV_OFFSET_REDUND
+#define CFG_ENV_SIZE 0x20000
+
+#define CONFIG_JFFS2_NAND 1
+#define CONFIG_JFFS2_NAND_DEV "nand0" /* nand device jffs2 lives on */
+#define CONFIG_JFFS2_NAND_OFF 0x80000 /* start of jffs2 partition */
+#define CONFIG_JFFS2_NAND_SIZE 64*1024*1024 /* size of jffs2 partition */
+
+
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nand0=triton320-nand"
+#define MTDPARTS_DEFAULT "mtdparts=triton320-nand:128k(sbootl),256k(u-boot),128k(env),2m(linux_kernel),83456k(userfs),32m(wince);"
+
+#endif /* __CONFIG_H */
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIGS_TX25_H
+#define __CONFIGS_TX25_H
/*
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
GENERATED_GBL_DATA_SIZE)
-#endif /* __CONFIG_H */
+#endif /* __CONFIGS_TX25_H */
--- /dev/null
+/*
+ * Copyright (C) 2012 <LW@KARO-electronics.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __CONFIGS_TX28_H
+#define __CONFIGS_TX28_H
+
+#include <asm/sizes.h>
+#include <asm/arch/regs-base.h>
+
+/*
+ * Ka-Ro TX28 board - SoC configuration
+ */
+#define CONFIG_MX28 /* i.MX28 SoC */
+#define CONFIG_MXS_GPIO /* GPIO control */
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+#ifdef CONFIG_TX28_S
+#define PHYS_SDRAM_1_SIZE SZ_64M
+#define TX28_MOD_SUFFIX "1"
+#else
+#define PHYS_SDRAM_1_SIZE SZ_128M
+#define CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
+#define TX28_MOD_SUFFIX "0"
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SHOW_ACTIVITY
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* LCD Logo and Splash screen support */
+#define CONFIG_LCD
+#ifdef CONFIG_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_MXS
+#define CONFIG_LCD_LOGO
+#define LCD_BPP LCD_COLOR24
+#define CONFIG_CMD_BMP
+#define CONFIG_VIDEO_BMP_RLE8
+#endif /* CONFIG_LCD */
+#endif /* CONFIG_SPL_BUILD */
+
+/*
+ * Memory configuration options
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of SDRAM */
+#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
+#define CONFIG_STACKSIZE SZ_64K
+#define CONFIG_SYS_MALLOC_LEN SZ_4M
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M)
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "TX28 U-Boot > "
+#define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Flattened Device Tree (FDT) support
+*/
+#define CONFIG_OF_LIBFDT
+#ifdef CONFIG_OF_LIBFDT
+#define CONFIG_FDT_FIXUP_PARTITIONS
+#define CONFIG_OF_EMBED
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_DEFAULT_DEVICE_TREE tx28
+#define CONFIG_ARCH_DEVICE_TREE mx28
+#define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
+#endif
+
+/*
+ * Boot Linux
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+#define __pfx(x, s) (x##s)
+#define _pfx(x, s) __pfx(x, s)
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SYS_AUTOLOAD "no"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200 ro debug panic=1"
+#define CONFIG_BOOTCOMMAND "run bootcmd_nand"
+#define CONFIG_LOADADDR 43000000
+#define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
+#define CONFIG_U_BOOT_IMG_SIZE SZ_1M
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autostart=no\0" \
+ "baseboard=stk5-v3\0" \
+ "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mmcblk0p3 rootwait\0" \
+ "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mtdblock3 rootfstype=jffs2\0" \
+ "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\
+ "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
+ "fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \
+ "bootcmd_nand=set autostart no;run bootargs_nand;" \
+ "nboot linux;run bootm_cmd\0" \
+ "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
+ "run bootm_cmd\0" \
+ "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \
+ "default_bootargs=set bootargs " CONFIG_BOOTARGS \
+ " mxsfb.mode=${video_mode} ${append_bootargs}\0" \
+ "fdtaddr=41000000\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nfsroot=/tftpboot/rootfs\0" \
+ "otg_mode=device\0" \
+ "touchpanel=tsc2007\0" \
+ "video_mode=VGA\0"
+
+#define MTD_NAME "gpmi-nand"
+#define MTDIDS_DEFAULT "nand0=" MTD_NAME
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_BOOTCE
+#define CONFIG_CMD_TIME
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 24000000
+#define CONFIG_PL01x_PORTS { \
+ (void *)MXS_UARTDBG_BASE, \
+ }
+#define CONFIG_CONS_INDEX 0 /* do not change! */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/*
+ * Ethernet Driver
+ */
+#define CONFIG_FEC_MXC
+#ifdef CONFIG_FEC_MXC
+/* This is required for the FEC driver to work with cache enabled */
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+
+#ifndef CONFIG_TX28_S
+#define CONFIG_FEC_MXC_MULTI
+#else
+#define IMX_FEC_BASE MXS_ENET0_BASE
+#define CONFIG_FEC_MXC_PHYADDR 0x00
+#endif
+
+#define CONFIG_MII
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#define CONFIG_NET_MULTI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+/* Add for working with "strict" DHCP server */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#endif
+
+/*
+ * NAND flash driver
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_MTD_DEVICE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_NAND_MXS
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_SYS_MXS_DMA_CHANNEL 4
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
+#define CONFIG_ENV_SIZE SZ_128K
+#define CONFIG_ENV_RANGE 0x60000
+#endif /* CONFIG_ENV_IS_IN_NAND */
+#define CONFIG_SYS_NAND_BASE 0x00000000
+#define CONFIG_CMD_ROMUPDATE
+#endif /* CONFIG_CMD_NAND */
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#ifndef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_MMC
+#endif
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXS_MMC
+#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/*
+ * Environments on MMC
+ */
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OVERWRITE
+/* Associated with the MMC layout defined in mmcops.c */
+#define CONFIG_ENV_OFFSET SZ_1K
+#define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
+#define CONFIG_DYNAMIC_MMC_DEVNO
+#endif /* CONFIG_ENV_IS_IN_MMC */
+#endif /* CONFIG_CMD_MMC */
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "1m@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) "(u-boot)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env2),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
+#else
+#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "1m@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) "(u-boot)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+ GENERATED_GBL_DATA_SIZE)
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
+#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SYS_SPL_VDDD_VAL 1500
+#define CONFIG_SYS_SPL_BATT_BO_LEVEL 2800
+#define CONFIG_SYS_SPL_VDDMEM_VAL 0 /* VDDMEM is not utilized on TX28 */
+
+#endif /* __CONFIGS_TX28_H */
--- /dev/null
+/*
+ * tx48.h
+ *
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * based on: am335x_evm
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIGS_TX48_H
+#define __CONFIGS_TX48_H
+
+#include <asm/sizes.h>
+
+/*
+ * Ka-Ro TX48 board - SoC configuration
+ */
+#define CONFIG_AM33XX
+#define CONFIG_AM33XX_GPIO
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SHOW_ACTIVITY
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_LATE_INIT
+
+/* LCD Logo and Splash screen support */
+#define CONFIG_LCD
+#ifdef CONFIG_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_DA8XX
+#define DAVINCI_LCD_CNTL_BASE 0x4830e000
+#define CONFIG_LCD_LOGO
+#define LCD_BPP LCD_COLOR24
+#define CONFIG_CMD_BMP
+#define CONFIG_VIDEO_BMP_RLE8
+#endif /* CONFIG_LCD */
+#endif /* CONFIG_SPL_BUILD */
+
+/* Clock Defines */
+#define V_OSCK 24000000 /* Clock output from T2 */
+#define V_SCLK V_OSCK
+
+/*
+ * Memory configuration options
+ */
+#define CONFIG_SYS_SDRAM_DDR3
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of SDRAM */
+#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
+#define CONFIG_MAX_RAM_BANK_SIZE SZ_1G
+
+#define CONFIG_STACKSIZE SZ_64K
+#define CONFIG_SYS_MALLOC_LEN SZ_4M
+
+#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + SZ_64M)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_8M)
+#define CONFIG_SYS_SDRAM_CLK 266
+
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "TX48 U-Boot > "
+#define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Flattened Device Tree (FDT) support
+*/
+#ifdef CONFIG_OF_LIBFDT /* set via cmdline parameter thru boards.cfg */
+#define CONFIG_FDT_FIXUP_PARTITIONS
+#define CONFIG_OF_EMBED
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_DEFAULT_DEVICE_TREE tx48
+#define CONFIG_ARCH_DEVICE_TREE am33xx
+#define CONFIG_MACH_TYPE (-1)
+#define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
+#else
+#ifndef MACH_TYPE_TIAM335EVM
+#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
+#endif
+#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
+#endif
+
+/*
+ * Boot Linux
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+#define __pfx(x, s) (x##s)
+#define _pfx(x, s) __pfx(x, s)
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SYS_AUTOLOAD "no"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttyO0,115200 ro debug panic=1"
+#define CONFIG_BOOTCOMMAND "run bootcmd_nand"
+#define CONFIG_LOADADDR 83000000
+#define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
+#define CONFIG_U_BOOT_IMG_SIZE SZ_1M
+#if 0
+#define CONFIG_HW_WATCHDOG
+#endif
+
+/*
+ * Extra Environments
+ */
+#ifdef CONFIG_OF_LIBFDT
+#define TX48_BOOTM_CMD \
+ "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0"
+#define TX48_MTDPARTS_CMD ""
+#else
+#define TX48_BOOTM_CMD \
+ "bootm_cmd=bootm\0"
+#define TX48_MTDPARTS_CMD "${mtdparts} "
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autostart=no\0" \
+ "baseboard=stk5-v3\0" \
+ "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mmcblk0p2 rootwait\0" \
+ "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mtdblock4 rootfstype=jffs2\0" \
+ "nfsroot=/tftpboot/rootfs\0" \
+ "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\
+ "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
+ " fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \
+ "bootcmd_nand=set autostart no;run bootargs_nand;" \
+ " nboot linux;run bootm_cmd\0" \
+ "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
+ " run bootm_cmd\0" \
+ TX48_BOOTM_CMD \
+ "default_bootargs=set bootargs " CONFIG_BOOTARGS \
+ TX48_MTDPARTS_CMD \
+ " video=${video_mode} ${append_bootargs}\0" \
+ "cpu_clk=400\0" \
+ "fdtaddr=81000000\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "otg_mode=device\0" \
+ "touchpanel=tsc2007\0" \
+ "video_mode=640x480MR-24@60\0"
+
+#define MTD_NAME "omap2-nand.0"
+#define MTDIDS_DEFAULT "nand0=" MTD_NAME
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_BOOTCE
+#define CONFIG_CMD_TIME
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK 48000000
+#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
+#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
+
+#define CONFIG_SYS_NS16550_COM3 0x481aa000 /* UART2 */
+#define CONFIG_SYS_NS16550_COM4 0x481aa000 /* UART3 */
+#define CONFIG_SYS_NS16550_COM5 0x481aa000 /* UART4 */
+#define CONFIG_CONS_INDEX 1 /* one based! */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/*
+ * Ethernet Driver
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHY_SMSC
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR (-1)
+#define CONFIG_MII
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+/* Add for working with "strict" DHCP server */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#endif
+
+/*
+ * NAND flash driver
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_MTD_DEVICE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_NAND_AM33XX
+#define GPMC_NAND_ECC_LP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT_KERNEL GPMC_NAND_HW_ECC_LAYOUT
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_MAXBAD 20 /* Max. number of bad blocks guaranteed by manufacturer */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
+#define CONFIG_ENV_SIZE SZ_128K
+#define CONFIG_ENV_RANGE 0x60000
+#endif /* CONFIG_ENV_IS_IN_NAND */
+#define CONFIG_SYS_NAND_BASE 0x08000000 /* must be defined but value is irrelevant */
+#define NAND_BASE CONFIG_SYS_NAND_BASE
+#endif /* CONFIG_CMD_NAND */
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#ifndef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_MMC
+#endif
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_OMAP_MMC_DEV_1
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/*
+ * Environments on MMC
+ */
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OVERWRITE
+/* Associated with the MMC layout defined in mmcops.c */
+#define CONFIG_ENV_OFFSET SZ_1K
+#define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
+#define CONFIG_DYNAMIC_MMC_DEVNO
+#endif /* CONFIG_ENV_IS_IN_MMC */
+#endif /* CONFIG_CMD_MMC */
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "128k(u-boot-spl)," \
+ "1m(u-boot)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env2),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
+#else
+#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "128k(u-boot-spl)," \
+ "1m(u-boot)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define SRAM0_SIZE SZ_64K
+#define CONFIG_SYS_INIT_SP_ADDR 0x4030B7FC
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+
+ /* Platform/Board specific defs */
+#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_MAX_SIZE (46 * SZ_1K)
+#define CONFIG_SPL_GPIO_SUPPORT
+#ifdef CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_BLOCK_SIZE SZ_128K
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+#endif
+
+#define CONFIG_SPL_BSS_START_ADDR PHYS_SDRAM_1
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_512K
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_SPL_MALLOC_START (PHYS_SDRAM_1 + SZ_2M + SZ_32K)
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_1M
+
+#endif /* __CONFIGS_TX48_H */
--- /dev/null
+/*
+ * Copyright (C) 2012 <LW@KARO-electronics.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __CONFIGS_TX51_H
+#define __CONFIGS_TX51_H
+
+#include <asm/sizes.h>
+
+/*
+ * Ka-Ro TX51 board - SoC configuration
+ */
+#define CONFIG_MX51 /* i.MX51 SoC */
+#define CONFIG_SYS_MX5_IOMUX_V3
+#define CONFIG_MXC_GPIO /* GPIO control */
+#define CONFIG_SYS_MX5_HCLK 24000000
+#define CONFIG_SYS_MX5_CLK32 32768
+#define CONFIG_SYS_DDR_CLKSEL 0
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+#define CONFIG_SHOW_ACTIVITY
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#if CONFIG_SYS_CPU_CLK == 600
+#define TX51_MOD_PREFIX "6"
+#elif CONFIG_SYS_CPU_CLK == 800
+#define TX51_MOD_PREFIX "8"
+#define CONFIG_MX51_PLL_ERRATA
+#else
+#error Invalid CPU clock
+#endif
+
+/* LCD Logo and Splash screen support */
+#define CONFIG_LCD
+#ifdef CONFIG_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_IPUV3_CLK 200000000
+#define CONFIG_LCD_LOGO
+#define LCD_BPP LCD_COLOR24
+#define CONFIG_CMD_BMP
+#define CONFIG_VIDEO_BMP_RLE8
+#endif /* CONFIG_LCD */
+
+/*
+ * Memory configurations
+ */
+#define PHYS_SDRAM_1 0x90000000 /* Base address of bank 1 */
+#define PHYS_SDRAM_1_SIZE SZ_128M
+#if CONFIG_NR_DRAM_BANKS > 1
+#define PHYS_SDRAM_2 0x98000000 /* Base address of bank 2 */
+#define PHYS_SDRAM_2_SIZE SZ_128M
+#else
+#define TX51_MOD_SUFFIX "0"
+#endif
+#define CONFIG_STACKSIZE SZ_128K
+#define CONFIG_SYS_MALLOC_LEN SZ_8M
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M) /* 4 MB RAM test */
+#if CONFIG_SYS_SDRAM_CLK == 200
+#define CONFIG_SYS_CLKTL_CBCDR 0x59e35180
+#define TX51_MOD_SUFFIX "1"
+#elif CONFIG_SYS_SDRAM_CLK == 166
+#define CONFIG_SYS_CLKTL_CBCDR 0x01e35180
+#ifndef TX51_MOD_SUFFIX
+#define TX51_MOD_SUFFIX "2"
+#endif
+#else
+#error Invalid SDRAM clock
+#endif
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "TX51 U-Boot > "
+#define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Flattened Device Tree (FDT) support
+*/
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_EMBED
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_DEFAULT_DEVICE_TREE tx51
+#define CONFIG_ARCH_DEVICE_TREE mx51
+#define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
+
+/*
+ * Boot Linux
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+#define __pfx(x, s) (x##s)
+#define _pfx(x, s) __pfx(x, s)
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SYS_AUTOLOAD "no"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1"
+#define CONFIG_BOOTCOMMAND "run bootcmd_nand"
+#define CONFIG_LOADADDR 94000000
+#define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
+#define CONFIG_U_BOOT_IMG_SIZE SZ_1M
+#define CONFIG_HW_WATCHDOG
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autostart=no\0" \
+ "baseboard=stk5-v3\0" \
+ "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mmcblk0p3 rootwait\0" \
+ "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mtdblock3 rootfstype=jffs2\0" \
+ "nfsroot=/tftpboot/rootfs\0" \
+ "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\
+ "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
+ "mmc read ${loadaddr} 100 3000;run bootm_cmd\0" \
+ "bootcmd_nand=set autostart no;run bootargs_nand;" \
+ "nboot linux;run bootm_cmd\0" \
+ "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
+ "run bootm_cmd\0" \
+ "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \
+ "default_bootargs=set bootargs " CONFIG_BOOTARGS \
+ " video=${video_mode} ${append_bootargs}\0" \
+ "cpu_clk=" xstr(CONFIG_SYS_CPU_CLK) "\0" \
+ "fdtaddr=91000000\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "otg_mode=device\0" \
+ "touchpanel=tsc2007\0" \
+ "video_mode=VGA-1:640x480MR-24@60\0"
+
+#define MTD_NAME "mxc_nand"
+#define MTDIDS_DEFAULT "nand0=" MTD_NAME
+#define CONFIG_FDT_FIXUP_PARTITIONS
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_IIM
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_BOOTCE
+#define CONFIG_CMD_TIME
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+#define CONFIG_MXC_GPIO
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/*
+ * Ethernet Driver
+ */
+#define CONFIG_FEC_MXC
+#ifdef CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x1f
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+#define CONFIG_MII
+#define CONFIG_FEC_XCV_TYPE MII100
+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+/* Add for working with "strict" DHCP server */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#endif
+
+/*
+ * NAND flash driver
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_MTD_DEVICE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE 0xcfff0000
+#define CONFIG_MXC_NAND_IP_BASE 0x83fdb000
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE
+#define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */
+#define CONFIG_ENV_RANGE 0x60000
+#endif
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_NAND_BASE 0xa0000000
+#define CONFIG_FIT
+#else
+#define CONFIG_SYS_NAND_BASE 0x00000000
+#define CONFIG_CMD_ROMUPDATE
+#endif
+#endif /* CONFIG_CMD_NAND */
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#ifndef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_MMC
+#endif
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_USE_PIO
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 2
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/*
+ * Environments on MMC
+ */
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OVERWRITE
+/* Associated with the MMC layout defined in mmcops.c */
+#define CONFIG_ENV_OFFSET SZ_1K
+#define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
+#define CONFIG_DYNAMIC_MMC_DEVNO
+#endif /* CONFIG_ENV_IS_IN_MMC */
+#endif /* CONFIG_CMD_MMC */
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "1m(u-boot)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env2),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
+#else
+#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "1m(u-boot)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+ GENERATED_GBL_DATA_SIZE)
+
+#ifdef CONFIG_CMD_IIM
+#define CONFIG_IMX_IIM
+#endif
+
+#endif /* __CONFIGS_TX51_H */
--- /dev/null
+/*
+ * Copyright (C) 2012 <LW@KARO-electronics.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __CONFIGS_TX53_H
+#define __CONFIGS_TX53_H
+
+#include <asm/sizes.h>
+
+/*
+ * Ka-Ro TX53 board - SoC configuration
+ */
+#define CONFIG_TX53 /* TX53 SoM */
+#define CONFIG_MX53 /* i.MX53 SoC */
+#define CONFIG_SYS_MX5_IOMUX_V3
+#define CONFIG_MXC_GPIO /* GPIO control */
+#define CONFIG_SYS_MX5_HCLK 24000000
+#define CONFIG_SYS_MX5_CLK32 32768
+#define CONFIG_SYS_DDR_CLKSEL 0
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+#define CONFIG_SHOW_ACTIVITY
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* LCD Logo and Splash screen support */
+#define CONFIG_LCD
+#ifdef CONFIG_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_IPUV3_CLK 200000000
+#define CONFIG_LCD_LOGO
+#define LCD_BPP LCD_COLOR24
+#define CONFIG_CMD_BMP
+#define CONFIG_VIDEO_BMP_RLE8
+#endif /* CONFIG_LCD */
+
+/*
+ * Memory configurations
+ */
+#define PHYS_SDRAM_1 0x70000000 /* Base address of bank 1 */
+#define PHYS_SDRAM_1_SIZE SZ_512M
+#if CONFIG_NR_DRAM_BANKS > 1
+#define PHYS_SDRAM_2 0xb0000000 /* Base address of bank 2 */
+#define PHYS_SDRAM_2_SIZE SZ_512M
+#define TX53_MOD_SUFFIX "1"
+#else
+#define TX53_MOD_SUFFIX "0"
+#endif
+#define CONFIG_STACKSIZE SZ_128K
+#define CONFIG_SYS_MALLOC_LEN SZ_8M
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + SZ_4M) /* 4 MB RAM test */
+#define CONFIG_SYS_SDRAM_CLK 400
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "TX53 U-Boot > "
+#define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Flattened Device Tree (FDT) support
+*/
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_EMBED
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_DEFAULT_DEVICE_TREE tx53
+#define CONFIG_ARCH_DEVICE_TREE mx53
+#define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
+
+/*
+ * Boot Linux
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+#define __pfx(x, s) (x##s)
+#define _pfx(x, s) __pfx(x, s)
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SYS_AUTOLOAD "no"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1"
+#define CONFIG_BOOTCOMMAND "run bootcmd_nand"
+#define CONFIG_LOADADDR 78000000
+#define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
+#define CONFIG_U_BOOT_IMG_SIZE SZ_1M
+#define CONFIG_HW_WATCHDOG
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autostart=no\0" \
+ "baseboard=stk5-v3\0" \
+ "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mmcblk0p3 rootwait\0" \
+ "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mtdblock3 rootfstype=jffs2\0" \
+ "nfsroot=/tftpboot/rootfs\0" \
+ "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\
+ "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
+ "mmc read ${loadaddr} 100 3000;run bootm_cmd\0" \
+ "bootcmd_nand=set autostart no;run bootargs_nand;" \
+ "nboot linux;run bootm_cmd\0" \
+ "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
+ "run bootm_cmd\0" \
+ "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \
+ "default_bootargs=set bootargs " CONFIG_BOOTARGS \
+ " video=${video_mode} ${append_bootargs}\0" \
+ "cpu_clk=800\0" \
+ "fdtaddr=71000000\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "otg_mode=device\0" \
+ "touchpanel=tsc2007\0" \
+ "video_mode=VGA-1:640x480MR-24@60\0"
+
+#define MTD_NAME "mxc_nand"
+#define MTDIDS_DEFAULT "nand0=" MTD_NAME
+#define CONFIG_FDT_FIXUP_PARTITIONS
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_IIM
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_BOOTCE
+#define CONFIG_CMD_TIME
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+#define CONFIG_MXC_GPIO
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/*
+ * Ethernet Driver
+ */
+#define CONFIG_FEC_MXC
+#ifdef CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+#define CONFIG_MII
+#define CONFIG_FEC_XCV_TYPE MII100
+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+/* Add for working with "strict" DHCP server */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#endif
+
+/*
+ * NAND flash driver
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_MTD_DEVICE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE 0xf7ff0000
+#define CONFIG_MXC_NAND_IP_BASE 0x63fdb000
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET CONFIG_U_BOOT_IMG_SIZE
+#define CONFIG_ENV_SIZE 0x20000 /* 128 KiB */
+#define CONFIG_ENV_RANGE 0x60000
+#endif
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_NAND_BASE 0xa0000000
+#define CONFIG_FIT
+#else
+#define CONFIG_SYS_NAND_BASE 0x00000000
+#define CONFIG_CMD_ROMUPDATE
+#endif
+#endif /* CONFIG_CMD_NAND */
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#ifndef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_MMC
+#endif
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_USE_PIO
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 2
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/*
+ * Environments on MMC
+ */
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OVERWRITE
+/* Associated with the MMC layout defined in mmcops.c */
+#define CONFIG_ENV_OFFSET SZ_1K
+#define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
+#define CONFIG_DYNAMIC_MMC_DEVNO
+#endif /* CONFIG_ENV_IS_IN_MMC */
+#endif /* CONFIG_CMD_MMC */
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "1m(u-boot)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env2),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
+#else
+#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "1m(u-boot)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+ GENERATED_GBL_DATA_SIZE)
+
+#ifdef CONFIG_CMD_IIM
+#define CONFIG_IMX_IIM
+#endif
+
+#endif /* __CONFIGS_TX53_H */
--- /dev/null
+/*
+ * Copyright (C) 2012 <LW@KARO-electronics.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __TX6Q_H
+#define __TX6Q_H
+
+#include <asm/sizes.h>
+
+/*
+ * Ka-Ro TX6Q board - SoC configuration
+ */
+#define CONFIG_MX6Q
+#define CONFIG_SYS_MX6_HCLK 24000000
+#define CONFIG_SYS_MX6_CLK32 32768
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+#define CONFIG_SHOW_ACTIVITY
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#if 0
+#define CONFIG_NETCONSOLE
+#endif
+
+/* LCD Logo and Splash screen support */
+#if 1
+#define CONFIG_LCD
+#endif
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#ifdef CONFIG_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_IPU_CLKRATE 266000000
+#define CONFIG_LCD_LOGO
+#define LCD_BPP LCD_COLOR24
+#define CONFIG_CMD_BMP
+#define CONFIG_VIDEO_BMP_RLE8
+#endif /* CONFIG_LCD */
+
+/*
+ * Memory configuration options
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* # of SDRAM banks */
+#define PHYS_SDRAM_1 0x10000000 /* Base address of bank 1 */
+#define PHYS_SDRAM_1_SIZE SZ_1G
+#define CONFIG_STACKSIZE SZ_128K
+#define CONFIG_SYS_MALLOC_LEN SZ_8M
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M)
+#define CONFIG_SYS_SDRAM_CLK 528
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "TX6Q U-Boot > "
+#define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Flattened Device Tree (FDT) support
+*/
+#define CONFIG_OF_LIBFDT
+#ifdef CONFIG_OF_LIBFDT
+#define CONFIG_FDT_FIXUP_PARTITIONS
+#define CONFIG_OF_EMBED
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_DEFAULT_DEVICE_TREE tx6q
+#define CONFIG_ARCH_DEVICE_TREE mx6q
+#define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
+#endif
+
+/*
+ * Boot Linux
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+#define __pfx(x, s) (x##s)
+#define _pfx(x, s) __pfx(x, s)
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SYS_AUTOLOAD "no"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttymxc0,115200 ro debug panic=1"
+#define CONFIG_BOOTCOMMAND "run bootcmd_nand"
+#define CONFIG_LOADADDR 18000000
+#define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
+#define CONFIG_U_BOOT_IMG_SIZE SZ_1M
+#define CONFIG_IMX_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS 3000
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autostart=no\0" \
+ "baseboard=stk5-v3\0" \
+ "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mmcblk0p3 rootwait\0" \
+ "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/mtdblock3 rootfstype=jffs2\0" \
+ "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
+ " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\
+ "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
+ "fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \
+ "bootcmd_nand=set autostart no;run bootargs_nand;" \
+ "nboot linux;run bootm_cmd\0" \
+ "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
+ "run bootm_cmd\0" \
+ "bootdelay=-1\0" \
+ "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0" \
+ "cpu_clk=800\0" \
+ "default_bootargs=set bootargs " CONFIG_BOOTARGS \
+ " video=${video_mode} ${append_bootargs}\0" \
+ "fdtaddr=11000000\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nfsroot=/tftpboot/rootfs\0" \
+ "otg_mode=device\0" \
+ "touchpanel=tsc2007\0" \
+ "video_mode=VGA-1:640x480MR-24@60\0"
+
+#define MTD_NAME "gpmi-nand"
+#define MTDIDS_DEFAULT "nand0=" MTD_NAME
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+#if 1
+#define CONFIG_CMD_BOOTCE
+#endif
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_I2C
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/*
+ * GPIO driver
+ */
+#define CONFIG_MXC_GPIO
+
+/*
+ * Ethernet Driver
+ */
+#define CONFIG_FEC_MXC
+#ifdef CONFIG_FEC_MXC
+/* This is required for the FEC driver to work with cache enabled */
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+#define CONFIG_MII
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+/* Add for working with "strict" DHCP server */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#endif
+
+/*
+ * I2C Configs
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
+#define CONFIG_SYS_I2C_MX6_PORT1
+#define CONFIG_SYS_I2C_SPEED 10000
+#define CONFIG_SYS_I2C_SLAVE 0x3c
+#define CONFIG_MX6_INTER_LDO_BYPASS 0
+#endif
+
+/*
+ * NAND flash driver
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_MTD_DEVICE
+#if 0
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE 4
+#endif
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_NAND_MXS
+#define CONFIG_NAND_PAGE_SIZE 2048
+#define CONFIG_NAND_OOB_SIZE 64
+#define CONFIG_NAND_PAGES_PER_BLOCK 64
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_SYS_MXS_DMA_CHANNEL 4
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
+#define CONFIG_ENV_SIZE SZ_128K
+#define CONFIG_ENV_RANGE 0x60000
+#endif
+#define CONFIG_SYS_NAND_BASE 0x00000000
+#define CONFIG_CMD_ROMUPDATE
+#endif /* CONFIG_CMD_NAND */
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#ifndef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_MMC
+#endif
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#if 0
+#define CONFIG_SYS_FSL_ESDHC_USE_PIO
+#endif
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 2
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/*
+ * Environments on MMC
+ */
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OVERWRITE
+/* Associated with the MMC layout defined in mmcops.c */
+#define CONFIG_ENV_OFFSET SZ_1K
+#define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
+#define CONFIG_DYNAMIC_MMC_DEVNO
+#endif /* CONFIG_ENV_IS_IN_MMC */
+#endif /* CONFIG_CMD_MMC */
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "1m@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) "(u-boot)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env2),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
+#else
+#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
+ "1m@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) "(u-boot)," \
+ xstr(CONFIG_ENV_RANGE) \
+ "(env),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+ GENERATED_GBL_DATA_SIZE)
+
+#ifdef CONFIG_CMD_IIM
+#define CONFIG_IMX_IIM
+#endif
+
+#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * CPSW Ethernet Switch Driver
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _CPSW_H_
-#define _CPSW_H_
-
-struct cpsw_slave_data {
- u32 slave_reg_ofs;
- u32 sliver_reg_ofs;
- int phy_id;
- int phy_if;
-};
-
-enum {
- CPSW_CTRL_VERSION_1 = 0,
- CPSW_CTRL_VERSION_2 /* am33xx like devices */
-};
-
-struct cpsw_platform_data {
- u32 mdio_base;
- u32 cpsw_base;
- int mdio_div;
- int channels; /* number of cpdma channels (symmetric) */
- u32 cpdma_reg_ofs; /* cpdma register offset */
- int slaves; /* number of slave cpgmac ports */
- u32 ale_reg_ofs; /* address lookup engine reg offset */
- int ale_entries; /* ale table size */
- u32 host_port_reg_ofs; /* cpdma host port registers */
- u32 hw_stats_reg_ofs; /* cpsw hw stats counters */
- u32 mac_control;
- struct cpsw_slave_data *slave_data;
- void (*control)(int enabled);
- u32 host_port_num;
- u8 version;
-};
-
-int cpsw_register(struct cpsw_platform_data *data);
-
-#endif /* _CPSW_H_ */
#ifndef __FSL_ESDHC_H__
#define __FSL_ESDHC_H__
+#include <linux/compat.h>
#include <asm/errno.h>
#include <asm/byteorder.h>
#define ESDHC_HOSTCAPBLT_HSS 0x00200000
struct fsl_esdhc_cfg {
- u32 esdhc_base;
+ void __iomem *esdhc_base;
u32 sdhc_clk;
+ int cd_gpio;
+ int wp_gpio;
};
/* Select the correct accessors depending on endianess */
--- /dev/null
+/*
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMX_SPI_H__
+#define __IMX_SPI_H__
+
+#include <spi.h>
+
+#undef IMX_SPI_DEBUG
+
+#define IMX_SPI_ACTIVE_HIGH 1
+#define IMX_SPI_ACTIVE_LOW 0
+#define SPI_RETRY_TIMES 100
+
+#if defined(IMX_CSPI_VER_0_7)
+ #define SPI_RX_DATA 0x0
+ #define SPI_TX_DATA 0x4
+ #define SPI_CON_REG 0x8
+ #define SPI_INT_REG 0xC
+ #define SPI_DMA_REG 0x10
+ #define SPI_STAT_REG 0x14
+ #define SPI_PERIOD_REG 0x18
+
+ #define SPI_CTRL_EN (1 << 0)
+ #define SPI_CTRL_MODE (1 << 1)
+ #define SPI_CTRL_REG_XCH_BIT (1 << 2)
+ #define SPI_CTRL_SSPOL (1 << 7)
+ #define SPI_CTRL_SSPOL_OFF (7)
+ #define SPI_CTRL_SSCTL (1 << 6)
+ #define SPI_CTRL_SSCTL_OFF (6)
+ #define SPI_CTRL_SCLK_POL (1 << 4)
+ #define SPI_CTRL_SCLK_POL_OFF (4)
+ #define SPI_CTRL_SCLK_PHA (1 << 5)
+ #define SPI_CTRL_SCLK_PHA_OFF (5)
+ #define SPI_CTRL_SS_OFF (12)
+ #define SPI_CTRL_SS_MASK (3 << 12)
+ #define SPI_CTRL_DATA_OFF (16)
+ #define SPI_CTRL_DATA_MASK (7 << 16)
+ #define SPI_CTRL_BURST_OFF (20)
+ #define SPI_CTRL_BURST_MASK (0xFFF << 20)
+ #define SPI_INT_STAT_TC (1 << 7)
+
+#elif defined(IMX_CSPI_VER_2_3)
+ #define SPI_RX_DATA 0x0
+ #define SPI_TX_DATA 0x4
+ #define SPI_CON_REG 0x8
+ #define SPI_CFG_REG 0xC
+ #define SPI_INT_REG 0x10
+ #define SPI_DMA_REG 0x14
+ #define SPI_STAT_REG 0x18
+ #define SPI_PERIOD_REG 0x1C
+#endif
+
+struct spi_reg_t {
+ u32 ctrl_reg;
+ u32 cfg_reg;
+};
+
+struct imx_spi_dev_t {
+ struct spi_slave slave;
+ u32 base; /* base address of SPI module the device is connected to */
+ u32 freq; /* desired clock freq in Hz for this device */
+ u32 ss_pol; /* ss polarity: 1=active high; 0=active low */
+ u32 ss; /* slave select */
+ u32 in_sctl; /* inactive sclk ctl: 1=stay low; 0=stay high */
+ u32 in_dctl; /* inactive data ctl: 1=stay low; 0=stay high */
+ u32 ssctl; /* single burst mode vs multiple: 0=single; 1=multi */
+ u32 sclkpol; /* sclk polarity: active high=0; active low=1 */
+ u32 sclkpha; /* sclk phase: 0=phase 0; 1=phase1 */
+ u32 fifo_sz; /* fifo size in bytes for either tx or rx. Don't add them up! */
+ u32 us_delay; /* us delay in each xfer */
+ struct spi_reg_t reg; /* pointer to a set of SPI registers */
+};
+
+extern void spi_io_init(struct imx_spi_dev_t *dev);
+
+#endif /* __IMX_SPI_H__ */
--- /dev/null
+/*
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _IMX_SPI_NOR_H_
+#define _IMX_SPI_NOR_H_
+
+#define READ 0x03 /* tx:1 byte cmd + 3 byte addr;rx:variable bytes */
+#define READ_HS 0x0B /* tx:1 byte cmd + 3 byte addr + 1 byte dummy; */
+#define RDSR 0x05 /* read stat reg 1 byte tx cmd + 1 byte rx status */
+#define RDSR_BUSY (1 << 0) /* 1=write-in-progress (default 0) */
+#define RDSR_WEL (1 << 1) /* 1=write enable (default 0) */
+#define RDSR_BP0 (1 << 2) /* block write prot level (default 1) */
+#define RDSR_BP1 (1 << 3) /* block write prot level (default 1) */
+#define RDSR_BP2 (1 << 4) /* block write prot level (default 1) */
+#define RDSR_BP3 (1 << 5) /* block write prot level (default 1) */
+#define RDSR_AAI (1 << 6) /* 1=AAI prog mode; 0=byte prog (def 0) */
+#define RDSR_BPL (1 << 7) /* 1=BP3,BP2,BP1,BP0 RO; 0=R/W (def 0) */
+#define WREN 0x06 /* write enable. 1 byte tx cmd */
+#define WRDI 0x04 /* write disable. 1 byte tx cmd */
+#define EWSR 0x50 /* Enable write status. 1 byte tx cmd */
+#define WRSR 0x01 /* Write stat reg. 1 byte tx cmd + 1 byte tx val */
+#define ERASE_4K 0x20 /* sector erase. 1 byte cmd + 3 byte addr */
+#define ERASE_32K 0x52 /* 32K block erase. 1 byte cmd + 3 byte addr */
+#define ERASE_64K 0xD8 /* 64K block erase. 1 byte cmd + 3 byte addr */
+#define ERASE_CHIP 0x60 /* whole chip erase */
+#define BYTE_PROG 0x02 /* all tx: 1 cmd + 3 addr + 1 data */
+#define AAI_PROG 0xAD /* all tx: [1 cmd + 3 addr + 2 data] + RDSR */
+ /* + [1cmd + 2 data] + .. + [WRDI] + [RDSR] */
+#define JEDEC_ID 0x9F /* read JEDEC ID. tx: 1 byte cmd; rx: 3 byte ID */
+
+/* Atmel SPI-NOR commands */
+#define WR_2_MEM_DIR 0x82
+#define BUF1_WR 0x84
+#define BUF2_WR 0x87
+#define BUF1_TO_MEM 0x83
+#define BUF2_TO_MEM 0x86
+#define STAT_READ 0xD7
+#define STAT_PG_SZ (1 << 0) /* 1=Page size is 512, 0=Page size is 528 */
+#define STAT_PROT (1 << 1) /* 1=sector protection enabled (default 0) */
+#define STAT_COMP (1 << 6)
+#define STAT_BUSY (1 << 7) /* 1=Device not busy */
+#define CONFIG_REG1 0x3D
+#define CONFIG_REG2 0x2A
+#define CONFIG_REG3 0x80
+#define CONFIG_REG4 0xA6
+
+#define SZ_64K 0x10000
+#define SZ_32K 0x8000
+#define SZ_4K 0x1000
+
+#endif /* _IMX_SPI_NOR_H_ */
--- /dev/null
+/*
+ * IMX SSP MMC Defines
+ *-------------------------------------------------------------------
+ *
+ * Copyright (C) 2007-2008, 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *-------------------------------------------------------------------
+ *
+ */
+
+#ifndef __IMX_SSP_MMC_H__
+#define __IMX_SSP_MMC_H__
+
+/* Common definition */
+#define BM_CLKCTRL_SSP_CLKGATE 0x80000000
+#define BM_CLKCTRL_SSP_BUSY 0x20000000
+#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200
+#define BM_CLKCTRL_SSP_DIV 0x000001FF
+#define BP_CLKCTRL_SSP_DIV 0
+
+struct imx_ssp_mmc_cfg {
+ u32 ssp_mmc_base;
+
+ /* CLKCTRL register offset */
+ u32 clkctrl_ssp_offset;
+ u32 clkctrl_clkseq_ssp_offset;
+};
+
+#ifdef CONFIG_IMX_SSP_MMC
+int imx_ssp_mmc_initialize(bd_t *bis, struct imx_ssp_mmc_cfg *cfg);
+
+extern u32 ssp_mmc_is_wp(struct mmc *mmc);
+#endif /* CONFIG_IMX_SSP_MMC */
+
+#endif /* __IMX_SSP_MMC_H__ */
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de
*
- * Linux IPU driver for MX51:
+ * Linux IPU driver:
*
- * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
+ * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#define __ASM_ARCH_IPU_H__
#include <linux/types.h>
-#include <ipu_pixfmt.h>
+#include <linux/list.h>
+#include <linux/fb.h>
+
+struct clk;
#define IDMA_CHAN_INVALID 0xFF
#define HIGH_RESOLUTION_WIDTH 1024
-struct clk {
- const char *name;
- int id;
- /* Source clock this clk depends on */
- struct clk *parent;
- /* Secondary clock to enable/disable with this clock */
- struct clk *secondary;
- /* Current clock rate */
- unsigned long rate;
- /* Reference count of clock enable/disable */
- __s8 usecount;
- /* Register bit position for clock's enable/disable control. */
- u8 enable_shift;
- /* Register address for clock's enable/disable control. */
- void *enable_reg;
- u32 flags;
- /*
- * Function ptr to recalculate the clock's rate based on parent
- * clock's rate
- */
- void (*recalc) (struct clk *);
- /*
- * Function ptr to set the clock to a new rate. The rate must match a
- * supported rate returned from round_rate. Leave blank if clock is not
- * programmable
- */
- int (*set_rate) (struct clk *, unsigned long);
- /*
- * Function ptr to round the requested clock rate to the nearest
- * supported rate that is less than or equal to the requested rate.
- */
- unsigned long (*round_rate) (struct clk *, unsigned long);
- /*
- * Function ptr to enable the clock. Leave blank if clock can not
- * be gated.
- */
- int (*enable) (struct clk *);
- /*
- * Function ptr to disable the clock. Leave blank if clock can not
- * be gated.
- */
- void (*disable) (struct clk *);
- /* Function ptr to set the parent clock of the clock. */
- int (*set_parent) (struct clk *, struct clk *);
-};
-
/*
* Enumeration of Synchronous (Memory-less) panel types
*/
IPU_PANEL_TFT,
} ipu_panel_t;
+/* IPU Pixel format definitions */
+#define fourcc(a, b, c, d)\
+ (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
+
+/*
+ * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
+ * the same used by V4L2 API.
+ */
+
+#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0')
+#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1')
+#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6')
+#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8')
+
+#define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*< 8 RGB-3-3-2 */
+#define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*< 16 RGB-5-5-5 */
+#define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*< 1 6 RGB-5-6-5 */
+#define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*< 18 RGB-6-6-6 */
+#define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*< 18 BGR-6-6-6 */
+#define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*< 24 BGR-8-8-8 */
+#define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*< 24 RGB-8-8-8 */
+#define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*< 32 BGR-8-8-8-8 */
+#define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*< 32 BGR-8-8-8-8 */
+#define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*< 32 RGB-8-8-8-8 */
+#define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*< 32 RGB-8-8-8-8 */
+#define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*< 32 ABGR-8-8-8-8 */
+
+/* YUV Interleaved Formats */
+#define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*< 16 YUV 4:2:2 */
+#define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*< 16 YUV 4:2:2 */
+#define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*< 12 YUV 4:1:1 */
+#define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*< 24 YUV 4:4:4 */
+
+/* two planes -- one Y, one Cb + Cr interleaved */
+#define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
+
+#define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*< 8 Greyscale */
+#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*< 9 YVU 4:1:0 */
+#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*< 9 YUV 4:1:0 */
+#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*< 12 YVU 4:2:0 */
+#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*< 12 YUV 4:2:0 */
+#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*< 12 YUV 4:2:0 */
+#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*< 16 YVU 4:2:2 */
+#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */
+
/*
* IPU Driver channels definitions.
* Note these are different from IDMA channels
* Enumeration of types of buffers for a logical channel.
*/
typedef enum {
- IPU_OUTPUT_BUFFER = 0, /*< Buffer for output from IPU */
- IPU_ALPHA_IN_BUFFER = 1, /*< Buffer for input to IPU */
- IPU_GRAPH_IN_BUFFER = 2, /*< Buffer for input to IPU */
- IPU_VIDEO_IN_BUFFER = 3, /*< Buffer for input to IPU */
+ IPU_OUTPUT_BUFFER = 0, /* Buffer for output from IPU */
+ IPU_ALPHA_IN_BUFFER = 1, /* Buffer for input to IPU */
+ IPU_GRAPH_IN_BUFFER = 2, /* Buffer for input to IPU */
+ IPU_VIDEO_IN_BUFFER = 3, /* Buffer for input to IPU */
IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
} ipu_buffer_t;
+
+/*
+ * Enumeration of version of IPU V3 .
+ */
+typedef enum {
+ IPUV3_HW_REV_IPUV3DEX = 2, /* IPUv3D, IPUv3E IPUv3EX */
+ IPUV3_HW_REV_IPUV3M = 3, /* IPUv3M */
+ IPUV3_HW_REV_IPUV3H = 4, /* IPUv3H */
+} ipu3_hw_rev_t;
+
+
#define IPU_PANEL_SERIAL 1
#define IPU_PANEL_PARALLEL 2
YUV
} ipu_color_space_t;
+typedef enum {
+ DI_PCLK_PLL3,
+ DI_PCLK_LDB,
+ DI_PCLK_TVE
+} ipu_di_clk_parent_t;
+
/* Common IPU API */
+int ipuv3_fb_init(struct fb_videomode *mode, int di,
+ unsigned int interface_pix_fmt,
+ ipu_di_clk_parent_t di_clk_parent,
+ unsigned long di_clk_val, int bpp);
+
int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);
void ipu_uninit_channel(ipu_channel_t channel);
uint32_t bytes_per_pixel(uint32_t fmt);
-void clk_enable(struct clk *clk);
+int clk_enable(struct clk *clk);
void clk_disable(struct clk *clk);
u32 clk_get_rate(struct clk *clk);
int clk_set_rate(struct clk *clk, unsigned long rate);
struct clk *clk_get_parent(struct clk *clk);
void ipu_dump_registers(void);
-int ipu_probe(void);
+int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val);
void ipu_dmfc_init(int dmfc_type, int first);
void ipu_init_dc_mappings(void);
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de
- *
- * Based on Linux IPU driver for MX51 (ipu.h):
- *
- * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __IPU_PIXFMT_H__
-#define __IPU_PIXFMT_H__
-
-#include <linux/list.h>
-#include <linux/fb.h>
-
-/* IPU Pixel format definitions */
-#define fourcc(a, b, c, d)\
- (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
-
-/*
- * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
- * the same used by V4L2 API.
- */
-
-#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0')
-#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1')
-#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6')
-#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8')
-
-#define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*< 8 RGB-3-3-2 */
-#define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*< 16 RGB-5-5-5 */
-#define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*< 1 6 RGB-5-6-5 */
-#define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*< 18 RGB-6-6-6 */
-#define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*< 18 BGR-6-6-6 */
-#define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*< 24 BGR-8-8-8 */
-#define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*< 24 RGB-8-8-8 */
-#define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*< 32 BGR-8-8-8-8 */
-#define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*< 32 BGR-8-8-8-8 */
-#define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*< 32 RGB-8-8-8-8 */
-#define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*< 32 RGB-8-8-8-8 */
-#define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*< 32 ABGR-8-8-8-8 */
-
-/* YUV Interleaved Formats */
-#define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*< 16 YUV 4:2:2 */
-#define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*< 16 YUV 4:2:2 */
-#define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*< 12 YUV 4:1:1 */
-#define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*< 24 YUV 4:4:4 */
-
-/* two planes -- one Y, one Cb + Cr interleaved */
-#define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
-
-#define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*< 8 Greyscale */
-#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*< 9 YVU 4:1:0 */
-#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*< 9 YUV 4:1:0 */
-#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*< 12 YVU 4:2:0 */
-#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*< 12 YUV 4:2:0 */
-#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*< 12 YUV 4:2:0 */
-#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*< 16 YVU 4:2:2 */
-#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */
-
-int ipuv3_fb_init(struct fb_videomode const *mode,
- uint8_t disp,
- uint32_t pixfmt);
-void ipuv3_fb_shutdown(void);
-
-#endif
/*
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc.
+ *
* MPC823 and PXA LCD Controller
*
* Modeled after video interface by Paolo Scaffardi
/* Video functions */
-#if defined(CONFIG_RBC823)
void lcd_disable (void);
-#endif
-
+void lcd_panel_disable(void);
/* int lcd_init (void *lcdbase); */
void lcd_putc (const char c);
#define LCD_COLOR4 2
#define LCD_COLOR8 3
#define LCD_COLOR16 4
+#define LCD_COLOR24 5
/*----------------------------------------------------------------------*/
#if defined(CONFIG_LCD_INFO_BELOW_LOGO)
# define CONSOLE_COLOR_GREY 14
# define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */
-#else
+#elif LCD_BPP == LCD_COLOR16
/*
* 16bpp color definitions
*/
# define CONSOLE_COLOR_BLACK 0x0000
+# define CONSOLE_COLOR_RED 0xf800
+# define CONSOLE_COLOR_GREEN 0x07e0
+# define CONSOLE_COLOR_YELLOW 0xffe0
+# define CONSOLE_COLOR_BLUE 0x001f
+# define CONSOLE_COLOR_MAGENTA 0xf81f
+# define CONSOLE_COLOR_CYAN 0x07ff
+# define CONSOLE_COLOR_GREY 0xcccc
# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */
+#elif LCD_BPP == LCD_COLOR24
+/*
+ * 16bpp color definitions
+ */
+# define CONSOLE_COLOR_BLACK 0x00000000
+# define CONSOLE_COLOR_RED 0x00ff0000
+# define CONSOLE_COLOR_GREEN 0x0000ff00
+# define CONSOLE_COLOR_YELLOW 0x00ffff00
+# define CONSOLE_COLOR_BLUE 0x000000ff
+# define CONSOLE_COLOR_MAGENTA 0x00ff00ff
+# define CONSOLE_COLOR_CYAN 0x0000ffff
+# define CONSOLE_COLOR_GREY 0x00cccccc
+# define CONSOLE_COLOR_WHITE 0x00ffffff /* Must remain last / highest */
+#else
+#error Invalid LCD_BPP setting
#endif /* color definitions */
/************************************************************************/
#if LCD_BPP == LCD_MONOCHROME
# define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \
(c) << 4 | (c) << 5 | (c) << 6 | (c) << 7)
-#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16)
+#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) || (LCD_BPP == LCD_COLOR24)
# define COLOR_MASK(c) (c)
#else
# error Unsupported LCD BPP.
* NAND family Bad Block Management (BBM) header file
* - Bad Block Table (BBT) implementation
*
- * Copyright (c) 2005-2007 Samsung Electronics
+ * Copyright © 2005 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
- * Copyright (c) 2000-2005
+ * Copyright © 2000-2005
* Thomas Gleixner <tglx@linuxtronix.de>
*
* This program is free software; you can redistribute it and/or modify
/**
* struct nand_bbt_descr - bad block table descriptor
- * @param options options for this descriptor
- * @param pages the page(s) where we find the bbt, used with
- * option BBT_ABSPAGE when bbt is searched,
- * then we store the found bbts pages here.
- * Its an array and supports up to 8 chips now
- * @param offs offset of the pattern in the oob area of the page
- * @param veroffs offset of the bbt version counter in the oob are of the page
- * @param version version read from the bbt page during scan
- * @param len length of the pattern, if 0 no pattern check is performed
- * @param maxblocks maximum number of blocks to search for a bbt. This number of
- * blocks is reserved at the end of the device
- * where the tables are written.
- * @param reserved_block_code if non-0, this pattern denotes a reserved
- * (rather than bad) block in the stored bbt
- * @param pattern pattern to identify bad block table or factory marked
- * good / bad blocks, can be NULL, if len = 0
+ * @options: options for this descriptor
+ * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
+ * when bbt is searched, then we store the found bbts pages here.
+ * Its an array and supports up to 8 chips now
+ * @offs: offset of the pattern in the oob area of the page
+ * @veroffs: offset of the bbt version counter in the oob are of the page
+ * @version: version read from the bbt page during scan
+ * @len: length of the pattern, if 0 no pattern check is performed
+ * @maxblocks: maximum number of blocks to search for a bbt. This number of
+ * blocks is reserved at the end of the device where the tables are
+ * written.
+ * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
+ * bad) block in the stored bbt
+ * @pattern: pattern to identify bad block table or factory marked good /
+ * bad blocks, can be NULL, if len = 0
*
* Descriptor for the bad block table marker and the descriptor for the
* pattern which identifies good and bad blocks. The assumption is made
/*
* Constants for oob configuration
*/
-#define ONENAND_BADBLOCK_POS 0
+#define NAND_SMALL_BADBLOCK_POS 5
+#define NAND_LARGE_BADBLOCK_POS 0
+#define ONENAND_BADBLOCK_POS 0
/*
* Bad block scanning errors
*/
-#define ONENAND_BBT_READ_ERROR 1
-#define ONENAND_BBT_READ_ECC_ERROR 2
-#define ONENAND_BBT_READ_FATAL_ERROR 4
+#define ONENAND_BBT_READ_ERROR 1
+#define ONENAND_BBT_READ_ECC_ERROR 2
+#define ONENAND_BBT_READ_FATAL_ERROR 4
/**
- * struct bbt_info - [GENERIC] Bad Block Table data structure
- * @param bbt_erase_shift [INTERN] number of address bits in a bbt entry
- * @param badblockpos [INTERN] position of the bad block marker in the oob area
- * @param bbt [INTERN] bad block table pointer
- * @param badblock_pattern [REPLACEABLE] bad block scan pattern used for initial bad block scan
- * @param priv [OPTIONAL] pointer to private bbm date
+ * struct bbm_info - [GENERIC] Bad Block Table data structure
+ * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
+ * @badblockpos: [INTERN] position of the bad block marker in the oob area
+ * @options: options for this descriptor
+ * @bbt: [INTERN] bad block table pointer
+ * @isbad_bbt: function to determine if a block is bad
+ * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for
+ * initial bad block scan
+ * @priv: [OPTIONAL] pointer to private bbm date
*/
struct bbm_info {
int bbt_erase_shift;
uint8_t *bbt;
- int (*isbad_bbt) (struct mtd_info * mtd, loff_t ofs, int allowbbt);
+ int (*isbad_bbt)(struct mtd_info *mtd, loff_t ofs, int allowbbt);
/* TODO Add more NAND specific fileds */
struct nand_bbt_descr *badblock_pattern;
};
/* OneNAND BBT interface */
-extern int onenand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
-extern int onenand_default_bbt (struct mtd_info *mtd);
+extern int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
+extern int onenand_default_bbt(struct mtd_info *mtd);
-#endif /* __LINUX_MTD_BBM_H */
+#endif /* __LINUX_MTD_BBM_H */
--- /dev/null
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MAX8997_PMIC_H_
+#define __MAX8997_PMIC_H_
+
+/* MAX 8997 registers */
+enum {
+ MAX8997_REG_PMIC_ID0 = 0x00,
+ MAX8997_REG_PMIC_ID1 = 0x01,
+ MAX8997_REG_INTSRC = 0x02,
+ MAX8997_REG_INT1 = 0x03,
+ MAX8997_REG_INT2 = 0x04,
+ MAX8997_REG_INT3 = 0x05,
+ MAX8997_REG_INT4 = 0x06,
+
+ MAX8997_REG_INT1MSK = 0x08,
+ MAX8997_REG_INT2MSK = 0x09,
+ MAX8997_REG_INT3MSK = 0x0a,
+ MAX8997_REG_INT4MSK = 0x0b,
+
+ MAX8997_REG_STATUS1 = 0x0d,
+ MAX8997_REG_STATUS2 = 0x0e,
+ MAX8997_REG_STATUS3 = 0x0f,
+ MAX8997_REG_STATUS4 = 0x10,
+
+ MAX8997_REG_MAINCON1 = 0x13,
+ MAX8997_REG_MAINCON2 = 0x14,
+ MAX8997_REG_BUCKRAMP = 0x15,
+
+ MAX8997_REG_BUCK1CTRL = 0x18,
+ MAX8997_REG_BUCK1DVS1 = 0x19,
+ MAX8997_REG_BUCK1DVS2 = 0x1a,
+ MAX8997_REG_BUCK1DVS3 = 0x1b,
+ MAX8997_REG_BUCK1DVS4 = 0x1c,
+ MAX8997_REG_BUCK1DVS5 = 0x1d,
+ MAX8997_REG_BUCK1DVS6 = 0x1e,
+ MAX8997_REG_BUCK1DVS7 = 0x1f,
+ MAX8997_REG_BUCK1DVS8 = 0x20,
+ MAX8997_REG_BUCK2CTRL = 0x21,
+ MAX8997_REG_BUCK2DVS1 = 0x22,
+ MAX8997_REG_BUCK2DVS2 = 0x23,
+ MAX8997_REG_BUCK2DVS3 = 0x24,
+ MAX8997_REG_BUCK2DVS4 = 0x25,
+ MAX8997_REG_BUCK2DVS5 = 0x26,
+ MAX8997_REG_BUCK2DVS6 = 0x27,
+ MAX8997_REG_BUCK2DVS7 = 0x28,
+ MAX8997_REG_BUCK2DVS8 = 0x29,
+ MAX8997_REG_BUCK3CTRL = 0x2a,
+ MAX8997_REG_BUCK3DVS = 0x2b,
+ MAX8997_REG_BUCK4CTRL = 0x2c,
+ MAX8997_REG_BUCK4DVS = 0x2d,
+ MAX8997_REG_BUCK5CTRL = 0x2e,
+ MAX8997_REG_BUCK5DVS1 = 0x2f,
+ MAX8997_REG_BUCK5DVS2 = 0x30,
+ MAX8997_REG_BUCK5DVS3 = 0x31,
+ MAX8997_REG_BUCK5DVS4 = 0x32,
+ MAX8997_REG_BUCK5DVS5 = 0x33,
+ MAX8997_REG_BUCK5DVS6 = 0x34,
+ MAX8997_REG_BUCK5DVS7 = 0x35,
+ MAX8997_REG_BUCK5DVS8 = 0x36,
+ MAX8997_REG_BUCK6CTRL = 0x37,
+ MAX8997_REG_BUCK6BPSKIPCTRL = 0x38,
+ MAX8997_REG_BUCK7CTRL = 0x39,
+ MAX8997_REG_BUCK7DVS = 0x3a,
+ MAX8997_REG_LDO1CTRL = 0x3b,
+ MAX8997_REG_LDO2CTRL = 0x3c,
+ MAX8997_REG_LDO3CTRL = 0x3d,
+ MAX8997_REG_LDO4CTRL = 0x3e,
+ MAX8997_REG_LDO5CTRL = 0x3f,
+ MAX8997_REG_LDO6CTRL = 0x40,
+ MAX8997_REG_LDO7CTRL = 0x41,
+ MAX8997_REG_LDO8CTRL = 0x42,
+ MAX8997_REG_LDO9CTRL = 0x43,
+ MAX8997_REG_LDO10CTRL = 0x44,
+ MAX8997_REG_LDO11CTRL = 0x45,
+ MAX8997_REG_LDO12CTRL = 0x46,
+ MAX8997_REG_LDO13CTRL = 0x47,
+ MAX8997_REG_LDO14CTRL = 0x48,
+ MAX8997_REG_LDO15CTRL = 0x49,
+ MAX8997_REG_LDO16CTRL = 0x4a,
+ MAX8997_REG_LDO17CTRL = 0x4b,
+ MAX8997_REG_LDO18CTRL = 0x4c,
+ MAX8997_REG_LDO21CTRL = 0x4d,
+
+ MAX8997_REG_MBCCTRL1 = 0x50,
+ MAX8997_REG_MBCCTRL2 = 0x51,
+ MAX8997_REG_MBCCTRL3 = 0x52,
+ MAX8997_REG_MBCCTRL4 = 0x53,
+ MAX8997_REG_MBCCTRL5 = 0x54,
+ MAX8997_REG_MBCCTRL6 = 0x55,
+ MAX8997_REG_OTPCGHCVS = 0x56,
+
+ MAX8997_REG_SAFEOUTCTRL = 0x5a,
+
+ MAX8997_REG_LBCNFG1 = 0x5e,
+ MAX8997_REG_LBCNFG2 = 0x5f,
+ MAX8997_REG_BBCCTRL = 0x60,
+
+ MAX8997_REG_FLASH1_CUR = 0x63, /* 0x63 ~ 0x6e for FLASH */
+ MAX8997_REG_FLASH2_CUR = 0x64,
+ MAX8997_REG_MOVIE_CUR = 0x65,
+ MAX8997_REG_GSMB_CUR = 0x66,
+ MAX8997_REG_BOOST_CNTL = 0x67,
+ MAX8997_REG_LEN_CNTL = 0x68,
+ MAX8997_REG_FLASH_CNTL = 0x69,
+ MAX8997_REG_WDT_CNTL = 0x6a,
+ MAX8997_REG_MAXFLASH1 = 0x6b,
+ MAX8997_REG_MAXFLASH2 = 0x6c,
+ MAX8997_REG_FLASHSTATUS = 0x6d,
+ MAX8997_REG_FLASHSTATUSMASK = 0x6e,
+
+ MAX8997_REG_GPIOCNTL1 = 0x70,
+ MAX8997_REG_GPIOCNTL2 = 0x71,
+ MAX8997_REG_GPIOCNTL3 = 0x72,
+ MAX8997_REG_GPIOCNTL4 = 0x73,
+ MAX8997_REG_GPIOCNTL5 = 0x74,
+ MAX8997_REG_GPIOCNTL6 = 0x75,
+ MAX8997_REG_GPIOCNTL7 = 0x76,
+ MAX8997_REG_GPIOCNTL8 = 0x77,
+ MAX8997_REG_GPIOCNTL9 = 0x78,
+ MAX8997_REG_GPIOCNTL10 = 0x79,
+ MAX8997_REG_GPIOCNTL11 = 0x7a,
+ MAX8997_REG_GPIOCNTL12 = 0x7b,
+
+ MAX8997_REG_LDO1CONFIG = 0x80,
+ MAX8997_REG_LDO2CONFIG = 0x81,
+ MAX8997_REG_LDO3CONFIG = 0x82,
+ MAX8997_REG_LDO4CONFIG = 0x83,
+ MAX8997_REG_LDO5CONFIG = 0x84,
+ MAX8997_REG_LDO6CONFIG = 0x85,
+ MAX8997_REG_LDO7CONFIG = 0x86,
+ MAX8997_REG_LDO8CONFIG = 0x87,
+ MAX8997_REG_LDO9CONFIG = 0x88,
+ MAX8997_REG_LDO10CONFIG = 0x89,
+ MAX8997_REG_LDO11CONFIG = 0x8a,
+ MAX8997_REG_LDO12CONFIG = 0x8b,
+ MAX8997_REG_LDO13CONFIG = 0x8c,
+ MAX8997_REG_LDO14CONFIG = 0x8d,
+ MAX8997_REG_LDO15CONFIG = 0x8e,
+ MAX8997_REG_LDO16CONFIG = 0x8f,
+ MAX8997_REG_LDO17CONFIG = 0x90,
+ MAX8997_REG_LDO18CONFIG = 0x91,
+ MAX8997_REG_LDO21CONFIG = 0x92,
+
+ MAX8997_REG_DVSOKTIMER1 = 0x97,
+ MAX8997_REG_DVSOKTIMER2 = 0x98,
+ MAX8997_REG_DVSOKTIMER4 = 0x99,
+ MAX8997_REG_DVSOKTIMER5 = 0x9a,
+
+ PMIC_NUM_OF_REGS = 0x9b,
+};
+
+#define ENSAFEOUT1 (1 << 6)
+#define ENSAFEOUT2 (1 << 7)
+
+#define MAX8997_I2C_ADDR (0xCC >> 1)
+#define MAX8997_RTC_ADDR (0x0C >> 1)
+#define MAX8997_MUIC_ADDR (0x4A >> 1)
+#define MAX8997_FG_ADDR (0x6C >> 1)
+
+enum {
+ LDO_OFF = 0,
+ LDO_ON = 1,
+
+ DIS_LDO = (0x00 << 6),
+ EN_LDO = (0x3 << 6),
+};
+
+#endif /* __MAX8997_PMIC_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mx2fb.h
+ *
+ * @brief MX 25 LCD controller header file.
+ *
+ *
+ */
+
+#ifndef __MX2FB_H__
+#define __MX2FB_H__
+
+
+/* LCDC register settings */
+
+#define LCDC_LSCR 0x00120300
+
+#define LCDC_LRMCR 0x00000000
+
+#define LCDC_LDCR 0x00020010
+
+#define LCDC_LPCCR 0x00a9037f
+
+#define LCDC_LPCR 0xFA008B80
+
+#define LCDC_LPCR_PCD 0x4
+
+#define FB_SYNC_OE_LOW_ACT 0x80000000
+#define FB_SYNC_CLK_LAT_FALL 0x40000000
+#define FB_SYNC_DATA_INVERT 0x20000000
+#define FB_SYNC_CLK_IDLE_EN 0x10000000
+#define FB_SYNC_SHARP_MODE 0x08000000
+#define FB_SYNC_SWAP_RGB 0x04000000
+
+#endif /* __MX2FB_H__ */
--- /dev/null
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup keypad Keypad Driver
+ */
+
+/*!
+ * @file mxc_keyb.h
+ *
+ * @brief MXC keypad header file.
+ *
+ * @ingroup keypad
+ */
+#ifndef __MXC_KEYB_H__
+#define __MXC_KEYB_H__
+
+/*!
+ * Keypad Module Name
+ */
+#define MOD_NAME "mxckpd"
+
+/*!
+ * Keypad irq number
+ */
+#define KPP_IRQ MXC_INT_KPP
+
+/*!
+ * XLATE mode selection
+ */
+#define KEYPAD_XLATE 0
+
+/*!
+ * RAW mode selection
+ */
+#define KEYPAD_RAW 1
+
+/*!
+ * Maximum number of keys.
+ */
+#define MAXROW 8
+#define MAXCOL 8
+#define MXC_MAXKEY (MAXROW * MAXCOL)
+
+/*!
+ * This define indicates break scancode for every key release. A constant
+ * of 128 is added to the key press scancode.
+ */
+#define MXC_KEYRELEASE 128
+
+/*
+ * _reg_KPP_KPCR _reg_KPP_KPSR _reg_KPP_KDDR _reg_KPP_KPDR
+ * Keypad Control Register Address
+ */
+#define KPCR (KPP_BASE_ADDR + 0x00)
+
+/*
+ * Keypad Status Register Address
+ */
+#define KPSR (KPP_BASE_ADDR + 0x02)
+
+/*
+ * Keypad Data Direction Address
+ */
+#define KDDR (KPP_BASE_ADDR + 0x04)
+
+/*
+ * Keypad Data Register
+ */
+#define KPDR (KPP_BASE_ADDR + 0x06)
+
+/*
+ * Key Press Interrupt Status bit
+ */
+#define KBD_STAT_KPKD 0x01
+
+/*
+ * Key Release Interrupt Status bit
+ */
+#define KBD_STAT_KPKR 0x02
+
+/*
+ * Key Depress Synchronizer Chain Status bit
+ */
+#define KBD_STAT_KDSC 0x04
+
+/*
+ * Key Release Synchronizer Status bit
+ */
+#define KBD_STAT_KRSS 0x08
+
+/*
+ * Key Depress Interrupt Enable Status bit
+ */
+#define KBD_STAT_KDIE 0x100
+
+/*
+ * Key Release Interrupt Enable
+ */
+#define KBD_STAT_KRIE 0x200
+
+/*
+ * Keypad Clock Enable
+ */
+#define KBD_STAT_KPPEN 0x400
+
+/*!
+ * Buffer size of keypad queue. Should be a power of 2.
+ */
+#define KPP_BUF_SIZE 128
+
+/*!
+ * Test whether bit is set for integer c
+ */
+#define TEST_BIT(c, n) ((c) & (0x1 << (n)))
+
+/*!
+ * Set nth bit in the integer c
+ */
+#define BITSET(c, n) ((c) | (1 << (n)))
+
+/*!
+ * Reset nth bit in the integer c
+ */
+#define BITRESET(c, n) ((c) & ~(1 << (n)))
+
+enum KeyEvent {
+ KDepress,
+ KRelease
+};
+
+/*!
+ * This enum represents the keypad state machine to maintain debounce logic
+ * for key press/release.
+ */
+enum KeyState {
+
+ /*!
+ * Key press state.
+ */
+ KStateUp,
+
+ /*!
+ * Key press debounce state.
+ */
+ KStateFirstDown,
+
+ /*!
+ * Key release state.
+ */
+ KStateDown,
+
+ /*!
+ * Key release debounce state.
+ */
+ KStateFirstUp
+};
+
+/*!
+ * Keypad Private Data Structure
+ */
+typedef struct keypad_priv {
+
+ /*!
+ * Keypad state machine.
+ */
+ enum KeyState iKeyState;
+
+ /*!
+ * Number of rows configured in the keypad matrix
+ */
+ unsigned long kpp_rows;
+
+ /*!
+ * Number of Columns configured in the keypad matrix
+ */
+ unsigned long kpp_cols;
+} keypad_priv;
+
+/*!
+ * Keypad Data Structure
+ * */
+struct kpp_key_info {
+ enum KeyEvent evt;
+ unsigned short val;
+};
+
+int mxc_kpp_init(void);
+int mxc_kpp_getc(struct kpp_key_info *);
+
+#endif /* __MXC_KEYB_H__ */
#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)
#define CONFIG_SYS_NAND_SELF_INIT
#endif
+#if defined(CONFIG_NAND_MXC)
+#define CONFIG_SYS_NAND_SELF_INIT
+#endif
extern void nand_init(void);
enum proto_t {
BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP,
- TFTPSRV, TFTPPUT, LINKLOCAL
+ TFTPSRV, TFTPPUT, LINKLOCAL, BOOTME
};
/* from net/net.c */
net_loop_last_protocol = protocol;
#endif
}
+#ifdef CONFIG_CMD_BOOTCE
+void BootmeStart(void);
+#endif
/*
* Check if autoload is enabled. If so, use either NFS or TFTP to download
int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
#endif /* CONFIG_MV88E61XX_SWITCH */
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+enum {
+ CPSW_CTRL_VERSION_1 = 0, /* version1 devices */
+ CPSW_CTRL_VERSION_2 /* version2 devices */
+};
+
+struct cpsw_slave_data {
+ u32 slave_reg_ofs;
+ u32 sliver_reg_ofs;
+ int phy_id;
+ int phy_if;
+};
+
+struct cpsw_platform_data {
+ u32 mdio_base;
+ u32 cpsw_base;
+ int mdio_div;
+ int channels; /* number of cpdma channels (symmetric) */
+ u32 cpdma_reg_ofs; /* cpdma register offset */
+ int slaves; /* number of slave cpgmac ports */
+ u32 ale_reg_ofs; /* address lookup engine reg offset */
+ int ale_entries; /* ale table size */
+ u32 host_port_reg_ofs; /* cpdma host port registers */
+ u32 hw_stats_reg_ofs; /* cpsw hw stats counters */
+ u32 mac_control;
+ struct cpsw_slave_data *slave_data;
+ void (*control)(int enabled);
+ void (*phy_init)(char *name, int addr);
+ u32 gigabit_en; /* gigabit capable AND enabled */
+ u32 host_port_num;
+ u8 version;
+};
+
+int cpsw_register(struct cpsw_platform_data *data);
+
+#endif /* CONFIG_DRIVER_TI_CPSW */
/*
* Allow FEC to fine-tune MII configuration on boards which require this.
*/
--- /dev/null
+#ifndef __PATA_H__
+#define __PATA_H__
+
+/*
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/types.h>
+
+int init_pata(int dev);
+int scan_pata(int dev);
+ulong pata_read(int dev, ulong blknr, ulong blkcnt, void *buffer);
+ulong pata_write(int dev, ulong blknr, ulong blkcnt, const void *buffer);
+
+int pata_initialize();
+
+#endif
int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg);
int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg);
void twl6035_init_settings(void);
-int twl6035_mmc1_poweron_ldo(void);
+void twl6035_mmc1_poweron_ldo(void);
--- /dev/null
+/*
+ * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __WINCE_H__
+#define __WINCE_H__
+
+/* Bin image parse results */
+#define CE_PR_EOF 0
+#define CE_PR_MORE 1
+#define CE_PR_ERROR 2
+
+#pragma pack(1)
+
+/* Edbg BOOTME packet structures */
+typedef struct {
+ unsigned int id; /* Protocol identifier ("EDBG" on the wire) */
+ unsigned char service; /* Service identifier */
+ unsigned char flags; /* Flags (see defs below) */
+ unsigned char seqNum; /* For detection of dropped packets */
+ unsigned char cmd; /* For administrative messages */
+ uchar data[]; /* Cmd specific data starts here (format is determined by
+ * Cmd, len is determined by UDP packet size)
+ */
+} eth_dbg_hdr;
+
+#define OFFSETOF(s,m) ((unsigned int)&(((s*)0)->m))
+#define EDBG_DATA_OFFSET (OFFSETOF(eth_dbg_hdr, data))
+
+typedef struct {
+ unsigned char versionMajor; /* Bootloader version */
+ unsigned char versionMinor; /* Bootloader version */
+ unsigned char macAddr[6]; /* Ether address of device (net byte order) */
+ unsigned int ipAddr; /* IP address of device (net byte order) */
+ char platformId[17]; /* Platform Id string (NULL terminated) */
+ char deviceName[17]; /* Device name string (NULL terminated). Should include
+ * platform and number based on Ether address
+ * (e.g. Odo42, CEPCLS2346, etc)
+ */
+ unsigned char cpuId; /* CPU identifier (upper nibble = type) */
+/* The following fields were added in CE 3.0 Platform Builder release */
+ unsigned char bootmeVer; /* BOOTME Version.
+ * Must be in the range 2 -> EDBG_CURRENT_BOOTME_VERSION,
+ * or remaining fields will be ignored by Eshell and defaults will be used.
+ */
+ unsigned int bootFlags; /* Boot Flags */
+ unsigned short downloadPort; /* Download Port (net byte order) (0 -> EDBG_DOWNLOAD_PORT) */
+ unsigned short svcPort; /* Service Port (net byte order) (0 -> EDBG_SVC_PORT) */
+} edbg_bootme_data;
+
+#define BOOTME_PKT_SIZE (EDBG_DATA_OFFSET + sizeof(edbg_bootme_data))
+
+// WinCE .BIN file format signature
+#define CE_BIN_SIGN "B000FF\x0A"
+#define CE_BIN_SIGN_LEN 7
+
+typedef struct {
+ unsigned char sign[CE_BIN_SIGN_LEN];
+ unsigned int rtiPhysAddr;
+ unsigned int rtiPhysLen;
+} ce_bin_hdr;
+
+typedef struct {
+ unsigned int physAddr;
+ unsigned int physLen;
+ unsigned int chkSum;
+ unsigned char data[];
+} ce_bin_entry;
+
+// CE ROM image structures
+
+#define ROM_SIGNATURE_OFFSET 0x40 /* Offset from the image's physfirst address to the ROM signature. */
+#define ROM_SIGNATURE 0x43454345 /* Signature 'CECE' (little endian) */
+#define ROM_TOC_POINTER_OFFSET 0x44 /* Offset from the image's physfirst address to the TOC pointer. */
+#define ROM_TOC_OFFSET_OFFSET 0x48 /* Offset from the image's physfirst address to the TOC offset (from physfirst). */
+
+typedef struct {
+ unsigned int dllfirst; /* first DLL address */
+ unsigned int dlllast; /* last DLL address */
+ unsigned int physfirst; /* first physical address */
+ unsigned int physlast; /* highest physical address */
+ unsigned int nummods; /* number of TOCentry's */
+ unsigned int ramStart; /* start of RAM */
+ unsigned int ramFree; /* start of RAM free space */
+ unsigned int ramEnd; /* end of RAM */
+ unsigned int copyEntries; /* number of copy section entries */
+ unsigned int copyOffset; /* offset to copy section */
+ unsigned int profileLen; /* length of PROFentries RAM */
+ unsigned int profileOffset; /* offset to PROFentries */
+ unsigned int numfiles; /* number of FILES */
+ unsigned int kernelFlags; /* optional kernel flags from ROMFLAGS .bib config option */
+ unsigned int fsRamPercent; /* Percentage of RAM used for filesystem */
+/* from FSRAMPERCENT .bib config option
+ * byte 0 = #4K chunks/Mbyte of RAM for filesystem 0-2Mbytes 0-255
+ * byte 1 = #4K chunks/Mbyte of RAM for filesystem 2-4Mbytes 0-255
+ * byte 2 = #4K chunks/Mbyte of RAM for filesystem 4-6Mbytes 0-255
+ * byte 3 = #4K chunks/Mbyte of RAM for filesystem > 6Mbytes 0-255
+ */
+ unsigned int drivglobStart; /* device driver global starting address */
+ unsigned int drivglobLen; /* device driver global length */
+ unsigned short cpuType; /* CPU (machine) Type */
+ unsigned short miscFlags; /* Miscellaneous flags */
+ void *extensions; /* pointer to ROM Header extensions */
+ unsigned int trackingStart; /* tracking memory starting address */
+ unsigned int trackingLen; /* tracking memory ending address */
+} ce_rom_hdr;
+
+/* Win32 FILETIME strcuture */
+typedef struct {
+ unsigned int loDateTime;
+ unsigned int hiDateTime;
+} ce_file_time;
+
+/* Table Of Contents entry structure */
+typedef struct {
+ unsigned int fileAttributes;
+ ce_file_time fileTime;
+ unsigned int fileSize;
+ char *fileName;
+ unsigned int e32Offset; /* Offset to E32 structure */
+ unsigned int o32Offset; /* Offset to O32 structure */
+ unsigned int loadOffset; /* MODULE load buffer offset */
+} ce_toc_entry;
+
+/* Extra information header block */
+typedef struct {
+ unsigned int rva; /* Virtual relative address of info */
+ unsigned int size; /* Size of information block */
+} e32_info;
+
+#define ROM_EXTRA 9
+
+typedef struct {
+ unsigned short e32_objcnt; /* Number of memory objects */
+ unsigned short e32_imageflags; /* Image flags */
+ unsigned int e32_entryrva; /* Relative virt. addr. of entry point */
+ unsigned int e32_vbase; /* Virtual base address of module */
+ unsigned short e32_subsysmajor;/* The subsystem major version number */
+ unsigned short e32_subsysminor;/* The subsystem minor version number */
+ unsigned int e32_stackmax; /* Maximum stack size */
+ unsigned int e32_vsize; /* Virtual size of the entire image */
+ unsigned int e32_sect14rva; /* section 14 rva */
+ unsigned int e32_sect14size; /* section 14 size */
+ unsigned int e32_timestamp; /* Time EXE/DLL was created/modified */
+ e32_info e32_unit[ROM_EXTRA]; /* Array of extra info units */
+ unsigned short e32_subsys; /* The subsystem type */
+} e32_rom;
+
+/* OS config msg */
+
+#define EDBG_FL_DBGMSG 0x01 /* Debug messages */
+#define EDBG_FL_PPSH 0x02 /* Text shell */
+#define EDBG_FL_KDBG 0x04 /* Kernel debugger */
+#define EDBG_FL_CLEANBOOT 0x08 /* Force a clean boot */
+
+typedef struct {
+ unsigned char flags; /* Flags that will be used to determine what features are
+ * enabled over ethernet (saved in driver globals by bootloader)
+ */
+ unsigned char kitlTransport; /* Tells KITL which transport to start */
+
+ /* The following specify addressing info, only valid if the corresponding
+ * flag is set in the Flags field.
+ */
+ unsigned int dbgMsgIPAddr;
+ unsigned short dbgMsgPort;
+ unsigned int ppshIPAddr;
+ unsigned short ppshPort;
+ unsigned int kdbgIPAddr;
+ unsigned short kdbgPort;
+} edbg_os_config_data;
+
+/* Driver globals structure
+ * Used to pass driver globals info from RedBoot to WinCE core
+ */
+#define DRV_GLB_SIGNATURE 0x424C4744 /* "DGLB" */
+#define STD_DRV_GLB_SIGNATURE 0x53475241 /* "ARGS" */
+
+typedef struct {
+ unsigned int signature; /* Signature */
+ unsigned int flags; /* Misc flags */
+ unsigned int ipAddr; /* IP address of device (net byte order) */
+ unsigned int ipGate; /* IP address of gateway (net byte order) */
+ unsigned int ipMask; /* Subnet mask */
+ unsigned char macAddr[6]; /* Ether address of device (net byte order) */
+ edbg_os_config_data edbgConfig; /* EDBG services info */
+} ce_driver_globals;
+
+#pragma pack(4)
+
+typedef struct
+{
+ unsigned long signature;
+ unsigned short oalVersion;
+ unsigned short bspVersion;
+} OAL_ARGS_HEADER;
+
+typedef struct _DEVICE_LOCATION
+{
+ unsigned long IfcType;
+ unsigned long BusNumber;
+ unsigned long LogicalLoc;
+ void *PhysicalLoc;
+ unsigned long Pin;
+} DEVICE_LOCATION;
+
+typedef struct
+{
+ unsigned long flags;
+ DEVICE_LOCATION devLoc;
+ union {
+ struct {
+ unsigned long baudRate;
+ unsigned long dataBits;
+ unsigned long stopBits;
+ unsigned long parity;
+ };
+ struct {
+ unsigned short mac[3];
+ unsigned long ipAddress;
+ unsigned long ipMask;
+ unsigned long ipRoute;
+ };
+ };
+} OAL_KITL_ARGS;
+
+typedef struct
+{
+ OAL_ARGS_HEADER header;
+ char deviceId[16]; // Device identification
+ OAL_KITL_ARGS kitl;
+ char mtdparts[];
+} ce_std_driver_globals;
+
+typedef struct {
+ void *rtiPhysAddr;
+ unsigned int rtiPhysLen;
+ void *ePhysAddr;
+ unsigned int ePhysLen;
+ unsigned int eChkSum;
+
+ void *eEntryPoint;
+ void *eRamStart;
+ unsigned int eRamLen;
+ ce_driver_globals *eDrvGlb;
+
+ unsigned char parseState;
+ unsigned int parseChkSum;
+ int parseLen;
+ unsigned char *parsePtr;
+ int section;
+
+ int dataLen;
+ unsigned char *data;
+
+ int binLen;
+ int endOfBin;
+
+ edbg_os_config_data edbgConfig;
+} ce_bin;
+
+/* IPv4 support */
+
+/* Socket/connection information */
+struct sockaddr_in {
+ IPaddr_t sin_addr;
+ unsigned short sin_port;
+ unsigned short sin_family;
+ short sin_len;
+};
+
+#define AF_INET 1
+#define INADDR_ANY 0
+#ifndef ETH_ALEN
+#define ETH_ALEN 6
+#endif
+
+enum bootme_state {
+ BOOTME_INIT,
+ BOOTME_DOWNLOAD,
+ BOOTME_DEBUG,
+ BOOTME_DONE,
+ BOOTME_ERROR,
+};
+
+typedef struct {
+ int verbose;
+ int link;
+#ifdef BORKED
+ struct sockaddr_in locAddr;
+ struct sockaddr_in srvAddrSend;
+ struct sockaddr_in srvAddrRecv;
+#else
+ IPaddr_t server_ip;
+#endif
+ int gotJumpingRequest;
+ int dataLen;
+// int align_offset;
+// int got_packet_4me;
+// int status;
+ enum bootme_state state;
+ unsigned short blockNum;
+ unsigned char seqNum;
+ unsigned char pad;
+#if 0
+ unsigned char data[PKTSIZE_ALIGN];
+#else
+ unsigned char *data;
+#endif
+} ce_net;
+
+struct timeval {
+ long tv_sec; /* seconds */
+ long tv_usec; /* and microseconds */
+};
+
+/* Default UDP ports used for Ethernet download and EDBG messages. May be overriden
+ * by device in BOOTME message.
+ */
+#define EDBG_DOWNLOAD_PORT 980 /* For downloading images to bootloader via TFTP */
+#define EDBG_SVC_PORT 981 /* Other types of transfers */
+
+/* Byte string for Id field (note - must not conflict with valid TFTP
+ * opcodes (0-5), as we share the download port with TFTP)
+ */
+#define EDBG_ID 0x47424445 /* "EDBG" */
+
+/* Defs for reserved values of the Service field */
+#define EDBG_SVC_DBGMSG 0 /* Debug messages */
+#define EDBG_SVC_PPSH 1 /* Text shell and PPFS file system */
+#define EDBG_SVC_KDBG 2 /* Kernel debugger */
+#define EDBG_SVC_ADMIN 0xFF /* Administrative messages */
+
+/* Commands */
+#define EDBG_CMD_READ_REQ 1 /* Read request */
+#define EDBG_CMD_WRITE_REQ 2 /* Write request */
+#define EDBG_CMD_WRITE 3 /* Host ack */
+#define EDBG_CMD_WRITE_ACK 4 /* Target ack */
+#define EDBG_CMD_ERROR 5 /* Error */
+
+/* Service Ids from 3-FE are used for user apps */
+#define NUM_DFLT_EDBG_SERVICES 3
+
+/* Size of send and receive windows (except for stop and wait mode) */
+#define EDBG_WINDOW_SIZE 8
+
+/* The window size can be negotiated up to this amount if a client provides
+* enough memory.
+ */
+#define EDBG_MAX_WINDOW_SIZE 16
+
+/* Max size for an EDBG frame. Based on ethernet MTU - protocol overhead.
+* Limited to one MTU because we don't do IP fragmentation on device.
+ */
+#define EDBG_MAX_DATA_SIZE 1446
+
+/* Defs for Flags field. */
+#define EDBG_FL_FROM_DEV 0x01 /* Set if message is from the device */
+#define EDBG_FL_NACK 0x02 /* Set if frame is a nack */
+#define EDBG_FL_ACK 0x04 /* Set if frame is an ack */
+#define EDBG_FL_SYNC 0x08 /* Can be used to reset sequence # to 0 */
+#define EDBG_FL_ADMIN_RESP 0x10 /* For admin messages, indicate whether this is a response */
+
+/* Definitions for Cmd field (used for administrative messages) */
+/* Msgs from device */
+#define EDBG_CMD_BOOTME 0 /* Initial bootup message from device */
+
+/* Msgs from PC */
+#define EDBG_CMD_SETDEBUG 1 /* Used to set debug zones on device (TBD) */
+#define EDBG_CMD_JUMPIMG 2 /* Command to tell bootloader to jump to existing
+ * flash or RAM image. Data is same as CMD_OS_CONFIG. */
+#define EDBG_CMD_OS_CONFIG 3 /* Configure OS for debug ethernet services */
+#define EDBG_CMD_QUERYINFO 4 /* "Ping" device, and return information (same fmt as bootme) */
+#define EDBG_CMD_RESET 5 /* Command to have platform perform SW reset (e.g. so it
+ * can be reprogrammed). Support for this command is
+ * processor dependant, and may not be implemented
+ * on all platforms (requires HW mods for Odo).
+ */
+/* Msgs from device or PC */
+#define EDBG_CMD_SVC_CONFIG 6
+#define EDBG_CMD_SVC_DATA 7
+
+#define EDBG_CMD_DEBUGBREAK 8 /* Break into debugger */
+
+/* Structures for Data portion of EDBG packets */
+#define EDBG_MAX_DEV_NAMELEN 16
+
+/* BOOTME message - Devices broadcast this message when booted to request configuration */
+#define EDBG_CURRENT_BOOTME_VERSION 2
+
+/*
+ * Capability and boot Flags for dwBootFlags in EDBG_BOOTME_DATA
+ * LOWORD for boot flags, HIWORD for capability flags
+ */
+
+/* Always download image */
+#define EDBG_BOOTFLAG_FORCE_DOWNLOAD 0x00000001
+
+/* Support passive-kitl */
+#define EDBG_CAPS_PASSIVEKITL 0x00010000
+
+/* Defs for CPUId */
+#define EDBG_CPU_TYPE_SHX 0x10
+#define EDBG_CPU_TYPE_MIPS 0x20
+#define EDBG_CPU_TYPE_X86 0x30
+#define EDBG_CPU_TYPE_ARM 0x40
+#define EDBG_CPU_TYPE_PPC 0x50
+#define EDBG_CPU_TYPE_THUMB 0x60
+
+#define EDBG_CPU_SH3 (EDBG_CPU_TYPE_SHX | 0)
+#define EDBG_CPU_SH4 (EDBG_CPU_TYPE_SHX | 1)
+#define EDBG_CPU_R3000 (EDBG_CPU_TYPE_MIPS | 0)
+#define EDBG_CPU_R4101 (EDBG_CPU_TYPE_MIPS | 1)
+#define EDBG_CPU_R4102 (EDBG_CPU_TYPE_MIPS | 2)
+#define EDBG_CPU_R4111 (EDBG_CPU_TYPE_MIPS | 3)
+#define EDBG_CPU_R4200 (EDBG_CPU_TYPE_MIPS | 4)
+#define EDBG_CPU_R4300 (EDBG_CPU_TYPE_MIPS | 5)
+#define EDBG_CPU_R5230 (EDBG_CPU_TYPE_MIPS | 6)
+#define EDBG_CPU_R5432 (EDBG_CPU_TYPE_MIPS | 7)
+#define EDBG_CPU_i486 (EDBG_CPU_TYPE_X86 | 0)
+#define EDBG_CPU_SA1100 (EDBG_CPU_TYPE_ARM | 0)
+#define EDBG_CPU_ARM720 (EDBG_CPU_TYPE_ARM | 1)
+#define EDBG_CPU_PPC821 (EDBG_CPU_TYPE_PPC | 0)
+#define EDBG_CPU_PPC403 (EDBG_CPU_TYPE_PPC | 1)
+#define EDBG_CPU_THUMB720 (EDBG_CPU_TYPE_THUMB | 0)
+
+typedef enum bootme_state bootme_hand_f(const void *pkt, size_t len);
+
+int bootme_recv_frame(void *buf, size_t len, int timeout);
+int bootme_send_frame(const void *buf, size_t len);
+//void bootme_init(IPaddr_t server_ip);
+int BootMeRequest(IPaddr_t server_ip, const void *buf, size_t len, int timeout);
+//int ce_download_handler(const void *buf, size_t len);
+int BootMeDownload(bootme_hand_f *pkt_handler);
+int BootMeDebugStart(bootme_hand_f *pkt_handler);
+#endif
LIB = $(obj)libnet.o
+COBJS-$(CONFIG_CMD_BOOTCE) += bootme.o
COBJS-$(CONFIG_CMD_NET) += arp.o
COBJS-$(CONFIG_CMD_NET) += bootp.o
COBJS-$(CONFIG_CMD_CDP) += cdp.o
#define CONFIG_DHCP_MIN_EXT_LEN 64
#endif
-ulong BootpID;
+static ulong BootpID;
int BootpTry;
#if defined(CONFIG_CMD_DHCP)
*/
/* bootp.c */
-extern ulong BootpID; /* ID of cur BOOTP request */
extern char BootFile[128]; /* Boot file name */
extern int BootpTry;
case LINKLOCAL:
link_local_start();
break;
+#endif
+#if defined(CONFIG_CMD_BOOTCE)
+ case BOOTME:
+ BootmeStart();
+ break;
#endif
default:
break;
* Check for a timeout, and run the timeout handler
* if we have one.
*/
- if (timeHandler && ((get_timer(0) - timeStart) > timeDelta)) {
+ if (timeHandler && ((get_timer(timeStart)) > timeDelta)) {
thand_f *x;
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
sprintf(buf, "%lX", (unsigned long)load_addr);
setenv("fileaddr", buf);
}
- if (protocol != NETCONS)
+ if (protocol != NETCONS) {
eth_halt();
- else
+ } else {
eth_halt_state_only();
+ }
eth_set_last_protocol(protocol);
static int net_check_prereq(enum proto_t protocol)
{
switch (protocol) {
- /* Fall through */
#if defined(CONFIG_CMD_PING)
case PING:
if (NetPingIP == 0) {
#endif
/* Fall through */
+ case BOOTME:
case NETCONS:
case TFTPSRV:
if (NetOurIP == 0) {
--- /dev/null
+Copyright (c) 2004-2010 Freescale Semiconductor, Inc.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this list
+ of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+
+* Neither the name of the Freescale Semiconductor, Inc. nor the names of its
+ contributors may be used to endorse or promote products derived from this
+ software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
--- /dev/null
+elftosb 2.x read me
+-------------------
+
+Directories
+
+elftosb2 - elftosb 2.x
+sbtool - sbtool 1.x
+keygen - keygen 1.x
+common - source files common between elftosb2, sbtool, and keygen
+winsupport - files needed only by the windows build
+elftosb - old elftosb 1.x, does not use anything from common
+generatekeys - old key generation tool for elftosb 1.x
+decrypt - old decryption tool for elftosb 1.x
+unittests - old unit tests for elftosb 1.x
+test_files - test ELF and Srecord files
+old - contains old makefiles for elftosb 1.x
+
+Development
+
+The preferred way to work on elftosb and related tools is to use Xcode on Mac OS X. The
+elftosb.xcodeproj directory is an Xcode project "file". It has targets for elftosb,
+keygen, sbtool, and an aggregate target that builds all of the above. The main reason
+to use Xcode is that the project is set up so that the flex and bison input files are
+processed automatically and the output files compiled.
+
+The Windows project and Linux makefile are not configured to build the flex or bison
+source files. They simply use the output files copied into the elftosb2 directory.
+You can run flex or bison manually to generate these files if you don't want to use Xcode.
+If you do use the Xcode project and make changes to the .l or .y files, be sure to copy
+the output .cpp files into the elftosb2 directory before you move the changes to either
+Windows or Linux.
+
+Building
+
+On Windows, open the .sln file in Microsoft Visual Studio. The solution contains projects
+for each of the individual projects, including the old elftosb 1.x and related tools.
+
+For Linux, run 'make all' from within the top level elftosb directory. This will build only
+the new elftosb 2.x, sbtool, and keygen. The old makefile to build elftosb 1.x and its
+tools is located in the "old" directory.
+
+On Mac OS X just open the .xcodeproj project and build the "Everything" target.
+
+
+
--- /dev/null
+
+# ooh! test input command file for elftosb 2!
+
+options {
+ coalesce = yes;
+
+ # most elf files are GHS produced
+ toolset = "GHS";
+
+ # set versions
+ productVersion = "111.222.333";
+ componentVersion = "999.888.777";
+
+ # set file flags
+ flags = (1 << 0) | (1 << 1);
+}
+
+constants {
+ ocram_start = 0;
+ ocram_size = 256K;
+ ocram_end = ocram_start + ocram_size - 1;
+
+# ocram = ocram_start .. ocram_end;
+#
+# ocram = ocram_start +.. ocram_size;
+
+ string_addr = 0x4500;
+
+ # boot modes
+ USB_BM = 0;
+ JTAG_BM = 7;
+ newBootMode = USB_BM;
+}
+
+sources {
+ hello = extern(0); # elf
+ redboot = extern(1); # srec
+ hostlink = extern(2); # elf
+ sd_player = extern(3) ( toolset="GCC" ); # elf
+ datasrc = "test0.key"; # binary
+}
+
+section (0) {
+ # load dcd
+ load dcd {{ 00 11 22 33 }} > 0;
+
+ # same load without dcd
+ load {{ 00 11 22 33 }} > 0;
+
+ call 0xf000;
+
+ hab call 0xf0000000 (128);
+ hab jump 0;
+
+/*
+ # load a simple IVT to an absolute address
+ # this fills in the IVT self address field from the target address
+ load ivt (entry=hello:_start) > 0x1000;
+
+ # load simple IVT. the IVT self address is set explicitly in the IVT declaration,
+ # giving the IVT a natural address so you don't have to tell where to load it.
+ load ivt (entry=hello:_start, self=0x1000);
+
+ load ivt (entry=hello:_start, self=0x1000, csf=0x2000, dcd=0);
+
+ # Setting IVT entry point to the default entry point of a source file.
+ load ivt (entry=hostlink) > 0;
+
+ load ivt (entry=hello:_start, self=0x1000);
+ hab call 0x1000;
+
+ # Special syntax that combines the load and call into one statement.
+ hab call ivt(entry=hello:_start, self=0x1000);
+
+
+
+ load ivt (
+ entry = hello:_start,
+ csf = 0x2000
+ ) > 0x1000;
+
+ # All supported IVT fields.
+ load ivt (
+ entry = hello:,
+ dcd = 0,
+ boot_data = 0,
+ self = 0,
+ csf = 0
+ );
+
+ hab call ivt; # Call the last loaded IVT. */
+}
+
+section (32) {
+ # load a string to some address
+ load "some string" > string_addr;
+
+ # byte fill a region
+ load 0x55.b > ocram_start..ocram_end;
+
+ from hostlink {
+ load $*;
+ }
+
+ # jump to a symbol
+ jump hostlink:_start (100);
+}
+
+section (100)
+{
+ load redboot;
+ call redboot;
+}
+
+section(0x5a)
+{
+ load datasrc > 0..8;
+
+ from hostlink
+ {
+# load $* ( $.ocram.*, ~$.sdram.* );
+
+# load $.sdram.*;
+# load $.ocram.*;
+
+ call :main;
+ call :_start;
+ }
+
+# goto 0x5b;
+}
+
+section (0x5b)
+{
+# load $* from sd_player;
+
+# load hello$.text @ 64K;
+# load hello$*
+
+ load $.text from hello > 0x10000;
+ call sd_player (0xdeadbeef);
+}
+
+section (0x5c)
+{
+ # these loads should produce fill commands with a
+ # length equal to the pattern word size
+ load 0x55.b > 0x200;
+ load 0x55aa.h > 0x400;
+ load 0x55aa66bb.w > 0x800;
+
+# load 0x55.b to 0x200;
+# load 0x55aa.h to 0x400;
+# load 0x55aa66bb.w to 0x800;
+
+# load 0x55.b @ 0x200;
+# load 0x55aa.h @ 0x400;
+# load 0x55aa66bb.w @ 0x800;
+
+# load $.text from hello @ .;
+# load hello$.text @ .;
+# load hello$* @ .
+
+ # this should produce a fill command with a length
+ # of 0x100
+ load 0x4c8e.h > 0x100..0x200;
+
+# load [ 0a 9b 77 66 55 44 33 22 11 00 ] @ 0x100;
+}
+
+# non-bootable section
+section (0x100) <= datasrc;
+
+#section (1K)
+#{
+# load 0xff.b > hostlink:g_wUsbVID + 4;
+#
+# load "Fred's Auto Service\x00" > hostlink:g_wUsbVendorName;
+#
+# from sd_player
+# {
+# load [ 00 11 22 33 44 55 66 77 ] > :g_data + 16;
+# }
+#
+## (0x10 .. 0x20) + 5 == 0x15 .. 0x25
+#}
+
+# section that switches modes
+section (2K)
+{
+ mode newBootMode;
+}
--- /dev/null
+/*
+ * Copyright (c) 2006 SigmaTel, Inc.
+ *
+ * elftosb boot description file that creates some complicated situations for
+ * the loader to handle. of course this is also a good test for elftosb itself.
+ */
+
+/* testing C style comments */
+// testing C++ style comments
+# testing shell style comments
+
+constants {
+ kProgressReportsImageFlag = 0x1;
+
+ kPlayerDriveTag = 0xa0;
+ kHostlinkDriveTag = 0xb0;
+}
+
+options {
+ productVersion = "5.0.999";
+ componentVersion = "5.0.999";
+
+ flags = kProgressReportsImageFlag; // turn on progress reports
+
+ secinfoClear = "ignore";
+}
+
+constants {
+ arg = 0xfeedf00d;
+
+ callArg1 = 2;
+ callArg2 = 3;
+
+ halfword = 10.h;
+
+// flag = 1;
+
+ testboolexpr = 1 > 0;
+
+ mainSizeIsDefined = defined(mainSize);
+}
+
+sources {
+ elffile = extern(0) (toolset="ghs");
+ binfile1 = extern(1);
+ binfile2 = extern(2);
+ foofile = "file.dat";
+ anotherfile = "another.dat";
+ srecfile = "test_files/sd_player_gcc.srec";
+}
+
+options {
+ driveTag = kPlayerDriveTag;
+
+ some_option = defined(testboolexpr);
+}
+
+constants {
+ printMessageAddr = elffile:printMessage;
+ printMessageSize = sizeof(elffile:printMessage);
+
+ // create const with address of main() in elffile
+ mainAddr = elffile:main;
+
+ mainSize = sizeof(elffile:main);
+
+ halfwordSize = sizeof(halfword);
+
+ elf_startAddr = elffile:_start;
+
+// poop = exists(nonexistantfile);
+
+ binfile1size = sizeof(binfile1);
+}
+
+/*
+ * test s-record support
+ */
+section (0)
+{
+ load dcd {{ 00 11 22 33 }} > 0;
+ load srecfile;
+ call srecfile;
+}
+
+section(1; coalesce=true) {
+
+ info "welcome to section 1!";
+ info "elffile path = $(elffile)";
+ info "mainSizeIsDefined = $(d:mainSizeIsDefined)";
+ info "printMessage = $(x:printMessageAddr)";
+
+ info "size of binfile1 = $(binfile1size)";
+
+ // can use symbol refs inside bool expressions in an if stmt
+ if elffile:main == 0
+ {
+ warning "$(elffile) does not seem to have a main() function";
+ }
+ else
+ {
+ info "address of main() of $(elffile) is $(x:mainAddr)";
+ }
+
+ if defined(flag) && flag != 0
+ {
+ load 0x1234.h > 0..10K;
+ }
+ else
+ {
+ // print message using both decimal and hex formatting
+ warning "loading only halfword = $(d:halfword) [$(x:halfword)]!";
+ load halfword > 0..1K;
+ }
+
+ info "size of main() in $(elffile) is $(mainSize)";
+ info "printMessage() size is $(printMessageSize)";
+ info "size of halfword = $(halfwordSize)";
+
+ load 0xff.b > 32K..32K + sizeof(elffile:printMessage);
+
+ from elffile {
+ load {{ 00 01 02 03 04 }} > 1K;
+
+ // load all sections except .mytext
+ load ~$.mytext;
+
+ // figure out where to go from here
+ call :maybeSwitchSections(callArg1);
+
+ // print msg and loop
+ load "hi from section 1" > :szMsg;
+ call :printMessage(0);
+
+ jump :hello(0);
+ }
+
+ // erase a function in memory
+ load 0.w > (elffile:endOfLine)..(elffile:endOfLine + sizeof(elffile:endOfLine));
+}
+
+section(2; alignment=64K) {
+ // cause an error if testConst has not been set
+ if !defined(testConst)
+ {
+ error "testConst is not defined!";
+ }
+
+ from elffile {
+ load "in section 2" > :szMsg;
+ call :printMessage();
+ }
+
+ // load the contents of binfile1 into the upper 128KB of ocram
+ load binfile1 > 128K..192K;
+
+ from elffile {
+ load "loaded binfile1" > :szMsg;
+ call :printMessage(0);
+
+ call :maybeSwitchSections(callArg2);
+
+ jump :endOfLine(2);
+ }
+}
+
+// non-bootable section between two bootable sections
+section(0xbeef; alignment=32K, cleartext=false) <= binfile2;
+
+section(3; alignment=8K) {
+ // load our special section
+ load $.mytext from elffile;
+ call elffile:countToN(5);
+
+ if (exists(foofile) && exists(anotherfile))
+ {
+ // a trainload of beef!
+ load 0xbeef.h > 128K..192K;
+ }
+ else if (exists(elffile) && callArg1 == 2)
+ {
+ // aaaaaaah!
+ load 0x12345678.w > 128K..192K;
+ }
+ else
+ {
+ from elffile
+ {
+ // aaaaaaah!
+ load 0xaaaa.h > 128K..192K;
+ load $.text;
+ load 0xbbbb.h > 128K..192K;
+ }
+ }
+
+ from elffile {
+ load "hold on now, in section 3" > :szMsg;
+ call :printMessage(0);
+
+ jump :endOfLine(3);
+ }
+
+ from elffile {
+ load elffile;
+ load elffile > .;
+ load elffile[ $.bss ] > elffile:countToN;
+// load [ $.bss ] > (elffile:countToN)..(elffile:countToN + sizeof(elffile:countToN));
+ call elffile;
+ call elffile(1);
+ }
+
+ info "address of _start in $(elffile) is $(elf_startAddr)";
+}
+
+section ('four'; alignment=8K, sectionFlags=0x1000) <= binfile1;
+
+section ('five'; alignment=8K, cleartext=1, sectionFlags=0x1000) <= binfile1;
+
+/*
+ * create a data section out of some sections of an elf file
+ */
+section (1234) <= ~$.bss, ~$.data from elffile;
+section (4321) <= elffile [ $* ];
+section (1111) <= elffile;
+
+/* test data sections from various data sources */
+section (0xaa) <= 0x12345678.w;
+section (0xbb) <= "hi there! this is a data section.";
+section (0xcc) <= {{ aa55aa55aa55aa55aa55aa55aa55aa55 }};
+
+
+section (2345)
+{
+ load elffile[ $*.text*, ~$.sdram* ];
+}
+
+
+section ('six_')
+{
+ // load a blob at address 0x1000
+ load {{
+ 00 0a 07 b0 bb ff 03 78
+ 00 0a 07 b0 bb ff 03 78
+ 00 0a 07 b0 bb ff 03 78
+ 00 0a 07 b0 bb ff 03 78
+ 00 0a 07 b0 bb ff 03 78
+ }} > 0x1000;
+}
+
+section ('bad_')
+{
+ // uncomment to test better error reporting for files that failed to open
+// load foofile;
+}
+
+//section (2345) <= {{ 00 11 22 33 44 55 }};
+
+
+
+
--- /dev/null
+sources {
+ elffile = extern(0) (toolset="ghs");
+ redboot = extern(1);
+ hostlink = extern(2);
+ srecfile = "test_files/sd_player_gcc.srec";
+}
+
+constants {
+ IVT_ADDR = 0x1000;
+}
+
+section (0)
+{
+
+ load hostlink;
+ call hostlink;
+
+ load dcd {{ 00 11 22 33 }} > 0x100;
+
+ load ivt (
+ entry = elffile:_start
+// dcd = 0x2000,
+// csf = 0x3000,
+// boot_data = 0x55aa55aa.w
+// self = IVT_ADDR
+ ) > IVT_ADDR;
+
+ hab call IVT_ADDR;
+
+ load ivt (entry=hostlink:_start, self=IVT_ADDR);
+
+ hab jump IVT_ADDR;
+}
+
+
+
--- /dev/null
+options {}\r
+\r
+# create a section\r
+section (0) {\r
+ load 0 > 0..256K;\r
+ load "hello world!" > 0x1000;\r
+}\r
+\r
--- /dev/null
+
+# ooh! test input command file for elftosb 2!
+
+options {
+ searchPath = "elftosb2:elftosb2/elf_test_files";
+
+ maximumLoadBlock = 4K;
+ sectionAlign = 4K;
+
+ productVersion = "4.4.720";
+ componentVersion = "4.4.999";
+
+ coalesce = yes;
+}
+
+constants {
+ ocram_start = 0;
+ ocram_size = 256K;
+ ocram_end = ocram_start + ocram_size - 1;
+
+ prec_test = 1 + 5 * 10;
+ paren_test = (1 + 5) * 10;
+
+ a = 123;
+ foo = (1 + 0x1cf1.w).w ^ 5 + a;
+
+ bar1 = 0xa << 2;
+ bar2 = bar1 | 0x1000;
+ bar3 = bar2 & 0x5555;
+ bar4 = bar3 >> 1;
+
+ mod = 35 % 16;
+
+ n = -1;
+ x = 1 + -2;
+
+ c1 = 'x';
+ c2 = 'oh';
+ c4 = 'shit';
+
+ # test int size promotion
+ x = 0xff.b;
+ y = 0x1234.h;
+ z = 0x55aa55aa.w;
+ xx = x - (x / 2.b); # should produce byte
+ xy = x + y; # should produce half-word
+ xz = x - z; # should produce word
+ yz = y + z; # should produce word
+ xh = x.h;
+ xw = x.w;
+}
+
+sources {
+ hostlink = extern(0);
+ redboot = extern(1);
+
+ sd_player_elf="elftosb2/elf_test_files/sd_player_gcc";
+ sd_player_srec="elftosb2/elf_test_files/sd_player_gcc.srec";
+
+ datafile="elftosb2/elf_test_files/hello_NOR_arm";
+}
+
+#section('foo!') {
+# load 0.w > ocram_start..ocram_end; # word fill all ocram with 0
+#
+# load hostlink; # load all of hostlink source
+#
+# load 0x1000ffff.w > 0x1000; # load a word to address 0x1000
+# load 0x55aa.h > 0x2000; # load a half-word to address 0x2000
+# load redboot; # load all sections of redboot source
+#
+# from hostlink {
+# load $.*.text; # load some sections to their natural location
+# call :_start; # call function "_start" from hostlink
+# call hostlink:foofn; # call function "foofn" from hostlink
+#
+# call :monkey (1 + 1); # call function "monkey" from hostlink with an argument
+#
+# load $* > .; # load all sections of hostlink to their natural location
+#
+# load $.text > 0x1000; # load .text section to address 0x1000
+#
+# load 0x55.b > 0x0..0x4000; # fill 0 through 0x4000 with byte pattern 0x55
+# }
+#
+# load $*.text from hostlink > .; # load sections match "*.text" from hostlink to default places
+#
+# jump redboot; # jump to entry point of redboot source
+#}
+
+## this section...
+#section(2) {
+# from sd_player_elf {
+# load $* > .;
+# call :_start();
+# }
+#}
+#
+## and this one are both equivalent except for section ids
+#section(3) {
+# load $* from sd_player_elf;
+# call sd_player_elf:_start();
+#}
+#
+#section(100) {
+# # set the value of a symbol
+# load hostlink;
+# load 0x5555.h > hostlink:g_USBPID;
+#
+# # load a string to memory
+# load "this is a string" > 0x1e0;
+#}
+
+section (32) {
+ load sd_player_srec;
+ call sd_player_srec;
+}
+
+#section('rsrc') <= datafile;
+
--- /dev/null
+/*
+ * File: AESKey.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "AESKey.h"
+#include <stdexcept>
+#include "smart_ptr.h"
+#include "HexValues.h"
+#include <ctype.h>
+
+//! The data from the stream is expected to be hex encoded. Each two characters
+//! from the stream encode a single result byte. All non-hexadecimal characters
+//! are ignored, including newlines. Every two hexadecimal characters form
+//! an encoded byte. This is true even if the two characters representing the
+//! upper and lower nibbles are separated by whitespace or other characters.
+//!
+//! \post The stream read head is left pointing just after the last encoded byte.
+//!
+//! \param stream Input stream to read from.
+//! \param bytes Number of encoded bytes to read. This is the number of \e
+//! result bytes, not the count of bytes to read from the stream.
+//! \param[out] buffer Pointer to the buffer where decoded data is written.
+//!
+//! \exception std::runtime_error This exception will be thrown if less
+//! data than required is available from \a stream, or if some other
+//! error occurs while reading from \a stream.
+void AESKeyBase::_readFromStream(std::istream & stream, unsigned bytes, uint8_t * buffer)
+{
+ char temp[2];
+ char c;
+ char n = 0;
+
+ while (bytes)
+ {
+ if (stream.get(c).fail())
+ {
+ throw std::runtime_error("not enough data in stream");
+ }
+
+ if (isHexDigit(c))
+ {
+ temp[n++] = c;
+ if (n == 2)
+ {
+ *buffer++ = hexByteToInt(temp);
+ bytes--;
+ n = 0;
+ }
+ }
+ }
+}
+
+//! Key data is written to \a stream as a sequence of hex encoded octets, each two
+//! characters long. No spaces or newlines are inserted between the encoded octets
+//! or at the end of the sequence.
+//!
+//! \exception std::runtime_error Thrown if the \a stream reports an error while
+//! writing the key data.
+void AESKeyBase::_writeToStream(std::ostream & stream, unsigned bytes, const uint8_t * buffer)
+{
+ const char hexChars[] = "0123456789ABCDEF";
+ while (bytes--)
+ {
+ uint8_t thisByte = *buffer++;
+ char byteString[2];
+ byteString[0] = hexChars[(thisByte & 0xf0) >> 4];
+ byteString[1] = hexChars[thisByte & 0x0f];
+ if (stream.write(byteString, 2).bad())
+ {
+ throw std::runtime_error("error while writing to stream");
+ }
+ }
+}
+
+
--- /dev/null
+/*
+ * File: AESKey.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_AESKey_h_)
+#define _AESKey_h_
+
+#include "stdafx.h"
+#include <string.h>
+#include <iostream>
+#include "Random.h"
+
+//! An AES-128 key is 128 bits, or 16 bytes.
+typedef uint8_t aes128_key_t[16];
+
+/*!
+ * \brief Base class for AESKey<S>.
+ *
+ * This class implements some bigger, non-template methods used in the
+ * AESKey<S> templated subclass.
+ */
+class AESKeyBase
+{
+public:
+ //! \brief Reads hex encoded data from \a stream.
+ void _readFromStream(std::istream & stream, unsigned bytes, uint8_t * buffer);
+
+ //! \brief Writes hex encoded data to \a stream.
+ void _writeToStream(std::ostream & stream, unsigned bytes, const uint8_t * buffer);
+};
+
+/*!
+ * \brief Generic AES key class.
+ *
+ * The template parameter \a S is the number of bits in the key.
+ *
+ * The underlying key type can be accessed like this: AESKey<128>::key_t
+ *
+ * When a key instance is destroyed, it erases the key data by setting it
+ * to all zeroes.
+ *
+ * \todo Add a way to allow only key sizes of 128, 192, and 256 bits.
+ * \todo Find a cross platform way to prevent the key data from being written
+ * to the VM swapfile.
+ *
+ * AESKey<128> key = AESKey<128>::readFromStream(s);
+ */
+template <int S>
+class AESKey : public AESKeyBase
+{
+public:
+ //! Type for this size of AES key.
+ typedef uint8_t key_t[S/8];
+
+public:
+ //! \brief Default constructor.
+ //!
+ //! Initializes the key to 0.
+ AESKey()
+ {
+ memset(m_key, 0, sizeof(m_key));
+ }
+
+ //! \brief Constructor taking a key value reference.
+ AESKey(const key_t & key)
+ {
+ memcpy(m_key, &key, sizeof(m_key));
+ }
+
+ // \brief Constructor taking a key value pointer.
+ AESKey(const key_t * key)
+ {
+ memcpy(m_key, key, sizeof(m_key));
+ }
+
+ //! \brief Constructor, reads key from stream in hex format.
+ AESKey(std::istream & stream)
+ {
+ readFromStream(stream);
+ }
+
+ //! \brief Copy constructor.
+ AESKey(const AESKey<S> & other)
+ {
+ memcpy(m_key, other.m_key, sizeof(m_key));
+ }
+
+ //! \brief Destructor.
+ //!
+ //! Sets the key value to zero.
+ ~AESKey()
+ {
+ memset(m_key, 0, sizeof(m_key));
+ }
+
+ //! \brief Set to the key to a randomly generated value.
+ void randomize()
+ {
+ RandomNumberGenerator rng;
+ rng.generateBlock(m_key, sizeof(m_key));
+ }
+
+ //! \brief Reads the key from a hex encoded data stream.
+ void readFromStream(std::istream & stream)
+ {
+ _readFromStream(stream, S/8, reinterpret_cast<uint8_t*>(&m_key));
+ }
+
+ //! \brief Writes the key to a data stream in hex encoded format.
+ void writeToStream(std::ostream & stream)
+ {
+ _writeToStream(stream, S/8, reinterpret_cast<uint8_t*>(&m_key));
+ }
+
+ //! \name Key accessors
+ //@{
+ inline const key_t & getKey() const { return m_key; }
+ inline void getKey(key_t * key) const { memcpy(key, m_key, sizeof(m_key)); }
+
+ inline void setKey(const key_t & key) { memcpy(m_key, &key, sizeof(m_key)); }
+ inline void setKey(const key_t * key) { memcpy(m_key, key, sizeof(m_key)); }
+ inline void setKey(const AESKey<S> & key) { memcpy(m_key, key.m_key, sizeof(m_key)); }
+ //@}
+
+ //! \name Operators
+ //@{
+ const AESKey<S> & operator = (const AESKey<S> & key) { setKey(key); return *this; }
+ const AESKey<S> & operator = (const key_t & key) { setKey(key); return *this; }
+ const AESKey<S> & operator = (const key_t * key) { setKey(key); return *this; }
+
+ operator const key_t & () const { return m_key; }
+ operator const key_t * () const { return m_key; }
+ //@}
+
+protected:
+ key_t m_key; //!< The key value.
+};
+
+//! Standard type definition for an AES-128 key.
+typedef AESKey<128> AES128Key;
+
+#endif // _AESKey_h_
--- /dev/null
+/*
+ * File: Blob.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "Blob.h"
+#include <stdexcept>
+#include <stdlib.h>
+#include <string.h>
+
+Blob::Blob()
+: m_data(0),
+ m_length(0)
+{
+}
+
+//! Makes a local copy of the \a data argument.
+//!
+Blob::Blob(const uint8_t * data, unsigned length)
+: m_data(0),
+ m_length(length)
+{
+ m_data = reinterpret_cast<uint8_t*>(malloc(length));
+ memcpy(m_data, data, length);
+}
+
+//! Makes a local copy of the data owned by \a other.
+//!
+Blob::Blob(const Blob & other)
+: m_data(0),
+ m_length(other.m_length)
+{
+ m_data = reinterpret_cast<uint8_t *>(malloc(m_length));
+ memcpy(m_data, other.m_data, m_length);
+}
+
+//! Disposes of the binary data associated with this object.
+Blob::~Blob()
+{
+ if (m_data)
+ {
+ free(m_data);
+ }
+}
+
+//! Copies \a data onto the blob's data. The blob does not assume ownership
+//! of \a data.
+//!
+//! \param data Pointer to a buffer containing the data which will be copied
+//! into the blob.
+//! \param length Number of bytes pointed to by \a data.
+void Blob::setData(const uint8_t * data, unsigned length)
+{
+ setLength(length);
+ memcpy(m_data, data, length);
+}
+
+//! Sets the #m_length member variable to \a length and resizes #m_data to
+//! the new length. The contents of #m_data past any previous contents are undefined.
+//! If the new \a length is 0 then the data will be freed and a subsequent call
+//! to getData() will return NULL.
+//!
+//! \param length New length of the blob's data in bytes.
+void Blob::setLength(unsigned length)
+{
+ if (length == 0)
+ {
+ clear();
+ return;
+ }
+
+ // Allocate new block.
+ if (!m_data)
+ {
+ m_data = reinterpret_cast<uint8_t*>(malloc(length));
+ if (!m_data)
+ {
+ throw std::runtime_error("failed to allocate memory");
+ }
+ }
+ // Reallocate previous block.
+ else
+ {
+ void * newBlob = realloc(m_data, length);
+ if (!newBlob)
+ {
+ throw std::runtime_error("failed to reallocate memory");
+ }
+ m_data = reinterpret_cast<uint8_t*>(newBlob);
+ }
+
+ // Set length.
+ m_length = length;
+}
+
+void Blob::append(const uint8_t * newData, unsigned newDataLength)
+{
+ unsigned oldLength = m_length;
+
+ setLength(m_length + newDataLength);
+
+ memcpy(m_data + oldLength, newData, newDataLength);
+}
+
+void Blob::clear()
+{
+ if (m_data)
+ {
+ free(m_data);
+ m_data = NULL;
+ }
+
+ m_length = 0;
+}
+
+void Blob::relinquish()
+{
+ m_data = NULL;
+ m_length = 0;
+}
+
--- /dev/null
+/*
+ * File: Blob.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_Blob_h_)
+#define _Blob_h_
+
+#include "stdafx.h"
+
+/*!
+ * \brief Manages a binary object of arbitrary length.
+ *
+ * The data block is allocated with malloc() instead of the new
+ * operator so that we can use realloc() to resize it.
+ */
+class Blob
+{
+public:
+ //! \brief Default constructor.
+ Blob();
+
+ //! \brief Constructor.
+ Blob(const uint8_t * data, unsigned length);
+
+ //! \brief Copy constructor.
+ Blob(const Blob & other);
+
+ //! \brief Destructor.
+ virtual ~Blob();
+
+ //! \name Operations
+ //@{
+ //! \brief Replaces the blob's data.
+ void setData(const uint8_t * data, unsigned length);
+
+ //! \brief Change the size of the blob's data.
+ void setLength(unsigned length);
+
+ //! \brief Adds data to the end of the blob.
+ void append(const uint8_t * newData, unsigned newDataLength);
+
+ //! \brief Disposes of the data.
+ void clear();
+
+ //! \brief Tell the blob that it no longer owns its data.
+ void relinquish();
+ //@}
+
+ //! \name Accessors
+ //@{
+ uint8_t * getData() { return m_data; }
+ const uint8_t * getData() const { return m_data; }
+ unsigned getLength() const { return m_length; }
+ //@}
+
+ //! \name Operators
+ //@{
+ operator uint8_t * () { return m_data; }
+ operator const uint8_t * () const { return m_data; }
+ //@}
+
+protected:
+ uint8_t * m_data; //!< The binary data held by this object.
+ unsigned m_length; //!< Number of bytes pointed to by #m_data.
+};
+
+#endif // _Blob_h_
+
--- /dev/null
+/*
+ * File: BootImage.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_BootImage_h_)
+#define _BootImage_h_
+
+#include <iostream>
+#include "Version.h"
+
+namespace elftosb
+{
+
+/*!
+ * \brief Abstract base class for all boot image format classes.
+ *
+ * Provides virtual methods for all of the common features between different
+ * boot image formats. These are the product and component version numbers
+ * and the drive tag.
+ *
+ * Also provided is the virtual method writeToStream() that lets the caller
+ * stream out the boot image without knowing the underlying format type.
+ */
+class BootImage
+{
+public:
+ //! \brief Constructor.
+ BootImage() {}
+
+ //! \brief Destructor.
+ virtual ~BootImage() {}
+
+ //! \name Versions
+ //@{
+ virtual void setProductVersion(const version_t & version)=0;
+ virtual void setComponentVersion(const version_t & version)=0;
+ //@}
+
+ //! \brief Specify the drive tag to be set in the output file header.
+ virtual void setDriveTag(uint16_t tag)=0;
+
+ //! \brief Returns a string containing the preferred file extension for image format.
+ virtual std::string getFileExtension() const=0;
+
+ //! \brief Write the boot image to an output stream.
+ virtual void writeToStream(std::ostream & stream)=0;
+};
+
+}; // namespace elftosb
+
+#endif // _BootImage_h_
+
--- /dev/null
+/*
+ * File: DataSource.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "DataSource.h"
+#include "DataTarget.h"
+#include <assert.h>
+#include <string.h>
+using namespace elftosb;
+
+#pragma mark *** DataSource::PatternSegment ***
+
+DataSource::PatternSegment::PatternSegment(DataSource & source)
+: DataSource::Segment(source), m_pattern()
+{
+}
+
+DataSource::PatternSegment::PatternSegment(DataSource & source, const SizedIntegerValue & pattern)
+: DataSource::Segment(source), m_pattern(pattern)
+{
+}
+
+DataSource::PatternSegment::PatternSegment(DataSource & source, uint8_t pattern)
+: DataSource::Segment(source), m_pattern(static_cast<uint8_t>(pattern))
+{
+}
+
+DataSource::PatternSegment::PatternSegment(DataSource & source, uint16_t pattern)
+: DataSource::Segment(source), m_pattern(static_cast<uint16_t>(pattern))
+{
+}
+
+DataSource::PatternSegment::PatternSegment(DataSource & source, uint32_t pattern)
+: DataSource::Segment(source), m_pattern(static_cast<uint32_t>(pattern))
+{
+}
+
+unsigned DataSource::PatternSegment::getData(unsigned offset, unsigned maxBytes, uint8_t * buffer)
+{
+ memset(buffer, 0, maxBytes);
+
+ return maxBytes;
+}
+
+//! The pattern segment's length is a function of the data target. If the
+//! target is bounded, then the segment's length is simply the target's
+//! length. Otherwise, if no target has been set or the target is unbounded,
+//! then the length returned is 0.
+unsigned DataSource::PatternSegment::getLength()
+{
+ DataTarget * target = m_source.getTarget();
+ if (!target)
+ {
+ return 0;
+ }
+
+ uint32_t length;
+ if (target->isBounded())
+ {
+ length = target->getEndAddress() - target->getBeginAddress();
+ }
+ else
+ {
+ length = m_pattern.getSize();
+ }
+ return length;
+}
+
+#pragma mark *** PatternSource ***
+
+PatternSource::PatternSource()
+: DataSource(), DataSource::PatternSegment((DataSource&)*this)
+{
+}
+
+PatternSource::PatternSource(const SizedIntegerValue & value)
+: DataSource(), DataSource::PatternSegment((DataSource&)*this, value)
+{
+}
+
+#pragma mark *** UnmappedDataSource ***
+
+UnmappedDataSource::UnmappedDataSource()
+: DataSource(), DataSource::Segment((DataSource&)*this), m_data(), m_length(0)
+{
+}
+
+UnmappedDataSource::UnmappedDataSource(const uint8_t * data, unsigned length)
+: DataSource(), DataSource::Segment((DataSource&)*this), m_data(), m_length(0)
+{
+ setData(data, length);
+}
+
+//! Makes a copy of \a data that is freed when the data source is
+//! destroyed. The caller does not have to maintain \a data after this call
+//! returns.
+void UnmappedDataSource::setData(const uint8_t * data, unsigned length)
+{
+ m_data.safe_delete();
+
+ uint8_t * dataCopy = new uint8_t[length];
+ memcpy(dataCopy, data, length);
+ m_data = dataCopy;
+ m_length = length;
+}
+
+unsigned UnmappedDataSource::getData(unsigned offset, unsigned maxBytes, uint8_t * buffer)
+{
+ assert(offset < m_length);
+ unsigned copyBytes = std::min<unsigned>(m_length - offset, maxBytes);
+ memcpy(buffer, m_data.get(), copyBytes);
+ return copyBytes;
+}
+
+#pragma mark *** MemoryImageDataSource ***
+
+MemoryImageDataSource::MemoryImageDataSource(StExecutableImage * image)
+: DataSource(), m_image(image)
+{
+ // reserve enough room for all segments
+ m_segments.reserve(m_image->getRegionCount());
+}
+
+MemoryImageDataSource::~MemoryImageDataSource()
+{
+ segment_array_t::iterator it = m_segments.begin();
+ for (; it != m_segments.end(); ++it)
+ {
+ // delete this segment if it has been created
+ if (*it)
+ {
+ delete *it;
+ }
+ }
+}
+
+unsigned MemoryImageDataSource::getSegmentCount()
+{
+ return m_image->getRegionCount();
+}
+
+DataSource::Segment * MemoryImageDataSource::getSegmentAt(unsigned index)
+{
+ // return previously created segment
+ if (index < m_segments.size() && m_segments[index])
+ {
+ return m_segments[index];
+ }
+
+ // extend array out to this index
+ if (index >= m_segments.size() && index < m_image->getRegionCount())
+ {
+ m_segments.resize(index + 1, NULL);
+ }
+
+ // create the new segment object
+ DataSource::Segment * newSegment;
+ const StExecutableImage::MemoryRegion & region = m_image->getRegionAtIndex(index);
+ if (region.m_type == StExecutableImage::TEXT_REGION)
+ {
+ newSegment = new TextSegment(*this, m_image, index);
+ }
+ else if (region.m_type == StExecutableImage::FILL_REGION)
+ {
+ newSegment = new FillSegment(*this, m_image, index);
+ }
+
+ m_segments[index] = newSegment;
+ return newSegment;
+}
+
+#pragma mark *** MemoryImageDataSource::TextSegment ***
+
+MemoryImageDataSource::TextSegment::TextSegment(MemoryImageDataSource & source, StExecutableImage * image, unsigned index)
+: DataSource::Segment(source), m_image(image), m_index(index)
+{
+}
+
+unsigned MemoryImageDataSource::TextSegment::getData(unsigned offset, unsigned maxBytes, uint8_t * buffer)
+{
+ const StExecutableImage::MemoryRegion & region = m_image->getRegionAtIndex(m_index);
+ assert(region.m_type == StExecutableImage::TEXT_REGION);
+
+ unsigned copyBytes = std::min<unsigned>(region.m_length - offset, maxBytes);
+ memcpy(buffer, ®ion.m_data[offset], copyBytes);
+
+ return copyBytes;
+}
+
+unsigned MemoryImageDataSource::TextSegment::getLength()
+{
+ const StExecutableImage::MemoryRegion & region = m_image->getRegionAtIndex(m_index);
+ return region.m_length;
+}
+
+uint32_t MemoryImageDataSource::TextSegment::getBaseAddress()
+{
+ const StExecutableImage::MemoryRegion & region = m_image->getRegionAtIndex(m_index);
+ return region.m_address;
+}
+
+#pragma mark *** MemoryImageDataSource::FillSegment ***
+
+MemoryImageDataSource::FillSegment::FillSegment(MemoryImageDataSource & source, StExecutableImage * image, unsigned index)
+: DataSource::PatternSegment(source), m_image(image), m_index(index)
+{
+ SizedIntegerValue zero(0, kWordSize);
+ setPattern(zero);
+}
+
+unsigned MemoryImageDataSource::FillSegment::getLength()
+{
+ const StExecutableImage::MemoryRegion & region = m_image->getRegionAtIndex(m_index);
+ return region.m_length;
+}
+
+uint32_t MemoryImageDataSource::FillSegment::getBaseAddress()
+{
+ const StExecutableImage::MemoryRegion & region = m_image->getRegionAtIndex(m_index);
+ return region.m_address;
+}
--- /dev/null
+/*
+ * File: DataSource.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_DataSource_h_)
+#define _DataSource_h_
+
+#include <vector>
+#include "Value.h"
+#include "smart_ptr.h"
+#include "StExecutableImage.h"
+
+namespace elftosb
+{
+
+// Forward declaration
+class DataTarget;
+
+/*!
+ * \brief Abstract base class for data sources.
+ *
+ * Data sources represent any sort of data that can be placed or loaded
+ * into a target region. Sources may be a single blob of data read from
+ * a file or may consist of many segments.
+ *
+ * The three most important features of data sources are:
+ * - Sources may be multi-segmented.
+ * - Sources and/or segments can have a "natural" or default target location.
+ * - The target for a source may be taken into consideration when the source
+ * describes itself.
+ */
+class DataSource
+{
+public:
+ /*!
+ * \brief Discrete, contiguous part of the source's data.
+ *
+ * This class is purely abstract and subclasses of DataSource are expected
+ * to subclass it to implement a segment particular to their needs.
+ */
+ class Segment
+ {
+ public:
+ //! \brief Default constructor.
+ Segment(DataSource & source) : m_source(source) {}
+
+ //! \brief Destructor.
+ virtual ~Segment() {}
+
+ //! \brief Gets all or a portion of the segment's data.
+ //!
+ //! The data is copied into \a buffer. Up to \a maxBytes bytes may be
+ //! copied, so \a buffer must be at least that large.
+ //!
+ //! \param offset Index of the first byte to start copying from.
+ //! \param maxBytes The maximum number of bytes that can be returned. \a buffer
+ //! must be at least this large.
+ //! \param buffer Pointer to buffer where the data is copied.
+ //! \return The number of bytes copied into \a buffer.
+ virtual unsigned getData(unsigned offset, unsigned maxBytes, uint8_t * buffer)=0;
+
+ //! \brief Gets the length of the segment's data.
+ virtual unsigned getLength()=0;
+
+ //! \brief Returns whether the segment has an associated address.
+ virtual bool hasNaturalLocation()=0;
+
+ //! \brief Returns the address associated with the segment.
+ virtual uint32_t getBaseAddress() { return 0; }
+
+ protected:
+ DataSource & m_source; //!< The data source to which this segment belongs.
+ };
+
+ /*!
+ * \brief This is a special type of segment containing a repeating pattern.
+ *
+ * By default the segment doesn't have a specific length or data. The length depends
+ * on the target's address range. And the data is just the pattern, repeated
+ * many times. In addition, pattern segments do not have a natural location.
+ *
+ * Calling code should look for instances of PatternSegment and handle them
+ * as special cases that can be optimized.
+ */
+ class PatternSegment : public Segment
+ {
+ public:
+ //! \brief Default constructor.
+ PatternSegment(DataSource & source);
+
+ //! \brief Constructor taking a fill pattern.
+ PatternSegment(DataSource & source, const SizedIntegerValue & pattern);
+
+ //! \brief Constructor taking a byte fill pattern.
+ PatternSegment(DataSource & source, uint8_t pattern);
+
+ //! \brief Constructor taking a half-word fill pattern.
+ PatternSegment(DataSource & source, uint16_t pattern);
+
+ //! \brief Constructor taking a word fill pattern.
+ PatternSegment(DataSource & source, uint32_t pattern);
+
+ //! \name Segment methods
+ //@{
+ //! \brief Pattern segments have no natural address.
+ virtual bool hasNaturalLocation() { return false; }
+
+ //! \brief Performs a pattern fill into the \a buffer.
+ virtual unsigned getData(unsigned offset, unsigned maxBytes, uint8_t * buffer);
+
+ //! \brief Returns a length based on the data target's address range.
+ virtual unsigned getLength();
+ //@}
+
+ //! \name Pattern accessors
+ //@{
+ //! \brief Assigns a new fill pattern.
+ inline void setPattern(const SizedIntegerValue & newPattern) { m_pattern = newPattern; }
+
+ //! \brief Return the fill pattern for the segment.
+ inline SizedIntegerValue & getPattern() { return m_pattern; }
+
+ //! \brief Assignment operator, sets the pattern value and length.
+ PatternSegment & operator = (const SizedIntegerValue & value) { m_pattern = value; return *this; }
+ //@}
+
+ protected:
+ SizedIntegerValue m_pattern; //!< The fill pattern.
+ };
+
+public:
+ //! \brief Default constructor.
+ DataSource() : m_target(0) {}
+
+ //! \brief Destructor.
+ virtual ~DataSource() {}
+
+ //! \name Data target
+ //@{
+ //! \brief Sets the associated data target.
+ inline void setTarget(DataTarget * target) { m_target = target; }
+
+ //! \brief Gets the associated data target.
+ inline DataTarget * getTarget() const { return m_target; }
+ //@}
+
+ //! \name Segments
+ //@{
+ //! \brief Returns the number of segments in this data source.
+ virtual unsigned getSegmentCount()=0;
+
+ //! \brief Returns segment number \a index of the data source.
+ virtual Segment * getSegmentAt(unsigned index)=0;
+ //@}
+
+protected:
+ DataTarget * m_target; //!< Corresponding target for this source.
+};
+
+/*!
+ * \brief Data source for a repeating pattern.
+ *
+ * The pattern is represented by a SizedIntegerValue object. Thus the pattern
+ * can be either byte, half-word, or word sized.
+ *
+ * This data source has only one segment, and the PatternSource instance acts
+ * as its own single segment.
+ */
+class PatternSource : public DataSource, public DataSource::PatternSegment
+{
+public:
+ //! \brief Default constructor.
+ PatternSource();
+
+ //! \brief Constructor taking the pattern value.
+ PatternSource(const SizedIntegerValue & value);
+
+ //! \brief There is only one segment.
+ virtual unsigned getSegmentCount() { return 1; }
+
+ //! \brief Returns this object, as it is its own segment.
+ virtual DataSource::Segment * getSegmentAt(unsigned index) { return this; }
+
+ //! \brief Assignment operator, sets the pattern value and length.
+ PatternSource & operator = (const SizedIntegerValue & value) { setPattern(value); return *this; }
+};
+
+/*!
+ * \brief Data source for data that is not memory mapped (has no natural address).
+ *
+ * This data source can only manage a single block of data, which has no
+ * associated address. It acts as its own Segment.
+ */
+class UnmappedDataSource : public DataSource, public DataSource::Segment
+{
+public:
+ //! \brief Default constructor.
+ UnmappedDataSource();
+
+ //! \brief Constructor taking the data, which is copied.
+ UnmappedDataSource(const uint8_t * data, unsigned length);
+
+ //! \brief Sets the source's data.
+ void setData(const uint8_t * data, unsigned length);
+
+ //! \brief There is only one segment.
+ virtual unsigned getSegmentCount() { return 1; }
+
+ //! \brief Returns this object, as it is its own segment.
+ virtual DataSource::Segment * getSegmentAt(unsigned index) { return this; }
+
+ //! \name Segment methods
+ //@{
+ //! \brief Unmapped data sources have no natural address.
+ virtual bool hasNaturalLocation() { return false; }
+
+ //! \brief Copies a portion of the data into \a buffer.
+ virtual unsigned getData(unsigned offset, unsigned maxBytes, uint8_t * buffer);
+
+ //! \brief Returns the number of bytes of data managed by the source.
+ virtual unsigned getLength() { return m_length; }
+ //@}
+
+protected:
+ smart_array_ptr<uint8_t> m_data; //!< The data.
+ unsigned m_length; //!< Byte count of the data.
+};
+
+/*!
+ * \brief Data source that takes its data from an executable image.
+ *
+ * \see StExecutableImage
+ */
+class MemoryImageDataSource : public DataSource
+{
+public:
+ //! \brief Default constructor.
+ MemoryImageDataSource(StExecutableImage * image);
+
+ //! \brief Destructor.
+ virtual ~MemoryImageDataSource();
+
+ //! \brief Returns the number of memory regions in the image.
+ virtual unsigned getSegmentCount();
+
+ //! \brief Returns the data source segment at position \a index.
+ virtual DataSource::Segment * getSegmentAt(unsigned index);
+
+protected:
+ /*!
+ * \brief Segment corresponding to a text region of the executable image.
+ */
+ class TextSegment : public DataSource::Segment
+ {
+ public:
+ //! \brief Default constructor
+ TextSegment(MemoryImageDataSource & source, StExecutableImage * image, unsigned index);
+
+ virtual unsigned getData(unsigned offset, unsigned maxBytes, uint8_t * buffer);
+ virtual unsigned getLength();
+
+ virtual bool hasNaturalLocation() { return true; }
+ virtual uint32_t getBaseAddress();
+
+ protected:
+ StExecutableImage * m_image; //!< Coalesced image of the file.
+ unsigned m_index; //!< Record index.
+ };
+
+ /*!
+ * \brief Segment corresponding to a fill region of the executable image.
+ */
+ class FillSegment : public DataSource::PatternSegment
+ {
+ public:
+ FillSegment(MemoryImageDataSource & source, StExecutableImage * image, unsigned index);
+
+ virtual unsigned getLength();
+
+ virtual bool hasNaturalLocation() { return true; }
+ virtual uint32_t getBaseAddress();
+
+ protected:
+ StExecutableImage * m_image; //!< Coalesced image of the file.
+ unsigned m_index; //!< Record index.
+ };
+
+protected:
+ StExecutableImage * m_image; //!< The memory image that is the data source.
+
+ typedef std::vector<DataSource::Segment*> segment_array_t; //!< An array of segments.
+ segment_array_t m_segments; //!< The array of Segment instances.
+};
+
+}; // namespace elftosb
+
+#endif // _DataSource_h_
--- /dev/null
+/*
+ * File: DataSourceImager.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "DataSourceImager.h"
+#include <stdlib.h>
+#include <string.h>
+
+using namespace elftosb;
+
+DataSourceImager::DataSourceImager()
+: Blob(),
+ m_fill(0),
+ m_baseAddress(0),
+ m_isBaseAddressSet(false)
+{
+}
+
+void DataSourceImager::setBaseAddress(uint32_t address)
+{
+ m_baseAddress = address;
+ m_isBaseAddressSet = true;
+}
+
+void DataSourceImager::setFillPattern(uint8_t pattern)
+{
+ m_fill = pattern;
+}
+
+void DataSourceImager::reset()
+{
+ clear();
+
+ m_fill = 0;
+ m_baseAddress = 0;
+ m_isBaseAddressSet = false;
+}
+
+//! \param dataSource Pointer to an instance of a concrete data source subclass.
+//!
+void DataSourceImager::addDataSource(DataSource * source)
+{
+ unsigned segmentCount = source->getSegmentCount();
+ unsigned index = 0;
+ for (; index < segmentCount; ++index)
+ {
+ addDataSegment(source->getSegmentAt(index));
+ }
+}
+
+//! \param segment The segment to add. May be any type of data segment, including
+//! a pattern segment.
+void DataSourceImager::addDataSegment(DataSource::Segment * segment)
+{
+ DataSource::PatternSegment * patternSegment = dynamic_cast<DataSource::PatternSegment*>(segment);
+
+ unsigned segmentLength = segment->getLength();
+ bool segmentHasLocation = segment->hasNaturalLocation();
+ uint32_t segmentAddress = segment->getBaseAddress();
+
+ uint8_t * toPtr = NULL;
+ unsigned addressDelta;
+ unsigned newLength;
+
+ // If a pattern segment's length is 0 then make it as big as the fill pattern.
+ // This needs to be done before the buffer is adjusted.
+ if (patternSegment && segmentLength == 0)
+ {
+ SizedIntegerValue & pattern = patternSegment->getPattern();
+ segmentLength = pattern.getSize();
+ }
+
+ if (segmentLength)
+ {
+ if (segmentHasLocation)
+ {
+ // Make sure a base address is set.
+ if (!m_isBaseAddressSet)
+ {
+ m_baseAddress = segmentAddress;
+ m_isBaseAddressSet = true;
+ }
+
+ // The segment is located before our buffer's first address.
+ // toPtr is not set in this if, but in the else branch of the next if.
+ // Unless the segment completely overwrite the current data.
+ if (segmentAddress < m_baseAddress)
+ {
+ addressDelta = m_baseAddress - segmentAddress;
+
+ uint8_t * newData = (uint8_t *)malloc(m_length + addressDelta);
+ memcpy(&newData[addressDelta], m_data, m_length);
+ free(m_data);
+
+ m_data = newData;
+ m_length += addressDelta;
+ m_baseAddress = segmentAddress;
+ }
+
+ // This segment is located or extends outside of our buffer.
+ if (segmentAddress + segmentLength > m_baseAddress + m_length)
+ {
+ newLength = segmentAddress + segmentLength - m_baseAddress;
+
+ m_data = (uint8_t *)realloc(m_data, newLength);
+
+ // Clear any bytes between the old data and the new segment.
+ addressDelta = segmentAddress - (m_baseAddress + m_length);
+ if (addressDelta)
+ {
+ memset(m_data + m_length, 0, addressDelta);
+ }
+
+ toPtr = m_data + (segmentAddress - m_baseAddress);
+ m_length = newLength;
+ }
+ else
+ {
+ toPtr = m_data + (segmentAddress - m_baseAddress);
+ }
+ }
+ // Segment has no natural location, so just append it to the end of our buffer.
+ else
+ {
+ newLength = m_length + segmentLength;
+ m_data = (uint8_t *)realloc(m_data, newLength);
+ toPtr = m_data + m_length;
+ m_length = newLength;
+ }
+ }
+
+ // A loop is used because getData() may fill in less than the requested
+ // number of bytes per call.
+ unsigned offset = 0;
+ while (offset < segmentLength)
+ {
+ offset += segment->getData(offset, segmentLength - offset, toPtr + offset);
+ }
+}
+
--- /dev/null
+/*
+ * File: DataSourceImager.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_DataSourceImager_h_)
+#define _DataSourceImager_h_
+
+#include "Blob.h"
+#include "DataSource.h"
+
+namespace elftosb {
+
+/*!
+ * \brief Converts a DataSource into a single binary buffer.
+ */
+class DataSourceImager : public Blob
+{
+public:
+ //! \brief Constructor.
+ DataSourceImager();
+
+ //! \name Setup
+ //@{
+ void setBaseAddress(uint32_t address);
+ void setFillPattern(uint8_t pattern);
+ //@}
+
+ void reset();
+
+ //! \name Accessors
+ //@{
+ uint32_t getBaseAddress() { return m_baseAddress; }
+ //@}
+
+ //! \name Operations
+ //@{
+ //! \brief Adds all of the segments of which \a dataSource is composed.
+ void addDataSource(DataSource * source);
+
+ //! \brief Adds the data from one data segment.
+ void addDataSegment(DataSource::Segment * segment);
+ //@}
+
+protected:
+ uint8_t m_fill;
+ uint32_t m_baseAddress;
+ bool m_isBaseAddressSet;
+};
+
+};
+
+#endif // _DataSourceImager_h_
--- /dev/null
+/*
+ * File: DataTarget.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "DataTarget.h"
+#include "DataSource.h"
+#include "ElftosbErrors.h"
+
+using namespace elftosb;
+
+//! \exception elftosb::semantic_error Thrown if the source has multiple segments.
+DataTarget::AddressRange ConstantDataTarget::getRangeForSegment(DataSource & source, DataSource::Segment & segment)
+{
+ // can't handle multi-segment data sources
+ if (source.getSegmentCount() > 1)
+ {
+ throw semantic_error("constant targets only support single-segment sources");
+ }
+
+ // always relocate the segment to our begin address
+ AddressRange range;
+ range.m_begin = m_begin;
+
+ if (isBounded())
+ {
+ // we have an end address. trim the result range to the segment size
+ // or let the end address crop the segment.
+ range.m_end = std::min<uint32_t>(m_end, m_begin + segment.getLength());
+ }
+ else
+ {
+ // we have no end address, so the segment size determines it.
+ range.m_end = m_begin + segment.getLength();
+ }
+
+ return range;
+}
+
+//! If the \a segment has a natural location, the returned address range extends
+//! from the segment's base address to its base address plus its length.
+//!
+//! \exception elftosb::semantic_error This exception is thrown if the \a segment
+//! does not have a natural location associated with it.
+DataTarget::AddressRange NaturalDataTarget::getRangeForSegment(DataSource & source, DataSource::Segment & segment)
+{
+ if (!segment.hasNaturalLocation())
+ {
+ throw semantic_error("source has no natural location");
+ }
+
+ AddressRange range;
+ range.m_begin = segment.getBaseAddress();
+ range.m_end = segment.getBaseAddress() + segment.getLength();
+ return range;
+}
+
--- /dev/null
+/*
+ * File: DataTarget.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_DataTarget_h_)
+#define _DataTarget_h_
+
+#include "stdafx.h"
+#include "DataSource.h"
+
+namespace elftosb
+{
+
+// Forward declaration
+class DataSource;
+
+/*!
+ * \brief Abstract base class for the target address or range of data.
+ *
+ * Targets at the most basic level have a single address, and potentially
+ * an address range. Unbounded targets have a beginning address but no
+ * specific end address, while bounded targets do have an end address.
+ *
+ * Users of a data target can access the begin and end addresses directly.
+ * However, the most powerful way to use a target is with the
+ * getRangeForSegment() method. This method returns the target address range
+ * for a segment of a data source. The value of the resulting range can be
+ * completely dependent upon the segment's properties, those of its data
+ * source, and the type of data target.
+ *
+ * \see elftosb::DataSource
+ */
+class DataTarget
+{
+public:
+ //! \brief Simple structure that describes an addressed region of memory.
+ //! \todo Decide if the end address is inclusive or not.
+ struct AddressRange
+ {
+ uint32_t m_begin;
+ uint32_t m_end;
+ };
+
+public:
+ //! \brief Default constructor.
+ DataTarget() : m_source(0) {}
+
+ //! \brief Destructor.
+ virtual ~DataTarget() {}
+
+ //! \brief Whether the target is just a single address or has an end to it.
+ virtual bool isBounded() { return false; }
+
+ virtual uint32_t getBeginAddress() { return 0; }
+ virtual uint32_t getEndAddress() { return 0; }
+
+ //! \brief Return the address range for a segment of a data source.
+ virtual DataTarget::AddressRange getRangeForSegment(DataSource & source, DataSource::Segment & segment)=0;
+
+ inline void setSource(DataSource * source) { m_source = source; }
+ inline DataSource * getSource() const { return m_source; }
+
+protected:
+ DataSource * m_source; //!< Corresponding data source for this target.
+};
+
+/*!
+ * \brief Target with a constant values for the addresses.
+ *
+ * This target type supports can be both bounded and unbounded. It always has
+ * at least one address, the beginning address. The end address is optional,
+ * and if not provided makes the target unbounded.
+ */
+class ConstantDataTarget : public DataTarget
+{
+public:
+ //! \brief Constructor taking only a begin address.
+ ConstantDataTarget(uint32_t start) : DataTarget(), m_begin(start), m_end(0), m_hasEnd(false) {}
+
+ //! \brief Constructor taking both begin and end addresses.
+ ConstantDataTarget(uint32_t start, uint32_t end) : DataTarget(), m_begin(start), m_end(end), m_hasEnd(true) {}
+
+ //! \brief The target is bounded if an end address was specified.
+ virtual bool isBounded() { return m_hasEnd; }
+
+ virtual uint32_t getBeginAddress() { return m_begin; }
+ virtual uint32_t getEndAddress() { return m_end; }
+
+ //! \brief Return the address range for a segment of a data source.
+ virtual DataTarget::AddressRange getRangeForSegment(DataSource & source, DataSource::Segment & segment);
+
+protected:
+ uint32_t m_begin; //!< Start address.
+ uint32_t m_end; //!< End address.
+ bool m_hasEnd; //!< Was an end address specified?
+};
+
+/*!
+ * \brief Target address that is the "natural" location of whatever the source data is.
+ *
+ * The data source used with the target must have a natural location. If
+ * getRangeForSegment() is called with a segment that does not have a natural
+ * location, a semantic_error will be thrown.
+ */
+class NaturalDataTarget : public DataTarget
+{
+public:
+ //! \brief Default constructor.
+ NaturalDataTarget() : DataTarget() {}
+
+ //! \brief Natural data targets are bounded by their source's segment lengths.
+ virtual bool isBounded() { return true; }
+
+ //! \brief Return the address range for a segment of a data source.
+ virtual DataTarget::AddressRange getRangeForSegment(DataSource & source, DataSource::Segment & segment);
+};
+
+}; // namespace elftosb
+
+#endif // _DataTarget_h_
--- /dev/null
+/*
+ * File: ELF.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_ELF_h_)
+#define _ELF_h_
+
+//! \name ELF types
+//! Types used in ELF file structures.
+//@{
+typedef uint32_t Elf32_Addr;
+typedef uint16_t Elf32_Half;
+typedef /*off_t*/ uint32_t Elf32_Off;
+typedef int32_t Elf32_Sword;
+typedef uint32_t Elf32_Word;
+//@}
+
+// All ELF structures are byte aligned. Any alignment padding is explicit.
+#pragma pack(1)
+
+//! \name File header
+//@{
+
+/*!
+ * Constants for the various fields of Elf32_Ehdr.e_ident.
+ */
+enum {
+ EI_MAG0 = 0,
+ EI_MAG1,
+ EI_MAG2,
+ EI_MAG3,
+ EI_CLASS,
+ EI_DATA,
+ EI_VERSION,
+ EI_PAD,
+ EI_NIDENT = 16,
+
+ // Magic number.
+ ELFMAG0 = 0x7f,
+ ELFMAG1 = 'E',
+ ELFMAG2 = 'L',
+ ELFMAG3 = 'F',
+
+ // EI_CLASS
+ ELFCLASSNONE = 0,
+ ELFCLASS32 = 1,
+ ELFCLASS64 = 2,
+
+ // EI_DATA
+ ELFDATANONE = 0,
+ ELFDATA2LSB = 1,
+ ELFDATA2MSB = 2
+};
+
+/*!
+ * \brief ELF file header.
+ */
+struct Elf32_Ehdr
+{
+ unsigned char e_ident[EI_NIDENT]; //!< Magic number identifying the file format.
+ Elf32_Half e_type; //!< Identifies the object file format.
+ Elf32_Half e_machine; //!< Specified the architecture for the object file.
+ Elf32_Word e_version; //!< Object file version.
+ Elf32_Addr e_entry; //!< Virtual address of the entry point, or 0.
+ Elf32_Off e_phoff; //!< Program header table offset in bytes, or 0 if no program header table.
+ Elf32_Off e_shoff; //!< Section header table offset in bytes, or 0 if no section header table.
+ Elf32_Word e_flags; //!< Processor-specific flags associated with the file.
+ Elf32_Half e_ehsize; //!< The ELF header's size in bytes.
+ Elf32_Half e_phentsize; //!< Size in bytes of one entry in the program header table.
+ Elf32_Half e_phnum; //!< Number of entries in the program header table.
+ Elf32_Half e_shentsize; //!< Size in bytes of an entry in the section header table.
+ Elf32_Half e_shnum; //!< Number of entries in the section header table.
+ Elf32_Half e_shstrndx; //!< Section header table index of the section name string table.
+};
+
+/*!
+ * Constants for #Elf32_Ehdr.e_type.
+ */
+enum {
+ ET_NONE, //!< No file type.
+ ET_REL, //!< Relocatable file.
+ ET_EXEC, //!< Executable file.
+ ET_DYN, //!< Shared object file.
+ ET_CORE, //!< Core file.
+ ET_LOPROC, //!< Low bound of processor-specific file types.
+ ET_HIPROC //!< High bound of processor-specific file types.
+};
+
+/*!
+ * ARM-specific #Elf32_Ehdr.e_flags
+ */
+enum {
+ EF_ARM_HASENTRY = 0x02, //!< #Elf32_Ehdr.e_entry contains a program-loader entry point.
+ EF_ARM_SYMSARESORTED = 0x04, //!< Each subsection of the symbol table is sorted by symbol value.
+ EF_ARM_DYNSYMSUSESEGIDX = 0x08, //!< Symbols in dynamic symbol tables that are defined in sections included in program segment n have #Elf32_Sym.st_shndx = n + 1.
+ EF_ARM_MAPSYMSFIRST = 0x10, //!< Mapping symbols precede other local symbols in the symbol table.
+ EF_ARM_EABIMASK = 0xff000000, //!< This masks an 8-bit version number, the version of the ARM EABI to which this ELF file conforms. The current EABI version is #ARM_EABI_VERSION.
+
+ ARM_EABI_VERSION = 0x02000000 //!< Current ARM EABI version.
+};
+
+//@}
+
+//! \name Sections
+//@{
+
+/*!
+ * \brief ELF section header.
+ *
+ * An object file's section header table lets one locate all the file's
+ * sections. The section header table is an array of #Elf32_Shdr structures.
+ * A section header table index is a subscript into this array. The ELF
+ * header's #Elf32_Ehdr::e_shoff member gives the byte offset from the beginning of
+ * the file to the section header table; #Elf32_Ehdr::e_shnum tells how many entries
+ * the section header table contains; #Elf32_Ehdr::e_shentsize gives the size in bytes
+ * of each entry.
+ *
+ * Some section header table indexes are reserved. An object file will not
+ * have sections for these special indexes:
+ * - #SHN_UNDEF
+ * - #SHN_LORESERVE
+ * - #SHN_LOPROC
+ * - #SHN_HIPROC
+ * - #SHN_ABS
+ * - #SHN_COMMON
+ * - #SHN_HIRESERVE
+ */
+struct Elf32_Shdr
+{
+ Elf32_Word sh_name; //!< The section's name. Index into the section header string table section.
+ Elf32_Word sh_type; //!< Section type, describing the contents and semantics.
+ Elf32_Word sh_flags; //!< Section flags describing various attributes.
+ Elf32_Addr sh_addr; //!< The address at which the section will appear in the memory image, or 0.
+ Elf32_Off sh_offset; //!< Offset from beginning of the file to the first byte in the section.
+ Elf32_Word sh_size; //!< The section's size in bytes.
+ Elf32_Word sh_link; //!< Section header table link index. Interpretation depends on section type.
+ Elf32_Word sh_info; //!< Extra information about the section. Depends on section type.
+ Elf32_Word sh_addralign; //!< Address alignment constraint. Values are 0 and positive powers of 2.
+ Elf32_Word sh_entsize; //!< Size in bytes of section entries, or 0 if the section does not have fixed-size entries.
+};
+
+/*!
+ * Special section indexes.
+ */
+enum {
+ SHN_UNDEF = 0,
+ SHN_LORESERVE = 0xff00,
+ SHN_LOPROC = 0xff00,
+ SHN_HIPROC = 0xff1f,
+ SHN_ABS = 0xfff1, //!< The symbol has an absolute value that will not change because of relocation.
+ SHN_COMMON = 0xfff2, //!< The symbol labels a common block that has not yet been allocated.
+ SHN_HIRESERVE = 0xffff
+};
+
+/*!
+ * Section type constants.
+ */
+enum {
+ SHT_NULL = 0,
+ SHT_PROGBITS = 1,
+ SHT_SYMTAB = 2,
+ SHT_STRTAB = 3,
+ SHT_RELA = 4,
+ SHT_HASH = 5,
+ SHT_DYNAMIC = 6,
+ SHT_NOTE = 7,
+ SHT_NOBITS = 8,
+ SHT_REL = 9,
+ SHT_SHLIB = 10,
+ SHT_DYNSYM = 11
+};
+
+/*!
+ * Section flag constants.
+ */
+enum {
+ SHF_WRITE = 0x1, //!< Section is writable.
+ SHF_ALLOC = 0x2, //!< Allocate section.
+ SHF_EXECINSTR = 0x4 //!< Section contains executable instructions.
+};
+
+/*!
+ * ARM-specific section flag constants
+ */
+enum {
+ SHF_ENTRYSECT = 0x10000000, //!< The section contains an entry point.
+ SHF_COMDEF = 0x80000000 //!< The section may be multiply defined in the input to a link step.
+};
+
+#define BSS_SECTION_NAME ".bss"
+#define DATA_SECTION_NAME ".data"
+#define TEXT_SECTION_NAME ".text"
+#define SHSTRTAB_SECTION_NAME ".shstrtab"
+#define STRTAB_SECTION_NAME ".strtab"
+#define SYMTAB_SECTION_NAME ".symtab"
+
+//@}
+
+//! \name Segments
+//@{
+
+/*!
+ * \brief ELF program header.
+ *
+ * An executable or shared object file's program header table is an array of
+ * structures, each describing a segment or other information the system needs
+ * to prepare the program for execution. An object file segment contains one
+ * or more sections. Program headers are meaningful only for executable and
+ * shared object files. A file specifies its own program header size with the
+ * ELF header's #Elf32_Ehdr::e_phentsize and #Elf32_Ehdr::e_phnum members.
+ */
+struct Elf32_Phdr
+{
+ Elf32_Word p_type; //!< What type of segment this header describes.
+ Elf32_Off p_offset; //!< Offset in bytes from start of file to the first byte of the segment.
+ Elf32_Addr p_vaddr; //!< Virtual address at which the segment will reside in memory.
+ Elf32_Addr p_paddr; //!< Physical address, for systems where this is relevant.
+ Elf32_Word p_filesz; //!< Number of bytes of file data the segment consumes. May be zero.
+ Elf32_Word p_memsz; //!< Size in bytes of the segment in memory. May be zero.
+ Elf32_Word p_flags; //!< Flags relevant to the segment.
+ Elf32_Word p_align; //!< Alignment constraint for segment addresses. Possible values are 0 and positive powers of 2.
+};
+
+/*!
+ * Segment type constants.
+ */
+enum {
+ PT_NULL = 0,
+ PT_LOAD = 1,
+ PT_DYNAMIC = 2,
+ PT_INTERP = 3,
+ PT_NOTE = 4,
+ PT_SHLIB = 5,
+ PT_PHDR = 6
+};
+
+/*!
+ * Program header flag constants.
+ */
+enum {
+ PF_X = 0x1, //!< Segment is executable.
+ PF_W = 0x2, //!< Segment is writable.
+ PF_R = 0x4 //!< Segment is readable.
+};
+
+//@}
+
+//! \name Symbol table
+//@{
+
+enum {
+ STN_UNDEF = 0 //!< Undefined symbol index.
+};
+
+/*!
+ * \brief ELF symbol table entry.
+ *
+ * An object file's symbol table holds information needed to locate and
+ * relocate a program's symbolic definitions and references. A symbol
+ * table index is a subscript into this array. Index 0 both designates
+ * the first entry in the table and serves as the undefined symbol index.
+ */
+struct Elf32_Sym
+{
+ Elf32_Word st_name; //!< Index into file's string table.
+ Elf32_Addr st_value; //!< Value associated with the symbol. Depends on context.
+ Elf32_Word st_size; //!< Size associated with symbol. 0 if the symbol has no size or an unknown size.
+ unsigned char st_info; //!< Specified the symbol's type and binding attributes.
+ unsigned char st_other; //!< Currently 0 (reserved).
+ Elf32_Half st_shndx; //!< Section header table index for this symbol.
+};
+
+//! \name st_info macros
+//! Macros for manipulating the st_info field of Elf32_Sym struct.
+//@{
+#define ELF32_ST_BIND(i) ((i) >> 4) //!< Get binding attributes.
+#define ELF32_ST_TYPE(i) ((i) & 0x0f) //!< Get symbol type.
+#define ELF32_ST_INFO(b, t) (((b) << 4) + ((t) & 0x0f)) //!< Construct st_info value from binding attributes and symbol type.
+//@}
+
+/*!
+ * \brief Symbol binding attributes.
+ *
+ * These constants are mask values.
+ */
+enum {
+ STB_LOCAL = 0, //!< Local symbol not visible outside the object file.
+ STB_GLOBAL = 1, //!< Symbol is visible to all object files being linked together.
+ STB_WEAK = 2, //!< Like global symbols, but with lower precedence.
+
+ // Processor-specific semantics.
+ STB_LOPROC = 13,
+ STB_HIPROC = 15
+};
+
+/*!
+ * \brief Symbol types.
+ */
+enum {
+ STT_NOTYPE = 0, //!< The symbol's type is not specified.
+ STT_OBJECT = 1, //!< The symbol is associated with a data object, such as a variable or array.
+ STT_FUNC = 2, //!< The symbol is associated with a function or other executable code.
+ STT_SECTION = 3, //!< The synmbol is associated with a section. Primarily used for relocation.
+ STT_FILE = 4, //!< A file symbol has STB_LOCAL binding, its section index is SHN_ABS, and it precedes the other STB_LOCAL symbols for the file, if it is present.
+
+ STT_LOPROC = 13, //!< Low bound of processor-specific symbol types.
+ STT_HIPROC = 15 //!< High bound of processor-specific symbol types.
+};
+
+/*!
+ * GHS-specific constants
+ */
+enum {
+ STO_THUMB = 1 //!< This flag is set on #Elf32_Sym.st_other if the symbol is Thumb mode code.
+};
+
+#define ARM_SEQUENCE_MAPSYM "$a"
+#define DATA_SEQUENCE_MAPSYM "$d"
+#define THUMB_SEQUENCE_MAPSYM "$t"
+
+#define THUMB_BL_TAGSYM "$b"
+#define FN_PTR_CONST_TAGSYM "$f"
+#define INDIRECT_FN_CALL_TAGSYM "$p"
+#define MAPPING_SYMBOL_COUNT_TAGSYM "$m"
+
+//@}
+
+#pragma pack()
+
+#endif // _ELF_h_
--- /dev/null
+/*
+ * File: ELFSourceFile.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "ELFSourceFile.h"
+#include "Logging.h"
+#include "GHSSecInfo.h"
+#include <ctype.h>
+#include <algorithm>
+#include "string.h"
+
+//! The name of the toolset option.
+#define kToolsetOptionName "toolset"
+#define kGHSToolsetName "GHS"
+#define kGCCToolsetName "GCC"
+#define kGNUToolsetName "GNU"
+#define kADSToolsetName "ADS"
+
+//! Name of the option to control .secinfo action.
+#define kSecinfoClearOptionName "secinfoClear"
+#define kSecinfoDefaultName "DEFAULT"
+#define kSecinfoIgnoreName "IGNORE"
+#define kSecinfoROMName "ROM"
+#define kSecinfoCName "C"
+
+using namespace elftosb;
+
+ELFSourceFile::ELFSourceFile(const std::string & path)
+: SourceFile(path),
+ m_toolset(kUnknownToolset),
+ m_secinfoOption(kSecinfoDefault)
+{
+}
+
+ELFSourceFile::~ELFSourceFile()
+{
+}
+
+bool ELFSourceFile::isELFFile(std::istream & stream)
+{
+ try
+ {
+ StELFFile elf(stream);
+ return true;
+ }
+ catch (...)
+ {
+ return false;
+ }
+}
+
+void ELFSourceFile::open()
+{
+ // Read toolset option
+ m_toolset = readToolsetOption();
+
+ // Read option and select default value
+ m_secinfoOption = readSecinfoClearOption();
+ if (m_secinfoOption == kSecinfoDefault)
+ {
+ m_secinfoOption = kSecinfoCStartupClear;
+ }
+
+ // Open the stream
+ SourceFile::open();
+
+ m_file = new StELFFile(*m_stream);
+// m_file->dumpSections();
+
+ // Set toolset in elf file object
+ switch (m_toolset)
+ {
+ // default toolset is GHS
+ case kGHSToolset:
+ case kUnknownToolset:
+ m_file->setELFVariant(eGHSVariant);
+ break;
+ case kGCCToolset:
+ m_file->setELFVariant(eGCCVariant);
+ break;
+ case kADSToolset:
+ m_file->setELFVariant(eARMVariant);
+ break;
+ }
+}
+
+void ELFSourceFile::close()
+{
+ SourceFile::close();
+
+ m_file.safe_delete();
+}
+
+elf_toolset_t ELFSourceFile::readToolsetOption()
+{
+ do {
+ const OptionContext * options = getOptions();
+ if (!options || !options->hasOption(kToolsetOptionName))
+ {
+ break;
+ }
+
+ const Value * value = options->getOption(kToolsetOptionName);
+ const StringValue * stringValue = dynamic_cast<const StringValue*>(value);
+ if (!stringValue)
+ {
+ // Not a string value, warn the user.
+ Log::log(Logger::WARNING, "invalid type for 'toolset' option\n");
+ break;
+ }
+
+ std::string toolsetName = *stringValue;
+
+ // convert option value to uppercase
+ std::transform<std::string::const_iterator, std::string::iterator, int (*)(int)>(toolsetName.begin(), toolsetName.end(), toolsetName.begin(), toupper);
+
+ if (toolsetName == kGHSToolsetName)
+ {
+ return kGHSToolset;
+ }
+ else if (toolsetName == kGCCToolsetName || toolsetName == kGNUToolsetName)
+ {
+ return kGCCToolset;
+ }
+ else if (toolsetName == kADSToolsetName)
+ {
+ return kADSToolset;
+ }
+
+ // Unrecognized option value, log a warning.
+ Log::log(Logger::WARNING, "unrecognized value for 'toolset' option\n");
+ } while (0);
+
+ return kUnknownToolset;
+}
+
+//! It is up to the caller to convert from kSecinfoDefault to the actual default
+//! value.
+secinfo_clear_t ELFSourceFile::readSecinfoClearOption()
+{
+ do {
+ const OptionContext * options = getOptions();
+ if (!options || !options->hasOption(kSecinfoClearOptionName))
+ {
+ break;
+ }
+
+ const Value * value = options->getOption(kSecinfoClearOptionName);
+ const StringValue * stringValue = dynamic_cast<const StringValue*>(value);
+ if (!stringValue)
+ {
+ // Not a string value, warn the user.
+ Log::log(Logger::WARNING, "invalid type for 'secinfoClear' option\n");
+ break;
+ }
+
+ std::string secinfoOption = *stringValue;
+
+ // convert option value to uppercase
+ std::transform<std::string::const_iterator, std::string::iterator, int (*)(int)>(secinfoOption.begin(), secinfoOption.end(), secinfoOption.begin(), toupper);
+
+ if (secinfoOption == kSecinfoDefaultName)
+ {
+ return kSecinfoDefault;
+ }
+ else if (secinfoOption == kSecinfoIgnoreName)
+ {
+ return kSecinfoIgnore;
+ }
+ else if (secinfoOption == kSecinfoROMName)
+ {
+ return kSecinfoROMClear;
+ }
+ else if (secinfoOption == kSecinfoCName)
+ {
+ return kSecinfoCStartupClear;
+ }
+
+ // Unrecognized option value, log a warning.
+ Log::log(Logger::WARNING, "unrecognized value for 'secinfoClear' option\n");
+ } while (0);
+
+ return kSecinfoDefault;
+}
+
+//! To create a data source for all sections of the ELF file, a WildcardMatcher
+//! is instantiated and passed to createDataSource(StringMatcher&).
+DataSource * ELFSourceFile::createDataSource()
+{
+ WildcardMatcher matcher;
+ return createDataSource(matcher);
+}
+
+DataSource * ELFSourceFile::createDataSource(StringMatcher & matcher)
+{
+ assert(m_file);
+ ELFDataSource * source = new ELFDataSource(m_file);
+ source->setSecinfoOption(m_secinfoOption);
+
+ Log::log(Logger::DEBUG2, "filtering sections of file: %s\n", getPath().c_str());
+
+ // We start at section 1 to skip the null section that is always first.
+ unsigned index = 1;
+ for (; index < m_file->getSectionCount(); ++index)
+ {
+ const Elf32_Shdr & header = m_file->getSectionAtIndex(index);
+ std::string name = m_file->getSectionNameAtIndex(header.sh_name);
+
+ // Ignore most section types
+ switch (header.sh_type) {
+ case SHT_PROGBITS:
+ case SHT_NOBITS:
+ case SHT_REL:
+ case SHT_DYNSYM:
+ break;
+
+ default:
+ continue;
+ }
+
+ // Ignore sections that don't have the allocate flag set.
+ if ((header.sh_flags & SHF_ALLOC) == 0)
+ {
+ continue;
+ }
+
+ if (matcher.match(name))
+ {
+ Log::log(Logger::DEBUG2, "creating segment for section %s\n", name.c_str());
+ source->addSection(index);
+ }
+ else
+ {
+ Log::log(Logger::DEBUG2, "section %s did not match\n", name.c_str());
+ }
+ }
+
+ return source;
+}
+
+//! It is assumed that all ELF files have an entry point.
+//!
+bool ELFSourceFile::hasEntryPoint()
+{
+ return true;
+}
+
+//! The StELFFile::getTypeOfSymbolAtIndex() method uses different methods of determining
+//! ARM/Thumb mode depending on the toolset.
+uint32_t ELFSourceFile::getEntryPointAddress()
+{
+ uint32_t entryPoint = 0;
+
+ // get entry point address
+ const Elf32_Ehdr & header = m_file->getFileHeader();
+
+ // find symbol corresponding to entry point and determine if
+ // it is arm or thumb mode
+ unsigned symbolIndex = m_file->getIndexOfSymbolAtAddress(header.e_entry);
+ if (symbolIndex != 0)
+ {
+ ARMSymbolType_t symbolType = m_file->getTypeOfSymbolAtIndex(symbolIndex);
+ bool entryPointIsThumb = (symbolType == eThumbSymbol);
+ const Elf32_Sym & symbol = m_file->getSymbolAtIndex(symbolIndex);
+ std::string symbolName = m_file->getSymbolName(symbol);
+
+ Log::log(Logger::DEBUG2, "Entry point is %s@0x%08x (%s)\n", symbolName.c_str(), symbol.st_value, entryPointIsThumb ? "Thumb" : "ARM");
+
+ // set entry point, setting the low bit if it is thumb mode
+ entryPoint = header.e_entry + (entryPointIsThumb ? 1 : 0);
+ }
+ else
+ {
+ entryPoint = header.e_entry;
+ }
+
+ return entryPoint;
+}
+
+//! \return A DataTarget that describes the named section.
+//! \retval NULL There was no section with the requested name.
+DataTarget * ELFSourceFile::createDataTargetForSection(const std::string & section)
+{
+ assert(m_file);
+ unsigned index = m_file->getIndexOfSectionWithName(section);
+ if (index == SHN_UNDEF)
+ {
+ return NULL;
+ }
+
+ const Elf32_Shdr & sectionHeader = m_file->getSectionAtIndex(index);
+ uint32_t beginAddress = sectionHeader.sh_addr;
+ uint32_t endAddress = beginAddress + sectionHeader.sh_size;
+ ConstantDataTarget * target = new ConstantDataTarget(beginAddress, endAddress);
+ return target;
+}
+
+//! \return A DataTarget instance pointing at the requested symbol.
+//! \retval NULL No symbol matching the requested name was found.
+DataTarget * ELFSourceFile::createDataTargetForSymbol(const std::string & symbol)
+{
+ assert(m_file);
+ unsigned symbolCount = m_file->getSymbolCount();
+ unsigned i;
+
+ for (i=0; i < symbolCount; ++i)
+ {
+ const Elf32_Sym & symbolHeader = m_file->getSymbolAtIndex(i);
+ std::string symbolName = m_file->getSymbolName(symbolHeader);
+ if (symbolName == symbol)
+ {
+ ARMSymbolType_t symbolType = m_file->getTypeOfSymbolAtIndex(i);
+ bool symbolIsThumb = (symbolType == eThumbSymbol);
+
+ uint32_t beginAddress = symbolHeader.st_value + (symbolIsThumb ? 1 : 0);
+ uint32_t endAddress = beginAddress + symbolHeader.st_size;
+ ConstantDataTarget * target = new ConstantDataTarget(beginAddress, endAddress);
+ return target;
+ }
+ }
+
+ // didn't find a matching symbol
+ return NULL;
+}
+
+bool ELFSourceFile::hasSymbol(const std::string & name)
+{
+ Elf32_Sym symbol;
+ return lookupSymbol(name, symbol);
+}
+
+uint32_t ELFSourceFile::getSymbolValue(const std::string & name)
+{
+ unsigned symbolCount = m_file->getSymbolCount();
+ unsigned i;
+
+ for (i=0; i < symbolCount; ++i)
+ {
+ const Elf32_Sym & symbolHeader = m_file->getSymbolAtIndex(i);
+ std::string symbolName = m_file->getSymbolName(symbolHeader);
+ if (symbolName == name)
+ {
+ // If the symbol is a function, then we check to see if it is Thumb code and set bit 0 if so.
+ if (ELF32_ST_TYPE(symbolHeader.st_info) == STT_FUNC)
+ {
+ ARMSymbolType_t symbolType = m_file->getTypeOfSymbolAtIndex(i);
+ bool symbolIsThumb = (symbolType == eThumbSymbol);
+ return symbolHeader.st_value + (symbolIsThumb ? 1 : 0);
+ }
+ else
+ {
+ return symbolHeader.st_value;
+ }
+ }
+ }
+
+ // Couldn't find the symbol, so return 0.
+ return 0;
+}
+
+unsigned ELFSourceFile::getSymbolSize(const std::string & name)
+{
+ Elf32_Sym symbol;
+ if (!lookupSymbol(name, symbol))
+ {
+ return 0;
+ }
+
+ return symbol.st_size;
+}
+
+//! \param name The name of the symbol on which info is wanted.
+//! \param[out] info Upon succssful return this is filled in with the symbol's information.
+//!
+//! \retval true The symbol was found and \a info is valid.
+//! \retval false No symbol with \a name was found in the file.
+bool ELFSourceFile::lookupSymbol(const std::string & name, Elf32_Sym & info)
+{
+ assert(m_file);
+ unsigned symbolCount = m_file->getSymbolCount();
+ unsigned i;
+
+ for (i=0; i < symbolCount; ++i)
+ {
+ const Elf32_Sym & symbol = m_file->getSymbolAtIndex(i);
+ std::string thisSymbolName = m_file->getSymbolName(symbol);
+
+ // Is this the symbol we're looking for?
+ if (thisSymbolName == name)
+ {
+ info = symbol;
+ return true;
+ }
+ }
+
+ // Didn't file the symbol.
+ return false;
+}
+
+ELFSourceFile::ELFDataSource::~ELFDataSource()
+{
+ segment_vector_t::iterator it = m_segments.begin();
+ for (; it != m_segments.end(); ++it)
+ {
+ delete *it;
+ }
+}
+
+//! Not all sections will actually result in a new segment being created. Only
+//! those sections whose type is #SHT_PROGBITS or #SHT_NOBITS will create
+//! a new segment. Also, only sections whose size is non-zero will actually
+//! create a segment.
+//!
+//! In addition to this, ELF files that have been marked as being created by
+//! the Green Hills Software toolset have an extra step. #SHT_NOBITS sections
+//! are looked up in the .secinfo section to determine if they really
+//! should be filled. If not in the .secinfo table, no segment will be
+//! created for the section.
+void ELFSourceFile::ELFDataSource::addSection(unsigned sectionIndex)
+{
+ // get section info
+ const Elf32_Shdr & section = m_elf->getSectionAtIndex(sectionIndex);
+ if (section.sh_size == 0)
+ {
+ // empty section, so ignore it
+ return;
+ }
+
+ // create the right segment subclass based on the section type
+ DataSource::Segment * segment = NULL;
+ switch (section.sh_type) {
+ case SHT_PROGBITS:
+ case SHT_REL:
+ case SHT_DYNSYM:
+ segment = new ProgBitsSegment(*this, m_elf, sectionIndex);
+ break;
+
+ case SHT_NOBITS:
+ {
+ // Always add NOBITS sections by default.
+ bool addNobits = true;
+
+ // For GHS ELF files, we use the secinfoClear option to figure out what to do.
+ // If set to ignore, treat like a normal ELF file and always add. If set to
+ // ROM, then only clear if the section is listed in .secinfo. Otherwise if set
+ // to C startup, then let the C startup do all clearing.
+ addNobits = false;
+ if (m_elf->ELFVariant() == eGHSVariant)
+ {
+ GHSSecInfo secinfo(m_elf);
+
+ // If there isn't a .secinfo section present then use the normal ELF rules
+ // and always add NOBITS sections.
+ if (secinfo.hasSecinfo() && m_secinfoOption != kSecinfoIgnore)
+ {
+ switch (m_secinfoOption)
+ {
+ case kSecinfoROMClear:
+ addNobits = secinfo.isSectionFilled(section);
+ break;
+
+ case kSecinfoCStartupClear:
+ addNobits = false;
+ break;
+ }
+ }
+ }
+
+ if (addNobits)
+ {
+ segment = new NoBitsSegment(*this, m_elf, sectionIndex);
+ }
+ else
+ {
+ std::string name = m_elf->getSectionNameAtIndex(section.sh_name);
+ Log::log(Logger::DEBUG2, "..section %s is not filled\n", name.c_str());
+ }
+ }
+ break;
+ }
+ // add segment if one was created
+ if (segment)
+ {
+ m_segments.push_back(segment);
+ }
+}
+
+ELFSourceFile::ELFDataSource::ProgBitsSegment::ProgBitsSegment(ELFDataSource & source, StELFFile * elf, unsigned index)
+: DataSource::Segment(source), m_elf(elf), m_sectionIndex(index)
+{
+}
+
+unsigned ELFSourceFile::ELFDataSource::ProgBitsSegment::getData(unsigned offset, unsigned maxBytes, uint8_t * buffer)
+{
+ const Elf32_Shdr & section = m_elf->getSectionAtIndex(m_sectionIndex);
+ uint8_t * data = m_elf->getSectionDataAtIndex(m_sectionIndex);
+
+ assert(offset < section.sh_size);
+
+ unsigned copyBytes = std::min<unsigned>(section.sh_size - offset, maxBytes);
+ if (copyBytes)
+ {
+ memcpy(buffer, &data[offset], copyBytes);
+ }
+
+ return copyBytes;
+}
+
+unsigned ELFSourceFile::ELFDataSource::ProgBitsSegment::getLength()
+{
+ const Elf32_Shdr & section = m_elf->getSectionAtIndex(m_sectionIndex);
+ return section.sh_size;
+}
+
+uint32_t ELFSourceFile::ELFDataSource::ProgBitsSegment::getBaseAddress()
+{
+ const Elf32_Shdr & section = m_elf->getSectionAtIndex(m_sectionIndex);
+ return section.sh_addr;
+}
+
+ELFSourceFile::ELFDataSource::NoBitsSegment::NoBitsSegment(ELFDataSource & source, StELFFile * elf, unsigned index)
+: DataSource::PatternSegment(source), m_elf(elf), m_sectionIndex(index)
+{
+}
+
+unsigned ELFSourceFile::ELFDataSource::NoBitsSegment::getLength()
+{
+ const Elf32_Shdr & section = m_elf->getSectionAtIndex(m_sectionIndex);
+ return section.sh_size;
+}
+
+uint32_t ELFSourceFile::ELFDataSource::NoBitsSegment::getBaseAddress()
+{
+ const Elf32_Shdr & section = m_elf->getSectionAtIndex(m_sectionIndex);
+ return section.sh_addr;
+}
+
--- /dev/null
+/*
+ * File: ELFSourceFile.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_ELFSourceFile_h_)
+#define _ELFSourceFile_h_
+
+#include "SourceFile.h"
+#include "StELFFile.h"
+#include "smart_ptr.h"
+#include "DataSource.h"
+#include "DataTarget.h"
+#include "ELF.h"
+
+namespace elftosb
+{
+
+//! Set of supported compiler toolsets.
+enum elf_toolset_t
+{
+ kUnknownToolset, //!< Unknown.
+ kGHSToolset, //!< Green Hills Software MULTI
+ kGCCToolset, //!< GNU GCC
+ kADSToolset //!< ARM UK RealView
+};
+
+//! Options for handling the .secinfo section in GHS-produced ELF files.
+enum secinfo_clear_t
+{
+ // Default value for the .secinfo action.
+ kSecinfoDefault,
+
+ //! Ignore the .secinfo section if present. The standard ELF loading
+ //! rules are followed.
+ kSecinfoIgnore,
+
+ //! The boot ROM clears only those SHT_NOBITS sections present in .secinfo.
+ kSecinfoROMClear,
+
+ //! The C startup is responsible for clearing sections. No fill commands
+ //! are generated for any SHT_NOBITS sections.
+ kSecinfoCStartupClear
+};
+
+/*!
+ * \brief Executable and Loading Format (ELF) source file.
+ */
+class ELFSourceFile : public SourceFile
+{
+public:
+ //! \brief Default constructor.
+ ELFSourceFile(const std::string & path);
+
+ //! \brief Destructor.
+ virtual ~ELFSourceFile();
+
+ //! \brief Identifies whether the stream contains an ELF file.
+ static bool isELFFile(std::istream & stream);
+
+ //! \name Opening and closing
+ //@{
+ //! \brief Opens the file.
+ virtual void open();
+
+ //! \brief Closes the file.
+ virtual void close();
+ //@}
+
+ //! \name Format capabilities
+ //@{
+ virtual bool supportsNamedSections() const { return true; }
+ virtual bool supportsNamedSymbols() const { return true; }
+ //@}
+
+ //! \name Data source
+ //@{
+ //! \brief Creates a data source from the entire file.
+ virtual DataSource * createDataSource();
+
+ //! \brief Creates a data source from one or more sections of the file.
+ virtual DataSource * createDataSource(StringMatcher & matcher);
+ //@}
+
+ //! \name Entry point
+ //@{
+ //! \brief Returns true if an entry point was set in the file.
+ virtual bool hasEntryPoint();
+
+ //! \brief Returns the entry point address.
+ virtual uint32_t getEntryPointAddress();
+ //@}
+
+ //! \name Data target
+ //@{
+ virtual DataTarget * createDataTargetForSection(const std::string & section);
+ virtual DataTarget * createDataTargetForSymbol(const std::string & symbol);
+ //@}
+
+ //! \name Symbols
+ //@{
+ //! \brief Returns whether a symbol exists in the source file.
+ virtual bool hasSymbol(const std::string & name);
+
+ //! \brief Returns the value of a symbol.
+ virtual uint32_t getSymbolValue(const std::string & name);
+
+ //! \brief Returns the size of a symbol.
+ virtual unsigned getSymbolSize(const std::string & name);
+ //@}
+
+ //! \name Direct ELF format access
+ //@{
+ //! \brief Returns the underlying StELFFile object.
+ StELFFile * getELFFile() { return m_file; }
+
+ //! \brief Gets information about a symbol in the ELF file.
+ bool lookupSymbol(const std::string & name, Elf32_Sym & info);
+ //@}
+
+protected:
+ smart_ptr<StELFFile> m_file; //!< Parser for the ELF file.
+ elf_toolset_t m_toolset; //!< Toolset that produced the ELF file.
+ secinfo_clear_t m_secinfoOption; //!< How to deal with the .secinfo section. Ignored if the toolset is not GHS.
+
+protected:
+ //! \brief Parses the toolset option value.
+ elf_toolset_t readToolsetOption();
+
+ //! \brief Reads the secinfoClear option.
+ secinfo_clear_t readSecinfoClearOption();
+
+protected:
+ /*!
+ * \brief A data source with ELF file sections as the contents.
+ *
+ * Each segment of this data source corresponds directly with a named section
+ * of the ELF file it represents. When the data source is created, it contains
+ * no segments. Segments are created with the addSection() method, which takes
+ * the index of an ELF section and creates a corresponding segment.
+ *
+ * Two segment subclasses are used with this data source. The first, ProgBitsSegment,
+ * is used to represent sections whose type is #SHT_PROGBITS. These sections have
+ * binary data stored in the ELF file. The second segment type is NoBitsSegment.
+ * It is used to represent sections whose type is #SHT_NOBITS. These sections have
+ * no data, but simply allocate a region of memory to be filled with zeroes.
+ * As such, the NoBitsSegment class is a subclass of DataSource::PatternSegment.
+ */
+ class ELFDataSource : public DataSource
+ {
+ public:
+ /*!
+ * \brief Represents one named #SHT_PROGBITS section within the ELF file.
+ */
+ class ProgBitsSegment : public DataSource::Segment
+ {
+ public:
+ ProgBitsSegment(ELFDataSource & source, StELFFile * elf, unsigned index);
+
+ virtual unsigned getData(unsigned offset, unsigned maxBytes, uint8_t * buffer);
+ virtual unsigned getLength();
+
+ virtual bool hasNaturalLocation() { return true; }
+ virtual uint32_t getBaseAddress();
+
+ protected:
+ StELFFile * m_elf; //!< The format parser instance for this ELF file.
+ unsigned m_sectionIndex; //!< The index of the section this segment represents.
+ };
+
+ /*!
+ * \brief Represents one named #SHT_NOBITS section within the ELF file.
+ *
+ * This segment class is a subclass of DataSource::PatternSegment since it
+ * represents a region of memory to be filled with zeroes.
+ */
+ class NoBitsSegment : public DataSource::PatternSegment
+ {
+ public:
+ NoBitsSegment(ELFDataSource & source, StELFFile * elf, unsigned index);
+
+ virtual unsigned getLength();
+
+ virtual bool hasNaturalLocation() { return true; }
+ virtual uint32_t getBaseAddress();
+
+ protected:
+ StELFFile * m_elf; //!< The format parser instance for this ELF file.
+ unsigned m_sectionIndex; //!< The index of the section this segment represents.
+ };
+
+ public:
+ //! \brief Default constructor.
+ ELFDataSource(StELFFile * elf) : DataSource(), m_elf(elf) {}
+
+ //! \brief Destructor.
+ virtual ~ELFDataSource();
+
+ //! Set the option to control .secinfo usage.
+ inline void setSecinfoOption(secinfo_clear_t option) { m_secinfoOption = option; }
+
+ //! \brief Adds the ELF section at position \a sectionIndex to the data source.
+ void addSection(unsigned sectionIndex);
+
+ //! \brief Returns the number of segments in the source.
+ virtual unsigned getSegmentCount() { return (unsigned)m_segments.size(); }
+
+ //! \brief Returns the segment at position \a index.
+ virtual DataSource::Segment * getSegmentAt(unsigned index) { return m_segments[index]; }
+
+ protected:
+ StELFFile * m_elf; //!< The ELF file parser.
+ secinfo_clear_t m_secinfoOption; //!< How to deal with the .secinfo section. Ignored if the toolset is not GHS.
+
+ typedef std::vector<DataSource::Segment*> segment_vector_t; //!< A list of segment instances.
+ segment_vector_t m_segments; //!< The segments of this data source.
+ };
+
+};
+
+}; // namespace elftosb
+
+#endif // _ELFSourceFile_h_
--- /dev/null
+/*
+ * File: EncoreBootImage.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "EncoreBootImage.h"
+#include <stdexcept>
+#include <algorithm>
+#include <time.h>
+#include "crc.h"
+#include "SHA1.h"
+#include "Random.h"
+#include "rijndael.h"
+#include "RijndaelCBCMAC.h"
+#include "Logging.h"
+#include "EndianUtilities.h"
+
+using namespace elftosb;
+
+EncoreBootImage::EncoreBootImage()
+: m_headerFlags(0),
+ m_productVersion(),
+ m_componentVersion(),
+ m_driveTag(0)
+{
+}
+
+EncoreBootImage::~EncoreBootImage()
+{
+ // dispose of all sections
+ section_iterator_t it = beginSection();
+ for (; it != endSection(); ++it)
+ {
+ delete *it;
+ }
+}
+
+//! \exception std::runtime_error Raised if \a newSection has the same tag as a previously
+//! added section.
+void EncoreBootImage::addSection(Section * newSection)
+{
+ // check for another section with this tag
+ section_iterator_t it = beginSection();
+ for (; it != endSection(); ++it)
+ {
+ if ((*it)->getIdentifier() == newSection->getIdentifier())
+ {
+ throw std::runtime_error("new section with non-unique tag");
+ }
+ }
+
+ // no conflicting section tags, so add it
+ m_sections.push_back(newSection);
+
+ // tell the image who owns it now
+ newSection->setImage(this);
+}
+
+EncoreBootImage::section_iterator_t EncoreBootImage::findSection(Section * section)
+{
+ return std::find(beginSection(), endSection(), section);
+}
+
+void EncoreBootImage::setProductVersion(const version_t & version)
+{
+ m_productVersion = version;
+}
+
+void EncoreBootImage::setComponentVersion(const version_t & version)
+{
+ m_componentVersion = version;
+}
+
+//! \todo Optimize writing section data. Right now it only writes one block at a
+//! time, which is of course quite slow (in relative terms).
+//! \todo Refactor this into several different methods for writing each region
+//! of the image. Use a context structure to keep track of shared data between
+//! each of the methods.
+//! \todo Refactor the section and boot tag writing code to only have a single
+//! copy of the block writing and encryption loop.
+void EncoreBootImage::writeToStream(std::ostream & stream)
+{
+ // always generate the session key or DEK even if image is unencrypted
+ m_sessionKey.randomize();
+
+ // prepare to compute CBC-MACs with each KEK
+ unsigned i;
+ smart_array_ptr<RijndaelCBCMAC> macs(0);
+ if (isEncrypted())
+ {
+ macs = new RijndaelCBCMAC[m_keys.size()];
+ for (i=0; i < m_keys.size(); ++i)
+ {
+ RijndaelCBCMAC mac(m_keys[i]);
+ (macs.get())[i] = mac;
+ }
+ }
+
+ // prepare to compute SHA-1 digest over entire image
+ CSHA1 hash;
+ hash.Reset();
+
+ // count of total blocks written to the file
+ unsigned fileBlocksWritten = 0;
+
+ // we need some pieces of the header down below
+ boot_image_header_t imageHeader;
+ prepareImageHeader(imageHeader);
+
+ // write plaintext header
+ {
+ // write header
+ assert(sizeOfPaddingForCipherBlocks(sizeof(boot_image_header_t)) == 0);
+ stream.write(reinterpret_cast<char *>(&imageHeader), sizeof(imageHeader));
+ fileBlocksWritten += numberOfCipherBlocks(sizeof(imageHeader));
+
+ // update CBC-MAC over image header
+ if (isEncrypted())
+ {
+ for (i=0; i < m_keys.size(); ++i)
+ {
+ (macs.get())[i].update(reinterpret_cast<uint8_t *>(&imageHeader), sizeof(imageHeader));
+ }
+ }
+
+ // update SHA-1
+ hash.Update(reinterpret_cast<uint8_t *>(&imageHeader), sizeof(imageHeader));
+ }
+
+ // write plaintext section table
+ {
+ section_iterator_t it = beginSection();
+ for (; it != endSection(); ++it)
+ {
+ Section * section = *it;
+
+ // write header for this section
+ assert(sizeOfPaddingForCipherBlocks(sizeof(section_header_t)) == 0);
+ section_header_t sectionHeader;
+ section->fillSectionHeader(sectionHeader);
+ stream.write(reinterpret_cast<char *>(§ionHeader), sizeof(sectionHeader));
+ fileBlocksWritten += numberOfCipherBlocks(sizeof(sectionHeader));
+
+ // update CBC-MAC over this entry
+ if (isEncrypted())
+ {
+ for (i=0; i < m_keys.size(); ++i)
+ {
+ (macs.get())[i].update(reinterpret_cast<uint8_t *>(§ionHeader), sizeof(sectionHeader));
+ }
+ }
+
+ // update SHA-1
+ hash.Update(reinterpret_cast<uint8_t *>(§ionHeader), sizeof(sectionHeader));
+ }
+ }
+
+ // finished with the CBC-MAC
+ if (isEncrypted())
+ {
+ for (i=0; i < m_keys.size(); ++i)
+ {
+ (macs.get())[i].finalize();
+ }
+ }
+
+ // write key dictionary
+ if (isEncrypted())
+ {
+ key_iterator_t it = beginKeys();
+ for (i=0; it != endKeys(); ++it, ++i)
+ {
+ // write CBC-MAC result for this key, then update SHA-1
+ RijndaelCBCMAC & mac = (macs.get())[i];
+ const RijndaelCBCMAC::block_t & macResult = mac.getMAC();
+ stream.write(reinterpret_cast<const char *>(&macResult), sizeof(RijndaelCBCMAC::block_t));
+ hash.Update(reinterpret_cast<const uint8_t *>(&macResult), sizeof(RijndaelCBCMAC::block_t));
+ fileBlocksWritten++;
+
+ // encrypt DEK with this key, write it out, and update image digest
+ Rijndael cipher;
+ cipher.init(Rijndael::CBC, Rijndael::Encrypt, *it, Rijndael::Key16Bytes, imageHeader.m_iv);
+ AESKey<128>::key_t wrappedSessionKey;
+ cipher.blockEncrypt(m_sessionKey, sizeof(AESKey<128>::key_t) * 8, wrappedSessionKey);
+ stream.write(reinterpret_cast<char *>(&wrappedSessionKey), sizeof(wrappedSessionKey));
+ hash.Update(reinterpret_cast<uint8_t *>(&wrappedSessionKey), sizeof(wrappedSessionKey));
+ fileBlocksWritten++;
+ }
+ }
+
+ // write sections and boot tags
+ {
+ section_iterator_t it = beginSection();
+ for (; it != endSection(); ++it)
+ {
+ section_iterator_t itCopy = it;
+ bool isLastSection = (++itCopy == endSection());
+
+ Section * section = *it;
+ cipher_block_t block;
+ unsigned blockCount = section->getBlockCount();
+ unsigned blocksWritten = 0;
+
+ Rijndael cipher;
+ cipher.init(Rijndael::CBC, Rijndael::Encrypt, m_sessionKey, Rijndael::Key16Bytes, imageHeader.m_iv);
+
+ // Compute the number of padding blocks needed to align the section. This first
+ // call to getPadBlockCountForOffset() passes an offset that excludes
+ // the boot tag for this section.
+ unsigned paddingBlocks = getPadBlockCountForSection(section, fileBlocksWritten);
+
+ // Insert nop commands as padding to align the start of the section, if
+ // the section has special alignment requirements.
+ NopCommand nop;
+ while (paddingBlocks--)
+ {
+ blockCount = nop.getBlockCount();
+ blocksWritten = 0;
+ while (blocksWritten < blockCount)
+ {
+ nop.getBlocks(blocksWritten, 1, &block);
+
+ if (isEncrypted())
+ {
+ // re-init after encrypt to update IV
+ cipher.blockEncrypt(block, sizeof(cipher_block_t) * 8, block);
+ cipher.init(Rijndael::CBC, Rijndael::Encrypt, m_sessionKey, Rijndael::Key16Bytes, block);
+ }
+
+ stream.write(reinterpret_cast<char *>(&block), sizeof(cipher_block_t));
+ hash.Update(reinterpret_cast<uint8_t *>(&block), sizeof(cipher_block_t));
+
+ blocksWritten++;
+ fileBlocksWritten++;
+ }
+ }
+
+ // reinit cipher for boot tag
+ cipher.init(Rijndael::CBC, Rijndael::Encrypt, m_sessionKey, Rijndael::Key16Bytes, imageHeader.m_iv);
+
+ // write boot tag
+ TagCommand tag(*section);
+ tag.setLast(isLastSection);
+ if (!isLastSection)
+ {
+ // If this isn't the last section, the tag needs to include any
+ // padding for the next section in its length, otherwise the ROM
+ // won't be able to find the next section's boot tag.
+ unsigned nextSectionOffset = fileBlocksWritten + section->getBlockCount() + 1;
+ tag.setSectionLength(section->getBlockCount() + getPadBlockCountForSection(*itCopy, nextSectionOffset));
+ }
+ blockCount = tag.getBlockCount();
+ blocksWritten = 0;
+ while (blocksWritten < blockCount)
+ {
+ tag.getBlocks(blocksWritten, 1, &block);
+
+ if (isEncrypted())
+ {
+ // re-init after encrypt to update IV
+ cipher.blockEncrypt(block, sizeof(cipher_block_t) * 8, block);
+ cipher.init(Rijndael::CBC, Rijndael::Encrypt, m_sessionKey, Rijndael::Key16Bytes, block);
+ }
+
+ stream.write(reinterpret_cast<char *>(&block), sizeof(cipher_block_t));
+ hash.Update(reinterpret_cast<uint8_t *>(&block), sizeof(cipher_block_t));
+
+ blocksWritten++;
+ fileBlocksWritten++;
+ }
+
+ // reinit cipher for section data
+ cipher.init(Rijndael::CBC, Rijndael::Encrypt, m_sessionKey, Rijndael::Key16Bytes, imageHeader.m_iv);
+
+ // write section data
+ blockCount = section->getBlockCount();
+ blocksWritten = 0;
+ while (blocksWritten < blockCount)
+ {
+ section->getBlocks(blocksWritten, 1, &block);
+
+ // Only encrypt the section contents if the entire boot image is encrypted
+ // and the section doesn't have the "leave unencrypted" flag set. Even if the
+ // section is unencrypted the boot tag will remain encrypted.
+ if (isEncrypted() && !section->getLeaveUnencrypted())
+ {
+ // re-init after encrypt to update IV
+ cipher.blockEncrypt(block, sizeof(cipher_block_t) * 8, block);
+ cipher.init(Rijndael::CBC, Rijndael::Encrypt, m_sessionKey, Rijndael::Key16Bytes, block);
+ }
+
+ stream.write(reinterpret_cast<char *>(&block), sizeof(cipher_block_t));
+ hash.Update(reinterpret_cast<uint8_t *>(&block), sizeof(cipher_block_t));
+
+ blocksWritten++;
+ fileBlocksWritten++;
+ }
+ }
+ }
+
+ // write SHA-1 digest over entire image
+ {
+ // allocate enough room for digest and bytes to pad out to the next cipher block
+ const unsigned padBytes = sizeOfPaddingForCipherBlocks(sizeof(sha1_digest_t));
+ unsigned digestBlocksSize = sizeof(sha1_digest_t) + padBytes;
+ smart_array_ptr<uint8_t> digestBlocks = new uint8_t[digestBlocksSize];
+ hash.Final();
+ hash.GetHash(digestBlocks.get());
+
+ // set the pad bytes to random values
+ RandomNumberGenerator rng;
+ rng.generateBlock(&(digestBlocks.get())[sizeof(sha1_digest_t)], padBytes);
+
+ // encrypt with session key
+ if (isEncrypted())
+ {
+ Rijndael cipher;
+ cipher.init(Rijndael::CBC, Rijndael::Encrypt, m_sessionKey, Rijndael::Key16Bytes, imageHeader.m_iv);
+ cipher.blockEncrypt(digestBlocks.get(), digestBlocksSize * 8, digestBlocks.get());
+ }
+
+ // write to the stream
+ stream.write(reinterpret_cast<char *>(digestBlocks.get()), digestBlocksSize);
+ }
+}
+
+void EncoreBootImage::prepareImageHeader(boot_image_header_t & header)
+{
+ // get identifier for the first bootable section
+ Section * firstBootSection = findFirstBootableSection();
+ section_id_t firstBootSectionID = 0;
+ if (firstBootSection)
+ {
+ firstBootSectionID = firstBootSection->getIdentifier();
+ }
+
+ // fill in header fields
+ header.m_signature[0] = 'S';
+ header.m_signature[1] = 'T';
+ header.m_signature[2] = 'M';
+ header.m_signature[3] = 'P';
+ header.m_majorVersion = ROM_BOOT_IMAGE_MAJOR_VERSION;
+ header.m_minorVersion = ROM_BOOT_IMAGE_MINOR_VERSION;
+ header.m_flags = ENDIAN_HOST_TO_LITTLE_U16(m_headerFlags);
+ header.m_imageBlocks = ENDIAN_HOST_TO_LITTLE_U32(getImageSize());
+ header.m_firstBootableSectionID = ENDIAN_HOST_TO_LITTLE_U32(firstBootSectionID);
+ header.m_keyCount = ENDIAN_HOST_TO_LITTLE_U16((uint16_t)m_keys.size());
+ header.m_headerBlocks = ENDIAN_HOST_TO_LITTLE_U16((uint16_t)numberOfCipherBlocks(sizeof(header)));
+ header.m_sectionCount = ENDIAN_HOST_TO_LITTLE_U16((uint16_t)m_sections.size());
+ header.m_sectionHeaderSize = ENDIAN_HOST_TO_LITTLE_U16((uint16_t)numberOfCipherBlocks(sizeof(section_header_t)));
+ header.m_signature2[0] = 's';
+ header.m_signature2[1] = 'g';
+ header.m_signature2[2] = 't';
+ header.m_signature2[3] = 'l';
+ header.m_timestamp = ENDIAN_HOST_TO_LITTLE_U64(getTimestamp());
+ header.m_driveTag = m_driveTag;
+
+ // Prepare version fields by converting them to the correct byte order.
+ header.m_productVersion = m_productVersion;
+ header.m_componentVersion = m_componentVersion;
+ header.m_productVersion.fixByteOrder();
+ header.m_componentVersion.fixByteOrder();
+
+ // the fields are dependant on others
+ header.m_keyDictionaryBlock = ENDIAN_HOST_TO_LITTLE_U16(header.m_headerBlocks + header.m_sectionCount * header.m_sectionHeaderSize);
+ header.m_firstBootTagBlock = ENDIAN_HOST_TO_LITTLE_U32(header.m_keyDictionaryBlock + header.m_keyCount * 2);
+
+ // generate random pad bytes
+ RandomNumberGenerator rng;
+ rng.generateBlock(header.m_padding0, sizeof(header.m_padding0));
+ rng.generateBlock(header.m_padding1, sizeof(header.m_padding1));
+
+ // compute SHA-1 digest over the image header
+ uint8_t * message = reinterpret_cast<uint8_t *>(&header.m_signature);
+ uint32_t length = static_cast<uint32_t>(sizeof(header) - sizeof(header.m_digest)); // include padding
+
+ CSHA1 hash;
+ hash.Reset();
+ hash.Update(message, length);
+ hash.Final();
+ hash.GetHash(header.m_digest);
+}
+
+//! Returns the number of microseconds since 00:00 1-1-2000. In actuality, the timestamp
+//! is only accurate to seconds, and is simply extended out to microseconds.
+//!
+//! \todo Use the operating system's low-level functions to get a true microsecond
+//! timestamp, instead of faking it like we do now.
+//! \bug The timestamp might be off an hour.
+uint64_t EncoreBootImage::getTimestamp()
+{
+#if WIN32
+ struct tm epoch = { 0, 0, 0, 1, 0, 100, 0, 0 }; // 00:00 1-1-2000
+#else
+ struct tm epoch = { 0, 0, 0, 1, 0, 100, 0, 0, 1, 0, NULL }; // 00:00 1-1-2000
+#endif
+ time_t epochTime = mktime(&epoch);
+ time_t now = time(NULL);
+ now -= epochTime;
+ uint64_t microNow = uint64_t(now) * 1000000; // convert to microseconds
+ return microNow;
+}
+
+//! Scans the section list looking for the first section which has
+//! the #ROM_SECTION_BOOTABLE flag set on it.
+EncoreBootImage::Section * EncoreBootImage::findFirstBootableSection()
+{
+ section_iterator_t it = beginSection();
+ for (; it != endSection(); ++it)
+ {
+ if ((*it)->getFlags() & ROM_SECTION_BOOTABLE)
+ {
+ return *it;
+ }
+ }
+
+ // no bootable sections were found
+ return NULL;
+}
+
+//! The boot tag for \a section is taken into account, thus making the
+//! result offset point to the first block of the actual section data.
+//!
+//! \note The offset will only be valid if all encryption keys and all
+//! sections have already been added to the image.
+uint32_t EncoreBootImage::getSectionOffset(Section * section)
+{
+ // start with boot image headers
+ uint32_t offset = numberOfCipherBlocks(sizeof(boot_image_header_t)); // header
+ offset += numberOfCipherBlocks(sizeof(section_header_t)) * sectionCount(); // section table
+ offset += 2 * keyCount(); // key dictiontary
+
+ // add up sections before this one
+ section_iterator_t it = beginSection();
+ for (; it != endSection() && *it != section; ++it)
+ {
+ Section * thisSection = *it;
+
+ // insert padding for section alignment
+ offset += getPadBlockCountForSection(thisSection, offset);
+
+ // add one for boot tag associated with this section
+ offset++;
+
+ // now add the section's contents
+ offset += thisSection->getBlockCount();
+ }
+
+ // and add padding for this section
+ offset += getPadBlockCountForSection(section, offset);
+
+ // skip over this section's boot tag
+ offset++;
+
+ return offset;
+}
+
+//! Computes the number of blocks of padding required to align \a section while
+//! taking into account the boot tag that gets inserted before the section contents.
+unsigned EncoreBootImage::getPadBlockCountForSection(Section * section, unsigned offset)
+{
+ // Compute the number of padding blocks needed to align the section. This first
+ // call to getPadBlockCountForOffset() passes an offset that excludes
+ // the boot tag for this section.
+ unsigned paddingBlocks = section->getPadBlockCountForOffset(offset);
+
+ // If the pad count comes back as 0 then we need to try again with an offset that
+ // includes the boot tag. This is all because we're aligning the section contents
+ // start and not the section's boot tag.
+ if (paddingBlocks == 0)
+ {
+ paddingBlocks = section->getPadBlockCountForOffset(offset + 1);
+ }
+ // Otherwise if we get a nonzero pad amount then we need to subtract the block
+ // for the section's boot tag from the pad count.
+ else
+ {
+ paddingBlocks--;
+ }
+
+ return paddingBlocks;
+}
+
+uint32_t EncoreBootImage::getImageSize()
+{
+ // determine to total size of the image
+ const uint32_t headerBlocks = numberOfCipherBlocks(sizeof(boot_image_header_t));
+ const uint32_t sectionHeaderSize = numberOfCipherBlocks(sizeof(section_header_t));
+ uint32_t imageBlocks = headerBlocks;
+ imageBlocks += sectionHeaderSize * m_sections.size(); // section table
+ imageBlocks += 2 * m_keys.size(); // key dict
+
+ // add in each section's size
+ section_iterator_t it = beginSection();
+ for (; it != endSection(); ++it)
+ {
+ // add in this section's size, padding to align it, and its boot tag
+ imageBlocks += getPadBlockCountForSection(*it, imageBlocks);
+ imageBlocks += (*it)->getBlockCount();
+ imageBlocks++;
+ }
+
+ // image MAC
+ imageBlocks += 2;
+
+ return imageBlocks;
+}
+
+void EncoreBootImage::debugPrint() const
+{
+ const_section_iterator_t it = beginSection();
+ for (; it != endSection(); ++it)
+ {
+ const Section * section = *it;
+ section->debugPrint();
+ }
+}
+
+//! \param blocks Pointer to the raw data blocks.
+//! \param count Number of blocks pointed to by \a blocks.
+//! \param[out] consumed On exit, this points to the number of cipher blocks that were occupied
+//! by the command. Should be at least 1 for every command. This must not be NULL
+//! on entry!
+//!
+//! \return A new boot command instance.
+//! \retval NULL The boot command pointed to by \a blocks was not recognized as a known
+//! command type.
+//!
+//! \exception std::runtime_error This exception indicates that a command was recognized
+//! but contained invalid data. Compare this to a NULL result which indicates that
+//! no command was recognized at all.
+EncoreBootImage::BootCommand * EncoreBootImage::BootCommand::createFromData(const cipher_block_t * blocks, unsigned count, unsigned * consumed)
+{
+ const boot_command_t * header = reinterpret_cast<const boot_command_t *>(blocks);
+ BootCommand * command = NULL;
+
+ switch (header->m_tag)
+ {
+ case ROM_NOP_CMD:
+ command = new NopCommand();
+ break;
+ case ROM_TAG_CMD:
+ command = new TagCommand();
+ break;
+ case ROM_LOAD_CMD:
+ command = new LoadCommand();
+ break;
+ case ROM_FILL_CMD:
+ command = new FillCommand();
+ break;
+ case ROM_MODE_CMD:
+ command = new ModeCommand();
+ break;
+ case ROM_JUMP_CMD:
+ command = new JumpCommand();
+ break;
+ case ROM_CALL_CMD:
+ command = new CallCommand();
+ break;
+ }
+
+ if (command)
+ {
+ command->initFromData(blocks, count, consumed);
+ }
+ return command;
+}
+
+//! The checksum algorithm is totally straightforward, except that the
+//! initial checksum byte value is set to 0x5a instead of 0.
+uint8_t EncoreBootImage::BootCommand::calculateChecksum(const boot_command_t & header)
+{
+ const uint8_t * bytes = reinterpret_cast<const uint8_t *>(&header);
+ uint8_t checksum = 0x5a;
+ int i;
+
+ // start at one to skip checksum field
+ for (i = 1; i < sizeof(header); ++i)
+ {
+ checksum += bytes[i];
+ }
+
+ return checksum;
+}
+
+//! The default implementation returns 0, indicating that no blocks are
+//! available.
+unsigned EncoreBootImage::BootCommand::getBlockCount() const
+{
+ return 1 + getDataBlockCount();
+}
+
+//! Up to \a maxCount cipher blocks are copied into the buffer pointed to by
+//! the \a data argument. The index of the first block to copy is
+//! held in the \a offset argument.
+//!
+//! \param offset Starting block number to copy. Zero means the first available block.
+//! \param maxCount Up to this number of blocks may be copied into \a data. Must be 1 or greater.
+//! \param data Buffer for outgoing cipher blocks. Must have enough room to hold
+//! \a maxCount blocks.
+//!
+//! \return The number of cipher blocks copied into \a data.
+//! \retval 0 No more blocks are available and nothing was written to \a data.
+//!
+//! \exception std::out_of_range If \a offset is invalid.
+unsigned EncoreBootImage::BootCommand::getBlocks(unsigned offset, unsigned maxCount, cipher_block_t * data)
+{
+ assert(data);
+ assert(maxCount >= 1);
+
+ // check for valid offset
+ if (offset >= getBlockCount())
+ {
+ throw std::out_of_range("invalid offset");
+ }
+
+ // handle the command header block separately
+ if (offset == 0)
+ {
+ assert(sizeof(boot_command_t) == sizeof(cipher_block_t));
+
+ boot_command_t header;
+ fillCommandHeader(header);
+ memcpy(data, &header, sizeof(header));
+
+ return 1;
+ }
+
+ // handle any data blocks
+ return getDataBlocks(offset - 1, maxCount, data);
+}
+
+//! The checksum field of \a testHeader is always computed and checked against itself.
+//! All other fields are compared to the corresponding value set in \a modelHeader
+//! if the appropriate flag is set in \a whichFields. For example, the m_address fields
+//! in \a testHeader and \a modelHeader are compared when the CMD_ADDRESS_FIELD bit
+//! is set in \a whichFields. An exception is thrown if any comparison fails.
+//!
+//! \param modelHeader The baseline header to compare against. Only those fields that
+//! have corresponding bits set in \a whichFields need to be set.
+//! \param testHeader The actual command header which is being validated.
+//! \param whichFields A bitfield used to determine which fields of the boot command
+//! header are compared. Possible values are:
+//! - CMD_TAG_FIELD
+//! - CMD_FLAGS_FIELD
+//! - CMD_ADDRESS_FIELD
+//! - CMD_COUNT_FIELD
+//! - CMD_DATA_FIELD
+//!
+//! \exception std::runtime_error Thrown if any requested validation fails.
+void EncoreBootImage::BootCommand::validateHeader(const boot_command_t * modelHeader, const boot_command_t * testHeader, unsigned whichFields)
+{
+ // compare all the fields that were requested
+ if ((whichFields & CMD_TAG_FIELD) && (testHeader->m_tag != modelHeader->m_tag))
+ {
+ throw std::runtime_error("invalid tag field");
+ }
+
+ if ((whichFields & CMD_FLAGS_FIELD) && (testHeader->m_flags != modelHeader->m_flags))
+ {
+ throw std::runtime_error("invalid flags field");
+ }
+
+ if ((whichFields & CMD_ADDRESS_FIELD) && (testHeader->m_address != modelHeader->m_address))
+ {
+ throw std::runtime_error("invalid address field");
+ }
+
+ if ((whichFields & CMD_COUNT_FIELD) && (testHeader->m_count != modelHeader->m_count))
+ {
+ throw std::runtime_error("invalid count field");
+ }
+
+ if ((whichFields & CMD_DATA_FIELD) && (testHeader->m_data != modelHeader->m_data))
+ {
+ throw std::runtime_error("invalid data field");
+ }
+
+ // calculate checksum
+ uint8_t testChecksum = calculateChecksum(*testHeader);
+ if (testChecksum != testHeader->m_checksum)
+ {
+ throw std::runtime_error("invalid checksum");
+ }
+}
+
+//! Since the NOP command has no data, this method just validates the command header.
+//! All fields except the checksum are expected to be set to 0.
+//!
+//! \param blocks Pointer to the raw data blocks.
+//! \param count Number of blocks pointed to by \a blocks.
+//! \param[out] consumed On exit, this points to the number of cipher blocks that were occupied
+//! by the command. Should be at least 1 for every command. This must not be NULL
+//! on entry!
+//!
+//! \exception std::runtime_error Thrown if header fields are invalid.
+void EncoreBootImage::NopCommand::initFromData(const cipher_block_t * blocks, unsigned count, unsigned * consumed)
+{
+ const boot_command_t model = { 0, ROM_NOP_CMD, 0, 0, 0, 0 };
+ const boot_command_t * header = reinterpret_cast<const boot_command_t *>(blocks);
+ validateHeader(&model, header, CMD_TAG_FIELD | CMD_FLAGS_FIELD | CMD_ADDRESS_FIELD | CMD_COUNT_FIELD | CMD_DATA_FIELD);
+
+ *consumed = 1;
+}
+
+//! All fields of the boot command header structure are set to 0, except
+//! for the checksum. This includes the tag field since the tag value for
+//! the #ROM_NOP_CMD is zero. And since all fields are zeroes the checksum
+//! remains the initial checksum value of 0x5a.
+void EncoreBootImage::NopCommand::fillCommandHeader(boot_command_t & header)
+{
+ header.m_tag = getTag();
+ header.m_flags = 0;
+ header.m_address = 0;
+ header.m_count = 0;
+ header.m_data = 0;
+ header.m_checksum = calculateChecksum(header); // do this last
+}
+
+void EncoreBootImage::NopCommand::debugPrint() const
+{
+ Log::log(Logger::INFO2, "\tNOOP\n");
+}
+
+//! The identifier, length, and flags fields are taken from \a section.
+//!
+//! \todo How does length get set correctly if the length is supposed to include
+//! this command?
+EncoreBootImage::TagCommand::TagCommand(const Section & section)
+{
+ m_sectionIdentifier = section.getIdentifier();
+ m_sectionLength = section.getBlockCount();
+ m_sectionFlags = section.getFlags();
+}
+
+//! \param blocks Pointer to the raw data blocks.
+//! \param count Number of blocks pointed to by \a blocks.
+//! \param[out] consumed On exit, this points to the number of cipher blocks that were occupied
+//! by the command. Should be at least 1 for every command. This must not be NULL
+//! on entry!
+//!
+//! \exception std::runtime_error Thrown if header fields are invalid.
+void EncoreBootImage::TagCommand::initFromData(const cipher_block_t * blocks, unsigned count, unsigned * consumed)
+{
+ const boot_command_t model = { 0, ROM_TAG_CMD, 0, 0, 0, 0 };
+ const boot_command_t * header = reinterpret_cast<const boot_command_t *>(blocks);
+ validateHeader(&model, header, CMD_TAG_FIELD);
+
+ // read fields from header
+ m_isLast = (ENDIAN_LITTLE_TO_HOST_U16(header->m_flags) & ROM_LAST_TAG) != 0;
+ m_sectionIdentifier = ENDIAN_LITTLE_TO_HOST_U32(header->m_address);
+ m_sectionLength = ENDIAN_LITTLE_TO_HOST_U32(header->m_count);
+ m_sectionFlags = ENDIAN_LITTLE_TO_HOST_U32(header->m_data);
+
+ *consumed = 1;
+}
+
+//! This method currently assumes that the next tag command will come immediately
+//! after the data for this section.
+void EncoreBootImage::TagCommand::fillCommandHeader(boot_command_t & header)
+{
+ header.m_tag = getTag();
+ header.m_flags = ENDIAN_HOST_TO_LITTLE_U16(m_isLast ? ROM_LAST_TAG : 0);
+ header.m_address = ENDIAN_HOST_TO_LITTLE_U32(m_sectionIdentifier);
+ header.m_count = ENDIAN_HOST_TO_LITTLE_U32(m_sectionLength);
+ header.m_data = ENDIAN_HOST_TO_LITTLE_U32(m_sectionFlags);
+ header.m_checksum = calculateChecksum(header); // do this last
+}
+
+void EncoreBootImage::TagCommand::debugPrint() const
+{
+ Log::log(Logger::INFO2, " BTAG | sec=0x%08x | cnt=0x%08x | flg=0x%08x\n", m_sectionIdentifier, m_sectionLength, m_sectionFlags);
+}
+
+//! All fields are set to zero.
+//!
+EncoreBootImage::LoadCommand::LoadCommand()
+: BootCommand(), m_data(), m_padCount(0), m_length(0), m_address(0), m_loadDCD(false)
+{
+ fillPadding();
+}
+
+EncoreBootImage::LoadCommand::LoadCommand(uint32_t address, const uint8_t * data, uint32_t length)
+: BootCommand(), m_data(), m_padCount(0), m_length(0), m_address(address), m_loadDCD(false)
+{
+ fillPadding();
+ setData(data, length);
+}
+
+//! \param blocks Pointer to the raw data blocks.
+//! \param count Number of blocks pointed to by \a blocks.
+//! \param[out] consumed On exit, this points to the number of cipher blocks that were occupied
+//! by the command. Should be at least 1 for every command. This must not be NULL
+//! on entry!
+//!
+//! \exception std::runtime_error This exception is thrown if the actual CRC of the load
+//! data does not match the CRC stored in the command header. Also thrown if the
+//! \a count parameter is less than the number of data blocks needed for the length
+//! specified in the command header or if header fields are invalid.
+void EncoreBootImage::LoadCommand::initFromData(const cipher_block_t * blocks, unsigned count, unsigned * consumed)
+{
+ // check static fields
+ const boot_command_t model = { 0, ROM_LOAD_CMD, 0, 0, 0, 0 };
+ const boot_command_t * header = reinterpret_cast<const boot_command_t *>(blocks);
+ validateHeader(&model, header, CMD_TAG_FIELD);
+
+ // read fields from header
+ m_address = ENDIAN_LITTLE_TO_HOST_U32(header->m_address);
+ m_length = ENDIAN_LITTLE_TO_HOST_U32(header->m_count);
+ unsigned crc = ENDIAN_LITTLE_TO_HOST_U32(header->m_data);
+ unsigned dataBlockCount = numberOfCipherBlocks(m_length);
+ m_padCount = sizeOfPaddingForCipherBlocks(dataBlockCount);
+ m_loadDCD = (ENDIAN_LITTLE_TO_HOST_U16(header->m_flags) & ROM_LOAD_DCD) != 0;
+
+ // make sure there are enough blocks
+ if (count - 1 < dataBlockCount)
+ {
+ throw std::runtime_error("not enough cipher blocks for load data");
+ }
+
+ // copy data
+ setData(reinterpret_cast<const uint8_t *>(blocks + 1), m_length);
+
+ // copy padding
+ if (m_padCount)
+ {
+ const uint8_t * firstPadByte = reinterpret_cast<const uint8_t *> (blocks + (1 + dataBlockCount)) - m_padCount;
+ memcpy(m_padding, firstPadByte, m_padCount);
+ }
+
+ // check CRC
+ uint32_t actualCRC = calculateCRC();
+ if (actualCRC != crc)
+ {
+ throw std::runtime_error("load data failed CRC check");
+ }
+
+ *consumed = 1 + dataBlockCount;
+}
+
+//! The only thing unique in the load command header is the
+//! #elftosb::EncoreBootImage::boot_command_t::m_data. It contains a CRC-32 over the
+//! load data, plus any bytes of padding in the last data cipher block.
+void EncoreBootImage::LoadCommand::fillCommandHeader(boot_command_t & header)
+{
+ header.m_tag = getTag();
+ header.m_flags = ENDIAN_HOST_TO_LITTLE_U16(m_loadDCD ? ROM_LOAD_DCD : 0);
+ header.m_address = ENDIAN_HOST_TO_LITTLE_U32(m_address);
+ header.m_count = ENDIAN_HOST_TO_LITTLE_U32(m_length);
+ header.m_data = ENDIAN_HOST_TO_LITTLE_U32(calculateCRC());
+
+ // do this last
+ header.m_checksum = calculateChecksum(header);
+}
+
+//! A CRC-32 is calculated over the load data, including any pad bytes
+//! that are required in the last data cipher block. Including the
+//! pad bytes in the CRC makes it vastly easier for the ROM to calculate
+//! the CRC for validation.
+uint32_t EncoreBootImage::LoadCommand::calculateCRC() const
+{
+ uint32_t result;
+ CRC32 crc;
+ crc.update(m_data, m_length);
+ if (m_padCount)
+ {
+ // include random padding in the CRC
+ crc.update(m_padding, m_padCount);
+ }
+ crc.truncatedFinal(reinterpret_cast<uint8_t*>(&result), sizeof(result));
+
+ return result;
+}
+
+//! A local copy of the load data is made. This copy will be disposed of when this object
+//! is destroyed. This means the caller is free to deallocate \a data after this call
+//! returns. It also means the caller can pass a pointer into the middle of a buffer for
+//! \a data and not worry about ownership issues.
+void EncoreBootImage::LoadCommand::setData(const uint8_t * data, uint32_t length)
+{
+ assert(data);
+ assert(length);
+
+ uint8_t * dataCopy = new uint8_t[length];
+ memcpy(dataCopy, data, length);
+
+ m_data = dataCopy;
+ m_length = length;
+
+ m_padCount = sizeOfPaddingForCipherBlocks(m_length);
+}
+
+//! \return The number of cipher blocks required to hold the load data,
+//! rounded up as necessary.
+unsigned EncoreBootImage::LoadCommand::getDataBlockCount() const
+{
+ // round up to the next cipher block
+ return numberOfCipherBlocks(m_length);
+}
+
+//! Up to \a maxCount data blocks are copied into the buffer pointed to by
+//! the \a data argument. This is only a request for \a maxCount blocks.
+//! A return value of 0 indicates that no more blocks are available. The
+//! index of the first block to copy is held in the \a offset argument.
+//! If there are pad bytes needed to fill out the last data block, they
+//! will be filled with random data in order to add to the "whiteness" of
+//! the data on both sides of encryption.
+//!
+//! \param offset Starting block number to copy. Zero means the first available block.
+//! \param maxCount Up to this number of blocks may be copied into \a data. Must be 1 or greater.
+//! \param data Buffer for outgoing data blocks. Must have enough room to hold
+//! \a maxCount blocks.
+//!
+//! \return The number of data blocks copied into \a data.
+//! \retval 0 No more blocks are available and nothing was written to \a data.
+//!
+//! \exception std::out_of_range Thrown when offset is invalid.
+//!
+//! \todo fill pad bytes with random bytes
+unsigned EncoreBootImage::LoadCommand::getDataBlocks(unsigned offset, unsigned maxCount, cipher_block_t * data)
+{
+ assert(data);
+ assert(maxCount != 0);
+
+ uint32_t blockCount = getDataBlockCount();
+
+ // check offset
+ if (offset >= blockCount)
+ {
+ throw std::out_of_range("invalid offset");
+ }
+
+ // figure out how many blocks to return
+ unsigned resultBlocks = blockCount - offset;
+ if (resultBlocks > maxCount)
+ {
+ resultBlocks = maxCount;
+
+ // exclude last block if there is padding
+ if (m_padCount && (offset != blockCount - 1) && (offset + resultBlocks == blockCount))
+ {
+ resultBlocks--;
+ }
+ }
+
+ // if there are pad bytes, handle the last block specially
+ if (m_padCount && offset == blockCount - 1)
+ {
+ // copy the remainder of the load data into the first part of the result block
+ unsigned remainderLength = sizeof(cipher_block_t) - m_padCount;
+ memcpy(data, &m_data[sizeof(cipher_block_t) * offset], remainderLength);
+
+ // copy pad bytes we previously generated into the last part of the result block
+ // data is a cipher block pointer, so indexing is done on cipher block
+ // boundaries, thus we need a byte pointer to index properly
+ uint8_t * bytePtr = reinterpret_cast<uint8_t*>(data);
+ memcpy(bytePtr + remainderLength, &m_padding, m_padCount);
+ }
+ else
+ {
+ memcpy(data, &m_data[sizeof(cipher_block_t) * offset], sizeof(cipher_block_t) * resultBlocks);
+ }
+
+ return resultBlocks;
+}
+
+//! Fills #m_padding with random bytes that may be used to fill up the last data
+//! cipher block.
+void EncoreBootImage::LoadCommand::fillPadding()
+{
+ RandomNumberGenerator rng;
+ rng.generateBlock(m_padding, sizeof(m_padding));
+}
+
+void EncoreBootImage::LoadCommand::debugPrint() const
+{
+ Log::log(Logger::INFO2, " LOAD | adr=0x%08x | len=0x%08x | crc=0x%08x | flg=0x%08x\n", m_address, m_length, calculateCRC(), m_loadDCD ? ROM_LOAD_DCD : 0);
+}
+
+//! The pattern, address, and count are all initialized to zero, and the pattern
+//! size is set to a word.
+EncoreBootImage::FillCommand::FillCommand()
+: BootCommand(), m_address(0), m_count(0), m_pattern(0)
+{
+}
+
+//! \param blocks Pointer to the raw data blocks.
+//! \param count Number of blocks pointed to by \a blocks.
+//! \param[out] consumed On exit, this points to the number of cipher blocks that were occupied
+//! by the command. Should be at least 1 for every command. This must not be NULL
+//! on entry!
+//!
+//! \exception std::runtime_error Thrown if header fields are invalid.
+void EncoreBootImage::FillCommand::initFromData(const cipher_block_t * blocks, unsigned count, unsigned * consumed)
+{
+ // check static fields
+ const boot_command_t model = { 0, ROM_FILL_CMD, 0, 0, 0, 0 };
+ const boot_command_t * header = reinterpret_cast<const boot_command_t *>(blocks);
+ validateHeader(&model, header, CMD_TAG_FIELD | CMD_FLAGS_FIELD);
+
+ // read fields from header
+ m_address = ENDIAN_LITTLE_TO_HOST_U32(header->m_address);
+ m_count = ENDIAN_LITTLE_TO_HOST_U32(header->m_count);
+ m_pattern = ENDIAN_LITTLE_TO_HOST_U32(header->m_data);
+
+ *consumed = 1;
+}
+
+void EncoreBootImage::FillCommand::fillCommandHeader(boot_command_t & header)
+{
+ header.m_tag = getTag();
+ header.m_flags = 0;
+ header.m_address = ENDIAN_HOST_TO_LITTLE_U32(m_address);
+ header.m_count = ENDIAN_HOST_TO_LITTLE_U32(m_count);
+ header.m_data = ENDIAN_HOST_TO_LITTLE_U32(m_pattern);
+ header.m_checksum = calculateChecksum(header); // do this last
+}
+
+//! Extends the pattern across 32 bits.
+//!
+void EncoreBootImage::FillCommand::setPattern(uint8_t pattern)
+{
+ m_pattern = (pattern << 24) | (pattern << 16) | (pattern << 8) | pattern;
+}
+
+//! Extends the pattern across 32 bits.
+//!
+void EncoreBootImage::FillCommand::setPattern(uint16_t pattern)
+{
+ m_pattern = (pattern << 16) | pattern;
+}
+
+void EncoreBootImage::FillCommand::setPattern(uint32_t pattern)
+{
+ m_pattern = pattern;
+}
+
+void EncoreBootImage::FillCommand::debugPrint() const
+{
+ Log::log(Logger::INFO2, " FILL | adr=0x%08x | len=0x%08x | ptn=0x%08x\n", m_address, m_count, m_pattern);
+}
+
+//! \param blocks Pointer to the raw data blocks.
+//! \param count Number of blocks pointed to by \a blocks.
+//! \param[out] consumed On exit, this points to the number of cipher blocks that were occupied
+//! by the command. Should be at least 1 for every command. This must not be NULL
+//! on entry!
+//!
+//! \exception std::runtime_error Thrown if header fields are invalid.
+void EncoreBootImage::ModeCommand::initFromData(const cipher_block_t * blocks, unsigned count, unsigned * consumed)
+{
+ // check static fields
+ const boot_command_t model = { 0, ROM_MODE_CMD, 0, 0, 0, 0 };
+ const boot_command_t * header = reinterpret_cast<const boot_command_t *>(blocks);
+ validateHeader(&model, header, CMD_TAG_FIELD | CMD_FLAGS_FIELD | CMD_ADDRESS_FIELD | CMD_COUNT_FIELD);
+
+ // read fields from header
+ m_mode = ENDIAN_LITTLE_TO_HOST_U32(header->m_data);
+
+ *consumed = 1;
+}
+
+void EncoreBootImage::ModeCommand::fillCommandHeader(boot_command_t & header)
+{
+ header.m_tag = getTag();
+ header.m_flags = 0;
+ header.m_address = 0;
+ header.m_count = 0;
+ header.m_data = ENDIAN_HOST_TO_LITTLE_U32(m_mode);
+ header.m_checksum = calculateChecksum(header); // do this last
+}
+
+void EncoreBootImage::ModeCommand::debugPrint() const
+{
+ Log::log(Logger::INFO2, " MODE | mod=0x%08x\n", m_mode);
+}
+
+//! \param blocks Pointer to the raw data blocks.
+//! \param count Number of blocks pointed to by \a blocks.
+//! \param[out] consumed On exit, this points to the number of cipher blocks that were occupied
+//! by the command. Should be at least 1 for every command. This must not be NULL
+//! on entry!
+//!
+//! \exception std::runtime_error Thrown if header fields are invalid.
+void EncoreBootImage::JumpCommand::initFromData(const cipher_block_t * blocks, unsigned count, unsigned * consumed)
+{
+ // check static fields
+ const boot_command_t model = { 0, getTag(), 0, 0, 0, 0 };
+ const boot_command_t * header = reinterpret_cast<const boot_command_t *>(blocks);
+ validateHeader(&model, header, CMD_TAG_FIELD | CMD_COUNT_FIELD);
+
+ // read fields from header
+ m_address = ENDIAN_LITTLE_TO_HOST_U32(header->m_address);
+ m_argument = ENDIAN_LITTLE_TO_HOST_U32(header->m_data);
+ m_isHAB = (ENDIAN_LITTLE_TO_HOST_U16(header->m_flags) & ROM_HAB_EXEC) != 0;
+
+ *consumed = 1;
+}
+
+void EncoreBootImage::JumpCommand::fillCommandHeader(boot_command_t & header)
+{
+ header.m_tag = getTag();
+ header.m_flags = ENDIAN_HOST_TO_LITTLE_U16(m_isHAB ? ROM_HAB_EXEC : 0);
+ header.m_address = ENDIAN_HOST_TO_LITTLE_U32(m_address);
+ header.m_count = 0;
+ header.m_data = ENDIAN_HOST_TO_LITTLE_U32(m_argument);
+ header.m_checksum = calculateChecksum(header); // do this last
+}
+
+void EncoreBootImage::JumpCommand::debugPrint() const
+{
+ Log::log(Logger::INFO2, " JUMP | adr=0x%08x | arg=0x%08x | flg=0x%08x\n", m_address, m_argument, m_isHAB ? ROM_HAB_EXEC : 0);
+}
+
+void EncoreBootImage::CallCommand::debugPrint() const
+{
+ Log::log(Logger::INFO2, " CALL | adr=0x%08x | arg=0x%08x | flg=0x%08x\n", m_address, m_argument, m_isHAB ? ROM_HAB_EXEC : 0);
+}
+
+//! Only if the section has been assigned a boot image owner object will this
+//! method be able to fill in the #section_header_t::m_offset field. If no
+//! boot image has been set the offset will be set to 0.
+void EncoreBootImage::Section::fillSectionHeader(section_header_t & header)
+{
+ header.m_tag = getIdentifier();
+ header.m_offset = 0;
+ header.m_length = ENDIAN_HOST_TO_LITTLE_U32(getBlockCount());
+ header.m_flags = ENDIAN_HOST_TO_LITTLE_U32(getFlags());
+
+ // if we're attached to an image, we can compute our real offset
+ if (m_image)
+ {
+ header.m_offset = ENDIAN_HOST_TO_LITTLE_U32(m_image->getSectionOffset(this));
+ }
+}
+
+//! The alignment will never be less than 16, since that is the size of the
+//! cipher block which is the basic unit of the boot image format. If an
+//! alignment less than 16 is set it will be ignored.
+//!
+//! \param alignment Alignment in bytes for this section. Must be a power of two.
+//! Ignored if less than 16.
+void EncoreBootImage::Section::setAlignment(unsigned alignment)
+{
+ if (alignment > BOOT_IMAGE_MINIMUM_SECTION_ALIGNMENT)
+ {
+ m_alignment = alignment;
+ }
+}
+
+//! This method calculates the number of padding blocks that need to be inserted
+//! from a given offset for the section to be properly aligned. The value returned
+//! is the number of padding blocks that should be inserted starting just after
+//! \a offset to align the first cipher block of the section contents. The section's
+//! boot tag is \i not taken into account by this method, so the caller must
+//! deal with that herself.
+//!
+//! \param offset Start offset in cipher blocks (not bytes).
+//!
+//! \return A number of cipher blocks of padding to insert.
+unsigned EncoreBootImage::Section::getPadBlockCountForOffset(unsigned offset)
+{
+ // convert alignment from byte to block alignment
+ unsigned blockAlignment = m_alignment >> 4;
+
+ unsigned nextAlignmentOffset = (offset + blockAlignment - 1) / blockAlignment * blockAlignment;
+
+ return nextAlignmentOffset - offset;
+}
+
+EncoreBootImage::BootSection::~BootSection()
+{
+ deleteCommands();
+}
+
+void EncoreBootImage::BootSection::deleteCommands()
+{
+ // dispose of all sections
+ iterator_t it = begin();
+ for (; it != end(); ++it)
+ {
+ delete *it;
+ }
+}
+
+//! Always returns at least 1 for the required tag command.
+//!
+unsigned EncoreBootImage::BootSection::getBlockCount() const
+{
+ unsigned count = 0;
+
+ const_iterator_t it = begin();
+ for (; it != end(); ++it)
+ {
+ count += (*it)->getBlockCount();
+ }
+
+ return count;
+}
+
+//! Up to \a maxCount cipher blocks are copied into the buffer pointed to by
+//! the \a data argument. A return value of 0 indicates that
+//! no more blocks are available. The index of the first block to copy is
+//! held in the \a offset argument.
+//!
+//! \param offset Starting block number to copy. Zero means the first available block.
+//! \param maxCount Up to this number of blocks may be copied into \a data.
+//! \param data Buffer for outgoing cipher blocks. Must have enough room to hold
+//! \a maxCount blocks.
+//!
+//! \return The number of cipher blocks copied into \a data.
+//! \retval 0 No more blocks are available and nothing was written to \a data.
+unsigned EncoreBootImage::BootSection::getBlocks(unsigned offset, unsigned maxCount, cipher_block_t * data)
+{
+ assert(data);
+ assert(maxCount >= 1);
+
+ unsigned currentOffset = 0;
+ unsigned readCount = maxCount;
+
+ iterator_t it = begin();
+ for (; it != end(); ++it)
+ {
+ BootCommand * command = *it;
+ unsigned commandBlocks = command->getBlockCount();
+
+ // this should never be false!
+ assert(offset >= currentOffset);
+
+ // skip forward until we hit the requested offset
+ if (offset >= currentOffset + commandBlocks)
+ {
+ currentOffset += commandBlocks;
+ continue;
+ }
+
+ // read from this command
+ unsigned commandOffset = offset - currentOffset;
+ unsigned commandRemaining = commandBlocks - commandOffset;
+ if (readCount > commandRemaining)
+ {
+ readCount = commandRemaining;
+ }
+ return command->getBlocks(commandOffset, readCount, data);
+ }
+
+ return 0;
+}
+
+//! The entire contents of the section must be in memory, pointed to by \a blocks.
+//! Any commands that had previously been added to the section are disposed of.
+//!
+//! \param blocks Pointer to the section contents.
+//! \param count Number of blocks pointed to by \a blocks.
+//!
+//! \exception std::runtime_error Thrown if a boot command cannot be created from
+//! the cipher block stream.
+void EncoreBootImage::BootSection::fillFromData(const cipher_block_t * blocks, unsigned count)
+{
+ // start with an empty slate
+ deleteCommands();
+
+ const cipher_block_t * currentBlock = blocks;
+ unsigned remaining = count;
+ while (remaining)
+ {
+ // try to create a command from the next cipher block. the number of
+ // blocks the command used up is returned in consumed.
+ unsigned consumed;
+ BootCommand * command = BootCommand::createFromData(currentBlock, remaining, &consumed);
+ if (!command)
+ {
+ throw std::runtime_error("invalid boot section data");
+ }
+
+ addCommand(command);
+
+ // update loop counters
+ remaining -= consumed;
+ currentBlock += consumed;
+ }
+}
+
+void EncoreBootImage::BootSection::debugPrint() const
+{
+ Log::log(Logger::INFO2, "Boot Section 0x%08x:\n", m_identifier);
+
+ const_iterator_t it = begin();
+ for (; it != end(); ++it)
+ {
+ const BootCommand * command = *it;
+ command->debugPrint();
+ }
+}
+
+//! A copy is made of \a data. Any previously assigned data is disposed of.
+//!
+void EncoreBootImage::DataSection::setData(const uint8_t * data, unsigned length)
+{
+ m_data = new uint8_t[length];
+ memcpy(m_data.get(), data, length);
+ m_length = length;
+}
+
+//! The section takes ownership of \a data and will dispose of it using the
+//! array delete operator upon its destruction.
+void EncoreBootImage::DataSection::setDataNoCopy(const uint8_t * data, unsigned length)
+{
+ m_data = data;
+ m_length = length;
+}
+
+unsigned EncoreBootImage::DataSection::getBlockCount() const
+{
+ return numberOfCipherBlocks(m_length);
+}
+
+unsigned EncoreBootImage::DataSection::getBlocks(unsigned offset, unsigned maxCount, cipher_block_t * data)
+{
+ assert(data);
+ assert(maxCount != 0);
+
+ unsigned blockCount = getBlockCount();
+ unsigned padCount = sizeOfPaddingForCipherBlocks(m_length);
+
+ // check offset
+ if (offset >= blockCount)
+ {
+ throw std::out_of_range("invalid offset");
+ }
+
+ // figure out how many blocks to return
+ unsigned resultBlocks = blockCount - offset;
+ if (resultBlocks > maxCount)
+ {
+ resultBlocks = maxCount;
+
+ // exclude last block if there is padding
+ if (padCount && (offset != blockCount - 1) && (offset + resultBlocks == blockCount))
+ {
+ resultBlocks--;
+ }
+ }
+
+ // if there are pad bytes, handle the last block specially
+ if (padCount && offset == blockCount - 1)
+ {
+ // copy the remainder of the load data into the first part of the result block
+ unsigned remainderLength = sizeof(cipher_block_t) - padCount;
+ memcpy(data, &m_data[sizeOfCipherBlocks(offset)], remainderLength);
+
+ // set pad bytes to zeroes.
+ // data is a cipher block pointer, so indexing is done on cipher block
+ // boundaries, thus we need a byte pointer to index properly
+ uint8_t * bytePtr = reinterpret_cast<uint8_t*>(data);
+ memset(bytePtr + remainderLength, 0, padCount);
+ }
+ else
+ {
+ memcpy(data, &m_data[sizeOfCipherBlocks(offset)], sizeOfCipherBlocks(resultBlocks));
+ }
+
+ return resultBlocks;
+}
+
+void EncoreBootImage::DataSection::debugPrint() const
+{
+ Log::log(Logger::INFO2, "Data Section 0x%08x: (%d bytes, %d blocks)\n", m_identifier, m_length, getBlockCount());
+}
+
--- /dev/null
+/*
+ * File: EncoreBootImage.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_EncoreBootImage_h_)
+#define _EncoreBootImage_h_
+
+#include <list>
+#include <vector>
+#include <string>
+#include <iostream>
+#include <fstream>
+#include <string.h>
+#include "BootImage.h"
+#include "rijndael.h"
+#include "smart_ptr.h"
+#include "AESKey.h"
+#include "StExecutableImage.h"
+
+namespace elftosb
+{
+
+//! An AES-128 cipher block is 16 bytes.
+typedef uint8_t cipher_block_t[16];
+
+//! A SHA-1 digest is 160 bits, or 20 bytes.
+typedef uint8_t sha1_digest_t[20];
+
+//! Unique identifier type for a section.
+typedef uint32_t section_id_t;
+
+//! Utility to return the byte length of a number of cipher blocks.
+inline size_t sizeOfCipherBlocks(unsigned count) { return sizeof(cipher_block_t) * count; }
+
+//! Utility to return the number of cipher blocks required to hold an object
+//! that is \a s bytes long.
+inline size_t numberOfCipherBlocks(size_t s) { return (s + sizeof(cipher_block_t) - 1) / sizeof(cipher_block_t); }
+
+//! Utility to calculate the byte length for the cipher blocks required to hold
+//! and object that is \a bytes long.
+inline size_t sizeInCipherBlocks(size_t s) { return (unsigned)sizeOfCipherBlocks(numberOfCipherBlocks(s)); }
+
+//! Utility to return the number of bytes of padding required to fill out
+//! the last cipher block in a set of cipher blocks large enough to hold
+//! an object that is \a s bytes large. The result may be 0 if \a s is
+//! an even multiple of the cipher block size.
+inline size_t sizeOfPaddingForCipherBlocks(size_t s) { return sizeInCipherBlocks(s) - s; }
+
+/*!
+ * \brief Class to manage Encore boot image files.
+ *
+ * Initially this class will only support generation of boot images, but
+ * its design will facilitate the addition of the ability to read an
+ * image and examine its contents.
+ *
+ * A boot image is composed of the following regions:
+ * - Header
+ * - Section table
+ * - Key dictionary
+ * - Section data
+ * - Authentication
+ *
+ * Multiple sections are within a boot image are fully supported. Two general types
+ * of sections are supported with this class. Bootable sections, represented by the
+ * EncoreBootImage::BootSection class, contain a sequence of commands to be
+ * interpreted by the boot ROM. Data sections are represented by the
+ * EncoreBootImage::DataSection class and can contain any arbitrary data.
+ *
+ * An image can either be encrypted or unencrypted. The image uses a session key,
+ * or DEK (data encryption key), and the key dictionary to support any number of keys
+ * using a single image. The header and section table are always unencrypted even
+ * in encrypted images. This allows host utilities to access the individual
+ * sections without needing to have access to an encryption key.
+ *
+ * To construct a boot image, first create an instance of EncoreBootImage. Then
+ * create instances of the EncoreBootImage::BootSection or EncoreBootImage::DataSection
+ * for each of the sections in the image. For bootable sections, create and add
+ * the desired boot command objects. These are all subclasses of
+ * EncoreBootImage::BootCommand.
+ *
+ * If the boot image is to be encrypted, you need to add keys, which are instances
+ * of the AES128Key class. If no keys are added, the entire boot image will be unencrypted.
+ *
+ * When the image is fully constructed, it can be written to any std::ostream with
+ * a call to writeToStream(). The same image can be written to streams any
+ * number of times.
+ */
+class EncoreBootImage : public BootImage
+{
+public:
+ //! \brief Flag constants for the m_flags field of #elftosb::EncoreBootImage::boot_image_header_t.
+ enum
+ {
+ ROM_DISPLAY_PROGRESS = (1 << 0), //!< Print progress reports.
+ ROM_VERBOSE_PROGRESS = (1 << 1) //!< Progress reports are verbose.
+ };
+
+ enum {
+ ROM_IMAGE_HEADER_SIGNATURE = 'STMP', //!< Signature in #elftosb::EncoreBootImage::boot_image_header_t::m_signature.
+ ROM_IMAGE_HEADER_SIGNATURE2 = 'sgtl', //!< Value for #elftosb::EncoreBootImage::boot_image_header_t::m_signature2;
+ ROM_BOOT_IMAGE_MAJOR_VERSION = 1, //!< Current boot image major version.
+ ROM_BOOT_IMAGE_MINOR_VERSION = 1 //!< Current boot image minor version.
+ };
+
+ enum {
+ //! Minimum alignment for a section is 16 bytes.
+ BOOT_IMAGE_MINIMUM_SECTION_ALIGNMENT = sizeof(cipher_block_t)
+ };
+
+// All of these structures are packed to byte alignment in order to match
+// the structure on disk.
+#pragma pack(1)
+
+ //! \brief Header for the entire boot image.
+ //!
+ //! Fields of this header are arranged so that those used by the bootloader ROM all come
+ //! first. They are also set up so that all fields are not split across cipher block
+ //! boundaries. The fields not used by the bootloader are not subject to this
+ //! restraint.
+ //!
+ //! Image header size is always a round number of cipher blocks. The same also applies to
+ //! the boot image itself. The padding, held in #elftosb::EncoreBootImage::boot_image_header_t::m_padding0
+ //! and #elftosb::EncoreBootImage::boot_image_header_t::m_padding1 is filled with random bytes.
+ //!
+ //! The DEK dictionary, section table, and each section data region must all start on
+ //! cipher block boundaries.
+ //!
+ //! This header is not encrypted in the image file.
+ //!
+ //! The m_digest field contains a SHA-1 digest of the fields of the header that follow it.
+ //! It is the first field in the header so it doesn't change position or split the header
+ //! in two if fields are added to the header.
+ struct boot_image_header_t
+ {
+ union
+ {
+ sha1_digest_t m_digest; //!< SHA-1 digest of image header. Also used as the crypto IV.
+ struct
+ {
+ cipher_block_t m_iv; //!< The first 16 bytes of the digest form the initialization vector.
+ uint8_t m_extra[4]; //!< The leftover top four bytes of the SHA-1 digest.
+ };
+ };
+ uint8_t m_signature[4]; //!< 'STMP', see #ROM_IMAGE_HEADER_SIGNATURE.
+ uint8_t m_majorVersion; //!< Major version for the image format, see #ROM_BOOT_IMAGE_MAJOR_VERSION.
+ uint8_t m_minorVersion; //!< Minor version of the boot image format, see #ROM_BOOT_IMAGE_MINOR_VERSION.
+ uint16_t m_flags; //!< Flags or options associated with the entire image.
+ uint32_t m_imageBlocks; //!< Size of entire image in blocks.
+ uint32_t m_firstBootTagBlock; //!< Offset from start of file to the first boot tag, in blocks.
+ section_id_t m_firstBootableSectionID; //!< ID of section to start booting from.
+ uint16_t m_keyCount; //!< Number of entries in DEK dictionary.
+ uint16_t m_keyDictionaryBlock; //!< Starting block number for the key dictionary.
+ uint16_t m_headerBlocks; //!< Size of this header, including this size word, in blocks.
+ uint16_t m_sectionCount; //!< Number of section headers in this table.
+ uint16_t m_sectionHeaderSize; //!< Size in blocks of a section header.
+ uint8_t m_padding0[2]; //!< Padding to align #m_timestamp to long word.
+ uint8_t m_signature2[4]; //!< Second signature to distinguish this .sb format from the 36xx format, see #ROM_IMAGE_HEADER_SIGNATURE2.
+ uint64_t m_timestamp; //!< Timestamp when image was generated in microseconds since 1-1-2000.
+ version_t m_productVersion; //!< Product version.
+ version_t m_componentVersion; //!< Component version.
+ uint16_t m_driveTag; //!< Drive tag for the system drive which this boot image belongs to.
+ uint8_t m_padding1[6]; //!< Padding to round up to next cipher block.
+ };
+
+ //! \brief Entry in #elftosb::EncoreBootImage::dek_dictionary_t.
+ //!
+ //! The m_dek field in each entry is encrypted using the KEK with the m_iv field from
+ //! the image header as the IV.
+ struct dek_dictionary_entry_t
+ {
+ cipher_block_t m_mac; //!< CBC-MAC of the header.
+ aes128_key_t m_dek; //!< AES-128 key with which the image payload is encrypted.
+ };
+
+ //! \brief The DEK dictionary always follows the image header, in the next cipher block.
+ struct dek_dictionary_t
+ {
+ dek_dictionary_entry_t m_entries[1];
+ };
+
+ //! \brief Section flags constants for the m_flags field of #elftosb::EncoreBootImage::section_header_t.
+ enum
+ {
+ ROM_SECTION_BOOTABLE = (1 << 0), //!< The section contains bootloader commands.
+ ROM_SECTION_CLEARTEXT = (1 << 1) //!< The section is unencrypted. Applies only if the rest of the boot image is encrypted.
+ };
+
+ //! \brief Information about each section, held in the section table.
+ //! \see section_table_t
+ struct section_header_t
+ {
+ uint32_t m_tag; //!< Unique identifier for this section. High bit must be zero.
+ uint32_t m_offset; //!< Offset to section data from start of image in blocks.
+ uint32_t m_length; //!< Size of section data in blocks.
+ uint32_t m_flags; //!< Section flags.
+ };
+
+ //! \brief An index of all sections within the boot image.
+ //!
+ //! The section table will be padded so that its length is divisible by 16 (if necessary).
+ //! Actually, each entry is padded to be a round number of cipher blocks, which
+ //! automatically makes this true for the entire table.
+ //!
+ //! Sections are ordered as they appear in this table, but are identified by the
+ //! #elftosb::EncoreBootImage::section_header_t::m_tag.
+ //!
+ //! The data for each section in encrypted separately with the DEK in CBC mode using
+ //! m_iv for the IV. This allows the ROM to jump to any given section without needing
+ //! to read the previous cipher block. In addition, the data for each section is
+ //! prefixed with a "boot tag", which describes the section which follows it. Boot
+ //! tags are the same format as a boot command, and are described by the
+ //! EncoreBootImage::TagCommand class.
+ //!
+ //! The section table starts immediately after the image header, coming before the
+ //! key dictionary (if present). The section table is not encrypted.
+ struct section_table_t
+ {
+ section_header_t m_sections[1]; //!< The table entries.
+ };
+
+ //! \brief Structure for a Piano bootloader command.
+ //!
+ //! Each command is composed of a fixed length header of 16 bytes. This happens to be
+ //! the size of a cipher block. Most commands will only require the header.
+ //!
+ //! But some commands, i.e. the "load data" command, may require additional arbitrary
+ //! amounts of data. This data is packed into the N cipher blocks that immediately
+ //! follow the command header. If the length of the data is not divisible by 16, then
+ //! random (not zero!) pad bytes will be added.
+ struct boot_command_t
+ {
+ uint8_t m_checksum; //!< Simple checksum over other command fields.
+ uint8_t m_tag; //!< Tag telling which command this is.
+ uint16_t m_flags; //!< Flags for this command.
+ uint32_t m_address; //!< Target address.
+ uint32_t m_count; //!< Number of bytes on which to operate.
+ uint32_t m_data; //!< Additional data used by certain commands.
+ };
+
+#pragma pack()
+
+ //! \brief Bootloader command tag constants.
+ enum
+ {
+ ROM_NOP_CMD = 0x00, //!< A no-op command.
+ ROM_TAG_CMD = 0x01, //!< Section tag command.
+ ROM_LOAD_CMD = 0x02, //!< Load data command.
+ ROM_FILL_CMD = 0x03, //!< Pattern fill command.
+ ROM_JUMP_CMD = 0x04, //!< Jump to address command.
+ ROM_CALL_CMD = 0x05, //!< Call function command.
+ ROM_MODE_CMD = 0x06 //!< Change boot mode command.
+ };
+
+ //! \brief Flag field constants for #ROM_TAG_CMD.
+ enum
+ {
+ ROM_LAST_TAG = (1 << 0) //!< This tag command is the last one in the image.
+ };
+
+ //! \brief Flag field constants for #ROM_LOAD_CMD.
+ enum
+ {
+ ROM_LOAD_DCD = (1 << 0) //!< Execute the DCD after loading completes.
+ };
+
+ //! \brief Flag field constants for #ROM_FILL_CMD.
+ enum
+ {
+ ROM_FILL_BYTE = 0, //!< Fill with byte sized pattern.
+ ROM_FILL_HALF_WORD = 1, //!< Fill with half-word sized pattern.
+ ROM_FILL_WORD = 2 //!< Fill with word sized pattern.
+ };
+
+ //! brief Flag field constants for #ROM_JUMP_CMD and #ROM_CALL_CMD.
+ enum
+ {
+ ROM_HAB_EXEC = (1 << 0) //!< Changes jump or call command to a HAB jump or call.
+ };
+
+public:
+ // Forward declaration.
+ class Section;
+
+ /*!
+ * \brief Base class for objects that produce cipher blocks.
+ */
+ class CipherBlockGenerator
+ {
+ public:
+
+ //! \name Cipher blocks
+ //@{
+ //! \brief Returns the total number of cipher blocks.
+ //!
+ //! The default implementation returns 0, indicating that no blocks are
+ //! available.
+ virtual unsigned getBlockCount() const { return 0; }
+
+ //! \brief Returns the contents of up to \a maxCount cipher blocks.
+ //!
+ //! Up to \a maxCount cipher blocks are copied into the buffer pointed to by
+ //! the \a data argument. This is only a request for \a maxCount blocks,
+ //! the subclass implementation of this method is free to return any number
+ //! of blocks from 0 up to \a maxCount. A return value of 0 indicates that
+ //! no more blocks are available. The index of the first block to copy is
+ //! held in the \a offset argument.
+ //!
+ //! \param offset Starting block number to copy. Zero means the first available block.
+ //! \param maxCount Up to this number of blocks may be copied into \a data. Must be 1 or greater.
+ //! \param data Buffer for outgoing cipher blocks. Must have enough room to hold
+ //! \a maxCount blocks.
+ //!
+ //! \return The number of cipher blocks copied into \a data.
+ //! \retval 0 No more blocks are available and nothing was written to \a data.
+ virtual unsigned getBlocks(unsigned offset, unsigned maxCount, cipher_block_t * data) { return 0; }
+ //@}
+
+ //! \brief Print out a string representation of the object.
+ virtual void debugPrint() const {}
+ };
+
+ /*!
+ * \brief Abstract base class for all bootloader commands.
+ */
+ class BootCommand : public CipherBlockGenerator
+ {
+ public:
+ //! \brief Creates the correct subclass of BootCommand for the given raw data.
+ static BootCommand * createFromData(const cipher_block_t * blocks, unsigned count, unsigned * consumed);
+
+ public:
+ //! \brief Default constructor.
+ BootCommand() : CipherBlockGenerator() {}
+
+ //! \brief Destructor.
+ virtual ~BootCommand() {}
+
+ //! \brief Read the command contents from raw data.
+ //!
+ //! The subclass implementations should validate the contents of the command, including
+ //! the fields of the command header in the first block. It should be assumed that
+ //! only the tag field was examined to determine which subclass of BootCommand
+ //! should be created.
+ //!
+ //! \param blocks Pointer to the raw data blocks.
+ //! \param count Number of blocks pointed to by \a blocks.
+ //! \param[out] consumed On exit, this points to the number of cipher blocks that were occupied
+ //! by the command. Should be at least 1 for every command. This must not be NULL
+ //! on entry!
+ virtual void initFromData(const cipher_block_t * blocks, unsigned count, unsigned * consumed)=0;
+
+ //! \name Header
+ //@{
+ //! \brief Pure virtual method to return the tag value for this command.
+ virtual uint8_t getTag() const = 0;
+
+ //! \brief Pure virtual method to construct the header for this boot command.
+ virtual void fillCommandHeader(boot_command_t & header) = 0;
+
+ //! \brief Calculates the checksum for the given command header.
+ virtual uint8_t calculateChecksum(const boot_command_t & header);
+ //@}
+
+ //! \name Cipher blocks
+ //@{
+ //! \brief Returns the total number of cipher blocks.
+ virtual unsigned getBlockCount() const;
+
+ //! \brief Returns the contents of up to \a maxCount cipher blocks.
+ virtual unsigned getBlocks(unsigned offset, unsigned maxCount, cipher_block_t * data);
+ //@}
+
+ //! \name Data blocks
+ //@{
+ //! \brief Returns the number of data cipher blocks that follow this command.
+ //!
+ //! The default implementation returns 0, indicating that no data blocks are
+ //! available.
+ virtual unsigned getDataBlockCount() const { return 0; }
+
+ //! \brief Returns the contents of up to \a maxCount data blocks.
+ //!
+ //! Up to \a maxCount data blocks are copied into the buffer pointed to by
+ //! the \a data argument. This is only a request for \a maxCount blocks,
+ //! the subclass implementation of this method is free to return any number
+ //! of blocks from 0 up to \a maxCount. A return value of 0 indicates that
+ //! no more blocks are available. The index of the first block to copy is
+ //! held in the \a offset argument.
+ //!
+ //! \param offset Starting block number to copy. Zero means the first available block.
+ //! \param maxCount Up to this number of blocks may be copied into \a data. Must be 1 or greater.
+ //! \param data Buffer for outgoing data blocks. Must have enough room to hold
+ //! \a maxCount blocks.
+ //!
+ //! \return The number of data blocks copied into \a data.
+ //! \retval 0 No more blocks are available and nothing was written to \a data.
+ virtual unsigned getDataBlocks(unsigned offset, unsigned maxCount, cipher_block_t * data) { return 0; }
+ //@}
+
+ protected:
+ //! The flag bit values for the \a whichFields parameter of validateHeader().
+ enum
+ {
+ CMD_TAG_FIELD = 1,
+ CMD_FLAGS_FIELD = 2,
+ CMD_ADDRESS_FIELD = 4,
+ CMD_COUNT_FIELD = 8,
+ CMD_DATA_FIELD = 16
+ };
+
+ //! \brief
+ void validateHeader(const boot_command_t * modelHeader, const boot_command_t * testHeader, unsigned whichFields);
+ };
+
+ /*!
+ * \brief No operation bootloader command.
+ */
+ class NopCommand : public BootCommand
+ {
+ public:
+ //! \brief Default constructor.
+ NopCommand() : BootCommand() {}
+
+ //! \brief Read the command contents from raw data.
+ virtual void initFromData(const cipher_block_t * blocks, unsigned count, unsigned * consumed);
+
+ //! \name Header
+ //@{
+ //! \brief Returns the tag value for this command.
+ virtual uint8_t getTag() const { return ROM_NOP_CMD; }
+
+ //! \brief Constructs the header for this boot command.
+ virtual void fillCommandHeader(boot_command_t & header);
+ //@}
+
+ //! \brief Print out a string representation of the object.
+ virtual void debugPrint() const;
+ };
+
+ /*!
+ * \brief Section tag bootloader command.
+ */
+ class TagCommand : public BootCommand
+ {
+ public:
+ //! \brief Default constructor.
+ TagCommand() : BootCommand() {}
+
+ //! \brief Constructor taking a section object.
+ TagCommand(const Section & section);
+
+ //! \brief Read the command contents from raw data.
+ virtual void initFromData(const cipher_block_t * blocks, unsigned count, unsigned * consumed);
+
+ //! \name Header
+ //@{
+ //! \brief Returns the tag value for this command.
+ virtual uint8_t getTag() const { return ROM_TAG_CMD; }
+
+ //! \brief Constructs the header for this boot command.
+ virtual void fillCommandHeader(boot_command_t & header);
+ //@}
+
+ //! \name Field accessors
+ //@{
+ inline void setSectionIdentifier(uint32_t identifier) { m_sectionIdentifier = identifier; }
+ inline void setSectionLength(uint32_t length) { m_sectionLength = length; }
+ inline void setSectionFlags(uint32_t flags) { m_sectionFlags = flags; }
+ inline void setLast(bool isLast) { m_isLast = isLast; }
+ //@}
+
+ //! \brief Print out a string representation of the object.
+ virtual void debugPrint() const;
+
+ protected:
+ uint32_t m_sectionIdentifier; //!< Unique identifier for the section containing this command.
+ uint32_t m_sectionLength; //!< Number of cipher blocks this section occupies.
+ uint32_t m_sectionFlags; //!< Flags pertaining to this section.
+ bool m_isLast; //!< Is this the last tag command?
+ };
+
+ /*!
+ * \brief Load data bootloader command.
+ */
+ class LoadCommand : public BootCommand
+ {
+ public:
+ //! \brief Default constructor.
+ LoadCommand();
+
+ //! \brief Constructor.
+ LoadCommand(uint32_t address, const uint8_t * data, uint32_t length);
+
+ //! \brief Read the command contents from raw data.
+ virtual void initFromData(const cipher_block_t * blocks, unsigned count, unsigned * consumed);
+
+ //! \name Header
+ //@{
+ //! \brief Returns the tag value for this command.
+ virtual uint8_t getTag() const { return ROM_LOAD_CMD; }
+
+ //! \brief Constructs the header for this boot command.
+ virtual void fillCommandHeader(boot_command_t & header);
+
+ //! \brief Sets the load-dcd flag.
+ inline void setDCD(bool isDCD) { m_loadDCD = isDCD; }
+ //@}
+
+ //! \name Address
+ //@{
+ inline void setLoadAddress(uint32_t address) { m_address = address; }
+ inline uint32_t getLoadAddress() const { return m_address; }
+ //@}
+
+ //! \name Load data
+ //@{
+ //! \brief Set the data for the command to load.
+ void setData(const uint8_t * data, uint32_t length);
+
+ inline uint8_t * getData() { return m_data; }
+ inline const uint8_t * getData() const { return m_data; }
+ inline uint32_t getLength() const { return m_length; }
+ //@}
+
+ //! \name Data blocks
+ //@{
+ //! \brief Returns the number of data cipher blocks that follow this command.
+ virtual unsigned getDataBlockCount() const;
+
+ //! \brief Returns the contents of up to \a maxCount data blocks.
+ virtual unsigned getDataBlocks(unsigned offset, unsigned maxCount, cipher_block_t * data);
+ //@}
+
+ //! \brief Print out a string representation of the object.
+ virtual void debugPrint() const;
+
+ protected:
+ smart_array_ptr<uint8_t> m_data; //!< Pointer to data to load.
+ uint8_t m_padding[15]; //!< Up to 15 pad bytes may be required.
+ unsigned m_padCount; //!< Number of pad bytes.
+ uint32_t m_length; //!< Number of bytes to load.
+ uint32_t m_address; //!< Address to which data will be loaded.
+ bool m_loadDCD; //!< Whether to execute the DCD after loading.
+
+ void fillPadding();
+ uint32_t calculateCRC() const;
+ };
+
+ /*!
+ * \brief Pattern fill bootloader command.
+ */
+ class FillCommand : public BootCommand
+ {
+ public:
+ //! \brief Default constructor.
+ FillCommand();
+
+ //! \brief Read the command contents from raw data.
+ virtual void initFromData(const cipher_block_t * blocks, unsigned count, unsigned * consumed);
+
+ //! \name Header
+ //@{
+ //! \brief Returns the tag value for this command.
+ virtual uint8_t getTag() const { return ROM_FILL_CMD; }
+
+ //! \brief Constructs the header for this boot command.
+ virtual void fillCommandHeader(boot_command_t & header);
+ //@}
+
+ //! \name Address range
+ //@{
+ inline void setAddress(uint32_t address) { m_address = address; };
+ inline uint32_t getAddress() const { return m_address; }
+
+ inline void setFillCount(uint32_t count) { m_count = count; }
+ inline uint32_t getFillCount() const { return m_count; }
+ //@}
+
+ //! \name Pattern
+ //@{
+ void setPattern(uint8_t pattern);
+ void setPattern(uint16_t pattern);
+ void setPattern(uint32_t pattern);
+
+ inline uint32_t getPattern() const { return m_pattern; }
+ //@}
+
+ //! \brief Print out a string representation of the object.
+ virtual void debugPrint() const;
+
+ protected:
+ uint32_t m_address; //!< Fill start address.
+ uint32_t m_count; //!< Number of bytes to fill.
+ uint32_t m_pattern; //!< Fill pattern.
+ };
+
+ /*!
+ * \brief Change boot mode bootloader command.
+ */
+ class ModeCommand : public BootCommand
+ {
+ public:
+ //! \brief Default constructor.
+ ModeCommand() : BootCommand(), m_mode(0) {}
+
+ //! \brief Read the command contents from raw data.
+ virtual void initFromData(const cipher_block_t * blocks, unsigned count, unsigned * consumed);
+
+ //! \name Header
+ //@{
+ //! \brief Returns the tag value for this command.
+ virtual uint8_t getTag() const { return ROM_MODE_CMD; }
+
+ //! \brief Constructs the header for this boot command.
+ virtual void fillCommandHeader(boot_command_t & header);
+ //@}
+
+ //! \name Boot mode
+ //@{
+ inline void setBootMode(uint32_t mode) { m_mode = mode; }
+ inline uint32_t getBootMode() const { return m_mode; }
+ //@}
+
+ //! \brief Print out a string representation of the object.
+ virtual void debugPrint() const;
+
+ protected:
+ uint32_t m_mode; //!< New boot mode.
+ };
+
+ /*!
+ * \brief Jump to address bootloader command.
+ */
+ class JumpCommand : public BootCommand
+ {
+ public:
+ //! \brief Default constructor.
+ JumpCommand() : BootCommand(), m_address(0), m_argument(0), m_isHAB(false), m_ivtSize(0) {}
+
+ //! \brief Read the command contents from raw data.
+ virtual void initFromData(const cipher_block_t * blocks, unsigned count, unsigned * consumed);
+
+ //! \name Header
+ //@{
+ //! \brief Returns the tag value for this command.
+ virtual uint8_t getTag() const { return ROM_JUMP_CMD; }
+
+ //! \brief Constructs the header for this boot command.
+ virtual void fillCommandHeader(boot_command_t & header);
+ //@}
+
+ //! \name Accessors
+ //@{
+ inline void setAddress(uint32_t address) { m_address = address; }
+ inline uint32_t getAddress() const { return m_address; }
+
+ inline void setArgument(uint32_t argument) { m_argument = argument; }
+ inline uint32_t getArgument() const { return m_argument; }
+
+ inline void setIsHAB(bool isHAB) { m_isHAB = isHAB; }
+ inline bool isHAB() const { return m_isHAB; }
+
+ inline void setIVTSize(uint32_t ivtSize) { m_ivtSize = ivtSize; }
+ inline uint32_t getIVTSize() const { return m_ivtSize; }
+ //@}
+
+ //! \brief Print out a string representation of the object.
+ virtual void debugPrint() const;
+
+ protected:
+ uint32_t m_address; //!< Address of the code to execute.
+ uint32_t m_argument; //!< Sole argument to pass to code.
+ bool m_isHAB; //!< Whether this jump/call is a special HAB jump/call. When this flag is set, m_address becomes the IVT address and m_ivtSize is the IVT size.
+ uint32_t m_ivtSize; //!< Size of the IVT for a HAB jump/call.
+ };
+
+ /*!
+ * \brief Call function bootloader command.
+ */
+ class CallCommand : public JumpCommand
+ {
+ public:
+ //! \brief Default constructor.
+ CallCommand() : JumpCommand() {}
+
+ //! \brief Returns the tag value for this command.
+ virtual uint8_t getTag() const { return ROM_CALL_CMD; }
+
+ //! \brief Print out a string representation of the object.
+ virtual void debugPrint() const;
+ };
+
+ /*!
+ * \brief Base class for a section of an Encore boot image.
+ *
+ * Provides methods to manage the unique identifier that all sections have, and
+ * to set the boot image object which owns the section. There are also virtual
+ * methods to get header flags and fill in the header used in the section
+ * table. Subclasses must implement at least fillSectionHeader().
+ */
+ class Section : public CipherBlockGenerator
+ {
+ public:
+ //! \brief Default constructor.
+ Section() : CipherBlockGenerator(), m_identifier(0), m_image(0), m_alignment(BOOT_IMAGE_MINIMUM_SECTION_ALIGNMENT), m_flags(0), m_leaveUnencrypted(false) {}
+
+ //! \brief Constructor taking the unique identifier for this section.
+ Section(uint32_t identifier) : CipherBlockGenerator(), m_identifier(identifier), m_image(0), m_alignment(BOOT_IMAGE_MINIMUM_SECTION_ALIGNMENT), m_flags(0), m_leaveUnencrypted(false) {}
+
+ //! \name Identifier
+ //@{
+ inline void setIdentifier(uint32_t identifier) { m_identifier = identifier; }
+ inline uint32_t getIdentifier() const { return m_identifier; }
+ //@}
+
+ //! \name Header
+ //@{
+ //! \brief Sets explicit flags for this section.
+ virtual void setFlags(uint32_t flags) { m_flags = flags; }
+
+ //! \brief Returns the flags for this section.
+ //!
+ //! The return value consists of the flags set with setFlags() possibly or-ed
+ //! with #ROM_SECTION_CLEARTEXT if the section has been set to be left
+ //! unencrypted.
+ virtual uint32_t getFlags() const { return m_flags | ( m_leaveUnencrypted ? ROM_SECTION_CLEARTEXT : 0); }
+
+ //! \brief Pure virtual method to construct the header for this section.
+ virtual void fillSectionHeader(section_header_t & header);
+ //@}
+
+ //! \name Owner image
+ //@{
+ //! \brief Called when the section is added to an image.
+ void setImage(EncoreBootImage * image) { m_image = image; }
+
+ //! \brief Returns a pointer to the image that this section belongs to.
+ EncoreBootImage * getImage() const { return m_image; }
+ //@}
+
+ //! \name Alignment
+ //@{
+ //! \brief Sets the required alignment in the output file for this section.
+ void setAlignment(unsigned alignment);
+
+ //! \brief Returns the current alignment, the minimum of which will be 16.
+ unsigned getAlignment() const { return m_alignment; }
+
+ //! \brief Computes padding amount for alignment requirement.
+ unsigned getPadBlockCountForOffset(unsigned offset);
+ //@}
+
+ //! \name Leave unencrypted flag
+ //@{
+ //! \brief Sets whether the section will be left unencrypted.
+ void setLeaveUnencrypted(unsigned flag) { m_leaveUnencrypted = flag; }
+
+ //! \brief Returns true if the section will remain unencrypted.
+ bool getLeaveUnencrypted() const { return m_leaveUnencrypted; }
+ //@}
+
+ protected:
+ uint32_t m_identifier; //!< Unique identifier for this section.
+ EncoreBootImage * m_image; //!< The image to which this section belongs.
+ unsigned m_alignment; //!< Alignment requirement for the start of this section.
+ uint32_t m_flags; //!< Section flags set by the user.
+ bool m_leaveUnencrypted; //!< Set to true to prevent this section from being encrypted.
+ };
+
+ /*!
+ * \brief A bootable section of an Encore boot image.
+ */
+ class BootSection : public Section
+ {
+ public:
+ typedef std::list<BootCommand*> command_list_t;
+ typedef command_list_t::iterator iterator_t;
+ typedef command_list_t::const_iterator const_iterator_t;
+
+ public:
+ //! \brief Default constructor.
+ BootSection() : Section() {}
+
+ //! \brief Constructor taking the unique identifier for this section.
+ BootSection(uint32_t identifier) : Section(identifier) {}
+
+ //! \brief Destructor.
+ virtual ~BootSection();
+
+ //! \brief Load the section from raw data.
+ virtual void fillFromData(const cipher_block_t * blocks, unsigned count);
+
+ //! \name Header
+ //@{
+ //! \brief Returns the flags for this section.
+ virtual uint32_t getFlags() const { return Section::getFlags() | ROM_SECTION_BOOTABLE; }
+ //@}
+
+ //! \name Commands
+ //@{
+ //! \brief Append a new command to the section.
+ //!
+ //! The section takes ownership of the command and will delete it when
+ //! the section is destroyed.
+ void addCommand(BootCommand * command) { m_commands.push_back(command); }
+
+ //! \brief Returns the number of commands in this section, excluding the tag command.
+ unsigned getCommandCount() const { return (unsigned)m_commands.size(); }
+
+ iterator_t begin() { return m_commands.begin(); }
+ iterator_t end() { return m_commands.end(); }
+
+ const_iterator_t begin() const { return m_commands.begin(); }
+ const_iterator_t end() const { return m_commands.end(); }
+ //@}
+
+ //! \name Cipher blocks
+ //@{
+ //! \brief Returns the total number of cipher blocks occupied by this section.
+ virtual unsigned getBlockCount() const;
+
+ //! \brief Returns the contents of up to \a maxCount cipher blocks.
+ virtual unsigned getBlocks(unsigned offset, unsigned maxCount, cipher_block_t * data);
+ //@}
+
+ //! \brief Print out a string representation of the object.
+ virtual void debugPrint() const;
+
+ protected:
+ command_list_t m_commands; //!< Commands held in this section.
+
+ protected:
+ //! \brief Remove all commands from the section.
+ void deleteCommands();
+ };
+
+ /*!
+ * \brief A non-bootable section of an Encore boot image.
+ */
+ class DataSection : public Section
+ {
+ public:
+ //! \brief Default constructor.
+ DataSection() : Section(), m_data(), m_length(0) {}
+
+ //! \brief Constructor taking the unique identifier for this section.
+ DataSection(uint32_t identifier) : Section(identifier), m_data(), m_length(0) {}
+
+ //! \brief Set the data section's contents.
+ void setData(const uint8_t * data, unsigned length);
+
+ //! \brief Set the data section's contents without copying \a data.
+ void setDataNoCopy(const uint8_t * data, unsigned length);
+
+ //! \name Cipher blocks
+ //@{
+ //! \brief Returns the total number of cipher blocks occupied by this section.
+ virtual unsigned getBlockCount() const;
+
+ //! \brief Returns the contents of up to \a maxCount cipher blocks.
+ virtual unsigned getBlocks(unsigned offset, unsigned maxCount, cipher_block_t * data);
+ //@}
+
+ //! \brief Print out a string representation of the object.
+ virtual void debugPrint() const;
+
+ protected:
+ smart_array_ptr<uint8_t> m_data; //!< The section's contents.
+ unsigned m_length; //!< Number of bytes of data.
+ };
+
+public:
+ typedef std::list<Section*> section_list_t; //!< List of image sections.
+ typedef section_list_t::iterator section_iterator_t; //!< Iterator over sections.
+ typedef section_list_t::const_iterator const_section_iterator_t; //!< Const iterator over sections.
+
+ typedef std::vector<AES128Key> key_list_t; //!< List of KEKs.
+ typedef key_list_t::iterator key_iterator_t; //!< Iterator over KEKs.
+ typedef key_list_t::const_iterator const_key_iterator_t; //!< Const iterator over KEKs.
+
+public:
+ //! \brief Default constructor.
+ EncoreBootImage();
+
+ //! \brief Destructor.
+ virtual ~EncoreBootImage();
+
+ //! \name Sections
+ //@{
+ void addSection(Section * newSection);
+ inline unsigned sectionCount() const { return (unsigned)m_sections.size(); }
+
+ inline section_iterator_t beginSection() { return m_sections.begin(); }
+ inline section_iterator_t endSection() { return m_sections.end(); }
+ inline const_section_iterator_t beginSection() const { return m_sections.begin(); }
+ inline const_section_iterator_t endSection() const { return m_sections.end(); }
+
+ section_iterator_t findSection(Section * section);
+
+ //! \brief Calculates the starting block number for the given section.
+ uint32_t getSectionOffset(Section * section);
+ //@}
+
+ //! \name Encryption keys
+ //@{
+ inline void addKey(const AES128Key & newKey) { m_keys.push_back(newKey); }
+ inline unsigned keyCount() const { return (unsigned)m_keys.size(); }
+
+ inline key_iterator_t beginKeys() { return m_keys.begin(); }
+ inline key_iterator_t endKeys() { return m_keys.end(); }
+ inline const_key_iterator_t beginKeys() const { return m_keys.begin(); }
+ inline const_key_iterator_t endKeys() const { return m_keys.end(); }
+
+ //! \brief The image is encrypted if there is at least one key.
+ inline bool isEncrypted() const { return m_keys.size() != 0; }
+ //@}
+
+ //! \name Versions
+ //@{
+ virtual void setProductVersion(const version_t & version);
+ virtual void setComponentVersion(const version_t & version);
+ //@}
+
+ //! \name Flags
+ //@{
+ inline void setFlags(uint16_t flags) { m_headerFlags = flags; }
+ inline uint32_t getFlags() const { return m_headerFlags; }
+ //@}
+
+ //! \brief Specify the drive tag to be set in the output file header.
+ virtual void setDriveTag(uint16_t tag) { m_driveTag = tag; }
+
+ //! \brief Calculates the total number of cipher blocks the image consumes.
+ uint32_t getImageSize();
+
+ //! \brief Returns the preferred ".sb" extension for Encore boot images.
+ virtual std::string getFileExtension() const { return ".sb"; }
+
+ //! \name Output
+ //@{
+ //! \brief Write the boot image to an output stream.
+ virtual void writeToStream(std::ostream & stream);
+ //@}
+
+ //! \brief Print out a string representation of the object.
+ virtual void debugPrint() const;
+
+protected:
+ uint16_t m_headerFlags; //!< Flags field in the boot image header.
+ version_t m_productVersion; //!< Product version.
+ version_t m_componentVersion; //!< Component version.
+ uint16_t m_driveTag; //!< System drive tag for this boot image.
+ section_list_t m_sections; //!< Sections contained in this image.
+ key_list_t m_keys; //!< List of key encryption keys. If empty, the image is unencrypted.
+ AES128Key m_sessionKey; //!< Session key we're using.
+
+ void prepareImageHeader(boot_image_header_t & header);
+ uint64_t getTimestamp();
+ Section * findFirstBootableSection();
+ unsigned getPadBlockCountForSection(Section * section, unsigned offset);
+};
+
+}; // namespace elftosb
+
+#endif // _EncoreBootImage_h_
--- /dev/null
+/*
+ * File: EndianUtilities.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_EndianUtilities_h_)
+#define _EndianUtilities_h_
+
+//! \name Swap macros
+//! These macros always swap the data.
+//@{
+
+//! Byte swap 16-bit value.
+#define _BYTESWAP16(value) \
+ (((((uint16_t)value)<<8) & 0xFF00) | \
+ ((((uint16_t)value)>>8) & 0x00FF))
+
+//! Byte swap 32-bit value.
+#define _BYTESWAP32(value) \
+ (((((uint32_t)value)<<24) & 0xFF000000) | \
+ ((((uint32_t)value)<< 8) & 0x00FF0000) | \
+ ((((uint32_t)value)>> 8) & 0x0000FF00) | \
+ ((((uint32_t)value)>>24) & 0x000000FF))
+
+//! Byte swap 64-bit value.
+#define _BYTESWAP64(value) \
+ (((((uint64_t)value)<<56) & 0xFF00000000000000ULL) | \
+ ((((uint64_t)value)<<40) & 0x00FF000000000000ULL) | \
+ ((((uint64_t)value)<<24) & 0x0000FF0000000000ULL) | \
+ ((((uint64_t)value)<< 8) & 0x000000FF00000000ULL) | \
+ ((((uint64_t)value)>> 8) & 0x00000000FF000000ULL) | \
+ ((((uint64_t)value)>>24) & 0x0000000000FF0000ULL) | \
+ ((((uint64_t)value)>>40) & 0x000000000000FF00ULL) | \
+ ((((uint64_t)value)>>56) & 0x00000000000000FFULL))
+
+//@}
+
+//! \name Inline swap functions
+//@{
+
+inline uint16_t _swap_u16(uint16_t value) { return _BYTESWAP16(value); }
+inline int16_t _swap_s16(int16_t value) { return (int16_t)_BYTESWAP16((uint16_t)value); }
+
+inline uint32_t _swap_u32(uint32_t value) { return _BYTESWAP32(value); }
+inline int32_t _swap_s32(int32_t value) { return (int32_t)_BYTESWAP32((uint32_t)value); }
+
+inline uint64_t _swap_u64(uint64_t value) { return _BYTESWAP64(value); }
+inline int64_t _swap_s64(int64_t value) { return (uint64_t)_BYTESWAP64((uint64_t)value); }
+
+//@}
+
+#if defined(__LITTLE_ENDIAN__)
+
+ /* little endian host */
+
+ #define ENDIAN_BIG_TO_HOST_U16(value) (_swap_u16(value))
+ #define ENDIAN_HOST_TO_BIG_U16(value) (_swap_u16(value))
+
+ #define ENDIAN_BIG_TO_HOST_S16(value) (_swap_s16(value))
+ #define ENDIAN_HOST_TO_BIG_S16(value) (_swap_s16(value))
+
+ #define ENDIAN_BIG_TO_HOST_U32(value) (_swap_u32(value))
+ #define ENDIAN_HOST_TO_BIG_U32(value) (_swap_u32(value))
+
+ #define ENDIAN_BIG_TO_HOST_S32(value) (_swap_s32(value))
+ #define ENDIAN_HOST_TO_BIG_S32(value) (_swap_s32(value))
+
+ #define ENDIAN_BIG_TO_HOST_U64(value) (_swap_u64(value))
+ #define ENDIAN_HOST_TO_BIG_U64(value) (_swap_u64(value))
+
+ #define ENDIAN_BIG_TO_HOST_S64(value) (_swap_s64(value))
+ #define ENDIAN_HOST_TO_BIG_S64(value) (_swap_s64(value))
+
+ /* no-ops */
+
+ #define ENDIAN_LITTLE_TO_HOST_U16(value) (value)
+ #define ENDIAN_HOST_TO_LITTLE_U16(value) (value)
+
+ #define ENDIAN_LITTLE_TO_HOST_S16(value) (value)
+ #define ENDIAN_HOST_TO_LITTLE_S16(value) (value)
+
+ #define ENDIAN_LITTLE_TO_HOST_U32(value) (value)
+ #define ENDIAN_HOST_TO_LITTLE_U32(value) (value)
+
+ #define ENDIAN_LITTLE_TO_HOST_S32(value) (value)
+ #define ENDIAN_HOST_TO_LITTLE_S32(value) (value)
+
+ #define ENDIAN_LITTLE_TO_HOST_U64(value) (value)
+ #define ENDIAN_HOST_TO_LITTLE_U64(value) (value)
+
+ #define ENDIAN_LITTLE_TO_HOST_S64(value) (value)
+ #define ENDIAN_HOST_TO_LITTLE_S64(value) (value)
+
+#elif defined(__BIG_ENDIAN__)
+
+ /* big endian host */
+
+ #define ENDIAN_LITTLE_TO_HOST_U16(value) (_swap_u16(value))
+ #define ENDIAN_HOST_TO_LITTLE_U16(value) (_swap_u16(value))
+
+ #define ENDIAN_LITTLE_TO_HOST_S16(value) (_swap_s16(value))
+ #define ENDIAN_HOST_TO_LITTLE_S16(value) (_swap_s16(value))
+
+ #define ENDIAN_LITTLE_TO_HOST_U32(value) (_swap_u32(value))
+ #define ENDIAN_HOST_TO_LITTLE_U32(value) (_swap_u32(value))
+
+ #define ENDIAN_LITTLE_TO_HOST_S32(value) (_swap_s32(value))
+ #define ENDIAN_HOST_TO_LITTLE_S32(value) (_swap_s32(value))
+
+ #define ENDIAN_LITTLE_TO_HOST_U64(value) (_swap_u64(value))
+ #define ENDIAN_HOST_TO_LITTLE_U64(value) (_swap_u64(value))
+
+ #define ENDIAN_LITTLE_TO_HOST_S64(value) (_swap_s64(value))
+ #define ENDIAN_HOST_TO_LITTLE_S64(value) (_swap_s64(value))
+
+ /* no-ops */
+
+ #define ENDIAN_BIG_TO_HOST_U16(value) (value)
+ #define ENDIAN_HOST_TO_BIG_U16(value) (value)
+
+ #define ENDIAN_BIG_TO_HOST_S16(value) (value)
+ #define ENDIAN_HOST_TO_BIG_S16(value) (value)
+
+ #define ENDIAN_BIG_TO_HOST_U32(value) (value)
+ #define ENDIAN_HOST_TO_BIG_U32(value) (value)
+
+ #define ENDIAN_BIG_TO_HOST_S32(value) (value)
+ #define ENDIAN_HOST_TO_BIG_S32(value) (value)
+
+ #define ENDIAN_BIG_TO_HOST_U64(value) (value)
+ #define ENDIAN_HOST_TO_BIG_U64(value) (value)
+
+ #define ENDIAN_BIG_TO_HOST_S64(value) (value)
+ #define ENDIAN_HOST_TO_BIG_S64(value) (value)
+
+#endif
+
+
+
+#endif // _EndianUtilities_h_
--- /dev/null
+/*
+ * File: EvalContext.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "EvalContext.h"
+#include <stdexcept>
+#include "format_string.h"
+
+using namespace elftosb;
+
+EvalContext::EvalContext()
+: m_sourcesManager(0)
+{
+}
+
+EvalContext::~EvalContext()
+{
+}
+
+bool EvalContext::isVariableDefined(const std::string & name)
+{
+ variable_map_t::const_iterator it = m_variables.find(name);
+ return it != m_variables.end();
+}
+
+uint32_t EvalContext::getVariableValue(const std::string & name)
+{
+ variable_map_t::const_iterator it = m_variables.find(name);
+ if (it == m_variables.end())
+ {
+ throw std::runtime_error(format_string("undefined variable '%s'", name.c_str()));
+ }
+
+ return it->second.m_value;
+}
+
+int_size_t EvalContext::getVariableSize(const std::string & name)
+{
+ variable_map_t::const_iterator it = m_variables.find(name);
+ if (it == m_variables.end())
+ {
+ throw std::runtime_error(format_string("undefined variable '%s'", name.c_str()));
+ }
+
+ return it->second.m_size;
+}
+
+void EvalContext::setVariable(const std::string & name, uint32_t value, int_size_t size)
+{
+ // check if var is locked
+ variable_map_t::const_iterator it = m_variables.find(name);
+ if (it != m_variables.end() && it->second.m_isLocked)
+ {
+ return;
+ }
+
+ // set var info
+ variable_info_t info;
+ info.m_value = value;
+ info.m_size = size;
+ info.m_isLocked = false;
+ m_variables[name] = info;
+}
+
+bool EvalContext::isVariableLocked(const std::string & name)
+{
+ variable_map_t::const_iterator it = m_variables.find(name);
+ if (it == m_variables.end())
+ {
+ throw std::runtime_error(format_string("undefined variable '%s'", name.c_str()));
+ }
+
+ return it->second.m_isLocked;
+}
+
+void EvalContext::lockVariable(const std::string & name)
+{
+ variable_map_t::iterator it = m_variables.find(name);
+ if (it == m_variables.end())
+ {
+ throw std::runtime_error(format_string("undefined variable '%s'", name.c_str()));
+ }
+
+ it->second.m_isLocked = true;
+}
+
+void EvalContext::unlockVariable(const std::string & name)
+{
+ variable_map_t::iterator it = m_variables.find(name);
+ if (it == m_variables.end())
+ {
+ throw std::runtime_error("undefined variable");
+ }
+
+ it->second.m_isLocked = false;
+}
+
+void EvalContext::dump()
+{
+ variable_map_t::iterator it = m_variables.begin();
+ for (; it != m_variables.end(); ++it)
+ {
+ variable_info_t & info = it->second;
+ const char * lockedString = info.m_isLocked ? "locked" : "unlocked";
+ printf("%s = %u:%d (%s)\n", it->first.c_str(), info.m_value, (int)info.m_size, lockedString);
+ }
+}
+
--- /dev/null
+/*
+ * File: EvalContext.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_EvalContext_h_)
+#define _EvalContext_h_
+
+#include <map>
+#include <string>
+#include "Value.h"
+#include "int_size.h"
+#include "SourceFile.h"
+
+namespace elftosb
+{
+
+/*!
+ * \brief Context for evaluating AST tree and expressions.
+ *
+ * Keeps a map of variable names to integer values. Each integer value has a
+ * size attribute in addition to the actual value. Variables can be locked, which
+ * simply means that they cannot be assigned a new value.
+ *
+ * \todo Switch to using Value instances to keep track of variable values. This
+ * will enable variables to have string values, for one.
+ */
+class EvalContext
+{
+public:
+ /*!
+ * \brief Abstract interface for a manager of source files.
+ */
+ class SourceFileManager
+ {
+ public:
+ //! \brief Returns true if a source file with the name \a name exists.
+ virtual bool hasSourceFile(const std::string & name)=0;
+
+ //! \brief Gets the requested source file.
+ virtual SourceFile * getSourceFile(const std::string & name)=0;
+
+ //! \brief Returns the default source file, or NULL if none is set.
+ virtual SourceFile * getDefaultSourceFile()=0;
+ };
+
+public:
+ //! \brief Constructor.
+ EvalContext();
+
+ //! \brief Destructor.
+ virtual ~EvalContext();
+
+ //! \name Source file manager
+ //@{
+ //! \brief
+ void setSourceFileManager(SourceFileManager * manager) { m_sourcesManager = manager; }
+
+ //! \brief
+ SourceFileManager * getSourceFileManager() { return m_sourcesManager; }
+ //@}
+
+ //! \name Variables
+ //@{
+ bool isVariableDefined(const std::string & name);
+ uint32_t getVariableValue(const std::string & name);
+ int_size_t getVariableSize(const std::string & name);
+ void setVariable(const std::string & name, uint32_t value, int_size_t size=kWordSize);
+ //@}
+
+ //! \name Locks
+ //@{
+ bool isVariableLocked(const std::string & name);
+ void lockVariable(const std::string & name);
+ void unlockVariable(const std::string & name);
+ //@}
+
+ void dump();
+
+protected:
+ //! Information about a variable's value.
+ struct variable_info_t
+ {
+ uint32_t m_value; //!< Variable value.
+ int_size_t m_size; //!< Number of bytes
+ bool m_isLocked; //!< Can this variable's value be changed?
+ };
+
+ //! Type to maps between the variable name and its info.
+ typedef std::map<std::string, variable_info_t> variable_map_t;
+
+ SourceFileManager * m_sourcesManager; //!< Interface to source file manager.
+ variable_map_t m_variables; //!< Map of variables to their final values.
+};
+
+}; // namespace elftosb
+
+#endif // _EvalContext_h_
--- /dev/null
+/*
+ * File: ExcludesListMatcher.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "ExcludesListMatcher.h"
+
+using namespace elftosb;
+
+ExcludesListMatcher::ExcludesListMatcher()
+: GlobMatcher("")
+{
+}
+
+ExcludesListMatcher::~ExcludesListMatcher()
+{
+}
+
+//! \param isInclude True if this pattern is an include, false if it is an exclude.
+//! \param pattern String containing the glob pattern.
+void ExcludesListMatcher::addPattern(bool isInclude, const std::string & pattern)
+{
+ glob_list_item_t item;
+ item.m_isInclude = isInclude;
+ item.m_glob = pattern;
+
+ // add to end of list
+ m_patterns.push_back(item);
+}
+
+//! If there are no entries in the match list, the match fails.
+//!
+//! \param testValue The string to match against the pattern list.
+//! \retval true The \a testValue argument matches.
+//! \retval false No match was made against the argument.
+bool ExcludesListMatcher::match(const std::string & testValue)
+{
+ if (!m_patterns.size())
+ {
+ return false;
+ }
+
+ // Iterate over the match list. Includes act as an OR operator, while
+ // excludes act as an AND operator.
+ bool didMatch = false;
+ bool isFirstItem = true;
+ glob_list_t::iterator it = m_patterns.begin();
+ for (; it != m_patterns.end(); ++it)
+ {
+ glob_list_item_t & item = *it;
+
+ // if this pattern is an include and it doesn't match, or
+ // if this pattern is an exclude and it does match, then the match fails
+ bool didItemMatch = globMatch(testValue.c_str(), item.m_glob.c_str());
+
+ if (item.m_isInclude)
+ {
+ // Include
+ if (isFirstItem)
+ {
+ didMatch = didItemMatch;
+ }
+ else
+ {
+ didMatch = didMatch || didItemMatch;
+ }
+ }
+ else
+ {
+ // Exclude
+ if (isFirstItem)
+ {
+ didMatch = !didItemMatch;
+ }
+ else
+ {
+ didMatch = didMatch && !didItemMatch;
+ }
+ }
+
+ isFirstItem = false;
+ }
+
+ return didMatch;
+}
+
--- /dev/null
+/*
+ * File: ExcludesListMatcher.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_ExcludesListMatcher_h_)
+#define _ExcludesListMatcher_h_
+
+#include "GlobMatcher.h"
+#include <vector>
+#include <string>
+
+namespace elftosb
+{
+
+/*!
+ * \brief Matches strings using a series of include and exclude glob patterns.
+ *
+ * This string matcher class uses a sequential, ordered list of glob patterns to
+ * determine whether a string matches. Attached to each pattern is an include/exclude
+ * action. The patterns in the list effectively form a Boolean expression. Includes
+ * act as an OR operator while excludes act as an AND NOT operator.
+ *
+ * Examples (plus prefix is include, minus prefix is exclude):
+ * - +foo: foo
+ * - -foo: !foo
+ * - +foo, +bar: foo || bar
+ * - +foo, -bar: foo && !bar
+ * - +foo, -bar, +baz: foo && !bar || baz
+ *
+ * The only reason for inheriting from GlobMatcher is so we can access the protected
+ * globMatch() method.
+ */
+class ExcludesListMatcher : public GlobMatcher
+{
+public:
+ //! \brief Default constructor.
+ ExcludesListMatcher();
+
+ //! \brief Destructor.
+ ~ExcludesListMatcher();
+
+ //! \name Pattern list
+ //@{
+ //! \brief Add one include or exclude pattern to the end of the match list.
+ void addPattern(bool isInclude, const std::string & pattern);
+ //@}
+
+ //! \brief Performs a single string match test against testValue.
+ virtual bool match(const std::string & testValue);
+
+protected:
+ //! \brief Information about one glob pattern entry in a match list.
+ struct glob_list_item_t
+ {
+ bool m_isInclude; //!< True if include, false if exclude.
+ std::string m_glob; //!< The glob pattern to match.
+ };
+
+ typedef std::vector<glob_list_item_t> glob_list_t;
+ glob_list_t m_patterns; //!< Ordered list of include and exclude patterns.
+};
+
+}; // namespace elftosb
+
+#endif // _ExcludesListMatcher_h_
--- /dev/null
+/*
+ * File: GHSSecInfo.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "GHSSecInfo.h"
+#include <stdexcept>
+#include "Logging.h"
+#include "EndianUtilities.h"
+
+//! The name of the GHS-specific section info table ELF section.
+const char * const kSecInfoSectionName = ".secinfo";
+
+using namespace elftosb;
+
+//! The ELF file passed into this constructor as the \a elf argument must remain
+//! valid for the life of this object.
+//!
+//! \param elf The ELF file parser. An assertion is raised if this is NULL.
+GHSSecInfo::GHSSecInfo(StELFFile * elf)
+: m_elf(elf), m_hasInfo(false), m_info(0), m_entryCount(0)
+{
+ assert(elf);
+
+ // look up the section. if it's not there just leave m_info and m_entryCount to 0
+ unsigned sectionIndex = m_elf->getIndexOfSectionWithName(kSecInfoSectionName);
+ if (sectionIndex == SHN_UNDEF)
+ {
+ return;
+ }
+
+ // get the section data
+ const Elf32_Shdr & secInfo = m_elf->getSectionAtIndex(sectionIndex);
+ if (secInfo.sh_type != SHT_PROGBITS)
+ {
+ // .secinfo section isn't the right type, so something is wrong
+ return;
+ }
+
+ m_hasInfo = true;
+ m_info = (ghs_secinfo_t *)m_elf->getSectionDataAtIndex(sectionIndex);
+ m_entryCount = secInfo.sh_size / sizeof(ghs_secinfo_t);
+}
+
+//! Looks up \a addr for \a length in the .secinfo array. Only if that address is in the
+//! .secinfo array does this section need to be filled. If the section is found but the
+//! length does not match the \a length argument, a message is logged at the
+//! #Logger::WARNING level.
+//!
+//! If the .secinfo section is not present in the ELF file, this method always returns
+//! true.
+//!
+//! \param addr The start address of the section to query.
+//! \param length The length of the section. If a section with a start address matching
+//! \a addr is found, its length must match \a length to be considered.
+//!
+//! \retval true The section matching \a addr and \a length was found and should be filled.
+//! True is also returned when the ELF file does not have a .secinfo section.
+//! \retval false The section was not found and should not be filled.
+bool GHSSecInfo::isSectionFilled(uint32_t addr, uint32_t length)
+{
+ if (!m_hasInfo)
+ {
+ return true;
+ }
+
+ unsigned i;
+ for (i = 0; i < m_entryCount; ++i)
+ {
+ // byte swap these values into host endianness
+ uint32_t clearAddr = ENDIAN_LITTLE_TO_HOST_U32(m_info[i].m_clearAddr);
+ uint32_t numBytesToClear = ENDIAN_LITTLE_TO_HOST_U32(m_info[i].m_numBytesToClear);
+
+ // we only consider non-zero length clear regions
+ if ((addr == clearAddr) && (numBytesToClear != 0))
+ {
+ // it is an error if the address matches but the length does not
+ if (length != numBytesToClear)
+ {
+ Log::log(Logger::WARNING, "ELF Error: Size mismatch @ sect=%u, .secinfo=%u at addr 0x%08X\n", length, numBytesToClear, addr);
+ }
+ return true;
+ }
+ }
+
+ return false;
+}
+
+//! Simply calls through to isSectionFilled(uint32_t, uint32_t) to determine
+//! if \a section should be filled.
+//!
+//! If the .secinfo section is not present in the ELF file, this method always returns
+//! true.
+bool GHSSecInfo::isSectionFilled(const Elf32_Shdr & section)
+{
+ return isSectionFilled(section.sh_addr, section.sh_size);
+}
+
--- /dev/null
+/*
+ * File: GHSSecInfo.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_GHSSecInfo_h_)
+#define _GHSSecInfo_h_
+
+#include "StELFFile.h"
+#include "smart_ptr.h"
+
+namespace elftosb
+{
+
+/*!
+ * \brief Wrapper around the GHS-specific .secinfo ELF section.
+ *
+ * ELF files produced by the Green Hills MULTI toolset will have a
+ * special .secinfo section. For the most part, this section contains
+ * a list of address
+ * ranges that should be filled by the C runtime startup code. The
+ * address ranges correspond to those of ELF sections whose type is
+ * #SHT_NOBITS. The GHS runtime uses this table instead of just filling
+ * all #SHT_NOBITS sections because the linker command file can
+ * be used to optionally not fill individual sections.
+ *
+ * The isSectionFilled() methods let calling code determine if an ELF
+ * section is found in the .secinfo table. If the section is found,
+ * then it should be filled.
+ */
+class GHSSecInfo
+{
+public:
+ //! \brief Default constructor.
+ GHSSecInfo(StELFFile * elf);
+
+ //! \brief Returns true if there is a .secinfo section present in the ELF file.
+ bool hasSecinfo() const { return m_hasInfo; }
+
+ //! \brief Determines if a section should be filled.
+ bool isSectionFilled(uint32_t addr, uint32_t length);
+
+ //! \brief Determines if \a section should be filled.
+ bool isSectionFilled(const Elf32_Shdr & section);
+
+protected:
+
+#pragma pack(1)
+
+ /*!
+ * \brief The structure of one .secinfo entry.
+ */
+ struct ghs_secinfo_t
+ {
+ uint32_t m_clearAddr; //!< Address to start filling from.
+ uint32_t m_clearValue; //!< Value to fill with.
+ uint32_t m_numBytesToClear; //!< Number of bytes to fill.
+ };
+
+#pragma pack()
+
+protected:
+ StELFFile * m_elf; //!< The parser object for our ELF file.
+ bool m_hasInfo; //!< Whether .secinfo is present in the ELF file.
+ smart_array_ptr<ghs_secinfo_t> m_info; //!< Pointer to the .secinfo entries. Will be NULL if there is no .secinfo section in the file.
+ unsigned m_entryCount; //!< Number of entries in #m_info.
+};
+
+}; // namespace elftosb
+
+#endif // _GHSSecInfo_h_
--- /dev/null
+/*
+ * File: GlobMatcher.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "GlobMatcher.h"
+
+#ifndef NEGATE
+#define NEGATE '^' // std cset negation char
+#endif
+
+using namespace elftosb;
+
+//! The glob pattern must match the \e entire test value argument in order
+//! for the match to be considered successful. Thus, even if, for example,
+//! the pattern matches all but the last character the result will be false.
+//!
+//! \retval true The test value does match the glob pattern.
+//! \retval false The test value does not match the glob pattern.
+bool GlobMatcher::match(const std::string & testValue)
+{
+ return globMatch(testValue.c_str(), m_pattern.c_str());
+}
+
+//! \note This glob implementation was originally written by ozan s. yigit in
+//! December 1994. This is public domain source code.
+bool GlobMatcher::globMatch(const char *str, const char *p)
+{
+ int negate;
+ int match;
+ int c;
+
+ while (*p) {
+ if (!*str && *p != '*')
+ return false;
+
+ switch (c = *p++) {
+
+ case '*':
+ while (*p == '*')
+ p++;
+
+ if (!*p)
+ return true;
+
+ if (*p != '?' && *p != '[' && *p != '\\')
+ while (*str && *p != *str)
+ str++;
+
+ while (*str) {
+ if (globMatch(str, p))
+ return true;
+ str++;
+ }
+ return false;
+
+ case '?':
+ if (*str)
+ break;
+ return false;
+
+ // set specification is inclusive, that is [a-z] is a, z and
+ // everything in between. this means [z-a] may be interpreted
+ // as a set that contains z, a and nothing in between.
+ case '[':
+ if (*p != NEGATE)
+ negate = false;
+ else {
+ negate = true;
+ p++;
+ }
+
+ match = false;
+
+ while (!match && (c = *p++)) {
+ if (!*p)
+ return false;
+ if (*p == '-') { // c-c
+ if (!*++p)
+ return false;
+ if (*p != ']') {
+ if (*str == c || *str == *p ||
+ (*str > c && *str < *p))
+ match = true;
+ }
+ else { // c-]
+ if (*str >= c)
+ match = true;
+ break;
+ }
+ }
+ else { // cc or c]
+ if (c == *str)
+ match = true;
+ if (*p != ']') {
+ if (*p == *str)
+ match = true;
+ }
+ else
+ break;
+ }
+ }
+
+ if (negate == match)
+ return false;
+ // if there is a match, skip past the cset and continue on
+ while (*p && *p != ']')
+ p++;
+ if (!*p++) // oops!
+ return false;
+ break;
+
+ case '\\':
+ if (*p)
+ c = *p++;
+ default:
+ if (c != *str)
+ return false;
+ break;
+
+ }
+ str++;
+ }
+
+ return !*str;
+}
+
--- /dev/null
+/*
+ * File: GlobMatcher.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_GlobMatcher_h_)
+#define _GlobMatcher_h_
+
+#include "StringMatcher.h"
+
+namespace elftosb
+{
+
+/*!
+ * \brief This class uses glob pattern matching to match strings.
+ *
+ * Glob patterns:
+ * - * matches zero or more characters
+ * - ? matches any single character
+ * - [set] matches any character in the set
+ * - [^set] matches any character NOT in the set
+ * where a set is a group of characters or ranges. a range
+ * is written as two characters seperated with a hyphen: a-z denotes
+ * all characters between a to z inclusive.
+ * - [-set] set matches a literal hypen and any character in the set
+ * - []set] matches a literal close bracket and any character in the set
+ *
+ * - char matches itself except where char is '*' or '?' or '['
+ * - \\char matches char, including any pattern character
+ *
+ * Examples:
+ * - a*c ac abc abbc ...
+ * - a?c acc abc aXc ...
+ * - a[a-z]c aac abc acc ...
+ * - a[-a-z]c a-c aac abc ...
+ */
+class GlobMatcher : public StringMatcher
+{
+public:
+ //! \brief Constructor.
+ GlobMatcher(const std::string & pattern)
+ : StringMatcher(), m_pattern(pattern)
+ {
+ }
+
+ //! \brief Returns whether \a testValue matches the glob pattern.
+ virtual bool match(const std::string & testValue);
+
+protected:
+ std::string m_pattern; //!< The glob pattern to match against.
+
+ //! \brief Glob implementation.
+ bool globMatch(const char * str, const char * p);
+};
+
+}; // namespace elftosb
+
+#endif // _GlobMatcher_h_
--- /dev/null
+/*
+ * File: HexValues.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "HexValues.h"
+
+bool isHexDigit(char c)
+{
+ return isdigit(c) || (c >= 'a' && c <= 'f') || (c >= 'A' && c <= 'F');
+}
+
+//! \return The integer equivalent to \a c.
+//! \retval -1 The character \a c is not a hex character.
+uint8_t hexCharToInt(char c)
+{
+ if (c >= '0' && c <= '9')
+ return c - '0';
+ else if (c >= 'a' && c <= 'f')
+ return c - 'a' + 10;
+ else if (c >= 'A' && c <= 'F')
+ return c - 'A' + 10;
+ else
+ return static_cast<uint8_t>(-1);
+}
+
+//! \param encodedByte Must point to at least two ASCII hex characters.
+//!
+uint8_t hexByteToInt(const char * encodedByte)
+{
+ return (hexCharToInt(encodedByte[0]) << 4) | hexCharToInt(encodedByte[1]);
+}
--- /dev/null
+/*
+ * File: HexValues.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_HexValues_h_)
+#define _HexValues_h_
+
+#include "stdafx.h"
+
+//! \brief Determines whether \a c is a hex digit character.
+bool isHexDigit(char c);
+
+//! \brief Converts a hexidecimal character to the integer equivalent.
+uint8_t hexCharToInt(char c);
+
+//! \brief Converts a hex-encoded byte to the integer equivalent.
+uint8_t hexByteToInt(const char * encodedByte);
+
+#endif // _HexValues_h_
--- /dev/null
+/*
+ * File: DataSource.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Freescale Semiconductor, Inc.
+ * Proprietary & Confidential
+ *
+ * This source code and the algorithms implemented therein constitute
+ * confidential information and may comprise trade secrets of Freescale Semiconductor, Inc.
+ * or its associates, and any use thereof is subject to the terms and
+ * conditions of the Confidential Disclosure Agreement pursual to which this
+ * source code was originally received.
+ */
+
+#include "IVTDataSource.h"
+#include "DataTarget.h"
+#include "EndianUtilities.h"
+#include <algorithm>
+#include <stdlib.h>
+#include <string.h>
+
+using namespace elftosb;
+
+IVTDataSource::IVTDataSource()
+: DataSource(),
+ DataSource::Segment((DataSource&)*this),
+ m_isSelfSet(false)
+{
+ // Init the IVT structure.
+ memset(&m_ivt, 0, sizeof(m_ivt));
+ hab_hdr_t hdr = IVT_HDR(sizeof(m_ivt), HAB_VERSION);
+ m_ivt.hdr = hdr;
+}
+
+unsigned IVTDataSource::getData(unsigned offset, unsigned maxBytes, uint8_t * buffer)
+{
+ // Bail if the offset is out of range.
+ if (offset >= sizeof(m_ivt))
+ {
+ return 0;
+ }
+
+ // If we have an associated target, and the IVT self pointer is not set, then
+ // fill in the self pointer from the target address.
+ if (m_target && !m_isSelfSet)
+ {
+ m_ivt.self = ENDIAN_HOST_TO_LITTLE_U32(m_target->getBeginAddress());
+ }
+
+ // Truncate max bytes at the end of the IVT.
+ maxBytes = std::min<unsigned>(maxBytes, sizeof(m_ivt) - offset);
+
+ // Copy into output buffer.
+ if (maxBytes)
+ {
+ memcpy(buffer, (uint8_t *)&m_ivt + offset, maxBytes);
+ }
+
+ return maxBytes;
+}
+
+unsigned IVTDataSource::getLength()
+{
+ return sizeof(m_ivt);
+}
+
+//! The IVT has a natural location if its self pointer was explicitly specified.
+//!
+bool IVTDataSource::hasNaturalLocation()
+{
+ return m_isSelfSet;
+}
+
+//!
+uint32_t IVTDataSource::getBaseAddress()
+{
+ return m_ivt.self;
+}
+
+bool IVTDataSource::setFieldByName(const std::string & name, uint32_t value)
+{
+ if (name == "entry")
+ {
+ m_ivt.entry = ENDIAN_HOST_TO_LITTLE_U32(value);
+ }
+ else if (name == "dcd")
+ {
+ m_ivt.dcd = ENDIAN_HOST_TO_LITTLE_U32(value);
+ }
+ else if (name == "boot_data")
+ {
+ m_ivt.boot_data = ENDIAN_HOST_TO_LITTLE_U32(value);
+ }
+ else if (name == "self")
+ {
+ m_ivt.self = ENDIAN_HOST_TO_LITTLE_U32(value);
+ m_isSelfSet = true;
+ }
+ else if (name == "csf")
+ {
+ m_ivt.csf = ENDIAN_HOST_TO_LITTLE_U32(value);
+ }
+ else
+ {
+ // Unrecognized field name.
+ return false;
+ }
+
+ return true;
+}
+
+
--- /dev/null
+/*
+ * File: DataSource.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Freescale Semiconductor, Inc.
+ * Proprietary & Confidential
+ *
+ * This source code and the algorithms implemented therein constitute
+ * confidential information and may comprise trade secrets of Freescale Semiconductor, Inc.
+ * or its associates, and any use thereof is subject to the terms and
+ * conditions of the Confidential Disclosure Agreement pursual to which this
+ * source code was originally received.
+ */
+#if !defined(_IVTDataSource_h_)
+#define _IVTDataSource_h_
+
+#include "DataSource.h"
+
+/** Header field components
+ * @ingroup hdr
+ */
+typedef struct hab_hdr {
+ uint8_t tag; /**< Tag field */
+ uint8_t len[2]; /**< Length field in bytes (big-endian) */
+ uint8_t par; /**< Parameters field */
+} hab_hdr_t;
+
+/** Image entry function prototype
+ * @ingroup rvt
+ *
+ * This typedef serves as the return type for hab_rvt.authenticate_image(). It
+ * specifies a void-void function pointer, but can be cast to another function
+ * pointer type if required.
+ */
+typedef void (*hab_image_entry_f)(void);
+
+/** @ref ivt structure
+ * @ingroup ivt
+ *
+ * @par Format
+ *
+ * An @ref ivt consists of a @ref hdr followed by a list of addresses as
+ * described further below.
+ *
+ * @warning The @a entry address may not be NULL.
+ *
+ * @warning On an IC not configured as #HAB_CFG_CLOSED, the
+ * @a csf address may be NULL. If it is not NULL, the @ref csf will be
+ * processed, but any failures should be non-fatal.
+ *
+ * @warning On an IC configured as #HAB_CFG_CLOSED, the @a
+ * csf address may not be NULL, and @ref csf failures are typically fatal.
+ *
+ * @remark The Boot Data located using the @a boot_data field is interpreted
+ * by the HAB caller in a boot-mode specific manner. This may be used by the
+ * boot ROM as to determine the load address and boot device configuration for
+ * images loaded from block devices (see @ref ref_rug for details).
+ *
+ * @remark All addresses given in the IVT, including the Boot Data (if
+ * present) are those for the final load location.
+ *
+ * @anchor ila
+ *
+ * @par Initial load addresses
+ *
+ * The @a self field is used to calculate addresses in boot modes where an
+ * initial portion of the image is loaded to an initial location. In such
+ * cases, the IVT, Boot Data (if present) and DCD (if present) are used in
+ * configuring the IC and loading the full image to its final location. Only
+ * the IVT, Boot Data (if present) and DCD (if present) are required to be
+ * within the initial image portion.
+ *
+ * The method for calculating an initial load address for the DCD is
+ * illustrated in the following C fragment. Similar calculations apply to
+ * other fields.
+ *
+@verbatim
+ hab_ivt_t* ivt_initial = <initial IVT load address>;
+ const void* dcd_initial = ivt_initial->dcd;
+ if (ivt_initial->dcd != NULL)
+ dcd_initial = (const uint8_t*)ivt_initial
+ + (ivt_initial->dcd - ivt_initial->self)
+@endverbatim
+
+ * \note The void* types in this structure have been changed to uint32_t so
+ * that this code will work correctly when compiled on a 64-bit host.
+ * Otherwise the structure would come out incorrect.
+ */
+struct hab_ivt {
+ /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields
+ * (see @ref data)
+ */
+ hab_hdr_t hdr;
+ /** Absolute address of the first instruction to execute from the
+ * image
+ */
+ /*hab_image_entry_f*/ uint32_t entry;
+ /** Reserved in this version of HAB: should be NULL. */
+ /*const void*/ uint32_t reserved1;
+ /** Absolute address of the image DCD: may be NULL. */
+ /*const void*/ uint32_t dcd;
+ /** Absolute address of the Boot Data: may be NULL, but not interpreted
+ * any further by HAB
+ */
+ /*const void*/ uint32_t boot_data;
+ /** Absolute address of the IVT.*/
+ /*const void*/ uint32_t self;
+ /** Absolute address of the image CSF.*/
+ /*const void*/ uint32_t csf;
+ /** Reserved in this version of HAB: should be zero. */
+ uint32_t reserved2;
+};
+
+/** @ref ivt type
+ * @ingroup ivt
+ */
+typedef struct hab_ivt hab_ivt_t;
+
+/*
+ * Helper macros
+ */
+#define HAB_CMD_UNS 0xff
+
+#define DEFAULT_IMG_KEY_IDX 2
+
+#define GEN_MASK(width) \
+ ((1UL << (width)) - 1)
+
+#define GEN_FIELD(f, width, shift) \
+ (((f) & GEN_MASK(width)) << (shift))
+
+#define PACK_UINT32(a, b, c, d) \
+ ( (((a) & 0xFF) << 24) \
+ |(((b) & 0xFF) << 16) \
+ |(((c) & 0xFF) << 8) \
+ |(((d) & 0xFF)) )
+
+#define EXPAND_UINT32(w) \
+ (uint8_t)((w)>>24), (uint8_t)((w)>>16), (uint8_t)((w)>>8), (uint8_t)(w)
+
+#define HDR(tag, bytes, par) \
+ (uint8_t)(tag), (uint8_t)((bytes)>>8), (uint8_t)(bytes), (uint8_t)(par)
+
+#define HAB_VER(maj, min) \
+ (GEN_FIELD((maj), HAB_VER_MAJ_WIDTH, HAB_VER_MAJ_SHIFT) \
+ | GEN_FIELD((min), HAB_VER_MIN_WIDTH, HAB_VER_MIN_SHIFT))
+
+/*
+ * CSF header
+ */
+
+#define CSF_HDR(bytes, HABVER) \
+ HDR(HAB_TAG_CSF, (bytes), HABVER)
+
+
+/*
+ * DCD header
+ */
+
+#define DCD_HDR(bytes, HABVER) \
+ HDR(HAB_TAG_DCD, (bytes), HABVER)
+
+/*
+ * IVT header (goes in the struct's hab_hdr_t field, not a byte array)
+ */
+#define IVT_HDR(bytes, HABVER) \
+ {HAB_TAG_IVT, {(uint8_t)((bytes)>>8), (uint8_t)(bytes)}, HABVER}
+
+/** @name External data structure tags
+ * @anchor dat_tag
+ *
+ * Tag values 0x00 .. 0xef are reserved for HAB. Values 0xf0 .. 0xff
+ * are available for custom use.
+ */
+/*@{*/
+#define HAB_TAG_IVT 0xd1 /**< Image Vector Table */
+#define HAB_TAG_DCD 0xd2 /**< Device Configuration Data */
+#define HAB_TAG_CSF 0xd4 /**< Command Sequence File */
+#define HAB_TAG_CRT 0xd7 /**< Certificate */
+#define HAB_TAG_SIG 0xd8 /**< Signature */
+#define HAB_TAG_EVT 0xdb /**< Event */
+#define HAB_TAG_RVT 0xdd /**< ROM Vector Table */
+/* Values b0 ... cf reserved for CSF commands. Values e0 ... ef reserved for
+ * key types.
+ *
+ * Available values: 03, 05, 06, 09, 0a, 0c, 0f, 11, 12, 14, 17, 18, 1b, 1d,
+ * 1e, 21, 22, 24, 27, 28, 2b, 2d, 2e, 30, 33, 35, 36, 39, 3a, 3c, 3f, 41, 42,
+ * 44, 47, 48, 4b, 4d, 4e, 50, 53, 55, 56, 59, 5a, 5c, 5f, 60, 63, 65, 66, 69,
+ * 6a, 6c, 6f, 71, 72, 74, 77, 78, 7b, 7d, 7e, 81, 82, 84, 87, 88, 8b, 8d, 8e,
+ * 90, 93, 95, 96, 99, 9a, 9c, 9f, a0, a3, a5, a6, a9, aa, ac, af, b1, b2, b4,
+ * b7, b8, bb, bd, be
+ *
+ * Custom values: f0, f3, f5, f6, f9, fa, fc, ff
+ */
+/*@}*/
+
+/** @name HAB version */
+/*@{*/
+#define HAB_MAJOR_VERSION 4 /**< Major version of this HAB release */
+#define HAB_MINOR_VERSION 0 /**< Minor version of this HAB release */
+#define HAB_VER_MAJ_WIDTH 4 /**< Major version field width */
+#define HAB_VER_MAJ_SHIFT 4 /**< Major version field offset */
+#define HAB_VER_MIN_WIDTH 4 /**< Minor version field width */
+#define HAB_VER_MIN_SHIFT 0 /**< Minor version field offset */
+/** Full version of this HAB release @hideinitializer */
+#define HAB_VERSION HAB_VER(HAB_MAJOR_VERSION, HAB_MINOR_VERSION)
+/** Base version for this HAB release @hideinitializer */
+#define HAB_BASE_VERSION HAB_VER(HAB_MAJOR_VERSION, 0)
+
+/*@}*/
+
+namespace elftosb {
+
+/*!
+ * \brief Data source for an IVT structure used by HAB4.
+ *
+ * This data source represents an IVT structure used by HAB4. Fields of the IVT can be set
+ * by name, making it easy to interface with a parser. And it has some intelligence regarding
+ * the IVT's self pointer. Before the data is copied out by the getData() method, the self field
+ * will be filled in automatically if it has not already been set and there is an associated
+ * data target object. This lets the IVT pick up its own address from the location where it is
+ * being loaded. Alternatively, if the self pointer is filled in explicitly, then the data
+ * source will have a natural location equal to the self pointer.
+ *
+ * This data source acts as its own segment.
+ */
+class IVTDataSource : public DataSource, public DataSource::Segment
+{
+public:
+ //! \brief Default constructor.
+ IVTDataSource();
+
+ //! \brief There is only one segment.
+ virtual unsigned getSegmentCount() { return 1; }
+
+ //! \brief Returns this object, as it is its own segment.
+ virtual DataSource::Segment * getSegmentAt(unsigned index) { return this; }
+
+ //! \name Segment methods
+ //@{
+
+ //! \brief Copy out some or all of the IVT structure.
+ //!
+ virtual unsigned getData(unsigned offset, unsigned maxBytes, uint8_t * buffer);
+
+ //! \brief Gets the length of the segment's data.
+ virtual unsigned getLength();
+
+ //! \brief Returns whether the segment has an associated address.
+ virtual bool hasNaturalLocation();
+
+ //! \brief Returns the address associated with the segment.
+ virtual uint32_t getBaseAddress();
+
+ //@}
+
+ //! \name IVT access
+ //@{
+
+ //! \brief Set one of the IVT's fields by providing its name.
+ //!
+ //! Acceptable field names are:
+ //! - entry
+ //! - dcd
+ //! - boot_data
+ //! - self
+ //! - csf
+ //!
+ //! As long as the \a name parameter specifies one of these fields, the return value
+ //! will be true. If \a name contains any other value, then false will be returned and
+ //! the IVT left unmodified.
+ //!
+ //! Once the \a self field has been set to any value, the data source will have a
+ //! natural location. This works even if the \a self address is 0.
+ //!
+ //! \param name The name of the field to set. Field names are case sensitive, just like in
+ //! the C language.
+ //! \param value The value to which the field will be set.
+ //! \retval true The field was set successfully.
+ //! \retval false There is no field with the provided name.
+ bool setFieldByName(const std::string & name, uint32_t value);
+
+ //! \brief Returns a reference to the IVT structure.
+ hab_ivt_t & getIVT() { return m_ivt; }
+
+ //@}
+
+protected:
+ hab_ivt_t m_ivt; //!< The IVT structure.
+ bool m_isSelfSet; //!< True if the IVT self pointer was explicitly set.
+};
+
+} // elftosb
+
+#endif // _IVTDataSource_h_
--- /dev/null
+/*
+ * File: Logging.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "Logging.h"
+#include <stdarg.h>
+#include <stdio.h>
+#include "smart_ptr.h"
+
+// init global logger to null
+Logger * Log::s_logger = NULL;
+
+void Logger::log(const char * fmt, ...)
+{
+ va_list args;
+ va_start(args, fmt);
+ log(m_level, fmt, args);
+ va_end(args);
+}
+
+void Logger::log(log_level_t level, const char * fmt, ...)
+{
+ va_list args;
+ va_start(args, fmt);
+ log(level, fmt, args);
+ va_end(args);
+}
+
+void Logger::log(const char * fmt, va_list args)
+{
+ log(m_level, fmt, args);
+}
+
+//! Allocates a temporary 1KB buffer which is used to hold the
+//! formatted string.
+void Logger::log(log_level_t level, const char * fmt, va_list args)
+{
+ smart_array_ptr<char> buffer = new char[1024];
+ vsprintf(buffer, fmt, args);
+ if (level <= m_filter)
+ {
+ _log(buffer);
+ }
+}
+
+void Log::log(const char * fmt, ...)
+{
+ if (s_logger)
+ {
+ va_list args;
+ va_start(args, fmt);
+ s_logger->log(fmt, args);
+ va_end(args);
+ }
+}
+
+void Log::log(const std::string & msg)
+{
+ if (s_logger)
+ {
+ s_logger->log(msg);
+ }
+}
+
+void Log::log(Logger::log_level_t level, const char * fmt, ...)
+{
+ if (s_logger)
+ {
+ va_list args;
+ va_start(args, fmt);
+ s_logger->log(level, fmt, args);
+ va_end(args);
+ }
+}
+
+void Log::log(Logger::log_level_t level, const std::string & msg)
+{
+ if (s_logger)
+ {
+ s_logger->log(level, msg);
+ }
+}
+
+void StdoutLogger::_log(const char * msg)
+{
+ printf(msg);
+}
+
--- /dev/null
+/*
+ * File: Logging.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_Logging_h_)
+#define _Logging_h_
+
+#include <string>
+#include <assert.h>
+#include <stdarg.h>
+
+/*!
+ * \brief Base logger class.
+ *
+ * There are two types of logging levels that are used by this class. First
+ * there is the filter level. Any log message that is assigned a level
+ * higher than the current filter level is discarded. Secondly there is the
+ * current output level. Log messages that do not have their own level
+ * use the current output level to determine if they should be shown or
+ * not.
+ *
+ * The two methods setFilterLevel() and setOutputLevel() set the filter
+ * and default output logging levels, respectively. There are corresponding
+ * getter methods as well. Both the filter and output levels are
+ * initialized to #INFO during object construction.
+ *
+ * Most use of the logger classes is expected to be through the Log
+ * class. It provides static logging methods that call through to a global
+ * singleton logger instance. There is also a Log::SetOutputLevel utility
+ * class that makes it extremely easiy to temporarily change the default
+ * output logging level.
+ *
+ * Of all the overloaded log() methods in this class, none of them are
+ * really expected to be reimplemented by subclasses. Instead, there is
+ * the single protected _log() method that takes a simple string pointer.
+ * The other log methods all wind up calling _log(), so it provides a
+ * single point to override. In fact, _log() is pure virtual, so subclasses
+ * must implement it.
+ *
+ * \see Log
+ */
+class Logger
+{
+public:
+ //! \brief Logging levels.
+ enum log_level_t
+ {
+ URGENT = 0, //!< The lowest level, for messages that must always be logged.
+ ERROR, //!< For fatal error messages.
+ WARNING, //!< For non-fatal warning messages.
+ INFO, //!< The normal log level, for status messages.
+ INFO2, //!< For verbose status messages.
+ DEBUG, //!< For internal reporting.
+ DEBUG2 //!< Highest log level; verbose debug logging.
+ };
+
+public:
+ //! \brief Default constructor.
+ Logger() : m_filter(INFO), m_level(INFO) {}
+
+ //! \brief Destructor.
+ virtual ~Logger() {}
+
+ //! \name Logging levels
+ //@{
+ //! \brief Changes the logging level to \a level.
+ inline void setFilterLevel(log_level_t level) { m_filter = level; }
+
+ //! \brief Returns the current logging filter level.
+ inline log_level_t getFilterLevel() const { return m_filter; }
+
+ //! \brief Changes the logging output level to \a level.
+ inline void setOutputLevel(log_level_t level) { m_level = level; }
+
+ //! \brief Returns the current logging output level.
+ inline log_level_t getOutputLevel() const { return m_level; }
+ //@}
+
+ //! \name Logging
+ //@{
+ //! \brief Log with format.
+ virtual void log(const char * fmt, ...);
+
+ //! \brief Log a string object.
+ virtual void log(const std::string & msg) { log(msg.c_str()); }
+
+ //! \brief Log with format at a specific output level.
+ virtual void log(log_level_t level, const char * fmt, ...);
+
+ //! \brief Log a string output at a specific output level.
+ virtual void log(log_level_t level, const std::string & msg) { log(level, msg.c_str()); }
+
+ //! \brief Log with format using an argument list.
+ virtual void log(const char * fmt, va_list args);
+
+ //! \brief Log with format using an argument with a specific output level.
+ virtual void log(log_level_t level, const char * fmt, va_list args);
+ //@}
+
+protected:
+ log_level_t m_filter; //!< The current logging filter level.
+ log_level_t m_level; //!< The current log output level.
+
+protected:
+ //! \brief The base pure virtual logging function implemented by subclasses.
+ virtual void _log(const char * msg)=0;
+};
+
+/*!
+ * \brief Wraps a set of static functions for easy global logging access.
+ *
+ * This class has a set of static methods that make it easy to access a global
+ * logger instance without having to worry about extern symbols. It does this
+ * by keeping a static member variable pointing at the singleton logger instance,
+ * which is set with the setLogger() static method.
+ *
+ * There is also an inner utility class called SetOutputLevel that uses
+ * C++ scoping rules to temporarily change the output logging level. When the
+ * SetOutputLevel instance falls out of scope the output level is restored
+ * to the previous value.
+ */
+class Log
+{
+public:
+ //! \name Singleton logger access
+ //@{
+ //! \brief Returns the current global logger singleton.
+ static inline Logger * getLogger() { return s_logger; }
+
+ //! \brief Sets the global logger singleton instance.
+ static inline void setLogger(Logger * logger) { s_logger = logger; }
+ //@}
+
+ //! \name Logging
+ //@{
+ //! \brief Log with format.
+ static void log(const char * fmt, ...);
+
+ //! \brief Log a string object.
+ static void log(const std::string & msg);
+
+ //! \brief Log with format at a specific output level.
+ static void log(Logger::log_level_t level, const char * fmt, ...);
+
+ //! \brief Log a string output at a specific output level.
+ static void log(Logger::log_level_t level, const std::string & msg);
+ //@}
+
+protected:
+ static Logger * s_logger; //!< The single global logger instance.
+
+public:
+ /*!
+ * \brief Utility class to temporarily change the logging output level.
+ *
+ * This class will change the current logging output level of a given
+ * logger instance. Then when it falls out of scope it will set the
+ * level back to what it was originally.
+ *
+ * Use like this:
+ * \code
+ * // output level is some value here
+ * {
+ * Log::SetOutputLevel leveler(Logger::DEBUG);
+ * // now output level is DEBUG
+ * Log::log("my debug message 1");
+ * Log::log("my debug message 2");
+ * }
+ * // output level is restored to previous value
+ * \endcode
+ */
+ class SetOutputLevel
+ {
+ public:
+ //! \brief Default constructor.
+ //!
+ //! Saves the current logging output level of the global logger,
+ //! as managed by the Log class, and sets the new level to \a level.
+ SetOutputLevel(Logger::log_level_t level)
+ : m_logger(Log::getLogger()), m_saved(Logger::INFO)
+ {
+ assert(m_logger);
+ m_saved = m_logger->getOutputLevel();
+ m_logger->setOutputLevel(level);
+ }
+
+ //! \brief Constructor.
+ //!
+ //! Saves the current logging output level of \a logger and sets
+ //! the new level to \a level.
+ SetOutputLevel(Logger * logger, Logger::log_level_t level)
+ : m_logger(logger), m_saved(logger->getOutputLevel())
+ {
+ assert(m_logger);
+ m_logger->setOutputLevel(level);
+ }
+
+ //! \brief Destructor.
+ //!
+ //! Restores the saved logging output level.
+ ~SetOutputLevel()
+ {
+ m_logger->setOutputLevel(m_saved);
+ }
+
+ protected:
+ Logger * m_logger; //!< The logger instance we're controlling.
+ Logger::log_level_t m_saved; //!< Original logging output level.
+ };
+
+};
+
+
+/*!
+ * \brief Simple logger that writes to stdout.
+ */
+class StdoutLogger : public Logger
+{
+protected:
+ //! \brief Logs the message to stdout.
+ virtual void _log(const char * msg);
+};
+
+#endif // _Logging_h_
--- /dev/null
+/*
+ * File: Operation.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "Operation.h"
+
+using namespace elftosb;
+
+//! The operation object takes ownership of \a source.
+//!
+//! Cross references between the target and source are updated.
+void LoadOperation::setSource(DataSource * source)
+{
+ m_source = source;
+
+ if (m_target)
+ {
+ m_target->setSource(m_source);
+ }
+ if (m_source)
+ {
+ m_source->setTarget(m_target);
+ }
+}
+
+//! The operation object takes ownership of \a target.
+//!
+//! Cross references between the target and source are updated.
+void LoadOperation::setTarget(DataTarget * target)
+{
+ m_target = target;
+
+ if (m_target)
+ {
+ m_target->setSource(m_source);
+ }
+ if (m_source)
+ {
+ m_source->setTarget(m_target);
+ }
+}
+
+//! Disposes of operations objects in the sequence.
+OperationSequence::~OperationSequence()
+{
+// iterator_t it = begin();
+// for (; it != end(); ++it)
+// {
+// delete it->second;
+// }
+}
+
+void OperationSequence::append(const OperationSequence * other)
+{
+ const_iterator_t it = other->begin();
+ for (; it != other->end(); ++it)
+ {
+ m_operations.push_back(*it);
+ }
+}
--- /dev/null
+/*
+ * File: Operation.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_Operation_h_)
+#define _Operation_h_
+
+#include "stdafx.h"
+#include <vector>
+#include "DataSource.h"
+#include "DataTarget.h"
+#include "smart_ptr.h"
+
+namespace elftosb
+{
+
+/*!
+ * \brief Abstract base class for all boot operations.
+ */
+class Operation
+{
+public:
+ Operation() {}
+ virtual ~Operation() {}
+};
+
+/*!
+ * \brief Load data into memory operation.
+ */
+class LoadOperation : public Operation
+{
+public:
+ LoadOperation() : Operation(), m_source(), m_target() {}
+
+ void setSource(DataSource * source);
+ inline DataSource * getSource() { return m_source; }
+
+ void setTarget(DataTarget * target);
+ inline DataTarget * getTarget() { return m_target; }
+
+ inline void setDCDLoad(bool isDCD) { m_isDCDLoad = isDCD; }
+ inline bool isDCDLoad() const { return m_isDCDLoad; }
+
+protected:
+ smart_ptr<DataSource> m_source;
+ smart_ptr<DataTarget> m_target;
+ bool m_isDCDLoad;
+};
+
+/*!
+ * \brief Operation to execute code at a certain address.
+ */
+class ExecuteOperation : public Operation
+{
+public:
+ enum execute_type_t
+ {
+ kJump,
+ kCall
+ };
+
+public:
+ ExecuteOperation() : Operation(), m_target(), m_argument(0), m_type(kCall), m_isHAB(false) {}
+
+ inline void setTarget(DataTarget * target) { m_target = target; }
+ inline DataTarget * getTarget() { return m_target; }
+
+ inline void setArgument(uint32_t arg) { m_argument = arg; }
+ inline uint32_t getArgument() { return m_argument; }
+
+ inline void setExecuteType(execute_type_t type) { m_type = type; }
+ inline execute_type_t getExecuteType() { return m_type; }
+
+ inline void setIsHAB(bool isHAB) { m_isHAB = isHAB; }
+ inline bool isHAB() const { return m_isHAB; }
+
+protected:
+ smart_ptr<DataTarget> m_target;
+ uint32_t m_argument;
+ execute_type_t m_type;
+ bool m_isHAB;
+};
+
+/*!
+ * \brief Authenticate with HAB and execute the entry point.
+ */
+class HABExecuteOperation : public ExecuteOperation
+{
+public:
+ HABExecuteOperation() : ExecuteOperation() {}
+};
+
+/*!
+ * \brief Operation to switch boot modes.
+ */
+class BootModeOperation : public Operation
+{
+public:
+ BootModeOperation() : Operation() {}
+
+ inline void setBootMode(uint32_t mode) { m_bootMode = mode; }
+ inline uint32_t getBootMode() const { return m_bootMode; }
+
+protected:
+ uint32_t m_bootMode; //!< The new boot mode value.
+};
+
+/*!
+ * \brief Ordered sequence of operations.
+ *
+ * The operation objects owned by the sequence are \e not deleted when the
+ * sequence is destroyed. The owner of the sequence must manually delete
+ * the operation objects.
+ */
+class OperationSequence
+{
+public:
+ typedef std::vector<Operation*> operation_list_t; //!< Type for a list of operation objects.
+ typedef operation_list_t::iterator iterator_t; //!< Iterator over operations.
+ typedef operation_list_t::const_iterator const_iterator_t; //!< Const iterator over operations.
+
+public:
+ //! \brief Default constructor.
+ OperationSequence() {}
+
+ //! \brief Constructor. Makes a one-element sequence from \a soleElement.
+ OperationSequence(Operation * soleElement) { m_operations.push_back(soleElement); }
+
+ //! \brief Destructor.
+ virtual ~OperationSequence();
+
+ //! \name Iterators
+ //@{
+ inline iterator_t begin() { return m_operations.begin(); }
+ inline const_iterator_t begin() const { return m_operations.begin(); }
+ inline iterator_t end() { return m_operations.end(); }
+ inline const_iterator_t end() const { return m_operations.end(); }
+ //@}
+
+ inline Operation * operator [] (unsigned index) const { return m_operations[index]; }
+
+ //! \name Status
+ //@{
+ //! \brief Returns the number of operations in the sequence.
+ inline unsigned getCount() const { return m_operations.size(); }
+ //@}
+
+ //! \name Operations
+ //@{
+ //! \brief Append one operation object to the sequence.
+ inline void append(Operation * op) { m_operations.push_back(op); }
+
+ //! \brief Append the contents of \a other onto this sequence.
+ void append(const OperationSequence * other);
+
+ //! \brief Appends \a other onto this sequence.
+ OperationSequence & operator += (const OperationSequence * other) { append(other); return *this; }
+ //@}
+
+protected:
+ operation_list_t m_operations; //!< The list of operations.
+};
+
+}; // namespace elftosb
+
+#endif // _Operation_h_
--- /dev/null
+/*
+ * File: OptionContext.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_OptionContext_h_)
+#define _OptionContext_h_
+
+#include <string>
+#include "Value.h"
+
+namespace elftosb
+{
+
+/*!
+ * \brief Pure abstract interface class to a table of options.
+ */
+class OptionContext
+{
+public:
+ //! \brief Detemine whether the named option is present in the table.
+ //! \param name The name of the option to query.
+ //! \retval true The option is present and has a value.
+ //! \retval false No option with that name is in the table.
+ virtual bool hasOption(const std::string & name) const=0;
+
+ //! \brief Returns the option's value.
+ //! \param name The name of the option.
+ //! \return The value for the option named \a name.
+ //! \retval NULL No option is in the table with that name.
+ virtual const Value * getOption(const std::string & name) const=0;
+
+ //! \brief Adds or changes an option's value.
+ //!
+ //! If the option was not already present in the table, it is added.
+ //! Otherwise the old value is replaced.
+ //!
+ //! \param name The option's name.
+ //! \param value New value for the option.
+ virtual void setOption(const std::string & name, Value * value)=0;
+
+ //! \brief Removes an option from the table.
+ //! \param name The name of the option to remove.
+ virtual void deleteOption(const std::string & name)=0;
+};
+
+}; // namespace elftosb
+
+#endif // _OptionContext_h_
--- /dev/null
+/*
+ * File: OptionDictionary.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "OptionDictionary.h"
+
+using namespace elftosb;
+
+//! Deletes all of the option values that have been assigned locally.
+//!
+OptionDictionary::~OptionDictionary()
+{
+ option_map_t::iterator it = m_options.begin();
+ for (; it != m_options.end(); ++it)
+ {
+ if (it->second.m_value)
+ {
+ delete it->second.m_value;
+ }
+ }
+}
+
+//! If a parent context has been set and the option does not exist in
+//! this instance, then the parent is asked if it contains the option.
+//!
+//! \param name The name of the option to query.
+//! \retval true The option is present in this instance or one of the parent.
+//! \retval false No option with that name is in the dictionary, or any parent
+bool OptionDictionary::hasOption(const std::string & name) const
+{
+ bool hasIt = (m_options.find(name) != m_options.end());
+ if (!hasIt && m_parent)
+ {
+ return m_parent->hasOption(name);
+ }
+ return hasIt;
+}
+
+//! If this object does not contain an option with the name of \a name,
+//! then the parent is asked for the value (if a parent has been set).
+//!
+//! \param name The name of the option.
+//! \return The value for the option named \a name.
+//! \retval NULL No option is in the table with that name. An option may also
+//! explicitly be set to a NULL value. The only way to tell the difference
+//! is to use the hasOption() method.
+const Value * OptionDictionary::getOption(const std::string & name) const
+{
+ option_map_t::const_iterator it = m_options.find(name);
+ if (it == m_options.end())
+ {
+ if (m_parent)
+ {
+ return m_parent->getOption(name);
+ }
+ else
+ {
+ return NULL;
+ }
+ }
+
+ return it->second.m_value;
+}
+
+//! If the option was not already present in the table, it is added.
+//! Otherwise the old value is replaced. The option is always set locally;
+//! parent objects are never modified.
+//!
+//! If the option has been locked with a call to lockOption() before trying
+//! to set its value, the setOption() is effectively ignored. To tell if
+//! an option is locked, use the isOptionLocked() method.
+//!
+//! \warning If the option already had a value, that previous value is deleted.
+//! This means that it cannot currently be in use by another piece of code.
+//! See the note in getOption().
+//!
+//! \param name The option's name.
+//! \param value New value for the option.
+void OptionDictionary::setOption(const std::string & name, Value * value)
+{
+ option_map_t::iterator it = m_options.find(name);
+ OptionValue newValue;
+
+ // delete the option value instance before replacing it
+ if (it != m_options.end())
+ {
+ // Cannot modify value if locked.
+ if (it->second.m_isLocked)
+ {
+ return;
+ }
+
+ if (it->second.m_value)
+ {
+ delete it->second.m_value;
+ }
+
+ // save previous locked value
+ newValue.m_isLocked = it->second.m_isLocked;
+ }
+
+ // set new option value
+ newValue.m_value = value;
+ m_options[name] = newValue;
+}
+
+//! \param name The name of the option to remove.
+//!
+void OptionDictionary::deleteOption(const std::string & name)
+{
+ if (m_options.find(name) != m_options.end())
+ {
+ if (m_options[name].m_value)
+ {
+ delete m_options[name].m_value;
+ }
+ m_options.erase(name);
+ }
+}
+
+//! \param name Name of the option to query.
+//!
+//! \return True if the option is locked, false if unlocked or not present.
+//!
+bool OptionDictionary::isOptionLocked(const std::string & name) const
+{
+ option_map_t::const_iterator it = m_options.find(name);
+ if (it != m_options.end())
+ {
+ return it->second.m_isLocked;
+ }
+
+ return false;
+}
+
+//! \param name Name of the option to lock.
+//!
+void OptionDictionary::lockOption(const std::string & name)
+{
+ if (!hasOption(name))
+ {
+ m_options[name].m_value = 0;
+ }
+
+ m_options[name].m_isLocked = true;
+}
+
+//! \param name Name of the option to unlock.
+//!
+void OptionDictionary::unlockOption(const std::string & name)
+{
+ if (!hasOption(name))
+ {
+ m_options[name].m_value = 0;
+ }
+
+ m_options[name].m_isLocked = false;
+}
+
+
+//! Simply calls getOption().
+//!
+const Value * OptionDictionary::operator [] (const std::string & name) const
+{
+ return getOption(name);
+}
+
--- /dev/null
+/*
+ * File: OptionDictionary.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_OptionDictionary_h_)
+#define _OptionDictionary_h_
+
+#include "OptionContext.h"
+#include <map>
+
+namespace elftosb
+{
+
+/*!
+ * \brief Concrete implementation of OptionContext.
+ *
+ * This context subclass supports having a parent context. If an option is not
+ * found in the receiving instance, the request is passed to the parent.
+ * The hasOption() and getOption() methods will ask up the parent chain
+ * if the requested option does not exist in the receiving instance.
+ * But the setOption() and deleteOption() methods only operate locally,
+ * on the instance on which they were called. This allows a caller to
+ * locally override an option value without affecting any of the parent
+ * contexts.
+ */
+class OptionDictionary : public OptionContext
+{
+public:
+ //! \brief Default constructor.
+ OptionDictionary() : m_parent(0) {}
+
+ //! \brief Constructor taking a parent context.
+ OptionDictionary(OptionContext * parent) : m_parent(parent) {}
+
+ //! \brief Destructor.
+ ~OptionDictionary();
+
+ //! \name Parents
+ //@{
+ //! \brief Returns the current parent context.
+ //! \return The current parent context instance.
+ //! \retval NULL No parent has been set.
+ inline OptionContext * getParent() const { return m_parent; }
+
+ //! \brief Change the parent context.
+ //! \param newParent The parent context object. May be NULL, in which case
+ //! the object will no longer have a parent context.
+ inline void setParent(OptionContext * newParent) { m_parent = newParent; }
+ //@}
+
+ //! \name Options
+ //@{
+ //! \brief Detemine whether the named option is present in the table.
+ virtual bool hasOption(const std::string & name) const;
+
+ //! \brief Returns the option's value.
+ virtual const Value * getOption(const std::string & name) const;
+
+ //! \brief Adds or changes an option's value.
+ virtual void setOption(const std::string & name, Value * value);
+
+ //! \brief Removes an option from the table.
+ virtual void deleteOption(const std::string & name);
+ //@}
+
+ //! \name Locking
+ //@{
+ //! \brief Returns true if the specified option is locked from further changes.
+ bool isOptionLocked(const std::string & name) const;
+
+ //! \brief Prevent further modifications of an option's value.
+ void lockOption(const std::string & name);
+
+ //! \brief Allow an option to be changed.
+ void unlockOption(const std::string & name);
+ //@}
+
+ //! \name Operators
+ //@{
+ //! \brief Indexing operator; returns the value for the option \a name.
+ const Value * operator [] (const std::string & name) const;
+ //@}
+
+protected:
+ OptionContext * m_parent; //!< Our parent context.
+
+ /*!
+ * \brief Information about one option's value.
+ */
+ struct OptionValue
+ {
+ Value * m_value; //!< The object for this option's value.
+ bool m_isLocked; //!< True if this value is locked from further changes.
+
+ //! \brief Constructor.
+ OptionValue() : m_value(0), m_isLocked(false) {}
+ };
+
+ typedef std::map<std::string, OptionValue> option_map_t; //!< Map from option name to value.
+ option_map_t m_options; //!< The option dictionary.
+};
+
+}; // namespace elftosb
+
+#endif // _OptionDictionary_h_
--- /dev/null
+/*
+ * File: OutputSection.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "OutputSection.h"
+
--- /dev/null
+/*
+ * File: OutputSection.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_OutputSection_h_)
+#define _OutputSection_h_
+
+#include "Operation.h"
+#include "smart_ptr.h"
+#include "Blob.h"
+#include "OptionContext.h"
+
+namespace elftosb
+{
+
+/*!
+ * @brief Base class for data model of sections of the output file.
+ */
+class OutputSection
+{
+public:
+ OutputSection() : m_id(0), m_options(0) {}
+ OutputSection(uint32_t identifier) : m_id(identifier), m_options(0) {}
+ virtual ~OutputSection() {}
+
+ void setIdentifier(uint32_t identifier) { m_id = identifier; }
+ uint32_t getIdentifier() const { return m_id; }
+
+ //! \brief Set the option context.
+ //!
+ //! The output section object will assume ownership of the option context
+ //! and delete it when the section is deleted.
+ inline void setOptions(OptionContext * context) { m_options = context; }
+
+ //! \brief Return the option context.
+ inline const OptionContext * getOptions() const { return m_options; }
+
+protected:
+ uint32_t m_id; //!< Unique identifier.
+ smart_ptr<OptionContext> m_options; //!< Options associated with just this section.
+};
+
+/*!
+ * @brief A section of the output that contains boot operations.
+ */
+class OperationSequenceSection : public OutputSection
+{
+public:
+ OperationSequenceSection() : OutputSection() {}
+ OperationSequenceSection(uint32_t identifier) : OutputSection(identifier) {}
+
+ OperationSequence & getSequence() { return m_sequence; }
+
+protected:
+ OperationSequence m_sequence;
+};
+
+/*!
+ * @brief A section of the output file that contains arbitrary binary data.
+ */
+class BinaryDataSection : public OutputSection, public Blob
+{
+public:
+ BinaryDataSection() : OutputSection(), Blob() {}
+ BinaryDataSection(uint32_t identifier) : OutputSection(identifier), Blob() {}
+};
+
+}; // namespace elftosb
+
+#endif // _OutputSection_h_
--- /dev/null
+/*
+ * File: Random.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "Random.h"
+#include <stdexcept>
+
+#ifdef WIN32
+ #ifndef _WIN32_WINNT
+ #define _WIN32_WINNT 0x0400
+ #endif
+ #include <windows.h>
+ #include <wincrypt.h>
+#else // WIN32
+ #include <errno.h>
+ #include <fcntl.h>
+ #include <unistd.h>
+#endif // WIN32
+
+
+
+#ifdef WIN32
+
+MicrosoftCryptoProvider::MicrosoftCryptoProvider()
+{
+ if(!CryptAcquireContext(&m_hProvider, 0, 0, PROV_RSA_FULL, CRYPT_VERIFYCONTEXT))
+ {
+ throw std::runtime_error("CryptAcquireContext");
+ }
+}
+
+MicrosoftCryptoProvider::~MicrosoftCryptoProvider()
+{
+ CryptReleaseContext(m_hProvider, 0);
+}
+
+#endif // WIN32
+
+RandomNumberGenerator::RandomNumberGenerator()
+{
+#ifndef WIN32
+ m_fd = open("/dev/urandom",O_RDONLY);
+ if (m_fd == -1)
+ {
+ throw std::runtime_error("open /dev/urandom");
+ }
+#endif // WIN32
+}
+
+RandomNumberGenerator::~RandomNumberGenerator()
+{
+#ifndef WIN32
+ close(m_fd);
+#endif // WIN32
+}
+
+uint8_t RandomNumberGenerator::generateByte()
+{
+ uint8_t result;
+ generateBlock(&result, 1);
+ return result;
+}
+
+void RandomNumberGenerator::generateBlock(uint8_t * output, unsigned count)
+{
+#ifdef WIN32
+# ifdef WORKAROUND_MS_BUG_Q258000
+ static MicrosoftCryptoProvider m_provider;
+# endif
+ if (!CryptGenRandom(m_provider.GetProviderHandle(), count, output))
+ {
+ throw std::runtime_error("CryptGenRandom");
+ }
+#else // WIN32
+ if (read(m_fd, output, count) != count)
+ {
+ throw std::runtime_error("read /dev/urandom");
+ }
+#endif // WIN32
+}
+
+
--- /dev/null
+/*
+ * File: Random.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_Random_h_)
+#define _Random_h_
+
+#include "stdafx.h"
+
+#ifdef WIN32
+/*!
+ * This class is from the crypto++ library.
+ */
+class MicrosoftCryptoProvider
+{
+public:
+ MicrosoftCryptoProvider();
+ ~MicrosoftCryptoProvider();
+#if defined(_WIN64)
+ typedef unsigned __int64 ProviderHandle; // type HCRYPTPROV, avoid #include <windows.h>
+#else
+ typedef unsigned long ProviderHandle;
+#endif
+ ProviderHandle GetProviderHandle() const {return m_hProvider;}
+private:
+ ProviderHandle m_hProvider;
+};
+
+#pragma comment(lib, "advapi32.lib")
+#endif // WIN32
+
+/*!
+ * Encapsulates the Windows CryptoAPI's CryptGenRandom or /dev/urandom on Unix systems.
+ */
+class RandomNumberGenerator
+{
+public:
+ RandomNumberGenerator();
+ ~RandomNumberGenerator();
+
+ uint8_t generateByte();
+ void generateBlock(uint8_t * output, unsigned count);
+
+protected:
+#ifdef WIN32
+# ifndef WORKAROUND_MS_BUG_Q258000
+ MicrosoftCryptoProvider m_provider;
+# endif
+#else // WIN32
+ int m_fd;
+#endif // WIN32
+};
+
+
+#endif // _Random_h_
--- /dev/null
+/*
+ * File: RijndaelCBCMAC.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "RijndaelCBCMAC.h"
+#include "rijndael.h"
+#include <assert.h>
+#include "Logging.h"
+
+void logHexArray(Logger::log_level_t level, const uint8_t * bytes, unsigned count);
+
+//! \param key The key to use as the CBC-MAC secret.
+//! \param iv Initialization vector. Defaults to zero if not provided.
+RijndaelCBCMAC::RijndaelCBCMAC(const AESKey<128> & key, const uint8_t * iv)
+: m_key(key)
+{
+ if (iv)
+ {
+ memcpy(m_mac, iv, sizeof(m_mac));
+ }
+ else
+ {
+ memset(m_mac, 0, sizeof(m_mac));
+ }
+}
+
+//! \param data Pointer to data to process.
+//! \param length Number of bytes to process. Must be evenly divisible by #BLOCK_SIZE.
+void RijndaelCBCMAC::update(const uint8_t * data, unsigned length)
+{
+ assert(length % BLOCK_SIZE == 0);
+ unsigned blocks = length / BLOCK_SIZE;
+ while (blocks--)
+ {
+ updateOneBlock(data);
+ data += BLOCK_SIZE;
+ }
+}
+
+//! It appears that some forms of CBC-MAC encrypt the final output block again in
+//! order to protect against a plaintext attack. This method is a placeholder for
+//! such an operation, but it currently does nothing.
+void RijndaelCBCMAC::finalize()
+{
+}
+
+//! On entry the current value of m_mac becomes the initialization vector
+//! for the CBC encryption of this block. The output of the encryption then
+//! becomes the new MAC, which is stored in m_mac.
+void RijndaelCBCMAC::updateOneBlock(const uint8_t * data)
+{
+ Rijndael cipher;
+ cipher.init(Rijndael::CBC, Rijndael::Encrypt, m_key, Rijndael::Key16Bytes, m_mac);
+ cipher.blockEncrypt(data, BLOCK_SIZE * 8, m_mac); // size is in bits
+
+// Log::log(Logger::DEBUG2, "CBC-MAC output block:\n");
+// logHexArray(Logger::DEBUG2, (const uint8_t *)&m_mac, sizeof(m_mac));
+}
+
+/*!
+ * \brief Log an array of bytes as hex.
+ */
+void logHexArray(Logger::log_level_t level, const uint8_t * bytes, unsigned count)
+{
+ Log::SetOutputLevel leveler(level);
+// Log::log(" ");
+ unsigned i;
+ for (i = 0; i < count; ++i, ++bytes)
+ {
+ if ((i % 16 == 0) && (i < count - 1))
+ {
+ if (i != 0)
+ {
+ Log::log("\n");
+ }
+ Log::log(" 0x%04x: ", i);
+ }
+ Log::log("%02x ", *bytes & 0xff);
+ }
+
+ Log::log("\n");
+}
+
--- /dev/null
+/*
+ * File: RijndaelCBCMAC.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_RijndaelCBCMAC_h_)
+#define _RijndaelCBCMAC_h_
+
+#include "AESKey.h"
+#include <string.h>
+
+/*!
+ * \brief Class to compute CBC-MAC using the AES/Rijndael cipher.
+ *
+ * Currently only supports 128-bit keys and block sizes.
+ */
+class RijndaelCBCMAC
+{
+public:
+ enum
+ {
+ BLOCK_SIZE = 16 //!< Number of bytes in one cipher block.
+ };
+
+ //! The cipher block data type.
+ typedef uint8_t block_t[BLOCK_SIZE];
+
+public:
+ //! \brief Default constructor.
+ //!
+ //! The key and IV are both set to zero.
+ RijndaelCBCMAC() {}
+
+ //! \brief Constructor.
+ RijndaelCBCMAC(const AESKey<128> & key, const uint8_t * iv=0);
+
+ //! \brief Process data.
+ void update(const uint8_t * data, unsigned length);
+
+ //! \brief Signal that all data has been processed.
+ void finalize();
+
+ //! \brief Returns a reference to the current MAC value.
+ const block_t & getMAC() const { return m_mac; }
+
+ //! \brief Assignment operator.
+ RijndaelCBCMAC & operator = (const RijndaelCBCMAC & other)
+ {
+ m_key = other.m_key;
+ memcpy(m_mac, other.m_mac, sizeof(m_mac));
+ return *this;
+ }
+
+protected:
+ AESKey<128> m_key; //!< 128-bit key to use for the CBC-MAC.
+ block_t m_mac; //!< Current message authentication code value.
+
+ void updateOneBlock(const uint8_t * data);
+};
+
+#endif // _RijndaelCBCMAC_h_
--- /dev/null
+/*
+ 100% free public domain implementation of the SHA-1 algorithm
+ by Dominik Reichl <dominik.reichl@t-online.de>
+ Web: http://www.dominik-reichl.de/
+
+ Version 1.6 - 2005-02-07 (thanks to Howard Kapustein for patches)
+ - You can set the endianness in your files, no need to modify the
+ header file of the CSHA1 class any more
+ - Aligned data support
+ - Made support/compilation of the utility functions (ReportHash
+ and HashFile) optional (useful, if bytes count, for example in
+ embedded environments)
+
+ Version 1.5 - 2005-01-01
+ - 64-bit compiler compatibility added
+ - Made variable wiping optional (define SHA1_WIPE_VARIABLES)
+ - Removed unnecessary variable initializations
+ - ROL32 improvement for the Microsoft compiler (using _rotl)
+
+ ======== Test Vectors (from FIPS PUB 180-1) ========
+
+ SHA1("abc") =
+ A9993E36 4706816A BA3E2571 7850C26C 9CD0D89D
+
+ SHA1("abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq") =
+ 84983E44 1C3BD26E BAAE4AA1 F95129E5 E54670F1
+
+ SHA1(A million repetitions of "a") =
+ 34AA973C D4C4DAA4 F61EEB2B DBAD2731 6534016F
+*/
+
+#include "SHA1.h"
+
+#ifdef SHA1_UTILITY_FUNCTIONS
+#define SHA1_MAX_FILE_BUFFER 8000
+#endif
+
+// Rotate x bits to the left
+#ifndef ROL32
+#ifdef _MSC_VER
+#define ROL32(_val32, _nBits) _rotl(_val32, _nBits)
+#else
+#define ROL32(_val32, _nBits) (((_val32)<<(_nBits))|((_val32)>>(32-(_nBits))))
+#endif
+#endif
+
+#ifdef SHA1_LITTLE_ENDIAN
+#define SHABLK0(i) (m_block->l[i] = \
+ (ROL32(m_block->l[i],24) & 0xFF00FF00) | (ROL32(m_block->l[i],8) & 0x00FF00FF))
+#else
+#define SHABLK0(i) (m_block->l[i])
+#endif
+
+#define SHABLK(i) (m_block->l[i&15] = ROL32(m_block->l[(i+13)&15] ^ m_block->l[(i+8)&15] \
+ ^ m_block->l[(i+2)&15] ^ m_block->l[i&15],1))
+
+// SHA-1 rounds
+#define _R0(v,w,x,y,z,i) { z+=((w&(x^y))^y)+SHABLK0(i)+0x5A827999+ROL32(v,5); w=ROL32(w,30); }
+#define _R1(v,w,x,y,z,i) { z+=((w&(x^y))^y)+SHABLK(i)+0x5A827999+ROL32(v,5); w=ROL32(w,30); }
+#define _R2(v,w,x,y,z,i) { z+=(w^x^y)+SHABLK(i)+0x6ED9EBA1+ROL32(v,5); w=ROL32(w,30); }
+#define _R3(v,w,x,y,z,i) { z+=(((w|x)&y)|(w&x))+SHABLK(i)+0x8F1BBCDC+ROL32(v,5); w=ROL32(w,30); }
+#define _R4(v,w,x,y,z,i) { z+=(w^x^y)+SHABLK(i)+0xCA62C1D6+ROL32(v,5); w=ROL32(w,30); }
+
+CSHA1::CSHA1()
+{
+ m_block = (SHA1_WORKSPACE_BLOCK *)m_workspace;
+
+ Reset();
+}
+
+CSHA1::~CSHA1()
+{
+ Reset();
+}
+
+void CSHA1::Reset()
+{
+ // SHA1 initialization constants
+ m_state[0] = 0x67452301;
+ m_state[1] = 0xEFCDAB89;
+ m_state[2] = 0x98BADCFE;
+ m_state[3] = 0x10325476;
+ m_state[4] = 0xC3D2E1F0;
+
+ m_count[0] = 0;
+ m_count[1] = 0;
+}
+
+void CSHA1::Transform(uint32_t *state, const uint8_t *buffer)
+{
+ // Copy state[] to working vars
+ uint32_t a = state[0], b = state[1], c = state[2], d = state[3], e = state[4];
+
+ memcpy(m_block, buffer, 64);
+
+ // 4 rounds of 20 operations each. Loop unrolled.
+ _R0(a,b,c,d,e, 0); _R0(e,a,b,c,d, 1); _R0(d,e,a,b,c, 2); _R0(c,d,e,a,b, 3);
+ _R0(b,c,d,e,a, 4); _R0(a,b,c,d,e, 5); _R0(e,a,b,c,d, 6); _R0(d,e,a,b,c, 7);
+ _R0(c,d,e,a,b, 8); _R0(b,c,d,e,a, 9); _R0(a,b,c,d,e,10); _R0(e,a,b,c,d,11);
+ _R0(d,e,a,b,c,12); _R0(c,d,e,a,b,13); _R0(b,c,d,e,a,14); _R0(a,b,c,d,e,15);
+ _R1(e,a,b,c,d,16); _R1(d,e,a,b,c,17); _R1(c,d,e,a,b,18); _R1(b,c,d,e,a,19);
+ _R2(a,b,c,d,e,20); _R2(e,a,b,c,d,21); _R2(d,e,a,b,c,22); _R2(c,d,e,a,b,23);
+ _R2(b,c,d,e,a,24); _R2(a,b,c,d,e,25); _R2(e,a,b,c,d,26); _R2(d,e,a,b,c,27);
+ _R2(c,d,e,a,b,28); _R2(b,c,d,e,a,29); _R2(a,b,c,d,e,30); _R2(e,a,b,c,d,31);
+ _R2(d,e,a,b,c,32); _R2(c,d,e,a,b,33); _R2(b,c,d,e,a,34); _R2(a,b,c,d,e,35);
+ _R2(e,a,b,c,d,36); _R2(d,e,a,b,c,37); _R2(c,d,e,a,b,38); _R2(b,c,d,e,a,39);
+ _R3(a,b,c,d,e,40); _R3(e,a,b,c,d,41); _R3(d,e,a,b,c,42); _R3(c,d,e,a,b,43);
+ _R3(b,c,d,e,a,44); _R3(a,b,c,d,e,45); _R3(e,a,b,c,d,46); _R3(d,e,a,b,c,47);
+ _R3(c,d,e,a,b,48); _R3(b,c,d,e,a,49); _R3(a,b,c,d,e,50); _R3(e,a,b,c,d,51);
+ _R3(d,e,a,b,c,52); _R3(c,d,e,a,b,53); _R3(b,c,d,e,a,54); _R3(a,b,c,d,e,55);
+ _R3(e,a,b,c,d,56); _R3(d,e,a,b,c,57); _R3(c,d,e,a,b,58); _R3(b,c,d,e,a,59);
+ _R4(a,b,c,d,e,60); _R4(e,a,b,c,d,61); _R4(d,e,a,b,c,62); _R4(c,d,e,a,b,63);
+ _R4(b,c,d,e,a,64); _R4(a,b,c,d,e,65); _R4(e,a,b,c,d,66); _R4(d,e,a,b,c,67);
+ _R4(c,d,e,a,b,68); _R4(b,c,d,e,a,69); _R4(a,b,c,d,e,70); _R4(e,a,b,c,d,71);
+ _R4(d,e,a,b,c,72); _R4(c,d,e,a,b,73); _R4(b,c,d,e,a,74); _R4(a,b,c,d,e,75);
+ _R4(e,a,b,c,d,76); _R4(d,e,a,b,c,77); _R4(c,d,e,a,b,78); _R4(b,c,d,e,a,79);
+
+ // Add the working vars back into state
+ state[0] += a;
+ state[1] += b;
+ state[2] += c;
+ state[3] += d;
+ state[4] += e;
+
+ // Wipe variables
+#ifdef SHA1_WIPE_VARIABLES
+ a = b = c = d = e = 0;
+#endif
+}
+
+// Use this function to hash in binary data and strings
+void CSHA1::Update(const uint8_t *data, uint32_t len)
+{
+ uint32_t i, j;
+
+ j = (m_count[0] >> 3) & 63;
+
+ if((m_count[0] += len << 3) < (len << 3)) m_count[1]++;
+
+ m_count[1] += (len >> 29);
+
+ if((j + len) > 63)
+ {
+ i = 64 - j;
+ memcpy(&m_buffer[j], data, i);
+ Transform(m_state, m_buffer);
+
+ for( ; i + 63 < len; i += 64) Transform(m_state, &data[i]);
+
+ j = 0;
+ }
+ else i = 0;
+
+ memcpy(&m_buffer[j], &data[i], len - i);
+}
+
+#ifdef SHA1_UTILITY_FUNCTIONS
+// Hash in file contents
+bool CSHA1::HashFile(char *szFileName)
+{
+ unsigned long ulFileSize, ulRest, ulBlocks;
+ unsigned long i;
+ uint8_t uData[SHA1_MAX_FILE_BUFFER];
+ FILE *fIn;
+
+ if(szFileName == NULL) return false;
+
+ fIn = fopen(szFileName, "rb");
+ if(fIn == NULL) return false;
+
+ fseek(fIn, 0, SEEK_END);
+ ulFileSize = (unsigned long)ftell(fIn);
+ fseek(fIn, 0, SEEK_SET);
+
+ if(ulFileSize != 0)
+ {
+ ulBlocks = ulFileSize / SHA1_MAX_FILE_BUFFER;
+ ulRest = ulFileSize % SHA1_MAX_FILE_BUFFER;
+ }
+ else
+ {
+ ulBlocks = 0;
+ ulRest = 0;
+ }
+
+ for(i = 0; i < ulBlocks; i++)
+ {
+ fread(uData, 1, SHA1_MAX_FILE_BUFFER, fIn);
+ Update((uint8_t *)uData, SHA1_MAX_FILE_BUFFER);
+ }
+
+ if(ulRest != 0)
+ {
+ fread(uData, 1, ulRest, fIn);
+ Update((uint8_t *)uData, ulRest);
+ }
+
+ fclose(fIn); fIn = NULL;
+ return true;
+}
+#endif
+
+void CSHA1::Final()
+{
+ uint32_t i;
+ uint8_t finalcount[8];
+
+ for(i = 0; i < 8; i++)
+ finalcount[i] = (uint8_t)((m_count[((i >= 4) ? 0 : 1)]
+ >> ((3 - (i & 3)) * 8) ) & 255); // Endian independent
+
+ Update((uint8_t *)"\200", 1);
+
+ while ((m_count[0] & 504) != 448)
+ Update((uint8_t *)"\0", 1);
+
+ Update(finalcount, 8); // Cause a SHA1Transform()
+
+ for(i = 0; i < 20; i++)
+ {
+ m_digest[i] = (uint8_t)((m_state[i >> 2] >> ((3 - (i & 3)) * 8) ) & 255);
+ }
+
+ // Wipe variables for security reasons
+#ifdef SHA1_WIPE_VARIABLES
+ i = 0;
+ memset(m_buffer, 0, 64);
+ memset(m_state, 0, 20);
+ memset(m_count, 0, 8);
+ memset(finalcount, 0, 8);
+ Transform(m_state, m_buffer);
+#endif
+}
+
+#ifdef SHA1_UTILITY_FUNCTIONS
+// Get the final hash as a pre-formatted string
+void CSHA1::ReportHash(char *szReport, unsigned char uReportType)
+{
+ unsigned char i;
+ char szTemp[16];
+
+ if(szReport == NULL) return;
+
+ if(uReportType == REPORT_HEX)
+ {
+ sprintf(szTemp, "%02X", m_digest[0]);
+ strcat(szReport, szTemp);
+
+ for(i = 1; i < 20; i++)
+ {
+ sprintf(szTemp, " %02X", m_digest[i]);
+ strcat(szReport, szTemp);
+ }
+ }
+ else if(uReportType == REPORT_DIGIT)
+ {
+ sprintf(szTemp, "%u", m_digest[0]);
+ strcat(szReport, szTemp);
+
+ for(i = 1; i < 20; i++)
+ {
+ sprintf(szTemp, " %u", m_digest[i]);
+ strcat(szReport, szTemp);
+ }
+ }
+ else strcpy(szReport, "Error: Unknown report type!");
+}
+#endif
+
+// Get the raw message digest
+void CSHA1::GetHash(uint8_t *puDest)
+{
+ memcpy(puDest, m_digest, 20);
+}
--- /dev/null
+/*
+ 100% free public domain implementation of the SHA-1 algorithm
+ by Dominik Reichl <dominik.reichl@t-online.de>
+ Web: http://www.dominik-reichl.de/
+
+ Version 1.6 - 2005-02-07 (thanks to Howard Kapustein for patches)
+ - You can set the endianness in your files, no need to modify the
+ header file of the CSHA1 class any more
+ - Aligned data support
+ - Made support/compilation of the utility functions (ReportHash
+ and HashFile) optional (useful, if bytes count, for example in
+ embedded environments)
+
+ Version 1.5 - 2005-01-01
+ - 64-bit compiler compatibility added
+ - Made variable wiping optional (define SHA1_WIPE_VARIABLES)
+ - Removed unnecessary variable initializations
+ - ROL32 improvement for the Microsoft compiler (using _rotl)
+
+ ======== Test Vectors (from FIPS PUB 180-1) ========
+
+ SHA1("abc") =
+ A9993E36 4706816A BA3E2571 7850C26C 9CD0D89D
+
+ SHA1("abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq") =
+ 84983E44 1C3BD26E BAAE4AA1 F95129E5 E54670F1
+
+ SHA1(A million repetitions of "a") =
+ 34AA973C D4C4DAA4 F61EEB2B DBAD2731 6534016F
+*/
+
+#ifndef ___SHA1_HDR___
+#define ___SHA1_HDR___
+
+#if !defined(SHA1_UTILITY_FUNCTIONS) && !defined(SHA1_NO_UTILITY_FUNCTIONS)
+#define SHA1_UTILITY_FUNCTIONS
+#endif
+
+#include <memory.h> // Needed for memset and memcpy
+#include "stdafx.h"
+
+#ifdef SHA1_UTILITY_FUNCTIONS
+#include <stdio.h> // Needed for file access and sprintf
+#include <string.h> // Needed for strcat and strcpy
+#endif
+
+#ifdef _MSC_VER
+#include <stdlib.h>
+#endif
+
+// You can define the endian mode in your files, without modifying the SHA1
+// source files. Just #define SHA1_LITTLE_ENDIAN or #define SHA1_BIG_ENDIAN
+// in your files, before including the SHA1.h header file. If you don't
+// define anything, the class defaults to little endian.
+
+#if !defined(SHA1_LITTLE_ENDIAN) && !defined(SHA1_BIG_ENDIAN)
+#define SHA1_LITTLE_ENDIAN
+#endif
+
+// Same here. If you want variable wiping, #define SHA1_WIPE_VARIABLES, if
+// not, #define SHA1_NO_WIPE_VARIABLES. If you don't define anything, it
+// defaults to wiping.
+
+#if !defined(SHA1_WIPE_VARIABLES) && !defined(SHA1_NO_WIPE_VARIABLES)
+#define SHA1_WIPE_VARIABLES
+#endif
+
+/////////////////////////////////////////////////////////////////////////////
+// Define 8- and 32-bit variables
+
+//#ifndef uint32_t
+//
+//#ifdef _MSC_VER
+//
+//#define uint8_t unsigned __int8
+//#define uint32_t unsigned __int32
+//
+//#else
+//
+//#define uint8_t unsigned char
+//
+//#if (ULONG_MAX == 0xFFFFFFFF)
+//#define uint32_t unsigned long
+//#else
+//#define uint32_t unsigned int
+//#endif
+//
+//#endif
+//#endif
+
+/////////////////////////////////////////////////////////////////////////////
+// Declare SHA1 workspace
+
+typedef union
+{
+ uint8_t c[64];
+ uint32_t l[16];
+} SHA1_WORKSPACE_BLOCK;
+
+class CSHA1
+{
+public:
+#ifdef SHA1_UTILITY_FUNCTIONS
+ // Two different formats for ReportHash(...)
+ enum
+ {
+ REPORT_HEX = 0,
+ REPORT_DIGIT = 1
+ };
+#endif
+
+ // Constructor and Destructor
+ CSHA1();
+ ~CSHA1();
+
+ uint32_t m_state[5];
+ uint32_t m_count[2];
+ uint32_t __reserved1[1];
+ uint8_t m_buffer[64];
+ uint8_t m_digest[20];
+ uint32_t __reserved2[3];
+
+ void Reset();
+
+ // Update the hash value
+ void Update(const uint8_t *data, uint32_t len);
+#ifdef SHA1_UTILITY_FUNCTIONS
+ bool HashFile(char *szFileName);
+#endif
+
+ // Finalize hash and report
+ void Final();
+
+ // Report functions: as pre-formatted and raw data
+#ifdef SHA1_UTILITY_FUNCTIONS
+ void ReportHash(char *szReport, unsigned char uReportType = REPORT_HEX);
+#endif
+ void GetHash(uint8_t *puDest);
+
+private:
+ // Private SHA-1 transformation
+ void Transform(uint32_t *state, const uint8_t *buffer);
+
+ // Member variables
+ uint8_t m_workspace[64];
+ SHA1_WORKSPACE_BLOCK *m_block; // SHA1 pointer to the byte array above
+};
+
+#endif
--- /dev/null
+/*
+ * File: SRecordSourceFile.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "SRecordSourceFile.h"
+#include "Logging.h"
+#include "smart_ptr.h"
+#include <assert.h>
+#include <string.h>
+enum
+{
+ //! Size in bytes of the buffer used to collect S-record data records
+ //! before adding them to the executable image. Currently 64KB.
+ COLLECTION_BUFFER_SIZE = 64 * 1024
+};
+
+using namespace elftosb;
+
+SRecordSourceFile::SRecordSourceFile(const std::string & path)
+: SourceFile(path), m_image(0), m_hasEntryRecord(false)
+{
+}
+
+bool SRecordSourceFile::isSRecordFile(std::istream & stream)
+{
+ StSRecordFile srec(stream);
+ return srec.isSRecordFile();
+}
+
+void SRecordSourceFile::open()
+{
+ SourceFile::open();
+
+ // create file parser and examine file
+ m_file = new StSRecordFile(*m_stream);
+ m_file->parse();
+
+ // build an image of the file
+ m_image = new StExecutableImage();
+ buildMemoryImage();
+
+ // dispose of file parser object
+ delete m_file;
+ m_file = 0;
+}
+
+void SRecordSourceFile::close()
+{
+ assert(m_image);
+
+ SourceFile::close();
+
+ // dispose of memory image
+ delete m_image;
+ m_image = 0;
+}
+
+//! \pre The file must be open before this method can be called.
+//!
+DataSource * SRecordSourceFile::createDataSource()
+{
+ assert(m_image);
+ return new MemoryImageDataSource(m_image);
+}
+
+//! \retval true The file has an S7, S8, or S9 record.
+//! \retval false No entry point is available.
+bool SRecordSourceFile::hasEntryPoint()
+{
+ return m_hasEntryRecord;
+}
+
+//! If no entry point is available then 0 is returned instead. The method scans
+//! the records in the file looking for S7, S8, or S9 records. Thus, 16-bit,
+//! 24-bit, and 32-bit entry point records are supported.
+//!
+//! \return Entry point address.
+//! \retval 0 No entry point is available.
+uint32_t SRecordSourceFile::getEntryPointAddress()
+{
+ if (m_hasEntryRecord)
+ {
+ // the address in the record is the entry point
+ Log::log(Logger::DEBUG2, "entry point address is 0x%08x\n", m_entryRecord.m_address);
+ return m_entryRecord.m_address;
+ }
+
+ return 0;
+}
+
+//! Scans the S-records of the file looking for data records. These are S3, S2, or
+//! S1 records. The contents of these records are added to an StExecutableImage
+//! object, which coalesces the individual records into contiguous regions of
+//! memory.
+//!
+//! Also looks for S7, S8, or S9 records that contain the entry point. The first
+//! match of one of these records is saved off into the #m_entryRecord member.
+//!
+//! \pre The #m_file member must be valid.
+//! \pre The #m_image member variable must have been instantiated.
+void SRecordSourceFile::buildMemoryImage()
+{
+ assert(m_file);
+ assert(m_image);
+
+ // Clear the entry point related members.
+ m_hasEntryRecord = false;
+ memset(&m_entryRecord, 0, sizeof(m_entryRecord));
+
+ // Allocate buffer to hold data before adding it to the executable image.
+ // Contiguous records are added to this buffer. When overflowed or when a
+ // non-contiguous record is encountered the buffer is added to the executable
+ // image where it will be coalesced further. We don't add records individually
+ // to the image because coalescing record by record is very slow.
+ smart_array_ptr<uint8_t> buffer = new uint8_t[COLLECTION_BUFFER_SIZE];
+ unsigned startAddress;
+ unsigned nextAddress;
+ unsigned dataLength = 0;
+
+ // process SRecords
+ StSRecordFile::const_iterator it = m_file->getBegin();
+ for (; it != m_file->getEnd(); it++)
+ {
+ const StSRecordFile::SRecord & theRecord = *it;
+
+ // only handle S3,2,1 records
+ bool isDataRecord = theRecord.m_type == 3 || theRecord.m_type == 2 || theRecord.m_type == 1;
+ bool hasData = theRecord.m_data && theRecord.m_dataCount;
+ if (isDataRecord && hasData)
+ {
+ // If this record's data would overflow the collection buffer, or if the
+ // record is not contiguous with the rest of the data in the collection
+ // buffer, then flush the buffer to the executable image and restart.
+ if (dataLength && ((dataLength + theRecord.m_dataCount > COLLECTION_BUFFER_SIZE) || (theRecord.m_address != nextAddress)))
+ {
+ m_image->addTextRegion(startAddress, buffer, dataLength);
+
+ dataLength = 0;
+ }
+
+ // Capture addresses when starting an empty buffer.
+ if (dataLength == 0)
+ {
+ startAddress = theRecord.m_address;
+ nextAddress = startAddress;
+ }
+
+ // Copy record data into place in the collection buffer and update
+ // size and address.
+ memcpy(&buffer[dataLength], theRecord.m_data, theRecord.m_dataCount);
+ dataLength += theRecord.m_dataCount;
+ nextAddress += theRecord.m_dataCount;
+ }
+ else if (!m_hasEntryRecord)
+ {
+ // look for S7,8,9 records
+ bool isEntryPointRecord = theRecord.m_type == 7 || theRecord.m_type == 8 || theRecord.m_type == 9;
+ if (isEntryPointRecord)
+ {
+ // save off the entry point record so we don't have to scan again
+ memcpy(&m_entryRecord, &theRecord, sizeof(m_entryRecord));
+ m_hasEntryRecord = true;
+ }
+ }
+ }
+
+ // Add any leftover data in the collection buffer to the executable image.
+ if (dataLength)
+ {
+ m_image->addTextRegion(startAddress, buffer, dataLength);
+ }
+}
+
--- /dev/null
+/*
+ * File: SRecordSourceFile.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_SRecordSourceFile_h_)
+#define _SRecordSourceFile_h_
+
+#include "SourceFile.h"
+#include "StSRecordFile.h"
+#include "StExecutableImage.h"
+
+namespace elftosb
+{
+
+/*!
+ * \brief Executable file in the Motorola S-record format.
+ *
+ * Instead of presenting each S-record in the file separately, this class
+ * builds up a memory image of all of the records. Records next to each other
+ * in memory are coalesced into a single memory region. The data source that
+ * is returned from createDataSource() exposes these regions as its segments.
+ *
+ * Because the S-record format does not support the concepts, no support is
+ * provided for named sections or symbols.
+ */
+class SRecordSourceFile : public SourceFile
+{
+public:
+ //! \brief Default constructor.
+ SRecordSourceFile(const std::string & path);
+
+ //! \brief Destructor.
+ virtual ~SRecordSourceFile() {}
+
+ //! \brief Test whether the \a stream contains a valid S-record file.
+ static bool isSRecordFile(std::istream & stream);
+
+ //! \name Opening and closing
+ //@{
+ //! \brief Opens the file.
+ virtual void open();
+
+ //! \brief Closes the file.
+ virtual void close();
+ //@}
+
+ //! \name Format capabilities
+ //@{
+ virtual bool supportsNamedSections() const { return false; }
+ virtual bool supportsNamedSymbols() const { return false; }
+ //@}
+
+ //! \name Data sources
+ //@{
+ //! \brief Returns data source for the entire file.
+ virtual DataSource * createDataSource();
+ //@}
+
+ //! \name Entry point
+ //@{
+ //! \brief Returns true if an entry point was set in the file.
+ virtual bool hasEntryPoint();
+
+ //! \brief Returns the entry point address.
+ virtual uint32_t getEntryPointAddress();
+ //@}
+
+protected:
+ StSRecordFile * m_file; //!< S-record parser instance.
+ StExecutableImage * m_image; //!< Memory image of the S-record file.
+ bool m_hasEntryRecord; //!< Whether an S7,8,9 record was found.
+ StSRecordFile::SRecord m_entryRecord; //!< Record for the entry point.
+
+protected:
+ //! \brief Build memory image of the S-record file.
+ void buildMemoryImage();
+};
+
+}; // namespace elftosb
+
+#endif // _SRecordSourceFile_h_
--- /dev/null
+/*
+ * File: SearchPath.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "SearchPath.h"
+#include <stdio.h>
+
+#if defined(WIN32)
+ #define PATH_SEP_CHAR '\\'
+ #define PATH_SEP_STRING "\\"
+#else
+ #define PATH_SEP_CHAR '/'
+ #define PATH_SEP_STRING "/"
+#endif
+
+PathSearcher * PathSearcher::s_searcher = NULL;
+
+//! This function will create the global path search object if it has
+//! not already been created.
+PathSearcher & PathSearcher::getGlobalSearcher()
+{
+ if (!s_searcher)
+ {
+ s_searcher = new PathSearcher;
+ }
+
+ return *s_searcher;
+}
+
+void PathSearcher::addSearchPath(std::string & path)
+{
+ m_paths.push_back(path);
+}
+
+//! The \a base path argument can be either a relative or absolute path. If the path
+//! is relative, then it is joined with search paths one after another until a matching
+//! file is located or all search paths are exhausted. If the \a base is absolute,
+//! only that path is tested and if invalid false is returned.
+//!
+//! \param base A path to the file that is to be found.
+//! \param targetType Currently ignored. In the future it will let you select whether to
+//! find a file or directory.
+//! \param searchCwd If set to true, the current working directory is searched before using
+//! any of the search paths. Otherwise only the search paths are considered.
+//! \param[out] result When true is returned this string is set to the first path at which
+//! a valid file was found.
+//!
+//! \retval true A matching file was found among the search paths. The contents of \a result
+//! are a valid path.
+//! \retval false No match could be made. \a result has been left unmodified.
+bool PathSearcher::search(const std::string & base, target_type_t targetType, bool searchCwd, std::string & result)
+{
+ FILE * tempFile;
+ bool absolute = isAbsolute(base);
+
+ // Try cwd first if requested. Same process applies to absolute paths.
+ if (absolute || searchCwd)
+ {
+ tempFile = fopen(base.c_str(), "r");
+ if (tempFile)
+ {
+ fclose(tempFile);
+ result = base;
+ return true;
+ }
+ }
+
+ // If the base path is absolute and the previous test failed, then we don't go any further.
+ if (absolute)
+ {
+ return false;
+ }
+
+ // Iterate over all search paths.
+ string_list_t::const_iterator it = m_paths.begin();
+ for (; it != m_paths.end(); ++it)
+ {
+ std::string searchPath = joinPaths(*it, base);
+
+ tempFile = fopen(searchPath.c_str(), "r");
+ if (tempFile)
+ {
+ fclose(tempFile);
+ result = searchPath;
+ return true;
+ }
+ }
+
+ // Couldn't find anything matching the base path.
+ return false;
+}
+
+bool PathSearcher::isAbsolute(const std::string & path)
+{
+#if __WIN32__
+ return path.size() >= 3 && path[1] == ':' && path[2] == '\\';
+#else
+ return path.size() >= 1 && path[0] == '/';
+#endif
+}
+
+std::string PathSearcher::joinPaths(const std::string & first, const std::string & second)
+{
+ // Start with first string.
+ std::string result = first;
+
+ // Add path separator if needed
+ if ((first[first.size() - 1] != PATH_SEP_CHAR) && (second[0] != PATH_SEP_CHAR))
+ {
+ result += PATH_SEP_STRING;
+ }
+
+ // Append the second string.
+ result += second;
+
+ // And return the whole mess.
+ return result;
+}
--- /dev/null
+/*
+ * File: SearchPath.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_searchpath_h_)
+#define _searchpath_h_
+
+#include <string>
+#include <list>
+
+/*!
+ * \brief Handles searching a list of paths for a file.
+ */
+class PathSearcher
+{
+public:
+ //!
+ enum _target_type
+ {
+ kFindFile,
+ kFindDirectory
+ };
+
+ //!
+ typedef enum _target_type target_type_t;
+
+protected:
+ //! Global search object singleton.
+ static PathSearcher * s_searcher;
+
+public:
+ //! \brief Access global path searching object.
+ static PathSearcher & getGlobalSearcher();
+
+public:
+ //! \brief Constructor.
+ PathSearcher() {}
+
+ //! \brief Add a new search path to the end of the list.
+ void addSearchPath(std::string & path);
+
+ //! \brief Attempts to locate a file by using the search paths.
+ bool search(const std::string & base, target_type_t targetType, bool searchCwd, std::string & result);
+
+protected:
+ typedef std::list<std::string> string_list_t; //!< Linked list of strings.
+ string_list_t m_paths; //!< Ordered list of paths to search.
+
+ //! \brief Returns whether \a path is absolute.
+ bool isAbsolute(const std::string & path);
+
+ //! \brief Combines two paths into a single one.
+ std::string joinPaths(const std::string & first, const std::string & second);
+};
+
+#endif // _searchpath_h_
--- /dev/null
+/*
+ * File: SourceFile.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "SourceFile.h"
+#include "ELFSourceFile.h"
+#include "SRecordSourceFile.h"
+#include <assert.h>
+#include "format_string.h"
+#include "SearchPath.h"
+
+using namespace elftosb;
+
+//! The supported file types are currently:
+//! - ELF files
+//! - Motorola S-record files
+//! - Binary files
+//!
+//! Any file that is not picked up by the other subclasses will result in a
+//! an instance of BinaryDataFile.
+//!
+//! \return An instance of the correct subclass of SourceFile for the given path.
+//!
+//! \exception std::runtime_error Thrown if the file cannot be opened.
+//!
+//! \see elftosb::ELFSourceFile
+//! \see elftosb::SRecordSourceFile
+//! \see elftosb::BinarySourceFile
+SourceFile * SourceFile::openFile(const std::string & path)
+{
+ // Search for file using search paths
+ std::string actualPath;
+ bool found = PathSearcher::getGlobalSearcher().search(path, PathSearcher::kFindFile, true, actualPath);
+ if (!found)
+ {
+ throw std::runtime_error(format_string("unable to find file %s\n", path.c_str()));
+ }
+
+ std::ifstream testStream(actualPath.c_str(), std::ios_base::in | std::ios_base::binary);
+ if (!testStream.is_open())
+ {
+ throw std::runtime_error(format_string("failed to open file: %s", actualPath.c_str()));
+ }
+
+ // catch exceptions so we can close the file stream
+ try
+ {
+ if (ELFSourceFile::isELFFile(testStream))
+ {
+ testStream.close();
+ return new ELFSourceFile(actualPath);
+ }
+ else if (SRecordSourceFile::isSRecordFile(testStream))
+ {
+ testStream.close();
+ return new SRecordSourceFile(actualPath);
+ }
+
+ // treat it as a binary file
+ testStream.close();
+ return new BinarySourceFile(actualPath);
+ }
+ catch (...)
+ {
+ testStream.close();
+ throw;
+ }
+}
+
+SourceFile::SourceFile(const std::string & path)
+: m_path(path), m_stream()
+{
+}
+
+//! The file is closed if it had been left opened.
+//!
+SourceFile::~SourceFile()
+{
+ if (isOpen())
+ {
+ m_stream->close();
+ }
+}
+
+//! \exception std::runtime_error Raised if the file could not be opened successfully.
+void SourceFile::open()
+{
+ assert(!isOpen());
+ m_stream = new std::ifstream(m_path.c_str(), std::ios_base::in | std::ios_base::binary);
+ if (!m_stream->is_open())
+ {
+ throw std::runtime_error(format_string("failed to open file: %s", m_path.c_str()));
+ }
+}
+
+void SourceFile::close()
+{
+ assert(isOpen());
+
+ m_stream->close();
+ m_stream.safe_delete();
+}
+
+unsigned SourceFile::getSize()
+{
+ bool wasOpen = isOpen();
+ std::ifstream::pos_type oldPosition;
+
+ if (!wasOpen)
+ {
+ open();
+ }
+
+ assert(m_stream);
+ oldPosition = m_stream->tellg();
+ m_stream->seekg(0, std::ios_base::end);
+ unsigned resultSize = m_stream->tellg();
+ m_stream->seekg(oldPosition);
+
+ if (!wasOpen)
+ {
+ close();
+ }
+
+ return resultSize;
+}
+
+//! If the file does not support named sections, or if there is not a
+//! section with the given name, this method may return NULL.
+//!
+//! This method is just a small wrapper that creates an
+//! FixedMatcher string matcher instance and uses the createDataSource()
+//! that takes a reference to a StringMatcher.
+DataSource * SourceFile::createDataSource(const std::string & section)
+{
+ FixedMatcher matcher(section);
+ return createDataSource(matcher);
+}
+
+DataTarget * SourceFile::createDataTargetForEntryPoint()
+{
+ if (!hasEntryPoint())
+ {
+ return NULL;
+ }
+
+ return new ConstantDataTarget(getEntryPointAddress());
+}
+
+DataSource * BinarySourceFile::createDataSource()
+{
+ std::istream * fileStream = getStream();
+ assert(fileStream);
+
+ // get stream size
+ fileStream->seekg(0, std::ios_base::end);
+ int length = fileStream->tellg();
+
+ // allocate buffer
+ smart_array_ptr<uint8_t> data = new uint8_t[length];
+// if (!data)
+// {
+// throw std::bad_alloc();
+// }
+
+ // read entire file into the buffer
+ fileStream->seekg(0, std::ios_base::beg);
+ if (fileStream->read((char *)data.get(), length).bad())
+ {
+ throw std::runtime_error(format_string("unexpected end of file: %s", m_path.c_str()));
+ }
+
+ // create the data source. the buffer is copied, so we can dispose of it.
+ return new UnmappedDataSource(data, length);
+}
--- /dev/null
+/*
+ * File: SourceFile.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_SourceFile_h_)
+#define _SourceFile_h_
+
+#include <string>
+#include <iostream>
+#include <fstream>
+#include "smart_ptr.h"
+#include "DataSource.h"
+#include "DataTarget.h"
+#include "StringMatcher.h"
+#include "OptionContext.h"
+
+namespace elftosb
+{
+
+/*!
+ * \brief Abstract base class for a source file containing executable code.
+ *
+ * The purpose of this class cluster is to provide a common interface for
+ * accessing the contents of different file formats. This is accomplished
+ * through several small sets of methods along with the DataSource and
+ * DataTarget classes.
+ *
+ * The primary interface for creating instances of SourceFile is the static
+ * SourceFile::openFile() function. It will create the correct subclass of
+ * SourceFile by inspecting the file to determine its type.
+ */
+class SourceFile
+{
+public:
+ // \brief Factory function that creates the correct subclass of SourceFile.
+ static SourceFile * openFile(const std::string & path);
+
+public:
+ //! \brief Default constructor.
+ SourceFile(const std::string & path);
+
+ //! \brief Destructor.
+ virtual ~SourceFile();
+
+ //! \brief Set the option context.
+ //!
+ //! The source file will take ownership of the @a context and delete it
+ //! when the source file is itself deleted.
+ inline void setOptions(OptionContext * context) { m_options = context; }
+
+ //! \brief Return the option context.
+ inline const OptionContext * getOptions() const { return m_options; }
+
+ //! \brief Returns the path to the file.
+ inline const std::string & getPath() const { return m_path; }
+
+ //! \brief Get the size in bytes of the file.
+ unsigned getSize();
+
+ //! \name Opening and closing
+ //@{
+ //! \brief Opens the file.
+ virtual void open();
+
+ //! \brief Closes the file.
+ virtual void close();
+
+ //! \brief Returns whether the file is already open.
+ virtual bool isOpen() const { return (bool)m_stream && const_cast<std::ifstream*>(m_stream.get())->is_open(); }
+ //@}
+
+ //! \name Format capabilities
+ //@{
+ virtual bool supportsNamedSections() const=0;
+ virtual bool supportsNamedSymbols() const=0;
+ //@}
+
+ //! \name Data source creation
+ //@{
+ //! \brief Creates a data source from the entire file.
+ virtual DataSource * createDataSource()=0;
+
+ //! \brief Creates a data source out of one or more sections of the file.
+ //!
+ //! The \a selector object is used to perform the section name comparison.
+ //! If the file does not support named sections, or if there is not a
+ //! section with the given name, this method may return NULL.
+ virtual DataSource * createDataSource(StringMatcher & matcher) { return NULL; }
+
+ //! \brief Creates a data source out of one section of the file.
+ virtual DataSource * createDataSource(const std::string & section);
+ //@}
+
+ //! \name Entry point
+ //@{
+ //! \brief Returns true if an entry point was set in the file.
+ virtual bool hasEntryPoint()=0;
+
+ //! \brief Returns the entry point address.
+ virtual uint32_t getEntryPointAddress() { return 0; }
+ //@}
+
+ //! \name Data target creation
+ //@{
+ virtual DataTarget * createDataTargetForSection(const std::string & section) { return NULL; }
+ virtual DataTarget * createDataTargetForSymbol(const std::string & symbol) { return NULL; }
+ virtual DataTarget * createDataTargetForEntryPoint();
+ //@}
+
+ //! \name Symbols
+ //@{
+ //! \brief Returns whether a symbol exists in the source file.
+ virtual bool hasSymbol(const std::string & name) { return false; }
+
+ //! \brief Returns the value of a symbol.
+ virtual uint32_t getSymbolValue(const std::string & name) { return 0; }
+
+ //! \brief Returns the size of a symbol.
+ virtual unsigned getSymbolSize(const std::string & name) { return 0; }
+ //@}
+
+protected:
+ std::string m_path; //!< Path to the file.
+ smart_ptr<std::ifstream> m_stream; //!< File stream, or NULL if file is closed.
+ smart_ptr<OptionContext> m_options; //!< Table of option values.
+
+ //! \brief Internal access to the input stream object.
+ inline std::ifstream * getStream() { return m_stream; }
+};
+
+/*!
+ * \brief Binary data file.
+ */
+class BinarySourceFile : public SourceFile
+{
+public:
+ //! \brief Default constructor.
+ BinarySourceFile(const std::string & path) : SourceFile(path) {}
+
+ //! \name Format capabilities
+ //@{
+ virtual bool supportsNamedSections() const { return false; }
+ virtual bool supportsNamedSymbols() const { return false; }
+ //@}
+
+ //! \brief Creates an unmapped data source from the entire file.
+ virtual DataSource * createDataSource();
+
+ virtual bool hasEntryPoint() { return false; }
+};
+
+}; // namespace elftosb
+
+#endif // _SourceFile_h_
--- /dev/null
+/*
+ * File: StELFFile.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "StELFFile.h"
+#include <ios>
+#include <stdexcept>
+#include <stdio.h>
+#include "EndianUtilities.h"
+
+//! \exception StELFFileException is thrown if there is a problem with the file format.
+//!
+StELFFile::StELFFile(std::istream & inStream)
+: m_stream(inStream)
+{
+ readFileHeaders();
+}
+
+//! Disposes of the string table data.
+StELFFile::~StELFFile()
+{
+ SectionDataMap::iterator it = m_sectionDataCache.begin();
+ for (; it != m_sectionDataCache.end(); ++it)
+ {
+ SectionDataInfo & info = it->second;
+ if (info.m_data != NULL)
+ {
+ delete [] info.m_data;
+ }
+ }
+}
+
+//! \exception StELFFileException is thrown if the file is not an ELF file.
+//!
+void StELFFile::readFileHeaders()
+{
+ // move read head to beginning of stream
+ m_stream.seekg(0, std::ios_base::beg);
+
+ // read ELF header
+ m_stream.read(reinterpret_cast<char *>(&m_header), sizeof(m_header));
+ if (m_stream.bad())
+ {
+ throw StELFFileException("could not read file header");
+ }
+
+ // convert endianness
+ m_header.e_type = ENDIAN_LITTLE_TO_HOST_U16(m_header.e_type);
+ m_header.e_machine = ENDIAN_LITTLE_TO_HOST_U16(m_header.e_machine);
+ m_header.e_version = ENDIAN_LITTLE_TO_HOST_U32(m_header.e_version);
+ m_header.e_entry = ENDIAN_LITTLE_TO_HOST_U32(m_header.e_entry);
+ m_header.e_phoff = ENDIAN_LITTLE_TO_HOST_U32(m_header.e_phoff);
+ m_header.e_shoff = ENDIAN_LITTLE_TO_HOST_U32(m_header.e_shoff);
+ m_header.e_flags = ENDIAN_LITTLE_TO_HOST_U32(m_header.e_flags);
+ m_header.e_ehsize = ENDIAN_LITTLE_TO_HOST_U16(m_header.e_ehsize);
+ m_header.e_phentsize = ENDIAN_LITTLE_TO_HOST_U16(m_header.e_phentsize);
+ m_header.e_phnum = ENDIAN_LITTLE_TO_HOST_U16(m_header.e_phnum);
+ m_header.e_shentsize = ENDIAN_LITTLE_TO_HOST_U16(m_header.e_shentsize);
+ m_header.e_shnum = ENDIAN_LITTLE_TO_HOST_U16(m_header.e_shnum);
+ m_header.e_shstrndx = ENDIAN_LITTLE_TO_HOST_U16(m_header.e_shstrndx);
+
+ // check magic number
+ if (!(m_header.e_ident[EI_MAG0] == ELFMAG0 && m_header.e_ident[EI_MAG1] == ELFMAG1 && m_header.e_ident[EI_MAG2] == ELFMAG2 && m_header.e_ident[EI_MAG3] == ELFMAG3))
+ {
+ throw StELFFileException("invalid magic number in ELF header");
+ }
+
+ try
+ {
+ int i;
+
+ // read section headers
+ if (m_header.e_shoff != 0 && m_header.e_shnum > 0)
+ {
+ Elf32_Shdr sectionHeader;
+ for (i=0; i < m_header.e_shnum; ++i)
+ {
+ m_stream.seekg(m_header.e_shoff + m_header.e_shentsize * i, std::ios::beg);
+ m_stream.read(reinterpret_cast<char *>(§ionHeader), sizeof(sectionHeader));
+ if (m_stream.bad())
+ {
+ throw StELFFileException("could not read section header");
+ }
+
+ // convert endianness
+ sectionHeader.sh_name = ENDIAN_LITTLE_TO_HOST_U32(sectionHeader.sh_name);
+ sectionHeader.sh_type = ENDIAN_LITTLE_TO_HOST_U32(sectionHeader.sh_type);
+ sectionHeader.sh_flags = ENDIAN_LITTLE_TO_HOST_U32(sectionHeader.sh_flags);
+ sectionHeader.sh_addr = ENDIAN_LITTLE_TO_HOST_U32(sectionHeader.sh_addr);
+ sectionHeader.sh_offset = ENDIAN_LITTLE_TO_HOST_U32(sectionHeader.sh_offset);
+ sectionHeader.sh_size = ENDIAN_LITTLE_TO_HOST_U32(sectionHeader.sh_size);
+ sectionHeader.sh_link = ENDIAN_LITTLE_TO_HOST_U32(sectionHeader.sh_link);
+ sectionHeader.sh_info = ENDIAN_LITTLE_TO_HOST_U32(sectionHeader.sh_info);
+ sectionHeader.sh_addralign = ENDIAN_LITTLE_TO_HOST_U32(sectionHeader.sh_addralign);
+ sectionHeader.sh_entsize = ENDIAN_LITTLE_TO_HOST_U32(sectionHeader.sh_entsize);
+
+ m_sectionHeaders.push_back(sectionHeader);
+ }
+ }
+
+ // read program headers
+ if (m_header.e_phoff != 0 && m_header.e_phnum > 0)
+ {
+ Elf32_Phdr programHeader;
+ for (i=0; i < m_header.e_phnum; ++i)
+ {
+ m_stream.seekg(m_header.e_phoff + m_header.e_phentsize * i, std::ios::beg);
+ m_stream.read(reinterpret_cast<char *>(&programHeader), sizeof(programHeader));
+ if (m_stream.bad())
+ {
+ throw StELFFileException("could not read program header");
+ }
+
+ // convert endianness
+ programHeader.p_type = ENDIAN_LITTLE_TO_HOST_U32(programHeader.p_type);
+ programHeader.p_offset = ENDIAN_LITTLE_TO_HOST_U32(programHeader.p_type);
+ programHeader.p_vaddr = ENDIAN_LITTLE_TO_HOST_U32(programHeader.p_vaddr);
+ programHeader.p_paddr = ENDIAN_LITTLE_TO_HOST_U32(programHeader.p_paddr);
+ programHeader.p_filesz = ENDIAN_LITTLE_TO_HOST_U32(programHeader.p_filesz);
+ programHeader.p_memsz = ENDIAN_LITTLE_TO_HOST_U32(programHeader.p_memsz);
+ programHeader.p_flags = ENDIAN_LITTLE_TO_HOST_U32(programHeader.p_flags);
+ programHeader.p_align = ENDIAN_LITTLE_TO_HOST_U32(programHeader.p_align);
+
+ m_programHeaders.push_back(programHeader);
+ }
+ }
+
+ // look up symbol table section index
+ {
+ std::string symtab_section_name(SYMTAB_SECTION_NAME);
+ m_symbolTableIndex = getIndexOfSectionWithName(symtab_section_name);
+ }
+ }
+ catch (...)
+ {
+ throw StELFFileException("error reading file");
+ }
+}
+
+const Elf32_Shdr & StELFFile::getSectionAtIndex(unsigned inIndex) const
+{
+ if (inIndex > m_sectionHeaders.size())
+ throw std::invalid_argument("inIndex");
+
+ return m_sectionHeaders[inIndex];
+}
+
+//! If there is not a matching section, then #SHN_UNDEF is returned instead.
+//!
+unsigned StELFFile::getIndexOfSectionWithName(const std::string & inName)
+{
+ unsigned sectionIndex = 0;
+ const_section_iterator it = getSectionBegin();
+ for (; it != getSectionEnd(); ++it, ++sectionIndex)
+ {
+ const Elf32_Shdr & header = *it;
+ if (header.sh_name != 0)
+ {
+ std::string sectionName = getSectionNameAtIndex(header.sh_name);
+ if (inName == sectionName)
+ return sectionIndex;
+ }
+ }
+
+ // no matching section
+ return SHN_UNDEF;
+}
+
+//! The pointer returned from this method must be freed with the delete array operator (i.e., delete []).
+//! If either the section data offset (sh_offset) or the section size (sh_size) are 0, then NULL will
+//! be returned instead.
+//!
+//! The data is read directly from the input stream passed into the constructor. The stream must
+//! still be open, or an exception will be thrown.
+//!
+//! \exception StELFFileException is thrown if an error occurs while reading the file.
+//! \exception std::bad_alloc is thrown if memory for the data cannot be allocated.
+uint8_t * StELFFile::getSectionDataAtIndex(unsigned inIndex)
+{
+ return readSectionData(m_sectionHeaders[inIndex]);
+}
+
+//! The pointer returned from this method must be freed with the delete array operator (i.e., delete []).
+//! If either the section data offset (sh_offset) or the section size (sh_size) are 0, then NULL will
+//! be returned instead.
+//!
+//! The data is read directly from the input stream passed into the constructor. The stream must
+//! still be open, or an exception will be thrown.
+//!
+//! \exception StELFFileException is thrown if an error occurs while reading the file.
+//! \exception std::bad_alloc is thrown if memory for the data cannot be allocated.
+uint8_t * StELFFile::getSectionData(const_section_iterator inSection)
+{
+ return readSectionData(*inSection);
+}
+
+//! \exception StELFFileException is thrown if an error occurs while reading the file.
+//! \exception std::bad_alloc is thrown if memory for the data cannot be allocated.
+uint8_t * StELFFile::readSectionData(const Elf32_Shdr & inHeader)
+{
+ // check for empty data
+ if (inHeader.sh_offset == 0 || inHeader.sh_size == 0)
+ return NULL;
+
+ uint8_t * sectionData = new uint8_t[inHeader.sh_size];
+
+ try
+ {
+ m_stream.seekg(inHeader.sh_offset, std::ios::beg);
+ m_stream.read(reinterpret_cast<char *>(sectionData), inHeader.sh_size);
+ if (m_stream.bad())
+ throw StELFFileException("could not read entire section");
+ }
+ catch (StELFFileException)
+ {
+ throw;
+ }
+ catch (...)
+ {
+ throw StELFFileException("error reading section data");
+ }
+
+ return sectionData;
+}
+
+const Elf32_Phdr & StELFFile::getSegmentAtIndex(unsigned inIndex) const
+{
+ if (inIndex > m_programHeaders.size())
+ throw std::invalid_argument("inIndex");
+
+ return m_programHeaders[inIndex];
+}
+
+//! The pointer returned from this method must be freed with the delete array operator (i.e., delete []).
+//! If either the segment offset (p_offset) or the segment file size (p_filesz) are 0, then NULL will
+//! be returned instead.
+//!
+//! The data is read directly from the input stream passed into the constructor. The stream must
+//! still be open, or an exception will be thrown.
+//!
+//! \exception StELFFileException is thrown if an error occurs while reading the file.
+//! \exception std::bad_alloc is thrown if memory for the data cannot be allocated.
+uint8_t * StELFFile::getSegmentDataAtIndex(unsigned inIndex)
+{
+ return readSegmentData(m_programHeaders[inIndex]);
+}
+
+//! The pointer returned from this method must be freed with the delete array operator (i.e., delete []).
+//! If either the segment offset (p_offset) or the segment file size (p_filesz) are 0, then NULL will
+//! be returned instead.
+//!
+//! The data is read directly from the input stream passed into the constructor. The stream must
+//! still be open, or an exception will be thrown.
+//!
+//! \exception StELFFileException is thrown if an error occurs while reading the file.
+//! \exception std::bad_alloc is thrown if memory for the data cannot be allocated.
+uint8_t * StELFFile::getSegmentData(const_segment_iterator inSegment)
+{
+ return readSegmentData(*inSegment);
+}
+
+//! \exception StELFFileException is thrown if an error occurs while reading the file.
+//! \exception std::bad_alloc is thrown if memory for the data cannot be allocated.
+uint8_t * StELFFile::readSegmentData(const Elf32_Phdr & inHeader)
+{
+ // check for empty data
+ if (inHeader.p_offset == 0 || inHeader.p_filesz== 0)
+ return NULL;
+
+ uint8_t * segmentData = new uint8_t[inHeader.p_filesz];
+
+ try
+ {
+ m_stream.seekg(inHeader.p_offset, std::ios::beg);
+ m_stream.read(reinterpret_cast<char *>(segmentData), inHeader.p_filesz);
+ if (m_stream.bad())
+ throw StELFFileException("could not read entire segment");
+ }
+ catch (StELFFileException)
+ {
+ throw;
+ }
+ catch (...)
+ {
+ throw StELFFileException("error reading segment data");
+ }
+
+ return segmentData;
+}
+
+//! If the index is out of range, or if there is no string table in the file, then
+//! an empty string will be returned instead. This will also happen when the index
+//! is either 0 or the last byte in the table, since the table begins and ends with
+//! zero bytes.
+std::string StELFFile::getSectionNameAtIndex(unsigned inIndex)
+{
+ // make sure there's a section name string table
+ if (m_header.e_shstrndx == SHN_UNDEF)
+ return std::string("");
+
+ return getStringAtIndex(m_header.e_shstrndx, inIndex);
+}
+
+//! \exception std::invalid_argument is thrown if the section identified by \a
+//! inStringTableSectionIndex is not actually a string table, or if \a
+//! inStringIndex is out of range for the string table.
+std::string StELFFile::getStringAtIndex(unsigned inStringTableSectionIndex, unsigned inStringIndex)
+{
+ // check section type
+ const Elf32_Shdr & header = getSectionAtIndex(inStringTableSectionIndex);
+ if (header.sh_type != SHT_STRTAB)
+ throw std::invalid_argument("inStringTableSectionIndex");
+
+ if (inStringIndex >= header.sh_size)
+ throw std::invalid_argument("inStringTableSectionIndex");
+
+ // check cache
+ SectionDataInfo & info = getCachedSectionData(inStringTableSectionIndex);
+ return std::string(&reinterpret_cast<char *>(info.m_data)[inStringIndex]);
+}
+
+StELFFile::SectionDataInfo & StELFFile::getCachedSectionData(unsigned inSectionIndex)
+{
+ // check cache
+ SectionDataMap::iterator it = m_sectionDataCache.find(inSectionIndex);
+ if (it != m_sectionDataCache.end())
+ return it->second;
+
+ // not in cache, add it
+ const Elf32_Shdr & header = getSectionAtIndex(inSectionIndex);
+ uint8_t * data = getSectionDataAtIndex(inSectionIndex);
+
+ SectionDataInfo info;
+ info.m_data = data;
+ info.m_size = header.sh_size;
+
+ m_sectionDataCache[inSectionIndex] = info;
+ return m_sectionDataCache[inSectionIndex];
+}
+
+//! The number of entries in the symbol table is the symbol table section size
+//! divided by the size of each symbol entry (the #Elf32_Shdr::sh_entsize field of the
+//! symbol table section header).
+unsigned StELFFile::getSymbolCount()
+{
+ if (m_symbolTableIndex == SHN_UNDEF)
+ return 0;
+
+ const Elf32_Shdr & header = getSectionAtIndex(m_symbolTableIndex);
+ return header.sh_size / header.sh_entsize;
+}
+
+//! \exception std::invalid_argument is thrown if \a inIndex is out of range.]
+//!
+const Elf32_Sym & StELFFile::getSymbolAtIndex(unsigned inIndex)
+{
+ // get section data
+ const Elf32_Shdr & header = getSectionAtIndex(m_symbolTableIndex);
+ SectionDataInfo & info = getCachedSectionData(m_symbolTableIndex);
+
+ // has the symbol table been byte swapped yet?
+ if (!info.m_swapped)
+ {
+ byteSwapSymbolTable(header, info);
+ }
+
+ unsigned symbolOffset = header.sh_entsize * inIndex;
+ if (symbolOffset >= info.m_size)
+ {
+ throw std::invalid_argument("inIndex");
+ }
+
+ Elf32_Sym * symbol = reinterpret_cast<Elf32_Sym *>(&info.m_data[symbolOffset]);
+ return *symbol;
+}
+
+void StELFFile::byteSwapSymbolTable(const Elf32_Shdr & header, SectionDataInfo & info)
+{
+ unsigned symbolCount = getSymbolCount();
+ unsigned i = 0;
+ unsigned symbolOffset = 0;
+
+ for (; i < symbolCount; ++i, symbolOffset += header.sh_entsize)
+ {
+ Elf32_Sym * symbol = reinterpret_cast<Elf32_Sym *>(&info.m_data[symbolOffset]);
+ symbol->st_name = ENDIAN_LITTLE_TO_HOST_U32(symbol->st_name);
+ symbol->st_value = ENDIAN_LITTLE_TO_HOST_U32(symbol->st_value);
+ symbol->st_size = ENDIAN_LITTLE_TO_HOST_U32(symbol->st_size);
+ symbol->st_shndx = ENDIAN_LITTLE_TO_HOST_U16(symbol->st_shndx);
+ }
+
+ // remember that we've byte swapped the symbols
+ info.m_swapped = true;
+}
+
+unsigned StELFFile::getSymbolNameStringTableIndex() const
+{
+ const Elf32_Shdr & header = getSectionAtIndex(m_symbolTableIndex);
+ return header.sh_link;
+}
+
+std::string StELFFile::getSymbolName(const Elf32_Sym & inSymbol)
+{
+ unsigned symbolStringTableIndex = getSymbolNameStringTableIndex();
+ return getStringAtIndex(symbolStringTableIndex, inSymbol.st_name);
+}
+
+//! Returns STN_UNDEF if it cannot find a symbol at the given \a symbolAddress.
+unsigned StELFFile::getIndexOfSymbolAtAddress(uint32_t symbolAddress, bool strict)
+{
+ unsigned symbolCount = getSymbolCount();
+ unsigned symbolIndex = 0;
+ for (; symbolIndex < symbolCount; ++symbolIndex)
+ {
+ const Elf32_Sym & symbol = getSymbolAtIndex(symbolIndex);
+
+ // the GHS toolchain puts in STT_FUNC symbols marking the beginning and ending of each
+ // file. if the entry point happens to be at the beginning of the file, the beginning-
+ // of-file symbol will have the same value and type. fortunately, the size of these
+ // symbols is 0 (or seems to be). we also ignore symbols that start with two dots just
+ // in case.
+ if (symbol.st_value == symbolAddress && (strict && ELF32_ST_TYPE(symbol.st_info) == STT_FUNC && symbol.st_size != 0))
+ {
+ std::string symbolName = getSymbolName(symbol);
+
+ // ignore symbols that start with two dots
+ if (symbolName[0] == '.' && symbolName[1] == '.')
+ continue;
+
+ // found the symbol!
+ return symbolIndex;
+ }
+ }
+
+ return STN_UNDEF;
+}
+
+ARMSymbolType_t StELFFile::getTypeOfSymbolAtIndex(unsigned symbolIndex)
+{
+ ARMSymbolType_t symType = eARMSymbol;
+ const Elf32_Sym & symbol = getSymbolAtIndex(symbolIndex);
+
+ if (m_elfVariant == eGHSVariant)
+ {
+ if (symbol.st_other & STO_THUMB)
+ symType = eThumbSymbol;
+ }
+ else
+ {
+ unsigned mappingSymStart = 1;
+ unsigned mappingSymCount = getSymbolCount() - 1; // don't include first undefined symbol
+ bool mapSymsFirst = (m_header.e_flags & EF_ARM_MAPSYMSFIRST) != 0;
+ if (mapSymsFirst)
+ {
+ // first symbol '$m' is number of mapping syms
+ const Elf32_Sym & mappingSymCountSym = getSymbolAtIndex(1);
+ if (getSymbolName(mappingSymCountSym) == MAPPING_SYMBOL_COUNT_TAGSYM)
+ {
+ mappingSymCount = mappingSymCountSym.st_value;
+ mappingSymStart = 2;
+ }
+
+ }
+
+ uint32_t lastMappingSymAddress = 0;
+ unsigned mappingSymIndex = mappingSymStart;
+ for (; mappingSymIndex < mappingSymCount + mappingSymStart; ++mappingSymIndex)
+ {
+ const Elf32_Sym & mappingSym = getSymbolAtIndex(mappingSymIndex);
+ std::string mappingSymName = getSymbolName(mappingSym);
+ ARMSymbolType_t nextSymType = eUnknownSymbol;
+
+ if (mappingSymName == ARM_SEQUENCE_MAPSYM)
+ symType = eARMSymbol;
+ else if (mappingSymName == DATA_SEQUENCE_MAPSYM)
+ symType = eDataSymbol;
+ else if (mappingSymName == THUMB_SEQUENCE_MAPSYM)
+ symType = eThumbSymbol;
+
+ if (nextSymType != eUnknownSymbol)
+ {
+ if (symbol.st_value >= lastMappingSymAddress && symbol.st_value < mappingSym.st_value)
+ break;
+
+ symType = nextSymType;
+ lastMappingSymAddress = mappingSym.st_value;
+ }
+ }
+ }
+
+ return symType;
+}
+
+void StELFFile::dumpSections()
+{
+ unsigned count = getSectionCount();
+ unsigned i = 0;
+
+ const char * sectionTypes[12] = { "NULL", "PROGBITS", "SYMTAB", "STRTAB", "RELA", "HASH", "DYNAMIC", "NOTE", "NOBITS", "REL", "SHLIB", "DYNSYM" };
+
+ for (; i < count; ++i)
+ {
+ const Elf32_Shdr & header = getSectionAtIndex(i);
+ std::string name = getSectionNameAtIndex(header.sh_name);
+
+ if (header.sh_type < sizeof(sectionTypes) / sizeof(sectionTypes[0])) {
+ printf("%s: %s, 0x%08x, 0x%08x, 0x%08x, %d, %d, %d\n",
+ name.c_str(), sectionTypes[header.sh_type],
+ header.sh_addr, header.sh_offset,
+ header.sh_size, header.sh_link,
+ header.sh_info, header.sh_entsize);
+ } else {
+ printf("%s: 0x%02x, 0x%08x, 0x%08x, 0x%08x, %d, %d, %d\n",
+ name.c_str(), header.sh_type,
+ header.sh_addr, header.sh_offset,
+ header.sh_size, header.sh_link,
+ header.sh_info, header.sh_entsize);
+ }
+ }
+}
+
+void StELFFile::dumpSymbolTable()
+{
+ const char * symbolTypes[5] = { "NOTYPE", "OBJECT", "FUNC", "SECTION", "FILE" };
+ const char * symbolBinding[3] = { "LOCAL", "GLOBAL", "WEAK" };
+
+ unsigned count = getSymbolCount();
+ unsigned i = 0;
+
+ for (; i < count; ++i)
+ {
+ const Elf32_Sym & symbol = getSymbolAtIndex(i);
+ std::string name = getSymbolName(symbol);
+
+ printf("'%s': %s, %s, 0x%08x, 0x%08x, %d. 0x%08x\n", name.c_str(), symbolTypes[ELF32_ST_TYPE(symbol.st_info)], symbolBinding[ELF32_ST_BIND(symbol.st_info)], symbol.st_value, symbol.st_size, symbol.st_shndx, symbol.st_other);
+ }
+}
+
+
+
--- /dev/null
+/*
+ * File: StELFFile.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_StELFFile_h_)
+#define _StELFFile_h_
+
+#include "stdafx.h"
+#include <string>
+#include <vector>
+#include <map>
+#include <iostream>
+#include <stdexcept>
+#include "ELF.h"
+
+//! Variations of the ARM ELF format.
+typedef enum {
+ eARMVariant = 1, //!< Standard ARM ELF specification.
+ eGHSVariant, //!< Green Hills Software variant.
+ eGCCVariant //!< GNU Compiler Collection variant.
+} ELFVariant_t;
+
+//! Possible ARM ELF symbol types.
+typedef enum {
+ eUnknownSymbol,
+ eARMSymbol,
+ eThumbSymbol,
+ eDataSymbol
+} ARMSymbolType_t;
+
+/*!
+ * \brief Parser for Executable and Linking Format (ELF) files.
+ *
+ * The stream passed into the constructor needs to stay open for the life
+ * of the object. This is because calls to getSectionDataAtIndex() and
+ * getSegmentDataAtIndex() read the data directly from the input stream.
+ */
+class StELFFile
+{
+public:
+ typedef std::vector<Elf32_Shdr>::const_iterator const_section_iterator;
+ typedef std::vector<Elf32_Phdr>::const_iterator const_segment_iterator;
+
+public:
+ //! \brief Constructor.
+ StELFFile(std::istream & inStream);
+
+ //! \brief Destructor.
+ virtual ~StELFFile();
+
+ //! \name File format variant
+ //@{
+ //! \brief Return the ELF format variant to which this file is set.
+ virtual ELFVariant_t ELFVariant() { return m_elfVariant; }
+
+ //! \brief Set the ELF format variation to either #eARMVariant or #eGHSVariant.
+ virtual void setELFVariant(ELFVariant_t variant) { m_elfVariant = variant; }
+ //@}
+
+ //! \name File name
+ //@{
+ virtual void setName(const std::string & inName) { m_name = inName; }
+ virtual std::string getName() const { return m_name; }
+ //@}
+
+ //! \name ELF header
+ //@{
+ //! \brief Returns the ELF file header.
+ inline const Elf32_Ehdr & getFileHeader() const { return m_header; }
+ //@}
+
+ //! \name Sections
+ //! Methods pertaining to the object file's sections.
+ //@{
+ //! \brief Returns the number of sections in the file.
+ inline unsigned getSectionCount() const { return static_cast<unsigned>(m_sectionHeaders.size()); }
+
+ //! \brief Returns a reference to section number \a inIndex.
+ const Elf32_Shdr & getSectionAtIndex(unsigned inIndex) const;
+
+ inline const_section_iterator getSectionBegin() const { return m_sectionHeaders.begin(); }
+ inline const_section_iterator getSectionEnd() const { return m_sectionHeaders.end(); }
+
+ //! \brief Returns the index of the section with the name \a inName.
+ unsigned getIndexOfSectionWithName(const std::string & inName);
+
+ //! \brief Returns the data for the section.
+ uint8_t * getSectionDataAtIndex(unsigned inIndex);
+
+ //! \brief Returns the data for the section.
+ uint8_t * getSectionData(const_section_iterator inSection);
+ //@}
+
+ //! \name Segments
+ //! Methods for accessing the file's program headers for segments.
+ //@{
+ //! \brief Returns the number of segments, or program headers, in the file.
+ inline unsigned getSegmentCount() const { return static_cast<unsigned>(m_programHeaders.size()); }
+
+ //! \brief Returns a reference to the given segment.
+ const Elf32_Phdr & getSegmentAtIndex(unsigned inIndex) const;
+
+ inline const_segment_iterator getSegmentBegin() const { return m_programHeaders.begin(); }
+ inline const_segment_iterator getSegmentEnd() const { return m_programHeaders.end(); }
+
+ //! \brief Returns the data of the specified segment.
+ uint8_t * getSegmentDataAtIndex(unsigned inIndex);
+
+ //! \brief Returns the data of the specified segment.
+ uint8_t * getSegmentData(const_segment_iterator inSegment);
+ //@}
+
+ //! \name String table
+ //! Methods for accessing the string tables.
+ //@{
+ //! \brief Returns a string from the file's section name string table.
+ std::string getSectionNameAtIndex(unsigned inIndex);
+
+ //! \brief Returns a string from any string table in the object file.
+ std::string getStringAtIndex(unsigned inStringTableSectionIndex, unsigned inStringIndex);
+ //@}
+
+ //! \name Symbol table
+ //! Methods for accessing the object file's symbol table. Currently only
+ //! a single symbol table with the section name ".symtab" is supported.
+ //@{
+ //! \brief Returns the number of symbols in the default ".symtab" symbol table.
+ unsigned getSymbolCount();
+
+ //! \brief Returns the symbol with index \a inIndex.
+ const Elf32_Sym & getSymbolAtIndex(unsigned inIndex);
+
+ //! \brief Returns the section index of the string table containing symbol names.
+ unsigned getSymbolNameStringTableIndex() const;
+
+ //! \brief Returns the name of the symbol described by \a inSymbol.
+ std::string getSymbolName(const Elf32_Sym & inSymbol);
+
+ unsigned getIndexOfSymbolAtAddress(uint32_t symbolAddress, bool strict=true);
+
+ ARMSymbolType_t getTypeOfSymbolAtIndex(unsigned symbolIndex);
+ //@}
+
+ //! \name Debugging
+ //@{
+ void dumpSections();
+ void dumpSymbolTable();
+ //@}
+
+protected:
+ std::istream & m_stream; //!< The source stream for the ELF file.
+ ELFVariant_t m_elfVariant; //!< Variant of the ARM ELF format specification.
+ std::string m_name; //!< File name. (optional)
+ Elf32_Ehdr m_header; //!< The ELF file header.
+ std::vector<Elf32_Shdr> m_sectionHeaders; //!< All of the section headers.
+ std::vector<Elf32_Phdr> m_programHeaders; //!< All of the program headers.
+ unsigned m_symbolTableIndex; //!< Index of ".symtab" section, or #SHN_UNDEF if not present.
+
+ /*!
+ * Little structure containing information about cached section data.
+ */
+ struct SectionDataInfo
+ {
+ uint8_t * m_data; //!< Pointer to section data.
+ unsigned m_size; //!< Section data size in bytes.
+ bool m_swapped; //!< Has this section been byte swapped yet? Used for symbol table.
+ };
+ typedef std::map<unsigned, SectionDataInfo> SectionDataMap;
+ SectionDataMap m_sectionDataCache; //!< Cached data of sections.
+
+ //! \brief Reads a section's data either from cache or from disk.
+ SectionDataInfo & getCachedSectionData(unsigned inSectionIndex);
+
+ //! \brief Reads the file, section, and program headers into memory.
+ void readFileHeaders();
+
+ uint8_t * readSectionData(const Elf32_Shdr & inHeader);
+ uint8_t * readSegmentData(const Elf32_Phdr & inHeader);
+
+ //! \brief Byte swaps the symbol table data into host endianness.
+ void byteSwapSymbolTable(const Elf32_Shdr & header, SectionDataInfo & info);
+};
+
+/*!
+ * \brief Simple exception thrown to indicate an error in the input ELF file format.
+ */
+class StELFFileException : public std::runtime_error
+{
+public:
+ //! \brief Default constructor.
+ StELFFileException(const std::string & inMessage) : std::runtime_error(inMessage) {}
+};
+
+#endif // _StELFFile_h_
--- /dev/null
+/*
+ * File: StExecutableImage.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "StExecutableImage.h"
+#include <stdexcept>
+#include <algorithm>
+#include <string.h>
+#include <stdio.h>
+
+StExecutableImage::StExecutableImage(int inAlignment)
+: m_alignment(inAlignment),
+ m_hasEntry(false),
+ m_entry(0)
+{
+}
+
+//! Makes a duplicate of each memory region.
+StExecutableImage::StExecutableImage(const StExecutableImage & inOther)
+: m_name(inOther.m_name),
+ m_alignment(inOther.m_alignment),
+ m_hasEntry(inOther.m_hasEntry),
+ m_entry(inOther.m_entry),
+ m_filters(inOther.m_filters)
+{
+ const_iterator it = inOther.getRegionBegin();
+ for (; it != inOther.getRegionEnd(); ++it)
+ {
+ const MemoryRegion & region = *it;
+
+ MemoryRegion regionCopy(region);
+ if (region.m_type == FILL_REGION && region.m_data != NULL)
+ {
+ regionCopy.m_data = new uint8_t[region.m_length];
+ memcpy(regionCopy.m_data, region.m_data, region.m_length);
+ }
+
+ m_image.push_back(regionCopy);
+ }
+}
+
+//! Disposes of memory allocated for each region.
+StExecutableImage::~StExecutableImage()
+{
+ MemoryRegionList::iterator it;
+ for (it = m_image.begin(); it != m_image.end(); ++it)
+ {
+ if (it->m_data)
+ {
+ delete [] it->m_data;
+ it->m_data = NULL;
+ }
+ }
+}
+
+//! A copy of \a inName is made, so the original may be disposed of by the caller
+//! after this method returns.
+void StExecutableImage::setName(const std::string & inName)
+{
+ m_name = inName;
+}
+
+std::string StExecutableImage::getName() const
+{
+ return m_name;
+}
+
+// The region is added with read and write flags set.
+//! \exception std::runtime_error will be thrown if the new overlaps an
+//! existing region.
+void StExecutableImage::addFillRegion(uint32_t inAddress, unsigned inLength)
+{
+ MemoryRegion region;
+ region.m_type = FILL_REGION;
+ region.m_address = inAddress;
+ region.m_data = NULL;
+ region.m_length = inLength;
+ region.m_flags = REGION_RW_FLAG;
+
+ insertOrMergeRegion(region);
+}
+
+//! A copy of \a inData is made before returning. The copy will be deleted when
+//! the executable image is destructed. Currently, the text region is created with
+//! read, write, and executable flags set.
+//! \exception std::runtime_error will be thrown if the new overlaps an
+//! existing region.
+//! \exception std::bad_alloc is thrown if memory for the copy of \a inData
+//! cannot be allocated.
+void StExecutableImage::addTextRegion(uint32_t inAddress, const uint8_t * inData, unsigned inLength)
+{
+ MemoryRegion region;
+ region.m_type = TEXT_REGION;
+ region.m_address = inAddress;
+ region.m_flags = REGION_RW_FLAG | REGION_EXEC_FLAG;
+
+ // copy the data
+ region.m_data = new uint8_t[inLength];
+ region.m_length = inLength;
+ memcpy(region.m_data, inData, inLength);
+
+ insertOrMergeRegion(region);
+}
+
+//! \exception std::out_of_range is thrown if \a inIndex is out of range.
+//!
+const StExecutableImage::MemoryRegion & StExecutableImage::getRegionAtIndex(unsigned inIndex) const
+{
+ // check bounds
+ if (inIndex >= m_image.size())
+ throw std::out_of_range("inIndex");
+
+ // find region by index
+ MemoryRegionList::const_iterator it = m_image.begin();
+ unsigned i = 0;
+ for (; it != m_image.end(); ++it, ++i)
+ {
+ if (i == inIndex)
+ break;
+ }
+ return *it;
+}
+
+//! The list of address filters is kept sorted as filters are added.
+//!
+void StExecutableImage::addAddressFilter(const AddressFilter & filter)
+{
+ m_filters.push_back(filter);
+ m_filters.sort();
+}
+
+//!
+void StExecutableImage::clearAddressFilters()
+{
+ m_filters.clear();
+}
+
+//! \exception StExecutableImage::address_filter_exception Raised when a filter
+//! with the type #ADDR_FILTER_ERROR or #ADDR_FILTER_WARNING is matched.
+//!
+//! \todo Build a list of all matching filters and then execute them at once.
+//! For the warning and error filters, a single exception should be raised
+//! that identifies all the overlapping errors. Currently the user will only
+//! see the first (lowest address) overlap.
+void StExecutableImage::applyAddressFilters()
+{
+restart_loops:
+ // Iterate over filters.
+ AddressFilterList::const_iterator fit = m_filters.begin();
+ for (; fit != m_filters.end(); ++fit)
+ {
+ const AddressFilter & filter = *fit;
+
+ // Iterator over regions.
+ MemoryRegionList::iterator rit = m_image.begin();
+ for (; rit != m_image.end(); ++rit)
+ {
+ MemoryRegion & region = *rit;
+
+ if (filter.matchesMemoryRegion(region))
+ {
+ switch (filter.m_action)
+ {
+ case ADDR_FILTER_NONE:
+ // Do nothing.
+ break;
+
+ case ADDR_FILTER_ERROR:
+ // throw error exception
+ throw address_filter_exception(true, m_name, filter);
+ break;
+
+ case ADDR_FILTER_WARNING:
+ // throw warning exception
+ throw address_filter_exception(false, m_name, filter);
+ break;
+
+ case ADDR_FILTER_CROP:
+ // Delete the offending portion of the region and restart
+ // the iteration loops.
+ cropRegionToFilter(region, filter);
+ goto restart_loops;
+ break;
+ }
+ }
+ }
+ }
+}
+
+//! There are several possible cases here:
+//! - No overlap at all. Nothing is done.
+//!
+//! - All of the memory region is matched by the \a filter. The region is
+//! removed from #StExecutableImage::m_image and its data memory freed.
+//!
+//! - The remaining portion of the region is one contiguous chunk. In this
+//! case, \a region is simply modified.
+//!
+//! - The region is split in the middle by the filter. The original \a region
+//! is modified to match the first remaining chunk. And a new #StExecutableImage::MemoryRegion
+//! instance is created to hold the other leftover piece.
+void StExecutableImage::cropRegionToFilter(MemoryRegion & region, const AddressFilter & filter)
+{
+ uint32_t firstByte = region.m_address; // first byte occupied by this region
+ uint32_t lastByte = region.endAddress(); // last used byte in this region
+
+ // compute new address range
+ uint32_t cropFrom = filter.m_fromAddress;
+ if (cropFrom < firstByte)
+ {
+ cropFrom = firstByte;
+ }
+
+ uint32_t cropTo = filter.m_toAddress;
+ if (cropTo > lastByte)
+ {
+ cropTo = lastByte;
+ }
+
+ // is there actually a match?
+ if (cropFrom > filter.m_toAddress || cropTo < filter.m_fromAddress)
+ {
+ // nothing to do, so bail
+ return;
+ }
+
+ printf("Deleting region 0x%08x-0x%08x\n", cropFrom, cropTo);
+
+ // handle if the entire region is to be deleted
+ if (cropFrom == firstByte && cropTo == lastByte)
+ {
+ delete [] region.m_data;
+ region.m_data = NULL;
+ m_image.remove(region);
+ }
+
+ // there is at least a little of the original region remaining
+ uint32_t newLength = cropTo - cropFrom + 1;
+ uint32_t leftoverLength = lastByte - cropTo;
+ uint8_t * oldData = region.m_data;
+
+ // update the region
+ region.m_address = cropFrom;
+ region.m_length = newLength;
+
+ // crop data buffer for text regions
+ if (region.m_type == TEXT_REGION && oldData)
+ {
+ region.m_data = new uint8_t[newLength];
+ memcpy(region.m_data, &oldData[cropFrom - firstByte], newLength);
+
+ // dispose of old data
+ delete [] oldData;
+ }
+
+ // create a new region for any part of the original region that was past
+ // the crop to address. this will happen if the filter range falls in the
+ // middle of the region.
+ if (leftoverLength)
+ {
+ MemoryRegion newRegion;
+ newRegion.m_type = region.m_type;
+ newRegion.m_flags = region.m_flags;
+ newRegion.m_address = cropTo + 1;
+ newRegion.m_length = leftoverLength;
+
+ if (region.m_type == TEXT_REGION && oldData)
+ {
+ newRegion.m_data = new uint8_t[leftoverLength];
+ memcpy(newRegion.m_data, &oldData[cropTo - firstByte + 1], leftoverLength);
+ }
+
+ insertOrMergeRegion(newRegion);
+ }
+}
+
+//! \exception std::runtime_error will be thrown if \a inRegion overlaps an
+//! existing region.
+//!
+//! \todo Need to investigate if we can use the STL sort algorithm at all. Even
+//! though we're doing merges too, we could sort first then examine the list
+//! for merges.
+void StExecutableImage::insertOrMergeRegion(MemoryRegion & inRegion)
+{
+ uint32_t newStart = inRegion.m_address;
+ uint32_t newEnd = newStart + inRegion.m_length;
+
+ MemoryRegionList::iterator it = m_image.begin();
+ MemoryRegionList::iterator sortedPosition = m_image.begin();
+ for (; it != m_image.end(); ++it)
+ {
+ MemoryRegion & region = *it;
+ uint32_t thisStart = region.m_address;
+ uint32_t thisEnd = thisStart + region.m_length;
+
+ // keep track of where to insert it to retain sort order
+ if (thisStart >= newEnd)
+ {
+ break;
+ }
+
+ // region types and flags must match in order to merge
+ if (region.m_type == inRegion.m_type && region.m_flags == inRegion.m_flags)
+ {
+ if (newStart == thisEnd || newEnd == thisStart)
+ {
+ mergeRegions(region, inRegion);
+ return;
+ }
+ else if ((newStart >= thisStart && newStart < thisEnd) || (newEnd >= thisStart && newEnd < thisEnd))
+ {
+ throw std::runtime_error("new region overlaps existing region");
+ }
+ }
+ }
+
+ // not merged, so just insert it in the sorted position
+ m_image.insert(it, inRegion);
+}
+
+//! Extends \a inNewRegion to include the data in \a inOldRegion. It is
+//! assumed that the two regions are compatible. The new region may come either
+//! before or after the old region in memory. Note that while the two regions
+//! don't necessarily have to be touching, it's probably a good idea. That's
+//! because any data between the regions will be set to 0.
+//!
+//! For TEXT_REGION types, the two original regions will have their data deleted
+//! during the merge. Thus, this method is not safe if any outside callers may
+//! be accessing the region's data.
+void StExecutableImage::mergeRegions(MemoryRegion & inOldRegion, MemoryRegion & inNewRegion)
+{
+ bool isOldBefore = inOldRegion.m_address < inNewRegion.m_address;
+ uint32_t oldEnd = inOldRegion.m_address + inOldRegion.m_length;
+ uint32_t newEnd = inNewRegion.m_address + inNewRegion.m_length;
+
+ switch (inOldRegion.m_type)
+ {
+ case TEXT_REGION:
+ {
+ // calculate new length
+ unsigned newLength;
+ if (isOldBefore)
+ {
+ newLength = newEnd - inOldRegion.m_address;
+ }
+ else
+ {
+ newLength = oldEnd - inNewRegion.m_address;
+ }
+
+ // alloc memory
+ uint8_t * newData = new uint8_t[newLength];
+ memset(newData, 0, newLength);
+
+ // copy data from the two regions into new block
+ if (isOldBefore)
+ {
+ memcpy(newData, inOldRegion.m_data, inOldRegion.m_length);
+ memcpy(&newData[newLength - inNewRegion.m_length], inNewRegion.m_data, inNewRegion.m_length);
+ }
+ else
+ {
+ memcpy(newData, inNewRegion.m_data, inNewRegion.m_length);
+ memcpy(&newData[newLength - inOldRegion.m_length], inOldRegion.m_data, inOldRegion.m_length);
+
+ inOldRegion.m_address = inNewRegion.m_address;
+ }
+
+ // replace old region's data
+ delete [] inOldRegion.m_data;
+ inOldRegion.m_data = newData;
+ inOldRegion.m_length = newLength;
+
+ // delete new region's data
+ delete [] inNewRegion.m_data;
+ inNewRegion.m_data = NULL;
+ break;
+ }
+
+ case FILL_REGION:
+ {
+ if (isOldBefore)
+ {
+ inOldRegion.m_length = newEnd - inOldRegion.m_address;
+ }
+ else
+ {
+ inOldRegion.m_length = oldEnd - inNewRegion.m_address;
+ inOldRegion.m_address = inNewRegion.m_address;
+ }
+ break;
+ }
+ }
+}
+
+//! Used when we remove a region from the region list by value. Because this
+//! operator compares the #m_data member, it will only return true for either an
+//! exact copy or a reference to the original.
+bool StExecutableImage::MemoryRegion::operator == (const MemoryRegion & other)
+{
+ return (m_type == other.m_type) && (m_address == other.m_address) && (m_length == other.m_length) && (m_flags == other.m_flags) && (m_data == other.m_data);
+}
+
+//! Returns true if the address filter overlaps \a region.
+bool StExecutableImage::AddressFilter::matchesMemoryRegion(const MemoryRegion & region) const
+{
+ uint32_t firstByte = region.m_address; // first byte occupied by this region
+ uint32_t lastByte = region.endAddress(); // last used byte in this region
+ return (firstByte >= m_fromAddress && firstByte <= m_toAddress) || (lastByte >= m_fromAddress && lastByte <= m_toAddress);
+}
+
+//! The comparison does \em not take the action into account. It only looks at the
+//! priority and address ranges of each filter. Priority is considered only if the two
+//! filters overlap. Lower priority filters will come after higher priority ones.
+//!
+//! \retval -1 This filter is less than filter \a b.
+//! \retval 0 This filter is equal to filter \a b.
+//! \retval 1 This filter is greater than filter \a b.
+int StExecutableImage::AddressFilter::compare(const AddressFilter & other) const
+{
+ if (m_priority != other.m_priority && ((m_fromAddress >= other.m_fromAddress && m_fromAddress <= other.m_toAddress) || (m_toAddress >= other.m_fromAddress && m_toAddress <= other.m_toAddress)))
+ {
+ // we know the priorities are not equal
+ if (m_priority > other.m_priority)
+ {
+ return -1;
+ }
+ else
+ {
+ return 1;
+ }
+ }
+
+ if (m_fromAddress == other.m_fromAddress)
+ {
+ if (m_toAddress == other.m_toAddress)
+ {
+ return 0;
+ }
+ else if (m_toAddress < other.m_toAddress)
+ {
+ return -1;
+ }
+ else
+ {
+ return 1;
+ }
+ }
+ else if (m_fromAddress < other.m_fromAddress)
+ {
+ return -1;
+ }
+ else
+ {
+ return 1;
+ }
+}
+
+
+
--- /dev/null
+/*
+ * File: StExecutableImage.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_StExecutableImage_h_)
+#define _StExecutableImage_h_
+
+#include "stdafx.h"
+#include <list>
+
+/*!
+ * \brief Used to build a representation of memory regions.
+ *
+ * An intermediate representation of the memory regions and segments loaded
+ * from an executable file. Also used to find contiguous segments that are
+ * specified separately in the source file.
+ *
+ * When regions are added, an attempt is made to coalesce contiguous regions.
+ * In order for this to succeed, the touching regions must be of the same
+ * type and have the same permissions. Regions are also kept sorted by their
+ * address range as they are added.
+ *
+ * \todo Implement alignment support.
+ */
+class StExecutableImage
+{
+public:
+ //! Possible types of memory regions.
+ typedef enum {
+ TEXT_REGION, //!< A region containing data or instructions.
+ FILL_REGION //!< Region to be initialized with zero bytes.
+ } MemoryRegionType;
+
+ //! Memory region flag constants.
+ enum {
+ REGION_READ_FLAG = 1, //!< Region is readable.
+ REGION_WRITE_FLAG = 2, //!< Region is writable.
+ REGION_EXEC_FLAG = 4, //!< Region may contain executable code.
+
+ REGION_RW_FLAG = REGION_READ_FLAG | REGION_WRITE_FLAG, //!< Region is read-write.
+
+ //! Mask to access only permissions flags for a region.
+ REGION_PERM_FLAG_MASK = 0x7
+ };
+
+ /*!
+ * Representation of a contiguous region of memory.
+ *
+ * \todo Add comparison operators so we can use the STL sort algorithm.
+ */
+ struct MemoryRegion
+ {
+ MemoryRegionType m_type; //!< Memory region type.
+ uint32_t m_address; //!< The 32-bit start address of this region.
+ uint32_t m_length; //!< Number of bytes in this region.
+ uint8_t * m_data; //!< Pointer to data. Will be NULL for FILL_REGION type.
+ unsigned m_flags; //!< Flags for the region.
+
+ //! \brief Calculates the address of the last byte occupied by this region.
+ inline uint32_t endAddress() const { return m_address + m_length - 1; }
+
+ //! \brief Equality operator.
+ bool operator == (const MemoryRegion & other);
+ };
+
+ //! A list of #StExecutableImage::MemoryRegion objects.
+ typedef std::list<MemoryRegion> MemoryRegionList;
+
+ //! The iterator type used to access #StExecutableImage::MemoryRegion objects. This type
+ //! is used by the methods #getRegionBegin() and #getRegionEnd().
+ typedef MemoryRegionList::const_iterator const_iterator;
+
+ //! The possible actions for regions matching an address filter range.
+ typedef enum {
+ ADDR_FILTER_NONE, //!< Do nothing.
+ ADDR_FILTER_ERROR, //!< Raise an error exception.
+ ADDR_FILTER_WARNING, //!< Raise a warning exception.
+ ADDR_FILTER_CROP //!< Don't include the matching address range in the executable image.
+ } AddressFilterAction;
+
+ /*!
+ * An address filter consists of a single address range and an action. If a
+ * memory region overlaps the filter's range then the action will be performed.
+ * The possible filter actions are defined by the #AddressFilterAction enumeration.
+ */
+ struct AddressFilter
+ {
+ AddressFilterAction m_action; //!< Action to be performed when the filter is matched.
+ uint32_t m_fromAddress; //!< Start address of the filter. Should be lower than or equal to #m_toAddress.
+ uint32_t m_toAddress; //!< End address of the filter. Should be higher than or equal to #m_fromAddress.
+ unsigned m_priority; //!< Priority for this filter. Zero is the lowest priority.
+
+ //! \brief Constructor.
+ AddressFilter(AddressFilterAction action, uint32_t from, uint32_t to, unsigned priority=0)
+ : m_action(action), m_fromAddress(from), m_toAddress(to), m_priority(priority)
+ {
+ }
+
+ //! \brief Test routine.
+ bool matchesMemoryRegion(const MemoryRegion & region) const;
+
+ //! \brief Compares two address filter objects.
+ int compare(const AddressFilter & other) const;
+
+ //! \name Comparison operators
+ //@{
+ inline bool operator < (const AddressFilter & other) const { return compare(other) == -1; }
+ inline bool operator > (const AddressFilter & other) const { return compare(other) == 1; }
+ inline bool operator == (const AddressFilter & other) const { return compare(other) == 0; }
+ inline bool operator <= (const AddressFilter & other) const { return compare(other) != 1; }
+ inline bool operator >= (const AddressFilter & other) const { return compare(other) != -1; }
+ //@}
+ };
+
+ //! List of #StExecutableImage::AddressFilter objects.
+ typedef std::list<AddressFilter> AddressFilterList;
+
+ //! The exception class raised for the #ADDR_FILTER_ERROR and #ADDR_FILTER_WARNING
+ //! filter actions.
+ class address_filter_exception
+ {
+ public:
+ //! \brief Constructor.
+ //!
+ //! A local copy of \a matchingFilter is made, in case the image and/or filter
+ //! are on the stack and would be disposed of when the exception is raised.
+ address_filter_exception(bool isError, std::string & imageName, const AddressFilter & matchingFilter)
+ : m_isError(isError), m_imageName(imageName), m_filter(matchingFilter)
+ {
+ }
+
+ //! \brief Returns true if the exception is an error. Otherwise the exception
+ //! is for a warning.
+ inline bool isError() const { return m_isError; }
+
+ //! \brief
+ inline std::string getImageName() const { return m_imageName; }
+
+ //! \brief
+ inline const AddressFilter & getMatchingFilter() const { return m_filter; }
+
+ protected:
+ bool m_isError;
+ std::string m_imageName;
+ AddressFilter m_filter;
+ };
+
+public:
+ //! \brief Constructor.
+ StExecutableImage(int inAlignment=256);
+
+ //! \brief Copy constructor.
+ StExecutableImage(const StExecutableImage & inOther);
+
+ //! \brief Destructor.
+ virtual ~StExecutableImage();
+
+ //! \name Image name
+ //! Methods for getting and setting the image name.
+ //@{
+ //! \brief Sets the image's name to \a inName.
+ virtual void setName(const std::string & inName);
+
+ //! \brief Returns a copy of the image's name.
+ virtual std::string getName() const;
+ //@}
+
+ //! \name Regions
+ //! Methods to add and access memory regions.
+ //@{
+ //! \brief Add a region to be filled with zeroes.
+ virtual void addFillRegion(uint32_t inAddress, unsigned inLength);
+
+ //! \brief Add a region containing data to be loaded.
+ virtual void addTextRegion(uint32_t inAddress, const uint8_t * inData, unsigned inLength);
+
+ //! \brief Returns the total number of regions.
+ //!
+ //! Note that this count may not be the same as the number of calls to
+ //! addFillRegion() and addTextRegion() due to region coalescing.
+ inline unsigned getRegionCount() const { return static_cast<unsigned>(m_image.size()); }
+
+ //! \brief Returns a reference to the region specified by \a inIndex.
+ const MemoryRegion & getRegionAtIndex(unsigned inIndex) const;
+
+ //! \brief Return an iterator to the first region.
+ inline const_iterator getRegionBegin() const { return m_image.begin(); }
+
+ //! \brief Return an iterator to the next-after-last region.
+ inline const_iterator getRegionEnd() const { return m_image.end(); }
+ //@}
+
+ //! \name Entry point
+ //@{
+ //! \brief Sets the entry point address.
+ inline void setEntryPoint(uint32_t inEntryAddress) { m_entry = inEntryAddress; m_hasEntry = true; }
+
+ //! \brief Returns true if an entry point has been set.
+ inline bool hasEntryPoint() const { return m_hasEntry; }
+
+ //! \brief Returns the entry point address.
+ inline uint32_t getEntryPoint() const { return hasEntryPoint() ? m_entry : 0; }
+ //@}
+
+ //! \name Address filter
+ //@{
+ //! \brief Add a new address filter.
+ virtual void addAddressFilter(const AddressFilter & filter);
+
+ //! \brief Add multiple address filters at once.
+ //!
+ //! The template argument \a _T must be an iterator or const iterator that
+ //! dereferences to an StExecutableImage::AddressFilter reference. All filters
+ //! from \a from to \a to will be added to the address filter list.
+ template<typename _T> void addAddressFilters(_T from, _T to)
+ {
+ _T it = from;
+ for (; it != to; ++it)
+ {
+ addAddressFilter(*it);
+ }
+ }
+
+ //! \brief Remove all active filters.
+ virtual void clearAddressFilters();
+
+ //! \brief Process all active filters and perform associated actions.
+ virtual void applyAddressFilters();
+ //@}
+
+protected:
+ std::string m_name; //!< The name of the image (can be a file name, for instance).
+ int m_alignment; //!< The required address alignment for each memory region.
+ bool m_hasEntry; //!< True if an entry point has been set.
+ uint32_t m_entry; //!< Entry point address.
+ MemoryRegionList m_image; //!< The memory regions.
+ AddressFilterList m_filters; //!< List of active address filters.
+
+ //! \brief Deletes the portion \a region that overlaps \a filter.
+ void cropRegionToFilter(MemoryRegion & region, const AddressFilter & filter);
+
+ //! \brief Inserts the region in sorted order or merges with one already in the image.
+ void insertOrMergeRegion(MemoryRegion & inRegion);
+
+ //! \brief Merges two memory regions into one.
+ void mergeRegions(MemoryRegion & inOldRegion, MemoryRegion & inNewRegion);
+};
+
+#endif // _StExecutableImage_h_
--- /dev/null
+/*
+ * File: StSRecordFile.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "stdafx.h"
+#include "StSRecordFile.h"
+#include "string.h"
+
+StSRecordFile::StSRecordFile(std::istream & inStream)
+: m_stream(inStream)
+{
+}
+
+//! Frees any data allocated as part of an S-record.
+StSRecordFile::~StSRecordFile()
+{
+ const_iterator it;
+ for (it = m_records.begin(); it != m_records.end(); it++)
+ {
+ SRecord & theRecord = (SRecord &)*it;
+ if (theRecord.m_data)
+ {
+ delete [] theRecord.m_data;
+ theRecord.m_data = NULL;
+ }
+ }
+}
+
+//! Just looks for "S[0-9]" as the first two characters of the file.
+bool StSRecordFile::isSRecordFile()
+{
+ int savePosition = m_stream.tellg();
+ m_stream.seekg(0, std::ios_base::beg);
+
+ char buffer[2];
+ m_stream.read(buffer, 2);
+ bool isSRecord = (buffer[0] == 'S' && isdigit(buffer[1]));
+
+ m_stream.seekg(savePosition, std::ios_base::beg);
+
+ return isSRecord;
+}
+
+//! Extract records one line at a time and hand them to the parseLine()
+//! method. Either CR, LF, or CRLF line endings are supported. The input
+//! stream is read until EOF.
+//! The parse() method must be called after the object has been constructed
+//! before any of the records will become accessible.
+//! \exception StSRecordParseException will be thrown if any error occurs while
+//! parsing the input.
+void StSRecordFile::parse()
+{
+ // back to start of stream
+ m_stream.seekg(0, std::ios_base::beg);
+
+ std::string thisLine;
+
+ do {
+ char thisChar;
+ m_stream.get(thisChar);
+
+ if (thisChar == '\r' || thisChar == '\n')
+ {
+ // skip the LF in a CRLF
+ if (thisChar == '\r' && m_stream.peek() == '\n')
+ m_stream.ignore();
+
+ // parse line if it's not empty
+ if (!thisLine.empty())
+ {
+ parseLine(thisLine);
+
+ // reset line
+ thisLine.clear();
+ }
+ }
+ else
+ {
+ thisLine += thisChar;
+ }
+ } while (!m_stream.eof());
+}
+
+bool StSRecordFile::isHexDigit(char c)
+{
+ return (isdigit(c) || (c >= 'a' && c <= 'f') || (c >= 'A' && c <= 'F'));
+}
+
+int StSRecordFile::hexDigitToInt(char digit)
+{
+ if (isdigit(digit))
+ return digit - '0';
+ else if (digit >= 'a' && digit <= 'f')
+ return 10 + digit - 'a';
+ else if (digit >= 'A' && digit <= 'F')
+ return 10 + digit - 'A';
+
+ // unknow char
+ return 0;
+}
+
+//! \exception StSRecordParseException is thrown if either of the nibble characters
+//! is not a valid hex digit.
+int StSRecordFile::readHexByte(std::string & inString, int inIndex)
+{
+ char nibbleCharHi= inString[inIndex];
+ char nibbleCharLo = inString[inIndex + 1];
+
+ // must be hex digits
+ if (!(isHexDigit(nibbleCharHi) && isHexDigit(nibbleCharLo)))
+ {
+ throw StSRecordParseException("invalid hex digit");
+ }
+
+ return (hexDigitToInt(nibbleCharHi) << 4) | hexDigitToInt(nibbleCharLo);
+}
+
+//! \brief Parses individual S-records.
+//!
+//! Takes a single S-record line as input and appends a new SRecord struct
+//! to the m_records vector.
+//! \exception StSRecordParseException will be thrown if any error occurs while
+//! parsing \a inLine.
+void StSRecordFile::parseLine(std::string & inLine)
+{
+ int checksum = 0;
+ SRecord newRecord;
+ memset(&newRecord, 0, sizeof(newRecord));
+
+ // must start with "S" and be at least a certain length
+ if (inLine[0] != SRECORD_START_CHAR && inLine.length() >= SRECORD_MIN_LENGTH)
+ {
+ throw StSRecordParseException("invalid record length");
+ }
+
+ // parse type field
+ char typeChar = inLine[1];
+ if (!isdigit(typeChar))
+ {
+ throw StSRecordParseException("invalid S-record type");
+ }
+ newRecord.m_type = typeChar - '0';
+
+ // parse count field
+ newRecord.m_count = readHexByte(inLine, 2);
+ checksum += newRecord.m_count;
+
+ // verify the record length now that we know the count
+ if (inLine.length() != 4 + newRecord.m_count * 2)
+ {
+ throw StSRecordParseException("invalid record length");
+ }
+
+ // get address length
+ int addressLength; // len in bytes
+ bool hasData = false;
+ switch (newRecord.m_type)
+ {
+ case 0: // contains header information
+ addressLength = 2;
+ hasData = true;
+ break;
+ case 1: // data record with 2-byte address
+ addressLength = 2;
+ hasData = true;
+ break;
+ case 2: // data record with 3-byte address
+ addressLength = 3;
+ hasData = true;
+ break;
+ case 3: // data record with 4-byte address
+ addressLength = 4;
+ hasData = true;
+ break;
+ case 5: // the 2-byte address field contains a count of all prior S1, S2, and S3 records
+ addressLength = 2;
+ break;
+ case 7: // entry point record with 4-byte address
+ addressLength = 4;
+ break;
+ case 8: // entry point record with 3-byte address
+ addressLength = 3;
+ break;
+ case 9: // entry point record with 2-byte address
+ addressLength = 2;
+ break;
+ default:
+ // unrecognized type
+ //throw StSRecordParseException("unknown S-record type");
+ break;
+ }
+
+ // read address
+ int address = 0;
+ int i;
+ for (i=0; i < addressLength; ++i)
+ {
+ int addressByte = readHexByte(inLine, SRECORD_ADDRESS_START_CHAR_INDEX + i * 2);
+ address = (address << 8) | addressByte;
+ checksum += addressByte;
+ }
+ newRecord.m_address = address;
+
+ // read data
+ if (hasData)
+ {
+ int dataStartCharIndex = 4 + addressLength * 2;
+ int dataLength = newRecord.m_count - addressLength - 1; // total rem - addr - cksum (in bytes)
+ uint8_t * data = new uint8_t[dataLength];
+
+ for (i=0; i < dataLength; ++i)
+ {
+ int dataByte = readHexByte(inLine, dataStartCharIndex + i * 2);
+ data[i] = dataByte;
+ checksum += dataByte;
+ }
+
+ newRecord.m_data = data;
+ newRecord.m_dataCount = dataLength;
+ }
+
+ // read and compare checksum byte
+ checksum = (~checksum) & 0xff; // low byte of one's complement of sum of other bytes
+ newRecord.m_checksum = readHexByte(inLine, (int)inLine.length() - 2);
+ if (checksum != newRecord.m_checksum)
+ {
+ throw StSRecordParseException("invalid checksum");
+ }
+
+ // now save the new S-record
+ m_records.push_back(newRecord);
+}
--- /dev/null
+/*
+ * File: StSRecordFile.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_StSRecordFile_h_)
+#define _StSRecordFile_h_
+
+//#include <stdint.h>
+#include "stdafx.h"
+#include <istream>
+#include <string>
+#include <vector>
+#include <stdexcept>
+
+enum {
+ //! The required first character of an S-record.
+ SRECORD_START_CHAR = 'S',
+
+ //! The minimum length of a S-record. This is the type (2) + count (2) + addr (4) + cksum (2).
+ SRECORD_MIN_LENGTH = 10,
+
+ //! Index of the first character of the address field.
+ SRECORD_ADDRESS_START_CHAR_INDEX = 4
+};
+
+/*!
+ * \brief S-record parser.
+ *
+ * This class takes an input stream and parses it as an S-record file. While
+ * the individual records that comprise the file are available for access, the
+ * class also provides a higher-level view of the contents. It processes the
+ * individual records and builds an image of what the memory touched by the
+ * file looks like. Then you can access the contiguous sections of memory.
+ */
+class StSRecordFile
+{
+public:
+ /*!
+ * Structure representing each individual line of the S-record input data.
+ */
+ struct SRecord
+ {
+ unsigned m_type; //!< Record number type, such as 9 for "S9", 3 for "S3" and so on.
+ unsigned m_count; //!< Number of character pairs (bytes) from address through checksum.
+ uint32_t m_address; //!< The address specified as part of the S-record.
+ unsigned m_dataCount; //!< Number of bytes of data.
+ uint8_t * m_data; //!< Pointer to data, or NULL if no data for this record type.
+ uint8_t m_checksum; //!< The checksum byte present in the S-record.
+ };
+
+ //! Iterator type.
+ typedef std::vector<SRecord>::const_iterator const_iterator;
+
+public:
+ //! \brief Constructor.
+ StSRecordFile(std::istream & inStream);
+
+ //! \brief Destructor.
+ virtual ~StSRecordFile();
+
+ //! \name File name
+ //@{
+ virtual void setName(const std::string & inName) { m_name = inName; }
+ virtual std::string getName() const { return m_name; }
+ //@}
+
+ //! \name Parsing
+ //@{
+ //! \brief Determine if the file is an S-record file.
+ virtual bool isSRecordFile();
+
+ //! \brief Parses the entire S-record input stream.
+ virtual void parse();
+ //@}
+
+ //! \name Record access
+ //@{
+ //! \return the number of S-records that have been parsed from the input stream.
+ inline unsigned getRecordCount() const { return static_cast<unsigned>(m_records.size()); }
+
+ //! \return iterator for
+ inline const_iterator getBegin() const { return m_records.begin(); }
+ inline const_iterator getEnd() const { return m_records.end(); }
+ //@}
+
+ //! \name Operators
+ //@{
+ inline const SRecord & operator [] (unsigned inIndex) { return m_records[inIndex]; }
+ //@}
+
+protected:
+ std::istream& m_stream; //!< The input stream for the S-record data.
+ std::vector<SRecord> m_records; //!< Vector of S-records in the input data.
+
+ std::string m_name; //!< File name. (optional)
+
+ //! \name Parsing utilities
+ //@{
+ virtual void parseLine(std::string & inLine);
+
+ bool isHexDigit(char c);
+ int hexDigitToInt(char digit);
+ int readHexByte(std::string & inString, int inIndex);
+ //@}
+};
+
+/*!
+ * \brief Simple exception thrown to indicate an error in the input SRecord data format.
+ */
+class StSRecordParseException : public std::runtime_error
+{
+public:
+ //! \brief Default constructor.
+ StSRecordParseException(const std::string & inMessage) : std::runtime_error(inMessage) {}
+};
+
+#endif // _StSRecordFile_h_
--- /dev/null
+/*
+ * File: GlobSectionSelector.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_StringMatcher_h_)
+#define _StringMatcher_h_
+
+#include <string>
+
+namespace elftosb
+{
+
+/*!
+ * \brief Abstract interface class used to select strings by name.
+ */
+class StringMatcher
+{
+public:
+ //! \brief Performs a single string match test against testValue.
+ //!
+ //! \retval true The \a testValue argument matches.
+ //! \retval false No match was made against the argument.
+ virtual bool match(const std::string & testValue)=0;
+};
+
+/*!
+ * \brief String matcher subclass that matches all test strings.
+ */
+class WildcardMatcher : public StringMatcher
+{
+public:
+ //! \brief Always returns true, indicating a positive match.
+ virtual bool match(const std::string & testValue) { return true; }
+};
+
+/*!
+ * \brief Simple string matcher that compares against a fixed value.
+ */
+class FixedMatcher : public StringMatcher
+{
+public:
+ //! \brief Constructor. Sets the string to compare against to be \a fixedValue.
+ FixedMatcher(const std::string & fixedValue) : m_value(fixedValue) {}
+
+ //! \brief Returns whether \a testValue is the same as the value passed to the constructor.
+ //!
+ //! \retval true The \a testValue argument matches the fixed compare value.
+ //! \retval false The argument is not the same as the compare value.
+ virtual bool match(const std::string & testValue)
+ {
+ return testValue == m_value;
+ }
+
+protected:
+ const std::string & m_value; //!< The section name to look for.
+};
+
+}; // namespace elftosb
+
+#endif // _StringMatcher_h_
--- /dev/null
+/*
+ * File: Value.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "Value.h"
+
+using namespace elftosb;
+
+//! Returns a varying size depending on the word size attribute.
+//!
+size_t SizedIntegerValue::getSize() const
+{
+ switch (m_size)
+ {
+ case kWordSize:
+ return sizeof(uint32_t);
+ case kHalfWordSize:
+ return sizeof(uint16_t);
+ case kByteSize:
+ return sizeof(uint8_t);
+ }
+ return kWordSize;
+}
+
+//! The resulting mask can be used to truncate the integer value to be
+//! certain it doesn't extend beyond the associated word size.
+uint32_t SizedIntegerValue::getWordSizeMask() const
+{
+ switch (m_size)
+ {
+ case kWordSize:
+ return 0xffffffff;
+ case kHalfWordSize:
+ return 0x0000ffff;
+ case kByteSize:
+ return 0x000000ff;
+ }
+ return 0;
+}
+
--- /dev/null
+/*
+ * File: Value.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_Value_h_)
+#define _Value_h_
+
+#include "stdafx.h"
+#include <string>
+#include "int_size.h"
+#include "Blob.h"
+
+namespace elftosb
+{
+
+/*!
+ * \brief Abstract base class for values of arbitrary types.
+ */
+class Value
+{
+public:
+ Value() {}
+ virtual ~Value() {}
+
+ virtual std::string getTypeName() const = 0;
+ virtual size_t getSize() const = 0;
+};
+
+/*!
+ * \brief 32-bit signed integer value.
+ */
+class IntegerValue : public Value
+{
+public:
+ IntegerValue() : m_value(0) {}
+ IntegerValue(uint32_t value) : m_value(value) {}
+ IntegerValue(const IntegerValue & other) : m_value(other.m_value) {}
+
+ virtual std::string getTypeName() const { return "integer"; }
+ virtual size_t getSize() const { return sizeof(m_value); }
+
+ inline uint32_t getValue() const { return m_value; }
+
+ inline operator uint32_t () const { return m_value; }
+
+ inline IntegerValue & operator = (uint32_t value) { m_value = value; return *this; }
+
+protected:
+ uint32_t m_value; //!< The integer value.
+};
+
+/*!
+ * \brief Adds a word size attribute to IntegerValue.
+ *
+ * The word size really only acts as an attribute that is carried along
+ * with the integer value. It doesn't affect the actual value at all.
+ * However, you can use the getWordSizeMask() method to mask off bits
+ * that should not be there.
+ *
+ * The word size defaults to a 32-bit word.
+ */
+class SizedIntegerValue : public IntegerValue
+{
+public:
+ SizedIntegerValue() : IntegerValue(), m_size(kWordSize) {}
+ SizedIntegerValue(uint32_t value, int_size_t size=kWordSize) : IntegerValue(value), m_size(size) {}
+ SizedIntegerValue(uint16_t value) : IntegerValue(value), m_size(kHalfWordSize) {}
+ SizedIntegerValue(uint8_t value) : IntegerValue(value), m_size(kByteSize) {}
+ SizedIntegerValue(const SizedIntegerValue & other) : IntegerValue(other), m_size(other.m_size) {}
+
+ virtual std::string getTypeName() const { return "sized integer"; }
+ virtual size_t getSize() const;
+
+ inline int_size_t getWordSize() const { return m_size; }
+ inline void setWordSize(int_size_t size) { m_size = size; }
+
+ //! \brief Returns a 32-bit mask value dependant on the word size attribute.
+ uint32_t getWordSizeMask() const;
+
+ //! \name Assignment operators
+ //! These operators set the word size as well as the integer value.
+ //@{
+ SizedIntegerValue & operator = (uint8_t value) { m_value = value; m_size = kByteSize; return *this; }
+ SizedIntegerValue & operator = (uint16_t value) { m_value = value; m_size = kHalfWordSize; return *this; }
+ SizedIntegerValue & operator = (uint32_t value) { m_value = value; m_size = kWordSize; return *this; }
+ //@}
+
+protected:
+ int_size_t m_size; //!< Size of the integer.
+};
+
+/*!
+ * \brief String value.
+ *
+ * Simply wraps the STL std::string class.
+ */
+class StringValue : public Value
+{
+public:
+ StringValue() : m_value() {}
+ StringValue(const std::string & value) : m_value(value) {}
+ StringValue(const std::string * value) : m_value(*value) {}
+ StringValue(const StringValue & other) : m_value(other.m_value) {}
+
+ virtual std::string getTypeName() const { return "string"; }
+ virtual size_t getSize() const { return m_value.size(); }
+
+ operator const char * () const { return m_value.c_str(); }
+ operator const std::string & () const { return m_value; }
+ operator std::string & () { return m_value; }
+ operator const std::string * () { return &m_value; }
+ operator std::string * () { return &m_value; }
+
+ StringValue & operator = (const StringValue & other) { m_value = other.m_value; return *this; }
+ StringValue & operator = (const std::string & value) { m_value = value; return *this; }
+ StringValue & operator = (const char * value) { m_value = value; return *this; }
+
+protected:
+ std::string m_value;
+};
+
+/*!
+ * \brief Binary object value of arbitrary size.
+ */
+class BinaryValue : public Value, public Blob
+{
+public:
+ BinaryValue() : Value(), Blob() {}
+
+ virtual std::string getTypeName() const { return "binary"; }
+ virtual size_t getSize() const { return getLength(); }
+};
+
+}; // namespace elftosb
+
+#endif // _Value_h_
--- /dev/null
+/*
+ * File: Version.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "Version.h"
+#include "EndianUtilities.h"
+
+using namespace elftosb;
+
+/*!
+ * Parses a string in the form "xxx.xxx.xxx" (where x is a digit) into
+ * three version fields for major, minor, and revision. The output is
+ * right aligned BCD in host-natural byte order.
+ *
+ * \param versionString String containing the version.
+ */
+void version_t::set(const std::string & versionString)
+{
+ size_t length = versionString.size();
+ unsigned version = 0;
+ unsigned index = 0;
+
+ typedef enum {
+ kVersionStateNone,
+ kVersionStateMajor,
+ kVersionStateMinor,
+ kVersionStateRevision
+ } VersionParseState;
+
+ // set initial versions to 0s
+ m_major = 0;
+ m_minor = 0;
+ m_revision = 0;
+
+ VersionParseState parseState = kVersionStateNone;
+ bool done = false;
+ for (; index < length && !done; ++index)
+ {
+ char c = versionString[index];
+
+ if (isdigit(c))
+ {
+ switch (parseState)
+ {
+ case kVersionStateNone:
+ parseState = kVersionStateMajor;
+ version = c - '0';
+ break;
+ case kVersionStateMajor:
+ case kVersionStateMinor:
+ case kVersionStateRevision:
+ version = (version << 4) | (c - '0');
+ break;
+ }
+ }
+ else if (c == '.')
+ {
+ switch (parseState)
+ {
+ case kVersionStateNone:
+ parseState = kVersionStateNone;
+ break;
+ case kVersionStateMajor:
+ m_major = version;
+ version = 0;
+ parseState = kVersionStateMinor;
+ break;
+ case kVersionStateMinor:
+ m_minor = version;
+ version = 0;
+ parseState = kVersionStateRevision;
+ break;
+ case kVersionStateRevision:
+ m_revision = version;
+ version = 0;
+ done = true;
+ break;
+ }
+ }
+ else
+ {
+ switch (parseState)
+ {
+ case kVersionStateNone:
+ parseState = kVersionStateNone;
+ break;
+ case kVersionStateMajor:
+ m_major = version;
+ done = true;
+ break;
+ case kVersionStateMinor:
+ m_minor = version;
+ done = true;
+ break;
+ case kVersionStateRevision:
+ m_revision = version;
+ done = true;
+ break;
+ }
+ }
+ }
+
+ switch (parseState)
+ {
+ case kVersionStateMajor:
+ m_major = version;
+ break;
+ case kVersionStateMinor:
+ m_minor = version;
+ break;
+ case kVersionStateRevision:
+ m_revision = version;
+ break;
+ default:
+ // do nothing
+ break;
+ }
+}
+
+//! \brief Converts host endian BCD version values to the equivalent big-endian BCD values.
+//!
+//! The output is a half-word. And BCD is inherently big-endian, or byte ordered, if
+//! you prefer to think of it that way. So for little endian systems, we need to convert
+//! the output half-word in reverse byte order. When it is written to disk or a
+//! buffer it will come out big endian.
+//!
+//! For example:
+//! - The input is BCD in host endian format, so 0x1234. Written to a file, this would
+//! come out as 0x34 0x12, reverse of what we want.
+//! - The desired BCD output is the two bytes 0x12 0x34.
+//! - So the function's uint16_t result must be 0x3412 on a little-endian host.
+//!
+//! On big endian hosts, we don't have to worry about byte swapping.
+void version_t::fixByteOrder()
+{
+ m_major = ENDIAN_HOST_TO_BIG_U16(m_major);
+ m_minor = ENDIAN_HOST_TO_BIG_U16(m_minor);
+ m_revision = ENDIAN_HOST_TO_BIG_U16(m_revision);
+}
+
--- /dev/null
+/*
+ * File: Version.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_Version_h_)
+#define _Version_h_
+
+#include <string>
+#include "stdafx.h"
+
+namespace elftosb
+{
+
+//! Same version struct used for 3600 boot image.
+struct version_t
+{
+ uint16_t m_major;
+ uint16_t m_pad0;
+ uint16_t m_minor;
+ uint16_t m_pad1;
+ uint16_t m_revision;
+ uint16_t m_pad2;
+
+ version_t()
+ : m_major(0x999), m_pad0(0), m_minor(0x999), m_pad1(0), m_revision(0x999), m_pad2(0)
+ {
+ }
+
+ version_t(uint16_t maj, uint16_t min, uint16_t rev)
+ : m_major(maj), m_pad0(0), m_minor(min), m_pad1(0), m_revision(rev), m_pad2(0)
+ {
+ }
+
+ version_t(const std::string & versionString)
+ : m_major(0x999), m_pad0(0), m_minor(0x999), m_pad1(0), m_revision(0x999), m_pad2(0)
+ {
+ set(versionString);
+ }
+
+ //! \brief Sets the version by parsing a string.
+ void set(const std::string & versionString);
+
+ //! \brief
+ void fixByteOrder();
+};
+
+}; // namespace elftosb
+
+#endif // _Version_h_
--- /dev/null
+/*
+ * File: crc.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "crc.h"
+
+//! Table of CRC-32's of all single byte values. The values in
+//! this table are those used in the Ethernet CRC algorithm.
+const uint32_t CRC32::m_tab[] = {
+//#ifdef __LITTLE_ENDIAN__
+ 0x00000000,
+ 0x04c11db7, 0x09823b6e, 0x0d4326d9, 0x130476dc, 0x17c56b6b,
+ 0x1a864db2, 0x1e475005, 0x2608edb8, 0x22c9f00f, 0x2f8ad6d6,
+ 0x2b4bcb61, 0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd,
+ 0x4c11db70, 0x48d0c6c7, 0x4593e01e, 0x4152fda9, 0x5f15adac,
+ 0x5bd4b01b, 0x569796c2, 0x52568b75, 0x6a1936c8, 0x6ed82b7f,
+ 0x639b0da6, 0x675a1011, 0x791d4014, 0x7ddc5da3, 0x709f7b7a,
+ 0x745e66cd, 0x9823b6e0, 0x9ce2ab57, 0x91a18d8e, 0x95609039,
+ 0x8b27c03c, 0x8fe6dd8b, 0x82a5fb52, 0x8664e6e5, 0xbe2b5b58,
+ 0xbaea46ef, 0xb7a96036, 0xb3687d81, 0xad2f2d84, 0xa9ee3033,
+ 0xa4ad16ea, 0xa06c0b5d, 0xd4326d90, 0xd0f37027, 0xddb056fe,
+ 0xd9714b49, 0xc7361b4c, 0xc3f706fb, 0xceb42022, 0xca753d95,
+ 0xf23a8028, 0xf6fb9d9f, 0xfbb8bb46, 0xff79a6f1, 0xe13ef6f4,
+ 0xe5ffeb43, 0xe8bccd9a, 0xec7dd02d, 0x34867077, 0x30476dc0,
+ 0x3d044b19, 0x39c556ae, 0x278206ab, 0x23431b1c, 0x2e003dc5,
+ 0x2ac12072, 0x128e9dcf, 0x164f8078, 0x1b0ca6a1, 0x1fcdbb16,
+ 0x018aeb13, 0x054bf6a4, 0x0808d07d, 0x0cc9cdca, 0x7897ab07,
+ 0x7c56b6b0, 0x71159069, 0x75d48dde, 0x6b93dddb, 0x6f52c06c,
+ 0x6211e6b5, 0x66d0fb02, 0x5e9f46bf, 0x5a5e5b08, 0x571d7dd1,
+ 0x53dc6066, 0x4d9b3063, 0x495a2dd4, 0x44190b0d, 0x40d816ba,
+ 0xaca5c697, 0xa864db20, 0xa527fdf9, 0xa1e6e04e, 0xbfa1b04b,
+ 0xbb60adfc, 0xb6238b25, 0xb2e29692, 0x8aad2b2f, 0x8e6c3698,
+ 0x832f1041, 0x87ee0df6, 0x99a95df3, 0x9d684044, 0x902b669d,
+ 0x94ea7b2a, 0xe0b41de7, 0xe4750050, 0xe9362689, 0xedf73b3e,
+ 0xf3b06b3b, 0xf771768c, 0xfa325055, 0xfef34de2, 0xc6bcf05f,
+ 0xc27dede8, 0xcf3ecb31, 0xcbffd686, 0xd5b88683, 0xd1799b34,
+ 0xdc3abded, 0xd8fba05a, 0x690ce0ee, 0x6dcdfd59, 0x608edb80,
+ 0x644fc637, 0x7a089632, 0x7ec98b85, 0x738aad5c, 0x774bb0eb,
+ 0x4f040d56, 0x4bc510e1, 0x46863638, 0x42472b8f, 0x5c007b8a,
+ 0x58c1663d, 0x558240e4, 0x51435d53, 0x251d3b9e, 0x21dc2629,
+ 0x2c9f00f0, 0x285e1d47, 0x36194d42, 0x32d850f5, 0x3f9b762c,
+ 0x3b5a6b9b, 0x0315d626, 0x07d4cb91, 0x0a97ed48, 0x0e56f0ff,
+ 0x1011a0fa, 0x14d0bd4d, 0x19939b94, 0x1d528623, 0xf12f560e,
+ 0xf5ee4bb9, 0xf8ad6d60, 0xfc6c70d7, 0xe22b20d2, 0xe6ea3d65,
+ 0xeba91bbc, 0xef68060b, 0xd727bbb6, 0xd3e6a601, 0xdea580d8,
+ 0xda649d6f, 0xc423cd6a, 0xc0e2d0dd, 0xcda1f604, 0xc960ebb3,
+ 0xbd3e8d7e, 0xb9ff90c9, 0xb4bcb610, 0xb07daba7, 0xae3afba2,
+ 0xaafbe615, 0xa7b8c0cc, 0xa379dd7b, 0x9b3660c6, 0x9ff77d71,
+ 0x92b45ba8, 0x9675461f, 0x8832161a, 0x8cf30bad, 0x81b02d74,
+ 0x857130c3, 0x5d8a9099, 0x594b8d2e, 0x5408abf7, 0x50c9b640,
+ 0x4e8ee645, 0x4a4ffbf2, 0x470cdd2b, 0x43cdc09c, 0x7b827d21,
+ 0x7f436096, 0x7200464f, 0x76c15bf8, 0x68860bfd, 0x6c47164a,
+ 0x61043093, 0x65c52d24, 0x119b4be9, 0x155a565e, 0x18197087,
+ 0x1cd86d30, 0x029f3d35, 0x065e2082, 0x0b1d065b, 0x0fdc1bec,
+ 0x3793a651, 0x3352bbe6, 0x3e119d3f, 0x3ad08088, 0x2497d08d,
+ 0x2056cd3a, 0x2d15ebe3, 0x29d4f654, 0xc5a92679, 0xc1683bce,
+ 0xcc2b1d17, 0xc8ea00a0, 0xd6ad50a5, 0xd26c4d12, 0xdf2f6bcb,
+ 0xdbee767c, 0xe3a1cbc1, 0xe760d676, 0xea23f0af, 0xeee2ed18,
+ 0xf0a5bd1d, 0xf464a0aa, 0xf9278673, 0xfde69bc4, 0x89b8fd09,
+ 0x8d79e0be, 0x803ac667, 0x84fbdbd0, 0x9abc8bd5, 0x9e7d9662,
+ 0x933eb0bb, 0x97ffad0c, 0xafb010b1, 0xab710d06, 0xa6322bdf,
+ 0xa2f33668, 0xbcb4666d, 0xb8757bda, 0xb5365d03, 0xb1f740b4
+//#else
+// 0x00000000,
+// 0xb71dc104, 0x6e3b8209, 0xd926430d, 0xdc760413, 0x6b6bc517,
+// 0xb24d861a, 0x0550471e, 0xb8ed0826, 0x0ff0c922, 0xd6d68a2f,
+// 0x61cb4b2b, 0x649b0c35, 0xd386cd31, 0x0aa08e3c, 0xbdbd4f38,
+// 0x70db114c, 0xc7c6d048, 0x1ee09345, 0xa9fd5241, 0xacad155f,
+// 0x1bb0d45b, 0xc2969756, 0x758b5652, 0xc836196a, 0x7f2bd86e,
+// 0xa60d9b63, 0x11105a67, 0x14401d79, 0xa35ddc7d, 0x7a7b9f70,
+// 0xcd665e74, 0xe0b62398, 0x57abe29c, 0x8e8da191, 0x39906095,
+// 0x3cc0278b, 0x8bdde68f, 0x52fba582, 0xe5e66486, 0x585b2bbe,
+// 0xef46eaba, 0x3660a9b7, 0x817d68b3, 0x842d2fad, 0x3330eea9,
+// 0xea16ada4, 0x5d0b6ca0, 0x906d32d4, 0x2770f3d0, 0xfe56b0dd,
+// 0x494b71d9, 0x4c1b36c7, 0xfb06f7c3, 0x2220b4ce, 0x953d75ca,
+// 0x28803af2, 0x9f9dfbf6, 0x46bbb8fb, 0xf1a679ff, 0xf4f63ee1,
+// 0x43ebffe5, 0x9acdbce8, 0x2dd07dec, 0x77708634, 0xc06d4730,
+// 0x194b043d, 0xae56c539, 0xab068227, 0x1c1b4323, 0xc53d002e,
+// 0x7220c12a, 0xcf9d8e12, 0x78804f16, 0xa1a60c1b, 0x16bbcd1f,
+// 0x13eb8a01, 0xa4f64b05, 0x7dd00808, 0xcacdc90c, 0x07ab9778,
+// 0xb0b6567c, 0x69901571, 0xde8dd475, 0xdbdd936b, 0x6cc0526f,
+// 0xb5e61162, 0x02fbd066, 0xbf469f5e, 0x085b5e5a, 0xd17d1d57,
+// 0x6660dc53, 0x63309b4d, 0xd42d5a49, 0x0d0b1944, 0xba16d840,
+// 0x97c6a5ac, 0x20db64a8, 0xf9fd27a5, 0x4ee0e6a1, 0x4bb0a1bf,
+// 0xfcad60bb, 0x258b23b6, 0x9296e2b2, 0x2f2bad8a, 0x98366c8e,
+// 0x41102f83, 0xf60dee87, 0xf35da999, 0x4440689d, 0x9d662b90,
+// 0x2a7bea94, 0xe71db4e0, 0x500075e4, 0x892636e9, 0x3e3bf7ed,
+// 0x3b6bb0f3, 0x8c7671f7, 0x555032fa, 0xe24df3fe, 0x5ff0bcc6,
+// 0xe8ed7dc2, 0x31cb3ecf, 0x86d6ffcb, 0x8386b8d5, 0x349b79d1,
+// 0xedbd3adc, 0x5aa0fbd8, 0xeee00c69, 0x59fdcd6d, 0x80db8e60,
+// 0x37c64f64, 0x3296087a, 0x858bc97e, 0x5cad8a73, 0xebb04b77,
+// 0x560d044f, 0xe110c54b, 0x38368646, 0x8f2b4742, 0x8a7b005c,
+// 0x3d66c158, 0xe4408255, 0x535d4351, 0x9e3b1d25, 0x2926dc21,
+// 0xf0009f2c, 0x471d5e28, 0x424d1936, 0xf550d832, 0x2c769b3f,
+// 0x9b6b5a3b, 0x26d61503, 0x91cbd407, 0x48ed970a, 0xfff0560e,
+// 0xfaa01110, 0x4dbdd014, 0x949b9319, 0x2386521d, 0x0e562ff1,
+// 0xb94beef5, 0x606dadf8, 0xd7706cfc, 0xd2202be2, 0x653deae6,
+// 0xbc1ba9eb, 0x0b0668ef, 0xb6bb27d7, 0x01a6e6d3, 0xd880a5de,
+// 0x6f9d64da, 0x6acd23c4, 0xddd0e2c0, 0x04f6a1cd, 0xb3eb60c9,
+// 0x7e8d3ebd, 0xc990ffb9, 0x10b6bcb4, 0xa7ab7db0, 0xa2fb3aae,
+// 0x15e6fbaa, 0xccc0b8a7, 0x7bdd79a3, 0xc660369b, 0x717df79f,
+// 0xa85bb492, 0x1f467596, 0x1a163288, 0xad0bf38c, 0x742db081,
+// 0xc3307185, 0x99908a5d, 0x2e8d4b59, 0xf7ab0854, 0x40b6c950,
+// 0x45e68e4e, 0xf2fb4f4a, 0x2bdd0c47, 0x9cc0cd43, 0x217d827b,
+// 0x9660437f, 0x4f460072, 0xf85bc176, 0xfd0b8668, 0x4a16476c,
+// 0x93300461, 0x242dc565, 0xe94b9b11, 0x5e565a15, 0x87701918,
+// 0x306dd81c, 0x353d9f02, 0x82205e06, 0x5b061d0b, 0xec1bdc0f,
+// 0x51a69337, 0xe6bb5233, 0x3f9d113e, 0x8880d03a, 0x8dd09724,
+// 0x3acd5620, 0xe3eb152d, 0x54f6d429, 0x7926a9c5, 0xce3b68c1,
+// 0x171d2bcc, 0xa000eac8, 0xa550add6, 0x124d6cd2, 0xcb6b2fdf,
+// 0x7c76eedb, 0xc1cba1e3, 0x76d660e7, 0xaff023ea, 0x18ede2ee,
+// 0x1dbda5f0, 0xaaa064f4, 0x738627f9, 0xc49be6fd, 0x09fdb889,
+// 0xbee0798d, 0x67c63a80, 0xd0dbfb84, 0xd58bbc9a, 0x62967d9e,
+// 0xbbb03e93, 0x0cadff97, 0xb110b0af, 0x060d71ab, 0xdf2b32a6,
+// 0x6836f3a2, 0x6d66b4bc, 0xda7b75b8, 0x035d36b5, 0xb440f7b1
+//#endif // __LITTLE_ENDIAN__
+
+// This is the original table that came with this source.
+//#ifdef __LITTLE_ENDIAN__
+// 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
+// 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
+// 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
+// 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL,
+// 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L,
+// 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L,
+// 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L,
+// 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,
+// 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L,
+// 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL,
+// 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L,
+// 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L,
+// 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L,
+// 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL,
+// 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL,
+// 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,
+// 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL,
+// 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L,
+// 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L,
+// 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L,
+// 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL,
+// 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L,
+// 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L,
+// 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,
+// 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L,
+// 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L,
+// 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L,
+// 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L,
+// 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L,
+// 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL,
+// 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL,
+// 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,
+// 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L,
+// 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL,
+// 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL,
+// 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L,
+// 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL,
+// 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L,
+// 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL,
+// 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,
+// 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL,
+// 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L,
+// 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L,
+// 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL,
+// 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L,
+// 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L,
+// 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L,
+// 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,
+// 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L,
+// 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L,
+// 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL,
+// 0x2d02ef8dL
+//#else
+// 0x00000000L, 0x96300777L, 0x2c610eeeL, 0xba510999L, 0x19c46d07L,
+// 0x8ff46a70L, 0x35a563e9L, 0xa395649eL, 0x3288db0eL, 0xa4b8dc79L,
+// 0x1ee9d5e0L, 0x88d9d297L, 0x2b4cb609L, 0xbd7cb17eL, 0x072db8e7L,
+// 0x911dbf90L, 0x6410b71dL, 0xf220b06aL, 0x4871b9f3L, 0xde41be84L,
+// 0x7dd4da1aL, 0xebe4dd6dL, 0x51b5d4f4L, 0xc785d383L, 0x56986c13L,
+// 0xc0a86b64L, 0x7af962fdL, 0xecc9658aL, 0x4f5c0114L, 0xd96c0663L,
+// 0x633d0ffaL, 0xf50d088dL, 0xc8206e3bL, 0x5e10694cL, 0xe44160d5L,
+// 0x727167a2L, 0xd1e4033cL, 0x47d4044bL, 0xfd850dd2L, 0x6bb50aa5L,
+// 0xfaa8b535L, 0x6c98b242L, 0xd6c9bbdbL, 0x40f9bcacL, 0xe36cd832L,
+// 0x755cdf45L, 0xcf0dd6dcL, 0x593dd1abL, 0xac30d926L, 0x3a00de51L,
+// 0x8051d7c8L, 0x1661d0bfL, 0xb5f4b421L, 0x23c4b356L, 0x9995bacfL,
+// 0x0fa5bdb8L, 0x9eb80228L, 0x0888055fL, 0xb2d90cc6L, 0x24e90bb1L,
+// 0x877c6f2fL, 0x114c6858L, 0xab1d61c1L, 0x3d2d66b6L, 0x9041dc76L,
+// 0x0671db01L, 0xbc20d298L, 0x2a10d5efL, 0x8985b171L, 0x1fb5b606L,
+// 0xa5e4bf9fL, 0x33d4b8e8L, 0xa2c90778L, 0x34f9000fL, 0x8ea80996L,
+// 0x18980ee1L, 0xbb0d6a7fL, 0x2d3d6d08L, 0x976c6491L, 0x015c63e6L,
+// 0xf4516b6bL, 0x62616c1cL, 0xd8306585L, 0x4e0062f2L, 0xed95066cL,
+// 0x7ba5011bL, 0xc1f40882L, 0x57c40ff5L, 0xc6d9b065L, 0x50e9b712L,
+// 0xeab8be8bL, 0x7c88b9fcL, 0xdf1ddd62L, 0x492dda15L, 0xf37cd38cL,
+// 0x654cd4fbL, 0x5861b24dL, 0xce51b53aL, 0x7400bca3L, 0xe230bbd4L,
+// 0x41a5df4aL, 0xd795d83dL, 0x6dc4d1a4L, 0xfbf4d6d3L, 0x6ae96943L,
+// 0xfcd96e34L, 0x468867adL, 0xd0b860daL, 0x732d0444L, 0xe51d0333L,
+// 0x5f4c0aaaL, 0xc97c0dddL, 0x3c710550L, 0xaa410227L, 0x10100bbeL,
+// 0x86200cc9L, 0x25b56857L, 0xb3856f20L, 0x09d466b9L, 0x9fe461ceL,
+// 0x0ef9de5eL, 0x98c9d929L, 0x2298d0b0L, 0xb4a8d7c7L, 0x173db359L,
+// 0x810db42eL, 0x3b5cbdb7L, 0xad6cbac0L, 0x2083b8edL, 0xb6b3bf9aL,
+// 0x0ce2b603L, 0x9ad2b174L, 0x3947d5eaL, 0xaf77d29dL, 0x1526db04L,
+// 0x8316dc73L, 0x120b63e3L, 0x843b6494L, 0x3e6a6d0dL, 0xa85a6a7aL,
+// 0x0bcf0ee4L, 0x9dff0993L, 0x27ae000aL, 0xb19e077dL, 0x44930ff0L,
+// 0xd2a30887L, 0x68f2011eL, 0xfec20669L, 0x5d5762f7L, 0xcb676580L,
+// 0x71366c19L, 0xe7066b6eL, 0x761bd4feL, 0xe02bd389L, 0x5a7ada10L,
+// 0xcc4add67L, 0x6fdfb9f9L, 0xf9efbe8eL, 0x43beb717L, 0xd58eb060L,
+// 0xe8a3d6d6L, 0x7e93d1a1L, 0xc4c2d838L, 0x52f2df4fL, 0xf167bbd1L,
+// 0x6757bca6L, 0xdd06b53fL, 0x4b36b248L, 0xda2b0dd8L, 0x4c1b0aafL,
+// 0xf64a0336L, 0x607a0441L, 0xc3ef60dfL, 0x55df67a8L, 0xef8e6e31L,
+// 0x79be6946L, 0x8cb361cbL, 0x1a8366bcL, 0xa0d26f25L, 0x36e26852L,
+// 0x95770cccL, 0x03470bbbL, 0xb9160222L, 0x2f260555L, 0xbe3bbac5L,
+// 0x280bbdb2L, 0x925ab42bL, 0x046ab35cL, 0xa7ffd7c2L, 0x31cfd0b5L,
+// 0x8b9ed92cL, 0x1daede5bL, 0xb0c2649bL, 0x26f263ecL, 0x9ca36a75L,
+// 0x0a936d02L, 0xa906099cL, 0x3f360eebL, 0x85670772L, 0x13570005L,
+// 0x824abf95L, 0x147ab8e2L, 0xae2bb17bL, 0x381bb60cL, 0x9b8ed292L,
+// 0x0dbed5e5L, 0xb7efdc7cL, 0x21dfdb0bL, 0xd4d2d386L, 0x42e2d4f1L,
+// 0xf8b3dd68L, 0x6e83da1fL, 0xcd16be81L, 0x5b26b9f6L, 0xe177b06fL,
+// 0x7747b718L, 0xe65a0888L, 0x706a0fffL, 0xca3b0666L, 0x5c0b0111L,
+// 0xff9e658fL, 0x69ae62f8L, 0xd3ff6b61L, 0x45cf6c16L, 0x78e20aa0L,
+// 0xeed20dd7L, 0x5483044eL, 0xc2b30339L, 0x612667a7L, 0xf71660d0L,
+// 0x4d476949L, 0xdb776e3eL, 0x4a6ad1aeL, 0xdc5ad6d9L, 0x660bdf40L,
+// 0xf03bd837L, 0x53aebca9L, 0xc59ebbdeL, 0x7fcfb247L, 0xe9ffb530L,
+// 0x1cf2bdbdL, 0x8ac2bacaL, 0x3093b353L, 0xa6a3b424L, 0x0536d0baL,
+// 0x9306d7cdL, 0x2957de54L, 0xbf67d923L, 0x2e7a66b3L, 0xb84a61c4L,
+// 0x021b685dL, 0x942b6f2aL, 0x37be0bb4L, 0xa18e0cc3L, 0x1bdf055aL,
+// 0x8def022dL
+//#endif
+};
+
+CRC32::CRC32()
+{
+ reset();
+}
+
+void CRC32::update(const uint8_t * s, unsigned n)
+{
+ uint32_t crc = m_crc;
+ m_count += n;
+
+ while (n--)
+ {
+ uint8_t c = *s++ & 0xff;
+ crc = (crc << 8) ^ m_tab[(crc >> 24) ^ c];
+ }
+
+// for(; !((reinterpret_cast<uint32_t>(s) & 0x3) == 0) && n > 0; n--)
+// {
+// crc = m_tab[CRC32_INDEX(crc) ^ *s++] ^ CRC32_SHIFTED(crc);
+// }
+//
+// while (n >= 4)
+// {
+// crc ^= *(const uint32_t *)s;
+// crc = m_tab[CRC32_INDEX(crc)] ^ CRC32_SHIFTED(crc);
+// crc = m_tab[CRC32_INDEX(crc)] ^ CRC32_SHIFTED(crc);
+// crc = m_tab[CRC32_INDEX(crc)] ^ CRC32_SHIFTED(crc);
+// crc = m_tab[CRC32_INDEX(crc)] ^ CRC32_SHIFTED(crc);
+// n -= 4;
+// s += 4;
+// }
+//
+// while (n--)
+// {
+// crc = m_tab[CRC32_INDEX(crc) ^ *s++] ^ CRC32_SHIFTED(crc);
+// }
+
+ m_crc = crc;
+}
+
+void CRC32::truncatedFinal(uint8_t * hash, unsigned size)
+{
+ // pad with zeroes
+ if (m_count % 4)
+ {
+ unsigned i;
+ for (i = m_count % 4; i < 4; i++) {
+ m_crc = (m_crc << 8) ^ m_tab[(m_crc >> 24) ^ 0];
+ }
+ }
+
+// m_crc ^= CRC32_NEGL;
+
+ unsigned i;
+ for (i=0; i<size; i++)
+ {
+ hash[i] = getCrcByte(i);
+ }
+
+ reset();
+}
+
--- /dev/null
+/*
+ * File: crc.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_crc_h_)
+#define CRYPTOPP_CRC32_H
+
+#include "stdafx.h"
+
+const uint32_t CRC32_NEGL = 0xffffffffL;
+
+#ifdef __LITTLE_ENDIAN__
+ #define CRC32_INDEX(c) (c & 0xff)
+ #define CRC32_SHIFTED(c) (c >> 8)
+#else
+ #define CRC32_INDEX(c) (c >> 24)
+ #define CRC32_SHIFTED(c) (c << 8)
+#endif
+
+//! CRC Checksum Calculation
+class CRC32
+{
+public:
+ enum
+ {
+ DIGESTSIZE = 4
+ };
+
+ CRC32();
+
+ void update(const uint8_t * input, unsigned length);
+
+ void truncatedFinal(uint8_t * hash, unsigned size);
+
+ void updateByte(uint8_t b) { m_crc = m_tab[CRC32_INDEX(m_crc) ^ b] ^ CRC32_SHIFTED(m_crc); }
+ uint8_t getCrcByte(unsigned i) const { return ((uint8_t *)&(m_crc))[i]; }
+
+private:
+ void reset() { m_crc = CRC32_NEGL; m_count = 0; }
+
+ static const uint32_t m_tab[256];
+ uint32_t m_crc;
+ unsigned m_count;
+};
+
+#endif // _crc_h_
--- /dev/null
+/*
+ * File: format_string.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "format_string.h"
+#include <stdio.h>
+#include <stdarg.h>
+#include <stdexcept>
+#include <string.h>
+#include <stdlib.h>
+//! Size of the temporary buffer to hold the formatted output string.
+#define WIN32_FMT_BUF_LEN (512)
+
+/*!
+ * \brief Simple template class to free a pointer.
+ */
+template <typename T>
+class free_ptr
+{
+public:
+ //! \brief Constructor.
+ free_ptr(T ptr)
+ : m_p(ptr)
+ {
+ }
+
+ //! \brief Destructor.
+ ~free_ptr()
+ {
+ if (m_p)
+ {
+ free(m_p);
+ }
+ }
+
+protected:
+ T m_p; //!< The value to free.
+};
+
+//! The purpose of this function to provide a convenient way of generating formatted
+//! STL strings inline. This is especially useful when throwing exceptions that take
+//! a std::string for a message. The length of the formatted output string is limited
+//! only by memory. Memory temporarily allocated for the output string is disposed of
+//! before returning.
+//!
+//! Example usage:
+//! \code
+//! throw std::runtime_error(format_string("error on line %d", line));
+//! \endcode
+//!
+//! \param fmt Format string using printf-style format markers.
+//! \return An STL string object of the formatted output.
+std::string format_string(const char * fmt, ...)
+{
+ char * buf = 0;
+ va_list vargs;
+ va_start(vargs, fmt);
+ int result = -1;
+#if WIN32
+ buf = (char *)malloc(WIN32_FMT_BUF_LEN);
+ if (buf)
+ {
+ result = _vsnprintf(buf, WIN32_FMT_BUF_LEN, fmt, vargs);
+ }
+#else // WIN32
+ result = vasprintf(&buf, fmt, vargs);
+#endif // WIN32
+ va_end(vargs);
+ if (result != -1 && buf)
+ {
+ free_ptr<char *> freebuf(buf);
+ return std::string(buf);
+ }
+ return "";
+}
+
--- /dev/null
+/*
+ * File: format_string.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_format_string_h_)
+#define _format_string_h_
+
+#include <string>
+#include <stdexcept>
+
+/*!
+ * \brief Returns a formatted STL string using printf format strings.
+ */
+std::string format_string(const char * fmt, ...);
+
+
+#endif // _format_string_h_
+
--- /dev/null
+/*
+ * File: int_size.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_int_size_h_)
+#define _int_size_h_
+
+namespace elftosb
+{
+
+//! Supported sizes of integers.
+typedef enum {
+ kWordSize, //!< 32-bit word.
+ kHalfWordSize, //!< 16-bit half word.
+ kByteSize //!< 8-bit byte.
+} int_size_t;
+
+}; // namespace elftosb
+
+#endif // _int_size_h_
--- /dev/null
+// ****************************************************************************
+// ^FILE: options.c - implement the functions defined in <options.h>
+//
+// ^HISTORY:
+// 01/16/92 Brad Appleton <bradapp@enteract.com> Created
+//
+// 03/23/93 Brad Appleton <bradapp@enteract.com>
+// - Added OptIstreamIter class
+//
+// 10/08/93 Brad Appleton <bradapp@enteract.com>
+// - Added "hidden" options
+//
+// 02/08/94 Brad Appleton <bradapp@enteract.com>
+// - Added "OptionSpec" class
+// - Permitted use of stdio instead of iostreams via #ifdef USE_STDIO
+//
+// 03/08/94 Brad Appleton <bradapp@enteract.com>
+// - completed support for USE_STDIO
+// - added #ifdef NO_USAGE for people who always want to print their own
+// - Fixed stupid NULL pointer error in OptionsSpec class
+//
+// 07/31/97 Brad Appleton <bradapp@enteract.com>
+// - Added PARSE_POS control flag and POSITIONAL return value.
+// ^^**************************************************************************
+
+// #include <stdlib.h>
+#include <ctype.h>
+#include <string.h>
+
+#include "options.h"
+
+using namespace std;
+
+extern "C" {
+ void exit(int);
+}
+
+static const char ident[] = "@(#)Options 1.05" ;
+
+ // I need a portable version of "tolower" that does NOT modify
+ // non-uppercase characters.
+ //
+#define TOLOWER(c) (isupper(c) ? tolower(c) : c)
+
+ // Use this to shut the compiler up about NULL strings
+#define NULLSTR (char *)NULL
+
+// ******************************************************** insertion operators
+
+ // If you are using <stdio.h> then you need this stuff!
+ // If you are using <iostream.h> then #ifdef this stuff out
+ //
+
+
+#ifdef USE_STDIO
+
+ // Implement just enough of ostream to get this file to compile
+ //
+
+static const char endl = '\n' ;
+
+class ostream {
+public:
+ ostream(FILE * fileptr) : fp(fileptr) {}
+
+ ostream &
+ operator<<(char ch);
+
+ ostream &
+ operator<<(const char * str);
+
+ ostream &
+ write(const char * buf, unsigned bufsize);
+
+private:
+ FILE * fp;
+} ;
+
+ostream &
+ostream::operator<<(char ch) {
+ fputc(ch, fp);
+ return *this;
+}
+
+ostream &
+ostream::operator<<(const char * str) {
+ fputs(str, fp);
+ return *this;
+}
+
+ostream &
+ostream::write(const char * buf, unsigned ) {
+ fputs(buf, fp);
+ return *this;
+}
+
+static ostream cerr(stderr);
+static ostream cout(stdout);
+
+#endif /* USE_STDIO */
+
+// ************************************************************** OptIter
+
+OptIter::~OptIter(void) {}
+
+const char *
+OptIter::operator()(void) {
+ const char * elt = curr();
+ (void) next();
+ return elt;
+}
+
+// ************************************************************** OptIterRwd
+
+OptIterRwd::OptIterRwd(void) {}
+
+OptIterRwd::~OptIterRwd(void) {}
+
+// ************************************************************** OptArgvIter
+
+OptArgvIter::~OptArgvIter(void) {}
+
+const char *
+OptArgvIter::curr(void) {
+ return ((ndx == ac) || (av[ndx] == NULL)) ? NULLSTR : av[ndx];
+}
+
+void
+OptArgvIter::next(void) {
+ if ((ndx != ac) && av[ndx]) ++ndx;
+}
+
+const char *
+OptArgvIter::operator()(void) {
+ return ((ndx == ac) || (av[ndx] == NULL)) ? NULLSTR : av[ndx++];
+}
+
+void
+OptArgvIter::rewind(void) { ndx = 0; }
+
+// ************************************************************** OptStrTokIter
+
+static const char WHITESPACE[] = " \t\n\r\v\f" ;
+const char * OptStrTokIter::default_delims = WHITESPACE ;
+
+OptStrTokIter::OptStrTokIter(const char * tokens, const char * delimiters)
+ : len(unsigned(strlen(tokens))), str(tokens), seps(delimiters),
+ cur(NULLSTR), tokstr(NULLSTR)
+{
+ if (seps == NULL) seps = default_delims;
+ tokstr = new char[len + 1];
+ (void) ::strcpy(tokstr, str);
+ cur = ::strtok(tokstr, seps);
+}
+
+
+OptStrTokIter::~OptStrTokIter(void) { delete [] tokstr; }
+
+const char *
+OptStrTokIter::curr(void) { return cur; }
+
+void
+OptStrTokIter::next(void) { if (cur) cur = ::strtok(NULL, seps); }
+
+const char *
+OptStrTokIter::operator()(void) {
+ const char * elt = cur;
+ if (cur) cur = ::strtok(NULL, seps);
+ return elt;
+}
+
+void
+OptStrTokIter::rewind(void) {
+ (void) ::strcpy(tokstr, str);
+ cur = ::strtok(tokstr, seps);
+}
+
+// ************************************************************* OptIstreamIter
+
+#ifdef vms
+ enum { c_COMMENT = '!' } ;
+#else
+ enum { c_COMMENT = '#' } ;
+#endif
+
+const unsigned OptIstreamIter::MAX_LINE_LEN = 1024 ;
+
+ // Constructor
+OptIstreamIter::OptIstreamIter(istream & input) : is(input), tok_iter(NULL)
+{
+#ifdef USE_STDIO
+ fprintf(stderr, "%s: Can't use OptIstreamIter class:\n",
+ "OptIstreamIter::OptIstreamIter");
+ fprintf(stderr, "\tOptions(3C++) was compiled with USE_STDIO #defined.\n");
+ exit(-1);
+#endif /* USE_STDIO */
+}
+
+ // Destructor
+OptIstreamIter::~OptIstreamIter(void) {
+ delete tok_iter;
+}
+
+const char *
+OptIstreamIter::curr(void) {
+#ifdef USE_STDIO
+ return NULLSTR;
+#else
+ const char * result = NULLSTR;
+ if (tok_iter) result = tok_iter->curr();
+ if (result) return result;
+ fill();
+ return (! is) ? NULLSTR : tok_iter->curr();
+#endif /* USE_STDIO */
+}
+
+void
+OptIstreamIter::next(void) {
+#ifdef USE_STDIO
+ return;
+#else
+ const char * result = NULLSTR;
+ if (tok_iter) result = tok_iter->operator()();
+ if (result) return;
+ fill();
+ if (! is) tok_iter->next();
+#endif /* USE_STDIO */
+}
+
+const char *
+OptIstreamIter::operator()(void) {
+#ifdef USE_STDIO
+ return NULLSTR;
+#else
+ const char * result = NULLSTR;
+ if (tok_iter) result = tok_iter->operator()();
+ if (result) return result;
+ fill();
+ return (! is) ? NULLSTR : tok_iter->operator()();
+#endif /* USE_STDIO */
+}
+
+ // What we do is this: for each line of text in the istream, we use
+ // a OptStrTokIter to iterate over each token on the line.
+ //
+ // If the first non-white character on a line is c_COMMENT, then we
+ // consider the line to be a comment and we ignore it.
+ //
+void
+OptIstreamIter::fill(void) {
+#ifdef USE_STDIO
+ return;
+#else
+ char buf[OptIstreamIter::MAX_LINE_LEN];
+ do {
+ *buf = '\0';
+ is.getline(buf, sizeof(buf));
+ char * ptr = buf;
+ while (isspace(*ptr)) ++ptr;
+ if (*ptr && (*ptr != c_COMMENT)) {
+ delete tok_iter;
+ tok_iter = new OptStrTokIter(ptr);
+ return;
+ }
+ } while (is);
+#endif /* USE_STDIO */
+}
+
+// **************************************************** Options class utilities
+
+ // Is this option-char null?
+inline static int
+isNullOpt(char optchar) {
+ return ((! optchar) || isspace(optchar) || (! isprint(optchar)));
+}
+
+ // Check for explicit "end-of-options"
+inline static int
+isEndOpts(const char * token) {
+ return ((token == NULL) || (! ::strcmp(token, "--"))) ;
+}
+
+ // See if an argument is an option
+inline static int
+isOption(unsigned flags, const char * arg) {
+ return (((*arg != '\0') || (arg[1] != '\0')) &&
+ ((*arg == '-') || ((flags & Options::PLUS) && (*arg == '+')))) ;
+}
+
+ // See if we should be parsing only options or if we also need to
+ // parse positional arguments
+inline static int
+isOptsOnly(unsigned flags) {
+ return (flags & Options::PARSE_POS) ? 0 : 1;
+}
+
+ // return values for a keyword matching function
+enum kwdmatch_t { NO_MATCH, PARTIAL_MATCH, EXACT_MATCH } ;
+
+// ---------------------------------------------------------------------------
+// ^FUNCTION: kwdmatch - match a keyword
+//
+// ^SYNOPSIS:
+// static kwdmatch_t kwdmatch(src, attempt, len)
+//
+// ^PARAMETERS:
+// char * src -- the actual keyword to match
+// char * attempt -- the possible keyword to compare against "src"
+// int len -- number of character of "attempt" to consider
+// (if 0 then we should use all of "attempt")
+//
+// ^DESCRIPTION:
+// See if "attempt" matches some prefix of "src" (case insensitive).
+//
+// ^REQUIREMENTS:
+// - attempt should be non-NULL and non-empty
+//
+// ^SIDE-EFFECTS:
+// None.
+//
+// ^RETURN-VALUE:
+// An enumeration value of type kwdmatch_t corresponding to whether
+// We had an exact match, a partial match, or no match.
+//
+// ^ALGORITHM:
+// Trivial
+// ^^-------------------------------------------------------------------------
+static kwdmatch_t
+kwdmatch(const char * src, const char * attempt, int len =0) {
+ int i;
+
+ if (src == attempt) return EXACT_MATCH ;
+ if ((src == NULL) || (attempt == NULL)) return NO_MATCH ;
+ if ((! *src) && (! *attempt)) return EXACT_MATCH ;
+ if ((! *src) || (! *attempt)) return NO_MATCH ;
+
+ for (i = 0 ; ((i < len) || (len == 0)) &&
+ (attempt[i]) && (attempt[i] != ' ') ; i++) {
+ if (TOLOWER(src[i]) != TOLOWER(attempt[i])) return NO_MATCH ;
+ }
+
+ return (src[i]) ? PARTIAL_MATCH : EXACT_MATCH ;
+}
+
+// **************************************************************** OptionSpec
+
+ // Class that represents an option-specification
+ // *NOTE*:: Assumes that the char-ptr given to the constructor points
+ // to storage that will NOT be modified and whose lifetime will
+ // be as least as long as the OptionSpec object we construct.
+ //
+class OptionSpec {
+public:
+ OptionSpec(const char * decl =NULLSTR)
+ : hidden(0), spec(decl)
+ {
+ if (spec == NULL) spec = NULL_spec;
+ CheckHidden();
+ }
+
+ OptionSpec(const OptionSpec & cp) : hidden(cp.hidden), spec(cp.spec) {}
+
+ // NOTE: use default destructor!
+
+ // Assign to another OptionSpec
+ OptionSpec &
+ operator=(const OptionSpec & cp) {
+ if (this != &cp) {
+ spec = cp.spec;
+ hidden = cp.hidden;
+ }
+ return *this;
+ }
+
+ // Assign to a string
+ OptionSpec &
+ operator=(const char * decl) {
+ if (spec != decl) {
+ spec = decl;
+ hidden = 0;
+ CheckHidden();
+ }
+ return *this;
+ }
+
+ // Convert to char-ptr by returning the original declaration-string
+ operator const char*() { return isHiddenOpt() ? (spec - 1) : spec; }
+
+ // Is this option NULL?
+ int
+ isNULL(void) const { return ((spec == NULL) || (spec == NULL_spec)); }
+
+ // Is this options incorrectly specified?
+ int
+ isSyntaxError(const char * name) const;
+
+ // See if this is a Hidden option
+ int
+ isHiddenOpt(void) const { return hidden; }
+
+ // Get the corresponding option-character
+ char
+ OptChar(void) const { return *spec; }
+
+ // Get the corresponding long-option string
+ const char *
+ LongOpt(void) const {
+ return (spec[1] && spec[2] && (! isspace(spec[2]))) ? (spec + 2) : NULLSTR;
+ }
+
+ // Does this option require an argument?
+ int
+ isValRequired(void) const {
+ return ((spec[1] == ':') || (spec[1] == '+'));
+ }
+
+ // Does this option take an optional argument?
+ int
+ isValOptional(void) const {
+ return ((spec[1] == '?') || (spec[1] == '*'));
+ }
+
+ // Does this option take no arguments?
+ int
+ isNoArg(void) const {
+ return ((spec[1] == '|') || (! spec[1]));
+ }
+
+ // Can this option take more than one argument?
+ int
+ isList(void) const {
+ return ((spec[1] == '+') || (spec[1] == '*'));
+ }
+
+ // Does this option take any arguments?
+ int
+ isValTaken(void) const {
+ return (isValRequired() || isValOptional()) ;
+ }
+
+ // Format this option in the given buffer
+ unsigned
+ Format(char * buf, unsigned optctrls) const;
+
+private:
+ void
+ CheckHidden(void) {
+ if ((! hidden) && (*spec == '-')) {
+ ++hidden;
+ ++spec;
+ }
+ }
+
+ unsigned hidden : 1; // hidden-flag
+ const char * spec; // string specification
+
+ static const char NULL_spec[];
+} ;
+
+const char OptionSpec::NULL_spec[] = "\0\0\0" ;
+
+int
+OptionSpec::isSyntaxError(const char * name) const {
+ int error = 0;
+ if ((! spec) || (! *spec)) {
+ cerr << name << ": empty option specifier." << endl;
+ cerr << "\tmust be at least 1 character long." << endl;
+ ++error;
+ } else if (spec[1] && (strchr("|?:*+", spec[1]) == NULL)) {
+ cerr << name << ": bad option specifier \"" << spec << "\"." << endl;
+ cerr << "\t2nd character must be in the set \"|?:*+\"." << endl;
+ ++error;
+ }
+ return error;
+}
+
+// ---------------------------------------------------------------------------
+// ^FUNCTION: OptionSpec::Format - format an option-spec for a usage message
+//
+// ^SYNOPSIS:
+// unsigned OptionSpec::Format(buf, optctrls) const
+//
+// ^PARAMETERS:
+// char * buf -- where to print the formatted option
+// unsigned optctrls -- option-parsing configuration flags
+//
+// ^DESCRIPTION:
+// Self-explanatory.
+//
+// ^REQUIREMENTS:
+// - buf must be large enough to hold the result
+//
+// ^SIDE-EFFECTS:
+// - writes to buf.
+//
+// ^RETURN-VALUE:
+// Number of characters written to buf.
+//
+// ^ALGORITHM:
+// Follow along in the source - it's not hard but it is tedious!
+// ^^-------------------------------------------------------------------------
+unsigned
+OptionSpec::Format(char * buf, unsigned optctrls) const {
+#ifdef NO_USAGE
+ return (*buf = '\0');
+#else
+ static char default_value[] = "<value>";
+ if (isHiddenOpt()) return (unsigned)(*buf = '\0');
+ char optchar = OptChar();
+ const char * longopt = LongOpt();
+ char * p = buf ;
+
+ const char * value = NULLSTR;
+ int longopt_len = 0;
+ int value_len = 0;
+
+ if (longopt) {
+ value = ::strchr(longopt, ' ');
+ longopt_len = (value) ? (value - longopt) : ::strlen(longopt);
+ } else {
+ value = ::strchr(spec + 1, ' ');
+ }
+ while (value && (*value == ' ')) ++value;
+ if (value && *value) {
+ value_len = ::strlen(value);
+ } else {
+ value = default_value;
+ value_len = sizeof(default_value) - 1;
+ }
+
+ if ((optctrls & Options::SHORT_ONLY) &&
+ ((! isNullOpt(optchar)) || (optctrls & Options::NOGUESSING))) {
+ longopt = NULLSTR;
+ }
+ if ((optctrls & Options::LONG_ONLY) &&
+ (longopt || (optctrls & Options::NOGUESSING))) {
+ optchar = '\0';
+ }
+ if (isNullOpt(optchar) && (longopt == NULL)) {
+ *buf = '\0';
+ return 0;
+ }
+
+ *(p++) = '[';
+
+ // print the single character option
+ if (! isNullOpt(optchar)) {
+ *(p++) = '-';
+ *(p++) = optchar;
+ }
+
+ if ((! isNullOpt(optchar)) && (longopt)) *(p++) = '|';
+
+ // print the long option
+ if (longopt) {
+ *(p++) = '-';
+ if (! (optctrls & (Options::LONG_ONLY | Options::SHORT_ONLY))) {
+ *(p++) = '-';
+ }
+ strncpy(p, longopt, longopt_len);
+ p += longopt_len;
+ }
+
+ // print any argument the option takes
+ if (isValTaken()) {
+ *(p++) = ' ' ;
+ if (isValOptional()) *(p++) = '[' ;
+ strcpy(p, value);
+ p += value_len;
+ if (isList()) {
+ strcpy(p, " ...");
+ p += 4;
+ }
+ if (isValOptional()) *(p++) = ']' ;
+ }
+
+ *(p++) = ']';
+ *p = '\0';
+
+ return (unsigned) strlen(buf);
+#endif /* USE_STDIO */
+}
+
+// ******************************************************************* Options
+
+#if (defined(MSWIN) || defined(OS2) || defined(MSDOS))
+# define DIR_SEP_CHAR '\\'
+#else
+# define DIR_SEP_CHAR '/'
+#endif
+
+Options::Options(const char * name, const char * const optv[])
+ : cmdname(name), optvec(optv), explicit_end(0), optctrls(DEFAULT),
+ nextchar(NULLSTR), listopt(NULLSTR)
+{
+ const char * basename = ::strrchr(cmdname, DIR_SEP_CHAR);
+ if (basename) cmdname = basename + 1;
+ check_syntax();
+}
+
+Options::~Options(void) {}
+
+ // Make sure each option-specifier has correct syntax.
+ //
+ // If there is even one invalid specifier, then exit ungracefully!
+ //
+void
+Options::check_syntax(void) const {
+ int errors = 0;
+ if ((optvec == NULL) || (! *optvec)) return;
+
+ for (const char * const * optv = optvec ; *optv ; optv++) {
+ OptionSpec optspec = *optv;
+ errors += optspec.isSyntaxError(cmdname);
+ }
+ if (errors) exit(127);
+}
+
+// ---------------------------------------------------------------------------
+// ^FUNCTION: Options::match_opt - match an option
+//
+// ^SYNOPSIS:
+// const char * match_opt(opt, int ignore_case) const
+//
+// ^PARAMETERS:
+// char opt -- the option-character to match
+// int ignore_case -- should we ignore character-case?
+//
+// ^DESCRIPTION:
+// See if "opt" is found in "optvec"
+//
+// ^REQUIREMENTS:
+// - optvec should be non-NULL and terminated by a NULL pointer.
+//
+// ^SIDE-EFFECTS:
+// None.
+//
+// ^RETURN-VALUE:
+// NULL if no match is found,
+// otherwise a pointer to the matching option-spec.
+//
+// ^ALGORITHM:
+// foreach option-spec
+// - see if "opt" is a match, if so return option-spec
+// end-for
+// ^^-------------------------------------------------------------------------
+const char *
+Options::match_opt(char opt, int ignore_case) const {
+ if ((optvec == NULL) || (! *optvec)) return NULLSTR;
+
+ for (const char * const * optv = optvec ; *optv ; optv++) {
+ OptionSpec optspec = *optv;
+ char optchar = optspec.OptChar();
+ if (isNullOpt(optchar)) continue;
+ if (opt == optchar) {
+ return optspec;
+ } else if (ignore_case && (TOLOWER(opt) == TOLOWER(optchar))) {
+ return optspec;
+ }
+ }
+
+ return NULLSTR; // not found
+}
+
+// ---------------------------------------------------------------------------
+// ^FUNCTION: Options::match_longopt - match a long-option
+//
+// ^SYNOPSIS:
+// const char * Options::match_longopt(opt, len, ambiguous)
+//
+// ^PARAMETERS:
+// char * opt -- the long-option to match
+// int len -- the number of character of "opt" to match
+// int & ambiguous -- set by this routine before returning.
+//
+// ^DESCRIPTION:
+// Try to match "opt" against some unique prefix of a long-option
+// (case insensitive).
+//
+// ^REQUIREMENTS:
+// - optvec should be non-NULL and terminated by a NULL pointer.
+//
+// ^SIDE-EFFECTS:
+// - *ambiguous is set to '1' if "opt" matches >1 long-option
+// (otherwise it is set to 0).
+//
+// ^RETURN-VALUE:
+// NULL if no match is found,
+// otherwise a pointer to the matching option-spec.
+//
+// ^ALGORITHM:
+// ambiguous is FALSE
+// foreach option-spec
+// if we have an EXACT-MATCH, return the option-spec
+// if we have a partial-match then
+// if we already had a previous partial match then
+// set ambiguous = TRUE and return NULL
+// else
+// remember this options spec and continue matching
+// end-if
+// end-if
+// end-for
+// if we had exactly 1 partial match return it, else return NULL
+// ^^-------------------------------------------------------------------------
+const char *
+Options::match_longopt(const char * opt, int len, int & ambiguous) const {
+ kwdmatch_t result;
+ const char * matched = NULLSTR ;
+
+ ambiguous = 0;
+ if ((optvec == NULL) || (! *optvec)) return NULLSTR;
+
+ for (const char * const * optv = optvec ; *optv ; optv++) {
+ OptionSpec optspec = *optv;
+ const char * longopt = optspec.LongOpt();
+ if (longopt == NULL) continue;
+ result = kwdmatch(longopt, opt, len);
+ if (result == EXACT_MATCH) {
+ return optspec;
+ } else if (result == PARTIAL_MATCH) {
+ if (matched) {
+ ++ambiguous;
+ return NULLSTR;
+ } else {
+ matched = optspec;
+ }
+ }
+ }//for
+
+ return matched;
+}
+
+// ---------------------------------------------------------------------------
+// ^FUNCTION: Options::parse_opt - parse an option
+//
+// ^SYNOPSIS:
+// int Options::parse_opt(iter, optarg)
+//
+// ^PARAMETERS:
+// OptIter & iter -- option iterator
+// const char * & optarg -- where to store any option-argument
+//
+// ^DESCRIPTION:
+// Parse the next option in iter (advancing as necessary).
+// Make sure we update the nextchar pointer along the way. Any option
+// we find should be returned and optarg should point to its argument.
+//
+// ^REQUIREMENTS:
+// - nextchar must point to the prospective option character
+//
+// ^SIDE-EFFECTS:
+// - iter is advanced when an argument completely parsed
+// - optarg is modified to point to any option argument
+// - if Options::QUIET is not set, error messages are printed on cerr
+//
+// ^RETURN-VALUE:
+// 'c' if the -c option was matched (optarg points to its argument)
+// BADCHAR if the option is invalid (optarg points to the bad
+// option-character).
+//
+// ^ALGORITHM:
+// It gets complicated -- follow the comments in the source.
+// ^^-------------------------------------------------------------------------
+int
+Options::parse_opt(OptIter & iter, const char * & optarg) {
+ listopt = NULLSTR; // reset the list pointer
+
+ if ((optvec == NULL) || (! *optvec)) return Options::ENDOPTS;
+
+ // Try to match a known option
+ OptionSpec optspec = match_opt(*(nextchar++), (optctrls & Options::ANYCASE));
+
+ // Check for an unknown option
+ if (optspec.isNULL()) {
+ // See if this was a long-option in disguise
+ if (! (optctrls & Options::NOGUESSING)) {
+ unsigned save_ctrls = optctrls;
+ const char * save_nextchar = nextchar;
+ nextchar -= 1;
+ optctrls |= (Options::QUIET | Options::NOGUESSING);
+ int optchar = parse_longopt(iter, optarg);
+ optctrls = save_ctrls;
+ if (optchar > 0) {
+ return optchar;
+ } else {
+ nextchar = save_nextchar;
+ }
+ }
+ if (! (optctrls & Options::QUIET)) {
+ cerr << cmdname << ": unknown option -"
+ << *(nextchar - 1) << "." << endl ;
+ }
+ optarg = (nextchar - 1); // record the bad option in optarg
+ return Options::BADCHAR;
+ }
+
+ // If no argument is taken, then leave now
+ if (optspec.isNoArg()) {
+ optarg = NULLSTR;
+ return optspec.OptChar();
+ }
+
+ // Check for argument in this arg
+ if (*nextchar) {
+ optarg = nextchar; // the argument is right here
+ nextchar = NULLSTR; // we've exhausted this arg
+ if (optspec.isList()) listopt = optspec ; // save the list-spec
+ return optspec.OptChar();
+ }
+
+ // Check for argument in next arg
+ const char * nextarg = iter.curr();
+ if ((nextarg != NULL) &&
+ (optspec.isValRequired() || (! isOption(optctrls, nextarg)))) {
+ optarg = nextarg; // the argument is here
+ iter.next(); // end of arg - advance
+ if (optspec.isList()) listopt = optspec ; // save the list-spec
+ return optspec.OptChar();
+ }
+
+ // No argument given - if its required, thats an error
+ optarg = NULLSTR;
+ if (optspec.isValRequired() && !(optctrls & Options::QUIET)) {
+ cerr << cmdname << ": argument required for -" << optspec.OptChar()
+ << " option." << endl ;
+ }
+ return optspec.OptChar();
+}
+
+// ---------------------------------------------------------------------------
+// ^FUNCTION: Options::parse_longopt - parse a long-option
+//
+// ^SYNOPSIS:
+// int Options::parse_longopt(iter, optarg)
+//
+// ^PARAMETERS:
+// OptIter & iter -- option iterator
+// const char * & optarg -- where to store any option-argument
+//
+// ^DESCRIPTION:
+// Parse the next long-option in iter (advancing as necessary).
+// Make sure we update the nextchar pointer along the way. Any option
+// we find should be returned and optarg should point to its argument.
+//
+// ^REQUIREMENTS:
+// - nextchar must point to the prospective option character
+//
+// ^SIDE-EFFECTS:
+// - iter is advanced when an argument completely parsed
+// - optarg is modified to point to any option argument
+// - if Options::QUIET is not set, error messages are printed on cerr
+//
+// ^RETURN-VALUE:
+// 'c' if the the long-option corresponding to the -c option was matched
+// (optarg points to its argument)
+// BADKWD if the option is invalid (optarg points to the bad long-option
+// name).
+//
+// ^ALGORITHM:
+// It gets complicated -- follow the comments in the source.
+// ^^-------------------------------------------------------------------------
+int
+Options::parse_longopt(OptIter & iter, const char * & optarg) {
+ int len = 0, ambiguous = 0;
+
+ listopt = NULLSTR ; // reset the list-spec
+
+ if ((optvec == NULL) || (! *optvec)) return Options::ENDOPTS;
+
+ // if a value is supplied in this argv element, get it now
+ const char * val = strpbrk(nextchar, ":=") ;
+ if (val) {
+ len = val - nextchar ;
+ ++val ;
+ }
+
+ // Try to match a known long-option
+ OptionSpec optspec = match_longopt(nextchar, len, ambiguous);
+
+ // Check for an unknown long-option
+ if (optspec.isNULL()) {
+ // See if this was a short-option in disguise
+ if ((! ambiguous) && (! (optctrls & Options::NOGUESSING))) {
+ unsigned save_ctrls = optctrls;
+ const char * save_nextchar = nextchar;
+ optctrls |= (Options::QUIET | Options::NOGUESSING);
+ int optchar = parse_opt(iter, optarg);
+ optctrls = save_ctrls;
+ if (optchar > 0) {
+ return optchar;
+ } else {
+ nextchar = save_nextchar;
+ }
+ }
+ if (! (optctrls & Options::QUIET)) {
+ cerr << cmdname << ": " << ((ambiguous) ? "ambiguous" : "unknown")
+ << " option "
+ << ((optctrls & Options::LONG_ONLY) ? "-" : "--")
+ << nextchar << "." << endl ;
+ }
+ optarg = nextchar; // record the bad option in optarg
+ nextchar = NULLSTR; // we've exhausted this argument
+ return (ambiguous) ? Options::AMBIGUOUS : Options::BADKWD;
+ }
+
+ // If no argument is taken, then leave now
+ if (optspec.isNoArg()) {
+ if ((val) && ! (optctrls & Options::QUIET)) {
+ cerr << cmdname << ": option "
+ << ((optctrls & Options::LONG_ONLY) ? "-" : "--")
+ << optspec.LongOpt() << " does NOT take an argument." << endl ;
+ }
+ optarg = val; // record the unexpected argument
+ nextchar = NULLSTR; // we've exhausted this argument
+ return optspec.OptChar();
+ }
+
+ // Check for argument in this arg
+ if (val) {
+ optarg = val; // the argument is right here
+ nextchar = NULLSTR; // we exhausted the rest of this arg
+ if (optspec.isList()) listopt = optspec ; // save the list-spec
+ return optspec.OptChar();
+ }
+
+ // Check for argument in next arg
+ const char * nextarg = iter.curr(); // find the next argument to parse
+ if ((nextarg != NULL) &&
+ (optspec.isValRequired() || (! isOption(optctrls, nextarg)))) {
+ optarg = nextarg; // the argument is right here
+ iter.next(); // end of arg - advance
+ nextchar = NULLSTR; // we exhausted the rest of this arg
+ if (optspec.isList()) listopt = optspec ; // save the list-spec
+ return optspec.OptChar();
+ }
+
+ // No argument given - if its required, thats an error
+ optarg = NULLSTR;
+ if (optspec.isValRequired() && !(optctrls & Options::QUIET)) {
+ const char * longopt = optspec.LongOpt();
+ const char * spc = ::strchr(longopt, ' ');
+ int longopt_len;
+ if (spc) {
+ longopt_len = spc - longopt;
+ } else {
+ longopt_len = ::strlen(longopt);
+ }
+ cerr << cmdname << ": argument required for "
+ << ((optctrls & Options::LONG_ONLY) ? "-" : "--");
+ cerr.write(longopt, longopt_len) << " option." << endl ;
+ }
+ nextchar = NULLSTR; // we exhausted the rest of this arg
+ return optspec.OptChar();
+}
+
+// ---------------------------------------------------------------------------
+// ^FUNCTION: Options::usage - print usage
+//
+// ^SYNOPSIS:
+// void Options::usage(os, positionals)
+//
+// ^PARAMETERS:
+// ostream & os -- where to print the usage
+// char * positionals -- command-line syntax for any positional args
+//
+// ^DESCRIPTION:
+// Print command-usage (using either option or long-option syntax) on os.
+//
+// ^REQUIREMENTS:
+// os should correspond to an open output file.
+//
+// ^SIDE-EFFECTS:
+// Prints on os
+//
+// ^RETURN-VALUE:
+// None.
+//
+// ^ALGORITHM:
+// Print usage on os, wrapping long lines where necessary.
+// ^^-------------------------------------------------------------------------
+void
+Options::usage(ostream & os, const char * positionals) const {
+#ifdef NO_USAGE
+ return;
+#else
+ const char * const * optv = optvec;
+ unsigned cols = 79;
+ int first, nloop;
+ char buf[256] ;
+
+ if ((optv == NULL) || (! *optv)) return;
+
+ // print first portion "usage: progname"
+ os << "usage: " << cmdname ;
+ unsigned ll = strlen(cmdname) + 7;
+
+ // save the current length so we know how much space to skip for
+ // subsequent lines.
+ //
+ unsigned margin = ll + 1;
+
+ // print the options and the positional arguments
+ for (nloop = 0, first = 1 ; !nloop ; optv++, first = 0) {
+ unsigned len;
+ OptionSpec optspec = *optv;
+
+ // figure out how wide this parameter is (for printing)
+ if (! *optv) {
+ len = strlen(positionals);
+ ++nloop; // terminate this loop
+ } else {
+ if (optspec.isHiddenOpt()) continue;
+ len = optspec.Format(buf, optctrls);
+ }
+
+ // Will this fit?
+ if ((ll + len + 1) > (cols - first)) {
+ os << '\n' ; // No - start a new line;
+#ifdef USE_STDIO
+ for (int _i_ = 0; _i_ < margin; ++_i_) os << " ";
+#else
+ os.width(margin); os << "" ;
+#endif
+ ll = margin;
+ } else {
+ os << ' ' ; // Yes - just throw in a space
+ ++ll;
+ }
+ ll += len;
+ os << ((nloop) ? positionals : buf) ;
+ }// for each ad
+
+ os << endl ;
+#endif /* NO_USAGE */
+}
+
+
+// ---------------------------------------------------------------------------
+// ^FUNCTION: Options::operator() - get options from the command-line
+//
+// ^SYNOPSIS:
+// int Options::operator()(iter, optarg)
+//
+// ^PARAMETERS:
+// OptIter & iter -- option iterator
+// const char * & optarg -- where to store any option-argument
+//
+// ^DESCRIPTION:
+// Parse the next option in iter (advancing as necessary).
+// Make sure we update the nextchar pointer along the way. Any option
+// we find should be returned and optarg should point to its argument.
+//
+// ^REQUIREMENTS:
+// None.
+//
+// ^SIDE-EFFECTS:
+// - iter is advanced when an argument is completely parsed
+// - optarg is modified to point to any option argument
+// - if Options::QUIET is not set, error messages are printed on cerr
+//
+// ^RETURN-VALUE:
+// 0 if all options have been parsed.
+// 'c' if the the option or long-option corresponding to the -c option was
+// matched (optarg points to its argument).
+// BADCHAR if the option is invalid (optarg points to the bad option char).
+// BADKWD if the option is invalid (optarg points to the bad long-opt name).
+// AMBIGUOUS if an ambiguous keyword name was given (optarg points to the
+// ambiguous keyword name).
+// POSITIONAL if PARSE_POS was set and the current argument is a positional
+// parameter (in which case optarg points to the positional argument).
+//
+// ^ALGORITHM:
+// It gets complicated -- follow the comments in the source.
+// ^^-------------------------------------------------------------------------
+int
+Options::operator()(OptIter & iter, const char * & optarg) {
+ int parse_opts_only = isOptsOnly(optctrls);
+ if (parse_opts_only) explicit_end = 0;
+
+ // See if we have an option left over from before ...
+ if ((nextchar) && *nextchar) {
+ return parse_opt(iter, optarg);
+ }
+
+ // Check for end-of-options ...
+ const char * arg = NULLSTR;
+ int get_next_arg = 0;
+ do {
+ arg = iter.curr();
+ get_next_arg = 0;
+ if (arg == NULL) {
+ listopt = NULLSTR;
+ return Options::ENDOPTS;
+ } else if ((! explicit_end) && isEndOpts(arg)) {
+ iter.next(); // advance past end-of-options arg
+ listopt = NULLSTR;
+ explicit_end = 1;
+ if (parse_opts_only) return Options::ENDOPTS;
+ get_next_arg = 1; // make sure we look at the next argument.
+ }
+ } while (get_next_arg);
+
+ // Do we have a positional arg?
+ if ( explicit_end || (! isOption(optctrls, arg)) ) {
+ if (parse_opts_only) {
+ return Options::ENDOPTS;
+ } else {
+ optarg = arg; // set optarg to the positional argument
+ iter.next(); // advance iterator to the next argument
+ return Options::POSITIONAL;
+ }
+ }
+
+ iter.next(); // pass the argument that arg already points to
+
+ // See if we have a long option ...
+ if (! (optctrls & Options::SHORT_ONLY)) {
+ if ((*arg == '-') && (arg[1] == '-')) {
+ nextchar = arg + 2;
+ return parse_longopt(iter, optarg);
+ } else if ((optctrls & Options::PLUS) && (*arg == '+')) {
+ nextchar = arg + 1;
+ return parse_longopt(iter, optarg);
+ }
+ }
+ if (*arg == '-') {
+ nextchar = arg + 1;
+ if (optctrls & Options::LONG_ONLY) {
+ return parse_longopt(iter, optarg);
+ } else {
+ return parse_opt(iter, optarg);
+ }
+ }
+
+ // If we get here - it is because we have a list value
+ OptionSpec optspec = listopt;
+ optarg = arg ; // record the list value
+ return optspec.OptChar() ;
+}
+
--- /dev/null
+// ****************************************************************************
+// ^FILE: options.h - option parsing classes
+//
+// ^DESCRIPTION:
+// This file defines classes used to parse command-line options.
+// Options may be parsed from an array of strings, or from any structure
+// for which a corresponding option-iterator exists.
+//
+// ^HISTORY:
+// 03/06/92 Brad Appleton <bradapp@enteract.com> Created
+//
+// 03/23/93 Brad Appleton <bradapp@enteract.com>
+// - Added OptIstreamIter class
+//
+// 03/08/94 Brad Appleton <bradapp@enteract.com>
+// - Added Options::reset() member function
+//
+// 07/31/97 Brad Appleton <bradapp@enteract.com>
+// - Added PARSE_POS control flag and POSITIONAL return value
+//
+// 04/30/06 Chris Reed
+// - Updated to modern C++ and STL
+// - Converted comments to doxygen style
+// ^^**************************************************************************
+
+#ifndef _options_h
+#define _options_h
+
+#ifdef USE_STDIO
+ #include <stdio.h>
+#else
+ #include <iostream>
+#endif
+
+
+//! Abstract class to iterate through options/arguments
+//!
+class OptIter {
+public:
+ OptIter(void) {}
+ virtual ~OptIter(void);
+
+ //! curr() returns the current item in the iterator without
+ //! advancing on to the next item. If we are at the end of items
+ //! then NULL is returned.
+ virtual const char *
+ curr(void) = 0;
+
+ //! next() advances to the next item.
+ virtual void
+ next(void) = 0;
+
+ //! operator() returns the current item in the iterator and then
+ //! advances on to the next item. If we are at the end of items
+ //! then NULL is returned.
+ virtual const char *
+ operator()(void);
+} ;
+
+//! Abstract class for a rewindable OptIter
+//!
+class OptIterRwd : public OptIter {
+public:
+ OptIterRwd(void);
+
+ virtual ~OptIterRwd(void);
+
+ virtual const char *
+ curr(void) = 0;
+
+ virtual void
+ next(void) = 0;
+
+ virtual const char *
+ operator()(void) = 0;
+
+ //! rewind() resets the "current-element" to the first one in the "list"
+ virtual void
+ rewind(void) = 0;
+} ;
+
+//! Class to iterate through an array of tokens. The array may be terminated
+//! by NULL or a count containing the number of tokens may be given.
+//!
+class OptArgvIter : public OptIterRwd {
+private:
+ int ndx; // index of current arg
+ int ac; // arg count
+ const char * const * av; // arg vector
+
+public:
+ OptArgvIter(const char * const argv[])
+ : av(argv), ac(-1), ndx(0) {}
+
+ OptArgvIter(int argc, const char * const argv[])
+ : av(argv), ac(argc), ndx(0) {}
+
+ virtual
+ ~OptArgvIter(void);
+
+ virtual const char *
+ curr(void);
+
+ virtual void
+ next(void);
+
+ virtual const char *
+ operator()(void);
+
+ virtual void
+ rewind(void);
+
+ //! index returns the current index to use for argv[]
+ int index(void) { return ndx; }
+} ;
+
+
+//! Class to iterate through a string containing delimiter-separated tokens
+//!
+class OptStrTokIter : public OptIterRwd {
+private:
+ unsigned len; // length of token-string
+ const char * str; // the token-string
+ const char * seps; // delimiter-set (separator-characters)
+ const char * cur; // current token
+ char * tokstr; // our copy of the token-string
+
+ static const char * default_delims; // default delimiters = whitespace
+
+public:
+ OptStrTokIter(const char * tokens, const char * delimiters =0);
+
+ virtual
+ ~OptStrTokIter(void);
+
+ virtual const char *
+ curr(void);
+
+ virtual void
+ next(void);
+
+ virtual const char *
+ operator()(void);
+
+ virtual void
+ rewind(void);
+
+ //! delimiters() with NO arguments returns the current set of delimiters,
+ //! If an argument is given then it is used as the new set of delimiters.
+ const char *
+ delimiters(void) { return seps; }
+
+ void
+ delimiters(const char * delims) {
+ seps = (delims) ? delims : default_delims ;
+ }
+} ;
+
+
+//! OptIstreamIter is a class for iterating over arguments that come
+//! from an input stream. Each line of the input stream is considered
+//! to be a set of white-space separated tokens. If the the first
+//! non-white character on a line is '#' ('!' for VMS systems) then
+//! the line is considered a comment and is ignored.
+//!
+//! \note If a line is more than 1022 characters in length then we
+//! treat it as if it were several lines of length 1022 or less.
+//!
+//! \note The string tokens returned by this iterator are pointers
+//! to temporary buffers which may not necessarily stick around
+//! for too long after the call to curr() or operator(), hence
+//! if you need the string value to persist - you will need to
+//! make a copy.
+//!
+class OptIstreamIter : public OptIter {
+private:
+ std::istream & is ;
+ OptStrTokIter * tok_iter ;
+
+ void
+ fill(void);
+
+public:
+ static const unsigned MAX_LINE_LEN ;
+
+ OptIstreamIter(std::istream & input);
+
+ virtual
+ ~OptIstreamIter(void);
+
+ virtual const char *
+ curr(void);
+
+ virtual void
+ next(void);
+
+ virtual const char *
+ operator()(void);
+} ;
+
+
+//! \brief parse command-line options
+//!
+//! \section Synopsis
+//! \code
+//! #include <options.h>
+//!
+//! Options opts(cmdname, optv);
+//! char cmdname[], *optv[];
+//! \endcode
+//! \section Description
+//! The Options constructor expects a command-name (usually argv[0]) and
+//! a pointer to an array of strings. The last element in this array MUST
+//! be NULL. Each non-NULL string in the array must have the following format:
+//!
+//! The 1st character must be the option-name ('c' for a -c option).
+//!
+//! The 2nd character must be one of '|', '?', ':', '*', or '+'.
+//! '|' -- indicates that the option takes NO argument;
+//! '?' -- indicates that the option takes an OPTIONAL argument;
+//! ':' -- indicates that the option takes a REQUIRED argument;
+//! '*' -- indicates that the option takes 0 or more arguments;
+//! '+' -- indicates that the option takes 1 or more arguments;
+//!
+//! The remainder of the string must be the long-option name.
+//!
+//! If desired, the long-option name may be followed by one or more
+//! spaces and then by the name of the option value. This name will
+//! be used when printing usage messages. If the option-value-name
+//! is not given then the string "<value>" will be used in usage
+//! messages.
+//!
+//! One may use a space to indicate that a particular option does not
+//! have a corresponding long-option. For example, "c: " (or "c:")
+//! means the -c option takes a value & has NO corresponding long-option.
+//!
+//! To specify a long-option that has no corresponding single-character
+//! option is a bit trickier: Options::operator() still needs an "option-
+//! character" to return when that option is matched. One may use a whitespace
+//! character or a non-printable character as the single-character option
+//! in such a case. (hence " |hello" would only match "--hello").
+//!
+//! \section Exceptions Exceptions to the above
+//! If the 1st character of the string is '-', then the rest of the
+//! string must correspond to the above format, and the option is
+//! considered to be a hidden-option. This means it will be parsed
+//! when actually matching options from the command-line, but will
+//! NOT show-up if a usage message is printed using the usage() member
+//! function. Such an example might be "-h|hidden". If you want to
+//! use any "dummy" options (options that are not parsed, but that
+//! to show up in the usage message), you can specify them along with
+//! any positional parameters to the usage() member function.
+//!
+//! If the 2nd character of the string is '\0' then it is assumed
+//! that there is no corresponding long-option and that the option
+//! takes no argument (hence "f", and "f| " are equivalent).
+//!
+//! \code
+//! const char * optv[] = {
+//! "c:count <number>",
+//! "s?str <string>",
+//! "x",
+//! " |hello",
+//! "g+groups <newsgroup>",
+//! NULL
+//! } ;
+//! \endcode
+//! optv[] now corresponds to the following:
+//!
+//! usage: cmdname [-c|--count <number>] [-s|--str [<string>]]
+//! [-x] [--hello] [-g|--groups <newsgroup> ...]
+//!
+//! Long-option names are matched case-insensitive and only a unique prefix
+//! of the name needs to be specified.
+//!
+//! Option-name characters are case-sensitive!
+//!
+//! \section Caveat
+//! Because of the way in which multi-valued options and options with optional
+//! values are handled, it is NOT possible to supply a value to an option in
+//! a separate argument (different argv[] element) if the value is OPTIONAL
+//! and begins with a '-'. What this means is that if an option "-s" takes an
+//! optional value value and you wish to supply a value of "-foo" then you must
+//! specify this on the command-line as "-s-foo" instead of "-s -foo" because
+//! "-s -foo" will be considered to be two separate sets of options.
+//!
+//! A multi-valued option is terminated by another option or by the end-of
+//! options. The following are all equivalent (if "-l" is a multi-valued
+//! option and "-x" is an option that takes no value):
+//!
+//! cmdname -x -l item1 item2 item3 -- arg1 arg2 arg3
+//! cmdname -x -litem1 -litem2 -litem3 -- arg1 arg2 arg3
+//! cmdname -l item1 item2 item3 -x arg1 arg2 arg3
+//!
+//!
+//! \code
+//! #include <options.h>
+//!
+//! static const char * optv[] = {
+//! "H|help",
+//! "c:count <number>",
+//! "s?str <string>",
+//! "x",
+//! " |hello",
+//! "g+groups <newsgroup>",
+//! NULL
+//! } ;
+//!
+//! main(int argc, char * argv[]) {
+//! int optchar;
+//! const char * optarg;
+//! const char * str = "default_string";
+//! int count = 0, xflag = 0, hello = 0;
+//! int errors = 0, ngroups = 0;
+//!
+//! Options opts(*argv, optv);
+//! OptArgvIter iter(--argc, ++argv);
+//!
+//! while( optchar = opts(iter, optarg) ) {
+//! switch (optchar) {
+//! case 'H' :
+//! opts.usage(cout, "files ...");
+//! exit(0);
+//! break;
+//! case 'g' :
+//! ++ngroups; break; //! the groupname is in "optarg"
+//! case 's' :
+//! str = optarg; break;
+//! case 'x' :
+//! ++xflag; break;
+//! case ' ' :
+//! ++hello; break;
+//! case 'c' :
+//! if (optarg == NULL) ++errors;
+//! else count = (int) atol(optarg);
+//! break;
+//! default : ++errors; break;
+//! } //!switch
+//! }
+//!
+//! if (errors || (iter.index() == argc)) {
+//! if (! errors) {
+//! cerr << opts.name() << ": no filenames given." << endl ;
+//! }
+//! opts.usage(cerr, "files ...");
+//! exit(1);
+//! }
+//!
+//! cout << "xflag=" << ((xflag) ? "ON" : "OFF") << endl
+//! << "hello=" << ((hello) ? "YES" : "NO") << endl
+//! << "count=" << count << endl
+//! << "str=\"" << ((str) ? str : "No value given!") << "\"" << endl
+//! << "ngroups=" << ngroups << endl ;
+//!
+//! if (iter.index() < argc) {
+//! cout << "files=" ;
+//! for (int i = iter.index() ; i < argc ; i++) {
+//! cout << "\"" << argv[i] << "\" " ;
+//! }
+//! cout << endl ;
+//! }
+//! }
+//! \endcode
+class Options {
+private:
+ unsigned explicit_end : 1; //!< were we terminated because of "--"?
+ unsigned optctrls : 7; //!< control settings (a set of OptCtrl masks)
+ const char * const * optvec; //!< vector of option-specifications (last=NULL)
+ const char * nextchar; //!< next option-character to process
+ const char * listopt; //!< last list-option we matched
+ const char * cmdname; //!< name of the command
+
+ void
+ check_syntax(void) const;
+
+ const char *
+ match_opt(char opt, int ignore_case =0) const;
+
+ const char *
+ match_longopt(const char * opt, int len, int & ambiguous) const;
+
+ int
+ parse_opt(OptIter & iter, const char * & optarg);
+
+ int
+ parse_longopt(OptIter & iter, const char * & optarg);
+
+public:
+ enum OptCtrl {
+ DEFAULT = 0x00, //!< Default setting
+ ANYCASE = 0x01, //!< Ignore case when matching short-options
+ QUIET = 0x02, //!< Dont print error messages
+ PLUS = 0x04, //!< Allow "+" as a long-option prefix
+ SHORT_ONLY = 0x08, //!< Dont accept long-options
+ LONG_ONLY = 0x10, //!< Dont accept short-options
+ //!< (also allows "-" as a long-option prefix).
+ NOGUESSING = 0x20, //!< Normally, when we see a short (long) option
+ //!< on the command line that doesnt match any
+ //!< known short (long) options, then we try to
+ //!< "guess" by seeing if it will match any known
+ //!< long (short) option. Setting this mask prevents
+ //!< this "guessing" from occurring.
+ PARSE_POS = 0x40 //!< By default, Options will not present positional
+ //!< command-line arguments to the user and will
+ //!< instead stop parsing when the first positonal
+ //!< argument has been encountered. If this flag
+ //!< is given, Options will present positional
+ //!< arguments to the user with a return code of
+ //!< POSITIONAL; ENDOPTS will be returned only
+ //!< when the end of the argument list is reached.
+ } ;
+
+ //! Error return values for operator()
+ //!
+ enum OptRC {
+ ENDOPTS = 0,
+ BADCHAR = -1,
+ BADKWD = -2,
+ AMBIGUOUS = -3,
+ POSITIONAL = -4
+ } ;
+
+ Options(const char * name, const char * const optv[]);
+
+ virtual
+ ~Options(void);
+
+ //! name() returns the command name
+ const char *
+ name(void) const { return cmdname; }
+
+ //! ctrls() (with no arguments) returns the existing control settings
+ unsigned
+ ctrls(void) const { return optctrls; }
+
+ //! ctrls() (with 1 argument) sets new control settings
+ void
+ ctrls(unsigned newctrls) { optctrls = newctrls; }
+
+ //! reset for another pass to parse for options
+ void
+ reset(void) { nextchar = listopt = NULL; }
+
+ //! usage() prints options usage (followed by any positional arguments
+ //! listed in the parameter "positionals") on the given outstream
+ void
+ usage(std::ostream & os, const char * positionals) const ;
+
+ //! operator() iterates through the arguments as necessary (using the
+ //! given iterator) and returns the character value of the option
+ //! (or long-option) that it matched. If the option has a value
+ //! then the value given may be found in optarg (otherwise optarg
+ //! will be NULL).
+ //!
+ //! 0 is returned upon end-of-options. At this point, "iter" may
+ //! be used to process any remaining positional parameters. If the
+ //! PARSE_POS control-flag is set then 0 is returned only when all
+ //! arguments in "iter" have been exhausted.
+ //!
+ //! If an invalid option is found then BADCHAR is returned and *optarg
+ //! is the unrecognized option character.
+ //!
+ //! If an invalid long-option is found then BADKWD is returned and optarg
+ //! points to the bad long-option.
+ //!
+ //! If an ambiguous long-option is found then AMBIGUOUS is returned and
+ //! optarg points to the ambiguous long-option.
+ //!
+ //! If the PARSE_POS control-flag is set then POSITIONAL is returned
+ //! when a positional argument is encountered and optarg points to
+ //! the positonal argument (and "iter" is advanced to the next argument
+ //! in the iterator).
+ //!
+ //! Unless Options::QUIET is used, missing option-arguments and
+ //! invalid options (and the like) will automatically cause error
+ //! messages to be issued to cerr.
+ int
+ operator()(OptIter & iter, const char * & optarg) ;
+
+ //! Call this member function after operator() has returned 0
+ //! if you want to know whether or not options were explicitly
+ //! terminated because "--" appeared on the command-line.
+ //!
+ int
+ explicit_endopts() const { return explicit_end; }
+} ;
+
+#endif /* _options_h */
--- /dev/null
+//
+// File : rijndael.cpp
+// Creation date : Sun Nov 5 2000 03:22:10 CEST
+// Author : Szymon Stefanek (stefanek@tin.it)
+//
+// Another implementation of the Rijndael cipher.
+// This is intended to be an easily usable library file.
+// This code is public domain.
+// Based on the Vincent Rijmen and K.U.Leuven implementation 2.4.
+//
+
+//
+// Original Copyright notice:
+//
+// rijndael-alg-fst.c v2.4 April '2000
+// rijndael-alg-fst.h
+// rijndael-api-fst.c
+// rijndael-api-fst.h
+//
+// Optimised ANSI C code
+//
+// authors: v1.0: Antoon Bosselaers
+// v2.0: Vincent Rijmen, K.U.Leuven
+// v2.3: Paulo Barreto
+// v2.4: Vincent Rijmen, K.U.Leuven
+//
+// This code is placed in the public domain.
+//
+
+//
+// This implementation works on 128 , 192 , 256 bit keys
+// and on 128 bit blocks
+//
+
+#define _RIJNDAEL_CPP_
+
+#include "rijndael.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+
+static uint8_t S[256]=
+{
+ 99, 124, 119, 123, 242, 107, 111, 197, 48, 1, 103, 43, 254, 215, 171, 118,
+ 202, 130, 201, 125, 250, 89, 71, 240, 173, 212, 162, 175, 156, 164, 114, 192,
+ 183, 253, 147, 38, 54, 63, 247, 204, 52, 165, 229, 241, 113, 216, 49, 21,
+ 4, 199, 35, 195, 24, 150, 5, 154, 7, 18, 128, 226, 235, 39, 178, 117,
+ 9, 131, 44, 26, 27, 110, 90, 160, 82, 59, 214, 179, 41, 227, 47, 132,
+ 83, 209, 0, 237, 32, 252, 177, 91, 106, 203, 190, 57, 74, 76, 88, 207,
+ 208, 239, 170, 251, 67, 77, 51, 133, 69, 249, 2, 127, 80, 60, 159, 168,
+ 81, 163, 64, 143, 146, 157, 56, 245, 188, 182, 218, 33, 16, 255, 243, 210,
+ 205, 12, 19, 236, 95, 151, 68, 23, 196, 167, 126, 61, 100, 93, 25, 115,
+ 96, 129, 79, 220, 34, 42, 144, 136, 70, 238, 184, 20, 222, 94, 11, 219,
+ 224, 50, 58, 10, 73, 6, 36, 92, 194, 211, 172, 98, 145, 149, 228, 121,
+ 231, 200, 55, 109, 141, 213, 78, 169, 108, 86, 244, 234, 101, 122, 174, 8,
+ 186, 120, 37, 46, 28, 166, 180, 198, 232, 221, 116, 31, 75, 189, 139, 138,
+ 112, 62, 181, 102, 72, 3, 246, 14, 97, 53, 87, 185, 134, 193, 29, 158,
+ 225, 248, 152, 17, 105, 217, 142, 148, 155, 30, 135, 233, 206, 85, 40, 223,
+ 140, 161, 137, 13, 191, 230, 66, 104, 65, 153, 45, 15, 176, 84, 187, 22
+};
+
+
+static uint8_t T1[256][4]=
+{
+ 0xc6,0x63,0x63,0xa5, 0xf8,0x7c,0x7c,0x84, 0xee,0x77,0x77,0x99, 0xf6,0x7b,0x7b,0x8d,
+ 0xff,0xf2,0xf2,0x0d, 0xd6,0x6b,0x6b,0xbd, 0xde,0x6f,0x6f,0xb1, 0x91,0xc5,0xc5,0x54,
+ 0x60,0x30,0x30,0x50, 0x02,0x01,0x01,0x03, 0xce,0x67,0x67,0xa9, 0x56,0x2b,0x2b,0x7d,
+ 0xe7,0xfe,0xfe,0x19, 0xb5,0xd7,0xd7,0x62, 0x4d,0xab,0xab,0xe6, 0xec,0x76,0x76,0x9a,
+ 0x8f,0xca,0xca,0x45, 0x1f,0x82,0x82,0x9d, 0x89,0xc9,0xc9,0x40, 0xfa,0x7d,0x7d,0x87,
+ 0xef,0xfa,0xfa,0x15, 0xb2,0x59,0x59,0xeb, 0x8e,0x47,0x47,0xc9, 0xfb,0xf0,0xf0,0x0b,
+ 0x41,0xad,0xad,0xec, 0xb3,0xd4,0xd4,0x67, 0x5f,0xa2,0xa2,0xfd, 0x45,0xaf,0xaf,0xea,
+ 0x23,0x9c,0x9c,0xbf, 0x53,0xa4,0xa4,0xf7, 0xe4,0x72,0x72,0x96, 0x9b,0xc0,0xc0,0x5b,
+ 0x75,0xb7,0xb7,0xc2, 0xe1,0xfd,0xfd,0x1c, 0x3d,0x93,0x93,0xae, 0x4c,0x26,0x26,0x6a,
+ 0x6c,0x36,0x36,0x5a, 0x7e,0x3f,0x3f,0x41, 0xf5,0xf7,0xf7,0x02, 0x83,0xcc,0xcc,0x4f,
+ 0x68,0x34,0x34,0x5c, 0x51,0xa5,0xa5,0xf4, 0xd1,0xe5,0xe5,0x34, 0xf9,0xf1,0xf1,0x08,
+ 0xe2,0x71,0x71,0x93, 0xab,0xd8,0xd8,0x73, 0x62,0x31,0x31,0x53, 0x2a,0x15,0x15,0x3f,
+ 0x08,0x04,0x04,0x0c, 0x95,0xc7,0xc7,0x52, 0x46,0x23,0x23,0x65, 0x9d,0xc3,0xc3,0x5e,
+ 0x30,0x18,0x18,0x28, 0x37,0x96,0x96,0xa1, 0x0a,0x05,0x05,0x0f, 0x2f,0x9a,0x9a,0xb5,
+ 0x0e,0x07,0x07,0x09, 0x24,0x12,0x12,0x36, 0x1b,0x80,0x80,0x9b, 0xdf,0xe2,0xe2,0x3d,
+ 0xcd,0xeb,0xeb,0x26, 0x4e,0x27,0x27,0x69, 0x7f,0xb2,0xb2,0xcd, 0xea,0x75,0x75,0x9f,
+ 0x12,0x09,0x09,0x1b, 0x1d,0x83,0x83,0x9e, 0x58,0x2c,0x2c,0x74, 0x34,0x1a,0x1a,0x2e,
+ 0x36,0x1b,0x1b,0x2d, 0xdc,0x6e,0x6e,0xb2, 0xb4,0x5a,0x5a,0xee, 0x5b,0xa0,0xa0,0xfb,
+ 0xa4,0x52,0x52,0xf6, 0x76,0x3b,0x3b,0x4d, 0xb7,0xd6,0xd6,0x61, 0x7d,0xb3,0xb3,0xce,
+ 0x52,0x29,0x29,0x7b, 0xdd,0xe3,0xe3,0x3e, 0x5e,0x2f,0x2f,0x71, 0x13,0x84,0x84,0x97,
+ 0xa6,0x53,0x53,0xf5, 0xb9,0xd1,0xd1,0x68, 0x00,0x00,0x00,0x00, 0xc1,0xed,0xed,0x2c,
+ 0x40,0x20,0x20,0x60, 0xe3,0xfc,0xfc,0x1f, 0x79,0xb1,0xb1,0xc8, 0xb6,0x5b,0x5b,0xed,
+ 0xd4,0x6a,0x6a,0xbe, 0x8d,0xcb,0xcb,0x46, 0x67,0xbe,0xbe,0xd9, 0x72,0x39,0x39,0x4b,
+ 0x94,0x4a,0x4a,0xde, 0x98,0x4c,0x4c,0xd4, 0xb0,0x58,0x58,0xe8, 0x85,0xcf,0xcf,0x4a,
+ 0xbb,0xd0,0xd0,0x6b, 0xc5,0xef,0xef,0x2a, 0x4f,0xaa,0xaa,0xe5, 0xed,0xfb,0xfb,0x16,
+ 0x86,0x43,0x43,0xc5, 0x9a,0x4d,0x4d,0xd7, 0x66,0x33,0x33,0x55, 0x11,0x85,0x85,0x94,
+ 0x8a,0x45,0x45,0xcf, 0xe9,0xf9,0xf9,0x10, 0x04,0x02,0x02,0x06, 0xfe,0x7f,0x7f,0x81,
+ 0xa0,0x50,0x50,0xf0, 0x78,0x3c,0x3c,0x44, 0x25,0x9f,0x9f,0xba, 0x4b,0xa8,0xa8,0xe3,
+ 0xa2,0x51,0x51,0xf3, 0x5d,0xa3,0xa3,0xfe, 0x80,0x40,0x40,0xc0, 0x05,0x8f,0x8f,0x8a,
+ 0x3f,0x92,0x92,0xad, 0x21,0x9d,0x9d,0xbc, 0x70,0x38,0x38,0x48, 0xf1,0xf5,0xf5,0x04,
+ 0x63,0xbc,0xbc,0xdf, 0x77,0xb6,0xb6,0xc1, 0xaf,0xda,0xda,0x75, 0x42,0x21,0x21,0x63,
+ 0x20,0x10,0x10,0x30, 0xe5,0xff,0xff,0x1a, 0xfd,0xf3,0xf3,0x0e, 0xbf,0xd2,0xd2,0x6d,
+ 0x81,0xcd,0xcd,0x4c, 0x18,0x0c,0x0c,0x14, 0x26,0x13,0x13,0x35, 0xc3,0xec,0xec,0x2f,
+ 0xbe,0x5f,0x5f,0xe1, 0x35,0x97,0x97,0xa2, 0x88,0x44,0x44,0xcc, 0x2e,0x17,0x17,0x39,
+ 0x93,0xc4,0xc4,0x57, 0x55,0xa7,0xa7,0xf2, 0xfc,0x7e,0x7e,0x82, 0x7a,0x3d,0x3d,0x47,
+ 0xc8,0x64,0x64,0xac, 0xba,0x5d,0x5d,0xe7, 0x32,0x19,0x19,0x2b, 0xe6,0x73,0x73,0x95,
+ 0xc0,0x60,0x60,0xa0, 0x19,0x81,0x81,0x98, 0x9e,0x4f,0x4f,0xd1, 0xa3,0xdc,0xdc,0x7f,
+ 0x44,0x22,0x22,0x66, 0x54,0x2a,0x2a,0x7e, 0x3b,0x90,0x90,0xab, 0x0b,0x88,0x88,0x83,
+ 0x8c,0x46,0x46,0xca, 0xc7,0xee,0xee,0x29, 0x6b,0xb8,0xb8,0xd3, 0x28,0x14,0x14,0x3c,
+ 0xa7,0xde,0xde,0x79, 0xbc,0x5e,0x5e,0xe2, 0x16,0x0b,0x0b,0x1d, 0xad,0xdb,0xdb,0x76,
+ 0xdb,0xe0,0xe0,0x3b, 0x64,0x32,0x32,0x56, 0x74,0x3a,0x3a,0x4e, 0x14,0x0a,0x0a,0x1e,
+ 0x92,0x49,0x49,0xdb, 0x0c,0x06,0x06,0x0a, 0x48,0x24,0x24,0x6c, 0xb8,0x5c,0x5c,0xe4,
+ 0x9f,0xc2,0xc2,0x5d, 0xbd,0xd3,0xd3,0x6e, 0x43,0xac,0xac,0xef, 0xc4,0x62,0x62,0xa6,
+ 0x39,0x91,0x91,0xa8, 0x31,0x95,0x95,0xa4, 0xd3,0xe4,0xe4,0x37, 0xf2,0x79,0x79,0x8b,
+ 0xd5,0xe7,0xe7,0x32, 0x8b,0xc8,0xc8,0x43, 0x6e,0x37,0x37,0x59, 0xda,0x6d,0x6d,0xb7,
+ 0x01,0x8d,0x8d,0x8c, 0xb1,0xd5,0xd5,0x64, 0x9c,0x4e,0x4e,0xd2, 0x49,0xa9,0xa9,0xe0,
+ 0xd8,0x6c,0x6c,0xb4, 0xac,0x56,0x56,0xfa, 0xf3,0xf4,0xf4,0x07, 0xcf,0xea,0xea,0x25,
+ 0xca,0x65,0x65,0xaf, 0xf4,0x7a,0x7a,0x8e, 0x47,0xae,0xae,0xe9, 0x10,0x08,0x08,0x18,
+ 0x6f,0xba,0xba,0xd5, 0xf0,0x78,0x78,0x88, 0x4a,0x25,0x25,0x6f, 0x5c,0x2e,0x2e,0x72,
+ 0x38,0x1c,0x1c,0x24, 0x57,0xa6,0xa6,0xf1, 0x73,0xb4,0xb4,0xc7, 0x97,0xc6,0xc6,0x51,
+ 0xcb,0xe8,0xe8,0x23, 0xa1,0xdd,0xdd,0x7c, 0xe8,0x74,0x74,0x9c, 0x3e,0x1f,0x1f,0x21,
+ 0x96,0x4b,0x4b,0xdd, 0x61,0xbd,0xbd,0xdc, 0x0d,0x8b,0x8b,0x86, 0x0f,0x8a,0x8a,0x85,
+ 0xe0,0x70,0x70,0x90, 0x7c,0x3e,0x3e,0x42, 0x71,0xb5,0xb5,0xc4, 0xcc,0x66,0x66,0xaa,
+ 0x90,0x48,0x48,0xd8, 0x06,0x03,0x03,0x05, 0xf7,0xf6,0xf6,0x01, 0x1c,0x0e,0x0e,0x12,
+ 0xc2,0x61,0x61,0xa3, 0x6a,0x35,0x35,0x5f, 0xae,0x57,0x57,0xf9, 0x69,0xb9,0xb9,0xd0,
+ 0x17,0x86,0x86,0x91, 0x99,0xc1,0xc1,0x58, 0x3a,0x1d,0x1d,0x27, 0x27,0x9e,0x9e,0xb9,
+ 0xd9,0xe1,0xe1,0x38, 0xeb,0xf8,0xf8,0x13, 0x2b,0x98,0x98,0xb3, 0x22,0x11,0x11,0x33,
+ 0xd2,0x69,0x69,0xbb, 0xa9,0xd9,0xd9,0x70, 0x07,0x8e,0x8e,0x89, 0x33,0x94,0x94,0xa7,
+ 0x2d,0x9b,0x9b,0xb6, 0x3c,0x1e,0x1e,0x22, 0x15,0x87,0x87,0x92, 0xc9,0xe9,0xe9,0x20,
+ 0x87,0xce,0xce,0x49, 0xaa,0x55,0x55,0xff, 0x50,0x28,0x28,0x78, 0xa5,0xdf,0xdf,0x7a,
+ 0x03,0x8c,0x8c,0x8f, 0x59,0xa1,0xa1,0xf8, 0x09,0x89,0x89,0x80, 0x1a,0x0d,0x0d,0x17,
+ 0x65,0xbf,0xbf,0xda, 0xd7,0xe6,0xe6,0x31, 0x84,0x42,0x42,0xc6, 0xd0,0x68,0x68,0xb8,
+ 0x82,0x41,0x41,0xc3, 0x29,0x99,0x99,0xb0, 0x5a,0x2d,0x2d,0x77, 0x1e,0x0f,0x0f,0x11,
+ 0x7b,0xb0,0xb0,0xcb, 0xa8,0x54,0x54,0xfc, 0x6d,0xbb,0xbb,0xd6, 0x2c,0x16,0x16,0x3a
+};
+
+static uint8_t T2[256][4]=
+{
+ 0xa5,0xc6,0x63,0x63, 0x84,0xf8,0x7c,0x7c, 0x99,0xee,0x77,0x77, 0x8d,0xf6,0x7b,0x7b,
+ 0x0d,0xff,0xf2,0xf2, 0xbd,0xd6,0x6b,0x6b, 0xb1,0xde,0x6f,0x6f, 0x54,0x91,0xc5,0xc5,
+ 0x50,0x60,0x30,0x30, 0x03,0x02,0x01,0x01, 0xa9,0xce,0x67,0x67, 0x7d,0x56,0x2b,0x2b,
+ 0x19,0xe7,0xfe,0xfe, 0x62,0xb5,0xd7,0xd7, 0xe6,0x4d,0xab,0xab, 0x9a,0xec,0x76,0x76,
+ 0x45,0x8f,0xca,0xca, 0x9d,0x1f,0x82,0x82, 0x40,0x89,0xc9,0xc9, 0x87,0xfa,0x7d,0x7d,
+ 0x15,0xef,0xfa,0xfa, 0xeb,0xb2,0x59,0x59, 0xc9,0x8e,0x47,0x47, 0x0b,0xfb,0xf0,0xf0,
+ 0xec,0x41,0xad,0xad, 0x67,0xb3,0xd4,0xd4, 0xfd,0x5f,0xa2,0xa2, 0xea,0x45,0xaf,0xaf,
+ 0xbf,0x23,0x9c,0x9c, 0xf7,0x53,0xa4,0xa4, 0x96,0xe4,0x72,0x72, 0x5b,0x9b,0xc0,0xc0,
+ 0xc2,0x75,0xb7,0xb7, 0x1c,0xe1,0xfd,0xfd, 0xae,0x3d,0x93,0x93, 0x6a,0x4c,0x26,0x26,
+ 0x5a,0x6c,0x36,0x36, 0x41,0x7e,0x3f,0x3f, 0x02,0xf5,0xf7,0xf7, 0x4f,0x83,0xcc,0xcc,
+ 0x5c,0x68,0x34,0x34, 0xf4,0x51,0xa5,0xa5, 0x34,0xd1,0xe5,0xe5, 0x08,0xf9,0xf1,0xf1,
+ 0x93,0xe2,0x71,0x71, 0x73,0xab,0xd8,0xd8, 0x53,0x62,0x31,0x31, 0x3f,0x2a,0x15,0x15,
+ 0x0c,0x08,0x04,0x04, 0x52,0x95,0xc7,0xc7, 0x65,0x46,0x23,0x23, 0x5e,0x9d,0xc3,0xc3,
+ 0x28,0x30,0x18,0x18, 0xa1,0x37,0x96,0x96, 0x0f,0x0a,0x05,0x05, 0xb5,0x2f,0x9a,0x9a,
+ 0x09,0x0e,0x07,0x07, 0x36,0x24,0x12,0x12, 0x9b,0x1b,0x80,0x80, 0x3d,0xdf,0xe2,0xe2,
+ 0x26,0xcd,0xeb,0xeb, 0x69,0x4e,0x27,0x27, 0xcd,0x7f,0xb2,0xb2, 0x9f,0xea,0x75,0x75,
+ 0x1b,0x12,0x09,0x09, 0x9e,0x1d,0x83,0x83, 0x74,0x58,0x2c,0x2c, 0x2e,0x34,0x1a,0x1a,
+ 0x2d,0x36,0x1b,0x1b, 0xb2,0xdc,0x6e,0x6e, 0xee,0xb4,0x5a,0x5a, 0xfb,0x5b,0xa0,0xa0,
+ 0xf6,0xa4,0x52,0x52, 0x4d,0x76,0x3b,0x3b, 0x61,0xb7,0xd6,0xd6, 0xce,0x7d,0xb3,0xb3,
+ 0x7b,0x52,0x29,0x29, 0x3e,0xdd,0xe3,0xe3, 0x71,0x5e,0x2f,0x2f, 0x97,0x13,0x84,0x84,
+ 0xf5,0xa6,0x53,0x53, 0x68,0xb9,0xd1,0xd1, 0x00,0x00,0x00,0x00, 0x2c,0xc1,0xed,0xed,
+ 0x60,0x40,0x20,0x20, 0x1f,0xe3,0xfc,0xfc, 0xc8,0x79,0xb1,0xb1, 0xed,0xb6,0x5b,0x5b,
+ 0xbe,0xd4,0x6a,0x6a, 0x46,0x8d,0xcb,0xcb, 0xd9,0x67,0xbe,0xbe, 0x4b,0x72,0x39,0x39,
+ 0xde,0x94,0x4a,0x4a, 0xd4,0x98,0x4c,0x4c, 0xe8,0xb0,0x58,0x58, 0x4a,0x85,0xcf,0xcf,
+ 0x6b,0xbb,0xd0,0xd0, 0x2a,0xc5,0xef,0xef, 0xe5,0x4f,0xaa,0xaa, 0x16,0xed,0xfb,0xfb,
+ 0xc5,0x86,0x43,0x43, 0xd7,0x9a,0x4d,0x4d, 0x55,0x66,0x33,0x33, 0x94,0x11,0x85,0x85,
+ 0xcf,0x8a,0x45,0x45, 0x10,0xe9,0xf9,0xf9, 0x06,0x04,0x02,0x02, 0x81,0xfe,0x7f,0x7f,
+ 0xf0,0xa0,0x50,0x50, 0x44,0x78,0x3c,0x3c, 0xba,0x25,0x9f,0x9f, 0xe3,0x4b,0xa8,0xa8,
+ 0xf3,0xa2,0x51,0x51, 0xfe,0x5d,0xa3,0xa3, 0xc0,0x80,0x40,0x40, 0x8a,0x05,0x8f,0x8f,
+ 0xad,0x3f,0x92,0x92, 0xbc,0x21,0x9d,0x9d, 0x48,0x70,0x38,0x38, 0x04,0xf1,0xf5,0xf5,
+ 0xdf,0x63,0xbc,0xbc, 0xc1,0x77,0xb6,0xb6, 0x75,0xaf,0xda,0xda, 0x63,0x42,0x21,0x21,
+ 0x30,0x20,0x10,0x10, 0x1a,0xe5,0xff,0xff, 0x0e,0xfd,0xf3,0xf3, 0x6d,0xbf,0xd2,0xd2,
+ 0x4c,0x81,0xcd,0xcd, 0x14,0x18,0x0c,0x0c, 0x35,0x26,0x13,0x13, 0x2f,0xc3,0xec,0xec,
+ 0xe1,0xbe,0x5f,0x5f, 0xa2,0x35,0x97,0x97, 0xcc,0x88,0x44,0x44, 0x39,0x2e,0x17,0x17,
+ 0x57,0x93,0xc4,0xc4, 0xf2,0x55,0xa7,0xa7, 0x82,0xfc,0x7e,0x7e, 0x47,0x7a,0x3d,0x3d,
+ 0xac,0xc8,0x64,0x64, 0xe7,0xba,0x5d,0x5d, 0x2b,0x32,0x19,0x19, 0x95,0xe6,0x73,0x73,
+ 0xa0,0xc0,0x60,0x60, 0x98,0x19,0x81,0x81, 0xd1,0x9e,0x4f,0x4f, 0x7f,0xa3,0xdc,0xdc,
+ 0x66,0x44,0x22,0x22, 0x7e,0x54,0x2a,0x2a, 0xab,0x3b,0x90,0x90, 0x83,0x0b,0x88,0x88,
+ 0xca,0x8c,0x46,0x46, 0x29,0xc7,0xee,0xee, 0xd3,0x6b,0xb8,0xb8, 0x3c,0x28,0x14,0x14,
+ 0x79,0xa7,0xde,0xde, 0xe2,0xbc,0x5e,0x5e, 0x1d,0x16,0x0b,0x0b, 0x76,0xad,0xdb,0xdb,
+ 0x3b,0xdb,0xe0,0xe0, 0x56,0x64,0x32,0x32, 0x4e,0x74,0x3a,0x3a, 0x1e,0x14,0x0a,0x0a,
+ 0xdb,0x92,0x49,0x49, 0x0a,0x0c,0x06,0x06, 0x6c,0x48,0x24,0x24, 0xe4,0xb8,0x5c,0x5c,
+ 0x5d,0x9f,0xc2,0xc2, 0x6e,0xbd,0xd3,0xd3, 0xef,0x43,0xac,0xac, 0xa6,0xc4,0x62,0x62,
+ 0xa8,0x39,0x91,0x91, 0xa4,0x31,0x95,0x95, 0x37,0xd3,0xe4,0xe4, 0x8b,0xf2,0x79,0x79,
+ 0x32,0xd5,0xe7,0xe7, 0x43,0x8b,0xc8,0xc8, 0x59,0x6e,0x37,0x37, 0xb7,0xda,0x6d,0x6d,
+ 0x8c,0x01,0x8d,0x8d, 0x64,0xb1,0xd5,0xd5, 0xd2,0x9c,0x4e,0x4e, 0xe0,0x49,0xa9,0xa9,
+ 0xb4,0xd8,0x6c,0x6c, 0xfa,0xac,0x56,0x56, 0x07,0xf3,0xf4,0xf4, 0x25,0xcf,0xea,0xea,
+ 0xaf,0xca,0x65,0x65, 0x8e,0xf4,0x7a,0x7a, 0xe9,0x47,0xae,0xae, 0x18,0x10,0x08,0x08,
+ 0xd5,0x6f,0xba,0xba, 0x88,0xf0,0x78,0x78, 0x6f,0x4a,0x25,0x25, 0x72,0x5c,0x2e,0x2e,
+ 0x24,0x38,0x1c,0x1c, 0xf1,0x57,0xa6,0xa6, 0xc7,0x73,0xb4,0xb4, 0x51,0x97,0xc6,0xc6,
+ 0x23,0xcb,0xe8,0xe8, 0x7c,0xa1,0xdd,0xdd, 0x9c,0xe8,0x74,0x74, 0x21,0x3e,0x1f,0x1f,
+ 0xdd,0x96,0x4b,0x4b, 0xdc,0x61,0xbd,0xbd, 0x86,0x0d,0x8b,0x8b, 0x85,0x0f,0x8a,0x8a,
+ 0x90,0xe0,0x70,0x70, 0x42,0x7c,0x3e,0x3e, 0xc4,0x71,0xb5,0xb5, 0xaa,0xcc,0x66,0x66,
+ 0xd8,0x90,0x48,0x48, 0x05,0x06,0x03,0x03, 0x01,0xf7,0xf6,0xf6, 0x12,0x1c,0x0e,0x0e,
+ 0xa3,0xc2,0x61,0x61, 0x5f,0x6a,0x35,0x35, 0xf9,0xae,0x57,0x57, 0xd0,0x69,0xb9,0xb9,
+ 0x91,0x17,0x86,0x86, 0x58,0x99,0xc1,0xc1, 0x27,0x3a,0x1d,0x1d, 0xb9,0x27,0x9e,0x9e,
+ 0x38,0xd9,0xe1,0xe1, 0x13,0xeb,0xf8,0xf8, 0xb3,0x2b,0x98,0x98, 0x33,0x22,0x11,0x11,
+ 0xbb,0xd2,0x69,0x69, 0x70,0xa9,0xd9,0xd9, 0x89,0x07,0x8e,0x8e, 0xa7,0x33,0x94,0x94,
+ 0xb6,0x2d,0x9b,0x9b, 0x22,0x3c,0x1e,0x1e, 0x92,0x15,0x87,0x87, 0x20,0xc9,0xe9,0xe9,
+ 0x49,0x87,0xce,0xce, 0xff,0xaa,0x55,0x55, 0x78,0x50,0x28,0x28, 0x7a,0xa5,0xdf,0xdf,
+ 0x8f,0x03,0x8c,0x8c, 0xf8,0x59,0xa1,0xa1, 0x80,0x09,0x89,0x89, 0x17,0x1a,0x0d,0x0d,
+ 0xda,0x65,0xbf,0xbf, 0x31,0xd7,0xe6,0xe6, 0xc6,0x84,0x42,0x42, 0xb8,0xd0,0x68,0x68,
+ 0xc3,0x82,0x41,0x41, 0xb0,0x29,0x99,0x99, 0x77,0x5a,0x2d,0x2d, 0x11,0x1e,0x0f,0x0f,
+ 0xcb,0x7b,0xb0,0xb0, 0xfc,0xa8,0x54,0x54, 0xd6,0x6d,0xbb,0xbb, 0x3a,0x2c,0x16,0x16
+};
+
+static uint8_t T3[256][4]=
+{
+ 0x63,0xa5,0xc6,0x63, 0x7c,0x84,0xf8,0x7c, 0x77,0x99,0xee,0x77, 0x7b,0x8d,0xf6,0x7b,
+ 0xf2,0x0d,0xff,0xf2, 0x6b,0xbd,0xd6,0x6b, 0x6f,0xb1,0xde,0x6f, 0xc5,0x54,0x91,0xc5,
+ 0x30,0x50,0x60,0x30, 0x01,0x03,0x02,0x01, 0x67,0xa9,0xce,0x67, 0x2b,0x7d,0x56,0x2b,
+ 0xfe,0x19,0xe7,0xfe, 0xd7,0x62,0xb5,0xd7, 0xab,0xe6,0x4d,0xab, 0x76,0x9a,0xec,0x76,
+ 0xca,0x45,0x8f,0xca, 0x82,0x9d,0x1f,0x82, 0xc9,0x40,0x89,0xc9, 0x7d,0x87,0xfa,0x7d,
+ 0xfa,0x15,0xef,0xfa, 0x59,0xeb,0xb2,0x59, 0x47,0xc9,0x8e,0x47, 0xf0,0x0b,0xfb,0xf0,
+ 0xad,0xec,0x41,0xad, 0xd4,0x67,0xb3,0xd4, 0xa2,0xfd,0x5f,0xa2, 0xaf,0xea,0x45,0xaf,
+ 0x9c,0xbf,0x23,0x9c, 0xa4,0xf7,0x53,0xa4, 0x72,0x96,0xe4,0x72, 0xc0,0x5b,0x9b,0xc0,
+ 0xb7,0xc2,0x75,0xb7, 0xfd,0x1c,0xe1,0xfd, 0x93,0xae,0x3d,0x93, 0x26,0x6a,0x4c,0x26,
+ 0x36,0x5a,0x6c,0x36, 0x3f,0x41,0x7e,0x3f, 0xf7,0x02,0xf5,0xf7, 0xcc,0x4f,0x83,0xcc,
+ 0x34,0x5c,0x68,0x34, 0xa5,0xf4,0x51,0xa5, 0xe5,0x34,0xd1,0xe5, 0xf1,0x08,0xf9,0xf1,
+ 0x71,0x93,0xe2,0x71, 0xd8,0x73,0xab,0xd8, 0x31,0x53,0x62,0x31, 0x15,0x3f,0x2a,0x15,
+ 0x04,0x0c,0x08,0x04, 0xc7,0x52,0x95,0xc7, 0x23,0x65,0x46,0x23, 0xc3,0x5e,0x9d,0xc3,
+ 0x18,0x28,0x30,0x18, 0x96,0xa1,0x37,0x96, 0x05,0x0f,0x0a,0x05, 0x9a,0xb5,0x2f,0x9a,
+ 0x07,0x09,0x0e,0x07, 0x12,0x36,0x24,0x12, 0x80,0x9b,0x1b,0x80, 0xe2,0x3d,0xdf,0xe2,
+ 0xeb,0x26,0xcd,0xeb, 0x27,0x69,0x4e,0x27, 0xb2,0xcd,0x7f,0xb2, 0x75,0x9f,0xea,0x75,
+ 0x09,0x1b,0x12,0x09, 0x83,0x9e,0x1d,0x83, 0x2c,0x74,0x58,0x2c, 0x1a,0x2e,0x34,0x1a,
+ 0x1b,0x2d,0x36,0x1b, 0x6e,0xb2,0xdc,0x6e, 0x5a,0xee,0xb4,0x5a, 0xa0,0xfb,0x5b,0xa0,
+ 0x52,0xf6,0xa4,0x52, 0x3b,0x4d,0x76,0x3b, 0xd6,0x61,0xb7,0xd6, 0xb3,0xce,0x7d,0xb3,
+ 0x29,0x7b,0x52,0x29, 0xe3,0x3e,0xdd,0xe3, 0x2f,0x71,0x5e,0x2f, 0x84,0x97,0x13,0x84,
+ 0x53,0xf5,0xa6,0x53, 0xd1,0x68,0xb9,0xd1, 0x00,0x00,0x00,0x00, 0xed,0x2c,0xc1,0xed,
+ 0x20,0x60,0x40,0x20, 0xfc,0x1f,0xe3,0xfc, 0xb1,0xc8,0x79,0xb1, 0x5b,0xed,0xb6,0x5b,
+ 0x6a,0xbe,0xd4,0x6a, 0xcb,0x46,0x8d,0xcb, 0xbe,0xd9,0x67,0xbe, 0x39,0x4b,0x72,0x39,
+ 0x4a,0xde,0x94,0x4a, 0x4c,0xd4,0x98,0x4c, 0x58,0xe8,0xb0,0x58, 0xcf,0x4a,0x85,0xcf,
+ 0xd0,0x6b,0xbb,0xd0, 0xef,0x2a,0xc5,0xef, 0xaa,0xe5,0x4f,0xaa, 0xfb,0x16,0xed,0xfb,
+ 0x43,0xc5,0x86,0x43, 0x4d,0xd7,0x9a,0x4d, 0x33,0x55,0x66,0x33, 0x85,0x94,0x11,0x85,
+ 0x45,0xcf,0x8a,0x45, 0xf9,0x10,0xe9,0xf9, 0x02,0x06,0x04,0x02, 0x7f,0x81,0xfe,0x7f,
+ 0x50,0xf0,0xa0,0x50, 0x3c,0x44,0x78,0x3c, 0x9f,0xba,0x25,0x9f, 0xa8,0xe3,0x4b,0xa8,
+ 0x51,0xf3,0xa2,0x51, 0xa3,0xfe,0x5d,0xa3, 0x40,0xc0,0x80,0x40, 0x8f,0x8a,0x05,0x8f,
+ 0x92,0xad,0x3f,0x92, 0x9d,0xbc,0x21,0x9d, 0x38,0x48,0x70,0x38, 0xf5,0x04,0xf1,0xf5,
+ 0xbc,0xdf,0x63,0xbc, 0xb6,0xc1,0x77,0xb6, 0xda,0x75,0xaf,0xda, 0x21,0x63,0x42,0x21,
+ 0x10,0x30,0x20,0x10, 0xff,0x1a,0xe5,0xff, 0xf3,0x0e,0xfd,0xf3, 0xd2,0x6d,0xbf,0xd2,
+ 0xcd,0x4c,0x81,0xcd, 0x0c,0x14,0x18,0x0c, 0x13,0x35,0x26,0x13, 0xec,0x2f,0xc3,0xec,
+ 0x5f,0xe1,0xbe,0x5f, 0x97,0xa2,0x35,0x97, 0x44,0xcc,0x88,0x44, 0x17,0x39,0x2e,0x17,
+ 0xc4,0x57,0x93,0xc4, 0xa7,0xf2,0x55,0xa7, 0x7e,0x82,0xfc,0x7e, 0x3d,0x47,0x7a,0x3d,
+ 0x64,0xac,0xc8,0x64, 0x5d,0xe7,0xba,0x5d, 0x19,0x2b,0x32,0x19, 0x73,0x95,0xe6,0x73,
+ 0x60,0xa0,0xc0,0x60, 0x81,0x98,0x19,0x81, 0x4f,0xd1,0x9e,0x4f, 0xdc,0x7f,0xa3,0xdc,
+ 0x22,0x66,0x44,0x22, 0x2a,0x7e,0x54,0x2a, 0x90,0xab,0x3b,0x90, 0x88,0x83,0x0b,0x88,
+ 0x46,0xca,0x8c,0x46, 0xee,0x29,0xc7,0xee, 0xb8,0xd3,0x6b,0xb8, 0x14,0x3c,0x28,0x14,
+ 0xde,0x79,0xa7,0xde, 0x5e,0xe2,0xbc,0x5e, 0x0b,0x1d,0x16,0x0b, 0xdb,0x76,0xad,0xdb,
+ 0xe0,0x3b,0xdb,0xe0, 0x32,0x56,0x64,0x32, 0x3a,0x4e,0x74,0x3a, 0x0a,0x1e,0x14,0x0a,
+ 0x49,0xdb,0x92,0x49, 0x06,0x0a,0x0c,0x06, 0x24,0x6c,0x48,0x24, 0x5c,0xe4,0xb8,0x5c,
+ 0xc2,0x5d,0x9f,0xc2, 0xd3,0x6e,0xbd,0xd3, 0xac,0xef,0x43,0xac, 0x62,0xa6,0xc4,0x62,
+ 0x91,0xa8,0x39,0x91, 0x95,0xa4,0x31,0x95, 0xe4,0x37,0xd3,0xe4, 0x79,0x8b,0xf2,0x79,
+ 0xe7,0x32,0xd5,0xe7, 0xc8,0x43,0x8b,0xc8, 0x37,0x59,0x6e,0x37, 0x6d,0xb7,0xda,0x6d,
+ 0x8d,0x8c,0x01,0x8d, 0xd5,0x64,0xb1,0xd5, 0x4e,0xd2,0x9c,0x4e, 0xa9,0xe0,0x49,0xa9,
+ 0x6c,0xb4,0xd8,0x6c, 0x56,0xfa,0xac,0x56, 0xf4,0x07,0xf3,0xf4, 0xea,0x25,0xcf,0xea,
+ 0x65,0xaf,0xca,0x65, 0x7a,0x8e,0xf4,0x7a, 0xae,0xe9,0x47,0xae, 0x08,0x18,0x10,0x08,
+ 0xba,0xd5,0x6f,0xba, 0x78,0x88,0xf0,0x78, 0x25,0x6f,0x4a,0x25, 0x2e,0x72,0x5c,0x2e,
+ 0x1c,0x24,0x38,0x1c, 0xa6,0xf1,0x57,0xa6, 0xb4,0xc7,0x73,0xb4, 0xc6,0x51,0x97,0xc6,
+ 0xe8,0x23,0xcb,0xe8, 0xdd,0x7c,0xa1,0xdd, 0x74,0x9c,0xe8,0x74, 0x1f,0x21,0x3e,0x1f,
+ 0x4b,0xdd,0x96,0x4b, 0xbd,0xdc,0x61,0xbd, 0x8b,0x86,0x0d,0x8b, 0x8a,0x85,0x0f,0x8a,
+ 0x70,0x90,0xe0,0x70, 0x3e,0x42,0x7c,0x3e, 0xb5,0xc4,0x71,0xb5, 0x66,0xaa,0xcc,0x66,
+ 0x48,0xd8,0x90,0x48, 0x03,0x05,0x06,0x03, 0xf6,0x01,0xf7,0xf6, 0x0e,0x12,0x1c,0x0e,
+ 0x61,0xa3,0xc2,0x61, 0x35,0x5f,0x6a,0x35, 0x57,0xf9,0xae,0x57, 0xb9,0xd0,0x69,0xb9,
+ 0x86,0x91,0x17,0x86, 0xc1,0x58,0x99,0xc1, 0x1d,0x27,0x3a,0x1d, 0x9e,0xb9,0x27,0x9e,
+ 0xe1,0x38,0xd9,0xe1, 0xf8,0x13,0xeb,0xf8, 0x98,0xb3,0x2b,0x98, 0x11,0x33,0x22,0x11,
+ 0x69,0xbb,0xd2,0x69, 0xd9,0x70,0xa9,0xd9, 0x8e,0x89,0x07,0x8e, 0x94,0xa7,0x33,0x94,
+ 0x9b,0xb6,0x2d,0x9b, 0x1e,0x22,0x3c,0x1e, 0x87,0x92,0x15,0x87, 0xe9,0x20,0xc9,0xe9,
+ 0xce,0x49,0x87,0xce, 0x55,0xff,0xaa,0x55, 0x28,0x78,0x50,0x28, 0xdf,0x7a,0xa5,0xdf,
+ 0x8c,0x8f,0x03,0x8c, 0xa1,0xf8,0x59,0xa1, 0x89,0x80,0x09,0x89, 0x0d,0x17,0x1a,0x0d,
+ 0xbf,0xda,0x65,0xbf, 0xe6,0x31,0xd7,0xe6, 0x42,0xc6,0x84,0x42, 0x68,0xb8,0xd0,0x68,
+ 0x41,0xc3,0x82,0x41, 0x99,0xb0,0x29,0x99, 0x2d,0x77,0x5a,0x2d, 0x0f,0x11,0x1e,0x0f,
+ 0xb0,0xcb,0x7b,0xb0, 0x54,0xfc,0xa8,0x54, 0xbb,0xd6,0x6d,0xbb, 0x16,0x3a,0x2c,0x16
+};
+
+static uint8_t T4[256][4]=
+{
+ 0x63,0x63,0xa5,0xc6, 0x7c,0x7c,0x84,0xf8, 0x77,0x77,0x99,0xee, 0x7b,0x7b,0x8d,0xf6,
+ 0xf2,0xf2,0x0d,0xff, 0x6b,0x6b,0xbd,0xd6, 0x6f,0x6f,0xb1,0xde, 0xc5,0xc5,0x54,0x91,
+ 0x30,0x30,0x50,0x60, 0x01,0x01,0x03,0x02, 0x67,0x67,0xa9,0xce, 0x2b,0x2b,0x7d,0x56,
+ 0xfe,0xfe,0x19,0xe7, 0xd7,0xd7,0x62,0xb5, 0xab,0xab,0xe6,0x4d, 0x76,0x76,0x9a,0xec,
+ 0xca,0xca,0x45,0x8f, 0x82,0x82,0x9d,0x1f, 0xc9,0xc9,0x40,0x89, 0x7d,0x7d,0x87,0xfa,
+ 0xfa,0xfa,0x15,0xef, 0x59,0x59,0xeb,0xb2, 0x47,0x47,0xc9,0x8e, 0xf0,0xf0,0x0b,0xfb,
+ 0xad,0xad,0xec,0x41, 0xd4,0xd4,0x67,0xb3, 0xa2,0xa2,0xfd,0x5f, 0xaf,0xaf,0xea,0x45,
+ 0x9c,0x9c,0xbf,0x23, 0xa4,0xa4,0xf7,0x53, 0x72,0x72,0x96,0xe4, 0xc0,0xc0,0x5b,0x9b,
+ 0xb7,0xb7,0xc2,0x75, 0xfd,0xfd,0x1c,0xe1, 0x93,0x93,0xae,0x3d, 0x26,0x26,0x6a,0x4c,
+ 0x36,0x36,0x5a,0x6c, 0x3f,0x3f,0x41,0x7e, 0xf7,0xf7,0x02,0xf5, 0xcc,0xcc,0x4f,0x83,
+ 0x34,0x34,0x5c,0x68, 0xa5,0xa5,0xf4,0x51, 0xe5,0xe5,0x34,0xd1, 0xf1,0xf1,0x08,0xf9,
+ 0x71,0x71,0x93,0xe2, 0xd8,0xd8,0x73,0xab, 0x31,0x31,0x53,0x62, 0x15,0x15,0x3f,0x2a,
+ 0x04,0x04,0x0c,0x08, 0xc7,0xc7,0x52,0x95, 0x23,0x23,0x65,0x46, 0xc3,0xc3,0x5e,0x9d,
+ 0x18,0x18,0x28,0x30, 0x96,0x96,0xa1,0x37, 0x05,0x05,0x0f,0x0a, 0x9a,0x9a,0xb5,0x2f,
+ 0x07,0x07,0x09,0x0e, 0x12,0x12,0x36,0x24, 0x80,0x80,0x9b,0x1b, 0xe2,0xe2,0x3d,0xdf,
+ 0xeb,0xeb,0x26,0xcd, 0x27,0x27,0x69,0x4e, 0xb2,0xb2,0xcd,0x7f, 0x75,0x75,0x9f,0xea,
+ 0x09,0x09,0x1b,0x12, 0x83,0x83,0x9e,0x1d, 0x2c,0x2c,0x74,0x58, 0x1a,0x1a,0x2e,0x34,
+ 0x1b,0x1b,0x2d,0x36, 0x6e,0x6e,0xb2,0xdc, 0x5a,0x5a,0xee,0xb4, 0xa0,0xa0,0xfb,0x5b,
+ 0x52,0x52,0xf6,0xa4, 0x3b,0x3b,0x4d,0x76, 0xd6,0xd6,0x61,0xb7, 0xb3,0xb3,0xce,0x7d,
+ 0x29,0x29,0x7b,0x52, 0xe3,0xe3,0x3e,0xdd, 0x2f,0x2f,0x71,0x5e, 0x84,0x84,0x97,0x13,
+ 0x53,0x53,0xf5,0xa6, 0xd1,0xd1,0x68,0xb9, 0x00,0x00,0x00,0x00, 0xed,0xed,0x2c,0xc1,
+ 0x20,0x20,0x60,0x40, 0xfc,0xfc,0x1f,0xe3, 0xb1,0xb1,0xc8,0x79, 0x5b,0x5b,0xed,0xb6,
+ 0x6a,0x6a,0xbe,0xd4, 0xcb,0xcb,0x46,0x8d, 0xbe,0xbe,0xd9,0x67, 0x39,0x39,0x4b,0x72,
+ 0x4a,0x4a,0xde,0x94, 0x4c,0x4c,0xd4,0x98, 0x58,0x58,0xe8,0xb0, 0xcf,0xcf,0x4a,0x85,
+ 0xd0,0xd0,0x6b,0xbb, 0xef,0xef,0x2a,0xc5, 0xaa,0xaa,0xe5,0x4f, 0xfb,0xfb,0x16,0xed,
+ 0x43,0x43,0xc5,0x86, 0x4d,0x4d,0xd7,0x9a, 0x33,0x33,0x55,0x66, 0x85,0x85,0x94,0x11,
+ 0x45,0x45,0xcf,0x8a, 0xf9,0xf9,0x10,0xe9, 0x02,0x02,0x06,0x04, 0x7f,0x7f,0x81,0xfe,
+ 0x50,0x50,0xf0,0xa0, 0x3c,0x3c,0x44,0x78, 0x9f,0x9f,0xba,0x25, 0xa8,0xa8,0xe3,0x4b,
+ 0x51,0x51,0xf3,0xa2, 0xa3,0xa3,0xfe,0x5d, 0x40,0x40,0xc0,0x80, 0x8f,0x8f,0x8a,0x05,
+ 0x92,0x92,0xad,0x3f, 0x9d,0x9d,0xbc,0x21, 0x38,0x38,0x48,0x70, 0xf5,0xf5,0x04,0xf1,
+ 0xbc,0xbc,0xdf,0x63, 0xb6,0xb6,0xc1,0x77, 0xda,0xda,0x75,0xaf, 0x21,0x21,0x63,0x42,
+ 0x10,0x10,0x30,0x20, 0xff,0xff,0x1a,0xe5, 0xf3,0xf3,0x0e,0xfd, 0xd2,0xd2,0x6d,0xbf,
+ 0xcd,0xcd,0x4c,0x81, 0x0c,0x0c,0x14,0x18, 0x13,0x13,0x35,0x26, 0xec,0xec,0x2f,0xc3,
+ 0x5f,0x5f,0xe1,0xbe, 0x97,0x97,0xa2,0x35, 0x44,0x44,0xcc,0x88, 0x17,0x17,0x39,0x2e,
+ 0xc4,0xc4,0x57,0x93, 0xa7,0xa7,0xf2,0x55, 0x7e,0x7e,0x82,0xfc, 0x3d,0x3d,0x47,0x7a,
+ 0x64,0x64,0xac,0xc8, 0x5d,0x5d,0xe7,0xba, 0x19,0x19,0x2b,0x32, 0x73,0x73,0x95,0xe6,
+ 0x60,0x60,0xa0,0xc0, 0x81,0x81,0x98,0x19, 0x4f,0x4f,0xd1,0x9e, 0xdc,0xdc,0x7f,0xa3,
+ 0x22,0x22,0x66,0x44, 0x2a,0x2a,0x7e,0x54, 0x90,0x90,0xab,0x3b, 0x88,0x88,0x83,0x0b,
+ 0x46,0x46,0xca,0x8c, 0xee,0xee,0x29,0xc7, 0xb8,0xb8,0xd3,0x6b, 0x14,0x14,0x3c,0x28,
+ 0xde,0xde,0x79,0xa7, 0x5e,0x5e,0xe2,0xbc, 0x0b,0x0b,0x1d,0x16, 0xdb,0xdb,0x76,0xad,
+ 0xe0,0xe0,0x3b,0xdb, 0x32,0x32,0x56,0x64, 0x3a,0x3a,0x4e,0x74, 0x0a,0x0a,0x1e,0x14,
+ 0x49,0x49,0xdb,0x92, 0x06,0x06,0x0a,0x0c, 0x24,0x24,0x6c,0x48, 0x5c,0x5c,0xe4,0xb8,
+ 0xc2,0xc2,0x5d,0x9f, 0xd3,0xd3,0x6e,0xbd, 0xac,0xac,0xef,0x43, 0x62,0x62,0xa6,0xc4,
+ 0x91,0x91,0xa8,0x39, 0x95,0x95,0xa4,0x31, 0xe4,0xe4,0x37,0xd3, 0x79,0x79,0x8b,0xf2,
+ 0xe7,0xe7,0x32,0xd5, 0xc8,0xc8,0x43,0x8b, 0x37,0x37,0x59,0x6e, 0x6d,0x6d,0xb7,0xda,
+ 0x8d,0x8d,0x8c,0x01, 0xd5,0xd5,0x64,0xb1, 0x4e,0x4e,0xd2,0x9c, 0xa9,0xa9,0xe0,0x49,
+ 0x6c,0x6c,0xb4,0xd8, 0x56,0x56,0xfa,0xac, 0xf4,0xf4,0x07,0xf3, 0xea,0xea,0x25,0xcf,
+ 0x65,0x65,0xaf,0xca, 0x7a,0x7a,0x8e,0xf4, 0xae,0xae,0xe9,0x47, 0x08,0x08,0x18,0x10,
+ 0xba,0xba,0xd5,0x6f, 0x78,0x78,0x88,0xf0, 0x25,0x25,0x6f,0x4a, 0x2e,0x2e,0x72,0x5c,
+ 0x1c,0x1c,0x24,0x38, 0xa6,0xa6,0xf1,0x57, 0xb4,0xb4,0xc7,0x73, 0xc6,0xc6,0x51,0x97,
+ 0xe8,0xe8,0x23,0xcb, 0xdd,0xdd,0x7c,0xa1, 0x74,0x74,0x9c,0xe8, 0x1f,0x1f,0x21,0x3e,
+ 0x4b,0x4b,0xdd,0x96, 0xbd,0xbd,0xdc,0x61, 0x8b,0x8b,0x86,0x0d, 0x8a,0x8a,0x85,0x0f,
+ 0x70,0x70,0x90,0xe0, 0x3e,0x3e,0x42,0x7c, 0xb5,0xb5,0xc4,0x71, 0x66,0x66,0xaa,0xcc,
+ 0x48,0x48,0xd8,0x90, 0x03,0x03,0x05,0x06, 0xf6,0xf6,0x01,0xf7, 0x0e,0x0e,0x12,0x1c,
+ 0x61,0x61,0xa3,0xc2, 0x35,0x35,0x5f,0x6a, 0x57,0x57,0xf9,0xae, 0xb9,0xb9,0xd0,0x69,
+ 0x86,0x86,0x91,0x17, 0xc1,0xc1,0x58,0x99, 0x1d,0x1d,0x27,0x3a, 0x9e,0x9e,0xb9,0x27,
+ 0xe1,0xe1,0x38,0xd9, 0xf8,0xf8,0x13,0xeb, 0x98,0x98,0xb3,0x2b, 0x11,0x11,0x33,0x22,
+ 0x69,0x69,0xbb,0xd2, 0xd9,0xd9,0x70,0xa9, 0x8e,0x8e,0x89,0x07, 0x94,0x94,0xa7,0x33,
+ 0x9b,0x9b,0xb6,0x2d, 0x1e,0x1e,0x22,0x3c, 0x87,0x87,0x92,0x15, 0xe9,0xe9,0x20,0xc9,
+ 0xce,0xce,0x49,0x87, 0x55,0x55,0xff,0xaa, 0x28,0x28,0x78,0x50, 0xdf,0xdf,0x7a,0xa5,
+ 0x8c,0x8c,0x8f,0x03, 0xa1,0xa1,0xf8,0x59, 0x89,0x89,0x80,0x09, 0x0d,0x0d,0x17,0x1a,
+ 0xbf,0xbf,0xda,0x65, 0xe6,0xe6,0x31,0xd7, 0x42,0x42,0xc6,0x84, 0x68,0x68,0xb8,0xd0,
+ 0x41,0x41,0xc3,0x82, 0x99,0x99,0xb0,0x29, 0x2d,0x2d,0x77,0x5a, 0x0f,0x0f,0x11,0x1e,
+ 0xb0,0xb0,0xcb,0x7b, 0x54,0x54,0xfc,0xa8, 0xbb,0xbb,0xd6,0x6d, 0x16,0x16,0x3a,0x2c
+};
+
+static uint8_t T5[256][4]=
+{
+ 0x51,0xf4,0xa7,0x50, 0x7e,0x41,0x65,0x53, 0x1a,0x17,0xa4,0xc3, 0x3a,0x27,0x5e,0x96,
+ 0x3b,0xab,0x6b,0xcb, 0x1f,0x9d,0x45,0xf1, 0xac,0xfa,0x58,0xab, 0x4b,0xe3,0x03,0x93,
+ 0x20,0x30,0xfa,0x55, 0xad,0x76,0x6d,0xf6, 0x88,0xcc,0x76,0x91, 0xf5,0x02,0x4c,0x25,
+ 0x4f,0xe5,0xd7,0xfc, 0xc5,0x2a,0xcb,0xd7, 0x26,0x35,0x44,0x80, 0xb5,0x62,0xa3,0x8f,
+ 0xde,0xb1,0x5a,0x49, 0x25,0xba,0x1b,0x67, 0x45,0xea,0x0e,0x98, 0x5d,0xfe,0xc0,0xe1,
+ 0xc3,0x2f,0x75,0x02, 0x81,0x4c,0xf0,0x12, 0x8d,0x46,0x97,0xa3, 0x6b,0xd3,0xf9,0xc6,
+ 0x03,0x8f,0x5f,0xe7, 0x15,0x92,0x9c,0x95, 0xbf,0x6d,0x7a,0xeb, 0x95,0x52,0x59,0xda,
+ 0xd4,0xbe,0x83,0x2d, 0x58,0x74,0x21,0xd3, 0x49,0xe0,0x69,0x29, 0x8e,0xc9,0xc8,0x44,
+ 0x75,0xc2,0x89,0x6a, 0xf4,0x8e,0x79,0x78, 0x99,0x58,0x3e,0x6b, 0x27,0xb9,0x71,0xdd,
+ 0xbe,0xe1,0x4f,0xb6, 0xf0,0x88,0xad,0x17, 0xc9,0x20,0xac,0x66, 0x7d,0xce,0x3a,0xb4,
+ 0x63,0xdf,0x4a,0x18, 0xe5,0x1a,0x31,0x82, 0x97,0x51,0x33,0x60, 0x62,0x53,0x7f,0x45,
+ 0xb1,0x64,0x77,0xe0, 0xbb,0x6b,0xae,0x84, 0xfe,0x81,0xa0,0x1c, 0xf9,0x08,0x2b,0x94,
+ 0x70,0x48,0x68,0x58, 0x8f,0x45,0xfd,0x19, 0x94,0xde,0x6c,0x87, 0x52,0x7b,0xf8,0xb7,
+ 0xab,0x73,0xd3,0x23, 0x72,0x4b,0x02,0xe2, 0xe3,0x1f,0x8f,0x57, 0x66,0x55,0xab,0x2a,
+ 0xb2,0xeb,0x28,0x07, 0x2f,0xb5,0xc2,0x03, 0x86,0xc5,0x7b,0x9a, 0xd3,0x37,0x08,0xa5,
+ 0x30,0x28,0x87,0xf2, 0x23,0xbf,0xa5,0xb2, 0x02,0x03,0x6a,0xba, 0xed,0x16,0x82,0x5c,
+ 0x8a,0xcf,0x1c,0x2b, 0xa7,0x79,0xb4,0x92, 0xf3,0x07,0xf2,0xf0, 0x4e,0x69,0xe2,0xa1,
+ 0x65,0xda,0xf4,0xcd, 0x06,0x05,0xbe,0xd5, 0xd1,0x34,0x62,0x1f, 0xc4,0xa6,0xfe,0x8a,
+ 0x34,0x2e,0x53,0x9d, 0xa2,0xf3,0x55,0xa0, 0x05,0x8a,0xe1,0x32, 0xa4,0xf6,0xeb,0x75,
+ 0x0b,0x83,0xec,0x39, 0x40,0x60,0xef,0xaa, 0x5e,0x71,0x9f,0x06, 0xbd,0x6e,0x10,0x51,
+ 0x3e,0x21,0x8a,0xf9, 0x96,0xdd,0x06,0x3d, 0xdd,0x3e,0x05,0xae, 0x4d,0xe6,0xbd,0x46,
+ 0x91,0x54,0x8d,0xb5, 0x71,0xc4,0x5d,0x05, 0x04,0x06,0xd4,0x6f, 0x60,0x50,0x15,0xff,
+ 0x19,0x98,0xfb,0x24, 0xd6,0xbd,0xe9,0x97, 0x89,0x40,0x43,0xcc, 0x67,0xd9,0x9e,0x77,
+ 0xb0,0xe8,0x42,0xbd, 0x07,0x89,0x8b,0x88, 0xe7,0x19,0x5b,0x38, 0x79,0xc8,0xee,0xdb,
+ 0xa1,0x7c,0x0a,0x47, 0x7c,0x42,0x0f,0xe9, 0xf8,0x84,0x1e,0xc9, 0x00,0x00,0x00,0x00,
+ 0x09,0x80,0x86,0x83, 0x32,0x2b,0xed,0x48, 0x1e,0x11,0x70,0xac, 0x6c,0x5a,0x72,0x4e,
+ 0xfd,0x0e,0xff,0xfb, 0x0f,0x85,0x38,0x56, 0x3d,0xae,0xd5,0x1e, 0x36,0x2d,0x39,0x27,
+ 0x0a,0x0f,0xd9,0x64, 0x68,0x5c,0xa6,0x21, 0x9b,0x5b,0x54,0xd1, 0x24,0x36,0x2e,0x3a,
+ 0x0c,0x0a,0x67,0xb1, 0x93,0x57,0xe7,0x0f, 0xb4,0xee,0x96,0xd2, 0x1b,0x9b,0x91,0x9e,
+ 0x80,0xc0,0xc5,0x4f, 0x61,0xdc,0x20,0xa2, 0x5a,0x77,0x4b,0x69, 0x1c,0x12,0x1a,0x16,
+ 0xe2,0x93,0xba,0x0a, 0xc0,0xa0,0x2a,0xe5, 0x3c,0x22,0xe0,0x43, 0x12,0x1b,0x17,0x1d,
+ 0x0e,0x09,0x0d,0x0b, 0xf2,0x8b,0xc7,0xad, 0x2d,0xb6,0xa8,0xb9, 0x14,0x1e,0xa9,0xc8,
+ 0x57,0xf1,0x19,0x85, 0xaf,0x75,0x07,0x4c, 0xee,0x99,0xdd,0xbb, 0xa3,0x7f,0x60,0xfd,
+ 0xf7,0x01,0x26,0x9f, 0x5c,0x72,0xf5,0xbc, 0x44,0x66,0x3b,0xc5, 0x5b,0xfb,0x7e,0x34,
+ 0x8b,0x43,0x29,0x76, 0xcb,0x23,0xc6,0xdc, 0xb6,0xed,0xfc,0x68, 0xb8,0xe4,0xf1,0x63,
+ 0xd7,0x31,0xdc,0xca, 0x42,0x63,0x85,0x10, 0x13,0x97,0x22,0x40, 0x84,0xc6,0x11,0x20,
+ 0x85,0x4a,0x24,0x7d, 0xd2,0xbb,0x3d,0xf8, 0xae,0xf9,0x32,0x11, 0xc7,0x29,0xa1,0x6d,
+ 0x1d,0x9e,0x2f,0x4b, 0xdc,0xb2,0x30,0xf3, 0x0d,0x86,0x52,0xec, 0x77,0xc1,0xe3,0xd0,
+ 0x2b,0xb3,0x16,0x6c, 0xa9,0x70,0xb9,0x99, 0x11,0x94,0x48,0xfa, 0x47,0xe9,0x64,0x22,
+ 0xa8,0xfc,0x8c,0xc4, 0xa0,0xf0,0x3f,0x1a, 0x56,0x7d,0x2c,0xd8, 0x22,0x33,0x90,0xef,
+ 0x87,0x49,0x4e,0xc7, 0xd9,0x38,0xd1,0xc1, 0x8c,0xca,0xa2,0xfe, 0x98,0xd4,0x0b,0x36,
+ 0xa6,0xf5,0x81,0xcf, 0xa5,0x7a,0xde,0x28, 0xda,0xb7,0x8e,0x26, 0x3f,0xad,0xbf,0xa4,
+ 0x2c,0x3a,0x9d,0xe4, 0x50,0x78,0x92,0x0d, 0x6a,0x5f,0xcc,0x9b, 0x54,0x7e,0x46,0x62,
+ 0xf6,0x8d,0x13,0xc2, 0x90,0xd8,0xb8,0xe8, 0x2e,0x39,0xf7,0x5e, 0x82,0xc3,0xaf,0xf5,
+ 0x9f,0x5d,0x80,0xbe, 0x69,0xd0,0x93,0x7c, 0x6f,0xd5,0x2d,0xa9, 0xcf,0x25,0x12,0xb3,
+ 0xc8,0xac,0x99,0x3b, 0x10,0x18,0x7d,0xa7, 0xe8,0x9c,0x63,0x6e, 0xdb,0x3b,0xbb,0x7b,
+ 0xcd,0x26,0x78,0x09, 0x6e,0x59,0x18,0xf4, 0xec,0x9a,0xb7,0x01, 0x83,0x4f,0x9a,0xa8,
+ 0xe6,0x95,0x6e,0x65, 0xaa,0xff,0xe6,0x7e, 0x21,0xbc,0xcf,0x08, 0xef,0x15,0xe8,0xe6,
+ 0xba,0xe7,0x9b,0xd9, 0x4a,0x6f,0x36,0xce, 0xea,0x9f,0x09,0xd4, 0x29,0xb0,0x7c,0xd6,
+ 0x31,0xa4,0xb2,0xaf, 0x2a,0x3f,0x23,0x31, 0xc6,0xa5,0x94,0x30, 0x35,0xa2,0x66,0xc0,
+ 0x74,0x4e,0xbc,0x37, 0xfc,0x82,0xca,0xa6, 0xe0,0x90,0xd0,0xb0, 0x33,0xa7,0xd8,0x15,
+ 0xf1,0x04,0x98,0x4a, 0x41,0xec,0xda,0xf7, 0x7f,0xcd,0x50,0x0e, 0x17,0x91,0xf6,0x2f,
+ 0x76,0x4d,0xd6,0x8d, 0x43,0xef,0xb0,0x4d, 0xcc,0xaa,0x4d,0x54, 0xe4,0x96,0x04,0xdf,
+ 0x9e,0xd1,0xb5,0xe3, 0x4c,0x6a,0x88,0x1b, 0xc1,0x2c,0x1f,0xb8, 0x46,0x65,0x51,0x7f,
+ 0x9d,0x5e,0xea,0x04, 0x01,0x8c,0x35,0x5d, 0xfa,0x87,0x74,0x73, 0xfb,0x0b,0x41,0x2e,
+ 0xb3,0x67,0x1d,0x5a, 0x92,0xdb,0xd2,0x52, 0xe9,0x10,0x56,0x33, 0x6d,0xd6,0x47,0x13,
+ 0x9a,0xd7,0x61,0x8c, 0x37,0xa1,0x0c,0x7a, 0x59,0xf8,0x14,0x8e, 0xeb,0x13,0x3c,0x89,
+ 0xce,0xa9,0x27,0xee, 0xb7,0x61,0xc9,0x35, 0xe1,0x1c,0xe5,0xed, 0x7a,0x47,0xb1,0x3c,
+ 0x9c,0xd2,0xdf,0x59, 0x55,0xf2,0x73,0x3f, 0x18,0x14,0xce,0x79, 0x73,0xc7,0x37,0xbf,
+ 0x53,0xf7,0xcd,0xea, 0x5f,0xfd,0xaa,0x5b, 0xdf,0x3d,0x6f,0x14, 0x78,0x44,0xdb,0x86,
+ 0xca,0xaf,0xf3,0x81, 0xb9,0x68,0xc4,0x3e, 0x38,0x24,0x34,0x2c, 0xc2,0xa3,0x40,0x5f,
+ 0x16,0x1d,0xc3,0x72, 0xbc,0xe2,0x25,0x0c, 0x28,0x3c,0x49,0x8b, 0xff,0x0d,0x95,0x41,
+ 0x39,0xa8,0x01,0x71, 0x08,0x0c,0xb3,0xde, 0xd8,0xb4,0xe4,0x9c, 0x64,0x56,0xc1,0x90,
+ 0x7b,0xcb,0x84,0x61, 0xd5,0x32,0xb6,0x70, 0x48,0x6c,0x5c,0x74, 0xd0,0xb8,0x57,0x42
+};
+
+static uint8_t T6[256][4]=
+{
+ 0x50,0x51,0xf4,0xa7, 0x53,0x7e,0x41,0x65, 0xc3,0x1a,0x17,0xa4, 0x96,0x3a,0x27,0x5e,
+ 0xcb,0x3b,0xab,0x6b, 0xf1,0x1f,0x9d,0x45, 0xab,0xac,0xfa,0x58, 0x93,0x4b,0xe3,0x03,
+ 0x55,0x20,0x30,0xfa, 0xf6,0xad,0x76,0x6d, 0x91,0x88,0xcc,0x76, 0x25,0xf5,0x02,0x4c,
+ 0xfc,0x4f,0xe5,0xd7, 0xd7,0xc5,0x2a,0xcb, 0x80,0x26,0x35,0x44, 0x8f,0xb5,0x62,0xa3,
+ 0x49,0xde,0xb1,0x5a, 0x67,0x25,0xba,0x1b, 0x98,0x45,0xea,0x0e, 0xe1,0x5d,0xfe,0xc0,
+ 0x02,0xc3,0x2f,0x75, 0x12,0x81,0x4c,0xf0, 0xa3,0x8d,0x46,0x97, 0xc6,0x6b,0xd3,0xf9,
+ 0xe7,0x03,0x8f,0x5f, 0x95,0x15,0x92,0x9c, 0xeb,0xbf,0x6d,0x7a, 0xda,0x95,0x52,0x59,
+ 0x2d,0xd4,0xbe,0x83, 0xd3,0x58,0x74,0x21, 0x29,0x49,0xe0,0x69, 0x44,0x8e,0xc9,0xc8,
+ 0x6a,0x75,0xc2,0x89, 0x78,0xf4,0x8e,0x79, 0x6b,0x99,0x58,0x3e, 0xdd,0x27,0xb9,0x71,
+ 0xb6,0xbe,0xe1,0x4f, 0x17,0xf0,0x88,0xad, 0x66,0xc9,0x20,0xac, 0xb4,0x7d,0xce,0x3a,
+ 0x18,0x63,0xdf,0x4a, 0x82,0xe5,0x1a,0x31, 0x60,0x97,0x51,0x33, 0x45,0x62,0x53,0x7f,
+ 0xe0,0xb1,0x64,0x77, 0x84,0xbb,0x6b,0xae, 0x1c,0xfe,0x81,0xa0, 0x94,0xf9,0x08,0x2b,
+ 0x58,0x70,0x48,0x68, 0x19,0x8f,0x45,0xfd, 0x87,0x94,0xde,0x6c, 0xb7,0x52,0x7b,0xf8,
+ 0x23,0xab,0x73,0xd3, 0xe2,0x72,0x4b,0x02, 0x57,0xe3,0x1f,0x8f, 0x2a,0x66,0x55,0xab,
+ 0x07,0xb2,0xeb,0x28, 0x03,0x2f,0xb5,0xc2, 0x9a,0x86,0xc5,0x7b, 0xa5,0xd3,0x37,0x08,
+ 0xf2,0x30,0x28,0x87, 0xb2,0x23,0xbf,0xa5, 0xba,0x02,0x03,0x6a, 0x5c,0xed,0x16,0x82,
+ 0x2b,0x8a,0xcf,0x1c, 0x92,0xa7,0x79,0xb4, 0xf0,0xf3,0x07,0xf2, 0xa1,0x4e,0x69,0xe2,
+ 0xcd,0x65,0xda,0xf4, 0xd5,0x06,0x05,0xbe, 0x1f,0xd1,0x34,0x62, 0x8a,0xc4,0xa6,0xfe,
+ 0x9d,0x34,0x2e,0x53, 0xa0,0xa2,0xf3,0x55, 0x32,0x05,0x8a,0xe1, 0x75,0xa4,0xf6,0xeb,
+ 0x39,0x0b,0x83,0xec, 0xaa,0x40,0x60,0xef, 0x06,0x5e,0x71,0x9f, 0x51,0xbd,0x6e,0x10,
+ 0xf9,0x3e,0x21,0x8a, 0x3d,0x96,0xdd,0x06, 0xae,0xdd,0x3e,0x05, 0x46,0x4d,0xe6,0xbd,
+ 0xb5,0x91,0x54,0x8d, 0x05,0x71,0xc4,0x5d, 0x6f,0x04,0x06,0xd4, 0xff,0x60,0x50,0x15,
+ 0x24,0x19,0x98,0xfb, 0x97,0xd6,0xbd,0xe9, 0xcc,0x89,0x40,0x43, 0x77,0x67,0xd9,0x9e,
+ 0xbd,0xb0,0xe8,0x42, 0x88,0x07,0x89,0x8b, 0x38,0xe7,0x19,0x5b, 0xdb,0x79,0xc8,0xee,
+ 0x47,0xa1,0x7c,0x0a, 0xe9,0x7c,0x42,0x0f, 0xc9,0xf8,0x84,0x1e, 0x00,0x00,0x00,0x00,
+ 0x83,0x09,0x80,0x86, 0x48,0x32,0x2b,0xed, 0xac,0x1e,0x11,0x70, 0x4e,0x6c,0x5a,0x72,
+ 0xfb,0xfd,0x0e,0xff, 0x56,0x0f,0x85,0x38, 0x1e,0x3d,0xae,0xd5, 0x27,0x36,0x2d,0x39,
+ 0x64,0x0a,0x0f,0xd9, 0x21,0x68,0x5c,0xa6, 0xd1,0x9b,0x5b,0x54, 0x3a,0x24,0x36,0x2e,
+ 0xb1,0x0c,0x0a,0x67, 0x0f,0x93,0x57,0xe7, 0xd2,0xb4,0xee,0x96, 0x9e,0x1b,0x9b,0x91,
+ 0x4f,0x80,0xc0,0xc5, 0xa2,0x61,0xdc,0x20, 0x69,0x5a,0x77,0x4b, 0x16,0x1c,0x12,0x1a,
+ 0x0a,0xe2,0x93,0xba, 0xe5,0xc0,0xa0,0x2a, 0x43,0x3c,0x22,0xe0, 0x1d,0x12,0x1b,0x17,
+ 0x0b,0x0e,0x09,0x0d, 0xad,0xf2,0x8b,0xc7, 0xb9,0x2d,0xb6,0xa8, 0xc8,0x14,0x1e,0xa9,
+ 0x85,0x57,0xf1,0x19, 0x4c,0xaf,0x75,0x07, 0xbb,0xee,0x99,0xdd, 0xfd,0xa3,0x7f,0x60,
+ 0x9f,0xf7,0x01,0x26, 0xbc,0x5c,0x72,0xf5, 0xc5,0x44,0x66,0x3b, 0x34,0x5b,0xfb,0x7e,
+ 0x76,0x8b,0x43,0x29, 0xdc,0xcb,0x23,0xc6, 0x68,0xb6,0xed,0xfc, 0x63,0xb8,0xe4,0xf1,
+ 0xca,0xd7,0x31,0xdc, 0x10,0x42,0x63,0x85, 0x40,0x13,0x97,0x22, 0x20,0x84,0xc6,0x11,
+ 0x7d,0x85,0x4a,0x24, 0xf8,0xd2,0xbb,0x3d, 0x11,0xae,0xf9,0x32, 0x6d,0xc7,0x29,0xa1,
+ 0x4b,0x1d,0x9e,0x2f, 0xf3,0xdc,0xb2,0x30, 0xec,0x0d,0x86,0x52, 0xd0,0x77,0xc1,0xe3,
+ 0x6c,0x2b,0xb3,0x16, 0x99,0xa9,0x70,0xb9, 0xfa,0x11,0x94,0x48, 0x22,0x47,0xe9,0x64,
+ 0xc4,0xa8,0xfc,0x8c, 0x1a,0xa0,0xf0,0x3f, 0xd8,0x56,0x7d,0x2c, 0xef,0x22,0x33,0x90,
+ 0xc7,0x87,0x49,0x4e, 0xc1,0xd9,0x38,0xd1, 0xfe,0x8c,0xca,0xa2, 0x36,0x98,0xd4,0x0b,
+ 0xcf,0xa6,0xf5,0x81, 0x28,0xa5,0x7a,0xde, 0x26,0xda,0xb7,0x8e, 0xa4,0x3f,0xad,0xbf,
+ 0xe4,0x2c,0x3a,0x9d, 0x0d,0x50,0x78,0x92, 0x9b,0x6a,0x5f,0xcc, 0x62,0x54,0x7e,0x46,
+ 0xc2,0xf6,0x8d,0x13, 0xe8,0x90,0xd8,0xb8, 0x5e,0x2e,0x39,0xf7, 0xf5,0x82,0xc3,0xaf,
+ 0xbe,0x9f,0x5d,0x80, 0x7c,0x69,0xd0,0x93, 0xa9,0x6f,0xd5,0x2d, 0xb3,0xcf,0x25,0x12,
+ 0x3b,0xc8,0xac,0x99, 0xa7,0x10,0x18,0x7d, 0x6e,0xe8,0x9c,0x63, 0x7b,0xdb,0x3b,0xbb,
+ 0x09,0xcd,0x26,0x78, 0xf4,0x6e,0x59,0x18, 0x01,0xec,0x9a,0xb7, 0xa8,0x83,0x4f,0x9a,
+ 0x65,0xe6,0x95,0x6e, 0x7e,0xaa,0xff,0xe6, 0x08,0x21,0xbc,0xcf, 0xe6,0xef,0x15,0xe8,
+ 0xd9,0xba,0xe7,0x9b, 0xce,0x4a,0x6f,0x36, 0xd4,0xea,0x9f,0x09, 0xd6,0x29,0xb0,0x7c,
+ 0xaf,0x31,0xa4,0xb2, 0x31,0x2a,0x3f,0x23, 0x30,0xc6,0xa5,0x94, 0xc0,0x35,0xa2,0x66,
+ 0x37,0x74,0x4e,0xbc, 0xa6,0xfc,0x82,0xca, 0xb0,0xe0,0x90,0xd0, 0x15,0x33,0xa7,0xd8,
+ 0x4a,0xf1,0x04,0x98, 0xf7,0x41,0xec,0xda, 0x0e,0x7f,0xcd,0x50, 0x2f,0x17,0x91,0xf6,
+ 0x8d,0x76,0x4d,0xd6, 0x4d,0x43,0xef,0xb0, 0x54,0xcc,0xaa,0x4d, 0xdf,0xe4,0x96,0x04,
+ 0xe3,0x9e,0xd1,0xb5, 0x1b,0x4c,0x6a,0x88, 0xb8,0xc1,0x2c,0x1f, 0x7f,0x46,0x65,0x51,
+ 0x04,0x9d,0x5e,0xea, 0x5d,0x01,0x8c,0x35, 0x73,0xfa,0x87,0x74, 0x2e,0xfb,0x0b,0x41,
+ 0x5a,0xb3,0x67,0x1d, 0x52,0x92,0xdb,0xd2, 0x33,0xe9,0x10,0x56, 0x13,0x6d,0xd6,0x47,
+ 0x8c,0x9a,0xd7,0x61, 0x7a,0x37,0xa1,0x0c, 0x8e,0x59,0xf8,0x14, 0x89,0xeb,0x13,0x3c,
+ 0xee,0xce,0xa9,0x27, 0x35,0xb7,0x61,0xc9, 0xed,0xe1,0x1c,0xe5, 0x3c,0x7a,0x47,0xb1,
+ 0x59,0x9c,0xd2,0xdf, 0x3f,0x55,0xf2,0x73, 0x79,0x18,0x14,0xce, 0xbf,0x73,0xc7,0x37,
+ 0xea,0x53,0xf7,0xcd, 0x5b,0x5f,0xfd,0xaa, 0x14,0xdf,0x3d,0x6f, 0x86,0x78,0x44,0xdb,
+ 0x81,0xca,0xaf,0xf3, 0x3e,0xb9,0x68,0xc4, 0x2c,0x38,0x24,0x34, 0x5f,0xc2,0xa3,0x40,
+ 0x72,0x16,0x1d,0xc3, 0x0c,0xbc,0xe2,0x25, 0x8b,0x28,0x3c,0x49, 0x41,0xff,0x0d,0x95,
+ 0x71,0x39,0xa8,0x01, 0xde,0x08,0x0c,0xb3, 0x9c,0xd8,0xb4,0xe4, 0x90,0x64,0x56,0xc1,
+ 0x61,0x7b,0xcb,0x84, 0x70,0xd5,0x32,0xb6, 0x74,0x48,0x6c,0x5c, 0x42,0xd0,0xb8,0x57
+};
+
+static uint8_t T7[256][4]=
+{
+ 0xa7,0x50,0x51,0xf4, 0x65,0x53,0x7e,0x41, 0xa4,0xc3,0x1a,0x17, 0x5e,0x96,0x3a,0x27,
+ 0x6b,0xcb,0x3b,0xab, 0x45,0xf1,0x1f,0x9d, 0x58,0xab,0xac,0xfa, 0x03,0x93,0x4b,0xe3,
+ 0xfa,0x55,0x20,0x30, 0x6d,0xf6,0xad,0x76, 0x76,0x91,0x88,0xcc, 0x4c,0x25,0xf5,0x02,
+ 0xd7,0xfc,0x4f,0xe5, 0xcb,0xd7,0xc5,0x2a, 0x44,0x80,0x26,0x35, 0xa3,0x8f,0xb5,0x62,
+ 0x5a,0x49,0xde,0xb1, 0x1b,0x67,0x25,0xba, 0x0e,0x98,0x45,0xea, 0xc0,0xe1,0x5d,0xfe,
+ 0x75,0x02,0xc3,0x2f, 0xf0,0x12,0x81,0x4c, 0x97,0xa3,0x8d,0x46, 0xf9,0xc6,0x6b,0xd3,
+ 0x5f,0xe7,0x03,0x8f, 0x9c,0x95,0x15,0x92, 0x7a,0xeb,0xbf,0x6d, 0x59,0xda,0x95,0x52,
+ 0x83,0x2d,0xd4,0xbe, 0x21,0xd3,0x58,0x74, 0x69,0x29,0x49,0xe0, 0xc8,0x44,0x8e,0xc9,
+ 0x89,0x6a,0x75,0xc2, 0x79,0x78,0xf4,0x8e, 0x3e,0x6b,0x99,0x58, 0x71,0xdd,0x27,0xb9,
+ 0x4f,0xb6,0xbe,0xe1, 0xad,0x17,0xf0,0x88, 0xac,0x66,0xc9,0x20, 0x3a,0xb4,0x7d,0xce,
+ 0x4a,0x18,0x63,0xdf, 0x31,0x82,0xe5,0x1a, 0x33,0x60,0x97,0x51, 0x7f,0x45,0x62,0x53,
+ 0x77,0xe0,0xb1,0x64, 0xae,0x84,0xbb,0x6b, 0xa0,0x1c,0xfe,0x81, 0x2b,0x94,0xf9,0x08,
+ 0x68,0x58,0x70,0x48, 0xfd,0x19,0x8f,0x45, 0x6c,0x87,0x94,0xde, 0xf8,0xb7,0x52,0x7b,
+ 0xd3,0x23,0xab,0x73, 0x02,0xe2,0x72,0x4b, 0x8f,0x57,0xe3,0x1f, 0xab,0x2a,0x66,0x55,
+ 0x28,0x07,0xb2,0xeb, 0xc2,0x03,0x2f,0xb5, 0x7b,0x9a,0x86,0xc5, 0x08,0xa5,0xd3,0x37,
+ 0x87,0xf2,0x30,0x28, 0xa5,0xb2,0x23,0xbf, 0x6a,0xba,0x02,0x03, 0x82,0x5c,0xed,0x16,
+ 0x1c,0x2b,0x8a,0xcf, 0xb4,0x92,0xa7,0x79, 0xf2,0xf0,0xf3,0x07, 0xe2,0xa1,0x4e,0x69,
+ 0xf4,0xcd,0x65,0xda, 0xbe,0xd5,0x06,0x05, 0x62,0x1f,0xd1,0x34, 0xfe,0x8a,0xc4,0xa6,
+ 0x53,0x9d,0x34,0x2e, 0x55,0xa0,0xa2,0xf3, 0xe1,0x32,0x05,0x8a, 0xeb,0x75,0xa4,0xf6,
+ 0xec,0x39,0x0b,0x83, 0xef,0xaa,0x40,0x60, 0x9f,0x06,0x5e,0x71, 0x10,0x51,0xbd,0x6e,
+ 0x8a,0xf9,0x3e,0x21, 0x06,0x3d,0x96,0xdd, 0x05,0xae,0xdd,0x3e, 0xbd,0x46,0x4d,0xe6,
+ 0x8d,0xb5,0x91,0x54, 0x5d,0x05,0x71,0xc4, 0xd4,0x6f,0x04,0x06, 0x15,0xff,0x60,0x50,
+ 0xfb,0x24,0x19,0x98, 0xe9,0x97,0xd6,0xbd, 0x43,0xcc,0x89,0x40, 0x9e,0x77,0x67,0xd9,
+ 0x42,0xbd,0xb0,0xe8, 0x8b,0x88,0x07,0x89, 0x5b,0x38,0xe7,0x19, 0xee,0xdb,0x79,0xc8,
+ 0x0a,0x47,0xa1,0x7c, 0x0f,0xe9,0x7c,0x42, 0x1e,0xc9,0xf8,0x84, 0x00,0x00,0x00,0x00,
+ 0x86,0x83,0x09,0x80, 0xed,0x48,0x32,0x2b, 0x70,0xac,0x1e,0x11, 0x72,0x4e,0x6c,0x5a,
+ 0xff,0xfb,0xfd,0x0e, 0x38,0x56,0x0f,0x85, 0xd5,0x1e,0x3d,0xae, 0x39,0x27,0x36,0x2d,
+ 0xd9,0x64,0x0a,0x0f, 0xa6,0x21,0x68,0x5c, 0x54,0xd1,0x9b,0x5b, 0x2e,0x3a,0x24,0x36,
+ 0x67,0xb1,0x0c,0x0a, 0xe7,0x0f,0x93,0x57, 0x96,0xd2,0xb4,0xee, 0x91,0x9e,0x1b,0x9b,
+ 0xc5,0x4f,0x80,0xc0, 0x20,0xa2,0x61,0xdc, 0x4b,0x69,0x5a,0x77, 0x1a,0x16,0x1c,0x12,
+ 0xba,0x0a,0xe2,0x93, 0x2a,0xe5,0xc0,0xa0, 0xe0,0x43,0x3c,0x22, 0x17,0x1d,0x12,0x1b,
+ 0x0d,0x0b,0x0e,0x09, 0xc7,0xad,0xf2,0x8b, 0xa8,0xb9,0x2d,0xb6, 0xa9,0xc8,0x14,0x1e,
+ 0x19,0x85,0x57,0xf1, 0x07,0x4c,0xaf,0x75, 0xdd,0xbb,0xee,0x99, 0x60,0xfd,0xa3,0x7f,
+ 0x26,0x9f,0xf7,0x01, 0xf5,0xbc,0x5c,0x72, 0x3b,0xc5,0x44,0x66, 0x7e,0x34,0x5b,0xfb,
+ 0x29,0x76,0x8b,0x43, 0xc6,0xdc,0xcb,0x23, 0xfc,0x68,0xb6,0xed, 0xf1,0x63,0xb8,0xe4,
+ 0xdc,0xca,0xd7,0x31, 0x85,0x10,0x42,0x63, 0x22,0x40,0x13,0x97, 0x11,0x20,0x84,0xc6,
+ 0x24,0x7d,0x85,0x4a, 0x3d,0xf8,0xd2,0xbb, 0x32,0x11,0xae,0xf9, 0xa1,0x6d,0xc7,0x29,
+ 0x2f,0x4b,0x1d,0x9e, 0x30,0xf3,0xdc,0xb2, 0x52,0xec,0x0d,0x86, 0xe3,0xd0,0x77,0xc1,
+ 0x16,0x6c,0x2b,0xb3, 0xb9,0x99,0xa9,0x70, 0x48,0xfa,0x11,0x94, 0x64,0x22,0x47,0xe9,
+ 0x8c,0xc4,0xa8,0xfc, 0x3f,0x1a,0xa0,0xf0, 0x2c,0xd8,0x56,0x7d, 0x90,0xef,0x22,0x33,
+ 0x4e,0xc7,0x87,0x49, 0xd1,0xc1,0xd9,0x38, 0xa2,0xfe,0x8c,0xca, 0x0b,0x36,0x98,0xd4,
+ 0x81,0xcf,0xa6,0xf5, 0xde,0x28,0xa5,0x7a, 0x8e,0x26,0xda,0xb7, 0xbf,0xa4,0x3f,0xad,
+ 0x9d,0xe4,0x2c,0x3a, 0x92,0x0d,0x50,0x78, 0xcc,0x9b,0x6a,0x5f, 0x46,0x62,0x54,0x7e,
+ 0x13,0xc2,0xf6,0x8d, 0xb8,0xe8,0x90,0xd8, 0xf7,0x5e,0x2e,0x39, 0xaf,0xf5,0x82,0xc3,
+ 0x80,0xbe,0x9f,0x5d, 0x93,0x7c,0x69,0xd0, 0x2d,0xa9,0x6f,0xd5, 0x12,0xb3,0xcf,0x25,
+ 0x99,0x3b,0xc8,0xac, 0x7d,0xa7,0x10,0x18, 0x63,0x6e,0xe8,0x9c, 0xbb,0x7b,0xdb,0x3b,
+ 0x78,0x09,0xcd,0x26, 0x18,0xf4,0x6e,0x59, 0xb7,0x01,0xec,0x9a, 0x9a,0xa8,0x83,0x4f,
+ 0x6e,0x65,0xe6,0x95, 0xe6,0x7e,0xaa,0xff, 0xcf,0x08,0x21,0xbc, 0xe8,0xe6,0xef,0x15,
+ 0x9b,0xd9,0xba,0xe7, 0x36,0xce,0x4a,0x6f, 0x09,0xd4,0xea,0x9f, 0x7c,0xd6,0x29,0xb0,
+ 0xb2,0xaf,0x31,0xa4, 0x23,0x31,0x2a,0x3f, 0x94,0x30,0xc6,0xa5, 0x66,0xc0,0x35,0xa2,
+ 0xbc,0x37,0x74,0x4e, 0xca,0xa6,0xfc,0x82, 0xd0,0xb0,0xe0,0x90, 0xd8,0x15,0x33,0xa7,
+ 0x98,0x4a,0xf1,0x04, 0xda,0xf7,0x41,0xec, 0x50,0x0e,0x7f,0xcd, 0xf6,0x2f,0x17,0x91,
+ 0xd6,0x8d,0x76,0x4d, 0xb0,0x4d,0x43,0xef, 0x4d,0x54,0xcc,0xaa, 0x04,0xdf,0xe4,0x96,
+ 0xb5,0xe3,0x9e,0xd1, 0x88,0x1b,0x4c,0x6a, 0x1f,0xb8,0xc1,0x2c, 0x51,0x7f,0x46,0x65,
+ 0xea,0x04,0x9d,0x5e, 0x35,0x5d,0x01,0x8c, 0x74,0x73,0xfa,0x87, 0x41,0x2e,0xfb,0x0b,
+ 0x1d,0x5a,0xb3,0x67, 0xd2,0x52,0x92,0xdb, 0x56,0x33,0xe9,0x10, 0x47,0x13,0x6d,0xd6,
+ 0x61,0x8c,0x9a,0xd7, 0x0c,0x7a,0x37,0xa1, 0x14,0x8e,0x59,0xf8, 0x3c,0x89,0xeb,0x13,
+ 0x27,0xee,0xce,0xa9, 0xc9,0x35,0xb7,0x61, 0xe5,0xed,0xe1,0x1c, 0xb1,0x3c,0x7a,0x47,
+ 0xdf,0x59,0x9c,0xd2, 0x73,0x3f,0x55,0xf2, 0xce,0x79,0x18,0x14, 0x37,0xbf,0x73,0xc7,
+ 0xcd,0xea,0x53,0xf7, 0xaa,0x5b,0x5f,0xfd, 0x6f,0x14,0xdf,0x3d, 0xdb,0x86,0x78,0x44,
+ 0xf3,0x81,0xca,0xaf, 0xc4,0x3e,0xb9,0x68, 0x34,0x2c,0x38,0x24, 0x40,0x5f,0xc2,0xa3,
+ 0xc3,0x72,0x16,0x1d, 0x25,0x0c,0xbc,0xe2, 0x49,0x8b,0x28,0x3c, 0x95,0x41,0xff,0x0d,
+ 0x01,0x71,0x39,0xa8, 0xb3,0xde,0x08,0x0c, 0xe4,0x9c,0xd8,0xb4, 0xc1,0x90,0x64,0x56,
+ 0x84,0x61,0x7b,0xcb, 0xb6,0x70,0xd5,0x32, 0x5c,0x74,0x48,0x6c, 0x57,0x42,0xd0,0xb8
+};
+
+static uint8_t T8[256][4]=
+{
+ 0xf4,0xa7,0x50,0x51, 0x41,0x65,0x53,0x7e, 0x17,0xa4,0xc3,0x1a, 0x27,0x5e,0x96,0x3a,
+ 0xab,0x6b,0xcb,0x3b, 0x9d,0x45,0xf1,0x1f, 0xfa,0x58,0xab,0xac, 0xe3,0x03,0x93,0x4b,
+ 0x30,0xfa,0x55,0x20, 0x76,0x6d,0xf6,0xad, 0xcc,0x76,0x91,0x88, 0x02,0x4c,0x25,0xf5,
+ 0xe5,0xd7,0xfc,0x4f, 0x2a,0xcb,0xd7,0xc5, 0x35,0x44,0x80,0x26, 0x62,0xa3,0x8f,0xb5,
+ 0xb1,0x5a,0x49,0xde, 0xba,0x1b,0x67,0x25, 0xea,0x0e,0x98,0x45, 0xfe,0xc0,0xe1,0x5d,
+ 0x2f,0x75,0x02,0xc3, 0x4c,0xf0,0x12,0x81, 0x46,0x97,0xa3,0x8d, 0xd3,0xf9,0xc6,0x6b,
+ 0x8f,0x5f,0xe7,0x03, 0x92,0x9c,0x95,0x15, 0x6d,0x7a,0xeb,0xbf, 0x52,0x59,0xda,0x95,
+ 0xbe,0x83,0x2d,0xd4, 0x74,0x21,0xd3,0x58, 0xe0,0x69,0x29,0x49, 0xc9,0xc8,0x44,0x8e,
+ 0xc2,0x89,0x6a,0x75, 0x8e,0x79,0x78,0xf4, 0x58,0x3e,0x6b,0x99, 0xb9,0x71,0xdd,0x27,
+ 0xe1,0x4f,0xb6,0xbe, 0x88,0xad,0x17,0xf0, 0x20,0xac,0x66,0xc9, 0xce,0x3a,0xb4,0x7d,
+ 0xdf,0x4a,0x18,0x63, 0x1a,0x31,0x82,0xe5, 0x51,0x33,0x60,0x97, 0x53,0x7f,0x45,0x62,
+ 0x64,0x77,0xe0,0xb1, 0x6b,0xae,0x84,0xbb, 0x81,0xa0,0x1c,0xfe, 0x08,0x2b,0x94,0xf9,
+ 0x48,0x68,0x58,0x70, 0x45,0xfd,0x19,0x8f, 0xde,0x6c,0x87,0x94, 0x7b,0xf8,0xb7,0x52,
+ 0x73,0xd3,0x23,0xab, 0x4b,0x02,0xe2,0x72, 0x1f,0x8f,0x57,0xe3, 0x55,0xab,0x2a,0x66,
+ 0xeb,0x28,0x07,0xb2, 0xb5,0xc2,0x03,0x2f, 0xc5,0x7b,0x9a,0x86, 0x37,0x08,0xa5,0xd3,
+ 0x28,0x87,0xf2,0x30, 0xbf,0xa5,0xb2,0x23, 0x03,0x6a,0xba,0x02, 0x16,0x82,0x5c,0xed,
+ 0xcf,0x1c,0x2b,0x8a, 0x79,0xb4,0x92,0xa7, 0x07,0xf2,0xf0,0xf3, 0x69,0xe2,0xa1,0x4e,
+ 0xda,0xf4,0xcd,0x65, 0x05,0xbe,0xd5,0x06, 0x34,0x62,0x1f,0xd1, 0xa6,0xfe,0x8a,0xc4,
+ 0x2e,0x53,0x9d,0x34, 0xf3,0x55,0xa0,0xa2, 0x8a,0xe1,0x32,0x05, 0xf6,0xeb,0x75,0xa4,
+ 0x83,0xec,0x39,0x0b, 0x60,0xef,0xaa,0x40, 0x71,0x9f,0x06,0x5e, 0x6e,0x10,0x51,0xbd,
+ 0x21,0x8a,0xf9,0x3e, 0xdd,0x06,0x3d,0x96, 0x3e,0x05,0xae,0xdd, 0xe6,0xbd,0x46,0x4d,
+ 0x54,0x8d,0xb5,0x91, 0xc4,0x5d,0x05,0x71, 0x06,0xd4,0x6f,0x04, 0x50,0x15,0xff,0x60,
+ 0x98,0xfb,0x24,0x19, 0xbd,0xe9,0x97,0xd6, 0x40,0x43,0xcc,0x89, 0xd9,0x9e,0x77,0x67,
+ 0xe8,0x42,0xbd,0xb0, 0x89,0x8b,0x88,0x07, 0x19,0x5b,0x38,0xe7, 0xc8,0xee,0xdb,0x79,
+ 0x7c,0x0a,0x47,0xa1, 0x42,0x0f,0xe9,0x7c, 0x84,0x1e,0xc9,0xf8, 0x00,0x00,0x00,0x00,
+ 0x80,0x86,0x83,0x09, 0x2b,0xed,0x48,0x32, 0x11,0x70,0xac,0x1e, 0x5a,0x72,0x4e,0x6c,
+ 0x0e,0xff,0xfb,0xfd, 0x85,0x38,0x56,0x0f, 0xae,0xd5,0x1e,0x3d, 0x2d,0x39,0x27,0x36,
+ 0x0f,0xd9,0x64,0x0a, 0x5c,0xa6,0x21,0x68, 0x5b,0x54,0xd1,0x9b, 0x36,0x2e,0x3a,0x24,
+ 0x0a,0x67,0xb1,0x0c, 0x57,0xe7,0x0f,0x93, 0xee,0x96,0xd2,0xb4, 0x9b,0x91,0x9e,0x1b,
+ 0xc0,0xc5,0x4f,0x80, 0xdc,0x20,0xa2,0x61, 0x77,0x4b,0x69,0x5a, 0x12,0x1a,0x16,0x1c,
+ 0x93,0xba,0x0a,0xe2, 0xa0,0x2a,0xe5,0xc0, 0x22,0xe0,0x43,0x3c, 0x1b,0x17,0x1d,0x12,
+ 0x09,0x0d,0x0b,0x0e, 0x8b,0xc7,0xad,0xf2, 0xb6,0xa8,0xb9,0x2d, 0x1e,0xa9,0xc8,0x14,
+ 0xf1,0x19,0x85,0x57, 0x75,0x07,0x4c,0xaf, 0x99,0xdd,0xbb,0xee, 0x7f,0x60,0xfd,0xa3,
+ 0x01,0x26,0x9f,0xf7, 0x72,0xf5,0xbc,0x5c, 0x66,0x3b,0xc5,0x44, 0xfb,0x7e,0x34,0x5b,
+ 0x43,0x29,0x76,0x8b, 0x23,0xc6,0xdc,0xcb, 0xed,0xfc,0x68,0xb6, 0xe4,0xf1,0x63,0xb8,
+ 0x31,0xdc,0xca,0xd7, 0x63,0x85,0x10,0x42, 0x97,0x22,0x40,0x13, 0xc6,0x11,0x20,0x84,
+ 0x4a,0x24,0x7d,0x85, 0xbb,0x3d,0xf8,0xd2, 0xf9,0x32,0x11,0xae, 0x29,0xa1,0x6d,0xc7,
+ 0x9e,0x2f,0x4b,0x1d, 0xb2,0x30,0xf3,0xdc, 0x86,0x52,0xec,0x0d, 0xc1,0xe3,0xd0,0x77,
+ 0xb3,0x16,0x6c,0x2b, 0x70,0xb9,0x99,0xa9, 0x94,0x48,0xfa,0x11, 0xe9,0x64,0x22,0x47,
+ 0xfc,0x8c,0xc4,0xa8, 0xf0,0x3f,0x1a,0xa0, 0x7d,0x2c,0xd8,0x56, 0x33,0x90,0xef,0x22,
+ 0x49,0x4e,0xc7,0x87, 0x38,0xd1,0xc1,0xd9, 0xca,0xa2,0xfe,0x8c, 0xd4,0x0b,0x36,0x98,
+ 0xf5,0x81,0xcf,0xa6, 0x7a,0xde,0x28,0xa5, 0xb7,0x8e,0x26,0xda, 0xad,0xbf,0xa4,0x3f,
+ 0x3a,0x9d,0xe4,0x2c, 0x78,0x92,0x0d,0x50, 0x5f,0xcc,0x9b,0x6a, 0x7e,0x46,0x62,0x54,
+ 0x8d,0x13,0xc2,0xf6, 0xd8,0xb8,0xe8,0x90, 0x39,0xf7,0x5e,0x2e, 0xc3,0xaf,0xf5,0x82,
+ 0x5d,0x80,0xbe,0x9f, 0xd0,0x93,0x7c,0x69, 0xd5,0x2d,0xa9,0x6f, 0x25,0x12,0xb3,0xcf,
+ 0xac,0x99,0x3b,0xc8, 0x18,0x7d,0xa7,0x10, 0x9c,0x63,0x6e,0xe8, 0x3b,0xbb,0x7b,0xdb,
+ 0x26,0x78,0x09,0xcd, 0x59,0x18,0xf4,0x6e, 0x9a,0xb7,0x01,0xec, 0x4f,0x9a,0xa8,0x83,
+ 0x95,0x6e,0x65,0xe6, 0xff,0xe6,0x7e,0xaa, 0xbc,0xcf,0x08,0x21, 0x15,0xe8,0xe6,0xef,
+ 0xe7,0x9b,0xd9,0xba, 0x6f,0x36,0xce,0x4a, 0x9f,0x09,0xd4,0xea, 0xb0,0x7c,0xd6,0x29,
+ 0xa4,0xb2,0xaf,0x31, 0x3f,0x23,0x31,0x2a, 0xa5,0x94,0x30,0xc6, 0xa2,0x66,0xc0,0x35,
+ 0x4e,0xbc,0x37,0x74, 0x82,0xca,0xa6,0xfc, 0x90,0xd0,0xb0,0xe0, 0xa7,0xd8,0x15,0x33,
+ 0x04,0x98,0x4a,0xf1, 0xec,0xda,0xf7,0x41, 0xcd,0x50,0x0e,0x7f, 0x91,0xf6,0x2f,0x17,
+ 0x4d,0xd6,0x8d,0x76, 0xef,0xb0,0x4d,0x43, 0xaa,0x4d,0x54,0xcc, 0x96,0x04,0xdf,0xe4,
+ 0xd1,0xb5,0xe3,0x9e, 0x6a,0x88,0x1b,0x4c, 0x2c,0x1f,0xb8,0xc1, 0x65,0x51,0x7f,0x46,
+ 0x5e,0xea,0x04,0x9d, 0x8c,0x35,0x5d,0x01, 0x87,0x74,0x73,0xfa, 0x0b,0x41,0x2e,0xfb,
+ 0x67,0x1d,0x5a,0xb3, 0xdb,0xd2,0x52,0x92, 0x10,0x56,0x33,0xe9, 0xd6,0x47,0x13,0x6d,
+ 0xd7,0x61,0x8c,0x9a, 0xa1,0x0c,0x7a,0x37, 0xf8,0x14,0x8e,0x59, 0x13,0x3c,0x89,0xeb,
+ 0xa9,0x27,0xee,0xce, 0x61,0xc9,0x35,0xb7, 0x1c,0xe5,0xed,0xe1, 0x47,0xb1,0x3c,0x7a,
+ 0xd2,0xdf,0x59,0x9c, 0xf2,0x73,0x3f,0x55, 0x14,0xce,0x79,0x18, 0xc7,0x37,0xbf,0x73,
+ 0xf7,0xcd,0xea,0x53, 0xfd,0xaa,0x5b,0x5f, 0x3d,0x6f,0x14,0xdf, 0x44,0xdb,0x86,0x78,
+ 0xaf,0xf3,0x81,0xca, 0x68,0xc4,0x3e,0xb9, 0x24,0x34,0x2c,0x38, 0xa3,0x40,0x5f,0xc2,
+ 0x1d,0xc3,0x72,0x16, 0xe2,0x25,0x0c,0xbc, 0x3c,0x49,0x8b,0x28, 0x0d,0x95,0x41,0xff,
+ 0xa8,0x01,0x71,0x39, 0x0c,0xb3,0xde,0x08, 0xb4,0xe4,0x9c,0xd8, 0x56,0xc1,0x90,0x64,
+ 0xcb,0x84,0x61,0x7b, 0x32,0xb6,0x70,0xd5, 0x6c,0x5c,0x74,0x48, 0xb8,0x57,0x42,0xd0
+};
+
+static uint8_t S5[256]=
+{
+ 0x52,0x09,0x6a,0xd5,
+ 0x30,0x36,0xa5,0x38,
+ 0xbf,0x40,0xa3,0x9e,
+ 0x81,0xf3,0xd7,0xfb,
+ 0x7c,0xe3,0x39,0x82,
+ 0x9b,0x2f,0xff,0x87,
+ 0x34,0x8e,0x43,0x44,
+ 0xc4,0xde,0xe9,0xcb,
+ 0x54,0x7b,0x94,0x32,
+ 0xa6,0xc2,0x23,0x3d,
+ 0xee,0x4c,0x95,0x0b,
+ 0x42,0xfa,0xc3,0x4e,
+ 0x08,0x2e,0xa1,0x66,
+ 0x28,0xd9,0x24,0xb2,
+ 0x76,0x5b,0xa2,0x49,
+ 0x6d,0x8b,0xd1,0x25,
+ 0x72,0xf8,0xf6,0x64,
+ 0x86,0x68,0x98,0x16,
+ 0xd4,0xa4,0x5c,0xcc,
+ 0x5d,0x65,0xb6,0x92,
+ 0x6c,0x70,0x48,0x50,
+ 0xfd,0xed,0xb9,0xda,
+ 0x5e,0x15,0x46,0x57,
+ 0xa7,0x8d,0x9d,0x84,
+ 0x90,0xd8,0xab,0x00,
+ 0x8c,0xbc,0xd3,0x0a,
+ 0xf7,0xe4,0x58,0x05,
+ 0xb8,0xb3,0x45,0x06,
+ 0xd0,0x2c,0x1e,0x8f,
+ 0xca,0x3f,0x0f,0x02,
+ 0xc1,0xaf,0xbd,0x03,
+ 0x01,0x13,0x8a,0x6b,
+ 0x3a,0x91,0x11,0x41,
+ 0x4f,0x67,0xdc,0xea,
+ 0x97,0xf2,0xcf,0xce,
+ 0xf0,0xb4,0xe6,0x73,
+ 0x96,0xac,0x74,0x22,
+ 0xe7,0xad,0x35,0x85,
+ 0xe2,0xf9,0x37,0xe8,
+ 0x1c,0x75,0xdf,0x6e,
+ 0x47,0xf1,0x1a,0x71,
+ 0x1d,0x29,0xc5,0x89,
+ 0x6f,0xb7,0x62,0x0e,
+ 0xaa,0x18,0xbe,0x1b,
+ 0xfc,0x56,0x3e,0x4b,
+ 0xc6,0xd2,0x79,0x20,
+ 0x9a,0xdb,0xc0,0xfe,
+ 0x78,0xcd,0x5a,0xf4,
+ 0x1f,0xdd,0xa8,0x33,
+ 0x88,0x07,0xc7,0x31,
+ 0xb1,0x12,0x10,0x59,
+ 0x27,0x80,0xec,0x5f,
+ 0x60,0x51,0x7f,0xa9,
+ 0x19,0xb5,0x4a,0x0d,
+ 0x2d,0xe5,0x7a,0x9f,
+ 0x93,0xc9,0x9c,0xef,
+ 0xa0,0xe0,0x3b,0x4d,
+ 0xae,0x2a,0xf5,0xb0,
+ 0xc8,0xeb,0xbb,0x3c,
+ 0x83,0x53,0x99,0x61,
+ 0x17,0x2b,0x04,0x7e,
+ 0xba,0x77,0xd6,0x26,
+ 0xe1,0x69,0x14,0x63,
+ 0x55,0x21,0x0c,0x7d
+};
+
+static uint8_t U1[256][4]=
+{
+ 0x00,0x00,0x00,0x00, 0x0e,0x09,0x0d,0x0b, 0x1c,0x12,0x1a,0x16, 0x12,0x1b,0x17,0x1d,
+ 0x38,0x24,0x34,0x2c, 0x36,0x2d,0x39,0x27, 0x24,0x36,0x2e,0x3a, 0x2a,0x3f,0x23,0x31,
+ 0x70,0x48,0x68,0x58, 0x7e,0x41,0x65,0x53, 0x6c,0x5a,0x72,0x4e, 0x62,0x53,0x7f,0x45,
+ 0x48,0x6c,0x5c,0x74, 0x46,0x65,0x51,0x7f, 0x54,0x7e,0x46,0x62, 0x5a,0x77,0x4b,0x69,
+ 0xe0,0x90,0xd0,0xb0, 0xee,0x99,0xdd,0xbb, 0xfc,0x82,0xca,0xa6, 0xf2,0x8b,0xc7,0xad,
+ 0xd8,0xb4,0xe4,0x9c, 0xd6,0xbd,0xe9,0x97, 0xc4,0xa6,0xfe,0x8a, 0xca,0xaf,0xf3,0x81,
+ 0x90,0xd8,0xb8,0xe8, 0x9e,0xd1,0xb5,0xe3, 0x8c,0xca,0xa2,0xfe, 0x82,0xc3,0xaf,0xf5,
+ 0xa8,0xfc,0x8c,0xc4, 0xa6,0xf5,0x81,0xcf, 0xb4,0xee,0x96,0xd2, 0xba,0xe7,0x9b,0xd9,
+ 0xdb,0x3b,0xbb,0x7b, 0xd5,0x32,0xb6,0x70, 0xc7,0x29,0xa1,0x6d, 0xc9,0x20,0xac,0x66,
+ 0xe3,0x1f,0x8f,0x57, 0xed,0x16,0x82,0x5c, 0xff,0x0d,0x95,0x41, 0xf1,0x04,0x98,0x4a,
+ 0xab,0x73,0xd3,0x23, 0xa5,0x7a,0xde,0x28, 0xb7,0x61,0xc9,0x35, 0xb9,0x68,0xc4,0x3e,
+ 0x93,0x57,0xe7,0x0f, 0x9d,0x5e,0xea,0x04, 0x8f,0x45,0xfd,0x19, 0x81,0x4c,0xf0,0x12,
+ 0x3b,0xab,0x6b,0xcb, 0x35,0xa2,0x66,0xc0, 0x27,0xb9,0x71,0xdd, 0x29,0xb0,0x7c,0xd6,
+ 0x03,0x8f,0x5f,0xe7, 0x0d,0x86,0x52,0xec, 0x1f,0x9d,0x45,0xf1, 0x11,0x94,0x48,0xfa,
+ 0x4b,0xe3,0x03,0x93, 0x45,0xea,0x0e,0x98, 0x57,0xf1,0x19,0x85, 0x59,0xf8,0x14,0x8e,
+ 0x73,0xc7,0x37,0xbf, 0x7d,0xce,0x3a,0xb4, 0x6f,0xd5,0x2d,0xa9, 0x61,0xdc,0x20,0xa2,
+ 0xad,0x76,0x6d,0xf6, 0xa3,0x7f,0x60,0xfd, 0xb1,0x64,0x77,0xe0, 0xbf,0x6d,0x7a,0xeb,
+ 0x95,0x52,0x59,0xda, 0x9b,0x5b,0x54,0xd1, 0x89,0x40,0x43,0xcc, 0x87,0x49,0x4e,0xc7,
+ 0xdd,0x3e,0x05,0xae, 0xd3,0x37,0x08,0xa5, 0xc1,0x2c,0x1f,0xb8, 0xcf,0x25,0x12,0xb3,
+ 0xe5,0x1a,0x31,0x82, 0xeb,0x13,0x3c,0x89, 0xf9,0x08,0x2b,0x94, 0xf7,0x01,0x26,0x9f,
+ 0x4d,0xe6,0xbd,0x46, 0x43,0xef,0xb0,0x4d, 0x51,0xf4,0xa7,0x50, 0x5f,0xfd,0xaa,0x5b,
+ 0x75,0xc2,0x89,0x6a, 0x7b,0xcb,0x84,0x61, 0x69,0xd0,0x93,0x7c, 0x67,0xd9,0x9e,0x77,
+ 0x3d,0xae,0xd5,0x1e, 0x33,0xa7,0xd8,0x15, 0x21,0xbc,0xcf,0x08, 0x2f,0xb5,0xc2,0x03,
+ 0x05,0x8a,0xe1,0x32, 0x0b,0x83,0xec,0x39, 0x19,0x98,0xfb,0x24, 0x17,0x91,0xf6,0x2f,
+ 0x76,0x4d,0xd6,0x8d, 0x78,0x44,0xdb,0x86, 0x6a,0x5f,0xcc,0x9b, 0x64,0x56,0xc1,0x90,
+ 0x4e,0x69,0xe2,0xa1, 0x40,0x60,0xef,0xaa, 0x52,0x7b,0xf8,0xb7, 0x5c,0x72,0xf5,0xbc,
+ 0x06,0x05,0xbe,0xd5, 0x08,0x0c,0xb3,0xde, 0x1a,0x17,0xa4,0xc3, 0x14,0x1e,0xa9,0xc8,
+ 0x3e,0x21,0x8a,0xf9, 0x30,0x28,0x87,0xf2, 0x22,0x33,0x90,0xef, 0x2c,0x3a,0x9d,0xe4,
+ 0x96,0xdd,0x06,0x3d, 0x98,0xd4,0x0b,0x36, 0x8a,0xcf,0x1c,0x2b, 0x84,0xc6,0x11,0x20,
+ 0xae,0xf9,0x32,0x11, 0xa0,0xf0,0x3f,0x1a, 0xb2,0xeb,0x28,0x07, 0xbc,0xe2,0x25,0x0c,
+ 0xe6,0x95,0x6e,0x65, 0xe8,0x9c,0x63,0x6e, 0xfa,0x87,0x74,0x73, 0xf4,0x8e,0x79,0x78,
+ 0xde,0xb1,0x5a,0x49, 0xd0,0xb8,0x57,0x42, 0xc2,0xa3,0x40,0x5f, 0xcc,0xaa,0x4d,0x54,
+ 0x41,0xec,0xda,0xf7, 0x4f,0xe5,0xd7,0xfc, 0x5d,0xfe,0xc0,0xe1, 0x53,0xf7,0xcd,0xea,
+ 0x79,0xc8,0xee,0xdb, 0x77,0xc1,0xe3,0xd0, 0x65,0xda,0xf4,0xcd, 0x6b,0xd3,0xf9,0xc6,
+ 0x31,0xa4,0xb2,0xaf, 0x3f,0xad,0xbf,0xa4, 0x2d,0xb6,0xa8,0xb9, 0x23,0xbf,0xa5,0xb2,
+ 0x09,0x80,0x86,0x83, 0x07,0x89,0x8b,0x88, 0x15,0x92,0x9c,0x95, 0x1b,0x9b,0x91,0x9e,
+ 0xa1,0x7c,0x0a,0x47, 0xaf,0x75,0x07,0x4c, 0xbd,0x6e,0x10,0x51, 0xb3,0x67,0x1d,0x5a,
+ 0x99,0x58,0x3e,0x6b, 0x97,0x51,0x33,0x60, 0x85,0x4a,0x24,0x7d, 0x8b,0x43,0x29,0x76,
+ 0xd1,0x34,0x62,0x1f, 0xdf,0x3d,0x6f,0x14, 0xcd,0x26,0x78,0x09, 0xc3,0x2f,0x75,0x02,
+ 0xe9,0x10,0x56,0x33, 0xe7,0x19,0x5b,0x38, 0xf5,0x02,0x4c,0x25, 0xfb,0x0b,0x41,0x2e,
+ 0x9a,0xd7,0x61,0x8c, 0x94,0xde,0x6c,0x87, 0x86,0xc5,0x7b,0x9a, 0x88,0xcc,0x76,0x91,
+ 0xa2,0xf3,0x55,0xa0, 0xac,0xfa,0x58,0xab, 0xbe,0xe1,0x4f,0xb6, 0xb0,0xe8,0x42,0xbd,
+ 0xea,0x9f,0x09,0xd4, 0xe4,0x96,0x04,0xdf, 0xf6,0x8d,0x13,0xc2, 0xf8,0x84,0x1e,0xc9,
+ 0xd2,0xbb,0x3d,0xf8, 0xdc,0xb2,0x30,0xf3, 0xce,0xa9,0x27,0xee, 0xc0,0xa0,0x2a,0xe5,
+ 0x7a,0x47,0xb1,0x3c, 0x74,0x4e,0xbc,0x37, 0x66,0x55,0xab,0x2a, 0x68,0x5c,0xa6,0x21,
+ 0x42,0x63,0x85,0x10, 0x4c,0x6a,0x88,0x1b, 0x5e,0x71,0x9f,0x06, 0x50,0x78,0x92,0x0d,
+ 0x0a,0x0f,0xd9,0x64, 0x04,0x06,0xd4,0x6f, 0x16,0x1d,0xc3,0x72, 0x18,0x14,0xce,0x79,
+ 0x32,0x2b,0xed,0x48, 0x3c,0x22,0xe0,0x43, 0x2e,0x39,0xf7,0x5e, 0x20,0x30,0xfa,0x55,
+ 0xec,0x9a,0xb7,0x01, 0xe2,0x93,0xba,0x0a, 0xf0,0x88,0xad,0x17, 0xfe,0x81,0xa0,0x1c,
+ 0xd4,0xbe,0x83,0x2d, 0xda,0xb7,0x8e,0x26, 0xc8,0xac,0x99,0x3b, 0xc6,0xa5,0x94,0x30,
+ 0x9c,0xd2,0xdf,0x59, 0x92,0xdb,0xd2,0x52, 0x80,0xc0,0xc5,0x4f, 0x8e,0xc9,0xc8,0x44,
+ 0xa4,0xf6,0xeb,0x75, 0xaa,0xff,0xe6,0x7e, 0xb8,0xe4,0xf1,0x63, 0xb6,0xed,0xfc,0x68,
+ 0x0c,0x0a,0x67,0xb1, 0x02,0x03,0x6a,0xba, 0x10,0x18,0x7d,0xa7, 0x1e,0x11,0x70,0xac,
+ 0x34,0x2e,0x53,0x9d, 0x3a,0x27,0x5e,0x96, 0x28,0x3c,0x49,0x8b, 0x26,0x35,0x44,0x80,
+ 0x7c,0x42,0x0f,0xe9, 0x72,0x4b,0x02,0xe2, 0x60,0x50,0x15,0xff, 0x6e,0x59,0x18,0xf4,
+ 0x44,0x66,0x3b,0xc5, 0x4a,0x6f,0x36,0xce, 0x58,0x74,0x21,0xd3, 0x56,0x7d,0x2c,0xd8,
+ 0x37,0xa1,0x0c,0x7a, 0x39,0xa8,0x01,0x71, 0x2b,0xb3,0x16,0x6c, 0x25,0xba,0x1b,0x67,
+ 0x0f,0x85,0x38,0x56, 0x01,0x8c,0x35,0x5d, 0x13,0x97,0x22,0x40, 0x1d,0x9e,0x2f,0x4b,
+ 0x47,0xe9,0x64,0x22, 0x49,0xe0,0x69,0x29, 0x5b,0xfb,0x7e,0x34, 0x55,0xf2,0x73,0x3f,
+ 0x7f,0xcd,0x50,0x0e, 0x71,0xc4,0x5d,0x05, 0x63,0xdf,0x4a,0x18, 0x6d,0xd6,0x47,0x13,
+ 0xd7,0x31,0xdc,0xca, 0xd9,0x38,0xd1,0xc1, 0xcb,0x23,0xc6,0xdc, 0xc5,0x2a,0xcb,0xd7,
+ 0xef,0x15,0xe8,0xe6, 0xe1,0x1c,0xe5,0xed, 0xf3,0x07,0xf2,0xf0, 0xfd,0x0e,0xff,0xfb,
+ 0xa7,0x79,0xb4,0x92, 0xa9,0x70,0xb9,0x99, 0xbb,0x6b,0xae,0x84, 0xb5,0x62,0xa3,0x8f,
+ 0x9f,0x5d,0x80,0xbe, 0x91,0x54,0x8d,0xb5, 0x83,0x4f,0x9a,0xa8, 0x8d,0x46,0x97,0xa3
+};
+
+static uint8_t U2[256][4]=
+{
+ 0x00,0x00,0x00,0x00, 0x0b,0x0e,0x09,0x0d, 0x16,0x1c,0x12,0x1a, 0x1d,0x12,0x1b,0x17,
+ 0x2c,0x38,0x24,0x34, 0x27,0x36,0x2d,0x39, 0x3a,0x24,0x36,0x2e, 0x31,0x2a,0x3f,0x23,
+ 0x58,0x70,0x48,0x68, 0x53,0x7e,0x41,0x65, 0x4e,0x6c,0x5a,0x72, 0x45,0x62,0x53,0x7f,
+ 0x74,0x48,0x6c,0x5c, 0x7f,0x46,0x65,0x51, 0x62,0x54,0x7e,0x46, 0x69,0x5a,0x77,0x4b,
+ 0xb0,0xe0,0x90,0xd0, 0xbb,0xee,0x99,0xdd, 0xa6,0xfc,0x82,0xca, 0xad,0xf2,0x8b,0xc7,
+ 0x9c,0xd8,0xb4,0xe4, 0x97,0xd6,0xbd,0xe9, 0x8a,0xc4,0xa6,0xfe, 0x81,0xca,0xaf,0xf3,
+ 0xe8,0x90,0xd8,0xb8, 0xe3,0x9e,0xd1,0xb5, 0xfe,0x8c,0xca,0xa2, 0xf5,0x82,0xc3,0xaf,
+ 0xc4,0xa8,0xfc,0x8c, 0xcf,0xa6,0xf5,0x81, 0xd2,0xb4,0xee,0x96, 0xd9,0xba,0xe7,0x9b,
+ 0x7b,0xdb,0x3b,0xbb, 0x70,0xd5,0x32,0xb6, 0x6d,0xc7,0x29,0xa1, 0x66,0xc9,0x20,0xac,
+ 0x57,0xe3,0x1f,0x8f, 0x5c,0xed,0x16,0x82, 0x41,0xff,0x0d,0x95, 0x4a,0xf1,0x04,0x98,
+ 0x23,0xab,0x73,0xd3, 0x28,0xa5,0x7a,0xde, 0x35,0xb7,0x61,0xc9, 0x3e,0xb9,0x68,0xc4,
+ 0x0f,0x93,0x57,0xe7, 0x04,0x9d,0x5e,0xea, 0x19,0x8f,0x45,0xfd, 0x12,0x81,0x4c,0xf0,
+ 0xcb,0x3b,0xab,0x6b, 0xc0,0x35,0xa2,0x66, 0xdd,0x27,0xb9,0x71, 0xd6,0x29,0xb0,0x7c,
+ 0xe7,0x03,0x8f,0x5f, 0xec,0x0d,0x86,0x52, 0xf1,0x1f,0x9d,0x45, 0xfa,0x11,0x94,0x48,
+ 0x93,0x4b,0xe3,0x03, 0x98,0x45,0xea,0x0e, 0x85,0x57,0xf1,0x19, 0x8e,0x59,0xf8,0x14,
+ 0xbf,0x73,0xc7,0x37, 0xb4,0x7d,0xce,0x3a, 0xa9,0x6f,0xd5,0x2d, 0xa2,0x61,0xdc,0x20,
+ 0xf6,0xad,0x76,0x6d, 0xfd,0xa3,0x7f,0x60, 0xe0,0xb1,0x64,0x77, 0xeb,0xbf,0x6d,0x7a,
+ 0xda,0x95,0x52,0x59, 0xd1,0x9b,0x5b,0x54, 0xcc,0x89,0x40,0x43, 0xc7,0x87,0x49,0x4e,
+ 0xae,0xdd,0x3e,0x05, 0xa5,0xd3,0x37,0x08, 0xb8,0xc1,0x2c,0x1f, 0xb3,0xcf,0x25,0x12,
+ 0x82,0xe5,0x1a,0x31, 0x89,0xeb,0x13,0x3c, 0x94,0xf9,0x08,0x2b, 0x9f,0xf7,0x01,0x26,
+ 0x46,0x4d,0xe6,0xbd, 0x4d,0x43,0xef,0xb0, 0x50,0x51,0xf4,0xa7, 0x5b,0x5f,0xfd,0xaa,
+ 0x6a,0x75,0xc2,0x89, 0x61,0x7b,0xcb,0x84, 0x7c,0x69,0xd0,0x93, 0x77,0x67,0xd9,0x9e,
+ 0x1e,0x3d,0xae,0xd5, 0x15,0x33,0xa7,0xd8, 0x08,0x21,0xbc,0xcf, 0x03,0x2f,0xb5,0xc2,
+ 0x32,0x05,0x8a,0xe1, 0x39,0x0b,0x83,0xec, 0x24,0x19,0x98,0xfb, 0x2f,0x17,0x91,0xf6,
+ 0x8d,0x76,0x4d,0xd6, 0x86,0x78,0x44,0xdb, 0x9b,0x6a,0x5f,0xcc, 0x90,0x64,0x56,0xc1,
+ 0xa1,0x4e,0x69,0xe2, 0xaa,0x40,0x60,0xef, 0xb7,0x52,0x7b,0xf8, 0xbc,0x5c,0x72,0xf5,
+ 0xd5,0x06,0x05,0xbe, 0xde,0x08,0x0c,0xb3, 0xc3,0x1a,0x17,0xa4, 0xc8,0x14,0x1e,0xa9,
+ 0xf9,0x3e,0x21,0x8a, 0xf2,0x30,0x28,0x87, 0xef,0x22,0x33,0x90, 0xe4,0x2c,0x3a,0x9d,
+ 0x3d,0x96,0xdd,0x06, 0x36,0x98,0xd4,0x0b, 0x2b,0x8a,0xcf,0x1c, 0x20,0x84,0xc6,0x11,
+ 0x11,0xae,0xf9,0x32, 0x1a,0xa0,0xf0,0x3f, 0x07,0xb2,0xeb,0x28, 0x0c,0xbc,0xe2,0x25,
+ 0x65,0xe6,0x95,0x6e, 0x6e,0xe8,0x9c,0x63, 0x73,0xfa,0x87,0x74, 0x78,0xf4,0x8e,0x79,
+ 0x49,0xde,0xb1,0x5a, 0x42,0xd0,0xb8,0x57, 0x5f,0xc2,0xa3,0x40, 0x54,0xcc,0xaa,0x4d,
+ 0xf7,0x41,0xec,0xda, 0xfc,0x4f,0xe5,0xd7, 0xe1,0x5d,0xfe,0xc0, 0xea,0x53,0xf7,0xcd,
+ 0xdb,0x79,0xc8,0xee, 0xd0,0x77,0xc1,0xe3, 0xcd,0x65,0xda,0xf4, 0xc6,0x6b,0xd3,0xf9,
+ 0xaf,0x31,0xa4,0xb2, 0xa4,0x3f,0xad,0xbf, 0xb9,0x2d,0xb6,0xa8, 0xb2,0x23,0xbf,0xa5,
+ 0x83,0x09,0x80,0x86, 0x88,0x07,0x89,0x8b, 0x95,0x15,0x92,0x9c, 0x9e,0x1b,0x9b,0x91,
+ 0x47,0xa1,0x7c,0x0a, 0x4c,0xaf,0x75,0x07, 0x51,0xbd,0x6e,0x10, 0x5a,0xb3,0x67,0x1d,
+ 0x6b,0x99,0x58,0x3e, 0x60,0x97,0x51,0x33, 0x7d,0x85,0x4a,0x24, 0x76,0x8b,0x43,0x29,
+ 0x1f,0xd1,0x34,0x62, 0x14,0xdf,0x3d,0x6f, 0x09,0xcd,0x26,0x78, 0x02,0xc3,0x2f,0x75,
+ 0x33,0xe9,0x10,0x56, 0x38,0xe7,0x19,0x5b, 0x25,0xf5,0x02,0x4c, 0x2e,0xfb,0x0b,0x41,
+ 0x8c,0x9a,0xd7,0x61, 0x87,0x94,0xde,0x6c, 0x9a,0x86,0xc5,0x7b, 0x91,0x88,0xcc,0x76,
+ 0xa0,0xa2,0xf3,0x55, 0xab,0xac,0xfa,0x58, 0xb6,0xbe,0xe1,0x4f, 0xbd,0xb0,0xe8,0x42,
+ 0xd4,0xea,0x9f,0x09, 0xdf,0xe4,0x96,0x04, 0xc2,0xf6,0x8d,0x13, 0xc9,0xf8,0x84,0x1e,
+ 0xf8,0xd2,0xbb,0x3d, 0xf3,0xdc,0xb2,0x30, 0xee,0xce,0xa9,0x27, 0xe5,0xc0,0xa0,0x2a,
+ 0x3c,0x7a,0x47,0xb1, 0x37,0x74,0x4e,0xbc, 0x2a,0x66,0x55,0xab, 0x21,0x68,0x5c,0xa6,
+ 0x10,0x42,0x63,0x85, 0x1b,0x4c,0x6a,0x88, 0x06,0x5e,0x71,0x9f, 0x0d,0x50,0x78,0x92,
+ 0x64,0x0a,0x0f,0xd9, 0x6f,0x04,0x06,0xd4, 0x72,0x16,0x1d,0xc3, 0x79,0x18,0x14,0xce,
+ 0x48,0x32,0x2b,0xed, 0x43,0x3c,0x22,0xe0, 0x5e,0x2e,0x39,0xf7, 0x55,0x20,0x30,0xfa,
+ 0x01,0xec,0x9a,0xb7, 0x0a,0xe2,0x93,0xba, 0x17,0xf0,0x88,0xad, 0x1c,0xfe,0x81,0xa0,
+ 0x2d,0xd4,0xbe,0x83, 0x26,0xda,0xb7,0x8e, 0x3b,0xc8,0xac,0x99, 0x30,0xc6,0xa5,0x94,
+ 0x59,0x9c,0xd2,0xdf, 0x52,0x92,0xdb,0xd2, 0x4f,0x80,0xc0,0xc5, 0x44,0x8e,0xc9,0xc8,
+ 0x75,0xa4,0xf6,0xeb, 0x7e,0xaa,0xff,0xe6, 0x63,0xb8,0xe4,0xf1, 0x68,0xb6,0xed,0xfc,
+ 0xb1,0x0c,0x0a,0x67, 0xba,0x02,0x03,0x6a, 0xa7,0x10,0x18,0x7d, 0xac,0x1e,0x11,0x70,
+ 0x9d,0x34,0x2e,0x53, 0x96,0x3a,0x27,0x5e, 0x8b,0x28,0x3c,0x49, 0x80,0x26,0x35,0x44,
+ 0xe9,0x7c,0x42,0x0f, 0xe2,0x72,0x4b,0x02, 0xff,0x60,0x50,0x15, 0xf4,0x6e,0x59,0x18,
+ 0xc5,0x44,0x66,0x3b, 0xce,0x4a,0x6f,0x36, 0xd3,0x58,0x74,0x21, 0xd8,0x56,0x7d,0x2c,
+ 0x7a,0x37,0xa1,0x0c, 0x71,0x39,0xa8,0x01, 0x6c,0x2b,0xb3,0x16, 0x67,0x25,0xba,0x1b,
+ 0x56,0x0f,0x85,0x38, 0x5d,0x01,0x8c,0x35, 0x40,0x13,0x97,0x22, 0x4b,0x1d,0x9e,0x2f,
+ 0x22,0x47,0xe9,0x64, 0x29,0x49,0xe0,0x69, 0x34,0x5b,0xfb,0x7e, 0x3f,0x55,0xf2,0x73,
+ 0x0e,0x7f,0xcd,0x50, 0x05,0x71,0xc4,0x5d, 0x18,0x63,0xdf,0x4a, 0x13,0x6d,0xd6,0x47,
+ 0xca,0xd7,0x31,0xdc, 0xc1,0xd9,0x38,0xd1, 0xdc,0xcb,0x23,0xc6, 0xd7,0xc5,0x2a,0xcb,
+ 0xe6,0xef,0x15,0xe8, 0xed,0xe1,0x1c,0xe5, 0xf0,0xf3,0x07,0xf2, 0xfb,0xfd,0x0e,0xff,
+ 0x92,0xa7,0x79,0xb4, 0x99,0xa9,0x70,0xb9, 0x84,0xbb,0x6b,0xae, 0x8f,0xb5,0x62,0xa3,
+ 0xbe,0x9f,0x5d,0x80, 0xb5,0x91,0x54,0x8d, 0xa8,0x83,0x4f,0x9a, 0xa3,0x8d,0x46,0x97
+};
+
+static uint8_t U3[256][4]=
+{
+ 0x00,0x00,0x00,0x00, 0x0d,0x0b,0x0e,0x09, 0x1a,0x16,0x1c,0x12, 0x17,0x1d,0x12,0x1b,
+ 0x34,0x2c,0x38,0x24, 0x39,0x27,0x36,0x2d, 0x2e,0x3a,0x24,0x36, 0x23,0x31,0x2a,0x3f,
+ 0x68,0x58,0x70,0x48, 0x65,0x53,0x7e,0x41, 0x72,0x4e,0x6c,0x5a, 0x7f,0x45,0x62,0x53,
+ 0x5c,0x74,0x48,0x6c, 0x51,0x7f,0x46,0x65, 0x46,0x62,0x54,0x7e, 0x4b,0x69,0x5a,0x77,
+ 0xd0,0xb0,0xe0,0x90, 0xdd,0xbb,0xee,0x99, 0xca,0xa6,0xfc,0x82, 0xc7,0xad,0xf2,0x8b,
+ 0xe4,0x9c,0xd8,0xb4, 0xe9,0x97,0xd6,0xbd, 0xfe,0x8a,0xc4,0xa6, 0xf3,0x81,0xca,0xaf,
+ 0xb8,0xe8,0x90,0xd8, 0xb5,0xe3,0x9e,0xd1, 0xa2,0xfe,0x8c,0xca, 0xaf,0xf5,0x82,0xc3,
+ 0x8c,0xc4,0xa8,0xfc, 0x81,0xcf,0xa6,0xf5, 0x96,0xd2,0xb4,0xee, 0x9b,0xd9,0xba,0xe7,
+ 0xbb,0x7b,0xdb,0x3b, 0xb6,0x70,0xd5,0x32, 0xa1,0x6d,0xc7,0x29, 0xac,0x66,0xc9,0x20,
+ 0x8f,0x57,0xe3,0x1f, 0x82,0x5c,0xed,0x16, 0x95,0x41,0xff,0x0d, 0x98,0x4a,0xf1,0x04,
+ 0xd3,0x23,0xab,0x73, 0xde,0x28,0xa5,0x7a, 0xc9,0x35,0xb7,0x61, 0xc4,0x3e,0xb9,0x68,
+ 0xe7,0x0f,0x93,0x57, 0xea,0x04,0x9d,0x5e, 0xfd,0x19,0x8f,0x45, 0xf0,0x12,0x81,0x4c,
+ 0x6b,0xcb,0x3b,0xab, 0x66,0xc0,0x35,0xa2, 0x71,0xdd,0x27,0xb9, 0x7c,0xd6,0x29,0xb0,
+ 0x5f,0xe7,0x03,0x8f, 0x52,0xec,0x0d,0x86, 0x45,0xf1,0x1f,0x9d, 0x48,0xfa,0x11,0x94,
+ 0x03,0x93,0x4b,0xe3, 0x0e,0x98,0x45,0xea, 0x19,0x85,0x57,0xf1, 0x14,0x8e,0x59,0xf8,
+ 0x37,0xbf,0x73,0xc7, 0x3a,0xb4,0x7d,0xce, 0x2d,0xa9,0x6f,0xd5, 0x20,0xa2,0x61,0xdc,
+ 0x6d,0xf6,0xad,0x76, 0x60,0xfd,0xa3,0x7f, 0x77,0xe0,0xb1,0x64, 0x7a,0xeb,0xbf,0x6d,
+ 0x59,0xda,0x95,0x52, 0x54,0xd1,0x9b,0x5b, 0x43,0xcc,0x89,0x40, 0x4e,0xc7,0x87,0x49,
+ 0x05,0xae,0xdd,0x3e, 0x08,0xa5,0xd3,0x37, 0x1f,0xb8,0xc1,0x2c, 0x12,0xb3,0xcf,0x25,
+ 0x31,0x82,0xe5,0x1a, 0x3c,0x89,0xeb,0x13, 0x2b,0x94,0xf9,0x08, 0x26,0x9f,0xf7,0x01,
+ 0xbd,0x46,0x4d,0xe6, 0xb0,0x4d,0x43,0xef, 0xa7,0x50,0x51,0xf4, 0xaa,0x5b,0x5f,0xfd,
+ 0x89,0x6a,0x75,0xc2, 0x84,0x61,0x7b,0xcb, 0x93,0x7c,0x69,0xd0, 0x9e,0x77,0x67,0xd9,
+ 0xd5,0x1e,0x3d,0xae, 0xd8,0x15,0x33,0xa7, 0xcf,0x08,0x21,0xbc, 0xc2,0x03,0x2f,0xb5,
+ 0xe1,0x32,0x05,0x8a, 0xec,0x39,0x0b,0x83, 0xfb,0x24,0x19,0x98, 0xf6,0x2f,0x17,0x91,
+ 0xd6,0x8d,0x76,0x4d, 0xdb,0x86,0x78,0x44, 0xcc,0x9b,0x6a,0x5f, 0xc1,0x90,0x64,0x56,
+ 0xe2,0xa1,0x4e,0x69, 0xef,0xaa,0x40,0x60, 0xf8,0xb7,0x52,0x7b, 0xf5,0xbc,0x5c,0x72,
+ 0xbe,0xd5,0x06,0x05, 0xb3,0xde,0x08,0x0c, 0xa4,0xc3,0x1a,0x17, 0xa9,0xc8,0x14,0x1e,
+ 0x8a,0xf9,0x3e,0x21, 0x87,0xf2,0x30,0x28, 0x90,0xef,0x22,0x33, 0x9d,0xe4,0x2c,0x3a,
+ 0x06,0x3d,0x96,0xdd, 0x0b,0x36,0x98,0xd4, 0x1c,0x2b,0x8a,0xcf, 0x11,0x20,0x84,0xc6,
+ 0x32,0x11,0xae,0xf9, 0x3f,0x1a,0xa0,0xf0, 0x28,0x07,0xb2,0xeb, 0x25,0x0c,0xbc,0xe2,
+ 0x6e,0x65,0xe6,0x95, 0x63,0x6e,0xe8,0x9c, 0x74,0x73,0xfa,0x87, 0x79,0x78,0xf4,0x8e,
+ 0x5a,0x49,0xde,0xb1, 0x57,0x42,0xd0,0xb8, 0x40,0x5f,0xc2,0xa3, 0x4d,0x54,0xcc,0xaa,
+ 0xda,0xf7,0x41,0xec, 0xd7,0xfc,0x4f,0xe5, 0xc0,0xe1,0x5d,0xfe, 0xcd,0xea,0x53,0xf7,
+ 0xee,0xdb,0x79,0xc8, 0xe3,0xd0,0x77,0xc1, 0xf4,0xcd,0x65,0xda, 0xf9,0xc6,0x6b,0xd3,
+ 0xb2,0xaf,0x31,0xa4, 0xbf,0xa4,0x3f,0xad, 0xa8,0xb9,0x2d,0xb6, 0xa5,0xb2,0x23,0xbf,
+ 0x86,0x83,0x09,0x80, 0x8b,0x88,0x07,0x89, 0x9c,0x95,0x15,0x92, 0x91,0x9e,0x1b,0x9b,
+ 0x0a,0x47,0xa1,0x7c, 0x07,0x4c,0xaf,0x75, 0x10,0x51,0xbd,0x6e, 0x1d,0x5a,0xb3,0x67,
+ 0x3e,0x6b,0x99,0x58, 0x33,0x60,0x97,0x51, 0x24,0x7d,0x85,0x4a, 0x29,0x76,0x8b,0x43,
+ 0x62,0x1f,0xd1,0x34, 0x6f,0x14,0xdf,0x3d, 0x78,0x09,0xcd,0x26, 0x75,0x02,0xc3,0x2f,
+ 0x56,0x33,0xe9,0x10, 0x5b,0x38,0xe7,0x19, 0x4c,0x25,0xf5,0x02, 0x41,0x2e,0xfb,0x0b,
+ 0x61,0x8c,0x9a,0xd7, 0x6c,0x87,0x94,0xde, 0x7b,0x9a,0x86,0xc5, 0x76,0x91,0x88,0xcc,
+ 0x55,0xa0,0xa2,0xf3, 0x58,0xab,0xac,0xfa, 0x4f,0xb6,0xbe,0xe1, 0x42,0xbd,0xb0,0xe8,
+ 0x09,0xd4,0xea,0x9f, 0x04,0xdf,0xe4,0x96, 0x13,0xc2,0xf6,0x8d, 0x1e,0xc9,0xf8,0x84,
+ 0x3d,0xf8,0xd2,0xbb, 0x30,0xf3,0xdc,0xb2, 0x27,0xee,0xce,0xa9, 0x2a,0xe5,0xc0,0xa0,
+ 0xb1,0x3c,0x7a,0x47, 0xbc,0x37,0x74,0x4e, 0xab,0x2a,0x66,0x55, 0xa6,0x21,0x68,0x5c,
+ 0x85,0x10,0x42,0x63, 0x88,0x1b,0x4c,0x6a, 0x9f,0x06,0x5e,0x71, 0x92,0x0d,0x50,0x78,
+ 0xd9,0x64,0x0a,0x0f, 0xd4,0x6f,0x04,0x06, 0xc3,0x72,0x16,0x1d, 0xce,0x79,0x18,0x14,
+ 0xed,0x48,0x32,0x2b, 0xe0,0x43,0x3c,0x22, 0xf7,0x5e,0x2e,0x39, 0xfa,0x55,0x20,0x30,
+ 0xb7,0x01,0xec,0x9a, 0xba,0x0a,0xe2,0x93, 0xad,0x17,0xf0,0x88, 0xa0,0x1c,0xfe,0x81,
+ 0x83,0x2d,0xd4,0xbe, 0x8e,0x26,0xda,0xb7, 0x99,0x3b,0xc8,0xac, 0x94,0x30,0xc6,0xa5,
+ 0xdf,0x59,0x9c,0xd2, 0xd2,0x52,0x92,0xdb, 0xc5,0x4f,0x80,0xc0, 0xc8,0x44,0x8e,0xc9,
+ 0xeb,0x75,0xa4,0xf6, 0xe6,0x7e,0xaa,0xff, 0xf1,0x63,0xb8,0xe4, 0xfc,0x68,0xb6,0xed,
+ 0x67,0xb1,0x0c,0x0a, 0x6a,0xba,0x02,0x03, 0x7d,0xa7,0x10,0x18, 0x70,0xac,0x1e,0x11,
+ 0x53,0x9d,0x34,0x2e, 0x5e,0x96,0x3a,0x27, 0x49,0x8b,0x28,0x3c, 0x44,0x80,0x26,0x35,
+ 0x0f,0xe9,0x7c,0x42, 0x02,0xe2,0x72,0x4b, 0x15,0xff,0x60,0x50, 0x18,0xf4,0x6e,0x59,
+ 0x3b,0xc5,0x44,0x66, 0x36,0xce,0x4a,0x6f, 0x21,0xd3,0x58,0x74, 0x2c,0xd8,0x56,0x7d,
+ 0x0c,0x7a,0x37,0xa1, 0x01,0x71,0x39,0xa8, 0x16,0x6c,0x2b,0xb3, 0x1b,0x67,0x25,0xba,
+ 0x38,0x56,0x0f,0x85, 0x35,0x5d,0x01,0x8c, 0x22,0x40,0x13,0x97, 0x2f,0x4b,0x1d,0x9e,
+ 0x64,0x22,0x47,0xe9, 0x69,0x29,0x49,0xe0, 0x7e,0x34,0x5b,0xfb, 0x73,0x3f,0x55,0xf2,
+ 0x50,0x0e,0x7f,0xcd, 0x5d,0x05,0x71,0xc4, 0x4a,0x18,0x63,0xdf, 0x47,0x13,0x6d,0xd6,
+ 0xdc,0xca,0xd7,0x31, 0xd1,0xc1,0xd9,0x38, 0xc6,0xdc,0xcb,0x23, 0xcb,0xd7,0xc5,0x2a,
+ 0xe8,0xe6,0xef,0x15, 0xe5,0xed,0xe1,0x1c, 0xf2,0xf0,0xf3,0x07, 0xff,0xfb,0xfd,0x0e,
+ 0xb4,0x92,0xa7,0x79, 0xb9,0x99,0xa9,0x70, 0xae,0x84,0xbb,0x6b, 0xa3,0x8f,0xb5,0x62,
+ 0x80,0xbe,0x9f,0x5d, 0x8d,0xb5,0x91,0x54, 0x9a,0xa8,0x83,0x4f, 0x97,0xa3,0x8d,0x46
+};
+
+static uint8_t U4[256][4]=
+{
+ 0x00,0x00,0x00,0x00, 0x09,0x0d,0x0b,0x0e, 0x12,0x1a,0x16,0x1c, 0x1b,0x17,0x1d,0x12,
+ 0x24,0x34,0x2c,0x38, 0x2d,0x39,0x27,0x36, 0x36,0x2e,0x3a,0x24, 0x3f,0x23,0x31,0x2a,
+ 0x48,0x68,0x58,0x70, 0x41,0x65,0x53,0x7e, 0x5a,0x72,0x4e,0x6c, 0x53,0x7f,0x45,0x62,
+ 0x6c,0x5c,0x74,0x48, 0x65,0x51,0x7f,0x46, 0x7e,0x46,0x62,0x54, 0x77,0x4b,0x69,0x5a,
+ 0x90,0xd0,0xb0,0xe0, 0x99,0xdd,0xbb,0xee, 0x82,0xca,0xa6,0xfc, 0x8b,0xc7,0xad,0xf2,
+ 0xb4,0xe4,0x9c,0xd8, 0xbd,0xe9,0x97,0xd6, 0xa6,0xfe,0x8a,0xc4, 0xaf,0xf3,0x81,0xca,
+ 0xd8,0xb8,0xe8,0x90, 0xd1,0xb5,0xe3,0x9e, 0xca,0xa2,0xfe,0x8c, 0xc3,0xaf,0xf5,0x82,
+ 0xfc,0x8c,0xc4,0xa8, 0xf5,0x81,0xcf,0xa6, 0xee,0x96,0xd2,0xb4, 0xe7,0x9b,0xd9,0xba,
+ 0x3b,0xbb,0x7b,0xdb, 0x32,0xb6,0x70,0xd5, 0x29,0xa1,0x6d,0xc7, 0x20,0xac,0x66,0xc9,
+ 0x1f,0x8f,0x57,0xe3, 0x16,0x82,0x5c,0xed, 0x0d,0x95,0x41,0xff, 0x04,0x98,0x4a,0xf1,
+ 0x73,0xd3,0x23,0xab, 0x7a,0xde,0x28,0xa5, 0x61,0xc9,0x35,0xb7, 0x68,0xc4,0x3e,0xb9,
+ 0x57,0xe7,0x0f,0x93, 0x5e,0xea,0x04,0x9d, 0x45,0xfd,0x19,0x8f, 0x4c,0xf0,0x12,0x81,
+ 0xab,0x6b,0xcb,0x3b, 0xa2,0x66,0xc0,0x35, 0xb9,0x71,0xdd,0x27, 0xb0,0x7c,0xd6,0x29,
+ 0x8f,0x5f,0xe7,0x03, 0x86,0x52,0xec,0x0d, 0x9d,0x45,0xf1,0x1f, 0x94,0x48,0xfa,0x11,
+ 0xe3,0x03,0x93,0x4b, 0xea,0x0e,0x98,0x45, 0xf1,0x19,0x85,0x57, 0xf8,0x14,0x8e,0x59,
+ 0xc7,0x37,0xbf,0x73, 0xce,0x3a,0xb4,0x7d, 0xd5,0x2d,0xa9,0x6f, 0xdc,0x20,0xa2,0x61,
+ 0x76,0x6d,0xf6,0xad, 0x7f,0x60,0xfd,0xa3, 0x64,0x77,0xe0,0xb1, 0x6d,0x7a,0xeb,0xbf,
+ 0x52,0x59,0xda,0x95, 0x5b,0x54,0xd1,0x9b, 0x40,0x43,0xcc,0x89, 0x49,0x4e,0xc7,0x87,
+ 0x3e,0x05,0xae,0xdd, 0x37,0x08,0xa5,0xd3, 0x2c,0x1f,0xb8,0xc1, 0x25,0x12,0xb3,0xcf,
+ 0x1a,0x31,0x82,0xe5, 0x13,0x3c,0x89,0xeb, 0x08,0x2b,0x94,0xf9, 0x01,0x26,0x9f,0xf7,
+ 0xe6,0xbd,0x46,0x4d, 0xef,0xb0,0x4d,0x43, 0xf4,0xa7,0x50,0x51, 0xfd,0xaa,0x5b,0x5f,
+ 0xc2,0x89,0x6a,0x75, 0xcb,0x84,0x61,0x7b, 0xd0,0x93,0x7c,0x69, 0xd9,0x9e,0x77,0x67,
+ 0xae,0xd5,0x1e,0x3d, 0xa7,0xd8,0x15,0x33, 0xbc,0xcf,0x08,0x21, 0xb5,0xc2,0x03,0x2f,
+ 0x8a,0xe1,0x32,0x05, 0x83,0xec,0x39,0x0b, 0x98,0xfb,0x24,0x19, 0x91,0xf6,0x2f,0x17,
+ 0x4d,0xd6,0x8d,0x76, 0x44,0xdb,0x86,0x78, 0x5f,0xcc,0x9b,0x6a, 0x56,0xc1,0x90,0x64,
+ 0x69,0xe2,0xa1,0x4e, 0x60,0xef,0xaa,0x40, 0x7b,0xf8,0xb7,0x52, 0x72,0xf5,0xbc,0x5c,
+ 0x05,0xbe,0xd5,0x06, 0x0c,0xb3,0xde,0x08, 0x17,0xa4,0xc3,0x1a, 0x1e,0xa9,0xc8,0x14,
+ 0x21,0x8a,0xf9,0x3e, 0x28,0x87,0xf2,0x30, 0x33,0x90,0xef,0x22, 0x3a,0x9d,0xe4,0x2c,
+ 0xdd,0x06,0x3d,0x96, 0xd4,0x0b,0x36,0x98, 0xcf,0x1c,0x2b,0x8a, 0xc6,0x11,0x20,0x84,
+ 0xf9,0x32,0x11,0xae, 0xf0,0x3f,0x1a,0xa0, 0xeb,0x28,0x07,0xb2, 0xe2,0x25,0x0c,0xbc,
+ 0x95,0x6e,0x65,0xe6, 0x9c,0x63,0x6e,0xe8, 0x87,0x74,0x73,0xfa, 0x8e,0x79,0x78,0xf4,
+ 0xb1,0x5a,0x49,0xde, 0xb8,0x57,0x42,0xd0, 0xa3,0x40,0x5f,0xc2, 0xaa,0x4d,0x54,0xcc,
+ 0xec,0xda,0xf7,0x41, 0xe5,0xd7,0xfc,0x4f, 0xfe,0xc0,0xe1,0x5d, 0xf7,0xcd,0xea,0x53,
+ 0xc8,0xee,0xdb,0x79, 0xc1,0xe3,0xd0,0x77, 0xda,0xf4,0xcd,0x65, 0xd3,0xf9,0xc6,0x6b,
+ 0xa4,0xb2,0xaf,0x31, 0xad,0xbf,0xa4,0x3f, 0xb6,0xa8,0xb9,0x2d, 0xbf,0xa5,0xb2,0x23,
+ 0x80,0x86,0x83,0x09, 0x89,0x8b,0x88,0x07, 0x92,0x9c,0x95,0x15, 0x9b,0x91,0x9e,0x1b,
+ 0x7c,0x0a,0x47,0xa1, 0x75,0x07,0x4c,0xaf, 0x6e,0x10,0x51,0xbd, 0x67,0x1d,0x5a,0xb3,
+ 0x58,0x3e,0x6b,0x99, 0x51,0x33,0x60,0x97, 0x4a,0x24,0x7d,0x85, 0x43,0x29,0x76,0x8b,
+ 0x34,0x62,0x1f,0xd1, 0x3d,0x6f,0x14,0xdf, 0x26,0x78,0x09,0xcd, 0x2f,0x75,0x02,0xc3,
+ 0x10,0x56,0x33,0xe9, 0x19,0x5b,0x38,0xe7, 0x02,0x4c,0x25,0xf5, 0x0b,0x41,0x2e,0xfb,
+ 0xd7,0x61,0x8c,0x9a, 0xde,0x6c,0x87,0x94, 0xc5,0x7b,0x9a,0x86, 0xcc,0x76,0x91,0x88,
+ 0xf3,0x55,0xa0,0xa2, 0xfa,0x58,0xab,0xac, 0xe1,0x4f,0xb6,0xbe, 0xe8,0x42,0xbd,0xb0,
+ 0x9f,0x09,0xd4,0xea, 0x96,0x04,0xdf,0xe4, 0x8d,0x13,0xc2,0xf6, 0x84,0x1e,0xc9,0xf8,
+ 0xbb,0x3d,0xf8,0xd2, 0xb2,0x30,0xf3,0xdc, 0xa9,0x27,0xee,0xce, 0xa0,0x2a,0xe5,0xc0,
+ 0x47,0xb1,0x3c,0x7a, 0x4e,0xbc,0x37,0x74, 0x55,0xab,0x2a,0x66, 0x5c,0xa6,0x21,0x68,
+ 0x63,0x85,0x10,0x42, 0x6a,0x88,0x1b,0x4c, 0x71,0x9f,0x06,0x5e, 0x78,0x92,0x0d,0x50,
+ 0x0f,0xd9,0x64,0x0a, 0x06,0xd4,0x6f,0x04, 0x1d,0xc3,0x72,0x16, 0x14,0xce,0x79,0x18,
+ 0x2b,0xed,0x48,0x32, 0x22,0xe0,0x43,0x3c, 0x39,0xf7,0x5e,0x2e, 0x30,0xfa,0x55,0x20,
+ 0x9a,0xb7,0x01,0xec, 0x93,0xba,0x0a,0xe2, 0x88,0xad,0x17,0xf0, 0x81,0xa0,0x1c,0xfe,
+ 0xbe,0x83,0x2d,0xd4, 0xb7,0x8e,0x26,0xda, 0xac,0x99,0x3b,0xc8, 0xa5,0x94,0x30,0xc6,
+ 0xd2,0xdf,0x59,0x9c, 0xdb,0xd2,0x52,0x92, 0xc0,0xc5,0x4f,0x80, 0xc9,0xc8,0x44,0x8e,
+ 0xf6,0xeb,0x75,0xa4, 0xff,0xe6,0x7e,0xaa, 0xe4,0xf1,0x63,0xb8, 0xed,0xfc,0x68,0xb6,
+ 0x0a,0x67,0xb1,0x0c, 0x03,0x6a,0xba,0x02, 0x18,0x7d,0xa7,0x10, 0x11,0x70,0xac,0x1e,
+ 0x2e,0x53,0x9d,0x34, 0x27,0x5e,0x96,0x3a, 0x3c,0x49,0x8b,0x28, 0x35,0x44,0x80,0x26,
+ 0x42,0x0f,0xe9,0x7c, 0x4b,0x02,0xe2,0x72, 0x50,0x15,0xff,0x60, 0x59,0x18,0xf4,0x6e,
+ 0x66,0x3b,0xc5,0x44, 0x6f,0x36,0xce,0x4a, 0x74,0x21,0xd3,0x58, 0x7d,0x2c,0xd8,0x56,
+ 0xa1,0x0c,0x7a,0x37, 0xa8,0x01,0x71,0x39, 0xb3,0x16,0x6c,0x2b, 0xba,0x1b,0x67,0x25,
+ 0x85,0x38,0x56,0x0f, 0x8c,0x35,0x5d,0x01, 0x97,0x22,0x40,0x13, 0x9e,0x2f,0x4b,0x1d,
+ 0xe9,0x64,0x22,0x47, 0xe0,0x69,0x29,0x49, 0xfb,0x7e,0x34,0x5b, 0xf2,0x73,0x3f,0x55,
+ 0xcd,0x50,0x0e,0x7f, 0xc4,0x5d,0x05,0x71, 0xdf,0x4a,0x18,0x63, 0xd6,0x47,0x13,0x6d,
+ 0x31,0xdc,0xca,0xd7, 0x38,0xd1,0xc1,0xd9, 0x23,0xc6,0xdc,0xcb, 0x2a,0xcb,0xd7,0xc5,
+ 0x15,0xe8,0xe6,0xef, 0x1c,0xe5,0xed,0xe1, 0x07,0xf2,0xf0,0xf3, 0x0e,0xff,0xfb,0xfd,
+ 0x79,0xb4,0x92,0xa7, 0x70,0xb9,0x99,0xa9, 0x6b,0xae,0x84,0xbb, 0x62,0xa3,0x8f,0xb5,
+ 0x5d,0x80,0xbe,0x9f, 0x54,0x8d,0xb5,0x91, 0x4f,0x9a,0xa8,0x83, 0x46,0x97,0xa3,0x8d
+};
+
+static uint32_t rcon[30]=
+{
+ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20,
+ 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8,
+ 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc,
+ 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4,
+ 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91
+};
+
+
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// API
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+Rijndael::Rijndael()
+{
+ m_state = Invalid;
+}
+
+Rijndael::~Rijndael()
+{
+ // nothing here
+}
+
+int Rijndael::init(Mode mode,Direction dir,const uint8_t * key,KeyLength keyLen,uint8_t * initVector)
+{
+ // Not initialized yet
+ m_state = Invalid;
+
+ // Check the mode
+ if((mode != CBC) && (mode != ECB) && (mode != CFB1))return RIJNDAEL_UNSUPPORTED_MODE;
+ m_mode = mode;
+
+ // And the direction
+ if((dir != Encrypt) && (dir != Decrypt))return RIJNDAEL_UNSUPPORTED_DIRECTION;
+ m_direction = dir;
+
+ // Allow to set an init vector
+ if(initVector)
+ {
+ // specified init vector
+ for(int i = 0;i < MAX_IV_SIZE;i++)
+ {
+ m_initVector[i] = initVector[i];
+ }
+ } else {
+ // zero init vector
+ for(int i = 0;i < MAX_IV_SIZE;i++)
+ {
+ m_initVector[i] = 0;
+ }
+ }
+
+ uint32_t uKeyLenInBytes;
+
+ // And check the key length
+ switch(keyLen)
+ {
+ case Key16Bytes:
+ uKeyLenInBytes = 16;
+ m_uRounds = 10;
+ break;
+ case Key24Bytes:
+ uKeyLenInBytes = 24;
+ m_uRounds = 12;
+ break;
+ case Key32Bytes:
+ uKeyLenInBytes = 32;
+ m_uRounds = 14;
+ break;
+ default:
+ return RIJNDAEL_UNSUPPORTED_KEY_LENGTH;
+ break;
+ }
+ // The number of rounds is calculated as
+ // m_uRounds = (m_uKeyLenInBits / 32) + 6;
+
+ if(!key)return RIJNDAEL_BAD_KEY;
+
+ uint8_t keyMatrix[_MAX_KEY_COLUMNS][4];
+
+ for(uint32_t i = 0;i < uKeyLenInBytes;i++)keyMatrix[i >> 2][i & 3] = key[i];
+
+ keySched(keyMatrix);
+
+ if(m_direction == Decrypt)keyEncToDec();
+
+ m_state = Valid;
+
+ return RIJNDAEL_SUCCESS;
+}
+
+int Rijndael::blockEncrypt(const uint8_t *input,int inputLen,uint8_t *outBuffer)
+{
+ int i, k, numBlocks;
+ uint8_t block[16], iv[4][4];
+
+ if(m_state != Valid)return RIJNDAEL_NOT_INITIALIZED;
+ if(m_direction != Encrypt)return RIJNDAEL_BAD_DIRECTION;
+
+ if(input == 0 || inputLen <= 0)return 0;
+
+ numBlocks = inputLen/128;
+
+ switch(m_mode){
+ case ECB:
+ for(i = numBlocks;i > 0;i--)
+ {
+ encrypt(input,outBuffer);
+ input += 16;
+ outBuffer += 16;
+ }
+ break;
+ case CBC:
+ ((uint32_t*)block)[0] = ((uint32_t*)m_initVector)[0] ^ ((uint32_t*)input)[0];
+ ((uint32_t*)block)[1] = ((uint32_t*)m_initVector)[1] ^ ((uint32_t*)input)[1];
+ ((uint32_t*)block)[2] = ((uint32_t*)m_initVector)[2] ^ ((uint32_t*)input)[2];
+ ((uint32_t*)block)[3] = ((uint32_t*)m_initVector)[3] ^ ((uint32_t*)input)[3];
+ encrypt(block,outBuffer);
+ input += 16;
+ for(i = numBlocks - 1;i > 0;i--)
+ {
+ ((uint32_t*)block)[0] = ((uint32_t*)outBuffer)[0] ^ ((uint32_t*)input)[0];
+ ((uint32_t*)block)[1] = ((uint32_t*)outBuffer)[1] ^ ((uint32_t*)input)[1];
+ ((uint32_t*)block)[2] = ((uint32_t*)outBuffer)[2] ^ ((uint32_t*)input)[2];
+ ((uint32_t*)block)[3] = ((uint32_t*)outBuffer)[3] ^ ((uint32_t*)input)[3];
+ outBuffer += 16;
+ encrypt(block,outBuffer);
+ input += 16;
+ }
+ break;
+ case CFB1:
+#if STRICT_ALIGN
+ memcpy(iv,m_initVector,16);
+#else /* !STRICT_ALIGN */
+ *((uint32_t*)iv[0]) = *((uint32_t*)(m_initVector ));
+ *((uint32_t*)iv[1]) = *((uint32_t*)(m_initVector + 4));
+ *((uint32_t*)iv[2]) = *((uint32_t*)(m_initVector + 8));
+ *((uint32_t*)iv[3]) = *((uint32_t*)(m_initVector +12));
+#endif /* ?STRICT_ALIGN */
+ for(i = numBlocks; i > 0; i--)
+ {
+ for(k = 0; k < 128; k++)
+ {
+ *((uint32_t*) block ) = *((uint32_t*)iv[0]);
+ *((uint32_t*)(block+ 4)) = *((uint32_t*)iv[1]);
+ *((uint32_t*)(block+ 8)) = *((uint32_t*)iv[2]);
+ *((uint32_t*)(block+12)) = *((uint32_t*)iv[3]);
+ encrypt(block,block);
+ outBuffer[k/8] ^= (block[0] & 0x80) >> (k & 7);
+ iv[0][0] = (iv[0][0] << 1) | (iv[0][1] >> 7);
+ iv[0][1] = (iv[0][1] << 1) | (iv[0][2] >> 7);
+ iv[0][2] = (iv[0][2] << 1) | (iv[0][3] >> 7);
+ iv[0][3] = (iv[0][3] << 1) | (iv[1][0] >> 7);
+ iv[1][0] = (iv[1][0] << 1) | (iv[1][1] >> 7);
+ iv[1][1] = (iv[1][1] << 1) | (iv[1][2] >> 7);
+ iv[1][2] = (iv[1][2] << 1) | (iv[1][3] >> 7);
+ iv[1][3] = (iv[1][3] << 1) | (iv[2][0] >> 7);
+ iv[2][0] = (iv[2][0] << 1) | (iv[2][1] >> 7);
+ iv[2][1] = (iv[2][1] << 1) | (iv[2][2] >> 7);
+ iv[2][2] = (iv[2][2] << 1) | (iv[2][3] >> 7);
+ iv[2][3] = (iv[2][3] << 1) | (iv[3][0] >> 7);
+ iv[3][0] = (iv[3][0] << 1) | (iv[3][1] >> 7);
+ iv[3][1] = (iv[3][1] << 1) | (iv[3][2] >> 7);
+ iv[3][2] = (iv[3][2] << 1) | (iv[3][3] >> 7);
+ iv[3][3] = (iv[3][3] << 1) | (outBuffer[k/8] >> (7-(k&7))) & 1;
+ }
+ }
+ break;
+ default:
+ return -1;
+ break;
+ }
+
+ return 128 * numBlocks;
+}
+
+int Rijndael::padEncrypt(const uint8_t *input, int inputOctets, uint8_t *outBuffer)
+{
+ int i, numBlocks, padLen;
+ uint8_t block[16], *iv;
+
+ if(m_state != Valid)return RIJNDAEL_NOT_INITIALIZED;
+ if(m_direction != Encrypt)return RIJNDAEL_NOT_INITIALIZED;
+
+ if(input == 0 || inputOctets <= 0)return 0;
+
+ numBlocks = inputOctets/16;
+
+ switch(m_mode)
+ {
+ case ECB:
+ for(i = numBlocks; i > 0; i--)
+ {
+ encrypt(input, outBuffer);
+ input += 16;
+ outBuffer += 16;
+ }
+ padLen = 16 - (inputOctets - 16*numBlocks);
+// assert(padLen > 0 && padLen <= 16);
+ memcpy(block, input, 16 - padLen);
+ memset(block + 16 - padLen, padLen, padLen);
+ encrypt(block,outBuffer);
+ break;
+ case CBC:
+ iv = m_initVector;
+ for(i = numBlocks; i > 0; i--)
+ {
+ ((uint32_t*)block)[0] = ((uint32_t*)input)[0] ^ ((uint32_t*)iv)[0];
+ ((uint32_t*)block)[1] = ((uint32_t*)input)[1] ^ ((uint32_t*)iv)[1];
+ ((uint32_t*)block)[2] = ((uint32_t*)input)[2] ^ ((uint32_t*)iv)[2];
+ ((uint32_t*)block)[3] = ((uint32_t*)input)[3] ^ ((uint32_t*)iv)[3];
+ encrypt(block, outBuffer);
+ iv = outBuffer;
+ input += 16;
+ outBuffer += 16;
+ }
+ padLen = 16 - (inputOctets - 16*numBlocks);
+// assert(padLen > 0 && padLen <= 16); // DO SOMETHING HERE ?
+ for (i = 0; i < 16 - padLen; i++) {
+ block[i] = input[i] ^ iv[i];
+ }
+ for (i = 16 - padLen; i < 16; i++) {
+ block[i] = (uint8_t)padLen ^ iv[i];
+ }
+ encrypt(block,outBuffer);
+ break;
+ default:
+ return -1;
+ break;
+ }
+
+ return 16*(numBlocks + 1);
+}
+
+int Rijndael::blockDecrypt(const uint8_t *input, int inputLen, uint8_t *outBuffer)
+{
+ int i, k, numBlocks;
+ uint8_t block[16], iv[4][4];
+
+ if(m_state != Valid)return RIJNDAEL_NOT_INITIALIZED;
+ if((m_mode != CFB1) && (m_direction == Encrypt))return RIJNDAEL_BAD_DIRECTION;
+
+ if (input == 0 || inputLen <= 0)return 0;
+
+ numBlocks = inputLen/128;
+
+ switch(m_mode)
+ {
+ case ECB:
+ for (i = numBlocks; i > 0; i--)
+ {
+ decrypt(input,outBuffer);
+ input += 16;
+ outBuffer += 16;
+ }
+ break;
+ case CBC:
+#if STRICT_ALIGN
+ memcpy(iv,m_initVector,16);
+#else
+ *((uint32_t*)iv[0]) = *((uint32_t*)(m_initVector ));
+ *((uint32_t*)iv[1]) = *((uint32_t*)(m_initVector+ 4));
+ *((uint32_t*)iv[2]) = *((uint32_t*)(m_initVector+ 8));
+ *((uint32_t*)iv[3]) = *((uint32_t*)(m_initVector+12));
+#endif
+ for (i = numBlocks; i > 0; i--)
+ {
+ decrypt(input, block);
+ ((uint32_t*)block)[0] ^= *((uint32_t*)iv[0]);
+ ((uint32_t*)block)[1] ^= *((uint32_t*)iv[1]);
+ ((uint32_t*)block)[2] ^= *((uint32_t*)iv[2]);
+ ((uint32_t*)block)[3] ^= *((uint32_t*)iv[3]);
+#if STRICT_ALIGN
+ memcpy(iv, input, 16);
+ memcpy(outBuf, block, 16);
+#else
+ *((uint32_t*)iv[0]) = ((uint32_t*)input)[0]; ((uint32_t*)outBuffer)[0] = ((uint32_t*)block)[0];
+ *((uint32_t*)iv[1]) = ((uint32_t*)input)[1]; ((uint32_t*)outBuffer)[1] = ((uint32_t*)block)[1];
+ *((uint32_t*)iv[2]) = ((uint32_t*)input)[2]; ((uint32_t*)outBuffer)[2] = ((uint32_t*)block)[2];
+ *((uint32_t*)iv[3]) = ((uint32_t*)input)[3]; ((uint32_t*)outBuffer)[3] = ((uint32_t*)block)[3];
+#endif
+ input += 16;
+ outBuffer += 16;
+ }
+ break;
+ case CFB1:
+#if STRICT_ALIGN
+ memcpy(iv, m_initVector, 16);
+#else
+ *((uint32_t*)iv[0]) = *((uint32_t*)(m_initVector));
+ *((uint32_t*)iv[1]) = *((uint32_t*)(m_initVector+ 4));
+ *((uint32_t*)iv[2]) = *((uint32_t*)(m_initVector+ 8));
+ *((uint32_t*)iv[3]) = *((uint32_t*)(m_initVector+12));
+#endif
+ for(i = numBlocks; i > 0; i--)
+ {
+ for(k = 0; k < 128; k++)
+ {
+ *((uint32_t*) block ) = *((uint32_t*)iv[0]);
+ *((uint32_t*)(block+ 4)) = *((uint32_t*)iv[1]);
+ *((uint32_t*)(block+ 8)) = *((uint32_t*)iv[2]);
+ *((uint32_t*)(block+12)) = *((uint32_t*)iv[3]);
+ encrypt(block, block);
+ iv[0][0] = (iv[0][0] << 1) | (iv[0][1] >> 7);
+ iv[0][1] = (iv[0][1] << 1) | (iv[0][2] >> 7);
+ iv[0][2] = (iv[0][2] << 1) | (iv[0][3] >> 7);
+ iv[0][3] = (iv[0][3] << 1) | (iv[1][0] >> 7);
+ iv[1][0] = (iv[1][0] << 1) | (iv[1][1] >> 7);
+ iv[1][1] = (iv[1][1] << 1) | (iv[1][2] >> 7);
+ iv[1][2] = (iv[1][2] << 1) | (iv[1][3] >> 7);
+ iv[1][3] = (iv[1][3] << 1) | (iv[2][0] >> 7);
+ iv[2][0] = (iv[2][0] << 1) | (iv[2][1] >> 7);
+ iv[2][1] = (iv[2][1] << 1) | (iv[2][2] >> 7);
+ iv[2][2] = (iv[2][2] << 1) | (iv[2][3] >> 7);
+ iv[2][3] = (iv[2][3] << 1) | (iv[3][0] >> 7);
+ iv[3][0] = (iv[3][0] << 1) | (iv[3][1] >> 7);
+ iv[3][1] = (iv[3][1] << 1) | (iv[3][2] >> 7);
+ iv[3][2] = (iv[3][2] << 1) | (iv[3][3] >> 7);
+ iv[3][3] = (iv[3][3] << 1) | (input[k/8] >> (7-(k&7))) & 1;
+ outBuffer[k/8] ^= (block[0] & 0x80) >> (k & 7);
+ }
+ }
+ break;
+ default:
+ return -1;
+ break;
+ }
+
+ return 128*numBlocks;
+}
+
+int Rijndael::padDecrypt(const uint8_t *input, int inputOctets, uint8_t *outBuffer)
+{
+ int i, numBlocks, padLen;
+ uint8_t block[16];
+ uint32_t iv[4];
+
+ if(m_state != Valid)return RIJNDAEL_NOT_INITIALIZED;
+ if(m_direction != Decrypt)return RIJNDAEL_BAD_DIRECTION;
+
+ if(input == 0 || inputOctets <= 0)return 0;
+
+ if((inputOctets % 16) != 0)return RIJNDAEL_CORRUPTED_DATA;
+
+ numBlocks = inputOctets/16;
+
+ switch(m_mode){
+ case ECB:
+ for (i = numBlocks - 1; i > 0; i--)
+ {
+ decrypt(input, outBuffer);
+ input += 16;
+ outBuffer += 16;
+ }
+
+ decrypt(input, block);
+ padLen = block[15];
+ if (padLen >= 16)return RIJNDAEL_CORRUPTED_DATA;
+ for(i = 16 - padLen; i < 16; i++)
+ {
+ if(block[i] != padLen)return RIJNDAEL_CORRUPTED_DATA;
+ }
+ memcpy(outBuffer, block, 16 - padLen);
+ break;
+ case CBC:
+ memcpy(iv, m_initVector, 16);
+ /* all blocks but last */
+ for (i = numBlocks - 1; i > 0; i--)
+ {
+ decrypt(input, block);
+ ((uint32_t*)block)[0] ^= iv[0];
+ ((uint32_t*)block)[1] ^= iv[1];
+ ((uint32_t*)block)[2] ^= iv[2];
+ ((uint32_t*)block)[3] ^= iv[3];
+ memcpy(iv, input, 16);
+ memcpy(outBuffer, block, 16);
+ input += 16;
+ outBuffer += 16;
+ }
+ /* last block */
+ decrypt(input, block);
+ ((uint32_t*)block)[0] ^= iv[0];
+ ((uint32_t*)block)[1] ^= iv[1];
+ ((uint32_t*)block)[2] ^= iv[2];
+ ((uint32_t*)block)[3] ^= iv[3];
+ padLen = block[15];
+ if(padLen <= 0 || padLen > 16)return RIJNDAEL_CORRUPTED_DATA;
+ for(i = 16 - padLen; i < 16; i++)
+ {
+ if(block[i] != padLen)return RIJNDAEL_CORRUPTED_DATA;
+ }
+ memcpy(outBuffer, block, 16 - padLen);
+ break;
+
+ default:
+ return -1;
+ break;
+ }
+
+ return 16*numBlocks - padLen;
+}
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// ALGORITHM
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+
+void Rijndael::keySched(uint8_t key[_MAX_KEY_COLUMNS][4])
+{
+ unsigned j,rconpointer = 0;
+
+ // Calculate the necessary round keys
+ // The number of calculations depends on keyBits and blockBits
+ unsigned uKeyColumns = m_uRounds - 6;
+
+ uint8_t tempKey[_MAX_KEY_COLUMNS][4];
+
+ // Copy the input key to the temporary key matrix
+
+ for(j = 0;j < uKeyColumns;j++)
+ {
+ *((uint32_t*)(tempKey[j])) = *((uint32_t*)(key[j]));
+ }
+
+ unsigned r = 0;
+ unsigned t = 0;
+
+ // copy values into round key array
+ for(j = 0;(j < uKeyColumns) && (r <= m_uRounds); )
+ {
+ for(;(j < uKeyColumns) && (t < 4); j++, t++)
+ {
+ *((uint32_t*)m_expandedKey[r][t]) = *((uint32_t*)tempKey[j]);
+ }
+
+
+ if(t == 4)
+ {
+ r++;
+ t = 0;
+ }
+ }
+
+ while(r <= m_uRounds)
+ {
+ tempKey[0][0] ^= S[tempKey[uKeyColumns-1][1]];
+ tempKey[0][1] ^= S[tempKey[uKeyColumns-1][2]];
+ tempKey[0][2] ^= S[tempKey[uKeyColumns-1][3]];
+ tempKey[0][3] ^= S[tempKey[uKeyColumns-1][0]];
+ tempKey[0][0] ^= rcon[rconpointer++];
+
+ if (uKeyColumns != 8)
+ {
+ for(j = 1; j < uKeyColumns; j++)
+ {
+ *((uint32_t*)tempKey[j]) ^= *((uint32_t*)tempKey[j-1]);
+ }
+ } else {
+ for(j = 1; j < uKeyColumns/2; j++)
+ {
+ *((uint32_t*)tempKey[j]) ^= *((uint32_t*)tempKey[j-1]);
+ }
+ tempKey[uKeyColumns/2][0] ^= S[tempKey[uKeyColumns/2 - 1][0]];
+ tempKey[uKeyColumns/2][1] ^= S[tempKey[uKeyColumns/2 - 1][1]];
+ tempKey[uKeyColumns/2][2] ^= S[tempKey[uKeyColumns/2 - 1][2]];
+ tempKey[uKeyColumns/2][3] ^= S[tempKey[uKeyColumns/2 - 1][3]];
+ for(j = uKeyColumns/2 + 1; j < uKeyColumns; j++)
+ {
+ *((uint32_t*)tempKey[j]) ^= *((uint32_t*)tempKey[j-1]);
+ }
+ }
+ for(j = 0; (j < uKeyColumns) && (r <= m_uRounds); )
+ {
+ for(; (j < uKeyColumns) && (t < 4); j++, t++)
+ {
+ *((uint32_t*)m_expandedKey[r][t]) = *((uint32_t*)tempKey[j]);
+ }
+ if(t == 4)
+ {
+ r++;
+ t = 0;
+ }
+ }
+ }
+}
+
+void Rijndael::keyEncToDec()
+{
+ unsigned r;
+ uint8_t *w;
+
+ for(r = 1; r < m_uRounds; r++)
+ {
+ w = m_expandedKey[r][0];
+ *((uint32_t*)w) = *((uint32_t*)U1[w[0]]) ^ *((uint32_t*)U2[w[1]]) ^ *((uint32_t*)U3[w[2]]) ^ *((uint32_t*)U4[w[3]]);
+ w = m_expandedKey[r][1];
+ *((uint32_t*)w) = *((uint32_t*)U1[w[0]]) ^ *((uint32_t*)U2[w[1]]) ^ *((uint32_t*)U3[w[2]]) ^ *((uint32_t*)U4[w[3]]);
+ w = m_expandedKey[r][2];
+ *((uint32_t*)w) = *((uint32_t*)U1[w[0]]) ^ *((uint32_t*)U2[w[1]]) ^ *((uint32_t*)U3[w[2]]) ^ *((uint32_t*)U4[w[3]]);
+ w = m_expandedKey[r][3];
+ *((uint32_t*)w) = *((uint32_t*)U1[w[0]]) ^ *((uint32_t*)U2[w[1]]) ^ *((uint32_t*)U3[w[2]]) ^ *((uint32_t*)U4[w[3]]);
+ }
+}
+
+void Rijndael::encrypt(const uint8_t a[16], uint8_t b[16])
+{
+ unsigned r;
+ uint8_t temp[4][4];
+
+ *((uint32_t*)temp[0]) = *((uint32_t*)(a )) ^ *((uint32_t*)m_expandedKey[0][0]);
+ *((uint32_t*)temp[1]) = *((uint32_t*)(a+ 4)) ^ *((uint32_t*)m_expandedKey[0][1]);
+ *((uint32_t*)temp[2]) = *((uint32_t*)(a+ 8)) ^ *((uint32_t*)m_expandedKey[0][2]);
+ *((uint32_t*)temp[3]) = *((uint32_t*)(a+12)) ^ *((uint32_t*)m_expandedKey[0][3]);
+ *((uint32_t*)(b )) = *((uint32_t*)T1[temp[0][0]])
+ ^ *((uint32_t*)T2[temp[1][1]])
+ ^ *((uint32_t*)T3[temp[2][2]])
+ ^ *((uint32_t*)T4[temp[3][3]]);
+ *((uint32_t*)(b + 4)) = *((uint32_t*)T1[temp[1][0]])
+ ^ *((uint32_t*)T2[temp[2][1]])
+ ^ *((uint32_t*)T3[temp[3][2]])
+ ^ *((uint32_t*)T4[temp[0][3]]);
+ *((uint32_t*)(b + 8)) = *((uint32_t*)T1[temp[2][0]])
+ ^ *((uint32_t*)T2[temp[3][1]])
+ ^ *((uint32_t*)T3[temp[0][2]])
+ ^ *((uint32_t*)T4[temp[1][3]]);
+ *((uint32_t*)(b +12)) = *((uint32_t*)T1[temp[3][0]])
+ ^ *((uint32_t*)T2[temp[0][1]])
+ ^ *((uint32_t*)T3[temp[1][2]])
+ ^ *((uint32_t*)T4[temp[2][3]]);
+ for(r = 1; r < m_uRounds-1; r++)
+ {
+ *((uint32_t*)temp[0]) = *((uint32_t*)(b )) ^ *((uint32_t*)m_expandedKey[r][0]);
+ *((uint32_t*)temp[1]) = *((uint32_t*)(b+ 4)) ^ *((uint32_t*)m_expandedKey[r][1]);
+ *((uint32_t*)temp[2]) = *((uint32_t*)(b+ 8)) ^ *((uint32_t*)m_expandedKey[r][2]);
+ *((uint32_t*)temp[3]) = *((uint32_t*)(b+12)) ^ *((uint32_t*)m_expandedKey[r][3]);
+
+ *((uint32_t*)(b )) = *((uint32_t*)T1[temp[0][0]])
+ ^ *((uint32_t*)T2[temp[1][1]])
+ ^ *((uint32_t*)T3[temp[2][2]])
+ ^ *((uint32_t*)T4[temp[3][3]]);
+ *((uint32_t*)(b + 4)) = *((uint32_t*)T1[temp[1][0]])
+ ^ *((uint32_t*)T2[temp[2][1]])
+ ^ *((uint32_t*)T3[temp[3][2]])
+ ^ *((uint32_t*)T4[temp[0][3]]);
+ *((uint32_t*)(b + 8)) = *((uint32_t*)T1[temp[2][0]])
+ ^ *((uint32_t*)T2[temp[3][1]])
+ ^ *((uint32_t*)T3[temp[0][2]])
+ ^ *((uint32_t*)T4[temp[1][3]]);
+ *((uint32_t*)(b +12)) = *((uint32_t*)T1[temp[3][0]])
+ ^ *((uint32_t*)T2[temp[0][1]])
+ ^ *((uint32_t*)T3[temp[1][2]])
+ ^ *((uint32_t*)T4[temp[2][3]]);
+ }
+ *((uint32_t*)temp[0]) = *((uint32_t*)(b )) ^ *((uint32_t*)m_expandedKey[m_uRounds-1][0]);
+ *((uint32_t*)temp[1]) = *((uint32_t*)(b+ 4)) ^ *((uint32_t*)m_expandedKey[m_uRounds-1][1]);
+ *((uint32_t*)temp[2]) = *((uint32_t*)(b+ 8)) ^ *((uint32_t*)m_expandedKey[m_uRounds-1][2]);
+ *((uint32_t*)temp[3]) = *((uint32_t*)(b+12)) ^ *((uint32_t*)m_expandedKey[m_uRounds-1][3]);
+ b[ 0] = T1[temp[0][0]][1];
+ b[ 1] = T1[temp[1][1]][1];
+ b[ 2] = T1[temp[2][2]][1];
+ b[ 3] = T1[temp[3][3]][1];
+ b[ 4] = T1[temp[1][0]][1];
+ b[ 5] = T1[temp[2][1]][1];
+ b[ 6] = T1[temp[3][2]][1];
+ b[ 7] = T1[temp[0][3]][1];
+ b[ 8] = T1[temp[2][0]][1];
+ b[ 9] = T1[temp[3][1]][1];
+ b[10] = T1[temp[0][2]][1];
+ b[11] = T1[temp[1][3]][1];
+ b[12] = T1[temp[3][0]][1];
+ b[13] = T1[temp[0][1]][1];
+ b[14] = T1[temp[1][2]][1];
+ b[15] = T1[temp[2][3]][1];
+ *((uint32_t*)(b )) ^= *((uint32_t*)m_expandedKey[m_uRounds][0]);
+ *((uint32_t*)(b+ 4)) ^= *((uint32_t*)m_expandedKey[m_uRounds][1]);
+ *((uint32_t*)(b+ 8)) ^= *((uint32_t*)m_expandedKey[m_uRounds][2]);
+ *((uint32_t*)(b+12)) ^= *((uint32_t*)m_expandedKey[m_uRounds][3]);
+}
+
+void Rijndael::decrypt(const uint8_t a[16], uint8_t b[16])
+{
+ int r;
+ uint8_t temp[4][4];
+
+ *((uint32_t*)temp[0]) = *((uint32_t*)(a )) ^ *((uint32_t*)m_expandedKey[m_uRounds][0]);
+ *((uint32_t*)temp[1]) = *((uint32_t*)(a+ 4)) ^ *((uint32_t*)m_expandedKey[m_uRounds][1]);
+ *((uint32_t*)temp[2]) = *((uint32_t*)(a+ 8)) ^ *((uint32_t*)m_expandedKey[m_uRounds][2]);
+ *((uint32_t*)temp[3]) = *((uint32_t*)(a+12)) ^ *((uint32_t*)m_expandedKey[m_uRounds][3]);
+
+ *((uint32_t*)(b )) = *((uint32_t*)T5[temp[0][0]])
+ ^ *((uint32_t*)T6[temp[3][1]])
+ ^ *((uint32_t*)T7[temp[2][2]])
+ ^ *((uint32_t*)T8[temp[1][3]]);
+ *((uint32_t*)(b+ 4)) = *((uint32_t*)T5[temp[1][0]])
+ ^ *((uint32_t*)T6[temp[0][1]])
+ ^ *((uint32_t*)T7[temp[3][2]])
+ ^ *((uint32_t*)T8[temp[2][3]]);
+ *((uint32_t*)(b+ 8)) = *((uint32_t*)T5[temp[2][0]])
+ ^ *((uint32_t*)T6[temp[1][1]])
+ ^ *((uint32_t*)T7[temp[0][2]])
+ ^ *((uint32_t*)T8[temp[3][3]]);
+ *((uint32_t*)(b+12)) = *((uint32_t*)T5[temp[3][0]])
+ ^ *((uint32_t*)T6[temp[2][1]])
+ ^ *((uint32_t*)T7[temp[1][2]])
+ ^ *((uint32_t*)T8[temp[0][3]]);
+ for(r = m_uRounds-1; r > 1; r--)
+ {
+ *((uint32_t*)temp[0]) = *((uint32_t*)(b )) ^ *((uint32_t*)m_expandedKey[r][0]);
+ *((uint32_t*)temp[1]) = *((uint32_t*)(b+ 4)) ^ *((uint32_t*)m_expandedKey[r][1]);
+ *((uint32_t*)temp[2]) = *((uint32_t*)(b+ 8)) ^ *((uint32_t*)m_expandedKey[r][2]);
+ *((uint32_t*)temp[3]) = *((uint32_t*)(b+12)) ^ *((uint32_t*)m_expandedKey[r][3]);
+ *((uint32_t*)(b )) = *((uint32_t*)T5[temp[0][0]])
+ ^ *((uint32_t*)T6[temp[3][1]])
+ ^ *((uint32_t*)T7[temp[2][2]])
+ ^ *((uint32_t*)T8[temp[1][3]]);
+ *((uint32_t*)(b+ 4)) = *((uint32_t*)T5[temp[1][0]])
+ ^ *((uint32_t*)T6[temp[0][1]])
+ ^ *((uint32_t*)T7[temp[3][2]])
+ ^ *((uint32_t*)T8[temp[2][3]]);
+ *((uint32_t*)(b+ 8)) = *((uint32_t*)T5[temp[2][0]])
+ ^ *((uint32_t*)T6[temp[1][1]])
+ ^ *((uint32_t*)T7[temp[0][2]])
+ ^ *((uint32_t*)T8[temp[3][3]]);
+ *((uint32_t*)(b+12)) = *((uint32_t*)T5[temp[3][0]])
+ ^ *((uint32_t*)T6[temp[2][1]])
+ ^ *((uint32_t*)T7[temp[1][2]])
+ ^ *((uint32_t*)T8[temp[0][3]]);
+ }
+
+ *((uint32_t*)temp[0]) = *((uint32_t*)(b )) ^ *((uint32_t*)m_expandedKey[1][0]);
+ *((uint32_t*)temp[1]) = *((uint32_t*)(b+ 4)) ^ *((uint32_t*)m_expandedKey[1][1]);
+ *((uint32_t*)temp[2]) = *((uint32_t*)(b+ 8)) ^ *((uint32_t*)m_expandedKey[1][2]);
+ *((uint32_t*)temp[3]) = *((uint32_t*)(b+12)) ^ *((uint32_t*)m_expandedKey[1][3]);
+ b[ 0] = S5[temp[0][0]];
+ b[ 1] = S5[temp[3][1]];
+ b[ 2] = S5[temp[2][2]];
+ b[ 3] = S5[temp[1][3]];
+ b[ 4] = S5[temp[1][0]];
+ b[ 5] = S5[temp[0][1]];
+ b[ 6] = S5[temp[3][2]];
+ b[ 7] = S5[temp[2][3]];
+ b[ 8] = S5[temp[2][0]];
+ b[ 9] = S5[temp[1][1]];
+ b[10] = S5[temp[0][2]];
+ b[11] = S5[temp[3][3]];
+ b[12] = S5[temp[3][0]];
+ b[13] = S5[temp[2][1]];
+ b[14] = S5[temp[1][2]];
+ b[15] = S5[temp[0][3]];
+ *((uint32_t*)(b )) ^= *((uint32_t*)m_expandedKey[0][0]);
+ *((uint32_t*)(b+ 4)) ^= *((uint32_t*)m_expandedKey[0][1]);
+ *((uint32_t*)(b+ 8)) ^= *((uint32_t*)m_expandedKey[0][2]);
+ *((uint32_t*)(b+12)) ^= *((uint32_t*)m_expandedKey[0][3]);
+}
--- /dev/null
+#ifndef _RIJNDAEL_H_
+#define _RIJNDAEL_H_
+
+//
+// File : rijndael.h
+// Creation date : Sun Nov 5 2000 03:21:05 CEST
+// Author : Szymon Stefanek (stefanek@tin.it)
+//
+// Another implementation of the Rijndael cipher.
+// This is intended to be an easily usable library file.
+// This code is public domain.
+// Based on the Vincent Rijmen and K.U.Leuven implementation 2.4.
+//
+
+//
+// Original Copyright notice:
+//
+// rijndael-alg-fst.c v2.4 April '2000
+// rijndael-alg-fst.h
+// rijndael-api-fst.c
+// rijndael-api-fst.h
+//
+// Optimised ANSI C code
+//
+// authors: v1.0: Antoon Bosselaers
+// v2.0: Vincent Rijmen, K.U.Leuven
+// v2.3: Paulo Barreto
+// v2.4: Vincent Rijmen, K.U.Leuven
+//
+// This code is placed in the public domain.
+//
+
+//
+// This implementation works on 128 , 192 , 256 bit keys
+// and on 128 bit blocks
+//
+
+//
+// Example of usage:
+//
+// // Input data
+// unsigned char key[32]; // The key
+// initializeYour256BitKey(); // Obviously initialized with sth
+// const unsigned char * plainText = getYourPlainText(); // Your plain text
+// int plainTextLen = strlen(plainText); // Plain text length
+//
+// // Encrypting
+// Rijndael rin;
+// unsigned char output[plainTextLen + 16];
+//
+// rin.init(Rijndael::CBC,Rijndael::Encrypt,key,Rijndael::Key32Bytes);
+// // It is a good idea to check the error code
+// int len = rin.padEncrypt(plainText,len,output);
+// if(len >= 0)useYourEncryptedText();
+// else encryptError(len);
+//
+// // Decrypting: we can reuse the same object
+// unsigned char output2[len];
+// rin.init(Rijndael::CBC,Rijndael::Decrypt,key,Rijndael::Key32Bytes));
+// len = rin.padDecrypt(output,len,output2);
+// if(len >= 0)useYourDecryptedText();
+// else decryptError(len);
+//
+
+#include "stdafx.h"
+
+#define _MAX_KEY_COLUMNS (256/32)
+#define _MAX_ROUNDS 14
+#define MAX_IV_SIZE 16
+
+// We assume that unsigned int is 32 bits long....
+//typedef unsigned char uint8_t;
+//typedef unsigned int uint32_t;
+//typedef unsigned short uint16_t;
+
+// Error codes
+#define RIJNDAEL_SUCCESS 0
+#define RIJNDAEL_UNSUPPORTED_MODE -1
+#define RIJNDAEL_UNSUPPORTED_DIRECTION -2
+#define RIJNDAEL_UNSUPPORTED_KEY_LENGTH -3
+#define RIJNDAEL_BAD_KEY -4
+#define RIJNDAEL_NOT_INITIALIZED -5
+#define RIJNDAEL_BAD_DIRECTION -6
+#define RIJNDAEL_CORRUPTED_DATA -7
+
+class Rijndael
+{
+public:
+ enum Direction { Encrypt , Decrypt };
+ enum Mode { ECB , CBC , CFB1 };
+ enum KeyLength { Key16Bytes , Key24Bytes , Key32Bytes };
+ //
+ // Creates a Rijndael cipher object
+ // You have to call init() before you can encrypt or decrypt stuff
+ //
+ Rijndael();
+ ~Rijndael();
+protected:
+ // Internal stuff
+ enum State { Valid , Invalid };
+
+ State m_state;
+ Mode m_mode;
+ Direction m_direction;
+ uint8_t m_initVector[MAX_IV_SIZE];
+ uint32_t m_uRounds;
+ uint8_t m_expandedKey[_MAX_ROUNDS+1][4][4];
+public:
+ //////////////////////////////////////////////////////////////////////////////////////////
+ // API
+ //////////////////////////////////////////////////////////////////////////////////////////
+
+ // init(): Initializes the crypt session
+ // Returns RIJNDAEL_SUCCESS or an error code
+ // mode : Rijndael::ECB, Rijndael::CBC or Rijndael::CFB1
+ // You have to use the same mode for encrypting and decrypting
+ // dir : Rijndael::Encrypt or Rijndael::Decrypt
+ // A cipher instance works only in one direction
+ // (Well , it could be easily modified to work in both
+ // directions with a single init() call, but it looks
+ // useless to me...anyway , it is a matter of generating
+ // two expanded keys)
+ // key : array of unsigned octets , it can be 16 , 24 or 32 bytes long
+ // this CAN be binary data (it is not expected to be null terminated)
+ // keyLen : Rijndael::Key16Bytes , Rijndael::Key24Bytes or Rijndael::Key32Bytes
+ // initVector: initialization vector, you will usually use 0 here
+ int init(Mode mode,Direction dir,const uint8_t *key,KeyLength keyLen,uint8_t * initVector = 0);
+ // Encrypts the input array (can be binary data)
+ // The input array length must be a multiple of 16 bytes, the remaining part
+ // is DISCARDED.
+ // so it actually encrypts inputLen / 128 blocks of input and puts it in outBuffer
+ // Input len is in BITS!
+ // outBuffer must be at least inputLen / 8 bytes long.
+ // Returns the encrypted buffer length in BITS or an error code < 0 in case of error
+ int blockEncrypt(const uint8_t *input, int inputLen, uint8_t *outBuffer);
+ // Encrypts the input array (can be binary data)
+ // The input array can be any length , it is automatically padded on a 16 byte boundary.
+ // Input len is in BYTES!
+ // outBuffer must be at least (inputLen + 16) bytes long
+ // Returns the encrypted buffer length in BYTES or an error code < 0 in case of error
+ int padEncrypt(const uint8_t *input, int inputOctets, uint8_t *outBuffer);
+ // Decrypts the input vector
+ // Input len is in BITS!
+ // outBuffer must be at least inputLen / 8 bytes long
+ // Returns the decrypted buffer length in BITS and an error code < 0 in case of error
+ int blockDecrypt(const uint8_t *input, int inputLen, uint8_t *outBuffer);
+ // Decrypts the input vector
+ // Input len is in BYTES!
+ // outBuffer must be at least inputLen bytes long
+ // Returns the decrypted buffer length in BYTES and an error code < 0 in case of error
+ int padDecrypt(const uint8_t *input, int inputOctets, uint8_t *outBuffer);
+protected:
+ void keySched(uint8_t key[_MAX_KEY_COLUMNS][4]);
+ void keyEncToDec();
+ void encrypt(const uint8_t a[16], uint8_t b[16]);
+ void decrypt(const uint8_t a[16], uint8_t b[16]);
+};
+
+#endif // _RIJNDAEL_H_
--- /dev/null
+/*
+ * smart_ptr.h
+ * elftosb
+ *
+ * Created by Chris Reed on 4/18/06.
+ * Copyright 2006 __MyCompanyName__. All rights reserved.
+ *
+ */
+#if !defined(_smart_ptr_h_)
+#define _smart_ptr_h_
+
+/*!
+ * \brief Simple, standard smart pointer class.
+ *
+ * This class only supports the single-owner paradigm.
+ */
+template <typename T>
+class smart_ptr
+{
+public:
+ typedef T data_type;
+ typedef T * ptr_type;
+ typedef const T * const_ptr_type;
+ typedef T & ref_type;
+ typedef const T & const_ref_type;
+
+ //! Default constuctor. Initialises with no pointer set.
+ smart_ptr() : _p(0) {}
+
+ //! This constructor takes a pointer to the object to be deleted.
+ smart_ptr(ptr_type p) : _p(p) {}
+
+ //! Destructor. If an object (pointer) has been set, it will be deleted.
+ //! Deletes the object using safe_delete().
+ virtual ~smart_ptr() { safe_delete(); }
+
+ //! Return the current pointer value.
+ ptr_type get() { return _p; }
+
+ //! Return the const form of the current pointer value.
+ const_ptr_type get() const { return _p; }
+
+ //! Change the pointer value, or set if if the default constructor was used.
+ //! If a pointer had previously been associated with the object, and \a p is
+ //! different than that previous pointer, it will be deleted before taking
+ //! ownership of \a p. If this is not desired, call reset() beforehand.
+ void set(ptr_type p)
+ {
+ if (_p && p != _p)
+ {
+ safe_delete();
+ }
+ _p = p;
+ }
+
+ //! Dissociates any previously set pointer value without deleting it.
+ void reset() { _p = 0; }
+
+ //! Dissociates a previously set pointer value, deleting it at the same time.
+ void clear() { safe_delete(); }
+
+ //! Forces immediate deletion of the object. If you are planning on using
+ //! this method, think about just using a normal pointer. It probably makes
+ //! more sense.
+ virtual void safe_delete()
+ {
+ if (_p)
+ {
+ delete _p;
+ _p = 0;
+ }
+ }
+
+ //! \name Operators
+ //@{
+
+ //! Makes the object transparent as the template type.
+ operator ptr_type () { return _p; }
+
+ //! Const version of the pointer operator.
+ operator const_ptr_type () const { return _p; }
+
+ //! Makes the object transparent as a reference of the template type.
+ operator ref_type () { return *_p; }
+
+ //! Const version of the reference operator.
+ operator const_ref_type () const { return *_p; }
+
+ //! Returns a boolean indicating whether the object has a pointer set or not.
+ operator bool () const { return _p != 0; }
+
+ //! To allow setting the pointer directly. Equivalent to a call to set().
+ smart_ptr<T> & operator = (const_ptr_type p)
+ {
+ set(const_cast<ptr_type>(p));
+ return *this;
+ }
+
+ //! Another operator to allow you to treat the object just like a pointer.
+ ptr_type operator ->() { return _p; }
+
+ //! Another operator to allow you to treat the object just like a pointer.
+ const_ptr_type operator ->() const { return _p; }
+
+// //! Pointer dereferencing operator.
+// ref_type operator * () const { return *_p; }
+//
+// //! Const version of the pointer dereference operator.
+// const_ref_type operator * () const { return *_p; }
+
+ //@}
+
+protected:
+ ptr_type _p; //!< The wrapped pointer.
+};
+
+/*!
+ * \brief Simple, standard smart pointer class that uses the array delete operator.
+ *
+ * This class only supports the single-owner paradigm.
+ *
+ * This is almost entirely a copy of smart_ptr since the final C++ specification
+ * does not allow template subclass members to access members of the parent that
+ * do not depend on the template parameter.
+ */
+template <typename T>
+class smart_array_ptr
+{
+public:
+ typedef T data_type;
+ typedef T * ptr_type;
+ typedef const T * const_ptr_type;
+ typedef T & ref_type;
+ typedef const T & const_ref_type;
+
+ //! Default constuctor. Initialises with no pointer set.
+ smart_array_ptr() : _p(0) {}
+
+ //! This constructor takes a pointer to the object to be deleted.
+ smart_array_ptr(ptr_type p) : _p(p) {}
+
+ //! Destructor. If an array has been set, it will be deleted.
+ //! Deletes the array using safe_delete().
+ virtual ~smart_array_ptr() { safe_delete(); }
+
+ //! Return the current pointer value.
+ ptr_type get() { return _p; }
+
+ //! Return the const form of the current pointer value.
+ const_ptr_type get() const { return _p; }
+
+ //! Change the pointer value, or set if if the default constructor was used.
+ //! If a pointer had previously been associated with the object, and \a p is
+ //! different than that previous pointer, it will be deleted before taking
+ //! ownership of \a p. If this is not desired, call reset() beforehand.
+ void set(ptr_type p)
+ {
+ if (_p && p != _p)
+ {
+ safe_delete();
+ }
+ _p = p;
+ }
+
+ //! Dissociates any previously set pointer value without deleting it.
+ void reset() { _p = 0; }
+
+ //! Dissociates a previously set pointer value, deleting it at the same time.
+ void clear() { safe_delete(); }
+
+ //! Forces immediate deletion of the object. If you are planning on using
+ //! this method, think about just using a normal pointer. It probably makes
+ //! more sense.
+ virtual void safe_delete()
+ {
+ if (_p)
+ {
+ delete [] _p;
+ _p = 0;
+ }
+ }
+
+ //! \name Operators
+ //@{
+
+ //! Makes the object transparent as the template type.
+ operator ptr_type () { return _p; }
+
+ //! Const version of the pointer operator.
+ operator const_ptr_type () const { return _p; }
+
+ //! Makes the object transparent as a reference of the template type.
+ operator ref_type () { return *_p; }
+
+ //! Const version of the reference operator.
+ operator const_ref_type () const { return *_p; }
+
+ //! Returns a boolean indicating whether the object has a pointer set or not.
+ operator bool () const { return _p != 0; }
+
+ //! To allow setting the pointer directly. Equivalent to a call to set().
+ smart_array_ptr<T> & operator = (const_ptr_type p)
+ {
+ set(const_cast<ptr_type>(p));
+ return *this;
+ }
+
+ //! Another operator to allow you to treat the object just like a pointer.
+ ptr_type operator ->() { return _p; }
+
+ //! Another operator to allow you to treat the object just like a pointer.
+ const_ptr_type operator ->() const { return _p; }
+
+ //! Indexing operator.
+ ref_type operator [] (unsigned index) { return _p[index]; }
+
+ //! Indexing operator.
+ const_ref_type operator [] (unsigned index) const { return _p[index]; }
+
+// //! Pointer dereferencing operator.
+// ref_type operator * () const { return *_p; }
+//
+// //! Const version of the pointer dereference operator.
+// const_ref_type operator * () const { return *_p; }
+
+ //@}
+
+protected:
+ ptr_type _p; //!< The wrapped pointer.
+};
+
+#endif // _smart_ptr_h_
--- /dev/null
+// stdafx.cpp : source file that includes just the standard includes
+// elftosb.pch will be the pre-compiled header
+// stdafx.obj will contain the pre-compiled type information
+
+#include "stdafx.h"
+
+// TODO: reference any additional headers you need in STDAFX.H
+// and not in this file
--- /dev/null
+#ifndef stdafx_h_
+#define stdafx_h_
+
+// stdafx.h : include file for standard system include files,
+// or project specific include files that are used frequently, but
+// are changed infrequently
+//
+
+// Default to external release.
+#ifndef SGTL_INTERNAL
+ #define SGTL_INTERNAL 0
+#endif
+
+#include <iostream>
+#include <stdexcept>
+
+#if defined(WIN32)
+//#include <tchar.h>
+
+ // define this macro for use in VC++
+ #if !defined(__LITTLE_ENDIAN__)
+ #define __LITTLE_ENDIAN__ 1
+ #endif // !defined(__LITTLE_ENDIAN__)
+#endif // defined(WIN32)
+
+#if defined(Linux)
+// For Linux systems only, types.h only defines the signed
+// integer types. This is not professional code.
+// Update: They are defined in the header files in the more recent version of redhat enterprise gcc.
+#include "/usr/include/sys/types.h"
+#include <stdint.h>
+//typedef unsigned long uint32_t;
+//typedef unsigned short uint16_t;
+//typedef unsigned char uint8_t;
+
+//#define TCHAR char
+//#define _tmain main
+
+ // give a default endian in case one is not defined on Linux (it should be, though)
+ #if !defined(__LITTLE_ENDIAN__) && !defined(__BIG_ENDIAN__)
+ #define __LITTLE_ENDIAN__ 1
+ #endif // !defined(__LITTLE_ENDIAN__) && !defined(__BIG_ENDIAN__)
+
+#endif // defined(Linux)
+
+// gcc on Mac OS X
+#if defined(__GNUC__) && ( defined(__APPLE_CPP__) || defined(__APPLE_CC__) || defined(__MACOS_CLASSIC__) )
+ #include <TargetConditionals.h>
+
+ #if defined(TARGET_RT_LITTLE_ENDIAN) && TARGET_RT_LITTLE_ENDIAN
+ #if !defined(__LITTLE_ENDIAN__)
+ #define __LITTLE_ENDIAN__
+ #endif
+ #elif defined(TARGET_RT_BIG_ENDIAN) && TARGET_RT_BIG_ENDIAN
+ #if !defined(__BIG_ENDIAN__)
+ #define __BIG_ENDIAN__
+ #endif
+ #endif
+#endif
+
+#if defined(WIN32) //!defined(Linux) || !defined(__GNUC__)
+// redefine missing typedefs from stdint.h or syst/types.h
+
+typedef unsigned long long uint64_t;
+typedef unsigned long uint32_t;
+typedef unsigned short uint16_t;
+typedef unsigned char uint8_t;
+
+typedef long long int64_t;
+typedef long int32_t;
+typedef short int16_t;
+typedef char int8_t;
+#endif // !defined(Linux)
+
+#if !defined(TRUE)
+ #define TRUE 1
+#endif // !defined(TRUE)
+
+#if !defined(FALSE)
+ #define FALSE 0
+#endif // !defined(FALSE)
+
+#endif // stdafx_h_
--- /dev/null
+..\elftosb\elftosb.vcproj\r
+..\unittests\unittests.vcproj\r
+..\generatekeys\generatekeys.vcproj\r
+..\decrypt\decrypt.vcproj\r
+..\elftosb2\elftosb2.vcproj\r
+..\sbtool\sbtool.vcproj\r
+..\keygen\keygen.vcproj\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE plist PUBLIC "-//Apple Computer//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
+<plist version="1.0">
+<dict>
+ <key>ActivePerspectiveName</key>
+ <string>Project</string>
+ <key>AllowedModules</key>
+ <array>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>PBXSmartGroupTreeModule</string>
+ <key>Name</key>
+ <string>Groups and Files Outline View</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>PBXNavigatorGroup</string>
+ <key>Name</key>
+ <string>Editor</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>XCTaskListModule</string>
+ <key>Name</key>
+ <string>Task List</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>XCDetailModule</string>
+ <key>Name</key>
+ <string>File and Smart Group Detail Viewer</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>1</string>
+ <key>Module</key>
+ <string>PBXBuildResultsModule</string>
+ <key>Name</key>
+ <string>Detailed Build Results Viewer</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>1</string>
+ <key>Module</key>
+ <string>PBXProjectFindModule</string>
+ <key>Name</key>
+ <string>Project Batch Find Tool</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>PBXRunSessionModule</string>
+ <key>Name</key>
+ <string>Run Log</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>PBXBookmarksModule</string>
+ <key>Name</key>
+ <string>Bookmarks Tool</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>PBXClassBrowserModule</string>
+ <key>Name</key>
+ <string>Class Browser</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>PBXCVSModule</string>
+ <key>Name</key>
+ <string>Source Code Control Tool</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>PBXDebugBreakpointsModule</string>
+ <key>Name</key>
+ <string>Debug Breakpoints Tool</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>XCDockableInspector</string>
+ <key>Name</key>
+ <string>Inspector</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>PBXOpenQuicklyModule</string>
+ <key>Name</key>
+ <string>Open Quickly Tool</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>1</string>
+ <key>Module</key>
+ <string>PBXDebugSessionModule</string>
+ <key>Name</key>
+ <string>Debugger</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>1</string>
+ <key>Module</key>
+ <string>PBXDebugCLIModule</string>
+ <key>Name</key>
+ <string>Debug Console</string>
+ </dict>
+ </array>
+ <key>Description</key>
+ <string>DefaultDescriptionKey</string>
+ <key>DockingSystemVisible</key>
+ <false/>
+ <key>Extension</key>
+ <string>mode1</string>
+ <key>FavBarConfig</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>0246B7EF09C375FC009A0CA3</string>
+ <key>XCBarModuleItemNames</key>
+ <dict/>
+ <key>XCBarModuleItems</key>
+ <array/>
+ </dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>com.apple.perspectives.project.mode1</string>
+ <key>MajorVersion</key>
+ <integer>31</integer>
+ <key>MinorVersion</key>
+ <integer>1</integer>
+ <key>Name</key>
+ <string>Default</string>
+ <key>Notifications</key>
+ <array>
+ <dict>
+ <key>XCObserverAutoDisconnectKey</key>
+ <true/>
+ <key>XCObserverDefintionKey</key>
+ <dict/>
+ <key>XCObserverFactoryKey</key>
+ <string>XCPerspectivesSpecificationIdentifier</string>
+ <key>XCObserverGUIDKey</key>
+ <string>XCObserverProjectIdentifier</string>
+ <key>XCObserverNotificationKey</key>
+ <string>PBXStatusBuildStateMessageNotification</string>
+ <key>XCObserverTargetKey</key>
+ <string>XCMainBuildResultsModuleGUID</string>
+ <key>XCObserverTriggerKey</key>
+ <string>awakenModuleWithObserver:</string>
+ <key>XCObserverValidationKey</key>
+ <dict/>
+ </dict>
+ </array>
+ <key>OpenEditors</key>
+ <array/>
+ <key>PerspectiveWidths</key>
+ <array>
+ <integer>-1</integer>
+ <integer>-1</integer>
+ </array>
+ <key>Perspectives</key>
+ <array>
+ <dict>
+ <key>ChosenToolbarItems</key>
+ <array>
+ <string>active-target-popup</string>
+ <string>active-buildstyle-popup</string>
+ <string>action</string>
+ <string>NSToolbarFlexibleSpaceItem</string>
+ <string>buildOrClean</string>
+ <string>build-and-runOrDebug</string>
+ <string>com.apple.ide.PBXToolbarStopButton</string>
+ <string>show-inspector</string>
+ <string>get-info</string>
+ <string>toggle-editor</string>
+ <string>NSToolbarFlexibleSpaceItem</string>
+ <string>com.apple.pbx.toolbar.searchfield</string>
+ </array>
+ <key>ControllerClassBaseName</key>
+ <string></string>
+ <key>IconName</key>
+ <string>WindowOfProjectWithEditor</string>
+ <key>Identifier</key>
+ <string>perspective.project</string>
+ <key>IsVertical</key>
+ <false/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXBottomSmartGroupGIDs</key>
+ <array>
+ <string>1C37FBAC04509CD000000102</string>
+ <string>1C37FAAC04509CD000000102</string>
+ <string>1C08E77C0454961000C914BD</string>
+ <string>1C37FABC05509CD000000102</string>
+ <string>1C37FABC05539CD112110102</string>
+ <string>E2644B35053B69B200211256</string>
+ <string>1C37FABC04509CD000100104</string>
+ <string>1CC0EA4004350EF90044410B</string>
+ <string>1CC0EA4004350EF90041110B</string>
+ </array>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CE0B1FE06471DED0097A5F4</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Files</string>
+ <key>PBXProjectStructureProvided</key>
+ <string>yes</string>
+ <key>PBXSmartGroupTreeModuleColumnData</key>
+ <dict>
+ <key>PBXSmartGroupTreeModuleColumnWidthsKey</key>
+ <array>
+ <real>22</real>
+ <real>22</real>
+ <real>260</real>
+ </array>
+ <key>PBXSmartGroupTreeModuleColumnsKey_v4</key>
+ <array>
+ <string>TargetStatusColumn</string>
+ <string>SCMStatusColumn</string>
+ <string>MainColumn</string>
+ </array>
+ </dict>
+ <key>PBXSmartGroupTreeModuleOutlineStateKey_v7</key>
+ <dict>
+ <key>PBXSmartGroupTreeModuleOutlineStateExpansionKey</key>
+ <array>
+ <string>08FB7794FE84155DC02AAC07</string>
+ <string>02FE65020BFE669B004A1450</string>
+ <string>08FB7795FE84155DC02AAC07</string>
+ <string>0296A45909D9AE9400F80AFF</string>
+ <string>020D47700A1691F10027E24E</string>
+ <string>1C37FBAC04509CD000000102</string>
+ <string>1C37FAAC04509CD000000102</string>
+ </array>
+ <key>PBXSmartGroupTreeModuleOutlineStateSelectionKey</key>
+ <array>
+ <array>
+ <integer>2</integer>
+ <integer>0</integer>
+ </array>
+ </array>
+ <key>PBXSmartGroupTreeModuleOutlineStateVisibleRectKey</key>
+ <string>{{0, 0}, {304, 786}}</string>
+ </dict>
+ <key>PBXTopSmartGroupGIDs</key>
+ <array/>
+ <key>XCIncludePerspectivesSwitch</key>
+ <true/>
+ <key>XCSharingToken</key>
+ <string>com.apple.Xcode.GFSharingToken</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {321, 804}}</string>
+ <key>GroupTreeTableConfiguration</key>
+ <array>
+ <string>TargetStatusColumn</string>
+ <real>22</real>
+ <string>SCMStatusColumn</string>
+ <real>22</real>
+ <string>MainColumn</string>
+ <real>260</real>
+ </array>
+ <key>RubberWindowFrame</key>
+ <string>8 33 1079 845 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXSmartGroupTreeModule</string>
+ <key>Proportion</key>
+ <string>321pt</string>
+ </dict>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>BecomeActive</key>
+ <true/>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CE0B20306471E060097A5F4</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>elftosb.cpp</string>
+ <key>PBXSplitModuleInNavigatorKey</key>
+ <dict>
+ <key>Split0</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CE0B20406471E060097A5F4</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>elftosb.cpp</string>
+ <key>_historyCapacity</key>
+ <integer>0</integer>
+ <key>bookmark</key>
+ <string>0292B61F0CDA9CFD00A3A500</string>
+ <key>history</key>
+ <array>
+ <string>02DC60CD0A87DBB90027E7F9</string>
+ <string>021CA4400A8D2F740028326F</string>
+ <string>021CA4420A8D2F740028326F</string>
+ <string>021CA4480A8D2F740028326F</string>
+ <string>02C5DBD20A926A7F003B9C11</string>
+ <string>02C5DBDA0A926A7F003B9C11</string>
+ <string>02C5DBDB0A926A7F003B9C11</string>
+ <string>02C5DC310A93C14E003B9C11</string>
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+ <string>02C5DC350A93C14E003B9C11</string>
+ <string>02C5DC5B0A93C796003B9C11</string>
+ <string>02C5DCB50A93CA0A003B9C11</string>
+ <string>02C5DCB60A93CA0A003B9C11</string>
+ <string>02C5DD520A93D327003B9C11</string>
+ <string>02C5DDCD0A940126003B9C11</string>
+ <string>02C5DDCF0A940126003B9C11</string>
+ <string>02C5DDD00A940126003B9C11</string>
+ <string>02C5DE8D0A98B7E7003B9C11</string>
+ <string>02CAC9B90BA06EA50020B29B</string>
+ <string>02CAC9BA0BA06EA50020B29B</string>
+ <string>02D1FD190BD039BF007C7450</string>
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+ <string>02FE651B0BFF94B2004A1450</string>
+ <string>02FE65200BFF94B2004A1450</string>
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+ <string>0292B6180CDA9CFD00A3A500</string>
+ <string>0292B6190CDA9CFD00A3A500</string>
+ </array>
+ <key>nextStack</key>
+ <array>
+ <string>0292B61A0CDA9CFD00A3A500</string>
+ <string>0292B61B0CDA9CFD00A3A500</string>
+ <string>0292B61C0CDA9CFD00A3A500</string>
+ <string>0292B61D0CDA9CFD00A3A500</string>
+ <string>0292B61E0CDA9CFD00A3A500</string>
+ </array>
+ <key>prevStack</key>
+ <array>
+ <string>02DC60DC0A87DBB90027E7F9</string>
+ <string>027EE3D80BD6930A00A6A136</string>
+ <string>027EE3D90BD6930A00A6A136</string>
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+ <string>024A0F250C53B9D8000317D4</string>
+ <string>0259C9790CA30C56005285B7</string>
+ </array>
+ </dict>
+ <key>SplitCount</key>
+ <string>1</string>
+ </dict>
+ <key>StatusBarVisibility</key>
+ <true/>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {753, 799}}</string>
+ <key>RubberWindowFrame</key>
+ <string>8 33 1079 845 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXNavigatorGroup</string>
+ <key>Proportion</key>
+ <string>799pt</string>
+ </dict>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CE0B20506471E060097A5F4</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Detail</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 804}, {753, 0}}</string>
+ <key>RubberWindowFrame</key>
+ <string>8 33 1079 845 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>XCDetailModule</string>
+ <key>Proportion</key>
+ <string>0pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>753pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Project</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>XCModuleDock</string>
+ <string>PBXSmartGroupTreeModule</string>
+ <string>XCModuleDock</string>
+ <string>PBXNavigatorGroup</string>
+ <string>XCDetailModule</string>
+ </array>
+ <key>TableOfContents</key>
+ <array>
+ <string>0292B6200CDA9CFD00A3A500</string>
+ <string>1CE0B1FE06471DED0097A5F4</string>
+ <string>0292B6210CDA9CFD00A3A500</string>
+ <string>1CE0B20306471E060097A5F4</string>
+ <string>1CE0B20506471E060097A5F4</string>
+ </array>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.default</string>
+ </dict>
+ <dict>
+ <key>ControllerClassBaseName</key>
+ <string></string>
+ <key>IconName</key>
+ <string>WindowOfProject</string>
+ <key>Identifier</key>
+ <string>perspective.morph</string>
+ <key>IsVertical</key>
+ <integer>0</integer>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>BecomeActive</key>
+ <integer>1</integer>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXBottomSmartGroupGIDs</key>
+ <array>
+ <string>1C37FBAC04509CD000000102</string>
+ <string>1C37FAAC04509CD000000102</string>
+ <string>1C08E77C0454961000C914BD</string>
+ <string>1C37FABC05509CD000000102</string>
+ <string>1C37FABC05539CD112110102</string>
+ <string>E2644B35053B69B200211256</string>
+ <string>1C37FABC04509CD000100104</string>
+ <string>1CC0EA4004350EF90044410B</string>
+ <string>1CC0EA4004350EF90041110B</string>
+ </array>
+ <key>PBXProjectModuleGUID</key>
+ <string>11E0B1FE06471DED0097A5F4</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Files</string>
+ <key>PBXProjectStructureProvided</key>
+ <string>yes</string>
+ <key>PBXSmartGroupTreeModuleColumnData</key>
+ <dict>
+ <key>PBXSmartGroupTreeModuleColumnWidthsKey</key>
+ <array>
+ <real>186</real>
+ </array>
+ <key>PBXSmartGroupTreeModuleColumnsKey_v4</key>
+ <array>
+ <string>MainColumn</string>
+ </array>
+ </dict>
+ <key>PBXSmartGroupTreeModuleOutlineStateKey_v7</key>
+ <dict>
+ <key>PBXSmartGroupTreeModuleOutlineStateExpansionKey</key>
+ <array>
+ <string>29B97314FDCFA39411CA2CEA</string>
+ <string>1C37FABC05509CD000000102</string>
+ </array>
+ <key>PBXSmartGroupTreeModuleOutlineStateSelectionKey</key>
+ <array>
+ <array>
+ <integer>0</integer>
+ </array>
+ </array>
+ <key>PBXSmartGroupTreeModuleOutlineStateVisibleRectKey</key>
+ <string>{{0, 0}, {186, 337}}</string>
+ </dict>
+ <key>PBXTopSmartGroupGIDs</key>
+ <array/>
+ <key>XCIncludePerspectivesSwitch</key>
+ <integer>1</integer>
+ <key>XCSharingToken</key>
+ <string>com.apple.Xcode.GFSharingToken</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {203, 355}}</string>
+ <key>GroupTreeTableConfiguration</key>
+ <array>
+ <string>MainColumn</string>
+ <real>186</real>
+ </array>
+ <key>RubberWindowFrame</key>
+ <string>373 269 690 397 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXSmartGroupTreeModule</string>
+ <key>Proportion</key>
+ <string>100%</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Morph</string>
+ <key>PreferredWidth</key>
+ <integer>300</integer>
+ <key>ServiceClasses</key>
+ <array>
+ <string>XCModuleDock</string>
+ <string>PBXSmartGroupTreeModule</string>
+ </array>
+ <key>TableOfContents</key>
+ <array>
+ <string>11E0B1FE06471DED0097A5F4</string>
+ </array>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.default.short</string>
+ </dict>
+ </array>
+ <key>PerspectivesBarVisible</key>
+ <false/>
+ <key>ShelfIsVisible</key>
+ <false/>
+ <key>SourceDescription</key>
+ <string>file at '/System/Library/PrivateFrameworks/DevToolsInterface.framework/Versions/A/Resources/XCPerspectivesSpecificationMode1.xcperspec'</string>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>TimeStamp</key>
+ <real>215653629.27717999</real>
+ <key>ToolbarDisplayMode</key>
+ <integer>2</integer>
+ <key>ToolbarIsVisible</key>
+ <true/>
+ <key>ToolbarSizeMode</key>
+ <integer>2</integer>
+ <key>Type</key>
+ <string>Perspectives</string>
+ <key>UpdateMessage</key>
+ <string>The Default Workspace in this version of Xcode now includes support to hide and show the detail view (what has been referred to as the "Metro-Morph" feature). You must discard your current Default Workspace settings and update to the latest Default Workspace in order to gain this feature. Do you wish to update to the latest Workspace defaults for project '%@'?</string>
+ <key>WindowJustification</key>
+ <integer>5</integer>
+ <key>WindowOrderList</key>
+ <array>
+ <string>0292B6220CDA9CFD00A3A500</string>
+ <string>0292B6230CDA9CFD00A3A500</string>
+ <string>02CD175D09F6CC1200ABE650</string>
+ <string>0292B5F70CD9689200A3A500</string>
+ <string>0246B8AB09C37E4E009A0CA3</string>
+ <string>1CD10A99069EF8BA00B06720</string>
+ <string>/Users/creed/projects/sgtl/elftosb/elftosb.xcodeproj</string>
+ <string>1C0AD2B3069F1EA900FABCE6</string>
+ </array>
+ <key>WindowString</key>
+ <string>8 33 1079 845 0 0 1440 878 </string>
+ <key>WindowTools</key>
+ <array>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.build</string>
+ <key>IsVertical</key>
+ <true/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CD0528F0623707200166675</string>
+ <key>PBXProjectModuleLabel</key>
+ <string></string>
+ <key>StatusBarVisibility</key>
+ <true/>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {744, 0}}</string>
+ <key>RubberWindowFrame</key>
+ <string>566 98 744 502 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXNavigatorGroup</string>
+ <key>Proportion</key>
+ <string>0pt</string>
+ </dict>
+ <dict>
+ <key>BecomeActive</key>
+ <true/>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXBuildLogShowsTranscriptDefaultKey</key>
+ <string>{{0, 207}, {744, 249}}</string>
+ <key>PBXProjectModuleGUID</key>
+ <string>XCMainBuildResultsModuleGUID</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Build</string>
+ <key>XCBuildResultsTrigger_Collapse</key>
+ <integer>1022</integer>
+ <key>XCBuildResultsTrigger_Open</key>
+ <integer>1010</integer>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 5}, {744, 456}}</string>
+ <key>RubberWindowFrame</key>
+ <string>566 98 744 502 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXBuildResultsModule</string>
+ <key>Proportion</key>
+ <string>456pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>461pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Build Results</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXBuildResultsModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>TableOfContents</key>
+ <array>
+ <string>0246B8AB09C37E4E009A0CA3</string>
+ <string>0292B5ED0CD9677200A3A500</string>
+ <string>1CD0528F0623707200166675</string>
+ <string>XCMainBuildResultsModuleGUID</string>
+ </array>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.build</string>
+ <key>WindowString</key>
+ <string>566 98 744 502 0 0 1440 878 </string>
+ <key>WindowToolGUID</key>
+ <string>0246B8AB09C37E4E009A0CA3</string>
+ <key>WindowToolIsVisible</key>
+ <false/>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.debugger</string>
+ <key>IsVertical</key>
+ <true/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>Debugger</key>
+ <dict>
+ <key>HorizontalSplitView</key>
+ <dict>
+ <key>_collapsingFrameDimension</key>
+ <real>0.0</real>
+ <key>_indexOfCollapsedView</key>
+ <integer>0</integer>
+ <key>_percentageOfCollapsedView</key>
+ <real>0.0</real>
+ <key>isCollapsed</key>
+ <string>yes</string>
+ <key>sizes</key>
+ <array>
+ <string>{{0, 0}, {307, 301}}</string>
+ <string>{{0, 301}, {307, 480}}</string>
+ </array>
+ </dict>
+ <key>VerticalSplitView</key>
+ <dict>
+ <key>_collapsingFrameDimension</key>
+ <real>0.0</real>
+ <key>_indexOfCollapsedView</key>
+ <integer>0</integer>
+ <key>_percentageOfCollapsedView</key>
+ <real>0.0</real>
+ <key>isCollapsed</key>
+ <string>yes</string>
+ <key>sizes</key>
+ <array>
+ <string>{{0, 0}, {307, 781}}</string>
+ <string>{{307, 0}, {792, 781}}</string>
+ </array>
+ </dict>
+ </dict>
+ <key>LauncherConfigVersion</key>
+ <string>8</string>
+ <key>PBXProjectModuleGUID</key>
+ <string>1C162984064C10D400B95A72</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Debug - GLUTExamples (Underwater)</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>DebugConsoleDrawerSize</key>
+ <string>{100, 120}</string>
+ <key>DebugConsoleVisible</key>
+ <string>None</string>
+ <key>DebugConsoleWindowFrame</key>
+ <string>{{200, 200}, {500, 300}}</string>
+ <key>DebugSTDIOWindowFrame</key>
+ <string>{{200, 200}, {500, 300}}</string>
+ <key>Frame</key>
+ <string>{{0, 0}, {1099, 781}}</string>
+ <key>RubberWindowFrame</key>
+ <string>142 56 1099 822 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXDebugSessionModule</string>
+ <key>Proportion</key>
+ <string>781pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>781pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Debugger</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXDebugSessionModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>TableOfContents</key>
+ <array>
+ <string>1CD10A99069EF8BA00B06720</string>
+ <string>0292B5F10CD9689200A3A500</string>
+ <string>1C162984064C10D400B95A72</string>
+ <string>0292B5F20CD9689200A3A500</string>
+ <string>0292B5F30CD9689200A3A500</string>
+ <string>0292B5F40CD9689200A3A500</string>
+ <string>0292B5F50CD9689200A3A500</string>
+ <string>0292B5F60CD9689200A3A500</string>
+ <string>0292B5F70CD9689200A3A500</string>
+ </array>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.debug</string>
+ <key>WindowString</key>
+ <string>142 56 1099 822 0 0 1440 878 </string>
+ <key>WindowToolGUID</key>
+ <string>1CD10A99069EF8BA00B06720</string>
+ <key>WindowToolIsVisible</key>
+ <true/>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.find</string>
+ <key>IsVertical</key>
+ <true/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>BecomeActive</key>
+ <true/>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CDD528C0622207200134675</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>SourceFile.cpp</string>
+ <key>StatusBarVisibility</key>
+ <true/>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {792, 405}}</string>
+ <key>RubberWindowFrame</key>
+ <string>387 14 792 854 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXNavigatorGroup</string>
+ <key>Proportion</key>
+ <string>792pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>405pt</string>
+ </dict>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CD0528E0623707200166675</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Project Find</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 410}, {792, 403}}</string>
+ <key>RubberWindowFrame</key>
+ <string>387 14 792 854 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXProjectFindModule</string>
+ <key>Proportion</key>
+ <string>403pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>813pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Project Find</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXProjectFindModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>TableOfContents</key>
+ <array>
+ <string>1C530D57069F1CE1000CFCEE</string>
+ <string>02D1FD080BD039AB007C7450</string>
+ <string>02D1FD090BD039AB007C7450</string>
+ <string>1CDD528C0622207200134675</string>
+ <string>1CD0528E0623707200166675</string>
+ </array>
+ <key>WindowString</key>
+ <string>387 14 792 854 0 0 1440 878 </string>
+ <key>WindowToolGUID</key>
+ <string>1C530D57069F1CE1000CFCEE</string>
+ <key>WindowToolIsVisible</key>
+ <true/>
+ </dict>
+ <dict>
+ <key>Identifier</key>
+ <string>MENUSEPARATOR</string>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.debuggerConsole</string>
+ <key>IsVertical</key>
+ <true/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1C78EAAC065D492600B07095</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Debugger Console</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {440, 358}}</string>
+ <key>RubberWindowFrame</key>
+ <string>928 1 440 400 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXDebugCLIModule</string>
+ <key>Proportion</key>
+ <string>358pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>359pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Debugger Console</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXDebugCLIModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>TableOfContents</key>
+ <array>
+ <string>02CD175D09F6CC1200ABE650</string>
+ <string>0292B5F80CD9689200A3A500</string>
+ <string>1C78EAAC065D492600B07095</string>
+ </array>
+ <key>WindowString</key>
+ <string>928 1 440 400 0 0 1440 878 </string>
+ <key>WindowToolGUID</key>
+ <string>02CD175D09F6CC1200ABE650</string>
+ <key>WindowToolIsVisible</key>
+ <false/>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.run</string>
+ <key>IsVertical</key>
+ <true/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>LauncherConfigVersion</key>
+ <string>3</string>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CD0528B0623707200166675</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Run</string>
+ <key>Runner</key>
+ <dict>
+ <key>HorizontalSplitView</key>
+ <dict>
+ <key>_collapsingFrameDimension</key>
+ <real>0.0</real>
+ <key>_indexOfCollapsedView</key>
+ <integer>0</integer>
+ <key>_percentageOfCollapsedView</key>
+ <real>0.0</real>
+ <key>isCollapsed</key>
+ <string>yes</string>
+ <key>sizes</key>
+ <array>
+ <string>{{0, 0}, {367, 168}}</string>
+ <string>{{0, 173}, {367, 270}}</string>
+ </array>
+ </dict>
+ <key>VerticalSplitView</key>
+ <dict>
+ <key>_collapsingFrameDimension</key>
+ <real>0.0</real>
+ <key>_indexOfCollapsedView</key>
+ <integer>0</integer>
+ <key>_percentageOfCollapsedView</key>
+ <real>0.0</real>
+ <key>isCollapsed</key>
+ <string>yes</string>
+ <key>sizes</key>
+ <array>
+ <string>{{0, 0}, {406, 443}}</string>
+ <string>{{411, 0}, {517, 443}}</string>
+ </array>
+ </dict>
+ </dict>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {662, 502}}</string>
+ <key>RubberWindowFrame</key>
+ <string>708 293 662 543 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXRunSessionModule</string>
+ <key>Proportion</key>
+ <string>502pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>502pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Run Log</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXRunSessionModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>TableOfContents</key>
+ <array>
+ <string>1C0AD2B3069F1EA900FABCE6</string>
+ <string>0292B5F90CD9689200A3A500</string>
+ <string>1CD0528B0623707200166675</string>
+ <string>0292B5FA0CD9689200A3A500</string>
+ </array>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.run</string>
+ <key>WindowString</key>
+ <string>708 293 662 543 0 0 1440 878 </string>
+ <key>WindowToolGUID</key>
+ <string>1C0AD2B3069F1EA900FABCE6</string>
+ <key>WindowToolIsVisible</key>
+ <true/>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.scm</string>
+ <key>IsVertical</key>
+ <true/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1C78EAB2065D492600B07095</string>
+ <key>PBXProjectModuleLabel</key>
+ <string></string>
+ <key>StatusBarVisibility</key>
+ <true/>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {452, 0}}</string>
+ <key>RubberWindowFrame</key>
+ <string>30 547 452 308 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXNavigatorGroup</string>
+ <key>Proportion</key>
+ <string>0pt</string>
+ </dict>
+ <dict>
+ <key>BecomeActive</key>
+ <true/>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CD052920623707200166675</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>SCM Results</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 5}, {452, 262}}</string>
+ <key>RubberWindowFrame</key>
+ <string>30 547 452 308 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXCVSModule</string>
+ <key>Proportion</key>
+ <string>262pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>267pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>SCM</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXCVSModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>TableOfContents</key>
+ <array>
+ <string>02FE643D0BF793B0004A1450</string>
+ <string>02FE643E0BF793B0004A1450</string>
+ <string>1C78EAB2065D492600B07095</string>
+ <string>1CD052920623707200166675</string>
+ </array>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.scm</string>
+ <key>WindowString</key>
+ <string>30 547 452 308 0 0 1440 878 </string>
+ <key>WindowToolGUID</key>
+ <string>02FE643D0BF793B0004A1450</string>
+ <key>WindowToolIsVisible</key>
+ <false/>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.breakpoints</string>
+ <key>IsVertical</key>
+ <false/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXBottomSmartGroupGIDs</key>
+ <array>
+ <string>1C77FABC04509CD000000102</string>
+ </array>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CE0B1FE06471DED0097A5F4</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Files</string>
+ <key>PBXProjectStructureProvided</key>
+ <string>no</string>
+ <key>PBXSmartGroupTreeModuleColumnData</key>
+ <dict>
+ <key>PBXSmartGroupTreeModuleColumnWidthsKey</key>
+ <array>
+ <real>168</real>
+ </array>
+ <key>PBXSmartGroupTreeModuleColumnsKey_v4</key>
+ <array>
+ <string>MainColumn</string>
+ </array>
+ </dict>
+ <key>PBXSmartGroupTreeModuleOutlineStateKey_v7</key>
+ <dict>
+ <key>PBXSmartGroupTreeModuleOutlineStateExpansionKey</key>
+ <array>
+ <string>1C77FABC04509CD000000102</string>
+ <string>1C3E0DCA080725EA00A55177</string>
+ </array>
+ <key>PBXSmartGroupTreeModuleOutlineStateSelectionKey</key>
+ <array>
+ <array>
+ <integer>0</integer>
+ </array>
+ </array>
+ <key>PBXSmartGroupTreeModuleOutlineStateVisibleRectKey</key>
+ <string>{{0, 0}, {168, 350}}</string>
+ </dict>
+ <key>PBXTopSmartGroupGIDs</key>
+ <array/>
+ <key>XCIncludePerspectivesSwitch</key>
+ <false/>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {185, 368}}</string>
+ <key>GroupTreeTableConfiguration</key>
+ <array>
+ <string>MainColumn</string>
+ <real>168</real>
+ </array>
+ <key>RubberWindowFrame</key>
+ <string>28 375 744 409 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXSmartGroupTreeModule</string>
+ <key>Proportion</key>
+ <string>185pt</string>
+ </dict>
+ <dict>
+ <key>BecomeActive</key>
+ <true/>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CA1AED706398EBD00589147</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Detail</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{190, 0}, {554, 368}}</string>
+ <key>RubberWindowFrame</key>
+ <string>28 375 744 409 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>XCDetailModule</string>
+ <key>Proportion</key>
+ <string>554pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>368pt</string>
+ </dict>
+ </array>
+ <key>MajorVersion</key>
+ <integer>2</integer>
+ <key>MinorVersion</key>
+ <integer>0</integer>
+ <key>Name</key>
+ <string>Breakpoints</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXSmartGroupTreeModule</string>
+ <string>XCDetailModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>TableOfContents</key>
+ <array>
+ <string>027EE4730BD6D24700A6A136</string>
+ <string>027EE4740BD6D24700A6A136</string>
+ <string>1CE0B1FE06471DED0097A5F4</string>
+ <string>1CA1AED706398EBD00589147</string>
+ </array>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.breakpoints</string>
+ <key>WindowString</key>
+ <string>28 375 744 409 0 0 1440 878 </string>
+ <key>WindowToolGUID</key>
+ <string>027EE4730BD6D24700A6A136</string>
+ <key>WindowToolIsVisible</key>
+ <false/>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.debugAnimator</string>
+ <key>IsVertical</key>
+ <true/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>BecomeActive</key>
+ <true/>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>02E39A7909F721C80055992A</string>
+ <key>PBXProjectModuleLabel</key>
+ <string></string>
+ <key>StatusBarVisibility</key>
+ <true/>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {700, 459}}</string>
+ <key>RubberWindowFrame</key>
+ <string>36 211 700 500 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXNavigatorGroup</string>
+ <key>Proportion</key>
+ <string>459pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>459pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Debug Visualizer</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXNavigatorGroup</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>TableOfContents</key>
+ <array>
+ <string>027EE4660BD6CDCB00A6A136</string>
+ <string>027EE4670BD6CDCB00A6A136</string>
+ <string>02E39A7909F721C80055992A</string>
+ </array>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.debugAnimator</string>
+ <key>WindowString</key>
+ <string>36 211 700 500 0 0 1440 878 </string>
+ <key>WindowToolGUID</key>
+ <string>027EE4660BD6CDCB00A6A136</string>
+ <key>WindowToolIsVisible</key>
+ <false/>
+ </dict>
+ <dict>
+ <key>Identifier</key>
+ <string>windowTool.bookmarks</string>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>Module</key>
+ <string>PBXBookmarksModule</string>
+ <key>Proportion</key>
+ <string>100%</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>100%</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Bookmarks</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXBookmarksModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <integer>0</integer>
+ <key>WindowString</key>
+ <string>538 42 401 187 0 0 1280 1002 </string>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.classBrowser</string>
+ <key>IsVertical</key>
+ <true/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>OptionsSetName</key>
+ <string>Hierarchy, project classes</string>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CA6456E063B45B4001379D8</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Class Browser - RijndaelCBCMAC</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>ClassesFrame</key>
+ <string>{{0, 0}, {759, 298}}</string>
+ <key>ClassesTreeTableConfiguration</key>
+ <array>
+ <string>PBXClassNameColumnIdentifier</string>
+ <real>208</real>
+ <string>PBXClassBookColumnIdentifier</string>
+ <real>22</real>
+ </array>
+ <key>Frame</key>
+ <string>{{0, 0}, {1011, 802}}</string>
+ <key>MembersFrame</key>
+ <string>{{0, 303}, {759, 499}}</string>
+ <key>MembersTreeTableConfiguration</key>
+ <array>
+ <string>PBXMemberTypeIconColumnIdentifier</string>
+ <real>22</real>
+ <string>PBXMemberNameColumnIdentifier</string>
+ <real>216</real>
+ <string>PBXMemberTypeColumnIdentifier</string>
+ <real>482</real>
+ <string>PBXMemberBookColumnIdentifier</string>
+ <real>22</real>
+ </array>
+ <key>RubberWindowFrame</key>
+ <string>159 56 1011 822 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXClassBrowserModule</string>
+ <key>Proportion</key>
+ <string>802pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>802pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Class Browser</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXClassBrowserModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <false/>
+ <key>TableOfContents</key>
+ <array>
+ <string>1C0AD2AF069F1E9B00FABCE6</string>
+ <string>027EE3B20BD5CE9600A6A136</string>
+ <string>1CA6456E063B45B4001379D8</string>
+ </array>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.classbrowser</string>
+ <key>WindowString</key>
+ <string>159 56 1011 822 0 0 1440 878 </string>
+ <key>WindowToolGUID</key>
+ <string>1C0AD2AF069F1E9B00FABCE6</string>
+ <key>WindowToolIsVisible</key>
+ <false/>
+ </dict>
+ </array>
+</dict>
+</plist>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
+<plist version="1.0">
+<dict>
+ <key>ActivePerspectiveName</key>
+ <string>Project</string>
+ <key>AllowedModules</key>
+ <array>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>PBXSmartGroupTreeModule</string>
+ <key>Name</key>
+ <string>Groups and Files Outline View</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>PBXNavigatorGroup</string>
+ <key>Name</key>
+ <string>Editor</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>XCTaskListModule</string>
+ <key>Name</key>
+ <string>Task List</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>XCDetailModule</string>
+ <key>Name</key>
+ <string>File and Smart Group Detail Viewer</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>1</string>
+ <key>Module</key>
+ <string>PBXBuildResultsModule</string>
+ <key>Name</key>
+ <string>Detailed Build Results Viewer</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>1</string>
+ <key>Module</key>
+ <string>PBXProjectFindModule</string>
+ <key>Name</key>
+ <string>Project Batch Find Tool</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>XCProjectFormatConflictsModule</string>
+ <key>Name</key>
+ <string>Project Format Conflicts List</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>PBXBookmarksModule</string>
+ <key>Name</key>
+ <string>Bookmarks Tool</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>PBXClassBrowserModule</string>
+ <key>Name</key>
+ <string>Class Browser</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>PBXCVSModule</string>
+ <key>Name</key>
+ <string>Source Code Control Tool</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>PBXDebugBreakpointsModule</string>
+ <key>Name</key>
+ <string>Debug Breakpoints Tool</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>XCDockableInspector</string>
+ <key>Name</key>
+ <string>Inspector</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>PBXOpenQuicklyModule</string>
+ <key>Name</key>
+ <string>Open Quickly Tool</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>1</string>
+ <key>Module</key>
+ <string>PBXDebugSessionModule</string>
+ <key>Name</key>
+ <string>Debugger</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>1</string>
+ <key>Module</key>
+ <string>PBXDebugCLIModule</string>
+ <key>Name</key>
+ <string>Debug Console</string>
+ </dict>
+ <dict>
+ <key>BundleLoadPath</key>
+ <string></string>
+ <key>MaxInstances</key>
+ <string>n</string>
+ <key>Module</key>
+ <string>XCSnapshotModule</string>
+ <key>Name</key>
+ <string>Snapshots Tool</string>
+ </dict>
+ </array>
+ <key>Description</key>
+ <string>DefaultDescriptionKey</string>
+ <key>DockingSystemVisible</key>
+ <false/>
+ <key>Extension</key>
+ <string>mode1v3</string>
+ <key>FavBarConfig</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>025881920CF13C0400681C7E</string>
+ <key>XCBarModuleItemNames</key>
+ <dict/>
+ <key>XCBarModuleItems</key>
+ <array/>
+ </dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>com.apple.perspectives.project.mode1v3</string>
+ <key>MajorVersion</key>
+ <integer>33</integer>
+ <key>MinorVersion</key>
+ <integer>0</integer>
+ <key>Name</key>
+ <string>Default</string>
+ <key>Notifications</key>
+ <array>
+ <dict>
+ <key>XCObserverAutoDisconnectKey</key>
+ <true/>
+ <key>XCObserverDefintionKey</key>
+ <dict/>
+ <key>XCObserverFactoryKey</key>
+ <string>XCPerspectivesSpecificationIdentifier</string>
+ <key>XCObserverGUIDKey</key>
+ <string>XCObserverProjectIdentifier</string>
+ <key>XCObserverNotificationKey</key>
+ <string>PBXStatusBuildStateMessageNotification</string>
+ <key>XCObserverTargetKey</key>
+ <string>XCMainBuildResultsModuleGUID</string>
+ <key>XCObserverTriggerKey</key>
+ <string>awakenModuleWithObserver:</string>
+ <key>XCObserverValidationKey</key>
+ <dict/>
+ </dict>
+ </array>
+ <key>OpenEditors</key>
+ <array/>
+ <key>PerspectiveWidths</key>
+ <array>
+ <integer>1079</integer>
+ <integer>300</integer>
+ </array>
+ <key>Perspectives</key>
+ <array>
+ <dict>
+ <key>ChosenToolbarItems</key>
+ <array>
+ <string>active-combo-popup</string>
+ <string>action</string>
+ <string>NSToolbarFlexibleSpaceItem</string>
+ <string>debugger-enable-breakpoints</string>
+ <string>build-and-go</string>
+ <string>buildOrClean</string>
+ <string>com.apple.ide.PBXToolbarStopButton</string>
+ <string>get-info</string>
+ <string>show-inspector</string>
+ <string>NSToolbarFlexibleSpaceItem</string>
+ <string>servicesModuleCVS</string>
+ <string>servicesModuledebug</string>
+ <string>servicesModulebreakpoints</string>
+ <string>servicesModulefind</string>
+ <string>com.apple.pbx.toolbar.searchfield</string>
+ </array>
+ <key>ControllerClassBaseName</key>
+ <string></string>
+ <key>IconName</key>
+ <string>WindowOfProjectWithEditor</string>
+ <key>Identifier</key>
+ <string>perspective.project</string>
+ <key>IsVertical</key>
+ <false/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXBottomSmartGroupGIDs</key>
+ <array>
+ <string>1C37FBAC04509CD000000102</string>
+ <string>1C37FAAC04509CD000000102</string>
+ <string>1C37FABC05509CD000000102</string>
+ <string>1C37FABC05539CD112110102</string>
+ <string>E2644B35053B69B200211256</string>
+ <string>1C37FABC04509CD000100104</string>
+ <string>1CC0EA4004350EF90044410B</string>
+ <string>1CC0EA4004350EF90041110B</string>
+ </array>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CE0B1FE06471DED0097A5F4</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Files</string>
+ <key>PBXProjectStructureProvided</key>
+ <string>yes</string>
+ <key>PBXSmartGroupTreeModuleColumnData</key>
+ <dict>
+ <key>PBXSmartGroupTreeModuleColumnWidthsKey</key>
+ <array>
+ <real>22</real>
+ <real>22</real>
+ <real>260</real>
+ </array>
+ <key>PBXSmartGroupTreeModuleColumnsKey_v4</key>
+ <array>
+ <string>TargetStatusColumn</string>
+ <string>SCMStatusColumn</string>
+ <string>MainColumn</string>
+ </array>
+ </dict>
+ <key>PBXSmartGroupTreeModuleOutlineStateKey_v7</key>
+ <dict>
+ <key>PBXSmartGroupTreeModuleOutlineStateExpansionKey</key>
+ <array>
+ <string>08FB7794FE84155DC02AAC07</string>
+ <string>02FE65020BFE669B004A1450</string>
+ <string>08FB7795FE84155DC02AAC07</string>
+ <string>0296A45909D9AE9400F80AFF</string>
+ <string>02D46C140FED492C00E65706</string>
+ <string>020D47700A1691F10027E24E</string>
+ <string>1C37FAAC04509CD000000102</string>
+ <string>1C37FABC05509CD000000102</string>
+ </array>
+ <key>PBXSmartGroupTreeModuleOutlineStateSelectionKey</key>
+ <array>
+ <array>
+ <integer>26</integer>
+ <integer>11</integer>
+ <integer>7</integer>
+ <integer>0</integer>
+ </array>
+ </array>
+ <key>PBXSmartGroupTreeModuleOutlineStateVisibleRectKey</key>
+ <string>{{0, 44}, {304, 1080}}</string>
+ </dict>
+ <key>PBXTopSmartGroupGIDs</key>
+ <array/>
+ <key>XCIncludePerspectivesSwitch</key>
+ <true/>
+ <key>XCSharingToken</key>
+ <string>com.apple.Xcode.GFSharingToken</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {321, 1098}}</string>
+ <key>GroupTreeTableConfiguration</key>
+ <array>
+ <string>TargetStatusColumn</string>
+ <real>22</real>
+ <string>SCMStatusColumn</string>
+ <real>22</real>
+ <string>MainColumn</string>
+ <real>260</real>
+ </array>
+ <key>RubberWindowFrame</key>
+ <string>19 39 1197 1139 0 0 1920 1178 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXSmartGroupTreeModule</string>
+ <key>Proportion</key>
+ <string>321pt</string>
+ </dict>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>BecomeActive</key>
+ <true/>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CE0B20306471E060097A5F4</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>elftosb.cpp</string>
+ <key>PBXSplitModuleInNavigatorKey</key>
+ <dict>
+ <key>Split0</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CE0B20406471E060097A5F4</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>elftosb.cpp</string>
+ <key>_historyCapacity</key>
+ <integer>0</integer>
+ <key>bookmark</key>
+ <string>022B47721218CDBF00A74F96</string>
+ <key>history</key>
+ <array>
+ <string>021CA4400A8D2F740028326F</string>
+ <string>021CA4420A8D2F740028326F</string>
+ <string>02C5DBD20A926A7F003B9C11</string>
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+ <string>02C5DD520A93D327003B9C11</string>
+ <string>02C5DDCD0A940126003B9C11</string>
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+ <string>022B47281218C17F00A74F96</string>
+ <string>022B47391218C46A00A74F96</string>
+ <string>022B473A1218C46A00A74F96</string>
+ <string>022B474B1218CA9A00A74F96</string>
+ <string>022B474C1218CA9A00A74F96</string>
+ <string>022B476F1218CDBF00A74F96</string>
+ <string>022B47701218CDBF00A74F96</string>
+ <string>022B47711218CDBF00A74F96</string>
+ </array>
+ </dict>
+ <key>SplitCount</key>
+ <string>1</string>
+ </dict>
+ <key>StatusBarVisibility</key>
+ <true/>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {871, 1093}}</string>
+ <key>RubberWindowFrame</key>
+ <string>19 39 1197 1139 0 0 1920 1178 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXNavigatorGroup</string>
+ <key>Proportion</key>
+ <string>1093pt</string>
+ </dict>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CE0B20506471E060097A5F4</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Detail</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 1098}, {871, 0}}</string>
+ <key>RubberWindowFrame</key>
+ <string>19 39 1197 1139 0 0 1920 1178 </string>
+ </dict>
+ <key>Module</key>
+ <string>XCDetailModule</string>
+ <key>Proportion</key>
+ <string>0pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>871pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Project</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>XCModuleDock</string>
+ <string>PBXSmartGroupTreeModule</string>
+ <string>XCModuleDock</string>
+ <string>PBXNavigatorGroup</string>
+ <string>XCDetailModule</string>
+ </array>
+ <key>TableOfContents</key>
+ <array>
+ <string>022B46261216FEA700A74F96</string>
+ <string>1CE0B1FE06471DED0097A5F4</string>
+ <string>022B46271216FEA700A74F96</string>
+ <string>1CE0B20306471E060097A5F4</string>
+ <string>1CE0B20506471E060097A5F4</string>
+ </array>
+ <key>ToolbarConfigUserDefaultsMinorVersion</key>
+ <string>2</string>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.defaultV3</string>
+ </dict>
+ <dict>
+ <key>ChosenToolbarItems</key>
+ <array>
+ <string>XCToolbarPerspectiveControl</string>
+ <string>NSToolbarSeparatorItem</string>
+ <string>buildOrClean</string>
+ <string>build-and-goOrGo</string>
+ <string>debugger-enable-breakpoints</string>
+ <string>com.apple.ide.PBXToolbarStopButton</string>
+ <string>NSToolbarFlexibleSpaceItem</string>
+ <string>get-info</string>
+ </array>
+ <key>ControllerClassBaseName</key>
+ <string></string>
+ <key>IconName</key>
+ <string>WindowOfProject</string>
+ <key>Identifier</key>
+ <string>perspective.morph</string>
+ <key>IsVertical</key>
+ <false/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXBottomSmartGroupGIDs</key>
+ <array>
+ <string>1C37FBAC04509CD000000102</string>
+ <string>1C37FAAC04509CD000000102</string>
+ <string>1C08E77C0454961000C914BD</string>
+ <string>1C37FABC05509CD000000102</string>
+ <string>1C37FABC05539CD112110102</string>
+ <string>E2644B35053B69B200211256</string>
+ <string>1C37FABC04509CD000100104</string>
+ <string>1CC0EA4004350EF90044410B</string>
+ <string>1CC0EA4004350EF90041110B</string>
+ </array>
+ <key>PBXProjectModuleGUID</key>
+ <string>11E0B1FE06471DED0097A5F4</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Files</string>
+ <key>PBXProjectStructureProvided</key>
+ <string>yes</string>
+ <key>PBXSmartGroupTreeModuleColumnData</key>
+ <dict>
+ <key>PBXSmartGroupTreeModuleColumnWidthsKey</key>
+ <array>
+ <real>22</real>
+ <real>22</real>
+ <real>239</real>
+ </array>
+ <key>PBXSmartGroupTreeModuleColumnsKey_v4</key>
+ <array>
+ <string>TargetStatusColumn</string>
+ <string>SCMStatusColumn</string>
+ <string>MainColumn</string>
+ </array>
+ </dict>
+ <key>PBXSmartGroupTreeModuleOutlineStateKey_v7</key>
+ <dict>
+ <key>PBXSmartGroupTreeModuleOutlineStateExpansionKey</key>
+ <array>
+ <string>08FB7794FE84155DC02AAC07</string>
+ <string>02FE65020BFE669B004A1450</string>
+ <string>08FB7795FE84155DC02AAC07</string>
+ <string>0296A45909D9AE9400F80AFF</string>
+ <string>020D47700A1691F10027E24E</string>
+ <string>1C37FBAC04509CD000000102</string>
+ <string>1C37FAAC04509CD000000102</string>
+ <string>1C37FABC05509CD000000102</string>
+ </array>
+ <key>PBXSmartGroupTreeModuleOutlineStateSelectionKey</key>
+ <array>
+ <array>
+ <integer>42</integer>
+ <integer>7</integer>
+ <integer>0</integer>
+ </array>
+ </array>
+ <key>PBXSmartGroupTreeModuleOutlineStateVisibleRectKey</key>
+ <string>{{0, 0}, {283, 782}}</string>
+ </dict>
+ <key>PBXTopSmartGroupGIDs</key>
+ <array/>
+ <key>XCIncludePerspectivesSwitch</key>
+ <true/>
+ <key>XCSharingToken</key>
+ <string>com.apple.Xcode.GFSharingToken</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {300, 800}}</string>
+ <key>GroupTreeTableConfiguration</key>
+ <array>
+ <string>TargetStatusColumn</string>
+ <real>22</real>
+ <string>SCMStatusColumn</string>
+ <real>22</real>
+ <string>MainColumn</string>
+ <real>239</real>
+ </array>
+ </dict>
+ <key>Module</key>
+ <string>PBXSmartGroupTreeModule</string>
+ <key>Proportion</key>
+ <string>300pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Morph</string>
+ <key>PreferredWidth</key>
+ <integer>300</integer>
+ <key>ServiceClasses</key>
+ <array>
+ <string>XCModuleDock</string>
+ <string>PBXSmartGroupTreeModule</string>
+ </array>
+ <key>TableOfContents</key>
+ <array>
+ <string>025881910CF13C0400681C7E</string>
+ <string>11E0B1FE06471DED0097A5F4</string>
+ </array>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.default.shortV3</string>
+ </dict>
+ </array>
+ <key>PerspectivesBarVisible</key>
+ <false/>
+ <key>ShelfIsVisible</key>
+ <false/>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>TimeStamp</key>
+ <real>303615423.96806198</real>
+ <key>ToolbarDisplayMode</key>
+ <integer>2</integer>
+ <key>ToolbarIsVisible</key>
+ <true/>
+ <key>ToolbarSizeMode</key>
+ <integer>1</integer>
+ <key>Type</key>
+ <string>Perspectives</string>
+ <key>UpdateMessage</key>
+ <string>The Default Workspace in this version of Xcode now includes support to hide and show the detail view (what has been referred to as the "Metro-Morph" feature). You must discard your current Default Workspace settings and update to the latest Default Workspace in order to gain this feature. Do you wish to update to the latest Workspace defaults for project '%@'?</string>
+ <key>WindowJustification</key>
+ <integer>5</integer>
+ <key>WindowOrderList</key>
+ <array>
+ <string>022B46991218659A00A74F96</string>
+ <string>022B469A1218659A00A74F96</string>
+ <string>02D46D160FED80AF00E65706</string>
+ <string>1CD10A99069EF8BA00B06720</string>
+ <string>1C530D57069F1CE1000CFCEE</string>
+ <string>025880F00CEE3D1200681C7E</string>
+ <string>/Users/creed/projects/fsl/fromsvr/elftosb/elftosb.xcodeproj</string>
+ <string>1C78EAAD065D492600B07095</string>
+ </array>
+ <key>WindowString</key>
+ <string>19 39 1197 1139 0 0 1920 1178 </string>
+ <key>WindowToolsV3</key>
+ <array>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.build</string>
+ <key>IsVertical</key>
+ <true/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CD0528F0623707200166675</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>ElftosbAST.cpp</string>
+ <key>StatusBarVisibility</key>
+ <true/>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {744, 171}}</string>
+ <key>RubberWindowFrame</key>
+ <string>1048 148 744 502 0 0 1920 1178 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXNavigatorGroup</string>
+ <key>Proportion</key>
+ <string>171pt</string>
+ </dict>
+ <dict>
+ <key>BecomeActive</key>
+ <true/>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>XCMainBuildResultsModuleGUID</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Build Results</string>
+ <key>XCBuildResultsTrigger_Collapse</key>
+ <integer>1022</integer>
+ <key>XCBuildResultsTrigger_Open</key>
+ <integer>1010</integer>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 176}, {744, 285}}</string>
+ <key>RubberWindowFrame</key>
+ <string>1048 148 744 502 0 0 1920 1178 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXBuildResultsModule</string>
+ <key>Proportion</key>
+ <string>285pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>461pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Build Results</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXBuildResultsModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>TableOfContents</key>
+ <array>
+ <string>025880F00CEE3D1200681C7E</string>
+ <string>022B461512136A6A00A74F96</string>
+ <string>1CD0528F0623707200166675</string>
+ <string>XCMainBuildResultsModuleGUID</string>
+ </array>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.buildV3</string>
+ <key>WindowString</key>
+ <string>1048 148 744 502 0 0 1920 1178 </string>
+ <key>WindowToolGUID</key>
+ <string>025880F00CEE3D1200681C7E</string>
+ <key>WindowToolIsVisible</key>
+ <false/>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.debugger</string>
+ <key>IsVertical</key>
+ <true/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>Debugger</key>
+ <dict>
+ <key>HorizontalSplitView</key>
+ <dict>
+ <key>_collapsingFrameDimension</key>
+ <real>0.0</real>
+ <key>_indexOfCollapsedView</key>
+ <integer>0</integer>
+ <key>_percentageOfCollapsedView</key>
+ <real>0.0</real>
+ <key>isCollapsed</key>
+ <string>yes</string>
+ <key>sizes</key>
+ <array>
+ <string>{{0, 0}, {308, 302}}</string>
+ <string>{{0, 302}, {308, 479}}</string>
+ </array>
+ </dict>
+ <key>VerticalSplitView</key>
+ <dict>
+ <key>_collapsingFrameDimension</key>
+ <real>0.0</real>
+ <key>_indexOfCollapsedView</key>
+ <integer>0</integer>
+ <key>_percentageOfCollapsedView</key>
+ <real>0.0</real>
+ <key>isCollapsed</key>
+ <string>yes</string>
+ <key>sizes</key>
+ <array>
+ <string>{{0, 0}, {308, 781}}</string>
+ <string>{{308, 0}, {791, 781}}</string>
+ </array>
+ </dict>
+ </dict>
+ <key>LauncherConfigVersion</key>
+ <string>8</string>
+ <key>PBXProjectModuleGUID</key>
+ <string>1C162984064C10D400B95A72</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Debug - GLUTExamples (Underwater)</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>DebugConsoleVisible</key>
+ <string>None</string>
+ <key>DebugConsoleWindowFrame</key>
+ <string>{{200, 200}, {500, 300}}</string>
+ <key>DebugSTDIOWindowFrame</key>
+ <string>{{200, 200}, {500, 300}}</string>
+ <key>Frame</key>
+ <string>{{0, 0}, {1099, 781}}</string>
+ <key>PBXDebugSessionStackFrameViewKey</key>
+ <dict>
+ <key>DebugVariablesTableConfiguration</key>
+ <array>
+ <string>Name</string>
+ <real>120</real>
+ <string>Value</string>
+ <real>85</real>
+ <string>Summary</string>
+ <real>80</real>
+ </array>
+ <key>Frame</key>
+ <string>{{0, 302}, {308, 479}}</string>
+ <key>RubberWindowFrame</key>
+ <string>342 356 1099 822 0 0 1920 1178 </string>
+ </dict>
+ <key>RubberWindowFrame</key>
+ <string>342 356 1099 822 0 0 1920 1178 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXDebugSessionModule</string>
+ <key>Proportion</key>
+ <string>781pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>781pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Debugger</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXDebugSessionModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>TableOfContents</key>
+ <array>
+ <string>1CD10A99069EF8BA00B06720</string>
+ <string>022B4633121700F300A74F96</string>
+ <string>1C162984064C10D400B95A72</string>
+ <string>022B4634121700F300A74F96</string>
+ <string>022B4635121700F300A74F96</string>
+ <string>022B4636121700F300A74F96</string>
+ <string>022B4637121700F300A74F96</string>
+ <string>022B4638121700F300A74F96</string>
+ </array>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.debugV3</string>
+ <key>WindowString</key>
+ <string>342 356 1099 822 0 0 1920 1178 </string>
+ <key>WindowToolGUID</key>
+ <string>1CD10A99069EF8BA00B06720</string>
+ <key>WindowToolIsVisible</key>
+ <false/>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.find</string>
+ <key>IsVertical</key>
+ <true/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CDD528C0622207200134675</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Operation.cpp</string>
+ <key>StatusBarVisibility</key>
+ <true/>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {792, 405}}</string>
+ <key>RubberWindowFrame</key>
+ <string>674 189 792 854 0 0 1920 1178 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXNavigatorGroup</string>
+ <key>Proportion</key>
+ <string>792pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>405pt</string>
+ </dict>
+ <dict>
+ <key>BecomeActive</key>
+ <true/>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CD0528E0623707200166675</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Project Find</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 410}, {792, 403}}</string>
+ <key>RubberWindowFrame</key>
+ <string>674 189 792 854 0 0 1920 1178 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXProjectFindModule</string>
+ <key>Proportion</key>
+ <string>403pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>813pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Project Find</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXProjectFindModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>TableOfContents</key>
+ <array>
+ <string>1C530D57069F1CE1000CFCEE</string>
+ <string>022B461B1216FE9C00A74F96</string>
+ <string>022B461C1216FE9C00A74F96</string>
+ <string>1CDD528C0622207200134675</string>
+ <string>1CD0528E0623707200166675</string>
+ </array>
+ <key>WindowString</key>
+ <string>674 189 792 854 0 0 1920 1178 </string>
+ <key>WindowToolGUID</key>
+ <string>1C530D57069F1CE1000CFCEE</string>
+ <key>WindowToolIsVisible</key>
+ <false/>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>MENUSEPARATOR</string>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.debuggerConsole</string>
+ <key>IsVertical</key>
+ <true/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>BecomeActive</key>
+ <true/>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1C78EAAC065D492600B07095</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Debugger Console</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {734, 603}}</string>
+ <key>RubberWindowFrame</key>
+ <string>998 534 734 644 0 0 1920 1178 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXDebugCLIModule</string>
+ <key>Proportion</key>
+ <string>603pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>603pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Debugger Console</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXDebugCLIModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>TableOfContents</key>
+ <array>
+ <string>1C78EAAD065D492600B07095</string>
+ <string>022B46821218654500A74F96</string>
+ <string>1C78EAAC065D492600B07095</string>
+ </array>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.consoleV3</string>
+ <key>WindowString</key>
+ <string>998 534 734 644 0 0 1920 1178 </string>
+ <key>WindowToolGUID</key>
+ <string>1C78EAAD065D492600B07095</string>
+ <key>WindowToolIsVisible</key>
+ <true/>
+ </dict>
+ <dict>
+ <key>Identifier</key>
+ <string>windowTool.snapshots</string>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>Module</key>
+ <string>XCSnapshotModule</string>
+ <key>Proportion</key>
+ <string>100%</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>100%</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Snapshots</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>XCSnapshotModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <string>Yes</string>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.snapshots</string>
+ <key>WindowString</key>
+ <string>315 824 300 550 0 0 1440 878 </string>
+ <key>WindowToolIsVisible</key>
+ <string>Yes</string>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.scm</string>
+ <key>IsVertical</key>
+ <true/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1C78EAB2065D492600B07095</string>
+ <key>PBXProjectModuleLabel</key>
+ <string></string>
+ <key>StatusBarVisibility</key>
+ <true/>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {721, 0}}</string>
+ <key>RubberWindowFrame</key>
+ <string>1006 695 721 483 0 0 1920 1178 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXNavigatorGroup</string>
+ <key>Proportion</key>
+ <string>0pt</string>
+ </dict>
+ <dict>
+ <key>BecomeActive</key>
+ <true/>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXCVSModuleFilterTypeKey</key>
+ <integer>1032</integer>
+ <key>PBXCVSModuleTreeModuleColumnData</key>
+ <dict>
+ <key>PBXCVSModuleTreeModuleColumnWidthsKey</key>
+ <array>
+ <real>305</real>
+ <real>56</real>
+ <real>63</real>
+ <real>60</real>
+ <real>63</real>
+ <real>139</real>
+ </array>
+ <key>PBXCVSModuleTreeModuleColumnsKey</key>
+ <array>
+ <string>Name</string>
+ <string>Status</string>
+ <string>Update</string>
+ <string>Revision</string>
+ <string>Author</string>
+ <string>Date</string>
+ </array>
+ </dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CD052920623707200166675</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>SCM Results</string>
+ <key>SCMActivityViewerShowingDefaultKey</key>
+ <string>{{0, 304}, {721, 133}}</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 5}, {721, 437}}</string>
+ <key>RubberWindowFrame</key>
+ <string>1006 695 721 483 0 0 1920 1178 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXCVSModule</string>
+ <key>Proportion</key>
+ <string>437pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>442pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>SCM</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXCVSModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>TableOfContents</key>
+ <array>
+ <string>02D46D160FED80AF00E65706</string>
+ <string>022B463B121700F300A74F96</string>
+ <string>1C78EAB2065D492600B07095</string>
+ <string>1CD052920623707200166675</string>
+ </array>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.scm</string>
+ <key>WindowString</key>
+ <string>1006 695 721 483 0 0 1920 1178 </string>
+ <key>WindowToolGUID</key>
+ <string>02D46D160FED80AF00E65706</string>
+ <key>WindowToolIsVisible</key>
+ <false/>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.breakpoints</string>
+ <key>IsVertical</key>
+ <false/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXBottomSmartGroupGIDs</key>
+ <array>
+ <string>1C77FABC04509CD000000102</string>
+ </array>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CE0B1FE06471DED0097A5F4</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Files</string>
+ <key>PBXProjectStructureProvided</key>
+ <string>no</string>
+ <key>PBXSmartGroupTreeModuleColumnData</key>
+ <dict>
+ <key>PBXSmartGroupTreeModuleColumnWidthsKey</key>
+ <array>
+ <real>168</real>
+ </array>
+ <key>PBXSmartGroupTreeModuleColumnsKey_v4</key>
+ <array>
+ <string>MainColumn</string>
+ </array>
+ </dict>
+ <key>PBXSmartGroupTreeModuleOutlineStateKey_v7</key>
+ <dict>
+ <key>PBXSmartGroupTreeModuleOutlineStateExpansionKey</key>
+ <array>
+ <string>1C77FABC04509CD000000102</string>
+ <string>1C3E0DCA080725EA00A55177</string>
+ </array>
+ <key>PBXSmartGroupTreeModuleOutlineStateSelectionKey</key>
+ <array>
+ <array>
+ <integer>0</integer>
+ </array>
+ </array>
+ <key>PBXSmartGroupTreeModuleOutlineStateVisibleRectKey</key>
+ <string>{{0, 0}, {168, 350}}</string>
+ </dict>
+ <key>PBXTopSmartGroupGIDs</key>
+ <array/>
+ <key>XCIncludePerspectivesSwitch</key>
+ <false/>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {185, 368}}</string>
+ <key>GroupTreeTableConfiguration</key>
+ <array>
+ <string>MainColumn</string>
+ <real>168</real>
+ </array>
+ <key>RubberWindowFrame</key>
+ <string>28 375 744 409 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXSmartGroupTreeModule</string>
+ <key>Proportion</key>
+ <string>185pt</string>
+ </dict>
+ <dict>
+ <key>BecomeActive</key>
+ <true/>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CA1AED706398EBD00589147</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Detail</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{190, 0}, {554, 368}}</string>
+ <key>RubberWindowFrame</key>
+ <string>28 375 744 409 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>XCDetailModule</string>
+ <key>Proportion</key>
+ <string>554pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>368pt</string>
+ </dict>
+ </array>
+ <key>MajorVersion</key>
+ <integer>3</integer>
+ <key>MinorVersion</key>
+ <integer>0</integer>
+ <key>Name</key>
+ <string>Breakpoints</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXSmartGroupTreeModule</string>
+ <string>XCDetailModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>TableOfContents</key>
+ <array>
+ <string>0258810E0CEE488000681C7E</string>
+ <string>0258810F0CEE488000681C7E</string>
+ <string>1CE0B1FE06471DED0097A5F4</string>
+ <string>1CA1AED706398EBD00589147</string>
+ </array>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.breakpointsV3</string>
+ <key>WindowString</key>
+ <string>28 375 744 409 0 0 1440 878 </string>
+ <key>WindowToolGUID</key>
+ <string>0258810E0CEE488000681C7E</string>
+ <key>WindowToolIsVisible</key>
+ <false/>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.debugAnimator</string>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>BecomeActive</key>
+ <true/>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>PBXProjectModuleGUID</key>
+ <string>02E39A7909F721C80055992A</string>
+ <key>PBXProjectModuleLabel</key>
+ <string></string>
+ <key>StatusBarVisibility</key>
+ <true/>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{{0, 0}, {700, 459}}</string>
+ <key>RubberWindowFrame</key>
+ <string>36 211 700 500 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXNavigatorGroup</string>
+ <key>Proportion</key>
+ <string>459pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>459pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Debug Visualizer</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXNavigatorGroup</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <true/>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.debugAnimatorV3</string>
+ <key>WindowString</key>
+ <string>36 211 700 500 0 0 1440 878 </string>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.bookmarks</string>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>Module</key>
+ <string>PBXBookmarksModule</string>
+ <key>Proportion</key>
+ <string>100%</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>100%</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Bookmarks</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXBookmarksModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <false/>
+ <key>WindowString</key>
+ <string>538 42 401 187 0 0 1280 1002 </string>
+ </dict>
+ <dict>
+ <key>Identifier</key>
+ <string>windowTool.projectFormatConflicts</string>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>Module</key>
+ <string>XCProjectFormatConflictsModule</string>
+ <key>Proportion</key>
+ <string>100%</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>100%</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Project Format Conflicts</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>XCProjectFormatConflictsModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <false/>
+ <key>WindowContentMinSize</key>
+ <string>450 300</string>
+ <key>WindowString</key>
+ <string>50 850 472 307 0 0 1440 877</string>
+ </dict>
+ <dict>
+ <key>FirstTimeWindowDisplayed</key>
+ <false/>
+ <key>Identifier</key>
+ <string>windowTool.classBrowser</string>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>ContentConfiguration</key>
+ <dict>
+ <key>OptionsSetName</key>
+ <string>Hierarchy, project classes</string>
+ <key>PBXProjectModuleGUID</key>
+ <string>1CA6456E063B45B4001379D8</string>
+ <key>PBXProjectModuleLabel</key>
+ <string>Class Browser - RijndaelCBCMAC</string>
+ </dict>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>ClassesFrame</key>
+ <string>{{0, 0}, {759, 298}}</string>
+ <key>ClassesTreeTableConfiguration</key>
+ <array>
+ <string>PBXClassNameColumnIdentifier</string>
+ <real>208</real>
+ <string>PBXClassBookColumnIdentifier</string>
+ <real>22</real>
+ </array>
+ <key>Frame</key>
+ <string>{{0, 0}, {1011, 802}}</string>
+ <key>MembersFrame</key>
+ <string>{{0, 303}, {759, 499}}</string>
+ <key>MembersTreeTableConfiguration</key>
+ <array>
+ <string>PBXMemberTypeIconColumnIdentifier</string>
+ <real>22</real>
+ <string>PBXMemberNameColumnIdentifier</string>
+ <real>216</real>
+ <string>PBXMemberTypeColumnIdentifier</string>
+ <real>482</real>
+ <string>PBXMemberBookColumnIdentifier</string>
+ <real>22</real>
+ </array>
+ <key>RubberWindowFrame</key>
+ <string>159 56 1011 822 0 0 1440 878 </string>
+ </dict>
+ <key>Module</key>
+ <string>PBXClassBrowserModule</string>
+ <key>Proportion</key>
+ <string>802pt</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>802pt</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Class Browser</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>PBXClassBrowserModule</string>
+ </array>
+ <key>StatusbarIsVisible</key>
+ <false/>
+ <key>TableOfContents</key>
+ <array>
+ <string>1C0AD2AF069F1E9B00FABCE6</string>
+ <string>1C0AD2B0069F1E9B00FABCE6</string>
+ <string>1CA6456E063B45B4001379D8</string>
+ </array>
+ <key>ToolbarConfiguration</key>
+ <string>xcode.toolbar.config.classbrowser</string>
+ <key>WindowString</key>
+ <string>159 56 1011 822 0 0 1440 878 </string>
+ <key>WindowToolGUID</key>
+ <string>1C0AD2AF069F1E9B00FABCE6</string>
+ <key>WindowToolIsVisible</key>
+ <false/>
+ </dict>
+ <dict>
+ <key>Identifier</key>
+ <string>windowTool.refactoring</string>
+ <key>IncludeInToolsMenu</key>
+ <false/>
+ <key>Layout</key>
+ <array>
+ <dict>
+ <key>Dock</key>
+ <array>
+ <dict>
+ <key>BecomeActive</key>
+ <true/>
+ <key>GeometryConfiguration</key>
+ <dict>
+ <key>Frame</key>
+ <string>{0, 0}, {500, 335}</string>
+ <key>RubberWindowFrame</key>
+ <string>{0, 0}, {500, 335}</string>
+ </dict>
+ <key>Module</key>
+ <string>XCRefactoringModule</string>
+ <key>Proportion</key>
+ <string>100%</string>
+ </dict>
+ </array>
+ <key>Proportion</key>
+ <string>100%</string>
+ </dict>
+ </array>
+ <key>Name</key>
+ <string>Refactoring</string>
+ <key>ServiceClasses</key>
+ <array>
+ <string>XCRefactoringModule</string>
+ </array>
+ <key>WindowString</key>
+ <string>200 200 500 356 0 0 1920 1200 </string>
+ </dict>
+ </array>
+</dict>
+</plist>
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+ PBXFileDataSource_Errors_ColumnID,
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+ PBXFileDataSource_ObjectSize_ColumnID,
+ PBXFileDataSource_Errors_ColumnID,
+ PBXFileDataSource_Warnings_ColumnID,
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+ executables = (
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+ };
+}
--- /dev/null
+// !$*UTF8*$!
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+ };
+ objectVersion = 45;
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+
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+ productName = Everything;
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+
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+}
--- /dev/null
+/*
+ * BootImageGenerator.cpp
+ * elftosb
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "BootImageGenerator.h"
+#include "Logging.h"
+
+//! Name of product version option.
+#define kProductVersionOption "productVersion"
+
+//! Name of component version option.
+#define kComponentVersionOption "componentVersion"
+
+//! Name of option that specifies the drive tag for this .sb file.
+#define kDriveTagOption "driveTag"
+
+using namespace elftosb;
+
+void BootImageGenerator::processVersionOptions(BootImage * image)
+{
+ // bail if no option context was set
+ if (!m_options)
+ {
+ return;
+ }
+
+ const StringValue * stringValue;
+ version_t version;
+
+ // productVersion
+ if (m_options->hasOption(kProductVersionOption))
+ {
+ stringValue = dynamic_cast<const StringValue *>(m_options->getOption(kProductVersionOption));
+ if (stringValue)
+ {
+ version.set(*stringValue);
+ image->setProductVersion(version);
+ }
+ else
+ {
+ Log::log(Logger::WARNING, "warning: productVersion option is an unexpected type\n");
+ }
+ }
+
+ // componentVersion
+ if (m_options->hasOption(kComponentVersionOption))
+ {
+ stringValue = dynamic_cast<const StringValue *>(m_options->getOption(kComponentVersionOption));
+ if (stringValue)
+ {
+ version.set(*stringValue);
+ image->setComponentVersion(version);
+ }
+ else
+ {
+ Log::log(Logger::WARNING, "warning: componentVersion option is an unexpected type\n");
+ }
+ }
+}
+
+void BootImageGenerator::processDriveTagOption(BootImage * image)
+{
+ if (m_options->hasOption(kDriveTagOption))
+ {
+ const IntegerValue * intValue = dynamic_cast<const IntegerValue *>(m_options->getOption(kDriveTagOption));
+ if (intValue)
+ {
+ image->setDriveTag(intValue->getValue());
+ }
+ else
+ {
+ Log::log(Logger::WARNING, "warning: driveTag option is an unexpected type\n");
+ }
+ }
+}
+
--- /dev/null
+/*
+ * File: BootImageGenerator.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_BootImageGenerator_h_)
+#define _BootImageGenerator_h_
+
+#include "OutputSection.h"
+#include "BootImage.h"
+#include "OptionContext.h"
+
+namespace elftosb
+{
+
+/*!
+ * \brief Abstract base class for generators of specific boot image formats.
+ *
+ * Subclasses implement a concrete generator for a certain boot image format, but
+ * they all have the same interface.
+ *
+ * After creating an instance of a subclass the user adds OutputSection objects
+ * to the generator. These objects describe discrete sections within the resulting
+ * boot image file. If the format does not support multiple sections then only
+ * the first will be used.
+ *
+ * Options that are common to all boot image formats are handled by methods
+ * defined in this class. These are the current common options:
+ * - productVersion
+ * - componentVersion
+ * - driveTag
+ */
+class BootImageGenerator
+{
+public:
+ //! \brief Constructor.
+ BootImageGenerator() {}
+
+ //! \brief Destructor.
+ virtual ~BootImageGenerator() {}
+
+ //! \brief Add another section to the output.
+ void addOutputSection(OutputSection * section) { m_sections.push_back(section); }
+
+ //! \brief Set the global option context.
+ void setOptionContext(OptionContext * context) { m_options = context; }
+
+ //! \brief Pure virtual method to generate the output BootImage from input sections.
+ virtual BootImage * generate()=0;
+
+protected:
+ //! Type for a list of model output sections.
+ typedef std::vector<OutputSection*> section_vector_t;
+
+ section_vector_t m_sections; //!< Requested output sections.
+ OptionContext * m_options; //!< Global option context.
+
+ //! \brief Handle common product and component version options.
+ void processVersionOptions(BootImage * image);
+
+ //! \brief Handle the common option which sets the system drive tag.
+ void processDriveTagOption(BootImage * image);
+};
+
+}; // namespace elftosb
+
+#endif // _BootImageGenerator_h_
+
--- /dev/null
+/*
+ * File: ConversionController.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "ConversionController.h"
+#include <stdexcept>
+#include "EvalContext.h"
+#include "ElftosbErrors.h"
+#include "GlobMatcher.h"
+#include "ExcludesListMatcher.h"
+#include "BootImageGenerator.h"
+#include "EncoreBootImageGenerator.h"
+#include "Logging.h"
+#include "OptionDictionary.h"
+#include "format_string.h"
+#include "SearchPath.h"
+#include "DataSourceImager.h"
+#include "IVTDataSource.h"
+#include <algorithm>
+
+//! Set to 1 to cause the ConversionController to print information about
+//! the values that it processes (options, constants, etc.).
+#define PRINT_VALUES 1
+
+using namespace elftosb;
+
+// Define the parser function prototype;
+extern int yyparse(ElftosbLexer * lexer, CommandFileASTNode ** resultAST);
+
+bool elftosb::g_enableHABSupport = false;
+
+ConversionController::ConversionController()
+: OptionDictionary(),
+ m_commandFilePath(),
+ m_ast(),
+ m_defaultSource(0)
+{
+ m_context.setSourceFileManager(this);
+}
+
+ConversionController::~ConversionController()
+{
+ // clean up sources
+ source_map_t::iterator it = m_sources.begin();
+ for (; it != m_sources.end(); ++it)
+ {
+ if (it->second)
+ {
+ delete it->second;
+ }
+ }
+}
+
+void ConversionController::setCommandFilePath(const std::string & path)
+{
+ m_commandFilePath = new std::string(path);
+}
+
+//! The paths provided to this method are added to an array and accessed with the
+//! "extern(N)" notation in the command file. So the path provided in the third
+//! call to addExternalFilePath() will be found with N=2 in the source definition.
+void ConversionController::addExternalFilePath(const std::string & path)
+{
+ m_externPaths.push_back(path);
+}
+
+bool ConversionController::hasSourceFile(const std::string & name)
+{
+ return m_sources.find(name) != m_sources.end();
+}
+
+SourceFile * ConversionController::getSourceFile(const std::string & name)
+{
+ if (!hasSourceFile(name))
+ {
+ return NULL;
+ }
+
+ return m_sources[name];
+}
+
+SourceFile * ConversionController::getDefaultSourceFile()
+{
+ return m_defaultSource;
+}
+
+//! These steps are executed while running this method:
+//! - The command file is parsed into an abstract syntax tree.
+//! - The list of options is extracted.
+//! - Constant expressions are evaluated.
+//! - The list of source files is extracted and source file objects created.
+//! - Section definitions are extracted.
+//!
+//! This method does not produce any output. It processes the input files and
+//! builds a representation of the output in memory. Use the generateOutput() method
+//! to produce a BootImage object after this method returns.
+//!
+//! \note This method is \e not reentrant. And in fact, the whole class is not designed
+//! to be reentrant.
+//!
+//! \exception std::runtime_error Any number of problems will cause this exception to
+//! be thrown.
+//!
+//! \see parseCommandFile()
+//! \see processOptions()
+//! \see processConstants()
+//! \see processSources()
+//! \see processSections()
+void ConversionController::run()
+{
+#if PRINT_VALUES
+ Log::SetOutputLevel debugLevel(Logger::DEBUG2);
+#endif
+
+ parseCommandFile();
+ assert(m_ast);
+
+ ListASTNode * blocks = m_ast->getBlocks();
+ if (!blocks)
+ {
+ throw std::runtime_error("command file has no blocks");
+ }
+
+ ListASTNode::iterator it = blocks->begin();
+ for (; it != blocks->end(); ++it)
+ {
+ ASTNode * node = *it;
+
+ // Handle an options block.
+ OptionsBlockASTNode * options = dynamic_cast<OptionsBlockASTNode *>(node);
+ if (options)
+ {
+ processOptions(options->getOptions());
+ continue;
+ }
+
+ // Handle a constants block.
+ ConstantsBlockASTNode * constants = dynamic_cast<ConstantsBlockASTNode *>(node);
+ if (constants)
+ {
+ processConstants(constants->getConstants());
+ continue;
+ }
+
+ // Handle a sources block.
+ SourcesBlockASTNode * sources = dynamic_cast<SourcesBlockASTNode *>(node);
+ if (sources)
+ {
+ processSources(sources->getSources());
+ }
+ }
+
+ processSections(m_ast->getSections());
+}
+
+//! Opens the command file and runs it through the lexer and parser. The resulting
+//! abstract syntax tree is held in the m_ast member variable. After parsing, the
+//! command file is closed.
+//!
+//! \exception std::runtime_error Several problems will cause this exception to be
+//! raised, including an unspecified command file path or an error opening the
+//! file.
+void ConversionController::parseCommandFile()
+{
+ if (!m_commandFilePath)
+ {
+ throw std::runtime_error("no command file path was provided");
+ }
+
+ // Search for command file
+ std::string actualPath;
+ bool found = PathSearcher::getGlobalSearcher().search(*m_commandFilePath, PathSearcher::kFindFile, true, actualPath);
+ if (!found)
+ {
+ throw runtime_error(format_string("unable to find command file %s\n", m_commandFilePath->c_str()));
+ }
+
+ // open command file
+ std::ifstream commandFile(actualPath.c_str(), ios_base::in | ios_base::binary);
+ if (!commandFile.is_open())
+ {
+ throw std::runtime_error("could not open command file");
+ }
+
+ try
+ {
+ // create lexer instance
+ ElftosbLexer lexer(commandFile);
+// testLexer(lexer);
+
+ CommandFileASTNode * ast = NULL;
+ int result = yyparse(&lexer, &ast);
+ m_ast = ast;
+
+ // check results
+ if (result || !m_ast)
+ {
+ throw std::runtime_error("failed to parse command file");
+ }
+
+ // dump AST
+// m_ast->printTree(0);
+
+ // close command file
+ commandFile.close();
+ }
+ catch (...)
+ {
+ // close command file
+ commandFile.close();
+
+ // rethrow exception
+ throw;
+ }
+}
+
+//! Iterates over the option definition AST nodes. elftosb::Value objects are created for
+//! each option value and added to the option dictionary.
+//!
+//! \exception std::runtime_error Various errors will cause this exception to be thrown. These
+//! include AST nodes being an unexpected type or expression not evaluating to integers.
+void ConversionController::processOptions(ListASTNode * options)
+{
+ if (!options)
+ {
+ return;
+ }
+
+ ListASTNode::iterator it = options->begin();
+ for (; it != options->end(); ++it)
+ {
+ std::string ident;
+ Value * value = convertAssignmentNodeToValue(*it, ident);
+
+ // check if this option has already been set
+ if (hasOption(ident))
+ {
+ throw semantic_error(format_string("line %d: option already set", (*it)->getFirstLine()));
+ }
+
+ // now save the option value in our map
+ if (value)
+ {
+ setOption(ident, value);
+ }
+ }
+}
+
+//! Scans the constant definition AST nodes, evaluates expression nodes by calling their
+//! elftosb::ExprASTNode::reduce() method, and updates the evaluation context member so
+//! those constant values can be used in other expressions.
+//!
+//! \exception std::runtime_error Various errors will cause this exception to be thrown. These
+//! include AST nodes being an unexpected type or expression not evaluating to integers.
+void ConversionController::processConstants(ListASTNode * constants)
+{
+ if (!constants)
+ {
+ return;
+ }
+
+ ListASTNode::iterator it = constants->begin();
+ for (; it != constants->end(); ++it)
+ {
+ std::string ident;
+ Value * value = convertAssignmentNodeToValue(*it, ident);
+
+ SizedIntegerValue * intValue = dynamic_cast<SizedIntegerValue*>(value);
+ if (!intValue)
+ {
+ throw semantic_error(format_string("line %d: constant value is an invalid type", (*it)->getFirstLine()));
+ }
+
+//#if PRINT_VALUES
+// Log::log("constant ");
+// printIntConstExpr(ident, intValue);
+//#endif
+
+ // record this constant's value in the evaluation context
+ m_context.setVariable(ident, intValue->getValue(), intValue->getWordSize());
+ }
+}
+
+//! \exception std::runtime_error Various errors will cause this exception to be thrown. These
+//! include AST nodes being an unexpected type or expression not evaluating to integers.
+//!
+//! \todo Handle freeing of dict if an exception occurs.
+void ConversionController::processSources(ListASTNode * sources)
+{
+ if (!sources)
+ {
+ return;
+ }
+
+ ListASTNode::iterator it = sources->begin();
+ for (; it != sources->end(); ++it)
+ {
+ SourceDefASTNode * node = dynamic_cast<SourceDefASTNode*>(*it);
+ if (!node)
+ {
+ throw semantic_error(format_string("line %d: source definition node is an unexpected type", node->getFirstLine()));
+ }
+
+ // get source name and check if it has already been defined
+ std::string * name = node->getName();
+ if (m_sources.find(*name) != m_sources.end())
+ {
+ // can't define a source multiple times
+ throw semantic_error(format_string("line %d: source already defined", node->getFirstLine()));
+ }
+
+ // convert attributes into an option dict
+ OptionDictionary * dict = new OptionDictionary(this);
+ ListASTNode * attrsNode = node->getAttributes();
+ if (attrsNode)
+ {
+ ListASTNode::iterator attrIt = attrsNode->begin();
+ for (; attrIt != attrsNode->end(); ++attrIt)
+ {
+ std::string ident;
+ Value * value = convertAssignmentNodeToValue(*attrIt, ident);
+ dict->setOption(ident, value);
+ }
+ }
+
+ // figure out which type of source definition this is
+ PathSourceDefASTNode * pathNode = dynamic_cast<PathSourceDefASTNode*>(node);
+ ExternSourceDefASTNode * externNode = dynamic_cast<ExternSourceDefASTNode*>(node);
+ SourceFile * file = NULL;
+
+ if (pathNode)
+ {
+ // explicit path
+ std::string * path = pathNode->getPath();
+
+#if PRINT_VALUES
+ Log::log("source %s => path(%s)\n", name->c_str(), path->c_str());
+#endif
+
+ try
+ {
+ file = SourceFile::openFile(*path);
+ }
+ catch (...)
+ {
+ // file doesn't exist
+ Log::log(Logger::INFO2, "failed to open source file: %s (ignoring for now)\n", path->c_str());
+ m_failedSources.push_back(*name);
+ }
+ }
+ else if (externNode)
+ {
+ // externally provided path
+ ExprASTNode * expr = externNode->getSourceNumberExpr()->reduce(m_context);
+ IntConstExprASTNode * intConst = dynamic_cast<IntConstExprASTNode*>(expr);
+ if (!intConst)
+ {
+ throw semantic_error(format_string("line %d: expression didn't evaluate to an integer", expr->getFirstLine()));
+ }
+
+ uint32_t externalFileNumber = static_cast<uint32_t>(intConst->getValue());
+
+ // make sure the extern number is valid
+ if (externalFileNumber >= 0 && externalFileNumber < m_externPaths.size())
+ {
+
+#if PRINT_VALUES
+ Log::log("source %s => extern(%d=%s)\n", name->c_str(), externalFileNumber, m_externPaths[externalFileNumber].c_str());
+#endif
+
+ try
+ {
+ file = SourceFile::openFile(m_externPaths[externalFileNumber]);
+ }
+ catch (...)
+ {
+ Log::log(Logger::INFO2, "failed to open source file: %s (ignoring for now)\n", m_externPaths[externalFileNumber].c_str());
+ m_failedSources.push_back(*name);
+ }
+ }
+ }
+ else
+ {
+ throw semantic_error(format_string("line %d: unexpected source definition node type", node->getFirstLine()));
+ }
+
+ if (file)
+ {
+ // set options
+ file->setOptions(dict);
+
+ // stick the file object in the source map
+ m_sources[*name] = file;
+ }
+ }
+}
+
+void ConversionController::processSections(ListASTNode * sections)
+{
+ if (!sections)
+ {
+ Log::log(Logger::WARNING, "warning: no sections were defined in command file");
+ return;
+ }
+
+ ListASTNode::iterator it = sections->begin();
+ for (; it != sections->end(); ++it)
+ {
+ SectionContentsASTNode * node = dynamic_cast<SectionContentsASTNode*>(*it);
+ if (!node)
+ {
+ throw semantic_error(format_string("line %d: section definition is unexpected type", node->getFirstLine()));
+ }
+
+ // evaluate section number
+ ExprASTNode * idExpr = node->getSectionNumberExpr()->reduce(m_context);
+ IntConstExprASTNode * idConst = dynamic_cast<IntConstExprASTNode*>(idExpr);
+ if (!idConst)
+ {
+ throw semantic_error(format_string("line %d: section number did not evaluate to an integer", idExpr->getFirstLine()));
+ }
+ uint32_t sectionID = idConst->getValue();
+
+ // Create options context for this section. The options context has the
+ // conversion controller as its parent context so it will inherit global options.
+ // The context will be set in the section after the section is created below.
+ OptionDictionary * optionsDict = new OptionDictionary(this);
+ ListASTNode * attrsNode = node->getOptions();
+ if (attrsNode)
+ {
+ ListASTNode::iterator attrIt = attrsNode->begin();
+ for (; attrIt != attrsNode->end(); ++attrIt)
+ {
+ std::string ident;
+ Value * value = convertAssignmentNodeToValue(*attrIt, ident);
+ optionsDict->setOption(ident, value);
+ }
+ }
+
+ // Now create the actual section object based on its type.
+ OutputSection * outputSection = NULL;
+ BootableSectionContentsASTNode * bootableSection;
+ DataSectionContentsASTNode * dataSection;
+ if (bootableSection = dynamic_cast<BootableSectionContentsASTNode*>(node))
+ {
+ // process statements into a sequence of operations
+ ListASTNode * statements = bootableSection->getStatements();
+ OperationSequence * sequence = convertStatementList(statements);
+
+#if 0
+ Log::log("section ID = %d\n", sectionID);
+ statements->printTree(0);
+
+ Log::log("sequence has %d operations\n", sequence->getCount());
+ OperationSequence::iterator_t it = sequence->begin();
+ for (; it != sequence->end(); ++it)
+ {
+ Operation * op = *it;
+ Log::log("op = %p\n", op);
+ }
+#endif
+
+ // create the output section and add it to the list
+ OperationSequenceSection * opSection = new OperationSequenceSection(sectionID);
+ opSection->setOptions(optionsDict);
+ opSection->getSequence() += sequence;
+ outputSection = opSection;
+ }
+ else if (dataSection = dynamic_cast<DataSectionContentsASTNode*>(node))
+ {
+ outputSection = convertDataSection(dataSection, sectionID, optionsDict);
+ }
+ else
+ {
+ throw semantic_error(format_string("line %d: unexpected section contents type", node->getFirstLine()));
+ }
+
+ if (outputSection)
+ {
+ m_outputSections.push_back(outputSection);
+ }
+ }
+}
+
+//! Creates an instance of BinaryDataSection from the AST node passed in the
+//! \a dataSection parameter. The section-specific options for this node will
+//! have already been converted into an OptionDictionary, the one passed in
+//! the \a optionsDict parameter.
+//!
+//! The \a dataSection node will have as its contents one of the AST node
+//! classes that represents a source of data. The member function
+//! createSourceFromNode() is used to convert this AST node into an
+//! instance of a DataSource subclass. Then the method imageDataSource()
+//! converts the segments of the DataSource into a raw binary buffer that
+//! becomes the contents of the BinaryDataSection this is returned.
+//!
+//! \param dataSection The AST node for the data section.
+//! \param sectionID Unique tag value the user has assigned to this section.
+//! \param optionsDict Options that apply only to this section. This dictionary
+//! will be assigned as the options dictionary for the resulting section
+//! object. Its parent is the conversion controller itself.
+//! \return An instance of BinaryDataSection. Its contents are a contiguous
+//! binary representation of the contents of \a dataSection.
+OutputSection * ConversionController::convertDataSection(DataSectionContentsASTNode * dataSection, uint32_t sectionID, OptionDictionary * optionsDict)
+{
+ // Create a data source from the section contents AST node.
+ ASTNode * contents = dataSection->getContents();
+ DataSource * dataSource = createSourceFromNode(contents);
+
+ // Convert the data source to a raw buffer.
+ DataSourceImager imager;
+ imager.addDataSource(dataSource);
+
+ // Then make a data section from the buffer.
+ BinaryDataSection * resultSection = new BinaryDataSection(sectionID);
+ resultSection->setOptions(optionsDict);
+ if (imager.getLength())
+ {
+ resultSection->setData(imager.getData(), imager.getLength());
+ }
+
+ return resultSection;
+}
+
+//! @param node The AST node instance for the assignment expression.
+//! @param[out] ident Upon exit this string will be set the the left hand side of the
+//! assignment expression, the identifier name.
+//!
+//! @return An object that is a subclass of Value is returned. The specific subclass will
+//! depend on the type of the right hand side of the assignment expression whose AST
+//! node was provided in the @a node argument.
+//!
+//! @exception semantic_error Thrown for any error where an AST node is an unexpected type.
+//! This may be the @a node argument itself, if it is not an AssignmentASTNode. Or it
+//! may be an unexpected type for either the right or left hand side of the assignment.
+//! The message for the exception will contain a description of the error.
+Value * ConversionController::convertAssignmentNodeToValue(ASTNode * node, std::string & ident)
+{
+ Value * resultValue = NULL;
+
+ // each item of the options list should be an assignment node
+ AssignmentASTNode * assignmentNode = dynamic_cast<AssignmentASTNode*>(node);
+ if (!node)
+ {
+ throw semantic_error(format_string("line %d: node is wrong type", assignmentNode->getFirstLine()));
+ }
+
+ // save the left hand side (the identifier) into ident
+ ident = *assignmentNode->getIdent();
+
+ // get the right hand side and convert it to a Value instance
+ ASTNode * valueNode = assignmentNode->getValue();
+ StringConstASTNode * str;
+ ExprASTNode * expr;
+ if (str = dynamic_cast<StringConstASTNode*>(valueNode))
+ {
+ // the option value is a string constant
+ resultValue = new StringValue(str->getString());
+
+//#if PRINT_VALUES
+// Log::log("option %s => \'%s\'\n", ident->c_str(), str->getString()->c_str());
+//#endif
+ }
+ else if (expr = dynamic_cast<ExprASTNode*>(valueNode))
+ {
+ ExprASTNode * reducedExpr = expr->reduce(m_context);
+ IntConstExprASTNode * intConst = dynamic_cast<IntConstExprASTNode*>(reducedExpr);
+ if (!intConst)
+ {
+ throw semantic_error(format_string("line %d: expression didn't evaluate to an integer", expr->getFirstLine()));
+ }
+
+//#if PRINT_VALUES
+// Log::log("option ");
+// printIntConstExpr(*ident, intConst);
+//#endif
+
+ resultValue = new SizedIntegerValue(intConst->getValue(), intConst->getSize());
+ }
+ else
+ {
+ throw semantic_error(format_string("line %d: right hand side node is an unexpected type", valueNode->getFirstLine()));
+ }
+
+ return resultValue;
+}
+
+//! Builds up a sequence of Operation objects that are equivalent to the
+//! statements in the \a statements list. The statement list is simply iterated
+//! over and the results of convertOneStatement() are used to build up
+//! the final result sequence.
+//!
+//! \see convertOneStatement()
+OperationSequence * ConversionController::convertStatementList(ListASTNode * statements)
+{
+ OperationSequence * resultSequence = new OperationSequence();
+ ListASTNode::iterator it = statements->begin();
+ for (; it != statements->end(); ++it)
+ {
+ StatementASTNode * statement = dynamic_cast<StatementASTNode*>(*it);
+ if (!statement)
+ {
+ throw semantic_error(format_string("line %d: statement node is unexpected type", (*it)->getFirstLine()));
+ }
+
+ // convert this statement and append it to the result
+ OperationSequence * sequence = convertOneStatement(statement);
+ if (sequence)
+ {
+ *resultSequence += sequence;
+ }
+ }
+
+ return resultSequence;
+}
+
+//! Uses C++ RTTI to identify the particular subclass of StatementASTNode that
+//! the \a statement argument matches. Then the appropriate conversion method
+//! is called.
+//!
+//! \see convertLoadStatement()
+//! \see convertCallStatement()
+//! \see convertFromStatement()
+OperationSequence * ConversionController::convertOneStatement(StatementASTNode * statement)
+{
+ // see if it's a load statement
+ LoadStatementASTNode * load = dynamic_cast<LoadStatementASTNode*>(statement);
+ if (load)
+ {
+ return convertLoadStatement(load);
+ }
+
+ // see if it's a call statement
+ CallStatementASTNode * call = dynamic_cast<CallStatementASTNode*>(statement);
+ if (call)
+ {
+ return convertCallStatement(call);
+ }
+
+ // see if it's a from statement
+ FromStatementASTNode * from = dynamic_cast<FromStatementASTNode*>(statement);
+ if (from)
+ {
+ return convertFromStatement(from);
+ }
+
+ // see if it's a mode statement
+ ModeStatementASTNode * mode = dynamic_cast<ModeStatementASTNode*>(statement);
+ if (mode)
+ {
+ return convertModeStatement(mode);
+ }
+
+ // see if it's an if statement
+ IfStatementASTNode * ifStmt = dynamic_cast<IfStatementASTNode*>(statement);
+ if (ifStmt)
+ {
+ return convertIfStatement(ifStmt);
+ }
+
+ // see if it's a message statement
+ MessageStatementASTNode * messageStmt = dynamic_cast<MessageStatementASTNode*>(statement);
+ if (messageStmt)
+ {
+ // Message statements don't produce operation sequences.
+ handleMessageStatement(messageStmt);
+ return NULL;
+ }
+
+ // didn't match any of the expected statement types
+ throw semantic_error(format_string("line %d: unexpected statement type", statement->getFirstLine()));
+ return NULL;
+}
+
+//! Possible load data node types:
+//! - StringConstASTNode
+//! - ExprASTNode
+//! - SourceASTNode
+//! - SectionMatchListASTNode
+//!
+//! Possible load target node types:
+//! - SymbolASTNode
+//! - NaturalLocationASTNode
+//! - AddressRangeASTNode
+OperationSequence * ConversionController::convertLoadStatement(LoadStatementASTNode * statement)
+{
+ LoadOperation * op = NULL;
+
+ try
+ {
+ // build load operation from source and target
+ op = new LoadOperation();
+ op->setSource(createSourceFromNode(statement->getData()));
+ op->setTarget(createTargetFromNode(statement->getTarget()));
+ op->setDCDLoad(statement->isDCDLoad());
+
+ return new OperationSequence(op);
+ }
+ catch (...)
+ {
+ if (op)
+ {
+ delete op;
+ }
+ throw;
+ }
+}
+
+//! Possible call target node types:
+//! - SymbolASTNode
+//! - ExprASTNode
+//!
+//! Possible call argument node types:
+//! - ExprASTNode
+//! - NULL
+OperationSequence * ConversionController::convertCallStatement(CallStatementASTNode * statement)
+{
+ ExecuteOperation * op = NULL;
+
+ try
+ {
+ // create operation from AST nodes
+ op = new ExecuteOperation();
+
+ bool isHAB = statement->isHAB();
+
+ op->setTarget(createTargetFromNode(statement->getTarget()));
+
+ // set argument value, which defaults to 0 if no expression was provided
+ uint32_t arg = 0;
+ ASTNode * argNode = statement->getArgument();
+ if (argNode)
+ {
+ ExprASTNode * argExprNode = dynamic_cast<ExprASTNode*>(argNode);
+ if (!argExprNode)
+ {
+ throw semantic_error(format_string("line %d: call argument is unexpected type", argNode->getFirstLine()));
+ }
+ argExprNode = argExprNode->reduce(m_context);
+ IntConstExprASTNode * intNode = dynamic_cast<IntConstExprASTNode*>(argExprNode);
+ if (!intNode)
+ {
+ throw semantic_error(format_string("line %d: call argument did not evaluate to an integer", argExprNode->getFirstLine()));
+ }
+
+ arg = intNode->getValue();
+ }
+ op->setArgument(arg);
+
+ // set call type
+ switch (statement->getCallType())
+ {
+ case CallStatementASTNode::kCallType:
+ op->setExecuteType(ExecuteOperation::kCall);
+ break;
+ case CallStatementASTNode::kJumpType:
+ op->setExecuteType(ExecuteOperation::kJump);
+ break;
+ }
+
+ // Set the HAB mode flag.
+ op->setIsHAB(isHAB);
+
+ return new OperationSequence(op);
+ }
+ catch (...)
+ {
+ // delete op and rethrow exception
+ if (op)
+ {
+ delete op;
+ }
+ throw;
+ }
+}
+
+//! First this method sets the default source to the source identified in
+//! the from statement. Then the statements within the from block are
+//! processed recursively by calling convertStatementList(). The resulting
+//! operation sequence is returned.
+OperationSequence * ConversionController::convertFromStatement(FromStatementASTNode * statement)
+{
+ if (m_defaultSource)
+ {
+ throw semantic_error(format_string("line %d: from statements cannot be nested", statement->getFirstLine()));
+ }
+
+ // look up source file instance
+ std::string * fromSourceName = statement->getSourceName();
+ assert(fromSourceName);
+
+ // make sure it's a valid source name
+ source_map_t::iterator sourceIt = m_sources.find(*fromSourceName);
+ if (sourceIt == m_sources.end())
+ {
+ throw semantic_error(format_string("line %d: bad source name", statement->getFirstLine()));
+ }
+
+ // set default source
+ m_defaultSource = sourceIt->second;
+ assert(m_defaultSource);
+
+ // get statements inside the from block
+ ListASTNode * fromStatements = statement->getStatements();
+ assert(fromStatements);
+
+ // produce resulting operation sequence
+ OperationSequence * result = convertStatementList(fromStatements);
+
+ // restore default source to NULL
+ m_defaultSource = NULL;
+
+ return result;
+}
+
+//! Evaluates the expression to get the new boot mode value. Then creates a
+//! BootModeOperation object and returns an OperationSequence containing it.
+//!
+//! \exception elftosb::semantic_error Thrown if a semantic problem is found with
+//! the boot mode expression.
+OperationSequence * ConversionController::convertModeStatement(ModeStatementASTNode * statement)
+{
+ BootModeOperation * op = NULL;
+
+ try
+ {
+ op = new BootModeOperation();
+
+ // evaluate the boot mode expression
+ ExprASTNode * modeExprNode = statement->getModeExpr();
+ if (!modeExprNode)
+ {
+ throw semantic_error(format_string("line %d: mode statement has invalid boot mode expression", statement->getFirstLine()));
+ }
+ modeExprNode = modeExprNode->reduce(m_context);
+ IntConstExprASTNode * intNode = dynamic_cast<IntConstExprASTNode*>(modeExprNode);
+ if (!intNode)
+ {
+ throw semantic_error(format_string("line %d: boot mode did not evaluate to an integer", statement->getFirstLine()));
+ }
+
+ op->setBootMode(intNode->getValue());
+
+ return new OperationSequence(op);
+ }
+ catch (...)
+ {
+ if (op)
+ {
+ delete op;
+ }
+
+ // rethrow exception
+ throw;
+ }
+}
+
+//! Else branches, including else-if, are handled recursively, so there is a limit
+//! on the number of them based on the stack size.
+//!
+//! \return Returns the operation sequence for the branch of the if statement that
+//! evaluated to true. If the statement did not have an else branch and the
+//! condition expression evaluated to false, then NULL will be returned.
+//!
+//! \todo Handle else branches without recursion.
+OperationSequence * ConversionController::convertIfStatement(IfStatementASTNode * statement)
+{
+ // Get the if's conditional expression.
+ ExprASTNode * conditionalExpr = statement->getConditionExpr();
+ if (!conditionalExpr)
+ {
+ throw semantic_error(format_string("line %d: missing or invalid conditional expression", statement->getFirstLine()));
+ }
+
+ // Reduce the conditional to a single integer.
+ conditionalExpr = conditionalExpr->reduce(m_context);
+ IntConstExprASTNode * intNode = dynamic_cast<IntConstExprASTNode*>(conditionalExpr);
+ if (!intNode)
+ {
+ throw semantic_error(format_string("line %d: if statement conditional expression did not evaluate to an integer", statement->getFirstLine()));
+ }
+
+ // Decide which statements to further process by the conditional's boolean value.
+ if (intNode->getValue() && statement->getIfStatements())
+ {
+ return convertStatementList(statement->getIfStatements());
+ }
+ else if (statement->getElseStatements())
+ {
+ return convertStatementList(statement->getElseStatements());
+ }
+ else
+ {
+ // No else branch and the conditional was false, so there are no operations to return.
+ return NULL;
+ }
+}
+
+//! Message statements are executed immediately, by this method. They are
+//! not converted into an abstract operation. All messages are passed through
+//! substituteVariables() before being output.
+//!
+//! \param statement The message statement AST node object.
+void ConversionController::handleMessageStatement(MessageStatementASTNode * statement)
+{
+ string * message = statement->getMessage();
+ if (!message)
+ {
+ throw runtime_error("message statement had no message");
+ }
+
+ smart_ptr<string> finalMessage = substituteVariables(message);
+
+ switch (statement->getType())
+ {
+ case MessageStatementASTNode::kInfo:
+ Log::log(Logger::INFO, "%s\n", finalMessage->c_str());
+ break;
+
+ case MessageStatementASTNode::kWarning:
+ Log::log(Logger::WARNING, "warning: %s\n", finalMessage->c_str());
+ break;
+
+ case MessageStatementASTNode::kError:
+ throw runtime_error(*finalMessage);
+ break;
+ }
+}
+
+//! Performs shell-like variable substitution on the string passed into it.
+//! Both sources and constants can be substituted. Sources will be replaced
+//! with their path and constants with their integer value. The syntax allows
+//! for some simple formatting for constants.
+//!
+//! The syntax is mostly standard. A substitution begins with a dollar-sign
+//! and is followed by the source or constant name in parentheses. For instance,
+//! "$(mysource)" or "$(myconst)". The parentheses are always required.
+//!
+//! Constant names can be prefixed by a single formatting character followed
+//! by a colon. The only formatting characters currently supported are 'd' for
+//! decimal and 'x' for hex. For example, "$(x:myconst)" will be replaced with
+//! the value of the constant named "myconst" formatted as hexadecimal. The
+//! default is decimal, so the 'd' formatting character isn't really ever
+//! needed.
+//!
+//! \param message The string to perform substitution on.
+//! \return Returns a newly allocated std::string object that has all
+//! substitutions replaced with the associated value. The caller is
+//! responsible for freeing the string object using the delete operator.
+std::string * ConversionController::substituteVariables(const std::string * message)
+{
+ string * result = new string();
+ int i;
+ int state = 0;
+ string name;
+
+ for (i=0; i < message->size(); ++i)
+ {
+ char c = (*message)[i];
+ switch (state)
+ {
+ case 0:
+ if (c == '$')
+ {
+ state = 1;
+ }
+ else
+ {
+ (*result) += c;
+ }
+ break;
+
+ case 1:
+ if (c == '(')
+ {
+ state = 2;
+ }
+ else
+ {
+ // Wasn't a variable substitution, so revert to initial state after
+ // inserting the original characters.
+ (*result) += '$';
+ (*result) += c;
+ state = 0;
+ }
+ break;
+
+ case 2:
+ if (c == ')')
+ {
+ // Try the name as a source name first.
+ if (m_sources.find(name) != m_sources.end())
+ {
+ (*result) += m_sources[name]->getPath();
+ }
+ // Otherwise try it as a variable.
+ else
+ {
+ // Select format.
+ const char * fmt = "%d";
+ if (name[1] == ':' && (name[0] == 'd' || name[0] == 'x'))
+ {
+ if (name[0] == 'x')
+ {
+ fmt = "0x%x";
+ }
+
+ // Delete the format characters.
+ name.erase(0, 2);
+ }
+
+ // Now insert the formatted variable if it exists.
+ if (m_context.isVariableDefined(name))
+ {
+ (*result) += format_string(fmt, m_context.getVariableValue(name));
+ }
+ }
+
+ // Switch back to initial state and clear name.
+ state = 0;
+ name.clear();
+ }
+ else
+ {
+ // Just keep building up the variable name.
+ name += c;
+ }
+ break;
+ }
+ }
+
+ return result;
+}
+
+//!
+//! \param generator The generator to use.
+BootImage * ConversionController::generateOutput(BootImageGenerator * generator)
+{
+ // set the generator's option context
+ generator->setOptionContext(this);
+
+ // add output sections to the generator in sequence
+ section_vector_t::iterator it = m_outputSections.begin();
+ for (; it != m_outputSections.end(); ++it)
+ {
+ generator->addOutputSection(*it);
+ }
+
+ // and produce the output
+ BootImage * image = generator->generate();
+// Log::log("boot image = %p\n", image);
+ return image;
+}
+
+//! Takes an AST node that is one of the following subclasses and creates the corresponding
+//! type of DataSource object from it.
+//! - StringConstASTNode
+//! - ExprASTNode
+//! - SourceASTNode
+//! - SectionASTNode
+//! - SectionMatchListASTNode
+//! - BlobConstASTNode
+//! - IVTConstASTNode
+//!
+//! \exception elftosb::semantic_error Thrown if a semantic problem is found with
+//! the data node.
+//! \exception std::runtime_error Thrown if an error occurs that shouldn't be possible
+//! based on the grammar.
+DataSource * ConversionController::createSourceFromNode(ASTNode * dataNode)
+{
+ assert(dataNode);
+
+ DataSource * source = NULL;
+ StringConstASTNode * stringNode;
+ BlobConstASTNode * blobNode;
+ ExprASTNode * exprNode;
+ SourceASTNode * sourceNode;
+ SectionASTNode * sectionNode;
+ SectionMatchListASTNode * matchListNode;
+ IVTConstASTNode * ivtNode;
+
+ if (stringNode = dynamic_cast<StringConstASTNode*>(dataNode))
+ {
+ // create a data source with the string contents
+ std::string * stringData = stringNode->getString();
+ const uint8_t * stringContents = reinterpret_cast<const uint8_t *>(stringData->c_str());
+ source = new UnmappedDataSource(stringContents, static_cast<unsigned>(stringData->size()));
+ }
+ else if (blobNode = dynamic_cast<BlobConstASTNode*>(dataNode))
+ {
+ // create a data source with the raw binary data
+ Blob * blob = blobNode->getBlob();
+ source = new UnmappedDataSource(blob->getData(), blob->getLength());
+ }
+ else if (exprNode = dynamic_cast<ExprASTNode*>(dataNode))
+ {
+ // reduce the expression first
+ exprNode = exprNode->reduce(m_context);
+ IntConstExprASTNode * intNode = dynamic_cast<IntConstExprASTNode*>(exprNode);
+ if (!intNode)
+ {
+ throw semantic_error("load pattern expression did not evaluate to an integer");
+ }
+
+ SizedIntegerValue intValue(intNode->getValue(), intNode->getSize());
+ source = new PatternSource(intValue);
+ }
+ else if (sourceNode = dynamic_cast<SourceASTNode*>(dataNode))
+ {
+ // load the entire source contents
+ SourceFile * sourceFile = getSourceFromName(sourceNode->getSourceName(), sourceNode->getFirstLine());
+ source = sourceFile->createDataSource();
+ }
+ else if (sectionNode = dynamic_cast<SectionASTNode*>(dataNode))
+ {
+ // load some subset of the source
+ SourceFile * sourceFile = getSourceFromName(sectionNode->getSourceName(), sectionNode->getFirstLine());
+ if (!sourceFile->supportsNamedSections())
+ {
+ throw semantic_error(format_string("line %d: source does not support sections", sectionNode->getFirstLine()));
+ }
+
+ // create data source from the section name
+ std::string * sectionName = sectionNode->getSectionName();
+ GlobMatcher globber(*sectionName);
+ source = sourceFile->createDataSource(globber);
+ if (!source)
+ {
+ throw semantic_error(format_string("line %d: no sections match the pattern", sectionNode->getFirstLine()));
+ }
+ }
+ else if (matchListNode = dynamic_cast<SectionMatchListASTNode*>(dataNode))
+ {
+ SourceFile * sourceFile = getSourceFromName(matchListNode->getSourceName(), matchListNode->getFirstLine());
+ if (!sourceFile->supportsNamedSections())
+ {
+ throw semantic_error(format_string("line %d: source type does not support sections", matchListNode->getFirstLine()));
+ }
+
+ // create string matcher
+ ExcludesListMatcher matcher;
+
+ // add each pattern to the matcher
+ ListASTNode * matchList = matchListNode->getSections();
+ ListASTNode::iterator it = matchList->begin();
+ for (; it != matchList->end(); ++it)
+ {
+ ASTNode * node = *it;
+ sectionNode = dynamic_cast<SectionASTNode*>(node);
+ if (!sectionNode)
+ {
+ throw std::runtime_error(format_string("line %d: unexpected node type in section pattern list", (*it)->getFirstLine()));
+ }
+ bool isInclude = sectionNode->getAction() == SectionASTNode::kInclude;
+ matcher.addPattern(isInclude, *(sectionNode->getSectionName()));
+ }
+
+ // create data source from the section match list
+ source = sourceFile->createDataSource(matcher);
+ if (!source)
+ {
+ throw semantic_error(format_string("line %d: no sections match the section pattern list", matchListNode->getFirstLine()));
+ }
+ }
+ else if (ivtNode = dynamic_cast<IVTConstASTNode*>(dataNode))
+ {
+ source = createIVTDataSource(ivtNode);
+ }
+ else
+ {
+ throw semantic_error(format_string("line %d: unexpected load data node type", dataNode->getFirstLine()));
+ }
+
+ return source;
+}
+
+DataSource * ConversionController::createIVTDataSource(IVTConstASTNode * ivtNode)
+{
+ IVTDataSource * source = new IVTDataSource;
+
+ // Iterate over the assignment statements in the IVT definition.
+ ListASTNode * fieldList = ivtNode->getFieldAssignments();
+
+ if (fieldList)
+ {
+ ListASTNode::iterator it = fieldList->begin();
+ for (; it != fieldList->end(); ++it)
+ {
+ AssignmentASTNode * assignmentNode = dynamic_cast<AssignmentASTNode*>(*it);
+ if (!assignmentNode)
+ {
+ throw std::runtime_error(format_string("line %d: unexpected node type in IVT definition", (*it)->getFirstLine()));
+ }
+
+ // Get the IVT field name.
+ std::string * fieldName = assignmentNode->getIdent();
+
+ // Reduce the field expression and get the integer result.
+ ASTNode * valueNode = assignmentNode->getValue();
+ ExprASTNode * valueExpr = dynamic_cast<ExprASTNode*>(valueNode);
+ if (!valueExpr)
+ {
+ throw semantic_error("IVT field must have a valid expression");
+ }
+ IntConstExprASTNode * valueIntExpr = dynamic_cast<IntConstExprASTNode*>(valueExpr->reduce(m_context));
+ if (!valueIntExpr)
+ {
+ throw semantic_error(format_string("line %d: IVT field '%s' does not evaluate to an integer", valueNode->getFirstLine(), fieldName->c_str()));
+ }
+ uint32_t value = static_cast<uint32_t>(valueIntExpr->getValue());
+
+ // Set the field in the IVT data source.
+ if (!source->setFieldByName(*fieldName, value))
+ {
+ throw semantic_error(format_string("line %d: unknown IVT field '%s'", assignmentNode->getFirstLine(), fieldName->c_str()));
+ }
+ }
+ }
+
+ return source;
+}
+
+//! Takes an AST node subclass and returns an appropriate DataTarget object that contains
+//! the same information. Supported AST node types are:
+//! - SymbolASTNode
+//! - NaturalLocationASTNode
+//! - AddressRangeASTNode
+//!
+//! \exception elftosb::semantic_error Thrown if a semantic problem is found with
+//! the target node.
+DataTarget * ConversionController::createTargetFromNode(ASTNode * targetNode)
+{
+ assert(targetNode);
+
+ DataTarget * target = NULL;
+ SymbolASTNode * symbolNode;
+ NaturalLocationASTNode * naturalNode;
+ AddressRangeASTNode * addressNode;
+
+ if (symbolNode = dynamic_cast<SymbolASTNode*>(targetNode))
+ {
+ SourceFile * sourceFile = getSourceFromName(symbolNode->getSource(), symbolNode->getFirstLine());
+ std::string * symbolName = symbolNode->getSymbolName();
+
+ // symbol name is optional
+ if (symbolName)
+ {
+ if (!sourceFile->supportsNamedSymbols())
+ {
+ throw std::runtime_error(format_string("line %d: source does not support symbols", symbolNode->getFirstLine()));
+ }
+
+ target = sourceFile->createDataTargetForSymbol(*symbolName);
+ if (!target)
+ {
+ throw std::runtime_error(format_string("line %d: source does not have a symbol with that name", symbolNode->getFirstLine()));
+ }
+ }
+ else
+ {
+ // no symbol name was specified so use entry point
+ target = sourceFile->createDataTargetForEntryPoint();
+ if (!target)
+ {
+ throw std::runtime_error(format_string("line %d: source does not have an entry point", symbolNode->getFirstLine()));
+ }
+ }
+ }
+ else if (naturalNode = dynamic_cast<NaturalLocationASTNode*>(targetNode))
+ {
+ // the target is the source's natural location
+ target = new NaturalDataTarget();
+ }
+ else if (addressNode = dynamic_cast<AddressRangeASTNode*>(targetNode))
+ {
+ // evaluate begin address
+ ExprASTNode * beginExpr = dynamic_cast<ExprASTNode*>(addressNode->getBegin());
+ if (!beginExpr)
+ {
+ throw semantic_error("address range must always have a beginning expression");
+ }
+ IntConstExprASTNode * beginIntExpr = dynamic_cast<IntConstExprASTNode*>(beginExpr->reduce(m_context));
+ if (!beginIntExpr)
+ {
+ throw semantic_error("address range begin did not evaluate to an integer");
+ }
+ uint32_t beginAddress = static_cast<uint32_t>(beginIntExpr->getValue());
+
+ // evaluate end address
+ ExprASTNode * endExpr = dynamic_cast<ExprASTNode*>(addressNode->getEnd());
+ uint32_t endAddress = 0;
+ bool hasEndAddress = false;
+ if (endExpr)
+ {
+ IntConstExprASTNode * endIntExpr = dynamic_cast<IntConstExprASTNode*>(endExpr->reduce(m_context));
+ if (!endIntExpr)
+ {
+ throw semantic_error("address range end did not evaluate to an integer");
+ }
+ endAddress = static_cast<uint32_t>(endIntExpr->getValue());
+ hasEndAddress = true;
+ }
+
+ // create target
+ if (hasEndAddress)
+ {
+ target = new ConstantDataTarget(beginAddress, endAddress);
+ }
+ else
+ {
+ target = new ConstantDataTarget(beginAddress);
+ }
+ }
+ else
+ {
+ throw semantic_error("unexpected load target node type");
+ }
+
+ return target;
+}
+
+//! \param sourceName Pointer to string containing the name of the source to look up.
+//! May be NULL, in which case the default source is used.
+//! \param line The line number on which the source name was located.
+//!
+//! \result A source file object that was previously created in the processSources()
+//! stage.
+//!
+//! \exception std::runtime_error Thrown if the source name is invalid, or if it
+//! was NULL and there is no default source (i.e., we're not inside a from
+//! statement).
+SourceFile * ConversionController::getSourceFromName(std::string * sourceName, int line)
+{
+ SourceFile * sourceFile = NULL;
+ if (sourceName)
+ {
+ // look up source in map
+ source_map_t::iterator it = m_sources.find(*sourceName);
+ if (it == m_sources.end())
+ {
+ source_name_vector_t::const_iterator findIt = std::find<source_name_vector_t::const_iterator, std::string>(m_failedSources.begin(), m_failedSources.end(), *sourceName);
+ if (findIt != m_failedSources.end())
+ {
+ throw semantic_error(format_string("line %d: error opening source '%s'", line, sourceName->c_str()));
+ }
+ else
+ {
+ throw semantic_error(format_string("line %d: invalid source name '%s'", line, sourceName->c_str()));
+ }
+ }
+ sourceFile = it->second;
+ }
+ else
+ {
+ // no name provided - use default source
+ sourceFile = m_defaultSource;
+ if (!sourceFile)
+ {
+ throw semantic_error(format_string("line %d: source required but no default source is available", line));
+ }
+ }
+
+ // open the file if it hasn't already been
+ if (!sourceFile->isOpen())
+ {
+ sourceFile->open();
+ }
+ return sourceFile;
+}
+
+//! Exercises the lexer by printing out the value of every token produced by the
+//! lexer. It is assumed that the lexer object has already be configured to read
+//! from some input file. The method will return when the lexer has exhausted all
+//! tokens, or an error occurs.
+void ConversionController::testLexer(ElftosbLexer & lexer)
+{
+ // test lexer
+ while (1)
+ {
+ YYSTYPE value;
+ int lexresult = lexer.yylex();
+ if (lexresult == 0)
+ break;
+ lexer.getSymbolValue(&value);
+ Log::log("%d -> int:%d, ast:%p", lexresult, value.m_int, value.m_str, value.m_ast);
+ if (lexresult == TOK_IDENT || lexresult == TOK_SOURCE_NAME || lexresult == TOK_STRING_LITERAL)
+ {
+ if (value.m_str)
+ {
+ Log::log(", str:%s\n", value.m_str->c_str());
+ }
+ else
+ {
+ Log::log("str:NULL\n");
+ }
+ }
+ else
+ {
+ Log::log("\n");
+ }
+ }
+}
+
+//! Prints out the value of an integer constant expression AST node. Also prints
+//! the name of the identifier associated with that node, as well as the integer
+//! size.
+void ConversionController::printIntConstExpr(const std::string & ident, IntConstExprASTNode * expr)
+{
+ // print constant value
+ char sizeChar;
+ switch (expr->getSize())
+ {
+ case kWordSize:
+ sizeChar = 'w';
+ break;
+ case kHalfWordSize:
+ sizeChar = 'h';
+ break;
+ case kByteSize:
+ sizeChar = 'b';
+ break;
+ }
+ Log::log("%s => %d:%c\n", ident.c_str(), expr->getValue(), sizeChar);
+}
+
--- /dev/null
+/*
+ * File: ConversionController.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_ConversionController_h_)
+#define _ConversionController_h_
+
+#include <iostream>
+#include <fstream>
+#include <string>
+#include <stdexcept>
+#include <smart_ptr.h>
+#include <ElftosbLexer.h>
+#include <ElftosbAST.h>
+#include "EvalContext.h"
+#include "Value.h"
+#include "SourceFile.h"
+#include "Operation.h"
+#include "DataSource.h"
+#include "DataTarget.h"
+#include "OutputSection.h"
+#include "BootImage.h"
+#include "OptionDictionary.h"
+#include "BootImageGenerator.h"
+
+namespace elftosb
+{
+
+/*!
+ * \brief Manages the entire elftosb file conversion process.
+ *
+ * Instances of this class are intended to be used only once. There is no
+ * way to reset an instance once it has started or completed a conversion.
+ * Thus the run() method is not reentrant. State information is stored in
+ * the object during the conversion process.
+ *
+ * Two things need to be done before the conversion can be started. The
+ * command file path has to be set with the setCommandFilePath() method,
+ * and the paths of any externally provided (i.e., from the command line)
+ * files need to be added with addExternalFilePath(). Once these tasks
+ * are completed, the run() method can be called to parse and execute the
+ * command file. After run() returns, pass an instance of
+ * BootImageGenerator to the generateOutput() method in order to get
+ * an instance of BootImage that can be written to the output file.
+ */
+class ConversionController : public OptionDictionary, public EvalContext::SourceFileManager
+{
+public:
+ //! \brief Default constructor.
+ ConversionController();
+
+ //! \brief Destructor.
+ virtual ~ConversionController();
+
+ //! \name Paths
+ //@{
+ //! \brief Specify the command file that controls the conversion process.
+ void setCommandFilePath(const std::string & path);
+
+ //! \brief Specify the path of a file provided by the user from outside the command file.
+ void addExternalFilePath(const std::string & path);
+ //@}
+
+ //! \name Conversion
+ //@{
+ //! \brief Process input files.
+ void run();
+
+ //! \brief Uses a BootImageGenerator object to create the final output boot image.
+ BootImage * generateOutput(BootImageGenerator * generator);
+ //@}
+
+ //! \name SourceFileManager interface
+ //@{
+ //! \brief Returns true if a source file with the name \a name exists.
+ virtual bool hasSourceFile(const std::string & name);
+
+ //! \brief Gets the requested source file.
+ virtual SourceFile * getSourceFile(const std::string & name);
+
+ //! \brief Returns the default source file, or NULL if none is set.
+ virtual SourceFile * getDefaultSourceFile();
+ //@}
+
+ //! \brief Returns a reference to the context used for expression evaluation.
+ inline EvalContext & getEvalContext() { return m_context; }
+
+protected:
+ //! \name AST processing
+ //@{
+ void parseCommandFile();
+ void processOptions(ListASTNode * options);
+ void processConstants(ListASTNode * constants);
+ void processSources(ListASTNode * sources);
+ void processSections(ListASTNode * sections);
+ OutputSection * convertDataSection(DataSectionContentsASTNode * dataSection, uint32_t sectionID, OptionDictionary * optionsDict);
+ //@}
+
+ //! \name Statement conversion
+ //@{
+ OperationSequence * convertStatementList(ListASTNode * statements);
+ OperationSequence * convertOneStatement(StatementASTNode * statement);
+ OperationSequence * convertLoadStatement(LoadStatementASTNode * statement);
+ OperationSequence * convertCallStatement(CallStatementASTNode * statement);
+ OperationSequence * convertFromStatement(FromStatementASTNode * statement);
+ OperationSequence * convertModeStatement(ModeStatementASTNode * statement);
+ OperationSequence * convertIfStatement(IfStatementASTNode * statement);
+ void handleMessageStatement(MessageStatementASTNode * statement);
+ //@}
+
+ //! \name Utilities
+ //@{
+ Value * convertAssignmentNodeToValue(ASTNode * node, std::string & ident);
+ SourceFile * getSourceFromName(std::string * sourceName, int line);
+ DataSource * createSourceFromNode(ASTNode * dataNode);
+ DataTarget * createTargetFromNode(ASTNode * targetNode);
+ std::string * substituteVariables(const std::string * message);
+ DataSource * createIVTDataSource(IVTConstASTNode * ivtNode);
+ //@}
+
+ //! \name Debugging
+ //@{
+ void testLexer(ElftosbLexer & lexer);
+ void printIntConstExpr(const std::string & ident, IntConstExprASTNode * expr);
+ //@}
+
+protected:
+ typedef std::map<std::string, SourceFile*> source_map_t; //!< Map from source name to object.
+ typedef std::vector<std::string> path_vector_t; //!< List of file paths.
+ typedef std::vector<OutputSection*> section_vector_t; //!< List of output sections.
+ typedef std::vector<std::string> source_name_vector_t; //!< List of source names.
+
+ smart_ptr<std::string> m_commandFilePath; //!< Path to command file.
+ smart_ptr<CommandFileASTNode> m_ast; //!< Root of the abstract syntax tree.
+ EvalContext m_context; //!< Evaluation context for expressions.
+ source_map_t m_sources; //!< Map of source names to file objects.
+ path_vector_t m_externPaths; //!< Paths provided on the command line by the user.
+ SourceFile * m_defaultSource; //!< Source to use when one isn't provided.
+ section_vector_t m_outputSections; //!< List of output sections the user wants.
+ source_name_vector_t m_failedSources; //!< List of sources that failed to open successfully.
+};
+
+//! \brief Whether to support HAB keywords during parsing.
+//!
+//! This is a standalone global solely so that the bison-generated parser code can get to it
+//! as simply as possible.
+extern bool g_enableHABSupport;
+
+}; // namespace elftosb
+
+#endif // _ConversionController_h_
--- /dev/null
+# Doxyfile 1.3.9
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+PROJECT_NAME = elftosb
+PROJECT_NUMBER = 2.0
+OUTPUT_DIRECTORY = .
+CREATE_SUBDIRS = YES
+OUTPUT_LANGUAGE = English
+USE_WINDOWS_ENCODING = YES
+BRIEF_MEMBER_DESC = YES
+REPEAT_BRIEF = YES
+ABBREVIATE_BRIEF = "The $name class" \
+ "The $name widget" \
+ "The $name file" \
+ is \
+ provides \
+ specifies \
+ contains \
+ represents \
+ a \
+ an \
+ the
+ALWAYS_DETAILED_SEC = NO
+INLINE_INHERITED_MEMB = NO
+FULL_PATH_NAMES = NO
+STRIP_FROM_PATH = "/Users/creed/projects/elftosb/elftosb2" \
+ "/Users/creed/projects/sgtl/elftosb/sbtool" \
+ "/Users/creed/projects/elftosb/common" \
+ "/Users/creed/projects/sgtl/elftosb/common"
+STRIP_FROM_INC_PATH =
+SHORT_NAMES = NO
+JAVADOC_AUTOBRIEF = NO
+MULTILINE_CPP_IS_BRIEF = NO
+DETAILS_AT_TOP = YES
+INHERIT_DOCS = YES
+DISTRIBUTE_GROUP_DOC = NO
+TAB_SIZE = 4
+ALIASES =
+OPTIMIZE_OUTPUT_FOR_C = NO
+OPTIMIZE_OUTPUT_JAVA = NO
+SUBGROUPING = YES
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL = YES
+EXTRACT_PRIVATE = YES
+EXTRACT_STATIC = YES
+EXTRACT_LOCAL_CLASSES = YES
+EXTRACT_LOCAL_METHODS = NO
+HIDE_UNDOC_MEMBERS = NO
+HIDE_UNDOC_CLASSES = NO
+HIDE_FRIEND_COMPOUNDS = NO
+HIDE_IN_BODY_DOCS = NO
+INTERNAL_DOCS = NO
+CASE_SENSE_NAMES = NO
+HIDE_SCOPE_NAMES = NO
+SHOW_INCLUDE_FILES = YES
+INLINE_INFO = YES
+SORT_MEMBER_DOCS = YES
+SORT_BRIEF_DOCS = NO
+SORT_BY_SCOPE_NAME = NO
+GENERATE_TODOLIST = YES
+GENERATE_TESTLIST = YES
+GENERATE_BUGLIST = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS =
+MAX_INITIALIZER_LINES = 30
+SHOW_USED_FILES = YES
+SHOW_DIRECTORIES = YES
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET = NO
+WARNINGS = YES
+WARN_IF_UNDOCUMENTED = YES
+WARN_IF_DOC_ERROR = YES
+WARN_FORMAT = "$file:$line: $text"
+WARN_LOGFILE =
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT = . ../common
+FILE_PATTERNS = *.c \
+ *.cc \
+ *.cxx \
+ *.cpp \
+ *.c++ \
+ *.java \
+ *.ii \
+ *.ixx \
+ *.ipp \
+ *.i++ \
+ *.inl \
+ *.h \
+ *.hh \
+ *.hxx \
+ *.hpp \
+ *.h++ \
+ *.idl \
+ *.odl \
+ *.cs \
+ *.php \
+ *.php3 \
+ *.inc \
+ *.m \
+ *.mm
+RECURSIVE = NO
+EXCLUDE =
+EXCLUDE_SYMLINKS = NO
+EXCLUDE_PATTERNS =
+EXAMPLE_PATH =
+EXAMPLE_PATTERNS = *
+EXAMPLE_RECURSIVE = NO
+IMAGE_PATH =
+INPUT_FILTER =
+FILTER_PATTERNS =
+FILTER_SOURCE_FILES = NO
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER = NO
+INLINE_SOURCES = NO
+STRIP_CODE_COMMENTS = YES
+REFERENCED_BY_RELATION = NO
+REFERENCES_RELATION = NO
+VERBATIM_HEADERS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX = NO
+COLS_IN_ALPHA_INDEX = 5
+IGNORE_PREFIX =
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML = YES
+HTML_OUTPUT = html
+HTML_FILE_EXTENSION = .html
+HTML_HEADER =
+HTML_FOOTER =
+HTML_STYLESHEET =
+HTML_ALIGN_MEMBERS = YES
+GENERATE_HTMLHELP = NO
+CHM_FILE =
+HHC_LOCATION =
+GENERATE_CHI = NO
+BINARY_TOC = NO
+TOC_EXPAND = NO
+DISABLE_INDEX = NO
+ENUM_VALUES_PER_LINE = 4
+GENERATE_TREEVIEW = YES
+TREEVIEW_WIDTH = 250
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX = NO
+LATEX_OUTPUT = latex
+LATEX_CMD_NAME = latex
+MAKEINDEX_CMD_NAME = makeindex
+COMPACT_LATEX = NO
+PAPER_TYPE = a4wide
+EXTRA_PACKAGES =
+LATEX_HEADER =
+PDF_HYPERLINKS = NO
+USE_PDFLATEX = NO
+LATEX_BATCHMODE = NO
+LATEX_HIDE_INDICES = NO
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF = NO
+RTF_OUTPUT = rtf
+COMPACT_RTF = NO
+RTF_HYPERLINKS = NO
+RTF_STYLESHEET_FILE =
+RTF_EXTENSIONS_FILE =
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN = NO
+MAN_OUTPUT = man
+MAN_EXTENSION = .3
+MAN_LINKS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML = NO
+XML_OUTPUT = xml
+XML_SCHEMA =
+XML_DTD =
+XML_PROGRAMLISTING = YES
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF = NO
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD = NO
+PERLMOD_LATEX = NO
+PERLMOD_PRETTY = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING = YES
+MACRO_EXPANSION = NO
+EXPAND_ONLY_PREDEF = NO
+SEARCH_INCLUDES = YES
+INCLUDE_PATH =
+INCLUDE_FILE_PATTERNS =
+PREDEFINED =
+EXPAND_AS_DEFINED =
+SKIP_FUNCTION_MACROS = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+TAGFILES =
+GENERATE_TAGFILE =
+ALLEXTERNALS = NO
+EXTERNAL_GROUPS = YES
+PERL_PATH = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS = NO
+HIDE_UNDOC_RELATIONS = YES
+HAVE_DOT = NO
+CLASS_GRAPH = YES
+COLLABORATION_GRAPH = YES
+UML_LOOK = NO
+TEMPLATE_RELATIONS = NO
+INCLUDE_GRAPH = YES
+INCLUDED_BY_GRAPH = YES
+CALL_GRAPH = NO
+GRAPHICAL_HIERARCHY = YES
+DOT_IMAGE_FORMAT = png
+DOT_PATH =
+DOTFILE_DIRS =
+MAX_DOT_GRAPH_WIDTH = 1024
+MAX_DOT_GRAPH_HEIGHT = 1024
+MAX_DOT_GRAPH_DEPTH = 1000
+GENERATE_LEGEND = YES
+DOT_CLEANUP = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to the search engine
+#---------------------------------------------------------------------------
+SEARCHENGINE = NO
--- /dev/null
+/*
+ * File: ElftosbAST.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "ElftosbAST.h"
+#include <stdexcept>
+#include <math.h>
+#include <assert.h>
+#include "ElftosbErrors.h"
+#include "format_string.h"
+
+using namespace elftosb;
+
+#pragma mark = ASTNode =
+
+void ASTNode::printTree(int indent) const
+{
+ printIndent(indent);
+ printf("%s\n", nodeName().c_str());
+}
+
+void ASTNode::printIndent(int indent) const
+{
+ int i;
+ for (i=0; i<indent; ++i)
+ {
+ printf(" ");
+ }
+}
+
+void ASTNode::setLocation(token_loc_t & first, token_loc_t & last)
+{
+ m_location.m_firstLine = first.m_firstLine;
+ m_location.m_lastLine = last.m_lastLine;
+}
+
+void ASTNode::setLocation(ASTNode * first, ASTNode * last)
+{
+ m_location.m_firstLine = first->getLocation().m_firstLine;
+ m_location.m_lastLine = last->getLocation().m_lastLine;
+}
+
+#pragma mark = ListASTNode =
+
+ListASTNode::ListASTNode(const ListASTNode & other)
+: ASTNode(other), m_list()
+{
+ // deep copy each item of the original's list
+ const_iterator it = other.begin();
+ for (; it != other.end(); ++it)
+ {
+ m_list.push_back((*it)->clone());
+ }
+}
+
+//! Deletes child node in the list.
+//!
+ListASTNode::~ListASTNode()
+{
+ iterator it = begin();
+ for (; it != end(); it++)
+ {
+ delete *it;
+ }
+}
+
+//! If \a node is NULL then the list is left unmodified.
+//!
+//! The list node's location is automatically updated after the node is added by a call
+//! to updateLocation().
+void ListASTNode::appendNode(ASTNode * node)
+{
+ if (node)
+ {
+ m_list.push_back(node);
+ updateLocation();
+ }
+}
+
+void ListASTNode::printTree(int indent) const
+{
+ ASTNode::printTree(indent);
+
+ int n = 0;
+ const_iterator it = begin();
+ for (; it != end(); it++, n++)
+ {
+ printIndent(indent + 1);
+ printf("%d:\n", n);
+ (*it)->printTree(indent + 2);
+ }
+}
+
+void ListASTNode::updateLocation()
+{
+ token_loc_t current = { 0 };
+ const_iterator it = begin();
+ for (; it != end(); it++)
+ {
+ const ASTNode * node = *it;
+ const token_loc_t & loc = node->getLocation();
+
+ // handle first node
+ if (current.m_firstLine == 0)
+ {
+ current = loc;
+ continue;
+ }
+
+ if (loc.m_firstLine < current.m_firstLine)
+ {
+ current.m_firstLine = loc.m_firstLine;
+ }
+
+ if (loc.m_lastLine > current.m_lastLine)
+ {
+ current.m_lastLine = loc.m_lastLine;
+ }
+ }
+
+ setLocation(current);
+}
+
+#pragma mark = CommandFileASTNode =
+
+CommandFileASTNode::CommandFileASTNode()
+: ASTNode(), m_options(), m_constants(), m_sources(), m_sections()
+{
+}
+
+CommandFileASTNode::CommandFileASTNode(const CommandFileASTNode & other)
+: ASTNode(other), m_options(), m_constants(), m_sources(), m_sections()
+{
+ m_options = dynamic_cast<ListASTNode*>(other.m_options->clone());
+ m_constants = dynamic_cast<ListASTNode*>(other.m_constants->clone());
+ m_sources = dynamic_cast<ListASTNode*>(other.m_sources->clone());
+ m_sections = dynamic_cast<ListASTNode*>(other.m_sections->clone());
+}
+
+void CommandFileASTNode::printTree(int indent) const
+{
+ ASTNode::printTree(indent);
+
+ printIndent(indent + 1);
+ printf("options:\n");
+ if (m_options) m_options->printTree(indent + 2);
+
+ printIndent(indent + 1);
+ printf("constants:\n");
+ if (m_constants) m_constants->printTree(indent + 2);
+
+ printIndent(indent + 1);
+ printf("sources:\n");
+ if (m_sources) m_sources->printTree(indent + 2);
+
+ printIndent(indent + 1);
+ printf("sections:\n");
+ if (m_sections) m_sections->printTree(indent + 2);
+}
+
+#pragma mark = ExprASTNode =
+
+int_size_t ExprASTNode::resultIntSize(int_size_t a, int_size_t b)
+{
+ int_size_t result;
+ switch (a)
+ {
+ case kWordSize:
+ result = kWordSize;
+ break;
+ case kHalfWordSize:
+ if (b == kWordSize)
+ {
+ result = kWordSize;
+ }
+ else
+ {
+ result = kHalfWordSize;
+ }
+ break;
+ case kByteSize:
+ if (b == kWordSize)
+ {
+ result = kWordSize;
+ }
+ else if (b == kHalfWordSize)
+ {
+ result = kHalfWordSize;
+ }
+ else
+ {
+ result = kByteSize;
+ }
+ break;
+ }
+
+ return result;
+}
+
+#pragma mark = IntConstExprASTNode =
+
+IntConstExprASTNode::IntConstExprASTNode(const IntConstExprASTNode & other)
+: ExprASTNode(other), m_value(other.m_value), m_size(other.m_size)
+{
+}
+
+void IntConstExprASTNode::printTree(int indent) const
+{
+ printIndent(indent);
+ char sizeChar='?';
+ switch (m_size)
+ {
+ case kWordSize:
+ sizeChar = 'w';
+ break;
+ case kHalfWordSize:
+ sizeChar = 'h';
+ break;
+ case kByteSize:
+ sizeChar = 'b';
+ break;
+ }
+ printf("%s(%d:%c)\n", nodeName().c_str(), m_value, sizeChar);
+}
+
+#pragma mark = VariableExprASTNode =
+
+VariableExprASTNode::VariableExprASTNode(const VariableExprASTNode & other)
+: ExprASTNode(other), m_variable()
+{
+ m_variable = new std::string(*other.m_variable);
+}
+
+void VariableExprASTNode::printTree(int indent) const
+{
+ printIndent(indent);
+ printf("%s(%s)\n", nodeName().c_str(), m_variable->c_str());
+}
+
+ExprASTNode * VariableExprASTNode::reduce(EvalContext & context)
+{
+ if (!context.isVariableDefined(*m_variable))
+ {
+ throw std::runtime_error(format_string("line %d: undefined variable '%s'", getFirstLine(), m_variable->c_str()));
+ }
+
+ uint32_t value = context.getVariableValue(*m_variable);
+ int_size_t size = context.getVariableSize(*m_variable);
+ return new IntConstExprASTNode(value, size);
+}
+
+#pragma mark = SymbolRefExprASTNode =
+
+SymbolRefExprASTNode::SymbolRefExprASTNode(const SymbolRefExprASTNode & other)
+: ExprASTNode(other), m_symbol(NULL)
+{
+ if (other.m_symbol)
+ {
+ m_symbol = dynamic_cast<SymbolASTNode*>(other.m_symbol->clone());
+ }
+}
+
+void SymbolRefExprASTNode::printTree(int indent) const
+{
+}
+
+ExprASTNode * SymbolRefExprASTNode::reduce(EvalContext & context)
+{
+ EvalContext::SourceFileManager * manager = context.getSourceFileManager();
+ if (!manager)
+ {
+ throw std::runtime_error("no source manager available");
+ }
+
+ if (!m_symbol)
+ {
+ throw semantic_error("no symbol provided");
+ }
+
+ // Get the name of the symbol
+ std::string * symbolName = m_symbol->getSymbolName();
+// if (!symbolName)
+// {
+// throw semantic_error(format_string("line %d: no symbol name provided", getFirstLine()));
+// }
+
+ // Get the source file.
+ std::string * sourceName = m_symbol->getSource();
+ SourceFile * sourceFile;
+
+ if (sourceName)
+ {
+ sourceFile = manager->getSourceFile(*sourceName);
+ if (!sourceFile)
+ {
+ throw semantic_error(format_string("line %d: no source file named %s", getFirstLine(), sourceName->c_str()));
+ }
+ }
+ else
+ {
+ sourceFile = manager->getDefaultSourceFile();
+ if (!sourceFile)
+ {
+ throw semantic_error(format_string("line %d: no default source file is set", getFirstLine()));
+ }
+ }
+
+ // open the file if it hasn't already been
+ if (!sourceFile->isOpen())
+ {
+ sourceFile->open();
+ }
+
+ // Make sure the source file supports symbols before going any further
+ if (symbolName && !sourceFile->supportsNamedSymbols())
+ {
+ throw semantic_error(format_string("line %d: source file %s does not support symbols", getFirstLine(), sourceFile->getPath().c_str()));
+ }
+
+ if (!symbolName && !sourceFile->hasEntryPoint())
+ {
+ throw semantic_error(format_string("line %d: source file %s does not have an entry point", getFirstLine(), sourceFile->getPath().c_str()));
+ }
+
+ // Returns a const expr node with the symbol's value.
+ uint32_t value;
+ if (symbolName)
+ {
+ value = sourceFile->getSymbolValue(*symbolName);
+ }
+ else
+ {
+ value = sourceFile->getEntryPointAddress();
+ }
+ return new IntConstExprASTNode(value);
+}
+
+#pragma mark = NegativeExprASTNode =
+
+NegativeExprASTNode::NegativeExprASTNode(const NegativeExprASTNode & other)
+: ExprASTNode(other), m_expr()
+{
+ m_expr = dynamic_cast<ExprASTNode*>(other.m_expr->clone());
+}
+
+void NegativeExprASTNode::printTree(int indent) const
+{
+ ExprASTNode::printTree(indent);
+ if (m_expr) m_expr->printTree(indent + 1);
+}
+
+ExprASTNode * NegativeExprASTNode::reduce(EvalContext & context)
+{
+ if (!m_expr)
+ {
+ return this;
+ }
+
+ m_expr = m_expr->reduce(context);
+ IntConstExprASTNode * intConst = dynamic_cast<IntConstExprASTNode*>(m_expr.get());
+ if (intConst)
+ {
+ int32_t value = -(int32_t)intConst->getValue();
+ return new IntConstExprASTNode((uint32_t)value, intConst->getSize());
+ }
+ else
+ {
+ return this;
+ }
+}
+
+#pragma mark = BooleanNotExprASTNode =
+
+BooleanNotExprASTNode::BooleanNotExprASTNode(const BooleanNotExprASTNode & other)
+: ExprASTNode(other), m_expr()
+{
+ m_expr = dynamic_cast<ExprASTNode*>(other.m_expr->clone());
+}
+
+void BooleanNotExprASTNode::printTree(int indent) const
+{
+ ExprASTNode::printTree(indent);
+ if (m_expr) m_expr->printTree(indent + 1);
+}
+
+ExprASTNode * BooleanNotExprASTNode::reduce(EvalContext & context)
+{
+ if (!m_expr)
+ {
+ return this;
+ }
+
+ m_expr = m_expr->reduce(context);
+ IntConstExprASTNode * intConst = dynamic_cast<IntConstExprASTNode*>(m_expr.get());
+ if (intConst)
+ {
+ int32_t value = !((int32_t)intConst->getValue());
+ return new IntConstExprASTNode((uint32_t)value, intConst->getSize());
+ }
+ else
+ {
+ throw semantic_error(format_string("line %d: expression did not evaluate to an integer", m_expr->getFirstLine()));
+ }
+}
+
+#pragma mark = SourceFileFunctionASTNode =
+
+SourceFileFunctionASTNode::SourceFileFunctionASTNode(const SourceFileFunctionASTNode & other)
+: ExprASTNode(other), m_functionName(), m_sourceFile()
+{
+ m_functionName = new std::string(*other.m_functionName);
+ m_sourceFile = new std::string(*other.m_sourceFile);
+}
+
+void SourceFileFunctionASTNode::printTree(int indent) const
+{
+ ExprASTNode::printTree(indent);
+ printIndent(indent+1);
+
+ // for some stupid reason the msft C++ compiler barfs on the following line if the ".get()" parts are remove,
+ // even though the first line of reduce() below has the same expression, just in parentheses. stupid compiler.
+ if (m_functionName.get() && m_sourceFile.get())
+ {
+ printf("%s ( %s )\n", m_functionName->c_str(), m_sourceFile->c_str());
+ }
+}
+
+ExprASTNode * SourceFileFunctionASTNode::reduce(EvalContext & context)
+{
+ if (!(m_functionName && m_sourceFile))
+ {
+ throw std::runtime_error("unset function name or source file");
+ }
+
+ // Get source file manager from evaluation context. This will be the
+ // conversion controller itself.
+ EvalContext::SourceFileManager * mgr = context.getSourceFileManager();
+ if (!mgr)
+ {
+ throw std::runtime_error("source file manager is not set");
+ }
+
+ // Perform function
+ uint32_t functionResult = 0;
+ if (*m_functionName == "exists")
+ {
+ functionResult = static_cast<uint32_t>(mgr->hasSourceFile(*m_sourceFile));
+ }
+
+ // Return function result as an expression node
+ return new IntConstExprASTNode(functionResult);
+}
+
+#pragma mark = DefinedOperatorASTNode =
+
+DefinedOperatorASTNode::DefinedOperatorASTNode(const DefinedOperatorASTNode & other)
+: ExprASTNode(other), m_constantName()
+{
+ m_constantName = new std::string(*other.m_constantName);
+}
+
+void DefinedOperatorASTNode::printTree(int indent) const
+{
+ ExprASTNode::printTree(indent);
+ printIndent(indent+1);
+
+ if (m_constantName)
+ {
+ printf("defined ( %s )\n", m_constantName->c_str());
+ }
+}
+
+ExprASTNode * DefinedOperatorASTNode::reduce(EvalContext & context)
+{
+ assert(m_constantName);
+
+ // Return function result as an expression node
+ return new IntConstExprASTNode(context.isVariableDefined(m_constantName) ? 1 : 0);
+}
+
+#pragma mark = SizeofOperatorASTNode =
+
+SizeofOperatorASTNode::SizeofOperatorASTNode(const SizeofOperatorASTNode & other)
+: ExprASTNode(other), m_constantName(), m_symbol()
+{
+ m_constantName = new std::string(*other.m_constantName);
+ m_symbol = dynamic_cast<SymbolASTNode*>(other.m_symbol->clone());
+}
+
+void SizeofOperatorASTNode::printTree(int indent) const
+{
+ ExprASTNode::printTree(indent);
+
+ printIndent(indent+1);
+
+ if (m_constantName)
+ {
+ printf("sizeof: %s\n", m_constantName->c_str());
+ }
+ else if (m_symbol)
+ {
+ printf("sizeof:\n");
+ m_symbol->printTree(indent + 2);
+ }
+}
+
+ExprASTNode * SizeofOperatorASTNode::reduce(EvalContext & context)
+{
+ // One or the other must be defined.
+ assert(m_constantName || m_symbol);
+
+ EvalContext::SourceFileManager * manager = context.getSourceFileManager();
+ assert(manager);
+
+ unsigned sizeInBytes = 0;
+ SourceFile * sourceFile;
+
+ if (m_symbol)
+ {
+ // Get the symbol name.
+ std::string * symbolName = m_symbol->getSymbolName();
+ assert(symbolName);
+
+ // Get the source file, using the default if one is not specified.
+ std::string * sourceName = m_symbol->getSource();
+ if (sourceName)
+ {
+ sourceFile = manager->getSourceFile(*sourceName);
+ if (!sourceFile)
+ {
+ throw semantic_error(format_string("line %d: invalid source file: %s", getFirstLine(), sourceName->c_str()));
+ }
+ }
+ else
+ {
+ sourceFile = manager->getDefaultSourceFile();
+ if (!sourceFile)
+ {
+ throw semantic_error(format_string("line %d: no default source file is set", getFirstLine()));
+ }
+ }
+
+ // Get the size of the symbol.
+ if (sourceFile->hasSymbol(*symbolName))
+ {
+ sizeInBytes = sourceFile->getSymbolSize(*symbolName);
+ }
+ }
+ else if (m_constantName)
+ {
+ // See if the "constant" is really a constant or if it's a source name.
+ if (manager->hasSourceFile(m_constantName))
+ {
+ sourceFile = manager->getSourceFile(m_constantName);
+ if (sourceFile)
+ {
+ sizeInBytes = sourceFile->getSize();
+ }
+ }
+ else
+ {
+ // Regular constant.
+ if (!context.isVariableDefined(*m_constantName))
+ {
+ throw semantic_error(format_string("line %d: cannot get size of undefined constant %s", getFirstLine(), m_constantName->c_str()));
+ }
+
+ int_size_t intSize = context.getVariableSize(*m_constantName);
+ switch (intSize)
+ {
+ case kWordSize:
+ sizeInBytes = sizeof(uint32_t);
+ break;
+ case kHalfWordSize:
+ sizeInBytes = sizeof(uint16_t);
+ break;
+ case kByteSize:
+ sizeInBytes = sizeof(uint8_t);
+ break;
+ }
+ }
+ }
+
+ // Return function result as an expression node
+ return new IntConstExprASTNode(sizeInBytes);
+}
+
+#pragma mark = BinaryOpExprASTNode =
+
+BinaryOpExprASTNode::BinaryOpExprASTNode(const BinaryOpExprASTNode & other)
+: ExprASTNode(other), m_left(), m_op(other.m_op), m_right()
+{
+ m_left = dynamic_cast<ExprASTNode*>(other.m_left->clone());
+ m_right = dynamic_cast<ExprASTNode*>(other.m_right->clone());
+}
+
+void BinaryOpExprASTNode::printTree(int indent) const
+{
+ ExprASTNode::printTree(indent);
+
+ printIndent(indent + 1);
+ printf("left:\n");
+ if (m_left) m_left->printTree(indent + 2);
+
+ printIndent(indent + 1);
+ printf("op: %s\n", getOperatorName().c_str());
+
+ printIndent(indent + 1);
+ printf("right:\n");
+ if (m_right) m_right->printTree(indent + 2);
+}
+
+std::string BinaryOpExprASTNode::getOperatorName() const
+{
+ switch (m_op)
+ {
+ case kAdd:
+ return "+";
+ case kSubtract:
+ return "-";
+ case kMultiply:
+ return "*";
+ case kDivide:
+ return "/";
+ case kModulus:
+ return "%";
+ case kPower:
+ return "**";
+ case kBitwiseAnd:
+ return "&";
+ case kBitwiseOr:
+ return "|";
+ case kBitwiseXor:
+ return "^";
+ case kShiftLeft:
+ return "<<";
+ case kShiftRight:
+ return ">>";
+ case kLessThan:
+ return "<";
+ case kGreaterThan:
+ return ">";
+ case kLessThanEqual:
+ return "<=";
+ case kGreaterThanEqual:
+ return ">";
+ case kEqual:
+ return "==";
+ case kNotEqual:
+ return "!=";
+ case kBooleanAnd:
+ return "&&";
+ case kBooleanOr:
+ return "||";
+ }
+
+ return "???";
+}
+
+//! \todo Fix power operator under windows!!!
+//!
+ExprASTNode * BinaryOpExprASTNode::reduce(EvalContext & context)
+{
+ if (!m_left || !m_right)
+ {
+ return this;
+ }
+
+ IntConstExprASTNode * leftIntConst = NULL;
+ IntConstExprASTNode * rightIntConst = NULL;
+ uint32_t leftValue;
+ uint32_t rightValue;
+ uint32_t result = 0;
+
+ // Always reduce the left hand side.
+ m_left = m_left->reduce(context);
+ leftIntConst = dynamic_cast<IntConstExprASTNode*>(m_left.get());
+ if (!leftIntConst)
+ {
+ throw semantic_error(format_string("left hand side of %s operator failed to evaluate to an integer", getOperatorName().c_str()));
+ }
+ leftValue = leftIntConst->getValue();
+
+ // Boolean && and || operators are handled separately so that we can perform
+ // short-circuit evaluation.
+ if (m_op == kBooleanAnd || m_op == kBooleanOr)
+ {
+ // Reduce right hand side only if required to evaluate the boolean operator.
+ if ((m_op == kBooleanAnd && leftValue != 0) || (m_op == kBooleanOr && leftValue == 0))
+ {
+ m_right = m_right->reduce(context);
+ rightIntConst = dynamic_cast<IntConstExprASTNode*>(m_right.get());
+ if (!rightIntConst)
+ {
+ throw semantic_error(format_string("right hand side of %s operator failed to evaluate to an integer", getOperatorName().c_str()));
+ }
+ rightValue = rightIntConst->getValue();
+
+ // Perform the boolean operation.
+ switch (m_op)
+ {
+ case kBooleanAnd:
+ result = leftValue && rightValue;
+ break;
+
+ case kBooleanOr:
+ result = leftValue && rightValue;
+ break;
+ }
+ }
+ else if (m_op == kBooleanAnd)
+ {
+ // The left hand side is false, so the && operator's result must be false
+ // without regard to the right hand side.
+ result = 0;
+ }
+ else if (m_op == kBooleanOr)
+ {
+ // The left hand value is true so the || result is automatically true.
+ result = 1;
+ }
+ }
+ else
+ {
+ // Reduce right hand side always for most operators.
+ m_right = m_right->reduce(context);
+ rightIntConst = dynamic_cast<IntConstExprASTNode*>(m_right.get());
+ if (!rightIntConst)
+ {
+ throw semantic_error(format_string("right hand side of %s operator failed to evaluate to an integer", getOperatorName().c_str()));
+ }
+ rightValue = rightIntConst->getValue();
+
+ switch (m_op)
+ {
+ case kAdd:
+ result = leftValue + rightValue;
+ break;
+ case kSubtract:
+ result = leftValue - rightValue;
+ break;
+ case kMultiply:
+ result = leftValue * rightValue;
+ break;
+ case kDivide:
+ result = leftValue / rightValue;
+ break;
+ case kModulus:
+ result = leftValue % rightValue;
+ break;
+ case kPower:
+ #ifdef WIN32
+ result = 0;
+ #else
+ result = lroundf(powf(float(leftValue), float(rightValue)));
+ #endif
+ break;
+ case kBitwiseAnd:
+ result = leftValue & rightValue;
+ break;
+ case kBitwiseOr:
+ result = leftValue | rightValue;
+ break;
+ case kBitwiseXor:
+ result = leftValue ^ rightValue;
+ break;
+ case kShiftLeft:
+ result = leftValue << rightValue;
+ break;
+ case kShiftRight:
+ result = leftValue >> rightValue;
+ break;
+ case kLessThan:
+ result = leftValue < rightValue;
+ break;
+ case kGreaterThan:
+ result = leftValue > rightValue;
+ break;
+ case kLessThanEqual:
+ result = leftValue <= rightValue;
+ break;
+ case kGreaterThanEqual:
+ result = leftValue >= rightValue;
+ break;
+ case kEqual:
+ result = leftValue == rightValue;
+ break;
+ case kNotEqual:
+ result = leftValue != rightValue;
+ break;
+ }
+ }
+
+ // Create the result value.
+ int_size_t resultSize;
+ if (leftIntConst && rightIntConst)
+ {
+ resultSize = resultIntSize(leftIntConst->getSize(), rightIntConst->getSize());
+ }
+ else if (leftIntConst)
+ {
+ resultSize = leftIntConst->getSize();
+ }
+ else
+ {
+ // This shouldn't really be possible, but just in case.
+ resultSize = kWordSize;
+ }
+ return new IntConstExprASTNode(result, resultSize);
+}
+
+#pragma mark = IntSizeExprASTNode =
+
+IntSizeExprASTNode::IntSizeExprASTNode(const IntSizeExprASTNode & other)
+: ExprASTNode(other), m_expr(), m_size(other.m_size)
+{
+ m_expr = dynamic_cast<ExprASTNode*>(other.m_expr->clone());
+}
+
+void IntSizeExprASTNode::printTree(int indent) const
+{
+ ExprASTNode::printTree(indent);
+
+ char sizeChar='?';
+ switch (m_size)
+ {
+ case kWordSize:
+ sizeChar = 'w';
+ break;
+ case kHalfWordSize:
+ sizeChar = 'h';
+ break;
+ case kByteSize:
+ sizeChar = 'b';
+ break;
+ }
+ printIndent(indent + 1);
+ printf("size: %c\n", sizeChar);
+
+ printIndent(indent + 1);
+ printf("expr:\n");
+ if (m_expr) m_expr->printTree(indent + 2);
+}
+
+ExprASTNode * IntSizeExprASTNode::reduce(EvalContext & context)
+{
+ if (!m_expr)
+ {
+ return this;
+ }
+
+ m_expr = m_expr->reduce(context);
+ IntConstExprASTNode * intConst = dynamic_cast<IntConstExprASTNode*>(m_expr.get());
+ if (!intConst)
+ {
+ return this;
+ }
+
+ return new IntConstExprASTNode(intConst->getValue(), m_size);
+}
+
+#pragma mark = ExprConstASTNode =
+
+ExprConstASTNode::ExprConstASTNode(const ExprConstASTNode & other)
+: ConstASTNode(other), m_expr()
+{
+ m_expr = dynamic_cast<ExprASTNode*>(other.m_expr->clone());
+}
+
+void ExprConstASTNode::printTree(int indent) const
+{
+ ConstASTNode::printTree(indent);
+ if (m_expr) m_expr->printTree(indent + 1);
+}
+
+#pragma mark = StringConstASTNode =
+
+StringConstASTNode::StringConstASTNode(const StringConstASTNode & other)
+: ConstASTNode(other), m_value()
+{
+ m_value = new std::string(other.m_value);
+}
+
+void StringConstASTNode::printTree(int indent) const
+{
+ printIndent(indent);
+ printf("%s(%s)\n", nodeName().c_str(), m_value->c_str());
+}
+
+#pragma mark = BlobConstASTNode =
+
+BlobConstASTNode::BlobConstASTNode(const BlobConstASTNode & other)
+: ConstASTNode(other), m_blob()
+{
+ m_blob = new Blob(*other.m_blob);
+}
+
+void BlobConstASTNode::printTree(int indent) const
+{
+ printIndent(indent);
+
+ const uint8_t * dataPtr = m_blob->getData();
+ unsigned dataLen = m_blob->getLength();
+ printf("%s(%p:%d)\n", nodeName().c_str(), dataPtr, dataLen);
+}
+
+#pragma mark = IVTConstASTNode =
+
+IVTConstASTNode::IVTConstASTNode(const IVTConstASTNode & other)
+: ConstASTNode(other), m_fields()
+{
+ m_fields = dynamic_cast<ListASTNode*>(other.m_fields->clone());
+}
+
+void IVTConstASTNode::printTree(int indent) const
+{
+ printIndent(indent);
+ printf("%s:\n", nodeName().c_str());
+ if (m_fields)
+ {
+ m_fields->printTree(indent + 1);
+ }
+}
+
+#pragma mark = AssignmentASTNode =
+
+AssignmentASTNode::AssignmentASTNode(const AssignmentASTNode & other)
+: ASTNode(other), m_ident(), m_value()
+{
+ m_ident = new std::string(*other.m_ident);
+ m_value = dynamic_cast<ConstASTNode*>(other.m_value->clone());
+}
+
+void AssignmentASTNode::printTree(int indent) const
+{
+ printIndent(indent);
+ printf("%s(%s)\n", nodeName().c_str(), m_ident->c_str());
+
+ if (m_value) m_value->printTree(indent + 1);
+}
+
+#pragma mark = SourceDefASTNode =
+
+SourceDefASTNode::SourceDefASTNode(const SourceDefASTNode & other)
+: ASTNode(other), m_name()
+{
+ m_name = new std::string(*other.m_name);
+}
+
+#pragma mark = PathSourceDefASTNode =
+
+PathSourceDefASTNode::PathSourceDefASTNode(const PathSourceDefASTNode & other)
+: SourceDefASTNode(other), m_path()
+{
+ m_path = new std::string(*other.m_path);
+}
+
+void PathSourceDefASTNode::printTree(int indent) const
+{
+ SourceDefASTNode::printTree(indent);
+
+ printIndent(indent+1);
+ printf("path: %s\n", m_path->c_str());
+
+ printIndent(indent+1);
+ printf("attributes:\n");
+ if (m_attributes)
+ {
+ m_attributes->printTree(indent+2);
+ }
+}
+
+#pragma mark = ExternSourceDefASTNode =
+
+ExternSourceDefASTNode::ExternSourceDefASTNode(const ExternSourceDefASTNode & other)
+: SourceDefASTNode(other), m_expr()
+{
+ m_expr = dynamic_cast<ExprASTNode*>(other.m_expr->clone());
+}
+
+void ExternSourceDefASTNode::printTree(int indent) const
+{
+ SourceDefASTNode::printTree(indent);
+
+ printIndent(indent+1);
+ printf("expr:\n");
+ if (m_expr) m_expr->printTree(indent + 2);
+
+ printIndent(indent+1);
+ printf("attributes:\n");
+ if (m_attributes)
+ {
+ m_attributes->printTree(indent+2);
+ }
+}
+
+#pragma mark = SectionContentsASTNode =
+
+SectionContentsASTNode::SectionContentsASTNode(const SectionContentsASTNode & other)
+: ASTNode(other), m_sectionExpr()
+{
+ m_sectionExpr = dynamic_cast<ExprASTNode*>(other.m_sectionExpr->clone());
+}
+
+void SectionContentsASTNode::printTree(int indent) const
+{
+ ASTNode::printTree(indent);
+
+ printIndent(indent + 1);
+ printf("section#:\n");
+ if (m_sectionExpr) m_sectionExpr->printTree(indent + 2);
+}
+
+#pragma mark = DataSectionContentsASTNode =
+
+DataSectionContentsASTNode::DataSectionContentsASTNode(const DataSectionContentsASTNode & other)
+: SectionContentsASTNode(other), m_contents()
+{
+ m_contents = dynamic_cast<ASTNode*>(other.m_contents->clone());
+}
+
+void DataSectionContentsASTNode::printTree(int indent) const
+{
+ SectionContentsASTNode::printTree(indent);
+
+ if (m_contents)
+ {
+ m_contents->printTree(indent + 1);
+ }
+}
+
+#pragma mark = BootableSectionContentsASTNode =
+
+BootableSectionContentsASTNode::BootableSectionContentsASTNode(const BootableSectionContentsASTNode & other)
+: SectionContentsASTNode(other), m_statements()
+{
+ m_statements = dynamic_cast<ListASTNode*>(other.m_statements->clone());
+}
+
+void BootableSectionContentsASTNode::printTree(int indent) const
+{
+ SectionContentsASTNode::printTree(indent);
+
+ printIndent(indent + 1);
+ printf("statements:\n");
+ if (m_statements) m_statements->printTree(indent + 2);
+}
+
+#pragma mark = IfStatementASTNode =
+
+//! \warning Be careful; this method could enter an infinite loop if m_nextIf feeds
+//! back onto itself. m_nextIf must be NULL at some point down the next if list.
+IfStatementASTNode::IfStatementASTNode(const IfStatementASTNode & other)
+: StatementASTNode(),
+ m_conditionExpr(),
+ m_ifStatements(),
+ m_nextIf(),
+ m_elseStatements()
+{
+ m_conditionExpr = dynamic_cast<ExprASTNode*>(other.m_conditionExpr->clone());
+ m_ifStatements = dynamic_cast<ListASTNode*>(other.m_ifStatements->clone());
+ m_nextIf = dynamic_cast<IfStatementASTNode*>(other.m_nextIf->clone());
+ m_elseStatements = dynamic_cast<ListASTNode*>(other.m_elseStatements->clone());
+}
+
+#pragma mark = ModeStatementASTNode =
+
+ModeStatementASTNode::ModeStatementASTNode(const ModeStatementASTNode & other)
+: StatementASTNode(other), m_modeExpr()
+{
+ m_modeExpr = dynamic_cast<ExprASTNode*>(other.m_modeExpr->clone());
+}
+
+void ModeStatementASTNode::printTree(int indent) const
+{
+ StatementASTNode::printTree(indent);
+ printIndent(indent + 1);
+ printf("mode:\n");
+ if (m_modeExpr) m_modeExpr->printTree(indent + 2);
+}
+
+#pragma mark = MessageStatementASTNode =
+
+MessageStatementASTNode::MessageStatementASTNode(const MessageStatementASTNode & other)
+: StatementASTNode(other), m_type(other.m_type), m_message()
+{
+ m_message = new std::string(*other.m_message);
+}
+
+void MessageStatementASTNode::printTree(int indent) const
+{
+ StatementASTNode::printTree(indent);
+ printIndent(indent + 1);
+ printf("%s: %s\n", getTypeName(), m_message->c_str());
+}
+
+const char * MessageStatementASTNode::getTypeName() const
+{
+ switch (m_type)
+ {
+ case kInfo:
+ return "info";
+
+ case kWarning:
+ return "warning";
+
+ case kError:
+ return "error";
+ }
+
+ return "unknown";
+}
+
+#pragma mark = LoadStatementASTNode =
+
+LoadStatementASTNode::LoadStatementASTNode(const LoadStatementASTNode & other)
+: StatementASTNode(other), m_data(), m_target(), m_isDCDLoad(other.m_isDCDLoad)
+{
+ m_data = other.m_data->clone();
+ m_target = other.m_target->clone();
+}
+
+void LoadStatementASTNode::printTree(int indent) const
+{
+ StatementASTNode::printTree(indent);
+
+ printIndent(indent + 1);
+ printf("data:\n");
+ if (m_data) m_data->printTree(indent + 2);
+
+ printIndent(indent + 1);
+ printf("target:\n");
+ if (m_target) m_target->printTree(indent + 2);
+}
+
+#pragma mark = CallStatementASTNode =
+
+CallStatementASTNode::CallStatementASTNode(const CallStatementASTNode & other)
+: StatementASTNode(other), m_type(other.m_type), m_target(), m_arg()
+{
+ m_target = other.m_target->clone();
+ m_arg = other.m_arg->clone();
+}
+
+void CallStatementASTNode::printTree(int indent) const
+{
+ printIndent(indent);
+ printf("%s(%s)%s\n", nodeName().c_str(), (m_type == kCallType ? "call" : "jump"), (m_isHAB ? "/HAB" : ""));
+
+ printIndent(indent + 1);
+ printf("target:\n");
+ if (m_target) m_target->printTree(indent + 2);
+
+ printIndent(indent + 1);
+ printf("arg:\n");
+ if (m_arg) m_arg->printTree(indent + 2);
+}
+
+#pragma mark = SourceASTNode =
+
+SourceASTNode::SourceASTNode(const SourceASTNode & other)
+: ASTNode(other), m_name()
+{
+ m_name = new std::string(*other.m_name);
+}
+
+void SourceASTNode::printTree(int indent) const
+{
+ printIndent(indent);
+ printf("%s(%s)\n", nodeName().c_str(), m_name->c_str());
+}
+
+#pragma mark = SectionMatchListASTNode =
+
+SectionMatchListASTNode::SectionMatchListASTNode(const SectionMatchListASTNode & other)
+: ASTNode(other), m_sections(), m_source()
+{
+ if (other.m_sections)
+ {
+ m_sections = dynamic_cast<ListASTNode *>(other.m_sections->clone());
+ }
+
+ if (other.m_source)
+ {
+ m_source = new std::string(*other.m_source);
+ }
+}
+
+void SectionMatchListASTNode::printTree(int indent) const
+{
+ ASTNode::printTree(indent);
+
+ printIndent(indent+1);
+ printf("sections:\n");
+ if (m_sections)
+ {
+ m_sections->printTree(indent+2);
+ }
+
+ printIndent(indent+1);
+ printf("source: ", m_source->c_str());
+ if (m_source)
+ {
+ printf("%s\n", m_source->c_str());
+ }
+ else
+ {
+ printf("\n");
+ }
+}
+
+#pragma mark = SectionASTNode =
+
+SectionASTNode::SectionASTNode(const SectionASTNode & other)
+: ASTNode(other), m_name(), m_source()
+{
+ m_action = other.m_action;
+
+ if (other.m_name)
+ {
+ m_name = new std::string(*other.m_name);
+ }
+
+ if (other.m_source)
+ {
+ m_source = new std::string(*other.m_source);
+ }
+}
+
+void SectionASTNode::printTree(int indent) const
+{
+ printIndent(indent);
+
+ const char * actionName;
+ switch (m_action)
+ {
+ case kInclude:
+ actionName = "include";
+ break;
+ case kExclude:
+ actionName = "exclude";
+ break;
+ }
+
+ if (m_source)
+ {
+ printf("%s(%s:%s:%s)\n", nodeName().c_str(), actionName, m_name->c_str(), m_source->c_str());
+ }
+ else
+ {
+ printf("%s(%s:%s)\n", nodeName().c_str(), actionName, m_name->c_str());
+ }
+}
+
+#pragma mark = SymbolASTNode =
+
+SymbolASTNode::SymbolASTNode(const SymbolASTNode & other)
+: ASTNode(other), m_symbol(), m_source()
+{
+ m_symbol = new std::string(*other.m_symbol);
+ m_source = new std::string(*other.m_source);
+}
+
+void SymbolASTNode::printTree(int indent) const
+{
+ printIndent(indent);
+
+ const char * symbol = NULL;
+ if (m_symbol)
+ {
+ symbol = m_symbol->c_str();
+ }
+
+ const char * source = NULL;
+ if (m_source)
+ {
+ source = m_source->c_str();
+ }
+
+ printf("%s(", nodeName().c_str());
+ if (source)
+ {
+ printf(source);
+ }
+ else
+ {
+ printf(".");
+ }
+ printf(":");
+ if (symbol)
+ {
+ printf(symbol);
+ }
+ else
+ {
+ printf(".");
+ }
+ printf(")\n");
+}
+
+#pragma mark = AddressRangeASTNode =
+
+AddressRangeASTNode::AddressRangeASTNode(const AddressRangeASTNode & other)
+: ASTNode(other), m_begin(), m_end()
+{
+ m_begin = other.m_begin->clone();
+ m_end = other.m_end->clone();
+}
+
+void AddressRangeASTNode::printTree(int indent) const
+{
+ ASTNode::printTree(indent);
+
+ printIndent(indent + 1);
+ printf("begin:\n");
+ if (m_begin) m_begin->printTree(indent + 2);
+
+ printIndent(indent + 1);
+ printf("end:\n");
+ if (m_end) m_end->printTree(indent + 2);
+}
+
+#pragma mark = FromStatementASTNode =
+
+FromStatementASTNode::FromStatementASTNode(std::string * source, ListASTNode * statements)
+: StatementASTNode(), m_source(source), m_statements(statements)
+{
+}
+
+FromStatementASTNode::FromStatementASTNode(const FromStatementASTNode & other)
+: StatementASTNode(), m_source(), m_statements()
+{
+ m_source = new std::string(*other.m_source);
+ m_statements = dynamic_cast<ListASTNode*>(other.m_statements->clone());
+}
+
+void FromStatementASTNode::printTree(int indent) const
+{
+ ASTNode::printTree(indent);
+
+ printIndent(indent + 1);
+ printf("source: ");
+ if (m_source) printf("%s\n", m_source->c_str());
+
+ printIndent(indent + 1);
+ printf("statements:\n");
+ if (m_statements) m_statements->printTree(indent + 2);
+}
+
--- /dev/null
+/*
+ * File: ElftosbAST.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_ElftosbAST_h_)
+#define _ElftosbAST_h_
+
+#include "stdafx.h"
+#include <string>
+#include <list>
+#include "smart_ptr.h"
+#include "EvalContext.h"
+
+namespace elftosb
+{
+
+// forward reference
+class SymbolASTNode;
+
+/*!
+ * \brief Token location in the source file.
+ */
+struct token_loc_t
+{
+ int m_firstLine; //!< Starting line of the token.
+ int m_lastLine; //!< Ending line of the token.
+};
+
+/*!
+ * \brief The base class for all AST node classes.
+ */
+class ASTNode
+{
+public:
+ //! \brief Default constructor.
+ ASTNode() : m_parent(0) {}
+
+ //! \brief Constructor taking a parent node.
+ ASTNode(ASTNode * parent) : m_parent(parent) {}
+
+ //! \brief Copy constructor.
+ ASTNode(const ASTNode & other) : m_parent(other.m_parent) {}
+
+ //! \brief Destructor.
+ virtual ~ASTNode() {}
+
+ //! \brief Returns an exact duplicate of this object.
+ virtual ASTNode * clone() const = 0;
+
+ //! \brief Returns the name of the object's class.
+ virtual std::string nodeName() const { return "ASTNode"; }
+
+ //! \name Parents
+ //@{
+ virtual ASTNode * getParent() const { return m_parent; }
+ virtual void setParent(ASTNode * newParent) { m_parent = newParent; }
+ //@}
+
+ //! \name Tree printing
+ //@{
+ virtual void printTree() const { printTree(0); }
+ virtual void printTree(int indent) const;
+ //@}
+
+ //! \name Location
+ //@{
+ virtual void setLocation(token_loc_t & loc) { m_location = loc; }
+ virtual void setLocation(token_loc_t & first, token_loc_t & last);
+ virtual void setLocation(ASTNode * loc) { setLocation(loc->getLocation()); }
+ virtual void setLocation(ASTNode * first, ASTNode * last);
+
+ virtual token_loc_t & getLocation() { return m_location; }
+ virtual const token_loc_t & getLocation() const { return m_location; }
+
+ virtual int getFirstLine() { return m_location.m_firstLine; }
+ virtual int getLastLine() { return m_location.m_lastLine; }
+ //@}
+
+protected:
+ ASTNode * m_parent; //!< Pointer to parent node of this object. May be NULL.
+ token_loc_t m_location; //!< Location of this node in the source file.
+
+ //! \brief Prints \a indent number of spaces.
+ void printIndent(int indent) const;
+};
+
+/*!
+ * \brief AST node that contains other AST nodes.
+ *
+ * Unlike other AST nodes, the location of a ListASTNode is computed dynamically
+ * based on the nodes in its list. Or mostly dynamic at least. The updateLocation()
+ * method is used to force the list object to recalculate its beginning and ending
+ * line numbers.
+ *
+ * \todo Figure out why it crashes in the destructor when the
+ * ast_list_t type is a list of smart_ptr<ASTNode>.
+ */
+class ListASTNode : public ASTNode
+{
+public:
+ typedef std::list< /*smart_ptr<ASTNode>*/ ASTNode * > ast_list_t;
+ typedef ast_list_t::iterator iterator;
+ typedef ast_list_t::const_iterator const_iterator;
+
+public:
+ ListASTNode() {}
+
+ ListASTNode(const ListASTNode & other);
+
+ virtual ~ListASTNode();
+
+ virtual ASTNode * clone() const { return new ListASTNode(*this); }
+
+ virtual std::string nodeName() const { return "ListASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ //! \name List operations
+ //@{
+ //! \brief Adds \a node to the end of the ordered list of child nodes.
+ virtual void appendNode(ASTNode * node);
+
+ //! \brief Returns the number of nodes in this list.
+ virtual unsigned nodeCount() const { return static_cast<unsigned>(m_list.size()); }
+ //@}
+
+ //! \name Node iterators
+ //@{
+ inline iterator begin() { return m_list.begin(); }
+ inline iterator end() { return m_list.end(); }
+
+ inline const_iterator begin() const { return m_list.begin(); }
+ inline const_iterator end() const { return m_list.end(); }
+ //@}
+
+ //! \name Location
+ //@{
+ virtual void updateLocation();
+ //@}
+
+protected:
+ ast_list_t m_list; //!< Ordered list of child nodes.
+};
+
+/*!
+ *
+ */
+class OptionsBlockASTNode : public ASTNode
+{
+public:
+ OptionsBlockASTNode(ListASTNode * options) : ASTNode(), m_options(options) {}
+
+ inline ListASTNode * getOptions() { return m_options; }
+
+ virtual ASTNode * clone() const { return NULL; }
+
+protected:
+ smart_ptr<ListASTNode> m_options;
+};
+
+/*!
+ *
+ */
+class ConstantsBlockASTNode : public ASTNode
+{
+public:
+ ConstantsBlockASTNode(ListASTNode * constants) : ASTNode(), m_constants(constants) {}
+
+ inline ListASTNode * getConstants() { return m_constants; }
+
+ virtual ASTNode * clone() const { return NULL; }
+
+protected:
+ smart_ptr<ListASTNode> m_constants;
+};
+
+/*!
+ *
+ */
+class SourcesBlockASTNode : public ASTNode
+{
+public:
+ SourcesBlockASTNode(ListASTNode * sources) : ASTNode(), m_sources(sources) {}
+
+ inline ListASTNode * getSources() { return m_sources; }
+
+ virtual ASTNode * clone() const { return NULL; }
+
+protected:
+ smart_ptr<ListASTNode> m_sources;
+};
+
+/*!
+ * \brief Root node for the entire file.
+ */
+class CommandFileASTNode : public ASTNode
+{
+public:
+ CommandFileASTNode();
+ CommandFileASTNode(const CommandFileASTNode & other);
+
+ virtual std::string nodeName() const { return "CommandFileASTNode"; }
+
+ virtual ASTNode * clone() const { return new CommandFileASTNode(*this); }
+
+ virtual void printTree(int indent) const;
+
+ inline void setBlocks(ListASTNode * blocks) { m_blocks = blocks; }
+ inline void setOptions(ListASTNode * options) { m_options = options; }
+ inline void setConstants(ListASTNode * constants) { m_constants = constants; }
+ inline void setSources(ListASTNode * sources) { m_sources = sources; }
+ inline void setSections(ListASTNode * sections) { m_sections = sections; }
+
+ inline ListASTNode * getBlocks() { return m_blocks; }
+ inline ListASTNode * getOptions() { return m_options; }
+ inline ListASTNode * getConstants() { return m_constants; }
+ inline ListASTNode * getSources() { return m_sources; }
+ inline ListASTNode * getSections() { return m_sections; }
+
+protected:
+ smart_ptr<ListASTNode> m_blocks;
+ smart_ptr<ListASTNode> m_options;
+ smart_ptr<ListASTNode> m_constants;
+ smart_ptr<ListASTNode> m_sources;
+ smart_ptr<ListASTNode> m_sections;
+};
+
+/*!
+ * \brief Abstract base class for all expression AST nodes.
+ */
+class ExprASTNode : public ASTNode
+{
+public:
+ ExprASTNode() : ASTNode() {}
+ ExprASTNode(const ExprASTNode & other) : ASTNode(other) {}
+
+ virtual std::string nodeName() const { return "ExprASTNode"; }
+
+ //! \brief Evaluate the expression and produce a result node to replace this one.
+ //!
+ //! The default implementation simply return this node unmodified. This
+ //! method is responsible for deleting any nodes that are no longer needed.
+ //! (?) how to delete this?
+ virtual ExprASTNode * reduce(EvalContext & context) { return this; }
+
+ int_size_t resultIntSize(int_size_t a, int_size_t b);
+};
+
+/*!
+ *
+ */
+class IntConstExprASTNode : public ExprASTNode
+{
+public:
+ IntConstExprASTNode(uint32_t value, int_size_t size=kWordSize)
+ : ExprASTNode(), m_value(value), m_size(size)
+ {
+ }
+
+ IntConstExprASTNode(const IntConstExprASTNode & other);
+
+ virtual std::string nodeName() const { return "IntConstExprASTNode"; }
+
+ virtual ASTNode * clone() const { return new IntConstExprASTNode(*this); }
+
+ virtual void printTree(int indent) const;
+
+ uint32_t getValue() const { return m_value; }
+ int_size_t getSize() const { return m_size; }
+
+protected:
+ uint32_t m_value;
+ int_size_t m_size;
+};
+
+/*!
+ *
+ */
+class VariableExprASTNode : public ExprASTNode
+{
+public:
+ VariableExprASTNode(std::string * name) : ExprASTNode(), m_variable(name) {}
+ VariableExprASTNode(const VariableExprASTNode & other);
+
+ inline std::string * getVariableName() { return m_variable; }
+
+ virtual ASTNode * clone() const { return new VariableExprASTNode(*this); }
+
+ virtual std::string nodeName() const { return "VariableExprASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ virtual ExprASTNode * reduce(EvalContext & context);
+
+protected:
+ smart_ptr<std::string> m_variable;
+};
+
+/*!
+ * \brief Expression node for a symbol reference.
+ *
+ * The symbol evaluates to its address.
+ */
+class SymbolRefExprASTNode : public ExprASTNode
+{
+public:
+ SymbolRefExprASTNode(SymbolASTNode * sym) : ExprASTNode(), m_symbol(sym) {}
+ SymbolRefExprASTNode(const SymbolRefExprASTNode & other);
+
+ virtual ASTNode * clone() const { return new SymbolRefExprASTNode(*this); }
+
+ virtual std::string nodeName() const { return "SymbolRefExprASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ virtual ExprASTNode * reduce(EvalContext & context);
+
+protected:
+ SymbolASTNode * m_symbol;
+};
+
+/*!
+ * \brief Negates an expression.
+ */
+class NegativeExprASTNode : public ExprASTNode
+{
+public:
+ NegativeExprASTNode(ExprASTNode * expr) : ExprASTNode(), m_expr(expr) {}
+ NegativeExprASTNode(const NegativeExprASTNode & other);
+
+ virtual ASTNode * clone() const { return new NegativeExprASTNode(*this); }
+
+ virtual std::string nodeName() const { return "NegativeExprASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ virtual ExprASTNode * reduce(EvalContext & context);
+
+ ExprASTNode * getExpr() { return m_expr; }
+
+protected:
+ smart_ptr<ExprASTNode> m_expr;
+};
+
+/*!
+ * \brief Performa a boolean inversion.
+ */
+class BooleanNotExprASTNode : public ExprASTNode
+{
+public:
+ BooleanNotExprASTNode(ExprASTNode * expr) : ExprASTNode(), m_expr(expr) {}
+ BooleanNotExprASTNode(const BooleanNotExprASTNode & other);
+
+ virtual ASTNode * clone() const { return new BooleanNotExprASTNode(*this); }
+
+ virtual std::string nodeName() const { return "BooleanNotExprASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ virtual ExprASTNode * reduce(EvalContext & context);
+
+ ExprASTNode * getExpr() { return m_expr; }
+
+protected:
+ smart_ptr<ExprASTNode> m_expr;
+};
+
+/*!
+ * \brief Calls a built-in function with a source as the parameter.
+ */
+class SourceFileFunctionASTNode : public ExprASTNode
+{
+public:
+ SourceFileFunctionASTNode(std::string * functionName, std::string * sourceFileName) : ExprASTNode(), m_functionName(functionName), m_sourceFile(sourceFileName) {}
+ SourceFileFunctionASTNode(const SourceFileFunctionASTNode & other);
+
+ virtual ASTNode * clone() const { return new SourceFileFunctionASTNode(*this); }
+
+ virtual std::string nodeName() const { return "SourceFileFunctionASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ virtual ExprASTNode * reduce(EvalContext & context);
+
+ std::string * getFunctionName() { return m_functionName; }
+ std::string * getSourceFile() { return m_sourceFile; }
+
+protected:
+ smart_ptr<std::string> m_functionName;
+ smart_ptr<std::string> m_sourceFile;
+};
+
+/*!
+ * \brief Returns true or false depending on whether a constant is defined.
+ */
+class DefinedOperatorASTNode : public ExprASTNode
+{
+public:
+ DefinedOperatorASTNode(std::string * constantName) : ExprASTNode(), m_constantName(constantName) {}
+ DefinedOperatorASTNode(const DefinedOperatorASTNode & other);
+
+ virtual ASTNode * clone() const { return new DefinedOperatorASTNode(*this); }
+
+ virtual std::string nodeName() const { return "DefinedOperatorASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ virtual ExprASTNode * reduce(EvalContext & context);
+
+ std::string * getConstantName() { return m_constantName; }
+
+protected:
+ smart_ptr<std::string> m_constantName; //!< Name of the constant.
+};
+
+class SymbolASTNode;
+
+/*!
+ * \brief Returns an integer that is the size in bytes of the operand.
+ */
+class SizeofOperatorASTNode : public ExprASTNode
+{
+public:
+ SizeofOperatorASTNode(std::string * constantName) : ExprASTNode(), m_constantName(constantName), m_symbol() {}
+ SizeofOperatorASTNode(SymbolASTNode * symbol) : ExprASTNode(), m_constantName(), m_symbol(symbol) {}
+ SizeofOperatorASTNode(const SizeofOperatorASTNode & other);
+
+ virtual ASTNode * clone() const { return new SizeofOperatorASTNode(*this); }
+
+ virtual std::string nodeName() const { return "SizeofOperatorASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ virtual ExprASTNode * reduce(EvalContext & context);
+
+ std::string * getConstantName() { return m_constantName; }
+ SymbolASTNode * getSymbol() { return m_symbol; }
+
+protected:
+ smart_ptr<std::string> m_constantName; //!< Name of the constant.
+ smart_ptr<SymbolASTNode> m_symbol; //!< Symbol reference. If this is non-NULL then the constant name is used instead.
+};
+
+/*!
+ *
+ */
+class BinaryOpExprASTNode : public ExprASTNode
+{
+public:
+ enum operator_t
+ {
+ kAdd,
+ kSubtract,
+ kMultiply,
+ kDivide,
+ kModulus,
+ kPower,
+ kBitwiseAnd,
+ kBitwiseOr,
+ kBitwiseXor,
+ kShiftLeft,
+ kShiftRight,
+ kLessThan,
+ kGreaterThan,
+ kLessThanEqual,
+ kGreaterThanEqual,
+ kEqual,
+ kNotEqual,
+ kBooleanAnd,
+ kBooleanOr
+ };
+
+ BinaryOpExprASTNode(ExprASTNode * left, operator_t op, ExprASTNode * right)
+ : ExprASTNode(), m_left(left), m_op(op), m_right(right)
+ {
+ }
+
+ BinaryOpExprASTNode(const BinaryOpExprASTNode & other);
+
+ virtual ASTNode * clone() const { return new BinaryOpExprASTNode(*this); }
+
+ virtual std::string nodeName() const { return "BinaryOpExprASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ virtual ExprASTNode * reduce(EvalContext & context);
+
+ ExprASTNode * getLeftExpr() { return m_left; }
+ ExprASTNode * getRightExpr() { return m_right; }
+ operator_t getOp() const { return m_op; }
+
+protected:
+ smart_ptr<ExprASTNode> m_left;
+ smart_ptr<ExprASTNode> m_right;
+ operator_t m_op;
+
+ std::string getOperatorName() const;
+};
+
+/*!
+ * \brief Negates an expression.
+ */
+class IntSizeExprASTNode : public ExprASTNode
+{
+public:
+ IntSizeExprASTNode(ExprASTNode * expr, int_size_t intSize) : ExprASTNode(), m_expr(expr), m_size(intSize) {}
+ IntSizeExprASTNode(const IntSizeExprASTNode & other);
+
+ virtual ASTNode * clone() const { return new IntSizeExprASTNode(*this); }
+
+ virtual std::string nodeName() const { return "IntSizeExprASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ virtual ExprASTNode * reduce(EvalContext & context);
+
+ ExprASTNode * getExpr() { return m_expr; }
+ int_size_t getIntSize() { return m_size; }
+
+protected:
+ smart_ptr<ExprASTNode> m_expr;
+ int_size_t m_size;
+};
+
+/*!
+ * Base class for const AST nodes.
+ */
+class ConstASTNode : public ASTNode
+{
+public:
+ ConstASTNode() : ASTNode() {}
+ ConstASTNode(const ConstASTNode & other) : ASTNode(other) {}
+
+protected:
+};
+
+/*!
+ *
+ */
+class ExprConstASTNode : public ConstASTNode
+{
+public:
+ ExprConstASTNode(ExprASTNode * expr) : ConstASTNode(), m_expr(expr) {}
+ ExprConstASTNode(const ExprConstASTNode & other);
+
+ virtual ASTNode * clone() const { return new ExprConstASTNode(*this); }
+
+ virtual std::string nodeName() const { return "ExprConstASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ ExprASTNode * getExpr() { return m_expr; }
+
+protected:
+ smart_ptr<ExprASTNode> m_expr;
+};
+
+/*!
+ *
+ */
+class StringConstASTNode : public ConstASTNode
+{
+public:
+ StringConstASTNode(std::string * value) : ConstASTNode(), m_value(value) {}
+ StringConstASTNode(const StringConstASTNode & other);
+
+ virtual ASTNode * clone() const { return new StringConstASTNode(*this); }
+
+ virtual std::string nodeName() const { return "StringConstASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ std::string * getString() { return m_value; }
+
+protected:
+ smart_ptr<std::string> m_value;
+};
+
+/*!
+ *
+ */
+class BlobConstASTNode : public ConstASTNode
+{
+public:
+ BlobConstASTNode(Blob * value) : ConstASTNode(), m_blob(value) {}
+ BlobConstASTNode(const BlobConstASTNode & other);
+
+ virtual ASTNode * clone() const { return new BlobConstASTNode(*this); }
+
+ virtual std::string nodeName() const { return "BlobConstASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ Blob * getBlob() { return m_blob; }
+
+protected:
+ smart_ptr<Blob> m_blob;
+};
+
+// Forward declaration.
+struct hab_ivt;
+
+/*!
+ * \brief Node for a constant IVT structure as used by HAB4.
+ */
+class IVTConstASTNode : public ConstASTNode
+{
+public:
+ IVTConstASTNode() : ConstASTNode(), m_fields() {}
+ IVTConstASTNode(const IVTConstASTNode & other);
+
+ virtual ASTNode * clone() const { return new IVTConstASTNode(*this); }
+
+ virtual std::string nodeName() const { return "IVTConstASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ void setFieldAssignments(ListASTNode * fields) { m_fields = fields; }
+ ListASTNode * getFieldAssignments() { return m_fields; }
+
+protected:
+ //! Fields of the IVT are set through assignment statements.
+ smart_ptr<ListASTNode> m_fields;
+};
+
+/*!
+ *
+ */
+class AssignmentASTNode : public ASTNode
+{
+public:
+ AssignmentASTNode(std::string * ident, ASTNode * value)
+ : ASTNode(), m_ident(ident), m_value(value)
+ {
+ }
+
+ AssignmentASTNode(const AssignmentASTNode & other);
+
+ virtual ASTNode * clone() const { return new AssignmentASTNode(*this); }
+
+ virtual std::string nodeName() const { return "AssignmentASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ inline std::string * getIdent() { return m_ident; }
+ inline ASTNode * getValue() { return m_value; }
+
+protected:
+ smart_ptr<std::string> m_ident;
+ smart_ptr<ASTNode> m_value;
+};
+
+/*!
+ * Base class for PathSourceDefASTNode and ExternSourceDefASTNode.
+ */
+class SourceDefASTNode : public ASTNode
+{
+public:
+ SourceDefASTNode(std::string * name) : m_name(name) {}
+ SourceDefASTNode(const SourceDefASTNode & other);
+
+ inline std::string * getName() { return m_name; }
+
+ inline void setAttributes(ListASTNode * attributes) { m_attributes = attributes; }
+ inline ListASTNode * getAttributes() { return m_attributes; }
+
+protected:
+ smart_ptr<std::string> m_name;
+ smart_ptr<ListASTNode> m_attributes;
+};
+
+/*!
+ *
+ */
+class PathSourceDefASTNode : public SourceDefASTNode
+{
+public:
+ PathSourceDefASTNode(std::string * name, std::string * path)
+ : SourceDefASTNode(name), m_path(path)
+ {
+ }
+
+ PathSourceDefASTNode(const PathSourceDefASTNode & other);
+
+ virtual PathSourceDefASTNode * clone() const { return new PathSourceDefASTNode(*this); }
+
+ virtual std::string nodeName() const { return "PathSourceDefASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ std::string * getPath() { return m_path; }
+
+protected:
+ smart_ptr<std::string> m_path;
+};
+
+/*!
+ *
+ */
+class ExternSourceDefASTNode : public SourceDefASTNode
+{
+public:
+ ExternSourceDefASTNode(std::string * name, ExprASTNode * expr)
+ : SourceDefASTNode(name), m_expr(expr)
+ {
+ }
+
+ ExternSourceDefASTNode(const ExternSourceDefASTNode & other);
+
+ virtual ASTNode * clone() const { return new ExternSourceDefASTNode(*this); }
+
+ virtual std::string nodeName() const { return "ExternSourceDefASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ ExprASTNode * getSourceNumberExpr() { return m_expr; }
+
+protected:
+ smart_ptr<ExprASTNode> m_expr;
+};
+
+/*!
+ *
+ */
+class SectionContentsASTNode : public ASTNode
+{
+public:
+ SectionContentsASTNode() : m_sectionExpr() {}
+ SectionContentsASTNode(ExprASTNode * section) : m_sectionExpr(section) {}
+ SectionContentsASTNode(const SectionContentsASTNode & other);
+
+ virtual ASTNode * clone() const { return new SectionContentsASTNode(*this); }
+
+ virtual std::string nodeName() const { return "SectionContentsASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ inline void setSectionNumberExpr(ExprASTNode * section)
+ {
+ m_sectionExpr = section;
+ }
+
+ inline ExprASTNode * getSectionNumberExpr()
+ {
+ return m_sectionExpr;
+ }
+
+ inline void setOptions(ListASTNode * options)
+ {
+ m_options = options;
+ }
+
+ inline ListASTNode * getOptions()
+ {
+ return m_options;
+ }
+
+protected:
+ smart_ptr<ExprASTNode> m_sectionExpr;
+ smart_ptr<ListASTNode> m_options;
+};
+
+/*!
+ * @brief Node representing a raw binary section definition.
+ */
+class DataSectionContentsASTNode : public SectionContentsASTNode
+{
+public:
+ DataSectionContentsASTNode(ASTNode * contents)
+ : SectionContentsASTNode(), m_contents(contents)
+ {
+ }
+
+ DataSectionContentsASTNode(const DataSectionContentsASTNode & other);
+
+ virtual ASTNode * clone() const { return new DataSectionContentsASTNode(*this); }
+
+ virtual std::string nodeName() const { return "DataSectionContentsASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ ASTNode * getContents() { return m_contents; }
+
+protected:
+ smart_ptr<ASTNode> m_contents;
+};
+
+/*!
+ *
+ */
+class BootableSectionContentsASTNode : public SectionContentsASTNode
+{
+public:
+ BootableSectionContentsASTNode(ListASTNode * statements)
+ : SectionContentsASTNode(), m_statements(statements)
+ {
+ }
+
+ BootableSectionContentsASTNode(const BootableSectionContentsASTNode & other);
+
+ virtual ASTNode * clone() const { return new BootableSectionContentsASTNode(*this); }
+
+ virtual std::string nodeName() const { return "BootableSectionContentsASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ ListASTNode * getStatements() { return m_statements; }
+
+protected:
+ smart_ptr<ListASTNode> m_statements;
+};
+
+/*!
+ *
+ */
+class StatementASTNode : public ASTNode
+{
+public:
+ StatementASTNode() : ASTNode() {}
+ StatementASTNode(const StatementASTNode & other) : ASTNode(other) {}
+
+protected:
+};
+
+/*!
+ *
+ */
+class IfStatementASTNode : public StatementASTNode
+{
+public:
+ IfStatementASTNode() : StatementASTNode(), m_ifStatements(), m_nextIf(), m_elseStatements() {}
+ IfStatementASTNode(const IfStatementASTNode & other);
+
+ virtual ASTNode * clone() const { return new IfStatementASTNode(*this); }
+
+ void setConditionExpr(ExprASTNode * expr) { m_conditionExpr = expr; }
+ ExprASTNode * getConditionExpr() { return m_conditionExpr; }
+
+ void setIfStatements(ListASTNode * statements) { m_ifStatements = statements; }
+ ListASTNode * getIfStatements() { return m_ifStatements; }
+
+ void setNextIf(IfStatementASTNode * nextIf) { m_nextIf = nextIf; }
+ IfStatementASTNode * getNextIf() { return m_nextIf; }
+
+ void setElseStatements(ListASTNode * statements) { m_elseStatements = statements; }
+ ListASTNode * getElseStatements() { return m_elseStatements; }
+
+protected:
+ smart_ptr<ExprASTNode> m_conditionExpr; //!< Boolean expression.
+ smart_ptr<ListASTNode> m_ifStatements; //!< List of "if" section statements.
+ smart_ptr<IfStatementASTNode> m_nextIf; //!< Link to next "else if". If this is non-NULL then #m_elseStatements must be NULL and vice-versa.
+ smart_ptr<ListASTNode> m_elseStatements; //!< Statements for the "else" part of the statements.
+};
+
+/*!
+ * \brief Statement to insert a ROM_MODE_CMD command.
+ */
+class ModeStatementASTNode : public StatementASTNode
+{
+public:
+ ModeStatementASTNode() : StatementASTNode(), m_modeExpr() {}
+ ModeStatementASTNode(ExprASTNode * modeExpr) : StatementASTNode(), m_modeExpr(modeExpr) {}
+ ModeStatementASTNode(const ModeStatementASTNode & other);
+
+ virtual ASTNode * clone() const { return new ModeStatementASTNode(*this); }
+
+ virtual std::string nodeName() const { return "ModeStatementASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ inline void setModeExpr(ExprASTNode * modeExpr) { m_modeExpr = modeExpr; }
+ inline ExprASTNode * getModeExpr() { return m_modeExpr; }
+
+protected:
+ smart_ptr<ExprASTNode> m_modeExpr; //!< Expression that evaluates to the new boot mode.
+};
+
+/*!
+ * \brief Statement to print a message to the elftosb user.
+ */
+class MessageStatementASTNode : public StatementASTNode
+{
+public:
+ enum _message_type
+ {
+ kInfo, //!< Prints an informational messag to the user.
+ kWarning, //!< Prints a warning to the user.
+ kError //!< Throws an error exception.
+ };
+
+ typedef enum _message_type message_type_t;
+
+public:
+ MessageStatementASTNode(message_type_t messageType, std::string * message) : StatementASTNode(), m_type(messageType), m_message(message) {}
+ MessageStatementASTNode(const MessageStatementASTNode & other);
+
+ virtual ASTNode * clone() const { return new MessageStatementASTNode(*this); }
+
+ virtual std::string nodeName() const { return "MessageStatementASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ inline message_type_t getType() { return m_type; }
+ inline std::string * getMessage() { return m_message; }
+
+ const char * getTypeName() const;
+
+protected:
+ message_type_t m_type;
+ smart_ptr<std::string> m_message; //!< Message to report.
+};
+
+/*!
+ * \brief AST node for a load statement.
+ */
+class LoadStatementASTNode : public StatementASTNode
+{
+public:
+ LoadStatementASTNode()
+ : StatementASTNode(), m_data(), m_target(), m_isDCDLoad(false)
+ {
+ }
+
+ LoadStatementASTNode(ASTNode * data, ASTNode * target)
+ : StatementASTNode(), m_data(data), m_target(), m_isDCDLoad(false)
+ {
+ }
+
+ LoadStatementASTNode(const LoadStatementASTNode & other);
+
+ virtual ASTNode * clone() const { return new LoadStatementASTNode(*this); }
+
+ virtual std::string nodeName() const { return "LoadStatementASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ inline void setData(ASTNode * data) { m_data = data; }
+ inline ASTNode * getData() { return m_data; }
+
+ inline void setTarget(ASTNode * target) { m_target = target; }
+ inline ASTNode * getTarget() { return m_target; }
+
+ inline void setDCDLoad(bool isDCD) { m_isDCDLoad = isDCD; }
+ inline bool isDCDLoad() const { return m_isDCDLoad; }
+
+protected:
+ smart_ptr<ASTNode> m_data;
+ smart_ptr<ASTNode> m_target;
+ bool m_isDCDLoad;
+};
+
+/*!
+ * \brief AST node for a call statement.
+ */
+class CallStatementASTNode : public StatementASTNode
+{
+public:
+ //! Possible sub-types of call statements.
+ typedef enum {
+ kCallType,
+ kJumpType
+ } call_type_t;
+
+public:
+ CallStatementASTNode(call_type_t callType=kCallType)
+ : StatementASTNode(), m_type(callType), m_target(), m_arg(), m_isHAB(false)
+ {
+ }
+
+ CallStatementASTNode(call_type_t callType, ASTNode * target, ASTNode * arg)
+ : StatementASTNode(), m_type(callType), m_target(target), m_arg(arg), m_isHAB(false)
+ {
+ }
+
+ CallStatementASTNode(const CallStatementASTNode & other);
+
+ virtual ASTNode * clone() const { return new CallStatementASTNode(*this); }
+
+ virtual std::string nodeName() const { return "CallStatementASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ inline void setCallType(call_type_t callType) { m_type = callType; }
+ inline call_type_t getCallType() { return m_type; }
+
+ inline void setTarget(ASTNode * target) { m_target = target; }
+ inline ASTNode * getTarget() { return m_target; }
+
+ inline void setArgument(ASTNode * arg) { m_arg = arg; }
+ inline ASTNode * getArgument() { return m_arg; }
+
+ inline void setIsHAB(bool isHAB) { m_isHAB = isHAB; }
+ inline bool isHAB() const { return m_isHAB; }
+
+protected:
+ call_type_t m_type;
+ smart_ptr<ASTNode> m_target; //!< This becomes the IVT address in HAB mode.
+ smart_ptr<ASTNode> m_arg;
+ bool m_isHAB;
+};
+
+/*!
+ *
+ */
+class SourceASTNode : public ASTNode
+{
+public:
+ SourceASTNode(std::string * name) : ASTNode(), m_name(name) {}
+ SourceASTNode(const SourceASTNode & other);
+
+ virtual ASTNode * clone() const { return new SourceASTNode(*this); }
+
+ virtual std::string nodeName() const { return "SourceASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ inline std::string * getSourceName() { return m_name; }
+
+protected:
+ smart_ptr<std::string> m_name;
+};
+
+/*!
+ * \brief List of section matches for a particular source name.
+ */
+class SectionMatchListASTNode : public ASTNode
+{
+public:
+ SectionMatchListASTNode(ListASTNode * sections)
+ : ASTNode(), m_sections(sections), m_source()
+ {
+ }
+
+ SectionMatchListASTNode(ListASTNode * sections, std::string * source)
+ : ASTNode(), m_sections(sections), m_source(source)
+ {
+ }
+
+ SectionMatchListASTNode(const SectionMatchListASTNode & other);
+
+ virtual ASTNode * clone() const { return new SectionMatchListASTNode(*this); }
+
+ virtual std::string nodeName() const { return "SectionMatchListASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ inline ListASTNode * getSections() { return m_sections; }
+ inline std::string * getSourceName() { return m_source; }
+
+protected:
+ smart_ptr<ListASTNode> m_sections;
+ smart_ptr<std::string> m_source;
+};
+
+/*!
+ * \brief AST node for a section glob.
+ *
+ * Can be assigned an include or exclude action for when this node is part of a
+ * SectionMatchListASTNode.
+ */
+class SectionASTNode : public ASTNode
+{
+public:
+ //! Possible actions for a section match list.
+ typedef enum
+ {
+ kInclude, //!< Include sections matched by this node.
+ kExclude //!< Exclude sections matched by this node.
+ } match_action_t;
+
+public:
+ SectionASTNode(std::string * name)
+ : ASTNode(), m_action(kInclude), m_name(name), m_source()
+ {
+ }
+
+ SectionASTNode(std::string * name, match_action_t action)
+ : ASTNode(), m_action(action), m_name(name), m_source()
+ {
+ }
+
+ SectionASTNode(std::string * name, std::string * source)
+ : ASTNode(), m_action(kInclude), m_name(name), m_source(source)
+ {
+ }
+
+ SectionASTNode(const SectionASTNode & other);
+
+ virtual ASTNode * clone() const { return new SectionASTNode(*this); }
+
+ virtual std::string nodeName() const { return "SectionASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ inline match_action_t getAction() { return m_action; }
+ inline std::string * getSectionName() { return m_name; }
+ inline std::string * getSourceName() { return m_source; }
+
+protected:
+ match_action_t m_action;
+ smart_ptr<std::string> m_name;
+ smart_ptr<std::string> m_source;
+};
+
+/*!
+ *
+ */
+class SymbolASTNode : public ASTNode
+{
+public:
+ SymbolASTNode()
+ : ASTNode(), m_symbol(), m_source()
+ {
+ }
+
+ SymbolASTNode(std::string * symbol, std::string * source=0)
+ : ASTNode(), m_symbol(symbol), m_source(source)
+ {
+ }
+
+ SymbolASTNode(const SymbolASTNode & other);
+
+ virtual ASTNode * clone() const { return new SymbolASTNode(*this); }
+
+ virtual std::string nodeName() const { return "SymbolASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ inline void setSymbolName(std::string * symbol) { m_symbol = symbol; }
+ inline std::string * getSymbolName() { return m_symbol; }
+
+ inline void setSource(std::string * source) { m_source = source; }
+ inline std::string * getSource() { return m_source; }
+
+protected:
+ smart_ptr<std::string> m_symbol; //!< Required.
+ smart_ptr<std::string> m_source; //!< Optional, may be NULL;
+};
+
+/*!
+ * If the end of the range is NULL, then only a single address was specified.
+ */
+class AddressRangeASTNode : public ASTNode
+{
+public:
+ AddressRangeASTNode()
+ : ASTNode(), m_begin(), m_end()
+ {
+ }
+
+ AddressRangeASTNode(ASTNode * begin, ASTNode * end)
+ : ASTNode(), m_begin(begin), m_end(end)
+ {
+ }
+
+ AddressRangeASTNode(const AddressRangeASTNode & other);
+
+ virtual ASTNode * clone() const { return new AddressRangeASTNode(*this); }
+
+ virtual std::string nodeName() const { return "AddressRangeASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ inline void setBegin(ASTNode * begin) { m_begin = begin; }
+ inline ASTNode * getBegin() { return m_begin; }
+
+ inline void setEnd(ASTNode * end) { m_end = end; }
+ inline ASTNode * getEnd() { return m_end; }
+
+protected:
+ smart_ptr<ASTNode> m_begin;
+ smart_ptr<ASTNode> m_end;
+};
+
+/*!
+ *
+ */
+class NaturalLocationASTNode : public ASTNode
+{
+public:
+ NaturalLocationASTNode()
+ : ASTNode()
+ {
+ }
+
+ NaturalLocationASTNode(const NaturalLocationASTNode & other)
+ : ASTNode(other)
+ {
+ }
+
+ virtual ASTNode * clone() const { return new NaturalLocationASTNode(*this); }
+
+ virtual std::string nodeName() const { return "NaturalLocationASTNode"; }
+};
+
+/*!
+ *
+ */
+class FromStatementASTNode : public StatementASTNode
+{
+public:
+ FromStatementASTNode() : StatementASTNode() {}
+ FromStatementASTNode(std::string * source, ListASTNode * statements);
+ FromStatementASTNode(const FromStatementASTNode & other);
+
+ virtual ASTNode * clone() const { return new FromStatementASTNode(*this); }
+
+ virtual std::string nodeName() const { return "FromStatementASTNode"; }
+
+ virtual void printTree(int indent) const;
+
+ inline void setSourceName(std::string * source) { m_source = source; }
+ inline std::string * getSourceName() { return m_source; }
+
+ inline void setStatements(ListASTNode * statements) { m_statements = statements; }
+ inline ListASTNode * getStatements() { return m_statements; }
+
+protected:
+ smart_ptr<std::string> m_source;
+ smart_ptr<ListASTNode> m_statements;
+};
+
+}; // namespace elftosb
+
+#endif // _ElftosbAST_h_
--- /dev/null
+/*
+ * File: ConversionController.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_ElftosbErrors_h_)
+#define _ElftosbErrors_h_
+
+#include <string>
+#include <stdexcept>
+
+namespace elftosb
+{
+
+/*!
+ * \brief A semantic error discovered while processing the command file AST.
+ */
+class semantic_error : public std::runtime_error
+{
+public:
+ explicit semantic_error(const std::string & msg)
+ : std::runtime_error(msg)
+ {}
+};
+
+}; // namespace elftosb
+
+#endif // _ElftosbErrors_h_
--- /dev/null
+/*
+ * File: ElftosbLexer.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#include "ElftosbLexer.h"
+#include <algorithm>
+#include "HexValues.h"
+
+using namespace elftosb;
+
+ElftosbLexer::ElftosbLexer(istream & inputStream)
+: yyFlexLexer(&inputStream), m_line(1), m_blob(0), m_blobFirstLine(0)
+{
+}
+
+void ElftosbLexer::getSymbolValue(YYSTYPE * value)
+{
+ if (!value)
+ {
+ return;
+ }
+ *value = m_symbolValue;
+}
+
+void ElftosbLexer::addSourceName(std::string * ident)
+{
+ m_sources.push_back(*ident);
+}
+
+bool ElftosbLexer::isSourceName(std::string * ident)
+{
+ string_vector_t::iterator it = find(m_sources.begin(), m_sources.end(), *ident);
+ return it != m_sources.end();
+}
+
+void ElftosbLexer::LexerError(const char * msg)
+{
+ throw elftosb::lexical_error(msg);
+}
+
+//! Reads the \a in string and writes to the \a out string. These strings can be the same
+//! string since the read head is always in front of the write head.
+//!
+//! \param[in] in Input string containing C-style escape sequences.
+//! \param[out] out Output string. All escape sequences in the input string have been converted
+//! to the actual characters. May point to the same string as \a in.
+//! \return The length of the resulting \a out string. This length is necessary because
+//! the string may have contained escape sequences that inserted null characters.
+int ElftosbLexer::processStringEscapes(const char * in, char * out)
+{
+ int count = 0;
+ while (*in)
+ {
+ switch (*in)
+ {
+ case '\\':
+ {
+ // start of an escape sequence
+ char c = *++in;
+ switch (c)
+ {
+ case 0: // end of the string, bail
+ break;
+ case 'x':
+ {
+ // start of a hex char escape sequence
+
+ // read high and low nibbles, checking for end of string
+ char hi = *++in;
+ if (hi == 0) break;
+ char lo = *++in;
+ if (lo == 0) break;
+
+ if (isHexDigit(hi) && isHexDigit(lo))
+ {
+ if (hi >= '0' && hi <= '9')
+ c = (hi - '0') << 4;
+ else if (hi >= 'A' && hi <= 'F')
+ c = (hi - 'A' + 10) << 4;
+ else if (hi >= 'a' && hi <= 'f')
+ c = (hi - 'a' + 10) << 4;
+
+ if (lo >= '0' && lo <= '9')
+ c |= lo - '0';
+ else if (lo >= 'A' && lo <= 'F')
+ c |= lo - 'A' + 10;
+ else if (lo >= 'a' && lo <= 'f')
+ c |= lo - 'a' + 10;
+
+ *out++ = c;
+ count++;
+ }
+ else
+ {
+ // not hex digits, the \x must have wanted an 'x' char
+ *out++ = 'x';
+ *out++ = hi;
+ *out++ = lo;
+ count += 3;
+ }
+ break;
+ }
+ case 'n':
+ *out++ = '\n';
+ count++;
+ break;
+ case 't':
+ *out++ = '\t';
+ count++;
+ break;
+ case 'r':
+ *out++ = '\r';
+ count++;
+ break;
+ case 'b':
+ *out++ = '\b';
+ count++;
+ break;
+ case 'f':
+ *out++ = '\f';
+ count++;
+ break;
+ case '0':
+ *out++ = '\0';
+ count++;
+ break;
+ default:
+ *out++ = c;
+ count++;
+ break;
+ }
+ break;
+ }
+
+ default:
+ // copy all other chars directly
+ *out++ = *in++;
+ count++;
+ }
+ }
+
+ // place terminating null char on output
+ *out = 0;
+ return count;
+}
+
+
--- /dev/null
+/*
+ * File: ElftosbLexer.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+// This header just wraps the standard flex C++ header to make it easier to include
+// without having to worry about redefinitions of the class name every time.
+
+#if !defined(_ElftosbLexer_h_)
+#define _ElftosbLexer_h_
+
+#include "ElftosbAST.h"
+#include "FlexLexer.h"
+#include "elftosb_parser.tab.hpp"
+#include <vector>
+#include <string>
+#include <stdexcept>
+#include "Blob.h"
+
+using namespace std;
+
+namespace elftosb
+{
+
+/*!
+ * \brief Exception class for syntax errors.
+ */
+class syntax_error : public std::runtime_error
+{
+public:
+ explicit syntax_error(const std::string & __arg) : std::runtime_error(__arg) {}
+};
+
+/*!
+ * \brief Exception class for lexical errors.
+ */
+class lexical_error : public std::runtime_error
+{
+public:
+ explicit lexical_error(const std::string & __arg) : std::runtime_error(__arg) {}
+};
+
+/*!
+ * \brief Lexical scanner class for elftosb command files.
+ *
+ * This class is a subclass of the standard C++ lexer class produced by
+ * Flex. It's primary purpose is to provide a clean way to report values
+ * for symbols, without using the yylval global. This is necessary because
+ * the parser produced by Bison is a "pure" parser.
+ *
+ * In addition, this class manages a list of source names generated by
+ * parsing. The lexer uses this list to determine if an identifier is
+ * a source name or a constant identifier.
+ */
+class ElftosbLexer : public yyFlexLexer
+{
+public:
+ //! \brief Constructor.
+ ElftosbLexer(istream & inputStream);
+
+ //! \brief Lexer interface. Returns one token.
+ virtual int yylex();
+
+ //! \brief Returns the value for the most recently produced token in \a value.
+ virtual void getSymbolValue(YYSTYPE * value);
+
+ //! \brief Returns the current token's location in \a loc.
+ inline token_loc_t & getLocation() { return m_location; }
+
+ //! \name Source names
+ //@{
+ void addSourceName(std::string * ident);
+ bool isSourceName(std::string * ident);
+ //@}
+
+protected:
+ YYSTYPE m_symbolValue; //!< Value for the current token.
+ int m_line; //!< Current line number.
+ token_loc_t m_location; //!< Location for the current token.
+ Blob * m_blob; //!< The binary object value as its being constructed.
+ int m_blobFirstLine; //!< Line number for the first character of a blob.
+
+ typedef std::vector<std::string> string_vector_t;
+ string_vector_t m_sources; //!< Vector of source identifiers;
+
+ //! \brief Throw an elftosb::lexical_error exception.
+ virtual void LexerError(const char * msg);
+
+ //! \brief Process a string containing escape sequences.
+ int processStringEscapes(const char * in, char * out);
+};
+
+}; // namespace elftosb
+
+#endif // _ElftosbLexer_h_
--- /dev/null
+/*
+ * File: EncoreBootImageGenerator.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "EncoreBootImageGenerator.h"
+#include "Logging.h"
+
+#define kFlagsOption "flags"
+#define kSectionFlagsOption "sectionFlags"
+#define kProductVersionOption "productVersion"
+#define kComponentVersionOption "componentVersion"
+#define kAlignmentOption "alignment"
+#define kCleartextOption "cleartext"
+
+using namespace elftosb;
+
+BootImage * EncoreBootImageGenerator::generate()
+{
+ EncoreBootImage * image = new EncoreBootImage();
+
+ // process each output section
+ section_vector_t::iterator it = m_sections.begin();
+ for (; it != m_sections.end(); ++it)
+ {
+ OutputSection * section = *it;
+
+ OperationSequenceSection * opSection = dynamic_cast<OperationSequenceSection*>(section);
+ if (opSection)
+ {
+ processOperationSection(opSection, image);
+ continue;
+ }
+
+ BinaryDataSection * dataSection = dynamic_cast<BinaryDataSection*>(section);
+ if (dataSection)
+ {
+ processDataSection(dataSection, image);
+ continue;
+ }
+
+ Log::log(Logger::WARNING, "warning: unexpected output section type\n");
+ }
+
+ // handle global options that affect the image
+ processOptions(image);
+
+ return image;
+}
+
+void EncoreBootImageGenerator::processOptions(EncoreBootImage * image)
+{
+ // bail if no option context was set
+ if (!m_options)
+ {
+ return;
+ }
+
+ if (m_options->hasOption(kFlagsOption))
+ {
+ const IntegerValue * intValue = dynamic_cast<const IntegerValue *>(m_options->getOption(kFlagsOption));
+ if (intValue)
+ {
+ image->setFlags(intValue->getValue());
+ }
+ else
+ {
+ Log::log(Logger::WARNING, "warning: flags option is an unexpected type\n");
+ }
+ }
+
+ // handle common options
+ processVersionOptions(image);
+ processDriveTagOption(image);
+}
+
+void EncoreBootImageGenerator::processSectionOptions(EncoreBootImage::Section * imageSection, OutputSection * modelSection)
+{
+ // Get options context for this output section.
+ const OptionContext * context = modelSection->getOptions();
+ if (!context)
+ {
+ return;
+ }
+
+ // Check for and handle "sectionFlags" option.
+ if (context->hasOption(kSectionFlagsOption))
+ {
+ const Value * value = context->getOption(kSectionFlagsOption);
+ const IntegerValue * intValue = dynamic_cast<const IntegerValue *>(value);
+ if (intValue)
+ {
+ // set explicit flags for this section
+ imageSection->setFlags(intValue->getValue());
+ }
+ else
+ {
+ Log::log(Logger::WARNING, "warning: sectionFlags option is an unexpected type\n");
+ }
+ }
+
+ // Check for and handle "alignment" option.
+ if (context->hasOption(kAlignmentOption))
+ {
+ const Value * value = context->getOption(kAlignmentOption);
+ const IntegerValue * intValue = dynamic_cast<const IntegerValue *>(value);
+ if (intValue)
+ {
+ // verify alignment value
+ if (intValue->getValue() < EncoreBootImage::BOOT_IMAGE_MINIMUM_SECTION_ALIGNMENT)
+ {
+ Log::log(Logger::WARNING, "warning: alignment option value must be 16 or greater\n");
+ }
+
+ imageSection->setAlignment(intValue->getValue());
+ }
+ else
+ {
+ Log::log(Logger::WARNING, "warning: alignment option is an unexpected type\n");
+ }
+ }
+
+ // Check for and handle "cleartext" option.
+ if (context->hasOption(kCleartextOption))
+ {
+ const Value * value = context->getOption(kCleartextOption);
+ const IntegerValue * intValue = dynamic_cast<const IntegerValue *>(value);
+ if (intValue)
+ {
+ bool leaveUnencrypted = intValue->getValue() != 0;
+ imageSection->setLeaveUnencrypted(leaveUnencrypted);
+ }
+ else
+ {
+ Log::log(Logger::WARNING, "warning: cleartext option is an unexpected type\n");
+ }
+ }
+}
+
+void EncoreBootImageGenerator::processOperationSection(OperationSequenceSection * section, EncoreBootImage * image)
+{
+ EncoreBootImage::BootSection * newSection = new EncoreBootImage::BootSection(section->getIdentifier());
+
+ OperationSequence & sequence = section->getSequence();
+ OperationSequence::iterator_t it = sequence.begin();
+ for (; it != sequence.end(); ++it)
+ {
+ Operation * op = *it;
+
+ LoadOperation * loadOp = dynamic_cast<LoadOperation*>(op);
+ if (loadOp)
+ {
+ processLoadOperation(loadOp, newSection);
+ continue;
+ }
+
+ ExecuteOperation * execOp = dynamic_cast<ExecuteOperation*>(op);
+ if (execOp)
+ {
+ processExecuteOperation(execOp, newSection);
+ continue;
+ }
+
+ BootModeOperation * modeOp = dynamic_cast<BootModeOperation*>(op);
+ if (modeOp)
+ {
+ processBootModeOperation(modeOp, newSection);
+ continue;
+ }
+
+ Log::log(Logger::WARNING, "warning: unexpected operation type\n");
+ }
+
+ // Deal with options that apply to sections.
+ processSectionOptions(newSection, section);
+
+ // add the boot section to the image
+ image->addSection(newSection);
+}
+
+void EncoreBootImageGenerator::processLoadOperation(LoadOperation * op, EncoreBootImage::BootSection * section)
+{
+ DataSource * source = op->getSource();
+ DataTarget * target = op->getTarget();
+
+ // other sources get handled the same way
+ unsigned segmentCount = source->getSegmentCount();
+ unsigned index = 0;
+ for (; index < segmentCount; ++index)
+ {
+ DataSource::Segment * segment = source->getSegmentAt(index);
+ DataTarget::AddressRange range = target->getRangeForSegment(*source, *segment);
+ unsigned rangeLength = range.m_end - range.m_begin;
+
+ // handle a pattern segment as a special case to create a fill command
+ DataSource::PatternSegment * patternSegment = dynamic_cast<DataSource::PatternSegment*>(segment);
+ if (patternSegment)
+ {
+ SizedIntegerValue & pattern = patternSegment->getPattern();
+
+ EncoreBootImage::FillCommand * command = new EncoreBootImage::FillCommand();
+ command->setAddress(range.m_begin);
+ command->setFillCount(rangeLength);
+ setFillPatternFromValue(*command, pattern);
+
+ section->addCommand(command);
+ continue;
+ }
+
+ // get the data from the segment
+ uint8_t * data = new uint8_t[rangeLength];
+ segment->getData(0, rangeLength, data);
+
+ // create the boot command
+ EncoreBootImage::LoadCommand * command = new EncoreBootImage::LoadCommand();
+ command->setData(data, rangeLength); // Makes a copy of the data buffer.
+ command->setLoadAddress(range.m_begin);
+ command->setDCD(op->isDCDLoad());
+
+ section->addCommand(command);
+
+ // Free the segment buffer.
+ delete [] data;
+ }
+}
+
+void EncoreBootImageGenerator::setFillPatternFromValue(EncoreBootImage::FillCommand & command, SizedIntegerValue & pattern)
+{
+ uint32_t u32PatternValue = pattern.getValue() & pattern.getWordSizeMask();
+ switch (pattern.getWordSize())
+ {
+ case kWordSize:
+ {
+ command.setPattern(u32PatternValue);
+ break;
+ }
+
+ case kHalfWordSize:
+ {
+ uint16_t u16PatternValue = static_cast<uint16_t>(u32PatternValue);
+ command.setPattern(u16PatternValue);
+ break;
+ }
+
+ case kByteSize:
+ {
+ uint8_t u8PatternValue = static_cast<uint8_t>(u32PatternValue);
+ command.setPattern(u8PatternValue);
+ }
+ }
+}
+
+void EncoreBootImageGenerator::processExecuteOperation(ExecuteOperation * op, EncoreBootImage::BootSection * section)
+{
+ DataTarget * target = op->getTarget();
+ uint32_t arg = static_cast<uint32_t>(op->getArgument());
+
+ EncoreBootImage::JumpCommand * command;
+ switch (op->getExecuteType())
+ {
+ case ExecuteOperation::kJump:
+ command = new EncoreBootImage::JumpCommand();
+ break;
+
+ case ExecuteOperation::kCall:
+ command = new EncoreBootImage::CallCommand();
+ break;
+ }
+
+ command->setAddress(target->getBeginAddress());
+ command->setArgument(arg);
+ command->setIsHAB(op->isHAB());
+
+ section->addCommand(command);
+}
+
+void EncoreBootImageGenerator::processBootModeOperation(BootModeOperation * op, EncoreBootImage::BootSection * section)
+{
+ EncoreBootImage::ModeCommand * command = new EncoreBootImage::ModeCommand();
+ command->setBootMode(op->getBootMode());
+
+ section->addCommand(command);
+}
+
+void EncoreBootImageGenerator::processDataSection(BinaryDataSection * section, EncoreBootImage * image)
+{
+ EncoreBootImage::DataSection * dataSection = new EncoreBootImage::DataSection(section->getIdentifier());
+ dataSection->setData(section->getData(), section->getLength());
+
+ // Handle alignment option.
+ processSectionOptions(dataSection, section);
+
+ image->addSection(dataSection);
+}
+
--- /dev/null
+/*
+ * File: EncoreBootImageGenerator.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_EncoreBootImageGenerator_h_)
+#define _EncoreBootImageGenerator_h_
+
+#include "BootImageGenerator.h"
+#include "EncoreBootImage.h"
+
+namespace elftosb
+{
+
+/*!
+ * \brief Generator for Encore boot images.
+ *
+ * Takes the abstract model of the output file and processes it into a
+ * concrete boot image for the STMP37xx.
+ *
+ * In order to enable full i.mx28 support, you must call the setSupportHAB() method and
+ * pass true.
+ */
+class EncoreBootImageGenerator : public BootImageGenerator
+{
+public:
+ //! \brief Default constructor.
+ EncoreBootImageGenerator() : BootImageGenerator() {}
+
+ //! \brief Builds the resulting boot image from previously added output sections.
+ virtual BootImage * generate();
+
+ //! \brief Enable or disable HAB support.
+ void setSupportHAB(bool supportHAB) { m_supportHAB = supportHAB; }
+
+protected:
+
+ bool m_supportHAB; //!< True if HAB features are enabled.
+
+ void processOptions(EncoreBootImage * image);
+ void processSectionOptions(EncoreBootImage::Section * imageSection, OutputSection * modelSection);
+
+ void processOperationSection(OperationSequenceSection * section, EncoreBootImage * image);
+ void processDataSection(BinaryDataSection * section, EncoreBootImage * image);
+
+ void processLoadOperation(LoadOperation * op, EncoreBootImage::BootSection * section);
+ void processExecuteOperation(ExecuteOperation * op, EncoreBootImage::BootSection * section);
+ void processBootModeOperation(BootModeOperation * op, EncoreBootImage::BootSection * section);
+
+ void setFillPatternFromValue(EncoreBootImage::FillCommand & command, SizedIntegerValue & pattern);
+};
+
+}; // namespace elftosb
+
+#endif // _EncoreBootImageGenerator_h_
+
--- /dev/null
+// -*-C++-*-
+// FlexLexer.h -- define interfaces for lexical analyzer classes generated
+// by flex
+
+// Copyright (c) 1993 The Regents of the University of California.
+// All rights reserved.
+//
+// This code is derived from software contributed to Berkeley by
+// Kent Williams and Tom Epperly.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+
+// Neither the name of the University nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+
+// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+
+// This file defines FlexLexer, an abstract class which specifies the
+// external interface provided to flex C++ lexer objects, and yyFlexLexer,
+// which defines a particular lexer class.
+//
+// If you want to create multiple lexer classes, you use the -P flag
+// to rename each yyFlexLexer to some other xxFlexLexer. You then
+// include <FlexLexer.h> in your other sources once per lexer class:
+//
+// #undef yyFlexLexer
+// #define yyFlexLexer xxFlexLexer
+// #include <FlexLexer.h>
+//
+// #undef yyFlexLexer
+// #define yyFlexLexer zzFlexLexer
+// #include <FlexLexer.h>
+// ...
+
+#ifndef __FLEX_LEXER_H
+// Never included before - need to define base class.
+#define __FLEX_LEXER_H
+
+#include <iostream>
+# ifndef FLEX_STD
+# define FLEX_STD std::
+# endif
+
+extern "C++" {
+
+struct yy_buffer_state;
+typedef int yy_state_type;
+
+class FlexLexer {
+public:
+ virtual ~FlexLexer() { }
+
+ const char* YYText() const { return yytext; }
+ int YYLeng() const { return yyleng; }
+
+ virtual void
+ yy_switch_to_buffer( struct yy_buffer_state* new_buffer ) = 0;
+ virtual struct yy_buffer_state*
+ yy_create_buffer( FLEX_STD istream* s, int size ) = 0;
+ virtual void yy_delete_buffer( struct yy_buffer_state* b ) = 0;
+ virtual void yyrestart( FLEX_STD istream* s ) = 0;
+
+ virtual int yylex() = 0;
+
+ // Call yylex with new input/output sources.
+ int yylex( FLEX_STD istream* new_in, FLEX_STD ostream* new_out = 0 )
+ {
+ switch_streams( new_in, new_out );
+ return yylex();
+ }
+
+ // Switch to new input/output streams. A nil stream pointer
+ // indicates "keep the current one".
+ virtual void switch_streams( FLEX_STD istream* new_in = 0,
+ FLEX_STD ostream* new_out = 0 ) = 0;
+
+ int lineno() const { return yylineno; }
+
+ int debug() const { return yy_flex_debug; }
+ void set_debug( int flag ) { yy_flex_debug = flag; }
+
+protected:
+ char* yytext;
+ int yyleng;
+ int yylineno; // only maintained if you use %option yylineno
+ int yy_flex_debug; // only has effect with -d or "%option debug"
+};
+
+}
+#endif // FLEXLEXER_H
+
+//#if defined(yyFlexLexer) || ! defined(yyFlexLexerOnce)
+// had to disable the 'defined(yyFlexLexer)' part because it was causing duplicate class defs
+#if ! defined(yyFlexLexerOnce)
+// Either this is the first time through (yyFlexLexerOnce not defined),
+// or this is a repeated include to define a different flavor of
+// yyFlexLexer, as discussed in the flex manual.
+#define yyFlexLexerOnce
+
+extern "C++" {
+
+class yyFlexLexer : public FlexLexer {
+public:
+ // arg_yyin and arg_yyout default to the cin and cout, but we
+ // only make that assignment when initializing in yylex().
+ yyFlexLexer( FLEX_STD istream* arg_yyin = 0, FLEX_STD ostream* arg_yyout = 0 );
+
+ virtual ~yyFlexLexer();
+
+ void yy_switch_to_buffer( struct yy_buffer_state* new_buffer );
+ struct yy_buffer_state* yy_create_buffer( FLEX_STD istream* s, int size );
+ void yy_delete_buffer( struct yy_buffer_state* b );
+ void yyrestart( FLEX_STD istream* s );
+
+ void yypush_buffer_state( struct yy_buffer_state* new_buffer );
+ void yypop_buffer_state();
+
+ virtual int yylex();
+ virtual void switch_streams( FLEX_STD istream* new_in, FLEX_STD ostream* new_out = 0 );
+ virtual int yywrap();
+
+protected:
+ virtual int LexerInput( char* buf, int max_size );
+ virtual void LexerOutput( const char* buf, int size );
+ virtual void LexerError( const char* msg );
+
+ void yyunput( int c, char* buf_ptr );
+ int yyinput();
+
+ void yy_load_buffer_state();
+ void yy_init_buffer( struct yy_buffer_state* b, FLEX_STD istream* s );
+ void yy_flush_buffer( struct yy_buffer_state* b );
+
+ int yy_start_stack_ptr;
+ int yy_start_stack_depth;
+ int* yy_start_stack;
+
+ void yy_push_state( int new_state );
+ void yy_pop_state();
+ int yy_top_state();
+
+ yy_state_type yy_get_previous_state();
+ yy_state_type yy_try_NUL_trans( yy_state_type current_state );
+ int yy_get_next_buffer();
+
+ FLEX_STD istream* yyin; // input source for default LexerInput
+ FLEX_STD ostream* yyout; // output sink for default LexerOutput
+
+ // yy_hold_char holds the character lost when yytext is formed.
+ char yy_hold_char;
+
+ // Number of characters read into yy_ch_buf.
+ int yy_n_chars;
+
+ // Points to current character in buffer.
+ char* yy_c_buf_p;
+
+ int yy_init; // whether we need to initialize
+ int yy_start; // start state number
+
+ // Flag which is used to allow yywrap()'s to do buffer switches
+ // instead of setting up a fresh yyin. A bit of a hack ...
+ int yy_did_buffer_switch_on_eof;
+
+
+ size_t yy_buffer_stack_top; /**< index of top of stack. */
+ size_t yy_buffer_stack_max; /**< capacity of stack. */
+ struct yy_buffer_state ** yy_buffer_stack; /**< Stack as an array. */
+ void yyensure_buffer_stack(void);
+
+ // The following are not always needed, but may be depending
+ // on use of certain flex features (like REJECT or yymore()).
+
+ yy_state_type yy_last_accepting_state;
+ char* yy_last_accepting_cpos;
+
+ yy_state_type* yy_state_buf;
+ yy_state_type* yy_state_ptr;
+
+ char* yy_full_match;
+ int* yy_full_state;
+ int yy_full_lp;
+
+ int yy_lp;
+ int yy_looking_for_trail_begin;
+
+ int yy_more_flag;
+ int yy_more_len;
+ int yy_more_offset;
+ int yy_prev_more_offset;
+};
+
+}
+
+#endif // yyFlexLexer || ! yyFlexLexerOnce
+
--- /dev/null
+/*
+ * File: elftosb.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "stdafx.h"
+#include <iostream>
+#include <fstream>
+#include <sstream>
+#include <stdlib.h>
+#include <stdexcept>
+#include "ConversionController.h"
+#include "options.h"
+#include "Version.h"
+#include "EncoreBootImage.h"
+#include "smart_ptr.h"
+#include "Logging.h"
+#include "EncoreBootImageGenerator.h"
+#include "SearchPath.h"
+#include "format_string.h"
+
+//! An array of strings.
+typedef std::vector<std::string> string_vector_t;
+
+//! The tool's name.
+const char k_toolName[] = "elftosb";
+
+//! Current version number for the tool.
+const char k_version[] = "2.6.1";
+
+//! Copyright string.
+const char k_copyright[] = "Copyright (c) 2004-2010 Freescale Semiconductor, Inc.\nAll rights reserved.";
+
+static const char * k_optionsDefinition[] = {
+ "?|help",
+ "v|version",
+ "f:chip-family <family>",
+ "c:command <file>",
+ "o:output <file>",
+ "P:product <version>",
+ "C:component <version>",
+ "k:key <file>",
+ "z|zero-key",
+ "D:define <const>",
+ "O:option <option>",
+ "d|debug",
+ "q|quiet",
+ "V|verbose",
+ "p:search-path <path>",
+ NULL
+};
+
+//! Help string.
+const char k_usageText[] = "\nOptions:\n\
+ -?/--help Show this help\n\
+ -v/--version Display tool version\n\
+ -f/--chip-family <family> Select the chip family (default is 37xx)\n\
+ -c/--command <file> Use this command file\n\
+ -o/--output <file> Write output to this file\n\
+ -p/--search-path <path> Add a search path used to find input files\n\
+ -P/--product <version Set product version\n\
+ -C/--component <version> Set component version\n\
+ -k/--key <file> Add OTP key, enable encryption\n\
+ -z/--zero-key Add default key of all zeroes\n\
+ -D/--define <const>=<int> Define or override a constant value\n\
+ -O/--option <name>=<value> Set or override a processing option\n\
+ -d/--debug Enable debug output\n\
+ -q/--quiet Output only warnings and errors\n\
+ -V/--verbose Print extra detailed log information\n\n";
+
+// prototypes
+int main(int argc, char* argv[], char* envp[]);
+
+/*!
+ * \brief Class that encapsulates the elftosb tool.
+ *
+ * A single global logger instance is created during object construction. It is
+ * never freed because we need it up to the last possible minute, when an
+ * exception could be thrown.
+ */
+class elftosbTool
+{
+protected:
+ //! Supported chip families.
+ enum chip_family_t
+ {
+ k37xxFamily, //!< 37xx series.
+ kMX28Family, //!< Catskills series.
+ };
+
+ /*!
+ * \brief A structure describing an entry in the table of chip family names.
+ */
+ struct FamilyNameTableEntry
+ {
+ const char * const name;
+ chip_family_t family;
+ };
+
+ //! \brief Table that maps from family name strings to chip family constants.
+ static const FamilyNameTableEntry kFamilyNameTable[];
+
+ int m_argc; //!< Number of command line arguments.
+ char ** m_argv; //!< String value for each command line argument.
+ StdoutLogger * m_logger; //!< Singleton logger instance.
+ string_vector_t m_keyFilePaths; //!< Paths to OTP key files.
+ string_vector_t m_positionalArgs; //!< Arguments coming after explicit options.
+ bool m_isVerbose; //!< Whether the verbose flag was turned on.
+ bool m_useDefaultKey; //!< Include a default (zero) crypto key.
+ const char * m_commandFilePath; //!< Path to the elftosb command file.
+ const char * m_outputFilePath; //!< Path to the output .sb file.
+ const char * m_searchPath; //!< Optional search path for input files.
+ elftosb::version_t m_productVersion; //!< Product version specified on command line.
+ elftosb::version_t m_componentVersion; //!< Component version specified on command line.
+ bool m_productVersionSpecified; //!< True if the product version was specified on the command line.
+ bool m_componentVersionSpecified; //!< True if the component version was specified on the command line.
+ chip_family_t m_family; //!< Chip family that the output file is formatted for.
+ elftosb::ConversionController m_controller; //!< Our conversion controller instance.
+
+public:
+ /*!
+ * Constructor.
+ *
+ * Creates the singleton logger instance.
+ */
+ elftosbTool(int argc, char * argv[])
+ : m_argc(argc),
+ m_argv(argv),
+ m_logger(0),
+ m_keyFilePaths(),
+ m_positionalArgs(),
+ m_isVerbose(false),
+ m_useDefaultKey(false),
+ m_commandFilePath(NULL),
+ m_outputFilePath(NULL),
+ m_searchPath(NULL),
+ m_productVersion(),
+ m_componentVersion(),
+ m_productVersionSpecified(false),
+ m_componentVersionSpecified(false),
+ m_family(k37xxFamily),
+ m_controller()
+ {
+ // create logger instance
+ m_logger = new StdoutLogger();
+ m_logger->setFilterLevel(Logger::INFO);
+ Log::setLogger(m_logger);
+ }
+
+ /*!
+ * Destructor.
+ */
+ ~elftosbTool()
+ {
+ }
+
+ /*!
+ * \brief Searches the family name table.
+ *
+ * \retval true The \a name was found in the table, and \a family is valid.
+ * \retval false No matching family name was found. The \a family argument is not modified.
+ */
+ bool lookupFamilyName(const char * name, chip_family_t * family)
+ {
+ // Create a local read-write copy of the argument string.
+ std::string familyName(name);
+
+ // Convert the argument string to lower case for case-insensitive comparison.
+ for (int n=0; n < familyName.length(); n++)
+ {
+ familyName[n] = tolower(familyName[n]);
+ }
+
+ // Exit the loop if we hit the NULL terminator entry.
+ const FamilyNameTableEntry * entry = &kFamilyNameTable[0];
+ for (; entry->name; entry++)
+ {
+ // Compare lowercased name with the table entry.
+ if (familyName == entry->name)
+ {
+ *family = entry->family;
+ return true;
+ }
+ }
+
+ // Failed to find a matching name.
+ return false;
+ }
+
+ /*!
+ * Reads the command line options passed into the constructor.
+ *
+ * This method can return a return code to its caller, which will cause the
+ * tool to exit immediately with that return code value. Normally, though, it
+ * will return -1 to signal that the tool should continue to execute and
+ * all options were processed successfully.
+ *
+ * The Options class is used to parse command line options. See
+ * #k_optionsDefinition for the list of options and #k_usageText for the
+ * descriptive help for each option.
+ *
+ * \retval -1 The options were processed successfully. Let the tool run normally.
+ * \return A zero or positive result is a return code value that should be
+ * returned from the tool as it exits immediately.
+ */
+ int processOptions()
+ {
+ Options options(*m_argv, k_optionsDefinition);
+ OptArgvIter iter(--m_argc, ++m_argv);
+
+ // process command line options
+ int optchar;
+ const char * optarg;
+ while (optchar = options(iter, optarg))
+ {
+ switch (optchar)
+ {
+ case '?':
+ printUsage(options);
+ return 0;
+
+ case 'v':
+ printf("%s %s\n%s\n", k_toolName, k_version, k_copyright);
+ return 0;
+
+ case 'f':
+ if (!lookupFamilyName(optarg, &m_family))
+ {
+ Log::log(Logger::ERROR, "error: unknown chip family '%s'\n", optarg);
+ printUsage(options);
+ return 0;
+ }
+ break;
+
+ case 'c':
+ m_commandFilePath = optarg;
+ break;
+
+ case 'o':
+ m_outputFilePath = optarg;
+ break;
+
+ case 'P':
+ m_productVersion.set(optarg);
+ m_productVersionSpecified = true;
+ break;
+
+ case 'C':
+ m_componentVersion.set(optarg);
+ m_componentVersionSpecified = true;
+ break;
+
+ case 'k':
+ m_keyFilePaths.push_back(optarg);
+ break;
+
+ case 'z':
+ m_useDefaultKey = true;
+ break;
+
+ case 'D':
+ overrideVariable(optarg);
+ break;
+
+ case 'O':
+ overrideOption(optarg);
+ break;
+
+ case 'd':
+ Log::getLogger()->setFilterLevel(Logger::DEBUG);
+ break;
+
+ case 'q':
+ Log::getLogger()->setFilterLevel(Logger::WARNING);
+ break;
+
+ case 'V':
+ m_isVerbose = true;
+ break;
+
+ case 'p':
+ {
+ std::string newSearchPath(optarg);
+ PathSearcher::getGlobalSearcher().addSearchPath(newSearchPath);
+ break;
+ }
+
+ default:
+ Log::log(Logger::ERROR, "error: unrecognized option\n\n");
+ printUsage(options);
+ return 0;
+ }
+ }
+
+ // handle positional args
+ if (iter.index() < m_argc)
+ {
+ Log::SetOutputLevel leveler(Logger::DEBUG);
+ Log::log("positional args:\n");
+ int i;
+ for (i = iter.index(); i < m_argc; ++i)
+ {
+ Log::log("%d: %s\n", i - iter.index(), m_argv[i]);
+ m_positionalArgs.push_back(m_argv[i]);
+ }
+ }
+
+ // all is well
+ return -1;
+ }
+
+ /*!
+ * Prints help for the tool.
+ */
+ void printUsage(Options & options)
+ {
+ options.usage(std::cout, "files...");
+ printf(k_usageText, k_toolName);
+ }
+
+ /*!
+ * \brief Core of the tool.
+ *
+ * Calls processOptions() to handle command line options before performing the
+ * real work the tool does.
+ */
+ int run()
+ {
+ try
+ {
+ // read command line options
+ int result;
+ if ((result = processOptions()) != -1)
+ {
+ return result;
+ }
+
+ // set verbose logging
+ setVerboseLogging();
+
+ // check argument values
+ checkArguments();
+
+ // set up the controller
+ m_controller.setCommandFilePath(m_commandFilePath);
+
+ // add external paths to controller
+ string_vector_t::iterator it = m_positionalArgs.begin();
+ for (; it != m_positionalArgs.end(); ++it)
+ {
+ m_controller.addExternalFilePath(*it);
+ }
+
+ // run conversion
+ convert();
+ }
+ catch (std::exception & e)
+ {
+ Log::log(Logger::ERROR, "error: %s\n", e.what());
+ return 1;
+ }
+ catch (...)
+ {
+ Log::log(Logger::ERROR, "error: unexpected exception\n");
+ return 1;
+ }
+
+ return 0;
+ }
+
+ /*!
+ * \brief Validate arguments that can be checked.
+ * \exception std::runtime_error Thrown if an argument value fails to pass validation.
+ */
+ void checkArguments()
+ {
+ if (m_commandFilePath == NULL)
+ {
+ throw std::runtime_error("no command file was specified");
+ }
+ if (m_outputFilePath == NULL)
+ {
+ throw std::runtime_error("no output file was specified");
+ }
+ }
+
+ /*!
+ * \brief Turns on verbose logging.
+ */
+ void setVerboseLogging()
+ {
+ if (m_isVerbose)
+ {
+ // verbose only affects the INFO and DEBUG filter levels
+ // if the user has selected quiet mode, it overrides verbose
+ switch (Log::getLogger()->getFilterLevel())
+ {
+ case Logger::INFO:
+ Log::getLogger()->setFilterLevel(Logger::INFO2);
+ break;
+ case Logger::DEBUG:
+ Log::getLogger()->setFilterLevel(Logger::DEBUG2);
+ break;
+ }
+ }
+ }
+
+ /*!
+ * \brief Returns the integer value for a string.
+ *
+ * Metric multiplier prefixes are supported.
+ */
+ uint32_t parseIntValue(const char * value)
+ {
+ // Accept 'true'/'yes' and 'false'/'no' as integer values.
+ if ((strcmp(value, "true") == 0) || (strcmp(value, "yes") == 0))
+ {
+ return 1;
+ }
+ else if ((strcmp(value, "false") == 0) || (strcmp(value, "no") == 0))
+ {
+ return 0;
+ }
+
+ uint32_t intValue = strtoul(value, NULL, 0);
+ unsigned multiplier;
+ switch (value[strlen(value) - 1])
+ {
+ case 'G':
+ multiplier = 1024 * 1024 * 1024;
+ break;
+ case 'M':
+ multiplier = 1024 * 1024;
+ break;
+ case 'K':
+ multiplier = 1024;
+ break;
+ default:
+ multiplier = 1;
+ }
+ intValue *= multiplier;
+ return intValue;
+ }
+
+ /*!
+ * \brief Parses the -D option to override a constant value.
+ */
+ void overrideVariable(const char * optarg)
+ {
+ // split optarg into two strings
+ std::string constName(optarg);
+ int i;
+ for (i=0; i < strlen(optarg); ++i)
+ {
+ if (optarg[i] == '=')
+ {
+ constName.resize(i++);
+ break;
+ }
+ }
+
+ uint32_t constValue = parseIntValue(&optarg[i]);
+
+ elftosb::EvalContext & context = m_controller.getEvalContext();
+ context.setVariable(constName, constValue);
+ context.lockVariable(constName);
+ }
+
+ /*!
+ * \brief
+ */
+ void overrideOption(const char * optarg)
+ {
+ // split optarg into two strings
+ std::string optionName(optarg);
+ int i;
+ for (i=0; i < strlen(optarg); ++i)
+ {
+ if (optarg[i] == '=')
+ {
+ optionName.resize(i++);
+ break;
+ }
+ }
+
+ // handle quotes for option value
+ const char * valuePtr = &optarg[i];
+ bool isString = false;
+ int len;
+ if (valuePtr[0] == '"')
+ {
+ // remember that the value is a string and get rid of the opening quote
+ isString = true;
+ valuePtr++;
+
+ // remove trailing quote if present
+ len = strlen(valuePtr);
+ if (valuePtr[len] == '"')
+ {
+ len--;
+ }
+ }
+
+ elftosb::Value * value;
+ if (isString)
+ {
+ std::string stringValue(valuePtr);
+ stringValue.resize(len); // remove trailing quote
+ value = new elftosb::StringValue(stringValue);
+ }
+ else
+ {
+ value = new elftosb::IntegerValue(parseIntValue(valuePtr));
+ }
+
+ // Set and lock the option in the controller
+ m_controller.setOption(optionName, value);
+ m_controller.lockOption(optionName);
+ }
+
+ /*!
+ * \brief Do the conversion.
+ * \exception std::runtime_error This exception is thrown if the conversion controller does
+ * not produce a boot image, or if the output file cannot be opened. Other errors
+ * internal to the conversion controller may also produce this exception.
+ */
+ void convert()
+ {
+ // create a generator for the chosen chip family
+ smart_ptr<elftosb::BootImageGenerator> generator;
+ switch (m_family)
+ {
+ case k37xxFamily:
+ generator = new elftosb::EncoreBootImageGenerator;
+ elftosb::g_enableHABSupport = false;
+ break;
+
+ case kMX28Family:
+ generator = new elftosb::EncoreBootImageGenerator;
+ elftosb::g_enableHABSupport = true;
+ break;
+ }
+
+ // process input and get a boot image
+ m_controller.run();
+ smart_ptr<elftosb::BootImage> image = m_controller.generateOutput(generator);
+ if (!image)
+ {
+ throw std::runtime_error("failed to produce output!");
+ }
+
+ // set version numbers if they were provided on the command line
+ if (m_productVersionSpecified)
+ {
+ image->setProductVersion(m_productVersion);
+ }
+ if (m_componentVersionSpecified)
+ {
+ image->setComponentVersion(m_componentVersion);
+ }
+
+ // special handling for each family
+ switch (m_family)
+ {
+ case k37xxFamily:
+ case kMX28Family:
+ {
+ // add OTP keys
+ elftosb::EncoreBootImage * encoreImage = dynamic_cast<elftosb::EncoreBootImage*>(image.get());
+ if (encoreImage)
+ {
+ // add keys
+ addCryptoKeys(encoreImage);
+
+ // print debug image
+ encoreImage->debugPrint();
+ }
+ break;
+ }
+ }
+
+ // write output
+ std::ofstream outputStream(m_outputFilePath, std::ios_base::binary | std::ios_base::out | std::ios_base::trunc);
+ if (outputStream.is_open())
+ {
+ image->writeToStream(outputStream);
+ }
+ else
+ {
+ throw std::runtime_error(format_string("could not open output file %s", m_outputFilePath));
+ }
+ }
+
+ /*!
+ * \brief
+ */
+ void addCryptoKeys(elftosb::EncoreBootImage * encoreImage)
+ {
+ string_vector_t::iterator it = m_keyFilePaths.begin();
+ for (; it != m_keyFilePaths.end(); ++it)
+ {
+ std::string & keyPath = *it;
+
+ std::string actualPath;
+ bool found = PathSearcher::getGlobalSearcher().search(keyPath, PathSearcher::kFindFile, true, actualPath);
+ if (!found)
+ {
+ throw std::runtime_error(format_string("unable to find key file %s\n", keyPath.c_str()));
+ }
+
+ std::ifstream keyStream(actualPath.c_str(), std::ios_base::in);
+ if (!keyStream.is_open())
+ {
+ throw std::runtime_error(format_string("unable to read key file %s\n", keyPath.c_str()));
+ }
+ keyStream.seekg(0);
+
+ try
+ {
+ // read as many keys as possible from the stream
+ while (true)
+ {
+ AESKey<128> key(keyStream);
+ encoreImage->addKey(key);
+
+ // dump key bytes
+ dumpKey(key);
+ }
+ }
+ catch (...)
+ {
+ // ignore the exception -- there are just no more keys in the stream
+ }
+ }
+
+ // add the default key of all zero bytes if requested
+ if (m_useDefaultKey)
+ {
+ AESKey<128> defaultKey;
+ encoreImage->addKey(defaultKey);
+ }
+ }
+
+ /*!
+ * \brief Write the value of each byte of the \a key to the log.
+ */
+ void dumpKey(const AESKey<128> & key)
+ {
+ // dump key bytes
+ Log::log(Logger::DEBUG, "key bytes: ");
+ AESKey<128>::key_t the_key;
+ key.getKey(&the_key);
+ int q;
+ for (q=0; q<16; q++)
+ {
+ Log::log(Logger::DEBUG, "%02x ", the_key[q]);
+ }
+ Log::log(Logger::DEBUG, "\n");
+ }
+
+};
+
+const elftosbTool::FamilyNameTableEntry elftosbTool::kFamilyNameTable[] =
+ {
+ { "37xx", k37xxFamily },
+ { "377x", k37xxFamily },
+ { "378x", k37xxFamily },
+ { "mx23", k37xxFamily },
+ { "imx23", k37xxFamily },
+ { "i.mx23", k37xxFamily },
+ { "mx28", kMX28Family },
+ { "imx28", kMX28Family },
+ { "i.mx28", kMX28Family },
+
+ // Null terminator entry.
+ { NULL, k37xxFamily }
+ };
+
+/*!
+ * Main application entry point. Creates an sbtool instance and lets it take over.
+ */
+int main(int argc, char* argv[], char* envp[])
+{
+ try
+ {
+ return elftosbTool(argc, argv).run();
+ }
+ catch (...)
+ {
+ Log::log(Logger::ERROR, "error: unexpected exception\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+
+
--- /dev/null
+<?xml version="1.0" encoding="Windows-1252"?>\r
+<VisualStudioProject\r
+ ProjectType="Visual C++"\r
+ Version="9.00"\r
+ Name="elftosb2"\r
+ ProjectGUID="{ACBF9A30-8865-4DAA-B686-D8DC823CBF5C}"\r
+ RootNamespace="elftosb2"\r
+ Keyword="Win32Proj"\r
+ TargetFrameworkVersion="131072"\r
+ >\r
+ <Platforms>\r
+ <Platform\r
+ Name="Win32"\r
+ />\r
+ </Platforms>\r
+ <ToolFiles>\r
+ </ToolFiles>\r
+ <Configurations>\r
+ <Configuration\r
+ Name="Debug|Win32"\r
+ OutputDirectory="Debug"\r
+ IntermediateDirectory="Debug"\r
+ ConfigurationType="1"\r
+ InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops"\r
+ CharacterSet="2"\r
+ >\r
+ <Tool\r
+ Name="VCPreBuildEventTool"\r
+ />\r
+ <Tool\r
+ Name="VCCustomBuildTool"\r
+ />\r
+ <Tool\r
+ Name="VCXMLDataGeneratorTool"\r
+ />\r
+ <Tool\r
+ Name="VCWebServiceProxyGeneratorTool"\r
+ />\r
+ <Tool\r
+ Name="VCMIDLTool"\r
+ />\r
+ <Tool\r
+ Name="VCCLCompilerTool"\r
+ Optimization="0"\r
+ AdditionalIncludeDirectories=".;..\winsupport;..\common"\r
+ PreprocessorDefinitions="WIN32;_DEBUG;_CONSOLE"\r
+ MinimalRebuild="true"\r
+ BasicRuntimeChecks="3"\r
+ RuntimeLibrary="1"\r
+ ForceConformanceInForLoopScope="true"\r
+ RuntimeTypeInfo="true"\r
+ UsePrecompiledHeader="0"\r
+ BrowseInformation="1"\r
+ WarningLevel="2"\r
+ Detect64BitPortabilityProblems="true"\r
+ DebugInformationFormat="4"\r
+ DisableSpecificWarnings="4355"\r
+ />\r
+ <Tool\r
+ Name="VCManagedResourceCompilerTool"\r
+ />\r
+ <Tool\r
+ Name="VCResourceCompilerTool"\r
+ />\r
+ <Tool\r
+ Name="VCPreLinkEventTool"\r
+ />\r
+ <Tool\r
+ Name="VCLinkerTool"\r
+ OutputFile="$(OutDir)/elftosb.exe"\r
+ LinkIncremental="2"\r
+ GenerateDebugInformation="true"\r
+ ProgramDatabaseFile="$(OutDir)/elftosb.pdb"\r
+ SubSystem="1"\r
+ RandomizedBaseAddress="1"\r
+ DataExecutionPrevention="0"\r
+ TargetMachine="1"\r
+ />\r
+ <Tool\r
+ Name="VCALinkTool"\r
+ />\r
+ <Tool\r
+ Name="VCManifestTool"\r
+ />\r
+ <Tool\r
+ Name="VCXDCMakeTool"\r
+ />\r
+ <Tool\r
+ Name="VCBscMakeTool"\r
+ />\r
+ <Tool\r
+ Name="VCFxCopTool"\r
+ />\r
+ <Tool\r
+ Name="VCAppVerifierTool"\r
+ />\r
+ <Tool\r
+ Name="VCPostBuildEventTool"\r
+ />\r
+ </Configuration>\r
+ <Configuration\r
+ Name="Release|Win32"\r
+ OutputDirectory="Release"\r
+ IntermediateDirectory="Release"\r
+ ConfigurationType="1"\r
+ InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops"\r
+ CharacterSet="2"\r
+ >\r
+ <Tool\r
+ Name="VCPreBuildEventTool"\r
+ />\r
+ <Tool\r
+ Name="VCCustomBuildTool"\r
+ />\r
+ <Tool\r
+ Name="VCXMLDataGeneratorTool"\r
+ />\r
+ <Tool\r
+ Name="VCWebServiceProxyGeneratorTool"\r
+ />\r
+ <Tool\r
+ Name="VCMIDLTool"\r
+ />\r
+ <Tool\r
+ Name="VCCLCompilerTool"\r
+ PreprocessorDefinitions="WIN32;NDEBUG;_CONSOLE"\r
+ RuntimeLibrary="0"\r
+ UsePrecompiledHeader="0"\r
+ WarningLevel="3"\r
+ Detect64BitPortabilityProblems="true"\r
+ DebugInformationFormat="3"\r
+ />\r
+ <Tool\r
+ Name="VCManagedResourceCompilerTool"\r
+ />\r
+ <Tool\r
+ Name="VCResourceCompilerTool"\r
+ />\r
+ <Tool\r
+ Name="VCPreLinkEventTool"\r
+ />\r
+ <Tool\r
+ Name="VCLinkerTool"\r
+ OutputFile="$(OutDir)/elftosb2.exe"\r
+ LinkIncremental="1"\r
+ GenerateDebugInformation="true"\r
+ SubSystem="1"\r
+ OptimizeReferences="2"\r
+ EnableCOMDATFolding="2"\r
+ RandomizedBaseAddress="1"\r
+ DataExecutionPrevention="0"\r
+ TargetMachine="1"\r
+ />\r
+ <Tool\r
+ Name="VCALinkTool"\r
+ />\r
+ <Tool\r
+ Name="VCManifestTool"\r
+ />\r
+ <Tool\r
+ Name="VCXDCMakeTool"\r
+ />\r
+ <Tool\r
+ Name="VCBscMakeTool"\r
+ />\r
+ <Tool\r
+ Name="VCFxCopTool"\r
+ />\r
+ <Tool\r
+ Name="VCAppVerifierTool"\r
+ />\r
+ <Tool\r
+ Name="VCPostBuildEventTool"\r
+ />\r
+ </Configuration>\r
+ </Configurations>\r
+ <References>\r
+ </References>\r
+ <Files>\r
+ <Filter\r
+ Name="Source Files"\r
+ Filter="cpp;c;cxx;def;odl;idl;hpj;bat;asm;asmx"\r
+ UniqueIdentifier="{4FC737F1-C7A5-4376-A066-2A32D752A2FF}"\r
+ >\r
+ <Filter\r
+ Name="common"\r
+ >\r
+ <File\r
+ RelativePath="..\common\AESKey.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Blob.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\crc.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\DataSource.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\DataSourceImager.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\DataTarget.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\ELFSourceFile.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\EncoreBootImage.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\EvalContext.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\ExcludesListMatcher.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\format_string.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\GHSSecInfo.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\GlobMatcher.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\HexValues.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\IVTDataSource.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Logging.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Operation.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\OptionDictionary.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\options.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\OutputSection.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Random.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\rijndael.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\RijndaelCBCMAC.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SearchPath.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SHA1.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SourceFile.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SRecordSourceFile.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\stdafx.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StELFFile.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StExecutableImage.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StSRecordFile.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Value.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Version.cpp"\r
+ >\r
+ </File>\r
+ </Filter>\r
+ <Filter\r
+ Name="elftosb"\r
+ >\r
+ <File\r
+ RelativePath=".\BootImageGenerator.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\ConversionController.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\elftosb.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\elftosb_lexer.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\elftosb_parser.tab.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\ElftosbAST.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\ElftosbLexer.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\EncoreBootImageGenerator.cpp"\r
+ >\r
+ </File>\r
+ </Filter>\r
+ </Filter>\r
+ <Filter\r
+ Name="Header Files"\r
+ Filter="h;hpp;hxx;hm;inl;inc;xsd"\r
+ UniqueIdentifier="{93995380-89BD-4b04-88EB-625FBE52EBFB}"\r
+ >\r
+ <Filter\r
+ Name="common"\r
+ >\r
+ <File\r
+ RelativePath="..\common\AESKey.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Blob.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\BootImage.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\crc.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\DataSource.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\DataSourceImager.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\DataTarget.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\ELF.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\ELFSourceFile.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\EncoreBootImage.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\EndianUtilities.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\EvalContext.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\ExcludesListMatcher.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\format_string.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\GHSSecInfo.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\GlobMatcher.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\HexValues.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\int_size.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\IVTDataSource.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Logging.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Operation.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\OptionContext.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\OptionDictionary.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\options.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\OutputSection.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Random.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\rijndael.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\RijndaelCBCMAC.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SearchPath.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SHA1.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\smart_ptr.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SourceFile.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SRecordSourceFile.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\stdafx.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StELFFile.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StExecutableImage.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StringMatcher.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StSRecordFile.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Value.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Version.h"\r
+ >\r
+ </File>\r
+ </Filter>\r
+ <Filter\r
+ Name="elftosb"\r
+ >\r
+ <File\r
+ RelativePath=".\BootImageGenerator.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\ConversionController.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\crypto.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\default_rom_key.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\elftosb.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\elftosb_parser.tab.hpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\ElftosbAST.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\ElftosbErrors.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\ElftosbLexer.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\EncoreBootImageGenerator.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\FlexLexer.h"\r
+ >\r
+ </File>\r
+ </Filter>\r
+ </Filter>\r
+ <Filter\r
+ Name="Resource Files"\r
+ Filter="rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx"\r
+ UniqueIdentifier="{67DA6AB6-F800-4c08-8B7A-83BB121AAD01}"\r
+ >\r
+ </Filter>\r
+ </Files>\r
+ <Globals>\r
+ </Globals>\r
+</VisualStudioProject>\r
--- /dev/null
+#line 2 "/Users/creed/projects/fsl/fromsvr/elftosb/build/elftosb.build/Debug/elftosb.build/DerivedSources/elftosb_lexer.cpp"
+
+#line 4 "/Users/creed/projects/fsl/fromsvr/elftosb/build/elftosb.build/Debug/elftosb.build/DerivedSources/elftosb_lexer.cpp"
+
+#define YY_INT_ALIGNED short int
+
+/* A lexical scanner generated by flex */
+
+#define FLEX_SCANNER
+#define YY_FLEX_MAJOR_VERSION 2
+#define YY_FLEX_MINOR_VERSION 5
+#define YY_FLEX_SUBMINOR_VERSION 35
+#if YY_FLEX_SUBMINOR_VERSION > 0
+#define FLEX_BETA
+#endif
+
+ /* The c++ scanner is a mess. The FlexLexer.h header file relies on the
+ * following macro. This is required in order to pass the c++-multiple-scanners
+ * test in the regression suite. We get reports that it breaks inheritance.
+ * We will address this in a future release of flex, or omit the C++ scanner
+ * altogether.
+ */
+ #define yyFlexLexer yyFlexLexer
+
+/* First, we deal with platform-specific or compiler-specific issues. */
+
+/* begin standard C headers. */
+
+/* end standard C headers. */
+
+/* flex integer type definitions */
+
+#ifndef FLEXINT_H
+#define FLEXINT_H
+
+/* C99 systems have <inttypes.h>. Non-C99 systems may or may not. */
+
+#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
+
+/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h,
+ * if you want the limit (max/min) macros for int types.
+ */
+#ifndef __STDC_LIMIT_MACROS
+#define __STDC_LIMIT_MACROS 1
+#endif
+
+#include <inttypes.h>
+typedef int8_t flex_int8_t;
+typedef uint8_t flex_uint8_t;
+typedef int16_t flex_int16_t;
+typedef uint16_t flex_uint16_t;
+typedef int32_t flex_int32_t;
+typedef uint32_t flex_uint32_t;
+#else
+typedef signed char flex_int8_t;
+typedef short int flex_int16_t;
+typedef int flex_int32_t;
+typedef unsigned char flex_uint8_t;
+typedef unsigned short int flex_uint16_t;
+typedef unsigned int flex_uint32_t;
+#endif /* ! C99 */
+
+/* Limits of integral types. */
+#ifndef INT8_MIN
+#define INT8_MIN (-128)
+#endif
+#ifndef INT16_MIN
+#define INT16_MIN (-32767-1)
+#endif
+#ifndef INT32_MIN
+#define INT32_MIN (-2147483647-1)
+#endif
+#ifndef INT8_MAX
+#define INT8_MAX (127)
+#endif
+#ifndef INT16_MAX
+#define INT16_MAX (32767)
+#endif
+#ifndef INT32_MAX
+#define INT32_MAX (2147483647)
+#endif
+#ifndef UINT8_MAX
+#define UINT8_MAX (255U)
+#endif
+#ifndef UINT16_MAX
+#define UINT16_MAX (65535U)
+#endif
+#ifndef UINT32_MAX
+#define UINT32_MAX (4294967295U)
+#endif
+
+#endif /* ! FLEXINT_H */
+
+/* begin standard C++ headers. */
+#include <iostream>
+#include <errno.h>
+#include <cstdlib>
+#include <cstring>
+/* end standard C++ headers. */
+
+#ifdef __cplusplus
+
+/* The "const" storage-class-modifier is valid. */
+#define YY_USE_CONST
+
+#else /* ! __cplusplus */
+
+/* C99 requires __STDC__ to be defined as 1. */
+#if defined (__STDC__)
+
+#define YY_USE_CONST
+
+#endif /* defined (__STDC__) */
+#endif /* ! __cplusplus */
+
+#ifdef YY_USE_CONST
+#define yyconst const
+#else
+#define yyconst
+#endif
+
+/* Returned upon end-of-file. */
+#define YY_NULL 0
+
+/* Promotes a possibly negative, possibly signed char to an unsigned
+ * integer for use as an array index. If the signed char is negative,
+ * we want to instead treat it as an 8-bit unsigned char, hence the
+ * double cast.
+ */
+#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c)
+
+/* Enter a start condition. This macro really ought to take a parameter,
+ * but we do it the disgusting crufty way forced on us by the ()-less
+ * definition of BEGIN.
+ */
+#define BEGIN (yy_start) = 1 + 2 *
+
+/* Translate the current start state into a value that can be later handed
+ * to BEGIN to return to the state. The YYSTATE alias is for lex
+ * compatibility.
+ */
+#define YY_START (((yy_start) - 1) / 2)
+#define YYSTATE YY_START
+
+/* Action number for EOF rule of a given start state. */
+#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)
+
+/* Special action meaning "start processing a new file". */
+#define YY_NEW_FILE yyrestart( yyin )
+
+#define YY_END_OF_BUFFER_CHAR 0
+
+/* Size of default input buffer. */
+#ifndef YY_BUF_SIZE
+#define YY_BUF_SIZE 16384
+#endif
+
+/* The state buf must be large enough to hold one state per character in the main buffer.
+ */
+#define YY_STATE_BUF_SIZE ((YY_BUF_SIZE + 2) * sizeof(yy_state_type))
+
+#ifndef YY_TYPEDEF_YY_BUFFER_STATE
+#define YY_TYPEDEF_YY_BUFFER_STATE
+typedef struct yy_buffer_state *YY_BUFFER_STATE;
+#endif
+
+#ifndef YY_TYPEDEF_YY_SIZE_T
+#define YY_TYPEDEF_YY_SIZE_T
+typedef size_t yy_size_t;
+#endif
+
+extern yy_size_t yyleng;
+
+#define EOB_ACT_CONTINUE_SCAN 0
+#define EOB_ACT_END_OF_FILE 1
+#define EOB_ACT_LAST_MATCH 2
+
+ /* Note: We specifically omit the test for yy_rule_can_match_eol because it requires
+ * access to the local variable yy_act. Since yyless() is a macro, it would break
+ * existing scanners that call yyless() from OUTSIDE yylex.
+ * One obvious solution it to make yy_act a global. I tried that, and saw
+ * a 5% performance hit in a non-yylineno scanner, because yy_act is
+ * normally declared as a register variable-- so it is not worth it.
+ */
+ #define YY_LESS_LINENO(n) \
+ do { \
+ int yyl;\
+ for ( yyl = n; yyl < yyleng; ++yyl )\
+ if ( yytext[yyl] == '\n' )\
+ --yylineno;\
+ }while(0)
+
+/* Return all but the first "n" matched characters back to the input stream. */
+#define yyless(n) \
+ do \
+ { \
+ /* Undo effects of setting up yytext. */ \
+ int yyless_macro_arg = (n); \
+ YY_LESS_LINENO(yyless_macro_arg);\
+ *yy_cp = (yy_hold_char); \
+ YY_RESTORE_YY_MORE_OFFSET \
+ (yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \
+ YY_DO_BEFORE_ACTION; /* set up yytext again */ \
+ } \
+ while ( 0 )
+
+#define unput(c) yyunput( c, (yytext_ptr) )
+
+#ifndef YY_STRUCT_YY_BUFFER_STATE
+#define YY_STRUCT_YY_BUFFER_STATE
+struct yy_buffer_state
+ {
+
+ std::istream* yy_input_file;
+
+ char *yy_ch_buf; /* input buffer */
+ char *yy_buf_pos; /* current position in input buffer */
+
+ /* Size of input buffer in bytes, not including room for EOB
+ * characters.
+ */
+ yy_size_t yy_buf_size;
+
+ /* Number of characters read into yy_ch_buf, not including EOB
+ * characters.
+ */
+ yy_size_t yy_n_chars;
+
+ /* Whether we "own" the buffer - i.e., we know we created it,
+ * and can realloc() it to grow it, and should free() it to
+ * delete it.
+ */
+ int yy_is_our_buffer;
+
+ /* Whether this is an "interactive" input source; if so, and
+ * if we're using stdio for input, then we want to use getc()
+ * instead of fread(), to make sure we stop fetching input after
+ * each newline.
+ */
+ int yy_is_interactive;
+
+ /* Whether we're considered to be at the beginning of a line.
+ * If so, '^' rules will be active on the next match, otherwise
+ * not.
+ */
+ int yy_at_bol;
+
+ int yy_bs_lineno; /**< The line count. */
+ int yy_bs_column; /**< The column count. */
+
+ /* Whether to try to fill the input buffer when we reach the
+ * end of it.
+ */
+ int yy_fill_buffer;
+
+ int yy_buffer_status;
+
+#define YY_BUFFER_NEW 0
+#define YY_BUFFER_NORMAL 1
+ /* When an EOF's been seen but there's still some text to process
+ * then we mark the buffer as YY_EOF_PENDING, to indicate that we
+ * shouldn't try reading from the input source any more. We might
+ * still have a bunch of tokens to match, though, because of
+ * possible backing-up.
+ *
+ * When we actually see the EOF, we change the status to "new"
+ * (via yyrestart()), so that the user can continue scanning by
+ * just pointing yyin at a new input file.
+ */
+#define YY_BUFFER_EOF_PENDING 2
+
+ };
+#endif /* !YY_STRUCT_YY_BUFFER_STATE */
+
+/* We provide macros for accessing buffer states in case in the
+ * future we want to put the buffer states in a more general
+ * "scanner state".
+ *
+ * Returns the top of the stack, or NULL.
+ */
+#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \
+ ? (yy_buffer_stack)[(yy_buffer_stack_top)] \
+ : NULL)
+
+/* Same as previous macro, but useful when we know that the buffer stack is not
+ * NULL or when we need an lvalue. For internal use only.
+ */
+#define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)]
+
+void *yyalloc (yy_size_t );
+void *yyrealloc (void *,yy_size_t );
+void yyfree (void * );
+
+#define yy_new_buffer yy_create_buffer
+
+#define yy_set_interactive(is_interactive) \
+ { \
+ if ( ! YY_CURRENT_BUFFER ){ \
+ yyensure_buffer_stack (); \
+ YY_CURRENT_BUFFER_LVALUE = \
+ yy_create_buffer( yyin, YY_BUF_SIZE ); \
+ } \
+ YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \
+ }
+
+#define yy_set_bol(at_bol) \
+ { \
+ if ( ! YY_CURRENT_BUFFER ){\
+ yyensure_buffer_stack (); \
+ YY_CURRENT_BUFFER_LVALUE = \
+ yy_create_buffer( yyin, YY_BUF_SIZE ); \
+ } \
+ YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \
+ }
+
+#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol)
+
+/* Begin user sect3 */
+#define YY_SKIP_YYWRAP
+
+typedef unsigned char YY_CHAR;
+
+#define yytext_ptr yytext
+
+#include <FlexLexer.h>
+
+int yyFlexLexer::yywrap() { return 1; }
+int yyFlexLexer::yylex()
+ {
+ LexerError( "yyFlexLexer::yylex invoked but %option yyclass used" );
+ return 0;
+ }
+
+#define YY_DECL int ElftosbLexer::yylex()
+
+/* Done after the current pattern has been matched and before the
+ * corresponding action - sets up yytext.
+ */
+#define YY_DO_BEFORE_ACTION \
+ (yytext_ptr) = yy_bp; \
+ yyleng = (size_t) (yy_cp - yy_bp); \
+ (yy_hold_char) = *yy_cp; \
+ *yy_cp = '\0'; \
+ (yy_c_buf_p) = yy_cp;
+
+#define YY_NUM_RULES 74
+#define YY_END_OF_BUFFER 75
+/* This struct is not used in this scanner,
+ but its presence is necessary. */
+struct yy_trans_info
+ {
+ flex_int32_t yy_verify;
+ flex_int32_t yy_nxt;
+ };
+static yyconst flex_int16_t yy_accept[218] =
+ { 0,
+ 0, 0, 0, 0, 0, 0, 75, 73, 70, 71,
+ 71, 64, 73, 73, 73, 49, 54, 73, 34, 35,
+ 47, 45, 39, 46, 42, 48, 27, 27, 40, 41,
+ 57, 38, 43, 26, 36, 37, 51, 26, 26, 26,
+ 26, 26, 26, 26, 26, 26, 26, 26, 26, 26,
+ 26, 26, 26, 26, 32, 55, 33, 50, 73, 73,
+ 72, 70, 71, 72, 71, 61, 0, 65, 0, 0,
+ 69, 29, 62, 0, 0, 56, 44, 30, 0, 0,
+ 27, 27, 0, 0, 52, 59, 60, 58, 53, 26,
+ 23, 26, 26, 26, 26, 26, 26, 26, 26, 26,
+
+ 26, 26, 13, 26, 26, 26, 26, 26, 25, 26,
+ 26, 26, 26, 26, 26, 26, 26, 31, 63, 66,
+ 67, 68, 0, 0, 28, 0, 0, 27, 27, 26,
+ 26, 20, 26, 26, 26, 26, 26, 26, 26, 21,
+ 26, 22, 26, 26, 26, 26, 8, 26, 26, 26,
+ 26, 26, 24, 0, 0, 28, 0, 0, 0, 11,
+ 26, 26, 14, 26, 26, 26, 26, 7, 16, 10,
+ 9, 12, 26, 26, 26, 26, 26, 0, 0, 0,
+ 0, 28, 0, 26, 26, 18, 26, 26, 26, 26,
+ 26, 26, 26, 28, 0, 28, 0, 26, 26, 6,
+
+ 26, 26, 26, 19, 26, 26, 0, 26, 15, 4,
+ 1, 5, 3, 17, 26, 2, 0
+ } ;
+
+static yyconst flex_int32_t yy_ec[256] =
+ { 0,
+ 1, 1, 1, 1, 1, 1, 1, 1, 2, 3,
+ 1, 1, 4, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 2, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
+ 22, 22, 22, 22, 22, 22, 22, 23, 24, 25,
+ 26, 27, 28, 1, 29, 29, 30, 29, 31, 29,
+ 32, 33, 33, 33, 32, 33, 32, 33, 33, 33,
+ 33, 33, 34, 33, 33, 33, 33, 33, 33, 33,
+ 35, 1, 36, 37, 33, 1, 38, 39, 40, 41,
+
+ 42, 43, 44, 45, 46, 47, 33, 48, 49, 50,
+ 51, 52, 33, 53, 54, 55, 56, 57, 58, 59,
+ 60, 61, 62, 63, 64, 65, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1
+ } ;
+
+static yyconst flex_int32_t yy_meta[66] =
+ { 0,
+ 1, 1, 2, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 3, 1, 1, 3, 3, 1, 4,
+ 4, 4, 1, 1, 1, 1, 1, 3, 4, 4,
+ 4, 5, 5, 5, 3, 3, 3, 4, 4, 4,
+ 4, 4, 4, 5, 5, 5, 5, 5, 5, 5,
+ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+ 5, 1, 1, 1, 1
+ } ;
+
+static yyconst flex_int16_t yy_base[231] =
+ { 0,
+ 0, 0, 64, 127, 67, 73, 384, 385, 385, 385,
+ 380, 356, 66, 378, 0, 385, 370, 348, 385, 385,
+ 364, 385, 385, 385, 359, 59, 78, 94, 385, 385,
+ 57, 350, 62, 0, 385, 385, 385, 191, 41, 69,
+ 60, 74, 337, 75, 318, 322, 321, 320, 318, 331,
+ 92, 315, 329, 324, 303, 301, 385, 385, 0, 299,
+ 385, 385, 359, 342, 385, 385, 115, 385, 129, 357,
+ 385, 0, 385, 111, 128, 385, 385, 385, 356, 121,
+ 152, 385, 70, 0, 385, 385, 385, 385, 385, 0,
+ 385, 310, 307, 315, 312, 300, 300, 297, 303, 302,
+
+ 298, 309, 0, 304, 291, 296, 306, 302, 0, 287,
+ 283, 300, 278, 282, 281, 283, 281, 385, 385, 385,
+ 385, 385, 145, 113, 130, 200, 202, 218, 148, 286,
+ 279, 0, 286, 289, 279, 287, 274, 272, 277, 0,
+ 274, 0, 272, 282, 280, 275, 0, 265, 277, 265,
+ 275, 266, 0, 146, 284, 283, 102, 148, 210, 0,
+ 258, 262, 0, 258, 257, 267, 266, 0, 0, 0,
+ 0, 0, 256, 257, 247, 253, 242, 270, 153, 160,
+ 211, 212, 213, 214, 209, 0, 199, 195, 196, 189,
+ 194, 194, 185, 385, 200, 198, 151, 162, 148, 0,
+
+ 134, 132, 135, 0, 129, 111, 214, 90, 0, 0,
+ 0, 0, 0, 0, 86, 0, 385, 256, 261, 266,
+ 271, 274, 279, 281, 97, 286, 70, 291, 296, 301
+ } ;
+
+static yyconst flex_int16_t yy_def[231] =
+ { 0,
+ 217, 1, 218, 218, 219, 219, 217, 217, 217, 217,
+ 217, 217, 220, 221, 222, 217, 217, 223, 217, 217,
+ 217, 217, 217, 217, 217, 217, 217, 217, 217, 217,
+ 217, 217, 217, 224, 217, 217, 217, 224, 224, 224,
+ 224, 224, 38, 224, 224, 224, 224, 224, 224, 224,
+ 224, 224, 38, 224, 217, 217, 217, 217, 225, 217,
+ 217, 217, 217, 217, 217, 217, 220, 217, 220, 221,
+ 217, 222, 217, 226, 226, 217, 217, 217, 221, 217,
+ 217, 217, 217, 227, 217, 217, 217, 217, 217, 224,
+ 217, 224, 224, 224, 224, 224, 224, 224, 224, 224,
+
+ 224, 224, 224, 224, 224, 224, 224, 224, 224, 224,
+ 224, 224, 224, 224, 224, 224, 224, 217, 217, 217,
+ 217, 217, 220, 228, 228, 228, 228, 217, 227, 224,
+ 224, 224, 224, 224, 224, 224, 224, 224, 224, 224,
+ 224, 224, 224, 224, 224, 224, 224, 224, 224, 224,
+ 224, 224, 224, 220, 229, 229, 229, 229, 230, 224,
+ 224, 224, 224, 224, 224, 224, 224, 224, 224, 224,
+ 224, 224, 224, 224, 224, 224, 224, 217, 217, 217,
+ 228, 228, 228, 224, 224, 224, 224, 224, 224, 224,
+ 224, 224, 224, 217, 217, 229, 229, 224, 224, 224,
+
+ 224, 224, 224, 224, 224, 224, 228, 224, 224, 224,
+ 224, 224, 224, 224, 224, 224, 0, 217, 217, 217,
+ 217, 217, 217, 217, 217, 217, 217, 217, 217, 217
+ } ;
+
+static yyconst flex_int16_t yy_nxt[451] =
+ { 0,
+ 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
+ 28, 28, 29, 30, 31, 32, 33, 8, 34, 34,
+ 34, 34, 34, 34, 35, 36, 37, 34, 38, 39,
+ 40, 41, 42, 34, 43, 44, 45, 46, 47, 48,
+ 49, 34, 50, 51, 52, 34, 34, 53, 34, 54,
+ 34, 55, 56, 57, 58, 9, 10, 11, 62, 10,
+ 63, 68, 78, 129, 62, 10, 63, 79, 92, 80,
+ 64, 85, 86, 59, 59, 59, 64, 88, 89, 128,
+ 128, 93, 59, 59, 59, 80, 69, 81, 81, 81,
+
+ 120, 59, 59, 59, 59, 59, 59, 96, 94, 82,
+ 95, 99, 97, 81, 81, 81, 83, 103, 98, 100,
+ 68, 125, 80, 156, 104, 82, 101, 60, 9, 10,
+ 11, 105, 179, 112, 68, 180, 84, 113, 125, 216,
+ 156, 126, 114, 157, 215, 69, 59, 59, 59, 80,
+ 68, 68, 82, 80, 214, 59, 59, 59, 126, 69,
+ 157, 127, 123, 194, 59, 59, 59, 59, 59, 59,
+ 194, 81, 81, 81, 154, 69, 69, 181, 179, 82,
+ 207, 179, 213, 82, 212, 211, 195, 210, 209, 155,
+ 60, 91, 91, 91, 91, 91, 91, 91, 91, 91,
+
+ 91, 91, 91, 91, 91, 91, 91, 91, 91, 91,
+ 156, 208, 156, 91, 91, 91, 91, 91, 91, 80,
+ 182, 196, 196, 196, 196, 91, 91, 91, 179, 178,
+ 157, 159, 157, 158, 206, 205, 204, 128, 128, 203,
+ 183, 157, 157, 157, 157, 202, 197, 201, 200, 82,
+ 199, 198, 91, 91, 91, 91, 8, 8, 8, 8,
+ 8, 61, 61, 61, 61, 61, 67, 67, 67, 67,
+ 67, 70, 70, 70, 70, 70, 72, 72, 72, 74,
+ 194, 74, 74, 74, 90, 90, 124, 193, 124, 124,
+ 124, 155, 192, 155, 155, 155, 178, 191, 178, 178,
+
+ 178, 181, 190, 181, 181, 181, 189, 188, 109, 187,
+ 186, 185, 184, 179, 179, 177, 153, 176, 175, 174,
+ 173, 172, 171, 170, 169, 168, 167, 166, 165, 164,
+ 163, 162, 161, 160, 153, 152, 151, 150, 149, 148,
+ 147, 146, 145, 144, 143, 142, 141, 140, 139, 138,
+ 137, 136, 135, 134, 133, 132, 131, 130, 71, 71,
+ 122, 65, 121, 119, 118, 117, 116, 115, 111, 110,
+ 109, 108, 107, 106, 102, 87, 77, 76, 75, 73,
+ 71, 66, 65, 217, 7, 217, 217, 217, 217, 217,
+ 217, 217, 217, 217, 217, 217, 217, 217, 217, 217,
+
+ 217, 217, 217, 217, 217, 217, 217, 217, 217, 217,
+ 217, 217, 217, 217, 217, 217, 217, 217, 217, 217,
+ 217, 217, 217, 217, 217, 217, 217, 217, 217, 217,
+ 217, 217, 217, 217, 217, 217, 217, 217, 217, 217,
+ 217, 217, 217, 217, 217, 217, 217, 217, 217, 217
+ } ;
+
+static yyconst flex_int16_t yy_chk[451] =
+ { 0,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 3, 3, 3, 5, 5,
+ 5, 13, 26, 227, 6, 6, 6, 26, 39, 27,
+ 5, 31, 31, 3, 3, 3, 6, 33, 33, 83,
+ 83, 39, 3, 3, 3, 28, 13, 27, 27, 27,
+
+ 225, 3, 3, 3, 3, 3, 3, 41, 40, 27,
+ 40, 42, 41, 28, 28, 28, 27, 44, 41, 42,
+ 67, 74, 80, 124, 44, 28, 42, 3, 4, 4,
+ 4, 44, 157, 51, 69, 157, 27, 51, 75, 215,
+ 125, 74, 51, 124, 208, 67, 4, 4, 4, 129,
+ 123, 154, 80, 81, 206, 4, 4, 4, 75, 69,
+ 125, 75, 69, 179, 4, 4, 4, 4, 4, 4,
+ 180, 81, 81, 81, 123, 123, 154, 158, 158, 129,
+ 197, 197, 205, 81, 203, 202, 179, 201, 199, 180,
+ 4, 38, 38, 38, 38, 38, 38, 38, 38, 38,
+
+ 38, 38, 38, 38, 38, 38, 38, 38, 38, 38,
+ 126, 198, 127, 38, 38, 38, 38, 38, 38, 128,
+ 159, 181, 182, 183, 207, 38, 38, 38, 196, 195,
+ 126, 127, 127, 126, 193, 192, 191, 128, 128, 190,
+ 159, 181, 182, 183, 207, 189, 183, 188, 187, 128,
+ 185, 184, 38, 38, 38, 38, 218, 218, 218, 218,
+ 218, 219, 219, 219, 219, 219, 220, 220, 220, 220,
+ 220, 221, 221, 221, 221, 221, 222, 222, 222, 223,
+ 178, 223, 223, 223, 224, 224, 226, 177, 226, 226,
+ 226, 228, 176, 228, 228, 228, 229, 175, 229, 229,
+
+ 229, 230, 174, 230, 230, 230, 173, 167, 166, 165,
+ 164, 162, 161, 156, 155, 152, 151, 150, 149, 148,
+ 146, 145, 144, 143, 141, 139, 138, 137, 136, 135,
+ 134, 133, 131, 130, 117, 116, 115, 114, 113, 112,
+ 111, 110, 108, 107, 106, 105, 104, 102, 101, 100,
+ 99, 98, 97, 96, 95, 94, 93, 92, 79, 70,
+ 64, 63, 60, 56, 55, 54, 53, 52, 50, 49,
+ 48, 47, 46, 45, 43, 32, 25, 21, 18, 17,
+ 14, 12, 11, 7, 217, 217, 217, 217, 217, 217,
+ 217, 217, 217, 217, 217, 217, 217, 217, 217, 217,
+
+ 217, 217, 217, 217, 217, 217, 217, 217, 217, 217,
+ 217, 217, 217, 217, 217, 217, 217, 217, 217, 217,
+ 217, 217, 217, 217, 217, 217, 217, 217, 217, 217,
+ 217, 217, 217, 217, 217, 217, 217, 217, 217, 217,
+ 217, 217, 217, 217, 217, 217, 217, 217, 217, 217
+ } ;
+
+/* Table of booleans, true if rule could match eol. */
+static yyconst flex_int32_t yy_rule_can_match_eol[75] =
+ { 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, };
+
+/* The intent behind this definition is that it'll catch
+ * any uses of REJECT which flex missed.
+ */
+#define REJECT reject_used_but_not_detected
+#define yymore() yymore_used_but_not_detected
+#define YY_MORE_ADJ 0
+#define YY_RESTORE_YY_MORE_OFFSET
+#line 1 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+/* %option prefix="Elftosb" */
+#line 10 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+#include "ElftosbLexer.h"
+#include <stdlib.h>
+#include <limits.h>
+#include <string>
+#include "HexValues.h"
+#include "Value.h"
+
+using namespace elftosb;
+
+//! Always executed before all other actions when a token is matched.
+//! This action just assign the first and last lines of the token to
+//! the current line. In most cases this is correct.
+#define YY_USER_ACTION do { \
+ m_location.m_firstLine = m_line; \
+ m_location.m_lastLine = m_line; \
+ } while (0);
+
+/* start conditions */
+
+#line 628 "/Users/creed/projects/fsl/fromsvr/elftosb/build/elftosb.build/Debug/elftosb.build/DerivedSources/elftosb_lexer.cpp"
+
+#define INITIAL 0
+#define blob 1
+#define mlcmt 2
+
+#ifndef YY_NO_UNISTD_H
+/* Special case for "unistd.h", since it is non-ANSI. We include it way
+ * down here because we want the user's section 1 to have been scanned first.
+ * The user has a chance to override it with an option.
+ */
+#include <unistd.h>
+#endif
+
+#ifndef YY_EXTRA_TYPE
+#define YY_EXTRA_TYPE void *
+#endif
+
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char *,yyconst char *,int );
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * );
+#endif
+
+#ifndef YY_NO_INPUT
+
+#endif
+
+/* Amount of stuff to slurp up with each read. */
+#ifndef YY_READ_BUF_SIZE
+#define YY_READ_BUF_SIZE 8192
+#endif
+
+/* Copy whatever the last rule matched to the standard output. */
+#ifndef ECHO
+#define ECHO LexerOutput( yytext, yyleng )
+#endif
+
+/* Gets input and stuffs it into "buf". number of characters read, or YY_NULL,
+ * is returned in "result".
+ */
+#ifndef YY_INPUT
+#define YY_INPUT(buf,result,max_size) \
+\
+ if ( (result = LexerInput( (char *) buf, max_size )) < 0 ) \
+ YY_FATAL_ERROR( "input in flex scanner failed" );
+
+#endif
+
+/* No semi-colon after return; correct usage is to write "yyterminate();" -
+ * we don't want an extra ';' after the "return" because that will cause
+ * some compilers to complain about unreachable statements.
+ */
+#ifndef yyterminate
+#define yyterminate() return YY_NULL
+#endif
+
+/* Number of entries by which start-condition stack grows. */
+#ifndef YY_START_STACK_INCR
+#define YY_START_STACK_INCR 25
+#endif
+
+/* Report a fatal error. */
+#ifndef YY_FATAL_ERROR
+#define YY_FATAL_ERROR(msg) LexerError( msg )
+#endif
+
+/* end tables serialization structures and prototypes */
+
+/* Default declaration of generated scanner - a define so the user can
+ * easily add parameters.
+ */
+#ifndef YY_DECL
+#define YY_DECL_IS_OURS 1
+#define YY_DECL int yyFlexLexer::yylex()
+#endif /* !YY_DECL */
+
+/* Code executed at the beginning of each rule, after yytext and yyleng
+ * have been set up.
+ */
+#ifndef YY_USER_ACTION
+#define YY_USER_ACTION
+#endif
+
+/* Code executed at the end of each rule. */
+#ifndef YY_BREAK
+#define YY_BREAK break;
+#endif
+
+#define YY_RULE_SETUP \
+ YY_USER_ACTION
+
+/** The main scanner function which does all the work.
+ */
+YY_DECL
+{
+ register yy_state_type yy_current_state;
+ register char *yy_cp, *yy_bp;
+ register int yy_act;
+
+#line 38 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+
+
+#line 733 "/Users/creed/projects/fsl/fromsvr/elftosb/build/elftosb.build/Debug/elftosb.build/DerivedSources/elftosb_lexer.cpp"
+
+ if ( !(yy_init) )
+ {
+ (yy_init) = 1;
+
+#ifdef YY_USER_INIT
+ YY_USER_INIT;
+#endif
+
+ if ( ! (yy_start) )
+ (yy_start) = 1; /* first start state */
+
+ if ( ! yyin )
+ yyin = & std::cin;
+
+ if ( ! yyout )
+ yyout = & std::cout;
+
+ if ( ! YY_CURRENT_BUFFER ) {
+ yyensure_buffer_stack ();
+ YY_CURRENT_BUFFER_LVALUE =
+ yy_create_buffer( yyin, YY_BUF_SIZE );
+ }
+
+ yy_load_buffer_state( );
+ }
+
+ while ( 1 ) /* loops until end-of-file is reached */
+ {
+ yy_cp = (yy_c_buf_p);
+
+ /* Support of yytext. */
+ *yy_cp = (yy_hold_char);
+
+ /* yy_bp points to the position in yy_ch_buf of the start of
+ * the current run.
+ */
+ yy_bp = yy_cp;
+
+ yy_current_state = (yy_start);
+yy_match:
+ do
+ {
+ register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)];
+ if ( yy_accept[yy_current_state] )
+ {
+ (yy_last_accepting_state) = yy_current_state;
+ (yy_last_accepting_cpos) = yy_cp;
+ }
+ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+ {
+ yy_current_state = (int) yy_def[yy_current_state];
+ if ( yy_current_state >= 218 )
+ yy_c = yy_meta[(unsigned int) yy_c];
+ }
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+ ++yy_cp;
+ }
+ while ( yy_current_state != 217 );
+ yy_cp = (yy_last_accepting_cpos);
+ yy_current_state = (yy_last_accepting_state);
+
+yy_find_action:
+ yy_act = yy_accept[yy_current_state];
+
+ YY_DO_BEFORE_ACTION;
+
+ if ( yy_act != YY_END_OF_BUFFER && yy_rule_can_match_eol[yy_act] )
+ {
+ int yyl;
+ for ( yyl = 0; yyl < yyleng; ++yyl )
+ if ( yytext[yyl] == '\n' )
+
+ yylineno++;
+;
+ }
+
+do_action: /* This label is used only to access EOF actions. */
+
+ switch ( yy_act )
+ { /* beginning of action switch */
+ case 0: /* must back up */
+ /* undo the effects of YY_DO_BEFORE_ACTION */
+ *yy_cp = (yy_hold_char);
+ yy_cp = (yy_last_accepting_cpos);
+ yy_current_state = (yy_last_accepting_state);
+ goto yy_find_action;
+
+case 1:
+YY_RULE_SETUP
+#line 40 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_OPTIONS; }
+ YY_BREAK
+case 2:
+YY_RULE_SETUP
+#line 41 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_CONSTANTS; }
+ YY_BREAK
+case 3:
+YY_RULE_SETUP
+#line 42 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_SOURCES; }
+ YY_BREAK
+case 4:
+YY_RULE_SETUP
+#line 43 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_FILTERS; }
+ YY_BREAK
+case 5:
+YY_RULE_SETUP
+#line 44 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_SECTION; }
+ YY_BREAK
+case 6:
+YY_RULE_SETUP
+#line 45 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_EXTERN; }
+ YY_BREAK
+case 7:
+YY_RULE_SETUP
+#line 46 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_FROM; }
+ YY_BREAK
+case 8:
+YY_RULE_SETUP
+#line 47 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_RAW; }
+ YY_BREAK
+case 9:
+YY_RULE_SETUP
+#line 48 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_LOAD; }
+ YY_BREAK
+case 10:
+YY_RULE_SETUP
+#line 49 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_JUMP; }
+ YY_BREAK
+case 11:
+YY_RULE_SETUP
+#line 50 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_CALL; }
+ YY_BREAK
+case 12:
+YY_RULE_SETUP
+#line 51 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_MODE; }
+ YY_BREAK
+case 13:
+YY_RULE_SETUP
+#line 52 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_IF; }
+ YY_BREAK
+case 14:
+YY_RULE_SETUP
+#line 53 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_ELSE; }
+ YY_BREAK
+case 15:
+YY_RULE_SETUP
+#line 54 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_DEFINED; }
+ YY_BREAK
+case 16:
+YY_RULE_SETUP
+#line 55 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_INFO; }
+ YY_BREAK
+case 17:
+YY_RULE_SETUP
+#line 56 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_WARNING; }
+ YY_BREAK
+case 18:
+YY_RULE_SETUP
+#line 57 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_ERROR; }
+ YY_BREAK
+case 19:
+YY_RULE_SETUP
+#line 58 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_SIZEOF; }
+ YY_BREAK
+case 20:
+YY_RULE_SETUP
+#line 59 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_DCD; }
+ YY_BREAK
+case 21:
+YY_RULE_SETUP
+#line 60 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_HAB; }
+ YY_BREAK
+case 22:
+YY_RULE_SETUP
+#line 61 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_IVT; }
+ YY_BREAK
+case 23:
+/* rule 23 can match eol */
+*yy_cp = (yy_hold_char); /* undo effects of setting up yytext */
+(yy_c_buf_p) = yy_cp = yy_bp + 1;
+YY_DO_BEFORE_ACTION; /* set up yytext again */
+YY_RULE_SETUP
+#line 63 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ // must be followed by any non-ident char
+ int_size_t theSize;
+ switch (yytext[0])
+ {
+ case 'w':
+ theSize = kWordSize;
+ break;
+ case 'h':
+ theSize = kHalfWordSize;
+ break;
+ case 'b':
+ theSize = kByteSize;
+ break;
+ }
+ m_symbolValue.m_int = new elftosb::SizedIntegerValue(0, theSize);
+ return TOK_INT_SIZE;
+ }
+ YY_BREAK
+case 24:
+YY_RULE_SETUP
+#line 81 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{
+ m_symbolValue.m_int = new elftosb::SizedIntegerValue(1, kWordSize);
+ return TOK_INT_LITERAL;
+ }
+ YY_BREAK
+case 25:
+YY_RULE_SETUP
+#line 86 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{
+ m_symbolValue.m_int = new elftosb::SizedIntegerValue(0, kWordSize);
+ return TOK_INT_LITERAL;
+ }
+ YY_BREAK
+case 26:
+YY_RULE_SETUP
+#line 91 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{
+ m_symbolValue.m_str = new std::string(yytext);
+ if (isSourceName(m_symbolValue.m_str))
+ {
+ return TOK_SOURCE_NAME;
+ }
+ else
+ {
+ return TOK_IDENT;
+ }
+ }
+ YY_BREAK
+case 27:
+YY_RULE_SETUP
+#line 103 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{
+ int base = 0;
+ uint32_t value;
+ int mult;
+
+ // check for binary number
+ if (yytext[0] == '0' && yytext[1] == 'b')
+ {
+ base = 2; // this is a binary number
+ yytext += 2; // skip over the "0b"
+ }
+
+ // convert value
+ value = (uint32_t)strtoul(yytext, NULL, base);
+
+ // find multiplier
+ switch (yytext[strlen(yytext) - 1])
+ {
+ case 'G':
+ mult = 1024 * 1024 * 1024;
+ break;
+ case 'M':
+ mult = 1024 * 1024;
+ break;
+ case 'K':
+ mult = 1024;
+ break;
+ default:
+ mult = 1;
+ break;
+ }
+
+ // set resulting symbol value
+ m_symbolValue.m_int = new elftosb::SizedIntegerValue(value * mult, kWordSize);
+ return TOK_INT_LITERAL;
+ }
+ YY_BREAK
+case 28:
+YY_RULE_SETUP
+#line 140 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{
+ uint32_t value = 0;
+ int_size_t theSize;
+ int len = strlen(yytext);
+ if (len >= 3)
+ {
+ value = yytext[1];
+ theSize = kByteSize;
+ }
+ if (len >= 4)
+ {
+ value = (value << 8) | yytext[2];
+ theSize = kHalfWordSize;
+ }
+ if (len >= 6)
+ {
+ value = (value << 8) | yytext[3];
+ value = (value << 8) | yytext[4];
+ theSize = kWordSize;
+ }
+ m_symbolValue.m_int = new elftosb::SizedIntegerValue(value, theSize);
+ return TOK_INT_LITERAL;
+ }
+ YY_BREAK
+case 29:
+YY_RULE_SETUP
+#line 164 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{
+ // remove $ from string
+ m_symbolValue.m_str = new std::string(&yytext[1]);
+ return TOK_SECTION_NAME;
+ }
+ YY_BREAK
+case 30:
+YY_RULE_SETUP
+#line 171 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ BEGIN(mlcmt); }
+ YY_BREAK
+case 31:
+YY_RULE_SETUP
+#line 173 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{
+ m_blob = new Blob();
+ m_blobFirstLine = yylineno;
+ BEGIN(blob);
+ }
+ YY_BREAK
+case 32:
+YY_RULE_SETUP
+#line 179 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '{'; }
+ YY_BREAK
+case 33:
+YY_RULE_SETUP
+#line 181 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '}'; }
+ YY_BREAK
+case 34:
+YY_RULE_SETUP
+#line 183 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '('; }
+ YY_BREAK
+case 35:
+YY_RULE_SETUP
+#line 185 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return ')'; }
+ YY_BREAK
+case 36:
+YY_RULE_SETUP
+#line 187 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '['; }
+ YY_BREAK
+case 37:
+YY_RULE_SETUP
+#line 189 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return ']'; }
+ YY_BREAK
+case 38:
+YY_RULE_SETUP
+#line 191 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '='; }
+ YY_BREAK
+case 39:
+YY_RULE_SETUP
+#line 193 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return ','; }
+ YY_BREAK
+case 40:
+YY_RULE_SETUP
+#line 195 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return ':'; }
+ YY_BREAK
+case 41:
+YY_RULE_SETUP
+#line 197 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return ';'; }
+ YY_BREAK
+case 42:
+YY_RULE_SETUP
+#line 199 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '.'; }
+ YY_BREAK
+case 43:
+YY_RULE_SETUP
+#line 201 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '>'; }
+ YY_BREAK
+case 44:
+YY_RULE_SETUP
+#line 203 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_DOT_DOT; }
+ YY_BREAK
+case 45:
+YY_RULE_SETUP
+#line 205 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '+'; }
+ YY_BREAK
+case 46:
+YY_RULE_SETUP
+#line 207 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '-'; }
+ YY_BREAK
+case 47:
+YY_RULE_SETUP
+#line 209 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '*'; }
+ YY_BREAK
+case 48:
+YY_RULE_SETUP
+#line 211 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '/'; }
+ YY_BREAK
+case 49:
+YY_RULE_SETUP
+#line 213 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '%'; }
+ YY_BREAK
+case 50:
+YY_RULE_SETUP
+#line 215 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '~'; }
+ YY_BREAK
+case 51:
+YY_RULE_SETUP
+#line 217 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '^'; }
+ YY_BREAK
+case 52:
+YY_RULE_SETUP
+#line 219 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_LSHIFT; }
+ YY_BREAK
+case 53:
+YY_RULE_SETUP
+#line 221 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_RSHIFT; }
+ YY_BREAK
+case 54:
+YY_RULE_SETUP
+#line 223 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '&'; }
+ YY_BREAK
+case 55:
+YY_RULE_SETUP
+#line 225 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '|'; }
+ YY_BREAK
+case 56:
+YY_RULE_SETUP
+#line 227 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_POWER; }
+ YY_BREAK
+case 57:
+YY_RULE_SETUP
+#line 229 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '<'; }
+ YY_BREAK
+case 58:
+YY_RULE_SETUP
+#line 231 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_GEQ; }
+ YY_BREAK
+case 59:
+YY_RULE_SETUP
+#line 233 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_LEQ; }
+ YY_BREAK
+case 60:
+YY_RULE_SETUP
+#line 235 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_EQ; }
+ YY_BREAK
+case 61:
+YY_RULE_SETUP
+#line 237 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_NEQ; }
+ YY_BREAK
+case 62:
+YY_RULE_SETUP
+#line 239 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_AND; }
+ YY_BREAK
+case 63:
+YY_RULE_SETUP
+#line 241 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return TOK_OR; }
+ YY_BREAK
+case 64:
+YY_RULE_SETUP
+#line 243 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{ return '!'; }
+ YY_BREAK
+case 65:
+/* rule 65 can match eol */
+YY_RULE_SETUP
+#line 245 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{
+ // get rid of quotes
+ yytext++;
+ yytext[strlen(yytext) - 1] = 0;
+// processStringEscapes(yytext, yytext);
+ m_symbolValue.m_str = new std::string(yytext);
+ return TOK_STRING_LITERAL;
+ }
+ YY_BREAK
+case 66:
+YY_RULE_SETUP
+#line 254 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{
+ uint8_t x = (hexCharToInt(yytext[0]) << 4) | hexCharToInt(yytext[1]);
+ m_blob->append(&x, 1);
+ }
+ YY_BREAK
+case 67:
+YY_RULE_SETUP
+#line 259 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{
+ BEGIN(INITIAL);
+ m_symbolValue.m_blob = m_blob;
+ m_blob = NULL;
+ m_location.m_firstLine = m_blobFirstLine;
+ return TOK_BLOB;
+ }
+ YY_BREAK
+case 68:
+YY_RULE_SETUP
+#line 267 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{
+ // end of multi-line comment, return to initial state
+ BEGIN(INITIAL);
+ }
+ YY_BREAK
+case 69:
+*yy_cp = (yy_hold_char); /* undo effects of setting up yytext */
+(yy_c_buf_p) = yy_cp -= 1;
+YY_DO_BEFORE_ACTION; /* set up yytext again */
+YY_RULE_SETUP
+#line 273 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+/* absorb single-line comment */
+ YY_BREAK
+case 70:
+YY_RULE_SETUP
+#line 275 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+/* eat up whitespace in all states */
+ YY_BREAK
+case 71:
+/* rule 71 can match eol */
+YY_RULE_SETUP
+#line 277 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{
+ /* eat up whitespace and count lines in all states */
+ m_line++;
+ }
+ YY_BREAK
+case 72:
+YY_RULE_SETUP
+#line 282 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+/* ignore all other chars in a multi-line comment */
+ YY_BREAK
+case 73:
+YY_RULE_SETUP
+#line 284 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+{
+ /* all other chars produce errors */
+ char msg[50];
+ sprintf(msg, "unexpected character '%c' on line %d", yytext[0], m_line);
+ LexerError(msg);
+ }
+ YY_BREAK
+case 74:
+YY_RULE_SETUP
+#line 291 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+ECHO;
+ YY_BREAK
+#line 1325 "/Users/creed/projects/fsl/fromsvr/elftosb/build/elftosb.build/Debug/elftosb.build/DerivedSources/elftosb_lexer.cpp"
+case YY_STATE_EOF(INITIAL):
+case YY_STATE_EOF(blob):
+case YY_STATE_EOF(mlcmt):
+ yyterminate();
+
+ case YY_END_OF_BUFFER:
+ {
+ /* Amount of text matched not including the EOB char. */
+ int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1;
+
+ /* Undo the effects of YY_DO_BEFORE_ACTION. */
+ *yy_cp = (yy_hold_char);
+ YY_RESTORE_YY_MORE_OFFSET
+
+ if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW )
+ {
+ /* We're scanning a new file or input source. It's
+ * possible that this happened because the user
+ * just pointed yyin at a new source and called
+ * yylex(). If so, then we have to assure
+ * consistency between YY_CURRENT_BUFFER and our
+ * globals. Here is the right place to do so, because
+ * this is the first action (other than possibly a
+ * back-up) that will match for the new input source.
+ */
+ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+ YY_CURRENT_BUFFER_LVALUE->yy_input_file = yyin;
+ YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL;
+ }
+
+ /* Note that here we test for yy_c_buf_p "<=" to the position
+ * of the first EOB in the buffer, since yy_c_buf_p will
+ * already have been incremented past the NUL character
+ * (since all states make transitions on EOB to the
+ * end-of-buffer state). Contrast this with the test
+ * in input().
+ */
+ if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+ { /* This was really a NUL. */
+ yy_state_type yy_next_state;
+
+ (yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text;
+
+ yy_current_state = yy_get_previous_state( );
+
+ /* Okay, we're now positioned to make the NUL
+ * transition. We couldn't have
+ * yy_get_previous_state() go ahead and do it
+ * for us because it doesn't know how to deal
+ * with the possibility of jamming (and we don't
+ * want to build jamming into it because then it
+ * will run more slowly).
+ */
+
+ yy_next_state = yy_try_NUL_trans( yy_current_state );
+
+ yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+
+ if ( yy_next_state )
+ {
+ /* Consume the NUL. */
+ yy_cp = ++(yy_c_buf_p);
+ yy_current_state = yy_next_state;
+ goto yy_match;
+ }
+
+ else
+ {
+ yy_cp = (yy_last_accepting_cpos);
+ yy_current_state = (yy_last_accepting_state);
+ goto yy_find_action;
+ }
+ }
+
+ else switch ( yy_get_next_buffer( ) )
+ {
+ case EOB_ACT_END_OF_FILE:
+ {
+ (yy_did_buffer_switch_on_eof) = 0;
+
+ if ( yywrap( ) )
+ {
+ /* Note: because we've taken care in
+ * yy_get_next_buffer() to have set up
+ * yytext, we can now set up
+ * yy_c_buf_p so that if some total
+ * hoser (like flex itself) wants to
+ * call the scanner after we return the
+ * YY_NULL, it'll still work - another
+ * YY_NULL will get returned.
+ */
+ (yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ;
+
+ yy_act = YY_STATE_EOF(YY_START);
+ goto do_action;
+ }
+
+ else
+ {
+ if ( ! (yy_did_buffer_switch_on_eof) )
+ YY_NEW_FILE;
+ }
+ break;
+ }
+
+ case EOB_ACT_CONTINUE_SCAN:
+ (yy_c_buf_p) =
+ (yytext_ptr) + yy_amount_of_matched_text;
+
+ yy_current_state = yy_get_previous_state( );
+
+ yy_cp = (yy_c_buf_p);
+ yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+ goto yy_match;
+
+ case EOB_ACT_LAST_MATCH:
+ (yy_c_buf_p) =
+ &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)];
+
+ yy_current_state = yy_get_previous_state( );
+
+ yy_cp = (yy_c_buf_p);
+ yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+ goto yy_find_action;
+ }
+ break;
+ }
+
+ default:
+ YY_FATAL_ERROR(
+ "fatal flex scanner internal error--no action found" );
+ } /* end of action switch */
+ } /* end of scanning one token */
+} /* end of yylex */
+
+/* The contents of this function are C++ specific, so the () macro is not used.
+ */
+yyFlexLexer::yyFlexLexer( std::istream* arg_yyin, std::ostream* arg_yyout )
+{
+ yyin = arg_yyin;
+ yyout = arg_yyout;
+ yy_c_buf_p = 0;
+ yy_init = 0;
+ yy_start = 0;
+ yy_flex_debug = 0;
+ yylineno = 1; // this will only get updated if %option yylineno
+
+ yy_did_buffer_switch_on_eof = 0;
+
+ yy_looking_for_trail_begin = 0;
+ yy_more_flag = 0;
+ yy_more_len = 0;
+ yy_more_offset = yy_prev_more_offset = 0;
+
+ yy_start_stack_ptr = yy_start_stack_depth = 0;
+ yy_start_stack = NULL;
+
+ yy_buffer_stack = 0;
+ yy_buffer_stack_top = 0;
+ yy_buffer_stack_max = 0;
+
+ yy_state_buf = 0;
+
+}
+
+/* The contents of this function are C++ specific, so the () macro is not used.
+ */
+yyFlexLexer::~yyFlexLexer()
+{
+ delete [] yy_state_buf;
+ yyfree(yy_start_stack );
+ yy_delete_buffer( YY_CURRENT_BUFFER );
+ yyfree(yy_buffer_stack );
+}
+
+/* The contents of this function are C++ specific, so the () macro is not used.
+ */
+void yyFlexLexer::switch_streams( std::istream* new_in, std::ostream* new_out )
+{
+ if ( new_in )
+ {
+ yy_delete_buffer( YY_CURRENT_BUFFER );
+ yy_switch_to_buffer( yy_create_buffer( new_in, YY_BUF_SIZE ) );
+ }
+
+ if ( new_out )
+ yyout = new_out;
+}
+
+#ifdef YY_INTERACTIVE
+int yyFlexLexer::LexerInput( char* buf, int /* max_size */ )
+#else
+int yyFlexLexer::LexerInput( char* buf, int max_size )
+#endif
+{
+ if ( yyin->eof() || yyin->fail() )
+ return 0;
+
+#ifdef YY_INTERACTIVE
+ yyin->get( buf[0] );
+
+ if ( yyin->eof() )
+ return 0;
+
+ if ( yyin->bad() )
+ return -1;
+
+ return 1;
+
+#else
+ (void) yyin->read( buf, max_size );
+
+ if ( yyin->bad() )
+ return -1;
+ else
+ return yyin->gcount();
+#endif
+}
+
+void yyFlexLexer::LexerOutput( const char* buf, int size )
+{
+ (void) yyout->write( buf, size );
+}
+
+/* yy_get_next_buffer - try to read in a new buffer
+ *
+ * Returns a code representing an action:
+ * EOB_ACT_LAST_MATCH -
+ * EOB_ACT_CONTINUE_SCAN - continue scanning from current position
+ * EOB_ACT_END_OF_FILE - end of file
+ */
+int yyFlexLexer::yy_get_next_buffer()
+{
+ register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;
+ register char *source = (yytext_ptr);
+ register int number_to_move, i;
+ int ret_val;
+
+ if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] )
+ YY_FATAL_ERROR(
+ "fatal flex scanner internal error--end of buffer missed" );
+
+ if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 )
+ { /* Don't try to fill the buffer, so this is an EOF. */
+ if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 )
+ {
+ /* We matched a single character, the EOB, so
+ * treat this as a final EOF.
+ */
+ return EOB_ACT_END_OF_FILE;
+ }
+
+ else
+ {
+ /* We matched some text prior to the EOB, first
+ * process it.
+ */
+ return EOB_ACT_LAST_MATCH;
+ }
+ }
+
+ /* Try to read more data. */
+
+ /* First move last chars to start of buffer. */
+ number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1;
+
+ for ( i = 0; i < number_to_move; ++i )
+ *(dest++) = *(source++);
+
+ if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING )
+ /* don't do the read, it's not guaranteed to return an EOF,
+ * just force an EOF
+ */
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0;
+
+ else
+ {
+ yy_size_t num_to_read =
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1;
+
+ while ( num_to_read <= 0 )
+ { /* Not enough room in the buffer - grow it. */
+
+ /* just a shorter name for the current buffer */
+ YY_BUFFER_STATE b = YY_CURRENT_BUFFER;
+
+ int yy_c_buf_p_offset =
+ (int) ((yy_c_buf_p) - b->yy_ch_buf);
+
+ if ( b->yy_is_our_buffer )
+ {
+ yy_size_t new_size = b->yy_buf_size * 2;
+
+ if ( new_size <= 0 )
+ b->yy_buf_size += b->yy_buf_size / 8;
+ else
+ b->yy_buf_size *= 2;
+
+ b->yy_ch_buf = (char *)
+ /* Include room in for 2 EOB chars. */
+ yyrealloc((void *) b->yy_ch_buf,b->yy_buf_size + 2 );
+ }
+ else
+ /* Can't grow it, we don't own it. */
+ b->yy_ch_buf = 0;
+
+ if ( ! b->yy_ch_buf )
+ YY_FATAL_ERROR(
+ "fatal error - scanner input buffer overflow" );
+
+ (yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset];
+
+ num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size -
+ number_to_move - 1;
+
+ }
+
+ if ( num_to_read > YY_READ_BUF_SIZE )
+ num_to_read = YY_READ_BUF_SIZE;
+
+ /* Read in more data. */
+ YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]),
+ (yy_n_chars), num_to_read );
+
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+ }
+
+ if ( (yy_n_chars) == 0 )
+ {
+ if ( number_to_move == YY_MORE_ADJ )
+ {
+ ret_val = EOB_ACT_END_OF_FILE;
+ yyrestart( yyin );
+ }
+
+ else
+ {
+ ret_val = EOB_ACT_LAST_MATCH;
+ YY_CURRENT_BUFFER_LVALUE->yy_buffer_status =
+ YY_BUFFER_EOF_PENDING;
+ }
+ }
+
+ else
+ ret_val = EOB_ACT_CONTINUE_SCAN;
+
+ if ((yy_size_t) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) {
+ /* Extend the array by 50%, plus the number we really need. */
+ yy_size_t new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1);
+ YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size );
+ if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
+ YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" );
+ }
+
+ (yy_n_chars) += number_to_move;
+ YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR;
+ YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR;
+
+ (yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0];
+
+ return ret_val;
+}
+
+/* yy_get_previous_state - get the state just before the EOB char was reached */
+
+ yy_state_type yyFlexLexer::yy_get_previous_state()
+{
+ register yy_state_type yy_current_state;
+ register char *yy_cp;
+
+ yy_current_state = (yy_start);
+
+ for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp )
+ {
+ register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1);
+ if ( yy_accept[yy_current_state] )
+ {
+ (yy_last_accepting_state) = yy_current_state;
+ (yy_last_accepting_cpos) = yy_cp;
+ }
+ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+ {
+ yy_current_state = (int) yy_def[yy_current_state];
+ if ( yy_current_state >= 218 )
+ yy_c = yy_meta[(unsigned int) yy_c];
+ }
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+ }
+
+ return yy_current_state;
+}
+
+/* yy_try_NUL_trans - try to make a transition on the NUL character
+ *
+ * synopsis
+ * next_state = yy_try_NUL_trans( current_state );
+ */
+ yy_state_type yyFlexLexer::yy_try_NUL_trans( yy_state_type yy_current_state )
+{
+ register int yy_is_jam;
+ register char *yy_cp = (yy_c_buf_p);
+
+ register YY_CHAR yy_c = 1;
+ if ( yy_accept[yy_current_state] )
+ {
+ (yy_last_accepting_state) = yy_current_state;
+ (yy_last_accepting_cpos) = yy_cp;
+ }
+ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+ {
+ yy_current_state = (int) yy_def[yy_current_state];
+ if ( yy_current_state >= 218 )
+ yy_c = yy_meta[(unsigned int) yy_c];
+ }
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+ yy_is_jam = (yy_current_state == 217);
+
+ return yy_is_jam ? 0 : yy_current_state;
+}
+
+ void yyFlexLexer::yyunput( int c, register char* yy_bp)
+{
+ register char *yy_cp;
+
+ yy_cp = (yy_c_buf_p);
+
+ /* undo effects of setting up yytext */
+ *yy_cp = (yy_hold_char);
+
+ if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+ { /* need to shift things up to make room */
+ /* +2 for EOB chars. */
+ register yy_size_t number_to_move = (yy_n_chars) + 2;
+ register char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2];
+ register char *source =
+ &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move];
+
+ while ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
+ *--dest = *--source;
+
+ yy_cp += (int) (dest - source);
+ yy_bp += (int) (dest - source);
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars =
+ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_buf_size;
+
+ if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+ YY_FATAL_ERROR( "flex scanner push-back overflow" );
+ }
+
+ *--yy_cp = (char) c;
+
+ if ( c == '\n' ){
+ --yylineno;
+ }
+
+ (yytext_ptr) = yy_bp;
+ (yy_hold_char) = *yy_cp;
+ (yy_c_buf_p) = yy_cp;
+}
+
+ int yyFlexLexer::yyinput()
+{
+ int c;
+
+ *(yy_c_buf_p) = (yy_hold_char);
+
+ if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR )
+ {
+ /* yy_c_buf_p now points to the character we want to return.
+ * If this occurs *before* the EOB characters, then it's a
+ * valid NUL; if not, then we've hit the end of the buffer.
+ */
+ if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+ /* This was really a NUL. */
+ *(yy_c_buf_p) = '\0';
+
+ else
+ { /* need more input */
+ yy_size_t offset = (yy_c_buf_p) - (yytext_ptr);
+ ++(yy_c_buf_p);
+
+ switch ( yy_get_next_buffer( ) )
+ {
+ case EOB_ACT_LAST_MATCH:
+ /* This happens because yy_g_n_b()
+ * sees that we've accumulated a
+ * token and flags that we need to
+ * try matching the token before
+ * proceeding. But for input(),
+ * there's no matching to consider.
+ * So convert the EOB_ACT_LAST_MATCH
+ * to EOB_ACT_END_OF_FILE.
+ */
+
+ /* Reset buffer status. */
+ yyrestart( yyin );
+
+ /*FALLTHROUGH*/
+
+ case EOB_ACT_END_OF_FILE:
+ {
+ if ( yywrap( ) )
+ return 0;
+
+ if ( ! (yy_did_buffer_switch_on_eof) )
+ YY_NEW_FILE;
+#ifdef __cplusplus
+ return yyinput();
+#else
+ return input();
+#endif
+ }
+
+ case EOB_ACT_CONTINUE_SCAN:
+ (yy_c_buf_p) = (yytext_ptr) + offset;
+ break;
+ }
+ }
+ }
+
+ c = *(unsigned char *) (yy_c_buf_p); /* cast for 8-bit char's */
+ *(yy_c_buf_p) = '\0'; /* preserve yytext */
+ (yy_hold_char) = *++(yy_c_buf_p);
+
+ if ( c == '\n' )
+
+ yylineno++;
+;
+
+ return c;
+}
+
+/** Immediately switch to a different input stream.
+ * @param input_file A readable stream.
+ *
+ * @note This function does not reset the start condition to @c INITIAL .
+ */
+ void yyFlexLexer::yyrestart( std::istream* input_file )
+{
+
+ if ( ! YY_CURRENT_BUFFER ){
+ yyensure_buffer_stack ();
+ YY_CURRENT_BUFFER_LVALUE =
+ yy_create_buffer( yyin, YY_BUF_SIZE );
+ }
+
+ yy_init_buffer( YY_CURRENT_BUFFER, input_file );
+ yy_load_buffer_state( );
+}
+
+/** Switch to a different input buffer.
+ * @param new_buffer The new input buffer.
+ *
+ */
+ void yyFlexLexer::yy_switch_to_buffer( YY_BUFFER_STATE new_buffer )
+{
+
+ /* TODO. We should be able to replace this entire function body
+ * with
+ * yypop_buffer_state();
+ * yypush_buffer_state(new_buffer);
+ */
+ yyensure_buffer_stack ();
+ if ( YY_CURRENT_BUFFER == new_buffer )
+ return;
+
+ if ( YY_CURRENT_BUFFER )
+ {
+ /* Flush out information for old buffer. */
+ *(yy_c_buf_p) = (yy_hold_char);
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+ }
+
+ YY_CURRENT_BUFFER_LVALUE = new_buffer;
+ yy_load_buffer_state( );
+
+ /* We don't actually know whether we did this switch during
+ * EOF (yywrap()) processing, but the only time this flag
+ * is looked at is after yywrap() is called, so it's safe
+ * to go ahead and always set it.
+ */
+ (yy_did_buffer_switch_on_eof) = 1;
+}
+
+ void yyFlexLexer::yy_load_buffer_state()
+{
+ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+ (yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos;
+ yyin = YY_CURRENT_BUFFER_LVALUE->yy_input_file;
+ (yy_hold_char) = *(yy_c_buf_p);
+}
+
+/** Allocate and initialize an input buffer state.
+ * @param file A readable stream.
+ * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE.
+ *
+ * @return the allocated buffer state.
+ */
+ YY_BUFFER_STATE yyFlexLexer::yy_create_buffer( std::istream* file, int size )
+{
+ YY_BUFFER_STATE b;
+
+ b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state ) );
+ if ( ! b )
+ YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
+
+ b->yy_buf_size = size;
+
+ /* yy_ch_buf has to be 2 characters longer than the size given because
+ * we need to put in 2 end-of-buffer characters.
+ */
+ b->yy_ch_buf = (char *) yyalloc(b->yy_buf_size + 2 );
+ if ( ! b->yy_ch_buf )
+ YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
+
+ b->yy_is_our_buffer = 1;
+
+ yy_init_buffer( b, file );
+
+ return b;
+}
+
+/** Destroy the buffer.
+ * @param b a buffer created with yy_create_buffer()
+ *
+ */
+ void yyFlexLexer::yy_delete_buffer( YY_BUFFER_STATE b )
+{
+
+ if ( ! b )
+ return;
+
+ if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */
+ YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0;
+
+ if ( b->yy_is_our_buffer )
+ yyfree((void *) b->yy_ch_buf );
+
+ yyfree((void *) b );
+}
+
+/* Initializes or reinitializes a buffer.
+ * This function is sometimes called more than once on the same buffer,
+ * such as during a yyrestart() or at EOF.
+ */
+ void yyFlexLexer::yy_init_buffer( YY_BUFFER_STATE b, std::istream* file )
+
+{
+ int oerrno = errno;
+
+ yy_flush_buffer( b );
+
+ b->yy_input_file = file;
+ b->yy_fill_buffer = 1;
+
+ /* If b is the current buffer, then yy_init_buffer was _probably_
+ * called from yyrestart() or through yy_get_next_buffer.
+ * In that case, we don't want to reset the lineno or column.
+ */
+ if (b != YY_CURRENT_BUFFER){
+ b->yy_bs_lineno = 1;
+ b->yy_bs_column = 0;
+ }
+
+ b->yy_is_interactive = 0;
+ errno = oerrno;
+}
+
+/** Discard all buffered characters. On the next scan, YY_INPUT will be called.
+ * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER.
+ *
+ */
+ void yyFlexLexer::yy_flush_buffer( YY_BUFFER_STATE b )
+{
+ if ( ! b )
+ return;
+
+ b->yy_n_chars = 0;
+
+ /* We always need two end-of-buffer characters. The first causes
+ * a transition to the end-of-buffer state. The second causes
+ * a jam in that state.
+ */
+ b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;
+ b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;
+
+ b->yy_buf_pos = &b->yy_ch_buf[0];
+
+ b->yy_at_bol = 1;
+ b->yy_buffer_status = YY_BUFFER_NEW;
+
+ if ( b == YY_CURRENT_BUFFER )
+ yy_load_buffer_state( );
+}
+
+/** Pushes the new state onto the stack. The new state becomes
+ * the current state. This function will allocate the stack
+ * if necessary.
+ * @param new_buffer The new state.
+ *
+ */
+void yyFlexLexer::yypush_buffer_state (YY_BUFFER_STATE new_buffer)
+{
+ if (new_buffer == NULL)
+ return;
+
+ yyensure_buffer_stack();
+
+ /* This block is copied from yy_switch_to_buffer. */
+ if ( YY_CURRENT_BUFFER )
+ {
+ /* Flush out information for old buffer. */
+ *(yy_c_buf_p) = (yy_hold_char);
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+ }
+
+ /* Only push if top exists. Otherwise, replace top. */
+ if (YY_CURRENT_BUFFER)
+ (yy_buffer_stack_top)++;
+ YY_CURRENT_BUFFER_LVALUE = new_buffer;
+
+ /* copied from yy_switch_to_buffer. */
+ yy_load_buffer_state( );
+ (yy_did_buffer_switch_on_eof) = 1;
+}
+
+/** Removes and deletes the top of the stack, if present.
+ * The next element becomes the new top.
+ *
+ */
+void yyFlexLexer::yypop_buffer_state (void)
+{
+ if (!YY_CURRENT_BUFFER)
+ return;
+
+ yy_delete_buffer(YY_CURRENT_BUFFER );
+ YY_CURRENT_BUFFER_LVALUE = NULL;
+ if ((yy_buffer_stack_top) > 0)
+ --(yy_buffer_stack_top);
+
+ if (YY_CURRENT_BUFFER) {
+ yy_load_buffer_state( );
+ (yy_did_buffer_switch_on_eof) = 1;
+ }
+}
+
+/* Allocates the stack if it does not exist.
+ * Guarantees space for at least one push.
+ */
+void yyFlexLexer::yyensure_buffer_stack(void)
+{
+ yy_size_t num_to_alloc;
+
+ if (!(yy_buffer_stack)) {
+
+ /* First allocation is just for 2 elements, since we don't know if this
+ * scanner will even need a stack. We use 2 instead of 1 to avoid an
+ * immediate realloc on the next call.
+ */
+ num_to_alloc = 1;
+ (yy_buffer_stack) = (struct yy_buffer_state**)yyalloc
+ (num_to_alloc * sizeof(struct yy_buffer_state*)
+ );
+ if ( ! (yy_buffer_stack) )
+ YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" );
+
+ memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*));
+
+ (yy_buffer_stack_max) = num_to_alloc;
+ (yy_buffer_stack_top) = 0;
+ return;
+ }
+
+ if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){
+
+ /* Increase the buffer to prepare for a possible push. */
+ int grow_size = 8 /* arbitrary grow size */;
+
+ num_to_alloc = (yy_buffer_stack_max) + grow_size;
+ (yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc
+ ((yy_buffer_stack),
+ num_to_alloc * sizeof(struct yy_buffer_state*)
+ );
+ if ( ! (yy_buffer_stack) )
+ YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" );
+
+ /* zero only the new slots.*/
+ memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*));
+ (yy_buffer_stack_max) = num_to_alloc;
+ }
+}
+
+ void yyFlexLexer::yy_push_state( int new_state )
+{
+ if ( (yy_start_stack_ptr) >= (yy_start_stack_depth) )
+ {
+ yy_size_t new_size;
+
+ (yy_start_stack_depth) += YY_START_STACK_INCR;
+ new_size = (yy_start_stack_depth) * sizeof( int );
+
+ if ( ! (yy_start_stack) )
+ (yy_start_stack) = (int *) yyalloc(new_size );
+
+ else
+ (yy_start_stack) = (int *) yyrealloc((void *) (yy_start_stack),new_size );
+
+ if ( ! (yy_start_stack) )
+ YY_FATAL_ERROR( "out of memory expanding start-condition stack" );
+ }
+
+ (yy_start_stack)[(yy_start_stack_ptr)++] = YY_START;
+
+ BEGIN(new_state);
+}
+
+ void yyFlexLexer::yy_pop_state()
+{
+ if ( --(yy_start_stack_ptr) < 0 )
+ YY_FATAL_ERROR( "start-condition stack underflow" );
+
+ BEGIN((yy_start_stack)[(yy_start_stack_ptr)]);
+}
+
+ int yyFlexLexer::yy_top_state()
+{
+ return (yy_start_stack)[(yy_start_stack_ptr) - 1];
+}
+
+#ifndef YY_EXIT_FAILURE
+#define YY_EXIT_FAILURE 2
+#endif
+
+void yyFlexLexer::LexerError( yyconst char msg[] )
+{
+ std::cerr << msg << std::endl;
+ exit( YY_EXIT_FAILURE );
+}
+
+/* Redefine yyless() so it works in section 3 code. */
+
+#undef yyless
+#define yyless(n) \
+ do \
+ { \
+ /* Undo effects of setting up yytext. */ \
+ int yyless_macro_arg = (n); \
+ YY_LESS_LINENO(yyless_macro_arg);\
+ yytext[yyleng] = (yy_hold_char); \
+ (yy_c_buf_p) = yytext + yyless_macro_arg; \
+ (yy_hold_char) = *(yy_c_buf_p); \
+ *(yy_c_buf_p) = '\0'; \
+ yyleng = yyless_macro_arg; \
+ } \
+ while ( 0 )
+
+/* Accessor methods (get/set functions) to struct members. */
+
+/*
+ * Internal utility routines.
+ */
+
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char* s1, yyconst char * s2, int n )
+{
+ register int i;
+ for ( i = 0; i < n; ++i )
+ s1[i] = s2[i];
+}
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * s )
+{
+ register int n;
+ for ( n = 0; s[n]; ++n )
+ ;
+
+ return n;
+}
+#endif
+
+void *yyalloc (yy_size_t size )
+{
+ return (void *) malloc( size );
+}
+
+void *yyrealloc (void * ptr, yy_size_t size )
+{
+ /* The cast to (char *) in the following accommodates both
+ * implementations that use char* generic pointers, and those
+ * that use void* generic pointers. It works with the latter
+ * because both ANSI C and C++ allow castless assignment from
+ * any pointer type to void*, and deal with argument conversions
+ * as though doing an assignment.
+ */
+ return (void *) realloc( (char *) ptr, size );
+}
+
+void yyfree (void * ptr )
+{
+ free( (char *) ptr ); /* see yyrealloc() for (char *) cast */
+}
+
+#define YYTABLES_NAME "yytables"
+
+#line 291 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_lexer.l"
+
+
+
+// verbatim code copied to the bottom of the output
+
+
+
--- /dev/null
+/*
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+%option c++
+/* %option prefix="Elftosb" */
+%option yylineno
+%option never-interactive
+%option yyclass="ElftosbLexer"
+%option noyywrap
+
+%{
+#include "ElftosbLexer.h"
+#include <stdlib.h>
+#include <limits.h>
+#include <string>
+#include "HexValues.h"
+#include "Value.h"
+
+using namespace elftosb;
+
+//! Always executed before all other actions when a token is matched.
+//! This action just assign the first and last lines of the token to
+//! the current line. In most cases this is correct.
+#define YY_USER_ACTION do { \
+ m_location.m_firstLine = m_line; \
+ m_location.m_lastLine = m_line; \
+ } while (0);
+
+%}
+
+DIGIT [0-9]
+HEXDIGIT [0-9a-fA-F]
+BINDIGIT [0-1]
+IDENT [a-zA-Z_][a-zA-Z0-9_]*
+ESC \\(x{HEXDIGIT}{2}|.)
+
+/* start conditions */
+%x blob mlcmt
+
+%%
+
+options { return TOK_OPTIONS; }
+constants { return TOK_CONSTANTS; }
+sources { return TOK_SOURCES; }
+filters { return TOK_FILTERS; }
+section { return TOK_SECTION; }
+extern { return TOK_EXTERN; }
+from { return TOK_FROM; }
+raw { return TOK_RAW; }
+load { return TOK_LOAD; }
+jump { return TOK_JUMP; }
+call { return TOK_CALL; }
+mode { return TOK_MODE; }
+if { return TOK_IF; }
+else { return TOK_ELSE; }
+defined { return TOK_DEFINED; }
+info { return TOK_INFO; }
+warning { return TOK_WARNING; }
+error { return TOK_ERROR; }
+sizeof { return TOK_SIZEOF; }
+dcd { return TOK_DCD; }
+hab { return TOK_HAB; }
+ivt { return TOK_IVT; }
+
+[whb]/[^a-zA-Z_0-9] { // must be followed by any non-ident char
+ int_size_t theSize;
+ switch (yytext[0])
+ {
+ case 'w':
+ theSize = kWordSize;
+ break;
+ case 'h':
+ theSize = kHalfWordSize;
+ break;
+ case 'b':
+ theSize = kByteSize;
+ break;
+ }
+ m_symbolValue.m_int = new elftosb::SizedIntegerValue(0, theSize);
+ return TOK_INT_SIZE;
+ }
+
+true|yes {
+ m_symbolValue.m_int = new elftosb::SizedIntegerValue(1, kWordSize);
+ return TOK_INT_LITERAL;
+ }
+
+false|no {
+ m_symbolValue.m_int = new elftosb::SizedIntegerValue(0, kWordSize);
+ return TOK_INT_LITERAL;
+ }
+
+{IDENT} {
+ m_symbolValue.m_str = new std::string(yytext);
+ if (isSourceName(m_symbolValue.m_str))
+ {
+ return TOK_SOURCE_NAME;
+ }
+ else
+ {
+ return TOK_IDENT;
+ }
+ }
+
+({DIGIT}+|0x{HEXDIGIT}+|0b{BINDIGIT}+)([ \t]*[GMK])? {
+ int base = 0;
+ uint32_t value;
+ int mult;
+
+ // check for binary number
+ if (yytext[0] == '0' && yytext[1] == 'b')
+ {
+ base = 2; // this is a binary number
+ yytext += 2; // skip over the "0b"
+ }
+
+ // convert value
+ value = (uint32_t)strtoul(yytext, NULL, base);
+
+ // find multiplier
+ switch (yytext[strlen(yytext) - 1])
+ {
+ case 'G':
+ mult = 1024 * 1024 * 1024;
+ break;
+ case 'M':
+ mult = 1024 * 1024;
+ break;
+ case 'K':
+ mult = 1024;
+ break;
+ default:
+ mult = 1;
+ break;
+ }
+
+ // set resulting symbol value
+ m_symbolValue.m_int = new elftosb::SizedIntegerValue(value * mult, kWordSize);
+ return TOK_INT_LITERAL;
+ }
+
+\'(.|ESC)\'|\'(.|ESC){2}\'|\'(.|ESC){4}\' {
+ uint32_t value = 0;
+ int_size_t theSize;
+ int len = strlen(yytext);
+ if (len >= 3)
+ {
+ value = yytext[1];
+ theSize = kByteSize;
+ }
+ if (len >= 4)
+ {
+ value = (value << 8) | yytext[2];
+ theSize = kHalfWordSize;
+ }
+ if (len >= 6)
+ {
+ value = (value << 8) | yytext[3];
+ value = (value << 8) | yytext[4];
+ theSize = kWordSize;
+ }
+ m_symbolValue.m_int = new elftosb::SizedIntegerValue(value, theSize);
+ return TOK_INT_LITERAL;
+ }
+
+\$[\.\*a-zA-Z0-9_\[\]\^\?\-]+ {
+ // remove $ from string
+ m_symbolValue.m_str = new std::string(&yytext[1]);
+ return TOK_SECTION_NAME;
+ }
+
+
+"/*" { BEGIN(mlcmt); }
+
+"{{" {
+ m_blob = new Blob();
+ m_blobFirstLine = yylineno;
+ BEGIN(blob);
+ }
+
+"{" { return '{'; }
+
+"}" { return '}'; }
+
+"(" { return '('; }
+
+")" { return ')'; }
+
+"[" { return '['; }
+
+"]" { return ']'; }
+
+"=" { return '='; }
+
+"," { return ','; }
+
+":" { return ':'; }
+
+";" { return ';'; }
+
+"." { return '.'; }
+
+">" { return '>'; }
+
+".." { return TOK_DOT_DOT; }
+
+"+" { return '+'; }
+
+"-" { return '-'; }
+
+"*" { return '*'; }
+
+"/" { return '/'; }
+
+"%" { return '%'; }
+
+"~" { return '~'; }
+
+"^" { return '^'; }
+
+"<<" { return TOK_LSHIFT; }
+
+">>" { return TOK_RSHIFT; }
+
+"&" { return '&'; }
+
+"|" { return '|'; }
+
+"**" { return TOK_POWER; }
+
+"<" { return '<'; }
+
+">=" { return TOK_GEQ; }
+
+"<=" { return TOK_LEQ; }
+
+"==" { return TOK_EQ; }
+
+"!=" { return TOK_NEQ; }
+
+"&&" { return TOK_AND; }
+
+"||" { return TOK_OR; }
+
+"!" { return '!'; }
+
+\"(ESC|[^\"])*\" {
+ // get rid of quotes
+ yytext++;
+ yytext[strlen(yytext) - 1] = 0;
+// processStringEscapes(yytext, yytext);
+ m_symbolValue.m_str = new std::string(yytext);
+ return TOK_STRING_LITERAL;
+ }
+
+<blob>{HEXDIGIT}{2} {
+ uint8_t x = (hexCharToInt(yytext[0]) << 4) | hexCharToInt(yytext[1]);
+ m_blob->append(&x, 1);
+ }
+
+<blob>"}}" {
+ BEGIN(INITIAL);
+ m_symbolValue.m_blob = m_blob;
+ m_blob = NULL;
+ m_location.m_firstLine = m_blobFirstLine;
+ return TOK_BLOB;
+ }
+
+<mlcmt>\*\/ {
+ // end of multi-line comment, return to initial state
+ BEGIN(INITIAL);
+ }
+
+
+(#|\/\/).*$ /* absorb single-line comment */
+
+<*>[ \t] /* eat up whitespace in all states */
+
+<*>(\r\n|\r|\n) {
+ /* eat up whitespace and count lines in all states */
+ m_line++;
+ }
+
+<mlcmt>. /* ignore all other chars in a multi-line comment */
+
+<*>. {
+ /* all other chars produce errors */
+ char msg[50];
+ sprintf(msg, "unexpected character '%c' on line %d", yytext[0], m_line);
+ LexerError(msg);
+ }
+
+%%
+
+// verbatim code copied to the bottom of the output
+
+
--- /dev/null
+/* A Bison parser, made by GNU Bison 2.1. */
+
+/* Skeleton parser for Yacc-like parsing with Bison,
+ Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+/* As a special exception, when this file is copied by Bison into a
+ Bison output file, you may use that output file without restriction.
+ This special exception was added by the Free Software Foundation
+ in version 1.24 of Bison. */
+
+/* Written by Richard Stallman by simplifying the original so called
+ ``semantic'' parser. */
+
+/* All symbols defined below should begin with yy or YY, to avoid
+ infringing on user name space. This should be done even for local
+ variables, as they might otherwise be expanded by user macros.
+ There are some unavoidable exceptions within include files to
+ define necessary library symbols; they are noted "INFRINGES ON
+ USER NAME SPACE" below. */
+
+/* Identify Bison output. */
+#define YYBISON 1
+
+/* Bison version. */
+#define YYBISON_VERSION "2.1"
+
+/* Skeleton name. */
+#define YYSKELETON_NAME "yacc.c"
+
+/* Pure parsers. */
+#define YYPURE 1
+
+/* Using locations. */
+#define YYLSP_NEEDED 1
+
+
+
+/* Tokens. */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+ /* Put the tokens into the symbol table, so that GDB and other debuggers
+ know about them. */
+ enum yytokentype {
+ TOK_IDENT = 258,
+ TOK_STRING_LITERAL = 259,
+ TOK_INT_LITERAL = 260,
+ TOK_SECTION_NAME = 261,
+ TOK_SOURCE_NAME = 262,
+ TOK_BLOB = 263,
+ TOK_DOT_DOT = 264,
+ TOK_AND = 265,
+ TOK_OR = 266,
+ TOK_GEQ = 267,
+ TOK_LEQ = 268,
+ TOK_EQ = 269,
+ TOK_NEQ = 270,
+ TOK_POWER = 271,
+ TOK_LSHIFT = 272,
+ TOK_RSHIFT = 273,
+ TOK_INT_SIZE = 274,
+ TOK_OPTIONS = 275,
+ TOK_CONSTANTS = 276,
+ TOK_SOURCES = 277,
+ TOK_FILTERS = 278,
+ TOK_SECTION = 279,
+ TOK_EXTERN = 280,
+ TOK_FROM = 281,
+ TOK_RAW = 282,
+ TOK_LOAD = 283,
+ TOK_JUMP = 284,
+ TOK_CALL = 285,
+ TOK_MODE = 286,
+ TOK_IF = 287,
+ TOK_ELSE = 288,
+ TOK_DEFINED = 289,
+ TOK_INFO = 290,
+ TOK_WARNING = 291,
+ TOK_ERROR = 292,
+ TOK_SIZEOF = 293,
+ TOK_DCD = 294,
+ TOK_HAB = 295,
+ TOK_IVT = 296,
+ UNARY_OP = 297
+ };
+#endif
+/* Tokens. */
+#define TOK_IDENT 258
+#define TOK_STRING_LITERAL 259
+#define TOK_INT_LITERAL 260
+#define TOK_SECTION_NAME 261
+#define TOK_SOURCE_NAME 262
+#define TOK_BLOB 263
+#define TOK_DOT_DOT 264
+#define TOK_AND 265
+#define TOK_OR 266
+#define TOK_GEQ 267
+#define TOK_LEQ 268
+#define TOK_EQ 269
+#define TOK_NEQ 270
+#define TOK_POWER 271
+#define TOK_LSHIFT 272
+#define TOK_RSHIFT 273
+#define TOK_INT_SIZE 274
+#define TOK_OPTIONS 275
+#define TOK_CONSTANTS 276
+#define TOK_SOURCES 277
+#define TOK_FILTERS 278
+#define TOK_SECTION 279
+#define TOK_EXTERN 280
+#define TOK_FROM 281
+#define TOK_RAW 282
+#define TOK_LOAD 283
+#define TOK_JUMP 284
+#define TOK_CALL 285
+#define TOK_MODE 286
+#define TOK_IF 287
+#define TOK_ELSE 288
+#define TOK_DEFINED 289
+#define TOK_INFO 290
+#define TOK_WARNING 291
+#define TOK_ERROR 292
+#define TOK_SIZEOF 293
+#define TOK_DCD 294
+#define TOK_HAB 295
+#define TOK_IVT 296
+#define UNARY_OP 297
+
+
+
+
+/* Copy the first part of user declarations. */
+#line 14 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+
+#include "ElftosbLexer.h"
+#include "ElftosbAST.h"
+#include "Logging.h"
+#include "Blob.h"
+#include "format_string.h"
+#include "Value.h"
+#include "ConversionController.h"
+
+using namespace elftosb;
+
+//! Our special location type.
+#define YYLTYPE token_loc_t
+
+// this indicates that we're using our own type. it should be unset automatically
+// but that's not working for some reason with the .hpp file.
+#if defined(YYLTYPE_IS_TRIVIAL)
+ #undef YYLTYPE_IS_TRIVIAL
+ #define YYLTYPE_IS_TRIVIAL 0
+#endif
+
+//! Default location action
+#define YYLLOC_DEFAULT(Current, Rhs, N) \
+ do { \
+ if (N) \
+ { \
+ (Current).m_firstLine = YYRHSLOC(Rhs, 1).m_firstLine; \
+ (Current).m_lastLine = YYRHSLOC(Rhs, N).m_lastLine; \
+ } \
+ else \
+ { \
+ (Current).m_firstLine = (Current).m_lastLine = YYRHSLOC(Rhs, 0).m_lastLine; \
+ } \
+ } while (0)
+
+//! Forward declaration of yylex().
+static int yylex(YYSTYPE * lvalp, YYLTYPE * yylloc, ElftosbLexer * lexer);
+
+// Forward declaration of error handling function.
+static void yyerror(YYLTYPE * yylloc, ElftosbLexer * lexer, CommandFileASTNode ** resultAST, const char * error);
+
+
+
+/* Enabling traces. */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+
+/* Enabling verbose error messages. */
+#ifdef YYERROR_VERBOSE
+# undef YYERROR_VERBOSE
+# define YYERROR_VERBOSE 1
+#else
+# define YYERROR_VERBOSE 1
+#endif
+
+/* Enabling the token table. */
+#ifndef YYTOKEN_TABLE
+# define YYTOKEN_TABLE 0
+#endif
+
+#if ! defined (YYSTYPE) && ! defined (YYSTYPE_IS_DECLARED)
+#line 58 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+typedef union YYSTYPE {
+ int m_num;
+ elftosb::SizedIntegerValue * m_int;
+ Blob * m_blob;
+ std::string * m_str;
+ elftosb::ASTNode * m_ast; // must use full name here because this is put into *.tab.hpp
+} YYSTYPE;
+/* Line 196 of yacc.c. */
+#line 220 "/Users/creed/projects/fsl/fromsvr/elftosb/build/elftosb.build/Debug/elftosb.build/DerivedSources/elftosb_parser.tab.cpp"
+# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+# define YYSTYPE_IS_DECLARED 1
+# define YYSTYPE_IS_TRIVIAL 1
+#endif
+
+#if ! defined (YYLTYPE) && ! defined (YYLTYPE_IS_DECLARED)
+typedef struct YYLTYPE
+{
+ int first_line;
+ int first_column;
+ int last_line;
+ int last_column;
+} YYLTYPE;
+# define yyltype YYLTYPE /* obsolescent; will be withdrawn */
+# define YYLTYPE_IS_DECLARED 1
+# define YYLTYPE_IS_TRIVIAL 1
+#endif
+
+
+/* Copy the second part of user declarations. */
+
+
+/* Line 219 of yacc.c. */
+#line 244 "/Users/creed/projects/fsl/fromsvr/elftosb/build/elftosb.build/Debug/elftosb.build/DerivedSources/elftosb_parser.tab.cpp"
+
+#if ! defined (YYSIZE_T) && defined (__SIZE_TYPE__)
+# define YYSIZE_T __SIZE_TYPE__
+#endif
+#if ! defined (YYSIZE_T) && defined (size_t)
+# define YYSIZE_T size_t
+#endif
+#if ! defined (YYSIZE_T) && (defined (__STDC__) || defined (__cplusplus))
+# include <stddef.h> /* INFRINGES ON USER NAME SPACE */
+# define YYSIZE_T size_t
+#endif
+#if ! defined (YYSIZE_T)
+# define YYSIZE_T unsigned int
+#endif
+
+#ifndef YY_
+# if YYENABLE_NLS
+# if ENABLE_NLS
+# include <libintl.h> /* INFRINGES ON USER NAME SPACE */
+# define YY_(msgid) dgettext ("bison-runtime", msgid)
+# endif
+# endif
+# ifndef YY_
+# define YY_(msgid) msgid
+# endif
+#endif
+
+#if ! defined (yyoverflow) || YYERROR_VERBOSE
+
+/* The parser invokes alloca or malloc; define the necessary symbols. */
+
+# ifdef YYSTACK_USE_ALLOCA
+# if YYSTACK_USE_ALLOCA
+# ifdef __GNUC__
+# define YYSTACK_ALLOC __builtin_alloca
+# else
+# define YYSTACK_ALLOC alloca
+# if defined (__STDC__) || defined (__cplusplus)
+# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+# define YYINCLUDED_STDLIB_H
+# endif
+# endif
+# endif
+# endif
+
+# ifdef YYSTACK_ALLOC
+ /* Pacify GCC's `empty if-body' warning. */
+# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
+# ifndef YYSTACK_ALLOC_MAXIMUM
+ /* The OS might guarantee only one guard page at the bottom of the stack,
+ and a page size can be as small as 4096 bytes. So we cannot safely
+ invoke alloca (N) if N exceeds 4096. Use a slightly smaller number
+ to allow for a few compiler-allocated temporary stack slots. */
+# define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2005 */
+# endif
+# else
+# define YYSTACK_ALLOC YYMALLOC
+# define YYSTACK_FREE YYFREE
+# ifndef YYSTACK_ALLOC_MAXIMUM
+# define YYSTACK_ALLOC_MAXIMUM ((YYSIZE_T) -1)
+# endif
+# ifdef __cplusplus
+extern "C" {
+# endif
+# ifndef YYMALLOC
+# define YYMALLOC malloc
+# if (! defined (malloc) && ! defined (YYINCLUDED_STDLIB_H) \
+ && (defined (__STDC__) || defined (__cplusplus)))
+void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
+# endif
+# endif
+# ifndef YYFREE
+# define YYFREE free
+# if (! defined (free) && ! defined (YYINCLUDED_STDLIB_H) \
+ && (defined (__STDC__) || defined (__cplusplus)))
+void free (void *); /* INFRINGES ON USER NAME SPACE */
+# endif
+# endif
+# ifdef __cplusplus
+}
+# endif
+# endif
+#endif /* ! defined (yyoverflow) || YYERROR_VERBOSE */
+
+
+#if (! defined (yyoverflow) \
+ && (! defined (__cplusplus) \
+ || (defined (YYLTYPE_IS_TRIVIAL) && YYLTYPE_IS_TRIVIAL \
+ && defined (YYSTYPE_IS_TRIVIAL) && YYSTYPE_IS_TRIVIAL)))
+
+/* A type that is properly aligned for any stack member. */
+union yyalloc
+{
+ short int yyss;
+ YYSTYPE yyvs;
+ YYLTYPE yyls;
+};
+
+/* The size of the maximum gap between one aligned stack and the next. */
+# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
+
+/* The size of an array large to enough to hold all stacks, each with
+ N elements. */
+# define YYSTACK_BYTES(N) \
+ ((N) * (sizeof (short int) + sizeof (YYSTYPE) + sizeof (YYLTYPE)) \
+ + 2 * YYSTACK_GAP_MAXIMUM)
+
+/* Copy COUNT objects from FROM to TO. The source and destination do
+ not overlap. */
+# ifndef YYCOPY
+# if defined (__GNUC__) && 1 < __GNUC__
+# define YYCOPY(To, From, Count) \
+ __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
+# else
+# define YYCOPY(To, From, Count) \
+ do \
+ { \
+ YYSIZE_T yyi; \
+ for (yyi = 0; yyi < (Count); yyi++) \
+ (To)[yyi] = (From)[yyi]; \
+ } \
+ while (0)
+# endif
+# endif
+
+/* Relocate STACK from its old location to the new one. The
+ local variables YYSIZE and YYSTACKSIZE give the old and new number of
+ elements in the stack, and YYPTR gives the new location of the
+ stack. Advance YYPTR to a properly aligned location for the next
+ stack. */
+# define YYSTACK_RELOCATE(Stack) \
+ do \
+ { \
+ YYSIZE_T yynewbytes; \
+ YYCOPY (&yyptr->Stack, Stack, yysize); \
+ Stack = &yyptr->Stack; \
+ yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
+ yyptr += yynewbytes / sizeof (*yyptr); \
+ } \
+ while (0)
+
+#endif
+
+#if defined (__STDC__) || defined (__cplusplus)
+ typedef signed char yysigned_char;
+#else
+ typedef short int yysigned_char;
+#endif
+
+/* YYFINAL -- State number of the termination state. */
+#define YYFINAL 13
+/* YYLAST -- Last index in YYTABLE. */
+#define YYLAST 418
+
+/* YYNTOKENS -- Number of terminals. */
+#define YYNTOKENS 66
+/* YYNNTS -- Number of nonterminals. */
+#define YYNNTS 52
+/* YYNRULES -- Number of rules. */
+#define YYNRULES 133
+/* YYNRULES -- Number of states. */
+#define YYNSTATES 238
+
+/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */
+#define YYUNDEFTOK 2
+#define YYMAXUTOK 297
+
+#define YYTRANSLATE(YYX) \
+ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
+
+/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX. */
+static const unsigned char yytranslate[] =
+{
+ 0, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 26, 2, 2, 2, 64, 23, 2,
+ 9, 10, 62, 60, 16, 61, 20, 63, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 18, 17,
+ 25, 15, 19, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 13, 2, 14, 59, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 11, 24, 12, 22, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 1, 2, 3, 4,
+ 5, 6, 7, 8, 21, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
+ 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
+ 52, 53, 54, 55, 56, 57, 58, 65
+};
+
+#if YYDEBUG
+/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in
+ YYRHS. */
+static const unsigned short int yyprhs[] =
+{
+ 0, 0, 3, 6, 8, 11, 13, 15, 17, 22,
+ 27, 29, 32, 35, 36, 40, 45, 47, 50, 54,
+ 55, 59, 66, 70, 71, 73, 77, 81, 83, 86,
+ 93, 96, 97, 99, 100, 104, 108, 110, 113, 116,
+ 118, 120, 121, 123, 126, 129, 131, 132, 134, 136,
+ 138, 140, 145, 147, 148, 150, 152, 154, 156, 160,
+ 165, 167, 169, 171, 175, 177, 180, 183, 184, 186,
+ 188, 193, 195, 196, 200, 205, 207, 209, 211, 213,
+ 217, 220, 221, 227, 230, 233, 236, 239, 246, 251,
+ 254, 255, 257, 261, 263, 265, 267, 271, 275, 279,
+ 283, 287, 291, 295, 299, 302, 307, 311, 316, 318,
+ 322, 325, 327, 329, 331, 335, 339, 343, 347, 351,
+ 355, 359, 363, 367, 371, 375, 377, 381, 385, 390,
+ 395, 400, 403, 406
+};
+
+/* YYRHS -- A `-1'-separated list of the rules' RHS. */
+static const yysigned_char yyrhs[] =
+{
+ 67, 0, -1, 68, 82, -1, 69, -1, 68, 69,
+ -1, 70, -1, 71, -1, 75, -1, 37, 11, 72,
+ 12, -1, 38, 11, 72, 12, -1, 73, -1, 72,
+ 73, -1, 74, 17, -1, -1, 3, 15, 111, -1,
+ 39, 11, 76, 12, -1, 77, -1, 76, 77, -1,
+ 78, 79, 17, -1, -1, 3, 15, 4, -1, 3,
+ 15, 42, 9, 113, 10, -1, 9, 80, 10, -1,
+ -1, 81, -1, 80, 16, 81, -1, 3, 15, 111,
+ -1, 83, -1, 82, 83, -1, 41, 9, 113, 84,
+ 10, 86, -1, 17, 85, -1, -1, 80, -1, -1,
+ 30, 94, 17, -1, 11, 87, 12, -1, 88, -1,
+ 87, 88, -1, 91, 17, -1, 105, -1, 108, -1,
+ -1, 90, -1, 89, 90, -1, 91, 17, -1, 108,
+ -1, -1, 92, -1, 101, -1, 106, -1, 107, -1,
+ 45, 93, 94, 97, -1, 56, -1, -1, 113, -1,
+ 4, -1, 7, -1, 95, -1, 95, 43, 7, -1,
+ 7, 13, 95, 14, -1, 8, -1, 99, -1, 96,
+ -1, 95, 16, 96, -1, 6, -1, 22, 6, -1,
+ 19, 98, -1, -1, 20, -1, 110, -1, 58, 9,
+ 100, 10, -1, 80, -1, -1, 102, 103, 104, -1,
+ 57, 102, 110, 104, -1, 47, -1, 46, -1, 7,
+ -1, 113, -1, 9, 113, 10, -1, 9, 10, -1,
+ -1, 43, 7, 11, 89, 12, -1, 48, 113, -1,
+ 52, 4, -1, 53, 4, -1, 54, 4, -1, 49,
+ 112, 11, 87, 12, 109, -1, 50, 11, 87, 12,
+ -1, 50, 108, -1, -1, 113, -1, 113, 21, 113,
+ -1, 112, -1, 4, -1, 113, -1, 112, 25, 112,
+ -1, 112, 19, 112, -1, 112, 29, 112, -1, 112,
+ 30, 112, -1, 112, 31, 112, -1, 112, 32, 112,
+ -1, 112, 27, 112, -1, 112, 28, 112, -1, 26,
+ 112, -1, 3, 9, 7, 10, -1, 9, 112, 10,
+ -1, 51, 9, 3, 10, -1, 115, -1, 7, 18,
+ 3, -1, 18, 3, -1, 117, -1, 3, -1, 114,
+ -1, 115, 60, 115, -1, 115, 61, 115, -1, 115,
+ 62, 115, -1, 115, 63, 115, -1, 115, 64, 115,
+ -1, 115, 33, 115, -1, 115, 23, 115, -1, 115,
+ 24, 115, -1, 115, 59, 115, -1, 115, 34, 115,
+ -1, 115, 35, 115, -1, 116, -1, 115, 20, 36,
+ -1, 9, 115, 10, -1, 55, 9, 114, 10, -1,
+ 55, 9, 3, 10, -1, 55, 9, 7, 10, -1,
+ 60, 115, -1, 61, 115, -1, 5, -1
+};
+
+/* YYRLINE[YYN] -- source line where rule number YYN was defined. */
+static const unsigned short int yyrline[] =
+{
+ 0, 162, 162, 172, 178, 186, 187, 188, 191, 197,
+ 203, 209, 216, 217, 220, 227, 233, 239, 247, 259,
+ 262, 267, 275, 276, 280, 286, 294, 301, 307, 314,
+ 329, 334, 340, 345, 351, 357, 365, 371, 379, 380,
+ 381, 382, 385, 391, 399, 400, 401, 404, 405, 406,
+ 407, 410, 433, 443, 445, 449, 454, 459, 464, 469,
+ 474, 479, 484, 490, 498, 503, 510, 515, 521, 526,
+ 532, 544, 545, 548, 577, 614, 615, 618, 623, 630,
+ 631, 632, 635, 642, 649, 654, 659, 666, 677, 681,
+ 688, 691, 696, 703, 707, 714, 718, 725, 732, 739,
+ 746, 753, 760, 767, 774, 779, 784, 789, 796, 799,
+ 804, 812, 816, 821, 832, 839, 846, 853, 860, 867,
+ 874, 881, 888, 895, 902, 909, 913, 918, 923, 928,
+ 933, 940, 944, 951
+};
+#endif
+
+#if YYDEBUG || YYERROR_VERBOSE || YYTOKEN_TABLE
+/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
+ First, the terminals, then, starting at YYNTOKENS, nonterminals. */
+static const char *const yytname[] =
+{
+ "$end", "error", "$undefined", "\"identifier\"", "\"string\"",
+ "\"integer\"", "\"section name\"", "\"source name\"",
+ "\"binary object\"", "'('", "')'", "'{'", "'}'", "'['", "']'", "'='",
+ "','", "';'", "':'", "'>'", "'.'", "\"..\"", "'~'", "'&'", "'|'", "'<'",
+ "'!'", "\"&&\"", "\"||\"", "\">=\"", "\"<=\"", "\"==\"", "\"!=\"",
+ "\"**\"", "\"<<\"", "\">>\"", "\"integer size\"", "\"options\"",
+ "\"constants\"", "\"sources\"", "\"filters\"", "\"section\"",
+ "\"extern\"", "\"from\"", "\"raw\"", "\"load\"", "\"jump\"", "\"call\"",
+ "\"mode\"", "\"if\"", "\"else\"", "\"defined\"", "\"info\"",
+ "\"warning\"", "\"error\"", "\"sizeof\"", "\"dcd\"", "\"hab\"",
+ "\"ivt\"", "'^'", "'+'", "'-'", "'*'", "'/'", "'%'", "UNARY_OP",
+ "$accept", "command_file", "blocks_list", "pre_section_block",
+ "options_block", "constants_block", "const_def_list",
+ "const_def_list_elem", "const_def", "sources_block", "source_def_list",
+ "source_def_list_elem", "source_def", "source_attrs_opt",
+ "source_attr_list", "source_attr_list_elem", "section_defs",
+ "section_def", "section_options_opt", "source_attr_list_opt",
+ "section_contents", "full_stmt_list", "full_stmt_list_elem",
+ "basic_stmt_list", "basic_stmt_list_elem", "basic_stmt", "load_stmt",
+ "dcd_opt", "load_data", "section_list", "section_list_elem",
+ "load_target_opt", "load_target", "ivt_def", "assignment_list_opt",
+ "call_stmt", "call_or_jump", "call_target", "call_arg_opt", "from_stmt",
+ "mode_stmt", "message_stmt", "if_stmt", "else_opt", "address_or_range",
+ "const_expr", "bool_expr", "int_const_expr", "symbol_ref", "expr",
+ "unary_expr", "int_value", 0
+};
+#endif
+
+# ifdef YYPRINT
+/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to
+ token YYLEX-NUM. */
+static const unsigned short int yytoknum[] =
+{
+ 0, 256, 257, 258, 259, 260, 261, 262, 263, 40,
+ 41, 123, 125, 91, 93, 61, 44, 59, 58, 62,
+ 46, 264, 126, 38, 124, 60, 33, 265, 266, 267,
+ 268, 269, 270, 271, 272, 273, 274, 275, 276, 277,
+ 278, 279, 280, 281, 282, 283, 284, 285, 286, 287,
+ 288, 289, 290, 291, 292, 293, 294, 295, 296, 94,
+ 43, 45, 42, 47, 37, 297
+};
+# endif
+
+/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
+static const unsigned char yyr1[] =
+{
+ 0, 66, 67, 68, 68, 69, 69, 69, 70, 71,
+ 72, 72, 73, 73, 74, 75, 76, 76, 77, 77,
+ 78, 78, 79, 79, 80, 80, 81, 82, 82, 83,
+ 84, 84, 85, 85, 86, 86, 87, 87, 88, 88,
+ 88, 88, 89, 89, 90, 90, 90, 91, 91, 91,
+ 91, 92, 93, 93, 94, 94, 94, 94, 94, 94,
+ 94, 94, 95, 95, 96, 96, 97, 97, 98, 98,
+ 99, 100, 100, 101, 101, 102, 102, 103, 103, 104,
+ 104, 104, 105, 106, 107, 107, 107, 108, 109, 109,
+ 109, 110, 110, 111, 111, 112, 112, 112, 112, 112,
+ 112, 112, 112, 112, 112, 112, 112, 112, 113, 114,
+ 114, 115, 115, 115, 115, 115, 115, 115, 115, 115,
+ 115, 115, 115, 115, 115, 115, 115, 115, 115, 115,
+ 115, 116, 116, 117
+};
+
+/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */
+static const unsigned char yyr2[] =
+{
+ 0, 2, 2, 1, 2, 1, 1, 1, 4, 4,
+ 1, 2, 2, 0, 3, 4, 1, 2, 3, 0,
+ 3, 6, 3, 0, 1, 3, 3, 1, 2, 6,
+ 2, 0, 1, 0, 3, 3, 1, 2, 2, 1,
+ 1, 0, 1, 2, 2, 1, 0, 1, 1, 1,
+ 1, 4, 1, 0, 1, 1, 1, 1, 3, 4,
+ 1, 1, 1, 3, 1, 2, 2, 0, 1, 1,
+ 4, 1, 0, 3, 4, 1, 1, 1, 1, 3,
+ 2, 0, 5, 2, 2, 2, 2, 6, 4, 2,
+ 0, 1, 3, 1, 1, 1, 3, 3, 3, 3,
+ 3, 3, 3, 3, 2, 4, 3, 4, 1, 3,
+ 2, 1, 1, 1, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 3, 3, 1, 3, 3, 4, 4,
+ 4, 2, 2, 1
+};
+
+/* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
+ STATE-NUM when YYTABLE doesn't specify something else to do. Zero
+ means the default is an error. */
+static const unsigned char yydefact[] =
+{
+ 0, 0, 0, 0, 0, 0, 3, 5, 6, 7,
+ 13, 13, 19, 1, 0, 4, 2, 27, 0, 0,
+ 10, 0, 0, 0, 0, 16, 23, 0, 28, 0,
+ 8, 11, 12, 9, 0, 15, 17, 0, 0, 112,
+ 133, 0, 0, 0, 0, 0, 0, 31, 113, 108,
+ 125, 111, 112, 94, 0, 0, 0, 14, 93, 95,
+ 20, 0, 0, 0, 24, 18, 0, 0, 110, 0,
+ 131, 132, 33, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 108, 104,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 22, 0, 109, 127, 0, 0, 0, 32, 30,
+ 0, 126, 120, 121, 119, 123, 124, 122, 114, 115,
+ 116, 117, 118, 0, 106, 0, 97, 96, 102, 103,
+ 98, 99, 100, 101, 0, 26, 25, 129, 130, 128,
+ 41, 0, 29, 105, 107, 21, 0, 53, 76, 75,
+ 0, 0, 0, 0, 0, 0, 0, 36, 0, 47,
+ 48, 0, 39, 49, 50, 40, 55, 64, 56, 60,
+ 0, 0, 0, 57, 62, 61, 54, 0, 52, 0,
+ 83, 0, 84, 85, 86, 0, 35, 37, 38, 77,
+ 81, 78, 0, 65, 72, 34, 0, 0, 46, 67,
+ 41, 81, 91, 0, 73, 0, 71, 0, 63, 58,
+ 0, 42, 0, 45, 0, 51, 0, 74, 0, 80,
+ 0, 59, 70, 82, 43, 44, 68, 66, 69, 90,
+ 92, 79, 0, 87, 41, 89, 0, 88
+};
+
+/* YYDEFGOTO[NTERM-NUM]. */
+static const short int yydefgoto[] =
+{
+ -1, 4, 5, 6, 7, 8, 19, 20, 21, 9,
+ 24, 25, 26, 38, 63, 64, 16, 17, 73, 109,
+ 142, 156, 157, 210, 211, 158, 159, 179, 172, 173,
+ 174, 215, 227, 175, 207, 160, 161, 190, 204, 162,
+ 163, 164, 165, 233, 201, 57, 58, 59, 48, 49,
+ 50, 51
+};
+
+/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
+ STATE-NUM. */
+#define YYPACT_NINF -181
+static const short int yypact[] =
+{
+ 128, 17, 25, 48, 69, 123, -181, -181, -181, -181,
+ 96, 96, 101, -181, 80, -181, 68, -181, 112, 85,
+ -181, 115, 89, 114, 91, -181, 124, 30, -181, 47,
+ -181, -181, -181, -181, 11, -181, -181, 134, 125, -181,
+ -181, 133, 30, 140, 144, 30, 30, 153, -181, 225,
+ -181, -181, 148, -181, 61, 61, 162, -181, 359, -181,
+ -181, 164, 159, 22, -181, -181, 172, 121, -181, 9,
+ -181, -181, 134, 168, 143, 30, 30, 30, 30, 30,
+ 30, 30, 30, 30, 30, 30, 179, 303, 121, -181,
+ 194, 61, 61, 61, 61, 61, 61, 61, 61, 30,
+ 47, -181, 134, -181, -181, 188, 4, 200, 199, -181,
+ 56, -181, 241, 231, 236, 86, 86, 247, 76, 76,
+ 196, 196, 196, 208, -181, 210, -181, -181, 373, 373,
+ -181, -181, -181, -181, 216, -181, -181, -181, -181, -181,
+ 314, 2, -181, -181, -181, -181, 220, 175, -181, -181,
+ 30, 61, 228, 230, 237, 28, 147, -181, 223, -181,
+ -181, 108, -181, -181, -181, -181, -181, -181, 92, -181,
+ 240, 243, 233, 15, -181, -181, -181, 242, -181, 2,
+ -181, 345, -181, -181, -181, 30, -181, -181, -181, 133,
+ 246, -181, 7, -181, 134, -181, 7, 250, 361, 244,
+ 314, 246, 248, 16, -181, 104, 199, 252, -181, -181,
+ 190, -181, 251, -181, 75, -181, 160, -181, 30, -181,
+ 261, -181, -181, -181, -181, -181, -181, -181, -181, 222,
+ -181, -181, 6, -181, 314, -181, 176, -181
+};
+
+/* YYPGOTO[NTERM-NUM]. */
+static const short int yypgoto[] =
+{
+ -181, -181, -181, 268, -181, -181, 266, 106, -181, -181,
+ -181, 254, -181, -181, -70, 177, -181, 267, -181, -181,
+ -181, -151, -155, -181, 107, -180, -181, -181, 127, 122,
+ 129, -181, -181, -181, -181, -181, 163, -181, 118, -181,
+ -181, -181, -21, -181, 109, 221, -51, -27, 257, 270,
+ -181, -181
+};
+
+/* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If
+ positive, shift that token. If negative, reduce the rule which
+ number is the opposite. If zero, do what YYDEFACT says.
+ If YYTABLE_NINF, syntax error. */
+#define YYTABLE_NINF -1
+static const unsigned char yytable[] =
+{
+ 47, 187, 108, 87, 89, 39, 166, 40, 167, 168,
+ 169, 42, 105, 167, 138, 60, 106, 234, 212, 39,
+ 43, 40, 66, 41, 170, 42, 219, 43, 10, 170,
+ 212, 196, 101, 39, 43, 40, 11, 41, 102, 42,
+ 126, 127, 128, 129, 130, 131, 132, 133, 43, 216,
+ 52, 53, 40, 61, 41, 151, 54, 44, 197, 12,
+ 171, 187, 45, 46, 52, 43, 40, 140, 41, 13,
+ 54, 44, 134, 55, 148, 149, 45, 46, 39, 43,
+ 40, 187, 41, 236, 42, 44, 141, 55, 18, 27,
+ 45, 46, 18, 43, 23, 226, 74, 30, 56, 18,
+ 181, 33, 44, 35, 23, 192, 74, 45, 46, 14,
+ 66, 39, 56, 40, 176, 189, 44, 42, 221, 77,
+ 196, 45, 46, 180, 206, 31, 43, 29, 31, 34,
+ 44, 104, 32, 37, 191, 45, 46, 62, 83, 84,
+ 85, 74, 65, 68, 75, 76, 81, 82, 83, 84,
+ 85, 66, 176, 69, 77, 78, 79, 86, 202, 186,
+ 1, 2, 3, 44, 14, 1, 2, 3, 45, 46,
+ 72, 90, 229, 99, 100, 103, 220, 213, 110, 111,
+ 80, 81, 82, 83, 84, 85, 123, 202, 237, 213,
+ 146, 230, 147, 148, 149, 150, 151, 125, 137, 152,
+ 153, 154, 223, 146, 155, 147, 148, 149, 150, 151,
+ 139, 235, 152, 153, 154, 102, 74, 155, 143, 146,
+ 144, 147, 148, 149, 150, 151, 145, 177, 152, 153,
+ 154, 178, 182, 155, 183, 147, 148, 149, 150, 151,
+ 188, 184, 152, 153, 154, 74, 193, 155, 75, 76,
+ 195, 74, 194, 198, 75, 203, 74, 209, 77, 78,
+ 79, 74, 222, 214, 77, 78, 79, 74, 225, 218,
+ 75, 231, 232, 15, 77, 78, 79, 22, 36, 136,
+ 77, 78, 79, 28, 80, 81, 82, 83, 84, 85,
+ 80, 81, 82, 83, 84, 85, 81, 82, 83, 84,
+ 85, 81, 82, 83, 84, 85, 199, 81, 82, 83,
+ 84, 85, 67, 124, 205, 70, 71, 224, 185, 217,
+ 0, 135, 91, 228, 88, 208, 107, 0, 92, 0,
+ 93, 94, 95, 96, 97, 98, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 112, 113, 114, 115, 116,
+ 117, 118, 119, 120, 121, 122, 200, 146, 0, 147,
+ 148, 149, 150, 151, 91, 0, 152, 153, 154, 0,
+ 92, 155, 93, 94, 95, 96, 97, 98, 91, 0,
+ 0, 0, 0, 0, 92, 0, 93, 94, 95, 96,
+ 97, 98, 91, 0, 0, 0, 0, 0, 92, 0,
+ 0, 0, 95, 96, 97, 98, 147, 148, 149, 150,
+ 151, 0, 0, 152, 153, 154, 0, 0, 155
+};
+
+static const short int yycheck[] =
+{
+ 27, 156, 72, 54, 55, 3, 4, 5, 6, 7,
+ 8, 9, 3, 6, 10, 4, 7, 11, 198, 3,
+ 18, 5, 18, 7, 22, 9, 10, 18, 11, 22,
+ 210, 16, 10, 3, 18, 5, 11, 7, 16, 9,
+ 91, 92, 93, 94, 95, 96, 97, 98, 18, 200,
+ 3, 4, 5, 42, 7, 49, 9, 55, 43, 11,
+ 58, 216, 60, 61, 3, 18, 5, 11, 7, 0,
+ 9, 55, 99, 26, 46, 47, 60, 61, 3, 18,
+ 5, 236, 7, 234, 9, 55, 30, 26, 3, 9,
+ 60, 61, 3, 18, 3, 20, 20, 12, 51, 3,
+ 151, 12, 55, 12, 3, 13, 20, 60, 61, 41,
+ 18, 3, 51, 5, 141, 7, 55, 9, 14, 33,
+ 16, 60, 61, 150, 194, 19, 18, 15, 22, 15,
+ 55, 10, 17, 9, 161, 60, 61, 3, 62, 63,
+ 64, 20, 17, 3, 23, 24, 60, 61, 62, 63,
+ 64, 18, 179, 9, 33, 34, 35, 9, 185, 12,
+ 37, 38, 39, 55, 41, 37, 38, 39, 60, 61,
+ 17, 9, 12, 9, 15, 3, 203, 198, 10, 36,
+ 59, 60, 61, 62, 63, 64, 7, 214, 12, 210,
+ 43, 218, 45, 46, 47, 48, 49, 3, 10, 52,
+ 53, 54, 12, 43, 57, 45, 46, 47, 48, 49,
+ 10, 232, 52, 53, 54, 16, 20, 57, 10, 43,
+ 10, 45, 46, 47, 48, 49, 10, 7, 52, 53,
+ 54, 56, 4, 57, 4, 45, 46, 47, 48, 49,
+ 17, 4, 52, 53, 54, 20, 6, 57, 23, 24,
+ 17, 20, 9, 11, 23, 9, 20, 7, 33, 34,
+ 35, 20, 10, 19, 33, 34, 35, 20, 17, 21,
+ 23, 10, 50, 5, 33, 34, 35, 11, 24, 102,
+ 33, 34, 35, 16, 59, 60, 61, 62, 63, 64,
+ 59, 60, 61, 62, 63, 64, 60, 61, 62, 63,
+ 64, 60, 61, 62, 63, 64, 179, 60, 61, 62,
+ 63, 64, 42, 10, 192, 45, 46, 210, 155, 201,
+ -1, 100, 19, 214, 54, 196, 69, -1, 25, -1,
+ 27, 28, 29, 30, 31, 32, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, 75, 76, 77, 78, 79,
+ 80, 81, 82, 83, 84, 85, 11, 43, -1, 45,
+ 46, 47, 48, 49, 19, -1, 52, 53, 54, -1,
+ 25, 57, 27, 28, 29, 30, 31, 32, 19, -1,
+ -1, -1, -1, -1, 25, -1, 27, 28, 29, 30,
+ 31, 32, 19, -1, -1, -1, -1, -1, 25, -1,
+ -1, -1, 29, 30, 31, 32, 45, 46, 47, 48,
+ 49, -1, -1, 52, 53, 54, -1, -1, 57
+};
+
+/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
+ symbol of state STATE-NUM. */
+static const unsigned char yystos[] =
+{
+ 0, 37, 38, 39, 67, 68, 69, 70, 71, 75,
+ 11, 11, 11, 0, 41, 69, 82, 83, 3, 72,
+ 73, 74, 72, 3, 76, 77, 78, 9, 83, 15,
+ 12, 73, 17, 12, 15, 12, 77, 9, 79, 3,
+ 5, 7, 9, 18, 55, 60, 61, 113, 114, 115,
+ 116, 117, 3, 4, 9, 26, 51, 111, 112, 113,
+ 4, 42, 3, 80, 81, 17, 18, 115, 3, 9,
+ 115, 115, 17, 84, 20, 23, 24, 33, 34, 35,
+ 59, 60, 61, 62, 63, 64, 9, 112, 115, 112,
+ 9, 19, 25, 27, 28, 29, 30, 31, 32, 9,
+ 15, 10, 16, 3, 10, 3, 7, 114, 80, 85,
+ 10, 36, 115, 115, 115, 115, 115, 115, 115, 115,
+ 115, 115, 115, 7, 10, 3, 112, 112, 112, 112,
+ 112, 112, 112, 112, 113, 111, 81, 10, 10, 10,
+ 11, 30, 86, 10, 10, 10, 43, 45, 46, 47,
+ 48, 49, 52, 53, 54, 57, 87, 88, 91, 92,
+ 101, 102, 105, 106, 107, 108, 4, 6, 7, 8,
+ 22, 58, 94, 95, 96, 99, 113, 7, 56, 93,
+ 113, 112, 4, 4, 4, 102, 12, 88, 17, 7,
+ 103, 113, 13, 6, 9, 17, 16, 43, 11, 94,
+ 11, 110, 113, 9, 104, 95, 80, 100, 96, 7,
+ 89, 90, 91, 108, 19, 97, 87, 104, 21, 10,
+ 113, 14, 10, 12, 90, 17, 20, 98, 110, 12,
+ 113, 10, 50, 109, 11, 108, 87, 12
+};
+
+#define yyerrok (yyerrstatus = 0)
+#define yyclearin (yychar = YYEMPTY)
+#define YYEMPTY (-2)
+#define YYEOF 0
+
+#define YYACCEPT goto yyacceptlab
+#define YYABORT goto yyabortlab
+#define YYERROR goto yyerrorlab
+
+
+/* Like YYERROR except do call yyerror. This remains here temporarily
+ to ease the transition to the new meaning of YYERROR, for GCC.
+ Once GCC version 2 has supplanted version 1, this can go. */
+
+#define YYFAIL goto yyerrlab
+
+#define YYRECOVERING() (!!yyerrstatus)
+
+#define YYBACKUP(Token, Value) \
+do \
+ if (yychar == YYEMPTY && yylen == 1) \
+ { \
+ yychar = (Token); \
+ yylval = (Value); \
+ yytoken = YYTRANSLATE (yychar); \
+ YYPOPSTACK; \
+ goto yybackup; \
+ } \
+ else \
+ { \
+ yyerror (&yylloc, lexer, resultAST, YY_("syntax error: cannot back up")); \
+ YYERROR; \
+ } \
+while (0)
+
+
+#define YYTERROR 1
+#define YYERRCODE 256
+
+
+/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N].
+ If N is 0, then set CURRENT to the empty location which ends
+ the previous symbol: RHS[0] (always defined). */
+
+#define YYRHSLOC(Rhs, K) ((Rhs)[K])
+#ifndef YYLLOC_DEFAULT
+# define YYLLOC_DEFAULT(Current, Rhs, N) \
+ do \
+ if (N) \
+ { \
+ (Current).first_line = YYRHSLOC (Rhs, 1).first_line; \
+ (Current).first_column = YYRHSLOC (Rhs, 1).first_column; \
+ (Current).last_line = YYRHSLOC (Rhs, N).last_line; \
+ (Current).last_column = YYRHSLOC (Rhs, N).last_column; \
+ } \
+ else \
+ { \
+ (Current).first_line = (Current).last_line = \
+ YYRHSLOC (Rhs, 0).last_line; \
+ (Current).first_column = (Current).last_column = \
+ YYRHSLOC (Rhs, 0).last_column; \
+ } \
+ while (0)
+#endif
+
+
+/* YY_LOCATION_PRINT -- Print the location on the stream.
+ This macro was not mandated originally: define only if we know
+ we won't break user code: when these are the locations we know. */
+
+#ifndef YY_LOCATION_PRINT
+# if YYLTYPE_IS_TRIVIAL
+# define YY_LOCATION_PRINT(File, Loc) \
+ fprintf (File, "%d.%d-%d.%d", \
+ (Loc).first_line, (Loc).first_column, \
+ (Loc).last_line, (Loc).last_column)
+# else
+# define YY_LOCATION_PRINT(File, Loc) ((void) 0)
+# endif
+#endif
+
+
+/* YYLEX -- calling `yylex' with the right arguments. */
+
+#ifdef YYLEX_PARAM
+# define YYLEX yylex (&yylval, &yylloc, YYLEX_PARAM)
+#else
+# define YYLEX yylex (&yylval, &yylloc, lexer)
+#endif
+
+/* Enable debugging if requested. */
+#if YYDEBUG
+
+# ifndef YYFPRINTF
+# include <stdio.h> /* INFRINGES ON USER NAME SPACE */
+# define YYFPRINTF fprintf
+# endif
+
+# define YYDPRINTF(Args) \
+do { \
+ if (yydebug) \
+ YYFPRINTF Args; \
+} while (0)
+
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \
+do { \
+ if (yydebug) \
+ { \
+ YYFPRINTF (stderr, "%s ", Title); \
+ yysymprint (stderr, \
+ Type, Value, Location); \
+ YYFPRINTF (stderr, "\n"); \
+ } \
+} while (0)
+
+/*------------------------------------------------------------------.
+| yy_stack_print -- Print the state stack from its BOTTOM up to its |
+| TOP (included). |
+`------------------------------------------------------------------*/
+
+#if defined (__STDC__) || defined (__cplusplus)
+static void
+yy_stack_print (short int *bottom, short int *top)
+#else
+static void
+yy_stack_print (bottom, top)
+ short int *bottom;
+ short int *top;
+#endif
+{
+ YYFPRINTF (stderr, "Stack now");
+ for (/* Nothing. */; bottom <= top; ++bottom)
+ YYFPRINTF (stderr, " %d", *bottom);
+ YYFPRINTF (stderr, "\n");
+}
+
+# define YY_STACK_PRINT(Bottom, Top) \
+do { \
+ if (yydebug) \
+ yy_stack_print ((Bottom), (Top)); \
+} while (0)
+
+
+/*------------------------------------------------.
+| Report that the YYRULE is going to be reduced. |
+`------------------------------------------------*/
+
+#if defined (__STDC__) || defined (__cplusplus)
+static void
+yy_reduce_print (int yyrule)
+#else
+static void
+yy_reduce_print (yyrule)
+ int yyrule;
+#endif
+{
+ int yyi;
+ unsigned long int yylno = yyrline[yyrule];
+ YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu), ",
+ yyrule - 1, yylno);
+ /* Print the symbols being reduced, and their result. */
+ for (yyi = yyprhs[yyrule]; 0 <= yyrhs[yyi]; yyi++)
+ YYFPRINTF (stderr, "%s ", yytname[yyrhs[yyi]]);
+ YYFPRINTF (stderr, "-> %s\n", yytname[yyr1[yyrule]]);
+}
+
+# define YY_REDUCE_PRINT(Rule) \
+do { \
+ if (yydebug) \
+ yy_reduce_print (Rule); \
+} while (0)
+
+/* Nonzero means print parse trace. It is left uninitialized so that
+ multiple parsers can coexist. */
+int yydebug;
+#else /* !YYDEBUG */
+# define YYDPRINTF(Args)
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
+# define YY_STACK_PRINT(Bottom, Top)
+# define YY_REDUCE_PRINT(Rule)
+#endif /* !YYDEBUG */
+
+
+/* YYINITDEPTH -- initial size of the parser's stacks. */
+#ifndef YYINITDEPTH
+# define YYINITDEPTH 200
+#endif
+
+/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
+ if the built-in stack extension method is used).
+
+ Do not make this value too large; the results are undefined if
+ YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
+ evaluated with infinite-precision integer arithmetic. */
+
+#ifndef YYMAXDEPTH
+# define YYMAXDEPTH 10000
+#endif
+
+\f
+
+#if YYERROR_VERBOSE
+
+# ifndef yystrlen
+# if defined (__GLIBC__) && defined (_STRING_H)
+# define yystrlen strlen
+# else
+/* Return the length of YYSTR. */
+static YYSIZE_T
+# if defined (__STDC__) || defined (__cplusplus)
+yystrlen (const char *yystr)
+# else
+yystrlen (yystr)
+ const char *yystr;
+# endif
+{
+ const char *yys = yystr;
+
+ while (*yys++ != '\0')
+ continue;
+
+ return yys - yystr - 1;
+}
+# endif
+# endif
+
+# ifndef yystpcpy
+# if defined (__GLIBC__) && defined (_STRING_H) && defined (_GNU_SOURCE)
+# define yystpcpy stpcpy
+# else
+/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
+ YYDEST. */
+static char *
+# if defined (__STDC__) || defined (__cplusplus)
+yystpcpy (char *yydest, const char *yysrc)
+# else
+yystpcpy (yydest, yysrc)
+ char *yydest;
+ const char *yysrc;
+# endif
+{
+ char *yyd = yydest;
+ const char *yys = yysrc;
+
+ while ((*yyd++ = *yys++) != '\0')
+ continue;
+
+ return yyd - 1;
+}
+# endif
+# endif
+
+# ifndef yytnamerr
+/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
+ quotes and backslashes, so that it's suitable for yyerror. The
+ heuristic is that double-quoting is unnecessary unless the string
+ contains an apostrophe, a comma, or backslash (other than
+ backslash-backslash). YYSTR is taken from yytname. If YYRES is
+ null, do not copy; instead, return the length of what the result
+ would have been. */
+static YYSIZE_T
+yytnamerr (char *yyres, const char *yystr)
+{
+ if (*yystr == '"')
+ {
+ size_t yyn = 0;
+ char const *yyp = yystr;
+
+ for (;;)
+ switch (*++yyp)
+ {
+ case '\'':
+ case ',':
+ goto do_not_strip_quotes;
+
+ case '\\':
+ if (*++yyp != '\\')
+ goto do_not_strip_quotes;
+ /* Fall through. */
+ default:
+ if (yyres)
+ yyres[yyn] = *yyp;
+ yyn++;
+ break;
+
+ case '"':
+ if (yyres)
+ yyres[yyn] = '\0';
+ return yyn;
+ }
+ do_not_strip_quotes: ;
+ }
+
+ if (! yyres)
+ return yystrlen (yystr);
+
+ return yystpcpy (yyres, yystr) - yyres;
+}
+# endif
+
+#endif /* YYERROR_VERBOSE */
+
+\f
+
+#if YYDEBUG
+/*--------------------------------.
+| Print this symbol on YYOUTPUT. |
+`--------------------------------*/
+
+#if defined (__STDC__) || defined (__cplusplus)
+static void
+yysymprint (FILE *yyoutput, int yytype, YYSTYPE *yyvaluep, YYLTYPE *yylocationp)
+#else
+static void
+yysymprint (yyoutput, yytype, yyvaluep, yylocationp)
+ FILE *yyoutput;
+ int yytype;
+ YYSTYPE *yyvaluep;
+ YYLTYPE *yylocationp;
+#endif
+{
+ /* Pacify ``unused variable'' warnings. */
+ (void) yyvaluep;
+ (void) yylocationp;
+
+ if (yytype < YYNTOKENS)
+ YYFPRINTF (yyoutput, "token %s (", yytname[yytype]);
+ else
+ YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]);
+
+ YY_LOCATION_PRINT (yyoutput, *yylocationp);
+ YYFPRINTF (yyoutput, ": ");
+
+# ifdef YYPRINT
+ if (yytype < YYNTOKENS)
+ YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
+# endif
+ switch (yytype)
+ {
+ default:
+ break;
+ }
+ YYFPRINTF (yyoutput, ")");
+}
+
+#endif /* ! YYDEBUG */
+/*-----------------------------------------------.
+| Release the memory associated to this symbol. |
+`-----------------------------------------------*/
+
+#if defined (__STDC__) || defined (__cplusplus)
+static void
+yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep, YYLTYPE *yylocationp)
+#else
+static void
+yydestruct (yymsg, yytype, yyvaluep, yylocationp)
+ const char *yymsg;
+ int yytype;
+ YYSTYPE *yyvaluep;
+ YYLTYPE *yylocationp;
+#endif
+{
+ /* Pacify ``unused variable'' warnings. */
+ (void) yyvaluep;
+ (void) yylocationp;
+
+ if (!yymsg)
+ yymsg = "Deleting";
+ YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
+
+ switch (yytype)
+ {
+ case 3: /* "\"identifier\"" */
+#line 158 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { delete (yyvaluep->m_str); };
+#line 1209 "/Users/creed/projects/fsl/fromsvr/elftosb/build/elftosb.build/Debug/elftosb.build/DerivedSources/elftosb_parser.tab.cpp"
+ break;
+ case 4: /* "\"string\"" */
+#line 158 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { delete (yyvaluep->m_str); };
+#line 1214 "/Users/creed/projects/fsl/fromsvr/elftosb/build/elftosb.build/Debug/elftosb.build/DerivedSources/elftosb_parser.tab.cpp"
+ break;
+ case 5: /* "\"integer\"" */
+#line 158 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { delete (yyvaluep->m_int); };
+#line 1219 "/Users/creed/projects/fsl/fromsvr/elftosb/build/elftosb.build/Debug/elftosb.build/DerivedSources/elftosb_parser.tab.cpp"
+ break;
+ case 6: /* "\"section name\"" */
+#line 158 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { delete (yyvaluep->m_str); };
+#line 1224 "/Users/creed/projects/fsl/fromsvr/elftosb/build/elftosb.build/Debug/elftosb.build/DerivedSources/elftosb_parser.tab.cpp"
+ break;
+ case 7: /* "\"source name\"" */
+#line 158 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { delete (yyvaluep->m_str); };
+#line 1229 "/Users/creed/projects/fsl/fromsvr/elftosb/build/elftosb.build/Debug/elftosb.build/DerivedSources/elftosb_parser.tab.cpp"
+ break;
+ case 8: /* "\"binary object\"" */
+#line 158 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { delete (yyvaluep->m_blob); };
+#line 1234 "/Users/creed/projects/fsl/fromsvr/elftosb/build/elftosb.build/Debug/elftosb.build/DerivedSources/elftosb_parser.tab.cpp"
+ break;
+ case 36: /* "\"integer size\"" */
+#line 158 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { delete (yyvaluep->m_int); };
+#line 1239 "/Users/creed/projects/fsl/fromsvr/elftosb/build/elftosb.build/Debug/elftosb.build/DerivedSources/elftosb_parser.tab.cpp"
+ break;
+
+ default:
+ break;
+ }
+}
+\f
+
+/* Prevent warnings from -Wmissing-prototypes. */
+
+#ifdef YYPARSE_PARAM
+# if defined (__STDC__) || defined (__cplusplus)
+int yyparse (void *YYPARSE_PARAM);
+# else
+int yyparse ();
+# endif
+#else /* ! YYPARSE_PARAM */
+#if defined (__STDC__) || defined (__cplusplus)
+int yyparse (ElftosbLexer * lexer, CommandFileASTNode ** resultAST);
+#else
+int yyparse ();
+#endif
+#endif /* ! YYPARSE_PARAM */
+
+
+
+
+
+
+/*----------.
+| yyparse. |
+`----------*/
+
+#ifdef YYPARSE_PARAM
+# if defined (__STDC__) || defined (__cplusplus)
+int yyparse (void *YYPARSE_PARAM)
+# else
+int yyparse (YYPARSE_PARAM)
+ void *YYPARSE_PARAM;
+# endif
+#else /* ! YYPARSE_PARAM */
+#if defined (__STDC__) || defined (__cplusplus)
+int
+yyparse (ElftosbLexer * lexer, CommandFileASTNode ** resultAST)
+#else
+int
+yyparse (lexer, resultAST)
+ ElftosbLexer * lexer;
+ CommandFileASTNode ** resultAST;
+#endif
+#endif
+{
+ /* The look-ahead symbol. */
+int yychar;
+
+/* The semantic value of the look-ahead symbol. */
+YYSTYPE yylval;
+
+/* Number of syntax errors so far. */
+int yynerrs;
+/* Location data for the look-ahead symbol. */
+YYLTYPE yylloc;
+
+ int yystate;
+ int yyn;
+ int yyresult;
+ /* Number of tokens to shift before error messages enabled. */
+ int yyerrstatus;
+ /* Look-ahead token as an internal (translated) token number. */
+ int yytoken = 0;
+
+ /* Three stacks and their tools:
+ `yyss': related to states,
+ `yyvs': related to semantic values,
+ `yyls': related to locations.
+
+ Refer to the stacks thru separate pointers, to allow yyoverflow
+ to reallocate them elsewhere. */
+
+ /* The state stack. */
+ short int yyssa[YYINITDEPTH];
+ short int *yyss = yyssa;
+ short int *yyssp;
+
+ /* The semantic value stack. */
+ YYSTYPE yyvsa[YYINITDEPTH];
+ YYSTYPE *yyvs = yyvsa;
+ YYSTYPE *yyvsp;
+
+ /* The location stack. */
+ YYLTYPE yylsa[YYINITDEPTH];
+ YYLTYPE *yyls = yylsa;
+ YYLTYPE *yylsp;
+ /* The locations where the error started and ended. */
+ YYLTYPE yyerror_range[2];
+
+#define YYPOPSTACK (yyvsp--, yyssp--, yylsp--)
+
+ YYSIZE_T yystacksize = YYINITDEPTH;
+
+ /* The variables used to return semantic value and location from the
+ action routines. */
+ YYSTYPE yyval;
+ YYLTYPE yyloc;
+
+ /* When reducing, the number of symbols on the RHS of the reduced
+ rule. */
+ int yylen;
+
+ YYDPRINTF ((stderr, "Starting parse\n"));
+
+ yystate = 0;
+ yyerrstatus = 0;
+ yynerrs = 0;
+ yychar = YYEMPTY; /* Cause a token to be read. */
+
+ /* Initialize stack pointers.
+ Waste one element of value and location stack
+ so that they stay on the same level as the state stack.
+ The wasted elements are never initialized. */
+
+ yyssp = yyss;
+ yyvsp = yyvs;
+ yylsp = yyls;
+#if YYLTYPE_IS_TRIVIAL
+ /* Initialize the default location before parsing starts. */
+ yylloc.first_line = yylloc.last_line = 1;
+ yylloc.first_column = yylloc.last_column = 0;
+#endif
+
+ goto yysetstate;
+
+/*------------------------------------------------------------.
+| yynewstate -- Push a new state, which is found in yystate. |
+`------------------------------------------------------------*/
+ yynewstate:
+ /* In all cases, when you get here, the value and location stacks
+ have just been pushed. so pushing a state here evens the stacks.
+ */
+ yyssp++;
+
+ yysetstate:
+ *yyssp = yystate;
+
+ if (yyss + yystacksize - 1 <= yyssp)
+ {
+ /* Get the current used size of the three stacks, in elements. */
+ YYSIZE_T yysize = yyssp - yyss + 1;
+
+#ifdef yyoverflow
+ {
+ /* Give user a chance to reallocate the stack. Use copies of
+ these so that the &'s don't force the real ones into
+ memory. */
+ YYSTYPE *yyvs1 = yyvs;
+ short int *yyss1 = yyss;
+ YYLTYPE *yyls1 = yyls;
+
+ /* Each stack pointer address is followed by the size of the
+ data in use in that stack, in bytes. This used to be a
+ conditional around just the two extra args, but that might
+ be undefined if yyoverflow is a macro. */
+ yyoverflow (YY_("memory exhausted"),
+ &yyss1, yysize * sizeof (*yyssp),
+ &yyvs1, yysize * sizeof (*yyvsp),
+ &yyls1, yysize * sizeof (*yylsp),
+ &yystacksize);
+ yyls = yyls1;
+ yyss = yyss1;
+ yyvs = yyvs1;
+ }
+#else /* no yyoverflow */
+# ifndef YYSTACK_RELOCATE
+ goto yyexhaustedlab;
+# else
+ /* Extend the stack our own way. */
+ if (YYMAXDEPTH <= yystacksize)
+ goto yyexhaustedlab;
+ yystacksize *= 2;
+ if (YYMAXDEPTH < yystacksize)
+ yystacksize = YYMAXDEPTH;
+
+ {
+ short int *yyss1 = yyss;
+ union yyalloc *yyptr =
+ (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
+ if (! yyptr)
+ goto yyexhaustedlab;
+ YYSTACK_RELOCATE (yyss);
+ YYSTACK_RELOCATE (yyvs);
+ YYSTACK_RELOCATE (yyls);
+# undef YYSTACK_RELOCATE
+ if (yyss1 != yyssa)
+ YYSTACK_FREE (yyss1);
+ }
+# endif
+#endif /* no yyoverflow */
+
+ yyssp = yyss + yysize - 1;
+ yyvsp = yyvs + yysize - 1;
+ yylsp = yyls + yysize - 1;
+
+ YYDPRINTF ((stderr, "Stack size increased to %lu\n",
+ (unsigned long int) yystacksize));
+
+ if (yyss + yystacksize - 1 <= yyssp)
+ YYABORT;
+ }
+
+ YYDPRINTF ((stderr, "Entering state %d\n", yystate));
+
+ goto yybackup;
+
+/*-----------.
+| yybackup. |
+`-----------*/
+yybackup:
+
+/* Do appropriate processing given the current state. */
+/* Read a look-ahead token if we need one and don't already have one. */
+/* yyresume: */
+
+ /* First try to decide what to do without reference to look-ahead token. */
+
+ yyn = yypact[yystate];
+ if (yyn == YYPACT_NINF)
+ goto yydefault;
+
+ /* Not known => get a look-ahead token if don't already have one. */
+
+ /* YYCHAR is either YYEMPTY or YYEOF or a valid look-ahead symbol. */
+ if (yychar == YYEMPTY)
+ {
+ YYDPRINTF ((stderr, "Reading a token: "));
+ yychar = YYLEX;
+ }
+
+ if (yychar <= YYEOF)
+ {
+ yychar = yytoken = YYEOF;
+ YYDPRINTF ((stderr, "Now at end of input.\n"));
+ }
+ else
+ {
+ yytoken = YYTRANSLATE (yychar);
+ YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
+ }
+
+ /* If the proper action on seeing token YYTOKEN is to reduce or to
+ detect an error, take that action. */
+ yyn += yytoken;
+ if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
+ goto yydefault;
+ yyn = yytable[yyn];
+ if (yyn <= 0)
+ {
+ if (yyn == 0 || yyn == YYTABLE_NINF)
+ goto yyerrlab;
+ yyn = -yyn;
+ goto yyreduce;
+ }
+
+ if (yyn == YYFINAL)
+ YYACCEPT;
+
+ /* Shift the look-ahead token. */
+ YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
+
+ /* Discard the token being shifted unless it is eof. */
+ if (yychar != YYEOF)
+ yychar = YYEMPTY;
+
+ *++yyvsp = yylval;
+ *++yylsp = yylloc;
+
+ /* Count tokens shifted since error; after three, turn off error
+ status. */
+ if (yyerrstatus)
+ yyerrstatus--;
+
+ yystate = yyn;
+ goto yynewstate;
+
+
+/*-----------------------------------------------------------.
+| yydefault -- do the default action for the current state. |
+`-----------------------------------------------------------*/
+yydefault:
+ yyn = yydefact[yystate];
+ if (yyn == 0)
+ goto yyerrlab;
+ goto yyreduce;
+
+
+/*-----------------------------.
+| yyreduce -- Do a reduction. |
+`-----------------------------*/
+yyreduce:
+ /* yyn is the number of a rule to reduce with. */
+ yylen = yyr2[yyn];
+
+ /* If YYLEN is nonzero, implement the default value of the action:
+ `$$ = $1'.
+
+ Otherwise, the following line sets YYVAL to garbage.
+ This behavior is undocumented and Bison
+ users should not rely upon it. Assigning to YYVAL
+ unconditionally makes the parser a bit smaller, and it avoids a
+ GCC warning that YYVAL may be used uninitialized. */
+ yyval = yyvsp[1-yylen];
+
+ /* Default location. */
+ YYLLOC_DEFAULT (yyloc, yylsp - yylen, yylen);
+ YY_REDUCE_PRINT (yyn);
+ switch (yyn)
+ {
+ case 2:
+#line 163 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ CommandFileASTNode * commandFile = new CommandFileASTNode();
+ commandFile->setBlocks(dynamic_cast<ListASTNode*>((yyvsp[-1].m_ast)));
+ commandFile->setSections(dynamic_cast<ListASTNode*>((yyvsp[0].m_ast)));
+ commandFile->setLocation((yylsp[-1]), (yylsp[0]));
+ *resultAST = commandFile;
+ ;}
+ break;
+
+ case 3:
+#line 173 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = list;
+ ;}
+ break;
+
+ case 4:
+#line 179 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ dynamic_cast<ListASTNode*>((yyvsp[-1].m_ast))->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = (yyvsp[-1].m_ast);
+ ;}
+ break;
+
+ case 5:
+#line 186 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[0].m_ast); ;}
+ break;
+
+ case 6:
+#line 187 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[0].m_ast); ;}
+ break;
+
+ case 7:
+#line 188 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[0].m_ast); ;}
+ break;
+
+ case 8:
+#line 192 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new OptionsBlockASTNode(dynamic_cast<ListASTNode *>((yyvsp[-1].m_ast)));
+ ;}
+ break;
+
+ case 9:
+#line 198 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new ConstantsBlockASTNode(dynamic_cast<ListASTNode *>((yyvsp[-1].m_ast)));
+ ;}
+ break;
+
+ case 10:
+#line 204 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = list;
+ ;}
+ break;
+
+ case 11:
+#line 210 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ dynamic_cast<ListASTNode*>((yyvsp[-1].m_ast))->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = (yyvsp[-1].m_ast);
+ ;}
+ break;
+
+ case 12:
+#line 216 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[-1].m_ast); ;}
+ break;
+
+ case 13:
+#line 217 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = NULL; ;}
+ break;
+
+ case 14:
+#line 221 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new AssignmentASTNode((yyvsp[-2].m_str), (yyvsp[0].m_ast));
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 15:
+#line 228 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new SourcesBlockASTNode(dynamic_cast<ListASTNode *>((yyvsp[-1].m_ast)));
+ ;}
+ break;
+
+ case 16:
+#line 234 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = list;
+ ;}
+ break;
+
+ case 17:
+#line 240 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ dynamic_cast<ListASTNode*>((yyvsp[-1].m_ast))->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = (yyvsp[-1].m_ast);
+ ;}
+ break;
+
+ case 18:
+#line 248 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ // tell the lexer that this is the name of a source file
+ SourceDefASTNode * node = dynamic_cast<SourceDefASTNode*>((yyvsp[-2].m_ast));
+ if ((yyvsp[-1].m_ast))
+ {
+ node->setAttributes(dynamic_cast<ListASTNode*>((yyvsp[-1].m_ast)));
+ }
+ node->setLocation(node->getLocation(), (yylsp[0]));
+ lexer->addSourceName(node->getName());
+ (yyval.m_ast) = (yyvsp[-2].m_ast);
+ ;}
+ break;
+
+ case 19:
+#line 259 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = NULL; ;}
+ break;
+
+ case 20:
+#line 263 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new PathSourceDefASTNode((yyvsp[-2].m_str), (yyvsp[0].m_str));
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 21:
+#line 268 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new ExternSourceDefASTNode((yyvsp[-5].m_str), dynamic_cast<ExprASTNode*>((yyvsp[-1].m_ast)));
+ (yyval.m_ast)->setLocation((yylsp[-5]), (yylsp[0]));
+ ;}
+ break;
+
+ case 22:
+#line 275 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[-1].m_ast); ;}
+ break;
+
+ case 23:
+#line 276 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = NULL; ;}
+ break;
+
+ case 24:
+#line 281 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = list;
+ ;}
+ break;
+
+ case 25:
+#line 287 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ dynamic_cast<ListASTNode*>((yyvsp[-2].m_ast))->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = (yyvsp[-2].m_ast);
+ ;}
+ break;
+
+ case 26:
+#line 295 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new AssignmentASTNode((yyvsp[-2].m_str), (yyvsp[0].m_ast));
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 27:
+#line 302 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = list;
+ ;}
+ break;
+
+ case 28:
+#line 308 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ dynamic_cast<ListASTNode*>((yyvsp[-1].m_ast))->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = (yyvsp[-1].m_ast);
+ ;}
+ break;
+
+ case 29:
+#line 315 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ SectionContentsASTNode * sectionNode = dynamic_cast<SectionContentsASTNode*>((yyvsp[0].m_ast));
+ if (sectionNode)
+ {
+ ExprASTNode * exprNode = dynamic_cast<ExprASTNode*>((yyvsp[-3].m_ast));
+ sectionNode->setSectionNumberExpr(exprNode);
+ sectionNode->setOptions(dynamic_cast<ListASTNode*>((yyvsp[-2].m_ast)));
+ sectionNode->setLocation((yylsp[-5]), sectionNode->getLocation());
+ }
+ (yyval.m_ast) = (yyvsp[0].m_ast);
+ ;}
+ break;
+
+ case 30:
+#line 330 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = (yyvsp[0].m_ast);
+ ;}
+ break;
+
+ case 31:
+#line 334 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = NULL;
+ ;}
+ break;
+
+ case 32:
+#line 341 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = (yyvsp[0].m_ast);
+ ;}
+ break;
+
+ case 33:
+#line 345 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = NULL;
+ ;}
+ break;
+
+ case 34:
+#line 352 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ DataSectionContentsASTNode * dataSection = new DataSectionContentsASTNode((yyvsp[-1].m_ast));
+ dataSection->setLocation((yylsp[-2]), (yylsp[0]));
+ (yyval.m_ast) = dataSection;
+ ;}
+ break;
+
+ case 35:
+#line 358 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ListASTNode * listNode = dynamic_cast<ListASTNode*>((yyvsp[-1].m_ast));
+ (yyval.m_ast) = new BootableSectionContentsASTNode(listNode);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 36:
+#line 366 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = list;
+ ;}
+ break;
+
+ case 37:
+#line 372 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ dynamic_cast<ListASTNode*>((yyvsp[-1].m_ast))->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = (yyvsp[-1].m_ast);
+ ;}
+ break;
+
+ case 38:
+#line 379 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[-1].m_ast); ;}
+ break;
+
+ case 39:
+#line 380 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[0].m_ast); ;}
+ break;
+
+ case 40:
+#line 381 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[0].m_ast); ;}
+ break;
+
+ case 41:
+#line 382 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = NULL; ;}
+ break;
+
+ case 42:
+#line 386 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = list;
+ ;}
+ break;
+
+ case 43:
+#line 392 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ dynamic_cast<ListASTNode*>((yyvsp[-1].m_ast))->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = (yyvsp[-1].m_ast);
+ ;}
+ break;
+
+ case 44:
+#line 399 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[-1].m_ast); ;}
+ break;
+
+ case 45:
+#line 400 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[0].m_ast); ;}
+ break;
+
+ case 46:
+#line 401 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = NULL; ;}
+ break;
+
+ case 47:
+#line 404 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[0].m_ast); ;}
+ break;
+
+ case 48:
+#line 405 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[0].m_ast); ;}
+ break;
+
+ case 49:
+#line 406 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[0].m_ast); ;}
+ break;
+
+ case 50:
+#line 407 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[0].m_ast); ;}
+ break;
+
+ case 51:
+#line 411 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ LoadStatementASTNode * stmt = new LoadStatementASTNode();
+ stmt->setData((yyvsp[-1].m_ast));
+ stmt->setTarget((yyvsp[0].m_ast));
+ // set dcd load flag if the "dcd" keyword was present.
+ if ((yyvsp[-2].m_num))
+ {
+ stmt->setDCDLoad(true);
+ }
+ // set char locations for the statement
+ if ((yyvsp[0].m_ast))
+ {
+ stmt->setLocation((yylsp[-3]), (yylsp[0]));
+ }
+ else
+ {
+ stmt->setLocation((yylsp[-3]), (yylsp[-1]));
+ }
+ (yyval.m_ast) = stmt;
+ ;}
+ break;
+
+ case 52:
+#line 434 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ if (!elftosb::g_enableHABSupport)
+ {
+ yyerror(&yylloc, lexer, resultAST, "HAB features not supported with the selected family");
+ YYABORT;
+ }
+
+ (yyval.m_num) = 1;
+ ;}
+ break;
+
+ case 53:
+#line 443 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_num) = 0; ;}
+ break;
+
+ case 54:
+#line 446 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = (yyvsp[0].m_ast);
+ ;}
+ break;
+
+ case 55:
+#line 450 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new StringConstASTNode((yyvsp[0].m_str));
+ (yyval.m_ast)->setLocation((yylsp[0]));
+ ;}
+ break;
+
+ case 56:
+#line 455 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new SourceASTNode((yyvsp[0].m_str));
+ (yyval.m_ast)->setLocation((yylsp[0]));
+ ;}
+ break;
+
+ case 57:
+#line 460 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new SectionMatchListASTNode(dynamic_cast<ListASTNode*>((yyvsp[0].m_ast)));
+ (yyval.m_ast)->setLocation((yylsp[0]));
+ ;}
+ break;
+
+ case 58:
+#line 465 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new SectionMatchListASTNode(dynamic_cast<ListASTNode*>((yyvsp[-2].m_ast)), (yyvsp[0].m_str));
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 59:
+#line 470 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new SectionMatchListASTNode(dynamic_cast<ListASTNode*>((yyvsp[-1].m_ast)), (yyvsp[-3].m_str));
+ (yyval.m_ast)->setLocation((yylsp[-3]), (yylsp[0]));
+ ;}
+ break;
+
+ case 60:
+#line 475 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new BlobConstASTNode((yyvsp[0].m_blob));
+ (yyval.m_ast)->setLocation((yylsp[0]));
+ ;}
+ break;
+
+ case 61:
+#line 480 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ;}
+ break;
+
+ case 62:
+#line 485 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = list;
+ ;}
+ break;
+
+ case 63:
+#line 491 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ dynamic_cast<ListASTNode*>((yyvsp[-2].m_ast))->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = (yyvsp[-2].m_ast);
+ ;}
+ break;
+
+ case 64:
+#line 499 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new SectionASTNode((yyvsp[0].m_str), SectionASTNode::kInclude);
+ (yyval.m_ast)->setLocation((yylsp[0]));
+ ;}
+ break;
+
+ case 65:
+#line 504 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new SectionASTNode((yyvsp[0].m_str), SectionASTNode::kExclude);
+ (yyval.m_ast)->setLocation((yylsp[-1]), (yylsp[0]));
+ ;}
+ break;
+
+ case 66:
+#line 511 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = (yyvsp[0].m_ast);
+ ;}
+ break;
+
+ case 67:
+#line 515 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new NaturalLocationASTNode();
+// $$->setLocation();
+ ;}
+ break;
+
+ case 68:
+#line 522 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new NaturalLocationASTNode();
+ (yyval.m_ast)->setLocation((yylsp[0]));
+ ;}
+ break;
+
+ case 69:
+#line 527 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = (yyvsp[0].m_ast);
+ ;}
+ break;
+
+ case 70:
+#line 533 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ IVTConstASTNode * ivt = new IVTConstASTNode();
+ if ((yyvsp[-1].m_ast))
+ {
+ ivt->setFieldAssignments(dynamic_cast<ListASTNode*>((yyvsp[-1].m_ast)));
+ }
+ ivt->setLocation((yylsp[-3]), (yylsp[0]));
+ (yyval.m_ast) = ivt;
+ ;}
+ break;
+
+ case 71:
+#line 544 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[0].m_ast); ;}
+ break;
+
+ case 72:
+#line 545 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = NULL; ;}
+ break;
+
+ case 73:
+#line 549 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ CallStatementASTNode * stmt = new CallStatementASTNode();
+ switch ((yyvsp[-2].m_num))
+ {
+ case 1:
+ stmt->setCallType(CallStatementASTNode::kCallType);
+ break;
+ case 2:
+ stmt->setCallType(CallStatementASTNode::kJumpType);
+ break;
+ default:
+ yyerror(&yylloc, lexer, resultAST, "invalid call_or_jump value");
+ YYABORT;
+ break;
+ }
+ stmt->setTarget((yyvsp[-1].m_ast));
+ stmt->setArgument((yyvsp[0].m_ast));
+ stmt->setIsHAB(false);
+ if ((yyvsp[0].m_ast))
+ {
+ stmt->setLocation((yylsp[-2]), (yylsp[0]));
+ }
+ else
+ {
+ stmt->setLocation((yylsp[-2]), (yylsp[-1]));
+ }
+ (yyval.m_ast) = stmt;
+ ;}
+ break;
+
+ case 74:
+#line 578 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ if (!elftosb::g_enableHABSupport)
+ {
+ yyerror(&yylloc, lexer, resultAST, "HAB features not supported with the selected family");
+ YYABORT;
+ }
+
+ CallStatementASTNode * stmt = new CallStatementASTNode();
+ switch ((yyvsp[-2].m_num))
+ {
+ case 1:
+ stmt->setCallType(CallStatementASTNode::kCallType);
+ break;
+ case 2:
+ stmt->setCallType(CallStatementASTNode::kJumpType);
+ break;
+ default:
+ yyerror(&yylloc, lexer, resultAST, "invalid call_or_jump value");
+ YYABORT;
+ break;
+ }
+ stmt->setTarget((yyvsp[-1].m_ast));
+ stmt->setArgument((yyvsp[0].m_ast));
+ stmt->setIsHAB(true);
+ if ((yyvsp[0].m_ast))
+ {
+ stmt->setLocation((yylsp[-3]), (yylsp[0]));
+ }
+ else
+ {
+ stmt->setLocation((yylsp[-3]), (yylsp[-1]));
+ }
+ (yyval.m_ast) = stmt;
+ ;}
+ break;
+
+ case 75:
+#line 614 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_num) = 1; ;}
+ break;
+
+ case 76:
+#line 615 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_num) = 2; ;}
+ break;
+
+ case 77:
+#line 619 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new SymbolASTNode(NULL, (yyvsp[0].m_str));
+ (yyval.m_ast)->setLocation((yylsp[0]));
+ ;}
+ break;
+
+ case 78:
+#line 624 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new AddressRangeASTNode((yyvsp[0].m_ast), NULL);
+ (yyval.m_ast)->setLocation((yyvsp[0].m_ast));
+ ;}
+ break;
+
+ case 79:
+#line 630 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[-1].m_ast); ;}
+ break;
+
+ case 80:
+#line 631 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = NULL; ;}
+ break;
+
+ case 81:
+#line 632 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = NULL; ;}
+ break;
+
+ case 82:
+#line 636 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new FromStatementASTNode((yyvsp[-3].m_str), dynamic_cast<ListASTNode*>((yyvsp[-1].m_ast)));
+ (yyval.m_ast)->setLocation((yylsp[-4]), (yylsp[0]));
+ ;}
+ break;
+
+ case 83:
+#line 643 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new ModeStatementASTNode(dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast)));
+ (yyval.m_ast)->setLocation((yylsp[-1]), (yylsp[0]));
+ ;}
+ break;
+
+ case 84:
+#line 650 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new MessageStatementASTNode(MessageStatementASTNode::kInfo, (yyvsp[0].m_str));
+ (yyval.m_ast)->setLocation((yylsp[-1]), (yylsp[0]));
+ ;}
+ break;
+
+ case 85:
+#line 655 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new MessageStatementASTNode(MessageStatementASTNode::kWarning, (yyvsp[0].m_str));
+ (yyval.m_ast)->setLocation((yylsp[-1]), (yylsp[0]));
+ ;}
+ break;
+
+ case 86:
+#line 660 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new MessageStatementASTNode(MessageStatementASTNode::kError, (yyvsp[0].m_str));
+ (yyval.m_ast)->setLocation((yylsp[-1]), (yylsp[0]));
+ ;}
+ break;
+
+ case 87:
+#line 667 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ IfStatementASTNode * ifStmt = new IfStatementASTNode();
+ ifStmt->setConditionExpr(dynamic_cast<ExprASTNode*>((yyvsp[-4].m_ast)));
+ ifStmt->setIfStatements(dynamic_cast<ListASTNode*>((yyvsp[-2].m_ast)));
+ ifStmt->setElseStatements(dynamic_cast<ListASTNode*>((yyvsp[0].m_ast)));
+ ifStmt->setLocation((yylsp[-5]), (yylsp[0]));
+ (yyval.m_ast) = ifStmt;
+ ;}
+ break;
+
+ case 88:
+#line 678 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = (yyvsp[-1].m_ast);
+ ;}
+ break;
+
+ case 89:
+#line 682 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode((yyvsp[0].m_ast));
+ (yyval.m_ast) = list;
+ (yyval.m_ast)->setLocation((yylsp[-1]), (yylsp[0]));
+ ;}
+ break;
+
+ case 90:
+#line 688 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = NULL; ;}
+ break;
+
+ case 91:
+#line 692 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new AddressRangeASTNode((yyvsp[0].m_ast), NULL);
+ (yyval.m_ast)->setLocation((yyvsp[0].m_ast));
+ ;}
+ break;
+
+ case 92:
+#line 697 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new AddressRangeASTNode((yyvsp[-2].m_ast), (yyvsp[0].m_ast));
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 93:
+#line 704 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = (yyvsp[0].m_ast);
+ ;}
+ break;
+
+ case 94:
+#line 708 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new StringConstASTNode((yyvsp[0].m_str));
+ (yyval.m_ast)->setLocation((yylsp[0]));
+ ;}
+ break;
+
+ case 95:
+#line 715 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = (yyvsp[0].m_ast);
+ ;}
+ break;
+
+ case 96:
+#line 719 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kLessThan, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 97:
+#line 726 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kGreaterThan, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 98:
+#line 733 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kGreaterThanEqual, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 99:
+#line 740 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kLessThanEqual, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 100:
+#line 747 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kEqual, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 101:
+#line 754 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kNotEqual, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 102:
+#line 761 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kBooleanAnd, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 103:
+#line 768 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kBooleanOr, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 104:
+#line 775 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new BooleanNotExprASTNode(dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast)));
+ (yyval.m_ast)->setLocation((yylsp[-1]), (yylsp[0]));
+ ;}
+ break;
+
+ case 105:
+#line 780 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new SourceFileFunctionASTNode((yyvsp[-3].m_str), (yyvsp[-1].m_str));
+ (yyval.m_ast)->setLocation((yylsp[-3]), (yylsp[0]));
+ ;}
+ break;
+
+ case 106:
+#line 785 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = (yyvsp[-1].m_ast);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 107:
+#line 790 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new DefinedOperatorASTNode((yyvsp[-1].m_str));
+ (yyval.m_ast)->setLocation((yylsp[-3]), (yylsp[0]));
+ ;}
+ break;
+
+ case 108:
+#line 796 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ { (yyval.m_ast) = (yyvsp[0].m_ast); ;}
+ break;
+
+ case 109:
+#line 800 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new SymbolASTNode((yyvsp[0].m_str), (yyvsp[-2].m_str));
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 110:
+#line 805 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new SymbolASTNode((yyvsp[0].m_str));
+ (yyval.m_ast)->setLocation((yylsp[-1]), (yylsp[0]));
+ ;}
+ break;
+
+ case 111:
+#line 813 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = (yyvsp[0].m_ast);
+ ;}
+ break;
+
+ case 112:
+#line 817 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new VariableExprASTNode((yyvsp[0].m_str));
+ (yyval.m_ast)->setLocation((yylsp[0]));
+ ;}
+ break;
+
+ case 113:
+#line 822 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new SymbolRefExprASTNode(dynamic_cast<SymbolASTNode*>((yyvsp[0].m_ast)));
+ (yyval.m_ast)->setLocation((yylsp[0]));
+ ;}
+ break;
+
+ case 114:
+#line 833 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kAdd, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 115:
+#line 840 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kSubtract, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 116:
+#line 847 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kMultiply, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 117:
+#line 854 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kDivide, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 118:
+#line 861 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kModulus, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 119:
+#line 868 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kPower, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 120:
+#line 875 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kBitwiseAnd, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 121:
+#line 882 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kBitwiseOr, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 122:
+#line 889 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kBitwiseXor, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 123:
+#line 896 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kShiftLeft, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 124:
+#line 903 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast));
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast));
+ (yyval.m_ast) = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kShiftRight, right);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 125:
+#line 910 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = (yyvsp[0].m_ast);
+ ;}
+ break;
+
+ case 126:
+#line 914 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new IntSizeExprASTNode(dynamic_cast<ExprASTNode*>((yyvsp[-2].m_ast)), (yyvsp[0].m_int)->getWordSize());
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 127:
+#line 919 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = (yyvsp[-1].m_ast);
+ (yyval.m_ast)->setLocation((yylsp[-2]), (yylsp[0]));
+ ;}
+ break;
+
+ case 128:
+#line 924 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new SizeofOperatorASTNode(dynamic_cast<SymbolASTNode*>((yyvsp[-1].m_ast)));
+ (yyval.m_ast)->setLocation((yylsp[-3]), (yylsp[0]));
+ ;}
+ break;
+
+ case 129:
+#line 929 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new SizeofOperatorASTNode((yyvsp[-1].m_str));
+ (yyval.m_ast)->setLocation((yylsp[-3]), (yylsp[0]));
+ ;}
+ break;
+
+ case 130:
+#line 934 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new SizeofOperatorASTNode((yyvsp[-1].m_str));
+ (yyval.m_ast)->setLocation((yylsp[-3]), (yylsp[0]));
+ ;}
+ break;
+
+ case 131:
+#line 941 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = (yyvsp[0].m_ast);
+ ;}
+ break;
+
+ case 132:
+#line 945 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new NegativeExprASTNode(dynamic_cast<ExprASTNode*>((yyvsp[0].m_ast)));
+ (yyval.m_ast)->setLocation((yylsp[-1]), (yylsp[0]));
+ ;}
+ break;
+
+ case 133:
+#line 952 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+ {
+ (yyval.m_ast) = new IntConstExprASTNode((yyvsp[0].m_int)->getValue(), (yyvsp[0].m_int)->getWordSize());
+ (yyval.m_ast)->setLocation((yylsp[0]));
+ ;}
+ break;
+
+
+ default: break;
+ }
+
+/* Line 1126 of yacc.c. */
+#line 2663 "/Users/creed/projects/fsl/fromsvr/elftosb/build/elftosb.build/Debug/elftosb.build/DerivedSources/elftosb_parser.tab.cpp"
+\f
+ yyvsp -= yylen;
+ yyssp -= yylen;
+ yylsp -= yylen;
+
+ YY_STACK_PRINT (yyss, yyssp);
+
+ *++yyvsp = yyval;
+ *++yylsp = yyloc;
+
+ /* Now `shift' the result of the reduction. Determine what state
+ that goes to, based on the state we popped back to and the rule
+ number reduced by. */
+
+ yyn = yyr1[yyn];
+
+ yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
+ if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
+ yystate = yytable[yystate];
+ else
+ yystate = yydefgoto[yyn - YYNTOKENS];
+
+ goto yynewstate;
+
+
+/*------------------------------------.
+| yyerrlab -- here on detecting error |
+`------------------------------------*/
+yyerrlab:
+ /* If not already recovering from an error, report this error. */
+ if (!yyerrstatus)
+ {
+ ++yynerrs;
+#if YYERROR_VERBOSE
+ yyn = yypact[yystate];
+
+ if (YYPACT_NINF < yyn && yyn < YYLAST)
+ {
+ int yytype = YYTRANSLATE (yychar);
+ YYSIZE_T yysize0 = yytnamerr (0, yytname[yytype]);
+ YYSIZE_T yysize = yysize0;
+ YYSIZE_T yysize1;
+ int yysize_overflow = 0;
+ char *yymsg = 0;
+# define YYERROR_VERBOSE_ARGS_MAXIMUM 5
+ char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+ int yyx;
+
+#if 0
+ /* This is so xgettext sees the translatable formats that are
+ constructed on the fly. */
+ YY_("syntax error, unexpected %s");
+ YY_("syntax error, unexpected %s, expecting %s");
+ YY_("syntax error, unexpected %s, expecting %s or %s");
+ YY_("syntax error, unexpected %s, expecting %s or %s or %s");
+ YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s");
+#endif
+ char *yyfmt;
+ char const *yyf;
+ static char const yyunexpected[] = "syntax error, unexpected %s";
+ static char const yyexpecting[] = ", expecting %s";
+ static char const yyor[] = " or %s";
+ char yyformat[sizeof yyunexpected
+ + sizeof yyexpecting - 1
+ + ((YYERROR_VERBOSE_ARGS_MAXIMUM - 2)
+ * (sizeof yyor - 1))];
+ char const *yyprefix = yyexpecting;
+
+ /* Start YYX at -YYN if negative to avoid negative indexes in
+ YYCHECK. */
+ int yyxbegin = yyn < 0 ? -yyn : 0;
+
+ /* Stay within bounds of both yycheck and yytname. */
+ int yychecklim = YYLAST - yyn;
+ int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
+ int yycount = 1;
+
+ yyarg[0] = yytname[yytype];
+ yyfmt = yystpcpy (yyformat, yyunexpected);
+
+ for (yyx = yyxbegin; yyx < yyxend; ++yyx)
+ if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR)
+ {
+ if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
+ {
+ yycount = 1;
+ yysize = yysize0;
+ yyformat[sizeof yyunexpected - 1] = '\0';
+ break;
+ }
+ yyarg[yycount++] = yytname[yyx];
+ yysize1 = yysize + yytnamerr (0, yytname[yyx]);
+ yysize_overflow |= yysize1 < yysize;
+ yysize = yysize1;
+ yyfmt = yystpcpy (yyfmt, yyprefix);
+ yyprefix = yyor;
+ }
+
+ yyf = YY_(yyformat);
+ yysize1 = yysize + yystrlen (yyf);
+ yysize_overflow |= yysize1 < yysize;
+ yysize = yysize1;
+
+ if (!yysize_overflow && yysize <= YYSTACK_ALLOC_MAXIMUM)
+ yymsg = (char *) YYSTACK_ALLOC (yysize);
+ if (yymsg)
+ {
+ /* Avoid sprintf, as that infringes on the user's name space.
+ Don't have undefined behavior even if the translation
+ produced a string with the wrong number of "%s"s. */
+ char *yyp = yymsg;
+ int yyi = 0;
+ while ((*yyp = *yyf))
+ {
+ if (*yyp == '%' && yyf[1] == 's' && yyi < yycount)
+ {
+ yyp += yytnamerr (yyp, yyarg[yyi++]);
+ yyf += 2;
+ }
+ else
+ {
+ yyp++;
+ yyf++;
+ }
+ }
+ yyerror (&yylloc, lexer, resultAST, yymsg);
+ YYSTACK_FREE (yymsg);
+ }
+ else
+ {
+ yyerror (&yylloc, lexer, resultAST, YY_("syntax error"));
+ goto yyexhaustedlab;
+ }
+ }
+ else
+#endif /* YYERROR_VERBOSE */
+ yyerror (&yylloc, lexer, resultAST, YY_("syntax error"));
+ }
+
+ yyerror_range[0] = yylloc;
+
+ if (yyerrstatus == 3)
+ {
+ /* If just tried and failed to reuse look-ahead token after an
+ error, discard it. */
+
+ if (yychar <= YYEOF)
+ {
+ /* Return failure if at end of input. */
+ if (yychar == YYEOF)
+ YYABORT;
+ }
+ else
+ {
+ yydestruct ("Error: discarding", yytoken, &yylval, &yylloc);
+ yychar = YYEMPTY;
+ }
+ }
+
+ /* Else will try to reuse look-ahead token after shifting the error
+ token. */
+ goto yyerrlab1;
+
+
+/*---------------------------------------------------.
+| yyerrorlab -- error raised explicitly by YYERROR. |
+`---------------------------------------------------*/
+yyerrorlab:
+
+ /* Pacify compilers like GCC when the user code never invokes
+ YYERROR and the label yyerrorlab therefore never appears in user
+ code. */
+ if (0)
+ goto yyerrorlab;
+
+ yyerror_range[0] = yylsp[1-yylen];
+ yylsp -= yylen;
+ yyvsp -= yylen;
+ yyssp -= yylen;
+ yystate = *yyssp;
+ goto yyerrlab1;
+
+
+/*-------------------------------------------------------------.
+| yyerrlab1 -- common code for both syntax error and YYERROR. |
+`-------------------------------------------------------------*/
+yyerrlab1:
+ yyerrstatus = 3; /* Each real token shifted decrements this. */
+
+ for (;;)
+ {
+ yyn = yypact[yystate];
+ if (yyn != YYPACT_NINF)
+ {
+ yyn += YYTERROR;
+ if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
+ {
+ yyn = yytable[yyn];
+ if (0 < yyn)
+ break;
+ }
+ }
+
+ /* Pop the current state because it cannot handle the error token. */
+ if (yyssp == yyss)
+ YYABORT;
+
+ yyerror_range[0] = *yylsp;
+ yydestruct ("Error: popping", yystos[yystate], yyvsp, yylsp);
+ YYPOPSTACK;
+ yystate = *yyssp;
+ YY_STACK_PRINT (yyss, yyssp);
+ }
+
+ if (yyn == YYFINAL)
+ YYACCEPT;
+
+ *++yyvsp = yylval;
+
+ yyerror_range[1] = yylloc;
+ /* Using YYLLOC is tempting, but would change the location of
+ the look-ahead. YYLOC is available though. */
+ YYLLOC_DEFAULT (yyloc, yyerror_range - 1, 2);
+ *++yylsp = yyloc;
+
+ /* Shift the error token. */
+ YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
+
+ yystate = yyn;
+ goto yynewstate;
+
+
+/*-------------------------------------.
+| yyacceptlab -- YYACCEPT comes here. |
+`-------------------------------------*/
+yyacceptlab:
+ yyresult = 0;
+ goto yyreturn;
+
+/*-----------------------------------.
+| yyabortlab -- YYABORT comes here. |
+`-----------------------------------*/
+yyabortlab:
+ yyresult = 1;
+ goto yyreturn;
+
+#ifndef yyoverflow
+/*-------------------------------------------------.
+| yyexhaustedlab -- memory exhaustion comes here. |
+`-------------------------------------------------*/
+yyexhaustedlab:
+ yyerror (&yylloc, lexer, resultAST, YY_("memory exhausted"));
+ yyresult = 2;
+ /* Fall through. */
+#endif
+
+yyreturn:
+ if (yychar != YYEOF && yychar != YYEMPTY)
+ yydestruct ("Cleanup: discarding lookahead",
+ yytoken, &yylval, &yylloc);
+ while (yyssp != yyss)
+ {
+ yydestruct ("Cleanup: popping",
+ yystos[*yyssp], yyvsp, yylsp);
+ YYPOPSTACK;
+ }
+#ifndef yyoverflow
+ if (yyss != yyssa)
+ YYSTACK_FREE (yyss);
+#endif
+ return yyresult;
+}
+
+
+#line 958 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+
+
+/* code goes here */
+
+static int yylex(YYSTYPE * lvalp, YYLTYPE * yylloc, ElftosbLexer * lexer)
+{
+ int token = lexer->yylex();
+ *yylloc = lexer->getLocation();
+ lexer->getSymbolValue(lvalp);
+ return token;
+}
+
+static void yyerror(YYLTYPE * yylloc, ElftosbLexer * lexer, CommandFileASTNode ** resultAST, const char * error)
+{
+ throw syntax_error(format_string("line %d: %s\n", yylloc->m_firstLine, error));
+}
+
+
--- /dev/null
+/* A Bison parser, made by GNU Bison 2.1. */
+
+/* Skeleton parser for Yacc-like parsing with Bison,
+ Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+/* As a special exception, when this file is copied by Bison into a
+ Bison output file, you may use that output file without restriction.
+ This special exception was added by the Free Software Foundation
+ in version 1.24 of Bison. */
+
+/* Tokens. */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+ /* Put the tokens into the symbol table, so that GDB and other debuggers
+ know about them. */
+ enum yytokentype {
+ TOK_IDENT = 258,
+ TOK_STRING_LITERAL = 259,
+ TOK_INT_LITERAL = 260,
+ TOK_SECTION_NAME = 261,
+ TOK_SOURCE_NAME = 262,
+ TOK_BLOB = 263,
+ TOK_DOT_DOT = 264,
+ TOK_AND = 265,
+ TOK_OR = 266,
+ TOK_GEQ = 267,
+ TOK_LEQ = 268,
+ TOK_EQ = 269,
+ TOK_NEQ = 270,
+ TOK_POWER = 271,
+ TOK_LSHIFT = 272,
+ TOK_RSHIFT = 273,
+ TOK_INT_SIZE = 274,
+ TOK_OPTIONS = 275,
+ TOK_CONSTANTS = 276,
+ TOK_SOURCES = 277,
+ TOK_FILTERS = 278,
+ TOK_SECTION = 279,
+ TOK_EXTERN = 280,
+ TOK_FROM = 281,
+ TOK_RAW = 282,
+ TOK_LOAD = 283,
+ TOK_JUMP = 284,
+ TOK_CALL = 285,
+ TOK_MODE = 286,
+ TOK_IF = 287,
+ TOK_ELSE = 288,
+ TOK_DEFINED = 289,
+ TOK_INFO = 290,
+ TOK_WARNING = 291,
+ TOK_ERROR = 292,
+ TOK_SIZEOF = 293,
+ TOK_DCD = 294,
+ TOK_HAB = 295,
+ TOK_IVT = 296,
+ UNARY_OP = 297
+ };
+#endif
+/* Tokens. */
+#define TOK_IDENT 258
+#define TOK_STRING_LITERAL 259
+#define TOK_INT_LITERAL 260
+#define TOK_SECTION_NAME 261
+#define TOK_SOURCE_NAME 262
+#define TOK_BLOB 263
+#define TOK_DOT_DOT 264
+#define TOK_AND 265
+#define TOK_OR 266
+#define TOK_GEQ 267
+#define TOK_LEQ 268
+#define TOK_EQ 269
+#define TOK_NEQ 270
+#define TOK_POWER 271
+#define TOK_LSHIFT 272
+#define TOK_RSHIFT 273
+#define TOK_INT_SIZE 274
+#define TOK_OPTIONS 275
+#define TOK_CONSTANTS 276
+#define TOK_SOURCES 277
+#define TOK_FILTERS 278
+#define TOK_SECTION 279
+#define TOK_EXTERN 280
+#define TOK_FROM 281
+#define TOK_RAW 282
+#define TOK_LOAD 283
+#define TOK_JUMP 284
+#define TOK_CALL 285
+#define TOK_MODE 286
+#define TOK_IF 287
+#define TOK_ELSE 288
+#define TOK_DEFINED 289
+#define TOK_INFO 290
+#define TOK_WARNING 291
+#define TOK_ERROR 292
+#define TOK_SIZEOF 293
+#define TOK_DCD 294
+#define TOK_HAB 295
+#define TOK_IVT 296
+#define UNARY_OP 297
+
+
+
+
+#if ! defined (YYSTYPE) && ! defined (YYSTYPE_IS_DECLARED)
+#line 58 "/Users/creed/projects/fsl/fromsvr/elftosb/elftosb2/elftosb_parser.y"
+typedef union YYSTYPE {
+ int m_num;
+ elftosb::SizedIntegerValue * m_int;
+ Blob * m_blob;
+ std::string * m_str;
+ elftosb::ASTNode * m_ast; // must use full name here because this is put into *.tab.hpp
+} YYSTYPE;
+/* Line 1447 of yacc.c. */
+#line 130 "/Users/creed/projects/fsl/fromsvr/elftosb/build/elftosb.build/Debug/elftosb.build/DerivedSources/elftosb_parser.tab.hpp"
+# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+# define YYSTYPE_IS_DECLARED 1
+# define YYSTYPE_IS_TRIVIAL 1
+#endif
+
+
+
+#if ! defined (YYLTYPE) && ! defined (YYLTYPE_IS_DECLARED)
+typedef struct YYLTYPE
+{
+ int first_line;
+ int first_column;
+ int last_line;
+ int last_column;
+} YYLTYPE;
+# define yyltype YYLTYPE /* obsolescent; will be withdrawn */
+# define YYLTYPE_IS_DECLARED 1
+# define YYLTYPE_IS_TRIVIAL 1
+#endif
+
+
+
+
--- /dev/null
+/*
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+/* write header with token defines */
+%defines
+
+/* make it reentrant */
+%pure-parser
+
+/* put more info in error messages */
+%error-verbose
+
+/* enable location processing */
+%locations
+
+%{
+#include "ElftosbLexer.h"
+#include "ElftosbAST.h"
+#include "Logging.h"
+#include "Blob.h"
+#include "format_string.h"
+#include "Value.h"
+#include "ConversionController.h"
+
+using namespace elftosb;
+
+//! Our special location type.
+#define YYLTYPE token_loc_t
+
+// this indicates that we're using our own type. it should be unset automatically
+// but that's not working for some reason with the .hpp file.
+#if defined(YYLTYPE_IS_TRIVIAL)
+ #undef YYLTYPE_IS_TRIVIAL
+ #define YYLTYPE_IS_TRIVIAL 0
+#endif
+
+//! Default location action
+#define YYLLOC_DEFAULT(Current, Rhs, N) \
+ do { \
+ if (N) \
+ { \
+ (Current).m_firstLine = YYRHSLOC(Rhs, 1).m_firstLine; \
+ (Current).m_lastLine = YYRHSLOC(Rhs, N).m_lastLine; \
+ } \
+ else \
+ { \
+ (Current).m_firstLine = (Current).m_lastLine = YYRHSLOC(Rhs, 0).m_lastLine; \
+ } \
+ } while (0)
+
+//! Forward declaration of yylex().
+static int yylex(YYSTYPE * lvalp, YYLTYPE * yylloc, ElftosbLexer * lexer);
+
+// Forward declaration of error handling function.
+static void yyerror(YYLTYPE * yylloc, ElftosbLexer * lexer, CommandFileASTNode ** resultAST, const char * error);
+
+%}
+
+/* symbol types */
+%union {
+ int m_num;
+ elftosb::SizedIntegerValue * m_int;
+ Blob * m_blob;
+ std::string * m_str;
+ elftosb::ASTNode * m_ast; // must use full name here because this is put into *.tab.hpp
+}
+
+/* extra parameters for the parser and lexer */
+%parse-param {ElftosbLexer * lexer}
+%parse-param {CommandFileASTNode ** resultAST}
+%lex-param {ElftosbLexer * lexer}
+
+/* token definitions */
+%token <m_str> TOK_IDENT "identifier"
+%token <m_str> TOK_STRING_LITERAL "string"
+%token <m_int> TOK_INT_LITERAL "integer"
+%token <m_str> TOK_SECTION_NAME "section name"
+%token <m_str> TOK_SOURCE_NAME "source name"
+%token <m_blob> TOK_BLOB "binary object"
+%token '('
+%token ')'
+%token '{'
+%token '}'
+%token '['
+%token ']'
+%token '='
+%token ','
+%token ';'
+%token ':'
+%token '>'
+%token '.'
+%token TOK_DOT_DOT ".."
+%token '~'
+%token '&'
+%token '|'
+%token '<'
+%token '>'
+%token '!'
+%token TOK_AND "&&"
+%token TOK_OR "||"
+%token TOK_GEQ ">="
+%token TOK_LEQ "<="
+%token TOK_EQ "=="
+%token TOK_NEQ "!="
+%token TOK_POWER "**"
+%token TOK_LSHIFT "<<"
+%token TOK_RSHIFT ">>"
+%token <m_int> TOK_INT_SIZE "integer size"
+%token TOK_OPTIONS "options"
+%token TOK_CONSTANTS "constants"
+%token TOK_SOURCES "sources"
+%token TOK_FILTERS "filters"
+%token TOK_SECTION "section"
+%token TOK_EXTERN "extern"
+%token TOK_FROM "from"
+%token TOK_RAW "raw"
+%token TOK_LOAD "load"
+%token TOK_JUMP "jump"
+%token TOK_CALL "call"
+%token TOK_MODE "mode"
+%token TOK_IF "if"
+%token TOK_ELSE "else"
+%token TOK_DEFINED "defined"
+%token TOK_INFO "info"
+%token TOK_WARNING "warning"
+%token TOK_ERROR "error"
+%token TOK_SIZEOF "sizeof"
+%token TOK_DCD "dcd"
+%token TOK_HAB "hab"
+%token TOK_IVT "ivt"
+
+/* operator precedence */
+%left "&&" "||"
+%left '>' '<' ">=" "<=" "==" "!="
+%left '|'
+%left '^'
+%left '&'
+%left "<<" ">>"
+%left "**"
+%left '+' '-'
+%left '*' '/' '%'
+%left '.'
+%right UNARY_OP
+
+/* nonterminal types - most nonterminal symbols are subclasses of ASTNode */
+%type <m_ast> command_file blocks_list pre_section_block options_block const_def_list const_def_list_elem
+%type <m_ast> const_def const_expr expr int_const_expr unary_expr int_value constants_block
+%type <m_ast> sources_block source_def_list source_def_list_elem source_def
+%type <m_ast> section_defs section_def section_contents full_stmt_list full_stmt_list_elem
+%type <m_ast> basic_stmt load_stmt call_stmt from_stmt load_data load_target call_target
+%type <m_ast> address_or_range load_target_opt call_arg_opt basic_stmt_list basic_stmt_list_elem
+%type <m_ast> source_attr_list source_attr_list_elem source_attrs_opt
+%type <m_ast> section_list section_list_elem symbol_ref mode_stmt
+%type <m_ast> section_options_opt source_attr_list_opt
+%type <m_ast> if_stmt else_opt message_stmt
+%type <m_ast> bool_expr ivt_def assignment_list_opt
+
+%type <m_num> call_or_jump dcd_opt
+
+%destructor { delete $$; } TOK_IDENT TOK_STRING_LITERAL TOK_SECTION_NAME TOK_SOURCE_NAME TOK_BLOB TOK_INT_SIZE TOK_INT_LITERAL
+
+%%
+
+command_file : blocks_list section_defs
+ {
+ CommandFileASTNode * commandFile = new CommandFileASTNode();
+ commandFile->setBlocks(dynamic_cast<ListASTNode*>($1));
+ commandFile->setSections(dynamic_cast<ListASTNode*>($2));
+ commandFile->setLocation(@1, @2);
+ *resultAST = commandFile;
+ }
+ ;
+
+blocks_list : pre_section_block
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode($1);
+ $$ = list;
+ }
+ | blocks_list pre_section_block
+ {
+ dynamic_cast<ListASTNode*>($1)->appendNode($2);
+ $$ = $1;
+ }
+ ;
+
+pre_section_block
+ : options_block { $$ = $1; }
+ | constants_block { $$ = $1; }
+ | sources_block { $$ = $1; }
+ ;
+
+options_block : "options" '{' const_def_list '}'
+ {
+ $$ = new OptionsBlockASTNode(dynamic_cast<ListASTNode *>($3));
+ }
+ ;
+
+constants_block : "constants" '{' const_def_list '}'
+ {
+ $$ = new ConstantsBlockASTNode(dynamic_cast<ListASTNode *>($3));
+ }
+ ;
+
+const_def_list : const_def_list_elem
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode($1);
+ $$ = list;
+ }
+ | const_def_list const_def_list_elem
+ {
+ dynamic_cast<ListASTNode*>($1)->appendNode($2);
+ $$ = $1;
+ }
+ ;
+
+const_def_list_elem : const_def ';' { $$ = $1; }
+ | /* empty */ { $$ = NULL; }
+ ;
+
+const_def : TOK_IDENT '=' const_expr
+ {
+ $$ = new AssignmentASTNode($1, $3);
+ $$->setLocation(@1, @3);
+ }
+ ;
+
+sources_block : "sources" '{' source_def_list '}'
+ {
+ $$ = new SourcesBlockASTNode(dynamic_cast<ListASTNode *>($3));
+ }
+ ;
+
+source_def_list : source_def_list_elem
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode($1);
+ $$ = list;
+ }
+ | source_def_list source_def_list_elem
+ {
+ dynamic_cast<ListASTNode*>($1)->appendNode($2);
+ $$ = $1;
+ }
+ ;
+
+source_def_list_elem
+ : source_def source_attrs_opt ';'
+ {
+ // tell the lexer that this is the name of a source file
+ SourceDefASTNode * node = dynamic_cast<SourceDefASTNode*>($1);
+ if ($2)
+ {
+ node->setAttributes(dynamic_cast<ListASTNode*>($2));
+ }
+ node->setLocation(node->getLocation(), @3);
+ lexer->addSourceName(node->getName());
+ $$ = $1;
+ }
+ | /* empty */ { $$ = NULL; }
+ ;
+
+source_def : TOK_IDENT '=' TOK_STRING_LITERAL
+ {
+ $$ = new PathSourceDefASTNode($1, $3);
+ $$->setLocation(@1, @3);
+ }
+ | TOK_IDENT '=' "extern" '(' int_const_expr ')'
+ {
+ $$ = new ExternSourceDefASTNode($1, dynamic_cast<ExprASTNode*>($5));
+ $$->setLocation(@1, @6);
+ }
+ ;
+
+source_attrs_opt
+ : '(' source_attr_list ')' { $$ = $2; }
+ | /* empty */ { $$ = NULL; }
+ ;
+
+source_attr_list
+ : source_attr_list_elem
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode($1);
+ $$ = list;
+ }
+ | source_attr_list ',' source_attr_list_elem
+ {
+ dynamic_cast<ListASTNode*>($1)->appendNode($3);
+ $$ = $1;
+ }
+ ;
+
+source_attr_list_elem
+ : TOK_IDENT '=' const_expr
+ {
+ $$ = new AssignmentASTNode($1, $3);
+ $$->setLocation(@1, @3);
+ }
+ ;
+
+section_defs : section_def
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode($1);
+ $$ = list;
+ }
+ | section_defs section_def
+ {
+ dynamic_cast<ListASTNode*>($1)->appendNode($2);
+ $$ = $1;
+ }
+ ;
+
+section_def : "section" '(' int_const_expr section_options_opt ')' section_contents
+ {
+ SectionContentsASTNode * sectionNode = dynamic_cast<SectionContentsASTNode*>($6);
+ if (sectionNode)
+ {
+ ExprASTNode * exprNode = dynamic_cast<ExprASTNode*>($3);
+ sectionNode->setSectionNumberExpr(exprNode);
+ sectionNode->setOptions(dynamic_cast<ListASTNode*>($4));
+ sectionNode->setLocation(@1, sectionNode->getLocation());
+ }
+ $$ = $6;
+ }
+ ;
+
+section_options_opt
+ : ';' source_attr_list_opt
+ {
+ $$ = $2;
+ }
+ | /* empty */
+ {
+ $$ = NULL;
+ }
+ ;
+
+source_attr_list_opt
+ : source_attr_list
+ {
+ $$ = $1;
+ }
+ | /* empty */
+ {
+ $$ = NULL;
+ }
+ ;
+
+section_contents
+ : "<=" load_data ';'
+ {
+ DataSectionContentsASTNode * dataSection = new DataSectionContentsASTNode($2);
+ dataSection->setLocation(@1, @3);
+ $$ = dataSection;
+ }
+ | '{' full_stmt_list '}'
+ {
+ ListASTNode * listNode = dynamic_cast<ListASTNode*>($2);
+ $$ = new BootableSectionContentsASTNode(listNode);
+ $$->setLocation(@1, @3);
+ }
+ ;
+
+full_stmt_list : full_stmt_list_elem
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode($1);
+ $$ = list;
+ }
+ | full_stmt_list full_stmt_list_elem
+ {
+ dynamic_cast<ListASTNode*>($1)->appendNode($2);
+ $$ = $1;
+ }
+ ;
+
+full_stmt_list_elem
+ : basic_stmt ';' { $$ = $1; }
+ | from_stmt { $$ = $1; }
+ | if_stmt { $$ = $1; }
+ | /* empty */ { $$ = NULL; }
+ ;
+
+basic_stmt_list : basic_stmt_list_elem
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode($1);
+ $$ = list;
+ }
+ | basic_stmt_list basic_stmt_list_elem
+ {
+ dynamic_cast<ListASTNode*>($1)->appendNode($2);
+ $$ = $1;
+ }
+ ;
+
+basic_stmt_list_elem
+ : basic_stmt ';' { $$ = $1; }
+ | if_stmt { $$ = $1; }
+ | /* empty */ { $$ = NULL; }
+ ;
+
+basic_stmt : load_stmt { $$ = $1; }
+ | call_stmt { $$ = $1; }
+ | mode_stmt { $$ = $1; }
+ | message_stmt { $$ = $1; }
+ ;
+
+load_stmt : "load" dcd_opt load_data load_target_opt
+ {
+ LoadStatementASTNode * stmt = new LoadStatementASTNode();
+ stmt->setData($3);
+ stmt->setTarget($4);
+ // set dcd load flag if the "dcd" keyword was present.
+ if ($2)
+ {
+ stmt->setDCDLoad(true);
+ }
+ // set char locations for the statement
+ if ($4)
+ {
+ stmt->setLocation(@1, @4);
+ }
+ else
+ {
+ stmt->setLocation(@1, @3);
+ }
+ $$ = stmt;
+ }
+ ;
+
+dcd_opt : "dcd"
+ {
+ if (!elftosb::g_enableHABSupport)
+ {
+ yyerror(&yylloc, lexer, resultAST, "HAB features not supported with the selected family");
+ YYABORT;
+ }
+
+ $$ = 1;
+ }
+ | /* empty */ { $$ = 0; }
+
+load_data : int_const_expr
+ {
+ $$ = $1;
+ }
+ | TOK_STRING_LITERAL
+ {
+ $$ = new StringConstASTNode($1);
+ $$->setLocation(@1);
+ }
+ | TOK_SOURCE_NAME
+ {
+ $$ = new SourceASTNode($1);
+ $$->setLocation(@1);
+ }
+ | section_list
+ {
+ $$ = new SectionMatchListASTNode(dynamic_cast<ListASTNode*>($1));
+ $$->setLocation(@1);
+ }
+ | section_list "from" TOK_SOURCE_NAME
+ {
+ $$ = new SectionMatchListASTNode(dynamic_cast<ListASTNode*>($1), $3);
+ $$->setLocation(@1, @3);
+ }
+ | TOK_SOURCE_NAME '[' section_list ']'
+ {
+ $$ = new SectionMatchListASTNode(dynamic_cast<ListASTNode*>($3), $1);
+ $$->setLocation(@1, @4);
+ }
+ | TOK_BLOB
+ {
+ $$ = new BlobConstASTNode($1);
+ $$->setLocation(@1);
+ }
+ | ivt_def
+ {
+ }
+ ;
+
+section_list : section_list_elem
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode($1);
+ $$ = list;
+ }
+ | section_list ',' section_list_elem
+ {
+ dynamic_cast<ListASTNode*>($1)->appendNode($3);
+ $$ = $1;
+ }
+ ;
+
+section_list_elem
+ : TOK_SECTION_NAME
+ {
+ $$ = new SectionASTNode($1, SectionASTNode::kInclude);
+ $$->setLocation(@1);
+ }
+ | '~' TOK_SECTION_NAME
+ {
+ $$ = new SectionASTNode($2, SectionASTNode::kExclude);
+ $$->setLocation(@1, @2);
+ }
+ ;
+
+load_target_opt : '>' load_target
+ {
+ $$ = $2;
+ }
+ | /* empty */
+ {
+ $$ = new NaturalLocationASTNode();
+// $$->setLocation();
+ }
+ ;
+
+load_target : '.'
+ {
+ $$ = new NaturalLocationASTNode();
+ $$->setLocation(@1);
+ }
+ | address_or_range
+ {
+ $$ = $1;
+ }
+ ;
+
+ivt_def : "ivt" '(' assignment_list_opt ')'
+ {
+ IVTConstASTNode * ivt = new IVTConstASTNode();
+ if ($3)
+ {
+ ivt->setFieldAssignments(dynamic_cast<ListASTNode*>($3));
+ }
+ ivt->setLocation(@1, @4);
+ $$ = ivt;
+ }
+ ;
+
+assignment_list_opt : source_attr_list { $$ = $1; }
+ | /* empty */ { $$ = NULL; }
+ ;
+
+call_stmt : call_or_jump call_target call_arg_opt
+ {
+ CallStatementASTNode * stmt = new CallStatementASTNode();
+ switch ($1)
+ {
+ case 1:
+ stmt->setCallType(CallStatementASTNode::kCallType);
+ break;
+ case 2:
+ stmt->setCallType(CallStatementASTNode::kJumpType);
+ break;
+ default:
+ yyerror(&yylloc, lexer, resultAST, "invalid call_or_jump value");
+ YYABORT;
+ break;
+ }
+ stmt->setTarget($2);
+ stmt->setArgument($3);
+ stmt->setIsHAB(false);
+ if ($3)
+ {
+ stmt->setLocation(@1, @3);
+ }
+ else
+ {
+ stmt->setLocation(@1, @2);
+ }
+ $$ = stmt;
+ }
+ | "hab" call_or_jump address_or_range call_arg_opt
+ {
+ if (!elftosb::g_enableHABSupport)
+ {
+ yyerror(&yylloc, lexer, resultAST, "HAB features not supported with the selected family");
+ YYABORT;
+ }
+
+ CallStatementASTNode * stmt = new CallStatementASTNode();
+ switch ($2)
+ {
+ case 1:
+ stmt->setCallType(CallStatementASTNode::kCallType);
+ break;
+ case 2:
+ stmt->setCallType(CallStatementASTNode::kJumpType);
+ break;
+ default:
+ yyerror(&yylloc, lexer, resultAST, "invalid call_or_jump value");
+ YYABORT;
+ break;
+ }
+ stmt->setTarget($3);
+ stmt->setArgument($4);
+ stmt->setIsHAB(true);
+ if ($4)
+ {
+ stmt->setLocation(@1, @4);
+ }
+ else
+ {
+ stmt->setLocation(@1, @3);
+ }
+ $$ = stmt;
+ }
+ ;
+
+call_or_jump : "call" { $$ = 1; }
+ | "jump" { $$ = 2; }
+ ;
+
+call_target : TOK_SOURCE_NAME
+ {
+ $$ = new SymbolASTNode(NULL, $1);
+ $$->setLocation(@1);
+ }
+ | int_const_expr
+ {
+ $$ = new AddressRangeASTNode($1, NULL);
+ $$->setLocation($1);
+ }
+ ;
+
+call_arg_opt : '(' int_const_expr ')' { $$ = $2; }
+ | '(' ')' { $$ = NULL; }
+ | /* empty */ { $$ = NULL; }
+ ;
+
+from_stmt : "from" TOK_SOURCE_NAME '{' basic_stmt_list '}'
+ {
+ $$ = new FromStatementASTNode($2, dynamic_cast<ListASTNode*>($4));
+ $$->setLocation(@1, @5);
+ }
+ ;
+
+mode_stmt : "mode" int_const_expr
+ {
+ $$ = new ModeStatementASTNode(dynamic_cast<ExprASTNode*>($2));
+ $$->setLocation(@1, @2);
+ }
+ ;
+
+message_stmt : "info" TOK_STRING_LITERAL
+ {
+ $$ = new MessageStatementASTNode(MessageStatementASTNode::kInfo, $2);
+ $$->setLocation(@1, @2);
+ }
+ | "warning" TOK_STRING_LITERAL
+ {
+ $$ = new MessageStatementASTNode(MessageStatementASTNode::kWarning, $2);
+ $$->setLocation(@1, @2);
+ }
+ | "error" TOK_STRING_LITERAL
+ {
+ $$ = new MessageStatementASTNode(MessageStatementASTNode::kError, $2);
+ $$->setLocation(@1, @2);
+ }
+ ;
+
+if_stmt : "if" bool_expr '{' full_stmt_list '}' else_opt
+ {
+ IfStatementASTNode * ifStmt = new IfStatementASTNode();
+ ifStmt->setConditionExpr(dynamic_cast<ExprASTNode*>($2));
+ ifStmt->setIfStatements(dynamic_cast<ListASTNode*>($4));
+ ifStmt->setElseStatements(dynamic_cast<ListASTNode*>($6));
+ ifStmt->setLocation(@1, @6);
+ $$ = ifStmt;
+ }
+ ;
+
+else_opt : "else" '{' full_stmt_list '}'
+ {
+ $$ = $3;
+ }
+ | "else" if_stmt
+ {
+ ListASTNode * list = new ListASTNode();
+ list->appendNode($2);
+ $$ = list;
+ $$->setLocation(@1, @2);
+ }
+ | /* empty */ { $$ = NULL; }
+ ;
+
+address_or_range : int_const_expr
+ {
+ $$ = new AddressRangeASTNode($1, NULL);
+ $$->setLocation($1);
+ }
+ | int_const_expr ".." int_const_expr
+ {
+ $$ = new AddressRangeASTNode($1, $3);
+ $$->setLocation(@1, @3);
+ }
+ ;
+
+const_expr : bool_expr
+ {
+ $$ = $1;
+ }
+ | TOK_STRING_LITERAL
+ {
+ $$ = new StringConstASTNode($1);
+ $$->setLocation(@1);
+ }
+ ;
+
+bool_expr : int_const_expr
+ {
+ $$ = $1;
+ }
+ | bool_expr '<' bool_expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kLessThan, right);
+ $$->setLocation(@1, @3);
+ }
+ | bool_expr '>' bool_expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kGreaterThan, right);
+ $$->setLocation(@1, @3);
+ }
+ | bool_expr ">=" bool_expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kGreaterThanEqual, right);
+ $$->setLocation(@1, @3);
+ }
+ | bool_expr "<=" bool_expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kLessThanEqual, right);
+ $$->setLocation(@1, @3);
+ }
+ | bool_expr "==" bool_expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kEqual, right);
+ $$->setLocation(@1, @3);
+ }
+ | bool_expr "!=" bool_expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kNotEqual, right);
+ $$->setLocation(@1, @3);
+ }
+ | bool_expr "&&" bool_expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kBooleanAnd, right);
+ $$->setLocation(@1, @3);
+ }
+ | bool_expr "||" bool_expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kBooleanOr, right);
+ $$->setLocation(@1, @3);
+ }
+ | '!' bool_expr %prec UNARY_OP
+ {
+ $$ = new BooleanNotExprASTNode(dynamic_cast<ExprASTNode*>($2));
+ $$->setLocation(@1, @2);
+ }
+ | TOK_IDENT '(' TOK_SOURCE_NAME ')'
+ {
+ $$ = new SourceFileFunctionASTNode($1, $3);
+ $$->setLocation(@1, @4);
+ }
+ | '(' bool_expr ')'
+ {
+ $$ = $2;
+ $$->setLocation(@1, @3);
+ }
+ | "defined" '(' TOK_IDENT ')'
+ {
+ $$ = new DefinedOperatorASTNode($3);
+ $$->setLocation(@1, @4);
+ }
+ ;
+
+int_const_expr : expr { $$ = $1; }
+ ;
+
+symbol_ref : TOK_SOURCE_NAME ':' TOK_IDENT
+ {
+ $$ = new SymbolASTNode($3, $1);
+ $$->setLocation(@1, @3);
+ }
+ | ':' TOK_IDENT
+ {
+ $$ = new SymbolASTNode($2);
+ $$->setLocation(@1, @2);
+ }
+ ;
+
+
+expr : int_value
+ {
+ $$ = $1;
+ }
+ | TOK_IDENT
+ {
+ $$ = new VariableExprASTNode($1);
+ $$->setLocation(@1);
+ }
+ | symbol_ref
+ {
+ $$ = new SymbolRefExprASTNode(dynamic_cast<SymbolASTNode*>($1));
+ $$->setLocation(@1);
+ }
+/* | expr '..' expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new RangeExprASTNode(left, right);
+ }
+*/ | expr '+' expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kAdd, right);
+ $$->setLocation(@1, @3);
+ }
+ | expr '-' expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kSubtract, right);
+ $$->setLocation(@1, @3);
+ }
+ | expr '*' expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kMultiply, right);
+ $$->setLocation(@1, @3);
+ }
+ | expr '/' expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kDivide, right);
+ $$->setLocation(@1, @3);
+ }
+ | expr '%' expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kModulus, right);
+ $$->setLocation(@1, @3);
+ }
+ | expr "**" expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kPower, right);
+ $$->setLocation(@1, @3);
+ }
+ | expr '&' expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kBitwiseAnd, right);
+ $$->setLocation(@1, @3);
+ }
+ | expr '|' expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kBitwiseOr, right);
+ $$->setLocation(@1, @3);
+ }
+ | expr '^' expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kBitwiseXor, right);
+ $$->setLocation(@1, @3);
+ }
+ | expr "<<" expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kShiftLeft, right);
+ $$->setLocation(@1, @3);
+ }
+ | expr ">>" expr
+ {
+ ExprASTNode * left = dynamic_cast<ExprASTNode*>($1);
+ ExprASTNode * right = dynamic_cast<ExprASTNode*>($3);
+ $$ = new BinaryOpExprASTNode(left, BinaryOpExprASTNode::kShiftRight, right);
+ $$->setLocation(@1, @3);
+ }
+ | unary_expr
+ {
+ $$ = $1;
+ }
+ | expr '.' TOK_INT_SIZE
+ {
+ $$ = new IntSizeExprASTNode(dynamic_cast<ExprASTNode*>($1), $3->getWordSize());
+ $$->setLocation(@1, @3);
+ }
+ | '(' expr ')'
+ {
+ $$ = $2;
+ $$->setLocation(@1, @3);
+ }
+ | "sizeof" '(' symbol_ref ')'
+ {
+ $$ = new SizeofOperatorASTNode(dynamic_cast<SymbolASTNode*>($3));
+ $$->setLocation(@1, @4);
+ }
+ | "sizeof" '(' TOK_IDENT ')'
+ {
+ $$ = new SizeofOperatorASTNode($3);
+ $$->setLocation(@1, @4);
+ }
+ | "sizeof" '(' TOK_SOURCE_NAME ')'
+ {
+ $$ = new SizeofOperatorASTNode($3);
+ $$->setLocation(@1, @4);
+ }
+ ;
+
+unary_expr : '+' expr %prec UNARY_OP
+ {
+ $$ = $2;
+ }
+ | '-' expr %prec UNARY_OP
+ {
+ $$ = new NegativeExprASTNode(dynamic_cast<ExprASTNode*>($2));
+ $$->setLocation(@1, @2);
+ }
+ ;
+
+int_value : TOK_INT_LITERAL
+ {
+ $$ = new IntConstExprASTNode($1->getValue(), $1->getWordSize());
+ $$->setLocation(@1);
+ }
+ ;
+
+%%
+
+/* code goes here */
+
+static int yylex(YYSTYPE * lvalp, YYLTYPE * yylloc, ElftosbLexer * lexer)
+{
+ int token = lexer->yylex();
+ *yylloc = lexer->getLocation();
+ lexer->getSymbolValue(lvalp);
+ return token;
+}
+
+static void yyerror(YYLTYPE * yylloc, ElftosbLexer * lexer, CommandFileASTNode ** resultAST, const char * error)
+{
+ throw syntax_error(format_string("line %d: %s\n", yylloc->m_firstLine, error));
+}
+
--- /dev/null
+/*
+ * File: encryptgpk.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "stdafx.h"
+#include <iostream>
+#include <fstream>
+#include <sstream>
+#include <stdlib.h>
+#include <stdexcept>
+#include <stdio.h>
+#include "options.h"
+#include "EncoreBootImage.h"
+#include "smart_ptr.h"
+#include "Logging.h"
+#include "format_string.h"
+#include "Blob.h"
+#include "Random.h"
+#include "rijndael.h"
+
+using namespace elftosb;
+
+//! Size in bytes of the unencrypted group private key.
+#define GPK_LENGTH (40)
+
+//! Size in bytes of the encrypted output data. This size must be modulo 16, the chunk size for the
+//! AES-128 crypto algorithm. The group private key is inserted at offset 16.
+#define OUTPUT_DATA_LENGTH (64)
+
+//! Position in the output data of the first byte of the group private key.
+#define OUTPUT_DATA_GPK_OFFSET (16)
+
+//! The tool's name.
+const char k_toolName[] = "encryptgpk";
+
+//! Current version number for the tool.
+const char k_version[] = "1.0.2";
+
+//! Copyright string.
+const char k_copyright[] = "Copyright (c) 2008 Freescale Semiconductor. All rights reserved.";
+
+//! Default output array name.
+const char k_defaultArrayName[] = "_endDisplay";
+
+//! Definition of command line options.
+static const char * k_optionsDefinition[] = {
+ "?|help",
+ "v|version",
+ "k:key <file>",
+ "z|zero-key",
+ "o:output",
+ "p:prefix",
+ "a:array",
+ "d|debug",
+ "q|quiet",
+ "V|verbose",
+ NULL
+};
+
+//! Help string.
+const char k_usageText[] = "\nOptions:\n\
+ -?/--help Show this help\n\
+ -v/--version Display tool version\n\
+ -k/--key <file> Add OTP key used for decryption\n\
+ -z/--zero-key Add default key of all zeroes\n\
+ -o/--output <file> Write output to this file\n\
+ -p/--prefix <prefix> Set the output array prefix\n\
+ -a/--array <name> Specify the output array name\n\
+ -d/--debug Enable debug output\n\
+ -q/--quiet Output only warnings and errors\n\
+ -V/--verbose Print extra detailed log information\n\n";
+
+//! Init vector used for CBC encrypting the output data.
+static const uint8_t kInitVector[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+
+//! An array of strings.
+typedef std::vector<std::string> string_vector_t;
+
+// prototypes
+int main(int argc, char* argv[], char* envp[]);
+
+/*!
+ * \brief Class that encapsulates the sbtool interface.
+ *
+ * A single global logger instance is created during object construction. It is
+ * never freed because we need it up to the last possible minute, when an
+ * exception could be thrown.
+ */
+class encryptgpk
+{
+protected:
+ int m_argc; //!< Number of command line arguments.
+ char ** m_argv; //!< String value for each command line argument.
+ StdoutLogger * m_logger; //!< Singleton logger instance.
+ string_vector_t m_keyFilePaths; //!< Paths to OTP key files.
+ string_vector_t m_positionalArgs; //!< Arguments coming after explicit options.
+ bool m_isVerbose; //!< Whether the verbose flag was turned on.
+ bool m_useDefaultKey; //!< Include a default (zero) crypto key.
+ std::string m_outputPath; //!< Path to output file.
+ std::string m_gpkPath; //!< Path to input group private key file.
+ std::string m_outputPrefix; //!< Prefix to the output array.
+ std::string m_arrayName; //!< Output array's name.
+
+public:
+ /*!
+ * Constructor.
+ *
+ * Creates the singleton logger instance.
+ */
+ encryptgpk(int argc, char * argv[])
+ : m_argc(argc),
+ m_argv(argv),
+ m_logger(0),
+ m_keyFilePaths(),
+ m_positionalArgs(),
+ m_isVerbose(false),
+ m_useDefaultKey(false),
+ m_outputPath(),
+ m_gpkPath(),
+ m_outputPrefix(),
+ m_arrayName(k_defaultArrayName)
+ {
+ // create logger instance
+ m_logger = new StdoutLogger();
+ m_logger->setFilterLevel(Logger::INFO);
+ Log::setLogger(m_logger);
+ }
+
+ /*!
+ * Destructor.
+ */
+ ~encryptgpk()
+ {
+ }
+
+ /*!
+ * Reads the command line options passed into the constructor.
+ *
+ * This method can return a return code to its caller, which will cause the
+ * tool to exit immediately with that return code value. Normally, though, it
+ * will return -1 to signal that the tool should continue to execute and
+ * all options were processed successfully.
+ *
+ * The Options class is used to parse command line options. See
+ * #k_optionsDefinition for the list of options and #k_usageText for the
+ * descriptive help for each option.
+ *
+ * \retval -1 The options were processed successfully. Let the tool run normally.
+ * \return A zero or positive result is a return code value that should be
+ * returned from the tool as it exits immediately.
+ */
+ int processOptions()
+ {
+ Options options(*m_argv, k_optionsDefinition);
+ OptArgvIter iter(--m_argc, ++m_argv);
+
+ // process command line options
+ int optchar;
+ const char * optarg;
+ while (optchar = options(iter, optarg))
+ {
+ switch (optchar)
+ {
+ case '?':
+ printUsage(options);
+ return 0;
+
+ case 'v':
+ printf("%s %s\n%s\n", k_toolName, k_version, k_copyright);
+ return 0;
+
+ case 'k':
+ m_keyFilePaths.push_back(optarg);
+ break;
+
+ case 'z':
+ m_useDefaultKey = true;
+ break;
+
+ case 'o':
+ m_outputPath = optarg;
+ break;
+
+ case 'p':
+ m_outputPrefix = optarg;
+ break;
+
+ case 'a':
+ m_arrayName = optarg;
+ break;
+
+ case 'd':
+ Log::getLogger()->setFilterLevel(Logger::DEBUG);
+ break;
+
+ case 'q':
+ Log::getLogger()->setFilterLevel(Logger::WARNING);
+ break;
+
+ case 'V':
+ m_isVerbose = true;
+ break;
+
+ default:
+ Log::log(Logger::ERROR, "error: unrecognized option\n\n");
+ printUsage(options);
+ return 1;
+ }
+ }
+
+ // handle positional args
+ if (iter.index() < m_argc)
+ {
+// Log::SetOutputLevel leveler(Logger::DEBUG);
+// Log::log("positional args:\n");
+ int i;
+ for (i = iter.index(); i < m_argc; ++i)
+ {
+// Log::log("%d: %s\n", i - iter.index(), m_argv[i]);
+ m_positionalArgs.push_back(m_argv[i]);
+ }
+ }
+
+ // all is well
+ return -1;
+ }
+
+ /*!
+ * Prints help for the tool.
+ */
+ void printUsage(Options & options)
+ {
+ options.usage(std::cout, "gpk-file");
+ printf(k_usageText, k_toolName);
+ }
+
+ /*!
+ * Core of the tool. Calls processOptions() to handle command line options
+ * before performing the real work the tool does.
+ */
+ int run()
+ {
+ try
+ {
+ // read command line options
+ int result;
+ if ((result = processOptions()) != -1)
+ {
+ return result;
+ }
+
+ // set verbose logging
+ setVerboseLogging();
+
+ // make sure a file was provided
+ if (m_positionalArgs.size() < 1)
+ {
+ throw std::runtime_error("no input file path was provided");
+ }
+
+ // Make sure at least one key was specified.
+ if (m_keyFilePaths.size() == 0 && m_useDefaultKey == false)
+ {
+ throw std::runtime_error("no crypto key was specified");
+ }
+
+ // Do the work.
+ generateOutput();
+ }
+ catch (std::exception & e)
+ {
+ Log::log(Logger::ERROR, "error: %s\n", e.what());
+ return 1;
+ }
+ catch (...)
+ {
+ Log::log(Logger::ERROR, "error: unexpected exception\n");
+ return 1;
+ }
+
+ return 0;
+ }
+
+ /*!
+ * \brief Builds the output data blob, encrypts it, and writes it to the output file.
+ */
+ void generateOutput()
+ {
+ // Create the output data blob and set it to the correct size.
+ Blob data;
+ data.setLength(OUTPUT_DATA_LENGTH);
+
+ // Fill it with random values.
+ RandomNumberGenerator rng;
+ rng.generateBlock(data.getData(), OUTPUT_DATA_LENGTH);
+
+ // Read the GPK and overlay it into the output data.
+ // The first positional arg is the GPK file path.
+ Blob gpk = readGPK(m_positionalArgs[0]);
+ memcpy(data.getData() + OUTPUT_DATA_GPK_OFFSET, gpk.getData(), GPK_LENGTH);
+
+ // This is the key object for our crypto key.
+ AESKey<128> cryptoKey = readKeyFile();
+
+ // Read the key file.
+ // Encrypt the output data block.
+ Rijndael cipher;
+ cipher.init(Rijndael::CBC, Rijndael::Encrypt, cryptoKey, Rijndael::Key16Bytes, (uint8_t *)&kInitVector);
+ cipher.blockEncrypt(data.getData(), OUTPUT_DATA_LENGTH * 8, data.getData());
+
+ // Open the output file.
+ std::ofstream outputStream(m_outputPath.c_str(), std::ios_base::out | std::ios_base::trunc);
+ if (!outputStream.is_open())
+ {
+ throw std::runtime_error(format_string("could not open output file %s", m_outputPath.c_str()));
+ }
+
+ writeCArray(outputStream, data);
+ }
+
+ /*!
+ * \brief Reads the group private key binary data.
+ */
+ Blob readGPK(std::string & path)
+ {
+ std::ifstream stream(path.c_str(), std::ios_base::in | std::ios_base::binary);
+ if (!stream.is_open())
+ {
+ throw std::runtime_error("could not open group private key file");
+ }
+
+ Blob gpk;
+ gpk.setLength(GPK_LENGTH);
+
+ stream.read((char *)gpk.getData(), GPK_LENGTH);
+
+ return gpk;
+ }
+
+ /*!
+ * \brief Returns a key object based on the user's specified key.
+ */
+ AESKey<128> readKeyFile()
+ {
+ if (m_keyFilePaths.size() > 0)
+ {
+ // Open the key file.
+ std::string & keyPath = m_keyFilePaths[0];
+ std::ifstream keyStream(keyPath.c_str(), std::ios_base::in);
+ if (!keyStream.is_open())
+ {
+ throw std::runtime_error(format_string("unable to read key file %s\n", keyPath.c_str()));
+ }
+ keyStream.seekg(0);
+
+ // Read the first key in the file.
+ AESKey<128> key(keyStream);
+ return key;
+ }
+
+ // Otherwise, create a zero key and return it.
+ AESKey<128> defaultKey;
+ return defaultKey;
+
+ }
+
+ /*!
+ * \brief Writes the given data blob as an array in a C source file.
+ */
+ void writeCArray(std::ofstream & stream, const Blob & data)
+ {
+ const uint8_t * dataPtr = data.getData();
+ unsigned length = data.getLength();
+
+ // Write first line.
+ std::string text = format_string("%s%sunsigned char %s[%d] = {", m_outputPrefix.c_str(), m_outputPrefix.size() > 0 ? " " : "", m_arrayName.c_str(), length);
+ stream.write(text.c_str(), text.size());
+
+ // Write each word of the array.
+ unsigned i = 0;
+ while (i < length)
+ {
+ // Insert a comma at the end of the previous line unless this is the first word we're outputting.
+ text = format_string("%s\n 0x%02x", i == 0 ? "" : ",", (*dataPtr++) & 0xff);
+ stream.write(text.c_str(), text.size());
+
+ i++;
+ }
+
+ // Write last line, terminating the array.
+ text = "\n};\n\n";
+ stream.write(text.c_str(), text.size());
+ }
+
+ /*!
+ * \brief Turns on verbose logging.
+ */
+ void setVerboseLogging()
+ {
+ if (m_isVerbose)
+ {
+ // verbose only affects the INFO and DEBUG filter levels
+ // if the user has selected quiet mode, it overrides verbose
+ switch (Log::getLogger()->getFilterLevel())
+ {
+ case Logger::INFO:
+ Log::getLogger()->setFilterLevel(Logger::INFO2);
+ break;
+ case Logger::DEBUG:
+ Log::getLogger()->setFilterLevel(Logger::DEBUG2);
+ break;
+ }
+ }
+ }
+
+};
+
+/*!
+ * Main application entry point. Creates an sbtool instance and lets it take over.
+ */
+int main(int argc, char* argv[], char* envp[])
+{
+ try
+ {
+ return encryptgpk(argc, argv).run();
+ }
+ catch (...)
+ {
+ Log::log(Logger::ERROR, "error: unexpected exception\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+
+
+
+
--- /dev/null
+<?xml version="1.0" encoding="Windows-1252"?>\r
+<VisualStudioProject\r
+ ProjectType="Visual C++"\r
+ Version="9.00"\r
+ Name="encryptgpk"\r
+ ProjectGUID="{5C28390B-78FC-4484-BBB5-E425F9852CCE}"\r
+ Keyword="Win32Proj"\r
+ TargetFrameworkVersion="131072"\r
+ >\r
+ <Platforms>\r
+ <Platform\r
+ Name="Win32"\r
+ />\r
+ </Platforms>\r
+ <ToolFiles>\r
+ </ToolFiles>\r
+ <Configurations>\r
+ <Configuration\r
+ Name="Debug|Win32"\r
+ OutputDirectory="Debug"\r
+ IntermediateDirectory="Debug"\r
+ ConfigurationType="1"\r
+ InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops"\r
+ CharacterSet="2"\r
+ >\r
+ <Tool\r
+ Name="VCPreBuildEventTool"\r
+ />\r
+ <Tool\r
+ Name="VCCustomBuildTool"\r
+ />\r
+ <Tool\r
+ Name="VCXMLDataGeneratorTool"\r
+ />\r
+ <Tool\r
+ Name="VCWebServiceProxyGeneratorTool"\r
+ />\r
+ <Tool\r
+ Name="VCMIDLTool"\r
+ />\r
+ <Tool\r
+ Name="VCCLCompilerTool"\r
+ Optimization="0"\r
+ AdditionalIncludeDirectories="..\winsupport;..\common"\r
+ PreprocessorDefinitions="WIN32;_DEBUG;_CONSOLE"\r
+ MinimalRebuild="true"\r
+ BasicRuntimeChecks="3"\r
+ RuntimeLibrary="1"\r
+ UsePrecompiledHeader="0"\r
+ WarningLevel="3"\r
+ Detect64BitPortabilityProblems="true"\r
+ DebugInformationFormat="4"\r
+ />\r
+ <Tool\r
+ Name="VCManagedResourceCompilerTool"\r
+ />\r
+ <Tool\r
+ Name="VCResourceCompilerTool"\r
+ />\r
+ <Tool\r
+ Name="VCPreLinkEventTool"\r
+ />\r
+ <Tool\r
+ Name="VCLinkerTool"\r
+ OutputFile="$(OutDir)/encryptgpk.exe"\r
+ LinkIncremental="2"\r
+ GenerateDebugInformation="true"\r
+ ProgramDatabaseFile="$(OutDir)/encryptgpk.pdb"\r
+ SubSystem="1"\r
+ RandomizedBaseAddress="1"\r
+ DataExecutionPrevention="0"\r
+ TargetMachine="1"\r
+ />\r
+ <Tool\r
+ Name="VCALinkTool"\r
+ />\r
+ <Tool\r
+ Name="VCManifestTool"\r
+ />\r
+ <Tool\r
+ Name="VCXDCMakeTool"\r
+ />\r
+ <Tool\r
+ Name="VCBscMakeTool"\r
+ />\r
+ <Tool\r
+ Name="VCFxCopTool"\r
+ />\r
+ <Tool\r
+ Name="VCAppVerifierTool"\r
+ />\r
+ <Tool\r
+ Name="VCPostBuildEventTool"\r
+ />\r
+ </Configuration>\r
+ <Configuration\r
+ Name="Release|Win32"\r
+ OutputDirectory="Release"\r
+ IntermediateDirectory="Release"\r
+ ConfigurationType="1"\r
+ InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops"\r
+ CharacterSet="2"\r
+ >\r
+ <Tool\r
+ Name="VCPreBuildEventTool"\r
+ />\r
+ <Tool\r
+ Name="VCCustomBuildTool"\r
+ />\r
+ <Tool\r
+ Name="VCXMLDataGeneratorTool"\r
+ />\r
+ <Tool\r
+ Name="VCWebServiceProxyGeneratorTool"\r
+ />\r
+ <Tool\r
+ Name="VCMIDLTool"\r
+ />\r
+ <Tool\r
+ Name="VCCLCompilerTool"\r
+ AdditionalIncludeDirectories="..\winsupport;..\common"\r
+ PreprocessorDefinitions="WIN32;NDEBUG;_CONSOLE"\r
+ RuntimeLibrary="0"\r
+ UsePrecompiledHeader="0"\r
+ WarningLevel="3"\r
+ Detect64BitPortabilityProblems="true"\r
+ DebugInformationFormat="3"\r
+ />\r
+ <Tool\r
+ Name="VCManagedResourceCompilerTool"\r
+ />\r
+ <Tool\r
+ Name="VCResourceCompilerTool"\r
+ />\r
+ <Tool\r
+ Name="VCPreLinkEventTool"\r
+ />\r
+ <Tool\r
+ Name="VCLinkerTool"\r
+ OutputFile="$(OutDir)/encryptgpk.exe"\r
+ LinkIncremental="1"\r
+ GenerateDebugInformation="true"\r
+ SubSystem="1"\r
+ OptimizeReferences="2"\r
+ EnableCOMDATFolding="2"\r
+ RandomizedBaseAddress="1"\r
+ DataExecutionPrevention="0"\r
+ TargetMachine="1"\r
+ />\r
+ <Tool\r
+ Name="VCALinkTool"\r
+ />\r
+ <Tool\r
+ Name="VCManifestTool"\r
+ />\r
+ <Tool\r
+ Name="VCXDCMakeTool"\r
+ />\r
+ <Tool\r
+ Name="VCBscMakeTool"\r
+ />\r
+ <Tool\r
+ Name="VCFxCopTool"\r
+ />\r
+ <Tool\r
+ Name="VCAppVerifierTool"\r
+ />\r
+ <Tool\r
+ Name="VCPostBuildEventTool"\r
+ />\r
+ </Configuration>\r
+ </Configurations>\r
+ <References>\r
+ </References>\r
+ <Files>\r
+ <Filter\r
+ Name="Source Files"\r
+ Filter="cpp;c;cxx;def;odl;idl;hpj;bat;asm;asmx"\r
+ UniqueIdentifier="{4FC737F1-C7A5-4376-A066-2A32D752A2FF}"\r
+ >\r
+ <File\r
+ RelativePath=".\encryptgpk.cpp"\r
+ >\r
+ </File>\r
+ <Filter\r
+ Name="common"\r
+ >\r
+ <File\r
+ RelativePath="..\common\AESKey.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Blob.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\crc.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\format_string.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\HexValues.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Logging.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\options.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Random.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\rijndael.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\RijndaelCBCMAC.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SearchPath.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SHA1.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\stdafx.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Value.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Version.cpp"\r
+ >\r
+ </File>\r
+ </Filter>\r
+ </Filter>\r
+ <Filter\r
+ Name="Header Files"\r
+ Filter="h;hpp;hxx;hm;inl;inc;xsd"\r
+ UniqueIdentifier="{93995380-89BD-4b04-88EB-625FBE52EBFB}"\r
+ >\r
+ <Filter\r
+ Name="common"\r
+ >\r
+ <File\r
+ RelativePath="..\common\AESKey.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Blob.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\BootImage.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\crc.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\ELF.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\EndianUtilities.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\format_string.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\HexValues.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\int_size.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Logging.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\options.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Random.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\rijndael.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\RijndaelCBCMAC.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SearchPath.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SHA1.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\smart_ptr.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\stdafx.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Value.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Version.h"\r
+ >\r
+ </File>\r
+ </Filter>\r
+ </Filter>\r
+ <Filter\r
+ Name="Resource Files"\r
+ Filter="rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx"\r
+ UniqueIdentifier="{67DA6AB6-F800-4c08-8B7A-83BB121AAD01}"\r
+ >\r
+ </Filter>\r
+ </Files>\r
+ <Globals>\r
+ </Globals>\r
+</VisualStudioProject>\r
--- /dev/null
+# Doxyfile 1.3.9
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+PROJECT_NAME = sbtool
+PROJECT_NUMBER = 1.0
+OUTPUT_DIRECTORY = .
+CREATE_SUBDIRS = YES
+OUTPUT_LANGUAGE = English
+USE_WINDOWS_ENCODING = YES
+BRIEF_MEMBER_DESC = YES
+REPEAT_BRIEF = YES
+ABBREVIATE_BRIEF = "The $name class" \
+ "The $name widget" \
+ "The $name file" \
+ is \
+ provides \
+ specifies \
+ contains \
+ represents \
+ a \
+ an \
+ the
+ALWAYS_DETAILED_SEC = NO
+INLINE_INHERITED_MEMB = NO
+FULL_PATH_NAMES = NO
+STRIP_FROM_PATH = "/Users/creed/projects/elftosb/sbtool" \
+ "/Users/creed/projects/sgtl/elftosb/sbtool" \
+ "/Users/creed/projects/elftosb/common" \
+ "/Users/creed/projects/sgtl/elftosb/common"
+STRIP_FROM_INC_PATH =
+SHORT_NAMES = NO
+JAVADOC_AUTOBRIEF = NO
+MULTILINE_CPP_IS_BRIEF = NO
+DETAILS_AT_TOP = YES
+INHERIT_DOCS = YES
+DISTRIBUTE_GROUP_DOC = NO
+TAB_SIZE = 4
+ALIASES =
+OPTIMIZE_OUTPUT_FOR_C = NO
+OPTIMIZE_OUTPUT_JAVA = NO
+SUBGROUPING = YES
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL = YES
+EXTRACT_PRIVATE = YES
+EXTRACT_STATIC = YES
+EXTRACT_LOCAL_CLASSES = YES
+EXTRACT_LOCAL_METHODS = NO
+HIDE_UNDOC_MEMBERS = NO
+HIDE_UNDOC_CLASSES = NO
+HIDE_FRIEND_COMPOUNDS = NO
+HIDE_IN_BODY_DOCS = NO
+INTERNAL_DOCS = NO
+CASE_SENSE_NAMES = NO
+HIDE_SCOPE_NAMES = NO
+SHOW_INCLUDE_FILES = YES
+INLINE_INFO = YES
+SORT_MEMBER_DOCS = YES
+SORT_BRIEF_DOCS = NO
+SORT_BY_SCOPE_NAME = NO
+GENERATE_TODOLIST = YES
+GENERATE_TESTLIST = YES
+GENERATE_BUGLIST = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS =
+MAX_INITIALIZER_LINES = 30
+SHOW_USED_FILES = YES
+SHOW_DIRECTORIES = YES
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET = NO
+WARNINGS = YES
+WARN_IF_UNDOCUMENTED = YES
+WARN_IF_DOC_ERROR = YES
+WARN_FORMAT = "$file:$line: $text"
+WARN_LOGFILE =
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT = . ../common
+FILE_PATTERNS = *.c \
+ *.cc \
+ *.cxx \
+ *.cpp \
+ *.c++ \
+ *.java \
+ *.ii \
+ *.ixx \
+ *.ipp \
+ *.i++ \
+ *.inl \
+ *.h \
+ *.hh \
+ *.hxx \
+ *.hpp \
+ *.h++ \
+ *.idl \
+ *.odl \
+ *.cs \
+ *.php \
+ *.php3 \
+ *.inc \
+ *.m \
+ *.mm
+RECURSIVE = NO
+EXCLUDE =
+EXCLUDE_SYMLINKS = NO
+EXCLUDE_PATTERNS =
+EXAMPLE_PATH =
+EXAMPLE_PATTERNS = *
+EXAMPLE_RECURSIVE = NO
+IMAGE_PATH =
+INPUT_FILTER =
+FILTER_PATTERNS =
+FILTER_SOURCE_FILES = NO
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER = NO
+INLINE_SOURCES = NO
+STRIP_CODE_COMMENTS = YES
+REFERENCED_BY_RELATION = NO
+REFERENCES_RELATION = NO
+VERBATIM_HEADERS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX = NO
+COLS_IN_ALPHA_INDEX = 5
+IGNORE_PREFIX =
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML = YES
+HTML_OUTPUT = html
+HTML_FILE_EXTENSION = .html
+HTML_HEADER =
+HTML_FOOTER =
+HTML_STYLESHEET =
+HTML_ALIGN_MEMBERS = YES
+GENERATE_HTMLHELP = NO
+CHM_FILE =
+HHC_LOCATION =
+GENERATE_CHI = NO
+BINARY_TOC = NO
+TOC_EXPAND = NO
+DISABLE_INDEX = NO
+ENUM_VALUES_PER_LINE = 4
+GENERATE_TREEVIEW = YES
+TREEVIEW_WIDTH = 250
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX = NO
+LATEX_OUTPUT = latex
+LATEX_CMD_NAME = latex
+MAKEINDEX_CMD_NAME = makeindex
+COMPACT_LATEX = NO
+PAPER_TYPE = a4wide
+EXTRA_PACKAGES =
+LATEX_HEADER =
+PDF_HYPERLINKS = NO
+USE_PDFLATEX = NO
+LATEX_BATCHMODE = NO
+LATEX_HIDE_INDICES = NO
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF = NO
+RTF_OUTPUT = rtf
+COMPACT_RTF = NO
+RTF_HYPERLINKS = NO
+RTF_STYLESHEET_FILE =
+RTF_EXTENSIONS_FILE =
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN = NO
+MAN_OUTPUT = man
+MAN_EXTENSION = .3
+MAN_LINKS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML = NO
+XML_OUTPUT = xml
+XML_SCHEMA =
+XML_DTD =
+XML_PROGRAMLISTING = YES
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF = NO
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD = NO
+PERLMOD_LATEX = NO
+PERLMOD_PRETTY = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING = YES
+MACRO_EXPANSION = NO
+EXPAND_ONLY_PREDEF = NO
+SEARCH_INCLUDES = YES
+INCLUDE_PATH =
+INCLUDE_FILE_PATTERNS =
+PREDEFINED =
+EXPAND_AS_DEFINED =
+SKIP_FUNCTION_MACROS = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+TAGFILES =
+GENERATE_TAGFILE =
+ALLEXTERNALS = NO
+EXTERNAL_GROUPS = YES
+PERL_PATH = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS = NO
+HIDE_UNDOC_RELATIONS = YES
+HAVE_DOT = NO
+CLASS_GRAPH = YES
+COLLABORATION_GRAPH = YES
+UML_LOOK = NO
+TEMPLATE_RELATIONS = NO
+INCLUDE_GRAPH = YES
+INCLUDED_BY_GRAPH = YES
+CALL_GRAPH = NO
+GRAPHICAL_HIERARCHY = YES
+DOT_IMAGE_FORMAT = png
+DOT_PATH =
+DOTFILE_DIRS =
+MAX_DOT_GRAPH_WIDTH = 1024
+MAX_DOT_GRAPH_HEIGHT = 1024
+MAX_DOT_GRAPH_DEPTH = 1000
+GENERATE_LEGEND = YES
+DOT_CLEANUP = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to the search engine
+#---------------------------------------------------------------------------
+SEARCHENGINE = NO
--- /dev/null
+/*
+ * File: keygen.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "stdafx.h"
+#include <iostream>
+#include <fstream>
+#include <sstream>
+#include <stdlib.h>
+#include <stdexcept>
+#include <string>
+#include <vector>
+#include "options.h"
+#include "smart_ptr.h"
+#include "Logging.h"
+#include "AESKey.h"
+
+//! The tool's name.
+const char k_toolName[] = "keygen";
+
+//! Current version number for the tool.
+const char k_version[] = "1.0";
+
+//! Copyright string.
+const char k_copyright[] = "Copyright (c) 2006-2009 Freescale Semiconductor, Inc.\nAll rights reserved.";
+
+//! Definition of command line options.
+static const char * k_optionsDefinition[] = {
+ "?|help",
+ "v|version",
+ "q|quiet",
+ "V|verbose",
+ "n:number <int>",
+ NULL
+};
+
+//! Help string.
+const char k_usageText[] = "\nOptions:\n\
+ -?/--help Show this help\n\
+ -v/--version Display tool version\n\
+ -q/--quiet Output only warnings and errors\n\
+ -V/--verbose Print extra detailed log information\n\
+ -n/--number <int> Number of keys to generate per file (default=1)\n\n";
+
+//! An array of strings.
+typedef std::vector<std::string> string_vector_t;
+
+// prototypes
+int main(int argc, char* argv[], char* envp[]);
+
+/*!
+ * \brief Class that encapsulates the keygen interface.
+ *
+ * A single global logger instance is created during object construction. It is
+ * never freed because we need it up to the last possible minute, when an
+ * exception could be thrown.
+ */
+class keygen
+{
+protected:
+ int m_argc; //!< Number of command line arguments.
+ char ** m_argv; //!< String value for each command line argument.
+ StdoutLogger * m_logger; //!< Singleton logger instance.
+ string_vector_t m_positionalArgs; //!< Arguments coming after explicit options.
+ bool m_isVerbose; //!< Whether the verbose flag was turned on.
+ int m_keyCount; //!< Number of keys to generate.
+
+public:
+ /*!
+ * Constructor.
+ *
+ * Creates the singleton logger instance.
+ */
+ keygen(int argc, char * argv[])
+ : m_argc(argc),
+ m_argv(argv),
+ m_logger(0),
+ m_positionalArgs(),
+ m_isVerbose(false),
+ m_keyCount(1)
+ {
+ // create logger instance
+ m_logger = new StdoutLogger();
+ m_logger->setFilterLevel(Logger::INFO);
+ Log::setLogger(m_logger);
+ }
+
+ /*!
+ * Destructor.
+ */
+ ~keygen()
+ {
+ }
+
+ /*!
+ * Reads the command line options passed into the constructor.
+ *
+ * This method can return a return code to its caller, which will cause the
+ * tool to exit immediately with that return code value. Normally, though, it
+ * will return -1 to signal that the tool should continue to execute and
+ * all options were processed successfully.
+ *
+ * The Options class is used to parse command line options. See
+ * #k_optionsDefinition for the list of options and #k_usageText for the
+ * descriptive help for each option.
+ *
+ * \retval -1 The options were processed successfully. Let the tool run normally.
+ * \return A zero or positive result is a return code value that should be
+ * returned from the tool as it exits immediately.
+ */
+ int processOptions()
+ {
+ Options options(*m_argv, k_optionsDefinition);
+ OptArgvIter iter(--m_argc, ++m_argv);
+
+ // process command line options
+ int optchar;
+ const char * optarg;
+ while (optchar = options(iter, optarg))
+ {
+ switch (optchar)
+ {
+ case '?':
+ printUsage(options);
+ return 0;
+
+ case 'v':
+ printf("%s %s\n%s\n", k_toolName, k_version, k_copyright);
+ return 0;
+
+ case 'd':
+ Log::getLogger()->setFilterLevel(Logger::DEBUG);
+ break;
+
+ case 'q':
+ Log::getLogger()->setFilterLevel(Logger::WARNING);
+ break;
+
+ case 'V':
+ m_isVerbose = true;
+ break;
+
+ case 'n':
+ m_keyCount = strtol(optarg, NULL, 0);
+ break;
+
+ default:
+ Log::log(Logger::ERROR, "error: unrecognized option\n\n");
+ printUsage(options);
+ return 1;
+ }
+ }
+
+ // handle positional args
+ if (iter.index() < m_argc)
+ {
+// Log::SetOutputLevel leveler(Logger::DEBUG);
+// Log::log("positional args:\n");
+ int i;
+ for (i = iter.index(); i < m_argc; ++i)
+ {
+// Log::log("%d: %s\n", i - iter.index(), m_argv[i]);
+ m_positionalArgs.push_back(m_argv[i]);
+ }
+ }
+
+ // all is well
+ return -1;
+ }
+
+ /*!
+ * Prints help for the tool.
+ */
+ void printUsage(Options & options)
+ {
+ options.usage(std::cout, "key-files...");
+ printf(k_usageText, k_toolName);
+ }
+
+ /*!
+ * Core of the tool. Calls processOptions() to handle command line options
+ * before performing the real work the tool does.
+ */
+ int run()
+ {
+ try
+ {
+ // read command line options
+ int result;
+ if ((result = processOptions()) != -1)
+ {
+ return result;
+ }
+
+ // set verbose logging
+ setVerboseLogging();
+
+ // make sure a file was provided
+ if (m_positionalArgs.size() < 1)
+ {
+ throw std::runtime_error("no output file path was provided");
+ }
+
+ // generate key files
+ string_vector_t::const_iterator it = m_positionalArgs.begin();
+ for (; it != m_positionalArgs.end(); ++it)
+ {
+ generateKeyFile(*it);
+ }
+ }
+ catch (std::exception & e)
+ {
+ Log::log(Logger::ERROR, "error: %s\n", e.what());
+ return 1;
+ }
+ catch (...)
+ {
+ Log::log(Logger::ERROR, "error: unexpected exception\n");
+ return 1;
+ }
+
+ return 0;
+ }
+
+ /*!
+ * \brief Turns on verbose logging.
+ */
+ void setVerboseLogging()
+ {
+ if (m_isVerbose)
+ {
+ // verbose only affects the INFO and DEBUG filter levels
+ // if the user has selected quiet mode, it overrides verbose
+ switch (Log::getLogger()->getFilterLevel())
+ {
+ case Logger::INFO:
+ Log::getLogger()->setFilterLevel(Logger::INFO2);
+ break;
+ case Logger::DEBUG:
+ Log::getLogger()->setFilterLevel(Logger::DEBUG2);
+ break;
+ }
+ }
+ }
+
+ /*!
+ * \brief Opens the file at \a path and writes a random key file.
+ *
+ * Each key file will have #m_keyCount number of keys written into it,
+ * each on a line by itself.
+ */
+ void generateKeyFile(const std::string & path)
+ {
+ std::ofstream outputStream(path.c_str(), std::ios_base::binary | std::ios_base::out | std::ios_base::trunc);
+ if (outputStream.is_open())
+ {
+ int i;
+ for (i = 0; i < m_keyCount; ++i)
+ {
+ AESKey<128> key;
+ key.randomize();
+ key.writeToStream(outputStream);
+
+ // put a newline after the key
+ outputStream.write("\n", 1);
+
+ // dump it
+ dumpKey(key);
+ }
+
+ Log::log(Logger::INFO, "wrote key file %s\n", path.c_str());
+ }
+ else
+ {
+ throw std::runtime_error("could not open output file");
+ }
+ }
+
+ /*!
+ * \brief Write the value of each byte of the \a key to the log.
+ */
+ void dumpKey(const AESKey<128> & key)
+ {
+ // dump key bytes
+ Log::log(Logger::INFO2, "key bytes: ");
+ AESKey<128>::key_t the_key;
+ key.getKey(&the_key);
+ int q;
+ for (q=0; q<16; q++)
+ {
+ Log::log(Logger::INFO2, "%02x ", the_key[q]);
+ }
+ Log::log(Logger::INFO2, "\n");
+ }
+
+ /*!
+ * \brief Log an array of bytes as hex.
+ */
+ void logHexArray(Logger::log_level_t level, const uint8_t * bytes, unsigned count)
+ {
+ Log::SetOutputLevel leveler(level);
+// Log::log(" ");
+ unsigned i;
+ for (i = 0; i < count; ++i, ++bytes)
+ {
+ if ((i % 16 == 0) && (i < count - 1))
+ {
+ if (i != 0)
+ {
+ Log::log("\n");
+ }
+ Log::log(" 0x%04x: ", i);
+ }
+ Log::log("%02x ", *bytes & 0xff);
+ }
+
+ Log::log("\n");
+ }
+
+};
+
+/*!
+ * Main application entry point. Creates an sbtool instance and lets it take over.
+ */
+int main(int argc, char* argv[], char* envp[])
+{
+ try
+ {
+ return keygen(argc, argv).run();
+ }
+ catch (...)
+ {
+ Log::log(Logger::ERROR, "error: unexpected exception\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+
+
+
+
--- /dev/null
+<?xml version="1.0" encoding="Windows-1252"?>\r
+<VisualStudioProject\r
+ ProjectType="Visual C++"\r
+ Version="9.00"\r
+ Name="keygen"\r
+ ProjectGUID="{09633A11-9AB3-4118-B83A-5D6CAFDBE74F}"\r
+ Keyword="Win32Proj"\r
+ TargetFrameworkVersion="131072"\r
+ >\r
+ <Platforms>\r
+ <Platform\r
+ Name="Win32"\r
+ />\r
+ </Platforms>\r
+ <ToolFiles>\r
+ </ToolFiles>\r
+ <Configurations>\r
+ <Configuration\r
+ Name="Debug|Win32"\r
+ OutputDirectory="Debug"\r
+ IntermediateDirectory="Debug"\r
+ ConfigurationType="1"\r
+ InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops"\r
+ CharacterSet="2"\r
+ >\r
+ <Tool\r
+ Name="VCPreBuildEventTool"\r
+ />\r
+ <Tool\r
+ Name="VCCustomBuildTool"\r
+ />\r
+ <Tool\r
+ Name="VCXMLDataGeneratorTool"\r
+ />\r
+ <Tool\r
+ Name="VCWebServiceProxyGeneratorTool"\r
+ />\r
+ <Tool\r
+ Name="VCMIDLTool"\r
+ />\r
+ <Tool\r
+ Name="VCCLCompilerTool"\r
+ Optimization="0"\r
+ AdditionalIncludeDirectories="..\winsupport;..\elftosb2;..\common"\r
+ PreprocessorDefinitions="WIN32;_DEBUG;_CONSOLE"\r
+ MinimalRebuild="true"\r
+ BasicRuntimeChecks="3"\r
+ RuntimeLibrary="1"\r
+ RuntimeTypeInfo="true"\r
+ UsePrecompiledHeader="0"\r
+ WarningLevel="2"\r
+ Detect64BitPortabilityProblems="true"\r
+ DebugInformationFormat="4"\r
+ DisableSpecificWarnings="4355"\r
+ />\r
+ <Tool\r
+ Name="VCManagedResourceCompilerTool"\r
+ />\r
+ <Tool\r
+ Name="VCResourceCompilerTool"\r
+ />\r
+ <Tool\r
+ Name="VCPreLinkEventTool"\r
+ />\r
+ <Tool\r
+ Name="VCLinkerTool"\r
+ OutputFile="$(OutDir)/keygen.exe"\r
+ LinkIncremental="2"\r
+ GenerateDebugInformation="true"\r
+ ProgramDatabaseFile="$(OutDir)/keygen.pdb"\r
+ SubSystem="1"\r
+ RandomizedBaseAddress="1"\r
+ DataExecutionPrevention="0"\r
+ TargetMachine="1"\r
+ />\r
+ <Tool\r
+ Name="VCALinkTool"\r
+ />\r
+ <Tool\r
+ Name="VCManifestTool"\r
+ />\r
+ <Tool\r
+ Name="VCXDCMakeTool"\r
+ />\r
+ <Tool\r
+ Name="VCBscMakeTool"\r
+ />\r
+ <Tool\r
+ Name="VCFxCopTool"\r
+ />\r
+ <Tool\r
+ Name="VCAppVerifierTool"\r
+ />\r
+ <Tool\r
+ Name="VCPostBuildEventTool"\r
+ />\r
+ </Configuration>\r
+ <Configuration\r
+ Name="Release|Win32"\r
+ OutputDirectory="Release"\r
+ IntermediateDirectory="Release"\r
+ ConfigurationType="1"\r
+ InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops"\r
+ CharacterSet="2"\r
+ >\r
+ <Tool\r
+ Name="VCPreBuildEventTool"\r
+ />\r
+ <Tool\r
+ Name="VCCustomBuildTool"\r
+ />\r
+ <Tool\r
+ Name="VCXMLDataGeneratorTool"\r
+ />\r
+ <Tool\r
+ Name="VCWebServiceProxyGeneratorTool"\r
+ />\r
+ <Tool\r
+ Name="VCMIDLTool"\r
+ />\r
+ <Tool\r
+ Name="VCCLCompilerTool"\r
+ PreprocessorDefinitions="WIN32;NDEBUG;_CONSOLE"\r
+ RuntimeLibrary="0"\r
+ UsePrecompiledHeader="0"\r
+ WarningLevel="3"\r
+ Detect64BitPortabilityProblems="true"\r
+ DebugInformationFormat="3"\r
+ />\r
+ <Tool\r
+ Name="VCManagedResourceCompilerTool"\r
+ />\r
+ <Tool\r
+ Name="VCResourceCompilerTool"\r
+ />\r
+ <Tool\r
+ Name="VCPreLinkEventTool"\r
+ />\r
+ <Tool\r
+ Name="VCLinkerTool"\r
+ OutputFile="$(OutDir)/keygen.exe"\r
+ LinkIncremental="1"\r
+ GenerateDebugInformation="true"\r
+ SubSystem="1"\r
+ OptimizeReferences="2"\r
+ EnableCOMDATFolding="2"\r
+ RandomizedBaseAddress="1"\r
+ DataExecutionPrevention="0"\r
+ TargetMachine="1"\r
+ />\r
+ <Tool\r
+ Name="VCALinkTool"\r
+ />\r
+ <Tool\r
+ Name="VCManifestTool"\r
+ />\r
+ <Tool\r
+ Name="VCXDCMakeTool"\r
+ />\r
+ <Tool\r
+ Name="VCBscMakeTool"\r
+ />\r
+ <Tool\r
+ Name="VCFxCopTool"\r
+ />\r
+ <Tool\r
+ Name="VCAppVerifierTool"\r
+ />\r
+ <Tool\r
+ Name="VCPostBuildEventTool"\r
+ />\r
+ </Configuration>\r
+ </Configurations>\r
+ <References>\r
+ </References>\r
+ <Files>\r
+ <Filter\r
+ Name="Source Files"\r
+ Filter="cpp;c;cxx;def;odl;idl;hpj;bat;asm;asmx"\r
+ UniqueIdentifier="{4FC737F1-C7A5-4376-A066-2A32D752A2FF}"\r
+ >\r
+ <Filter\r
+ Name="keygen"\r
+ >\r
+ <File\r
+ RelativePath=".\keygen.cpp"\r
+ >\r
+ </File>\r
+ </Filter>\r
+ <Filter\r
+ Name="common"\r
+ >\r
+ <File\r
+ RelativePath="..\common\AESKey.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\AESKey.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Blob.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Blob.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\BootImage.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\crc.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\crc.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\DataSource.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\DataSource.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\DataTarget.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\DataTarget.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\ELF.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\ELFSourceFile.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\ELFSourceFile.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\EncoreBootImage.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\EncoreBootImage.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\EndianUtilities.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\EvalContext.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\EvalContext.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\format_string.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\format_string.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\GHSSecInfo.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\GHSSecInfo.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\GlobMatcher.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\GlobMatcher.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\HexValues.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\HexValues.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\int_size.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Logging.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Logging.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Operation.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Operation.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\OptionContext.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\OptionDictionary.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\OptionDictionary.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\options.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\options.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\OutputSection.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\OutputSection.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Random.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Random.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\rijndael.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\rijndael.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\RijndaelCBCMAC.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\RijndaelCBCMAC.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SearchPath.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SearchPath.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SHA1.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SHA1.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\smart_ptr.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SourceFile.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SourceFile.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SRecordSourceFile.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SRecordSourceFile.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\stdafx.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\stdafx.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StELFFile.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StELFFile.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StExecutableImage.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StExecutableImage.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StringMatcher.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StSRecordFile.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StSRecordFile.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Value.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Value.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Version.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Version.h"\r
+ >\r
+ </File>\r
+ </Filter>\r
+ </Filter>\r
+ <Filter\r
+ Name="Header Files"\r
+ Filter="h;hpp;hxx;hm;inl;inc;xsd"\r
+ UniqueIdentifier="{93995380-89BD-4b04-88EB-625FBE52EBFB}"\r
+ >\r
+ </Filter>\r
+ <Filter\r
+ Name="Resource Files"\r
+ Filter="rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx"\r
+ UniqueIdentifier="{67DA6AB6-F800-4c08-8B7A-83BB121AAD01}"\r
+ >\r
+ </Filter>\r
+ </Files>\r
+ <Globals>\r
+ </Globals>\r
+</VisualStudioProject>\r
--- /dev/null
+#*******************************************************************************
+# makefile
+# Description:
+# gnu make makefile for elftosb executable
+
+#*******************************************************************************
+# Environment
+
+# UNAMES is going to be set to either "Linux" or "CYGWIN_NT-5.1"
+UNAMES = $(shell uname -s)
+
+ifeq ("${UNAMES}", "Linux")
+
+SRC_DIR = $(shell pwd)
+BUILD_DIR = bld/linux
+
+else
+ifeq ("${UNAMES}", "CYGWIN_NT-5.1")
+
+SRC_DIR = $(shell pwd)
+BUILD_DIR = bld/cygwin
+
+endif
+endif
+
+
+#*******************************************************************************
+# Targets
+
+all clean elftosb sbtool keygen:
+ @mkdir -p ${BUILD_DIR};
+ make -C ${BUILD_DIR} -f ${SRC_DIR}/makefile.rules SRC_DIR=${SRC_DIR} $@;
--- /dev/null
+#*******************************************************************************
+# makefile.rules
+# Description:
+# gnu make makefile rules for elftosb executable. make needs to be called
+# with the following command:
+#
+# make -C ${BUILD_DIR} -f ${SRC_DIR}/makefile.rules SRC_DIR=${SRC_DIR} $@;
+#
+# SRC_DIR needs to be passed in. It is assumed that make is running in
+# the build directory.
+
+#*******************************************************************************
+# Environment
+
+# UNAMES is going to be set to either "Linux" or "CYGWIN_NT-5.1"
+UNAMES = $(shell uname -s)
+
+#*******************************************************************************
+# Directories
+
+#*******************************************************************************
+# Paths
+
+# search path for source files. make finds them automatically.
+VPATH = \
+ ${SRC_DIR}/common \
+ ${SRC_DIR}/elftosb2 \
+ ${SRC_DIR}/sbtool \
+ ${SRC_DIR}/keygen
+
+# include directories
+INC_PATH = \
+ -I${SRC_DIR}/elftosb2 \
+ -I${SRC_DIR}/keygen \
+ -I${SRC_DIR}/sbtool \
+ -I${SRC_DIR}/common
+
+#*******************************************************************************
+# Build flags
+# gcc Compiler flags
+# -g : Produce debugging information.
+
+CFLAGS = -g $(INC_PATH) -D${UNAMES}
+
+#*******************************************************************************
+# File lists
+
+OBJ_FILES_COMMON = \
+ AESKey.o \
+ Blob.o \
+ crc.o \
+ DataSource.o \
+ DataTarget.o \
+ ELFSourceFile.o \
+ EncoreBootImage.o \
+ EvalContext.o \
+ GHSSecInfo.o \
+ GlobMatcher.o \
+ HexValues.o \
+ Logging.o \
+ Operation.o \
+ OptionDictionary.o \
+ options.o \
+ OutputSection.o \
+ Random.o \
+ RijndaelCBCMAC.o \
+ rijndael.o \
+ SHA1.o \
+ SourceFile.o \
+ SRecordSourceFile.o \
+ stdafx.o \
+ StELFFile.o \
+ StExecutableImage.o \
+ StSRecordFile.o \
+ Value.o \
+ Version.o \
+ format_string.o \
+ ExcludesListMatcher.o \
+ SearchPath.o \
+ DataSourceImager.o \
+ IVTDataSource.o
+
+OBJ_FILES_ELFTOSB2 = \
+ ${OBJ_FILES_COMMON} \
+ BootImageGenerator.o \
+ ConversionController.o \
+ ElftosbAST.o \
+ elftosb.o \
+ elftosb_lexer.o \
+ ElftosbLexer.o \
+ elftosb_parser.tab.o \
+ EncoreBootImageGenerator.o
+
+OBJ_FILES_SBTOOL = \
+ ${OBJ_FILES_COMMON} \
+ EncoreBootImageReader.o \
+ sbtool.o
+
+OBJ_FILES_KEYGEN = \
+ ${OBJ_FILES_COMMON} \
+ keygen.o
+
+
+LIBS = -lstdc++
+
+
+ifeq ("${UNAMES}", "Linux")
+EXEC_FILE_ELFTOSB2 = elftosb
+EXEC_FILE_SBTOOL = sbtool
+EXEC_FILE_KEYGEN = keygen
+else
+ifeq ("${UNAMES}", "CYGWIN_NT-5.1")
+EXEC_FILE_ELFTOSB2 = elftosb.exe
+EXEC_FILE_SBTOOL = sbtool.exe
+EXEC_FILE_KEYGEN = keygen.exe
+endif # ifeq ("${UNAMES}", "CYGWIN_NT-5.1")
+endif # ifeq ("${UNAMES}", "Linux")
+
+
+#*******************************************************************************
+# Targets
+
+all: elftosb sbtool keygen
+
+# Uncomment the next line to print out the environment variables.
+all: exec_always
+
+exec_always:
+ @echo "SRC_DIR = ${SRC_DIR}"
+ @echo "OBJ_FILES = ${OBJ_FILES_ELFTOSB2}"
+ @echo "LIBS = ${LIBS}"
+ @echo "EXEC_FILE = ${EXEC_FILE}"
+ @echo "BUILD_DIR = ${BUILD_DIR}"
+
+clean:
+ rm -f ${OBJ_FILES_ELFTOSB2} ${OBJ_FILES_SBTOOL} ${OBJ_FILES_KEYGEN} \
+ ${EXEC_FILE_ELFTOSB2} ${EXEC_FILE_SBTOOL} ${EXEC_FILE_KEYGEN}
+
+elftosb: ${OBJ_FILES_ELFTOSB2}
+ gcc ${OBJ_FILES_ELFTOSB2} ${LIBS} -o ${EXEC_FILE_ELFTOSB2}
+
+sbtool: ${OBJ_FILES_SBTOOL}
+ gcc ${OBJ_FILES_SBTOOL} ${LIBS} -o ${EXEC_FILE_SBTOOL}
+
+keygen: ${OBJ_FILES_KEYGEN}
+ gcc ${OBJ_FILES_KEYGEN} ${LIBS} -o ${EXEC_FILE_KEYGEN}
+
+
+#ifeq ("${UNAMES}", "Linux")
+#ifeq ("${UNAMES}", "Linux")
+# Use default rules for creating all the .o files from the .c files. Only
+# for linux
+.SUFFIXES : .c .cpp
+
+.c.o :
+ gcc ${CFLAGS} -c $<
+
+.cpp.o :
+ gcc ${CFLAGS} -c $<
+
+#endif
+
+#*******************************************************************************
+# Automatic dependency generation
+
+%.d: %.c
+ @set -e; \
+ $(CC) -MM $(CFLAGS) $< | \
+ sed 's/\($*\)\.o[ :]*/\1.o $@ : /g' > $@; \
+ [ -s $@ ] || rm -f $@
+
+%.d: %.cpp
+ @set -e; \
+ $(CC) -MM $(CFLAGS) $< | \
+ sed 's/\($*\)\.o[ :]*/\1.o $@ : /g' > $@; \
+ [ -s $@ ] || rm -f $@
+
+#*******************************************************************************
--- /dev/null
+# Doxyfile 1.3.9
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+PROJECT_NAME = sbtool
+PROJECT_NUMBER = 1.0
+OUTPUT_DIRECTORY = .
+CREATE_SUBDIRS = YES
+OUTPUT_LANGUAGE = English
+USE_WINDOWS_ENCODING = YES
+BRIEF_MEMBER_DESC = YES
+REPEAT_BRIEF = YES
+ABBREVIATE_BRIEF = "The $name class" \
+ "The $name widget" \
+ "The $name file" \
+ is \
+ provides \
+ specifies \
+ contains \
+ represents \
+ a \
+ an \
+ the
+ALWAYS_DETAILED_SEC = NO
+INLINE_INHERITED_MEMB = NO
+FULL_PATH_NAMES = NO
+STRIP_FROM_PATH = "/Users/creed/projects/elftosb/sbtool" \
+ "/Users/creed/projects/sgtl/elftosb/sbtool" \
+ "/Users/creed/projects/elftosb/common" \
+ "/Users/creed/projects/sgtl/elftosb/common"
+STRIP_FROM_INC_PATH =
+SHORT_NAMES = NO
+JAVADOC_AUTOBRIEF = NO
+MULTILINE_CPP_IS_BRIEF = NO
+DETAILS_AT_TOP = YES
+INHERIT_DOCS = YES
+DISTRIBUTE_GROUP_DOC = NO
+TAB_SIZE = 4
+ALIASES =
+OPTIMIZE_OUTPUT_FOR_C = NO
+OPTIMIZE_OUTPUT_JAVA = NO
+SUBGROUPING = YES
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL = YES
+EXTRACT_PRIVATE = YES
+EXTRACT_STATIC = YES
+EXTRACT_LOCAL_CLASSES = YES
+EXTRACT_LOCAL_METHODS = NO
+HIDE_UNDOC_MEMBERS = NO
+HIDE_UNDOC_CLASSES = NO
+HIDE_FRIEND_COMPOUNDS = NO
+HIDE_IN_BODY_DOCS = NO
+INTERNAL_DOCS = NO
+CASE_SENSE_NAMES = NO
+HIDE_SCOPE_NAMES = NO
+SHOW_INCLUDE_FILES = YES
+INLINE_INFO = YES
+SORT_MEMBER_DOCS = YES
+SORT_BRIEF_DOCS = NO
+SORT_BY_SCOPE_NAME = NO
+GENERATE_TODOLIST = YES
+GENERATE_TESTLIST = YES
+GENERATE_BUGLIST = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS =
+MAX_INITIALIZER_LINES = 30
+SHOW_USED_FILES = YES
+SHOW_DIRECTORIES = YES
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET = NO
+WARNINGS = YES
+WARN_IF_UNDOCUMENTED = YES
+WARN_IF_DOC_ERROR = YES
+WARN_FORMAT = "$file:$line: $text"
+WARN_LOGFILE =
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT = . ../common
+FILE_PATTERNS = *.c \
+ *.cc \
+ *.cxx \
+ *.cpp \
+ *.c++ \
+ *.java \
+ *.ii \
+ *.ixx \
+ *.ipp \
+ *.i++ \
+ *.inl \
+ *.h \
+ *.hh \
+ *.hxx \
+ *.hpp \
+ *.h++ \
+ *.idl \
+ *.odl \
+ *.cs \
+ *.php \
+ *.php3 \
+ *.inc \
+ *.m \
+ *.mm
+RECURSIVE = NO
+EXCLUDE =
+EXCLUDE_SYMLINKS = NO
+EXCLUDE_PATTERNS =
+EXAMPLE_PATH =
+EXAMPLE_PATTERNS = *
+EXAMPLE_RECURSIVE = NO
+IMAGE_PATH =
+INPUT_FILTER =
+FILTER_PATTERNS =
+FILTER_SOURCE_FILES = NO
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER = NO
+INLINE_SOURCES = NO
+STRIP_CODE_COMMENTS = YES
+REFERENCED_BY_RELATION = NO
+REFERENCES_RELATION = NO
+VERBATIM_HEADERS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX = NO
+COLS_IN_ALPHA_INDEX = 5
+IGNORE_PREFIX =
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML = YES
+HTML_OUTPUT = html
+HTML_FILE_EXTENSION = .html
+HTML_HEADER =
+HTML_FOOTER =
+HTML_STYLESHEET =
+HTML_ALIGN_MEMBERS = YES
+GENERATE_HTMLHELP = NO
+CHM_FILE =
+HHC_LOCATION =
+GENERATE_CHI = NO
+BINARY_TOC = NO
+TOC_EXPAND = NO
+DISABLE_INDEX = NO
+ENUM_VALUES_PER_LINE = 4
+GENERATE_TREEVIEW = YES
+TREEVIEW_WIDTH = 250
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX = NO
+LATEX_OUTPUT = latex
+LATEX_CMD_NAME = latex
+MAKEINDEX_CMD_NAME = makeindex
+COMPACT_LATEX = NO
+PAPER_TYPE = a4wide
+EXTRA_PACKAGES =
+LATEX_HEADER =
+PDF_HYPERLINKS = NO
+USE_PDFLATEX = NO
+LATEX_BATCHMODE = NO
+LATEX_HIDE_INDICES = NO
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF = NO
+RTF_OUTPUT = rtf
+COMPACT_RTF = NO
+RTF_HYPERLINKS = NO
+RTF_STYLESHEET_FILE =
+RTF_EXTENSIONS_FILE =
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN = NO
+MAN_OUTPUT = man
+MAN_EXTENSION = .3
+MAN_LINKS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML = NO
+XML_OUTPUT = xml
+XML_SCHEMA =
+XML_DTD =
+XML_PROGRAMLISTING = YES
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF = NO
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD = NO
+PERLMOD_LATEX = NO
+PERLMOD_PRETTY = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING = YES
+MACRO_EXPANSION = NO
+EXPAND_ONLY_PREDEF = NO
+SEARCH_INCLUDES = YES
+INCLUDE_PATH =
+INCLUDE_FILE_PATTERNS =
+PREDEFINED =
+EXPAND_AS_DEFINED =
+SKIP_FUNCTION_MACROS = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+TAGFILES =
+GENERATE_TAGFILE =
+ALLEXTERNALS = NO
+EXTERNAL_GROUPS = YES
+PERL_PATH = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS = NO
+HIDE_UNDOC_RELATIONS = YES
+HAVE_DOT = NO
+CLASS_GRAPH = YES
+COLLABORATION_GRAPH = YES
+UML_LOOK = NO
+TEMPLATE_RELATIONS = NO
+INCLUDE_GRAPH = YES
+INCLUDED_BY_GRAPH = YES
+CALL_GRAPH = NO
+GRAPHICAL_HIERARCHY = YES
+DOT_IMAGE_FORMAT = png
+DOT_PATH =
+DOTFILE_DIRS =
+MAX_DOT_GRAPH_WIDTH = 1024
+MAX_DOT_GRAPH_HEIGHT = 1024
+MAX_DOT_GRAPH_DEPTH = 1000
+GENERATE_LEGEND = YES
+DOT_CLEANUP = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to the search engine
+#---------------------------------------------------------------------------
+SEARCHENGINE = NO
--- /dev/null
+/*
+ * File: EncoreBootImageReader.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "EncoreBootImageReader.h"
+#include "SHA1.h"
+#include "rijndael.h"
+#include "RijndaelCBCMAC.h"
+#include <assert.h>
+#include "EndianUtilities.h"
+#include "Logging.h"
+
+using namespace elftosb;
+
+//! \post Stream head points to just after the image header.
+//! \exception read_error Thrown if the image header is invalid.
+void EncoreBootImageReader::readImageHeader()
+{
+ // seek to beginning of the stream/file and read the plaintext header
+ m_stream.seekg(0, std::ios_base::beg);
+ if (m_stream.read((char *)&m_header, sizeof(m_header)).bad())
+ {
+ throw read_error("failed to read image header");
+ }
+
+ m_header.m_flags = ENDIAN_LITTLE_TO_HOST_U16(m_header.m_flags);
+ m_header.m_imageBlocks = ENDIAN_LITTLE_TO_HOST_U32(m_header.m_imageBlocks);
+ m_header.m_firstBootTagBlock = ENDIAN_LITTLE_TO_HOST_U32(m_header.m_firstBootTagBlock);
+ m_header.m_firstBootableSectionID = ENDIAN_LITTLE_TO_HOST_U32(m_header.m_firstBootableSectionID);
+ m_header.m_keyCount = ENDIAN_LITTLE_TO_HOST_U16(m_header.m_keyCount);
+ m_header.m_keyDictionaryBlock = ENDIAN_LITTLE_TO_HOST_U16(m_header.m_keyDictionaryBlock);
+ m_header.m_headerBlocks = ENDIAN_LITTLE_TO_HOST_U16(m_header.m_headerBlocks);
+ m_header.m_sectionCount = ENDIAN_LITTLE_TO_HOST_U16(m_header.m_sectionCount);
+ m_header.m_sectionHeaderSize = ENDIAN_LITTLE_TO_HOST_U16(m_header.m_sectionHeaderSize);
+ m_header.m_timestamp = ENDIAN_LITTLE_TO_HOST_U64(m_header.m_timestamp);
+
+// m_header.m_componentVersion.m_major = ENDIAN_BIG_TO_HOST_U16(m_header.m_componentVersion.m_major);
+// m_header.m_componentVersion.m_minor = ENDIAN_BIG_TO_HOST_U16(m_header.m_componentVersion.m_minor);
+// m_header.m_componentVersion.m_revision = ENDIAN_BIG_TO_HOST_U16(m_header.m_componentVersion.m_revision);
+
+// m_header.m_productVersion.m_major = ENDIAN_BIG_TO_HOST_U16(m_header.m_productVersion.m_major);
+// m_header.m_productVersion.m_minor = ENDIAN_BIG_TO_HOST_U16(m_header.m_productVersion.m_minor);
+// m_header.m_productVersion.m_revision = ENDIAN_BIG_TO_HOST_U16(m_header.m_productVersion.m_revision);
+
+ // check header signature 1
+ if (m_header.m_signature[0] != 'S' || m_header.m_signature[1] != 'T' || m_header.m_signature[2] != 'M' || m_header.m_signature[3] != 'P')
+ {
+ throw read_error("invalid signature 1");
+ }
+
+ // check header signature 2 for version 1.1 and greater
+ if ((m_header.m_majorVersion > 1 || (m_header.m_majorVersion == 1 && m_header.m_minorVersion >= 1)) && (m_header.m_signature2[0] != 's' || m_header.m_signature2[1] != 'g' || m_header.m_signature2[2] != 't' || m_header.m_signature2[3] != 'l'))
+ {
+// throw read_error("invalid signature 2");
+ Log::log(Logger::WARNING, "warning: invalid signature 2\n");
+ }
+}
+
+//! \pre The image header must have already been read with a call to readImageHeader().
+//!
+void EncoreBootImageReader::computeHeaderDigest(sha1_digest_t & digest)
+{
+ CSHA1 hash;
+ hash.Reset();
+ hash.Update((uint8_t *)&m_header.m_signature, sizeof(m_header) - sizeof(sha1_digest_t));
+ hash.Final();
+ hash.GetHash(digest);
+}
+
+//! \pre The image header must have already been read.
+//! \pre The DEK must have been found already.
+//! \post The stream head is at the end of the digest.
+void EncoreBootImageReader::readImageDigest()
+{
+ unsigned digestPosition = sizeOfCipherBlocks(m_header.m_imageBlocks - 2);
+ m_stream.seekg(digestPosition, std::ios_base::beg);
+
+ // read the two cipher blocks containing the digest, including padding
+ cipher_block_t digestBlocks[2];
+ if (m_stream.read((char *)&digestBlocks, sizeof(digestBlocks)).bad())
+ {
+ throw read_error("failed to read image digest");
+ }
+
+ // decrypt the digest
+ if (isEncrypted())
+ {
+ Rijndael cipher;
+ cipher.init(Rijndael::CBC, Rijndael::Decrypt, m_dek, Rijndael::Key16Bytes, m_header.m_iv);
+ cipher.blockDecrypt((uint8_t *)&digestBlocks, sizeof(digestBlocks) * 8, (uint8_t *)&digestBlocks);
+ }
+
+ // copy the digest out of the padded blocks
+ memcpy(m_digest, &digestBlocks, sizeof(m_digest));
+}
+
+//! \pre The image header must have already been read with a call to readImageHeader().
+//! \post The stream head is at the end of the image minus the last two cipher blocks.
+//! \param digest Where to store the resulting digest.
+//! \exception read_error Thrown if the image header is invalid.
+void EncoreBootImageReader::computeImageDigest(sha1_digest_t & digest)
+{
+ m_stream.seekg(0, std::ios_base::beg);
+
+ CSHA1 hash;
+ hash.Reset();
+
+ unsigned blockCount = m_header.m_imageBlocks - 2; // exclude digest at end of image
+ while (blockCount--)
+ {
+ cipher_block_t block;
+ if (m_stream.read((char *)&block, sizeof(block)).bad())
+ {
+ throw read_error("failed to read block while computing image digest");
+ }
+ hash.Update(block, sizeof(block));
+ }
+
+ hash.Final();
+ hash.GetHash(digest);
+}
+
+//! \pre Image header must have been read before this method is called.
+//!
+void EncoreBootImageReader::readSectionTable()
+{
+ // seek to the table
+ m_stream.seekg(sizeOfCipherBlocks(m_header.m_headerBlocks), std::ios_base::beg);
+
+ unsigned sectionCount = m_header.m_sectionCount;
+ while (sectionCount--)
+ {
+ EncoreBootImage::section_header_t header;
+ if (m_stream.read((char *)&header, sizeof(header)).bad())
+ {
+ throw read_error("failed to read section header");
+ }
+
+ // swizzle section header
+ header.m_tag = ENDIAN_LITTLE_TO_HOST_U32(header.m_tag);
+ header.m_offset = ENDIAN_LITTLE_TO_HOST_U32(header.m_offset);
+ header.m_length = ENDIAN_LITTLE_TO_HOST_U32(header.m_length);
+ header.m_flags = ENDIAN_LITTLE_TO_HOST_U32(header.m_flags);
+
+ m_sections.push_back(header);
+ }
+}
+
+//! Requires that an OTP key has been provided as the sole argument. Passing the
+//! key into this method lets the caller search the key dictionary for any number
+//! of keys and determine which are valid. If \a kek is found in the dictionary,
+//! the decrypted DEK is saved and true is returned. A result of false means
+//! that \a kek was not found.
+//!
+//! \pre The image header and section table must have been read already.
+//! \post The stream head points somewhere inside the key dictionary, or just after it.
+//! \post If the search was successful, the #m_dek member will contain the decrypted
+//! session key. Otherwise #m_dek is not modified.
+//! \param kek Search for this KEK in the dictionary.
+//! \retval true The DEK was found and decrypted. True is also returned when the
+//! image is not encrypted at all.
+//! \retval false No matching key entry was found. The image cannot be decrypted.
+bool EncoreBootImageReader::readKeyDictionary(const AESKey<128> & kek)
+{
+ // do nothing if the image is not encrypted
+ if (!isEncrypted())
+ {
+ return true;
+ }
+
+ // first compute a CBC-MAC over the image header with our KEK
+ RijndaelCBCMAC mac(kek);
+ mac.update((const uint8_t *)&m_header, sizeof(m_header));
+
+ // run the CBC-MAC over each entry in the section table too
+ section_array_t::iterator it = m_sections.begin();
+ for (; it != m_sections.end(); ++it)
+ {
+ mac.update((const uint8_t *)&(*it), sizeof(EncoreBootImage::section_header_t));
+ }
+
+ // get the CBC-MAC result
+ mac.finalize();
+ const RijndaelCBCMAC::block_t & macResult = mac.getMAC();
+
+ // seek to the key dictionary
+ m_stream.seekg(sizeOfCipherBlocks(m_header.m_keyDictionaryBlock), std::ios_base::beg);
+
+ // decipher each key entry
+ unsigned entries = m_header.m_keyCount;
+ while (entries--)
+ {
+ // read the entry
+ EncoreBootImage::dek_dictionary_entry_t entry;
+ if (m_stream.read((char *)&entry, sizeof(entry)).bad())
+ {
+ throw read_error("failed to read key dictionary entry");
+ }
+
+ // compare the CBC-MAC we computed with the one in this entry
+ if (memcmp(macResult, entry.m_mac, sizeof(cipher_block_t)) == 0)
+ {
+ // it's a match! now decrypt this entry's key in place
+ Rijndael cipher;
+ cipher.init(Rijndael::CBC, Rijndael::Decrypt, kek, Rijndael::Key16Bytes, m_header.m_iv);
+ cipher.blockDecrypt(entry.m_dek, sizeof(entry.m_dek) * 8, entry.m_dek);
+
+ m_dek = entry.m_dek;
+ memset(entry.m_dek, 0, sizeof(entry.m_dek)); // wipe the key value from memory
+ return true;
+ }
+ }
+
+ // if we exit the loop normally then no matching MAC was found
+ return false;
+}
+
+//! Before the boot tag is added to the #m_bootTags member, some basic checks are performed.
+//! The command tag field is checked to make sure it matches #ROM_TAG_CMD. And
+//! the checksum field is verified to be sure it's correct.
+//!
+//! After the call to this method returns, the array of boot tags is accessible
+//! with the getBootTags() method. The array is sorted in the order in which
+//! the boot tags appeared in the image.
+//!
+//! \pre Image header must have been read.
+//! \pre Key dictionary must have been read and a valid DEK found.
+//! \post The stream head is left pointing just after the last boot tag.
+//! \exception read_error A failure to read the boot tag, or a failure on one
+//! of the consistency checks will cause this exception to be thrown.
+void EncoreBootImageReader::readBootTags()
+{
+ assert(m_header.m_firstBootTagBlock != 0);
+
+ unsigned bootTagOffset = m_header.m_firstBootTagBlock;
+
+ while (1)
+ {
+ // seek to this boot tag and read it into a temporary buffer
+ EncoreBootImage::boot_command_t header;
+ m_stream.seekg(sizeOfCipherBlocks(bootTagOffset), std::ios_base::beg);
+ if (m_stream.read((char *)&header, sizeof(header)).bad())
+ {
+ throw read_error("failed to read boot tag");
+ }
+
+ // swizzle to command header
+ header.m_flags = ENDIAN_LITTLE_TO_HOST_U16(header.m_flags);
+ header.m_address = ENDIAN_LITTLE_TO_HOST_U32(header.m_address);
+ header.m_count = ENDIAN_LITTLE_TO_HOST_U32(header.m_count);
+ header.m_data = ENDIAN_LITTLE_TO_HOST_U32(header.m_data);
+
+ // decrypt in place
+ if (isEncrypted())
+ {
+ Rijndael cipher;
+ cipher.init(Rijndael::CBC, Rijndael::Decrypt, m_dek, Rijndael::Key16Bytes, m_header.m_iv);
+ cipher.blockDecrypt((uint8_t *)&header, sizeof(header) * 8, (uint8_t *)&header);
+ }
+
+ // perform some basic checks
+ if (header.m_tag != EncoreBootImage::ROM_TAG_CMD)
+ {
+ throw read_error("boot tag is wrong command type");
+ }
+
+ uint8_t checksum = calculateCommandChecksum(header);
+ if (checksum != header.m_checksum)
+ {
+ throw read_error("boot tag checksum is invalid");
+ }
+
+ // save this boot tag
+ m_bootTags.push_back(header);
+
+ // and finally, update offset and break out of loop
+ bootTagOffset += header.m_count + 1; // include this boot tag in offset
+ if (header.m_flags & EncoreBootImage::ROM_LAST_TAG || bootTagOffset >= m_header.m_imageBlocks - 2)
+ {
+ break;
+ }
+ }
+}
+
+uint8_t EncoreBootImageReader::calculateCommandChecksum(EncoreBootImage::boot_command_t & header)
+{
+ uint8_t * bytes = reinterpret_cast<uint8_t *>(&header);
+ uint8_t checksum = 0x5a;
+ int i;
+
+ // start at one to skip checksum field
+ for (i = 1; i < sizeof(header); ++i)
+ {
+ checksum += bytes[i];
+ }
+
+ return checksum;
+}
+
+//! \param index The index of the section to read.
+//!
+//! \pre Both the image header and section table must have been read already before
+//! calling this method.
+//! \exception read_error This exception is raised if the stream reports an error while
+//! trying to read from the section.
+EncoreBootImage::Section * EncoreBootImageReader::readSection(unsigned index)
+{
+ // look up section header
+ assert(index < m_sections.size());
+ EncoreBootImage::section_header_t & header = m_sections[index];
+
+ // seek to the section
+ m_stream.seekg(sizeOfCipherBlocks(header.m_offset), std::ios_base::beg);
+
+ uint8_t * contents = NULL;
+ try
+ {
+ // allocate memory for the section contents and read the whole thing
+ unsigned contentLength = sizeOfCipherBlocks(header.m_length);
+ contents = new uint8_t[contentLength];
+ if (m_stream.read((char *)contents, contentLength).bad())
+ {
+ throw read_error("failed to read section");
+ }
+
+ // decrypt the entire section at once, if the image is encrypted and
+ // the cleartext flag is not set
+ if (isEncrypted() && (header.m_flags & EncoreBootImage::ROM_SECTION_CLEARTEXT) == 0)
+ {
+ Rijndael cipher;
+ cipher.init(Rijndael::CBC, Rijndael::Decrypt, m_dek, Rijndael::Key16Bytes, m_header.m_iv);
+ cipher.blockDecrypt(contents, contentLength * 8, contents);
+ }
+
+ // create section object
+ EncoreBootImage::Section * resultSection = NULL;
+ if (header.m_flags & EncoreBootImage::ROM_SECTION_BOOTABLE)
+ {
+ // a boot command section.
+ EncoreBootImage::BootSection * bootSection = new EncoreBootImage::BootSection(header.m_tag);
+
+ bootSection->fillFromData((cipher_block_t *)contents, header.m_length);
+
+ resultSection = bootSection;
+ }
+ else
+ {
+ // this is a raw data section
+ EncoreBootImage::DataSection * dataSection = new EncoreBootImage::DataSection(header.m_tag);
+ dataSection->setDataNoCopy(contents, contentLength);
+ contents = NULL;
+ resultSection = dataSection;
+ }
+
+ return resultSection;
+ }
+ catch (...)
+ {
+ if (contents)
+ {
+ delete [] contents;
+ }
+ throw;
+ }
+}
+
+
--- /dev/null
+/*
+ * File: EncoreBootImageReader.h
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+#if !defined(_EncoreBootImageReader_h_)
+#define _EncoreBootImageReader_h_
+
+#include "EncoreBootImage.h"
+
+namespace elftosb
+{
+
+/*!
+ * \brief Reads a Piano/Encore boot image from an input stream.
+ */
+class EncoreBootImageReader
+{
+public:
+ /*!
+ * \brief Exception class used for error found while reading a boot image.
+ */
+ class read_error : public std::runtime_error
+ {
+ public:
+ //! \brief Constructor.
+ read_error(const std::string & msg) : std::runtime_error(msg) {}
+ };
+
+ //! \brief An array of section headers.
+ typedef std::vector<EncoreBootImage::section_header_t> section_array_t;
+
+ //! \brief An array of boot tags.
+ typedef std::vector<EncoreBootImage::boot_command_t> boot_tag_array_t;
+
+public:
+ //! \brief Default constructor.
+ EncoreBootImageReader(std::istream & stream) : m_stream(stream) {}
+
+ //! \brief Destructor.
+ virtual ~EncoreBootImageReader() {}
+
+ //! \name Decryption key
+ //! These methods provide access to the Data Encryption Key (DEK). Normally
+ //! the DEK is discovered using the readKeyDictionary() method.
+ //@{
+ inline void setKey(const AESKey<128> & key) { m_dek = key; }
+ inline const AESKey<128> & getKey() const { return m_dek; }
+ //@}
+
+ //! \name Readers
+ //! This group of methods is responsible for reading and parsing different
+ //! pieces and parts of the boot image file.
+ //@{
+ //! \brief Reads the header from the image.
+ void readImageHeader();
+
+ //! \brief Computes the actual SHA-1 digest of the image header.
+ void computeHeaderDigest(sha1_digest_t & digest);
+
+ //! \brief Reads the digest at the end of the image.
+ void readImageDigest();
+
+ //! \brief Run a SHA-1 digest over the entire image.
+ void computeImageDigest(sha1_digest_t & digest);
+
+ //! \brief Read the plaintext section table entries.
+ void readSectionTable();
+
+ //! \brief Reads the key dictionary, if the image is encrypted.
+ bool readKeyDictionary(const AESKey<128> & kek);
+
+ //! \brief
+ void readBootTags();
+
+ //! \brief
+ EncoreBootImage::Section * readSection(unsigned index);
+ //@}
+
+ //! \name Accessors
+ //! Information retrieved with reader methods is accessible through
+ //! these methods.
+ //@{
+ //! \brief Returns whether the image is encrypted or not.
+ //! \pre The header must have been read already.
+ inline bool isEncrypted() const { return m_header.m_keyCount > 0; }
+
+ //! \brief Returns a reference to the image's header.
+ const EncoreBootImage::boot_image_header_t & getHeader() const { return m_header; }
+
+ //! \brief Returns a reference to the SHA-1 digest read from the image.
+ const sha1_digest_t & getDigest() const { return m_digest; }
+
+ //! \brief Returns a reference to the STL container holding the section headers.
+ inline const section_array_t & getSections() const { return m_sections; }
+
+ //! \brief Returns a reference to the STL container holding the boot tags.
+ inline const boot_tag_array_t & getBootTags() const { return m_bootTags; }
+ //@}
+
+protected:
+ std::istream & m_stream; //!< The input stream to read the image from.
+ AESKey<128> m_dek; //!< DEK (data encryption key) read from the key dictionary.
+ EncoreBootImage::boot_image_header_t m_header; //!< Header from the boot image.
+ sha1_digest_t m_digest; //!< SHA-1 digest as read from the image.
+ section_array_t m_sections; //!< The section table.
+ boot_tag_array_t m_bootTags; //!< The array of boot tags read from the image.
+
+protected:
+ //! \brief Calculates the 8-bit checksum on a boot command header.
+ uint8_t calculateCommandChecksum(EncoreBootImage::boot_command_t & header);
+};
+
+}; // namespace elftosb
+
+#endif // _EncoreBootImageReader_h_
--- /dev/null
+/*
+ * File: sbtool.cpp
+ *
+ * Copyright (c) Freescale Semiconductor, Inc. All rights reserved.
+ * See included license file for license details.
+ */
+
+#include "stdafx.h"
+#include <iostream>
+#include <fstream>
+#include <sstream>
+#include <stdlib.h>
+#include <stdexcept>
+#include <stdio.h>
+#include "options.h"
+#include "EncoreBootImage.h"
+#include "smart_ptr.h"
+#include "Logging.h"
+#include "EncoreBootImageReader.h"
+#include "format_string.h"
+
+using namespace elftosb;
+
+//! The tool's name.
+const char k_toolName[] = "sbtool";
+
+//! Current version number for the tool.
+const char k_version[] = "1.1.4";
+
+//! Copyright string.
+const char k_copyright[] = "Copyright (c) 2006-2010 Freescale Semiconductor, Inc.\nAll rights reserved.";
+
+//! Definition of command line options.
+static const char * k_optionsDefinition[] = {
+ "?|help",
+ "v|version",
+ "k:key <file>",
+ "z|zero-key",
+ "x:extract",
+ "b|binary",
+ "d|debug",
+ "q|quiet",
+ "V|verbose",
+ NULL
+};
+
+//! Help string.
+const char k_usageText[] = "\nOptions:\n\
+ -?/--help Show this help\n\
+ -v/--version Display tool version\n\
+ -k/--key <file> Add OTP key used for decryption\n\
+ -z/--zero-key Add default key of all zeroes\n\
+ -x/--extract <index> Extract section number <index>\n\
+ -b/--binary Extract section data as binary\n\
+ -d/--debug Enable debug output\n\
+ -q/--quiet Output only warnings and errors\n\
+ -V/--verbose Print extra detailed log information\n\n";
+
+//! An array of strings.
+typedef std::vector<std::string> string_vector_t;
+
+// prototypes
+int main(int argc, char* argv[], char* envp[]);
+
+/*!
+ * \brief Class that encapsulates the sbtool interface.
+ *
+ * A single global logger instance is created during object construction. It is
+ * never freed because we need it up to the last possible minute, when an
+ * exception could be thrown.
+ */
+class sbtool
+{
+protected:
+ int m_argc; //!< Number of command line arguments.
+ char ** m_argv; //!< String value for each command line argument.
+ StdoutLogger * m_logger; //!< Singleton logger instance.
+ string_vector_t m_keyFilePaths; //!< Paths to OTP key files.
+ string_vector_t m_positionalArgs; //!< Arguments coming after explicit options.
+ bool m_isVerbose; //!< Whether the verbose flag was turned on.
+ bool m_useDefaultKey; //!< Include a default (zero) crypto key.
+ bool m_doExtract; //!< True if extract mode is on.
+ unsigned m_sectionIndex; //!< Index of section to extract.
+ bool m_extractBinary; //!< True if extraction output is binary, false for hex.
+ smart_ptr<EncoreBootImageReader> m_reader; //!< Boot image reader object.
+
+public:
+ /*!
+ * Constructor.
+ *
+ * Creates the singleton logger instance.
+ */
+ sbtool(int argc, char * argv[])
+ : m_argc(argc),
+ m_argv(argv),
+ m_logger(0),
+ m_keyFilePaths(),
+ m_positionalArgs(),
+ m_isVerbose(false),
+ m_useDefaultKey(false),
+ m_doExtract(false),
+ m_sectionIndex(0),
+ m_extractBinary(false),
+ m_reader()
+ {
+ // create logger instance
+ m_logger = new StdoutLogger();
+ m_logger->setFilterLevel(Logger::INFO);
+ Log::setLogger(m_logger);
+ }
+
+ /*!
+ * Destructor.
+ */
+ ~sbtool()
+ {
+ }
+
+ /*!
+ * Reads the command line options passed into the constructor.
+ *
+ * This method can return a return code to its caller, which will cause the
+ * tool to exit immediately with that return code value. Normally, though, it
+ * will return -1 to signal that the tool should continue to execute and
+ * all options were processed successfully.
+ *
+ * The Options class is used to parse command line options. See
+ * #k_optionsDefinition for the list of options and #k_usageText for the
+ * descriptive help for each option.
+ *
+ * \retval -1 The options were processed successfully. Let the tool run normally.
+ * \return A zero or positive result is a return code value that should be
+ * returned from the tool as it exits immediately.
+ */
+ int processOptions()
+ {
+ Options options(*m_argv, k_optionsDefinition);
+ OptArgvIter iter(--m_argc, ++m_argv);
+
+ // process command line options
+ int optchar;
+ const char * optarg;
+ while (optchar = options(iter, optarg))
+ {
+ switch (optchar)
+ {
+ case '?':
+ printUsage(options);
+ return 0;
+
+ case 'v':
+ printf("%s %s\n%s\n", k_toolName, k_version, k_copyright);
+ return 0;
+
+ case 'k':
+ m_keyFilePaths.push_back(optarg);
+ break;
+
+ case 'z':
+ m_useDefaultKey = true;
+ break;
+
+ case 'x':
+ m_doExtract = true;
+ m_sectionIndex = strtoul(optarg, NULL, 0);
+ break;
+
+ case 'b':
+ m_extractBinary = true;
+ Log::getLogger()->setFilterLevel(Logger::WARNING);
+ break;
+
+ case 'd':
+ Log::getLogger()->setFilterLevel(Logger::DEBUG);
+ break;
+
+ case 'q':
+ Log::getLogger()->setFilterLevel(Logger::WARNING);
+ break;
+
+ case 'V':
+ m_isVerbose = true;
+ break;
+
+ default:
+ Log::log(Logger::ERROR, "error: unrecognized option\n\n");
+ printUsage(options);
+ return 1;
+ }
+ }
+
+ // handle positional args
+ if (iter.index() < m_argc)
+ {
+// Log::SetOutputLevel leveler(Logger::DEBUG);
+// Log::log("positional args:\n");
+ int i;
+ for (i = iter.index(); i < m_argc; ++i)
+ {
+// Log::log("%d: %s\n", i - iter.index(), m_argv[i]);
+ m_positionalArgs.push_back(m_argv[i]);
+ }
+ }
+
+ // all is well
+ return -1;
+ }
+
+ /*!
+ * Prints help for the tool.
+ */
+ void printUsage(Options & options)
+ {
+ options.usage(std::cout, "sb-file");
+ printf(k_usageText, k_toolName);
+ }
+
+ /*!
+ * Core of the tool. Calls processOptions() to handle command line options
+ * before performing the real work the tool does.
+ */
+ int run()
+ {
+ try
+ {
+ // read command line options
+ int result;
+ if ((result = processOptions()) != -1)
+ {
+ return result;
+ }
+
+ // set verbose logging
+ setVerboseLogging();
+
+ // make sure a file was provided
+ if (m_positionalArgs.size() < 1)
+ {
+ throw std::runtime_error("no sb file path was provided");
+ }
+
+ // read the boot image
+ readBootImage();
+ }
+ catch (std::exception & e)
+ {
+ Log::log(Logger::ERROR, "error: %s\n", e.what());
+ return 1;
+ }
+ catch (...)
+ {
+ Log::log(Logger::ERROR, "error: unexpected exception\n");
+ return 1;
+ }
+
+ return 0;
+ }
+
+ /*!
+ * \brief Turns on verbose logging.
+ */
+ void setVerboseLogging()
+ {
+ if (m_isVerbose)
+ {
+ // verbose only affects the INFO and DEBUG filter levels
+ // if the user has selected quiet mode, it overrides verbose
+ switch (Log::getLogger()->getFilterLevel())
+ {
+ case Logger::INFO:
+ Log::getLogger()->setFilterLevel(Logger::INFO2);
+ break;
+ case Logger::DEBUG:
+ Log::getLogger()->setFilterLevel(Logger::DEBUG2);
+ break;
+ }
+ }
+ }
+
+ /*!
+ * \brief Opens and reads the boot image identified on the command line.
+ * \pre At least one position argument must be present.
+ */
+ void readBootImage()
+ {
+ Log::SetOutputLevel infoLevel(Logger::INFO);
+
+ // open the sb file stream
+ std::ifstream sbStream(m_positionalArgs[0].c_str(), std::ios_base::binary | std::ios_base::in);
+ if (!sbStream.is_open())
+ {
+ throw std::runtime_error("failed to open input file");
+ }
+
+ // create the boot image reader
+ m_reader = new EncoreBootImageReader(sbStream);
+
+ // read image header
+ m_reader->readImageHeader();
+ const EncoreBootImage::boot_image_header_t & header = m_reader->getHeader();
+ if (header.m_majorVersion > 1)
+ {
+ throw std::runtime_error(format_string("boot image format version is too new (format version %d.%d)\n", header.m_majorVersion, header.m_minorVersion));
+ }
+ Log::log("---- Boot image header ----\n");
+ dumpImageHeader(header);
+
+ // compute SHA-1 over image header and test against the digest stored in the header
+ sha1_digest_t computedDigest;
+ m_reader->computeHeaderDigest(computedDigest);
+ if (compareDigests(computedDigest, m_reader->getHeader().m_digest))
+ {
+ Log::log("Header digest is correct.\n");
+ }
+ else
+ {
+ Log::log(Logger::WARNING, "warning: stored SHA-1 header digest does not match the actual header digest\n");
+ Log::log(Logger::WARNING, "\n---- Actual SHA-1 digest of image header ----\n");
+ logHexArray(Logger::WARNING, (uint8_t *)&computedDigest, sizeof(computedDigest));
+ }
+
+ // read the section table
+ m_reader->readSectionTable();
+ const EncoreBootImageReader::section_array_t & sectionTable = m_reader->getSections();
+ EncoreBootImageReader::section_array_t::const_iterator it = sectionTable.begin();
+ Log::log("\n---- Section table ----\n");
+ unsigned n = 0;
+ for (; it != sectionTable.end(); ++it, ++n)
+ {
+ const EncoreBootImage::section_header_t & sectionHeader = *it;
+ Log::log("Section %d:\n", n);
+ dumpSectionHeader(sectionHeader);
+ }
+
+ // read the key dictionary
+ // XXX need to support multiple keys, not just the first!
+ if (m_reader->isEncrypted())
+ {
+ Log::log("\n---- Key dictionary ----\n");
+ if (m_keyFilePaths.size() > 0 || m_useDefaultKey)
+ {
+ if (m_keyFilePaths.size() > 0)
+ {
+ std::string & keyPath = m_keyFilePaths[0];
+ std::ifstream keyStream(keyPath.c_str(), std::ios_base::binary | std::ios_base::in);
+ if (!keyStream.is_open())
+ {
+ Log::log(Logger::WARNING, "warning: unable to read key %s\n", keyPath.c_str());
+ }
+ AESKey<128> kek(keyStream);
+
+ // search for this key in the key dictionary
+ if (!m_reader->readKeyDictionary(kek))
+ {
+ throw std::runtime_error("the provided key is not valid for this encrypted boot image");
+ }
+
+ Log::log("\nKey %s was found in key dictionary.\n", keyPath.c_str());
+ }
+ else
+ {
+ // default key of zero, overriden if -k was used
+ AESKey<128> defaultKek;
+
+ // search for this key in the key dictionary
+ if (!m_reader->readKeyDictionary(defaultKek))
+ {
+ throw std::runtime_error("the default key is not valid for this encrypted boot image");
+ }
+
+ Log::log("\nDefault key was found in key dictionary.\n");
+ }
+
+ // print out the DEK
+ AESKey<128> dek = m_reader->getKey();
+ std::stringstream dekStringStream(std::ios_base::in | std::ios_base::out);
+ dek.writeToStream(dekStringStream);
+ std::string dekString = dekStringStream.str();
+// Log::log("\nData encryption key: %s\n", dekString.c_str());
+ Log::log("\nData encryption key:\n");
+ logHexArray(Logger::INFO, (const uint8_t *)&dek.getKey(), sizeof(AESKey<128>::key_t));
+ }
+ else
+ {
+ throw std::runtime_error("the image is encrypted but no key was provided");
+ }
+ }
+
+ // read the SHA-1 digest over the entire image. this is done after
+ // reading the key dictionary because the digest is encrypted in
+ // encrypted boot images.
+ m_reader->readImageDigest();
+ const sha1_digest_t & embeddedDigest = m_reader->getDigest();
+ Log::log("\n---- SHA-1 digest of entire image ----\n");
+ logHexArray(Logger::INFO, (const uint8_t *)&embeddedDigest, sizeof(embeddedDigest));
+
+ // compute the digest over the entire image and compare
+ m_reader->computeImageDigest(computedDigest);
+ if (compareDigests(computedDigest, embeddedDigest))
+ {
+ Log::log("Image digest is correct.\n");
+ }
+ else
+ {
+ Log::log(Logger::WARNING, "warning: stored SHA-1 digest does not match the actual digest\n");
+ Log::log(Logger::WARNING, "\n---- Actual SHA-1 digest of entire image ----\n");
+ logHexArray(Logger::WARNING, (uint8_t *)&computedDigest, sizeof(computedDigest));
+ }
+
+ // read the boot tags
+ m_reader->readBootTags();
+ Log::log("\n---- Boot tags ----\n");
+ unsigned block = header.m_firstBootTagBlock;
+ const EncoreBootImageReader::boot_tag_array_t & tags = m_reader->getBootTags();
+ EncoreBootImageReader::boot_tag_array_t::const_iterator tagIt = tags.begin();
+ for (n = 0; tagIt != tags.end(); ++tagIt, ++n)
+ {
+ const EncoreBootImage::boot_command_t & command = *tagIt;
+ Log::log("%04u: @ block %06u | id=0x%08x | length=%06u | flags=0x%08x\n", n, block, command.m_address, command.m_count, command.m_data);
+
+ if (command.m_data & EncoreBootImage::ROM_SECTION_BOOTABLE)
+ {
+ Log::log(" 0x1 = ROM_SECTION_BOOTABLE\n");
+ }
+
+ if (command.m_data & EncoreBootImage::ROM_SECTION_CLEARTEXT)
+ {
+ Log::log(" 0x2 = ROM_SECTION_CLEARTEXT\n");
+ }
+
+ block += command.m_count + 1;
+ }
+
+ // now read all of the sections
+ Log::log(Logger::INFO2, "\n---- Sections ----\n");
+ for (n = 0; n < header.m_sectionCount; ++n)
+ {
+ EncoreBootImage::Section * section = m_reader->readSection(n);
+ section->debugPrint();
+
+ // Check if this is the section the user wants to extract.
+ if (m_doExtract && n == m_sectionIndex)
+ {
+ extractSection(section);
+ }
+ }
+ }
+
+ //! \brief Dumps the contents of a section to stdout.
+ //!
+ //! If #m_extractBinary is true then the contents are written as
+ //! raw binary to stdout. Otherwise the data is formatted using
+ //! logHexArray().
+ void extractSection(EncoreBootImage::Section * section)
+ {
+ // Allocate buffer to hold section data.
+ unsigned blockCount = section->getBlockCount();
+ unsigned dataLength = sizeOfCipherBlocks(blockCount);
+ smart_array_ptr<uint8_t> buffer = new uint8_t[dataLength];
+ cipher_block_t * data = reinterpret_cast<cipher_block_t *>(buffer.get());
+
+ // Read section data into the buffer one block at a time.
+ unsigned offset;
+ for (offset = 0; offset < blockCount;)
+ {
+ unsigned blocksRead = section->getBlocks(offset, 1, data);
+ offset += blocksRead;
+ data += blocksRead;
+ }
+
+ // Print header.
+ Log::log(Logger::INFO, "\nSection %d contents:\n", m_sectionIndex);
+
+ // Now dump the extracted data to stdout.
+ if (m_extractBinary)
+ {
+ if (fwrite(buffer.get(), 1, dataLength, stdout) != dataLength)
+ {
+ throw std::runtime_error(format_string("failed to write data to stdout (%d)", ferror(stdout)));
+ }
+ }
+ else
+ {
+ // Use the warning log level so the data will be visible even in quiet mode.
+ logHexArray(Logger::WARNING, buffer, dataLength);
+ }
+ }
+
+ //! \brief Compares two SHA-1 digests and returns whether they are equal.
+ //! \retval true The two digests are equal.
+ //! \retval false The \a a and \a b digests are different from each other.
+ bool compareDigests(const sha1_digest_t & a, const sha1_digest_t & b)
+ {
+ return memcmp(a, b, sizeof(sha1_digest_t)) == 0;
+ }
+
+ /*
+ struct boot_image_header_t
+ {
+ union
+ {
+ sha1_digest_t m_digest; //!< SHA-1 digest of image header. Also used as the crypto IV.
+ struct
+ {
+ cipher_block_t m_iv; //!< The first four bytes of the digest form the initialization vector.
+ uint8_t m_extra[4]; //!< The leftover top four bytes of the SHA-1 digest.
+ };
+ };
+ uint8_t m_signature[4]; //!< 'STMP', see #ROM_IMAGE_HEADER_SIGNATURE.
+ uint16_t m_version; //!< Version of the boot image format, see #ROM_BOOT_IMAGE_VERSION.
+ uint16_t m_flags; //!< Flags or options associated with the entire image.
+ uint32_t m_imageBlocks; //!< Size of entire image in blocks.
+ uint32_t m_firstBootTagBlock; //!< Offset from start of file to the first boot tag, in blocks.
+ section_id_t m_firstBootableSectionID; //!< ID of section to start booting from.
+ uint16_t m_keyCount; //!< Number of entries in DEK dictionary.
+ uint16_t m_keyDictionaryBlock; //!< Starting block number for the key dictionary.
+ uint16_t m_headerBlocks; //!< Size of this header, including this size word, in blocks.
+ uint16_t m_sectionCount; //!< Number of section headers in this table.
+ uint16_t m_sectionHeaderSize; //!< Size in blocks of a section header.
+ uint8_t m_padding0[6]; //!< Padding to align #m_timestamp to long word.
+ uint64_t m_timestamp; //!< Timestamp when image was generated in microseconds since 1-1-2000.
+ version_t m_productVersion; //!< Product version.
+ version_t m_componentVersion; //!< Component version.
+ uint16_t m_driveTag;
+ uint8_t m_padding1[6]; //!< Padding to round up to next cipher block.
+ };
+ */
+ void dumpImageHeader(const EncoreBootImage::boot_image_header_t & header)
+ {
+ version_t vers;
+
+ Log::SetOutputLevel infoLevel(Logger::INFO);
+ Log::log("Signature 1: %c%c%c%c\n", header.m_signature[0], header.m_signature[1], header.m_signature[2], header.m_signature[3]);
+ Log::log("Signature 2: %c%c%c%c\n", header.m_signature2[0], header.m_signature2[1], header.m_signature2[2], header.m_signature2[3]);
+ Log::log("Format version: %d.%d\n", header.m_majorVersion, header.m_minorVersion);
+ Log::log("Flags: 0x%04x\n", header.m_flags);
+ Log::log("Image blocks: %u\n", header.m_imageBlocks);
+ Log::log("First boot tag block: %u\n", header.m_firstBootTagBlock);
+ Log::log("First boot section ID: 0x%08x\n", header.m_firstBootableSectionID);
+ Log::log("Key count: %u\n", header.m_keyCount);
+ Log::log("Key dictionary block: %u\n", header.m_keyDictionaryBlock);
+ Log::log("Header blocks: %u\n", header.m_headerBlocks);
+ Log::log("Section count: %u\n", header.m_sectionCount);
+ Log::log("Section header size: %u\n", header.m_sectionHeaderSize);
+ Log::log("Timestamp: %llu\n", header.m_timestamp);
+ vers = header.m_productVersion;
+ vers.fixByteOrder();
+ Log::log("Product version: %x.%x.%x\n", vers.m_major, vers.m_minor, vers.m_revision);
+ vers = header.m_componentVersion;
+ vers.fixByteOrder();
+ Log::log("Component version: %x.%x.%x\n", vers.m_major, vers.m_minor, vers.m_revision);
+ if (header.m_majorVersion == 1 && header.m_minorVersion >= 1)
+ {
+ Log::log("Drive tag: 0x%04x\n", header.m_driveTag);
+ }
+ Log::log("SHA-1 digest of header:\n");
+ logHexArray(Logger::INFO, (uint8_t *)&header.m_digest, sizeof(header.m_digest));
+ }
+
+ void dumpSectionHeader(const EncoreBootImage::section_header_t & header)
+ {
+ Log::SetOutputLevel infoLevel(Logger::INFO);
+ Log::log(" Identifier: 0x%x\n", header.m_tag);
+ Log::log(" Offset: %d block%s (%d bytes)\n", header.m_offset, header.m_offset!=1?"s":"", sizeOfCipherBlocks(header.m_offset));
+ Log::log(" Length: %d block%s (%d bytes)\n", header.m_length, header.m_length!=1?"s":"", sizeOfCipherBlocks(header.m_length));
+ Log::log(" Flags: 0x%08x\n", header.m_flags);
+
+ if (header.m_flags & EncoreBootImage::ROM_SECTION_BOOTABLE)
+ {
+ Log::log(" 0x1 = ROM_SECTION_BOOTABLE\n");
+ }
+
+ if (header.m_flags & EncoreBootImage::ROM_SECTION_CLEARTEXT)
+ {
+ Log::log(" 0x2 = ROM_SECTION_CLEARTEXT\n");
+ }
+ }
+
+ /*!
+ * \brief Log an array of bytes as hex.
+ */
+ void logHexArray(Logger::log_level_t level, const uint8_t * bytes, unsigned count)
+ {
+ Log::SetOutputLevel leveler(level);
+
+ unsigned i;
+ for (i = 0; i < count; ++i, ++bytes)
+ {
+ if ((i % 16 == 0) && (i < count - 1))
+ {
+ if (i != 0)
+ {
+ Log::log("\n");
+ }
+ Log::log(" 0x%08x: ", i);
+ }
+ Log::log("%02x ", *bytes & 0xff);
+ }
+
+ Log::log("\n");
+ }
+
+};
+
+/*!
+ * Main application entry point. Creates an sbtool instance and lets it take over.
+ */
+int main(int argc, char* argv[], char* envp[])
+{
+ try
+ {
+ return sbtool(argc, argv).run();
+ }
+ catch (...)
+ {
+ Log::log(Logger::ERROR, "error: unexpected exception\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+
+
+
+
--- /dev/null
+<?xml version="1.0" encoding="Windows-1252"?>\r
+<VisualStudioProject\r
+ ProjectType="Visual C++"\r
+ Version="9.00"\r
+ Name="sbtool"\r
+ ProjectGUID="{5C9AC9F0-C755-4BBB-B65B-78C5262A87D2}"\r
+ Keyword="Win32Proj"\r
+ TargetFrameworkVersion="131072"\r
+ >\r
+ <Platforms>\r
+ <Platform\r
+ Name="Win32"\r
+ />\r
+ </Platforms>\r
+ <ToolFiles>\r
+ </ToolFiles>\r
+ <Configurations>\r
+ <Configuration\r
+ Name="Debug|Win32"\r
+ OutputDirectory="Debug"\r
+ IntermediateDirectory="Debug"\r
+ ConfigurationType="1"\r
+ InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops"\r
+ CharacterSet="2"\r
+ >\r
+ <Tool\r
+ Name="VCPreBuildEventTool"\r
+ />\r
+ <Tool\r
+ Name="VCCustomBuildTool"\r
+ />\r
+ <Tool\r
+ Name="VCXMLDataGeneratorTool"\r
+ />\r
+ <Tool\r
+ Name="VCWebServiceProxyGeneratorTool"\r
+ />\r
+ <Tool\r
+ Name="VCMIDLTool"\r
+ />\r
+ <Tool\r
+ Name="VCCLCompilerTool"\r
+ Optimization="0"\r
+ AdditionalIncludeDirectories="..\elftosb2;..\winsupport;..\common"\r
+ PreprocessorDefinitions="WIN32;_DEBUG;_CONSOLE"\r
+ MinimalRebuild="true"\r
+ BasicRuntimeChecks="3"\r
+ RuntimeLibrary="1"\r
+ RuntimeTypeInfo="true"\r
+ UsePrecompiledHeader="0"\r
+ BrowseInformation="1"\r
+ WarningLevel="2"\r
+ Detect64BitPortabilityProblems="true"\r
+ DebugInformationFormat="4"\r
+ DisableSpecificWarnings="4355"\r
+ />\r
+ <Tool\r
+ Name="VCManagedResourceCompilerTool"\r
+ />\r
+ <Tool\r
+ Name="VCResourceCompilerTool"\r
+ />\r
+ <Tool\r
+ Name="VCPreLinkEventTool"\r
+ />\r
+ <Tool\r
+ Name="VCLinkerTool"\r
+ OutputFile="$(OutDir)/sbtool.exe"\r
+ LinkIncremental="2"\r
+ GenerateDebugInformation="true"\r
+ ProgramDatabaseFile="$(OutDir)/sbtool.pdb"\r
+ SubSystem="1"\r
+ RandomizedBaseAddress="1"\r
+ DataExecutionPrevention="0"\r
+ TargetMachine="1"\r
+ />\r
+ <Tool\r
+ Name="VCALinkTool"\r
+ />\r
+ <Tool\r
+ Name="VCManifestTool"\r
+ />\r
+ <Tool\r
+ Name="VCXDCMakeTool"\r
+ />\r
+ <Tool\r
+ Name="VCBscMakeTool"\r
+ />\r
+ <Tool\r
+ Name="VCFxCopTool"\r
+ />\r
+ <Tool\r
+ Name="VCAppVerifierTool"\r
+ />\r
+ <Tool\r
+ Name="VCPostBuildEventTool"\r
+ />\r
+ </Configuration>\r
+ <Configuration\r
+ Name="Release|Win32"\r
+ OutputDirectory="Release"\r
+ IntermediateDirectory="Release"\r
+ ConfigurationType="1"\r
+ InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops"\r
+ CharacterSet="2"\r
+ >\r
+ <Tool\r
+ Name="VCPreBuildEventTool"\r
+ />\r
+ <Tool\r
+ Name="VCCustomBuildTool"\r
+ />\r
+ <Tool\r
+ Name="VCXMLDataGeneratorTool"\r
+ />\r
+ <Tool\r
+ Name="VCWebServiceProxyGeneratorTool"\r
+ />\r
+ <Tool\r
+ Name="VCMIDLTool"\r
+ />\r
+ <Tool\r
+ Name="VCCLCompilerTool"\r
+ PreprocessorDefinitions="WIN32;NDEBUG;_CONSOLE"\r
+ RuntimeLibrary="0"\r
+ UsePrecompiledHeader="0"\r
+ WarningLevel="3"\r
+ Detect64BitPortabilityProblems="true"\r
+ DebugInformationFormat="3"\r
+ />\r
+ <Tool\r
+ Name="VCManagedResourceCompilerTool"\r
+ />\r
+ <Tool\r
+ Name="VCResourceCompilerTool"\r
+ />\r
+ <Tool\r
+ Name="VCPreLinkEventTool"\r
+ />\r
+ <Tool\r
+ Name="VCLinkerTool"\r
+ OutputFile="$(OutDir)/sbtool.exe"\r
+ LinkIncremental="1"\r
+ GenerateDebugInformation="true"\r
+ SubSystem="1"\r
+ OptimizeReferences="2"\r
+ EnableCOMDATFolding="2"\r
+ RandomizedBaseAddress="1"\r
+ DataExecutionPrevention="0"\r
+ TargetMachine="1"\r
+ />\r
+ <Tool\r
+ Name="VCALinkTool"\r
+ />\r
+ <Tool\r
+ Name="VCManifestTool"\r
+ />\r
+ <Tool\r
+ Name="VCXDCMakeTool"\r
+ />\r
+ <Tool\r
+ Name="VCBscMakeTool"\r
+ />\r
+ <Tool\r
+ Name="VCFxCopTool"\r
+ />\r
+ <Tool\r
+ Name="VCAppVerifierTool"\r
+ />\r
+ <Tool\r
+ Name="VCPostBuildEventTool"\r
+ />\r
+ </Configuration>\r
+ </Configurations>\r
+ <References>\r
+ </References>\r
+ <Files>\r
+ <Filter\r
+ Name="Source Files"\r
+ Filter="cpp;c;cxx;def;odl;idl;hpj;bat;asm;asmx"\r
+ UniqueIdentifier="{4FC737F1-C7A5-4376-A066-2A32D752A2FF}"\r
+ >\r
+ <Filter\r
+ Name="sbtool"\r
+ >\r
+ <File\r
+ RelativePath=".\EncoreBootImageReader.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath=".\sbtool.cpp"\r
+ >\r
+ </File>\r
+ </Filter>\r
+ <Filter\r
+ Name="common"\r
+ >\r
+ <File\r
+ RelativePath="..\common\AESKey.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\AESKey.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Blob.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Blob.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\BootImage.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\crc.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\crc.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\DataSource.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\DataSource.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\DataTarget.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\DataTarget.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\ELF.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\ELFSourceFile.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\ELFSourceFile.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\EncoreBootImage.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\EncoreBootImage.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\EndianUtilities.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\EvalContext.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\EvalContext.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\format_string.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\format_string.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\GHSSecInfo.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\GHSSecInfo.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\GlobMatcher.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\GlobMatcher.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\HexValues.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\HexValues.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\int_size.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Logging.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Logging.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Operation.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Operation.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\OptionContext.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\OptionDictionary.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\OptionDictionary.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\options.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\options.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\OutputSection.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\OutputSection.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Random.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Random.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\rijndael.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\rijndael.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\RijndaelCBCMAC.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\RijndaelCBCMAC.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SearchPath.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SHA1.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SHA1.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\smart_ptr.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SourceFile.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SourceFile.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SRecordSourceFile.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\SRecordSourceFile.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\stdafx.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\stdafx.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StELFFile.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StELFFile.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StExecutableImage.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StExecutableImage.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StringMatcher.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StSRecordFile.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\StSRecordFile.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Value.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Value.h"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Version.cpp"\r
+ >\r
+ </File>\r
+ <File\r
+ RelativePath="..\common\Version.h"\r
+ >\r
+ </File>\r
+ </Filter>\r
+ </Filter>\r
+ <Filter\r
+ Name="Header Files"\r
+ Filter="h;hpp;hxx;hm;inl;inc;xsd"\r
+ UniqueIdentifier="{93995380-89BD-4b04-88EB-625FBE52EBFB}"\r
+ >\r
+ <Filter\r
+ Name="sbtol"\r
+ >\r
+ <File\r
+ RelativePath=".\EncoreBootImageReader.h"\r
+ >\r
+ </File>\r
+ </Filter>\r
+ <Filter\r
+ Name="common"\r
+ >\r
+ <File\r
+ RelativePath="..\common\SearchPath.h"\r
+ >\r
+ </File>\r
+ </Filter>\r
+ </Filter>\r
+ <Filter\r
+ Name="Resource Files"\r
+ Filter="rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx"\r
+ UniqueIdentifier="{67DA6AB6-F800-4c08-8B7A-83BB121AAD01}"\r
+ >\r
+ </Filter>\r
+ </Files>\r
+ <Globals>\r
+ </Globals>\r
+</VisualStudioProject>\r
--- /dev/null
+#ifndef stdafx_h_
+#define stdafx_h_
+
+// stdafx.h : include file for standard system include files,
+// or project specific include files that are used frequently, but
+// are changed infrequently
+//
+
+// Default to external release.
+#ifndef SGTL_INTERNAL
+ #define SGTL_INTERNAL 0
+#endif
+
+#include <iostream>
+#include <stdexcept>
+
+#if defined(WIN32)
+//#include <tchar.h>
+
+ // define this macro for use in VC++
+ #if !defined(__LITTLE_ENDIAN__)
+ #define __LITTLE_ENDIAN__ 1
+ #endif // !defined(__LITTLE_ENDIAN__)
+#endif // defined(WIN32)
+
+#if defined(Linux)
+// For Linux systems only, types.h only defines the signed
+// integer types. This is not professional code.
+// Update: They are defined in the header files in the more recent version of redhat enterprise gcc.
+#include "/usr/include/sys/types.h"
+//typedef unsigned long uint32_t;
+//typedef unsigned short uint16_t;
+//typedef unsigned char uint8_t;
+
+//#define TCHAR char
+//#define _tmain main
+
+ // give a default endian in case one is not defined on Linux (it should be, though)
+ #if !defined(__LITTLE_ENDIAN__) && !defined(__BIG_ENDIAN__)
+ #define __LITTLE_ENDIAN__ 1
+ #endif // !defined(__LITTLE_ENDIAN__) && !defined(__BIG_ENDIAN__)
+
+#endif // defined(Linux)
+
+
+#if !defined(Linux)
+// redefine missing typedefs from stdint.h or syst/types.h
+
+typedef unsigned long uint32_t;
+typedef unsigned short uint16_t;
+typedef unsigned char uint8_t;
+
+typedef long int32_t;
+typedef short int16_t;
+typedef char int8_t;
+#endif // !defined(Linux)
+
+#if !defined(TRUE)
+ #define TRUE 1
+#endif // !defined(TRUE)
+
+#if !defined(FALSE)
+ #define FALSE 0
+#endif // !defined(FALSE)
+
+#endif // stdafx_h_
--- /dev/null
+
+mkdir test_output
+
+.\elftosb2\Debug\elftosb -Vdz -p bdfiles -p test_files -fmx28 -c simple.e -o test_output\output1.sb plugin_hello redboot_gcc.srec hostlink
+.\sbtool\Debug\sbtool -Vdz test_output\output1.sb > test_output\output1.txt
+
+.\elftosb2\Debug\elftosb -Vdz -p bdfiles -p test_files -fmx28 -c habtest.bd -o test_output\output2.sb plugin_hello redboot_gcc.srec hostlink
+.\sbtool\Debug\sbtool -Vdz test_output\output2.sb > test_output\output2.txt
+
+.\elftosb2\Debug\elftosb -Vdz -p bdfiles -p test_files -fmx28 -c basic_test_cmd.e -o test_output\output3.sb plugin_hello redboot_gcc.srec hostlink sd_player_gcc
+.\sbtool\Debug\sbtool -Vdz test_output\output2.sb > test_output\output3.txt
+
--- /dev/null
+#! /bin/bash
+
+# Tool paths
+if [ -d /System/Library/CoreServices ]; then
+ Elftosb=./build/Debug/elftosb
+ Sbtool=./build/Debug/sbtool
+else
+ Elftosb=./bld/linux/elftosb
+ Sbtool=./bld/linux/sbtool
+fi
+
+# Create test output file directory
+mkdir -p test_output
+
+# simple.e
+$Elftosb -Vdz -p bdfiles -p test_files -fmx28 -c simple.e -o test_output/output1.sb plugin_hello redboot_gcc.srec hostlink
+$Sbtool -Vdz test_output/output1.sb > test_output/output1.txt
+
+# habtest.bd
+$Elftosb -Vdz -p bdfiles -p test_files -fmx28 -c habtest.bd -o test_output/output2.sb plugin_hello redboot_gcc.srec hostlink
+$Sbtool -Vdz test_output/output2.sb > test_output/output2.txt
+
+# basic_test_cmd.e
+$Elftosb -Vdz -p bdfiles -p test_files -fmx28 -c basic_test_cmd.e -o test_output/output3.sb plugin_hello redboot_gcc.srec hostlink sd_player_gcc
+$Sbtool -Vdz test_output/output3.sb > test_output/output3.txt
+
--- /dev/null
+Link Date: Wed Dec 15 10:06:16 2004\r
+Host OS: GHS_WIN32\r
+Version: ELXR 4.0 (c) 1998-2003 Green Hills Software Build: Aug 3 2004\r
+\r
+\r
+Load Map Wed Dec 15 10:06:16 2004\r
+Image Summary\r
+\r
+ Section Base Size(hex) Size(dec) SecOffs\r
+ .text 70000000 00000100 256 00000a0\r
+ .rodata 70000100 00000020 32 00001a0\r
+ .NOR.data 70000120 00000000 0 00001c0\r
+ .data 00000040 00000000 0 00001c0\r
+ .bss 00000040 00000000 0 00001c0\r
+ .nor.bss 0003d000 00000005 5 00001c0\r
+\f\r
+Load Map Wed Dec 15 10:06:16 2004\r
+Module Summary\r
+\r
+ Origin+Size Section Module\r
+70000000+000090 .text main_NOR.o\r
+70000100+000020 .rodata main_NOR.o\r
+0003d000+000005 .nor.bss main_NOR.o\r
+70000090+000070 .text tool_lib.a(sim_tools.o)\r
+\f\r
+Load Map Wed Dec 15 10:06:16 2004\r
+Global Symbols (sorted alphabetically)\r
+\r
+ 70002800 __ghs_norend\r
+ 70000000 __ghs_norstart\r
+ 0003cfc0 __ghs_ramend\r
+ 00000040 __ghs_ramstart\r
+ .text 70000000 _start\r
+ .nor.bss 0003d000 i\r
+ .text 70000090 sim_write\r
+ .nor.bss 0003d004 szHelloWorldString\r
+ .rodata 70000100 szNORHelloWorldString\r
+ .text 700000c0 test_exit\r
--- /dev/null
+Link Date: Wed Dec 15 10:14:22 2004\r
+Host OS: GHS_WIN32\r
+Version: ELXR 4.0 (c) 1998-2003 Green Hills Software Build: Aug 3 2004\r
+\r
+\r
+Load Map Wed Dec 15 10:14:22 2004\r
+Image Summary\r
+\r
+ Section Base Size(hex) Size(dec) SecOffs\r
+ .text 70000000 00000114 276 00000a0\r
+ .rodata 70000114 00000020 32 00001b4\r
+ .NOR.data 70000134 00000000 0 00001d4\r
+ .data 00000040 00000000 0 00001d4\r
+ .bss 00000040 00000000 0 00001d4\r
+ .nor.bss 0003d000 00000005 5 00001d4\r
+\f\r
+Load Map Wed Dec 15 10:14:22 2004\r
+Module Summary\r
+\r
+ Origin+Size Section Module\r
+70000000+0000a4 .text main_NOR.o\r
+70000114+000020 .rodata main_NOR.o\r
+0003d000+000005 .nor.bss main_NOR.o\r
+700000a4+000070 .text tool_lib.a(sim_tools.o)\r
+\f\r
+Load Map Wed Dec 15 10:14:22 2004\r
+Global Symbols (sorted alphabetically)\r
+\r
+ 70002800 __ghs_norend\r
+ 70000000 __ghs_norstart\r
+ 0003cfc0 __ghs_ramend\r
+ 00000040 __ghs_ramstart\r
+ .text 70000014 _start\r
+ .text 70000000 a_thumb_routine\r
+ .nor.bss 0003d000 i\r
+ .text 700000a4 sim_write\r
+ .nor.bss 0003d004 szHelloWorldString\r
+ .rodata 70000114 szNORHelloWorldString\r
+ .text 700000d4 test_exit\r
--- /dev/null
+Link Date: Wed Dec 15 10:09:42 2004\r
+Host OS: GHS_WIN32\r
+Version: ELXR 4.0 (c) 1998-2003 Green Hills Software Build: Aug 3 2004\r
+\r
+\r
+Load Map Wed Dec 15 10:09:42 2004\r
+Image Summary\r
+\r
+ Section Base Size(hex) Size(dec) SecOffs\r
+ .text 70000000 000000a0 160 00000a0\r
+ .rodata 700000a0 00000020 32 0000140\r
+ .NOR.data 700000c0 00000000 0 0000160\r
+ .data 00000040 00000000 0 0000160\r
+ .bss 00000040 00000000 0 0000160\r
+ .nor.bss 0003d000 00000005 5 0000160\r
+\f\r
+Load Map Wed Dec 15 10:09:42 2004\r
+Module Summary\r
+\r
+ Origin+Size Section Module\r
+70000000+00005c .text main_NOR.o\r
+700000a0+000020 .rodata main_NOR.o\r
+0003d000+000005 .nor.bss main_NOR.o\r
+7000005c+000044 .text tool_lib.a(sim_tools.o)\r
+\f\r
+Load Map Wed Dec 15 10:09:42 2004\r
+Global Symbols (sorted alphabetically)\r
+\r
+ 70002800 __ghs_norend\r
+ 70000000 __ghs_norstart\r
+ 0003cfc0 __ghs_ramend\r
+ 00000040 __ghs_ramstart\r
+ .text 70000000 _start\r
+ .nor.bss 0003d000 i\r
+ .text 7000005c sim_write\r
+ .nor.bss 0003d004 szHelloWorldString\r
+ .rodata 700000a0 szNORHelloWorldString\r
+ .text 70000072 test_exit\r
--- /dev/null
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--- /dev/null
+F8B5A7C69EE6F795513B12227163A79C
projects / karo-tx-uboot.git / commitdiff
