am335x: fix GPMC config for NAND and NOR SPL boot

GPMC controller is common IP to interface with both NAND and NOR flash devices.
Also, it supports max 8 chip-selects, which can be independently connected to
any of the devices.
But ROM code expects the boot-device to be connected to only chip-select[0].
Thus to resolve conflict between NOR and NAND boot. This patch:
- combines NOR and NAND configs spread in board files to common gpmc_init()
- configures GPMC based on boot-mode selected for SPL boot.

Signed-off-by: Pekon Gupta <pekon@ti.com>

diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c
index b6eb46678fafe1cca053beb95d4fd8209e994cf7..56c9e7dbceb306fb22fec21454c3fff550f5252b 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/mem.c
+++ b/arch/arm/cpu/armv7/am33xx/mem.c
@@ -22,17 +22,6 @@
 
 struct gpmc *gpmc_cfg;
 
 
 struct gpmc *gpmc_cfg;
 

-#if defined(CONFIG_CMD_NAND)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
-       M_NAND_GPMC_CONFIG1,
-       M_NAND_GPMC_CONFIG2,
-       M_NAND_GPMC_CONFIG3,
-       M_NAND_GPMC_CONFIG4,
-       M_NAND_GPMC_CONFIG5,
-       M_NAND_GPMC_CONFIG6, 0
-};
-#endif
-

 
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
                        u32 size)
 
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
                        u32 size)


@@ -61,11 +50,34 @@ void gpmc_init(void)
 {
        /* putting a blanket check on GPMC based on ZeBu for now */
        gpmc_cfg = (struct gpmc *)GPMC_BASE;
 {
        /* putting a blanket check on GPMC based on ZeBu for now */
        gpmc_cfg = (struct gpmc *)GPMC_BASE;

-
-#ifdef CONFIG_CMD_NAND
-       const u32 *gpmc_config = NULL;
-       u32 base = 0;
+#if defined(CONFIG_NOR)
+/* configure GPMC for NOR */
+       const u32 gpmc_regs[GPMC_MAX_REG] = {   STNOR_GPMC_CONFIG1,
+                                               STNOR_GPMC_CONFIG2,
+                                               STNOR_GPMC_CONFIG3,
+                                               STNOR_GPMC_CONFIG4,
+                                               STNOR_GPMC_CONFIG5,
+                                               STNOR_GPMC_CONFIG6,
+                                               STNOR_GPMC_CONFIG7
+                                               };
+       u32 size = GPMC_SIZE_16M;
+       u32 base = CONFIG_SYS_FLASH_BASE;
+#elif defined(CONFIG_NAND)
+/* configure GPMC for NAND */
+       const u32  gpmc_regs[GPMC_MAX_REG] = {  M_NAND_GPMC_CONFIG1,
+                                               M_NAND_GPMC_CONFIG2,
+                                               M_NAND_GPMC_CONFIG3,
+                                               M_NAND_GPMC_CONFIG4,
+                                               M_NAND_GPMC_CONFIG5,
+                                               M_NAND_GPMC_CONFIG6,
+                                               0
+                                               };
+       u32 size = GPMC_SIZE_256M;
+       u32 base = CONFIG_SYS_NAND_BASE;
+#else
+       const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };

        u32 size = 0;
        u32 size = 0;

+       u32 base = 0;

 #endif
        /* global settings */
        writel(0x00000008, &gpmc_cfg->sysconfig);
 #endif
        /* global settings */
        writel(0x00000008, &gpmc_cfg->sysconfig);


@@ -81,12 +93,6 @@ void gpmc_init(void)
         */
        writel(0, &gpmc_cfg->cs[0].config7);
        sdelay(1000);
         */
        writel(0, &gpmc_cfg->cs[0].config7);
        sdelay(1000);

-
-#ifdef CONFIG_CMD_NAND
-       gpmc_config = gpmc_m_nand;
-
-       base = PISMO1_NAND_BASE;
-       size = PISMO1_NAND_SIZE;
-       enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#endif
+       /* enable chip-select specific configurations */
+       enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);

 }
 }

diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h
index 983ea28dc0ff689cfd8bb611221525a0a866818d..e7e8c58b0002662c5a74043a4b84508a0170f3a9 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/mem.h
+++ b/arch/arm/include/asm/arch-am33xx/mem.h
@@ -68,9 +68,4 @@
 #define PISMO2_NAND_CS0                7
 #define PISMO2_NAND_CS1                8
 
 #define PISMO2_NAND_CS0                7
 #define PISMO2_NAND_CS1                8
 

-/* make it readable for the gpmc_init */
-#define PISMO1_NOR_BASE        FLASH_BASE
-#define PISMO1_NAND_BASE       CONFIG_SYS_NAND_BASE
-#define PISMO1_NAND_SIZE       GPMC_SIZE_256M
-

 #endif /* endif _MEM_H_ */
 #endif /* endif _MEM_H_ */

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 57fedab340af29e767245aec6768d316104867a3..0299dd6486f093679ac2b6fbf2591bd03ced2dd4 100644 (file)
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -481,26 +481,14 @@ void sdram_init(void)
  */
 int board_init(void)
 {
  */
 int board_init(void)
 {

-#ifdef CONFIG_NOR
-       const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
-               STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4,
-               STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
-#endif
-

 #if defined(CONFIG_HW_WATCHDOG)
        hw_watchdog_init();
 #endif
 
        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 #if defined(CONFIG_HW_WATCHDOG)
        hw_watchdog_init();
 #endif
 
        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

-
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)

        gpmc_init();
        gpmc_init();

-
-#ifdef CONFIG_NOR
-       /* Reconfigure CS0 for NOR instead of NAND. */
-       enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0],
-                             CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M);

 #endif
 #endif

-

        return 0;
 }
 
        return 0;
 }