}
}
-void ocotp_clk_enable(void)
-{
- u32 reg = readl(&imx_ccm->CCGR2);
- reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
- writel(reg, &imx_ccm->CCGR2);
-}
-
-void ocotp_clk_disable(void)
-{
- u32 reg = readl(&imx_ccm->CCGR2);
- reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
- writel(reg, &imx_ccm->CCGR2);
-}
-
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
struct mx6_ocotp_regs *const ocotp_regs = (void *)OCOTP_BASE_ADDR;
if (!thermal_calib) {
- ocotp_clk_enable();
+ enable_ocotp_clk(1);
writel(1, &ocotp_regs->hw_ocotp_read_ctrl);
thermal_calib = readl(&ocotp_regs->hw_ocotp_ana1);
writel(0, &ocotp_regs->hw_ocotp_read_ctrl);
- ocotp_clk_disable();
+ enable_ocotp_clk(0);
}
if (thermal_calib == 0 || thermal_calib == 0xffffffff)
void ipu_di_clk_disable(int di);
void ldb_clk_enable(int ldb);
void ldb_clk_disable(int ldb);
-void ocotp_clk_enable(void);
-void ocotp_clk_disable(void);
#endif /* __ASM_ARCH_CLOCK_H */