static const struct gpio tx51_gpios[] = {
/* RESET_OUT */
- { TX51_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_LOW, "RESET_OUT", },
+ { TX51_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "RESET_OUT", },
/* FEC PHY control GPIOs */
- { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */
- { TX51_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */
- { TX51_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, /* PHY INT (TX_ER) */
+ { TX51_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */
+ { TX51_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */
+ { TX51_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", }, /* PHY INT (TX_ER) */
/* FEC PHY strap pins */
- { IMX_GPIO_NR(3, 11), GPIOF_OUTPUT_INIT_LOW, "FEC PHY REGOFF", }, /* RX_CLK/REGOFF */
- { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE0", }, /* RXD0/Mode0 */
- { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE1", }, /* RXD1/Mode1 */
- { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE2", }, /* RXD2/Mode2 */
- { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
- { IMX_GPIO_NR(3, 10), GPIOF_OUTPUT_INIT_LOW, "FEC PHY RMII", }, /* COL/RMII/CRSDV */
- { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
+ { IMX_GPIO_NR(3, 11), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY REGOFF", }, /* RX_CLK/REGOFF */
+ { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY MODE0", }, /* RXD0/Mode0 */
+ { IMX_GPIO_NR(2, 23), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY MODE1", }, /* RXD1/Mode1 */
+ { IMX_GPIO_NR(2, 27), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY MODE2", }, /* RXD2/Mode2 */
+ { IMX_GPIO_NR(2, 28), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
+ { IMX_GPIO_NR(3, 10), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RMII", }, /* COL/RMII/CRSDV */
+ { IMX_GPIO_NR(2, 30), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
/* module internal I2C bus */
- { IMX_GPIO_NR(4, 17), GPIOF_INPUT, "I2C1 SDA", },
- { IMX_GPIO_NR(4, 16), GPIOF_INPUT, "I2C1 SCL", },
+ { IMX_GPIO_NR(4, 17), GPIOFLAG_INPUT, "I2C1 SDA", },
+ { IMX_GPIO_NR(4, 16), GPIOFLAG_INPUT, "I2C1 SCL", },
/* Unconnected pins */
- { IMX_GPIO_NR(1, 0), GPIOF_OUTPUT_INIT_LOW, "N/C", },
- { IMX_GPIO_NR(1, 1), GPIOF_OUTPUT_INIT_LOW, "N/C", },
+ { IMX_GPIO_NR(1, 0), GPIOFLAG_OUTPUT_INIT_LOW, "N/C", },
+ { IMX_GPIO_NR(1, 1), GPIOFLAG_OUTPUT_INIT_LOW, "N/C", },
};
/*
cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
ret = gpio_request_one(cfg->cd_gpio,
- GPIOF_INPUT, "MMC CD");
+ GPIOFLAG_INPUT, "MMC CD");
if (ret) {
printf("Error %d requesting GPIO%d_%d\n",
ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
#define PHYAD4 ((CONFIG_FEC_MXC_PHYADDR >> 4) & !(CONFIG_FEC_MXC_PHYADDR >> 5))
static struct gpio tx51_fec_gpios[] = {
- { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY POWER", },
- { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode0", }, /* RXD0/Mode0 */
- { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode1", }, /* RXD1/Mode1 */
- { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode2", }, /* RXD2/Mode2 */
- { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
+ { TX51_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY POWER", },
+ { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY Mode0", }, /* RXD0/Mode0 */
+ { IMX_GPIO_NR(2, 23), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY Mode1", }, /* RXD1/Mode1 */
+ { IMX_GPIO_NR(2, 27), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY Mode2", }, /* RXD2/Mode2 */
+ { IMX_GPIO_NR(2, 28), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
#if PHYAD4
- { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
+ { IMX_GPIO_NR(2, 30), GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
#else
- { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
+ { IMX_GPIO_NR(2, 30), GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
#endif
};
/* Deassert RESET to the external phy */
gpio_set_value(TX51_FEC_RST_GPIO, 1);
- /* Without this delay the PHY won't work, though nothing in
- * the datasheets suggests that it should be necessary!
+ /*
+ * Due to an RC-filter in the PHY RESET line, a minimum
+ * delay of 535us is required to let the RESET line rise
+ * above the logic high threshold of the PHY input pin.
*/
- udelay(400);
+ udelay(550);
imx_iomux_v3_setup_multiple_pads(tx51_fec_pads,
ARRAY_SIZE(tx51_fec_pads));
};
static const struct gpio stk5_gpios[] = {
- { TX51_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
+ { TX51_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
- { IMX_GPIO_NR(1, 4), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY clk enable", },
- { IMX_GPIO_NR(1, 6), GPIOF_INPUT, "USBOTG OC", },
- { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY reset", },
- { IMX_GPIO_NR(1, 8), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
- { IMX_GPIO_NR(1, 9), GPIOF_INPUT, "USBH1 OC", },
+ { IMX_GPIO_NR(1, 4), GPIOFLAG_OUTPUT_INIT_LOW, "ULPI PHY clk enable", },
+ { IMX_GPIO_NR(1, 6), GPIOFLAG_INPUT, "USBOTG OC", },
+ { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "ULPI PHY reset", },
+ { IMX_GPIO_NR(1, 8), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
+ { IMX_GPIO_NR(1, 9), GPIOFLAG_INPUT, "USBH1 OC", },
};
#ifdef CONFIG_LCD
.vl_col = 1600,
.vl_row = 1200,
- .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+ .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
.cmap = tx51_cmap,
};
};
static const struct gpio stk5_lcd_gpios[] = {
- { TX51_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
- { TX51_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
- { TX51_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+ { TX51_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
+ { TX51_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
+ { TX51_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
};
void lcd_ctrl_init(void *lcdbase)
panel_info.vl_bpix = LCD_COLOR16;
break;
default:
- panel_info.vl_bpix = LCD_COLOR24;
+ panel_info.vl_bpix = LCD_COLOR32;
}
p->pixclock = KHZ2PICOS(refresh *
"edt,edt-ft5x06",
};
- void ft_board_setup(void *blob, bd_t *bd)
+ int ft_board_setup(void *blob, bd_t *bd)
{
const char *video_mode = karo_get_vmode(getenv("video_mode"));
int ret;
ret = fdt_increase_size(blob, 4096);
- if (ret)
+ if (ret) {
printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
-
+ return ret;
+ }
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
fdt_fixup_ethernet(blob);
ARRAY_SIZE(tx51_touchpanels));
karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
karo_fdt_update_fb_mode(blob, video_mode);
+
+ return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
/*
- * Copyright (C) 2012 <LW@KARO-electronics.de>
+ * Copyright (C) 2012-2015 <LW@KARO-electronics.de>
*
* SPDX-License-Identifier: GPL-2.0
*
#ifndef __CONFIG_H
#define __CONFIG_H
- #include <asm/sizes.h>
+ #include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
+ #include "mx6_common.h"
/*
* Ka-Ro TX6 board - SoC configuration
*/
- #define CONFIG_MX6
#define CONFIG_SYS_MX6_HCLK 24000000
#define CONFIG_SYS_MX6_CLK32 32768
#define CONFIG_SYS_HZ 1000 /* Ticks per second */
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_BOARD_EARLY_INIT_F
+ #define CONFIG_SYS_GENERIC_BOARD
- #ifndef CONFIG_MFG
+ #ifndef CONFIG_TX6_UBOOT_MFG
/* LCD Logo and Splash screen support */
- #define CONFIG_LCD
#ifdef CONFIG_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_VIDEO_IPUV3
#define CONFIG_IPUV3_CLK (CONFIG_SYS_SDRAM_CLK * 1000000 / 2)
#define CONFIG_LCD_LOGO
- #define LCD_BPP LCD_COLOR24
+ #define LCD_BPP LCD_COLOR32
#define CONFIG_CMD_BMP
#define CONFIG_VIDEO_BMP_RLE8
#endif /* CONFIG_LCD */
- #endif /* CONFIG_MFG */
+ #endif /* CONFIG_TX6_UBOOT_MFG */
/*
* Memory configuration options
#define PHYS_SDRAM_1 0x10000000 /* Base address of bank 1 */
#ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
#define PHYS_SDRAM_1_WIDTH CONFIG_SYS_SDRAM_BUS_WIDTH
+ #elif defined(CONFIG_SYS_SDRAM_BUS_WIDTH_32)
+ #define PHYS_SDRAM_1_WIDTH 32
+ #elif defined(CONFIG_SYS_SDRAM_BUS_WIDTH_16)
+ #define PHYS_SDRAM_1_WIDTH 16
#else
#define PHYS_SDRAM_1_WIDTH 64
#endif
#define PHYS_SDRAM_1_SIZE (SZ_512M / 32 * PHYS_SDRAM_1_WIDTH)
- #ifdef CONFIG_MX6Q
+ #ifdef CONFIG_SOC_MX6Q
#define CONFIG_SYS_SDRAM_CLK 528
#else
#define CONFIG_SYS_SDRAM_CLK 400
#endif
#define CONFIG_STACKSIZE SZ_128K
+ #define CONFIG_SPL_STACK (IRAM_BASE_ADDR + SZ_16K)
#define CONFIG_SYS_MALLOC_LEN SZ_8M
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M)
* U-Boot general configurations
*/
#define CONFIG_SYS_LONGHELP
- #if defined(CONFIG_MX6Q)
+ #if defined(CONFIG_SOC_MX6Q)
#define CONFIG_SYS_PROMPT "TX6Q U-Boot > "
- #elif defined(CONFIG_MX6DL)
+ #elif defined(CONFIG_SOC_MX6DL)
#define CONFIG_SYS_PROMPT "TX6DL U-Boot > "
- #elif defined(CONFIG_MX6S)
+ #elif defined(CONFIG_SOC_MX6S)
#define CONFIG_SYS_PROMPT "TX6S U-Boot > "
#else
#error Unsupported i.MX6 processor variant
#define CONFIG_CMDLINE_EDITING /* Command history etc */
#define CONFIG_SYS_64BIT_VSPRINTF
- #define CONFIG_SYS_NO_FLASH
/*
* Flattened Device Tree (FDT) support
*/
- #define CONFIG_OF_LIBFDT
#ifdef CONFIG_OF_LIBFDT
- #ifndef CONFIG_NO_NAND
- #define CONFIG_FDT_FIXUP_PARTITIONS
+ #ifdef CONFIG_TX6_NAND
#endif
- #define CONFIG_OF_BOARD_SETUP
#endif /* CONFIG_OF_LIBFDT */
/*
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_SETUP_MEMORY_TAGS
- #ifndef CONFIG_MFG
+ #ifndef CONFIG_TX6_UBOOT_MFG
#define CONFIG_BOOTDELAY 1
#else
#define CONFIG_BOOTDELAY 0
#endif
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_SYS_AUTOLOAD "no"
++#define DEFAULT_BOOTCMD "run bootcmd_${boot_mode} bootm_cmd"
+ #ifndef CONFIG_TX6_UBOOT_MFG
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_BOOTARGS "init=/linuxrc console=ttymxc0,115200 ro debug panic=1"
- #define DEFAULT_BOOTCMD "run bootcmd_${boot_mode} bootm_cmd"
- #ifndef CONFIG_MFG
-#define CONFIG_BOOTCOMMAND "run bootcmd_${boot_mode} bootm_cmd"
+#define CONFIG_BOOTCOMMAND DEFAULT_BOOTCMD
#else
-#define CONFIG_BOOTCOMMAND "env import " xstr(CONFIG_BOOTCMD_MFG_LOADADDR) ";run bootcmd_mfg"
+#define CONFIG_BOOTCOMMAND "set bootcmd '" DEFAULT_BOOTCMD "';" \
+ "env import " xstr(CONFIG_BOOTCMD_MFG_LOADADDR) ";run bootcmd_mfg"
#define CONFIG_BOOTCMD_MFG_LOADADDR 10500000
#define CONFIG_DELAY_ENVIRONMENT
- #endif /* CONFIG_MFG */
+ #endif /* CONFIG_TX6_UBOOT_MFG */
#define CONFIG_LOADADDR 18000000
#define CONFIG_FDTADDR 11000000
#define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
#define CONFIG_SYS_FDT_ADDR _pfx(0x, CONFIG_FDTADDR)
- #define CONFIG_HW_WATCHDOG
#ifndef CONFIG_SYS_LVDS_IF
#define DEFAULT_VIDEO_MODE "VGA"
#else
/*
* Extra Environments
*/
+ #ifndef CONFIG_TX6_UBOOT_MFG
#ifdef CONFIG_ENV_IS_NOWHERE
#define CONFIG_EXTRA_ENV_SETTINGS \
"autostart=no\0" \
"cpu_clk=800\0" \
"default_bootargs=set bootargs " CONFIG_BOOTARGS \
" ${append_bootargs}\0" \
+ EMMC_BOOT_PART_STR \
+ EMMC_BOOT_ACK_STR \
"fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \
CONFIG_SYS_FDTSAVE_CMD \
"mtdids=" MTDIDS_DEFAULT "\0" \
"touchpanel=tsc2007\0" \
"video_mode=" DEFAULT_VIDEO_MODE "\0"
#endif /* CONFIG_ENV_IS_NOWHERE */
+ #endif /* CONFIG_TX6_UBOOT_MFG */
- #ifndef CONFIG_NO_NAND
- #define CONFIG_SYS_DEFAULT_BOOT_MODE "nand"
+ #ifdef CONFIG_TX6_NAND
+ #define CONFIG_SYS_DEFAULT_BOOT_MODE "nand"
#define CONFIG_SYS_BOOT_CMD_NAND \
"bootcmd_nand=set autostart no;run bootargs_ubifs;nboot linux\0"
#define CONFIG_SYS_FDTSAVE_CMD \
#define MTDIDS_DEFAULT "nand0=" MTD_NAME
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define MMC_ROOT_STR " root=/dev/mmcblk0p2 rootwait\0"
- #define ROOTPART_UUID_STR ""
+ #define ROOTPART_UUID_STR ""
+ #define EMMC_BOOT_ACK_STR ""
+ #define EMMC_BOOT_PART_STR ""
#else
- #define CONFIG_SYS_DEFAULT_BOOT_MODE "mmc"
- #define CONFIG_SYS_BOOT_CMD_NAND ""
+ #define CONFIG_SYS_DEFAULT_BOOT_MODE "mmc"
+ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+ #define CONFIG_SYS_BOOT_CMD_NAND ""
#define CONFIG_SYS_FDTSAVE_CMD \
- "fdtsave=mmc open 0 1;mmc write ${fdtaddr} " \
- xstr(CONFIG_SYS_DTB_BLKNO) " 80;mmc close 0 1\0"
- #define MMC_ROOT_STR " root=PARTUUID=${rootpart_uuid} rootwait\0"
- #define ROOTPART_UUID_STR "rootpart_uuid=0cc66cc0-02\0"
+ "fdtsave=mmc partconf 0 ${emmc_boot_ack} ${emmc_boot_part} 1" \
+ ";mmc write ${fdtaddr} " xstr(CONFIG_SYS_DTB_BLKNO) " 80" \
+ ";mmc partconf 0 ${emmc_boot_ack} ${emmc_boot_part} 0\0"
#define MTD_NAME ""
#define MTDIDS_DEFAULT ""
- #define CONFIG_SUPPORT_EMMC_BOOT
- #define CONFIG_MMC_BOOT_DEV 0
- #endif
-
- /*
- * U-Boot Commands
- */
- #include <config_cmd_default.h>
- #define CONFIG_CMD_CACHE
- #define CONFIG_CMD_MMC
- #ifndef CONFIG_NO_NAND
- #define CONFIG_CMD_NAND
- #define CONFIG_CMD_MTDPARTS
- #endif
- #define CONFIG_CMD_BOOTCE
- #define CONFIG_CMD_BOOTZ
- #define CONFIG_CMD_TIME
- #define CONFIG_CMD_I2C
- #define CONFIG_CMD_MEMTEST
+ #define MMC_ROOT_STR " root=PARTUUID=${rootpart_uuid} rootwait\0"
+ #define ROOTPART_UUID_STR "rootpart_uuid=0cc66cc0-02\0"
+ #define EMMC_BOOT_ACK_STR "emmc_boot_ack=1\0"
+ #define EMMC_BOOT_PART_STR "emmc_boot_part=" \
+ xstr(CONFIG_SYS_MMCSD_FS_BOOT_PARTITION) "\0"
+ #endif /* CONFIG_TX6_NAND */
/*
* Serial Driver
/*
* Ethernet Driver
*/
- #define CONFIG_FEC_MXC
#ifdef CONFIG_FEC_MXC
/* This is required for the FEC driver to work with cache enabled */
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
- #define CONFIG_SYS_CACHELINE_SIZE 64
#define IMX_FEC_BASE ENET_BASE_ADDR
- #define CONFIG_FEC_MXC_PHYADDR 0
- #define CONFIG_PHYLIB
- #define CONFIG_PHY_SMSC
- #define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE RMII
- #define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
- #define CONFIG_CMD_MII
- #define CONFIG_CMD_DHCP
- #define CONFIG_CMD_PING
- /* Add for working with "strict" DHCP server */
- #define CONFIG_BOOTP_SUBNETMASK
- #define CONFIG_BOOTP_GATEWAY
- #define CONFIG_BOOTP_DNS
#endif
/*
* I2C Configs
*/
- #ifdef CONFIG_CMD_I2C
- #define CONFIG_HARD_I2C
- #define CONFIG_I2C_MXC
+ #ifdef CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
- #define CONFIG_SYS_I2C_MX6_PORT1
#define CONFIG_SYS_I2C_SPEED 400000
#if defined(CONFIG_TX6_REV)
#if CONFIG_TX6_REV == 0x1
#define CONFIG_RN5T567 /* TX6_REV == 3 */
#endif /* CONFIG_CMD_I2C */
- #ifndef CONFIG_ENV_IS_NOWHERE
- /* define one of the following options:
- #define CONFIG_ENV_IS_IN_NAND
- #define CONFIG_ENV_IS_IN_MMC
- */
- #define CONFIG_ENV_IS_IN_NAND
- #endif
#define CONFIG_ENV_OVERWRITE
/*
* NAND flash driver
*/
- #ifndef CONFIG_NO_NAND
- #define CONFIG_MTD_DEVICE
- #if 0
- #define CONFIG_MTD_DEBUG
- #define CONFIG_MTD_DEBUG_VERBOSE 4
- #endif
- #define CONFIG_NAND_MXS
- #define CONFIG_NAND_MXS_NO_BBM_SWAP
- #define CONFIG_APBH_DMA
- #define CONFIG_APBH_DMA_BURST
- #define CONFIG_APBH_DMA_BURST8
- #define CONFIG_CMD_NAND_TRIMFFS
+ #ifdef CONFIG_TX6_NAND
#define CONFIG_SYS_MXS_DMA_CHANNEL 4
#define CONFIG_SYS_MAX_FLASH_BANKS 0x1
#define CONFIG_SYS_NAND_MAX_CHIPS 0x1
#define CONFIG_SYS_MAX_NAND_DEVICE 0x1
- #define CONFIG_SYS_NAND_5_ADDR_CYCLE
- #define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BASE 0x00000000
- #define CONFIG_CMD_ROMUPDATE
+ #define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
#define CONFIG_ENV_SIZE SZ_128K
#define CONFIG_ENV_RANGE (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#undef CONFIG_ENV_IS_IN_NAND
- #endif /* CONFIG_NO_NAND */
+ #endif /* CONFIG_TX6_NAND */
#ifdef CONFIG_ENV_OFFSET_REDUND
#define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_SYS_ENV_PART_SIZE) \
/*
* MMC Driver
*/
- #ifdef CONFIG_CMD_MMC
- #define CONFIG_MMC
- #define CONFIG_GENERIC_MMC
- #define CONFIG_FSL_ESDHC
- #define CONFIG_FSL_USDHC
+ #ifdef CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-
- #define CONFIG_DOS_PARTITION
+ #endif
+ #ifdef CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
#define CONFIG_CMD_EXT2
#define CONFIG_ENV_SIZE SZ_4K
#endif
- #ifndef CONFIG_NO_NAND
+ #ifdef CONFIG_TX6_NAND
#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
xstr(CONFIG_SYS_U_BOOT_PART_SIZE) \
"@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) \
projects / karo-tx-uboot.git / commitdiff