mpc83xx: Update DIMM data bus width test to support 40-bit width

32-bit wide ECC memory modules report 40-bit width.
Changed the DIMM data bus width test to 'less than 64' instead of 'equal 32'.

Signed-off-by: Lee Nipper <lee.nipper@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 97ac7bb3d95a0f00bafe5745c9e8b4eb43ca72e0..70cd410298af240c4a440ad9c6bccd50a48f8987 100644 (file)
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -601,7 +601,7 @@ long int spd_sdram()
        debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
 
        /* Check DIMM data bus width */
-       if (spd.dataw_lsb == 0x20) {
+       if (spd.dataw_lsb < 64) {
                if (spd.mem_type == SPD_MEMTYPE_DDR)
                        burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
                else
@@ -763,7 +763,7 @@ long int spd_sdram()
                sdram_cfg |= SDRAM_CFG_RD_EN;
 
        /* The DIMM is 32bit width */
-       if (spd.dataw_lsb == 0x20) {
+       if (spd.dataw_lsb < 64) {
                if (spd.mem_type == SPD_MEMTYPE_DDR)
                        sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
                if (spd.mem_type == SPD_MEMTYPE_DDR2)