#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START
#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END
- /* CONTROL */
- #define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
- #define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000)
- #define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000)
-
- /* LPDDR2 IO regs */
- #define LPDDR2_IO_REGS_BASE 0x4A100638
-
/* CONTROL_ID_CODE */
#define CONTROL_ID_CODE 0x4A002204
/* Watchdog Timer2 - MPU watchdog */
#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
- /* 32KTIMER */
- #define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
-
/* GPMC */
#define OMAP44XX_GPMC_BASE 0x50000000
- /* SYSTEM CONTROL MODULE */
- #define SYSCTRL_GENERAL_CORE_BASE 0x4A002000
-
/*
* Hardware Register Details
*/
*/
#define NON_SECURE_SRAM_START 0x40304000
#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
+#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4030D000
+
+ /* ABB settings */
+ #define OMAP_ABB_SETTLING_TIME 50
+ #define OMAP_ABB_CLOCK_CYCLES 16
+
+ /* ABB tranxdone mask */
+ #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7)
+
#endif
#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START
#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END
- /* CONTROL */
- #define CTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
- #define CONTROL_PADCONF_CORE (CTRL_BASE + 0x0800)
- #define CONTROL_PADCONF_WKUP (OMAP54XX_L4_WKUP_BASE + 0xc800)
-
- /* LPDDR2 IO regs. To be verified */
- #define LPDDR2_IO_REGS_BASE 0x4A100638
-
- /* CONTROL_ID_CODE */
- #define CONTROL_ID_CODE (CTRL_BASE + 0x204)
+ /* CONTROL ID CODE */
+ #define CONTROL_CORE_ID_CODE 0x4A002204
+ #define CONTROL_WKUP_ID_CODE 0x4AE0C204
+
+ #ifdef CONFIG_DRA7XX
+ #define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE
+ #else
+ #define CONTROL_ID_CODE CONTROL_CORE_ID_CODE
+ #endif
/* To be verified */
#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
- /* STD_FUSE_PROD_ID_1 */
- #define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
- #define PROD_ID_1_SILICON_TYPE_SHIFT 16
- #define PROD_ID_1_SILICON_TYPE_MASK (3 << 16)
-
/* UART */
#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
/* Watchdog Timer2 - MPU watchdog */
#define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
- /* 32KTIMER */
- #define SYNC_32KTIMER_BASE (OMAP54XX_L4_WKUP_BASE + 0x4000)
-
/* GPMC */
#define OMAP54XX_GPMC_BASE 0x50000000
- /* SYSTEM CONTROL MODULE */
- #define SYSCTRL_GENERAL_CORE_BASE 0x4A002000
-
/*
* Hardware Register Details
*/
/* CONTROL_EFUSE_2 */
#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
+ #define SDCARD_BIAS_PWRDNZ (1 << 27)
#define SDCARD_PWRDNZ (1 << 26)
#define SDCARD_BIAS_HIZ_MODE (1 << 25)
- #define SDCARD_BIAS_PWRDNZ (1 << 22)
#define SDCARD_PBIASLITE_VMODE (1 << 21)
#ifndef __ASSEMBLY__
#define EFUSE_4 0x45145100
#endif /* __ASSEMBLY__ */
- /*
- * Non-secure SRAM Addresses
- * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
- * at 0x40304000(EMU base) so that our code works for both EMU and GP
- */
+ #ifdef CONFIG_DRA7XX
+ #define NON_SECURE_SRAM_START 0x40300000
+ #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
+ #else
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
+ #endif
+#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
+
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000
- /* Silicon revisions */
- #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
- #define OMAP4430_ES1_0 0x44300100
- #define OMAP4430_ES2_0 0x44300200
- #define OMAP4430_ES2_1 0x44300210
- #define OMAP4430_ES2_2 0x44300220
- #define OMAP4430_ES2_3 0x44300230
- #define OMAP4460_ES1_0 0x44600100
- #define OMAP4460_ES1_1 0x44600110
-
/* CONTROL_SRCOMP_XXX_SIDE */
#define OVERRIDE_XS_SHIFT 30
#define OVERRIDE_XS_MASK (1 << 30)
#define SRCODE_OVERRIDE_SEL_XS_SHIFT 0
#define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0)
+ /* ABB settings */
+ #define OMAP_ABB_SETTLING_TIME 50
+ #define OMAP_ABB_CLOCK_CYCLES 16
+
+ /* ABB tranxdone mask */
+ #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7)
+
+ /* ABB efuse masks */
+ #define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24)
+ #define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29)
+ #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10)
+ #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0)
+
#ifndef __ASSEMBLY__
struct srcomp_params {
s8 divide_factor;
u32 ctrl_ddrio_1;
u32 ctrl_ddrio_2;
u32 ctrl_emif_sdram_config_ext;
+ u32 ctrl_ddr_ctrl_ext_0;
};
#endif /* __ASSEMBLY__ */
#endif
#include <common.h>
- #define NUM_SYS_CLKS 8
+ #define NUM_SYS_CLKS 7
struct prcm_regs {
/* cm1.ckgen */
u32 cm_l3init_fsusb_clkctrl;
u32 cm_l3init_ocp2scp1_clkctrl;
+ u32 prm_irqstatus_mpu_2;
+
/* cm2.l4per */
u32 cm_l4per_clkstctrl;
u32 cm_l4per_dynamicdep;
/* l4 wkup regs */
u32 cm_abe_pll_ref_clksel;
u32 cm_sys_clksel;
+ u32 cm_abe_pll_sys_clksel;
u32 cm_wkup_clkstctrl;
u32 cm_wkup_l4wkup_clkctrl;
u32 cm_wkup_wdtimer1_clkctrl;
u32 prm_sldo_mpu_ctrl;
u32 prm_sldo_mm_setup;
u32 prm_sldo_mm_ctrl;
+ u32 prm_abbldo_mpu_setup;
+ u32 prm_abbldo_mpu_ctrl;
u32 cm_div_m4_dpll_core;
u32 cm_div_m5_dpll_core;
u32 cm_l3init_usbphy_clkctrl;
u32 cm_l4per_mcbsp4_clkctrl;
u32 prm_vc_cfg_channel;
+
+ /* SCRM stuff, used by some boards */
+ u32 scrm_auxclk0;
+ u32 scrm_auxclk1;
};
struct omap_sys_ctrl_regs {
u32 control_status;
+ u32 control_std_fuse_opp_vdd_mpu_2;
u32 control_core_mmr_lock1;
u32 control_core_mmr_lock2;
u32 control_core_mmr_lock3;
u32 control_ldosram_iva_voltage_ctrl;
u32 control_ldosram_mpu_voltage_ctrl;
u32 control_ldosram_core_voltage_ctrl;
+ u32 control_usbotghs_ctrl;
u32 control_padconf_core_base;
u32 control_paconf_global;
u32 control_paconf_mode;
u32 control_ddrio_0;
u32 control_ddrio_1;
u32 control_ddrio_2;
+ u32 control_ddr_control_ext_0;
u32 control_lpddr2io1_0;
u32 control_lpddr2io1_1;
u32 control_lpddr2io1_2;
u32 control_port_emif2_sdram_config;
u32 control_emif1_sdram_config_ext;
u32 control_emif2_sdram_config_ext;
+ u32 control_wkup_ldovbb_mpu_voltage_ctrl;
u32 control_smart1nopmio_padconf_0;
u32 control_smart1nopmio_padconf_1;
u32 control_padconf_mode;
u32 start_code;
unsigned gpio;
int gpio_en;
+ u32 i2c_slave_addr;
+ void (*pmic_bus_init)(void);
+ int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
+ };
+
+ /**
+ * struct volts_efuse_data - efuse definition for voltage
+ * @reg: register address for efuse
+ * @reg_bits: Number of bits in a register address, mandatory.
+ */
+ struct volts_efuse_data {
+ u32 reg;
+ u8 reg_bits;
};
struct volts {
u32 value;
u32 addr;
+ struct volts_efuse_data efuse;
struct pmic_data *pmic;
};
struct volts mpu;
struct volts core;
struct volts mm;
+ struct volts gpu;
+ struct volts eve;
+ struct volts iva;
};
extern struct prcm_regs const **prcm;
void scale_vcores(struct vcores_data const *);
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
-
- /* Max value for DPLL multiplier M */
- #define OMAP_DPLL_MAX_N 127
+ void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
+ u32 txdone, u32 txdone_mask, u32 opp);
+ s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
/* HW Init Context */
#define OMAP_INIT_CONTEXT_SPL 0
#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2
#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3
+ /* ABB */
+ #define OMAP_ABB_NOMINAL_OPP 0
+ #define OMAP_ABB_FAST_OPP 1
+ #define OMAP_ABB_SLOW_OPP 3
+ #define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK (0x1 << 0)
+ #define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK (0x1 << 1)
+ #define OMAP_ABB_CONTROL_OPP_CHANGE_MASK (0x1 << 2)
+ #define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK (0x1 << 6)
+ #define OMAP_ABB_SETUP_SR2EN_MASK (0x1 << 0)
+ #define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK (0x1 << 2)
+ #define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK (0x1 << 1)
+ #define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK (0xff << 8)
+
static inline u32 omap_revision(void)
{
extern u32 *const omap_si_rev;
return *omap_si_rev;
}
+
+ #define OMAP54xx 0x54000000
+
+ static inline u8 is_omap54xx(void)
+ {
+ extern u32 *const omap_si_rev;
+ return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
+ }
#endif
/*
/*
* SRAM scratch space entries
*/
-#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
#define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR
#define OMAP_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
#define OMAP_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
PHY_EN_DYN_PWRDN,
};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ return (serial_tstc() && serial_getc() == 'c');
+}
+#endif
+
#endif
/*
eth_setenv_enetaddr("ethaddr", mac_addr);
}
+ #ifdef CONFIG_DRIVER_TI_CPSW
if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
+ #endif
/*
*
projects / karo-tx-uboot.git / commitdiff