karo: tx6: remove obsolete write levelling code

diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S
index 7d38c6889fd12d60245b4ca5b8a1ae4863546a3c..92a27b558d4ebab9e0f84a5e58554222faac8941 100644 (file)
--- a/board/karo/tx6/lowlevel_init.S
+++ b/board/karo/tx6/lowlevel_init.S
@@ -844,7 +844,6 @@ dcd_hdr:
 
        MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
 
 
        MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
 

-#ifndef DO_WL_CALIB

 #define WL_DLY_DQS_VAL 30
 #define WL_DLY_DQS0    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS1    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS_VAL 30
 #define WL_DLY_DQS0    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS1    (WL_DLY_DQS_VAL + 0)


@@ -854,28 +853,11 @@ dcd_hdr:
 #define WL_DLY_DQS5    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS6    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS7    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS5    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS6    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS7    (WL_DLY_DQS_VAL + 0)

-#endif

        /* Write leveling */
        /* Write leveling */

-       MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
-#ifdef DO_WL_CALIB
-       MXC_DCD_ITEM(MMDC1_MDSCR, 0x00808231) /* MRS: start write leveling */
-       MXC_DCD_ITEM(MMDC1_MPWLGCR, 0x00000001) /* initiate Write leveling */
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000001)
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000f00)
-#if PHYS_SDRAM_1_WIDTH == 64
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000001)
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000f00)
-#endif /* PHYS_SDRAM_1_WIDTH == 64 */
-#else

        MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
        MXC_DCD_ITEM(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
        MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
        MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
        MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
        MXC_DCD_ITEM(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
        MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
        MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))

-#endif /* DO_WL_CALIB */
-
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-       MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
-

 
        /* DQS gating calibration */
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
 
        /* DQS gating calibration */
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */