Valentin Longchamp <valentin.longchamp@keymile.com>
km_kirkwood ARM926EJS (Kirkwood SoC)
+ kmnusa ARM926EJS (Kirkwood SoC)
+ mgcoge3un ARM926EJS (Kirkwood SoC)
+ kmcoge5un ARM926EJS (Kirkwood SoC)
portl2 ARM926EJS (Kirkwood SoC)
Nishanth Menon <nm@ti.com>
Jens Scharsig <esw@bus-elektronik.de>
eb_cpux9k2 ARM920T (AT91RM9200 SoC)
+ vl_ma2sc ARM926EJS (AT91SAM9263 SoC)
Heiko Schocher <hs@denx.de>
enbw_cmc ARM926EJS (AM1808 SoC)
magnesium i.MX27
- mgcoge3un ARM926EJS (Kirkwood SoC)
Michael Schwingen <michael@schwingen.org>
rd6281a ARM926EJS (Kirkwood SoC)
sheevaplug ARM926EJS (Kirkwood SoC)
+Michael Walle <michael@walle.cc>
+
+ lschlv2 ARM926EJS (Kirkwood SoC)
+ lsxhl ARM926EJS (Kirkwood SoC)
+
Tom Warren <twarren@nvidia.com>
harmony Tegra2 (ARM7 & A9 Dual Core)
ventana Tegra2 (ARM7 & A9 Dual Core)
paz00 Tegra2 (ARM7 & A9 Dual Core)
+ trimslice Tegra2 (ARM7 & A9 Dual Core)
+ whistler Tegra2 (ARM7 & A9 Dual Core)
Thomas Weber <weber@corscience.de>
elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
-o $(obj)u-boot.sb
+# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
+# Both images are created using mkimage (crc etc), so that the ROM
+# bootloader can check its integrity. Padding needs to be done to the
+# SPL image (with mkimage header) and not the binary. Otherwise the resulting image
+# which is loaded/copied by the ROM bootloader to SRAM doesn't fit.
+# The resulting image containing both U-Boot images is called u-boot.spr
+$(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
+ $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
+ -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER \
+ -d $(obj)spl/u-boot-spl.bin $(obj)spl/u-boot-spl.img
+ tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_SPL_PAD_TO) \
+ of=$(obj)spl/u-boot-spl-pad.img 2>/dev/null
+ dd if=$(obj)spl/u-boot-spl.img of=$(obj)spl/u-boot-spl-pad.img \
+ conv=notrunc 2>/dev/null
+ cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@
+
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
@rm -f $(obj)u-boot.ais
@rm -f $(obj)u-boot.dtb
@rm -f $(obj)u-boot.sb
+ @rm -f $(obj)u-boot.spr
@rm -f $(obj)tools/inca-swap-bytes
@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
@rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c
ldr r6, DDRVTPR
ldr r7, [r6]
- and r7, r7, $0x1f
- and r8, r7, $0x3e0
- orr r8, r7, r8
+ mov r8, r7, LSL #32-10
+ mov r8, r8, LSR #32-10 /* grab low 10 bits */
ldr r7, VTP_RECAL
orr r8, r7, r8
ldr r7, VTP_EN
VTP_MASK:
.word 0xffffdfff
VTP_RECAL:
- .word 0x40000
+ .word 0x08000
VTP_EN:
.word 0x02000
CFGTEST:
#define MPP_CTRL(i) (KW_MPP_BASE + (i* 4))
#define MPP_NR_REGS (1 + MPP_MAX/8)
-void kirkwood_mpp_conf(u32 *mpp_list)
+void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save)
{
u32 mpp_ctrl[MPP_NR_REGS];
unsigned int variant_mask;
while (*mpp_list) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);
+ unsigned int sel_save;
int shift;
if (num > MPP_MAX) {
}
shift = (num & 7) << 2;
+
+ if (mpp_save) {
+ sel_save = (mpp_ctrl[num / 8] >> shift) & 0xf;
+ *mpp_save = num | (sel_save << 8) | variant_mask;
+ mpp_save++;
+ }
+
mpp_ctrl[num / 8] &= ~(0xf << shift);
mpp_ctrl[num / 8] |= sel << shift;
}
#endif
-#ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void)
{
struct mx28_clkctrl_regs *clkctrl_regs =
return 0;
}
-#endif
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
0x00000000, 0x00010001
};
+void __mx28_adjust_memory_params(uint32_t *dram_vals)
+{
+}
+void mx28_adjust_memory_params(uint32_t *dram_vals)
+ __attribute__((weak, alias("__mx28_adjust_memory_params")));
+
void init_m28_200mhz_ddr2(void)
{
int i;
+ mx28_adjust_memory_params(dram_vals);
+
for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
LIB = $(obj)lib$(SOC).o
-COBJS := reset.o \
+COBJS-y := cpu.o \
+ reset.o \
timer.o
-SOBJS :=
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+ifdef CONFIG_SPL_BUILD
+COBJS-y += spl.o spl_boot.o
+COBJS-$(CONFIG_SPEAR600) += spear600.o
+COBJS-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
+COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
+COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
+COBJS-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
+endif
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+SRCS := $(START:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_misc.h>
+
+int arch_cpu_init(void)
+{
+ struct misc_regs *const misc_p =
+ (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ u32 periph1_clken, periph_clk_cfg;
+
+ periph1_clken = readl(&misc_p->periph1_clken);
+
+#if defined(CONFIG_SPEAR3XX)
+ periph1_clken |= MISC_GPT2ENB;
+#elif defined(CONFIG_SPEAR600)
+ periph1_clken |= MISC_GPT3ENB;
+#endif
+
+#if defined(CONFIG_PL011_SERIAL)
+ periph1_clken |= MISC_UART0ENB;
+
+ periph_clk_cfg = readl(&misc_p->periph_clk_cfg);
+ periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK;
+ periph_clk_cfg |= CONFIG_SPEAR_UART48M;
+ writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
+#endif
+#if defined(CONFIG_DESIGNWARE_ETH)
+ periph1_clken |= MISC_ETHENB;
+#endif
+#if defined(CONFIG_DW_UDC)
+ periph1_clken |= MISC_USBDENB;
+#endif
+#if defined(CONFIG_DW_I2C)
+ periph1_clken |= MISC_I2CENB;
+#endif
+#if defined(CONFIG_ST_SMI)
+ periph1_clken |= MISC_SMIENB;
+#endif
+#if defined(CONFIG_NAND_FSMC)
+ periph1_clken |= MISC_FSMCENB;
+#endif
+
+ writel(periph1_clken, &misc_p->periph1_clken);
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+#ifdef CONFIG_SPEAR300
+ printf("CPU: SPEAr300\n");
+#elif defined(CONFIG_SPEAR310)
+ printf("CPU: SPEAr310\n");
+#elif defined(CONFIG_SPEAR320)
+ printf("CPU: SPEAr320\n");
+#elif defined(CONFIG_SPEAR600)
+ printf("CPU: SPEAr600\n");
+#else
+#error CPU not supported in spear platform
+#endif
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2000-2009
+ * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_defs.h>
+
+#define FALSE 0
+#define TRUE (!FALSE)
+
+static void sel_1v8(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ u32 ddr1v8, ddr2v5;
+
+ ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+ ddr2v5 &= 0x8080ffc0;
+ ddr2v5 |= 0x78000003;
+ writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+ ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+ ddr1v8 &= 0x8080ffc0;
+ ddr1v8 |= 0x78000010;
+ writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+ while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
+ ;
+}
+
+static void sel_2v5(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ u32 ddr1v8, ddr2v5;
+
+ ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+ ddr1v8 &= 0x8080ffc0;
+ ddr1v8 |= 0x78000003;
+ writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+ ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+ ddr2v5 &= 0x8080ffc0;
+ ddr2v5 |= 0x78000010;
+ writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+ while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
+ ;
+}
+
+/*
+ * plat_ddr_init:
+ */
+void plat_ddr_init(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ u32 ddrpad;
+ u32 core3v3, ddr1v8, ddr2v5;
+
+ /* DDR pad register configurations */
+ ddrpad = readl(&misc_p->ddr_pad);
+ ddrpad &= ~DDR_PAD_CNF_MSK;
+
+#if (CONFIG_DDR_HCLK)
+ ddrpad |= 0xEAAB;
+#elif (CONFIG_DDR_2HCLK)
+ ddrpad |= 0xEAAD;
+#elif (CONFIG_DDR_PLL2)
+ ddrpad |= 0xEAAD;
+#endif
+ writel(ddrpad, &misc_p->ddr_pad);
+
+ /* Compensation register configurations */
+ core3v3 = readl(&misc_p->core_3v3_compensation);
+ core3v3 &= 0x8080ffe0;
+ core3v3 |= 0x78000002;
+ writel(core3v3, &misc_p->core_3v3_compensation);
+
+ ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+ ddr1v8 &= 0x8080ffc0;
+ ddr1v8 |= 0x78000004;
+ writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+ ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+ ddr2v5 &= 0x8080ffc0;
+ ddr2v5 |= 0x78000004;
+ writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+ if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
+ /* Software memory configuration */
+ if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
+ sel_1v8();
+ else
+ sel_2v5();
+ } else {
+ /* Hardware memory configuration */
+ if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
+ sel_1v8();
+ else
+ sel_2v5();
+ }
+}
+
+/*
+ * soc_init:
+ */
+void soc_init(void)
+{
+ /* Nothing to be done for SPEAr600 */
+}
+
+/*
+ * xxx_boot_selected:
+ *
+ * return TRUE if the particular booting option is selected
+ * return FALSE otherwise
+ */
+static u32 read_bootstrap(void)
+{
+ return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
+ & CONFIG_SPEAR_BOOTSTRAPMASK;
+}
+
+int snor_boot_selected(void)
+{
+ u32 bootstrap = read_bootstrap();
+
+ if (SNOR_BOOT_SUPPORTED) {
+ /* Check whether SNOR boot is selected */
+ if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
+ CONFIG_SPEAR_ONLYSNORBOOT)
+ return TRUE;
+
+ if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+ CONFIG_SPEAR_NORNAND8BOOT)
+ return TRUE;
+
+ if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+ CONFIG_SPEAR_NORNAND16BOOT)
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+int nand_boot_selected(void)
+{
+ u32 bootstrap = read_bootstrap();
+
+ if (NAND_BOOT_SUPPORTED) {
+ /* Check whether NAND boot is selected */
+ if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+ CONFIG_SPEAR_NORNAND8BOOT)
+ return TRUE;
+
+ if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+ CONFIG_SPEAR_NORNAND16BOOT)
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+int pnor_boot_selected(void)
+{
+ /* Parallel NOR boot is not selected in any SPEAr600 revision */
+ return FALSE;
+}
+
+int usb_boot_selected(void)
+{
+ u32 bootstrap = read_bootstrap();
+
+ if (USB_BOOT_SUPPORTED) {
+ /* Check whether USB boot is selected */
+ if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+int tftp_boot_selected(void)
+{
+ /* TFTP boot is not selected in any SPEAr600 revision */
+ return FALSE;
+}
+
+int uart_boot_selected(void)
+{
+ /* UART boot is not selected in any SPEAr600 revision */
+ return FALSE;
+}
+
+int spi_boot_selected(void)
+{
+ /* SPI boot is not selected in any SPEAr600 revision */
+ return FALSE;
+}
+
+int i2c_boot_selected(void)
+{
+ /* I2C boot is not selected in any SPEAr600 revision */
+ return FALSE;
+}
+
+int mmc_boot_selected(void)
+{
+ return FALSE;
+}
+
+void plat_late_init(void)
+{
+ spear_late_init();
+}
--- /dev/null
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_syscntl.h>
+
+inline void hang(void)
+{
+ serial_puts("### ERROR ### Please RESET the board ###\n");
+ for (;;)
+ ;
+}
+
+static void ddr_clock_init(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ u32 clkenb, ddrpll;
+
+ clkenb = readl(&misc_p->periph1_clken);
+ clkenb &= ~PERIPH_MPMCMSK;
+ clkenb |= PERIPH_MPMC_WE;
+
+ /* Intentionally done twice */
+ writel(clkenb, &misc_p->periph1_clken);
+ writel(clkenb, &misc_p->periph1_clken);
+
+ ddrpll = readl(&misc_p->pll_ctr_reg);
+ ddrpll &= ~MEM_CLK_SEL_MSK;
+#if (CONFIG_DDR_HCLK)
+ ddrpll |= MEM_CLK_HCLK;
+#elif (CONFIG_DDR_2HCLK)
+ ddrpll |= MEM_CLK_2HCLK;
+#elif (CONFIG_DDR_PLL2)
+ ddrpll |= MEM_CLK_PLL2;
+#else
+#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
+#endif
+ writel(ddrpll, &misc_p->pll_ctr_reg);
+
+ writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
+ &misc_p->periph1_clken);
+}
+
+static void mpmc_init_values(void)
+{
+ u32 i;
+ u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
+ u32 *mpmc_val_p = &mpmc_conf_vals[0];
+
+ for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++)
+ writel(*mpmc_val_p, mpmc_reg_p);
+
+ mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
+
+ /*
+ * MPMC controller start
+ * MPMC waiting for DLLLOCKREG high
+ */
+ writel(0x01000100, &mpmc_reg_p[7]);
+
+ while (!(readl(&mpmc_reg_p[3]) & 0x10000))
+ ;
+}
+
+static void mpmc_init(void)
+{
+ /* Clock related settings for DDR */
+ ddr_clock_init();
+
+ /*
+ * DDR pad register bits are different for different SoCs
+ * Compensation values are also handled separately
+ */
+ plat_ddr_init();
+
+ /* Initialize mpmc register values */
+ mpmc_init_values();
+}
+
+static void pll_init(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+ /* Initialize PLLs */
+ writel(FREQ_332, &misc_p->pll1_frq);
+ writel(0x1C0A, &misc_p->pll1_cntl);
+ writel(0x1C0E, &misc_p->pll1_cntl);
+ writel(0x1C06, &misc_p->pll1_cntl);
+ writel(0x1C0E, &misc_p->pll1_cntl);
+
+ writel(FREQ_332, &misc_p->pll2_frq);
+ writel(0x1C0A, &misc_p->pll2_cntl);
+ writel(0x1C0E, &misc_p->pll2_cntl);
+ writel(0x1C06, &misc_p->pll2_cntl);
+ writel(0x1C0E, &misc_p->pll2_cntl);
+
+ /* wait for pll locks */
+ while (!(readl(&misc_p->pll1_cntl) & 0x1))
+ ;
+ while (!(readl(&misc_p->pll2_cntl) & 0x1))
+ ;
+}
+
+static void mac_init(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+ writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
+ &misc_p->periph1_clken);
+
+ writel(SYNTH23, &misc_p->gmac_synth_clk);
+
+ switch (get_socrev()) {
+ case SOC_SPEAR600_AA:
+ case SOC_SPEAR600_AB:
+ case SOC_SPEAR600_BA:
+ case SOC_SPEAR600_BB:
+ case SOC_SPEAR600_BC:
+ case SOC_SPEAR600_BD:
+ writel(0x0, &misc_p->gmac_ctr_reg);
+ break;
+
+ case SOC_SPEAR300:
+ case SOC_SPEAR310:
+ case SOC_SPEAR320:
+ writel(0x4, &misc_p->gmac_ctr_reg);
+ break;
+ }
+
+ writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
+ &misc_p->periph1_clken);
+
+ writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
+ &misc_p->periph1_rst);
+ writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
+ &misc_p->periph1_rst);
+}
+
+static void sys_init(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ struct syscntl_regs *syscntl_p =
+ (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
+
+ /* Set system state to SLOW */
+ writel(SLOW, &syscntl_p->scctrl);
+ writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
+
+ /* Initialize PLLs */
+ pll_init();
+
+ /*
+ * Ethernet configuration
+ * To be done only if the tftp boot is not selected already
+ * Boot code ensures the correct configuration in tftp booting
+ */
+ if (!tftp_boot_selected())
+ mac_init();
+
+ writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
+ writel(0x555, &misc_p->amba_clk_cfg);
+
+ writel(NORMAL, &syscntl_p->scctrl);
+
+ /* Wait for system to switch to normal mode */
+ while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
+ != NORMAL)
+ ;
+}
+
+/*
+ * get_socrev
+ *
+ * Get SoC Revision.
+ * @return SOC_SPEARXXX
+ */
+int get_socrev(void)
+{
+#if defined(CONFIG_SPEAR600)
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ u32 soc_id = readl(&misc_p->soc_core_id);
+ u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
+ u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
+
+ if ((pri_socid == 'B') && (sec_socid == 'B'))
+ return SOC_SPEAR600_BB;
+ else if ((pri_socid == 'B') && (sec_socid == 'C'))
+ return SOC_SPEAR600_BC;
+ else if ((pri_socid == 'B') && (sec_socid == 'D'))
+ return SOC_SPEAR600_BD;
+ else if (soc_id == 0)
+ return SOC_SPEAR600_BA;
+ else
+ return SOC_SPEAR_NA;
+#elif defined(CONFIG_SPEAR300)
+ return SOC_SPEAR300;
+#elif defined(CONFIG_SPEAR310)
+ return SOC_SPEAR310;
+#elif defined(CONFIG_SPEAR320)
+ return SOC_SPEAR320;
+#endif
+}
+
+void lowlevel_init(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ const char *u_boot_rev = U_BOOT_VERSION;
+
+ /* Initialize PLLs */
+ sys_init();
+
+ /* Initialize UART */
+ serial_init();
+
+ /* Print U-Boot SPL version string */
+ serial_puts("\nU-Boot SPL ");
+ /* Avoid a second "U-Boot" coming from this string */
+ u_boot_rev = &u_boot_rev[7];
+ serial_puts(u_boot_rev);
+ serial_puts(" (");
+ serial_puts(U_BOOT_DATE);
+ serial_puts(" - ");
+ serial_puts(U_BOOT_TIME);
+ serial_puts(")\n");
+
+#if defined(CONFIG_OS_BOOT)
+ writel(readl(&misc_p->periph1_clken) | PERIPH_UART1,
+ &misc_p->periph1_clken);
+#endif
+
+ /* Enable IPs (release reset) */
+ writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
+
+ /* Initialize MPMC */
+ serial_puts("Configure DDR\n");
+ mpmc_init();
+
+ /* SoC specific initialization */
+ soc_init();
+}
+
+void spear_late_init(void)
+{
+ struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+ writel(0x80000007, &misc_p->arb_icm_ml1);
+ writel(0x80000007, &misc_p->arb_icm_ml2);
+ writel(0x80000007, &misc_p->arb_icm_ml3);
+ writel(0x80000007, &misc_p->arb_icm_ml4);
+ writel(0x80000007, &misc_p->arb_icm_ml5);
+ writel(0x80000007, &misc_p->arb_icm_ml6);
+ writel(0x80000007, &misc_p->arb_icm_ml7);
+ writel(0x80000007, &misc_p->arb_icm_ml8);
+ writel(0x80000007, &misc_p->arb_icm_ml9);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <image.h>
+#include <linux/compiler.h>
+#include <asm/io.h>
+#include <asm/arch/spr_defs.h>
+#include <linux/mtd/st_smi.h>
+
+static const char kernel_name[] = "Linux";
+static const char loader_name[] = "U-Boot";
+
+int image_check_header(image_header_t *hdr, const char *name)
+{
+ if (image_check_magic(hdr) &&
+ (!strncmp(image_get_name(hdr), name, strlen(name))) &&
+ image_check_hcrc(hdr)) {
+ return 1;
+ }
+ return 0;
+}
+
+int image_check_data(image_header_t *hdr)
+{
+ if (image_check_dcrc(hdr))
+ return 1;
+
+ return 0;
+}
+
+/*
+ * SNOR (Serial NOR flash) related functions
+ */
+void snor_init(void)
+{
+ struct smi_regs *const smicntl =
+ (struct smi_regs * const)CONFIG_SYS_SMI_BASE;
+
+ /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
+ writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
+ &smicntl->smi_cr1);
+}
+
+static int snor_image_load(u8 *load_addr, void (**image_p)(void),
+ const char *image_name)
+{
+ image_header_t *header;
+
+ /*
+ * Since calculating the crc in the SNOR flash does not
+ * work, we copy the image to the destination address
+ * minus the header size. And point the header to this
+ * new destination. This will not work for address 0
+ * of course.
+ */
+ header = (image_header_t *)load_addr;
+ memcpy((ulong *)(image_get_load(header) - sizeof(image_header_t)),
+ (const ulong *)load_addr,
+ image_get_data_size(header) + sizeof(image_header_t));
+ header = (image_header_t *)(image_get_load(header) -
+ sizeof(image_header_t));
+
+ if (image_check_header(header, image_name)) {
+ if (image_check_data(header)) {
+ /* Jump to boot image */
+ *image_p = (void *)image_get_load(header);
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+static void boot_image(void (*image)(void))
+{
+ void (*funcp)(void) __noreturn = (void *)image;
+
+ (*funcp)();
+}
+
+/*
+ * spl_boot:
+ *
+ * All supported booting types of all supported SoCs are listed here.
+ * Generic readback APIs are provided for each supported booting type
+ * eg. nand_read_skip_bad
+ */
+u32 spl_boot(void)
+{
+ void (*image)(void);
+
+#ifdef CONFIG_SPEAR_USBTTY
+ plat_late_init();
+ return 1;
+#endif
+
+ /*
+ * All the supported booting devices are listed here. Each of
+ * the booting type supported by the platform would define the
+ * macro xxx_BOOT_SUPPORTED to TRUE.
+ */
+
+ if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) {
+ /* SNOR-SMI initialization */
+ snor_init();
+
+ serial_puts("Booting via SNOR\n");
+ /* Serial NOR booting */
+ if (1 == snor_image_load((u8 *)CONFIG_SYS_UBOOT_BASE,
+ &image, loader_name)) {
+ /* Platform related late initialasations */
+ plat_late_init();
+
+ /* Jump to boot image */
+ serial_puts("Jumping to U-Boot\n");
+ boot_image(image);
+ return 1;
+ }
+ }
+
+ if (NAND_BOOT_SUPPORTED && nand_boot_selected()) {
+ /* NAND booting */
+ /* Not ported from XLoader to SPL yet */
+ return 0;
+ }
+
+ if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) {
+ /* PNOR booting */
+ /* Not ported from XLoader to SPL yet */
+ return 0;
+ }
+
+ if (MMC_BOOT_SUPPORTED && mmc_boot_selected()) {
+ /* MMC booting */
+ /* Not ported from XLoader to SPL yet */
+ return 0;
+ }
+
+ if (SPI_BOOT_SUPPORTED && spi_boot_selected()) {
+ /* SPI booting */
+ /* Not supported for any platform as of now */
+ return 0;
+ }
+
+ if (I2C_BOOT_SUPPORTED && i2c_boot_selected()) {
+ /* I2C booting */
+ /* Not supported for any platform as of now */
+ return 0;
+ }
+
+ /*
+ * All booting types without memory are listed as below
+ * Control has to be returned to BootROM in case of all
+ * the following booting scenarios
+ */
+
+ if (USB_BOOT_SUPPORTED && usb_boot_selected()) {
+ plat_late_init();
+ return 1;
+ }
+
+ if (TFTP_BOOT_SUPPORTED && tftp_boot_selected()) {
+ plat_late_init();
+ return 1;
+ }
+
+ if (UART_BOOT_SUPPORTED && uart_boot_selected()) {
+ plat_late_init();
+ return 1;
+ }
+
+ /* Ideally, the control should not reach here. */
+ hang();
+}
--- /dev/null
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+ 0x00000001,
+ 0x00000000,
+ 0x01000000,
+ 0x00000101,
+ 0x00000001,
+ 0x01000000,
+ 0x00010001,
+ 0x00000100,
+ 0x00010001,
+ 0x00000003,
+ 0x01000201,
+ 0x06000202,
+ 0x06060106,
+ 0x03050502,
+ 0x03040404,
+ 0x02020503,
+ 0x02010106,
+ 0x03000404,
+ 0x02030202,
+ 0x03000204,
+ 0x0707073f,
+ 0x07070707,
+ 0x06060607,
+ 0x06060606,
+ 0x05050506,
+ 0x05050505,
+ 0x04040405,
+ 0x04040404,
+ 0x03030304,
+ 0x03030303,
+ 0x02020203,
+ 0x02020202,
+ 0x01010102,
+ 0x01010101,
+ 0x08080a01,
+ 0x0000023f,
+ 0x00040800,
+ 0x00000000,
+ 0x00000f02,
+ 0x00001b1b,
+ 0x7f000000,
+ 0x005f0000,
+ 0x1c040b6a,
+ 0x00640064,
+ 0x00640064,
+ 0x00640064,
+ 0x00000064,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x000007ff,
+ 0x00000000,
+ 0x47ec00c8,
+ 0x00c8001f,
+ 0x00000000,
+ 0x0000cd98,
+ 0x00000000,
+ 0x03030100,
+ 0x03030303,
+ 0x03030303,
+ 0x03030303,
+ 0x00270000,
+ 0x00250027,
+ 0x00300000,
+ 0x008900b7,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+};
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+#if (CONFIG_DDR_PLL2)
+ 0x00000001,
+ 0x00000000,
+#elif (CONFIG_DDR_2HCLK)
+ 0x02020201,
+ 0x02020202,
+#endif
+ 0x01000000,
+ 0x00000101,
+ 0x00000101,
+ 0x01000000,
+ 0x00010001,
+ 0x00000100,
+ 0x01010001,
+ 0x00000201,
+ 0x01000101,
+ 0x06000002,
+ 0x06060106,
+ 0x03050502,
+ 0x03040404,
+ 0x02020503,
+ 0x02010106,
+ 0x03000405,
+ 0x03040202,
+ 0x04000305,
+ 0x0707073f,
+ 0x07070707,
+ 0x06060607,
+ 0x06060606,
+ 0x05050506,
+ 0x05050505,
+ 0x04040405,
+ 0x04040404,
+ 0x03030304,
+ 0x03030303,
+ 0x02020203,
+ 0x02020202,
+ 0x01010102,
+ 0x01010101,
+ 0x0a0a0a01,
+ 0x0000023f,
+ 0x00050a00,
+ 0x11000000,
+ 0x00001302,
+ 0x00000A0A,
+ 0x72000000,
+ 0x00550000,
+ 0x2b050e86,
+ 0x00640064,
+ 0x00640064,
+ 0x00640064,
+ 0x00000064,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00000a24,
+ 0x43C20000,
+ 0x5b1c00c8,
+ 0x00c8002e,
+ 0x00000000,
+ 0x0001046b,
+ 0x00000000,
+ 0x03030100,
+ 0x03030303,
+ 0x03030303,
+ 0x03030303,
+ 0x00210000,
+ 0x00010021,
+ 0x00200000,
+ 0x006c0090,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+};
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+ 0x03030301,
+ 0x03030303,
+ 0x01000000,
+ 0x00000101,
+ 0x00000001,
+ 0x01000000,
+ 0x00010001,
+ 0x00000100,
+ 0x00010001,
+ 0x00000003,
+ 0x01000201,
+ 0x06000202,
+ 0x06060106,
+ 0x03050502,
+ 0x03040404,
+ 0x02020503,
+ 0x02010106,
+ 0x03000404,
+ 0x02020202,
+ 0x03000203,
+ 0x0707073f,
+ 0x07070707,
+ 0x06060607,
+ 0x06060606,
+ 0x05050506,
+ 0x05050505,
+ 0x04040405,
+ 0x04040404,
+ 0x03030304,
+ 0x03030303,
+ 0x02020203,
+ 0x02020202,
+ 0x01010102,
+ 0x01010101,
+ 0x08080a01,
+ 0x0000023f,
+ 0x00030600,
+ 0x00000000,
+ 0x00000a02,
+ 0x00001c1c,
+ 0x7f000000,
+ 0x005f0000,
+ 0x12030743,
+ 0x00640064,
+ 0x00640064,
+ 0x00640064,
+ 0x00000064,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x0000050e,
+ 0x00000000,
+ 0x2d8900c8,
+ 0x00c80014,
+ 0x00000000,
+ 0x00008236,
+ 0x00000000,
+ 0x03030100,
+ 0x03030303,
+ 0x03030303,
+ 0x03030303,
+ 0x00400000,
+ 0x003a0040,
+ 0x00680000,
+ 0x00d80120,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+};
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+#if (CONFIG_DDR_PLL2)
+ 0x00000001,
+ 0x00000000,
+#elif (CONFIG_DDR_2HCLK)
+ 0x02020201,
+ 0x02020202,
+#endif
+ 0x01000000,
+ 0x00000101,
+ 0x00000101,
+ 0x01000000,
+ 0x00010001,
+ 0x00000100,
+ 0x01010001,
+ 0x00000201,
+ 0x01000101,
+ 0x06000002,
+ 0x06060106,
+ 0x03050502,
+ 0x03040404,
+ 0x02020503,
+#ifdef CONFIG_X600
+ 0x02030206,
+#else
+ 0x02010106,
+#endif
+ 0x03000405,
+ 0x03040202,
+ 0x04000305,
+ 0x0707073f,
+ 0x07070707,
+ 0x06060607,
+ 0x06060606,
+ 0x05050506,
+ 0x05050505,
+ 0x04040405,
+ 0x04040404,
+ 0x03030304,
+ 0x03030303,
+ 0x02020203,
+ 0x02020202,
+ 0x01010102,
+ 0x01010101,
+ 0x0a0a0a01,
+ 0x0000023f,
+ 0x00050a00,
+ 0x11000000,
+ 0x00001302,
+ 0x00000A0A,
+#ifdef CONFIG_X600
+ 0x7f000000,
+ 0x005c0000,
+#else
+ 0x72000000,
+ 0x00550000,
+#endif
+ 0x2b050e86,
+ 0x00640064,
+ 0x00640064,
+ 0x00640064,
+ 0x00000064,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00200020,
+ 0x00000a24,
+ 0x43C20000,
+ 0x5b1c00c8,
+ 0x00c8002e,
+ 0x00000000,
+ 0x0001046b,
+ 0x00000000,
+ 0x03030100,
+ 0x03030303,
+ 0x03030303,
+ 0x03030303,
+ 0x00210000,
+ 0x00010021,
+ 0x00200000,
+ 0x006c0090,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x003fffff,
+ 0x003fffff,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+};
+#endif
--- /dev/null
+/*
+ * armboot - Startup Code for ARM926EJS CPU-core
+ *
+ * Copyright (c) 2003 Texas Instruments
+ *
+ * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
+ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+
+.globl _start
+_start:
+ b reset
+ ldr pc, _undefined_instruction
+ ldr pc, _software_interrupt
+ ldr pc, _prefetch_abort
+ ldr pc, _data_abort
+ ldr pc, _not_used
+ ldr pc, _irq
+ ldr pc, _fiq
+
+_undefined_instruction:
+_software_interrupt:
+_prefetch_abort:
+_data_abort:
+_not_used:
+_irq:
+_fiq:
+ .word infinite_loop
+
+infinite_loop:
+ b infinite_loop
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * Below are the critical initializations already taken place in BootROM.
+ * So, these are not taken care in Xloader
+ * 1. Relocation to RAM
+ * 2. Initializing stacks
+ *
+ *************************************************************************
+ */
+
+/*
+ * the actual reset code
+ */
+
+reset:
+/*
+ * Xloader has to return back to BootROM in a few cases.
+ * eg. Ethernet boot, UART boot, USB boot
+ * Saving registers for returning back
+ */
+ stmdb sp!, {r0-r12,r14}
+ bl cpu_init_crit
+/*
+ * Clearing bss area is not done in Xloader.
+ * BSS area lies in the DDR location which is not yet initialized
+ * bss is assumed to be uninitialized.
+ */
+ bl spl_boot
+ ldmia sp!, {r0-r12,pc}
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+cpu_init_crit:
+ /*
+ * flush v4 I/D caches
+ */
+ mov r0, #0
+ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
+ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
+
+ /*
+ * enable instruction cache
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
+ mcr p15, 0, r0, c1, c0, 0
+
+ /*
+ * Go setup Memory and board specific bits prior to relocation.
+ */
+ stmdb sp!, {lr}
+ bl lowlevel_init /* go setup pll,mux,memory */
+ ldmia sp!, {pc}
--- /dev/null
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ arch/arm/cpu/arm926ejs/spear/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data)
+ }
+
+ . = ALIGN(4);
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ .bss : {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ }
+
+ _end = .;
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynsym*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.hash*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
#define UART_SMART_IDLE_EN (0x1 << 0x3)
#endif
+#ifdef CONFIG_SPL_BUILD
+/* Initialize timer */
+static void init_timer(void)
+{
+ /* Reset the Timer */
+ writel(0x2, (&timer_base->tscir));
+
+ /* Wait until the reset is done */
+ while (readl(&timer_base->tiocp_cfg) & 1)
+ ;
+
+ /* Start the Timer */
+ writel(0x1, (&timer_base->tclr));
+}
+#endif
+
/*
* early system init of muxing and clocks.
*/
enable_mmc0_pin_mux();
}
-/* Initialize timer */
-void init_timer(void)
-{
- /* Reset the Timer */
- writel(0x2, (&timer_base->tscir));
-
- /* Wait until the reset is done */
- while (readl(&timer_base->tiocp_cfg) & 1)
- ;
-
- /* Start the Timer */
- writel(0x1, (&timer_base->tclr));
-}
-
#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
#include <asm/system.h>
#include <asm/cache.h>
#include <asm/armv7.h>
+#include <linux/compiler.h>
-void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3)
+void __naked save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3)
{
+ /*
+ * Stack pointer is not yet initialized
+ * Don't save anything to stack even if compiled with -O0
+ */
+ asm("bx lr");
}
void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
LIB = $(obj)lib$(SOC).o
-COBJS += clock.o power.o soc.o system.o
+COBJS += clock.o power.o soc.o system.o pinmux.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
--- /dev/null
+/*
+ * Copyright (c) 2012 Samsung Electronics.
+ * Abhilash Kesavan <a.kesavan@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/sromc.h>
+
+static void exynos5_uart_config(int peripheral)
+{
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+ struct s5p_gpio_bank *bank;
+ int i, start, count;
+
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ bank = &gpio1->a0;
+ start = 0;
+ count = 4;
+ break;
+ case PERIPH_ID_UART1:
+ bank = &gpio1->a0;
+ start = 4;
+ count = 4;
+ break;
+ case PERIPH_ID_UART2:
+ bank = &gpio1->a1;
+ start = 0;
+ count = 4;
+ break;
+ case PERIPH_ID_UART3:
+ bank = &gpio1->a1;
+ start = 4;
+ count = 2;
+ break;
+ }
+ for (i = start; i < start + count; i++) {
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ }
+}
+
+static int exynos5_mmc_config(int peripheral, int flags)
+{
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+ struct s5p_gpio_bank *bank, *bank_ext;
+ int i;
+
+ switch (peripheral) {
+ case PERIPH_ID_SDMMC0:
+ bank = &gpio1->c0;
+ bank_ext = &gpio1->c1;
+ break;
+ case PERIPH_ID_SDMMC1:
+ bank = &gpio1->c1;
+ bank_ext = NULL;
+ break;
+ case PERIPH_ID_SDMMC2:
+ bank = &gpio1->c2;
+ bank_ext = &gpio1->c3;
+ break;
+ case PERIPH_ID_SDMMC3:
+ bank = &gpio1->c3;
+ bank_ext = NULL;
+ break;
+ }
+ if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+ debug("SDMMC device %d does not support 8bit mode",
+ peripheral);
+ return -1;
+ }
+ if (flags & PINMUX_FLAG_8BIT_MODE) {
+ for (i = 3; i <= 6; i++) {
+ s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
+ s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
+ s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+ }
+ }
+ for (i = 0; i < 2; i++) {
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+ s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ }
+ for (i = 3; i <= 6; i++) {
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
+ s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ }
+ return 0;
+}
+
+static void exynos5_sromc_config(int flags)
+{
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+ int i;
+
+ /*
+ * SROM:CS1 and EBI
+ *
+ * GPY0[0] SROM_CSn[0]
+ * GPY0[1] SROM_CSn[1](2)
+ * GPY0[2] SROM_CSn[2]
+ * GPY0[3] SROM_CSn[3]
+ * GPY0[4] EBI_OEn(2)
+ * GPY0[5] EBI_EEn(2)
+ *
+ * GPY1[0] EBI_BEn[0](2)
+ * GPY1[1] EBI_BEn[1](2)
+ * GPY1[2] SROM_WAIT(2)
+ * GPY1[3] EBI_DATA_RDn(2)
+ */
+ s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
+ GPIO_FUNC(2));
+ s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
+ s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
+
+ for (i = 0; i < 4; i++)
+ s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
+
+ /*
+ * EBI: 8 Addrss Lines
+ *
+ * GPY3[0] EBI_ADDR[0](2)
+ * GPY3[1] EBI_ADDR[1](2)
+ * GPY3[2] EBI_ADDR[2](2)
+ * GPY3[3] EBI_ADDR[3](2)
+ * GPY3[4] EBI_ADDR[4](2)
+ * GPY3[5] EBI_ADDR[5](2)
+ * GPY3[6] EBI_ADDR[6](2)
+ * GPY3[7] EBI_ADDR[7](2)
+ *
+ * EBI: 16 Data Lines
+ *
+ * GPY5[0] EBI_DATA[0](2)
+ * GPY5[1] EBI_DATA[1](2)
+ * GPY5[2] EBI_DATA[2](2)
+ * GPY5[3] EBI_DATA[3](2)
+ * GPY5[4] EBI_DATA[4](2)
+ * GPY5[5] EBI_DATA[5](2)
+ * GPY5[6] EBI_DATA[6](2)
+ * GPY5[7] EBI_DATA[7](2)
+ *
+ * GPY6[0] EBI_DATA[8](2)
+ * GPY6[1] EBI_DATA[9](2)
+ * GPY6[2] EBI_DATA[10](2)
+ * GPY6[3] EBI_DATA[11](2)
+ * GPY6[4] EBI_DATA[12](2)
+ * GPY6[5] EBI_DATA[13](2)
+ * GPY6[6] EBI_DATA[14](2)
+ * GPY6[7] EBI_DATA[15](2)
+ */
+ for (i = 0; i < 8; i++) {
+ s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
+ s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
+
+ s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
+ s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
+
+ s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
+ s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
+ }
+}
+
+static int exynos5_pinmux_config(int peripheral, int flags)
+{
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ exynos5_uart_config(peripheral);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC3:
+ return exynos5_mmc_config(peripheral, flags);
+ case PERIPH_ID_SROMC:
+ exynos5_sromc_config(flags);
+ break;
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ }
+
+ return 0;
+}
+
+int exynos_pinmux_config(int peripheral, int flags)
+{
+ if (cpu_is_exynos5())
+ return exynos5_pinmux_config(peripheral, flags);
+ else {
+ debug("pinmux functionality not supported\n");
+ return -1;
+ }
+}
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_USDHC
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#else
gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
+#endif
#endif
return 0;
}
set_usb_phy1_clk();
- writel((readl(tmp_base) & (~0x7)) | 0x4, tmp_base);
+ writel((readl(tmp_base) & (~0x6)) | 0x4, tmp_base);
}
#endif
return system_rev;
}
-#ifdef CONFIG_ARCH_CPU_INIT
void init_aips(void)
{
struct aipstz_regs *aips1, *aips2;
return 0;
}
-#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
* Core DPLL will be locked after setting up EMIF
* using the FREQ_UPDATE method(freq_update_core())
*/
- do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK,
- "core");
+ if (omap_revision() != OMAP5432_ES1_0)
+ do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
+ DPLL_NO_LOCK, "core");
+ else
+ do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
+ DPLL_LOCK, "core");
/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
(CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/utils.h>
+#include <linux/compiler.h>
+
+void set_lpmode_selfrefresh(u32 base)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ u32 reg;
+
+ reg = readl(&emif->emif_pwr_mgmt_ctrl);
+ reg &= ~EMIF_REG_LP_MODE_MASK;
+ reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
+ reg &= ~EMIF_REG_SR_TIM_MASK;
+ writel(reg, &emif->emif_pwr_mgmt_ctrl);
+
+ /* dummy read for the new SR_TIM to be loaded */
+ readl(&emif->emif_pwr_mgmt_ctrl);
+}
+
+void force_emif_self_refresh()
+{
+ set_lpmode_selfrefresh(EMIF1_BASE);
+ set_lpmode_selfrefresh(EMIF2_BASE);
+}
inline u32 emif_num(u32 base)
{
mr = readl(&emif->emif_lpddr2_mode_reg_data);
debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
cs, mr_addr, mr);
- return mr;
+ if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
+ ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
+ ((mr & 0xff000000) >> 24) == (mr & 0xff))
+ return mr & 0xff;
+ else
+ return mr;
}
static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
static void lpddr2_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 *ext_phy_ctrl_base = 0;
- u32 *emif_ext_phy_ctrl_base = 0;
- u32 i = 0;
/* Not NVM */
clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
- ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
- emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
-
- if (omap_revision() >= OMAP5430_ES1_0) {
- /* Configure external phy control timing registers */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
- writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
- }
-
- /*
- * external phy 6-24 registers do not change with
- * ddr frequency
- */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
- writel(ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
- }
- }
+ do_ext_phy_settings(base, regs);
do_lpddr2_init(base, CS0);
if (regs->sdram_config & EMIF_REG_EBANK_MASK)
/* Enable refresh now */
clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
+ }
+
+__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
}
void emif_update_timings(u32 base, const struct emif_regs *regs)
writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
- if (omap_revision() == OMAP5430_ES1_0) {
+ if (omap_revision() >= OMAP5430_ES1_0) {
writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
&emif->emif_l3_config);
} else if (omap_revision() >= OMAP4460_ES1_0) {
}
}
+static void ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ /* keep sdram in self-refresh */
+ writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
+ & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
+ __udelay(130);
+
+ /*
+ * Set invert_clkout (if activated)--DDR_PHYCTRL_1
+ * Invert clock adds an additional half cycle delay on the command
+ * interface. The additional half cycle, is usually meant to enable
+ * leveling in the situation that DQS is later than CK on the board.It
+ * also helps provide some additional margin for leveling.
+ */
+ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+ writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+ __udelay(130);
+
+ writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
+ & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
+
+ /* Launch Full leveling */
+ writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
+
+ /* Wait till full leveling is complete */
+ readl(&emif->emif_rd_wr_lvl_ctl);
+ __udelay(130);
+
+ /* Read data eye leveling no of samples */
+ config_data_eye_leveling_samples(base);
+
+ /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
+ writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
+ __udelay(130);
+
+ /* Launch Incremental leveling */
+ writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
+ __udelay(130);
+}
+
+static void ddr3_init(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ u32 *ext_phy_ctrl_base = 0;
+ u32 *emif_ext_phy_ctrl_base = 0;
+ u32 i = 0;
+
+ /*
+ * Set SDRAM_CONFIG and PHY control registers to locked frequency
+ * and RL =7. As the default values of the Mode Registers are not
+ * defined, contents of mode Registers must be fully initialized.
+ * H/W takes care of this initialization
+ */
+ writel(regs->sdram_config_init, &emif->emif_sdram_config);
+
+ writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+
+ /* Update timing registers */
+ writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
+ writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
+ writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
+
+ writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
+ writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
+
+ ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
+ emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
+
+ /* Configure external phy control timing registers */
+ for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+ writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+ /* Update shadow registers */
+ writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+ }
+
+ /*
+ * external phy 6-24 registers do not change with
+ * ddr frequency
+ */
+ for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
+ writel(ddr3_ext_phy_ctrl_const_base[i],
+ emif_ext_phy_ctrl_base++);
+ /* Update shadow registers */
+ writel(ddr3_ext_phy_ctrl_const_base[i],
+ emif_ext_phy_ctrl_base++);
+ }
+
+ /* enable leveling */
+ writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
+
+ ddr3_leveling(base, regs);
+}
+
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
}
mr = get_mr(base, cs, LPDDR2_MR5);
- if (mr >= 0xFF) {
+ if (mr > 0xFF) {
/* Mode register value bigger than 8 bit */
return 0;
}
return NULL;
/* Do the minimum init for mode register accesses */
- if (!running_from_sdram()) {
+ if (!(running_from_sdram() || warm_reset())) {
phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
writel(phy, &emif->emif_ddr_phy_ctrl_1);
}
* Changing the timing registers in EMIF can happen(going from one
* OPP to another)
*/
- if (!in_sdram)
- lpddr2_init(base, regs);
+ if (!(in_sdram || warm_reset())) {
+ if (omap_revision() != OMAP5432_ES1_0)
+ lpddr2_init(base, regs);
+ else
+ ddr3_init(base, regs);
+ }
/* Write to the shadow registers */
emif_update_timings(base, regs);
void sdram_init(void)
{
u32 in_sdram, size_prog, size_detect;
+ u32 omap_rev = omap_revision();
debug(">>sdram_init()\n");
in_sdram = running_from_sdram();
debug("in_sdram = %d\n", in_sdram);
- if (!in_sdram)
- bypass_dpll(&prcm->cm_clkmode_dpll_core);
-
+ if (!(in_sdram || warm_reset())) {
+ if (omap_rev != OMAP5432_ES1_0)
+ bypass_dpll(&prcm->cm_clkmode_dpll_core);
+ else
+ writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
+ }
do_sdram_init(EMIF1_BASE);
do_sdram_init(EMIF2_BASE);
- if (!in_sdram) {
+ if (!in_sdram)
dmm_init(DMM_BASE);
+
+ if (!(in_sdram || warm_reset())) {
emif_post_init_config(EMIF1_BASE);
emif_post_init_config(EMIF2_BASE);
}
/* for the shadow registers to take effect */
- freq_update_core();
+ if (omap_rev != OMAP5432_ES1_0)
+ freq_update_core();
/* Do some testing after the init */
if (!in_sdram) {
size_prog = omap_sdram_size();
+ size_prog = log_2_n_round_down(size_prog);
+ size_prog = (1 << size_prog);
+
size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
size_prog);
/* Compare with the size programmed */
void s_init(void)
{
init_omap_revision();
+#ifdef CONFIG_SPL_BUILD
+ if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
+ force_emif_self_refresh();
+#endif
watchdog_init();
set_mux_conf_regs();
#ifdef CONFIG_SPL_BUILD
*/
u32 omap_sdram_size(void)
{
- u32 section, i, total_size = 0, size, addr;
+ u32 section, i, valid;
+ u64 sdram_start = 0, sdram_end = 0, addr,
+ size, total_size = 0, trap_size = 0;
for (i = 0; i < 4; i++) {
section = __raw_readl(DMM_BASE + i*4);
+ valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
+ (EMIF_SDRC_ADDRSPC_SHIFT);
addr = section & EMIF_SYS_ADDR_MASK;
+
/* See if the address is valid */
if ((addr >= DRAM_ADDR_SPACE_START) &&
(addr < DRAM_ADDR_SPACE_END)) {
EMIF_SYS_SIZE_SHIFT);
size = 1 << size;
size *= SZ_16M;
- total_size += size;
+
+ if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
+ if (!sdram_start || (addr < sdram_start))
+ sdram_start = addr;
+ if (!sdram_end || ((addr + size) > sdram_end))
+ sdram_end = addr + size;
+ } else {
+ trap_size = size;
+ }
+
}
+
}
+ total_size = (sdram_end - sdram_start) - (trap_size);
return total_size;
}
{
writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
}
+
+u32 __weak warm_reset(void)
+{
+ return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK);
+}
{727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
{931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
{931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
- {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
+ {291, 11, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
};
/* ABE M & N values with sys_clk as source */
};
u32 *const clk_modules_hw_auto_essential[] = {
+ &prcm->cm_l3_2_gpmc_clkctrl,
&prcm->cm_memif_emif_1_clkctrl,
&prcm->cm_memif_emif_2_clkctrl,
&prcm->cm_l4cfg_l4_cfg_clkctrl,
&prcm->cm_l4per_gpio4_clkctrl,
&prcm->cm_l4per_gpio5_clkctrl,
&prcm->cm_l4per_gpio6_clkctrl,
- &prcm->cm_l3init_usbphy_clkctrl,
- &prcm->cm_clksel_usb_60mhz,
- &prcm->cm_l3init_hsusbtll_clkctrl,
0
};
&prcm->cm_l4per_gptimer2_clkctrl,
&prcm->cm_wkup_wdtimer2_clkctrl,
&prcm->cm_l4per_uart3_clkctrl,
- &prcm->cm_l3init_hsusbhost_clkctrl,
0
};
u32 *const clk_modules_hw_auto_essential[] = {
&prcm->cm_l3init_hsusbotg_clkctrl,
&prcm->cm_l3init_usbphy_clkctrl,
+ &prcm->cm_l3init_usbphy_clkctrl,
+ &prcm->cm_clksel_usb_60mhz,
+ &prcm->cm_l3init_hsusbtll_clkctrl,
0
};
&prcm->cm_l4per_i2c2_clkctrl,
&prcm->cm_l4per_i2c3_clkctrl,
&prcm->cm_l4per_i2c4_clkctrl,
+ &prcm->cm_l3init_hsusbhost_clkctrl,
0
};
};
u32 *const clk_modules_hw_auto_non_essential[] = {
- &prcm->cm_l3_2_gpmc_clkctrl,
&prcm->cm_l3instr_l3_3_clkctrl,
&prcm->cm_l3instr_l3_instr_clkctrl,
&prcm->cm_l3instr_intrconn_wp1_clkctrl,
&prcm->cm_l3init_hsi_clkctrl,
- &prcm->cm_l3init_hsusbtll_clkctrl,
0
};
&prcm->cm_cam_fdif_clkctrl,
&prcm->cm_dss_dss_clkctrl,
&prcm->cm_sgx_sgx_clkctrl,
- &prcm->cm_l3init_hsusbhost_clkctrl,
0
};
}
#endif
+/* dummy fuction for omap4 */
+void config_data_eye_leveling_samples(u32 emif_base)
+{
+}
+
void init_omap_revision(void)
{
/*
};
/* Dummy registers for OMAP44xx */
-const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
+const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,
*/
void scale_vcores(void)
{
- u32 volt;
+ u32 volt_core, volt_mpu, volt_mm;
omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
/* Palmas settings */
- volt = VDD_CORE;
- do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt);
-
- volt = VDD_MPU;
- do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt);
-
- volt = VDD_MM;
- do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt);
-
+ if (omap_revision() != OMAP5432_ES1_0) {
+ volt_core = VDD_CORE;
+ volt_mpu = VDD_MPU;
+ volt_mm = VDD_MM;
+ } else {
+ volt_core = VDD_CORE_5432;
+ volt_mpu = VDD_MPU_5432;
+ volt_mm = VDD_MM_5432;
+ }
+
+ do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core);
+ do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu);
+ do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm);
+
+ if (omap_revision() == OMAP5432_ES1_0) {
+ /* Configure LDO SRAM "magic" bits */
+ writel(2, &prcm->prm_sldo_core_setup);
+ writel(2, &prcm->prm_sldo_mpu_setup);
+ writel(2, &prcm->prm_sldo_mm_setup);
+ }
}
u32 get_offset_code(u32 volt_offset)
};
u32 *const clk_modules_hw_auto_essential[] = {
+ &prcm->cm_l3_2_gpmc_clkctrl,
&prcm->cm_memif_emif_1_clkctrl,
&prcm->cm_memif_emif_2_clkctrl,
&prcm->cm_l4cfg_l4_cfg_clkctrl,
&prcm->cm_l4per_i2c2_clkctrl,
&prcm->cm_l4per_i2c3_clkctrl,
&prcm->cm_l4per_i2c4_clkctrl,
+ &prcm->cm_l3init_hsusbtll_clkctrl,
+ &prcm->cm_l3init_hsusbhost_clkctrl,
+ &prcm->cm_l3init_fsusb_clkctrl,
0
};
&prcm->cm_ivahd_ivahd_clkctrl,
&prcm->cm_ivahd_sl2_clkctrl,
&prcm->cm_dsp_dsp_clkctrl,
- &prcm->cm_l3_2_gpmc_clkctrl,
&prcm->cm_l3instr_l3_3_clkctrl,
&prcm->cm_l3instr_l3_instr_clkctrl,
&prcm->cm_l3instr_intrconn_wp1_clkctrl,
&prcm->cm_l3init_hsi_clkctrl,
- &prcm->cm_l3init_hsusbtll_clkctrl,
&prcm->cm_l4per_hdq1w_clkctrl,
0
};
&prcm->cm_cam_fdif_clkctrl,
&prcm->cm_dss_dss_clkctrl,
&prcm->cm_sgx_sgx_clkctrl,
- &prcm->cm_l3init_hsusbhost_clkctrl,
- &prcm->cm_l3init_fsusb_clkctrl,
0
};
#include <asm/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
+#include <asm/emif.h>
DECLARE_GLOBAL_DATA_PTR;
const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
#ifdef CONFIG_SPL_BUILD
+/* LPDDR2 specific IO settings */
+static void io_settings_lpddr2(void)
+{
+ struct omap_sys_ctrl_regs *ioregs_base =
+ (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ &(ioregs_base->control_ddrch1_0));
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ &(ioregs_base->control_ddrch1_1));
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ &(ioregs_base->control_ddrch2_0));
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ &(ioregs_base->control_ddrch2_1));
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+ &(ioregs_base->control_lpddr2ch1_0));
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+ &(ioregs_base->control_lpddr2ch1_1));
+ writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
+ &(ioregs_base->control_ddrio_0));
+ writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
+ &(ioregs_base->control_ddrio_1));
+ writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
+ &(ioregs_base->control_ddrio_2));
+}
+
+/* DDR3 specific IO settings */
+static void io_settings_ddr3(void)
+{
+ u32 io_settings = 0;
+ struct omap_sys_ctrl_regs *ioregs_base =
+ (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+ writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddr3ch1_0));
+ writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddrch1_0));
+ writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddrch1_1));
+
+ writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddr3ch2_0));
+ writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddrch2_0));
+ writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddrch2_1));
+
+ writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE,
+ &(ioregs_base->control_ddrio_0));
+ writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE,
+ &(ioregs_base->control_ddrio_1));
+ writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE,
+ &(ioregs_base->control_ddrio_2));
+
+ /* omap5432 does not use lpddr2 */
+ writel(0x0, &(ioregs_base->control_lpddr2ch1_0));
+ writel(0x0, &(ioregs_base->control_lpddr2ch1_1));
+
+ writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+ &(ioregs_base->control_emif1_sdram_config_ext));
+ writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+ &(ioregs_base->control_emif2_sdram_config_ext));
+
+ /* Disable DLL select */
+ io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config))
+ & 0xFFEFFFFF);
+ writel(io_settings,
+ &(ioregs_base->control_port_emif1_sdram_config));
+
+ io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config))
+ & 0xFFEFFFFF);
+ writel(io_settings,
+ &(ioregs_base->control_port_emif2_sdram_config));
+}
+
/*
* Some tuning of IOs for optimal power and performance
*/
(sc_fast << 17) | (sc_fast << 14);
writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
- /* LPDDR2 io settings */
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch1_0));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch1_1));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch2_0));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch2_1));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
- &(ioregs_base->control_lpddr2ch1_0));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
- &(ioregs_base->control_lpddr2ch1_1));
- writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
- &(ioregs_base->control_ddrio_0));
- writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
- &(ioregs_base->control_ddrio_1));
- writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
- &(ioregs_base->control_ddrio_2));
+ if (omap_revision() <= OMAP5430_ES1_0)
+ io_settings_lpddr2();
+ else
+ io_settings_ddr3();
/* Efuse settings */
writel(EFUSE_1, &(ioregs_base->control_efuse_1));
}
#endif
+void config_data_eye_leveling_samples(u32 emif_base)
+{
+ struct omap_sys_ctrl_regs *ioregs_base =
+ (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+ /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
+ if (emif_base == EMIF1_BASE)
+ writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
+ &(ioregs_base->control_emif1_sdram_config_ext));
+ else if (emif_base == EMIF2_BASE)
+ writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
+ &(ioregs_base->control_emif2_sdram_config_ext));
+}
+
void init_omap_revision(void)
{
/*
switch (rev) {
case MIDR_CORTEX_A15_R0P0:
- *omap_si_rev = OMAP5430_ES1_0;
+ switch (readl(CONTROL_ID_CODE)) {
+ case OMAP5430_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = OMAP5430_ES1_0;
+ break;
+ case OMAP5432_CONTROL_ID_CODE_ES1_0:
+ default:
+ *omap_si_rev = OMAP5432_ES1_0;
+ break;
+ }
break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
.emif_ddr_ext_phy_ctrl_5 = 0x04010040
};
+const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
+ .sdram_config_init = 0x61851B32,
+ .sdram_config = 0x61851B32,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xCCCF36B3,
+ .sdram_tim2 = 0x308F7FDA,
+ .sdram_tim3 = 0x027F88A8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x0007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0020420A,
+ .emif_ddr_phy_ctlr_1 = 0x0024420A,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_5 = 0x04010040,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.dmm_lisa_map_0 = 0x0,
- .dmm_lisa_map_1 = 0,
- .dmm_lisa_map_2 = 0,
- .dmm_lisa_map_3 = 0x80740300
+ .dmm_lisa_map_1 = 0x0,
+ .dmm_lisa_map_2 = 0x80740300,
+ .dmm_lisa_map_3 = 0xFF020100
};
const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x00000077
};
+const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+ 0x01004010,
+ 0x00001004,
+ 0x04010040,
+ 0x01004010,
+ 0x00001004,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x80080080,
+ 0x00800800,
+ 0x08102040,
+ 0x00000002,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000057
+};
+
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
{
- *regs = &emif_regs_532_mhz_2cs;
+ if (omap_revision() == OMAP5432_ES1_0)
+ *regs = &emif_regs_ddr3_532_mhz_1cs;
+ else
+ *regs = &emif_regs_532_mhz_2cs;
}
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
__attribute__((weak, alias("emif_get_reg_dump_sdp")));
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
+ u32 *ext_phy_ctrl_base = 0;
+ u32 *emif_ext_phy_ctrl_base = 0;
+ u32 i = 0;
+
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
+ emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
+
+ /* Configure external phy control timing registers */
+ for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+ writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+ /* Update shadow registers */
+ writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+ }
+
+ /*
+ * external phy 6-24 registers do not change with
+ * ddr frequency
+ */
+ for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
+ writel(ext_phy_ctrl_const_base[i],
+ emif_ext_phy_ctrl_base++);
+ /* Update shadow registers */
+ writel(ext_phy_ctrl_const_base[i],
+ emif_ext_phy_ctrl_base++);
+ }
+}
+
#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
.max_freq = 532000000,
{
char buf[32];
- printf("CPU:\tS5P%X@%sMHz\n",
- s5p_cpu_id, strmhz(buf, get_arm_clk()));
+ printf("CPU:\t%s%X@%sMHz\n",
+ s5p_get_cpu_name(), s5p_cpu_id,
+ strmhz(buf, get_arm_clk()));
return 0;
}
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
#endif
+/*
+ * Move vector table
+ */
+#if !defined(CONFIG_TEGRA2)
+#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
+ /* Set vector address in CP15 VBAR register */
+ ldr r0, =_start
+ add r0, r0, r9
+ mcr p15, 0, r0, c12, c0, 0 @Set VBAR
+#endif
+#endif /* !Tegra2 */
+
ldr r0, _board_init_r_ofs
adr r1, _start
add lr, r0, r1
void init_pllx(void)
{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ struct clk_pll_simple *pll =
+ &clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE];
u32 reg;
/* If PLLX is already enabled, just return */
writel(reg, &scu->scu_ctrl);
}
+static u32 get_odmdata(void)
+{
+ /*
+ * ODMDATA is stored in the BCT in IRAM by the BootROM.
+ * The BCT start and size are stored in the BIT in IRAM.
+ * Read the data @ bct_start + (bct_size - 12). This works
+ * on T20 and T30 BCTs, which are locked down. If this changes
+ * in new chips (T114, etc.), we can revisit this algorithm.
+ */
+
+ u32 bct_start, odmdata;
+
+ bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
+ odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
+
+ return odmdata;
+}
+
void init_pmc_scratch(void)
{
struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+ u32 odmdata;
int i;
/* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
writel(0, &pmc->pmc_scratch1+i);
/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
- writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
+ odmdata = get_odmdata();
+ writel(odmdata, &pmc->pmc_scratch20);
#ifdef CONFIG_TEGRA2_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */
}
#endif
+static int uart_configs[] = {
+#if defined(CONFIG_TEGRA2_UARTA_UAA_UAB)
+ FUNCMUX_UART1_UAA_UAB,
+#elif defined(CONFIG_TEGRA2_UARTA_GPU)
+ FUNCMUX_UART1_GPU,
+#elif defined(CONFIG_TEGRA2_UARTA_SDIO1)
+ FUNCMUX_UART1_SDIO1,
+#else
+ FUNCMUX_UART1_IRRX_IRTX,
+#endif
+ FUNCMUX_UART2_IRDA,
+ -1,
+ FUNCMUX_UART4_GMC,
+ -1,
+};
+
/**
* Set up the specified uarts
*
if (uart_ids & (1 << i)) {
enum periph_id id = id_for_uart[i];
- funcmux_select(id, FUNCMUX_DEFAULT);
+ funcmux_select(id, uart_configs[i]);
clock_ll_start_uart(id);
}
}
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- assert(clock_id_isvalid(clkid));
+ assert(clock_id_is_pll(clkid));
return &clkrst->crc_pll[clkid];
}
assert(clkid != CLOCK_ID_USB);
/* Safety check, adds to code size but is small */
- if (!clock_id_isvalid(clkid) || clkid == CLOCK_ID_USB)
+ if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
return -1;
data = readl(&pll->pll_base);
*divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
# MA 02111-1307 USA
#
-# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build this
-# file with compatible flags
+# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build these
+# files with compatible flags
ifdef CONFIG_TEGRA2
CFLAGS_arch/arm/lib/board.o += -march=armv4t
+CFLAGS_arch/arm/lib/memset.o += -march=armv4t
+CFLAGS_lib/string.o += -march=armv4t
+CFLAGS_common/cmd_nvedit.o += -march=armv4t
endif
USE_PRIVATE_LIBGCC = yes
switch (id) {
case PERIPH_ID_UART1:
- if (config == FUNCMUX_UART1_IRRX_IRTX) {
+ switch (config) {
+ case FUNCMUX_UART1_IRRX_IRTX:
pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_IRRX);
pinmux_tristate_disable(PINGRP_IRTX);
+ break;
+ case FUNCMUX_UART1_UAA_UAB:
+ pinmux_set_func(PINGRP_UAA, PMUX_FUNC_UARTA);
+ pinmux_set_func(PINGRP_UAB, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PINGRP_UAA);
+ pinmux_tristate_disable(PINGRP_UAB);
+ bad_config = 0;
+ break;
+ case FUNCMUX_UART1_GPU:
+ pinmux_set_func(PINGRP_GPU, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PINGRP_GPU);
+ bad_config = 0;
+ break;
+ case FUNCMUX_UART1_SDIO1:
+ pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PINGRP_SDIO1);
+ bad_config = 0;
+ break;
+ }
+ if (!bad_config) {
/*
* Tegra appears to boot with function UARTA pre-
* selected on mux group SDB. If two mux groups are
}
break;
+ case PERIPH_ID_SDMMC1:
+ if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) {
+ pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1);
+ pinmux_tristate_disable(PINGRP_SDIO1);
+ }
+ break;
+
case PERIPH_ID_SDMMC2:
if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) {
pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2);
#ifndef _CLOCKS_AM33XX_H_
#define _CLOCKS_AM33XX_H_
-#define OSC 24
+#define OSC (V_OSCK/1000000)
/* MAIN PLL Fdll = 550 MHZ, */
#define MPUPLL_M 550
-#define MPUPLL_N 23
+#define MPUPLL_N (OSC-1)
#define MPUPLL_M2 1
/* Core PLL Fdll = 1 GHZ, */
#define COREPLL_M 1000
-#define COREPLL_N 23
+#define COREPLL_N (OSC-1)
#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
* For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
*/
#define PERPLL_M 960
-#define PERPLL_N 23
+#define PERPLL_N (OSC-1)
#define PERPLL_M2 5
/* DDR Freq is 266 MHZ for now */
/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
#define DDRPLL_M 266
-#define DDRPLL_N 23
+#define DDRPLL_N (OSC-1)
#define DDRPLL_M2 1
extern void pll_init(void);
/* Reset control */
#ifdef CONFIG_AM33XX
#define PRM_RSTCTRL 0x44E00F00
+#define PRM_RSTST 0x44E00F08
#endif
#define PRM_RSTCTRL_RESET 0x01
+#define PRM_RSTST_WARM_RESET_MASK 0x232
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct cm_wkuppll {
unsigned int wkclkstctrl; /* offset 0x00 */
unsigned int wkctrlclkctrl; /* offset 0x04 */
- unsigned int resv1[1];
+ unsigned int wkgpio0clkctrl; /* offset 0x08 */
unsigned int wkl4wkclkctrl; /* offset 0x0c */
unsigned int resv2[4];
unsigned int idlestdpllmpu; /* offset 0x20 */
unsigned int l3clkstctrl; /* offset 0x0c */
unsigned int resv1;
unsigned int cpgmac0clkctrl; /* offset 0x14 */
- unsigned int resv2[4];
+ unsigned int lcdclkctrl; /* offset 0x18 */
+ unsigned int usb0clkctrl; /* offset 0x1C */
+ unsigned int resv2;
+ unsigned int tptc0clkctrl; /* offset 0x24 */
unsigned int emifclkctrl; /* offset 0x28 */
unsigned int ocmcramclkctrl; /* offset 0x2c */
unsigned int gpmcclkctrl; /* offset 0x30 */
- unsigned int resv3[2];
+ unsigned int mcasp0clkctrl; /* offset 0x34 */
+ unsigned int uart5clkctrl; /* offset 0x38 */
unsigned int mmc0clkctrl; /* offset 0x3C */
unsigned int elmclkctrl; /* offset 0x40 */
unsigned int i2c2clkctrl; /* offset 0x44 */
unsigned int i2c1clkctrl; /* offset 0x48 */
unsigned int spi0clkctrl; /* offset 0x4C */
unsigned int spi1clkctrl; /* offset 0x50 */
- unsigned int resv4[3];
+ unsigned int resv3[3];
unsigned int l4lsclkctrl; /* offset 0x60 */
unsigned int l4fwclkctrl; /* offset 0x64 */
- unsigned int resv5[6];
+ unsigned int mcasp1clkctrl; /* offset 0x68 */
+ unsigned int uart1clkctrl; /* offset 0x6C */
+ unsigned int uart2clkctrl; /* offset 0x70 */
+ unsigned int uart3clkctrl; /* offset 0x74 */
+ unsigned int uart4clkctrl; /* offset 0x78 */
+ unsigned int timer7clkctrl; /* offset 0x7C */
unsigned int timer2clkctrl; /* offset 0x80 */
- unsigned int resv6[11];
+ unsigned int timer3clkctrl; /* offset 0x84 */
+ unsigned int timer4clkctrl; /* offset 0x88 */
+ unsigned int resv4[8];
+ unsigned int gpio1clkctrl; /* offset 0xAC */
unsigned int gpio2clkctrl; /* offset 0xB0 */
- unsigned int resv7[7];
+ unsigned int gpio3clkctrl; /* offset 0xB4 */
+ unsigned int resv5;
+ unsigned int tpccclkctrl; /* offset 0xBC */
+ unsigned int dcan0clkctrl; /* offset 0xC0 */
+ unsigned int dcan1clkctrl; /* offset 0xC4 */
+ unsigned int resv6[2];
unsigned int emiffwclkctrl; /* offset 0xD0 */
- unsigned int resv8[2];
+ unsigned int resv7[2];
unsigned int l3instrclkctrl; /* offset 0xDC */
unsigned int l3clkctrl; /* Offset 0xE0 */
- unsigned int resv9[14];
+ unsigned int resv8[4];
+ unsigned int mmc1clkctrl; /* offset 0xF4 */
+ unsigned int mmc2clkctrl; /* offset 0xF8 */
+ unsigned int resv9[8];
unsigned int l4hsclkstctrl; /* offset 0x11C */
unsigned int l4hsclkctrl; /* offset 0x120 */
unsigned int resv10[8];
- unsigned int cpswclkctrl; /* offset 0x144 */
+ unsigned int cpswclkstctrl; /* offset 0x144 */
};
/* Encapsulating Display pll registers */
unsigned int resv1[16];
unsigned int statusreg; /* ofset 0x40 */
};
-
-void init_timer(void);
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
unsigned short revnb_lo; /* 0x00 */
unsigned short res1;
unsigned short revnb_hi; /* 0x04 */
- unsigned short res2[13];
- unsigned short sysc; /* 0x20 */
- unsigned short res3;
+ unsigned short res2[5];
+ unsigned short sysc; /* 0x10 */
+ unsigned short res3[9];
unsigned short irqstatus_raw; /* 0x24 */
unsigned short res4;
unsigned short stat; /* 0x28 */
};
#define I2C_IP_CLK 48000000
-#define I2C_INTERNAL_SAMLPING_CLK 12000000
+#define I2C_INTERNAL_SAMPLING_CLK 12000000
#endif /* _I2C_H_ */
u32 puer; /* 0x64 Pull-up Enable Register */
u32 pusr; /* 0x68 Pad Pull-up Status Register */
u32 reserved4;
+#if defined(CPU_HAS_PIO3)
+ u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */
+ u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */
+ u32 reserved5[2];
+ u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */
+ u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */
+ u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */
+ u32 scdr; /* 0x8C SCLK Divider Debouncing Register */
+ u32 ppddr; /* 0x90 Pad Pull-down Disable Register */
+ u32 ppder; /* 0x94 Pad Pull-down Enable Register */
+ u32 ppdsr; /* 0x98 Pad Pull-down Status Register */
+ u32 reserved6; /* */
+#else
u32 asr; /* 0x70 Select A Register */
u32 bsr; /* 0x74 Select B Register */
u32 absr; /* 0x78 AB Select Status Register */
u32 reserved5[9]; /* */
+#endif
u32 ower; /* 0xA0 Output Write Enable Register */
u32 owdr; /* 0xA4 Output Write Disable Register */
- u32 owsr; /* OxA8 utput Write Status Register */
+ u32 owsr; /* OxA8 Output Write Status Register */
+#if defined(CPU_HAS_PIO3)
+ u32 reserved7; /* */
+ u32 aimer; /* 0xB0 Additional INT Modes Enable Register */
+ u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */
+ u32 aimmr; /* 0xB8 Additional INT Modes Mask Register */
+ u32 reserved8; /* */
+ u32 esr; /* 0xC0 Edge Select Register */
+ u32 lsr; /* 0xC4 Level Select Register */
+ u32 elsr; /* 0xC8 Edge/Level Status Register */
+ u32 reserved9; /* 0xCC */
+ u32 fellsr; /* 0xD0 Falling /Low Level Select Register */
+ u32 rehlsr; /* 0xD4 Rising /High Level Select Register */
+ u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */
+ u32 reserved10; /* */
+ u32 locksr; /* 0xE0 Lock Status */
+ u32 wpmr; /* 0xE4 Write Protect Mode Register */
+ u32 wpsr; /* 0xE8 Write Protect Status Register */
+ u32 reserved11[5]; /* */
+ u32 schmitt; /* 0x100 Schmitt Trigger Register */
+ u32 reserved12[63];
+#else
u32 reserved6[85];
+#endif
} at91_port_t;
typedef union at91_pio {
#ifdef CONFIG_AT91_GPIO
int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
+#if defined(CPU_HAS_PIO3)
+int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
+int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
+int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
+#endif
int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
int at91_set_pio_output(unsigned port, unsigned pin, int value);
#define DEVICE_NOT_AVAILABLE 0
+#define EXYNOS_CPU_NAME "Exynos"
#define EXYNOS4_ADDR_BASE 0x10000000
/* EXYNOS4 */
static inline void s5p_set_cpu_id(void)
{
- s5p_cpu_id = readl(EXYNOS4_PRO_ID);
- s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
-
- /*
- * 0xC200: EXYNOS4210 EVT0
- * 0xC210: EXYNOS4210 EVT1
- */
- if (s5p_cpu_id == 0xC200) {
- s5p_cpu_id |= 0x10;
+ unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12;
+
+ switch (pro_id) {
+ case 0x200:
+ /* Exynos4210 EVT0 */
+ s5p_cpu_id = 0x4210;
s5p_cpu_rev = 0;
- } else if (s5p_cpu_id == 0xC210) {
- s5p_cpu_rev = 1;
+ break;
+ case 0x210:
+ /* Exynos4210 EVT1 */
+ s5p_cpu_id = 0x4210;
+ break;
+ case 0x412:
+ /* Exynos4412 */
+ s5p_cpu_id = 0x4412;
+ break;
+ case 0x520:
+ /* Exynos5250 */
+ s5p_cpu_id = 0x5250;
+ break;
}
}
+static inline char *s5p_get_cpu_name(void)
+{
+ return EXYNOS_CPU_NAME;
+}
+
#define IS_SAMSUNG_TYPE(type, id) \
static inline int cpu_is_##type(void) \
{ \
- return s5p_cpu_id == id ? 1 : 0; \
+ return (s5p_cpu_id >> 12) == id; \
}
-IS_SAMSUNG_TYPE(exynos4, 0xc210)
-IS_SAMSUNG_TYPE(exynos5, 0xc520)
+IS_SAMSUNG_TYPE(exynos4, 0x4)
+IS_SAMSUNG_TYPE(exynos5, 0x5)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int samsung_get_base_##device(void) \
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_PERIPH_H
+#define __ASM_ARM_ARCH_PERIPH_H
+
+/*
+ * Peripherals requiring clock/pinmux configuration. List will
+ * grow with support for more devices getting added.
+ *
+ */
+enum periph_id {
+ PERIPH_ID_SDMMC0,
+ PERIPH_ID_SDMMC1,
+ PERIPH_ID_SDMMC2,
+ PERIPH_ID_SDMMC3,
+ PERIPH_ID_SROMC,
+ PERIPH_ID_UART0,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+ PERIPH_ID_UART3,
+
+ PERIPH_ID_COUNT,
+ PERIPH_ID_NONE = -1,
+};
+
+#endif /* __ASM_ARM_ARCH_PERIPH_H */
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Abhilash Kesavan <a.kesavan@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_PINMUX_H
+#define __ASM_ARM_ARCH_PINMUX_H
+
+#include "periph.h"
+
+/*
+ * Flags for setting specific configarations of peripherals.
+ * List will grow with support for more devices getting added.
+ */
+enum {
+ PINMUX_FLAG_NONE = 0x00000000,
+
+ /* Flags for eMMC */
+ PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */
+
+ /* Flags for SROM controller */
+ PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */
+ PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
+};
+
+/**
+ * Configures the pinmux for a particular peripheral.
+ *
+ * Each gpio can be configured in many different ways (4 bits on exynos)
+ * such as "input", "output", "special function", "external interrupt"
+ * etc. This function will configure the peripheral pinmux along with
+ * pull-up/down and drive strength.
+ *
+ * @param peripheral peripheral to be configured
+ * @param flags configure flags
+ * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
+ */
+int exynos_pinmux_config(int peripheral, int flags);
+
+#endif
#ifdef CONFIG_CMD_SF
#define CONFIG_HARD_SPI 1
#define CONFIG_KIRKWOOD_SPI 1
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */
+#ifndef CONFIG_ENV_SPI_BUS
+# define CONFIG_ENV_SPI_BUS 0
+#endif
+#ifndef CONFIG_ENV_SPI_CS
+# define CONFIG_ENV_SPI_CS 0
+#endif
+#ifndef CONFIG_ENV_SPI_MAX_HZ
+# define CONFIG_ENV_SPI_MAX_HZ 50000000
+#endif
#endif
/*
#define MPP_MAX 49
-void kirkwood_mpp_conf(unsigned int *mpp_list);
+void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save);
#endif
u32 irq_mask; /* 0x10614 */
};
+/* They are used to define CONFIG_SYS_KW_SPI_MPP
+ * each of the below #defines selects which mpp is
+ * configured for each SPI signal in spi_claim_bus
+ * bit 0: selects pin for MOSI (MPP1 if 0, MPP6 if 1)
+ * bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1)
+ * bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1)
+ */
+#define MOSI_MPP6 (1 << 0)
+#define SCK_MPP10 (1 << 1)
+#define MISO_MPP11 (1 << 2)
+
#define KWSPI_CLKPRESCL_MASK 0x1f
#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */
#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */
#define mx28_reg_8(name) \
union { \
struct { __mx28_reg_8(name) }; \
- struct mx28_register_32 name##_reg; \
+ struct mx28_register_8 name##_reg; \
};
#define mx28_reg_32(name) \
#define PAD_CTL_SRE_FAST (1 << 0)
#define PAD_CTL_SRE_SLOW (0 << 0)
-#define NO_MUX_I 0x3FF
-#define NO_PAD_I 0x7FF
+#define NO_MUX_I 0
+#define NO_PAD_I 0
enum {
MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),
#define PRM_RSTCTRL 0x48307250
#define PRM_RSTCTRL_RESET 0x04
+#define PRM_RSTST 0x48307258
+#define PRM_RSTST_WARM_RESET_MASK 0x7D2
#define SYSCLKDIV_1 (0x1 << 6)
#define SYSCLKDIV_2 (0x1 << 7)
void dieid_num_r(void);
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
void omap3_gp_romcode_call(u32 service_id, u32 parameter);
+u32 warm_reset(void);
#endif
#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
+/* CM_DLL_CTRL */
+#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
+#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
+#define CM_DLL_CTRL_NO_OVERRIDE 0
+
/* CM_CLKMODE_DPLL */
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
#define PRM_RSTCTRL PRM_DEVICE_BASE
#define PRM_RSTCTRL_RESET 0x01
+#define PRM_RSTST (PRM_DEVICE_BASE + 0x4)
+#define PRM_RSTST_WARM_RESET_MASK 0x07EA
#endif /* _CPU_H */
#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
#define LPDDR2IO_GR10_WD_MASK (3 << 17)
-#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00
+#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F
/* CONTROL_EFUSE_2 */
#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
void do_io_settings(void);
void omap_vc_init(u16 speed_khz);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
+u32 warm_reset(void);
+void force_emif_self_refresh(void);
/*
* This is used to verify if the configuration header
* was executed by Romcode prior to control of transfer
u32 pad217[4];
u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */
u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */
+ u32 pad218[2];
+ u32 prm_sldo_core_setup; /* 4ae07bc4 */
+ u32 prm_sldo_core_ctrl; /* 4ae07bc8 */
+ u32 prm_sldo_mpu_setup; /* 4ae07bcc */
+ u32 prm_sldo_mpu_ctrl; /* 4ae07bd0 */
+ u32 prm_sldo_mm_setup; /* 4ae07bd4 */
+ u32 prm_sldo_mm_ctrl; /* 4ae07bd8 */
};
/* DPLL register offsets */
#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
+/* CM_DLL_CTRL */
+#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
+#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
+#define CM_DLL_CTRL_NO_OVERRIDE 0
+
/* CM_CLKMODE_DPLL */
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
#define VDD_MPU 1000
#define VDD_MM 1000
#define VDD_CORE 1040
+#define VDD_MPU_5432 1150
+#define VDD_MM_5432 1150
+#define VDD_CORE_5432 1150
/* Standard offset is 0.5v expressed in uv */
#define PALMAS_SMPS_BASE_VOLT_UV 500000
#define PRM_RSTCTRL PRM_DEVICE_BASE
#define PRM_RSTCTRL_RESET 0x01
+#define PRM_RSTST (PRM_DEVICE_BASE + 0x4)
+#define PRM_RSTST_WARM_RESET_MASK 0x7FEA
#endif /* _CPU_H */
#define OMAP54XX_L4_PER_BASE 0x48000000
#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
-#define OMAP54XX_DRAM_ADDR_SPACE_END 0xD0000000
+#define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF
#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START
#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END
#define CONTROL_ID_CODE (CTRL_BASE + 0x204)
/* To be verified */
-#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B85202F
+#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
+#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
/* STD_FUSE_PROD_ID_1 */
#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
u32 control_srcomp_east_side; /*0x4A002E7C*/
u32 control_srcomp_west_side; /*0x4A002E80*/
u32 control_srcomp_code_latch; /*0x4A002E84*/
- u32 pad4[3680198];
+ u32 pad4[3679394];
+ u32 control_port_emif1_sdram_config; /*0x4AE0C110*/
+ u32 control_port_emif1_lpddr2_nvm_config; /*0x4AE0C114*/
+ u32 control_port_emif2_sdram_config; /*0x4AE0C118*/
+ u32 pad5[10];
+ u32 control_emif1_sdram_config_ext; /* 0x4AE0C144 */
+ u32 control_emif2_sdram_config_ext; /* 0x4AE0C148 */
+ u32 pad6[789];
u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
u32 control_padconf_mode; /* 0x4AE0CDA8 */
#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
+#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C
+#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464
+#define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631
+#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC
+#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0
+
#define EFUSE_1 0x45145100
#define EFUSE_2 0x45145100
#define EFUSE_3 0x45145100
void do_io_settings(void);
void omap_vc_init(u16 speed_khz);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
+u32 warm_reset(void);
+void force_emif_self_refresh(void);
/*
* This is used to verify if the configuration header
#ifndef _S5PC1XX_CPU_H
#define _S5PC1XX_CPU_H
+#define S5P_CPU_NAME "S5P"
#define S5PC1XX_ADDR_BASE 0xE0000000
/* S5PC100 */
s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12);
}
+static inline char *s5p_get_cpu_name(void)
+{
+ return S5P_CPU_NAME;
+}
+
#define IS_SAMSUNG_TYPE(type, id) \
static inline int cpu_is_##type(void) \
{ \
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
+{
+ return 83000000;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __ASM_ARCH_SPEAR_GPIO_H
+#define __ASM_ARCH_SPEAR_GPIO_H
+
+enum gpio_direction {
+ GPIO_DIRECTION_IN,
+ GPIO_DIRECTION_OUT,
+};
+
+struct gpio_regs {
+ u32 gpiodata[0x100]; /* 0x000 ... 0x3fc */
+ u32 gpiodir; /* 0x400 */
+};
+
+#define SPEAR_GPIO_COUNT 8
+#define DATA_REG_ADDR(gpio) (1 << (gpio + 2))
+
+#endif /* __ASM_ARCH_SPEAR_GPIO_H */
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
-#define CONFIG_SYS_USBD_BASE (0xE1100000)
-#define CONFIG_SYS_PLUG_BASE (0xE1200000)
-#define CONFIG_SYS_FIFO_BASE (0xE1000800)
-#define CONFIG_SYS_SMI_BASE (0xFC000000)
-#define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000)
-#define CONFIG_SPEAR_TIMERBASE (0xFC800000)
-#define CONFIG_SPEAR_MISCBASE (0xFCA80000)
+#define CONFIG_SYS_USBD_BASE 0xE1100000
+#define CONFIG_SYS_PLUG_BASE 0xE1200000
+#define CONFIG_SYS_FIFO_BASE 0xE1000800
+#define CONFIG_SYS_SMI_BASE 0xFC000000
+#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000
+#define CONFIG_SPEAR_TIMERBASE 0xFC800000
+#define CONFIG_SPEAR_MISCBASE 0xFCA80000
+#define CONFIG_SPEAR_ETHBASE 0xE0800000
+#define CONFIG_SPEAR_MPMCBASE 0xFC600000
+#define CONFIG_SSP1_BASE 0xD0100000
+#define CONFIG_SSP2_BASE 0xD0180000
+#define CONFIG_SSP3_BASE 0xD8180000
+#define CONFIG_GPIO_BASE 0xD8100000
#define CONFIG_SYS_NAND_CLE (1 << 16)
#define CONFIG_SYS_NAND_ALE (1 << 17)
#if defined(CONFIG_SPEAR600)
-#define CONFIG_SYS_I2C_BASE (0xD0200000)
-#define CONFIG_SPEAR_FSMCBASE (0xD1800000)
+#define CONFIG_SYS_I2C_BASE 0xD0200000
+#define CONFIG_SYS_FSMC_BASE 0xD1800000
+#define CONFIG_FSMC_NAND_BASE 0xD2000000
+
+#define CONFIG_SPEAR_BOOTSTRAPCFG 0xFCA80000
+#define CONFIG_SPEAR_BOOTSTRAPSHFT 16
+#define CONFIG_SPEAR_BOOTSTRAPMASK 0xB
+#define CONFIG_SPEAR_ONLYSNORBOOT 0xA
+#define CONFIG_SPEAR_NORNANDBOOT 0xB
+#define CONFIG_SPEAR_NORNAND8BOOT 0x8
+#define CONFIG_SPEAR_NORNAND16BOOT 0x9
+#define CONFIG_SPEAR_USBBOOT 0x8
+
+#define CONFIG_SPEAR_MPMCREGS 100
#elif defined(CONFIG_SPEAR300)
-#define CONFIG_SYS_I2C_BASE (0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE (0x94000000)
+#define CONFIG_SYS_I2C_BASE 0xD0180000
+#define CONFIG_SYS_FSMC_BASE 0x94000000
#elif defined(CONFIG_SPEAR310)
-#define CONFIG_SYS_I2C_BASE (0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE (0x44000000)
+#define CONFIG_SYS_I2C_BASE 0xD0180000
+#define CONFIG_SYS_FSMC_BASE 0x44000000
#undef CONFIG_SYS_NAND_CLE
#undef CONFIG_SYS_NAND_ALE
#define CONFIG_SYS_NAND_CLE (1 << 17)
#define CONFIG_SYS_NAND_ALE (1 << 16)
-#define CONFIG_SPEAR_EMIBASE (0x4F000000)
-#define CONFIG_SPEAR_RASBASE (0xB4000000)
+#define CONFIG_SPEAR_EMIBASE 0x4F000000
+#define CONFIG_SPEAR_RASBASE 0xB4000000
+
+#define CONFIG_SYS_MACB0_BASE 0xB0000000
+#define CONFIG_SYS_MACB1_BASE 0xB0800000
+#define CONFIG_SYS_MACB2_BASE 0xB1000000
+#define CONFIG_SYS_MACB3_BASE 0xB1800000
#elif defined(CONFIG_SPEAR320)
-#define CONFIG_SYS_I2C_BASE (0xD0180000)
-#define CONFIG_SPEAR_FSMCBASE (0x4C000000)
+#define CONFIG_SYS_I2C_BASE 0xD0180000
+#define CONFIG_SYS_FSMC_BASE 0x4C000000
+
+#define CONFIG_SPEAR_EMIBASE 0x40000000
+#define CONFIG_SPEAR_RASBASE 0xB3000000
-#define CONFIG_SPEAR_EMIBASE (0x40000000)
-#define CONFIG_SPEAR_RASBASE (0xB3000000)
+#define CONFIG_SYS_MACB0_BASE 0xAA000000
#endif
#endif /* _ASM_ARCH_HARDWARE_H */
extern void setfreq(unsigned int, unsigned int);
extern unsigned int setfreq_sz;
+void plat_ddr_init(void);
+void soc_init(void);
+void spear_late_init(void);
+void plat_late_init(void);
+
+int snor_boot_selected(void);
+int nand_boot_selected(void);
+int pnor_boot_selected(void);
+int usb_boot_selected(void);
+int uart_boot_selected(void);
+int tftp_boot_selected(void);
+int i2c_boot_selected(void);
+int spi_boot_selected(void);
+int mmc_boot_selected(void);
+
+extern u32 mpmc_conf_vals[];
+
struct chip_data {
int cpufreq;
int dramfreq;
#define MAC_OFF 0x2
#define MAC_LEN 0x6
+#define PNOR_WIDTH_8 0
+#define PNOR_WIDTH_16 1
+#define PNOR_WIDTH_32 2
+#define PNOR_WIDTH_NUM 3
+#define PNOR_WIDTH_SEARCH 0xff
+
#endif
#define GPT_FREE_RUNNING 0xFFFF
/* Timer, HZ specific defines */
-#define CONFIG_SPEAR_HZ (1000)
-#define CONFIG_SPEAR_HZ_CLOCK (8300000)
+#define CONFIG_SPEAR_HZ 1000
+#define CONFIG_SPEAR_HZ_CLOCK 8300000
#endif
u32 amba_clk_cfg; /* 0x24 */
u32 periph_clk_cfg; /* 0x28 */
u32 periph1_clken; /* 0x2C */
- u32 periph2_clken; /* 0x30 */
+ u32 soc_core_id; /* 0x30 */
u32 ras_clken; /* 0x34 */
u32 periph1_rst; /* 0x38 */
u32 periph2_rst; /* 0x3C */
u32 prsc2_clk_cfg; /* 0x48 */
u32 prsc3_clk_cfg; /* 0x4C */
u32 amem_cfg_ctrl; /* 0x50 */
- u32 port_cfg_ctrl; /* 0x54 */
+ u32 expi_clk_cfg; /* 0x54 */
u32 reserved_1; /* 0x58 */
u32 clcd_synth_clk; /* 0x5C */
u32 irda_synth_clk; /* 0x60 */
u32 ras_gpp2_out; /* 0x800C */
};
+/* SYNTH_CLK value*/
+#define SYNTH23 0x00020003
+
+/* PLLx_FRQ value */
+#if defined(CONFIG_SPEAR3XX)
+#define FREQ_332 0xA600010C
+#define FREQ_266 0x8500010C
+#elif defined(CONFIG_SPEAR600)
+#define FREQ_332 0xA600010F
+#define FREQ_266 0x8500010F
+#endif
+
+/* PLL_CTR_REG */
+#define MEM_CLK_SEL_MSK 0x70000000
+#define MEM_CLK_HCLK 0x00000000
+#define MEM_CLK_2HCLK 0x10000000
+#define MEM_CLK_PLL2 0x30000000
+
+#define EXPI_CLK_CFG_LOW_COMPR 0x2000
+#define EXPI_CLK_CFG_CLK_EN 0x0400
+#define EXPI_CLK_CFG_RST 0x0200
+#define EXPI_CLK_SYNT_EN 0x0010
+#define EXPI_CLK_CFG_SEL_PLL2 0x0004
+#define EXPI_CLK_CFG_INT_CLK_EN 0x0001
+
+#define PLL2_CNTL_6UA 0x1c00
+#define PLL2_CNTL_SAMPLE 0x0008
+#define PLL2_CNTL_ENABLE 0x0004
+#define PLL2_CNTL_RESETN 0x0002
+#define PLL2_CNTL_LOCK 0x0001
+
/* AUTO_CFG_REG value */
#define MISC_SOCCFGMSK 0x0000003F
#define MISC_SOCCFG30 0x0000000C
/* PERIPH_CLK_CFG value */
#define MISC_GPT3SYNTH 0x00000400
#define MISC_GPT4SYNTH 0x00000800
+#define CONFIG_SPEAR_UART48M 0
+#define CONFIG_SPEAR_UARTCLKMSK (0x1 << 4)
/* PRSC_CLK_CFG value */
/*
/* PERIPH1_CLKEN, PERIPH1_RST value */
#define MISC_USBDENB 0x01000000
+#define MISC_ETHENB 0x00800000
+#define MISC_SMIENB 0x00200000
+#define MISC_GPT3ENB 0x00010000
+#define MISC_GPIO4ENB 0x00002000
+#define MISC_GPT2ENB 0x00000800
+#define MISC_FSMCENB 0x00000200
+#define MISC_I2CENB 0x00000080
+#define MISC_SSP2ENB 0x00000070
+#define MISC_UART0ENB 0x00000008
+
+/* PERIPH_CLK_CFG */
+#define XTALTIMEEN 0x00000001
+#define PLLTIMEEN 0x00000002
+#define CLCDCLK_SYNTH 0x00000000
+#define CLCDCLK_48MHZ 0x00000004
+#define CLCDCLK_EXT 0x00000008
+#define UARTCLK_MASK (0x1 << 4)
+#define UARTCLK_48MHZ 0x00000000
+#define UARTCLK_SYNTH 0x00000010
+#define IRDACLK_48MHZ 0x00000000
+#define IRDACLK_SYNTH 0x00000020
+#define IRDACLK_EXT 0x00000040
+#define RTC_DISABLE 0x00000080
+#define GPT1CLK_48MHZ 0x00000000
+#define GPT1CLK_SYNTH 0x00000100
+#define GPT2CLK_48MHZ 0x00000000
+#define GPT2CLK_SYNTH 0x00000200
+#define GPT3CLK_48MHZ 0x00000000
+#define GPT3CLK_SYNTH 0x00000400
+#define GPT4CLK_48MHZ 0x00000000
+#define GPT4CLK_SYNTH 0x00000800
+#define GPT5CLK_48MHZ 0x00000000
+#define GPT5CLK_SYNTH 0x00001000
+#define GPT1_FREEZE 0x00002000
+#define GPT2_FREEZE 0x00004000
+#define GPT3_FREEZE 0x00008000
+#define GPT4_FREEZE 0x00010000
+#define GPT5_FREEZE 0x00020000
+
+/* PERIPH1_CLKEN bits */
+#define PERIPH_ARM1_WE 0x00000001
+#define PERIPH_ARM1 0x00000002
+#define PERIPH_ARM2 0x00000004
+#define PERIPH_UART1 0x00000008
+#define PERIPH_UART2 0x00000010
+#define PERIPH_SSP1 0x00000020
+#define PERIPH_SSP2 0x00000040
+#define PERIPH_I2C 0x00000080
+#define PERIPH_JPEG 0x00000100
+#define PERIPH_FSMC 0x00000200
+#define PERIPH_FIRDA 0x00000400
+#define PERIPH_GPT4 0x00000800
+#define PERIPH_GPT5 0x00001000
+#define PERIPH_GPIO4 0x00002000
+#define PERIPH_SSP3 0x00004000
+#define PERIPH_ADC 0x00008000
+#define PERIPH_GPT3 0x00010000
+#define PERIPH_RTC 0x00020000
+#define PERIPH_GPIO3 0x00040000
+#define PERIPH_DMA 0x00080000
+#define PERIPH_ROM 0x00100000
+#define PERIPH_SMI 0x00200000
+#define PERIPH_CLCD 0x00400000
+#define PERIPH_GMAC 0x00800000
+#define PERIPH_USBD 0x01000000
+#define PERIPH_USBH1 0x02000000
+#define PERIPH_USBH2 0x04000000
+#define PERIPH_MPMC 0x08000000
+#define PERIPH_RAMW 0x10000000
+#define PERIPH_MPMC_EN 0x20000000
+#define PERIPH_MPMC_WE 0x40000000
+#define PERIPH_MPMCMSK 0x60000000
+
+#define PERIPH_CLK_ALL 0x0FFFFFF8
+#define PERIPH_RST_ALL 0x00000004
+
+/* DDR_PAD values */
+#define DDR_PAD_CNF_MSK 0x0000ffff
+#define DDR_PAD_SW_CONF 0x00060000
+#define DDR_PAD_SSTL_SEL 0x00000001
+#define DDR_PAD_DRAM_TYPE 0x00008000
+
+/* DDR_COMP values */
+#define DDR_COMP_ACCURATE 0x00000010
+
+/* SoC revision stuff */
+#define SOC_PRI_SHFT 16
+#define SOC_SEC_SHFT 8
+
+/* Revision definitions */
+#define SOC_SPEAR_NA 0
+
+/*
+ * The definitons have started from
+ * 101 for SPEAr6xx
+ * 201 for SPEAr3xx
+ * 301 for SPEAr13xx
+ */
+#define SOC_SPEAR600_AA 101
+#define SOC_SPEAR600_AB 102
+#define SOC_SPEAR600_BA 103
+#define SOC_SPEAR600_BB 104
+#define SOC_SPEAR600_BC 105
+#define SOC_SPEAR600_BD 106
+
+#define SOC_SPEAR300 201
+#define SOC_SPEAR310 202
+#define SOC_SPEAR320 203
+
+extern int get_socrev(void);
#endif
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SPR_NAND_H__
-#define __SPR_NAND_H__
-
-struct fsmc_regs {
- u32 reserved_1[0x10];
- u32 genmemctrl_pc;
- u32 reserved_2;
- u32 genmemctrl_comm;
- u32 genmemctrl_attrib;
- u32 reserved_3;
- u32 genmemctrl_ecc;
-};
-
-/* genmemctrl_pc register definitions */
-#define FSMC_RESET (1 << 0)
-#define FSMC_WAITON (1 << 1)
-#define FSMC_ENABLE (1 << 2)
-#define FSMC_DEVTYPE_NAND (1 << 3)
-#define FSMC_DEVWID_8 (0 << 4)
-#define FSMC_DEVWID_16 (1 << 4)
-#define FSMC_ECCEN (1 << 6)
-#define FSMC_ECCPLEN_512 (0 << 7)
-#define FSMC_ECCPLEN_256 (1 << 7)
-#define FSMC_TCLR_1 (1 << 9)
-#define FSMC_TAR_1 (1 << 13)
-
-/* genmemctrl_comm register definitions */
-#define FSMC_TSET_0 (0 << 0)
-#define FSMC_TWAIT_6 (6 << 8)
-#define FSMC_THOLD_4 (4 << 16)
-#define FSMC_THIZ_1 (1 << 24)
-
-extern int spear_nand_init(struct nand_chip *nand);
-#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPR_SSP_H
+#define _SPR_SSP_H
+
+struct ssp_regs {
+ u32 sspcr0;
+ u32 sspcr1;
+ u32 sspdr;
+ u32 sspsr;
+ u32 sspcpsr;
+ u32 sspimsc;
+ u32 sspicr;
+ u32 sspdmacr;
+};
+
+#define SSPCR0_FRF_MOT_SPI 0x0000
+#define SSPCR0_DSS_16BITS 0x000f
+
+#define SSPCR1_SSE 0x0002
+
+#define SSPSR_TNF 0x2
+#define SSPSR_TFE 0x1
+
+#endif
* MA 02111-1307 USA
*/
+#ifndef __SYSCTRL_H
+#define __SYSCTRL_H
+
struct syscntl_regs {
u32 scctrl;
u32 scsysstat;
const u32 scperclken;
const u32 scperstat;
};
+
+#define MODE_SHIFT 0x00000003
+
+#define NORMAL 0x00000004
+#define SLOW 0x00000002
+#define DOZE 0x00000001
+#define SLEEP 0x00000000
+
+#define PLL_TIM 0x01FFFFFF
+
+#endif
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SPR_XLOADER_TABLE_H
-#define _SPR_XLOADER_TABLE_H
-
-#define XLOADER_TABLE_VERSION_1_1 2
-#define XLOADER_TABLE_VERSION_1_2 3
-
-#define XLOADER_TABLE_ADDRESS 0xD2801FF0
-
-#define DDRMOBILE 1
-#define DDR2 2
-
-#define REV_BA 1
-#define REV_AA 2
-#define REV_AB 3
-
-struct xloader_table_1_1 {
- unsigned short ddrfreq;
- unsigned char ddrsize;
- unsigned char ddrtype;
-
- unsigned char soc_rev;
-} __attribute__ ((packed));
-
-struct xloader_table_1_2 {
- unsigned const char *version;
-
- unsigned short ddrfreq;
- unsigned char ddrsize;
- unsigned char ddrtype;
-
- unsigned char soc_rev;
-} __attribute__ ((packed));
-
-union table_contents {
- struct xloader_table_1_1 table_1_1;
- struct xloader_table_1_2 table_1_2;
-};
-
-struct xloader_table {
- unsigned char table_version;
- union table_contents table;
-} __attribute__ ((packed));
-
-#endif
/* Mask value for a clock (within PERIPH_REG(id)) */
#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
-/* return 1 if a PLL ID is in range */
-#define clock_id_isvalid(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+/* return 1 if a PLL ID is in range, and not a simple PLL */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
+ (id) < CLOCK_ID_FIRST_SIMPLE)
/* PLL stabilization delay in usec */
#define CLOCK_PLL_STABLE_DELAY_US 300
/* UART configs */
FUNCMUX_UART1_IRRX_IRTX = 0,
+ FUNCMUX_UART1_UAA_UAB,
+ FUNCMUX_UART1_GPU,
+ FUNCMUX_UART1_SDIO1,
FUNCMUX_UART2_IRDA = 0,
FUNCMUX_UART4_GMC = 0,
FUNCMUX_I2C3_DTF = 0,
/* SDMMC configs */
+ FUNCMUX_SDMMC1_SDIO1_4BIT = 0,
FUNCMUX_SDMMC2_DTA_DTD_8BIT = 0,
FUNCMUX_SDMMC3_SDB_4BIT = 0,
FUNCMUX_SDMMC3_SDB_SLXA_8BIT,
* Copyright (c) 2011, Google Inc. All rights reserved.
* See file CREDITS for list of people who contributed to this
* project.
+ * Portions Copyright 2011-2012 NVIDIA Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* MA 02111-1307 USA
*/
-#ifndef _TEGRA2_GPIO_H_
-#define _TEGRA2_GPIO_H_
+#ifndef _TEGRA_GPIO_H_
+#define _TEGRA_GPIO_H_
/*
* The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports,
void gpio_info(void);
#define gpio_status() gpio_info()
-#endif /* TEGRA2_GPIO_H_ */
+#endif /* TEGRA_GPIO_H_ */
PINGRP_KBCF,
PINGRP_GMA,
PINGRP_GMC,
- PINGRP_SDMMC1,
+ PINGRP_SDIO1,
PINGRP_OWC,
/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
#define AP20_WB_RUN_ADDRESS 0x40020000
+#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */
+#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */
+
/* These are the available SKUs (product types) for Tegra */
enum {
SKU_ID_T20 = 0x8,
/*
* NVIDIA Tegra2 SPI-FLASH controller
*
- * Copyright 2010-2011 NVIDIA Corporation
+ * Copyright 2010-2012 NVIDIA Corporation
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* MA 02111-1307 USA
*/
-#ifndef _TEGRA2_SPI_H_
-#define _TEGRA2_SPI_H_
+#ifndef _TEGRA_SPI_H_
+#define _TEGRA_SPI_H_
#include <asm/types.h>
#define SPI_TIMEOUT 1000
#define TEGRA2_SPI_MAX_FREQ 52000000
-
-#endif /* _TEGRA2_SPI_H_ */
+#endif /* _TEGRA_SPI_H_ */
* time! If the board file provides this, the board config will declare it.
* Let this be a lesson for others.
*/
-void pinmux_select_uart(NS16550_t regs);
+void pinmux_select_uart(void);
/*
* Signal that we are about the use the SPI bus.
#else /* not CONFIG_SPI_UART_SWITCH */
-static inline void pinmux_select_uart(NS16550_t regs) {}
+static inline void pinmux_select_uart(void) {}
static inline void pinmux_select_spi(void) {}
#endif
#define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0
#define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0)
+/*EMIF_READ_WRITE_LEVELING_CONTROL*/
+#define EMIF_REG_RDWRLVLFULL_START_SHIFT 31
+#define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31)
+#define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24
+#define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24)
+#define EMIF_REG_RDLVLINC_INT_SHIFT 16
+#define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16)
+#define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8
+#define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8)
+#define EMIF_REG_WRLVLINC_INT_SHIFT 0
+#define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0)
+
+/*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/
+#define EMIF_REG_RDWRLVL_EN_SHIFT 31
+#define EMIF_REG_RDWRLVL_EN_MASK (1 << 31)
+#define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24
+#define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24)
+#define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16
+#define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16)
+#define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8
+#define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8)
+#define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0
+#define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0)
+
+/*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/
+#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0
+#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0)
+
+/*Leveling Fields */
+#define DDR3_WR_LVL_INT 0x73
+#define DDR3_RD_LVL_INT 0x33
+#define DDR3_RD_LVL_GATE_INT 0x59
+#define RD_RW_LVL_INC_PRE 0x0
+#define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT)
+
+#define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \
+ | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \
+ | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \
+ | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT))
+
+#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7
+#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7
+
/* DMM */
#define DMM_BASE 0x4E000040
};
extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
+extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
#define CS0 0
#define CS1 1
u32 emif_ddr_ext_phy_ctrl_3;
u32 emif_ddr_ext_phy_ctrl_4;
u32 emif_ddr_ext_phy_ctrl_5;
+ u32 emif_rd_wr_lvl_rmp_win;
+ u32 emif_rd_wr_lvl_rmp_ctl;
+ u32 emif_rd_wr_lvl_ctl;
+ u32 emif_rd_wr_exec_thresh;
};
/* assert macros */
const struct lpddr2_device_timings **cs1_device_timings);
#endif
+void do_ext_phy_settings(u32 base, const struct emif_regs *regs);
+
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
extern u32 *const T_num;
extern u32 *const T_den;
extern u32 *const emif_sizes;
#endif
-
+void config_data_eye_leveling_samples(u32 emif_base);
#endif
/* omap5 */
#define OMAP5430_SILICON_ID_INVALID 0
#define OMAP5430_ES1_0 0x54300100
+#define OMAP5432_ES1_0 0x54320100
#endif /* _OMAP_COMMON_H_ */
/* cpu/.../arch/cpu.c */
int arch_cpu_init(void);
int arch_misc_init(void);
+int arch_early_init_r(void);
/* board/.../... */
int board_init(void);
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
+#ifdef CONFIG_ARCH_EARLY_INIT_R
+ arch_early_init_r();
+#endif
+
#if !defined(CONFIG_SYS_NO_FLASH)
puts("Flash: ");
{
uint32_t reg;
+ reg = get_cr();
+ cp_delay();
+
if (cache_bit == CR_C) {
/* if cache isn;t enabled no need to disable */
- reg = get_cr();
if ((reg & CR_C) != CR_C)
return;
/* if disabling data cache, disable mmu too */
cache_bit |= CR_M;
flush_dcache_all();
}
- reg = get_cr();
- cp_delay();
set_cr(reg & ~cache_bit);
}
#endif
int raise (int signum)
{
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+ /* Even if printf() is available, it's large. Punt it for SPL builds */
+#if !defined(CONFIG_SPL_BUILD)
printf("raise: Signal # %d caught\n", signum);
#endif
return 0;
#
-# (C) Copyright 2009
-# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2009-2012
+# Jens Scharsig <esw@bus-elekronik.de>
+# BuS Elektronik GmbH & Co. KG
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# MA 02111-1307 USA
#
-#########################################################################
+include $(TOPDIR)/config.mk
-CONFIG_SYS_TEXT_BASE = 0x00700000
+LIB = $(obj)lib$(BOARD).o
-ALL-y += $(obj)u-boot.img
+COBJS += vl_ma2sc.o
-# Environment variables in NAND
-ifeq ($(ENV),NAND)
-PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
-else
-PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
-endif
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-# Support parallel flash
-ifeq ($(FLASH),PNOR)
-PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR
-endif
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
-ifeq ($(CONSOLE),USB)
-PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
-endif
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2009-2012
+ * Jens Scharsig <esw@bus-elekronik.de>
+ * BuS Elektronik GmbH & Co. KG
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_common.h>
+#include <lcd.h>
+#include <i2c.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NAND
+static void vl_ma2sc_nand_hw_init(void)
+{
+ unsigned long csa;
+ at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
+ at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */
+ at91_set_pio_output(AT91_PIO_PORTA, 12, 1); /* CAN_STB -> H */
+ at91_set_pio_output(AT91_PIO_PORTA, 11, 1); /* CAN_EN -> H */
+
+ /* Enable CS3 */
+ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->csa[0]);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+ writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE),
+ &pmc->pcer);
+
+ /* Configure RDY/BSY */
+#ifdef CONFIG_SYS_NAND_READY_PIN
+ at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+#endif
+ /* Enable NandFlash */
+ at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void vl_ma2sc_macb_hw_init(void)
+{
+ unsigned long erstl;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+ at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
+ /* Enable clock */
+ writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+
+ erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
+
+ /* Need to reset PHY -> 500ms reset */
+ writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
+ AT91_RSTC_MR_URSTEN, &rstc->mr);
+
+ writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
+ /* Wait for end hardware reset */
+ while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
+ ;
+
+ /* Restore NRST value */
+ writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+
+ at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ .vl_col = 320,
+ .vl_row = 240,
+ .vl_clk = 6500000,
+ .vl_sync = ATMEL_LCDC_INVDVAL_INVERTED |
+ ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVVD_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ .vl_bpix = (ATMEL_LCDC_PIXELSIZE_8 >> 5),
+ .vl_tft = 1,
+ .vl_hsync_len = 5, /* Horiz Sync Pulse Width */
+ .vl_left_margin = 68, /* horiz back porch */
+ .vl_right_margin = 20, /* horiz front porch */
+ .vl_vsync_len = 2, /* vert Sync Pulse Width */
+ .vl_upper_margin = 18, /* vert back porch */
+ .vl_lower_margin = 4, /* vert front porch */
+ .mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+}
+
+void lcd_disable(void)
+{
+}
+
+static void vl_ma2sc_lcd_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
+ at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
+ at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
+
+ at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD0 */
+ at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD1 */
+ at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
+
+ at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD9 */
+ at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
+ at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
+
+ at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD26 */
+ at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD17 */
+ at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
+ at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
+ at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
+ at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
+ at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
+ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
+
+ at91_set_pio_output(AT91_PIO_PORTE, 0, 0); /* LCD QXH */
+
+ at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* LCD SHUT */
+ at91_set_pio_output(AT91_PIO_PORTE, 3, 1); /* LCD TopBottom */
+ at91_set_pio_output(AT91_PIO_PORTE, 4, 0); /* LCD REV */
+ at91_set_pio_output(AT91_PIO_PORTE, 5, 1); /* LCD RightLeft */
+ at91_set_pio_output(AT91_PIO_PORTE, 6, 0); /* LCD Color Mode CM */
+ at91_set_pio_output(AT91_PIO_PORTE, 7, 0); /* LCD BGR */
+
+ at91_set_pio_output(AT91_PIO_PORTB, 9, 0); /* LCD CC */
+
+ writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+ gd->fb_base = ATMEL_BASE_SRAM0;
+}
+#endif /* Config LCD */
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable clocks for all PIOs */
+ writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+ (1 << ATMEL_ID_PIOCDE),
+ &pmc->pcer);
+
+ at91_seriald_hw_init();
+
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+ u32 pin;
+
+ pin = 0x1F000001;
+ writel(pin, &pio->pioa.idr);
+ writel(pin, &pio->pioa.pudr);
+ writel(pin, &pio->pioa.per);
+ writel(pin, &pio->pioa.oer);
+ writel(pin, &pio->pioa.sodr);
+ writel((1 << 25), &pio->pioa.codr);
+
+ pin = 0x1F000100;
+ writel(pin, &pio->piob.idr);
+ writel(pin, &pio->piob.pudr);
+ writel(pin, &pio->piob.per);
+ writel(pin, &pio->piob.oer);
+ writel(pin, &pio->piob.codr);
+ writel((1 << 24), &pio->piob.sodr);
+
+ pin = 0x40000000; /* Pullup DRxD enbable */
+ writel(pin, &pio->pioc.puer);
+
+ pin = 0x0000000F; /* HWversion als Input */
+ writel(pin, &pio->piod.idr);
+ writel(pin, &pio->piod.puer);
+ writel(pin, &pio->piod.per);
+ writel(pin, &pio->piod.odr);
+ writel(pin, &pio->piod.owdr);
+
+ /* Enable Ctrlc */
+ console_init_f();
+
+ gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup);
+ writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle);
+ writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse);
+ writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup);
+
+#ifdef CONFIG_CMD_NAND
+ vl_ma2sc_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+ vl_ma2sc_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+ at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+ vl_ma2sc_lcd_hw_init();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ uchar buffer[8];
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+ u32 pin;
+
+ buffer[0] = 0x04;
+ buffer[1] = 0x00;
+ if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0)
+ puts("error reseting rtc clock\n\0");
+
+ /* read hardware version */
+
+ pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44;
+ printf("Board: revision %c\n", pin);
+ buffer[0] = pin;
+ buffer[1] = 0;
+ setenv("revision", (char *) buffer);
+
+ pin = 0x40000000; /* Pullup DRxD enbable */
+ writel(pin, &pio->pioc.puer);
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+ /*
+ * Initialize ethernet HW addr prior to starting Linux,
+ * needed for nfsroot
+ */
+ eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01);
+#endif
+ return rc;
+}
+
+#ifdef CONFIG_SOFT_I2C
+void i2c_init_board(void)
+{
+ u32 pin;
+
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+ u8 sda = (1<<4);
+ u8 scl = (1<<5);
+
+ writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
+ pin = sda | scl;
+ writel(pin, &pio->piob.idr); /* Disable Interupt */
+ writel(pin, &pio->piob.pudr);
+ writel(pin, &pio->piob.per);
+ writel(pin, &pio->piob.oer);
+ writel(pin, &pio->piob.sodr);
+}
+#endif
+
+void watchdog_reset(void)
+{
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+ u32 pin = 0x1; /* PA0 */
+
+ if ((readl(&pio->pioa.odsr) & pin) > 0)
+ writel(pin, &pio->pioa.codr);
+ else
+ writel(pin, &pio->pioa.sodr);
+}
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
+
+/*---------------------------------------------------------------------------*/
+
+int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rcode = 1;
+ int row;
+ int col;
+ u32 pinz;
+ u32 pins;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+
+ at91_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LCD DIM */
+
+ pins = 0x1F000000;
+ writel(pins, &pio->pioa.idr);
+ writel(pins, &pio->pioa.pudr);
+ writel(pins, &pio->pioa.per);
+ writel(pins, &pio->pioa.oer);
+ writel(pins, &pio->pioa.sodr);
+
+ pinz = 0x1F000000;
+ writel(pinz, &pio->piob.idr);
+ writel(pinz, &pio->piob.pudr);
+ writel(pinz, &pio->piob.per);
+ writel(pinz, &pio->piob.oer);
+ writel(pinz, &pio->piob.sodr);
+
+ for (row = 0; row < 5; row++) {
+ for (col = 0; col < 5; col++) {
+ writel((0x01000000 << col), &pio->piob.sodr);
+ writel((0x01000000 << row), &pio->pioa.codr);
+ printf("LED Test %d x %d\n", row, col);
+ udelay(1000000);
+ writel(pinz, &pio->piob.codr);
+ writel(pins, &pio->pioa.sodr);
+ }
+ }
+ return rcode;
+}
+
+void poweroff(void)
+{
+ watchdog_reset();
+ at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */
+ udelay(100);
+ at91_set_pio_output(AT91_PIO_PORTA, 12, 0); /* CAN_STB -> L */
+ udelay(100);
+ at91_set_pio_output(AT91_PIO_PORTA, 11, 0); /* CAN_EN -> L */
+ udelay(100);
+ while (1)
+ watchdog_reset();
+}
+
+int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rcode = 1;
+ poweroff();
+ return rcode;
+}
+
+int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i;
+ u32 freq;
+ u32 durate;
+ int rcode = 1;
+
+ freq = 1000;
+ durate = 2;
+ switch (argc) {
+ case 3:
+ durate = simple_strtoul(argv[2], NULL, 10);
+ case 2:
+ freq = simple_strtoul(argv[1], NULL, 10);
+ case 1:
+ break;
+ default:
+ cmd_usage(cmdtp);
+ rcode = 1;
+ break;
+ }
+ durate = durate * freq;
+ freq = 500000 / freq;
+ for (i = 0; i < durate; i++) {
+ at91_set_pio_output(AT91_PIO_PORTB, 29, 1); /* Sound On*/
+ udelay(freq);
+ at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/
+ udelay(freq);
+ }
+ at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/
+ return rcode;
+}
+
+int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rcode = 1;
+ int row;
+ u32 col;
+ u32 pinz;
+ u32 pins;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ writel((1 << ATMEL_ID_PIOA), &pmc->pcer);
+
+ pins = 0x001F0000;
+ writel(pins, &pio->pioa.idr);
+ writel(pins, &pio->pioa.pudr);
+ writel(pins, &pio->pioa.per);
+ writel(pins, &pio->pioa.odr);
+
+ pinz = 0x000F0000;
+ writel(pinz, &pio->piob.idr);
+ writel(pinz, &pio->piob.pudr);
+ writel(pinz, &pio->piob.per);
+ writel(pinz, &pio->piob.oer);
+ writel(pinz, &pio->piob.codr);
+
+ while (1) {
+ col = 0;
+ for (row = 0; row < 4; row++) {
+ writel((0x00010000 << row), &pio->piob.sodr);
+ udelay(10000);
+ col <<= 4;
+ col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ;
+ writel(pinz, &pio->piob.codr);
+ }
+ printf("Matix: ");
+ for (row = 0; row < 16; row++) {
+ printf("%1.1d", col & 1);
+ col >>= 1;
+ }
+ printf(" SP %d\r ",
+ 1 ^ (1 & (readl(&pio->piob.pdsr) >> 20)));
+ if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) {
+ /* SHUTDOWN */
+ row = 0;
+ while (row < 1000) {
+ if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0)
+ row++;
+ udelay(100);
+ }
+ udelay(100000);
+ row = 0;
+ while (row < 1000) {
+ if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) {
+ row++;
+ udelay(1000);
+ }
+ }
+ poweroff();
+ while (1)
+ ;
+ }
+ }
+ return rcode;
+}
+
+/*****************************************************************************/
+
+U_BOOT_CMD(
+ ledtest, 1, 0, do_ledtest,
+ "test ledmatrix",
+ "\n"
+ );
+
+U_BOOT_CMD(
+ keytest, 1, 0, do_keytest,
+ "test keymatix and special keys, poweroff on pressing ON key",
+ "\n"
+ );
+
+U_BOOT_CMD(
+ poweroff, 1, 0, do_poweroff,
+ "power off",
+ "\n"
+ );
+
+U_BOOT_CMD(
+ beep, 3, 0, do_beep,
+ "[freq [duration]]",
+ "freq frequence of beep\nduration duration of beep\n"
+ );
+
+/*****************************************************************************/
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-void mv_phy_88e1116_init(const char *name)
+void mv_phy_88e1116_init(const char *name, u16 phyaddr)
{
u16 reg;
- u16 devadr;
if (miiphy_set_current_dev(name))
return;
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..(%s) could not read PHY dev address\n", __func__);
- return;
- }
-
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
- /* reset the phy */
- miiphy_reset(name, devadr);
+ miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
- printf("88E1116 Initialized on %s\n", name);
+ if (miiphy_reset(name, phyaddr) == 0)
+ printf("88E1116 Initialized on %s\n", name);
}
#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
#define _LACIE_COMMON_H
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
-void mv_phy_88e1116_init(const char *name);
+void mv_phy_88e1116_init(const char *name, u16 phyaddr);
#endif
#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
int lacie_read_mac_address(uchar *mac);
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
{
- mv_phy_88e1116_init("egiga0");
+ mv_phy_88e1116_init("egiga0", 8);
}
#endif /* CONFIG_RESET_PHY_R */
0
};
- kirkwood_mpp_conf(kwmpp_config);
+ kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
/* Configure and initialize PHY */
void reset_phy(void)
{
- mv_phy_88e1116_init("egiga0");
+ mv_phy_88e1116_init("egiga0", 8);
}
#endif
MPP33_GPIO, /* Fan speed (bit 2) */
0
};
- kirkwood_mpp_conf(kwmpp_config);
+ kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
/* Configure and initialize PHY */
void reset_phy(void)
{
- mv_phy_88e1116_init("egiga0");
+ mv_phy_88e1116_init("egiga0", 8);
}
#endif
MPP49_GPIO, /* Wifi AP LED */
0
};
- kirkwood_mpp_conf(kwmpp_config);
+ kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
MPP49_GPIO, /* B_GLED */
0
};
- kirkwood_mpp_conf(kwmpp_config);
+ kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
MPP49_GPIO,
0
};
- kirkwood_mpp_conf(kwmpp_config);
+ kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
0
};
- kirkwood_mpp_conf(kwmpp_config);
+ kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
MPP49_GPIO,
0
};
- kirkwood_mpp_conf(kwmpp_config);
+ kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
MPP49_GPIO,
0
};
- kirkwood_mpp_conf(kwmpp_config);
+ kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
MPP49_GPIO,
0
};
- kirkwood_mpp_conf(kwmpp_config);
+ kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
- {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
- {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
- {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
+ {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+ {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
};
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
- {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
- {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
- {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
+ {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+ {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
};
(1 << ATMEL_ID_PIOCDE),
&pmc->pcer);
+ at91_seriald_hw_init();
return 0;
}
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- at91_seriald_hw_init();
#ifdef CONFIG_CMD_NAND
at91sam9263ek_nand_hw_init();
#endif
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
- {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
- {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
- {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
+ {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+ {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
};
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
- {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
- {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
- {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
+ {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+ {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
};
#
-# (C) Copyright 2009
-# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
+# Copyright (c) 2012 Michael Walle
+# Michael Walle <michael@walle.cc>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
#
-#########################################################################
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := lsxl.o
-CONFIG_SYS_TEXT_BASE = 0x00700000
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-ALL-y += $(obj)u-boot.img
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-# Environment variables in NAND
-ifeq ($(ENV),NAND)
-PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
-else
-PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
-endif
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-# Support parallel flash
-ifeq ($(FLASH),PNOR)
-PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR
-endif
+sinclude $(obj).depend
-ifeq ($(CONSOLE),USB)
-PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
-endif
+#########################################################################
--- /dev/null
+#
+# Copyright (c) 2012 Michael Walle
+# Michael Walle <michael@walle.cc>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100E0 0x1B1B1B9B
+
+# L2 RAM Timing 0
+DATA 0xFFD20134 0xBBBBBBBB
+# not further specified in HW manual, timing taken from original vendor port
+
+# L2 RAM Timing 1
+DATA 0xFFD20138 0x00BBBBBB
+# not further specified in HW manual, timing taken from original vendor port
+
+# DDR Configuration register
+DATA 0xFFD01400 0x43000618
+# bit13-0: 0x618, 1560 DDR2 clks refresh rate
+# bit23-14: 0 required
+# bit24: 1, enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: 0 required
+# bit31-30: 0b01 required
+
+# DDR Controller Control Low
+DATA 0xFFD01404 0x39543000
+# bit3-0: 0 required
+# bit4: 0, addr/cmd in same cycle
+# bit5: 0, clk is driven during self refresh, we don't care for APX
+# bit6: 0, use recommended falling edge of clk for addr/cmd
+# bit11-7: 0 required
+# bit12: 1 required
+# bit13: 1 required
+# bit14: 0, input buffer always powered up
+# bit17-15: 0 required
+# bit18: 1, cpu lock transaction enabled
+# bit19: 0 required
+# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0, no additional STARTBURST delay
+
+# DDR Timing (Low)
+DATA 0xFFD01408 0x3302444F
+# bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0])
+# bit7-4: 4, 5 cycle tRCD
+# bit11-8: 4, 5 cyle tRP
+# bit15-12: 4, 5 cyle tWR
+# bit19-16: 2, 3 cyle tWTR
+# bit20: 0, 16 cycle tRAS (tRAS[4])
+# bit23-21: 0 required
+# bit27-24: 3, 4 cycle tRRD
+# bit31-28: 3, 4 cyle tRTP
+
+# DDR Timing (High)
+DATA 0xFFD0140C 0x00000823
+# bit6-0: 0x23, 35 cycle tRFC
+# bit8-7: 0, 1 cycle tR2R
+# bit10-9: 0, 1 cyle tR2W
+# bit12-11: 1, 2 cylce tW2W
+# bit31-13: 0 required
+
+# DDR Address Control
+DATA 0xFFD01410 0x00000009
+# bit1-0: 1, Cs0width=x16
+# bit3-2: 2, Cs0size=512Mbit
+# bit5-4: 0, Cs1width=nonexistent
+# bit7-6: 0, Cs1size=nonexistent
+# bit9-8: 0, Cs2width=nonexistent
+# bit11-10: 0, Cs2size=nonexistent
+# bit13-12: 0, Cs3width=nonexistent
+# bit15-14: 0, Cs3size=nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+# DDR Open Pages Control
+DATA 0xFFD01414 0x00000000
+# bit0: 0, OPEn=OpenPage enabled
+# bit31-1: 0 required
+
+# DDR Operation
+DATA 0xFFD01418 0x00000000
+# bit3-0: 0, Cmd=Normal SDRAM Mode
+# bit31-4: 0 required
+
+# DDR Mode
+DATA 0xFFD0141C 0x00000652
+# bit2-0: 2, Burst Length (2 required)
+# bit3: 0, Burst Type (0 required)
+# bit6-4: 5, CAS Latency (CL) 5
+# bit7: 0, (Test Mode) Normal operation
+# bit8: 0, (Reset DLL) Normal operation
+# bit11-9: 3, Write recovery for auto-precharge (3 required)
+# bit12: 0, Fast Active power down exit time (0 required)
+# bit31-13: 0 required
+
+# DDR Extended Mode
+DATA 0xFFD01420 0x00000042
+# bit0: 0, DRAM DLL enabled
+# bit1: 1, DRAM drive strength reduced
+# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
+# bit5-3: 0 required
+# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
+# bit9-7: 0 required
+# bit10: 0, differential DQS enabled
+# bit11: 0 required
+# bit12: 0, DRAM output buffer enabled
+# bit31-13: 0 required
+
+# DDR Controller Control High
+DATA 0xFFD01424 0x0000F17F
+# bit2-0: 0x7 required
+# bit3: 1, MBUS Burst Chop disabled
+# bit6-4: 0x7 required
+# bit7: 0 required (???)
+# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9: 0, no half clock cycle addition to dataout
+# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11: 0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf required
+# bit31-16: 0 required
+
+# DDR2 ODT Read Timing (default values)
+DATA 0xFFD01428 0x00085520
+# bit3-0: 0 required
+# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
+# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
+# bit31-20: 0 required
+
+# DDR2 ODT Write Timing (default values)
+DATA 0xFFD0147C 0x00008552
+# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
+# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
+# bit31-16: 0 required
+
+# CS[0]n Base address
+DATA 0xFFD01500 0x00000000
+# at 0x0
+
+# CS[0]n Size
+DATA 0xFFD01504 0x03FFFFF1
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 0x0, CS0 hit selected
+# bit23-4: 0xfffff required
+# bit31-24: 0x03, Size (i.e. 64MB)
+
+# CS[1]n Size
+DATA 0xFFD0150C 0x00000000
+# window disabled
+
+# CS[2]n Size
+DATA 0xFFD01514 0x00000000
+# window disabled
+
+# CS[3]n Size
+DATA 0xFFD0151C 0x00000000
+# window disabled
+
+# DDR ODT Control (Low)
+DATA 0xFFD01494 0x003C0000
+# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
+# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
+# bit15-8: 0 required
+# bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
+# bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1
+# bit31-24: 0 required
+
+# DDR ODT Control (High)
+DATA 0xFFD01498 0x00000000
+# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
+# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
+# bit31-4 0 required
+
+# CPU ODT Control
+DATA 0xFFD0149C 0x0000E80F
+# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
+# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
+# bit9-8: 0, Internal ODT assertion is controlled by fiels
+# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
+# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
+# bit14: 1, M_STARTBURST_IN ODT enabled
+# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
+# bit20-16: 0, Pad N channel driving strength for ODT
+# bit25-21: 0, Pad P channel driving strength for ODT
+# bit31-26: 0 required
+
+# DDR Initialization Control
+DATA 0xFFD01480 0x00000001
+# bit0: 1, enable DDR init upon this register write
+# bit31-1: 0, required
+
+# End of Header extension
+DATA 0x0 0x0
--- /dev/null
+#
+# Copyright (c) 2012 Michael Walle
+# Michael Walle <michael@walle.cc>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100E0 0x1B1B9B9B
+
+# L2 RAM Timing 0
+DATA 0xFFD20134 0xBBBBBBBB
+# not further specified in HW manual, timing taken from original vendor port
+
+# L2 RAM Timing 1
+DATA 0xFFD20138 0x00BBBBBB
+# not further specified in HW manual, timing taken from original vendor port
+
+# DDR Configuration register
+DATA 0xFFD01400 0x43000618
+# bit13-0: 0x618, 1560 DDR2 clks refresh rate
+# bit23-14: 0 required
+# bit24: 1, enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: 0 required
+# bit31-30: 0b01 required
+
+# DDR Controller Control Low
+DATA 0xFFD01404 0x39543010
+# bit3-0: 0 required
+# bit4: 1, T2 mode, addr/cmd are driven for two cycles
+# bit5: 0, clk is driven during self refresh, we don't care for APX
+# bit6: 0, use recommended falling edge of clk for addr/cmd
+# bit11-7: 0 required
+# bit12: 1 required
+# bit13: 1 required
+# bit14: 0, input buffer always powered up
+# bit17-15: 0 required
+# bit18: 1, cpu lock transaction enabled
+# bit19: 0 required
+# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0, no additional STARTBURST delay
+
+# DDR Timing (Low)
+DATA 0xFFD01408 0x22125441
+# bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0])
+# bit7-4: 4, 5 cycle tRCD
+# bit11-8: 4, 5 cyle tRP
+# bit15-12: 5, 6 cyle tWR
+# bit19-16: 2, 3 cyle tWTR
+# bit20: 1, 18 cycle tRAS (tRAS[4])
+# bit23-21: 0 required
+# bit27-24: 2, 3 cycle tRRD
+# bit31-28: 2, 3 cyle tRTP
+
+# DDR Timing (High)
+DATA 0xFFD0140C 0x00000832
+# bit6-0: 0x32, 50 cycle tRFC
+# bit8-7: 0, 1 cycle tR2R
+# bit10-9: 0, 1 cyle tR2W
+# bit12-11: 1, 2 cylce tW2W
+# bit31-13: 0 required
+
+# DDR Address Control
+DATA 0xFFD01410 0x0000000C
+# bit1-0: 0, Cs0width=x8
+# bit3-2: 3, Cs0size=1Gbit
+# bit5-4: 0, Cs1width=nonexistent
+# bit7-6: 0, Cs1size=nonexistent
+# bit9-8: 0, Cs2width=nonexistent
+# bit11-10: 0, Cs2size=nonexistent
+# bit13-12: 0, Cs3width=nonexistent
+# bit15-14: 0, Cs3size=nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+# DDR Open Pages Control
+DATA 0xFFD01414 0x00000000
+# bit0: 0, OPEn=OpenPage enabled
+# bit31-1: 0 required
+
+# DDR Operation
+DATA 0xFFD01418 0x00000000
+# bit3-0: 0, Cmd=Normal SDRAM Mode
+# bit31-4: 0 required
+
+# DDR Mode
+DATA 0xFFD0141C 0x00000652
+# bit2-0: 2, Burst Length (2 required)
+# bit3: 0, Burst Type (0 required)
+# bit6-4: 5, CAS Latency (CL) 5
+# bit7: 0, (Test Mode) Normal operation
+# bit8: 0, (Reset DLL) Normal operation
+# bit11-9: 3, Write recovery for auto-precharge (3 required)
+# bit12: 0, Fast Active power down exit time (0 required)
+# bit31-13: 0 required
+
+# DDR Extended Mode
+DATA 0xFFD01420 0x00000006
+# bit0: 0, DRAM DLL enabled
+# bit1: 1, DRAM drive strength reduced
+# bit2: 1, ODT control Rtt[0] (Rtt=1, 75 ohm termination)
+# bit5-3: 0 required
+# bit6: 0, ODT control Rtt[1] (Rtt=1, 75 ohm termination)
+# bit9-7: 0 required
+# bit10: 0, differential DQS enabled
+# bit11: 0 required
+# bit12: 0, DRAM output buffer enabled
+# bit31-13: 0 required
+
+# DDR Controller Control High
+DATA 0xFFD01424 0x0000F17F
+# bit2-0: 0x7 required
+# bit3: 1, MBUS Burst Chop disabled
+# bit6-4: 0x7 required
+# bit7: 0 required (???)
+# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9: 0, no half clock cycle addition to dataout
+# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11: 0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf required
+# bit31-16: 0 required
+
+# DDR2 ODT Read Timing (default values)
+DATA 0xFFD01428 0x00085520
+# bit3-0: 0 required
+# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
+# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
+# bit31-20: 0 required
+
+# DDR2 ODT Write Timing (default values)
+DATA 0xFFD0147C 0x00008552
+# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
+# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
+# bit31-16: 0 required
+
+# CS[0]n Base address
+DATA 0xFFD01500 0x00000000
+# at 0x0
+
+# CS[0]n Size
+DATA 0xFFD01504 0x0FFFFFF1
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 0x0, CS0 hit selected
+# bit23-4: 0xfffff required
+# bit31-24: 0x0f, Size (i.e. 256MB)
+
+# CS[1]n Size
+DATA 0xFFD0150C 0x00000000
+# window disabled
+
+# CS[2]n Size
+DATA 0xFFD01514 0x00000000
+# window disabled
+
+# CS[3]n Size
+DATA 0xFFD0151C 0x00000000
+# window disabled
+
+# DDR ODT Control (Low)
+DATA 0xFFD01494 0x00010000
+# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
+# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
+# bit15-8: 0 required
+# bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
+# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
+# bit31-24: 0 required
+
+# DDR ODT Control (High)
+DATA 0xFFD01498 0x00000000
+# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
+# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
+# bit31-4 0 required
+
+# CPU ODT Control
+DATA 0xFFD0149C 0x0000E80F
+# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
+# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
+# bit9-8: 0, Internal ODT assertion is controlled by fiels
+# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
+# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
+# bit14: 1, M_STARTBURST_IN ODT enabled
+# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
+# bit20-16: 0, Pad N channel driving strength for ODT
+# bit25-21: 0, Pad P channel driving strength for ODT
+# bit31-26: 0 required
+
+# DDR Initialization Control
+DATA 0xFFD01480 0x00000001
+# bit0: 1, enable DDR init upon this register write
+# bit31-1: 0, required
+
+# End of Header extension
+DATA 0x0 0x0
--- /dev/null
+/*
+ * Copyright (c) 2012 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * Based on sheevaplug/sheevaplug.c by
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+#include <spi_flash.h>
+
+#include "lsxl.h"
+
+/*
+ * Rescue mode
+ *
+ * Selected by holding the push button for 3 seconds, while powering on
+ * the device.
+ *
+ * These linkstations don't have a (populated) serial port. There is no
+ * way to access an (unmodified) board other than using the netconsole. If
+ * you want to recover from a bad environment setting or an empty environment,
+ * you can do this only with a working network connection. Therefore, a random
+ * ethernet address is generated if none is set and a DHCP request is sent.
+ * After a successful DHCP response is received, the network settings are
+ * configured and the ncip parameter is set to the serverip. Eg. for a working
+ * resuce mode, you should set 'next-server' to the host where the netconsole
+ * client is started.
+ * Additionally, the bootsource is set to 'rescue'.
+ */
+
+#ifndef CONFIG_ENV_OVERWRITE
+# error "You need to set CONFIG_ENV_OVERWRITE"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ kw_config_gpio(LSXL_OE_VAL_LOW,
+ LSXL_OE_VAL_HIGH,
+ LSXL_OE_LOW, LSXL_OE_HIGH);
+
+ /*
+ * Multi-Purpose Pins Functionality configuration
+ * These strappings are taken from the original vendor uboot port.
+ */
+ u32 kwmpp_config[] = {
+ MPP0_SPI_SCn,
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP4_UART0_RXD,
+ MPP5_UART0_TXD,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_GPIO,
+ MPP9_GPIO,
+ MPP10_GPO, /* HDD power */
+ MPP11_GPIO, /* USB Vbus enable */
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_GPO, /* fan speed high */
+ MPP19_GPO, /* fan speed low */
+ MPP20_GE1_0,
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO, /* function LED */
+ MPP37_GPIO, /* alarm LED */
+ MPP38_GPIO, /* info LED */
+ MPP39_GPIO, /* power LED */
+ MPP40_GPIO, /* fan alarm */
+ MPP41_GPIO, /* funtion button */
+ MPP42_GPIO, /* power switch */
+ MPP43_GPIO, /* power auto switch */
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO, /* function red LED */
+ MPP49_GPIO,
+ 0
+ };
+
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+
+ return 0;
+}
+
+#define LED_OFF 0
+#define LED_ALARM_ON 1
+#define LED_ALARM_BLINKING 2
+#define LED_POWER_ON 3
+#define LED_POWER_BLINKING 4
+#define LED_INFO_ON 5
+#define LED_INFO_BLINKING 6
+
+static void __set_led(int blink_alarm, int blink_info, int blink_power,
+ int value_alarm, int value_info, int value_power)
+{
+ kw_gpio_set_blink(GPIO_ALARM_LED, blink_alarm);
+ kw_gpio_set_blink(GPIO_INFO_LED, blink_info);
+ kw_gpio_set_blink(GPIO_POWER_LED, blink_power);
+ kw_gpio_set_value(GPIO_ALARM_LED, value_alarm);
+ kw_gpio_set_value(GPIO_INFO_LED, value_info);
+ kw_gpio_set_value(GPIO_POWER_LED, value_power);
+}
+
+static void set_led(int state)
+{
+ switch (state) {
+ case LED_OFF:
+ __set_led(0, 0, 0, 0, 0, 0);
+ break;
+ case LED_ALARM_ON:
+ __set_led(0, 0, 0, 0, 1, 1);
+ break;
+ case LED_ALARM_BLINKING:
+ __set_led(1, 0, 0, 1, 1, 1);
+ break;
+ case LED_INFO_ON:
+ __set_led(0, 0, 0, 1, 0, 1);
+ break;
+ case LED_INFO_BLINKING:
+ __set_led(0, 1, 0, 1, 1, 1);
+ break;
+ case LED_POWER_ON:
+ __set_led(0, 0, 0, 1, 1, 0);
+ break;
+ case LED_POWER_BLINKING:
+ __set_led(0, 0, 1, 1, 1, 1);
+ break;
+ }
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+ set_led(LED_POWER_BLINKING);
+
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+void check_enetaddr(void)
+{
+ uchar enetaddr[6];
+
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ /* signal unset/invalid ethaddr to user */
+ set_led(LED_INFO_BLINKING);
+ }
+}
+
+static void erase_environment(void)
+{
+ struct spi_flash *flash;
+
+ printf("Erasing environment..\n");
+ flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (!flash) {
+ printf("Erasing flash failed\n");
+ return;
+ }
+
+ spi_flash_erase(flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE);
+ spi_flash_free(flash);
+ do_reset(NULL, 0, 0, NULL);
+}
+
+static void rescue_mode(void)
+{
+ uchar enetaddr[6];
+
+ printf("Entering rescue mode..\n");
+#ifdef CONFIG_RANDOM_MACADDR
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ eth_random_enetaddr(enetaddr);
+ if (eth_setenv_enetaddr("ethaddr", enetaddr)) {
+ printf("Failed to set ethernet address\n");
+ set_led(LED_ALARM_BLINKING);
+ return;
+ }
+ }
+#endif
+ setenv("bootsource", "rescue");
+}
+
+static void check_push_button(void)
+{
+ int i = 0;
+
+ while (!kw_gpio_get_value(GPIO_FUNC_BUTTON)) {
+ udelay(100000);
+ i++;
+
+ if (i == 10)
+ set_led(LED_INFO_ON);
+
+ if (i >= 100) {
+ set_led(LED_INFO_BLINKING);
+ break;
+ }
+ }
+
+ if (i >= 100)
+ erase_environment();
+ else if (i >= 10)
+ rescue_mode();
+}
+
+int misc_init_r(void)
+{
+ check_enetaddr();
+ check_push_button();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int progress)
+{
+ if (progress > 0)
+ return;
+
+ /* this is not an error, eg. bootp with autoload=no will trigger this */
+ if (progress == -BOOTSTAGE_ID_NET_LOADED)
+ return;
+
+ set_led(LED_ALARM_BLINKING);
+}
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2012 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __LSXL_H
+#define __LSXL_H
+
+#define GPIO_HDD_POWER 10
+#define GPIO_USB_VBUS 11
+#define GPIO_FAN_HIGH 18
+#define GPIO_FAN_LOW 19
+#define GPIO_FUNC_LED 36
+#define GPIO_ALARM_LED 37
+#define GPIO_INFO_LED 38
+#define GPIO_POWER_LED 39
+#define GPIO_FAN_LOCK 40
+#define GPIO_FUNC_BUTTON 41
+#define GPIO_POWER_SWITCH 42
+#define GPIO_POWER_AUTO_SWITCH 43
+#define GPIO_FUNC_RED_LED 48
+
+#define _BIT(x) (1<<(x))
+
+#define LSXL_OE_LOW (~(_BIT(GPIO_HDD_POWER) \
+ | _BIT(GPIO_USB_VBUS) \
+ | _BIT(GPIO_FAN_HIGH) \
+ | _BIT(GPIO_FAN_LOW)))
+
+#define LSXL_OE_HIGH (~(_BIT(GPIO_FUNC_LED - 32) \
+ | _BIT(GPIO_ALARM_LED - 32) \
+ | _BIT(GPIO_INFO_LED - 32) \
+ | _BIT(GPIO_POWER_LED - 32) \
+ | _BIT(GPIO_FUNC_RED_LED - 32)))
+
+#define LSXL_OE_VAL_LOW (_BIT(GPIO_HDD_POWER) \
+ | _BIT(GPIO_USB_VBUS))
+
+#define LSXL_OE_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \
+ | _BIT(GPIO_ALARM_LED - 32) \
+ | _BIT(GPIO_INFO_LED - 32) \
+ | _BIT(GPIO_POWER_LED - 32) \
+ | _BIT(GPIO_FUNC_RED_LED - 32))
+
+#define LSXL_POL_VAL_LOW (_BIT(GPIO_FAN_HIGH) \
+ | _BIT(GPIO_FAN_LOW))
+
+#define LSXL_POL_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \
+ | _BIT(GPIO_ALARM_LED - 32) \
+ | _BIT(GPIO_INFO_LED - 32) \
+ | _BIT(GPIO_POWER_LED - 32) \
+ | _BIT(GPIO_FUNC_BUTTON - 32) \
+ | _BIT(GPIO_POWER_SWITCH - 32) \
+ | _BIT(GPIO_POWER_AUTO_SWITCH - 32) \
+ | _BIT(GPIO_FUNC_RED_LED - 32))
+
+#endif /* __LSXL_H */
MPP49_GPIO, /* LED orange */
0
};
- kirkwood_mpp_conf(kwmpp_config);
+ kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
return 0;
}
+static u32 cm_t3x_rev;
+
+/*
+ * Routine: get_board_rev
+ * Description: read system revision
+ */
+u32 get_board_rev(void)
+{
+ if (!cm_t3x_rev)
+ cm_t3x_rev = cm_t3x_eeprom_get_board_rev();
+
+ return cm_t3x_rev;
+};
+
+/*
+ * Routine: misc_init_r
+ * Description: display die ID
+ */
+int misc_init_r(void)
+{
+ u32 board_rev = get_board_rev();
+ u32 rev_major = board_rev / 100;
+ u32 rev_minor = board_rev - (rev_major * 100);
+
+ if ((rev_minor / 10) * 10 == rev_minor)
+ rev_minor = rev_minor / 10;
+
+ printf("PCB: %u.%u\n", rev_major, rev_minor);
+ dieid_num_r();
+
+ return 0;
+}
+
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
#define BOARD_SERIAL_OFFSET_LEGACY 8
#define BOARD_REV_OFFSET 0
#define BOARD_REV_OFFSET_LEGACY 6
-#define BOARD_REV_SIZE 4
-#define BOARD_REV_SIZE_LEGACY 2
+#define BOARD_REV_SIZE 2
#define MAC_ADDR_OFFSET 4
#define MAC_ADDR_OFFSET_LEGACY 0
}
/*
- * Routine: get_board_rev
- * Description: read system revision
+ * Routine: cm_t3x_eeprom_get_board_rev
+ * Description: read system revision from eeprom
*/
-u32 get_board_rev(void)
+u32 cm_t3x_eeprom_get_board_rev(void)
{
u32 rev = 0;
+ char str[5]; /* Legacy representation can contain at most 4 digits */
uint offset = BOARD_REV_OFFSET_LEGACY;
- int len = BOARD_REV_SIZE_LEGACY;
if (eeprom_setup_layout())
return 0;
- if (eeprom_layout != LAYOUT_LEGACY) {
+ if (eeprom_layout != LAYOUT_LEGACY)
offset = BOARD_REV_OFFSET;
- len = BOARD_REV_SIZE;
- }
- if (cm_t3x_eeprom_read(offset, (uchar *)&rev, len))
+ if (cm_t3x_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE))
return 0;
+ /*
+ * Convert legacy syntactic representation to semantic
+ * representation. i.e. for rev 1.00: 0x100 --> 0x64
+ */
+ if (eeprom_layout == LAYOUT_LEGACY) {
+ sprintf(str, "%x", rev);
+ rev = simple_strtoul(str, NULL, 10);
+ }
+
return rev;
};
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
int cm_t3x_eeprom_read_mac_addr(uchar *buf);
+u32 cm_t3x_eeprom_get_board_rev(void);
#else
static inline int cm_t3x_eeprom_read_mac_addr(uchar *buf)
{
return 1;
}
+static inline u32 cm_t3x_eeprom_get_board_rev(void)
+{
+ return 0;
+}
#endif
#endif
--- /dev/null
+/dts-v1/;
+
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "Toshiba AC100 / Dynabook AZ";
+ compatible = "compal,paz00", "nvidia,tegra20";
+
+ aliases {
+ usb0 = "/usb@c5008000";
+ };
+
+ memory {
+ reg = <0x00000000 0x20000000>;
+ };
+
+ clocks {
+ clk_32k: clk_32k {
+ clock-frequency = <32000>;
+ };
+ osc {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ clock@60006000 {
+ clocks = <&clk_32k &osc>;
+ };
+
+ serial@70006000 {
+ clock-frequency = < 216000000 >;
+ };
+
+ i2c@7000c000 {
+ status = "disabled";
+ };
+
+ i2c@7000c400 {
+ status = "disabled";
+ };
+
+ i2c@7000c500 {
+ status = "disabled";
+ };
+
+ i2c@7000d000 {
+ status = "disabled";
+ };
+
+ usb@c5000000 {
+ status = "disabled";
+ };
+
+ usb@c5004000 {
+ status = "disabled";
+ };
+};
pinmux_tristate_disable(PINGRP_GMA);
pinmux_tristate_disable(PINGRP_GME);
- /* SDMMC1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */
- pinmux_set_func(PINGRP_SDMMC1, PMUX_FUNC_SDIO1);
+ /* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */
+ pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1);
- pinmux_tristate_disable(PINGRP_SDMMC1);
+ pinmux_tristate_disable(PINGRP_SDIO1);
/* For power GPIO PV1 */
pinmux_tristate_disable(PINGRP_UAC);
- /* For CD GPIO PI5 */
- pinmux_tristate_disable(PINGRP_ATC);
+ /* For CD GPIO PV5 */
+ pinmux_tristate_disable(PINGRP_GPV);
}
/* this is a weak define that we are overriding */
debug("board_mmc_init: init SD slot\n");
/* init dev 3, SD slot, with 4-bit bus */
- tegra2_mmc_init(3, 4, GPIO_PV1, GPIO_PI5);
+ tegra2_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
return 0;
}
--- /dev/null
+/dts-v1/;
+
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "Compulab TrimSlice board";
+ compatible = "compulab,trimslice", "nvidia,tegra20";
+
+ aliases {
+ usb0 = "/usb@c5008000";
+ };
+
+ memory {
+ reg = <0x00000000 0x40000000>;
+ };
+
+ clocks {
+ clk_32k: clk_32k {
+ clock-frequency = <32000>;
+ };
+ osc {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ clock@60006000 {
+ clocks = <&clk_32k &osc>;
+ };
+
+ serial@70006000 {
+ clock-frequency = <216000000>;
+ };
+
+ i2c@7000c000 {
+ status = "disabled";
+ };
+
+ i2c@7000c400 {
+ status = "disabled";
+ };
+
+ i2c@7000c500 {
+ status = "disabled";
+ };
+
+ i2c@7000d000 {
+ status = "disabled";
+ };
+
+ usb@c5000000 {
+ status = "disabled";
+ };
+
+ usb@c5004000 {
+ status = "disabled";
+ };
+};
--- /dev/null
+#
+# (C) Copyright 2010-2012
+# NVIDIA Corporation <www.nvidia.com>
+#
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../../nvidia/common)
+endif
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+COBJS += ../../nvidia/common/board.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/mmc.h>
+#include <asm/gpio.h>
+#ifdef CONFIG_TEGRA2_MMC
+#include <mmc.h>
+#endif
+
+/*
+ * Routine: gpio_config_uart
+ * Description: Does nothing on TrimSlice - no UART-related GPIOs.
+ */
+void gpio_config_uart(void)
+{
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+static void pin_mux_mmc(void)
+{
+ funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT);
+ funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
+
+ /* For CD GPIO PP1 */
+ pinmux_tristate_disable(PINGRP_DAP3);
+}
+
+/* this is a weak define that we are overriding */
+int board_mmc_init(bd_t *bd)
+{
+ debug("board_mmc_init called\n");
+
+ /* Enable muxes, etc. for SDMMC controllers */
+ pin_mux_mmc();
+
+ /* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */
+ tegra2_mmc_init(0, 4, -1, GPIO_PP1);
+
+ /* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */
+ tegra2_mmc_init(3, 4, -1, -1);
+
+ return 0;
+}
MPP49_GPIO, /* thermal sensor */
0
};
- kirkwood_mpp_conf(kwmpp_config);
+ kirkwood_mpp_conf(kwmpp_config, NULL);
kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
COBJS += efikamx-usb.o
endif
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#include <mmc.h>
#include <net.h>
#include <netdev.h>
+#include <spi.h>
+#include <linux/ctype.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/da850_lowlevel.h>
{ pinmux(5), 1, 0 },
{ pinmux(5), 1, 3 },
{ pinmux(5), 1, 7 },
- { pinmux(6), 1, 0 },
- { pinmux(6), 1, 1 },
+ { pinmux(5), 1, 5 },
+ { pinmux(5), 1, 4 },
+ { pinmux(5), 1, 3 },
+ { pinmux(5), 1, 2 },
+ { pinmux(5), 1, 1 },
+ { pinmux(5), 1, 0 },
+ { pinmux(6), 8, 0 },
+ { pinmux(6), 8, 1 },
{ pinmux(6), 8, 2 },
{ pinmux(6), 8, 3 },
- { pinmux(6), 1, 4 },
+ { pinmux(6), 8, 4 },
{ pinmux(6), 8, 5 },
{ pinmux(6), 1, 7 },
{ pinmux(7), 8, 2 },
{ pinmux(7), 1, 3 },
- { pinmux(7), 1, 6 },
+ { pinmux(7), 8, 6 },
{ pinmux(7), 1, 7 },
{ pinmux(13), 8, 2 },
{ pinmux(13), 8, 3 },
unsigned char value;
};
-static const struct gpio_config enbw_gpio_config[] = {
+static const struct gpio_config enbw_gpio_config_hut[] = {
+ { "RS485 enable", 8, 11, 1, 0 },
+ { "RS485 iso", 8, 10, 1, 1 },
+ { "W2HUT RS485 Rx ena", 8, 9, 1, 0 },
+ { "W2HUT RS485 iso", 8, 8, 1, 1 },
+};
+
+static const struct gpio_config enbw_gpio_config_w[] = {
{ "RS485 enable", 8, 11, 1, 0 },
{ "RS485 iso", 8, 10, 1, 0 },
{ "W2HUT RS485 Rx ena", 8, 9, 1, 0 },
{ "W2HUT RS485 iso", 8, 8, 1, 0 },
+};
+
+static const struct gpio_config enbw_gpio_config[] = {
{ "LAN reset", 7, 15, 1, 1 },
{ "ena 11V PLC", 7, 14, 1, 0 },
{ "ena 1.5V PLC", 7, 13, 1, 0 },
{ "disable VBUS", 7, 12, 1, 1 },
- { "PLC reset", 6, 13, 1, 1 },
+ { "PLC reset", 6, 13, 1, 0 },
{ "LCM RS", 6, 12, 1, 0 },
{ "LCM R/W", 6, 11, 1, 0 },
{ "PLC pairing", 6, 10, 1, 1 },
{ "PLC MDIO CLK", 6, 9, 1, 0 },
{ "HK218", 6, 8, 1, 0 },
{ "HK218 Rx", 6, 1, 1, 1 },
- { "TPM reset", 6, 0, 1, 1 },
- { "LCM E", 2, 2, 1, 1 },
+ { "TPM reset", 6, 0, 1, 0 },
+ { "Board-Type", 3, 9, 0, 0 },
+ { "HW-ID0", 2, 7, 0, 0 },
+ { "HW-ID1", 2, 6, 0, 0 },
+ { "HW-ID2", 2, 3, 0, 0 },
{ "PV-IF RxD ena", 0, 15, 1, 1 },
{ "LED1", 1, 15, 1, 1 },
{ "LED2", 0, 1, 1, 1 },
}
}
-int board_init(void)
+static int enbw_cmc_init_gpio(const struct gpio_config *conf, int sz)
{
int i, ret;
-#ifndef CONFIG_USE_IRQ
- irq_init();
-#endif
- /* address of boot parameters, not used as booting with DTT */
- gd->bd->bi_boot_params = 0;
+ for (i = 0; i < sz; i++) {
+ int gpio = conf[i].bank * 16 +
+ conf[i].gpio;
- for (i = 0; i < ARRAY_SIZE(enbw_gpio_config); i++) {
- int gpio = enbw_gpio_config[i].bank * 16 +
- enbw_gpio_config[i].gpio;
-
- ret = gpio_request(gpio, enbw_gpio_config[i].name);
+ ret = gpio_request(gpio, conf[i].name);
if (ret) {
printf("%s: Could not get %s gpio\n", __func__,
- enbw_gpio_config[i].name);
- return -1;
+ conf[i].name);
+ return ret;
}
- if (enbw_gpio_config[i].out)
+ if (conf[i].out)
gpio_direction_output(gpio,
- enbw_gpio_config[i].value);
+ conf[i].value);
else
gpio_direction_input(gpio);
}
+ return 0;
+}
+
+int board_init(void)
+{
+ int board_type, hw_id;
+
+#ifndef CONFIG_USE_IRQ
+ irq_init();
+#endif
+ /* address of boot parameters, not used as booting with DTT */
+ gd->bd->bi_boot_params = 0;
+
+ enbw_cmc_init_gpio(enbw_gpio_config, ARRAY_SIZE(enbw_gpio_config));
+
+ /* detect HW version */
+ board_type = gpio_get_value(CONFIG_ENBW_CMC_BOARD_TYPE);
+ hw_id = gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT0) +
+ (gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT1) << 1) +
+ (gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT2) << 2);
+ printf("BOARD: CMC-%s hw id: %d\n", (board_type ? "w2" : "hut"),
+ hw_id);
+ if (board_type)
+ enbw_cmc_init_gpio(enbw_gpio_config_w,
+ ARRAY_SIZE(enbw_gpio_config_w));
+ else
+ enbw_cmc_init_gpio(enbw_gpio_config_hut,
+ ARRAY_SIZE(enbw_gpio_config_hut));
+
/* setup the SUSPSRC for ARM to control emulation suspend */
clrbits_le32(&davinci_syscfg_regs->suspsrc,
(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
}
#ifdef CONFIG_DRIVER_TI_EMAC
+
+#define KSZ_CMD_READ 0x03
+#define KSZ_CMD_WRITE 0x02
+#define KSZ_ID 0x95
+
+static int enbw_cmc_switch_read(struct spi_slave *spi, u8 reg, u8 *val)
+{
+ unsigned long flags = SPI_XFER_BEGIN;
+ int ret;
+ int cmd_len;
+ u8 cmd[2];
+
+ cmd[0] = KSZ_CMD_READ;
+ cmd[1] = reg;
+ cmd_len = 2;
+
+ ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
+ if (ret) {
+ debug("Failed to send command (%zu bytes): %d\n",
+ cmd_len, ret);
+ return -EINVAL;
+ }
+ flags |= SPI_XFER_END;
+ *val = 0;
+ cmd_len = 1;
+ ret = spi_xfer(spi, cmd_len * 8, NULL, val, flags);
+ if (ret) {
+ debug("Failed to read (%zu bytes): %d\n",
+ cmd_len, ret);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int enbw_cmc_switch_read_ident(struct spi_slave *spi)
+{
+ int ret;
+ u8 val;
+
+ ret = enbw_cmc_switch_read(spi, 0, &val);
+ if (ret) {
+ debug("Failed to read\n");
+ return -EINVAL;
+ }
+
+ if (val != KSZ_ID)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int enbw_cmc_switch_write(struct spi_slave *spi, unsigned long reg,
+ unsigned long val)
+{
+ unsigned long flags = SPI_XFER_BEGIN;
+ int ret;
+ int cmd_len;
+ u8 cmd[3];
+
+ cmd[0] = KSZ_CMD_WRITE;
+ cmd[1] = reg;
+ cmd[2] = val;
+ cmd_len = 3;
+ flags |= SPI_XFER_END;
+
+ ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
+ if (ret) {
+ debug("Failed to send command (%zu bytes): %d\n",
+ cmd_len, ret);
+ return -EINVAL;
+ }
+
+ udelay(1000);
+ ret = enbw_cmc_switch_read(spi, reg, &cmd[0]);
+ if (ret) {
+ debug("Failed to read\n");
+ return -EINVAL;
+ }
+ if (val != cmd[0])
+ debug("warning: reg: %lx va: %x soll: %lx\n",
+ reg, cmd[0], val);
+
+ return 0;
+}
+
+static int enbw_cmc_eof(unsigned char *ptr)
+{
+ if (*ptr == 0xff)
+ return 1;
+
+ return 0;
+}
+
+static char *enbw_cmc_getnewline(char *ptr)
+{
+ while (*ptr != 0x0a) {
+ ptr++;
+ if (enbw_cmc_eof((unsigned char *)ptr))
+ return NULL;
+ }
+
+ ptr++;
+ return ptr;
+}
+
+static char *enbw_cmc_getvalue(char *ptr, int *value)
+{
+ int end = 0;
+
+ *value = -EINVAL;
+
+ if (!isxdigit(*ptr))
+ end = 1;
+
+ while (end) {
+ if ((*ptr == '#') || (*ptr == ';')) {
+ ptr = enbw_cmc_getnewline(ptr);
+ return ptr;
+ }
+ if (ptr != NULL) {
+ if (isxdigit(*ptr)) {
+ end = 0;
+ } else if (*ptr == 0x0a) {
+ ptr++;
+ return ptr;
+ } else {
+ ptr++;
+ if (enbw_cmc_eof((unsigned char *)ptr))
+ return NULL;
+ }
+ } else {
+ return NULL;
+ }
+ }
+ *value = (int)simple_strtoul((const char *)ptr, &ptr, 16);
+ ptr++;
+ return ptr;
+}
+
+static int enbw_cmc_config_switch(unsigned long addr)
+{
+ struct spi_slave *spi;
+ char *ptr = (char *)addr;
+ int value, reg;
+ int ret;
+ int bus, cs, max_hz, spi_mode;
+
+ debug("configure switch with file on addr: 0x%lx\n", addr);
+
+ bus = 0;
+ cs = 0;
+ max_hz = 1000000;
+ spi_mode = 0;
+
+ spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ if (!spi) {
+ printf("Failed to set up slave\n");
+ return -EINVAL;
+ }
+
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ debug("Failed to claim SPI bus: %d\n", ret);
+ goto err_claim_bus;
+ }
+
+ ret = enbw_cmc_switch_read_ident(spi);
+ if (ret)
+ goto err_claim_bus;
+
+ ptr = (char *)addr;
+ while (ptr != NULL) {
+ ptr = enbw_cmc_getvalue(ptr, ®);
+ if (ptr != NULL) {
+ ptr = enbw_cmc_getvalue(ptr, &value);
+ if ((ptr != NULL) && (value >= 0))
+ if (enbw_cmc_switch_write(spi, reg, value))
+ goto err_read;
+ }
+ }
+ return 0;
+
+err_read:
+ spi_release_bus(spi);
+err_claim_bus:
+ spi_free_slave(spi);
+ return -EINVAL;
+}
+
+static int do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ unsigned long addr;
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+ enbw_cmc_config_switch(addr);
+
+ return 0;
+}
+
+U_BOOT_CMD(switch, 3, 1, do_switch,
+ "switch addr",
+ "[addr]"
+);
+
/*
* Initializes on-board ethernet controllers.
*/
int board_eth_init(bd_t *bis)
{
-#ifdef CONFIG_DRIVER_TI_EMAC
+ const char *s;
+ size_t len;
+
davinci_emac_mii_mode_sel(0);
-#endif /* CONFIG_DRIVER_TI_EMAC */
+
+ /* send a config file to the switch */
+ s = hwconfig_subarg("switch", "config", &len);
+ if (len) {
+ unsigned long addr = simple_strtoul(s, NULL, 16);
+
+ enbw_cmc_config_switch(addr);
+ }
if (!davinci_emac_initialize()) {
printf("Error: Ethernet init failed!\n");
}
#endif
+ulong post_word_load(void)
+{
+ struct davinci_rtc *reg =
+ (struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR;
+
+ return in_be32(®->scratch2);
+}
+
+void post_word_store(ulong value)
+{
+ struct davinci_rtc *reg =
+ (struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR;
+
+ /*
+ * write RTC kick register to enable write
+ * for RTC Scratch registers. Cratch0 and 1 are
+ * used for bootcount values.
+ */
+ writel(RTC_KICK0R_WE, ®->kick0r);
+ writel(RTC_KICK1R_WE, ®->kick1r);
+ out_be32(®->scratch2, value);
+}
+
void board_gpio_init(void)
{
struct davinci_gpio *gpio = davinci_gpio_bank01;
clrbits_le32(&gpio->out_data, 0x8000407e);
/* set LED 1 - 5 to state on */
setbits_le32(&gpio->out_data, 0x8000001e);
+
+ /*
+ * set some gpio pins to low, this is needed early,
+ * so we have no gpio Interface here
+ * gpios:
+ * 8[8] Mode PV select low
+ * 8[9] Debug Rx Enable low
+ * 8[10] Mode Select PV low
+ * 8[11] Counter Interface RS485 Rx-Enable low
+ */
+ gpio = davinci_gpio_bank8;
+ clrbits_le32(&gpio->dir, 0x00000f00);
+ clrbits_le32(&gpio->out_data, 0x0f00);
}
int board_late_init(void)
COBJS := ima3-mx53.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
};
+#define HW_DRAM_CTL29 (0x74 >> 2)
+#define CS_MAP 0xf
+#define COLUMN_SIZE 0x2
+#define ADDR_PINS 0x1
+#define APREBIT 0xa
+
+#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \
+ ADDR_PINS << 8 | APREBIT)
+
+void mx28_adjust_memory_params(uint32_t *dram_vals)
+{
+ dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
+}
+
void board_init_ll(void)
{
mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
COBJS := mx51evk.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
COBJS := mx53ard.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
COBJS := mx53evk.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
COBJS := mx53loco.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
int rev = readl(&fuse->gp[6]);
+ if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
+ rev = 0;
+
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
}
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
- setup_iomux_i2c();
- if (!power_init())
- clock_1GHz();
- print_cpuinfo();
-
setenv("stdout", "serial");
return 0;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
mxc_set_sata_internal_clock();
+ setup_iomux_i2c();
+ if (!power_init())
+ clock_1GHz();
+ print_cpuinfo();
lcd_enable();
COBJS := mx53smd.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
COBJS := mx6qarm2.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
DATA 4 0x020c4080 0x000003FF
# enable AXI cache for VDOA/VPU/IPU
-DATA 4 0x020e0010 0xF00000FF
+DATA 4 0x020e0010 0xF00000CF
# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
COBJS := mx6qsabrelite.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
DATA 4 0x020c4080 0x000003FF
# enable AXI cache for VDOA/VPU/IPU
-DATA 4 0x020e0010 0xF00000FF
+DATA 4 0x020e0010 0xF00000CF
# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
#
-# (C) Copyright 2009
-# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
+# Copyright (C) 2012 Marek Vasut <marex@denx.de>
+# on behalf of DENX Software Engineering GmbH
+#
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
#
-#########################################################################
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := tk71.o
-CONFIG_SYS_TEXT_BASE = 0x00700000
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-ALL-y += $(obj)u-boot.img
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-# Environment variables in NAND
-ifeq ($(ENV),NAND)
-PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
-else
-PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
-endif
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-ifeq ($(CONSOLE),USB)
-PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
-endif
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# adopted to TK71 by
+# Nils Faerber <nils.faerber@kernelconcepts.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x1101355b # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000034 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x00000000 # DDR Address Control
+# bit1-0: 01, Cs0width=x16
+# bit3-2: 10, Cs0size=512Mb
+# bit5-4: 01, Cs1width=x16
+# bit7-6: 10, Cs1size=512Mb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000652 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000042 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00110000 # DDR ODT Control (Low)
+# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
+# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
+# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
+# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000F80F # CPU ODT Control
+# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
+# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
+# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
+# bit14: 1, M_STARTBURST_IN ODT: Enabled
+# bit15: 1, DDR IO ODT Unit: Use ODT block
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
--- /dev/null
+/*
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TK71_OE_LOW (~0)
+#define TK71_OE_HIGH (~0)
+#define TK71_OE_VAL_LOW (0)
+#define TK71_OE_VAL_HIGH (0)
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ kw_config_gpio(TK71_OE_VAL_LOW,
+ TK71_OE_VAL_HIGH,
+ TK71_OE_LOW, TK71_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0,
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+
+#define MV88E1116_MAC_CTRL2_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+static void mv_phy_88e1118_init(char *name)
+{
+ u16 reg;
+ u16 devadr;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __func__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1118 Initialized on %s\n", name);
+}
+
+/* Configure and enable Switch and PHY */
+void reset_phy(void)
+{
+ /* configure and initialize PHY */
+ mv_phy_88e1118_init("egiga0");
+
+}
+#endif
int ethernet_present(void);
int ivm_read_eeprom(void);
+int trigger_fpga_config(void);
+int wait_for_fpga_config(void);
+int fpga_reset(void);
+int toggle_eeprom_spi_bus(void);
+
int set_km_env(void);
int fdt_set_node_and_value(void *blob,
char *nodename,
COBJS := $(BOARD).o ../common/common.o ../common/ivm.o
+ifdef CONFIG_KM_FPGA_CONFIG
+COBJS += fpga_config.o
+endif
+
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
--- /dev/null
+/*
+ * (C) Copyright 2012
+ * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/errno.h>
+
+/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
+#define KM_XLX_PROGRAM_B_PIN 39
+
+#define BOCO_ADDR 0x10
+
+#define ID_REG 0x00
+#define BOCO2_ID 0x5b
+
+static int check_boco2(void)
+{
+ int ret;
+ u8 id;
+
+ ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1);
+ if (ret) {
+ printf("%s: error reading the BOCO id !!\n", __func__);
+ return ret;
+ }
+
+ return (id == BOCO2_ID);
+}
+
+static int boco_clear_bits(u8 reg, u8 flags)
+{
+ int ret;
+ u8 regval;
+
+ /* give access to the EEPROM from FPGA */
+ ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1);
+ if (ret) {
+ printf("%s: error reading the BOCO @%#x !!\n",
+ __func__, reg);
+ return ret;
+ }
+ regval &= ~flags;
+ ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1);
+ if (ret) {
+ printf("%s: error writing the BOCO @%#x !!\n",
+ __func__, reg);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int boco_set_bits(u8 reg, u8 flags)
+{
+ int ret;
+ u8 regval;
+
+ /* give access to the EEPROM from FPGA */
+ ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1);
+ if (ret) {
+ printf("%s: error reading the BOCO @%#x !!\n",
+ __func__, reg);
+ return ret;
+ }
+ regval |= flags;
+ ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1);
+ if (ret) {
+ printf("%s: error writing the BOCO @%#x !!\n",
+ __func__, reg);
+ return ret;
+ }
+
+ return 0;
+}
+
+#define SPI_REG 0x06
+#define CFG_EEPROM 0x02
+#define FPGA_PROG 0x04
+#define FPGA_INIT_B 0x10
+#define FPGA_DONE 0x20
+
+static int fpga_done(void)
+{
+ int ret = 0;
+ u8 regval;
+
+ /* this is only supported with the boco2 design */
+ if (!check_boco2())
+ return 0;
+
+ ret = i2c_read(BOCO_ADDR, SPI_REG, 1, ®val, 1);
+ if (ret) {
+ printf("%s: error reading the BOCO @%#x !!\n",
+ __func__, SPI_REG);
+ return 0;
+ }
+
+ return regval & FPGA_DONE ? 1 : 0;
+}
+
+int skip;
+
+int trigger_fpga_config(void)
+{
+ int ret = 0;
+
+ /* if the FPGA is already configured, we do not want to
+ * reconfigure it */
+ skip = 0;
+ if (fpga_done()) {
+ printf("PCIe FPGA config: skipped\n");
+ skip = 1;
+ return 0;
+ }
+
+ if (check_boco2()) {
+ /* we have a BOCO2, this has to be triggered here */
+
+ /* make sure the FPGA_can access the EEPROM */
+ ret = boco_clear_bits(SPI_REG, CFG_EEPROM);
+ if (ret)
+ return ret;
+
+ /* trigger the config start */
+ ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B);
+ if (ret)
+ return ret;
+
+ /* small delay for the pulse */
+ udelay(10);
+
+ /* up signal for pulse end */
+ ret = boco_set_bits(SPI_REG, FPGA_PROG);
+ if (ret)
+ return ret;
+
+ /* finally, raise INIT_B to remove the config delay */
+ ret = boco_set_bits(SPI_REG, FPGA_INIT_B);
+ if (ret)
+ return ret;
+
+ } else {
+ /* we do it the old way, with the gpio pin */
+ kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
+ kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
+ /* small delay for the pulse */
+ udelay(10);
+ kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
+ }
+
+ return 0;
+}
+
+int wait_for_fpga_config(void)
+{
+ int ret = 0;
+ u8 spictrl;
+ u32 timeout = 20000;
+
+ if (skip)
+ return 0;
+
+ if (!check_boco2()) {
+ /* we do not have BOCO2, this is not really used */
+ return 0;
+ }
+
+ printf("PCIe FPGA config:");
+ do {
+ ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1);
+ if (ret) {
+ printf("%s: error reading the BOCO spictrl !!\n",
+ __func__);
+ return ret;
+ }
+ if (timeout-- == 0) {
+ printf(" FPGA_DONE timeout\n");
+ return -EFAULT;
+ }
+ udelay(10);
+ } while (!(spictrl & FPGA_DONE));
+
+ printf(" done\n");
+
+ return 0;
+}
+
+#define PRST1 0x4
+#define PCIE_RST 0x10
+#define TRAFFIC_RST 0x04
+
+int fpga_reset(void)
+{
+ int ret = 0;
+ u8 resets;
+
+ if (!check_boco2()) {
+ /* we do not have BOCO2, this is not really used */
+ return 0;
+ }
+
+ /* if we have skipped, we only want to reset the PCIe part */
+ resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST;
+
+ ret = boco_clear_bits(PRST1, resets);
+ if (ret)
+ return ret;
+
+ /* small delay for the pulse */
+ udelay(10);
+
+ ret = boco_set_bits(PRST1, resets);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+/* the FPGA was configured, we configure the BOCO2 so that the EEPROM
+ * is available from the Bobcat SPI bus */
+int toggle_eeprom_spi_bus(void)
+{
+ int ret = 0;
+
+ if (!check_boco2()) {
+ /* we do not have BOCO2, this is not really used */
+ return 0;
+ }
+
+ ret = boco_set_bits(SPI_REG, CFG_EEPROM);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
#include <nand.h>
#include <netdev.h>
#include <miiphy.h>
+#include <spi.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
0
};
-#if defined(CONFIG_MGCOGE3UN)
+#if defined(CONFIG_KM_MGCOGE3UN)
/*
* Wait for startup OK from mgcoge3ne
*/
}
#endif
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
/*
- * These two boards have always ethernet present. Its connected to the mv
- * switch.
+ * All boards with PIGGY4 connected via a simple switch have ethernet always
+ * present.
*/
int ethernet_present(void)
{
printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
gd->bd->bi_arch_number = mach_type;
}
-#if defined(CONFIG_MGCOGE3UN)
+#if defined(CONFIG_KM_MGCOGE3UN)
char *wait_for_ne;
wait_for_ne = getenv("waitforne");
if (wait_for_ne != NULL) {
int board_early_init_f(void)
{
+#if defined(CONFIG_SOFT_I2C)
u32 tmp;
- kirkwood_mpp_conf(kwmpp_config);
+ /* set the 2 bitbang i2c pins as output gpios */
+ tmp = readl(KW_GPIO0_BASE + 4);
+ writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
+#endif
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
/*
- * The FLASH_GPIO_PIN switches between using a
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+ /*
+ * The KM_FLASH_GPIO_PIN switches between using a
* NAND or a SPI FLASH. Set this pin on start
* to NAND mode.
*/
- tmp = readl(KW_GPIO0_BASE);
- writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
- tmp = readl(KW_GPIO0_BASE + 4);
- writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
+ kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
+ kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
#if defined(CONFIG_SOFT_I2C)
- /* init the GPIO for I2C Bitbang driver */
+ /*
+ * Reinit the GPIO for I2C Bitbang driver so that the now
+ * available gpio framework is consistent. The calls to
+ * direction output in are not necessary, they are already done in
+ * board_early_init_f
+ */
kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
- kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0);
- kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0);
#endif
+
#if defined(CONFIG_SYS_EEPROM_WREN)
kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
#endif
-#if defined(CONFIG_KM_RECONFIG_XLX)
- /* trigger the reconfiguration of the xilinx fpga */
- kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
- kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
- kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
+
+#if defined(CONFIG_KM_FPGA_CONFIG)
+ trigger_fpga_config();
#endif
+
return 0;
}
-int board_init(void)
+int board_late_init(void)
{
- /* address of boot parameters */
- gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+#if defined(CONFIG_KMCOGE5UN)
+/* I/O pin to erase flash RGPP09 = MPP43 */
+#define KM_FLASH_ERASE_ENABLE 43
+ u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
+
+ /* if pin 1 do full erase */
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ setenv("actual_bank", "0");
+ }
+#endif
+#if defined(CONFIG_KM_FPGA_CONFIG)
+ wait_for_fpga_config();
+ fpga_reset();
+ toggle_eeprom_spi_bus();
+#endif
return 0;
}
-#if defined(CONFIG_CMD_SF)
-int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int board_spi_claim_bus(struct spi_slave *slave)
{
- u32 tmp;
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- if ((strcmp(argv[1], "off") == 0)) {
- printf("SPI FLASH disabled, NAND enabled\n");
- /* Multi-Purpose Pins Functionality configuration */
- kwmpp_config[0] = MPP0_NF_IO2;
- kwmpp_config[1] = MPP1_NF_IO3;
- kwmpp_config[2] = MPP2_NF_IO4;
- kwmpp_config[3] = MPP3_NF_IO5;
-
- kirkwood_mpp_conf(kwmpp_config);
- tmp = readl(KW_GPIO0_BASE);
- writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
- } else if ((strcmp(argv[1], "on") == 0)) {
- printf("SPI FLASH enabled, NAND disabled\n");
- /* Multi-Purpose Pins Functionality configuration */
- kwmpp_config[0] = MPP0_SPI_SCn;
- kwmpp_config[1] = MPP1_SPI_MOSI;
- kwmpp_config[2] = MPP2_SPI_SCK;
- kwmpp_config[3] = MPP3_SPI_MISO;
-
- kirkwood_mpp_conf(kwmpp_config);
- tmp = readl(KW_GPIO0_BASE);
- writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
- } else {
- return cmd_usage(cmdtp);
- }
+ kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
return 0;
}
-U_BOOT_CMD(
- spitoggle, 2, 0, do_spi_toggle,
- "En-/disable SPI FLASH access",
- "<on|off> - Enable (on) or disable (off) SPI FLASH access\n"
- );
-#endif
+void board_spi_release_bus(struct spi_slave *slave)
+{
+ kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
+}
int dram_init(void)
{
}
}
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_KM_PIGGY4_88E6061))
-#define PHY_LED_SEL 0x18
-#define PHY_LED0_LINK (0x5)
-#define PHY_LED1_ACT (0x8<<4)
-#define PHY_LED2_INT (0xe<<8)
-#define PHY_SPEC_CTRL 0x1c
+#define PHY_LED_SEL_REG 0x18
+#define PHY_LED0_LINK (0x5)
+#define PHY_LED1_ACT (0x8<<4)
+#define PHY_LED2_INT (0xe<<8)
+#define PHY_SPEC_CTRL_REG 0x1c
#define PHY_RGMII_CLK_STABLE (0x1<<10)
-#define PHY_CLSA (0x1<<1)
+#define PHY_CLSA (0x1<<1)
/* Configure and enable MV88E3018 PHY */
void reset_phy(void)
return;
/* RGMII clk transition on data stable */
- if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, ®) != 0)
+ if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
printf("Error reading PHY spec ctrl reg\n");
- if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL,
- reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0)
+ if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
+ reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
printf("Error writing PHY spec ctrl reg\n");
/* leds setup */
- if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL,
- PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0)
+ if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
+ PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
printf("Error writing PHY LED reg\n");
/* reset the phy */
0xFF00FF00,
0x0F0F0F0F,
0xF0F0F0F0};
-const ulong NBR_OF_PATTERNS = sizeof(patterns)/sizeof(*patterns);
+const ulong NBR_OF_PATTERNS = ARRAY_SIZE(patterns);
const ulong OFFS_PATTERN = 3;
const ulong REPEAT_PATTERN = 1000;
int post_hotkeys_pressed(void)
{
+#if defined(CONFIG_KM_COGE5UN)
+ return kw_gpio_get_value(KM_POST_EN_L);
+#else
return !kw_gpio_get_value(KM_POST_EN_L);
+#endif
}
ulong post_word_load(void)
DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
# bit3-0 : 0000, required
# bit7-4 : 0010, M_ODT assertion 2 cycles after read
-# bit11-8 : 1001, M_ODT de-assertion 5 cycles after read
+# bit11-8 : 0101, M_ODT de-assertion 5 cycles after read
# bit15-12: 0100, internal ODT assertion 4 cycles after read
# bit19-16: 1000, internal ODT de-assertion 8 cycles after read
# bit31-20: 0 , required
--- /dev/null
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# (C) Copyright 2012
+# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
+# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com
+#
+# (C) Copyright 2012
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
+# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
+# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
+# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4 NF_IO[6]
+# bit 23-20: 1, MPPSel5 NF_IO[7]
+# bit 27-24: 1, MPPSel6 SYSRST_O
+# bit 31-28: 0, MPPSel7 GPO[7]
+
+DATA 0xFFD10004 0x03303300 # MPP Control 1 Register
+# bit 3-0: 0, MPPSel8 GPIO[8]
+# bit 7-4: 0, MPPSel9 GPIO[9]
+# bit 12-8: 3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 UA1_TXD
+# bit 27-24: 3, MPPSel14 UA1_RXD
+# bit 31-28: 0, MPPSel15 GPIO[15]
+
+DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
+# bit 3-0: 0, MPPSel16 GPIO[16]
+# bit 7-4: 0, MPPSel17 not connected
+# bit 12-8: 1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
+# bit 2-0: 3, Reserved
+# bit 5-3: 3, Reserved
+# bit 6: 0, Reserved
+# bit 7: 0, RGMII-pads voltage = 3.3V
+# bit 10-8: 3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14: 0, Reserved
+# bit 15: 0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16 0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
+# bit 0-1: 2, Tag RAM RTC RAM0
+# bit 3-2: 1, Tag RAM WTC RAM0
+# bit 7-4: 6, Reserve
+# bit 9-8: 2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
+# bit 15-0: ???, Reserve
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ???,Reserve
+
+DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
+# bit 23-0: 0x000200, Addr Config tuning
+# bit 31-24: 0, Reserved
+
+# ??? Missing register # CPU RAM Management Control2 Register
+
+DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
+# bit 15-0: 0x1C00, Opmux Tuning
+# bit 31-16: 0, Pc Dp Tuning
+
+DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
+# bit 1-0: 1, addr clk tune
+# bit 3-2: 0, reserved
+# bit 5-4: 0, dtcmp clk tune
+# bit 7-6: 0, reserved
+# bit 9-8: 0, macdrv clk tune
+# bit 11-10: 0, opmuxgm2 clk tune
+# bit 15-14: 0, rf clk tune
+# bit 17-16: 0, rfbypass clk tune
+# bit 19-18: 0, pc dp clk tune
+# bit 23-20: 0, icache clk tune
+# bit 27:24: 0, dcache clk tune
+# bit 31:28: 0, regfile tunin
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
+# bit 13-0: 0x4E0, DDR2 clks refresh rate
+# bit 14: 0, reserved
+# bit 15: 0, reserved
+# bit 16: 0, CPU to Dram Write buffer policy
+# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24: 1, enable exit self refresh mode on DDR access
+# bit 25: 1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
+# bit 3-0: 0, reserved
+# bit 4: 0, 2T mode =addr/cmd in same cycle
+# bit 5: 0, clk is driven during self refresh, we don't care for APX
+# bit 6: 0, use recommended falling edge of clk for addr/cmd
+# bit 7-11: 0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14: 0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18: 1, cpu lock transaction enabled
+# bit 19: 0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM
+# bit 30-28: 3, required
+# bit 31: 0,no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1)
+# bit 3-0: 0xE, TRAS, 15 clk (45 ns)
+# bit 7-4: 0x4, TRCD, 5 clk (15 ns)
+# bit 11-8: 0x4, TRP, 5 clk (15 ns)
+# bit 15-12: 0x4, TWR, 5 clk (15 ns)
+# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns)
+# bit 20: 0, extended TRAS msb
+# bit 23-21: 0, reserved
+# bit 27-24: 0x3, TRRD, 4 clk (10 ns)
+# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
+
+DATA 0xFFD0140C 0x0000003e # DDR Timing (High)
+# bit 6-0: 0x3E, TRFC, 63 clk (195 ns)
+# bit 8-7: 0, TR2R
+# bit 10-9: 0, TR2W
+# bit 12-11: 0, TW2W
+# bit 31-13: 0, reserved
+
+DATA 0xFFD01410 0x00000001 # DDR Address Control
+# bit 1-0: 1, Cs0width=x16
+# bit 3-2: 0, Cs0size=2Gb
+# bit 5-4: 0, Cs1width=nonexistent
+# bit 7-6: 0, Cs1size =nonexistent
+# bit 9-8: 0, Cs2width=nonexistent
+# bit 11-10: 0, Cs2size =nonexistent
+# bit 13-12: 0, Cs3width=nonexistent
+# bit 15-14: 0, Cs3size =nonexistent
+# bit 16: 0, Cs0AddrSel
+# bit 17: 0, Cs1AddrSel
+# bit 18: 0, Cs2AddrSel
+# bit 19: 0, Cs3AddrSel
+# bit 31-20: 0, required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit 0: 0, OpenPage enabled
+# bit 31-1: 0, required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit 3-0: 0, DDR cmd
+# bit 31-4: 0, required
+
+DATA 0xFFD0141C 0x00000652 # DDR Mode
+# bit 2-0: 2, Burst Length = 4
+# bit 3: 0, Burst Type
+# bit 6-4: 5, CAS Latency = 5
+# bit 7: 0, Test mode
+# bit 8: 0, DLL Reset
+# bit 11-9: 3, Write recovery for auto-precharge must be 3
+# bit 12: 0, Active power down exit time, fast exit
+# bit 14-13: 0, reserved
+# bit 31-15: 0, reserved
+
+DATA 0xFFD01420 0x00000006 # DDR Extended Mode
+# bit 0: 0, DDR DLL enabled
+# bit 1: 1, DDR drive strength reduced
+# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0]
+# bit 5-3: 0, required
+# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1]
+# bit 9-7: 0, required
+# bit 10: 0, differential DQS enabled
+# bit 11: 0, required
+# bit 12: 0, DDR output buffer enabled
+# bit 31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit 2-0: 7, required
+# bit 3: 1, MBUS Burst Chop disabled
+# bit 6-4: 7, required
+# bit 7: 0, reserved
+# bit 8: 1, add sample stage required for f > 266 MHz
+# bit 9: 0, no half clock cycle addition to dataout
+# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11: 0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16: 0, required
+
+DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
+# bit 3-0: 0, required
+# bit 7-4: 2, M_ODT assertion 2 cycles after read start command
+# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
+# (ODT turn off delay 2,5 clk cycles)
+# bit 15-12: 4, internal ODT time based on bit 7-4
+# with the considered SDRAM internal delay
+# bit 19-16: 8, internal ODT de-assertion based on bit 11-8
+# with the considered SDRAM internal delay
+# bit 31-20: 0, required
+
+DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
+# bit 3-0: 2, M_ODT assertion same as bit 11-8
+# bit 7-4: 5, M_ODT de-assertion same as bit 15-12
+# bit 11-8: 4, internal ODT assertion 2 cycles after write start command
+# with the considered SDRAM internal delay
+# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
+# with the considered SDRAM internal delay
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+# bit 23-0: 0, reserved
+# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit 0: 1, Window enabled
+# bit 1: 0, Write Protect disabled
+# bit 3-2: 0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
+# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit 7-4: 0, ODT0Rd, MODT[1] not asserted
+# bit 11-8: 0, required
+# big 15-11: 0, required
+# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20: 0, ODT0Wr, MODT[1] not asserted
+# bit 27-24: 0, required
+# bit 31-28: 0, required
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2: 0, ODT1 controlled by register
+# bit 31-4: 0, required
+
+DATA 0xFFD0149C 0x0000E801 # CPU ODT Control
+# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0
+# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM
+# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr
+# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14: 1, STARTBURST ODT enabled
+# bit 15: 1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+# bit 0: 1, enable DDR init upon this register write
+# bit 31-1: 0, reserved
+
+# End of Header extension
+DATA 0x0 0x0
--- /dev/null
+#
+# (C) Copyright 2012
+# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com
+# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com
+# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+# This configuration applies to COGE5 design (ARM-part)
+# Two 8-Bit devices are connected on the 16-Bit bus on the same
+# chip-select. The supported devices are
+# MT47H256M8EB-3IT:C
+# MT47H256M8EB-25EIT:C
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
+# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
+# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
+# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4 NF_IO[6]
+# bit 23-20: 1, MPPSel5 NF_IO[7]
+# bit 27-24: 1, MPPSel6 SYSRST_O
+# bit 31-28: 0, MPPSel7 GPO[7]
+
+DATA 0xFFD10004 0x03303300 # MPP Control 1 Register
+# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged
+# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged
+# bit 12-8: 3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 GPIO[14]
+# bit 27-24: 3, MPPSel14 GPIO[15]
+# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
+
+DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
+# bit 3-0: 0, MPPSel16 GPIO[16]
+# bit 7-4: 0, MPPSel17 not connected
+# bit 11-8: 1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
+# bit 2-0: 3, Reserved
+# bit 5-3: 3, Reserved
+# bit 6: 0, Reserved
+# bit 7: 0, RGMII-pads voltage = 3.3V
+# bit 10-8: 3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14: 0, Reserved
+# bit 15: 0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16 0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
+# bit 0-1: 2, Tag RAM RTC RAM0
+# bit 3-2: 1, Tag RAM WTC RAM0
+# bit 7-4: 6, Reserved
+# bit 9-8: 2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
+# bit 15-0: ?, Reserved
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ?,Reserved
+
+DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
+# bit 23-0: 0x000200, Addr Config tuning
+# bit 31-24: 0, Reserved
+
+# ??? Missing register # CPU RAM Management Control2 Register
+
+DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
+# bit 15-0: 0x1C00, Opmux Tuning
+# bit 31-16: 0, Pc Dp Tuning
+
+DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
+# bit 1-0: 1, addr clk tune
+# bit 3-2: 0, reserved
+# bit 5-4: 0, dtcmp clk tune
+# bit 7-6: 0, reserved
+# bit 9-8: 0, macdrv clk tune
+# bit 11-10: 0, opmuxgm2 clk tune
+# bit 15-14: 0, rf clk tune
+# bit 17-16: 0, rfbypass clk tune
+# bit 19-18: 0, pc dp clk tune
+# bit 23-20: 0, icache clk tune
+# bit 27:24: 0, dcache clk tune
+# bit 31:28: 0, regfile tunin
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
+# bit 13-0: 0x4E0, DDR2 clks refresh rate
+# bit 14: 0, reserved
+# bit 15: 0, reserved
+# bit 16: 0, CPU to Dram Write buffer policy
+# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24: 1, enable exit self refresh mode on DDR access
+# bit 25: 1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
+# bit 3-0: 0, reserved
+# bit 4: 0, 2T mode =addr/cmd in same cycle
+# bit 5: 0, clk is driven during self refresh, we don't care for APX
+# bit 6: 0, use recommended falling edge of clk for addr/cmd
+# bit 7-11: 0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14: 0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18: 1, cpu lock transaction enabled
+# bit 19: 0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM
+# bit 30-28: 3, required
+# bit 31: 0, no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1)
+# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles
+# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles
+# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles
+# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
+# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
+# bit 20: 0, extended TRAS msb
+# bit 23-21: 0, reserved
+# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
+# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
+
+DATA 0xFFD0140C 0x0000003E # DDR Timing (High)
+# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles
+# bit 8-7: 0, TR2R
+# bit 10-9: 0, TR2W
+# bit 12-11: 0, TW2W
+# bit 31-13: 0, reserved
+
+DATA 0xFFD01410 0x00000000 # DDR Address Control
+# bit 1-0: 0, Cs0width=x8 (2 devices)
+# bit 3-2: 0, Cs0size=2Gb
+# bit 5-4: 0, Cs1width=nonexistent
+# bit 7-6: 0, Cs1size =nonexistent
+# bit 9-8: 0, Cs2width=nonexistent
+# bit 11-10: 0, Cs2size =nonexistent
+# bit 13-12: 0, Cs3width=nonexistent
+# bit 15-14: 0, Cs3size =nonexistent
+# bit 16: 0, Cs0AddrSel
+# bit 17: 0, Cs1AddrSel
+# bit 18: 0, Cs2AddrSel
+# bit 19: 0, Cs3AddrSel
+# bit 31-20: 0, required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit 0: 0, OpenPage enabled
+# bit 31-1: 0, required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit 3-0: 0, DDR cmd
+# bit 31-4: 0, required
+
+DATA 0xFFD0141C 0x00000652 # DDR Mode
+# bit 2-0: 2, Burst Length = 4
+# bit 3: 0, Burst Type
+# bit 6-4: 5, CAS Latency = 5
+# bit 7: 0, Test mode
+# bit 8: 0, DLL Reset
+# bit 11-9: 3, Write recovery for auto-precharge must be 3
+# bit 12: 0, Active power down exit time, fast exit
+# bit 14-13: 0, reserved
+# bit 31-15: 0, reserved
+
+DATA 0xFFD01420 0x00000006 # DDR Extended Mode
+# bit 0: 0, DDR DLL enabled
+# bit 1: 1, DDR drive strenght reduced
+# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0]
+# bit 5-3: 0, required
+# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1]
+# bit 9-7: 0, required
+# bit 10: 0, differential DQS enabled
+# bit 11: 0, required
+# bit 12: 0, DDR output buffer enabled
+# bit 31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit 2-0: 7, required
+# bit 3: 1, MBUS Burst Chop disabled
+# bit 6-4: 7, required
+# bit 7: 0, reserved
+# bit 8: 1, add sample stage required for > 266Mhz
+# bit 9: 0, no half clock cycle addition to dataout
+# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11: 0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16: 0, required
+
+DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
+# bit 3-0: 0, required
+# bit 7-4: 2, M_ODT assertion 2 cycles after read start command
+# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
+# (ODT turn off delay 2,5 clk cycles)
+# bit 15-12: 4, internal ODT time based on bit 7-4
+# with the considered SDRAM internal delay
+# bit 19-16: 8, internal ODT de-assertion based on bit 11-8
+# with the considered SDRAM internal delay
+# bit 31-20: 0, required
+
+DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
+# bit 3-0: 2, M_ODT assertion same as bit 11-8
+# bit 7-4: 5, M_ODT de-assertion same as bit 15-12
+# bit 11-8: 4, internal ODT assertion 2 cycles after write start command
+# with the considered SDRAM internal delay
+# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
+# with the considered SDRAM internal delay
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+# bit 23-0: 0, reserved
+# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size
+# bit 0: 1, Window enabled
+# bit 1: 0, Write Protect disabled
+# bit 3-2: 0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24:0x1F, Size (i.e. 512MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
+# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit 7-4: 0, ODT0Rd, MODT[1] not asserted
+# bit 11-8: 0, required
+# big 15-11: 0, required
+# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20: 0, ODT0Wr, MODT[1] not asserted
+# bit 27-24: 0, required
+# bit 31-28: 0, required
+
+DATA 0xFFD01498 0x00000004 # DDR ODT Control (High)
+# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2: 1, ODT1 never active
+# bit 31-4: 0, required
+
+DATA 0xFFD0149C 0x0000E801 # CPU ODT Control
+# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
+# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr
+# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14: 1, STARTBURST ODT enabled
+# bit 15: 1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+# bit 0: 1, enable DDR init upon this register write
+# bit 31-1: 0, reserved
+
+# End of Header extension
+DATA 0x0 0x0
*/
#include <common.h>
-#include <ns16550.h>
#include <asm/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/uart-spi-switch.h>
#include <asm/arch/tegra2.h>
-#include <asm/arch/tegra2_spi.h>
+#include <asm/arch/tegra_spi.h>
/* position of the UART/SPI select switch */
/* Information about the spi/uart switch */
struct spi_uart {
int gpio; /* GPIO to control switch */
- NS16550_t regs; /* Address of UART affected */
u32 port; /* Port number of UART affected */
};
{
#if defined CONFIG_SPI_CORRUPTS_UART
config->gpio = CONFIG_UART_DISABLE_GPIO;
- config->regs = (NS16550_t)CONFIG_SPI_CORRUPTS_UART;
config->port = CONFIG_SPI_CORRUPTS_UART_NR;
#else
config->gpio = -1;
if (switch_pos == SWITCH_BOTH || new_pos == switch_pos)
return;
- /* if the UART was selected, allow it to drain */
- if (switch_pos == SWITCH_UART)
- NS16550_drain(config->regs, config->port);
+ /* pre-delay, allow SPI/UART to settle, FIFO to empty, etc. */
+ udelay(CONFIG_SPI_CORRUPTS_UART_DLY);
/* We need to dynamically change the pinmux, shared w/UART RXD/CTS */
pinmux_set_func(PINGRP_GMC, new_pos == SWITCH_SPI ?
PMUX_FUNC_SFLASH : PMUX_FUNC_UARTD);
/*
- * On Seaboard, MOSI/MISO are shared w/UART.
- * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity.
- * Enable UART later (cs_deactivate) so we can use it for U-Boot comms.
- */
+ * On Seaboard, MOSI/MISO are shared w/UART.
+ * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity.
+ * Enable UART later (cs_deactivate) so we can use it for U-Boot comms.
+ */
gpio_direction_output(config->gpio, new_pos == SWITCH_SPI);
switch_pos = new_pos;
-
- /* if the SPI was selected, clear any junk bytes in the UART */
- if (switch_pos == SWITCH_UART) {
- /* TODO: What if it is part-way through clocking in junk? */
- udelay(100);
- NS16550_clear(config->regs, config->port);
- }
}
-void pinmux_select_uart(NS16550_t regs)
+void pinmux_select_uart(void)
{
- /* Also prevents calling spi_uart_switch() before relocation */
- if (regs == local.regs)
spi_uart_switch(&local, SWITCH_UART);
}
--- /dev/null
+/dts-v1/;
+
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "NVIDIA Tegra2 Harmony evaluation board";
+ compatible = "nvidia,harmony", "nvidia,tegra20";
+
+ aliases {
+ usb0 = "/usb@c5008000";
+ };
+
+ memory {
+ reg = <0x00000000 0x40000000>;
+ };
+
+ clocks {
+ clk_32k: clk_32k {
+ clock-frequency = <32000>;
+ };
+ osc {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ clock@60006000 {
+ clocks = <&clk_32k &osc>;
+ };
+
+ serial@70006300 {
+ clock-frequency = < 216000000 >;
+ };
+
+ i2c@7000c000 {
+ status = "disabled";
+ };
+
+ i2c@7000c400 {
+ status = "disabled";
+ };
+
+ i2c@7000c500 {
+ status = "disabled";
+ };
+
+ i2c@7000d000 {
+ status = "disabled";
+ };
+
+ usb@c5000000 {
+ status = "disabled";
+ };
+
+ usb@c5004000 {
+ status = "disabled";
+ };
+};
--- /dev/null
+/dts-v1/;
+
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "NVIDIA Tegra2 Ventana evaluation board";
+ compatible = "nvidia,ventana", "nvidia,tegra20";
+
+ aliases {
+ usb0 = "/usb@c5008000";
+ };
+
+ memory {
+ reg = <0x00000000 0x40000000>;
+ };
+
+ clocks {
+ clk_32k: clk_32k {
+ clock-frequency = <32000>;
+ };
+ osc {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ clock@60006000 {
+ clocks = <&clk_32k &osc>;
+ };
+
+ serial@70006300 {
+ clock-frequency = < 216000000 >;
+ };
+
+ i2c@7000c000 {
+ status = "disabled";
+ };
+
+ i2c@7000c400 {
+ status = "disabled";
+ };
+
+ i2c@7000c500 {
+ status = "disabled";
+ };
+
+ i2c@7000d000 {
+ status = "disabled";
+ };
+
+ usb@c5000000 {
+ status = "disabled";
+ };
+
+ usb@c5004000 {
+ status = "disabled";
+ };
+};
--- /dev/null
+/dts-v1/;
+
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "NVIDIA Tegra2 Whistler evaluation board";
+ compatible = "nvidia,whistler", "nvidia,tegra20";
+
+ aliases {
+ i2c0 = "/i2c@7000d000";
+ usb0 = "/usb@c5008000";
+ usb1 = "/usb@c5000000";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = < 0x00000000 0x20000000 >;
+ };
+
+ clocks {
+ osc {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ clock@60006000 {
+ clocks = <&clk_32k &osc>;
+ };
+
+ serial@70006000 {
+ clock-frequency = < 216000000 >;
+ };
+
+ i2c@7000c000 {
+ status = "disabled";
+ };
+
+ i2c@7000c400 {
+ status = "disabled";
+ };
+
+ i2c@7000c500 {
+ status = "disabled";
+ };
+
+ i2c@7000d000 {
+ clock-frequency = <100000>;
+
+ pmic@3c {
+ compatible = "maxim,max8907b";
+ reg = <0x3c>;
+
+ clk_32k: clock {
+ compatible = "fixed-clock";
+ /*
+ * leave out for now due to CPP:
+ * #clock-cells = <0>;
+ */
+ clock-frequency = <32768>;
+ };
+ };
+ };
+
+ usb@c5004000 {
+ status = "disabled";
+ };
+};
#include <asm/arch/pinmux.h>
#include <asm/arch/mmc.h>
#include <asm/gpio.h>
-#ifdef CONFIG_TEGRA2_MMC
+#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
{
}
-#ifdef CONFIG_TEGRA2_MMC
+#ifdef CONFIG_TEGRA_MMC
/*
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
#include <asm/arch/pinmux.h>
#include <asm/arch/mmc.h>
#include <asm/gpio.h>
-#ifdef CONFIG_TEGRA2_MMC
+#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
}
#endif
-#ifdef CONFIG_TEGRA2_MMC
+#ifdef CONFIG_TEGRA_MMC
/*
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
--- /dev/null
+#
+# (C) Copyright 2010-2012
+# NVIDIA Corporation <www.nvidia.com>
+#
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/mmc.h>
+#include <asm/gpio.h>
+#ifdef CONFIG_TEGRA_MMC
+#include <mmc.h>
+#endif
+
+/*
+ * Routine: gpio_config_uart
+ * Description: Does nothing on Whistler - no UART-related GPIOs.
+ */
+void gpio_config_uart(void)
+{
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+static void pin_mux_mmc(void)
+{
+ funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT);
+ funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT);
+}
+
+/* this is a weak define that we are overriding */
+int board_mmc_init(bd_t *bd)
+{
+ uchar val;
+ int ret;
+
+ debug("board_mmc_init called\n");
+
+ /* Turn on MAX8907B LDO12 to 2.8V for J40 power */
+ ret = i2c_set_bus_num(0);
+ if (ret)
+ printf("i2c_set_bus_num failed: %d\n", ret);
+ val = 0x29;
+ ret = i2c_write(0x3c, 0x46, 1, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret);
+ val = 0x00;
+ ret = i2c_write(0x3c, 0x45, 1, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret);
+ val = 0x1f;
+ ret = i2c_write(0x3c, 0x44, 1, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret);
+
+ /* Enable muxes, etc. for SDMMC controllers */
+ pin_mux_mmc();
+
+ /* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */
+ tegra2_mmc_init(0, 8, -1, -1);
+
+ /* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */
+ tegra2_mmc_init(1, 8, -1, -1);
+
+ return 0;
+}
+
+/* this is a weak define that we are overriding */
+void pin_mux_usb(void)
+{
+ uchar val;
+ int ret;
+
+ /*
+ * This is a hack. This should be represented in DT using the
+ * vbus-gpio property. However, U-Boot's DT support doesn't
+ * support any GPIO controller other than the Tegra's yet.
+ */
+
+ /* Turn on TAC6416's GPIO 0+1 for USB1/3's VBUS */
+ ret = i2c_set_bus_num(0);
+ if (ret)
+ printf("i2c_set_bus_num failed: %d\n", ret);
+ val = 0x03;
+ ret = i2c_write(0x20, 2, 1, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x20 2 failed: %d\n", ret);
+ val = 0xfc;
+ ret = i2c_write(0x20, 6, 1, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x20 6 failed: %d\n", ret);
+}
MPP29_GPIO, /* USB Copy button */
0
};
- kirkwood_mpp_conf(kwmpp_config);
+ kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
#include <asm/arch/sromc.h>
DECLARE_GLOBAL_DATA_PTR;
-struct exynos5_gpio_part1 *gpio1;
#ifdef CONFIG_SMC911X
-static void smc9115_pre_init(void)
+static int smc9115_pre_init(void)
{
u32 smc_bw_conf, smc_bc_conf;
- int i;
-
- /*
- * SROM:CS1 and EBI
- *
- * GPY0[0] SROM_CSn[0]
- * GPY0[1] SROM_CSn[1](2)
- * GPY0[2] SROM_CSn[2]
- * GPY0[3] SROM_CSn[3]
- * GPY0[4] EBI_OEn(2)
- * GPY0[5] EBI_EEn(2)
- *
- * GPY1[0] EBI_BEn[0](2)
- * GPY1[1] EBI_BEn[1](2)
- * GPY1[2] SROM_WAIT(2)
- * GPY1[3] EBI_DATA_RDn(2)
- */
- s5p_gpio_cfg_pin(&gpio1->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
- s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
- s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
-
- for (i = 0; i < 4; i++)
- s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
-
- /*
- * EBI: 8 Addrss Lines
- *
- * GPY3[0] EBI_ADDR[0](2)
- * GPY3[1] EBI_ADDR[1](2)
- * GPY3[2] EBI_ADDR[2](2)
- * GPY3[3] EBI_ADDR[3](2)
- * GPY3[4] EBI_ADDR[4](2)
- * GPY3[5] EBI_ADDR[5](2)
- * GPY3[6] EBI_ADDR[6](2)
- * GPY3[7] EBI_ADDR[7](2)
- *
- * EBI: 16 Data Lines
- *
- * GPY5[0] EBI_DATA[0](2)
- * GPY5[1] EBI_DATA[1](2)
- * GPY5[2] EBI_DATA[2](2)
- * GPY5[3] EBI_DATA[3](2)
- * GPY5[4] EBI_DATA[4](2)
- * GPY5[5] EBI_DATA[5](2)
- * GPY5[6] EBI_DATA[6](2)
- * GPY5[7] EBI_DATA[7](2)
- *
- * GPY6[0] EBI_DATA[8](2)
- * GPY6[1] EBI_DATA[9](2)
- * GPY6[2] EBI_DATA[10](2)
- * GPY6[3] EBI_DATA[11](2)
- * GPY6[4] EBI_DATA[12](2)
- * GPY6[5] EBI_DATA[13](2)
- * GPY6[6] EBI_DATA[14](2)
- * GPY6[7] EBI_DATA[15](2)
- */
- for (i = 0; i < 8; i++) {
- s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
- s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
-
- s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
- s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
-
- s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
- s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
- }
+ int err;
/* Ethernet needs data bus width of 16 bits */
smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK)
| SROMC_BC_PMC(0x01);
/* Select and configure the SROMC bank */
+ err = exynos_pinmux_config(PERIPH_ID_SROMC,
+ CONFIG_ENV_SROM_BANK | PINMUX_FLAG_16BIT);
+ if (err) {
+ debug("SROMC not configured\n");
+ return err;
+ }
+
s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+ return 0;
}
#endif
int board_init(void)
{
- gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
return 0;
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_SMC911X
- smc9115_pre_init();
+ if (smc9115_pre_init())
+ return -1;
return smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return 0;
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
- int i, err;
-
- /*
- * MMC2 SD card GPIO:
- *
- * GPC2[0] SD_2_CLK(2)
- * GPC2[1] SD_2_CMD(2)
- * GPC2[2] SD_2_CDn
- * GPC2[3:6] SD_2_DATA[0:3](2)
- */
- for (i = 0; i < 7; i++) {
- /* GPC2[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio1->c2, i, GPIO_FUNC(0x2));
-
- /* GPK2[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio1->c2, i, GPIO_DRV_4X);
+ int err;
- /* GPK2[0:1] pull disable */
- if (i == 0 || i == 1) {
- s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_NONE);
- continue;
- }
-
- /* GPK2[2:6] pull up */
- s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_UP);
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("SDMMC2 not configured\n");
+ return err;
}
err = s5p_mmc_init(2, 4);
}
#endif
-static void board_uart_init(void)
+static int board_uart_init(void)
{
- struct exynos5_gpio_part1 *gpio1 =
- (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
- int i;
+ int err;
- /*
- * UART0 GPIOs : GPA0CON[3:0] 0x2222
- * Must set CFG17 switches to select UART0 to use.
- */
- for (i = 0; i <= 3; i++) {
- s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE);
- s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2));
+ err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("UART0 not configured\n");
+ return err;
}
- /*
- * UART1 GPIOs : GPA0CON[5:4] 0x22
- * Must set CFG17 switches to select UART1 to use.
- *
- * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down
- * in order to use them (so that those pins can be used for I2C).
- */
- for (i = 4; i <= 5; i++) {
- s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE);
- s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2));
+ err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("UART1 not configured\n");
+ return err;
}
- /*
- * UART2 GPIOs : GPA1CON[1:0] 0x22
- * Must set CFG17 switches to select UART2 to use.
- *
- * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down
- * in order to use them (so that those pins can be used for I2C).
- */
- for (i = 0; i <= 1; i++) {
- s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
- s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2));
+ err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("UART2 not configured\n");
+ return err;
}
- /*
- * UART3 GPIOs : GPA1CON[5:4] 0x22
- * Must set CFG16 switches to select UART3 to use.
- */
- for (i = 4; i <= 5; i++) {
- s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
- s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2));
+ err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("UART3 not configured\n");
+ return err;
}
- /*
- * There's no mux for UART4--it's internal only
- */
+ return 0;
}
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
- board_uart_init();
- return 0;
+ return board_uart_init();
}
#endif
static int s5pc210_phy_control(int on)
{
int ret = 0;
+ u32 val = 0;
struct pmic *p = get_pmic();
if (pmic_probe(p))
if (on) {
ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
ENSAFEOUT1, LDO_ON);
- ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO);
- ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO);
+ ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
+
+ ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
} else {
- ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO);
- ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO);
+ ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
+
+ ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
ENSAFEOUT1, LDO_OFF);
}
return 0;
}
+vidinfo_t panel_info = {
+ .vl_freq = 60,
+ .vl_col = 720,
+ .vl_row = 1280,
+ .vl_width = 720,
+ .vl_height = 1280,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_hsp = CONFIG_SYS_LOW,
+ .vl_vsp = CONFIG_SYS_LOW,
+ .vl_dp = CONFIG_SYS_LOW,
+ .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */
+
+ /* s6e8ax0 Panel infomation */
+ .vl_hspw = 5,
+ .vl_hbpd = 10,
+ .vl_hfpd = 10,
+
+ .vl_vspw = 2,
+ .vl_vbpd = 1,
+ .vl_vfpd = 13,
+ .vl_cmd_allow_len = 0xf,
+
+ .win_id = 3,
+ .cfg_gpio = NULL,
+ .backlight_on = NULL,
+ .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */
+ .reset_lcd = lcd_reset,
+ .dual_lcd_enabled = 0,
+
+ .init_delay = 0,
+ .power_on_delay = 0,
+ .reset_delay = 0,
+ .interface_mode = FIMD_RGB_INTERFACE,
+ .mipi_enabled = 1,
+};
+
void init_panel_info(vidinfo_t *vid)
{
- vid->vl_freq = 60;
- vid->vl_col = 720;
- vid->vl_row = 1280;
- vid->vl_width = 720;
- vid->vl_height = 1280;
- vid->vl_clkp = CONFIG_SYS_HIGH;
- vid->vl_hsp = CONFIG_SYS_LOW;
- vid->vl_vsp = CONFIG_SYS_LOW;
- vid->vl_dp = CONFIG_SYS_LOW;
-
- vid->vl_bpix = 5;
- vid->dual_lcd_enabled = 0;
-
- /* s6e8ax0 Panel */
- vid->vl_hspw = 5;
- vid->vl_hbpd = 10;
- vid->vl_hfpd = 10;
-
- vid->vl_vspw = 2;
- vid->vl_vbpd = 1;
- vid->vl_vfpd = 13;
- vid->vl_cmd_allow_len = 0xf;
-
- vid->win_id = 3;
- vid->cfg_gpio = NULL;
- vid->backlight_on = NULL;
- vid->lcd_power_on = NULL; /* lcd_power_on in mipi dsi driver */
- vid->reset_lcd = lcd_reset;
-
- vid->init_delay = 0;
- vid->power_on_delay = 0;
- vid->reset_delay = 0;
- vid->interface_mode = FIMD_RGB_INTERFACE;
- vid->mipi_enabled = 1;
vid->logo_on = 1,
vid->resolution = HD_RESOLUTION,
vid->rgb_mode = MODE_RGB_P,
LIB = $(obj)lib$(VENDOR).o
+ifndef CONFIG_SPL_BUILD
COBJS := spr_misc.o
SOBJS := spr_lowlevel_init.o
+endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
#include <command.h>
#include <i2c.h>
#include <net.h>
+#include <linux/mtd/st_smi.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_emi.h>
-#include <asm/arch/spr_xloader_table.h>
#include <asm/arch/spr_defs.h>
#define CPU 0
#define SRAM_REL 0xD2801000
DECLARE_GLOBAL_DATA_PTR;
-static struct chip_data chip_data;
+
+#if defined(CONFIG_CMD_NET)
+static int i2c_read_mac(uchar *buffer);
+#endif
int dram_init(void)
{
- struct xloader_table *xloader_tb =
- (struct xloader_table *)XLOADER_TABLE_ADDRESS;
- struct xloader_table_1_1 *table_1_1;
- struct xloader_table_1_2 *table_1_2;
- struct chip_data *chip = &chip_data;
-
+ /* Store complete RAM size and return */
gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE);
- if (XLOADER_TABLE_VERSION_1_1 == xloader_tb->table_version) {
- table_1_1 = &xloader_tb->table.table_1_1;
- chip->dramfreq = table_1_1->ddrfreq;
- chip->dramtype = table_1_1->ddrtype;
-
- } else if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) {
- table_1_2 = &xloader_tb->table.table_1_2;
- chip->dramfreq = table_1_2->ddrfreq;
- chip->dramtype = table_1_2->ddrtype;
- } else {
- chip->dramfreq = -1;
- }
-
return 0;
}
gd->bd->bi_dram[0].size = gd->ram_size;
}
+int board_early_init_f()
+{
+#if defined(CONFIG_ST_SMI)
+ smi_init();
+#endif
+ return 0;
+}
int misc_init_r(void)
{
#if defined(CONFIG_CMD_NET)
setenv("stdin", "usbtty");
setenv("stdout", "usbtty");
setenv("stderr", "usbtty");
+
+#ifndef CONFIG_SYS_NO_DCACHE
+ dcache_enable();
+#endif
#endif
return 0;
}
int spear_board_init(ulong mach_type)
{
- struct xloader_table *xloader_tb =
- (struct xloader_table *)XLOADER_TABLE_ADDRESS;
- struct xloader_table_1_2 *table_1_2;
- struct chip_data *chip = &chip_data;
-
gd->bd->bi_arch_number = mach_type;
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
- /* CPU is initialized to work at 333MHz in Xloader */
- chip->cpufreq = 333;
-
- if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) {
- table_1_2 = &xloader_tb->table.table_1_2;
- memcpy(chip->version, table_1_2->version,
- sizeof(chip->version));
- }
-
#ifdef CONFIG_SPEAR_EMI
spear_emi_init();
#endif
return 0;
}
+#if defined(CONFIG_CMD_NET)
static int i2c_read_mac(uchar *buffer)
{
u8 buf[2];
return 0;
}
- puts("I2C EEPROM writing failed \n");
+ puts("I2C EEPROM writing failed\n");
return -1;
}
+#endif
int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
void (*sram_setfreq) (unsigned int, unsigned int);
- struct chip_data *chip = &chip_data;
+ unsigned int frequency;
+#if defined(CONFIG_CMD_NET)
unsigned char mac[6];
- unsigned int reg, frequency;
- char *s, *e;
- char i2c_mac[20];
+#endif
if ((argc > 3) || (argc < 2))
return cmd_usage(cmdtp);
if (!strcmp(argv[1], "cpufreq")) {
sram_setfreq(CPU, frequency);
printf("CPU frequency changed to %u\n", frequency);
-
- chip->cpufreq = frequency;
} else {
sram_setfreq(DDR, frequency);
printf("DDR frequency changed to %u\n", frequency);
-
- chip->dramfreq = frequency;
}
return 0;
+
+#if defined(CONFIG_CMD_NET)
} else if (!strcmp(argv[1], "ethaddr")) {
- s = argv[2];
+ u32 reg;
+ char *e, *s = argv[2];
for (reg = 0; reg < 6; ++reg) {
mac[reg] = s ? simple_strtoul(s, &e, 16) : 0;
if (s)
write_mac(mac);
return 0;
+#endif
} else if (!strcmp(argv[1], "print")) {
-
- if (chip->cpufreq == -1)
- printf("CPU Freq = Not Known\n");
- else
- printf("CPU Freq = %d MHz\n", chip->cpufreq);
-
- if (chip->dramfreq == -1)
- printf("DDR Freq = Not Known\n");
- else
- printf("DDR Freq = %d MHz\n", chip->dramfreq);
-
- if (chip->dramtype == DDRMOBILE)
- printf("DDR Type = MOBILE\n");
- else if (chip->dramtype == DDR2)
- printf("DDR Type = DDR2\n");
- else
- printf("DDR Type = Not Known\n");
-
+#if defined(CONFIG_CMD_NET)
if (!i2c_read_mac(mac)) {
- sprintf(i2c_mac, "%pM", mac);
- printf("Ethaddr (from i2c mem) = %s\n", i2c_mac);
+ printf("Ethaddr (from i2c mem) = %pM\n", mac);
} else {
printf("Ethaddr (from i2c mem) = Not set\n");
}
-
- printf("Xloader Rev = %s\n", chip->version);
-
+#endif
return 0;
}
U_BOOT_CMD(chip_config, 3, 1, do_chip_config,
"configure chip",
"chip_config cpufreq/ddrfreq frequency\n"
+#if defined(CONFIG_CMD_NET)
+ "chip_config ethaddr XX:XX:XX:XX:XX:XX\n"
+#endif
"chip_config print");
*/
#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
#include <nand.h>
#include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_defs.h>
#include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_nand.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
int board_init(void)
{
* Called by nand_init_chip to initialize the board specific functions
*/
-int board_nand_init(struct nand_chip *nand)
+void board_nand_init()
{
struct misc_regs *const misc_regs_p =
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ struct nand_chip *nand = &nand_chip[0];
+#if defined(CONFIG_NAND_FSMC)
if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
MISC_SOCCFG30) ||
((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
MISC_SOCCFG31)) {
- return spear_nand_init(nand);
+ fsmc_nand_init(nand);
}
+#endif
+ return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
- return -1;
+#if defined(CONFIG_DESIGNWARE_ETH)
+ u32 interface = PHY_INTERFACE_MODE_MII;
+ if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
+ interface) >= 0)
+ ret++;
+#endif
+ return ret;
}
*/
#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
#include <nand.h>
#include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_defs.h>
#include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_nand.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
int board_init(void)
{
* Called by nand_init_chip to initialize the board specific functions
*/
-int board_nand_init(struct nand_chip *nand)
+void board_nand_init()
{
struct misc_regs *const misc_regs_p =
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ struct nand_chip *nand = &nand_chip[0];
+#if defined(CONFIG_NAND_FSMC)
if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
MISC_SOCCFG30) ||
((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
MISC_SOCCFG31)) {
- return spear_nand_init(nand);
+ fsmc_nand_init(nand);
}
+#endif
+ return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#if defined(CONFIG_DESIGNWARE_ETH)
+ u32 interface = PHY_INTERFACE_MODE_MII;
+ if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
+ interface) >= 0)
+ ret++;
+#endif
+#if defined(CONFIG_MACB)
+ if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
+ CONFIG_MACB0_PHY) >= 0)
+ ret++;
+
+ if (macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE,
+ CONFIG_MACB1_PHY) >= 0)
+ ret++;
+
+ if (macb_eth_initialize(2, (void *)CONFIG_SYS_MACB2_BASE,
+ CONFIG_MACB2_PHY) >= 0)
+ ret++;
- return -1;
+ if (macb_eth_initialize(3, (void *)CONFIG_SYS_MACB3_BASE,
+ CONFIG_MACB3_PHY) >= 0)
+ ret++;
+#endif
+ return ret;
}
*/
#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
#include <nand.h>
#include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_defs.h>
#include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_nand.h>
+
+#define PLGPIO_SEL_36 0xb3000028
+#define PLGPIO_IO_36 0xb3000038
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+static void spear_phy_reset(void)
+{
+ writel(0x10, PLGPIO_IO_36);
+ writel(0x10, PLGPIO_SEL_36);
+}
int board_init(void)
{
+ spear_phy_reset();
return spear_board_init(MACH_TYPE_SPEAR320);
}
* Called by nand_init_chip to initialize the board specific functions
*/
-int board_nand_init(struct nand_chip *nand)
+void board_nand_init()
{
struct misc_regs *const misc_regs_p =
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ struct nand_chip *nand = &nand_chip[0];
+#if defined(CONFIG_NAND_FSMC)
if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
MISC_SOCCFG30) ||
((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
MISC_SOCCFG31)) {
- return spear_nand_init(nand);
+ fsmc_nand_init(nand);
}
+#endif
+
+ return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
- return -1;
+#if defined(CONFIG_DESIGNWARE_ETH)
+ u32 interface = PHY_INTERFACE_MODE_MII;
+ if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
+ interface) >= 0)
+ ret++;
+#endif
+#if defined(CONFIG_MACB)
+ if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
+ CONFIG_MACB0_PHY) >= 0)
+ ret++;
+#endif
+ return ret;
}
LIB = $(obj)lib$(BOARD).o
+ifndef CONFIG_SPL_BUILD
COBJS := spear600.o
+endif
SOBJS :=
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+++ /dev/null
-#
-# (C) Copyright 2009
-# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#########################################################################
-
-CONFIG_SYS_TEXT_BASE = 0x00700000
-
-ALL-y += $(obj)u-boot.img
-
-# Environment variables in NAND
-ifeq ($(ENV),NAND)
-PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
-else
-PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
-endif
-
-ifeq ($(CONSOLE),USB)
-PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
-endif
*/
#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
#include <nand.h>
#include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_defs.h>
#include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_nand.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
int board_init(void)
{
* Called by nand_init_chip to initialize the board specific functions
*/
-int board_nand_init(struct nand_chip *nand)
+void board_nand_init()
{
struct misc_regs *const misc_regs_p =
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ struct nand_chip *nand = &nand_chip[0];
+#if defined(CONFIG_NAND_FSMC)
if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
- return spear_nand_init(nand);
+ fsmc_nand_init(nand);
+#endif
+ return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
- return -1;
+#if defined(CONFIG_DESIGNWARE_ETH)
+ u32 interface = PHY_INTERFACE_MODE_MII;
+#if defined(CONFIG_DW_AUTONEG)
+ interface = PHY_INTERFACE_MODE_GMII;
+#endif
+ if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
+ interface) >= 0)
+ ret++;
+#endif
+ return ret;
}
/*
* Basic board specific setup
*/
-int init_basic_setup(void)
-{
- /* Initialize the Timer */
- init_timer();
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
-
- return 0;
-}
-
int board_init(void)
{
enable_uart0_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
- init_basic_setup();
+ gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
return 0;
}
{SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3*/
{UART3_RX_IRRX, (PTU | IEN | M0)}, /* UART3_RX_IRRX */
{UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */
+ {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */
+ {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */
+ {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */
+ {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */
+ {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/
+ {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */
+ {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */
+ {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */
+ {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */
};
{UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */
{UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */
{UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */
- {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */
- {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */
- {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */
- {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */
{TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */
{DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */
{DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */
{UART6_RTS, (PTU | M0)}, /* UART6_RTS */
{UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */
{UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */
- {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/
- {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */
- {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */
- {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */
- {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */
{I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */
{I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */
{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
-{UART3_TX_IRTX, (M0)} /* uart3_tx */
-
+{UART3_TX_IRTX, (M0)}, /* uart3_tx */
+{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
+{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
+{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
+{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
+{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */
+{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */
+{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */
+{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */
+{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */
+{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */
+{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */
};
const struct pad_conf_entry wkup_padconf_array_essential[] = {
{USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */
{USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */
{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */
- {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
- {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
- {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
- {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
- {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */
- {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */
- {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */
- {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */
{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */
{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */
{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */
{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */
{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */
{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */
- {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */
- {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */
- {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */
{FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */
{FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */
{SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */
COBJS := vision2.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH
snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260
snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20
+vl_ma2sc arm arm926ejs vl_ma2sc BuS at91
+vl_ma2sc_ram arm arm926ejs vl_ma2sc BuS at91 vl_ma2sc:RAMLOAD
sbc35_a9g20_eeprom arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM
sbc35_a9g20_nandflash arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH
tny_a9260_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_EEPROM
calimain arm arm926ejs calimain omicron davinci
pogo_e02 arm arm926ejs - cloudengines kirkwood
dns325 arm arm926ejs - d-link kirkwood
-km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_DISABLE_PCI
-km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_RECONFIG_XLX
-mgcoge3un arm arm926ejs km_arm keymile kirkwood
-portl2 arm arm926ejs km_arm keymile kirkwood
+lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2
+lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL
+km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD
+km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI
+kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA
+mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN
+kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN
+portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2
inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2
net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2
netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2
sheevaplug arm arm926ejs - Marvell kirkwood
ib62x0 arm arm926ejs ib62x0 raidsonic kirkwood
dockstar arm arm926ejs - Seagate kirkwood
+tk71 arm arm926ejs tk71 karo kirkwood
devkit3250 arm arm926ejs devkit3250 timll lpc32xx
jadecpu arm arm926ejs jadecpu syteco mb86r0x
mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg
omap730p2_cs3boot arm arm926ejs omap730p2 ti omap omap730p2:CS3_BOOT
edminiv2 arm arm926ejs - LaCie orion5x
dkb arm arm926ejs - Marvell pantheon
-spear300 arm arm926ejs spear300 spear spear spear3xx:spear300
-spear310 arm arm926ejs spear310 spear spear spear3xx:spear310
-spear320 arm arm926ejs spear320 spear spear spear3xx:spear320
-spear600 arm arm926ejs spear600 spear spear spear6xx:spear600
+spear300 arm arm926ejs spear300 spear spear spear3xx_evb:spear300
+spear300_nand arm arm926ejs spear300 spear spear spear3xx_evb:spear300,nand
+spear300_usbtty arm arm926ejs spear300 spear spear spear3xx_evb:spear300,usbtty
+spear300_usbtty_nand arm arm926ejs spear300 spear spear spear3xx_evb:spear300,usbtty,nand
+spear310 arm arm926ejs spear310 spear spear spear3xx_evb:spear310
+spear310_pnor arm arm926ejs spear310 spear spear spear3xx_evb:spear310,FLASH_PNOR
+spear310_nand arm arm926ejs spear310 spear spear spear3xx_evb:spear310,nand
+spear310_usbtty arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty
+spear310_usbtty_pnor arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty,FLASH_PNOR
+spear310_usbtty_nand arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty,nand
+spear320 arm arm926ejs spear320 spear spear spear3xx_evb:spear320
+spear320_pnor arm arm926ejs spear320 spear spear spear3xx_evb:spear320,FLASH_PNOR
+spear320_nand arm arm926ejs spear320 spear spear spear3xx_evb:spear320,nand
+spear320_usbtty arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty
+spear320_usbtty_pnor arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty,FLASH_PNOR
+spear320_usbtty_nand arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty,nand
+spear600 arm arm926ejs spear600 spear spear spear6xx_evb:spear600
+spear600_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,nand
+spear600_usbtty arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty
+spear600_usbtty_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty,nand
versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB
versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB
versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB
harmony arm armv7 harmony nvidia tegra2
seaboard arm armv7 seaboard nvidia tegra2
ventana arm armv7 ventana nvidia tegra2
+whistler arm armv7 whistler nvidia tegra2
u8500_href arm armv7 u8500 st-ericsson u8500
actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2
actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB
plutux arm armv7 plutux avionic-design tegra2
medcom arm armv7 medcom avionic-design tegra2
paz00 arm armv7 paz00 compal tegra2
+trimslice arm armv7 trimslice compulab tegra2
atngw100 avr32 at32ap - atmel at32ap700x
atstk1002 avr32 at32ap atstk1000 atmel at32ap700x
atstk1003 avr32 at32ap atstk1000 atmel at32ap700x
COBJS-y += command.o
COBJS-y += exports.o
COBJS-$(CONFIG_SYS_HUSH_PARSER) += hush.o
-COBJS-y += image.o
COBJS-y += s_record.o
COBJS-$(CONFIG_SERIAL_MULTI) += serial.o
COBJS-y += xyzModem.o
endif
COBJS-y += console.o
COBJS-y += dlmalloc.o
+COBJS-y += image.o
COBJS-y += memsize.o
COBJS-y += stdio.o
int saveenv(void)
{
- env_t env_new;
+ ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1);
ssize_t len;
char *res;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
if (init_mmc_for_env(mmc) || mmc_get_env_addr(mmc, &offset))
return 1;
- res = (char *)&env_new.data;
+ res = (char *)&env_new->data;
len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
}
- env_new.crc = crc32(0, env_new.data, ENV_SIZE);
+ env_new->crc = crc32(0, &env_new->data[0], ENV_SIZE);
printf("Writing to MMC(%d)... ", CONFIG_SYS_MMC_ENV_DEV);
- if (write_env(mmc, CONFIG_ENV_SIZE, offset, (u_char *)&env_new)) {
+ if (write_env(mmc, CONFIG_ENV_SIZE, offset, (u_char *)env_new)) {
puts("failed\n");
return 1;
}
void env_relocate_spec(void)
{
#if !defined(ENV_IS_EMBEDDED)
- char buf[CONFIG_ENV_SIZE];
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
u32 offset;
CPPFLAGS += -DCONFIG_SPL_TEXT_BASE=$(CONFIG_SPL_TEXT_BASE)
endif
+ifneq ($(CONFIG_SPL_PAD_TO),)
+CPPFLAGS += -DCONFIG_SPL_PAD_TO=$(CONFIG_SPL_PAD_TO)
+endif
+
ifeq ($(CONFIG_SPL_BUILD),y)
CPPFLAGS += -DCONFIG_SPL_BUILD
endif
To boot MX28EVK from an SD card, set the boot mode DIP switches as:
* Boot Mode Select: 1 0 0 1 (Boot from SD card Slot 0 - U42)
- * JTAG PSWITCH RESET: To the left (reset enabled)
+ * JTAG PSWITCH RESET: To the right (reset disabled)
* Battery Source: Down
* Wall 5V: Up
* VDD 5V: To the left (off)
The SPEAr SoC family embeds a customizable logic that can be programmed
one-time by a customer at silicon mask level (i.e. not at runtime!).
-We are now adding the support in u-boot for two SoC: SPEAr600 and SPEAr3xx.
+U-Boot supports four SoCs: SPEAr600, SPEAr3xx
-All 4 SoCs share common peripherals.
+All 4 SoCs (SPEAr3xx and SPEAr600) share common peripherals. SPEAr300 and
+SPEAr600 do not have EMI.
1. ARM926ejs core based (sp600 has two cores, the 2nd handled only in Linux)
2. FastEthernet (sp600 has Gbit version, but same controller - GMAC)
10. others ..
Everything is supported in Linux.
-u-boot is not currently supporting all peripeharls (just a few as listed below).
+u-boot is currently not supporting all peripeharls (just a few as listed below).
1. USB Device
2. NAND controller (FSMC)
3. Serial Memory Interface
5. UART
Build options
- make spear600_config
+ make spear320_config
+ spear320 build with environment variables placed at default
+ location i.e. Serial NOR device
+ make spear320_pnor_config
+ This option generates a uboot image that supports emi controller
+ for CFI compliant parallel NOR flash. Environment variables are
+ placed in Parallel NOR device
+ make spear320_nand_config
+ spear320 build with environment variables placed in NAND device
+ make spear320_usbtty_config
+ spear320 build with usbtty terminal as default and environment
+ placed at default location
+ make spear320_usbtty_pnor_config
+ spear320 build with usbtty terminal as default and environment
+ placed in pnor device
+ make spear320_usbtty_nand_config
+ Build with usbtty terminal as default and environment placed in
+ NAND device
make spear300_config
+ make spear300_nand_config
+ make spear300_usbtty_config
+ make spear300_usbtty_nand_config
make spear310_config
- make spear320_config
-
-Further options
- make ENV=NAND (supported by all 4 SoCs)
- - This option generates a uboot image that saves environment inn NAND
+ make spear310_pnor_config
+ make spear310_nand_config
+ make spear310_usbtty_config
+ make spear310_usbtty_pnor_config
+ make spear310_usbtty_nand_config
+ make spear600_config
+ make spear600_nand_config
+ make spear600_usbtty_config
+ make spear600_usbtty_nand_config
- make CONSOLE=USB (supported by all 4 SoCs)
- - This option generates a uboot image for using usbdevice as a tty i/f
+Mac id storage and retrieval in spear platforms
- make FLASH=PNOR (supported by SPEAr310 and SPEAr320)
- - This option generates a uboot image that supports emi controller for
- CFI compliant parallel NOR flash
+Please read doc/README.enetaddr for the implementation guidelines for mac id
+usage. Basically, environment has precedence over board specific storage. The
+ethaddr beeing used for the network interface is always taken only from
+environment variables. Although, we can check the mac id programmed in i2c
+memory by using chip_config command
--- /dev/null
+On the enbw_cmc board is a KSZ8864RMN switch which needs
+configured through spi before working. This is done on
+startup from u-boot through a config file stored at an
+address specified in the "hwconfig" environment variable,
+subcommand "config".
+
+For example on the enbw_cmc board:
+
+hwconfig=switch:lan=on,pwl=off,config=0x60160000
+
+The file has the following structure:
+
+- a comment starts with a '#' or a ';' and ends with a newline
+- The switch needs for its config a reg/value pair, so we
+ have two columns in the file:
+ reg : contains the register address
+ value: contains a 8 bit register value
+ This 2 columns are seperated through space or tab.
+
+example (minimal configuration on the enbw_cmc board):
+
+;reg value comment
+;-----------------------------------------
+0x01 0x00
+0x01 0x01 ; Start Switch with this configuration
--- /dev/null
+.TH KWBOOT 1 "2012-05-19"
+
+.SH NAME
+kwboot \- Boot Marvell Kirkwood SoCs over a serial link.
+.SH SYNOPSIS
+.B kwboot
+.RB [ "-b \fIimage\fP" ]
+.RB [ "-p" ]
+.RB [ "-t" ]
+.RB [ "-B \fIbaudrate\fP" ]
+.RB \fITTY\fP
+.SH "DESCRIPTION"
+
+The \fBmkimage\fP program boots boards based on Marvell's Kirkwood
+platform over their integrated UART. Boot image files will typically
+contain a second stage boot loader, such as U-Boot. The image file
+must conform to Marvell's BootROM firmware image format
+(\fIkwbimage\fP), created using a tool such as \fBmkimage\fP.
+
+Following power-up or a system reset, system BootROM code polls the
+UART for a brief period of time, sensing a handshake message which
+initiates an image upload. This program sends this boot message until
+it receives a positive acknowledgement. The image is transfered using
+Xmodem.
+
+Additionally, this program implements a minimal terminal mode, which
+can be used either standalone, or entered immediately following boot
+image transfer completion. This is often useful to catch early boot
+messages, or to manually interrupt a default boot procedure performed
+by the second-stage loader.
+
+.SH "OPTIONS"
+
+.TP
+.BI "\-b \fIimage\fP"
+Handshake; then upload file \fIimage\fP over \fITTY\fP.
+
+Note that for the encapsulated boot code to be executed, \fIimage\fP
+must be of type "UART boot" (0x69). Boot images of different types,
+such as backup images of vendor firmware downloaded from flash memory
+(type 0x8B), will not work (or not as expected). See \fB-p\fP for a
+workaround.
+
+This mode writes handshake status and upload progress indication to
+stdout.
+
+.TP
+.BI "\-p"
+In combination with \fB-b\fP, patches the header in \fIimage\fP prior
+to upload, to "UART boot" type.
+
+This option attempts on-the-fly conversion of some none-UART image
+types, such as images which were originally formatted to be stored in
+flash memory.
+
+Conversion is performed in memory. The contents of \fIimage\fP will
+not be altered.
+
+.TP
+.BI "\-t"
+Run a terminal program, connecting standard input and output to
+.RB \fITTY\fP.
+
+If used in combination with \fB-b\fP, terminal mode is entered
+immediately following a successful image upload.
+
+If standard I/O streams connect to a console, this mode will terminate
+after receiving 'ctrl-\\' followed by 'c' from console input.
+
+.TP
+.BI "\-B \fIbaudrate\fP"
+Adjust the baud rate on \fITTY\fP. Default rate is 115200.
+
+.SH "SEE ALSO"
+.PP
+\fBmkimage\fP(1)
+
+.SH "AUTHORS"
+
+Daniel Stodden <daniel.stodden@gmail.com>
+.br
+Luka Perkov <uboot@lukaperkov.net>
+.br
+David Purdy <david.c.purdy@gmail.com>
COBJS-$(CONFIG_PCA9698) += pca9698.o
COBJS-$(CONFIG_S5P) += s5p_gpio.o
COBJS-$(CONFIG_SANDBOX_GPIO) += sandbox.o
-COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o
+COBJS-$(CONFIG_SPEAR_GPIO) += spear_gpio.o
+COBJS-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o
COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
mask = 1 << pin;
writel(mask, &pio->port[port].idr);
at91_set_pio_pullup(port, pin, use_pullup);
+#if defined(CPU_HAS_PIO3)
+ writel(readl(&pio->port[port].abcdsr1) & ~mask,
+ &pio->port[port].abcdsr1);
+ writel(readl(&pio->port[port].abcdsr2) & ~mask,
+ &pio->port[port].abcdsr2);
+#else
writel(mask, &pio->port[port].asr);
+#endif
writel(mask, &pio->port[port].pdr);
}
return 0;
mask = 1 << pin;
writel(mask, &pio->port[port].idr);
at91_set_pio_pullup(port, pin, use_pullup);
+#if defined(CPU_HAS_PIO3)
+ writel(readl(&pio->port[port].abcdsr1) | mask,
+ &pio->port[port].abcdsr1);
+ writel(readl(&pio->port[port].abcdsr2) & ~mask,
+ &pio->port[port].abcdsr2);
+#else
writel(mask, &pio->port[port].bsr);
+#endif
writel(mask, &pio->port[port].pdr);
}
return 0;
}
+#if defined(CPU_HAS_PIO3)
+/*
+ * mux the pin to the "C" internal peripheral role.
+ */
+int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
+{
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
+ u32 mask;
+
+ if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ mask = 1 << pin;
+ writel(mask, &pio->port[port].idr);
+ at91_set_pio_pullup(port, pin, use_pullup);
+ writel(readl(&pio->port[port].abcdsr1) & ~mask,
+ &pio->port[port].abcdsr1);
+ writel(readl(&pio->port[port].abcdsr2) | mask,
+ &pio->port[port].abcdsr2);
+ writel(mask, &pio->port[port].pdr);
+ }
+ return 0;
+}
+
+/*
+ * mux the pin to the "D" internal peripheral role.
+ */
+int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup)
+{
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
+ u32 mask;
+
+ if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ mask = 1 << pin;
+ writel(mask, &pio->port[port].idr);
+ at91_set_pio_pullup(port, pin, use_pullup);
+ writel(readl(&pio->port[port].abcdsr1) | mask,
+ &pio->port[port].abcdsr1);
+ writel(readl(&pio->port[port].abcdsr2) | mask,
+ &pio->port[port].abcdsr2);
+ writel(mask, &pio->port[port].pdr);
+ }
+ return 0;
+}
+#endif
+
/*
* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
* configure it for an input.
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
mask = 1 << pin;
- if (is_on)
+ if (is_on) {
+#if defined(CPU_HAS_PIO3)
+ writel(mask, &pio->port[port].ifscdr);
+#endif
writel(mask, &pio->port[port].ifer);
- else
+ } else {
writel(mask, &pio->port[port].ifdr);
+ }
+ }
+ return 0;
+}
+
+#if defined(CPU_HAS_PIO3)
+/*
+ * enable/disable the debounce filter.
+ */
+int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
+{
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
+ u32 mask;
+
+ if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ mask = 1 << pin;
+ if (is_on) {
+ writel(mask, &pio->port[port].ifscer);
+ writel(div & PIO_SCDR_DIV, &pio->port[port].scdr);
+ writel(mask, &pio->port[port].ifer);
+ } else {
+ writel(mask, &pio->port[port].ifdr);
+ }
+ }
+ return 0;
+}
+
+/*
+ * enable/disable the pull-down.
+ * If pull-up already enabled while calling the function, we disable it.
+ */
+int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
+{
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
+ u32 mask;
+
+ if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ mask = 1 << pin;
+ writel(mask, &pio->port[port].pudr);
+ if (is_on)
+ writel(mask, &pio->port[port].ppder);
+ else
+ writel(mask, &pio->port[port].ppddr);
+ }
+ return 0;
+}
+
+/*
+ * disable Schmitt trigger
+ */
+int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
+{
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
+ u32 mask;
+
+ if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ mask = 1 << pin;
+ writel(readl(&pio->port[port].schmitt) | mask,
+ &pio->port[port].schmitt);
}
return 0;
}
+#endif
/*
* enable/disable the multi-driver. This is only valid for output and
--- /dev/null
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Driver for SPEAr600 GPIO controller
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <errno.h>
+
+static int gpio_direction(unsigned gpio,
+ enum gpio_direction direction)
+{
+ struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
+ u32 val;
+
+ val = readl(®s->gpiodir);
+
+ if (direction == GPIO_DIRECTION_OUT)
+ val |= 1 << gpio;
+ else
+ val &= ~(1 << gpio);
+
+ writel(val, ®s->gpiodir);
+
+ return 0;
+}
+
+int gpio_set_value(unsigned gpio, int value)
+{
+ struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
+
+ writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
+
+ return 0;
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
+ u32 val;
+
+ val = readl(®s->gpiodata[DATA_REG_ADDR(gpio)]);
+
+ return !!val;
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+ if (gpio >= SPEAR_GPIO_COUNT)
+ return -EINVAL;
+
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
+void gpio_toggle_value(unsigned gpio)
+{
+ gpio_set_value(gpio, !gpio_get_value(gpio));
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ return gpio_direction(gpio, GPIO_DIRECTION_IN);
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ int ret = gpio_direction(gpio, GPIO_DIRECTION_OUT);
+
+ if (ret < 0)
+ return ret;
+
+ gpio_set_value(gpio, value);
+ return 0;
+}
/*
* NVIDIA Tegra2 GPIO handling.
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010-2012
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
*
* Set the i2c speed.
*/
-void i2c_set_bus_speed(int speed)
+int i2c_set_bus_speed(int speed)
{
if (speed >= I2C_MAX_SPEED)
set_speed(IC_SPEED_MODE_MAX);
set_speed(IC_SPEED_MODE_FAST);
else
set_speed(IC_SPEED_MODE_STANDARD);
+
+ return 0;
}
/*
static int i2c_xfer_init(uchar chip, uint addr)
{
- if (i2c_wait_for_bb()) {
- printf("Timed out waiting for bus\n");
+ if (i2c_wait_for_bb())
return 1;
- }
i2c_setaddress(chip);
writel(addr, &i2c_regs_p->ic_cmd_data);
start_time_rx = get_timer(0);
} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
- printf("Timed out. i2c read Failed\n");
return 1;
}
}
int i2c_probe(uchar chip)
{
u32 tmp;
+ int ret;
/*
* Try to read the first location of the chip.
*/
- return i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
+ ret = i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
+ if (ret)
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ return ret;
}
}
if (status & I2C_STAT_RRDY) {
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
- defined(CONFIG_OMAP44XX)
+ defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX)
*value = readb(&i2c_base->data);
#else
*value = readw(&i2c_base->data);
stat = readw(&i2c_base->stat);
if (stat == I2C_STAT_RRDY) {
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
- defined(CONFIG_OMAP44XX)
+ defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX)
readb(&i2c_base->data);
#else
readw(&i2c_base->data);
/* wait until bus not busy */
wait_for_bb();
- /* try to write one byte */
+ /* try to read one byte */
writew(1, &i2c_base->cnt);
/* set slave address */
writew(chip, &i2c_base->sa);
/* stop bit needed here */
- writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
- I2C_CON_STP, &i2c_base->con);
-
- status = wait_for_pin();
+ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con);
- /* check for ACK (!NAK) */
- if (!(status & I2C_STAT_NACK))
- res = 0;
-
- /* abort transfer (force idle state) */
- writew(0, &i2c_base->con);
+ while (1) {
+ status = wait_for_pin();
+ if (status == 0 || status & I2C_STAT_AL) {
+ res = 1;
+ goto probe_exit;
+ }
+ if (status & I2C_STAT_NACK) {
+ res = 1;
+ writew(0xff, &i2c_base->stat);
+ writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con);
+ wait_for_bb ();
+ break;
+ }
+ if (status & I2C_STAT_ARDY) {
+ writew(I2C_STAT_ARDY, &i2c_base->stat);
+ break;
+ }
+ if (status & I2C_STAT_RRDY) {
+ res = 0;
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
+ defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX)
+ readb(&i2c_base->data);
+#else
+ readw(&i2c_base->data);
+#endif
+ writew(I2C_STAT_RRDY, &i2c_base->stat);
+ }
+ }
+probe_exit:
flush_fifo();
/* don't allow any more data in... we don't want it. */
writew(0, &i2c_base->cnt);
COBJS-$(CONFIG_SDHCI) += sdhci.o
COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o
-COBJS-$(CONFIG_TEGRA2_MMC) += tegra2_mmc.o
+COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Jaehoon Chung <jh80.chung@samsung.com>
- * Portions Copyright 2011 NVIDIA Corporation
+ * Portions Copyright 2011-2012 NVIDIA Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <asm/io.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
-#include "tegra2_mmc.h"
+#include "tegra_mmc.h"
/* support 4 mmc hosts */
struct mmc mmc_dev[4];
/*
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang <mk7.kang@samsung.com>
- * Portions Copyright (C) 2011 NVIDIA Corporation
+ * Portions Copyright (C) 2011-2012 NVIDIA Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
*
*/
-#ifndef __TEGRA2_MMC_H_
-#define __TEGRA2_MMC_H_
+#ifndef __TEGRA_MMC_H_
+#define __TEGRA_MMC_H_
#define TEGRA2_SDMMC1_BASE 0xC8000000
#define TEGRA2_SDMMC2_BASE 0xC8000200
};
#endif /* __ASSEMBLY__ */
-#endif /* __TEGRA2_MMC_H_ */
+#endif /* __TEGRA_MMC_H_ */
COBJS-$(CONFIG_FTSMC020) += ftsmc020.o
COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o
-COBJS-$(CONFIG_SPEARSMI) += spr_smi.o
+COBJS-$(CONFIG_ST_SMI) += st_smi.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
+COBJS-$(CONFIG_NAND_FSMC) += fsmc_nand.o
COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com.
+ *
+ * (C) Copyright 2012
+ * Amit Virdi, ST Microelectronics, amit.virdi@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/fsmc_nand.h>
+#include <asm/arch/hardware.h>
+
+static u32 fsmc_version;
+static struct fsmc_regs *const fsmc_regs_p = (struct fsmc_regs *)
+ CONFIG_SYS_FSMC_BASE;
+
+/*
+ * ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of
+ * data. ECC4 can correct up to 8 bits in 512 bytes of data while ECC1 can
+ * correct 1 bit in 512 bytes
+ */
+
+static struct nand_ecclayout fsmc_ecc4_lp_layout = {
+ .eccbytes = 104,
+ .eccpos = { 2, 3, 4, 5, 6, 7, 8,
+ 9, 10, 11, 12, 13, 14,
+ 18, 19, 20, 21, 22, 23, 24,
+ 25, 26, 27, 28, 29, 30,
+ 34, 35, 36, 37, 38, 39, 40,
+ 41, 42, 43, 44, 45, 46,
+ 50, 51, 52, 53, 54, 55, 56,
+ 57, 58, 59, 60, 61, 62,
+ 66, 67, 68, 69, 70, 71, 72,
+ 73, 74, 75, 76, 77, 78,
+ 82, 83, 84, 85, 86, 87, 88,
+ 89, 90, 91, 92, 93, 94,
+ 98, 99, 100, 101, 102, 103, 104,
+ 105, 106, 107, 108, 109, 110,
+ 114, 115, 116, 117, 118, 119, 120,
+ 121, 122, 123, 124, 125, 126
+ },
+ .oobfree = {
+ {.offset = 15, .length = 3},
+ {.offset = 31, .length = 3},
+ {.offset = 47, .length = 3},
+ {.offset = 63, .length = 3},
+ {.offset = 79, .length = 3},
+ {.offset = 95, .length = 3},
+ {.offset = 111, .length = 3},
+ {.offset = 127, .length = 1}
+ }
+};
+
+/*
+ * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
+ * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
+ * bytes are free for use.
+ */
+static struct nand_ecclayout fsmc_ecc4_224_layout = {
+ .eccbytes = 104,
+ .eccpos = { 2, 3, 4, 5, 6, 7, 8,
+ 9, 10, 11, 12, 13, 14,
+ 18, 19, 20, 21, 22, 23, 24,
+ 25, 26, 27, 28, 29, 30,
+ 34, 35, 36, 37, 38, 39, 40,
+ 41, 42, 43, 44, 45, 46,
+ 50, 51, 52, 53, 54, 55, 56,
+ 57, 58, 59, 60, 61, 62,
+ 66, 67, 68, 69, 70, 71, 72,
+ 73, 74, 75, 76, 77, 78,
+ 82, 83, 84, 85, 86, 87, 88,
+ 89, 90, 91, 92, 93, 94,
+ 98, 99, 100, 101, 102, 103, 104,
+ 105, 106, 107, 108, 109, 110,
+ 114, 115, 116, 117, 118, 119, 120,
+ 121, 122, 123, 124, 125, 126
+ },
+ .oobfree = {
+ {.offset = 15, .length = 3},
+ {.offset = 31, .length = 3},
+ {.offset = 47, .length = 3},
+ {.offset = 63, .length = 3},
+ {.offset = 79, .length = 3},
+ {.offset = 95, .length = 3},
+ {.offset = 111, .length = 3},
+ {.offset = 127, .length = 97}
+ }
+};
+
+/*
+ * ECC placement definitions in oobfree type format
+ * There are 13 bytes of ecc for every 512 byte block and it has to be read
+ * consecutively and immediately after the 512 byte data block for hardware to
+ * generate the error bit offsets in 512 byte data
+ * Managing the ecc bytes in the following way makes it easier for software to
+ * read ecc bytes consecutive to data bytes. This way is similar to
+ * oobfree structure maintained already in u-boot nand driver
+ */
+static struct fsmc_eccplace fsmc_eccpl_lp = {
+ .eccplace = {
+ {.offset = 2, .length = 13},
+ {.offset = 18, .length = 13},
+ {.offset = 34, .length = 13},
+ {.offset = 50, .length = 13},
+ {.offset = 66, .length = 13},
+ {.offset = 82, .length = 13},
+ {.offset = 98, .length = 13},
+ {.offset = 114, .length = 13}
+ }
+};
+
+static struct nand_ecclayout fsmc_ecc4_sp_layout = {
+ .eccbytes = 13,
+ .eccpos = { 0, 1, 2, 3, 6, 7, 8,
+ 9, 10, 11, 12, 13, 14
+ },
+ .oobfree = {
+ {.offset = 15, .length = 1},
+ }
+};
+
+static struct fsmc_eccplace fsmc_eccpl_sp = {
+ .eccplace = {
+ {.offset = 0, .length = 4},
+ {.offset = 6, .length = 9}
+ }
+};
+
+static struct nand_ecclayout fsmc_ecc1_layout = {
+ .eccbytes = 24,
+ .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
+ 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
+ .oobfree = {
+ {.offset = 8, .length = 8},
+ {.offset = 24, .length = 8},
+ {.offset = 40, .length = 8},
+ {.offset = 56, .length = 8},
+ {.offset = 72, .length = 8},
+ {.offset = 88, .length = 8},
+ {.offset = 104, .length = 8},
+ {.offset = 120, .length = 8}
+ }
+};
+
+/* Count the number of 0's in buff upto a max of max_bits */
+static int count_written_bits(uint8_t *buff, int size, int max_bits)
+{
+ int k, written_bits = 0;
+
+ for (k = 0; k < size; k++) {
+ written_bits += hweight8(~buff[k]);
+ if (written_bits > max_bits)
+ break;
+ }
+
+ return written_bits;
+}
+
+static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+ ulong IO_ADDR_W;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ IO_ADDR_W = (ulong)this->IO_ADDR_W;
+
+ IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE);
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= CONFIG_SYS_NAND_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= CONFIG_SYS_NAND_ALE;
+
+ if (ctrl & NAND_NCE) {
+ writel(readl(&fsmc_regs_p->pc) |
+ FSMC_ENABLE, &fsmc_regs_p->pc);
+ } else {
+ writel(readl(&fsmc_regs_p->pc) &
+ ~FSMC_ENABLE, &fsmc_regs_p->pc);
+ }
+ this->IO_ADDR_W = (void *)IO_ADDR_W;
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+static int fsmc_bch8_correct_data(struct mtd_info *mtd, u_char *dat,
+ u_char *read_ecc, u_char *calc_ecc)
+{
+ /* The calculated ecc is actually the correction index in data */
+ u32 err_idx[8];
+ u32 num_err, i;
+ u32 ecc1, ecc2, ecc3, ecc4;
+
+ num_err = (readl(&fsmc_regs_p->sts) >> 10) & 0xF;
+
+ if (likely(num_err == 0))
+ return 0;
+
+ if (unlikely(num_err > 8)) {
+ /*
+ * This is a temporary erase check. A newly erased page read
+ * would result in an ecc error because the oob data is also
+ * erased to FF and the calculated ecc for an FF data is not
+ * FF..FF.
+ * This is a workaround to skip performing correction in case
+ * data is FF..FF
+ *
+ * Logic:
+ * For every page, each bit written as 0 is counted until these
+ * number of bits are greater than 8 (the maximum correction
+ * capability of FSMC for each 512 + 13 bytes)
+ */
+
+ int bits_ecc = count_written_bits(read_ecc, 13, 8);
+ int bits_data = count_written_bits(dat, 512, 8);
+
+ if ((bits_ecc + bits_data) <= 8) {
+ if (bits_data)
+ memset(dat, 0xff, 512);
+ return bits_data + bits_ecc;
+ }
+
+ return -EBADMSG;
+ }
+
+ ecc1 = readl(&fsmc_regs_p->ecc1);
+ ecc2 = readl(&fsmc_regs_p->ecc2);
+ ecc3 = readl(&fsmc_regs_p->ecc3);
+ ecc4 = readl(&fsmc_regs_p->sts);
+
+ err_idx[0] = (ecc1 >> 0) & 0x1FFF;
+ err_idx[1] = (ecc1 >> 13) & 0x1FFF;
+ err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
+ err_idx[3] = (ecc2 >> 7) & 0x1FFF;
+ err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
+ err_idx[5] = (ecc3 >> 1) & 0x1FFF;
+ err_idx[6] = (ecc3 >> 14) & 0x1FFF;
+ err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
+
+ i = 0;
+ while (i < num_err) {
+ err_idx[i] ^= 3;
+
+ if (err_idx[i] < 512 * 8)
+ __change_bit(err_idx[i], dat);
+
+ i++;
+ }
+
+ return num_err;
+}
+
+static int fsmc_read_hwecc(struct mtd_info *mtd,
+ const u_char *data, u_char *ecc)
+{
+ u_int ecc_tmp;
+ int timeout = CONFIG_SYS_HZ;
+ ulong start;
+
+ switch (fsmc_version) {
+ case FSMC_VER8:
+ start = get_timer(0);
+ while (get_timer(start) < timeout) {
+ /*
+ * Busy waiting for ecc computation
+ * to finish for 512 bytes
+ */
+ if (readl(&fsmc_regs_p->sts) & FSMC_CODE_RDY)
+ break;
+ }
+
+ ecc_tmp = readl(&fsmc_regs_p->ecc1);
+ ecc[0] = (u_char) (ecc_tmp >> 0);
+ ecc[1] = (u_char) (ecc_tmp >> 8);
+ ecc[2] = (u_char) (ecc_tmp >> 16);
+ ecc[3] = (u_char) (ecc_tmp >> 24);
+
+ ecc_tmp = readl(&fsmc_regs_p->ecc2);
+ ecc[4] = (u_char) (ecc_tmp >> 0);
+ ecc[5] = (u_char) (ecc_tmp >> 8);
+ ecc[6] = (u_char) (ecc_tmp >> 16);
+ ecc[7] = (u_char) (ecc_tmp >> 24);
+
+ ecc_tmp = readl(&fsmc_regs_p->ecc3);
+ ecc[8] = (u_char) (ecc_tmp >> 0);
+ ecc[9] = (u_char) (ecc_tmp >> 8);
+ ecc[10] = (u_char) (ecc_tmp >> 16);
+ ecc[11] = (u_char) (ecc_tmp >> 24);
+
+ ecc_tmp = readl(&fsmc_regs_p->sts);
+ ecc[12] = (u_char) (ecc_tmp >> 16);
+ break;
+
+ default:
+ ecc_tmp = readl(&fsmc_regs_p->ecc1);
+ ecc[0] = (u_char) (ecc_tmp >> 0);
+ ecc[1] = (u_char) (ecc_tmp >> 8);
+ ecc[2] = (u_char) (ecc_tmp >> 16);
+ break;
+ }
+
+ return 0;
+}
+
+void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+ writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCPLEN_256,
+ &fsmc_regs_p->pc);
+ writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCEN,
+ &fsmc_regs_p->pc);
+ writel(readl(&fsmc_regs_p->pc) | FSMC_ECCEN,
+ &fsmc_regs_p->pc);
+}
+
+/*
+ * fsmc_read_page_hwecc
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @page: page number to read
+ *
+ * This routine is needed for fsmc verison 8 as reading from NAND chip has to be
+ * performed in a strict sequence as follows:
+ * data(512 byte) -> ecc(13 byte)
+ * After this read, fsmc hardware generates and reports error data bits(upto a
+ * max of 8 bits)
+ */
+static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int page)
+{
+ struct fsmc_eccplace *fsmc_eccpl;
+ int i, j, s, stat, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ uint8_t *p = buf;
+ uint8_t *ecc_calc = chip->buffers->ecccalc;
+ uint8_t *ecc_code = chip->buffers->ecccode;
+ int off, len, group = 0;
+ uint8_t oob[13] __attribute__ ((aligned (2)));
+
+ /* Differentiate between small and large page ecc place definitions */
+ if (mtd->writesize == 512)
+ fsmc_eccpl = &fsmc_eccpl_sp;
+ else
+ fsmc_eccpl = &fsmc_eccpl_lp;
+
+ for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
+
+ chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
+ chip->ecc.hwctl(mtd, NAND_ECC_READ);
+ chip->read_buf(mtd, p, eccsize);
+
+ for (j = 0; j < eccbytes;) {
+ off = fsmc_eccpl->eccplace[group].offset;
+ len = fsmc_eccpl->eccplace[group].length;
+ group++;
+
+ /*
+ * length is intentionally kept a higher multiple of 2
+ * to read at least 13 bytes even in case of 16 bit NAND
+ * devices
+ */
+ if (chip->options & NAND_BUSWIDTH_16)
+ len = roundup(len, 2);
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
+ chip->read_buf(mtd, oob + j, len);
+ j += len;
+ }
+
+ memcpy(&ecc_code[i], oob, 13);
+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+ stat = chip->ecc.correct(mtd, p, &ecc_code[i],
+ &ecc_calc[i]);
+ if (stat < 0)
+ mtd->ecc_stats.failed++;
+ else
+ mtd->ecc_stats.corrected += stat;
+ }
+
+ return 0;
+}
+
+int fsmc_nand_init(struct nand_chip *nand)
+{
+ static int chip_nr;
+ struct mtd_info *mtd;
+ int i;
+ u32 peripid2 = readl(&fsmc_regs_p->peripid2);
+
+ fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) &
+ FSMC_REVISION_MSK;
+
+ writel(readl(&fsmc_regs_p->ctrl) | FSMC_WP, &fsmc_regs_p->ctrl);
+
+#if defined(CONFIG_SYS_FSMC_NAND_16BIT)
+ writel(FSMC_DEVWID_16 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,
+ &fsmc_regs_p->pc);
+#elif defined(CONFIG_SYS_FSMC_NAND_8BIT)
+ writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,
+ &fsmc_regs_p->pc);
+#else
+#error Please define CONFIG_SYS_FSMC_NAND_16BIT or CONFIG_SYS_FSMC_NAND_8BIT
+#endif
+ writel(readl(&fsmc_regs_p->pc) | FSMC_TCLR_1 | FSMC_TAR_1,
+ &fsmc_regs_p->pc);
+ writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
+ &fsmc_regs_p->comm);
+ writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
+ &fsmc_regs_p->attrib);
+
+ nand->options = 0;
+#if defined(CONFIG_SYS_FSMC_NAND_16BIT)
+ nand->options |= NAND_BUSWIDTH_16;
+#endif
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.size = 512;
+ nand->ecc.calculate = fsmc_read_hwecc;
+ nand->ecc.hwctl = fsmc_enable_hwecc;
+ nand->cmd_ctrl = fsmc_nand_hwcontrol;
+ nand->IO_ADDR_R = nand->IO_ADDR_W =
+ (void __iomem *)CONFIG_SYS_NAND_BASE;
+ nand->badblockbits = 7;
+
+ mtd = &nand_info[chip_nr++];
+ mtd->priv = nand;
+
+ switch (fsmc_version) {
+ case FSMC_VER8:
+ nand->ecc.bytes = 13;
+ nand->ecc.correct = fsmc_bch8_correct_data;
+ nand->ecc.read_page = fsmc_read_page_hwecc;
+ if (mtd->writesize == 512)
+ nand->ecc.layout = &fsmc_ecc4_sp_layout;
+ else {
+ if (mtd->oobsize == 224)
+ nand->ecc.layout = &fsmc_ecc4_224_layout;
+ else
+ nand->ecc.layout = &fsmc_ecc4_lp_layout;
+ }
+
+ break;
+ default:
+ nand->ecc.bytes = 3;
+ nand->ecc.layout = &fsmc_ecc1_layout;
+ nand->ecc.correct = nand_correct_data;
+ break;
+ }
+
+ /* Detect NAND chips */
+ if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL))
+ return -ENXIO;
+
+ if (nand_scan_tail(mtd))
+ return -ENXIO;
+
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ if (nand_register(i))
+ return -ENXIO;
+
+ return 0;
+}
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <nand.h>
-#include <linux/mtd/nand_ecc.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_nand.h>
-
-static struct fsmc_regs *const fsmc_regs_p =
- (struct fsmc_regs *)CONFIG_SPEAR_FSMCBASE;
-
-static struct nand_ecclayout spear_nand_ecclayout = {
- .eccbytes = 24,
- .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
- 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
- .oobfree = {
- {.offset = 8, .length = 8},
- {.offset = 24, .length = 8},
- {.offset = 40, .length = 8},
- {.offset = 56, .length = 8},
- {.offset = 72, .length = 8},
- {.offset = 88, .length = 8},
- {.offset = 104, .length = 8},
- {.offset = 120, .length = 8}
- }
-};
-
-static void spear_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
-{
- struct nand_chip *this = mtd->priv;
- ulong IO_ADDR_W;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- IO_ADDR_W = (ulong)this->IO_ADDR_W;
-
- IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE);
- if (ctrl & NAND_CLE)
- IO_ADDR_W |= CONFIG_SYS_NAND_CLE;
- if (ctrl & NAND_ALE)
- IO_ADDR_W |= CONFIG_SYS_NAND_ALE;
-
- if (ctrl & NAND_NCE) {
- writel(readl(&fsmc_regs_p->genmemctrl_pc) |
- FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc);
- } else {
- writel(readl(&fsmc_regs_p->genmemctrl_pc) &
- ~FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc);
- }
- this->IO_ADDR_W = (void *)IO_ADDR_W;
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-static int spear_read_hwecc(struct mtd_info *mtd,
- const u_char *data, u_char ecc[3])
-{
- u_int ecc_tmp;
-
- /* read the h/w ECC */
- ecc_tmp = readl(&fsmc_regs_p->genmemctrl_ecc);
-
- ecc[0] = (u_char) (ecc_tmp & 0xFF);
- ecc[1] = (u_char) ((ecc_tmp & 0xFF00) >> 8);
- ecc[2] = (u_char) ((ecc_tmp & 0xFF0000) >> 16);
-
- return 0;
-}
-
-void spear_enable_hwecc(struct mtd_info *mtd, int mode)
-{
- writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~0x80,
- &fsmc_regs_p->genmemctrl_pc);
- writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~FSMC_ECCEN,
- &fsmc_regs_p->genmemctrl_pc);
- writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_ECCEN,
- &fsmc_regs_p->genmemctrl_pc);
-}
-
-int spear_nand_init(struct nand_chip *nand)
-{
- writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,
- &fsmc_regs_p->genmemctrl_pc);
- writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_TCLR_1 | FSMC_TAR_1,
- &fsmc_regs_p->genmemctrl_pc);
- writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
- &fsmc_regs_p->genmemctrl_comm);
- writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
- &fsmc_regs_p->genmemctrl_attrib);
-
- nand->options = 0;
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.layout = &spear_nand_ecclayout;
- nand->ecc.size = 512;
- nand->ecc.bytes = 3;
- nand->ecc.calculate = spear_read_hwecc;
- nand->ecc.hwctl = spear_enable_hwecc;
- nand->ecc.correct = nand_correct_data;
- nand->cmd_ctrl = spear_nand_hwcontrol;
- return 0;
-}
.nr_blocks = 128,
.name = "W25X64",
},
+ {
+ .id = 0x4014,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 16,
+ .name = "W25Q80BL",
+ },
{
.id = 0x4015,
.l2_page_size = 8,
/*
* (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <common.h>
#include <flash.h>
#include <linux/err.h>
+#include <linux/mtd/st_smi.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
-#include <asm/arch/spr_smi.h>
#if !defined(CONFIG_SYS_NO_FLASH)
CONFIG_SYS_FLASH_ADDR_BASE;
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-#define ST_M25Pxx_ID 0x00002020
-
-static struct flash_dev flash_ids[] = {
- {0x10, 0x10000, 2}, /* 64K Byte */
- {0x11, 0x20000, 4}, /* 128K Byte */
- {0x12, 0x40000, 4}, /* 256K Byte */
- {0x13, 0x80000, 8}, /* 512K Byte */
- {0x14, 0x100000, 16}, /* 1M Byte */
- {0x15, 0x200000, 32}, /* 2M Byte */
- {0x16, 0x400000, 64}, /* 4M Byte */
- {0x17, 0x800000, 128}, /* 8M Byte */
- {0x18, 0x1000000, 64}, /* 16M Byte */
- {0x00,}
+/* data structure to maintain flash ids from different vendors */
+struct flash_device {
+ char *name;
+ u8 erase_cmd;
+ u32 device_id;
+ u32 pagesize;
+ unsigned long sectorsize;
+ unsigned long size_in_bytes;
+};
+
+#define FLASH_ID(n, es, id, psize, ssize, size) \
+{ \
+ .name = n, \
+ .erase_cmd = es, \
+ .device_id = id, \
+ .pagesize = psize, \
+ .sectorsize = ssize, \
+ .size_in_bytes = size \
+}
+
+/*
+ * List of supported flash devices.
+ * Currently the erase_cmd field is not used in this driver.
+ */
+static struct flash_device flash_devices[] = {
+ FLASH_ID("st m25p16" , 0xd8, 0x00152020, 0x100, 0x10000, 0x200000),
+ FLASH_ID("st m25p32" , 0xd8, 0x00162020, 0x100, 0x10000, 0x400000),
+ FLASH_ID("st m25p64" , 0xd8, 0x00172020, 0x100, 0x10000, 0x800000),
+ FLASH_ID("st m25p128" , 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000),
+ FLASH_ID("st m25p05" , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x10000),
+ FLASH_ID("st m25p10" , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x20000),
+ FLASH_ID("st m25p20" , 0xd8, 0x00122020, 0x100, 0x10000, 0x40000),
+ FLASH_ID("st m25p40" , 0xd8, 0x00132020, 0x100, 0x10000, 0x80000),
+ FLASH_ID("st m25p80" , 0xd8, 0x00142020, 0x100, 0x10000, 0x100000),
+ FLASH_ID("st m45pe10" , 0xd8, 0x00114020, 0x100, 0x10000, 0x20000),
+ FLASH_ID("st m45pe20" , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
+ FLASH_ID("st m45pe40" , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
+ FLASH_ID("st m45pe80" , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
+ FLASH_ID("sp s25fl004" , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
+ FLASH_ID("sp s25fl008" , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
+ FLASH_ID("sp s25fl016" , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000),
+ FLASH_ID("sp s25fl032" , 0xd8, 0x00150201, 0x100, 0x10000, 0x400000),
+ FLASH_ID("sp s25fl064" , 0xd8, 0x00160201, 0x100, 0x10000, 0x800000),
+ FLASH_ID("mac 25l512" , 0xd8, 0x001020C2, 0x010, 0x10000, 0x10000),
+ FLASH_ID("mac 25l1005" , 0xd8, 0x001120C2, 0x010, 0x10000, 0x20000),
+ FLASH_ID("mac 25l2005" , 0xd8, 0x001220C2, 0x010, 0x10000, 0x40000),
+ FLASH_ID("mac 25l4005" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
+ FLASH_ID("mac 25l4005a" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
+ FLASH_ID("mac 25l8005" , 0xd8, 0x001420C2, 0x010, 0x10000, 0x100000),
+ FLASH_ID("mac 25l1605" , 0xd8, 0x001520C2, 0x100, 0x10000, 0x200000),
+ FLASH_ID("mac 25l1605a" , 0xd8, 0x001520C2, 0x010, 0x10000, 0x200000),
+ FLASH_ID("mac 25l3205" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
+ FLASH_ID("mac 25l3205a" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
+ FLASH_ID("mac 25l6405" , 0xd8, 0x001720C2, 0x100, 0x10000, 0x800000),
+ FLASH_ID("wbd w25q128" , 0xd8, 0x001840EF, 0x100, 0x10000, 0x1000000),
};
/*
*
* Wait until TFF is set in status register
*/
-static void smi_wait_xfer_finish(int timeout)
+static int smi_wait_xfer_finish(int timeout)
{
- while (timeout--) {
+ ulong start = get_timer(0);
+
+ while (get_timer(start) < timeout) {
if (readl(&smicntl->smi_sr) & TFF)
- break;
- udelay(1000);
- }
+ return 0;
+
+ /* Try after 10 ms */
+ udelay(10);
+ };
+
+ return -1;
}
/*
writel(READ_ID, &smicntl->smi_tr);
writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3,
&smicntl->smi_cr2);
- smi_wait_xfer_finish(XFER_FINISH_TOUT);
+
+ if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
+ return -EIO;
value = (readl(&smicntl->smi_rr) & 0x00FFFFFF);
static ulong flash_get_size(ulong base, int banknum)
{
flash_info_t *info = &flash_info[banknum];
- struct flash_dev *dev;
- unsigned int value;
- unsigned int density;
+ int value;
int i;
value = smi_read_id(info, banknum);
- density = (value >> 16) & 0xff;
-
- for (i = 0, dev = &flash_ids[0]; dev->density != 0x0;
- i++, dev = &flash_ids[i]) {
- if (dev->density == density) {
- info->size = dev->size;
- info->sector_count = dev->sector_count;
- break;
- }
- }
- if (dev->density == 0x0)
+ if (value < 0) {
+ printf("Flash id could not be read\n");
return 0;
+ }
- info->flash_id = value & 0xffff;
- info->start[0] = base;
+ /* Matches chip-id to entire list of 'serial-nor flash' ids */
+ for (i = 0; i < ARRAY_SIZE(flash_devices); i++) {
+ if (flash_devices[i].device_id == value) {
+ info->size = flash_devices[i].size_in_bytes;
+ info->flash_id = value;
+ info->start[0] = base;
+ info->sector_count =
+ info->size/flash_devices[i].sectorsize;
- return info->size;
+ return info->size;
+ }
+ }
+
+ return 0;
}
/*
* This routine will get the status register of the flash chip present at the
* given bank
*/
-static unsigned int smi_read_sr(int bank)
+static int smi_read_sr(int bank)
{
- u32 ctrlreg1;
+ u32 ctrlreg1, val;
/* store the CTRL REG1 state */
ctrlreg1 = readl(&smicntl->smi_cr1);
/* Performing a RSR instruction in HW mode */
writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2);
- smi_wait_xfer_finish(XFER_FINISH_TOUT);
+ if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
+ return -1;
+
+ val = readl(&smicntl->smi_sr);
/* Restore the CTRL REG1 state */
writel(ctrlreg1, &smicntl->smi_cr1);
- return readl(&smicntl->smi_sr);
+ return val;
}
/*
*/
static int smi_wait_till_ready(int bank, int timeout)
{
- int count;
- unsigned int sr;
+ int sr;
+ ulong start = get_timer(0);
/* One chip guarantees max 5 msec wait here after page writes,
but potentially three seconds (!) after page erase. */
- for (count = 0; count < timeout; count++) {
-
+ while (get_timer(start) < timeout) {
sr = smi_read_sr(bank);
- if (sr < 0)
- break;
- else if (!(sr & WIP_BIT))
+ if ((sr >= 0) && (!(sr & WIP_BIT)))
return 0;
- /* Try again after 1m-sec */
- udelay(1000);
- }
+ /* Try again after 10 usec */
+ udelay(10);
+ } while (timeout--);
+
printf("SMI controller is still in wait, timeout=%d\n", timeout);
return -EIO;
}
static int smi_write_enable(int bank)
{
u32 ctrlreg1;
+ u32 start;
int timeout = WMODE_TOUT;
+ int sr;
/* Store the CTRL REG1 state */
ctrlreg1 = readl(&smicntl->smi_cr1);
/* Give the Flash, Write Enable command */
writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2);
- smi_wait_xfer_finish(XFER_FINISH_TOUT);
+ if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
+ return -1;
/* Restore the CTRL REG1 state */
writel(ctrlreg1, &smicntl->smi_cr1);
- while (timeout--) {
- if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT)))
- break;
- udelay(1000);
- }
+ start = get_timer(0);
+ while (get_timer(start) < timeout) {
+ sr = smi_read_sr(bank);
+ if ((sr >= 0) && (sr & (1 << (bank + WM_SHIFT))))
+ return 0;
- if (timeout)
- return 0;
+ /* Try again after 10 usec */
+ udelay(10);
+ };
return -1;
}
*
* SMI initialization routine. Sets SMI control register1.
*/
-static void smi_init(void)
+void smi_init(void)
{
/* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr);
- if (info->flash_id == ST_M25Pxx_ID) {
- /* Wait until finished previous write command. */
- if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
- return -EBUSY;
+ /* Wait until finished previous write command. */
+ if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
+ return -EBUSY;
- /* Send write enable, before erase commands. */
- if (smi_write_enable(bank))
- return -EIO;
+ /* Send write enable, before erase commands. */
+ if (smi_write_enable(bank))
+ return -EIO;
- /* Put SMI in SW mode */
- writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);
+ /* Put SMI in SW mode */
+ writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);
- /* Send Sector Erase command in SW Mode */
- writel(instruction, &smicntl->smi_tr);
- writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4,
+ /* Send Sector Erase command in SW Mode */
+ writel(instruction, &smicntl->smi_tr);
+ writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4,
&smicntl->smi_cr2);
- smi_wait_xfer_finish(XFER_FINISH_TOUT);
+ if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
+ return -EIO;
- if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
- return -EBUSY;
+ if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
+ return -EBUSY;
- /* Put SMI in HW mode */
- writel(readl(&smicntl->smi_cr1) & ~SW_MODE,
+ /* Put SMI in HW mode */
+ writel(readl(&smicntl->smi_cr1) & ~SW_MODE,
&smicntl->smi_cr1);
- return 0;
- } else {
- /* Put SMI in HW mode */
- writel(readl(&smicntl->smi_cr1) & ~SW_MODE,
- &smicntl->smi_cr1);
- return -EINVAL;
- }
+ return 0;
}
/*
* smi_write - Write to SMI flash
* @src_addr: source buffer
* @dst_addr: destination buffer
- * @length: length to write in words
+ * @length: length to write in bytes
* @bank: bank base address
*
* Write to SMI flash
static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
unsigned int length, ulong bank_addr)
{
+ u8 *src_addr8 = (u8 *)src_addr;
+ u8 *dst_addr8 = (u8 *)dst_addr;
int banknum;
+ int i;
switch (bank_addr) {
case SMIBANK0_BASE:
return -EIO;
/* Perform the write command */
- while (length--) {
+ for (i = 0; i < length; i += 4) {
if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) {
if (smi_wait_till_ready(banknum,
CONFIG_SYS_FLASH_WRITE_TOUT))
return -EIO;
}
- *dst_addr++ = *src_addr++;
+ if (length < 4) {
+ int k;
+
+ /*
+ * Handle special case, where length < 4 (redundant env)
+ */
+ for (k = 0; k < length; k++)
+ *dst_addr8++ = *src_addr8++;
+ } else {
+ /* Normal 32bit write */
+ *dst_addr++ = *src_addr++;
+ }
if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2)))
return -EIO;
int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
{
return smi_write((unsigned int *)src, (unsigned int *)dest_addr,
- (length + 3) / 4, info->start[0]);
+ length, info->start[0]);
}
/*
puts("missing or unknown FLASH type\n");
return;
}
- printf(" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
+
+ if (info->size >= 0x100000)
+ printf(" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+ else
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
puts(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
int prot = 0;
flash_sect_t sect;
- if (info->flash_id != ST_M25Pxx_ID) {
- puts("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
if ((s_first < 0) || (s_first > s_last)) {
puts("- no sectors to erase\n");
return 1;
miiphy_register(phy[i].name, davinci_mii_phy_read,
davinci_mii_phy_write);
}
+
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+ defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+ for (i = 0; i < num_phy; i++) {
+ if (phy[i].is_phy_connected(i))
+ phy[i].auto_negotiate(i);
+ }
+#endif
return(1);
}
#include <common.h>
#include <miiphy.h>
#include <malloc.h>
+#include <linux/compiler.h>
#include <linux/err.h>
#include <asm/io.h>
#include "designware.h"
if (priv->phy_configured != 1)
configure_phy(dev);
+ /* Print link status only once */
+ if (!priv->link_printed) {
+ printf("ENET Speed is %d Mbps - %s duplex connection\n",
+ priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL");
+ priv->link_printed = 1;
+ }
+
/* Reset ethernet hardware */
if (mac_reset(dev) < 0)
return -1;
conf = FRAMEBURSTENABLE | DISABLERXOWN;
- if (priv->speed != SPEED_1000M)
+ if (priv->speed != 1000)
conf |= MII_PORTSELECT;
- if (priv->duplex == FULL_DUPLEX)
+ if ((priv->interface != PHY_INTERFACE_MODE_MII) &&
+ (priv->interface != PHY_INTERFACE_MODE_GMII)) {
+
+ if (priv->speed == 100)
+ conf |= FES_100;
+ }
+
+ if (priv->duplex == FULL)
conf |= FULLDPLXMODE;
writel(conf, &mac_p->conf);
return 0;
}
+/*
+ * Add weak default function for board specific PHY configuration
+ */
+int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr,
+ int (*mii_write)(struct eth_device *, u8, u8, u16),
+ int dw_reset_phy(struct eth_device *))
+{
+ return 0;
+}
+
static int configure_phy(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
u16 bmsr;
u32 timeout;
ulong start;
- u16 anlpar, btsr;
-#else
- u16 ctrl;
#endif
#if defined(CONFIG_DW_SEARCH_PHY)
#else
phy_addr = priv->address;
#endif
+
+ /*
+ * Some boards need board specific PHY initialization. This is
+ * after the main driver init code but before the auto negotiation
+ * is run.
+ */
+ if (designware_board_phy_init(dev, phy_addr,
+ eth_mdio_write, dw_reset_phy) < 0)
+ return -1;
+
if (dw_reset_phy(dev) < 0)
return -1;
#if defined(CONFIG_DW_AUTONEG)
timeout = CONFIG_AUTONEG_TIMEOUT;
start = get_timer(0);
-
+ puts("Waiting for PHY auto negotiation to complete");
while (get_timer(start) < timeout) {
eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr);
- if (bmsr & BMSR_ANEGCOMPLETE)
+ if (bmsr & BMSR_ANEGCOMPLETE) {
+ priv->phy_configured = 1;
break;
-
- /* Try again after 10usec */
- udelay(10);
- };
-
- eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar);
- eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr);
-
- if (bmsr & BMSR_ANEGCOMPLETE) {
- if (btsr & PHY_1000BTSR_1000FD) {
- priv->speed = SPEED_1000M;
- bmcr |= BMCR_SPEED1000;
- priv->duplex = FULL_DUPLEX;
- bmcr |= BMCR_FULLDPLX;
- } else if (btsr & PHY_1000BTSR_1000HD) {
- priv->speed = SPEED_1000M;
- bmcr |= BMCR_SPEED1000;
- priv->duplex = HALF_DUPLEX;
- bmcr &= ~BMCR_FULLDPLX;
- } else if (anlpar & LPA_100FULL) {
- priv->speed = SPEED_100M;
- bmcr |= BMCR_SPEED100;
- priv->duplex = FULL_DUPLEX;
- bmcr |= BMCR_FULLDPLX;
- } else if (anlpar & LPA_100HALF) {
- priv->speed = SPEED_100M;
- bmcr |= BMCR_SPEED100;
- priv->duplex = HALF_DUPLEX;
- bmcr &= ~BMCR_FULLDPLX;
- } else if (anlpar & LPA_10FULL) {
- priv->speed = SPEED_10M;
- bmcr &= ~BMCR_SPEED100;
- priv->duplex = FULL_DUPLEX;
- bmcr |= BMCR_FULLDPLX;
- } else {
- priv->speed = SPEED_10M;
- bmcr &= ~BMCR_SPEED100;
- priv->duplex = HALF_DUPLEX;
- bmcr &= ~BMCR_FULLDPLX;
}
- if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
- return -1;
- } else
- return -1;
-#else
- if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0)
- return -1;
- if (ctrl & BMCR_FULLDPLX)
- priv->duplex = FULL_DUPLEX;
- else
- priv->duplex = HALF_DUPLEX;
+ /* Print dot all 1s to show progress */
+ if ((get_timer(start) % 1000) == 0)
+ putc('.');
- if (ctrl & BMCR_SPEED1000)
- priv->speed = SPEED_1000M;
- else if (ctrl & BMCR_SPEED100)
- priv->speed = SPEED_100M;
+ /* Try again after 1msec */
+ udelay(1000);
+ };
+
+ if (!(bmsr & BMSR_ANEGCOMPLETE))
+ puts(" TIMEOUT!\n");
else
- priv->speed = SPEED_10M;
-#endif
+ puts(" done\n");
+#else
priv->phy_configured = 1;
+#endif
+
+ priv->speed = miiphy_speed(dev->name, phy_addr);
+ priv->duplex = miiphy_duplex(dev->name, phy_addr);
return 0;
}
}
#endif
-int designware_initialize(u32 id, ulong base_addr, u32 phy_addr)
+int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface)
{
struct eth_device *dev;
struct dw_eth_dev *priv;
DW_DMA_BASE_OFFSET);
priv->address = phy_addr;
priv->phy_configured = 0;
-
- if (mac_reset(dev) < 0)
- return -1;
-
- configure_phy(dev);
+ priv->interface = interface;
dev->init = dw_eth_init;
dev->send = dw_eth_send;
struct dw_eth_dev {
u32 address;
+ u32 interface;
u32 speed;
u32 duplex;
u32 tx_currdescnum;
u32 rx_currdescnum;
u32 phy_configured;
+ int link_printed;
u32 padding;
struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
#define M41T62_FEATURE_HT (1 << 0)
#define M41T62_FEATURE_BL (1 << 1)
+#define M41T80_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */
+
int rtc_get(struct rtc_time *tm)
{
u8 buf[M41T62_DATETIME_REG_SIZE];
void rtc_reset(void)
{
+ u8 val;
+
/*
- * Nothing to do
+ * M41T82: Make sure HT (Halt Update) bit is cleared.
+ * This bit is 0 in M41T62 so its save to clear it always.
*/
+ i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
+ val &= ~M41T80_ALHOUR_HT;
+ i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
}
#endif
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
-COBJS-$(CONFIG_TEGRA2_SPI) += tegra2_spi.o
+COBJS-$(CONFIG_TEGRA_SPI) += tegra_spi.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE;
+u32 cs_spi_mpp_back[2];
+
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct spi_slave *slave;
u32 data;
- u32 kwspi_mpp_config[] = {
- MPP0_GPIO,
- MPP7_SPI_SCn,
- 0
- };
+ u32 kwspi_mpp_config[] = { 0, 0 };
if (!spi_cs_is_valid(bus, cs))
return NULL;
/* program mpp registers to select SPI_CSn */
if (cs) {
- kwspi_mpp_config[0] = MPP0_GPIO;
- kwspi_mpp_config[1] = MPP7_SPI_SCn;
+ kwspi_mpp_config[0] = MPP7_SPI_SCn;
} else {
kwspi_mpp_config[0] = MPP0_SPI_SCn;
- kwspi_mpp_config[1] = MPP7_GPO;
}
- kirkwood_mpp_conf(kwspi_mpp_config);
+ kirkwood_mpp_conf(kwspi_mpp_config, cs_spi_mpp_back);
return slave;
}
void spi_free_slave(struct spi_slave *slave)
{
+ kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
free(slave);
}
-int spi_claim_bus(struct spi_slave *slave)
+#if defined(CONFIG_SYS_KW_SPI_MPP)
+u32 spi_mpp_backup[4];
+#endif
+
+__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
{
return 0;
}
+int spi_claim_bus(struct spi_slave *slave)
+{
+#if defined(CONFIG_SYS_KW_SPI_MPP)
+ u32 config;
+ u32 spi_mpp_config[4];
+
+ config = CONFIG_SYS_KW_SPI_MPP;
+
+ if (config & MOSI_MPP6)
+ spi_mpp_config[0] = MPP6_SPI_MOSI;
+ else
+ spi_mpp_config[0] = MPP1_SPI_MOSI;
+
+ if (config & SCK_MPP10)
+ spi_mpp_config[1] = MPP10_SPI_SCK;
+ else
+ spi_mpp_config[1] = MPP2_SPI_SCK;
+
+ if (config & MISO_MPP11)
+ spi_mpp_config[2] = MPP11_SPI_MISO;
+ else
+ spi_mpp_config[2] = MPP3_SPI_MISO;
+
+ spi_mpp_config[3] = 0;
+ spi_mpp_backup[3] = 0;
+
+ /* set new spi mpp and save current mpp config */
+ kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
+
+#endif
+
+ return board_spi_claim_bus(slave);
+}
+
+__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
+{
+}
+
void spi_release_bus(struct spi_slave *slave)
{
+#if defined(CONFIG_SYS_KW_SPI_MPP)
+ kirkwood_mpp_conf(spi_mpp_backup, NULL);
+#endif
+
+ board_spi_release_bus(slave);
}
#ifndef CONFIG_SPI_CS_IS_VALID
/*
- * Copyright (c) 2010-2011 NVIDIA Corporation
+ * Copyright (c) 2010-2012 NVIDIA Corporation
* With help from the mpc8xxx SPI driver
* With more help from omap3_spi SPI driver
*
#include <spi.h>
#include <asm/io.h>
#include <asm/gpio.h>
-#include <ns16550.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/uart-spi-switch.h>
-#include <asm/arch/tegra2_spi.h>
+#include <asm/arch/tegra_spi.h>
+
+#if defined(CONFIG_SPI_CORRUPTS_UART)
+ #define corrupt_delay() udelay(CONFIG_SPI_CORRUPTS_UART_DLY);
+#else
+ #define corrupt_delay()
+#endif
struct tegra_spi_slave {
struct spi_slave slave;
/* CS is negated on Tegra, so drive a 1 to get a 0 */
setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
+
+ corrupt_delay(); /* Let UART settle */
}
void spi_cs_deactivate(struct spi_slave *slave)
{
struct tegra_spi_slave *spi = to_tegra_spi(slave);
+ pinmux_select_uart();
+
/* CS is negated on Tegra, so drive a 0 to get a 1 */
clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
+
+ corrupt_delay(); /* Let SPI settle */
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
# echi
COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o
COBJS-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o
+COBJS-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o
ifdef CONFIG_MPC512X
COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
else
--- /dev/null
+/*
+ * (C) Copyright 2012
+ * Atmel Semiconductor <www.atmel.com>
+ * Written-by: Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+
+#include "ehci.h"
+#include "ehci-core.h"
+
+/* Enable UTMI PLL time out 500us
+ * 10 times as datasheet specified
+ */
+#define EN_UPLL_TIMEOUT 500UL
+
+int ehci_hcd_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+ ulong start_time, tmp_time;
+
+ start_time = get_timer(0);
+ /* Enable UTMI PLL */
+ writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
+ while ((readl(&pmc->sr) & AT91_PMC_LOCKU) != AT91_PMC_LOCKU) {
+ WATCHDOG_RESET();
+ tmp_time = get_timer(0);
+ if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) {
+ printf("ERROR: failed to enable UPLL\n");
+ return -1;
+ }
+ }
+
+ /* Enable USB Host clock */
+ writel(1 << ATMEL_ID_UHPHS, &pmc->pcer);
+
+ hccr = (struct ehci_hccr *)ATMEL_BASE_EHCI;
+ hcor = (struct ehci_hcor *)((uint32_t)hccr +
+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+ ulong start_time, tmp_time;
+
+ /* Disable USB Host Clock */
+ writel(1 << ATMEL_ID_UHPHS, &pmc->pcdr);
+
+ start_time = get_timer(0);
+ /* Disable UTMI PLL */
+ writel(readl(&pmc->uckr) & ~AT91_PMC_UPLLEN, &pmc->uckr);
+ while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU) {
+ WATCHDOG_RESET();
+ tmp_time = get_timer(0);
+ if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) {
+ printf("ERROR: failed to stop UPLL\n");
+ return -1;
+ }
+ }
+
+ return 0;
+}
static unsigned int panel_width, panel_height;
-/* LCD Panel data */
-vidinfo_t panel_info;
-
static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
{
unsigned long palette_size;
/* lib/crc32.c */
#include <u-boot/crc.h>
+/* lib/rand.c */
+#if defined(CONFIG_RANDOM_MACADDR) || \
+ defined(CONFIG_BOOTP_RANDOM_DELAY) || \
+ defined(CONFIG_CMD_LINK_LOCAL)
+#define RAND_MAX -1U
+void srand(unsigned int seed);
+unsigned int rand(void);
+unsigned int rand_r(unsigned int *seedp);
+#endif
+
/* common/console.c */
int console_init_f(void); /* Before relocation; uses the serial stuff */
int console_init_r(void); /* After relocation; uses the console stuff */
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x4200
-#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=atmel_nand:-(root) " \
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x4200
-#define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTCOMMAND "cp.b 0xD0084000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=atmel_nand:-(root) " \
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE
/*
* Size of malloc() pool
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x4200
-#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=atmel_nand:-(root) " \
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x4200
-#define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTCOMMAND "cp.b 0xD0084000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=atmel_nand:-(root) " \
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
/*
* Size of malloc() pool
*/
#include <asm/hardware.h>
+#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
#define CONFIG_SYS_TEXT_BASE 0x21F00000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x0000000
+#endif
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007FE000)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000)
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
/* Address and size of Primary Environment Sector */
-#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SIZE 0x10000
#define xstr(s) str(s)
#define str(s) #s
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x4200
-#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=atmel_nand:-(root) "\
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
-/*
- * This needs to be defined for the OHCI code to work but it is defined as
- * ATMEL_ID_UHPHS in the CPU specific header files.
- */
-#define ATMEL_ID_UHP ATMEL_ID_UHPHS
-
-/*
- * Specify the clock enable bit in the PMC_SCER register.
- */
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
-
/* LCD */
#define CONFIG_LCD
#define LCD_BPP LCD_COLOR8
#define CONFIG_RESET_PHY_R
/* USB */
-#define CONFIG_USB_ATMEL
-#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
#define CONFIG_DOS_PARTITION
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_HCI
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x4200
-#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock0 " \
"mtdparts=atmel_nand:-(root) "\
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE
/*
* Size of malloc() pool
/*
* Size of malloc() pool
*/
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
+#define GPMC_NAND_ECC_LP_x8_LAYOUT
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
#define CONFIG_SYS_DTT_LOW_TEMP -30
#define CONFIG_SYS_DTT_HYSTERESIS 3
+/*
+ * SPI Configuration
+ */
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
+#define CONFIG_CMD_SPI
+
/*
* Flash & Environment
*/
"key_magic_2=2\0" \
"key_magic_3=3\0" \
"magic_keys=0123\0" \
- "hwconfig=switch:lan=on,pwl=off\0" \
+ "hwconfig=switch:lan=on,pwl=off,config=0x60100000\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addmisc=setenv bootargs ${bootargs} davinci_mmc.use_dma=0\0" \
+ "addmisc=setenv bootargs ${bootargs}\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"logversion=2\0" \
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MMC
+/* GPIO */
+#define CONFIG_ENBW_CMC_BOARD_TYPE 57
+#define CONFIG_ENBW_CMC_HW_ID_BIT0 39
+#define CONFIG_ENBW_CMC_HW_ID_BIT1 38
+#define CONFIG_ENBW_CMC_HW_ID_BIT2 35
/* FDT support */
#define CONFIG_OF_LIBFDT
#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY)
-#define CONFIG_SYS_POST_WORD_ADDR 0x8001FFF0
+#define CONFIG_POST_EXTERNAL_WORD_FUNCS
+#define CONFIG_SYS_POST_WORD_ADDR DAVINCI_RTC_BASE
#define CONFIG_LOGBUFFER
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010-2012
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
#include <asm/sizes.h>
#include "tegra2-common.h"
+/* Enable fdt support for Harmony. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE tegra2-harmony
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
/* High-level configuration options */
-#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M"
#define V_PROMPT "Tegra2 (Harmony) # "
#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Harmony"
#endif
#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY
-#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA2_MMC
+#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
/* Environment not stored */
#define CONFIG_ENV_IS_NOWHERE
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra2-common-post.h"
+
#endif /* __CONFIG_H */
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_MX31_PORT2
#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 0xfe
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_CMD_SF
#define CONFIG_SOFT_I2C /* I2C bit-banged */
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 5000000
+#define CONFIG_ENV_SPI_MODE SPI_MODE_3
+#endif
+
#include "asm/arch/config.h"
#define CONFIG_SYS_TEXT_BASE 0x07d00000 /* code address before reloc */
"boot=bootm ${load_addr_r} - -\0" \
"cramfsloadfdt=true\0" \
"u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.kwb\0" \
- CONFIG_KM_DEF_ENV_UPDATE \
+ CONFIG_KM_UPDATE_UBOOT \
""
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
*/
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_CMD_MII /* to debug mdio phy config */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
-#define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */
/*
* UBI related stuff
int get_scl(void);
#define KM_KIRKWOOD_SDA_PIN 8
#define KM_KIRKWOOD_SCL_PIN 9
+#define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300
#define KM_KIRKWOOD_ENV_WP 38
#define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0)
/*
* Environment variables configurations
*/
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_ENV_IS_IN_SPI_FLASH /* use SPI-Flash for environment vars */
+#define CONFIG_ENV_OFFSET 0xc0000 /* no bracets! */
+#define CONFIG_ENV_SIZE 0x02000 /* Size of Environment */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */
+#else
#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */
#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */
#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET)
#define CONFIG_I2C_ENV_EEPROM_BUS KM_ENV_BUS "\0"
-
-/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#endif
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
+/* SPI bus claim MPP configuration */
+#define CONFIG_SYS_KW_SPI_MPP 0x0
+
#define FLASH_GPIO_PIN 0x00010000
+#define KM_FLASH_GPIO_PIN 16
#ifndef MTDIDS_DEFAULT
# define MTDIDS_DEFAULT "nand0=orion_nand"
"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
#endif /* MTDPARTS_DEFAULT */
-#define CONFIG_KM_DEF_ENV_UPDATE \
+#define CONFIG_KM_UPDATE_UBOOT \
"update=" \
- "spi on;sf probe 0;sf erase 0 50000;" \
- "sf write ${load_addr_r} 0 ${filesize};" \
- "spi off\0"
+ "sf probe 0;sf erase 0 +${filesize};" \
+ "sf write ${load_addr_r} 0 ${filesize};\0"
+
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_KM_NEW_ENV \
+ "newenv=sf probe 0;" \
+ "sf erase " xstr(CONFIG_ENV_OFFSET) " " \
+ xstr(CONFIG_ENV_TOTAL_SIZE)"\0"
+#else
+#define CONFIG_KM_NEW_ENV \
+ "newenv=setenv addr 0x100000 && " \
+ "i2c dev 1; mw.b ${addr} 0 4 && " \
+ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
+ " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \
+ "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
+ " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0"
+#endif
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \
- "newenv=setenv addr 0x100000 && " \
- "i2c dev 1; mw.b ${addr} 0 4 && " \
- "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
- " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \
- "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
- " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \
+ CONFIG_KM_NEW_ENV \
"arch=arm\0" \
"EEprom_ivm=" KM_IVM_BUS "\0" \
""
#define CONFIG_POST_EXTERNAL_WORD_FUNCS
#define CONFIG_CMD_DIAG
+/* we do the whole PCIe FPGA config stuff here */
+#define BOARD_LATE_INIT
+
#endif /* _CONFIG_KM_ARM_H */
* (C) Copyright 2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
- * (C) Copyright 2011
- * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.de
+ * (C) Copyright 2011-2012
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
+ * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
*
* See file CREDITS for list of people who contributed to this
* project.
#ifndef _CONFIG_KM_KIRKWOOD_H
#define _CONFIG_KM_KIRKWOOD_H
+/* KM_KIRKWOOD */
+#if defined(CONFIG_KM_KIRKWOOD)
+#define CONFIG_IDENT_STRING "\nKeymile Kirkwood"
+#define CONFIG_HOSTNAME km_kirkwood
+#define CONFIG_KM_DISABLE_PCIE
+#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
+
+/* KM_KIRKWOOD_PCI */
+#elif defined(CONFIG_KM_KIRKWOOD_PCI)
+#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI"
+#define CONFIG_HOSTNAME km_kirkwood_pci
+#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_FPGA_CONFIG
+
+/* KM_NUSA */
+#elif defined(CONFIG_KM_NUSA)
+#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
+#define CONFIG_IDENT_STRING "\nKeymile NUSA"
+#define CONFIG_HOSTNAME kmnusa
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG \
+ $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
+#define CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_KM_FPGA_CONFIG
+#define CONFIG_KM_PIGGY4_88E6352
+
+/* KM_MGCOGE3UN */
+#elif defined(CONFIG_KM_MGCOGE3UN)
+#define CONFIG_IDENT_STRING "\nKeymile COGE3UN"
+#define CONFIG_HOSTNAME mgcoge3un
+#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG \
+ $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
+#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0"
+#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3
+#define CONFIG_KM_DISABLE_PCIE
+#define CONFIG_KM_PIGGY4_88E6061
+
+/* KMCOGE5UN */
+#elif defined(CONFIG_KM_COGE5UN)
+#define CONFIG_IDENT_STRING "\nKeymile COGE5UN"
+#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG \
+ $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
+#define CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3
+#define CONFIG_HOSTNAME kmcoge5un
+#define CONFIG_KM_DISABLE_PCIE
+#define CONFIG_KM_PIGGY4_88E6352
+
+/* KM_PORTL2 */
+#elif defined(CONFIG_KM_PORTL2)
+#define CONFIG_IDENT_STRING "\nKeymile Port-L2"
+#define CONFIG_HOSTNAME portl2
+#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_PIGGY4_88E6061
+
+#else
+#error ("Board unsupported")
+#endif
+
/* include common defines/options for all arm based Keymile boards */
#include "km/km_arm.h"
+#ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
+#endif
+
+#if defined(CONFIG_KM_PIGGY4_88E6352)
/*
- * Version number information
+ * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via
+ * an Marvell 88E6352 simple switch.
+ * In this case we have to change the default settings for the etherent mac.
+ * There is NO ethernet phy. The ARM and Switch are conencted directly over
+ * RGMII in MAC-MAC mode
+ * In this case 1GBit full duplex and autoneg off
*/
-#ifdef CONFIG_KM_DISABLE_PCI
-#define CONFIG_IDENT_STRING "\nKeymile Kirkwood"
-#undef CONFIG_KIRKWOOD_PCIE_INIT
-#else
-#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI"
+#define PORT_SERIAL_CONTROL_VALUE ( \
+ MVGBE_FORCE_LINK_PASS | \
+ MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
+ MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
+ MVGBE_ADV_NO_FLOW_CTRL | \
+ MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
+ MVGBE_FORCE_BP_MODE_NO_JAM | \
+ (1 << 9) /* Reserved bit has to be 1 */ | \
+ MVGBE_DO_NOT_FORCE_LINK_FAIL | \
+ MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
+ MVGBE_DTE_ADV_0 | \
+ MVGBE_MIIPHY_MAC_MODE | \
+ MVGBE_AUTO_NEG_NO_CHANGE | \
+ MVGBE_MAX_RX_PACKET_1552BYTE | \
+ MVGBE_CLR_EXT_LOOPBACK | \
+ MVGBE_SET_FULL_DUPLEX_MODE | \
+ MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
+ MVGBE_SET_GMII_SPEED_TO_1000 |\
+ MVGBE_SET_MII_SPEED_TO_100)
+
#endif
-#define CONFIG_HOSTNAME km_kirkwood
+#ifdef CONFIG_KM_PIGGY4_88E6061
+/*
+ * Some keymile boards like mgcoge3un have their PIGGY4 connected via
+ * an Marvell 88E6061 simple switch.
+ * In this case we have to change the default settings for the
+ * ethernet phy connected to the kirkwood.
+ * In this case 100MB full duplex and autoneg off
+ */
+#define PORT_SERIAL_CONTROL_VALUE ( \
+ MVGBE_FORCE_LINK_PASS | \
+ MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
+ MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
+ MVGBE_ADV_NO_FLOW_CTRL | \
+ MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
+ MVGBE_FORCE_BP_MODE_NO_JAM | \
+ (1 << 9) /* Reserved bit has to be 1 */ | \
+ MVGBE_DO_NOT_FORCE_LINK_FAIL | \
+ MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
+ MVGBE_DTE_ADV_0 | \
+ MVGBE_MIIPHY_MAC_MODE | \
+ MVGBE_AUTO_NEG_NO_CHANGE | \
+ MVGBE_MAX_RX_PACKET_1552BYTE | \
+ MVGBE_CLR_EXT_LOOPBACK | \
+ MVGBE_SET_FULL_DUPLEX_MODE | \
+ MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
+ MVGBE_SET_GMII_SPEED_TO_10_100 |\
+ MVGBE_SET_MII_SPEED_TO_100)
+#endif
-#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
-#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
+#ifdef CONFIG_KM_DISABLE_PCI
+#undef CONFIG_KIRKWOOD_PCIE_INIT
+#endif
-/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
-#define KM_XLX_PROGRAM_B_PIN 39
#endif /* _CONFIG_KM_KIRKWOOD */
/*
* SDRAM configuration
*/
-#if defined(CONFIG_NET2BIG_V2)
-#define CONFIG_NR_DRAM_BANKS 2
-#else
#define CONFIG_NR_DRAM_BANKS 1
-#endif
#ifdef CONFIG_INETSPACE_V2
/* Different SDRAM configuration and size for Internet Space v2 */
-#define CONFIG_SYS_KWD_CONFIG ($(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg)
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg
#endif
/*
--- /dev/null
+/*
+ * Copyright (c) 2012 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_LSXL_H
+#define _CONFIG_LSXL_H
+
+/*
+ * Version number information
+ */
+#if defined(CONFIG_LSCHLV2)
+#define CONFIG_IDENT_STRING " LS-CHLv2"
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
+#define CONFIG_MACH_TYPE 3006
+#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */
+#elif defined(CONFIG_LSXHL)
+#define CONFIG_IDENT_STRING " LS-XHL"
+#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
+#define CONFIG_MACH_TYPE 2663
+/* CONFIG_SYS_TCLK is 200000000 by default */
+#else
+#error "unknown board"
+#endif
+
+/*
+ * General configuration options
+ */
+#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
+#define CONFIG_KIRKWOOD /* SOC Family Name */
+#define CONFIG_KW88F6281 /* SOC Name */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_RANDOM_MACADDR
+#define CONFIG_KIRKWOOD_GPIO
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/*
+ * Enable u-boot API for standalone programs.
+ */
+#define CONFIG_API
+
+/*
+ * Commands configuration
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_USB
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* ST M25P40 */
+#undef CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_STMICRO
+#undef CONFIG_ENV_SPI_MAX_HZ
+#define CONFIG_ENV_SPI_MAX_HZ 25000000
+#undef CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_SF_DEFAULT_SPEED 25000000
+
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 8
+#define CONFIG_ENV_IS_IN_SPI_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE 0x10000 /* 64k */
+#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_LOADADDR 0x00800000
+#define CONFIG_BOOTCOMMAND "run bootcmd_${bootsource}"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/sda2"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootsource=hdd\0" \
+ "hdpart=0:1\0" \
+ "bootcmd_net=bootp 0x00100000 uImage " \
+ "&& tftpboot 0x00800000 uInitrd " \
+ "&& bootm 0x00100000 0x00800000\0" \
+ "bootcmd_hdd=ide reset " \
+ "&& ext2load ide ${hdpart} 0x00100000 /uImage " \
+ "&& ext2load ide ${hdpart} 0x00800000 /uInitrd " \
+ "&& bootm 0x00100000 0x00800000\0" \
+ "bootcmd_usb=usb start " \
+ "&& fatload usb 0:1 0x00100000 /uImage " \
+ "&& fatload usb 0:1 0x00800000 /uInitrd " \
+ "&& bootm 0x00100000 0x00800000\0" \
+ "bootcmd_rescue=run config_nc_dhcp; run nc\0" \
+ "eraseenv=sf probe 0 " \
+ "&& sf erase " MK_STR(CONFIG_ENV_OFFSET) \
+ " +" MK_STR(CONFIG_ENV_SIZE) "\0" \
+ "config_nc_dhcp=setenv autoload_old ${autoload}; " \
+ "setenv autoload no " \
+ "&& bootp " \
+ "&& setenv ncip ${serverip} " \
+ "&& setenv autoload ${autoload_old}; " \
+ "setenv autoload_old\0" \
+ "standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \
+ "setenv ncip; setenv gatewayip; setenv ethact; " \
+ "setenv bootfile; setenv dnsip; " \
+ "setenv bootsource hdd; run ser\0" \
+ "restore_env=run standard_env; saveenv; reset\0" \
+ "ser=setenv stdin serial; setenv stdout serial; " \
+ "setenv stderr serial\0" \
+ "nc=setenv stdin nc; setenv stdout nc; setenv stderr nc\0" \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS {0, 1} /* enable port 1 only */
+#define CONFIG_PHY_BASE_ADR 7
+#undef CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+#ifdef CONFIG_CMD_IDE
+#undef CONFIG_IDE_LED
+#undef CONFIG_SYS_IDE_MAXBUS
+#define CONFIG_SYS_IDE_MAXBUS 1
+#undef CONFIG_SYS_IDE_MAXDEVICE
+#define CONFIG_SYS_IDE_MAXDEVICE 1
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#endif
+
+#endif /* _CONFIG_LSXL_H */
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#ifndef __M28_H__
-#define __M28_H__
+#ifndef __M28EVK_CONFIG_H__
+#define __M28EVK_CONFIG_H__
#include <asm/arch/regs-base.h>
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_OF_LIBFDT
-
/*
* SPL
*/
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
-#define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */
+#define CONFIG_STACKSIZE (128 * 1024) /* 128 KB stack */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
"fi ; " \
"fi\0"
-#endif /* __M28_H__ */
+#endif /* __M28EVK_CONFIG_H__ */
#include "tegra2-common.h"
/* High-level configuration options */
-#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M"
#define V_PROMPT "Tegra2 (Medcom) # "
#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Medcom"
-#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA2_MMC
+#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
+#include "tegra2-common-post.h"
+
#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Prafulla Wadaskar <prafulla@marvell.com>
- *
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2010-2011
- * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* for linking errors see
- * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
-
-#ifndef _CONFIG_MGCOGE3UN_H
-#define _CONFIG_MGCOGE3UN_H
-
-/* include common defines/options for all arm based Keymile boards */
-#include "km/km_arm.h"
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nKeymile MGCOGE3UN"
-#define CONFIG_HOSTNAME mgcoge3un
-#define CONFIG_MGCOGE3UN
-
-#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
-#define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/
-
-/* we use a new RAM type on mgcoge3un board */
-#undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
-
-/*
- * mgcoge3un has a fixed link to the marvell switch
- * with 100MB full duplex and autoneg off, for this
- * reason we have to change the default settings
- */
-#define PORT_SERIAL_CONTROL_VALUE ( \
- MVGBE_FORCE_LINK_PASS | \
- MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
- MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
- MVGBE_ADV_NO_FLOW_CTRL | \
- MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
- MVGBE_FORCE_BP_MODE_NO_JAM | \
- (1 << 9) /* Reserved bit has to be 1 */ | \
- MVGBE_DO_NOT_FORCE_LINK_FAIL | \
- MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
- MVGBE_DTE_ADV_0 | \
- MVGBE_MIIPHY_MAC_MODE | \
- MVGBE_AUTO_NEG_NO_CHANGE | \
- MVGBE_MAX_RX_PACKET_1552BYTE | \
- MVGBE_CLR_EXT_LOOPBACK | \
- MVGBE_SET_FULL_DUPLEX_MODE | \
- MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
- MVGBE_SET_GMII_SPEED_TO_10_100 |\
- MVGBE_SET_MII_SPEED_TO_100)
-
-#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0"
-
-/*
- * PCIe port not used on mgcoge3un
- */
-#undef CONFIG_KIRKWOOD_PCIE_INIT
-
-#endif /* _CONFIG_MGCOGE3UN_H */
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __MX28EVK_CONFIG_H__
+#define __MX28EVK_CONFIG_H__
#include <asm/arch/regs-base.h>
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_ARCH_MISC_INIT
/*
#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FAT
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
"run netargs; " \
"dhcp ${uimage}; bootm\0" \
-#endif /* __CONFIG_H */
+#endif /* __MX28EVK_CONFIG_H__ */
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_MX35_PORT1
#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 0xfe
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_MX53_PORT2
#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 0xfe
/* MMC Configs */
#define CONFIG_FSL_ESDHC
/* Eth Configs */
#define CONFIG_HAS_ETH1
#define CONFIG_MII
-#define CONFIG_MII_GASKET
#define CONFIG_DISCOVER_PHY
#define CONFIG_CMD_PING
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_MX53_PORT2 1
#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 0xfe
/* PMIC Configs */
#define CONFIG_PMIC
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_REVISION_TAG
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_MX53_PORT1
#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 0xfe
/* PMIC Controller */
#define CONFIG_PMIC
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_MX53_PORT2
#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 0xfe
/* MMC Configs */
#define CONFIG_FSL_ESDHC
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MXC_GPIO
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
#define CONFIG_MXC_GPIO
/* commands to include */
#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
/* partition */
/* Environment information */
-#define CONFIG_BOOTDELAY 2
+#define CONFIG_BOOTDELAY 3
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
*/
#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
* Default environment
* -----------------------------------------------------------------------------
*/
-#define CONFIG_BOOTDELAY 10
+#define CONFIG_BOOTDELAY 3
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
/* Flash */
#define CONFIG_SYS_NO_FLASH 1
-/* clocks */
-#define CONFIG_SYS_CLOCKS_ENABLE_ALL
-
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
-
-#define CONFIG_SYS_ENABLE_PADS_ALL
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SYS_THUMB_BUILD
/* Clock Defines */
#define V_OSCK 19200000 /* Clock output from T2 */
#define V_SCLK V_OSCK
-#define CONFIG_SYS_CLOCKS_ENABLE_ALL 1 /* Enable all clocks */
-#define CONFIG_SYS_ENABLE_PADS_ALL 1 /* Enable all PADS for now */
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
/*
* 64 bytes before this address should be set aside for u-boot.img's
/*
- * Copyright (c) 2010,2011, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <asm/sizes.h>
#include "tegra2-common.h"
+/* Enable fdt support for Paz00. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE tegra2-paz00
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
/* High-level configuration options */
-#define TEGRA2_SYSMEM "mem=512M@0M"
#define V_PROMPT "Tegra2 (Paz00) MOD # "
#define CONFIG_TEGRA2_BOARD_STRING "Compal Paz00"
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
-#define CONFIG_SYS_BOARD_ODMDATA 0x800c0085 /* lp1, 512MB */
#define CONFIG_BOARD_EARLY_INIT_F
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA2_MMC
+#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
-/* Environment not stored */
-#define CONFIG_ENV_IS_NOWHERE
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra2-common-post.h"
+
#endif /* __CONFIG_H */
#include "tegra2-common.h"
/* High-level configuration options */
-#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M"
#define V_PROMPT "Tegra2 (Plutux) # "
#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Plutux"
-#define CONFIG_SYS_BOARD_ODMDATA 0x2b2d8011
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA2_MMC
+#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
+#include "tegra2-common-post.h"
+
#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Prafulla Wadaskar <prafulla@marvell.com>
- *
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2010-2011
- * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com.
- * Valentin Longchamp, Keymile AG Bern, valentin.longchamp@keymile.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* for linking errors see
- * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
-
-#ifndef _CONFIG_PORTL2_H
-#define _CONFIG_PORTL2_H
-
-/* include common defines/options for all arm based Keymile boards */
-#include "km/km_arm.h"
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING "\nKeymile Port-L2"
-#define CONFIG_HOSTNAME portl2
-#define CONFIG_PORTL2
-
-#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
-/*
- * Note: This is only valid for HW > P1A if you got an outdated P1A
- * use KM_ENV_BUS "pca9544a:70:a"
- */
-#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
-
-/*
- * portl2 has a fixed link to the XMPP backplane
- * with 100MB full duplex and autoneg off, for this
- * reason we have to change the default settings
- */
-#define PORT_SERIAL_CONTROL_VALUE ( \
- MVGBE_FORCE_LINK_PASS | \
- MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
- MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
- MVGBE_ADV_NO_FLOW_CTRL | \
- MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
- MVGBE_FORCE_BP_MODE_NO_JAM | \
- (1 << 9) /* Reserved bit has to be 1 */ | \
- MVGBE_DO_NOT_FORCE_LINK_FAIL | \
- MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
- MVGBE_DTE_ADV_0 | \
- MVGBE_MIIPHY_MAC_MODE | \
- MVGBE_AUTO_NEG_NO_CHANGE | \
- MVGBE_MAX_RX_PACKET_1552BYTE | \
- MVGBE_CLR_EXT_LOOPBACK | \
- MVGBE_SET_FULL_DUPLEX_MODE | \
- MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
- MVGBE_SET_GMII_SPEED_TO_10_100 |\
- MVGBE_SET_MII_SPEED_TO_100)
-
-/*
- * portl2 does use the PCIe Port0
- */
-#define CONFIG_KIRKWOOD_PCIE_INIT
-
-#endif /* _CONFIG_PORTL2_H */
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
-#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M"
#define V_PROMPT "Tegra2 (SeaBoard) # "
#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Seaboard"
#define CONFIG_UART_DISABLE_GPIO GPIO_PI3
#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
-#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F
-/* SPI */
-#define CONFIG_TEGRA2_SPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
/* I2C */
#define CONFIG_TEGRA_I2C
#define CONFIG_SYS_I2C_INIT_BOARD
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA2_MMC
+#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
-/* Environment in SPI */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_MAX_HZ 48000000
-#define CONFIG_ENV_SPI_MODE SPI_MODE_0
-
-#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-#define CONFIG_ENV_OFFSET (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE)
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
/* Enable keyboard */
#define CONFIG_TEGRA2_KEYBOARD
#define CONFIG_KEYBOARD
#define TEGRA2_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \
"stdout=serial\0" \
"stderr=serial\0"
+
+#include "tegra2-common-post.h"
+
#endif /* __CONFIG_H */
* Common configurations used for both spear3xx as well as spear6xx
*/
+/* U-boot Load Address */
+#define CONFIG_SYS_TEXT_BASE 0x00700000
+
+/* Ethernet driver configuration */
+#define CONFIG_MII
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_SEARCH_PHY
+#define CONFIG_DW0_PHY 1
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
+#define CONFIG_DW_AUTONEG
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+
/* USBD driver configuration */
+#if defined(CONFIG_SPEAR_USBTTY)
#define CONFIG_DW_UDC
#define CONFIG_USB_DEVICE
+#define CONFIG_USBD_HS
#define CONFIG_USB_TTY
#define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC"
#define CONFIG_USBD_MANUFACTURER "ST Microelectronics"
-#if defined(CONFIG_USB_TTY)
-#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0"
#endif
+#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0"
+
/* I2C driver configuration */
#define CONFIG_HARD_I2C
#define CONFIG_DW_I2C
#define CONFIG_I2C_CHIPADDRESS 0x50
/* Timer, HZ specific defines */
-#define CONFIG_SYS_HZ (1000)
-#define CONFIG_SYS_HZ_CLOCK (8300000)
+#define CONFIG_SYS_HZ 1000
/* Flash configuration */
#if defined(CONFIG_FLASH_PNOR)
-#define CONFIG_SPEAR_EMI 1
+#define CONFIG_SPEAR_EMI
#else
-#define CONFIG_SPEARSMI 1
+#define CONFIG_ST_SMI
#endif
-#if defined(CONFIG_SPEARSMI)
+#if defined(CONFIG_ST_SMI)
#define CONFIG_SYS_MAX_FLASH_BANKS 2
-#define CONFIG_SYS_FLASH_BASE (0xF8000000)
-#define CONFIG_SYS_CS1_FLASH_BASE (0xF9000000)
-#define CONFIG_SYS_FLASH_BANK_SIZE (0x01000000)
+#define CONFIG_SYS_FLASH_BASE 0xF8000000
+#define CONFIG_SYS_CS1_FLASH_BASE 0xF9000000
+#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
#define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \
CONFIG_SYS_CS1_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_SECT 128
-#define CONFIG_SYS_FLASH_EMPTY_INFO 1
#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
#define CONFIG_SYS_LOADS_BAUD_CHANGE
/* NAND FLASH Configuration */
+#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_NAND_SPEAR 1
+#define CONFIG_NAND_FSMC
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE 1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_QUIET_TEST
/*
* Command support defines
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_RUN
#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <config_cmd_default.h>
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
/*
* Default Environment Varible definitions
* U-Boot Environment placing definitions.
*/
#if defined(CONFIG_ENV_IS_IN_FLASH)
-#ifdef CONFIG_SPEARSMI
+#ifdef CONFIG_ST_SMI
/*
* Environment is in serial NOR flash
*/
#define CONFIG_SYS_MONITOR_LEN 0x00040000
#define CONFIG_ENV_SECT_SIZE 0x00010000
-#define CONFIG_FSMTDBLK "/dev/mtdblock8 "
+#define CONFIG_FSMTDBLK "/dev/mtdblock3 "
#define CONFIG_BOOTCOMMAND "bootm 0xf8050000"
"0x4C0000; bootm 0x1600000"
#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
CONFIG_SYS_MONITOR_LEN)
#elif defined(CONFIG_ENV_IS_IN_NAND)
/*
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_RANGE 0x10000
-#define CONFIG_FSMTDBLK "/dev/mtdblock12 "
+#define CONFIG_FSMTDBLK "/dev/mtdblock7 "
#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
"0x80000 0x4C0000; " \
"bootm 0x1600000"
#endif
-#define CONFIG_BOOTARGS_NFS "root=/dev/nfs ip=dhcp " \
- "console=ttyS0 init=/bin/sh"
-#define CONFIG_BOOTARGS "console=ttyS0 mem=128M " \
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
+ "mem=128M " \
"root="CONFIG_FSMTDBLK \
"rootfstype=jffs2"
+#define CONFIG_NFSBOOTCOMMAND \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):" \
+ "$(netmask):$(hostname):$(netdev):off " \
+ "console=ttyAMA0,115200 $(othbootargs);" \
+ "bootm; "
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=ttyAMA0,115200 $(othbootargs);" \
+ CONFIG_BOOTCOMMAND
+
+
#define CONFIG_ENV_SIZE 0x02000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
/* Miscellaneous configurable options */
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
-#define CONFIG_CMDLINE_TAG 1
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_MISC_INIT_R 1
-#define CONFIG_ZERO_BOOTDELAY_CHECK 1
-#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_MISC_INIT_R
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_STOP_STR " "
#define CONFIG_AUTOBOOT_PROMPT \
"Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR 0x00800000
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY
+#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Stack sizes */
#define CONFIG_STACKSIZE (128*1024)
* (easy to change)
*/
#if defined(CONFIG_spear300)
-#define CONFIG_SPEAR3XX 1
-#define CONFIG_SPEAR300 1
+#define CONFIG_SPEAR3XX
+#define CONFIG_SPEAR300
#elif defined(CONFIG_spear310)
-#define CONFIG_SPEAR3XX 1
-#define CONFIG_SPEAR310 1
+#define CONFIG_SPEAR3XX
+#define CONFIG_SPEAR310
#elif defined(CONFIG_spear320)
-#define CONFIG_SPEAR3XX 1
-#define CONFIG_SPEAR320 1
+#define CONFIG_SPEAR3XX
+#define CONFIG_SPEAR320
+#endif
+
+#if defined(CONFIG_usbtty)
+#define CONFIG_SPEAR_USBTTY
+#endif
+
+#if defined(CONFIG_nand)
+#define CONFIG_ENV_IS_IN_NAND
+#else
+#define CONFIG_ENV_IS_IN_FLASH
#endif
#include <configs/spear-common.h>
+/* Ethernet driver configuration */
+#define CONFIG_DW_ALTDESCRIPTOR
+
+#if defined(CONFIG_SPEAR310)
+#define CONFIG_MACB
+#define CONFIG_MACB0_PHY 0x01
+#define CONFIG_MACB1_PHY 0x03
+#define CONFIG_MACB2_PHY 0x05
+#define CONFIG_MACB3_PHY 0x07
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_MACB
+#define CONFIG_MACB0_PHY 0x01
+
+#endif
+
/* Serial Configuration (PL011) */
#define CONFIG_SYS_SERIAL0 0xD0000000
#define CONFIG_FLASH_CFI_DRIVER
#if defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_BASE 0x50000000
#define CONFIG_SYS_CS1_FLASH_BASE 0x60000000
#define CONFIG_SYS_CS2_FLASH_BASE 0x70000000
#define CONFIG_SYS_MAX_FLASH_BANKS 6
#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_BASE 0x44000000
#define CONFIG_SYS_CS1_FLASH_BASE 0x45000000
#define CONFIG_SYS_CS2_FLASH_BASE 0x46000000
#endif
#define CONFIG_SYS_MAX_FLASH_SECT (127 + 8)
-#define CONFIG_SYS_FLASH_QUIET_TEST 1
+#define CONFIG_SYS_FLASH_QUIET_TEST
#endif
+/* NAND flash configuration */
+#define CONFIG_SYS_FSMC_NAND_SP
+#define CONFIG_SYS_FSMC_NAND_8BIT
+
#if defined(CONFIG_SPEAR300)
-#define CONFIG_SYS_NAND_BASE (0x80000000)
+#define CONFIG_SYS_NAND_BASE 0x80000000
#elif defined(CONFIG_SPEAR310)
-#define CONFIG_SYS_NAND_BASE (0x40000000)
+#define CONFIG_SYS_NAND_BASE 0x40000000
#elif defined(CONFIG_SPEAR320)
-#define CONFIG_SYS_NAND_BASE (0x50000000)
+#define CONFIG_SYS_NAND_BASE 0x50000000
+
+#endif
+
+/* Environment Settings */
+#if defined(CONFIG_SPEAR300)
+#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY
+#elif defined(CONFIG_SPEAR310) || defined(CONFIG_SPEAR320)
+#define CONFIG_EXTRA_ENV_UNLOCK "unlock=yes\0"
+#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY \
+ CONFIG_EXTRA_ENV_UNLOCK
#endif
#endif /* __CONFIG_H */
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_SPEAR600 1
+#define CONFIG_SPEAR600
+
+#if defined(CONFIG_usbtty)
+#define CONFIG_SPEAR_USBTTY
+#endif
+
+#if defined(CONFIG_nand)
+#define CONFIG_ENV_IS_IN_NAND
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#endif
#include <configs/spear-common.h>
#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
(void *)CONFIG_SYS_SERIAL1 }
-#define CONFIG_SYS_NAND_BASE (0xD2000000)
+/* NAND flash configuration */
+#define CONFIG_SYS_FSMC_NAND_SP
+#define CONFIG_SYS_FSMC_NAND_8BIT
+#define CONFIG_SYS_NAND_BASE 0xD2000000
+
+/* Environment Settings */
+#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __TEGRA2_COMMON_POST_H
+#define __TEGRA2_COMMON_POST_H
+
+#ifdef CONFIG_BOOTCOMMAND
+
+#define BOOTCMDS_COMMON ""
+
+#else
+
+#ifdef CONFIG_CMD_EXT2
+#define BOOTCMD_FS_EXT2 "ext2 "
+#else
+#define BOOTCMD_FS_EXT2 ""
+#endif
+
+#ifdef CONFIG_CMD_FAT
+#define BOOTCMD_FS_FAT "fat"
+#else
+#define BOOTCMD_FS_FAT ""
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define BOOTCMDS_MMC \
+ "mmc_boot=" \
+ "setenv devtype mmc; " \
+ "if mmc dev ${devnum}; then " \
+ "run script_boot; " \
+ "fi\0" \
+ "mmc0_boot=setenv devnum 0; run mmc_boot;\0" \
+ "mmc1_boot=setenv devnum 1; run mmc_boot;\0" \
+ "bootcmd_mmc=run mmc1_boot; run mmc0_boot\0"
+#define BOOTCMD_MMC "run bootcmd_mmc; "
+#else
+#define BOOTCMDS_MMC ""
+#define BOOTCMD_MMC ""
+#endif
+
+#ifdef CONFIG_CMD_USB
+#define BOOTCMDS_USB \
+ "usb_boot=" \
+ "setenv devtype usb; " \
+ "if usb dev ${devnum}; then " \
+ "run script_boot; " \
+ "fi\0" \
+ "usb0_boot=setenv devnum 0; run usb_boot;\0" \
+ "bootcmd_usb=run usb0_boot\0"
+#define BOOTCMD_USB "run bootcmd_usb; "
+#define BOOTCMD_INIT_USB "usb start 0; "
+#else
+#define BOOTCMDS_USB ""
+#define BOOTCMD_USB ""
+#define BOOTCMD_INIT_USB ""
+#endif
+
+#ifdef CONFIG_CMD_DHCP
+#define BOOTCMDS_DHCP \
+ "bootcmd_dhcp=" \
+ "if dhcp ${scriptaddr} boot.scr.uimg; then "\
+ "source ${scriptaddr}; " \
+ "fi\0"
+#define BOOTCMD_DHCP "run bootcmd_dhcp; "
+#else
+#define BOOTCMDS_DHCP ""
+#define BOOTCMD_DHCP ""
+#endif
+
+#define BOOTCMDS_COMMON \
+ "scriptaddr=0x400000\0" \
+ "rootpart=1\0" \
+ "script_boot=" \
+ "for fs in " BOOTCMD_FS_EXT2 BOOTCMD_FS_FAT "; do " \
+ "for prefix in / /boot/; do " \
+ "for script in boot.scr.uimg boot.scr; do " \
+ "echo Scanning ${devtype} ${devnum}:${rootpart} ${fs} ${prefix}${script} ...; " \
+ "if ${fs}load ${devtype} ${devnum}:${rootpart} ${scriptaddr} ${prefix}${script}; then " \
+ "echo ${script} found! Executing ...;" \
+ "source ${scriptaddr};" \
+ "fi; " \
+ "done; " \
+ "done; " \
+ "done;\0" \
+ BOOTCMDS_MMC \
+ BOOTCMDS_USB \
+ BOOTCMDS_DHCP
+
+#define CONFIG_BOOTCOMMAND BOOTCMD_INIT_USB BOOTCMD_USB BOOTCMD_MMC BOOTCMD_DHCP
+
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ TEGRA2_DEVICE_SETTINGS \
+ BOOTCMDS_COMMON
+
+#endif /* __TEGRA2_COMMON_POST_H */
/*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010-2012
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
"stdout=serial\0" \
"stderr=serial\0"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=ttyS0,115200n8\0" \
- "mem=" TEGRA2_SYSMEM "\0" \
- "smpflag=smp\0" \
- TEGRA2_DEVICE_SETTINGS
-
#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
-#define CONFIG_TEGRA2_GPIO
+#define CONFIG_TEGRA_GPIO
#define CONFIG_CMD_GPIO
#endif /* __TEGRA2_COMMON_H */
--- /dev/null
+/*
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __CONFIG_TK71_H__
+#define __CONFIG_TK71_H__
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING "\nKa-Ro TK71"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
+#define CONFIG_KW88F6281 1 /* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define MACH_TYPE_TK71 2399
+#define CONFIG_MACH_TYPE MACH_TYPE_TK71
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * NAND flash
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_DEV "nand0,3"
+#endif
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS {1, 0}
+#define CONFIG_PHY_BASE_ADR 0x08
+#endif
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_KIRKWOOD
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_ADDR 0x80000
+#define CONFIG_ENV_OFFSET 0x80000
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND "nand read 0x800000 kernel 0x300000; bootm;"
+#define CONFIG_MTDPARTS "512K(u-boot),512K(u-boot-env),3M(kernel),-(root)"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "update_uboot=dhcp u-boot.kwb; nand erase.part u-boot; nand write ${fileaddr} u-boot ${filesize}\0" \
+ "update_kernel=dhcp uImage-tk71; nand erase.part kernel; nand write ${fileaddr} kernel ${filesize} \0" \
+ "update_rootfs=dhcp rootfs-tk71; nand erase.part root; nand write ${fileaddr} root ${filesize}\0" \
+ "update_all=run update_uboot; run update_kernel; run update_rootfs; reset\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts=mtdparts=orion_nand:"CONFIG_MTDPARTS"\0" \
+ "bootargs=console=ttyS0,115200 mtdparts=orion_nand:"CONFIG_MTDPARTS" rootfstype=jffs2 root=/dev/mtdblock3 rw\0"
+#define MTDIDS_DEFAULT "nand0=orion_nand"
+#define MTDPARTS_DEFAULT "mtdparts=orion_nand:"CONFIG_MTDPARTS
+
+#define PHYS_SDRAM_1 0x00000000 /* Base address */
+#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
+
+#endif /* __CONFIG_TK71_H__ */
--- /dev/null
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+#include "tegra2-common.h"
+
+/* Enable fdt support for TrimSlice. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE tegra2-trimslice
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT "Tegra2 (TrimSlice) # "
+#define CONFIG_TEGRA2_BOARD_STRING "Compulab Trimslice"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA2_ENABLE_UARTA
+#define CONFIG_TEGRA2_UARTA_GPU
+#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* SPI */
+#define CONFIG_TEGRA_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+
+/* I2C */
+#define CONFIG_TEGRA_I2C
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS 4
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_CMD_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+/* Environment in SPI */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MAX_HZ 48000000
+#define CONFIG_ENV_SPI_MODE SPI_MODE_0
+#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET (512 * 1024)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra2-common-post.h"
+
+#endif /* __CONFIG_H */
#include "tegra2-common.h"
/* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra2-seaboard
+#define CONFIG_DEFAULT_DEVICE_TREE tegra2-ventana
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
-#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M"
#define V_PROMPT "Tegra2 (Ventana) # "
#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Ventana"
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
-#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA2_MMC
+#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
-/* Environment not stored */
-#define CONFIG_ENV_IS_NOWHERE
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra2-common-post.h"
+
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2009-2012
+ * Jens Scharsig <esw@bus-elekronik.de>
+ * BuS Elektronik GmbH & Co. KG
+ *
+ * Configuation settings for the VL_MA2SC board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*--------------------------------------------------------------------------*/
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_ARM926EJS /* This is an ARM926EJS Core */
+#define CONFIG_AT91FAMILY
+#define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/
+#define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_MISC_INIT_R
+
+#include <asm/hardware.h>
+
+#define MACH_TYPE_VL_MA2SC 2412
+#define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC
+
+#define CONFIG_SYS_DCACHE_OFF
+
+#ifdef CONFIG_RAMLOAD
+#define CONFIG_SYS_TEXT_BASE 0x21000000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#endif
+#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
+
+#define CONFIG_IDENT_STRING " on MiS Activ 2"
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AT91_GPIO
+
+#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD)
+#define CONFIG_SYS_USE_NORFLASH
+#define CONFIG_SYS_USE_BOOT_NORFLASH
+#endif
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_WATCHDOG
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE ATMEL_BASE_DBGU
+#define CONFIG_USART_ID ATMEL_ID_SYS
+
+/* LCD */
+#define CONFIG_LCD
+#define CONFIG_ATMEL_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SYS_BLACK_ON_WHITE
+#define LCD_BPP LCD_COLOR8
+#define CONFIG_ATMEL_LCD_BGR555
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MD5SUM
+#define CONFIG_CMD_SHA1SUM
+/*
+#define CONFIG_CMD_SPI
+*/
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_MD5
+#define CONFIG_SHA1
+
+/*----------------------------------------------------------------------------
+ * Hardware confuguration
+ *---------------------------------------------------------------------------*/
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE
+#define CONFIG_AT91C_PQFP_UHPBUG
+
+/* I2C-Bus */
+
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
+
+#ifndef CONFIG_HARD_I2C
+#define CONFIG_SOFT_I2C
+
+/* Software I2C driver configuration */
+
+#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
+
+#define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */
+#define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */
+
+#define I2C_INIT i2c_init_board();
+#define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr);
+#define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder);
+#define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0)
+#define I2C_SDA(bit) \
+ do { \
+ if (bit) \
+ writel(AT91_PIN_SDA, &pio->piob.sodr); \
+ else \
+ writel(AT91_PIN_SDA, &pio->piob.codr); \
+ } while (0);
+#define I2C_SCL(bit) \
+ do { \
+ if (bit) \
+ writel(AT91_PIN_SCL, &pio->piob.sodr); \
+ else \
+ writel(AT91_PIN_SCL, &pio->piob.codr); \
+ } while (0);
+#endif
+
+/* I2C-RTC */
+
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_DS1338
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#endif
+
+/* EEPROM */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
+#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
+
+/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
+ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
+ AT91_MATRIX_CSA_EBI_CS1A)
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL \
+ (AT91_RSTC_KEY | \
+ AT91_RSTC_MR_URSTEN | \
+ AT91_RSTC_MR_ERSTL(15))
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL \
+ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
+ AT91_WDT_MR_WDV(0xFFF) | \
+ AT91_WDT_MR_WDDIS | \
+ AT91_WDT_MR_WDD(0xFFF))
+
+/* clocks */
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
+
+#define MHZ180
+#if defined(MHZ199)
+/* 199,8994 MHZ */
+#define MASTER_PLL_MUL 911
+#define MASTER_PLL_DIV 56
+#define MASTER_PLL_OUT 2
+#elif defined(MHZ180)
+/* 180 MHZ */
+#define MASTER_PLL_MUL 1875
+#define MASTER_PLL_DIV 128
+#define MASTER_PLL_OUT 2
+#elif defined(MHZTEST)
+/* Test MHZ */
+#define CONFIG_DISPLAY_CPUINFO
+#define MASTER_PLL_MUL 8
+#define MASTER_PLL_DIV 1
+#define MASTER_PLL_OUT 2
+#else
+/* 176.9472 MHZ */
+#define MASTER_PLL_MUL 72
+#define MASTER_PLL_DIV 5
+#define MASTER_PLL_OUT 2
+#endif
+
+#define CONFIG_SYS_MOR_VAL \
+ (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
+
+#define CONFIG_SYS_PLLAR_VAL \
+ (AT91_PMC_PLLAR_29 | \
+ AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
+ AT91_PMC_PLLXR_PLLCOUNT(63) | \
+ AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
+ AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define CONFIG_SYS_MCKR1_VAL \
+ (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
+ AT91_PMC_MCKR_MDIV_2)
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define CONFIG_SYS_MCKR2_VAL \
+ (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
+ AT91_PMC_MCKR_MDIV_2)
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
+#define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */
+
+#define CONFIG_SYS_SDRC_MR_VAL1 0
+#define CONFIG_SYS_SDRC_TR_VAL1 700
+#define CONFIG_SYS_SDRC_CR_VAL \
+ (AT91_SDRAMC_NC_9 | \
+ AT91_SDRAMC_NR_13 | \
+ AT91_SDRAMC_NB_4 | \
+ AT91_SDRAMC_CAS_3 | \
+ AT91_SDRAMC_DBW_32 | \
+ (2 << 8) | /* Write Recovery Delay */ \
+ (7 << 12) | /* Row Cycle Delay */ \
+ (2 << 16) | /* Row Precharge Delay */ \
+ (2 << 20) | /* Row to Column Delay */ \
+ (5 << 24) | /* Active to Precharge Delay */ \
+ (8 << 28)) /* Exit Self Refresh to Active Delay */
+
+#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
+
+/* NOR flash */
+
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define PHYS_FLASH_1 0x10000000
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
+#define CONFIG_SYS_SMC0_SETUP0_VAL \
+ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
+ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL \
+ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
+ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL \
+ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL \
+ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
+ AT91_SMC_MODE_DBW_16 | \
+ AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_DBW_8 1
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 0
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI
+#define CONFIG_NET_RETRY_COUNT 5
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END 0x21e00000
+
+/* Address and size of Primary Environment Sector */
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE 0x20000
+#else
+#define CONFIG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \
+ 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT "U-Boot> "
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN \
+ ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifndef CONFIG_RAMLOAD
+#define CONFIG_BOOTCOMMAND "run nfsboot"
+#endif
+#define CONFIG_BOOT_RETRY_TIME -1
+#define CONFIG_BOOT_RETRY_MIN 15
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "dhcp $(copy_addr) $(kernelname);" \
+ "run bootargsdefaults;" \
+ "set bootargs $(bootargs) boot=nfs " \
+ ";echo $(bootargs)" \
+ ";bootm"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ubootaddr=10000000\0" \
+ "splashimage=10080000\0" \
+ "kerneladdr=100A0000\0" \
+ "kernelsize=00800000\0" \
+ "minifsaddr=108A0000\0" \
+ "minifssize=00060000\0" \
+ "rootfsaddr=10900000\0" \
+ "copy_addr=20200000\0" \
+ "rootfssize=01700000\0" \
+ "kernelname=uImage_vl_ma2sc\0" \
+ "bootargsdefaults=set bootargs " \
+ "console=ttyS0,115200 " \
+ "video=atmel_lcdfb " \
+ "mem=62M " \
+ "panic=10 " \
+ "boardrevison=\\\"${revision}\\\" " \
+ "uboot=\\\"${ver}\\\" " \
+ "\0" \
+ "update_all=run update_kernel;run update_root;" \
+ "run update_splash; run update_uboot\0" \
+ "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
+ "dhcp $(copy_addr) $(kernelname);" \
+ "erase $(kerneladdr) +$(kernelsize);" \
+ "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
+ "protect on $(kerneladdr) +$(kernelsize)" \
+ "\0" \
+ "update_root=protect off $(rootfsaddr) +$(rootfssize);" \
+ "dhcp $(copy_addr) vl_ma2sc.root;" \
+ "erase $(rootfsaddr) +$(rootfssize);" \
+ "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
+ "\0" \
+ "update_splash=protect off $(splashimage) +20000;" \
+ "dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \
+ "erase $(splashimage) +20000;" \
+ "cp.b $(fileaddr) 10080000 $(filesize);" \
+ "protect on $(splashimage) +20000\0" \
+ "update_uboot=protect off 10000000 1005FFFF;" \
+ "dhcp $(copy_addr) u-boot_vl_ma2sc;" \
+ "erase 10000000 1005FFFF;" \
+ "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
+ "protect on 10000000 1005FFFF;reset\0" \
+ "emergency=run bootargsdefaults;" \
+ "set bootargs $(bootargs) root=initramfs boot=emergency " \
+ ";bootm $(kerneladdr)\0" \
+ "netemergency=run bootargsdefaults;" \
+ "dhcp $(copy_addr) $(kernelname);" \
+ "set bootargs $(bootargs) root=initramfs boot=emergency " \
+ ";bootm $(copy_addr)\0" \
+ "norboot=run bootargsdefaults;" \
+ "set bootargs $(bootargs) root=initramfs boot=local quiet " \
+ ";bootm $(kerneladdr)\0" \
+ "nandboot=run bootargsdefaults;" \
+ "set bootargs $(bootargs) root=initramfs boot=nand " \
+ ";bootm $(kerneladdr)\0" \
+ "setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \
+ "clearenv=protect off 10060000 1007FFFF;" \
+ "erase 10060000 1007FFFF;reset\0" \
+ " "
+
+/*--------------------------------------------------------------------------*/
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+#include "tegra2-common.h"
+
+/* Enable fdt support for Whistler. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE tegra2-whistler
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT "Tegra2 (Whistler) # "
+#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Whistler"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA2_ENABLE_UARTA
+#define CONFIG_TEGRA2_UARTA_UAA_UAB
+#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_TEGRA_I2C
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS 4
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_CMD_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+/*
+ * Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes
+ * the user plugged the standard 8MB MoviNAND card into J29/HSMMC/POP. If
+ * they didn't, the boot sector layout may be different. However, use of that
+ * particular card is standard practice as far as I know.
+ */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra2-common-post.h"
+
+#endif /* __CONFIG_H */
#undef CONFIG_BOARD_LATE_INIT
#undef CONFIG_USE_IRQ
#undef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_PREBOOT
/*
* Environment settings
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSMC_NAND_H__
+#define __FSMC_NAND_H__
+
+#include <linux/mtd/nand.h>
+
+struct fsmc_regs {
+ u32 ctrl; /* 0x00 */
+ u8 reserved_1[0x40 - 0x04];
+ u32 pc; /* 0x40 */
+ u32 sts; /* 0x44 */
+ u32 comm; /* 0x48 */
+ u32 attrib; /* 0x4c */
+ u32 ioata; /* 0x50 */
+ u32 ecc1; /* 0x54 */
+ u32 ecc2; /* 0x58 */
+ u32 ecc3; /* 0x5c */
+ u8 reserved_2[0xfe0 - 0x60];
+ u32 peripid0; /* 0xfe0 */
+ u32 peripid1; /* 0xfe4 */
+ u32 peripid2; /* 0xfe8 */
+ u32 peripid3; /* 0xfec */
+ u32 pcellid0; /* 0xff0 */
+ u32 pcellid1; /* 0xff4 */
+ u32 pcellid2; /* 0xff8 */
+ u32 pcellid3; /* 0xffc */
+};
+
+/* ctrl register definitions */
+#define FSMC_WP (1 << 7)
+
+/* pc register definitions */
+#define FSMC_RESET (1 << 0)
+#define FSMC_WAITON (1 << 1)
+#define FSMC_ENABLE (1 << 2)
+#define FSMC_DEVTYPE_NAND (1 << 3)
+#define FSMC_DEVWID_8 (0 << 4)
+#define FSMC_DEVWID_16 (1 << 4)
+#define FSMC_ECCEN (1 << 6)
+#define FSMC_ECCPLEN_512 (0 << 7)
+#define FSMC_ECCPLEN_256 (1 << 7)
+#define FSMC_TCLR_1 (1 << 9)
+#define FSMC_TAR_1 (1 << 13)
+
+/* sts register definitions */
+#define FSMC_CODE_RDY (1 << 15)
+
+/* comm register definitions */
+#define FSMC_TSET_0 (0 << 0)
+#define FSMC_TWAIT_6 (6 << 8)
+#define FSMC_THOLD_4 (4 << 16)
+#define FSMC_THIZ_1 (1 << 24)
+
+/* peripid2 register definitions */
+#define FSMC_REVISION_MSK (0xf)
+#define FSMC_REVISION_SHFT (0x4)
+
+#define FSMC_VER8 0x8
+
+/*
+ * There are 13 bytes of ecc for every 512 byte block and it has to be read
+ * consecutively and immediately after the 512 byte data block for hardware to
+ * generate the error bit offsets
+ * Managing the ecc bytes in the following way is easier. This way is similar to
+ * oobfree structure maintained already in u-boot nand driver
+ */
+#define FSMC_MAX_ECCPLACE_ENTRIES 32
+
+struct fsmc_nand_eccplace {
+ u32 offset;
+ u32 length;
+};
+
+struct fsmc_eccplace {
+ struct fsmc_nand_eccplace eccplace[FSMC_MAX_ECCPLACE_ENTRIES];
+};
+
+extern int fsmc_nand_init(struct nand_chip *nand);
+#endif
* MA 02111-1307 USA
*/
-#ifndef SPR_SMI_H
-#define SPR_SMI_H
+#ifndef ST_SMI_H
+#define ST_SMI_H
/* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */
/* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */
};
#define SFLASH_PAGE_SIZE 0x100 /* flash page size */
-#define XFER_FINISH_TOUT 2 /* xfer finish timeout */
-#define WMODE_TOUT 2 /* write enable timeout */
+#define XFER_FINISH_TOUT 15 /* xfer finish timeout(in ms) */
+#define WMODE_TOUT 15 /* write enable timeout(in ms) */
+
+extern void smi_init(void);
#endif
extern int eth_getenv_enetaddr_by_index(const char *base_name, int index,
uchar *enetaddr);
+#ifdef CONFIG_RANDOM_MACADDR
+/*
+ * The u-boot policy does not allow hardcoded ethernet addresses. Under the
+ * following circumstances a random generated address is allowed:
+ * - in emergency cases, where you need a working network connection to set
+ * the ethernet address.
+ * Eg. you want a rescue boot and don't have a serial port to access the
+ * CLI to set environment variables.
+ *
+ * In these cases, we generate a random locally administered ethernet address.
+ *
+ * Args:
+ * enetaddr - returns 6 byte hardware address
+ */
+extern void eth_random_enetaddr(uchar *enetaddr);
+#endif
+
extern int usb_eth_initialize(bd_t *bi);
extern int eth_init(bd_t *bis); /* Initialize the device */
extern int eth_send(void *packet, int length); /* Send a packet */
int cs8900_initialize(u8 dev_num, int base_addr);
int davinci_emac_initialize(void);
int dc21x4x_initialize(bd_t *bis);
-int designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
+int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface);
int dm9000_initialize(bd_t *bis);
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
int e1000_initialize(bd_t *bis);
COBJS-$(CONFIG_USB_TTY) += circbuf.o
COBJS-y += crc7.o
COBJS-y += crc16.o
-COBJS-y += crc32.o
COBJS-y += display_options.o
COBJS-y += errno.o
COBJS-$(CONFIG_OF_CONTROL) += fdtdec.o
ifdef CONFIG_SPL_BUILD
COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
endif
+COBJS-y += crc32.o
COBJS-y += ctype.o
COBJS-y += div64.o
COBJS-y += string.o
COBJS-y += time.o
COBJS-$(CONFIG_BOOTP_PXE) += uuid.o
COBJS-y += vsprintf.o
+COBJS-$(CONFIG_RANDOM_MACADDR) += rand.o
+COBJS-$(CONFIG_BOOTP_RANDOM_DELAY) += rand.o
+COBJS-$(CONFIG_CMD_LINK_LOCAL) += rand.o
-COBJS := $(COBJS-y)
+COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null
+/*
+ * Simple xorshift PRNG
+ * see http://www.jstatsoft.org/v08/i14/paper
+ *
+ * Copyright (c) 2012 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+static unsigned int y = 1U;
+
+unsigned int rand_r(unsigned int *seedp)
+{
+ *seedp ^= (*seedp << 13);
+ *seedp ^= (*seedp >> 17);
+ *seedp ^= (*seedp << 5);
+
+ return *seedp;
+}
+
+unsigned int rand(void)
+{
+ return rand_r(&y);
+}
+
+void srand(unsigned int seed)
+{
+ y = seed;
+}
COBJS-$(CONFIG_CMD_NET) += eth.o
COBJS-$(CONFIG_CMD_LINK_LOCAL) += link_local.o
COBJS-$(CONFIG_CMD_NET) += net.o
-COBJS-$(CONFIG_BOOTP_RANDOM_DELAY) += net_rand.o
-COBJS-$(CONFIG_CMD_LINK_LOCAL) += net_rand.o
COBJS-$(CONFIG_CMD_NFS) += nfs.o
COBJS-$(CONFIG_CMD_PING) += ping.o
COBJS-$(CONFIG_CMD_RARP) += rarp.o
return ((skip_state = getenv(enetvar)) != NULL);
}
+#ifdef CONFIG_RANDOM_MACADDR
+void eth_random_enetaddr(uchar *enetaddr)
+{
+ uint32_t rval;
+
+ srand(get_timer(0));
+
+ rval = rand();
+ enetaddr[0] = rval & 0xff;
+ enetaddr[1] = (rval >> 8) & 0xff;
+ enetaddr[2] = (rval >> 16) & 0xff;
+
+ rval = rand();
+ enetaddr[3] = rval & 0xff;
+ enetaddr[4] = (rval >> 8) & 0xff;
+ enetaddr[5] = (rval >> 16) & 0xff;
+
+ /* make sure it's local and unicast */
+ enetaddr[0] = (enetaddr[0] | 0x02) & ~0x01;
+}
+#endif
+
/*
* CPU and board-specific Ethernet initializations. Aliased function
* signals caller to move on
static unsigned nprobes;
static unsigned nclaims;
static int ready;
+static unsigned int seed;
static void link_local_timeout(void);
unsigned tmp;
do {
- tmp = rand() & IN_CLASSB_HOST;
+ tmp = rand_r(&seed) & IN_CLASSB_HOST;
} while (tmp > (IN_CLASSB_HOST - 0x0200));
return (IPaddr_t) htonl((LINKLOCAL_ADDR + 0x0100) + tmp);
}
*/
static inline unsigned random_delay_ms(unsigned secs)
{
- return rand() % (secs * 1000);
+ return rand_r(&seed) % (secs * 1000);
}
static void configure_wait(void)
}
NetOurSubnetMask = IN_CLASSB_NET;
- srand_mac();
+ seed = seed_mac();
if (ip == 0)
ip = pick();
+++ /dev/null
-/*
- * Based on LiMon - BOOTP.
- *
- * Copyright 1994, 1995, 2000 Neil Russell.
- * (See License)
- * Copyright 2000 Roland Borde
- * Copyright 2000 Paolo Scaffardi
- * Copyright 2000-2004 Wolfgang Denk, wd@denx.de
- */
-
-#include <common.h>
-#include <net.h>
-#include "net_rand.h"
-
-static ulong seed1, seed2;
-
-void srand_mac(void)
-{
- ulong tst1, tst2, m_mask;
- ulong m_value = 0;
- int reg;
- unsigned char bi_enetaddr[6];
-
- /* get our mac */
- eth_getenv_enetaddr("ethaddr", bi_enetaddr);
-
- debug("BootpRequest => Our Mac: ");
- for (reg = 0; reg < 6; reg++)
- debug("%x%c", bi_enetaddr[reg], reg == 5 ? '\n' : ':');
-
- /* Mac-Manipulation 2 get seed1 */
- tst1 = 0;
- tst2 = 0;
- for (reg = 2; reg < 6; reg++) {
- tst1 = tst1 << 8;
- tst1 = tst1 | bi_enetaddr[reg];
- }
- for (reg = 0; reg < 2; reg++) {
- tst2 = tst2 | bi_enetaddr[reg];
- tst2 = tst2 << 8;
- }
-
- seed1 = tst1^tst2;
-
- /* Mirror seed1*/
- m_mask = 0x1;
- for (reg = 1; reg <= 32; reg++) {
- m_value |= (m_mask & seed1);
- seed1 = seed1 >> 1;
- m_value = m_value << 1;
- }
- seed1 = m_value;
- seed2 = 0xb78d0945;
-}
-
-unsigned long rand(void)
-{
- ulong sum;
-
- /* Random Number Generator */
- sum = seed1 + seed2;
- if (sum < seed1 || sum < seed2)
- sum++;
- seed2 = seed1;
- seed1 = sum;
-
- return sum;
-}
#ifndef __NET_RAND_H__
#define __NET_RAND_H__
-#define RAND_MAX 0xffffffff
+#include <common.h>
/*
- * Seed the random number generator using the eth0 MAC address
+ * Return a seed for the PRNG derived from the eth0 MAC address.
*/
-void srand_mac(void);
+static inline unsigned int seed_mac(void)
+{
+ unsigned char enetaddr[6];
+ unsigned int seed;
+
+ /* get our mac */
+ eth_getenv_enetaddr("ethaddr", enetaddr);
+
+ seed = enetaddr[5];
+ seed ^= enetaddr[4] << 8;
+ seed ^= enetaddr[3] << 16;
+ seed ^= enetaddr[2] << 24;
+ seed ^= enetaddr[1];
+ seed ^= enetaddr[0] << 8;
+
+ return seed;
+}
/*
- * Get a random number (after seeding with MAC address)
- *
- * @return random number
+ * Seed the random number generator using the eth0 MAC address.
*/
-unsigned long rand(void);
+static inline void srand_mac(void)
+{
+ srand(seed_mac());
+}
#endif /* __NET_RAND_H__ */
BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
+BIN_FILES-$(CONFIG_KIRKWOOD) += kwboot$(SFX)
# Source files which exist outside the tools directory
EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o
NOPED_OBJ_FILES-y += os_support.o
OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
NOPED_OBJ_FILES-y += ublimage.o
+OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
# Don't build by default
#ifeq ($(ARCH),ppc)
$(obj)ubsha1$(SFX): $(obj)os_support.o $(obj)sha1.o $(obj)ubsha1.o
$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+$(obj)kwboot$(SFX): $(obj)kwboot.o
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+ $(HOSTSTRIP) $@
+
# Some of the tool objects need to be accessed from outside the tools directory
$(obj)%.o: $(SRCTREE)/common/%.c
$(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
--- /dev/null
+/*
+ * Boot a Marvell Kirkwood SoC, with Xmodem over UART0.
+ *
+ * (c) 2012 Daniel Stodden <daniel.stodden@gmail.com>
+ *
+ * References: marvell.com, "88F6180, 88F6190, 88F6192, and 88F6281
+ * Integrated Controller: Functional Specifications" December 2,
+ * 2008. Chapter 24.2 "BootROM Firmware".
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdarg.h>
+#include <libgen.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <unistd.h>
+#include <stdint.h>
+#include <termios.h>
+#include <sys/mman.h>
+#include <sys/stat.h>
+
+#include "kwbimage.h"
+
+#ifdef __GNUC__
+#define PACKED __attribute((packed))
+#else
+#define PACKED
+#endif
+
+/*
+ * Marvell BootROM UART Sensing
+ */
+
+static unsigned char kwboot_msg_boot[] = {
+ 0xBB, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
+};
+
+#define KWBOOT_MSG_REQ_DELAY 10 /* ms */
+#define KWBOOT_MSG_RSP_TIMEO 50 /* ms */
+
+/*
+ * Xmodem Transfers
+ */
+
+#define SOH 1 /* sender start of block header */
+#define EOT 4 /* sender end of block transfer */
+#define ACK 6 /* target block ack */
+#define NAK 21 /* target block negative ack */
+#define CAN 24 /* target/sender transfer cancellation */
+
+struct kwboot_block {
+ uint8_t soh;
+ uint8_t pnum;
+ uint8_t _pnum;
+ uint8_t data[128];
+ uint8_t csum;
+} PACKED;
+
+#define KWBOOT_BLK_RSP_TIMEO 1000 /* ms */
+
+static int kwboot_verbose;
+
+static void
+kwboot_printv(const char *fmt, ...)
+{
+ va_list ap;
+
+ if (kwboot_verbose) {
+ va_start(ap, fmt);
+ vprintf(fmt, ap);
+ va_end(ap);
+ fflush(stdout);
+ }
+}
+
+static void
+__spinner(void)
+{
+ const char seq[] = { '-', '\\', '|', '/' };
+ const int div = 8;
+ static int state, bs;
+
+ if (state % div == 0) {
+ fputc(bs, stdout);
+ fputc(seq[state / div % sizeof(seq)], stdout);
+ fflush(stdout);
+ }
+
+ bs = '\b';
+ state++;
+}
+
+static void
+kwboot_spinner(void)
+{
+ if (kwboot_verbose)
+ __spinner();
+}
+
+static void
+__progress(int pct, char c)
+{
+ const int width = 70;
+ static const char *nl = "";
+ static int pos;
+
+ if (pos % width == 0)
+ printf("%s%3d %% [", nl, pct);
+
+ fputc(c, stdout);
+
+ nl = "]\n";
+ pos++;
+
+ if (pct == 100) {
+ while (pos++ < width)
+ fputc(' ', stdout);
+ fputs(nl, stdout);
+ }
+
+ fflush(stdout);
+
+}
+
+static void
+kwboot_progress(int _pct, char c)
+{
+ static int pct;
+
+ if (_pct != -1)
+ pct = _pct;
+
+ if (kwboot_verbose)
+ __progress(pct, c);
+}
+
+static int
+kwboot_tty_recv(int fd, void *buf, size_t len, int timeo)
+{
+ int rc, nfds;
+ fd_set rfds;
+ struct timeval tv;
+ ssize_t n;
+
+ rc = -1;
+
+ FD_ZERO(&rfds);
+ FD_SET(fd, &rfds);
+
+ tv.tv_sec = 0;
+ tv.tv_usec = timeo * 1000;
+ if (tv.tv_usec > 1000000) {
+ tv.tv_sec += tv.tv_usec / 1000000;
+ tv.tv_usec %= 1000000;
+ }
+
+ do {
+ nfds = select(fd + 1, &rfds, NULL, NULL, &tv);
+ if (nfds < 0)
+ goto out;
+ if (!nfds) {
+ errno = ETIMEDOUT;
+ goto out;
+ }
+
+ n = read(fd, buf, len);
+ if (n < 0)
+ goto out;
+
+ buf = (char *)buf + n;
+ len -= n;
+ } while (len > 0);
+
+ rc = 0;
+out:
+ return rc;
+}
+
+static int
+kwboot_tty_send(int fd, const void *buf, size_t len)
+{
+ int rc;
+ ssize_t n;
+
+ rc = -1;
+
+ do {
+ n = write(fd, buf, len);
+ if (n < 0)
+ goto out;
+
+ buf = (char *)buf + n;
+ len -= n;
+ } while (len > 0);
+
+ rc = tcdrain(fd);
+out:
+ return rc;
+}
+
+static int
+kwboot_tty_send_char(int fd, unsigned char c)
+{
+ return kwboot_tty_send(fd, &c, 1);
+}
+
+static speed_t
+kwboot_tty_speed(int baudrate)
+{
+ switch (baudrate) {
+ case 115200:
+ return B115200;
+ case 57600:
+ return B57600;
+ case 38400:
+ return B38400;
+ case 19200:
+ return B19200;
+ case 9600:
+ return B9600;
+ }
+
+ return -1;
+}
+
+static int
+kwboot_open_tty(const char *path, speed_t speed)
+{
+ int rc, fd;
+ struct termios tio;
+
+ rc = -1;
+
+ fd = open(path, O_RDWR|O_NOCTTY|O_NDELAY);
+ if (fd < 0)
+ goto out;
+
+ memset(&tio, 0, sizeof(tio));
+
+ tio.c_iflag = 0;
+ tio.c_cflag = CREAD|CLOCAL|CS8;
+
+ tio.c_cc[VMIN] = 1;
+ tio.c_cc[VTIME] = 10;
+
+ cfsetospeed(&tio, speed);
+ cfsetispeed(&tio, speed);
+
+ rc = tcsetattr(fd, TCSANOW, &tio);
+ if (rc)
+ goto out;
+
+ rc = fd;
+out:
+ if (rc < 0) {
+ if (fd >= 0)
+ close(fd);
+ }
+
+ return rc;
+}
+
+static int
+kwboot_bootmsg(int tty, void *msg)
+{
+ int rc;
+ char c;
+
+ kwboot_printv("Sending boot message. Please reboot the target...");
+
+ do {
+ rc = tcflush(tty, TCIOFLUSH);
+ if (rc)
+ break;
+
+ rc = kwboot_tty_send(tty, msg, 8);
+ if (rc) {
+ usleep(KWBOOT_MSG_REQ_DELAY * 1000);
+ continue;
+ }
+
+ rc = kwboot_tty_recv(tty, &c, 1, KWBOOT_MSG_RSP_TIMEO);
+
+ kwboot_spinner();
+
+ } while (rc || c != NAK);
+
+ kwboot_printv("\n");
+
+ return rc;
+}
+
+static int
+kwboot_xm_makeblock(struct kwboot_block *block, const void *data,
+ size_t size, int pnum)
+{
+ const size_t blksz = sizeof(block->data);
+ size_t n;
+ int i;
+
+ block->pnum = pnum;
+ block->_pnum = ~block->pnum;
+
+ n = size < blksz ? size : blksz;
+ memcpy(&block->data[0], data, n);
+ memset(&block->data[n], 0, blksz - n);
+
+ block->csum = 0;
+ for (i = 0; i < n; i++)
+ block->csum += block->data[i];
+
+ return n;
+}
+
+static int
+kwboot_xm_sendblock(int fd, struct kwboot_block *block)
+{
+ int rc, retries;
+ char c;
+
+ retries = 16;
+ do {
+ rc = kwboot_tty_send(fd, block, sizeof(*block));
+ if (rc)
+ break;
+
+ rc = kwboot_tty_recv(fd, &c, 1, KWBOOT_BLK_RSP_TIMEO);
+ if (rc)
+ break;
+
+ if (c != ACK)
+ kwboot_progress(-1, '+');
+
+ } while (c == NAK && retries-- > 0);
+
+ rc = -1;
+
+ switch (c) {
+ case ACK:
+ rc = 0;
+ break;
+ case NAK:
+ errno = EBADMSG;
+ break;
+ case CAN:
+ errno = ECANCELED;
+ break;
+ default:
+ errno = EPROTO;
+ break;
+ }
+
+ return rc;
+}
+
+static int
+kwboot_xmodem(int tty, const void *_data, size_t size)
+{
+ const uint8_t *data = _data;
+ int rc, pnum, N, err;
+
+ pnum = 1;
+ N = 0;
+
+ kwboot_printv("Sending boot image...\n");
+
+ do {
+ struct kwboot_block block;
+ int n;
+
+ n = kwboot_xm_makeblock(&block,
+ data + N, size - N,
+ pnum++);
+ if (n < 0)
+ goto can;
+
+ if (!n)
+ break;
+
+ rc = kwboot_xm_sendblock(tty, &block);
+ if (rc)
+ goto out;
+
+ N += n;
+ kwboot_progress(N * 100 / size, '.');
+ } while (1);
+
+ rc = kwboot_tty_send_char(tty, EOT);
+
+out:
+ return rc;
+
+can:
+ err = errno;
+ kwboot_tty_send_char(tty, CAN);
+ errno = err;
+ goto out;
+}
+
+static int
+kwboot_term_pipe(int in, int out, char *quit, int *s)
+{
+ ssize_t nin, nout;
+ char _buf[128], *buf = _buf;
+
+ nin = read(in, buf, sizeof(buf));
+ if (nin < 0)
+ return -1;
+
+ if (quit) {
+ int i;
+
+ for (i = 0; i < nin; i++) {
+ if (*buf == quit[*s]) {
+ (*s)++;
+ if (!quit[*s])
+ return 0;
+ buf++;
+ nin--;
+ } else
+ while (*s > 0) {
+ nout = write(out, quit, *s);
+ if (nout <= 0)
+ return -1;
+ (*s) -= nout;
+ }
+ }
+ }
+
+ while (nin > 0) {
+ nout = write(out, buf, nin);
+ if (nout <= 0)
+ return -1;
+ nin -= nout;
+ }
+
+ return 0;
+}
+
+static int
+kwboot_terminal(int tty)
+{
+ int rc, in, s;
+ char *quit = "\34c";
+ struct termios otio, tio;
+
+ rc = -1;
+
+ in = STDIN_FILENO;
+ if (isatty(in)) {
+ rc = tcgetattr(in, &otio);
+ if (!rc) {
+ tio = otio;
+ cfmakeraw(&tio);
+ rc = tcsetattr(in, TCSANOW, &tio);
+ }
+ if (rc) {
+ perror("tcsetattr");
+ goto out;
+ }
+
+ kwboot_printv("[Type Ctrl-%c + %c to quit]\r\n",
+ quit[0]|0100, quit[1]);
+ } else
+ in = -1;
+
+ rc = 0;
+ s = 0;
+
+ do {
+ fd_set rfds;
+ int nfds = 0;
+
+ FD_SET(tty, &rfds);
+ nfds = nfds < tty ? tty : nfds;
+
+ if (in >= 0) {
+ FD_SET(in, &rfds);
+ nfds = nfds < in ? in : nfds;
+ }
+
+ nfds = select(nfds + 1, &rfds, NULL, NULL, NULL);
+ if (nfds < 0)
+ break;
+
+ if (FD_ISSET(tty, &rfds)) {
+ rc = kwboot_term_pipe(tty, STDOUT_FILENO, NULL, NULL);
+ if (rc)
+ break;
+ }
+
+ if (FD_ISSET(in, &rfds)) {
+ rc = kwboot_term_pipe(in, tty, quit, &s);
+ if (rc)
+ break;
+ }
+ } while (quit[s] != 0);
+
+ tcsetattr(in, TCSANOW, &otio);
+out:
+ return rc;
+}
+
+static void *
+kwboot_mmap_image(const char *path, size_t *size, int prot)
+{
+ int rc, fd, flags;
+ struct stat st;
+ void *img;
+
+ rc = -1;
+ fd = -1;
+ img = NULL;
+
+ fd = open(path, O_RDONLY);
+ if (fd < 0)
+ goto out;
+
+ rc = fstat(fd, &st);
+ if (rc)
+ goto out;
+
+ flags = (prot & PROT_WRITE) ? MAP_PRIVATE : MAP_SHARED;
+
+ img = mmap(NULL, st.st_size, prot, flags, fd, 0);
+ if (img == MAP_FAILED) {
+ img = NULL;
+ goto out;
+ }
+
+ rc = 0;
+ *size = st.st_size;
+out:
+ if (rc && img) {
+ munmap(img, st.st_size);
+ img = NULL;
+ }
+ if (fd >= 0)
+ close(fd);
+
+ return img;
+}
+
+static uint8_t
+kwboot_img_csum8(void *_data, size_t size)
+{
+ uint8_t *data = _data, csum;
+
+ for (csum = 0; size-- > 0; data++)
+ csum += *data;
+
+ return csum;
+}
+
+static int
+kwboot_img_patch_hdr(void *img, size_t size)
+{
+ int rc;
+ bhr_t *hdr;
+ uint8_t csum;
+ const size_t hdrsz = sizeof(*hdr);
+
+ rc = -1;
+ hdr = img;
+
+ if (size < hdrsz) {
+ errno = EINVAL;
+ goto out;
+ }
+
+ csum = kwboot_img_csum8(hdr, hdrsz) - hdr->checkSum;
+ if (csum != hdr->checkSum) {
+ errno = EINVAL;
+ goto out;
+ }
+
+ if (hdr->blockid == IBR_HDR_UART_ID) {
+ rc = 0;
+ goto out;
+ }
+
+ hdr->blockid = IBR_HDR_UART_ID;
+
+ hdr->nandeccmode = IBR_HDR_ECC_DISABLED;
+ hdr->nandpagesize = 0;
+
+ hdr->srcaddr = hdr->ext
+ ? sizeof(struct kwb_header)
+ : sizeof(*hdr);
+
+ hdr->checkSum = kwboot_img_csum8(hdr, hdrsz) - csum;
+
+ rc = 0;
+out:
+ return rc;
+}
+
+static void
+kwboot_usage(FILE *stream, char *progname)
+{
+ fprintf(stream,
+ "Usage: %s -b <image> [ -p ] [ -t ] "
+ "[-B <baud> ] <TTY>\n", progname);
+ fprintf(stream, "\n");
+ fprintf(stream, " -b <image>: boot <image>\n");
+ fprintf(stream, " -p: patch <image> to type 0x69 (uart boot)\n");
+ fprintf(stream, "\n");
+ fprintf(stream, " -t: mini terminal\n");
+ fprintf(stream, "\n");
+ fprintf(stream, " -B <baud>: set baud rate\n");
+ fprintf(stream, "\n");
+}
+
+int
+main(int argc, char **argv)
+{
+ const char *ttypath, *imgpath;
+ int rv, rc, tty, term, prot, patch;
+ void *bootmsg;
+ void *img;
+ size_t size;
+ speed_t speed;
+
+ rv = 1;
+ tty = -1;
+ bootmsg = NULL;
+ imgpath = NULL;
+ img = NULL;
+ term = 0;
+ patch = 0;
+ size = 0;
+ speed = B115200;
+
+ kwboot_verbose = isatty(STDOUT_FILENO);
+
+ do {
+ int c = getopt(argc, argv, "hb:ptB:");
+ if (c < 0)
+ break;
+
+ switch (c) {
+ case 'b':
+ bootmsg = kwboot_msg_boot;
+ imgpath = optarg;
+ break;
+
+ case 'p':
+ patch = 1;
+ break;
+
+ case 't':
+ term = 1;
+ break;
+
+ case 'B':
+ speed = kwboot_tty_speed(atoi(optarg));
+ if (speed == -1)
+ goto usage;
+ break;
+
+ case 'h':
+ rv = 0;
+ default:
+ goto usage;
+ }
+ } while (1);
+
+ if (!bootmsg && !term)
+ goto usage;
+
+ if (patch && !imgpath)
+ goto usage;
+
+ if (argc - optind < 1)
+ goto usage;
+
+ ttypath = argv[optind++];
+
+ tty = kwboot_open_tty(ttypath, speed);
+ if (tty < 0) {
+ perror(ttypath);
+ goto out;
+ }
+
+ if (imgpath) {
+ prot = PROT_READ | (patch ? PROT_WRITE : 0);
+
+ img = kwboot_mmap_image(imgpath, &size, prot);
+ if (!img) {
+ perror(imgpath);
+ goto out;
+ }
+ }
+
+ if (patch) {
+ rc = kwboot_img_patch_hdr(img, size);
+ if (rc) {
+ fprintf(stderr, "%s: Invalid image.\n", imgpath);
+ goto out;
+ }
+ }
+
+ if (bootmsg) {
+ rc = kwboot_bootmsg(tty, bootmsg);
+ if (rc) {
+ perror("bootmsg");
+ goto out;
+ }
+ }
+
+ if (img) {
+ rc = kwboot_xmodem(tty, img, size);
+ if (rc) {
+ perror("xmodem");
+ goto out;
+ }
+ }
+
+ if (term) {
+ rc = kwboot_terminal(tty);
+ if (rc && !(errno == EINTR)) {
+ perror("terminal");
+ goto out;
+ }
+ }
+
+ rv = 0;
+out:
+ if (tty >= 0)
+ close(tty);
+
+ if (img)
+ munmap(img, size);
+
+ return rv;
+
+usage:
+ kwboot_usage(rv ? stderr : stdout, basename(argv[0]));
+ goto out;
+}
projects / karo-tx-uboot.git / commitdiff