board/ti/dra7xx: add support for parallel NAND

This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC
chip-select[0] on DRA7xx EVM.
As GPMC pins are shared by multiple devices, so in addition to this patch
following board settings are required for NAND device detection [1]:

  SW5.9 (GPMC_WPN)   = OFF (logic-1)
  SW5.1 (NAND_BOOTn) = ON  (logic-0) /* Active-low */
  SW5.2 (NOR_BOOTn)  = OFF (logic-1)
  SW5.3 (eMMC_BOOTn) = OFF (logic-1)
  SW5.4 (QSPI_BOOTn) = OFF (logic-1)

And also set appropriate SYSBOOT configurations
  SW2.1 (SYSBOOT[0]) = ON  (logic-1) /* selects NAND Boot */
  SW2.2 (SYSBOOT[1]) = OFF (logic-0) /* selects NAND Boot */
  SW2.3 (SYSBOOT[2]) = OFF (logic-0) /* selects NAND Boot */
  SW2.4 (SYSBOOT[3]) = OFF (logic-0) /* selects NAND Boot */
  SW2.5 (SYSBOOT[4]) = ON  (logic-1) /* selects NAND Boot */
  SW2.6 (SYSBOOT[5]) = ON  (logic-1) /* selects NAND Boot */
  SW2.7 (SYSBOOT[6]) = OFF (logic-0) /* reserved */
  SW2.8 (SYSBOOT[7]) = OFF (logic-0) /* reserved */

  SW3.1 (SYSBOOT[ 8])= ON  (logic-1) /* selects SYS_CLK1 speed */
  SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
  SW3.3 (SYSBOOT[10])= ON  (logic-1) /* wait-pin monitoring = enabled */
  SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Addr/Data Muxed */
  SW3.5 (SYSBOOT[12])= ON  (logic-1) /* device type: Addr/Data Muxed */
  SW3.6 (SYSBOOT[13])= ON  (logic-1) /* device bus-width: 1(x16) */
  SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
  SW3.8 (SYSBOOT[15])= ON  (logic-1) /* reserved */

Following changes are required in board.cfg to enable NAND on J6-EVM:

diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 7db70324e9bc78a5d301bbbb1f75331969e77451..1ea236b4b8127c7dbc29af1bf52f942aa93e957f 100644 (file)
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -68,6 +68,33 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
        {VIN2A_D21, (IEN | M3)},
        {VIN2A_D22, (IEN | M3)},
        {VIN2A_D23, (IEN | M3)},
        {VIN2A_D21, (IEN | M3)},
        {VIN2A_D22, (IEN | M3)},
        {VIN2A_D23, (IEN | M3)},

+#ifdef CONFIG_NAND
+       /* NAND / NOR pin-mux */
+       {GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0  */
+       {GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1  */
+       {GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2  */
+       {GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3  */
+       {GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4  */
+       {GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5  */
+       {GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6  */
+       {GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7  */
+       {GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8  */
+       {GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9  */
+       {GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */
+       {GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */
+       {GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */
+       {GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */
+       {GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */
+       {GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */
+       {GPMC_CS0,      M0 | IDIS | PEN | PTU}, /* GPMC chip-select */
+       {GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */
+       {GPMC_OEN_REN,  M0 | IDIS | PEN | PTU}, /* GPMC Read enable */
+       {GPMC_WEN,      M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */
+       {GPMC_BEN0,     M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */
+       {GPMC_WAIT0,    M0 | IEN  | PEN | PTU}, /* GPMC Wait/Ready */
+       /* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */
+#else
+       /* QSPI pin-mux */

        {GPMC_A13, (IEN | PDIS | M1)},  /* QSPI1_RTCLK */
        {GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
        {GPMC_A15, (IEN | PDIS | M1)},  /* QSPI1_D[2] */
        {GPMC_A13, (IEN | PDIS | M1)},  /* QSPI1_RTCLK */
        {GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
        {GPMC_A15, (IEN | PDIS | M1)},  /* QSPI1_D[2] */


@@ -78,6 +105,7 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
        {GPMC_A4, (IEN | PDIS | M1)},   /* QSPI1_CS3 */
        {GPMC_CS2, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS0 */
        {GPMC_CS3, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS1*/
        {GPMC_A4, (IEN | PDIS | M1)},   /* QSPI1_CS3 */
        {GPMC_CS2, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS0 */
        {GPMC_CS3, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS1*/

+#endif /* CONFIG_NAND */

        {USB2_DRVVBUS, (M0 | IEN | FSC) },
 };
 #endif /* _MUX_DATA_DRA7XX_H_ */
        {USB2_DRVVBUS, (M0 | IEN | FSC) },
 };
 #endif /* _MUX_DATA_DRA7XX_H_ */

diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 8d0a0eb8bc65bd22a5bca333ab3c58f19b49a6be..10c88dcf96edd9d6c64a98fa0df0682ccbe93a16 100644 (file)
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -143,4 +143,54 @@
 #define CONFIG_SYS_SCSI_MAX_DEVICE     (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
                                                CONFIG_SYS_SCSI_MAX_LUN)
 
 #define CONFIG_SYS_SCSI_MAX_DEVICE     (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
                                                CONFIG_SYS_SCSI_MAX_LUN)
 

+/* NAND support */
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_PAGE_SIZE      2048
+#define CONFIG_SYS_NAND_OOBSIZE                64
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128*1024)
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+#define CONFIG_SYS_NAND_PAGE_COUNT     (CONFIG_SYS_NAND_BLOCK_SIZE / \
+                                        CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+/* NAND: driver related configs */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS  NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS         { 2, 3, 4, 5, 6, 7, 8, 9, \
+                                        10, 11, 12, 13, 14, 15, 16, 17, \
+                                        18, 19, 20, 21, 22, 23, 24, 25, \
+                                        26, 27, 28, 29, 30, 31, 32, 33, \
+                                        34, 35, 36, 37, 38, 39, 40, 41, \
+                                        42, 43, 44, 45, 46, 47, 48, 49, \
+                                        50, 51, 52, 53, 54, 55, 56, 57, }
+#define CONFIG_SYS_NAND_ECCSIZE                512
+#define CONFIG_SYS_NAND_ECCBYTES       14
+#define MTDIDS_DEFAULT                 "nand0=nand.0"
+#define MTDPARTS_DEFAULT               "mtdparts=nand.0:" \
+                                       "128k(NAND.SPL)," \
+                                       "128k(NAND.SPL.backup1)," \
+                                       "128k(NAND.SPL.backup2)," \
+                                       "128k(NAND.SPL.backup3)," \
+                                       "256k(NAND.u-boot-spl-os)," \
+                                       "1m(NAND.u-boot)," \
+                                       "128k(NAND.u-boot-env)," \
+                                       "128k(NAND.u-boot-env.backup1)," \
+                                       "8m(NAND.kernel)," \
+                                       "-(NAND.rootfs)"
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    0x000c0000
+/* NAND: SPL related configs */
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#endif
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS                0x00080000 /* os-boot params*/
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS        0x00200000 /* kernel offset */
+#define CONFIG_CMD_SPL_WRITE_SIZE      0x2000
+#endif
+#endif /* !CONFIG_NAND */
+

 #endif /* __CONFIG_DRA7XX_EVM_H */
 #endif /* __CONFIG_DRA7XX_EVM_H */