powerpc/b4860qds: Add the tlb entries for SRIO interfaces

Add the tlb entries based on the configuration of the SRIO interfaces.
Every SRIO interface has 256M space:

	#define CONFIG_SYS_SRIO1_MEM_VIRT   0xa0000000
	#define CONFIG_SYS_SRIO1_MEM_PHYS   0xc20000000ull

	#define CONFIG_SYS_SRIO2_MEM_VIRT   0xb0000000
	#define CONFIG_SYS_SRIO2_MEM_PHYS   0xc30000000ull

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
index 373cb7848cbafcbe5fbc0a247fb8662e2d80e3e2..6d634bf690aab49611b8baa628879706e453eea8 100644 (file)
--- a/board/freescale/b4860qds/tlb.c
+++ b/board/freescale/b4860qds/tlb.c
@@ -111,8 +111,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #ifdef CONFIG_SYS_NAND_BASE
        /*
         * *I*G - NAND
-        * entry 14 and 15 has been used hard coded, they will be disabled
-        * in cpu_init_f, so we use entry 16 for nand.
         */
        SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -122,6 +120,23 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 12, BOOKE_PAGESZ_4K, 1),
 
+       /*
+        * *I*G - SRIO
+        * entry 14 and 15 has been used hard coded, they will be disabled
+        * in cpu_init_f, so we use entry 16 for SRIO2.
+        */
+#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
+       /* *I*G* - SRIO1 */
+       SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
+               MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 13, BOOKE_PAGESZ_256M, 1),
+#endif
+#ifdef CONFIG_SYS_SRIO2_MEM_PHYS
+       /* *I*G* - SRIO2 */
+       SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS,
+               MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 16, BOOKE_PAGESZ_256M, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);