]> git.kernelconcepts.de Git - karo-tx-uboot.git/commitdiff
microblaze: Flush caches before enabling them
authorMichal Simek <monstr@monstr.eu>
Tue, 25 Sep 2012 08:13:35 +0000 (10:13 +0200)
committerMichal Simek <monstr@monstr.eu>
Wed, 7 Nov 2012 16:11:14 +0000 (17:11 +0100)
Flushing caches is necessary because of soft reset
which doesn't clear caches.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Reviewed-by: Marek Vasut <marex@denx.de>
arch/microblaze/cpu/cache.c
arch/microblaze/cpu/start.S
arch/microblaze/lib/bootm.c
include/configs/microblaze-generic.h

index d258a6938228e499c508845d3a985e0ed6e2f99e..ce066b96e99321fe62567cdf59ecde53e09937a5 100644 (file)
@@ -61,12 +61,7 @@ void dcache_enable (void) {
 
 void   dcache_disable(void) {
 #ifdef XILINX_USE_DCACHE
-#ifdef XILINX_DCACHE_BYTE_SIZE
        flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
-#else
-#warning please rebuild BSPs and update configuration
-       flush_cache(0, 32768);
-#endif
 #endif
        MSRCLR(0x80);
 }
index 8564c4e30ab5e70c6d1008c1cfcd3c8f14dfca9a..3da711d4d500449866d2464e96f0edf9d1baf45f 100644 (file)
@@ -132,6 +132,12 @@ _start:
        rsubi   r8, r10, 0x26
        sh      r6, r0, r8
 
+       /* Flush cache before enable cache */
+       addik   r5, r0, 0
+       addik   r6, r0, XILINX_DCACHE_BYTE_SIZE
+flush: bralid r15, flush_cache
+       nop
+
        /* enable instruction and data cache */
        mfs     r12, rmsr
        ori     r12, r12, 0xa0
index 95cee509d257857267b0b2ca8cd211b05f3061ff..66d21f4ef66fe8afb2d9d2a314cbe7b71fbcdb93 100644 (file)
@@ -70,12 +70,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 #endif
 
 #ifdef XILINX_USE_DCACHE
-#ifdef XILINX_DCACHE_BYTE_SIZE
        flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
-#else
-#warning please rebuild BSPs and update configuration
-       flush_cache(0, 32768);
-#endif
 #endif
        /*
         * Linux Kernel Parameters (passing device tree):
index 721cd906adb151ae5214c1bd4f9a7082b38aa5cb..eed38c165f0cf9bb259be4970906f76800969b10 100644 (file)
 # undef CONFIG_DCACHE
 #endif
 
+#ifndef XILINX_DCACHE_BYTE_SIZE
+#define XILINX_DCACHE_BYTE_SIZE        32768
+#endif
+
 /*
  * BOOTP options
  */