]> git.kernelconcepts.de Git - karo-tx-uboot.git/commitdiff
mpc512x: make MEM IO Control configuration a board config option
authorAnatolij Gustschin <agust@denx.de>
Sat, 24 Apr 2010 17:27:07 +0000 (19:27 +0200)
committerWolfgang Denk <wd@denx.de>
Sat, 24 Apr 2010 20:56:34 +0000 (22:56 +0200)
Signed-off-by: Anatolij Gustschin <agust@denx.de>
arch/powerpc/cpu/mpc512x/fixed_sdram.c
arch/powerpc/include/asm/immap_512x.h
include/configs/aria.h
include/configs/mecp5123.h
include/configs/mpc5121ads.h

index 442b5fc918009ddd9e310dfe5ced34bbec31ec9b..72d524caadcfed620f96e8c34ee15278fbc8f710 100644 (file)
@@ -91,7 +91,7 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config,
        }
 
        /* Initialize IO Control */
-       out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
+       out_be32(&im->io_ctrl.io_control_mem, CONFIG_SYS_IOCTRL_MUX_DDR);
 
        /* Initialize DDR Local Window */
        out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
index 8bce586b53815a3b52cba71e9d8d5dbb8feab2f2..c430cb640b29aff74c8e8ef992fb1fac3bb37363 100644 (file)
@@ -848,10 +848,6 @@ typedef struct ioctrl512x {
        u8      reserved[0x0cfc];               /* fill to 4096 bytes size */
 } ioctrl512x_t;
 
-/* Indexes in regs array */
-/* Set for DDR */
-#define IOCTRL_MUX_DDR         0x00000036
-
 /* IO pin fields */
 #define IO_PIN_FMUX(v) ((v) << 7)      /* pin function */
 #define IO_PIN_HOLD(v) ((v) << 5)      /* hold time, pci only */
index b6669e72a6a2c5349ff061c7b3d5d1034145fe92..7097ab72d012d04c86020d5e6debc23f6bc7f3c3 100644 (file)
@@ -79,6 +79,8 @@
 #define CONFIG_SYS_DDR_BASE            0x00000000
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
 
+#define CONFIG_SYS_IOCTRL_MUX_DDR      0x00000036
+
 /* DDR Controller Configuration
  *
  * SYS_CFG:
index cccc31d5edc983fd0430eb4c8727c43cc5d1ee7d..cafd6a7f66d81bc2cedf36a2f9b04e8dd7305dce 100644 (file)
@@ -67,6 +67,8 @@
 #define CONFIG_SYS_DDR_BASE            0x00000000      /* DDR is sys memory*/
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
 
+#define CONFIG_SYS_IOCTRL_MUX_DDR      0x00000036
+
 /* DDR Controller Configuration
  *
  * SYS_CFG:
index fb49388bd0f6b76f5f635d0df6099791f8cc6abc..8ecc9e114110bc3c23140cb47ca66a9268efd783 100644 (file)
@@ -86,6 +86,8 @@
 #define CONFIG_SYS_DDR_BASE            0x00000000      /* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
 
+#define CONFIG_SYS_IOCTRL_MUX_DDR      0x00000036
+
 /* DDR Controller Configuration
  *
  * SYS_CFG: