i.MX6: nitrogen6x: Don't bother setting PLL3(480) PFD1 divisor

This clock isn't feeding anything under U-Boot, so there's no
point in changing it from power-on default.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 1419f36b8e090c8044d5a21d813c045bad117c08..f664f6de6b398b03848fffa3344a4c6f6564eed5 100644 (file)
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -622,7 +622,6 @@ int board_video_skip(void)
 static void setup_display(void)
 {
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 static void setup_display(void)
 {
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

-       struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;

        struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
        int reg;
 
        struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
        int reg;
 


@@ -633,10 +632,6 @@ static void setup_display(void)
        reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
        writel(reg, &mxc_ccm->CCGR3);
 
        reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
        writel(reg, &mxc_ccm->CCGR3);
 

-       /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
-       writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
-       writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
-

        /* set LDB0, LDB1 clk select to 011/011 */
        reg = readl(&mxc_ccm->cs2cdr);
        reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
        /* set LDB0, LDB1 clk select to 011/011 */
        reg = readl(&mxc_ccm->cs2cdr);
        reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK