karo: tx6: increase WALAT/RALAT to max. during DDR calibration

This is mandated in the i.MX 6 Series DDR Calibration App Note (4467)
from Freescale.

diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S
index 8c3f8f2ddd16e1cc56f47553aa227f90e807203a..6953b7b45fd624b9fb00662a7a72987f77ccfd18 100644 (file)
--- a/board/karo/tx6/lowlevel_init.S
+++ b/board/karo/tx6/lowlevel_init.S
@@ -317,11 +317,14 @@ CK_MAX    tCKSRE, NS_TO_CK(10), 5, 0, 7
                                ((PHYS_SDRAM_1_WIDTH / 32) << 16) |     \
                                ((-1) << (32 - BANK_ADDR_BITS)))
 
                                ((PHYS_SDRAM_1_WIDTH / 32) << 16) |     \
                                ((-1) << (32 - BANK_ADDR_BITS)))
 

+#define MDMISC_WALAT(n)                (((n) & 3) << 16)
+#define MDMISC_RALAT(n)                (((n) & 7) << 6)
+

 #define MDMISC_VAL             ((ADDR_MIRROR << 19) |  \
 #define MDMISC_VAL             ((ADDR_MIRROR << 19) |  \

-                               (WALAT << 16) |         \
+                               MDMISC_WALAT(WALAT) |   \

                                (BI_ON << 12) |         \
                                (0x3 << 9) |            \
                                (BI_ON << 12) |         \
                                (0x3 << 9) |            \

-                               (RALAT << 6) |          \
+                               MDMISC_RALAT(RALAT) |   \

                                (DDR_TYPE << 3))
 
 #define MDOR_VAL               ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
                                (DDR_TYPE << 3))
 
 #define MDOR_VAL               ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))


@@ -907,6 +910,10 @@ dcd_hdr:
 #define WL_DLY_DQS6    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS7    (WL_DLY_DQS_VAL + 0)
        /* Write leveling */
 #define WL_DLY_DQS6    (WL_DLY_DQS_VAL + 0)
 #define WL_DLY_DQS7    (WL_DLY_DQS_VAL + 0)
        /* Write leveling */

+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
+       MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_RALAT(~0) | MDMISC_WALAT(~0)) /* increase WALAT/RALAT to max. */
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+

        MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
        MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
        MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
        MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
        MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
        MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))


@@ -953,6 +960,7 @@ dcd_hdr:
        MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x014f0150)
        MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x0144014a)
 #endif /* DO_DDR_CALIB */
        MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x014f0150)
        MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x0144014a)
 #endif /* DO_DDR_CALIB */

+       MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)

        /* DRAM_SDQS[0..7] pad config */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
        /* DRAM_SDQS[0..7] pad config */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)