/onenand_ipl/onenand-ipl*
/onenand_ipl/board/*/onenand*
/onenand_ipl/board/*/*.S
+
+# spl ais files
+/spl/*.ais
KUP4K MPC855
KUP4X MPC859
-Ilko Iliev <iliev@ronetix.at>
-
- PM9261 AT91SAM9261
- PM9263 AT91SAM9263
- PM9G45 ARM926EJS (AT91SAM9G45 SoC)
-
Gary Jennejohn <garyj@denx.de>
quad100hd PPC405EP
Andreas Bießmann <andreas.devel@gmail.com>
at91rm9200ek at91rm9200
- grasshopper avr32
Cliff Brake <cliff.brake@gmail.com>
meesc ARM926EJS (AT91SAM9263 SoC)
otc570 ARM926EJS (AT91SAM9263 SoC)
-Sedji Gaouaou<sedji.gaouaou@atmel.com>
+Bo Shen<voice.shen@atmel.com>
at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC)
at91sam9m10g45ek ARM926EJS (AT91SAM9G45 SoC)
am3517_evm ARM ARMV7 (AM35x SoC)
+Markus Hubig <mhubig@imko.de>
+
+ STAMP9G20 ARM926EJS
+
Grazvydas Ignotas <notasas@gmail.com>
omap3_pandora ARM ARMV7 (OMAP3xx SoC)
+Ilko Iliev <iliev@ronetix.at>
+
+ PM9261 AT91SAM9261
+ PM9263 AT91SAM9263
+ PM9G45 ARM926EJS (AT91SAM9G45 SoC)
+
Michael Jones <michael.jones@matrix-vision.de>
omap3_mvblx ARM ARMV7 (OMAP3xx SoC)
integratorap various
integratorcp various
+Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
+
+ apx4devkit i.MX28
+
Luka Perkov <uboot@lukaperkov.net>
ib62x0 ARM926EJS
omap730p2 ARM926EJS
+Mathieu Poirier <mathieu.poirier@linaro.org>
+
+ snowball ARM ARMV7 (u8500 SoC)
+
Stelian Pop <stelian@popies.net>
at91sam9260ek ARM926EJS (AT91SAM9260 SoC)
Thierry Reding <thierry.reding@avionic-design.de>
- plutux Tegra2 (ARM7 & A9 Dual Core)
- medcom Tegra2 (ARM7 & A9 Dual Core)
- tec Tegra2 (ARM7 & A9 Dual Core)
+ plutux Tegra20 (ARM7 & A9 Dual Core)
+ medcom Tegra20 (ARM7 & A9 Dual Core)
+ tec Tegra20 (ARM7 & A9 Dual Core)
Christian Riesch <christian.riesch@omicron.at>
Manfred Rudigier <manfred.rudigier@omicron.at>
actux4 xscale/ixp
dvlhost xscale/ixp
+Matt Sealey <matt@genesi-usa.com>
+
+ efikamx i.MX51
+ efikasb i.MX51
+
+Bo Shen <voice.shen@atmel.com>
+ at91sam9x5ek ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
+
Nick Thompson <nick.thompson@gefanuc.com>
da830evm ARM926EJS (DA830/OMAP-L137)
vpac270 xscale/pxa
zipitz2 xscale/pxa
m28evk i.MX28
- efikamx i.MX51
- efikasb i.MX51
+ sc_sps_1 i.MX28
Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
Tom Warren <twarren@nvidia.com>
- harmony Tegra2 (ARM7 & A9 Dual Core)
- seaboard Tegra2 (ARM7 & A9 Dual Core)
+ harmony Tegra20 (ARM7 & A9 Dual Core)
+ seaboard Tegra20 (ARM7 & A9 Dual Core)
Tom Warren <twarren@nvidia.com>
Stephen Warren <swarren@nvidia.com>
- ventana Tegra2 (ARM7 & A9 Dual Core)
- paz00 Tegra2 (ARM7 & A9 Dual Core)
- trimslice Tegra2 (ARM7 & A9 Dual Core)
- whistler Tegra2 (ARM7 & A9 Dual Core)
+ ventana Tegra20 (ARM7 & A9 Dual Core)
+ paz00 Tegra20 (ARM7 & A9 Dual Core)
+ trimslice Tegra20 (ARM7 & A9 Dual Core)
+ whistler Tegra20 (ARM7 & A9 Dual Core)
+
+Stephen Warren <swarren@wwwdotorg.org>
+
+ rpi_b BCM2835 (ARM1176)
Thomas Weber <weber@corscience.de>
# Board CPU #
#########################################################################
+Andreas Bießmann <andreas.devel@googlemail.com>
+ grasshopper AT32AP7000
+
Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
FAVR-32-EZKIT AT32AP7000
-c|--cpu)
# echo "Option CPU: argument \`$2'"
if [ "$opt_c" ] ; then
- opt_c="${opt_c%)} || \$3 == \"$2\")"
+ opt_c="${opt_c%)} || \$3 == \"$2\" || \$3 ~ /$2:/)"
else
- opt_c="(\$3 == \"$2\")"
+ opt_c="(\$3 == \"$2\" || \$3 ~ /$2:/)"
fi
SELECTED='y'
shift 2 ;;
# Helper funcs for parsing boards.cfg
boards_by_field()
{
+ FS="[ \t]+"
+ [ -n "$3" ] && FS="$3"
awk \
-v field="$1" \
-v select="$2" \
+ -F "$FS" \
'($1 !~ /^#/ && $field == select) { print $1 }' \
boards.cfg
}
boards_by_arch() { boards_by_field 2 "$@" ; }
-boards_by_cpu() { boards_by_field 3 "$@" ; }
+boards_by_cpu() { boards_by_field 3 "$@" "[: \t]+" ; }
boards_by_soc() { boards_by_field 6 "$@" ; }
#########################################################################
ifeq ($(SOC),exynos)
LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
endif
+ifeq ($(SOC),tegra20)
+LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
+endif
LIBS := $(addprefix $(obj),$(sort $(LIBS-y)))
.PHONY : $(LIBS)
ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
+# enable combined SPL/u-boot/dtb rules for tegra
+ifeq ($(SOC),tegra20)
+ifeq ($(CONFIG_OF_SEPARATE),y)
+ALL-y += $(obj)u-boot-dtb-tegra.bin
+else
+ALL-y += $(obj)u-boot-nodtb-tegra.bin
+endif
+endif
+
all: $(ALL-y) $(SUBDIR_EXAMPLES)
$(obj)u-boot.dtb: $(obj)u-boot
rm $(obj)spl/u-boot-spl-pad.bin
$(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
- $(obj)tools/mkimage -s -n /dev/null -T aisimage \
+ $(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \
+ -T aisimage \
-e $(CONFIG_SPL_TEXT_BASE) \
-d $(obj)spl/u-boot-spl.bin \
$(obj)spl/u-boot-spl.ais
$(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais
cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.bin > \
$(obj)u-boot.ais
- rm $(obj)spl/u-boot-spl{,-pad}.ais
+
+# Specify the target for use in elftosb call
+ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
- elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
+ elftosb -zdf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
-o $(obj)u-boot.sb
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
conv=notrunc 2>/dev/null
cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@
+ifeq ($(SOC),tegra20)
+ifeq ($(CONFIG_OF_SEPARATE),y)
+$(obj)u-boot-dtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(obj)u-boot.dtb
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(obj)u-boot.dtb > $@
+ rm $(obj)spl/u-boot-spl-pad.bin
+else
+$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
+ rm $(obj)spl/u-boot-spl-pad.bin
+endif
+endif
+
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
@rm -f $(obj)dts/*.tmp
+ @rm -f $(obj)spl/u-boot-spl{,-pad}.ais
mrproper \
distclean: clobber unconfig
- Monitor Functions:
Monitor commands can be included or excluded
from the build by using the #include files
- "config_cmd_all.h" and #undef'ing unwanted
- commands, or using "config_cmd_default.h"
+ <config_cmd_all.h> and #undef'ing unwanted
+ commands, or using <config_cmd_default.h>
and augmenting with additional #define's
for wanted commands.
Disable PCI-Express on systems where it is supported but not
required.
+- CONFIG_PCI_ENUM_ONLY
+ Only scan through and get the devices on the busses.
+ Don't do any setup work, presumably because someone or
+ something has already done it, and we don't need to do it
+ a second time. Useful for platforms that are pre-booted
+ by coreboot or similar.
+
- CONFIG_SYS_SRIO:
Chip has SRIO or not
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
#include <netdev.h>
#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
return freq;
}
-unsigned int mxc_get_main_clock(enum mxc_main_clocks clk)
+unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
{
u32 nfc_pdf, hsp_podf;
u32 pll, ret_val = 0, usb_prdf, usb_podf;
return ret_val;
}
-unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk)
+unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
{
u32 ret_val = 0, pdf, pre_pdf, clk_sel;
struct ccm_regs *ccm =
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
-
int cpu_eth_init(bd_t *bis)
{
int rc = -ENODEV;
return rc;
}
+#ifdef CONFIG_FSL_ESDHC
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+ return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC
#define MUX_INPUT_NUM_MUX \
(((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1)
-#define PIN_TO_IOMUX_INDEX(pin) ((PIN_TO_IOMUX_PAD(pin) - 0x328) >> 2)
-
/*
* Request ownership for an IO pin. This function has to be the first one
* being called before that pin is used.
--- /dev/null
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# version 2 as published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+SOBJS := lowlevel_init.o
+COBJS := reset.o timer.o
+
+SRCS := $(SOBJS:.o=.c) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2012 Stephen Warren
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# version 2 as published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+
+# Don't attempt to override the target CPU/ABI options;
+# the Raspberry Pi toolchain does the right thing by default.
+PLATFORM_RELFLAGS := $(filter-out -msoft-float,$(PLATFORM_RELFLAGS))
+PLATFORM_CPPFLAGS := $(filter-out -march=armv5t,$(PLATFORM_CPPFLAGS))
--- /dev/null
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+ mov pc, lr
--- /dev/null
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/wdog.h>
+
+#define RESET_TIMEOUT 10
+
+void reset_cpu(ulong addr)
+{
+ struct bcm2835_wdog_regs *regs =
+ (struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
+ uint32_t rstc;
+
+ rstc = readl(®s->rstc);
+ rstc &= ~BCM2835_WDOG_RSTC_WRCFG_MASK;
+ rstc |= BCM2835_WDOG_RSTC_WRCFG_FULL_RESET;
+
+ writel(BCM2835_WDOG_PASSWORD | RESET_TIMEOUT, ®s->wdog);
+ writel(BCM2835_WDOG_PASSWORD | rstc, ®s->rstc);
+}
--- /dev/null
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+
+int timer_init(void)
+{
+ return 0;
+}
+
+ulong get_timer(ulong base)
+{
+ struct bcm2835_timer_regs *regs =
+ (struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR;
+
+ return readl(®s->clo) - base;
+}
+
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
+
+void __udelay(unsigned long usec)
+{
+ ulong endtime;
+ signed long diff;
+
+ endtime = get_timer(0) + usec;
+
+ do {
+ ulong now = get_timer(0);
+ diff = endtime - now;
+ } while (diff >= 0);
+}
/* mem barrier to sync things */
asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
}
+
+int arch_cpu_init(void)
+{
+ icache_enable();
+
+ return 0;
+}
/* Nothing more needed */
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No cleanup before linux for IntegratorAP/CM720T as yet */
+#elif defined(CONFIG_TEGRA)
+ /* No cleanup before linux for tegra as yet */
#else
#error No cleanup_before_linux() defined for this CPU type
#endif
PUT32(T0TC, 0);
PUT32(T0TCR, 1); /* enable timer0 */
+#elif defined(CONFIG_TEGRA)
+ /* No timer routines for tegra as yet */
+ lastdec = 0;
#else
#error No timer_init() defined for this CPU type
#endif
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No timer routines for IntegratorAP/CM720T as yet */
+#elif defined(CONFIG_TEGRA)
+ /* No timer routines for tegra as yet */
#else
#error Timer routines not defined for this CPU type
#endif
ldr pc, _irq
ldr pc, _fiq
+#ifdef CONFIG_SPL_BUILD
+_undefined_instruction: .word _undefined_instruction
+_software_interrupt: .word _software_interrupt
+_prefetch_abort: .word _prefetch_abort
+_data_abort: .word _data_abort
+_not_used: .word _not_used
+_irq: .word _irq
+_fiq: .word _fiq
+_pad: .word 0x12345678 /* now 16*4=64 */
+#else
_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
+_pad: .word 0x12345678 /* now 16*4=64 */
+#endif /* CONFIG_SPL_BUILD */
.balignl 16,0xdeadbeef
.globl _TEXT_BASE
_TEXT_BASE:
+#ifdef CONFIG_SPL_BUILD
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
adr r0, _start
cmp r0, r6
+ moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
ldr r0, VPBDIV_ADR
mov r1, #0x01 /* VPB clock is same as process clock */
str r1, [r0]
+#elif defined(CONFIG_TEGRA)
+ /* No cpu_init_crit for tegra as yet */
#else
#error No cpu_init_crit() defined for current CPU type
#endif
str r1, [r0]
#endif
-#ifndef CONFIG_LPC2292
+#if !defined(CONFIG_LPC2292) && !defined(CONFIG_TEGRA)
mov ip, lr
/*
* before relocating, we have to setup RAM timing
mov pc, lr
+#ifndef CONFIG_SPL_BUILD
/*
*************************************************************************
*
bl do_fiq
#endif
+#endif /* CONFIG_SPL_BUILD */
#if defined(CONFIG_NETARM)
.align 5
.globl reset_cpu
reset_cpu:
mov pc, r0
+#elif defined(CONFIG_TEGRA)
+ /* No specific reset actions for tegra as yet */
#else
#error No reset_cpu() defined for current CPU type
#endif
--- /dev/null
+#
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS-y += cpu.o
+COBJS-$(CONFIG_SPL_BUILD) += spl.o
+
+SRCS := $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2010-2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+void board_init_uart_f(void);
+void gpio_config_uart(void);
#
-# (C) Copyright 2009
-# ISEE 2007 SL, <www.iseebcn.com>
+# (C) Copyright 2010,2011
+# NVIDIA Corporation <www.nvidia.com>
#
-# IGEP0030 uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
+USE_PRIVATE_LIBGCC = yes
*/
#include <asm/io.h>
-#include <asm/arch/tegra2.h>
-#include <asm/arch/ap20.h>
+#include <asm/arch/tegra20.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
-#include <asm/arch/fuse.h>
-#include <asm/arch/gp_padctrl.h>
#include <asm/arch/pmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/scu.h>
-#include <asm/arch/warmboot.h>
#include <common.h>
-
-int tegra_get_chip_type(void)
-{
- struct apb_misc_gp_ctlr *gp;
- struct fuse_regs *fuse = (struct fuse_regs *)TEGRA2_FUSE_BASE;
- uint tegra_sku_id, rev;
-
- /*
- * This is undocumented, Chip ID is bits 15:8 of the register
- * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
- * Tegra30
- */
- gp = (struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE;
- rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
-
- tegra_sku_id = readl(&fuse->sku_info) & 0xff;
-
- switch (rev) {
- case CHIPID_TEGRA2:
- switch (tegra_sku_id) {
- case SKU_ID_T20:
- return TEGRA_SOC_T20;
- case SKU_ID_T25SE:
- case SKU_ID_AP25:
- case SKU_ID_T25:
- case SKU_ID_AP25E:
- case SKU_ID_T25E:
- return TEGRA_SOC_T25;
- }
- break;
- }
- /* unknown sku id */
- return TEGRA_SOC_UNKNOWN;
-}
+#include "cpu.h"
/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
-static int ap20_cpu_is_cortexa9(void)
+int ap20_cpu_is_cortexa9(void)
{
u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
return id == (PG_UP_TAG_0_PID_CPU & 0xff);
void init_pllx(void)
{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct clk_pll_simple *pll =
- &clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE];
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
u32 reg;
/* If PLLX is already enabled, just return */
static int is_cpu_powered(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
}
static void remove_cpu_io_clamps(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
u32 reg;
/* Remove the clamps on the CPU I/O signals */
static void powerup_cpu(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
u32 reg;
int timeout = IO_STABILIZATION_DELAY;
static void enable_cpu_power_rail(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
u32 reg;
reg = readl(&pmc->pmc_cntrl);
FLOW_CTLR_HALT_COP_EVENTS);
}
}
-
-void enable_scu(void)
-{
- struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
- u32 reg;
-
- /* If SCU already setup/enabled, return */
- if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
- return;
-
- /* Invalidate all ways for all processors */
- writel(0xFFFF, &scu->scu_inv_all);
-
- /* Enable SCU - bit 0 */
- reg = readl(&scu->scu_ctrl);
- reg |= SCU_CTRL_ENABLE;
- writel(reg, &scu->scu_ctrl);
-}
-
-static u32 get_odmdata(void)
-{
- /*
- * ODMDATA is stored in the BCT in IRAM by the BootROM.
- * The BCT start and size are stored in the BIT in IRAM.
- * Read the data @ bct_start + (bct_size - 12). This works
- * on T20 and T30 BCTs, which are locked down. If this changes
- * in new chips (T114, etc.), we can revisit this algorithm.
- */
-
- u32 bct_start, odmdata;
-
- bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
- odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
-
- return odmdata;
-}
-
-void init_pmc_scratch(void)
-{
- struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
- u32 odmdata;
- int i;
-
- /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
- for (i = 0; i < 23; i++)
- writel(0, &pmc->pmc_scratch1+i);
-
- /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
- odmdata = get_odmdata();
- writel(odmdata, &pmc->pmc_scratch20);
-
-#ifdef CONFIG_TEGRA2_LP0
- /* save Sdram params to PMC 2, 4, and 24 for WB0 */
- warmboot_save_sdram_params();
-#endif
-}
-
-void tegra2_start(void)
-{
- struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-
- /* If we are the AVP, start up the first Cortex-A9 */
- if (!ap20_cpu_is_cortexa9()) {
- /* enable JTAG */
- writel(0xC0, &pmt->pmt_cfg_ctl);
-
- /*
- * If we are ARM7 - give it a different stack. We are about to
- * start up the A9 which will want to use this one.
- */
- asm volatile("mov sp, %0\n"
- : : "r"(AVP_EARLY_BOOT_STACK_LIMIT));
-
- start_cpu((u32)_start);
- halt_avp();
- /* not reached */
- }
-
- /* Init PMC scratch memory */
- init_pmc_scratch();
-
- enable_scu();
-
- /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
- asm volatile(
- "mrc p15, 0, r0, c1, c0, 1\n"
- "orr r0, r0, #0x41\n"
- "mcr p15, 0, r0, c1, c0, 1\n");
-
- /* FIXME: should have ap20's L2 disabled too? */
-}
--- /dev/null
+/*
+ * (C) Copyright 2010-2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <asm/types.h>
+
+/* Stabilization delays, in usec */
+#define PLL_STABILIZATION_DELAY (300)
+#define IO_STABILIZATION_DELAY (1000)
+
+#define NVBL_PLLP_KHZ (216000)
+
+#define PLLX_ENABLED (1 << 30)
+#define CCLK_BURST_POLICY 0x20008888
+#define SUPER_CCLK_DIVIDER 0x80000000
+
+/* Calculate clock fractional divider value from ref and target frequencies */
+#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
+
+/* Calculate clock frequency value from reference and clock divider value */
+#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
+
+/* AVP/CPU ID */
+#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
+#define PG_UP_TAG_0 0x0
+
+#define CORESIGHT_UNLOCK 0xC5ACCE55;
+
+/* AP20-Specific Base Addresses */
+
+/* AP20 Base physical address of SDRAM. */
+#define AP20_BASE_PA_SDRAM 0x00000000
+/* AP20 Base physical address of internal SRAM. */
+#define AP20_BASE_PA_SRAM 0x40000000
+/* AP20 Size of internal SRAM (256KB). */
+#define AP20_BASE_PA_SRAM_SIZE 0x00040000
+/* AP20 Base physical address of flash. */
+#define AP20_BASE_PA_NOR_FLASH 0xD0000000
+/* AP20 Base physical address of boot information table. */
+#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM
+
+/*
+ * Super-temporary stacks for EXTREMELY early startup. The values chosen for
+ * these addresses must be valid on ALL SOCs because this value is used before
+ * we are able to differentiate between the SOC types.
+ *
+ * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
+ * stack is placed below the AVP stack. Once the CPU stack has been moved,
+ * the AVP is free to use the IRAM the CPU stack previously occupied if
+ * it should need to do so.
+ *
+ * NOTE: In multi-processor CPU complex configurations, each processor will have
+ * its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
+ * limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
+ * stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
+ * CPU.
+ */
+
+/* Common AVP early boot stack limit */
+#define AVP_EARLY_BOOT_STACK_LIMIT \
+ (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
+/* Common AVP early boot stack size */
+#define AVP_EARLY_BOOT_STACK_SIZE 0x1000
+/* Common CPU early boot stack limit */
+#define CPU_EARLY_BOOT_STACK_LIMIT \
+ (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
+/* Common CPU early boot stack size */
+#define CPU_EARLY_BOOT_STACK_SIZE 0x1000
+
+#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
+#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
+#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
+#define FLOW_MODE_STOP 2
+#define HALT_COP_EVENT_JTAG (1 << 28)
+#define HALT_COP_EVENT_IRQ_1 (1 << 11)
+#define HALT_COP_EVENT_FIQ_1 (1 << 9)
+
+void start_cpu(u32 reset_vector);
+int ap20_cpu_is_cortexa9(void);
+void halt_avp(void) __attribute__ ((noreturn));
--- /dev/null
+/*
+ * (C) Copyright 2012
+ * NVIDIA Inc, <www.nvidia.com>
+ *
+ * Allen Martin <amartin@nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <nand.h>
+#include <mmc.h>
+#include <fat.h>
+#include <version.h>
+#include <i2c.h>
+#include <image.h>
+#include <malloc.h>
+#include <linux/compiler.h>
+#include "board.h"
+#include "cpu.h"
+
+#include <asm/io.h>
+#include <asm/arch/tegra20.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/scu.h>
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Define global data structure pointer to it*/
+static gd_t gdata __attribute__ ((section(".data")));
+static bd_t bdata __attribute__ ((section(".data")));
+
+inline void hang(void)
+{
+ puts("### ERROR ### Please RESET the board ###\n");
+ for (;;)
+ ;
+}
+
+void board_init_f(ulong dummy)
+{
+ board_init_uart_f();
+
+ /* Initialize periph GPIOs */
+#ifdef CONFIG_SPI_UART_SWITCH
+ gpio_early_init_uart();
+#else
+ gpio_config_uart();
+#endif
+
+ /*
+ * We call relocate_code() with relocation target same as the
+ * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting
+ * skipped. Instead, only .bss initialization will happen. That's
+ * all we need
+ */
+ debug(">>board_init_f()\n");
+ relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
+}
+
+/* This requires UART clocks to be enabled */
+static void preloader_console_init(void)
+{
+ const char *u_boot_rev = U_BOOT_VERSION;
+
+ gd = &gdata;
+ gd->bd = &bdata;
+ gd->flags |= GD_FLG_RELOC;
+ gd->baudrate = CONFIG_BAUDRATE;
+
+ serial_init(); /* serial communications setup */
+
+ gd->have_console = 1;
+
+ /* Avoid a second "U-Boot" coming from this string */
+ u_boot_rev = &u_boot_rev[7];
+
+ printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE,
+ U_BOOT_TIME);
+}
+
+void board_init_r(gd_t *id, ulong dummy)
+{
+ struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+
+ /* enable JTAG */
+ writel(0xC0, &pmt->pmt_cfg_ctl);
+
+ debug(">>spl:board_init_r()\n");
+
+ mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
+ CONFIG_SYS_SPL_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_BOARD_INIT
+ spl_board_init();
+#endif
+
+ clock_early_init();
+ serial_init();
+ preloader_console_init();
+
+ start_cpu((u32)CONFIG_SYS_TEXT_BASE);
+ halt_avp();
+ /* not reached */
+}
+
+int board_usb_init(const void *blob)
+{
+ return 0;
+}
COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o
COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
COBJS-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o
+COBJS-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
COBJS-$(CONFIG_AT91_EFLASH) += eflash.o
COBJS-$(CONFIG_AT91_LED) += led.o
COBJS-y += clock.o
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
+ /* Enable EMAC clock */
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+
at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* ETXCK_EREFCK */
at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ERXDV */
at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ERX0 */
--- /dev/null
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+
+unsigned int get_chip_id(void)
+{
+ /* The 0x40 is the offset of cidr in DBGU */
+ return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK;
+}
+
+unsigned int get_extension_chip_id(void)
+{
+ /* The 0x44 is the offset of exid in DBGU */
+ return readl(ATMEL_BASE_DBGU + 0x44);
+}
+
+unsigned int has_emac1()
+{
+ return cpu_is_at91sam9x25();
+}
+
+unsigned int has_emac0()
+{
+ return !(cpu_is_at91sam9g15());
+}
+
+unsigned int has_lcdc()
+{
+ return cpu_is_at91sam9g15() || cpu_is_at91sam9g35()
+ || cpu_is_at91sam9x35();
+}
+
+char *get_cpu_name()
+{
+ unsigned int extension_id = get_extension_chip_id();
+
+ if (cpu_is_at91sam9x5()) {
+ switch (extension_id) {
+ case ARCH_EXID_AT91SAM9G15:
+ return CONFIG_SYS_AT91_G15_CPU_NAME;
+ case ARCH_EXID_AT91SAM9G25:
+ return CONFIG_SYS_AT91_G25_CPU_NAME;
+ case ARCH_EXID_AT91SAM9G35:
+ return CONFIG_SYS_AT91_G35_CPU_NAME;
+ case ARCH_EXID_AT91SAM9X25:
+ return CONFIG_SYS_AT91_X25_CPU_NAME;
+ case ARCH_EXID_AT91SAM9X35:
+ return CONFIG_SYS_AT91_X35_CPU_NAME;
+ default:
+ return CONFIG_SYS_AT91_UNKNOWN_CPU;
+ }
+ } else {
+ return CONFIG_SYS_AT91_UNKNOWN_CPU;
+ }
+}
+
+void at91_seriald_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
+ at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
+
+ writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+}
+
+void at91_serial0_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */
+ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */
+
+ writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+}
+
+void at91_serial1_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */
+ at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */
+
+ writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+}
+
+void at91_serial2_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */
+ at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */
+
+ writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+}
+
+#ifdef CONFIG_ATMEL_SPI
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
+ at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
+
+ if (cs_mask & (1 << 0))
+ at91_set_a_periph(AT91_PIO_PORTA, 14, 0);
+ if (cs_mask & (1 << 1))
+ at91_set_b_periph(AT91_PIO_PORTA, 7, 0);
+ if (cs_mask & (1 << 2))
+ at91_set_b_periph(AT91_PIO_PORTA, 1, 0);
+ if (cs_mask & (1 << 3))
+ at91_set_b_periph(AT91_PIO_PORTB, 3, 0);
+ if (cs_mask & (1 << 4))
+ at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
+ if (cs_mask & (1 << 5))
+ at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
+ if (cs_mask & (1 << 6))
+ at91_set_pio_output(AT91_PIO_PORTA, 1, 0);
+ if (cs_mask & (1 << 7))
+ at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
+ at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
+ at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
+
+ if (cs_mask & (1 << 0))
+ at91_set_b_periph(AT91_PIO_PORTA, 8, 0);
+ if (cs_mask & (1 << 1))
+ at91_set_b_periph(AT91_PIO_PORTA, 0, 0);
+ if (cs_mask & (1 << 2))
+ at91_set_b_periph(AT91_PIO_PORTA, 31, 0);
+ if (cs_mask & (1 << 3))
+ at91_set_b_periph(AT91_PIO_PORTA, 30, 0);
+ if (cs_mask & (1 << 4))
+ at91_set_pio_output(AT91_PIO_PORTA, 8, 0);
+ if (cs_mask & (1 << 5))
+ at91_set_pio_output(AT91_PIO_PORTA, 0, 0);
+ if (cs_mask & (1 << 6))
+ at91_set_pio_output(AT91_PIO_PORTA, 31, 0);
+ if (cs_mask & (1 << 7))
+ at91_set_pio_output(AT91_PIO_PORTA, 30, 0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ if (has_emac0()) {
+ /* Enable EMAC0 clock */
+ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+ /* EMAC0 pins setup */
+ at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */
+ at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */
+ at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */
+ at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */
+ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */
+ at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */
+ at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */
+ at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */
+ at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */
+ at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */
+ }
+
+ if (has_emac1()) {
+ /* Enable EMAC1 clock */
+ writel(1 << ATMEL_ID_EMAC1, &pmc->pcer);
+ /* EMAC1 pins setup */
+ at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */
+ at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */
+ at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */
+ at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */
+ at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */
+ at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */
+ at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */
+ at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */
+ at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */
+ at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */
+ }
+
+#ifndef CONFIG_RMII
+ /* Only emac0 support MII */
+ if (has_emac0()) {
+ at91_set_b_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
+ at91_set_b_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
+ at91_set_b_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
+ at91_set_b_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
+ at91_set_b_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
+ at91_set_b_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
+ at91_set_b_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
+ at91_set_b_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
+ }
+#endif
+}
+#endif
* For now, assume this parentage won't change.
*/
mckr = readl(&pmc->mckr);
-#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
+ || defined(CONFIG_AT91SAM9X5)
/* plla divisor by 2 */
gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
#endif
freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
if (mckr & AT91_PMC_MCKR_MDIV_MASK)
freq /= 2; /* processor clock division */
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
+ || defined(CONFIG_AT91SAM9X5)
+ /* mdiv <==> divisor
+ * 0 <==> 1
+ * 1 <==> 2
+ * 2 <==> 4
+ * 3 <==> 3
+ */
gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
? freq / 3
LIB = $(obj)lib$(SOC).o
-COBJS-y += cpu.o misc.o timer.o psc.o pinmux.o
+COBJS-y += cpu.o misc.o timer.o psc.o pinmux.o reset.o
COBJS-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o
COBJS-$(CONFIG_SOC_DM355) += dm355.o
COBJS-$(CONFIG_SOC_DM365) += dm365.o
COBJS-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o
endif
-SOBJS = reset.o
-
ifndef CONFIG_SKIP_LOWLEVEL_INIT
SOBJS += lowlevel_init.o
endif
out:
return pll_out;
}
+
+int set_cpu_clk_info(void)
+{
+ gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
+ /* DDR PHY uses an x2 input clock */
+ gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
+ (clk_get(DAVINCI_DDR_CLKID) / 1000000);
+ gd->bd->bi_dsp_freq = 0;
+ return 0;
+}
+
#else /* CONFIG_SOC_DA8XX */
static unsigned pll_div(volatile void *pllbase, unsigned offset)
return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
}
#endif
-#endif /* !CONFIG_SOC_DA8XX */
int set_cpu_clk_info(void)
{
-#ifdef CONFIG_SOC_DA8XX
- gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
- /* DDR PHY uses an x2 input clock */
- gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000;
-#else
-
unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
#if defined(CONFIG_SOC_DM365)
pllbase = DAVINCI_PLL_CNTRL1_BASE;
pllbase = DAVINCI_PLL_CNTRL0_BASE;
#endif
gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
-#endif
+
return 0;
}
+#endif /* !CONFIG_SOC_DA8XX */
+
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
-
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
}
-
+ setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
- clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
- (1 << DDR_SLEW_CMOSEN_BIT));
+
+ if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
+ /* DDR2 */
+ clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
+ (1 << DDR_SLEW_DDR_PDENA_BIT) |
+ (1 << DDR_SLEW_CMOSEN_BIT));
+ } else {
+ /* MOBILE DDR */
+ setbits_le32(&davinci_syscfg1_regs->ddr_slew,
+ (1 << DDR_SLEW_DDR_PDENA_BIT) |
+ (1 << DDR_SLEW_CMOSEN_BIT));
+ }
/*
* SDRAM Configuration Register (SDCR):
writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
/* write memory configuration and timing */
- writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
+ if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
+ /* MOBILE DDR only*/
+ writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
+ &dv_ddr2_regs_ctrl->sdbcr2);
+ }
writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
/* disable self refresh */
clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
- DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
+ DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
return 0;
};
/* UART pin muxer settings */
+const struct pinmux_config uart0_pins_txrx[] = {
+ { pinmux(3), 2, 4 }, /* UART0_RXD */
+ { pinmux(3), 2, 5 }, /* UART0_TXD */
+};
+
const struct pinmux_config uart1_pins_txrx[] = {
{ pinmux(4), 2, 6 }, /* UART1_RXD */
{ pinmux(4), 2, 7 }, /* UART1_TXD */
{ pinmux(12), 1, 6 }, /* EMA_A[1] */
{ pinmux(12), 1, 7 }, /* EMA_A[0] */
};
+
+/* MMC0 pin muxer settings */
+const struct pinmux_config mmc0_pins[] = {
+ { pinmux(10), 2, 0 }, /* MMCSD0_CLK */
+ { pinmux(10), 2, 1 }, /* MMCSD0_CMD */
+ { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
+ { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
+ { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
+ { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */
+ /* DA850 supports only 4-bit mode, remaining pins are not configured */
+};
lpsc_transition(id, 0x01);
}
+void lpsc_disable(unsigned int id)
+{
+ lpsc_transition(id, 0x0);
+}
+
/* Not all DaVinci chips have a DSP power domain. */
#ifdef CONFIG_SOC_DM644X
+++ /dev/null
-/*
- * Processor reset using WDT for TI TMS320DM644x SoC.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * -----------------------------------------------------
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-.globl reset_cpu
-reset_cpu:
- ldr r0, WDT_TGCR
- mov r1, $0x08
- str r1, [r0]
- ldr r1, [r0]
- orr r1, r1, $0x03
- str r1, [r0]
- mov r1, $0
- ldr r0, WDT_TIM12
- str r1, [r0]
- ldr r0, WDT_TIM34
- str r1, [r0]
- ldr r0, WDT_PRD12
- str r1, [r0]
- ldr r0, WDT_PRD34
- str r1, [r0]
- ldr r0, WDT_TCR
- ldr r1, [r0]
- orr r1, r1, $0x40
- str r1, [r0]
- ldr r0, WDT_WDTCR
- ldr r1, [r0]
- orr r1, r1, $0x4000
- str r1, [r0]
- ldr r1, WDTCR_VAL1
- str r1, [r0]
- ldr r1, WDTCR_VAL2
- str r1, [r0]
- /* Write an invalid value to the WDKEY field to trigger
- * an immediate watchdog reset */
- mov r1, $0x4000
- str r1, [r0]
- nop
- nop
- nop
- nop
-reset_cpu_loop:
- b reset_cpu_loop
-
-WDT_TGCR:
- .word 0x01c21c24
-WDT_TIM12:
- .word 0x01c21c10
-WDT_TIM34:
- .word 0x01c21c14
-WDT_PRD12:
- .word 0x01c21c18
-WDT_PRD34:
- .word 0x01c21c1c
-WDT_TCR:
- .word 0x01c21c20
-WDT_WDTCR:
- .word 0x01c21c28
-WDTCR_VAL1:
- .word 0xa5c64000
-WDTCR_VAL2:
- .word 0xda7e4000
--- /dev/null
+/*
+ * Processor reset using WDT.
+ *
+ * Copyright (C) 2012 Dmitry Bondar <bond@inmys.ru>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+*/
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer_defs.h>
+#include <asm/arch/hardware.h>
+
+void reset_cpu(unsigned long a)
+{
+ struct davinci_timer *const wdttimer =
+ (struct davinci_timer *)DAVINCI_TIMER1_BASE;
+ writel(0x08, &wdttimer->tgcr);
+ writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr);
+ writel(0, &wdttimer->tim12);
+ writel(0, &wdttimer->tim34);
+ writel(0, &wdttimer->prd12);
+ writel(0, &wdttimer->prd34);
+ writel(readl(&wdttimer->tcr) | 0x40, &wdttimer->tcr);
+ writel(readl(&wdttimer->wdtcr) | 0x4000, &wdttimer->wdtcr);
+ writel(0xa5c64000, &wdttimer->wdtcr);
+ writel(0xda7e4000, &wdttimer->wdtcr);
+ writel(0x4000, &wdttimer->wdtcr);
+ while (1)
+ /*nothing*/;
+}
#include <ns16550.h>
#include <malloc.h>
#include <spi_flash.h>
+#include <mmc.h>
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
void board_init_r(gd_t *id, ulong dummy)
{
-#ifdef CONFIG_SPL_NAND_LOAD
- nand_init();
- puts("Nand boot...\n");
- nand_boot();
-#endif
-#ifdef CONFIG_SPL_SPI_LOAD
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
CONFIG_SYS_MALLOC_LEN);
serial_init(); /* serial communications setup */
gd->have_console = 1;
+#endif
+
+#ifdef CONFIG_SPL_NAND_LOAD
+ nand_init();
+ puts("Nand boot...\n");
+ nand_boot();
+#endif
+#ifdef CONFIG_SPL_SPI_LOAD
puts("SPI boot...\n");
spi_boot();
#endif
+#ifdef CONFIG_SPL_MMC_LOAD
+ puts("MMC boot...\n");
+ spl_mmc_load();
+#endif
}
}
#endif
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+#endif
+}
+
int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_FEC_MXC)
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
#ifdef CONFIG_MXC_MMC
#include <asm/arch/mxcmmc.h>
#endif
void imx_gpio_mode(int gpio_mode)
{
- struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
+ struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
unsigned int pin = gpio_mode & GPIO_PIN_MASK;
unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
/* Data direction */
if (gpio_mode & GPIO_OUT) {
- writel(readl(®s->port[port].ddir) | 1 << pin,
- ®s->port[port].ddir);
+ writel(readl(®s->port[port].gpio_dir) | 1 << pin,
+ ®s->port[port].gpio_dir);
} else {
- writel(readl(®s->port[port].ddir) & ~(1 << pin),
- ®s->port[port].ddir);
+ writel(readl(®s->port[port].gpio_dir) & ~(1 << pin),
+ ®s->port[port].gpio_dir);
}
/* Primary / alternate function */
LIB = $(obj)lib$(SOC).o
-COBJS = clock.o mx28.o iomux.o timer.o
+COBJS = clock.o mxs.o iomux.o timer.o
ifdef CONFIG_SPL_BUILD
COBJS += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
static uint32_t mx28_get_pclk(void)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
static uint32_t mx28_get_hclk(void)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t div;
uint32_t clkctrl;
static uint32_t mx28_get_emiclk(void)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
static uint32_t mx28_get_gpmiclk(void)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
*/
void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t div;
int io_reg;
*/
static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint8_t ret;
int io_reg;
*/
void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clk, clkreg;
if (ssp > MXC_SSPCLK3)
return;
clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
- (ssp * sizeof(struct mx28_register_32));
+ (ssp * sizeof(struct mxs_register_32));
clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
*/
static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clkreg;
uint32_t clk, tmp;
return XTAL_FREQ_KHZ;
clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
- (ssp * sizeof(struct mx28_register_32));
+ (ssp * sizeof(struct mxs_register_32));
tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
*/
void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
{
- struct mx28_ssp_regs *ssp_regs;
+ struct mxs_ssp_regs *ssp_regs;
const uint32_t sspclk = mx28_get_sspclk(bus);
uint32_t reg;
uint32_t divide, rate, tgtclk;
- ssp_regs = (struct mx28_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
+ ssp_regs = (struct mxs_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
/*
* SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
{
u32 reg, ofs, bp, bm;
void *iomux_base = (void *)MXS_PINCTRL_BASE;
- struct mx28_register_32 *mxs_reg;
+ struct mxs_register_32 *mxs_reg;
/* muxsel */
ofs = 0x100;
/* vol */
if (PAD_VOL_VALID(pad)) {
bp = PAD_PIN(pad) % 8 * 4 + 2;
- mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
+ mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
if (PAD_VOL(pad))
writel(1 << bp, &mxs_reg->reg_set);
else
ofs = PULL_OFFSET;
ofs += PAD_BANK(pad) * 0x10;
bp = PAD_PIN(pad);
- mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
+ mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
if (PAD_PULL(pad))
writel(1 << bp, &mxs_reg->reg_set);
else
/* 1 second delay should be plenty of time for block reset. */
#define RESET_MAX_TIMEOUT 1000000
-#define MX28_BLOCK_SFTRST (1 << 31)
-#define MX28_BLOCK_CLKGATE (1 << 30)
+#define MXS_BLOCK_SFTRST (1 << 31)
+#define MXS_BLOCK_CLKGATE (1 << 30)
/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
inline void lowlevel_init(void) {}
void reset_cpu(ulong ignored)
{
- struct mx28_rtc_regs *rtc_regs =
- (struct mx28_rtc_regs *)MXS_RTC_BASE;
- struct mx28_lcdif_regs *lcdif_regs =
- (struct mx28_lcdif_regs *)MXS_LCDIF_BASE;
+ struct mxs_rtc_regs *rtc_regs =
+ (struct mxs_rtc_regs *)MXS_RTC_BASE;
+ struct mxs_lcdif_regs *lcdif_regs =
+ (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
/*
* Shut down the LCD controller as it interferes with BootROM boot mode
#endif
}
-int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
+int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
+ int timeout)
{
while (--timeout) {
if ((readl(®->reg) & mask) == mask)
return !timeout;
}
-int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout)
+int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
+ int timeout)
{
while (--timeout) {
if ((readl(®->reg) & mask) == 0)
return !timeout;
}
-int mx28_reset_block(struct mx28_register_32 *reg)
+int mxs_reset_block(struct mxs_register_32 *reg)
{
/* Clear SFTRST */
- writel(MX28_BLOCK_SFTRST, ®->reg_clr);
+ writel(MXS_BLOCK_SFTRST, ®->reg_clr);
- if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
return 1;
/* Clear CLKGATE */
- writel(MX28_BLOCK_CLKGATE, ®->reg_clr);
+ writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
/* Set SFTRST */
- writel(MX28_BLOCK_SFTRST, ®->reg_set);
+ writel(MXS_BLOCK_SFTRST, ®->reg_set);
/* Wait for CLKGATE being set */
- if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+ if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
return 1;
/* Clear SFTRST */
- writel(MX28_BLOCK_SFTRST, ®->reg_clr);
+ writel(MXS_BLOCK_SFTRST, ®->reg_clr);
- if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
return 1;
/* Clear CLKGATE */
- writel(MX28_BLOCK_CLKGATE, ®->reg_clr);
+ writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
- if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
return 1;
return 0;
int arch_cpu_init(void)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
extern uint32_t _start;
mx28_fixup_vt((uint32_t)&_start);
}
#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
+static const char *get_cpu_type(void)
{
- struct mx28_spl_data *data = (struct mx28_spl_data *)
- ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
+ struct mxs_digctl_regs *digctl_regs =
+ (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
+
+ switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
+ case HW_DIGCTL_CHIPID_MX28:
+ return "28";
+ default:
+ return "??";
+ }
+}
- printf("Freescale i.MX28 family at %d MHz\n",
- mxc_get_clock(MXC_ARM_CLK) / 1000000);
- printf("BOOT: %s\n", mx28_boot_modes[data->boot_mode_idx].mode);
+static const char *get_cpu_rev(void)
+{
+ struct mxs_digctl_regs *digctl_regs =
+ (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
+ uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
+
+ switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
+ case HW_DIGCTL_CHIPID_MX28:
+ switch (rev) {
+ case 0x1:
+ return "1.2";
+ default:
+ return "??";
+ }
+ default:
+ return "??";
+ }
+}
+
+int print_cpuinfo(void)
+{
+ struct mxs_spl_data *data = (struct mxs_spl_data *)
+ ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
+
+ printf("CPU: Freescale i.MX%s rev%s at %d MHz\n",
+ get_cpu_type(),
+ get_cpu_rev(),
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
return 0;
}
#endif
/*
* Initializes on-chip ethernet controllers.
*/
-#ifdef CONFIG_CMD_NET
+#if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
int cpu_eth_init(bd_t *bis)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
/* Turn on ENET clocks */
clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
#define MXS_OCOTP_MAX_TIMEOUT 1000000
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
- struct mx28_ocotp_regs *ocotp_regs =
- (struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
+ struct mxs_ocotp_regs *ocotp_regs =
+ (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
uint32_t data;
memset(mac, 0, 6);
writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
- if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
+ if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
MXS_OCOTP_MAX_TIMEOUT)) {
printf("MXS FEC: Can't get MAC from OCOTP\n");
return;
}
#endif
-int mx28_dram_init(void)
+int mxs_dram_init(void)
{
- struct mx28_spl_data *data = (struct mx28_spl_data *)
- ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
+ struct mxs_spl_data *data = (struct mxs_spl_data *)
+ ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
if (data->mem_dram_size == 0) {
- printf("MX28:\n"
+ printf("MXS:\n"
"Error, the RAM size passed up from SPL is 0!\n");
hang();
}
void early_delay(int delay);
-void mx28_power_init(void);
+void mxs_power_init(void);
#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
-void mx28_power_wait_pswitch(void);
+void mxs_power_wait_pswitch(void);
#else
-static inline void mx28_power_wait_pswitch(void) { }
+static inline void mxs_power_wait_pswitch(void) { }
#endif
-void mx28_mem_init(void);
-uint32_t mx28_mem_get_size(void);
+void mxs_mem_init(void);
+uint32_t mxs_mem_get_size(void);
-void mx28_lradc_init(void);
-void mx28_lradc_enable_batt_measurement(void);
+void mxs_lradc_init(void);
+void mxs_lradc_enable_batt_measurement(void);
#endif /* __M28_INIT_H__ */
#include <common.h>
#include <config.h>
#include <asm/io.h>
-#include <asm/arch/iomux-mx28.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
-#include "mx28_init.h"
+#include "mxs_init.h"
/*
* This delay function is intended to be used only in early stage of boot, where
MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
};
-uint8_t mx28_get_bootmode_index(void)
+uint8_t mxs_get_bootmode_index(void)
{
uint8_t bootmode = 0;
int i;
bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4;
bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
- for (i = 0; i < ARRAY_SIZE(mx28_boot_modes); i++) {
- masked = bootmode & mx28_boot_modes[i].boot_mask;
- if (masked == mx28_boot_modes[i].boot_pads)
+ for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) {
+ masked = bootmode & mxs_boot_modes[i].boot_mask;
+ if (masked == mxs_boot_modes[i].boot_pads)
break;
}
return i;
}
-void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
+void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size)
{
- struct mx28_spl_data *data = (struct mx28_spl_data *)
- ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
- uint8_t bootmode = mx28_get_bootmode_index();
+ struct mxs_spl_data *data = (struct mxs_spl_data *)
+ ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
+ uint8_t bootmode = mxs_get_bootmode_index();
mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
- mx28_power_init();
+ mxs_power_init();
- mx28_mem_init();
- data->mem_dram_size = mx28_mem_get_size();
+ mxs_mem_init();
+ data->mem_dram_size = mxs_mem_get_size();
data->boot_mode_idx = bootmode;
- mx28_power_wait_pswitch();
+ mxs_power_wait_pswitch();
}
/* Support aparatus */
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include "mx28_init.h"
+#include "mxs_init.h"
-void mx28_lradc_init(void)
+void mxs_lradc_init(void)
{
- struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE;
+ struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
writel(LRADC_CTRL0_SFTRST, ®s->hw_lradc_ctrl0_clr);
writel(LRADC_CTRL0_CLKGATE, ®s->hw_lradc_ctrl0_clr);
LRADC_CTRL4_LRADC6SELECT_CHANNEL10);
}
-void mx28_lradc_enable_batt_measurement(void)
+void mxs_lradc_enable_batt_measurement(void)
{
- struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE;
+ struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
/* Check if the channel is present at all. */
if (!(readl(®s->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))
#include <common.h>
#include <config.h>
#include <asm/io.h>
-#include <asm/arch/iomux-mx28.h>
#include <asm/arch/imx-regs.h>
-#include "mx28_init.h"
+#include "mxs_init.h"
-uint32_t dram_vals[] = {
+static uint32_t mx28_dram_vals[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00010001
};
-void __mx28_adjust_memory_params(uint32_t *dram_vals)
+void __mxs_adjust_memory_params(uint32_t *dram_vals)
{
}
-void mx28_adjust_memory_params(uint32_t *dram_vals)
- __attribute__((weak, alias("__mx28_adjust_memory_params")));
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+ __attribute__((weak, alias("__mxs_adjust_memory_params")));
-void init_m28_200mhz_ddr2(void)
+void init_mx28_200mhz_ddr2(void)
{
int i;
- mx28_adjust_memory_params(dram_vals);
+ mxs_adjust_memory_params(mx28_dram_vals);
- for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
- writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+ for (i = 0; i < ARRAY_SIZE(mx28_dram_vals); i++)
+ writel(mx28_dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
-void mx28_mem_init_clock(void)
+void mxs_mem_init_clock(void)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
/* Gate EMI clock */
writeb(CLKCTRL_FRAC_CLKGATE,
early_delay(10000);
}
-void mx28_mem_setup_cpu_and_hbus(void)
+void mxs_mem_setup_cpu_and_hbus(void)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
* and ungate CPU clock */
early_delay(15000);
}
-void mx28_mem_setup_vdda(void)
+void mxs_mem_setup_vdda(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
(0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
&power_regs->hw_power_vddactrl);
}
-void mx28_mem_setup_vddd(void)
+void mxs_mem_setup_vddd(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
(0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
&power_regs->hw_power_vdddctrl);
}
-uint32_t mx28_mem_get_size(void)
+uint32_t mxs_mem_get_size(void)
{
uint32_t sz, da;
uint32_t *vt = (uint32_t *)0x20;
return sz;
}
-void mx28_mem_init(void)
+void mxs_mem_init(void)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
- struct mx28_pinctrl_regs *pinctrl_regs =
- (struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_pinctrl_regs *pinctrl_regs =
+ (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
/* Set DDR2 mode */
writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
early_delay(11000);
- mx28_mem_init_clock();
+ mxs_mem_init_clock();
- mx28_mem_setup_vdda();
+ mxs_mem_setup_vdda();
/*
* Configure the DRAM registers
/* Clear START bit from DRAM_CTL16 */
clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
- init_m28_200mhz_ddr2();
+ init_mx28_200mhz_ddr2();
/* Clear SREFRESH bit from DRAM_CTL17 */
clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
;
- mx28_mem_setup_vddd();
+ mxs_mem_setup_vddd();
early_delay(10000);
- mx28_mem_setup_cpu_and_hbus();
+ mxs_mem_setup_cpu_and_hbus();
}
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include "mx28_init.h"
+#include "mxs_init.h"
-void mx28_power_clock2xtal(void)
+void mxs_power_clock2xtal(void)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
/* Set XTAL as CPU reference clock */
writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
&clkctrl_regs->hw_clkctrl_clkseq_set);
}
-void mx28_power_clock2pll(void)
+void mxs_power_clock2pll(void)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
CLKCTRL_PLL0CTRL0_POWER);
CLKCTRL_CLKSEQ_BYPASS_CPU);
}
-void mx28_power_clear_auto_restart(void)
+void mxs_power_clear_auto_restart(void)
{
- struct mx28_rtc_regs *rtc_regs =
- (struct mx28_rtc_regs *)MXS_RTC_BASE;
+ struct mxs_rtc_regs *rtc_regs =
+ (struct mxs_rtc_regs *)MXS_RTC_BASE;
writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
;
}
-void mx28_power_set_linreg(void)
+void mxs_power_set_linreg(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
/* Set linear regulator 25mV below switching converter */
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
}
-int mx28_get_batt_volt(void)
+int mxs_get_batt_volt(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t volt = readl(&power_regs->hw_power_battmonitor);
volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
return volt;
}
-int mx28_is_batt_ready(void)
+int mxs_is_batt_ready(void)
{
- return (mx28_get_batt_volt() >= 3600);
+ return (mxs_get_batt_volt() >= 3600);
}
-int mx28_is_batt_good(void)
+int mxs_is_batt_good(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
- uint32_t volt = mx28_get_batt_volt();
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
+ uint32_t volt = mxs_get_batt_volt();
if ((volt >= 2400) && (volt <= 4300))
return 1;
early_delay(500000);
- volt = mx28_get_batt_volt();
+ volt = mxs_get_batt_volt();
if (volt >= 3500)
return 0;
return 0;
}
-void mx28_power_setup_5v_detect(void)
+void mxs_power_setup_5v_detect(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
/* Start 5V detection */
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_PWRUP_VBUS_CMPS);
}
-void mx28_src_power_init(void)
+void mxs_src_power_init(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
/* Improve efficieny and reduce transient ripple */
writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
}
-void mx28_power_init_4p2_params(void)
+void mxs_power_init_4p2_params(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
/* Setup 4P2 parameters */
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
}
-void mx28_enable_4p2_dcdc_input(int xfer)
+void mxs_enable_4p2_dcdc_input(int xfer)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
uint32_t prev_5v_brnout, prev_5v_droop;
POWER_CTRL_ENIRQ_VDD5V_DROOP);
}
-void mx28_power_init_4p2_regulator(void)
+void mxs_power_init_4p2_regulator(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, tmp2;
setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
* gradually to avoid large inrush current from the 5V cable which can
* cause transients/problems
*/
- mx28_enable_4p2_dcdc_input(0);
+ mxs_enable_4p2_dcdc_input(0);
if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
/*
writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
}
-void mx28_power_init_dcdc_4p2_source(void)
+void mxs_power_init_dcdc_4p2_source(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
if (!(readl(&power_regs->hw_power_dcdc4p2) &
POWER_DCDC4P2_ENABLE_DCDC)) {
hang();
}
- mx28_enable_4p2_dcdc_input(1);
+ mxs_enable_4p2_dcdc_input(1);
if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
clrbits_le32(&power_regs->hw_power_dcdc4p2,
}
}
-void mx28_power_enable_4p2(void)
+void mxs_power_enable_4p2(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t vdddctrl, vddactrl, vddioctrl;
uint32_t tmp;
setbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
- mx28_power_init_4p2_params();
- mx28_power_init_4p2_regulator();
+ mxs_power_init_4p2_params();
+ mxs_power_init_4p2_regulator();
/* Shutdown battery (none present) */
- if (!mx28_is_batt_ready()) {
+ if (!mxs_is_batt_ready()) {
clrbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_BO_MASK);
writel(POWER_CTRL_DCDC4P2_BO_IRQ,
&power_regs->hw_power_ctrl_clr);
}
- mx28_power_init_dcdc_4p2_source();
+ mxs_power_init_dcdc_4p2_source();
writel(vdddctrl, &power_regs->hw_power_vdddctrl);
early_delay(20);
&power_regs->hw_power_charge_clr);
}
-void mx28_boot_valid_5v(void)
+void mxs_boot_valid_5v(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
/*
* Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
&power_regs->hw_power_ctrl_clr);
- mx28_power_enable_4p2();
+ mxs_power_enable_4p2();
}
-void mx28_powerdown(void)
+void mxs_powerdown(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
&power_regs->hw_power_reset);
}
-void mx28_batt_boot(void)
+void mxs_batt_boot(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
clrsetbits_le32(&power_regs->hw_power_minpwr,
POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
- mx28_power_set_linreg();
+ mxs_power_set_linreg();
clrbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
}
-void mx28_handle_5v_conflict(void)
+void mxs_handle_5v_conflict(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
setbits_le32(&power_regs->hw_power_vddioctrl,
tmp = readl(&power_regs->hw_power_sts);
if (tmp & POWER_STS_VDDIO_BO) {
- mx28_powerdown();
+ /*
+ * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
+ * unreliable
+ */
+ mxs_powerdown();
break;
}
if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
- mx28_boot_valid_5v();
+ mxs_boot_valid_5v();
break;
} else {
- mx28_powerdown();
+ mxs_powerdown();
break;
}
if (tmp & POWER_STS_PSWITCH_MASK) {
- mx28_batt_boot();
+ mxs_batt_boot();
break;
}
}
}
-void mx28_5v_boot(void)
+void mxs_5v_boot(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
/*
* NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
* but their implementation always returns 1 so we omit it here.
*/
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
- mx28_boot_valid_5v();
+ mxs_boot_valid_5v();
return;
}
early_delay(1000);
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
- mx28_boot_valid_5v();
+ mxs_boot_valid_5v();
return;
}
- mx28_handle_5v_conflict();
+ mxs_handle_5v_conflict();
}
-void mx28_init_batt_bo(void)
+void mxs_init_batt_bo(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
/* Brownout at 3V */
clrsetbits_le32(&power_regs->hw_power_battmonitor,
writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
}
-void mx28_switch_vddd_to_dcdc_source(void)
+void mxs_switch_vddd_to_dcdc_source(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDDCTRL_DISABLE_STEPPING);
}
-void mx28_power_configure_power_source(void)
+void mxs_power_configure_power_source(void)
{
int batt_ready, batt_good;
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
- struct mx28_lradc_regs *lradc_regs =
- (struct mx28_lradc_regs *)MXS_LRADC_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
+ struct mxs_lradc_regs *lradc_regs =
+ (struct mxs_lradc_regs *)MXS_LRADC_BASE;
- mx28_src_power_init();
-
- batt_ready = mx28_is_batt_ready();
+ mxs_src_power_init();
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
- batt_good = mx28_is_batt_good();
+ batt_ready = mxs_is_batt_ready();
if (batt_ready) {
/* 5V source detected, good battery detected. */
- mx28_batt_boot();
+ mxs_batt_boot();
} else {
- if (batt_good) {
- /* 5V source detected, low battery detceted. */
- } else {
+ batt_good = mxs_is_batt_good();
+ if (!batt_good) {
/* 5V source detected, bad battery detected. */
writel(LRADC_CONVERSION_AUTOMATIC,
&lradc_regs->hw_lradc_conversion_clr);
clrbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_BATT_VAL_MASK);
}
- mx28_5v_boot();
+ mxs_5v_boot();
}
} else {
/* 5V not detected, booting from battery. */
- mx28_batt_boot();
+ mxs_batt_boot();
}
- mx28_power_clock2pll();
+ mxs_power_clock2pll();
- mx28_init_batt_bo();
+ mxs_init_batt_bo();
- mx28_switch_vddd_to_dcdc_source();
+ mxs_switch_vddd_to_dcdc_source();
}
-void mx28_enable_output_rail_protection(void)
+void mxs_enable_output_rail_protection(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
POWER_VDDIOCTRL_PWDN_BRNOUT);
}
-int mx28_get_vddio_power_source_off(void)
+int mxs_get_vddio_power_source_off(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
tmp = readl(&power_regs->hw_power_vddioctrl);
if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
- POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+ POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
return 1;
}
}
if (!(readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_ENABLE_DCDC)) {
if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
- POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+ POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
return 1;
}
}
}
-int mx28_get_vddd_power_source_off(void)
+int mxs_get_vddd_power_source_off(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
tmp = readl(&power_regs->hw_power_vdddctrl);
return 0;
}
-void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
+void mxs_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t cur_target, diff, bo_int = 0;
uint32_t powered_by_linreg = 0;
- new_brownout = new_target - new_brownout;
+ new_brownout = (new_target - new_brownout + 25) / 50;
cur_target = readl(&power_regs->hw_power_vddioctrl);
cur_target &= POWER_VDDIOCTRL_TRG_MASK;
cur_target *= 50; /* 50 mV step*/
cur_target += 2800; /* 2800 mV lowest */
- powered_by_linreg = mx28_get_vddio_power_source_off();
+ powered_by_linreg = mxs_get_vddio_power_source_off();
if (new_target > cur_target) {
if (powered_by_linreg) {
}
clrsetbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_VDDDCTRL_BO_OFFSET_MASK,
- new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
+ POWER_VDDIOCTRL_BO_OFFSET_MASK,
+ new_brownout << POWER_VDDIOCTRL_BO_OFFSET_OFFSET);
}
-void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
+void mxs_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t cur_target, diff, bo_int = 0;
uint32_t powered_by_linreg = 0;
- new_brownout = new_target - new_brownout;
+ new_brownout = (new_target - new_brownout + 12) / 25;
cur_target = readl(&power_regs->hw_power_vdddctrl);
cur_target &= POWER_VDDDCTRL_TRG_MASK;
cur_target *= 25; /* 25 mV step*/
cur_target += 800; /* 800 mV lowest */
- powered_by_linreg = mx28_get_vddd_power_source_off();
+ powered_by_linreg = mxs_get_vddd_power_source_off();
if (new_target > cur_target) {
if (powered_by_linreg) {
bo_int = readl(&power_regs->hw_power_vdddctrl);
new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
}
-void mx28_setup_batt_detect(void)
+void mxs_setup_batt_detect(void)
{
- mx28_lradc_init();
- mx28_lradc_enable_batt_measurement();
+ mxs_lradc_init();
+ mxs_lradc_enable_batt_measurement();
early_delay(10);
}
-void mx28_power_init(void)
+void mxs_power_init(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
- mx28_power_clock2xtal();
- mx28_power_clear_auto_restart();
- mx28_power_set_linreg();
- mx28_power_setup_5v_detect();
+ mxs_power_clock2xtal();
+ mxs_power_clear_auto_restart();
+ mxs_power_set_linreg();
+ mxs_power_setup_5v_detect();
- mx28_setup_batt_detect();
+ mxs_setup_batt_detect();
- mx28_power_configure_power_source();
- mx28_enable_output_rail_protection();
+ mxs_power_configure_power_source();
+ mxs_enable_output_rail_protection();
- mx28_power_set_vddio(3300, 3150);
+ mxs_power_set_vddio(3300, 3150);
- mx28_power_set_vddd(1350, 1200);
+ mxs_power_set_vddd(1350, 1200);
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
}
#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
-void mx28_power_wait_pswitch(void)
+void mxs_power_wait_pswitch(void)
{
- struct mx28_power_regs *power_regs =
- (struct mx28_power_regs *)MXS_POWER_BASE;
+ struct mxs_power_regs *power_regs =
+ (struct mxs_power_regs *)MXS_POWER_BASE;
while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
;
orr r0,r0,#0xd3
msr cpsr,r0
- /*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
-#endif
-
bl board_init_ll
/*
pop {r0-r12,r14}
bx lr
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-cpu_init_crit:
- /*
- * flush v4 I/D caches
- */
- mov r0, #0
- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
-
- /*
- * disable MMU stuff and caches
- */
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
- bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
- orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
- orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
- mcr p15, 0, r0, c1, c0, 0
-
- mov pc, lr /* back to my caller */
-
- .align 5
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
_hang:
ldr sp, _TEXT_BASE /* switch to abort stack */
1:
int timer_init(void)
{
- struct mx28_timrot_regs *timrot_regs =
- (struct mx28_timrot_regs *)MXS_TIMROT_BASE;
+ struct mxs_timrot_regs *timrot_regs =
+ (struct mxs_timrot_regs *)MXS_TIMROT_BASE;
/* Reset Timers and Rotary Encoder module */
- mx28_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
+ mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
/* Set fixed_count to 0 */
writel(0, &timrot_regs->hw_timrot_fixed_count0);
unsigned long long get_ticks(void)
{
- struct mx28_timrot_regs *timrot_regs =
- (struct mx28_timrot_regs *)MXS_TIMROT_BASE;
+ struct mxs_timrot_regs *timrot_regs =
+ (struct mxs_timrot_regs *)MXS_TIMROT_BASE;
/* Current tick value */
uint32_t now = readl(&timrot_regs->hw_timrot_running_count0);
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm926ejs/mx28/start.o (.text)
+ arch/arm/cpu/arm926ejs/mxs/start.o (.text)
*(.text)
}
COBJS += cpu.o
COBJS += syslib.o
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
+SOBJS += lowlevel_init.o
+endif
+
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)
*/
#include <common.h>
+#include <errno.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/common_def.h>
+#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/omap_common.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
DECLARE_GLOBAL_DATA_PTR;
struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+static const struct gpio_bank gpio_bank_am33xx[4] = {
+ { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
+ { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
+ { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
+ { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
+
+/* MII mode defines */
+#define MII_MODE_ENABLE 0x0
+#define RGMII_MODE_ENABLE 0xA
+
+/* GPIO that controls power to DDR on EVM-SK */
+#define GPIO_DDR_VTT_EN 7
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+static struct am335x_baseboard_id __attribute__((section (".data"))) header;
+
+static inline int board_is_bone(void)
+{
+ return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
+}
+
+static inline int board_is_evm_sk(void)
+{
+ return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
+}
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+ /* Check if baseboard eeprom is available */
+ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+ puts("Could not probe the EEPROM; something fundamentally "
+ "wrong on the I2C bus.\n");
+ return -ENODEV;
+ }
+
+ /* read the eeprom using i2c */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
+ sizeof(header))) {
+ puts("Could not read the EEPROM; something fundamentally"
+ " wrong on the I2C bus.\n");
+ return -EIO;
+ }
+
+ if (header.magic != 0xEE3355AA) {
+ /*
+ * read the eeprom using i2c again,
+ * but use only a 1 byte address
+ */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
+ (uchar *)&header, sizeof(header))) {
+ puts("Could not read the EEPROM; something "
+ "fundamentally wrong on the I2C bus.\n");
+ return -EIO;
+ }
+
+ if (header.magic != 0xEE3355AA) {
+ printf("Incorrect magic number (0x%x) in EEPROM\n",
+ header.magic);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
/* UART Defines */
#ifdef CONFIG_SPL_BUILD
#define UART_RESET (0x1 << 1)
}
#endif
+/*
+ * Determine what type of DDR we have.
+ */
+static short inline board_memory_type(void)
+{
+ /* The following boards are known to use DDR3. */
+ if (board_is_evm_sk())
+ return EMIF_REG_SDRAM_TYPE_DDR3;
+
+ return EMIF_REG_SDRAM_TYPE_DDR2;
+}
+
/*
* early system init of muxing and clocks.
*/
preloader_console_init();
- config_ddr();
-#endif
+ /* Initalize the board header */
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ if (read_eeprom() < 0)
+ puts("Could not get board ID.\n");
+
+ enable_board_pin_mux(&header);
+ if (board_is_evm_sk()) {
+ /*
+ * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
+ * This is safe enough to do on older revs.
+ */
+ gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
+ gpio_direction_output(GPIO_DDR_VTT_EN, 1);
+ }
- /* Enable MMC0 */
- enable_mmc0_pin_mux();
+ config_ddr(board_memory_type());
+#endif
}
#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- return omap_mmc_init(0, 0, 0);
+ int ret;
+
+ ret = omap_mmc_init(0, 0, 0);
+ if (ret)
+ return ret;
+
+ return omap_mmc_init(1, 0, 0);
}
#endif
/* Not yet implemented */
return;
}
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ if (read_eeprom() < 0)
+ puts("Could not get board ID.\n");
+
+ gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_id = 0,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_id = 1,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = AM335X_CPSW_MDIO_BASE,
+ .cpsw_base = AM335X_CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+ debug("<ethaddr> not set. Reading from E-fuse\n");
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ else
+ return -1;
+ }
+
+ if (board_is_bone()) {
+ writel(MII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
+ PHY_INTERFACE_MODE_MII;
+ } else {
+ writel(RGMII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
+ PHY_INTERFACE_MODE_RGMII;
+ }
+
+ return cpsw_register(&cpsw_data);
+}
+#endif
#define PRCM_MOD_EN 0x2
#define PRCM_FORCE_WAKEUP 0x2
+#define PRCM_FUNCTL 0x0
#define PRCM_EMIF_CLK_ACTIVITY BIT(2)
#define PRCM_L3_GCLK_ACTIVITY BIT(4)
#define CLK_MODE_SEL 0x7
#define CLK_MODE_MASK 0xfffffff8
#define CLK_DIV_SEL 0xFFFFFFE0
-
+#define CPGMAC0_IDLE 0x30000
const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
;
+
+ writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
+ while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
+ ;
}
/*
writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
;
+
+ /* gpio1 module */
+ writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
+ while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
+ ;
+
+ /* gpio2 module */
+ writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
+ while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
+ ;
+
+ /* gpio3 module */
+ writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
+ while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
+ ;
+
+ /* i2c1 */
+ writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
+ while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
+ ;
+
+ /* Ethernet */
+ writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
+ while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
+ ;
+
+ /* spi0 */
+ writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
+ while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
+ ;
}
static void mpu_pll_config(void)
;
}
-static void ddr_pll_config(void)
+void ddr_pll_config(unsigned int ddrpll_m)
{
u32 clkmode, clksel, div_m2;
;
clksel = clksel & (~CLK_SEL_MASK);
- clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N);
+ clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
writel(clksel, &cmwkup->clkseldpllddr);
div_m2 = div_m2 & CLK_DIV_SEL;
writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
/* Enable EMIF0 Clock */
writel(PRCM_MOD_EN, &cmper->emifclkctrl);
- /* Poll for emif_gclk & L3_G clock are active */
- while ((readl(&cmper->l3clkstctrl) & (PRCM_EMIF_CLK_ACTIVITY |
- PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY |
- PRCM_L3_GCLK_ACTIVITY))
- ;
/* Poll if module is functional */
while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
;
mpu_pll_config();
core_pll_config();
per_pll_config();
- ddr_pll_config();
/* Enable the required interconnect clocks */
enable_interface_clocks();
#include <asm/arch/cpu.h>
#include <asm/arch/ddr_defs.h>
+#include <asm/arch/sys_proto.h>
#include <asm/io.h>
+#include <asm/emif.h>
/**
* Base address for EMIF instances
*/
-static struct emif_regs *emif_reg = {
- (struct emif_regs *)EMIF4_0_CFG_BASE};
+static struct emif_reg_struct *emif_reg = {
+ (struct emif_reg_struct *)EMIF4_0_CFG_BASE};
/**
* Base address for DDR instance
static struct ddr_cmdtctrl *ioctrl_reg = {
(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
-/**
- * As a convention, all functions here return 0 on success
- * -1 on failure.
- */
-
/**
* Configure SDRAM
*/
-int config_sdram(struct sdram_config *cfg)
+void config_sdram(const struct emif_regs *regs)
{
- writel(cfg->sdrcr, &emif_reg->sdrcr);
- writel(cfg->sdrcr2, &emif_reg->sdrcr2);
- writel(cfg->refresh, &emif_reg->sdrrcr);
- writel(cfg->refresh_sh, &emif_reg->sdrrcsr);
-
- return 0;
+ writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
+ writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
+ if (regs->zq_config){
+ writel(regs->zq_config, &emif_reg->emif_zq_config);
+ writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+ }
+ writel(regs->sdram_config, &emif_reg->emif_sdram_config);
}
/**
* Set SDRAM timings
*/
-int set_sdram_timings(struct sdram_timing *t)
+void set_sdram_timings(const struct emif_regs *regs)
{
- writel(t->time1, &emif_reg->sdrtim1);
- writel(t->time1_sh, &emif_reg->sdrtim1sr);
- writel(t->time2, &emif_reg->sdrtim2);
- writel(t->time2_sh, &emif_reg->sdrtim2sr);
- writel(t->time3, &emif_reg->sdrtim3);
- writel(t->time3_sh, &emif_reg->sdrtim3sr);
-
- return 0;
+ writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
+ writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
+ writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
+ writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
+ writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
+ writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
}
/**
* Configure DDR PHY
*/
-int config_ddr_phy(struct ddr_phy_control *p)
+void config_ddr_phy(const struct emif_regs *regs)
{
- writel(p->reg, &emif_reg->ddrphycr);
- writel(p->reg_sh, &emif_reg->ddrphycsr);
-
- return 0;
+ writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
+ writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
}
/**
* Configure DDR CMD control registers
*/
-int config_cmd_ctrl(struct cmd_control *cmd)
+void config_cmd_ctrl(const struct cmd_control *cmd)
{
writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
- writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
- writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay);
writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
- writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce);
- writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay);
writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
- writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce);
- writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
-
- return 0;
}
/**
* Configure DDR DATA registers
*/
-int config_ddr_data(int macrono, struct ddr_data *data)
+void config_ddr_data(int macrono, const struct ddr_data *data)
{
writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
- writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1);
-
writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
- writel(data->datawdsratio1, &ddr_reg[macrono]->dt0wdsratio1);
-
writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
- writel(data->datawiratio1, &ddr_reg[macrono]->dt0wiratio1);
writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
- writel(data->datagiratio1, &ddr_reg[macrono]->dt0giratio1);
-
writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
- writel(data->datafwsratio1, &ddr_reg[macrono]->dt0fwsratio1);
-
writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
- writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1);
-
+ writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0);
writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
-
- return 0;
}
-int config_io_ctrl(struct ddr_ioctrl *ioctrl)
+void config_io_ctrl(unsigned long val)
{
- writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
- writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
- writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
- writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
- writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);
-
- return 0;
+ writel(val, &ioctrl_reg->cm0ioctl);
+ writel(val, &ioctrl_reg->cm1ioctl);
+ writel(val, &ioctrl_reg->cm2ioctl);
+ writel(val, &ioctrl_reg->dt0ioctl);
+ writel(val, &ioctrl_reg->dt1ioctl);
}
#include <asm/arch/ddr_defs.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
#include <asm/io.h>
+#include <asm/emif.h>
DECLARE_GLOBAL_DATA_PTR;
-struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
-struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
-struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
-
-
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
#ifdef CONFIG_SPL_BUILD
-static void data_macro_config(int dataMacroNum)
-{
- struct ddr_data data;
-
- data.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
- |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0));
- data.datardsratio1 = DDR2_RD_DQS>>2;
- data.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
- |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0));
- data.datawdsratio1 = DDR2_WR_DQS>>2;
- data.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
- |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0));
- data.datawiratio1 = DDR2_PHY_WRLVL>>2;
- data.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
- |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0));
- data.datagiratio1 = DDR2_PHY_GATELVL>>2;
- data.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
- |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0));
- data.datafwsratio1 = DDR2_PHY_FIFO_WE>>2;
- data.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
- |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0));
- data.datawrsratio1 = DDR2_PHY_WR_DATA>>2;
- data.datadldiff0 = PHY_DLL_LOCK_DIFF;
-
- config_ddr_data(dataMacroNum, &data);
-}
-
-static void cmd_macro_config(void)
-{
- struct cmd_control cmd;
-
- cmd.cmd0csratio = DDR2_RATIO;
- cmd.cmd0csforce = CMD_FORCE;
- cmd.cmd0csdelay = CMD_DELAY;
- cmd.cmd0dldiff = DDR2_DLL_LOCK_DIFF;
- cmd.cmd0iclkout = DDR2_INVERT_CLKOUT;
-
- cmd.cmd1csratio = DDR2_RATIO;
- cmd.cmd1csforce = CMD_FORCE;
- cmd.cmd1csdelay = CMD_DELAY;
- cmd.cmd1dldiff = DDR2_DLL_LOCK_DIFF;
- cmd.cmd1iclkout = DDR2_INVERT_CLKOUT;
-
- cmd.cmd2csratio = DDR2_RATIO;
- cmd.cmd2csforce = CMD_FORCE;
- cmd.cmd2csdelay = CMD_DELAY;
- cmd.cmd2dldiff = DDR2_DLL_LOCK_DIFF;
- cmd.cmd2iclkout = DDR2_INVERT_CLKOUT;
-
- config_cmd_ctrl(&cmd);
-
-}
+static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
+static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+
+static const struct ddr_data ddr2_data = {
+ .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
+ |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
+ .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
+ |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
+ .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
+ |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
+ .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
+ |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
+ .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
+ |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
+ .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
+ |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
+ .datauserank0delay = DDR2_PHY_RANK0_DELAY,
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr2_cmd_ctrl_data = {
+ .cmd0csratio = DDR2_RATIO,
+ .cmd0dldiff = DDR2_DLL_LOCK_DIFF,
+ .cmd0iclkout = DDR2_INVERT_CLKOUT,
+
+ .cmd1csratio = DDR2_RATIO,
+ .cmd1dldiff = DDR2_DLL_LOCK_DIFF,
+ .cmd1iclkout = DDR2_INVERT_CLKOUT,
+
+ .cmd2csratio = DDR2_RATIO,
+ .cmd2dldiff = DDR2_DLL_LOCK_DIFF,
+ .cmd2iclkout = DDR2_INVERT_CLKOUT,
+};
+
+static const struct emif_regs ddr2_emif_reg_data = {
+ .sdram_config = DDR2_EMIF_SDCFG,
+ .ref_ctrl = DDR2_EMIF_SDREF,
+ .sdram_tim1 = DDR2_EMIF_TIM1,
+ .sdram_tim2 = DDR2_EMIF_TIM2,
+ .sdram_tim3 = DDR2_EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
+};
+
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = DDR3_RD_DQS,
+ .datawdsratio0 = DDR3_WR_DQS,
+ .datafwsratio0 = DDR3_PHY_FIFO_WE,
+ .datawrsratio0 = DDR3_PHY_WR_DATA,
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = DDR3_RATIO,
+ .cmd0dldiff = DDR3_DLL_LOCK_DIFF,
+ .cmd0iclkout = DDR3_INVERT_CLKOUT,
+
+ .cmd1csratio = DDR3_RATIO,
+ .cmd1dldiff = DDR3_DLL_LOCK_DIFF,
+ .cmd1iclkout = DDR3_INVERT_CLKOUT,
+
+ .cmd2csratio = DDR3_RATIO,
+ .cmd2dldiff = DDR3_DLL_LOCK_DIFF,
+ .cmd2iclkout = DDR3_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = DDR3_EMIF_SDCFG,
+ .ref_ctrl = DDR3_EMIF_SDREF,
+ .sdram_tim1 = DDR3_EMIF_TIM1,
+ .sdram_tim2 = DDR3_EMIF_TIM2,
+ .sdram_tim3 = DDR3_EMIF_TIM3,
+ .zq_config = DDR3_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY,
+};
static void config_vtp(void)
{
;
}
-static void config_emif_ddr2(void)
-{
- int i;
- int ret;
- struct sdram_config cfg;
- struct sdram_timing tmg;
- struct ddr_phy_control phyc;
-
- /*Program EMIF0 CFG Registers*/
- phyc.reg = EMIF_READ_LATENCY;
- phyc.reg_sh = EMIF_READ_LATENCY;
- phyc.reg2 = EMIF_READ_LATENCY;
-
- tmg.time1 = EMIF_TIM1;
- tmg.time1_sh = EMIF_TIM1;
- tmg.time2 = EMIF_TIM2;
- tmg.time2_sh = EMIF_TIM2;
- tmg.time3 = EMIF_TIM3;
- tmg.time3_sh = EMIF_TIM3;
-
- cfg.sdrcr = EMIF_SDCFG;
- cfg.sdrcr2 = EMIF_SDCFG;
- cfg.refresh = 0x00004650;
- cfg.refresh_sh = 0x00004650;
-
- /* Program EMIF instance */
- ret = config_ddr_phy(&phyc);
- if (ret < 0)
- printf("Couldn't configure phyc\n");
-
- ret = config_sdram(&cfg);
- if (ret < 0)
- printf("Couldn't configure SDRAM\n");
-
- ret = set_sdram_timings(&tmg);
- if (ret < 0)
- printf("Couldn't configure timings\n");
-
- /* Delay */
- for (i = 0; i < 5000; i++)
- ;
-
- cfg.refresh = EMIF_SDREF;
- cfg.refresh_sh = EMIF_SDREF;
- cfg.sdrcr = EMIF_SDCFG;
- cfg.sdrcr2 = EMIF_SDCFG;
-
- ret = config_sdram(&cfg);
- if (ret < 0)
- printf("Couldn't configure SDRAM\n");
-}
-
-void config_ddr(void)
+void config_ddr(short ddr_type)
{
- int data_macro_0 = 0;
- int data_macro_1 = 1;
- struct ddr_ioctrl ioctrl;
+ int ddr_pll, ioctrl_val;
+ const struct emif_regs *emif_regs;
+ const struct ddr_data *ddr_data;
+ const struct cmd_control *cmd_ctrl_data;
+
+ if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
+ ddr_pll = 266;
+ cmd_ctrl_data = &ddr2_cmd_ctrl_data;
+ ddr_data = &ddr2_data;
+ ioctrl_val = DDR2_IOCTRL_VALUE;
+ emif_regs = &ddr2_emif_reg_data;
+ } else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) {
+ ddr_pll = 303;
+ cmd_ctrl_data = &ddr3_cmd_ctrl_data;
+ ddr_data = &ddr3_data;
+ ioctrl_val = DDR3_IOCTRL_VALUE;
+ emif_regs = &ddr3_emif_reg_data;
+ } else {
+ puts("Unknown memory type");
+ hang();
+ }
enable_emif_clocks();
-
+ ddr_pll_config(ddr_pll);
config_vtp();
+ config_cmd_ctrl(cmd_ctrl_data);
- cmd_macro_config();
-
- data_macro_config(data_macro_0);
- data_macro_config(data_macro_1);
+ config_ddr_data(0, ddr_data);
+ config_ddr_data(1, ddr_data);
- writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
- writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
+ config_io_ctrl(ioctrl_val);
- ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
- ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
- ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
- ioctrl.data1ctl = DDR_IOCTRL_VALUE;
- ioctrl.data2ctl = DDR_IOCTRL_VALUE;
+ /* Set CKE to be controlled by EMIF/DDR PHY */
+ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
- config_io_ctrl(&ioctrl);
-
- writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, &ddrctrl->ddrioctrl);
- writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, &ddrctrl->ddrckectrl);
-
- config_emif_ddr2();
+ /* Program EMIF instance */
+ config_ddr_phy(emif_regs);
+ set_sdram_timings(emif_regs);
+ config_sdram(emif_regs);
}
#endif
# supported by more tool-chains
PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5)
PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7)
-PF_CPPFLAGS_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
-PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_NO_UNALIGNED)
# =========================================================================
#
#include <asm/system.h>
#include <asm/cache.h>
#include <asm/armv7.h>
+#include <linux/compiler.h>
-void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3)
-{
-}
-
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
- __attribute__((weak, alias("save_boot_params_default")));
+void __weak cpu_cache_initialization(void){}
int cleanup_before_linux(void)
{
*/
invalidate_dcache_all();
+ /*
+ * Some CPU need more cache attention before starting the kernel.
+ */
+ cpu_cache_initialization();
+
return 0;
}
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long r, m, p, s, k = 0, mask, fout;
- unsigned int freq;
+ unsigned int freq, pll_div2_sel, fout_sel;
switch (pllreg) {
case APLL:
r = readl(&clk->vpll_con0);
k = readl(&clk->vpll_con1);
break;
+ case BPLL:
+ r = readl(&clk->bpll_con0);
+ break;
default:
printf("Unsupported PLL (%d)\n", pllreg);
return 0;
* MPLL_CON: MIDV [25:16]
* EPLL_CON: MIDV [24:16]
* VPLL_CON: MIDV [24:16]
+ * BPLL_CON: MIDV [25:16]
*/
- if (pllreg == APLL || pllreg == MPLL)
+ if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
mask = 0x3ff;
else
mask = 0x1ff;
fout = m * (freq / (p * (1 << (s - 1))));
}
+ /* According to the user manual, in EVT1 MPLL and BPLL always gives
+ * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
+ if (pllreg == MPLL || pllreg == BPLL) {
+ pll_div2_sel = readl(&clk->pll_div2_sel);
+
+ switch (pllreg) {
+ case MPLL:
+ fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
+ & MPLL_FOUT_SEL_MASK;
+ break;
+ case BPLL:
+ fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
+ & BPLL_FOUT_SEL_MASK;
+ break;
+ default:
+ fout_sel = -1;
+ break;
+ }
+
+ if (fout_sel == 0)
+ fout /= 2;
+ }
+
return fout;
}
return pclk;
}
+/* get_lcd_clk: return lcd clock frequency */
+static unsigned long exynos5_get_lcd_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+ * CLK_SRC_LCD0
+ * FIMD0_SEL [3:0]
+ */
+ sel = readl(&clk->src_disp1_0);
+ sel = sel & 0xf;
+
+ /*
+ * 0x6: SCLK_MPLL
+ * 0x7: SCLK_EPLL
+ * 0x8: SCLK_VPLL
+ */
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ /*
+ * CLK_DIV_LCD0
+ * FIMD0_RATIO [3:0]
+ */
+ ratio = readl(&clk->div_disp1_0);
+ ratio = ratio & 0xf;
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
void exynos4_set_lcd_clk(void)
{
struct exynos4_clock *clk =
writel(cfg, &clk->div_lcd0);
}
+void exynos5_set_lcd_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned int cfg = 0;
+
+ /*
+ * CLK_GATE_BLOCK
+ * CLK_CAM [0]
+ * CLK_TV [1]
+ * CLK_MFC [2]
+ * CLK_G3D [3]
+ * CLK_LCD0 [4]
+ * CLK_LCD1 [5]
+ * CLK_GPS [7]
+ */
+ cfg = readl(&clk->gate_block);
+ cfg |= 1 << 4;
+ writel(cfg, &clk->gate_block);
+
+ /*
+ * CLK_SRC_LCD0
+ * FIMD0_SEL [3:0]
+ * MDNIE0_SEL [7:4]
+ * MDNIE_PWM0_SEL [8:11]
+ * MIPI0_SEL [12:15]
+ * set lcd0 src clock 0x6: SCLK_MPLL
+ */
+ cfg = readl(&clk->src_disp1_0);
+ cfg &= ~(0xf);
+ cfg |= 0x8;
+ writel(cfg, &clk->src_disp1_0);
+
+ /*
+ * CLK_GATE_IP_LCD0
+ * CLK_FIMD0 [0]
+ * CLK_MIE0 [1]
+ * CLK_MDNIE0 [2]
+ * CLK_DSIM0 [3]
+ * CLK_SMMUFIMD0 [4]
+ * CLK_PPMULCD0 [5]
+ * Gating all clocks for FIMD0
+ */
+ cfg = readl(&clk->gate_ip_disp1);
+ cfg |= 1 << 0;
+ writel(cfg, &clk->gate_ip_disp1);
+
+ /*
+ * CLK_DIV_LCD0
+ * FIMD0_RATIO [3:0]
+ * MDNIE0_RATIO [7:4]
+ * MDNIE_PWM0_RATIO [11:8]
+ * MDNIE_PWM_PRE_RATIO [15:12]
+ * MIPI0_RATIO [19:16]
+ * MIPI0_PRE_RATIO [23:20]
+ * set fimd ratio
+ */
+ cfg &= ~(0xf);
+ cfg |= 0x0;
+ writel(cfg, &clk->div_disp1_0);
+}
+
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
else
- return 0;
+ return exynos5_get_lcd_clk();
}
void set_lcd_clk(void)
{
if (cpu_is_exynos4())
exynos4_set_lcd_clk();
+ else
+ exynos5_set_lcd_clk();
}
void set_mipi_clk(void)
count = 4;
break;
case PERIPH_ID_UART1:
- bank = &gpio1->a0;
- start = 4;
+ bank = &gpio1->d0;
+ start = 0;
count = 4;
break;
case PERIPH_ID_UART2:
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank, *bank_ext;
- int i;
+ int i, start = 0, gpio_func = 0;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = &gpio1->c0;
bank_ext = &gpio1->c1;
+ start = 0;
+ gpio_func = GPIO_FUNC(0x2);
break;
case PERIPH_ID_SDMMC1:
- bank = &gpio1->c1;
+ bank = &gpio1->c2;
bank_ext = NULL;
break;
case PERIPH_ID_SDMMC2:
- bank = &gpio1->c2;
- bank_ext = &gpio1->c3;
+ bank = &gpio1->c3;
+ bank_ext = &gpio1->c4;
+ start = 3;
+ gpio_func = GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC3:
- bank = &gpio1->c3;
+ bank = &gpio1->c4;
bank_ext = NULL;
break;
}
return -1;
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = 3; i <= 6; i++) {
- s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
+ for (i = start; i <= (start + 3); i++) {
+ s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
}
if (cpu_is_exynos5())
exynos5_set_usbhost_phy_ctrl(enable);
}
+
+static void exynos5_dp_phy_control(unsigned int enable)
+{
+ unsigned int cfg;
+ struct exynos5_power *power =
+ (struct exynos5_power *)samsung_get_base_power();
+
+ cfg = readl(&power->dptx_phy_control);
+ if (enable)
+ cfg |= EXYNOS_DP_PHY_ENABLE;
+ else
+ cfg &= ~EXYNOS_DP_PHY_ENABLE;
+
+ writel(cfg, &power->dptx_phy_control);
+}
+
+void set_dp_phy_ctrl(unsigned int enable)
+{
+ if (cpu_is_exynos5())
+ exynos5_dp_phy_control(enable);
+}
{
writel(0x1, samsung_get_base_swreset());
}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
writel(cfg, &sysreg->display_ctrl);
}
+static void exynos5_set_system_display(void)
+{
+ struct exynos5_sysreg *sysreg =
+ (struct exynos5_sysreg *)samsung_get_base_sysreg();
+ unsigned int cfg = 0;
+
+ /*
+ * system register path set
+ * 0: MIE/MDNIE
+ * 1: FIMD Bypass
+ */
+ cfg = readl(&sysreg->disp1blk_cfg);
+ cfg |= (1 << 15);
+ writel(cfg, &sysreg->disp1blk_cfg);
+}
+
void set_system_display_ctrl(void)
{
if (cpu_is_exynos4())
exynos4_set_system_display();
+ else
+ exynos5_set_system_display();
}
COBJS-y = iomux-v3.o timer.o cpu.o speed.o
COBJS-$(CONFIG_I2C_MXC) += i2c.o
+COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
COBJS := $(sort $(COBJS-y))
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
--- /dev/null
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/imx-common/boot_mode.h>
+#include <malloc.h>
+
+static const struct boot_mode *modes[2];
+
+static const struct boot_mode *search_modes(char *arg)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(modes); i++) {
+ const struct boot_mode *p = modes[i];
+ if (p) {
+ while (p->name) {
+ if (!strcmp(p->name, arg))
+ return p;
+ p++;
+ }
+ }
+ }
+ return NULL;
+}
+
+static int create_usage(char *dest)
+{
+ int i;
+ int size = 0;
+
+ for (i = 0; i < ARRAY_SIZE(modes); i++) {
+ const struct boot_mode *p = modes[i];
+ if (p) {
+ while (p->name) {
+ int len = strlen(p->name);
+ if (dest) {
+ memcpy(dest, p->name, len);
+ dest += len;
+ *dest++ = '|';
+ }
+ size += len + 1;
+ p++;
+ }
+ }
+ }
+ if (dest)
+ memcpy(dest - 1, " [noreset]", 11); /* include trailing 0 */
+ size += 10;
+ return size;
+}
+
+static int do_boot_mode(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ const struct boot_mode *p;
+ int reset_requested = 1;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+ p = search_modes(argv[1]);
+ if (!p)
+ return CMD_RET_USAGE;
+ if (argc == 3) {
+ if (strcmp(argv[2], "noreset"))
+ return CMD_RET_USAGE;
+ reset_requested = 0;
+ }
+
+ boot_mode_apply(p->cfg_val);
+ if (reset_requested && p->cfg_val)
+ do_reset(NULL, 0, 0, NULL);
+ return 0;
+}
+
+U_BOOT_CMD(
+ bmode, 3, 0, do_boot_mode,
+ NULL,
+ "");
+
+void add_board_boot_modes(const struct boot_mode *p)
+{
+ int size;
+ char *dest;
+
+ if (__u_boot_cmd_bmode.usage) {
+ free(__u_boot_cmd_bmode.usage);
+ __u_boot_cmd_bmode.usage = NULL;
+ }
+
+ modes[0] = p;
+ modes[1] = soc_boot_modes;
+ size = create_usage(NULL);
+ dest = malloc(size);
+ if (dest) {
+ create_usage(dest);
+ __u_boot_cmd_bmode.usage = dest;
+ }
+}
#if defined(CONFIG_DISPLAY_CPUINFO)
-static char *get_imx_type(u32 imxtype)
+static const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
case 0x63:
case 0x53:
return "53";
default:
- return "unknown";
+ return "??";
}
}
return rc;
}
+#ifdef CONFIG_FSL_ESDHC
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(bd_t *bis)
{
-#ifdef CONFIG_FSL_ESDHC
return fsl_esdhc_mmc_init(bis);
-#else
- return 0;
-#endif
}
+#endif
void reset_cpu(ulong addr)
{
static inline unsigned long long us_to_tick(unsigned long long usec)
{
- usec *= CLK_32KHZ;
+ usec = usec * CLK_32KHZ + 999999;
do_div(usec, 1000000);
return usec;
--- /dev/null
+/*
+ * A lowlevel_init function that sets up the stack to call a C function to
+ * perform further init.
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+ /*
+ * Setup a temporary stack
+ */
+ ldr sp, =CONFIG_SYS_INIT_SP_ADDR
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+
+ /*
+ * Save the old lr(passed in ip) and the current lr to stack
+ */
+ push {ip, lr}
+
+ /*
+ * go setup pll, mux, memory
+ */
+ bl s_init
+ pop {ip, pc}
+ENDPROC(lowlevel_init)
/* reconfigure L2 cache aux control reg */
mov r0, #0xC0 /* tag RAM */
add r0, r0, #0x4 /* data RAM */
- orr r0, r0, #(1 << 24) /* disable write allocate delay */
- orr r0, r0, #(1 << 23) /* disable write allocate combine */
- orr r0, r0, #(1 << 22) /* disable write allocate */
+ orr r0, r0, #1 << 24 /* disable write allocate delay */
+ orr r0, r0, #1 << 23 /* disable write allocate combine */
+ orr r0, r0, #1 << 22 /* disable write allocate */
#if defined(CONFIG_MX51)
ldr r1, =0x0
cmp r3, #0x10
/* disable write combine for TO 2 and lower revs */
- orrls r0, r0, #(1 << 25)
+ orrls r0, r0, #1 << 25
#endif
mcr 15, 1, r0, c9, c0, 2
movhi r1, #0
#else
mov r1, #0
-
#endif
str r1, [r0, #CLKCTL_CACRR]
+
/* Switch ARM back to PLL 1 */
mov r1, #0
str r1, [r0, #CLKCTL_CCSR]
/* Switch peripheral to PLL2 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00808145
- orr r1, r1, #(2 << 10)
- orr r1, r1, #(0 << 16)
- orr r1, r1, #(1 << 19)
+ orr r1, r1, #2 << 10
+ orr r1, r1, #0 << 16
+ orr r1, r1, #1 << 19
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x00016154
#if defined(CONFIG_MX51)
ldr r0, =GPIO1_BASE_ADDR
ldr r1, [r0, #0x0]
- orr r1, r1, #(1 << 23)
+ orr r1, r1, #1 << 23
str r1, [r0, #0x0]
ldr r1, [r0, #0x4]
- orr r1, r1, #(1 << 23)
+ orr r1, r1, #1 << 23
str r1, [r0, #0x4]
#endif
ENDPROC(lowlevel_init)
/* Board level setting value */
-W_DP_OP_864: .word DP_OP_864
-W_DP_MFD_864: .word DP_MFD_864
-W_DP_MFN_864: .word DP_MFN_864
-W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
-W_DP_OP_800: .word DP_OP_800
-W_DP_MFD_800: .word DP_MFD_800
-W_DP_MFN_800: .word DP_MFN_800
-W_DP_OP_665: .word DP_OP_665
-W_DP_MFD_665: .word DP_MFD_665
-W_DP_MFN_665: .word DP_MFN_665
-W_DP_OP_216: .word DP_OP_216
-W_DP_MFD_216: .word DP_MFD_216
-W_DP_MFN_216: .word DP_MFN_216
+W_DP_OP_864: .word DP_OP_864
+W_DP_MFD_864: .word DP_MFD_864
+W_DP_MFN_864: .word DP_MFN_864
+W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
+W_DP_OP_800: .word DP_OP_800
+W_DP_MFD_800: .word DP_MFD_800
+W_DP_MFN_800: .word DP_MFN_800
+W_DP_OP_665: .word DP_OP_665
+W_DP_MFD_665: .word DP_MFD_665
+W_DP_MFN_665: .word DP_MFN_665
+W_DP_OP_216: .word DP_OP_216
+W_DP_MFD_216: .word DP_MFD_216
+W_DP_MFN_216: .word DP_MFN_216
#include <asm/errno.h>
#include <asm/io.h>
+#include <asm/imx-common/boot_mode.h>
#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
#error "CPU_TYPE not defined"
return system_rev;
}
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
+
#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
writel(reg, &iomuxc_regs->gpr1);
}
+
+#ifdef CONFIG_MX53
+void boot_mode_apply(unsigned cfg_val)
+{
+ writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
+}
+/*
+ * cfg_val will be used for
+ * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
+ *
+ * If bit 28 of LPGR is set upon watchdog reset,
+ * bits[25:0] of LPGR will move to SBMR.
+ */
+const struct boot_mode soc_boot_modes[] = {
+ {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
+ /* usb or serial download */
+ {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
+ {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
+ {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
+ {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
+ {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
+ {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
+ /* 4 bit bus width */
+ {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
+ {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
+ {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
+ {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
+ {NULL, 0},
+};
+#endif
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/boot_mode.h>
u32 get_cpu_rev(void)
{
}
#endif
+
+void boot_mode_apply(unsigned cfg_val)
+{
+ unsigned reg;
+ struct src_regs *psrc = (struct src_regs *)SRC_BASE_ADDR;
+ writel(cfg_val, &psrc->gpr9);
+ reg = readl(&psrc->gpr10);
+ if (cfg_val)
+ reg |= 1 << 28;
+ else
+ reg &= ~(1 << 28);
+ writel(reg, &psrc->gpr10);
+}
+/*
+ * cfg_val will be used for
+ * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
+ * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
+ * to SBMR1, which will determine the boot device.
+ */
+const struct boot_mode soc_boot_modes[] = {
+ {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
+ /* reserved value should start rom usb */
+ {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
+ {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
+ {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
+ {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
+ {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
+ {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
+ /* 4 bit bus width */
+ {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+ {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
COBJS := timer.o
COBJS += utils.o
-ifdef CONFIG_OMAP
-COBJS += gpio.o
-endif
ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
COBJS += hwinit-common.o
bx lr
ENDPROC(save_boot_params)
-ENTRY(lowlevel_init)
- /*
- * Setup a temporary stack
- */
- ldr sp, =LOW_LEVEL_SRAM_STACK
-
- /*
- * Save the old lr(passed in ip) and the current lr to stack
- */
- push {ip, lr}
-
- /*
- * go setup pll, mux, memory
- */
- bl s_init
- pop {ip, pc}
-ENDPROC(lowlevel_init)
-
ENTRY(set_pl310_ctrl_reg)
PUSH {r4-r11, lr} @ save registers - ROM code may pollute
@ our registers
timer_rate_hz = get_pwm_clk() / ((prescaler + 1) *
(div + 1));
- timer_rate_hz = timer_rate_hz / 100;
+ timer_rate_hz = timer_rate_hz / CONFIG_SYS_HZ;
/* set count value */
offset = pwm_id * 3;
DECLARE_GLOBAL_DATA_PTR;
+unsigned long get_current_tick(void);
+
/* macro to read the 16 bit timer */
static inline struct s5p_timer *s5p_get_base_timer(void)
{
pwm_config(4, 0, 0);
pwm_enable(4);
+ reset_timer_masked();
+
return 0;
}
* 3. finish normalize.
*/
tmo = usec / 1000;
- tmo *= (CONFIG_SYS_HZ * count_value / 10);
+ tmo *= (CONFIG_SYS_HZ * count_value);
tmo /= 1000;
} else {
/* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CONFIG_SYS_HZ * count_value / 10;
+ tmo = usec * CONFIG_SYS_HZ * count_value;
tmo /= (1000 * 1000);
}
/* get current timestamp */
- tmp = get_timer(0);
+ tmp = get_current_tick();
/* if setting this fordward will roll time stamp */
/* reset "advancing" timestamp to 0, set lastinc value */
tmo += tmp;
/* loop till event */
- while (get_timer_masked() < tmo)
+ while (get_current_tick() < tmo)
; /* nop */
}
}
unsigned long get_timer_masked(void)
+{
+ struct s5p_timer *const timer = s5p_get_base_timer();
+ unsigned long count_value = readl(&timer->tcntb4);
+
+ return get_current_tick() / count_value;
+}
+
+unsigned long get_current_tick(void)
{
struct s5p_timer *const timer = s5p_get_base_timer();
unsigned long now = readl(&timer->tcnto4);
orr r0, r0, #0xd3
msr cpsr,r0
-#if !defined(CONFIG_TEGRA2)
/*
* Setup vector:
* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
ldr r0, =_start
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif
-#endif /* !Tegra2 */
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*
* Move vector table
*/
-#if !defined(CONFIG_TEGRA2)
+#if !defined(CONFIG_TEGRA20)
#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
/* Set vector address in CP15 VBAR register */
ldr r0, =_start
add r0, r0, r9
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif
-#endif /* !Tegra2 */
+#endif /* !Tegra20 */
ldr r0, _board_init_r_ofs
adr r1, _start
.word board_init_r - _start
ENDPROC(relocate_code)
+/*************************************************************************
+ *
+ * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
+ * __attribute__((weak));
+ *
+ * Stack pointer is not yet initialized at this moment
+ * Don't save anything to stack even if compiled with -O0
+ *
+ *************************************************************************/
+ENTRY(save_boot_params)
+ bx lr @ back to my caller
+ENDPROC(save_boot_params)
+ .weak save_boot_params
+
/*************************************************************************
*
* cpu_init_cp15
# MA 02111-1307 USA
#
-# The AVP is ARMv4T architecture so we must use special compiler
-# flags for any startup files it might use.
-CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t
-CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t
-CFLAGS_arch/arm/cpu/armv7/tegra2/warmboot_avp.o += -march=armv4t
-
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
-SOBJS := lowlevel_init.o
-COBJS-y := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
-COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
-COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
-COBJS-$(CONFIG_TEGRA2_LP0) += crypto.o warmboot.o warmboot_avp.o
COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
COBJS := $(COBJS-y)
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
all: $(obj).depend $(LIB)
*/
#include <common.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <asm/arch/pmc.h>
static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
puts("Entering RCM...\n");
udelay(50000);
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-
-# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build these
-# files with compatible flags
-ifdef CONFIG_TEGRA2
-CFLAGS_arch/arm/lib/board.o += -march=armv4t
-CFLAGS_arch/arm/lib/memset.o += -march=armv4t
-CFLAGS_lib/string.o += -march=armv4t
-CFLAGS_common/cmd_nvedit.o += -march=armv4t
-endif
-
-USE_PRIVATE_LIBGCC = yes
-
CONFIG_ARCH_DEVICE_TREE := tegra20
#include <common.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
LIB = $(obj)lib$(SOC).o
-COBJS = timer.o clock.o
+COBJS = timer.o clock.o prcmu.o cpu.o
SOBJS = lowlevel.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
if (cluster != -1)
writel(1 << cluster, &clkrst->pcken);
}
+
+void db8500_clocks_init(void)
+{
+ /*
+ * Enable all clocks. This is u-boot, we can enable it all. There is no
+ * powersave in u-boot.
+ */
+
+ u8500_clock_enable(1, 9, -1); /* GPIO0 */
+ u8500_clock_enable(2, 11, -1);/* GPIO1 */
+ u8500_clock_enable(3, 8, -1); /* GPIO2 */
+ u8500_clock_enable(5, 1, -1); /* GPIO3 */
+ u8500_clock_enable(3, 6, 6); /* UART2 */
+ u8500_clock_enable(3, 3, 3); /* I2C0 */
+ u8500_clock_enable(1, 5, 5); /* SDI0 */
+ u8500_clock_enable(2, 4, 2); /* SDI4 */
+ u8500_clock_enable(6, 6, -1); /* MTU0 */
+ u8500_clock_enable(3, 4, 4); /* SDI2 */
+
+ /*
+ * Enabling clocks for all devices which are AMBA devices in the
+ * kernel. Otherwise they will not get probe()'d because the
+ * peripheral ID register will not be powered.
+ */
+
+ /* XXX: some of these differ between ED/V1 */
+
+ u8500_clock_enable(1, 1, 1); /* UART1 */
+ u8500_clock_enable(1, 0, 0); /* UART0 */
+ u8500_clock_enable(3, 2, 2); /* SSP1 */
+ u8500_clock_enable(3, 1, 1); /* SSP0 */
+ u8500_clock_enable(2, 8, -1); /* SPI0 */
+ u8500_clock_enable(2, 5, 3); /* MSP2 */
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Linaro Limited
+ * Mathieu Poirier <mathieu.poirier@linaro.org>
+ *
+ * Based on original code from Joakim Axelsson at ST-Ericsson
+ * (C) Copyright 2010 ST-Ericsson
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/prcmu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+
+#include <asm/arch/hardware.h>
+
+#define CPUID_DB8500V1 0x411fc091
+#define CPUID_DB8500V2 0x412fc091
+#define ASICID_DB8500V11 0x008500A1
+
+#define CACHE_CONTR_BASE 0xA0412000
+/* Cache controller register offsets
+ * as found in ARM's technical reference manual
+ */
+#define CACHE_INVAL_BY_WAY (CACHE_CONTR_BASE + 0x77C)
+#define CACHE_LOCKDOWN_BY_D (CACHE_CONTR_BASE + 0X900)
+#define CACHE_LOCKDOWN_BY_I (CACHE_CONTR_BASE + 0X904)
+
+static unsigned int read_asicid(void);
+
+static inline unsigned int read_cpuid(void)
+{
+ unsigned int val;
+
+ /* Main ID register (MIDR) */
+ asm("mrc p15, 0, %0, c0, c0, 0"
+ : "=r" (val)
+ :
+ : "cc");
+
+ return val;
+}
+
+static int cpu_is_u8500v11(void)
+{
+ return read_asicid() == ASICID_DB8500V11;
+}
+
+static int cpu_is_u8500v2(void)
+{
+ return read_cpuid() == CPUID_DB8500V2;
+}
+
+static unsigned int read_asicid(void)
+{
+ unsigned int *address;
+
+ if (cpu_is_u8500v2())
+ address = (void *) U8500_ASIC_ID_LOC_V2;
+ else
+ address = (void *) U8500_ASIC_ID_LOC_ED_V1;
+
+ return readl(address);
+}
+
+void cpu_cache_initialization(void)
+{
+ unsigned int value;
+ /* invalidate all cache entries */
+ writel(0xFFFF, CACHE_INVAL_BY_WAY);
+
+ /* ways are set to '0' when they are totally
+ * cleaned and invalidated
+ */
+ do {
+ value = readl(CACHE_INVAL_BY_WAY);
+ } while (value & 0xFF);
+
+ /* Invalidate register 9 D and I lockdown */
+ writel(0xFF, CACHE_LOCKDOWN_BY_D);
+ writel(0xFF, CACHE_LOCKDOWN_BY_I);
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+/*
+ * SOC specific cpu init
+ */
+int arch_cpu_init(void)
+{
+ db8500_prcmu_init();
+ db8500_clocks_init();
+
+ return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+#ifdef CONFIG_MMC
+
+int u8500_mmc_power_init(void)
+{
+ int ret;
+ int enable, voltage;
+ int ab8500_revision;
+
+ if (!cpu_is_u8500v11() && !cpu_is_u8500v2())
+ return 0;
+
+ /* Get AB8500 revision */
+ ret = ab8500_read(AB8500_MISC, AB8500_REV_REG);
+ if (ret < 0)
+ goto out;
+
+ ab8500_revision = ret;
+
+ /*
+ * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD
+ * card to work. This is done by enabling the regulators in the AB8500
+ * via PRCMU I2C transactions.
+ *
+ * This code is derived from the handling of AB8500_LDO_VAUX3 in
+ * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux.
+ *
+ * Turn off and delay is required to have it work across soft reboots.
+ */
+
+ /* Turn off (read-modify-write) */
+ ret = ab8500_read(AB8500_REGU_CTRL2,
+ AB8500_REGU_VRF1VAUX3_REGU_REG);
+ if (ret < 0)
+ goto out;
+
+ enable = ret;
+
+ /* Turn off */
+ ret = ab8500_write(AB8500_REGU_CTRL2,
+ AB8500_REGU_VRF1VAUX3_REGU_REG,
+ enable & ~LDO_VAUX3_ENABLE_MASK);
+ if (ret < 0)
+ goto out;
+
+ udelay(10 * 1000);
+
+ /* Set the voltage to 2.91 V or 2.9 V without overriding VRF1 value */
+ ret = ab8500_read(AB8500_REGU_CTRL2,
+ AB8500_REGU_VRF1VAUX3_SEL_REG);
+ if (ret < 0)
+ goto out;
+
+ voltage = ret;
+
+ if (ab8500_revision < 0x20) {
+ voltage &= ~LDO_VAUX3_SEL_MASK;
+ voltage |= LDO_VAUX3_SEL_2V9;
+ } else {
+ voltage &= ~LDO_VAUX3_V2_SEL_MASK;
+ voltage |= LDO_VAUX3_V2_SEL_2V91;
+ }
+
+ ret = ab8500_write(AB8500_REGU_CTRL2,
+ AB8500_REGU_VRF1VAUX3_SEL_REG, voltage);
+ if (ret < 0)
+ goto out;
+
+ /* Turn on the supply */
+ enable &= ~LDO_VAUX3_ENABLE_MASK;
+ enable |= LDO_VAUX3_ENABLE_VAL;
+
+ ret = ab8500_write(AB8500_REGU_CTRL2,
+ AB8500_REGU_VRF1VAUX3_REGU_REG, enable);
+
+out:
+ return ret;
+}
+#endif /* CONFIG_MMC */
#include <asm/types.h>
#include <asm/io.h>
#include <asm/errno.h>
-
-#include "prcmu-fw.h"
+#include <asm/arch/prcmu.h>
/* CPU mailbox registers */
-#define PRCM_MBOX_CPU_VAL (U8500_PRCMU_BASE + 0x0fc)
-#define PRCM_MBOX_CPU_SET (U8500_PRCMU_BASE + 0x100)
-#define PRCM_MBOX_CPU_CLR (U8500_PRCMU_BASE + 0x104)
+#define PRCMU_I2C_WRITE(slave) \
+ (((slave) << 1) | I2CWRITE | (1 << 6))
+#define PRCMU_I2C_READ(slave) \
+ (((slave) << 1) | I2CREAD | (1 << 6))
+
+#define I2C_MBOX_BIT (1 << 5)
static int prcmu_is_ready(void)
{
return ready;
}
-static int _wait_for_req_complete(int num)
+static int wait_for_i2c_mbx_rdy(void)
{
- int timeout = 1000;
+ int timeout = 10000;
- /* checking any already on-going transaction */
- while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--)
- ;
+ if (readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) {
+ printf("prcmu: warning i2c mailbox was not acked\n");
+ /* clear mailbox 5 ack irq */
+ writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
+ }
- timeout = 1000;
+ /* check any already on-going transaction */
+ while ((readl(PRCM_MBOX_CPU_VAL) & I2C_MBOX_BIT) && timeout)
+ timeout--;
+
+ if (timeout == 0)
+ return -1;
+
+ return 0;
+}
+
+static int wait_for_i2c_req_done(void)
+{
+ int timeout = 10000;
/* Set an interrupt to XP70 */
- writel(1 << num, PRCM_MBOX_CPU_SET);
+ writel(I2C_MBOX_BIT, PRCM_MBOX_CPU_SET);
- while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--)
- ;
+ /* wait for mailbox 5 (i2c) ack */
+ while (!(readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) && timeout)
+ timeout--;
- if (!timeout) {
- printf("PRCMU operation timed out\n");
+ if (timeout == 0)
return -1;
- }
return 0;
}
{
uint8_t i2c_status;
uint8_t i2c_val;
+ int ret;
if (!prcmu_is_ready())
return -1;
debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n",
reg, slave);
+ ret = wait_for_i2c_mbx_rdy();
+ if (ret) {
+ printf("prcmu_i2c_read: mailbox became not ready\n");
+ return ret;
+ }
+
/* prepare the data for mailbox 5 */
- writeb((reg << 1) | I2CREAD, PRCM_REQ_MB5_I2COPTYPE_REG);
+ writeb(PRCMU_I2C_READ(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
writeb(0, PRCM_REQ_MB5_I2CVAL);
- _wait_for_req_complete(REQ_MB5);
+ ret = wait_for_i2c_req_done();
+ if (ret) {
+ printf("prcmu_i2c_read: mailbox request timed out\n");
+ return ret;
+ }
/* retrieve values */
debug("ack-mb5:transfer status = %x\n",
i2c_status = readb(PRCM_ACK_MB5_STATUS);
i2c_val = readb(PRCM_ACK_MB5_VAL);
+ /* clear mailbox 5 ack irq */
+ writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
if (i2c_status == I2C_RD_OK)
return i2c_val;
- else {
-
- printf("prcmu_i2c_read:read return status= %d\n",
- i2c_status);
- return -1;
- }
+ printf("prcmu_i2c_read:read return status= %d\n", i2c_status);
+ return -1;
}
/**
int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data)
{
uint8_t i2c_status;
+ int ret;
if (!prcmu_is_ready())
return -1;
debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n",
reg, slave);
+ ret = wait_for_i2c_mbx_rdy();
+ if (ret) {
+ printf("prcmu_i2c_write: mailbox became not ready\n");
+ return ret;
+ }
+
/* prepare the data for mailbox 5 */
- writeb((reg << 1) | I2CWRITE, PRCM_REQ_MB5_I2COPTYPE_REG);
+ writeb(PRCMU_I2C_WRITE(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
writeb(reg_data, PRCM_REQ_MB5_I2CVAL);
- debug("\ncpu_is_u8500v11\n");
- _wait_for_req_complete(REQ_MB5);
+ ret = wait_for_i2c_req_done();
+ if (ret) {
+ printf("prcmu_i2c_write: mailbox request timed out\n");
+ return ret;
+ }
/* retrieve values */
debug("ack-mb5:transfer status = %x\n",
i2c_status = readb(PRCM_ACK_MB5_STATUS);
debug("\ni2c_status = %x\n", i2c_status);
+ /* clear mailbox 5 ack irq */
+ writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
+
if (i2c_status == I2C_WR_OK)
return 0;
- else {
- printf("ape-i2c: i2c_status : 0x%x\n", i2c_status);
- return -1;
- }
+
+ printf("%s: i2c_status : 0x%x\n", __func__, i2c_status);
+ return -1;
+}
+
+void u8500_prcmu_enable(u32 *reg)
+{
+ writel(readl(reg) | (1 << 8), reg);
+}
+
+void db8500_prcmu_init(void)
+{
+ /* Enable timers */
+ writel(1 << 17, PRCM_TCR);
+
+ u8500_prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG);
+ u8500_prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG);
+ u8500_prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG);
+ /* PER4CLK does not exist */
+ u8500_prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG);
+ u8500_prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG);
+ /* Only exists in ED but is always ok to write to */
+ u8500_prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG);
+
+ u8500_prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG);
+ u8500_prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG);
+
+ u8500_prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG);
+
+ /* Clean up the mailbox interrupts after pre-u-boot code. */
+ writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
}
--- /dev/null
+#
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# The AVP is ARMv4T architecture so we must use special compiler
+# flags for any startup files it might use.
+CFLAGS_arch/arm/cpu/tegra20-common/warmboot_avp.o += -march=armv4t
+
+LIB = $(obj)lib$(SOC)-common.o
+
+SOBJS += lowlevel_init.o
+COBJS-y += ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
+COBJS-$(CONFIG_TEGRA20_LP0) += warmboot.o crypto.o warmboot_avp.o
+COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
+COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+* (C) Copyright 2010-2011
+* NVIDIA Corporation <www.nvidia.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+#include <asm/io.h>
+#include <asm/arch/ap20.h>
+#include <asm/arch/fuse.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pmc.h>
+#include <asm/arch/scu.h>
+#include <asm/arch/warmboot.h>
+#include <common.h>
+
+int tegra_get_chip_type(void)
+{
+ struct apb_misc_gp_ctlr *gp;
+ struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+ uint tegra_sku_id, rev;
+
+ /*
+ * This is undocumented, Chip ID is bits 15:8 of the register
+ * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
+ * Tegra30
+ */
+ gp = (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+ rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
+
+ tegra_sku_id = readl(&fuse->sku_info) & 0xff;
+
+ switch (rev) {
+ case CHIPID_TEGRA20:
+ switch (tegra_sku_id) {
+ case SKU_ID_T20:
+ return TEGRA_SOC_T20;
+ case SKU_ID_T25SE:
+ case SKU_ID_AP25:
+ case SKU_ID_T25:
+ case SKU_ID_AP25E:
+ case SKU_ID_T25E:
+ return TEGRA_SOC_T25;
+ }
+ break;
+ }
+ /* unknown sku id */
+ return TEGRA_SOC_UNKNOWN;
+}
+
+static void enable_scu(void)
+{
+ struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
+ u32 reg;
+
+ /* If SCU already setup/enabled, return */
+ if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
+ return;
+
+ /* Invalidate all ways for all processors */
+ writel(0xFFFF, &scu->scu_inv_all);
+
+ /* Enable SCU - bit 0 */
+ reg = readl(&scu->scu_ctrl);
+ reg |= SCU_CTRL_ENABLE;
+ writel(reg, &scu->scu_ctrl);
+}
+
+static u32 get_odmdata(void)
+{
+ /*
+ * ODMDATA is stored in the BCT in IRAM by the BootROM.
+ * The BCT start and size are stored in the BIT in IRAM.
+ * Read the data @ bct_start + (bct_size - 12). This works
+ * on T20 and T30 BCTs, which are locked down. If this changes
+ * in new chips (T114, etc.), we can revisit this algorithm.
+ */
+
+ u32 bct_start, odmdata;
+
+ bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
+ odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
+
+ return odmdata;
+}
+
+static void init_pmc_scratch(void)
+{
+ struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ u32 odmdata;
+ int i;
+
+ /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
+ for (i = 0; i < 23; i++)
+ writel(0, &pmc->pmc_scratch1+i);
+
+ /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
+ odmdata = get_odmdata();
+ writel(odmdata, &pmc->pmc_scratch20);
+}
+
+void s_init(void)
+{
+ /* Init PMC scratch memory */
+ init_pmc_scratch();
+
+ enable_scu();
+
+ /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
+ asm volatile(
+ "mrc p15, 0, r0, c1, c0, 1\n"
+ "orr r0, r0, #0x41\n"
+ "mcr p15, 0, r0, c1, c0, 1\n");
+
+ /* FIXME: should have ap20's L2 disabled too? */
+}
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/ap20.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pmc.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
+#include <asm/arch/warmboot.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned int query_sdram_size(void)
{
- struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+ struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
u32 reg;
reg = readl(&pmc->pmc_scratch20);
}
#endif /* CONFIG_DISPLAY_BOARDINFO */
-#ifdef CONFIG_ARCH_CPU_INIT
-/*
- * Note this function is executed by the ARM7TDMI AVP. It does not return
- * in this case. It is also called once the A9 starts up, but does nothing in
- * that case.
- */
-int arch_cpu_init(void)
-{
- /* Fire up the Cortex A9 */
- tegra2_start();
-
- /* We didn't do this init in start.S, so do it now */
- cpu_init_cp15();
-
- /* Initialize essential common plls */
- clock_early_init();
-
- return 0;
-}
-#endif
-
static int uart_configs[] = {
-#if defined(CONFIG_TEGRA2_UARTA_UAA_UAB)
+#if defined(CONFIG_TEGRA20_UARTA_UAA_UAB)
FUNCMUX_UART1_UAA_UAB,
-#elif defined(CONFIG_TEGRA2_UARTA_GPU)
+#elif defined(CONFIG_TEGRA20_UARTA_GPU)
FUNCMUX_UART1_GPU,
-#elif defined(CONFIG_TEGRA2_UARTA_SDIO1)
+#elif defined(CONFIG_TEGRA20_UARTA_SDIO1)
FUNCMUX_UART1_SDIO1,
#else
FUNCMUX_UART1_IRRX_IRTX,
{
int uart_ids = 0; /* bit mask of which UART ids to enable */
-#ifdef CONFIG_TEGRA2_ENABLE_UARTA
+#ifdef CONFIG_TEGRA20_ENABLE_UARTA
uart_ids |= UARTA;
#endif
-#ifdef CONFIG_TEGRA2_ENABLE_UARTB
+#ifdef CONFIG_TEGRA20_ENABLE_UARTB
uart_ids |= UARTB;
#endif
-#ifdef CONFIG_TEGRA2_ENABLE_UARTD
+#ifdef CONFIG_TEGRA20_ENABLE_UARTD
uart_ids |= UARTD;
#endif
setup_uarts(uart_ids);
* MA 02111-1307 USA
*/
-/* Tegra2 Clock control functions */
+/* Tegra20 Clock control functions */
#include <asm/io.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/timer.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <common.h>
#include <div64.h>
#include <fdtdec.h>
};
/*
- * Clock types that we can use as a source. The Tegra2 has muxes for the
+ * Clock types that we can use as a source. The Tegra20 has muxes for the
* peripheral clocks, and in most cases there are four options for the clock
* source. This gives us a clock 'type' and exploits what commonality exists
* in the device.
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 mask;
- /* Form the mask, which depends on the cpu chosen. Tegra2 has 2 */
+ /* Form the mask, which depends on the cpu chosen. Tegra20 has 2 */
assert(cpu >= 0 && cpu < 2);
mask = which << cpu;
* the same but we are very cautious so we check that a valid clock ID is
* provided.
*
- * @param clk_id Clock ID according to tegra2 device tree binding
+ * @param clk_id Clock ID according to tegra20 device tree binding
* @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
*/
static enum periph_id clk_id_to_periph_id(int clk_id)
#include <asm/arch/apb_misc.h>
#include <asm/arch/clock.h>
#include <asm/arch/emc.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
/*
* The EMC registers have shadow registers. When the EMC clock is updated
* MA 02111-1307 USA
*/
-/* Tegra2 high-level function multiplexing */
+/* Tegra20 high-level function multiplexing */
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
* MA 02111-1307 USA
*/
-/* Tegra2 pin multiplexing functions */
+/* Tegra20 pin multiplexing functions */
#include <asm/io.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <asm/arch/pinmux.h>
#include <common.h>
#include <tps6586x.h>
#include <asm/io.h>
#include <asm/arch/ap20.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <asm/arch/tegra_i2c.h>
#include <asm/arch/sys_proto.h>
/* Print CPU information */
int print_cpuinfo(void)
{
- puts("TEGRA2\n");
+ puts("TEGRA20\n");
/* TBD: Add printf of major/minor rev info, stepping, etc. */
return 0;
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <asm/arch/timer.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/clock.h>
#include <asm/arch/pmc.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <asm/arch/fuse.h>
#include <asm/arch/emc.h>
#include <asm/arch/gp_padctrl.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_TEGRA_CLOCK_SCALING
-#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA2_LP0"
+#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA20_LP0"
#endif
/*
u32 ram_code;
struct sdram_params sdram;
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE;
+ (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
union scratch2_reg scratch2;
union scratch4_reg scratch4;
{
u32 major_id;
struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE;
+ (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
HIDREV_MAJORPREV_SHIFT;
static int ap20_is_odm_production_mode(void)
{
- struct fuse_regs *fuse = (struct fuse_regs *)TEGRA2_FUSE_BASE;
+ struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
if (!is_failure_analysis_mode(fuse) &&
is_odm_production_mode_fuse_set(fuse))
static int ap20_is_production_mode(void)
{
- struct fuse_regs *fuse = (struct fuse_regs *)TEGRA2_FUSE_BASE;
+ struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
if (get_major_version() == 0)
return 1;
{
u32 chip_id;
struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE;
+ (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
HIDREV_CHIPID_SHIFT;
- if (chip_id == CHIPID_TEGRA2) {
+ if (chip_id == CHIPID_TEGRA20) {
if (ap20_is_odm_production_mode()) {
printf("!! odm_production_mode is not supported !!\n");
return MODE_UNDEFINED;
#include <asm/arch/flow.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/pmc.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <asm/arch/warmboot.h>
#include "warmboot_avp.h"
void wb_start(void)
{
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+++ /dev/null
-/*
- * common_def.h
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __COMMON_DEF_H__
-#define __COMMON_DEF_H__
-
-extern void enable_uart0_pin_mux(void);
-extern void enable_mmc0_pin_mux(void);
-extern void enable_i2c0_pin_mux(void);
-
-#endif/*__COMMON_DEF_H__ */
struct ctrl_stat {
unsigned int resv1[16];
unsigned int statusreg; /* ofset 0x40 */
+ unsigned int resv2[51];
+ unsigned int secure_emif_sdram_config; /* offset 0x0110 */
+};
+
+/* AM33XX GPIO registers */
+#define OMAP_GPIO_REVISION 0x0000
+#define OMAP_GPIO_SYSCONFIG 0x0010
+#define OMAP_GPIO_SYSSTATUS 0x0114
+#define OMAP_GPIO_IRQSTATUS1 0x002c
+#define OMAP_GPIO_IRQSTATUS2 0x0030
+#define OMAP_GPIO_CTRL 0x0130
+#define OMAP_GPIO_OE 0x0134
+#define OMAP_GPIO_DATAIN 0x0138
+#define OMAP_GPIO_DATAOUT 0x013c
+#define OMAP_GPIO_LEVELDETECT0 0x0140
+#define OMAP_GPIO_LEVELDETECT1 0x0144
+#define OMAP_GPIO_RISINGDETECT 0x0148
+#define OMAP_GPIO_FALLINGDETECT 0x014c
+#define OMAP_GPIO_DEBOUNCE_EN 0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL 0x0154
+#define OMAP_GPIO_CLEARDATAOUT 0x0190
+#define OMAP_GPIO_SETDATAOUT 0x0194
+
+/* Control Device Register */
+struct ctrl_dev {
+ unsigned int deviceid; /* offset 0x00 */
+ unsigned int resv1[11];
+ unsigned int macid0l; /* offset 0x30 */
+ unsigned int macid0h; /* offset 0x34 */
+ unsigned int macid1l; /* offset 0x38 */
+ unsigned int macid1h; /* offset 0x3c */
+ unsigned int resv2[4];
+ unsigned int miisel; /* offset 0x50 */
};
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
#define _DDR_DEFS_H
#include <asm/arch/hardware.h>
+#include <asm/emif.h>
/* AM335X EMIF Register values */
-#define EMIF_SDMGT 0x80000000
-#define EMIF_SDRAM 0x00004650
-#define EMIF_PHYCFG 0x2
-#define DDR_PHY_RESET (0x1 << 10)
-#define DDR_FUNCTIONAL_MODE_EN 0x1
-#define DDR_PHY_READY (0x1 << 2)
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
-#define VTP_CTRL_LOCK_EN (0x1 << 4)
#define VTP_CTRL_START_EN (0x1)
-#define DDR2_RATIO 0x80
-#define CMD_FORCE 0x00
-#define CMD_DELAY 0x00
-
-#define EMIF_READ_LATENCY 0x05
-#define EMIF_TIM1 0x0666B3D6
-#define EMIF_TIM2 0x143731DA
-#define EMIF_TIM3 0x00000347
-#define EMIF_SDCFG 0x43805332
-#define EMIF_SDREF 0x0000081a
+#define PHY_DLL_LOCK_DIFF 0x0
+#define DDR_CKE_CTRL_NORMAL 0x1
+
+#define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */
+#define DDR2_EMIF_TIM1 0x0666B3C9
+#define DDR2_EMIF_TIM2 0x243631CA
+#define DDR2_EMIF_TIM3 0x0000033F
+#define DDR2_EMIF_SDCFG 0x41805332
+#define DDR2_EMIF_SDREF 0x0000081a
#define DDR2_DLL_LOCK_DIFF 0x0
-#define DDR2_RD_DQS 0x12
-#define DDR2_PHY_FIFO_WE 0x80
-
+#define DDR2_RATIO 0x80
#define DDR2_INVERT_CLKOUT 0x00
+#define DDR2_RD_DQS 0x12
#define DDR2_WR_DQS 0x00
#define DDR2_PHY_WRLVL 0x00
#define DDR2_PHY_GATELVL 0x00
#define DDR2_PHY_WR_DATA 0x40
-#define PHY_RANK0_DELAY 0x01
-#define PHY_DLL_LOCK_DIFF 0x0
-#define DDR_IOCTRL_VALUE 0x18B
-
-/**
- * This structure represents the EMIF registers on AM33XX devices.
- */
-struct emif_regs {
- unsigned int sdrrev; /* offset 0x00 */
- unsigned int sdrstat; /* offset 0x04 */
- unsigned int sdrcr; /* offset 0x08 */
- unsigned int sdrcr2; /* offset 0x0C */
- unsigned int sdrrcr; /* offset 0x10 */
- unsigned int sdrrcsr; /* offset 0x14 */
- unsigned int sdrtim1; /* offset 0x18 */
- unsigned int sdrtim1sr; /* offset 0x1C */
- unsigned int sdrtim2; /* offset 0x20 */
- unsigned int sdrtim2sr; /* offset 0x24 */
- unsigned int sdrtim3; /* offset 0x28 */
- unsigned int sdrtim3sr; /* offset 0x2C */
- unsigned int res1[2];
- unsigned int sdrmcr; /* offset 0x38 */
- unsigned int sdrmcsr; /* offset 0x3C */
- unsigned int res2[8];
- unsigned int sdritr; /* offset 0x60 */
- unsigned int res3[32];
- unsigned int ddrphycr; /* offset 0xE4 */
- unsigned int ddrphycsr; /* offset 0xE8 */
- unsigned int ddrphycr2; /* offset 0xEC */
-};
-
-/**
- * Encapsulates DDR PHY control and corresponding shadow registers.
- */
-struct ddr_phy_control {
- unsigned long reg;
- unsigned long reg_sh;
- unsigned long reg2;
-};
-
-/**
- * Encapsulates SDRAM timing and corresponding shadow registers.
- */
-struct sdram_timing {
- unsigned long time1;
- unsigned long time1_sh;
- unsigned long time2;
- unsigned long time2_sh;
- unsigned long time3;
- unsigned long time3_sh;
-};
-
-/**
- * Encapsulates SDRAM configuration.
- * (Includes refresh control registers) */
-struct sdram_config {
- unsigned long sdrcr;
- unsigned long sdrcr2;
- unsigned long refresh;
- unsigned long refresh_sh;
-};
+#define DDR2_PHY_FIFO_WE 0x80
+#define DDR2_PHY_RANK0_DELAY 0x1
+#define DDR2_IOCTRL_VALUE 0x18B
+
+/* Micron MT41J128M16JT-125 */
+#define DDR3_EMIF_READ_LATENCY 0x06
+#define DDR3_EMIF_TIM1 0x0888A39B
+#define DDR3_EMIF_TIM2 0x26337FDA
+#define DDR3_EMIF_TIM3 0x501F830F
+#define DDR3_EMIF_SDCFG 0x61C04AB2
+#define DDR3_EMIF_SDREF 0x0000093B
+#define DDR3_ZQ_CFG 0x50074BE4
+#define DDR3_DLL_LOCK_DIFF 0x1
+#define DDR3_RATIO 0x40
+#define DDR3_INVERT_CLKOUT 0x1
+#define DDR3_RD_DQS 0x3B
+#define DDR3_WR_DQS 0x85
+#define DDR3_PHY_WR_DATA 0xC1
+#define DDR3_PHY_FIFO_WE 0x100
+#define DDR3_IOCTRL_VALUE 0x18B
/**
* Configure SDRAM
*/
-int config_sdram(struct sdram_config *cfg);
+void config_sdram(const struct emif_regs *regs);
/**
* Set SDRAM timings
*/
-int set_sdram_timings(struct sdram_timing *val);
+void set_sdram_timings(const struct emif_regs *regs);
/**
* Configure DDR PHY
*/
-int config_ddr_phy(struct ddr_phy_control *cfg);
+void config_ddr_phy(const struct emif_regs *regs);
/**
* This structure represents the DDR registers on AM33XX devices.
+ * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
+ * correspond to DATA1 registers defined here.
*/
struct ddr_regs {
unsigned int resv0[7];
unsigned int cm0csratio; /* offset 0x01C */
- unsigned int cm0csforce; /* offset 0x020 */
- unsigned int cm0csdelay; /* offset 0x024 */
+ unsigned int resv1[2];
unsigned int cm0dldiff; /* offset 0x028 */
unsigned int cm0iclkout; /* offset 0x02C */
- unsigned int resv1[8];
+ unsigned int resv2[8];
unsigned int cm1csratio; /* offset 0x050 */
- unsigned int cm1csforce; /* offset 0x054 */
- unsigned int cm1csdelay; /* offset 0x058 */
+ unsigned int resv3[2];
unsigned int cm1dldiff; /* offset 0x05C */
unsigned int cm1iclkout; /* offset 0x060 */
- unsigned int resv2[8];
+ unsigned int resv4[8];
unsigned int cm2csratio; /* offset 0x084 */
- unsigned int cm2csforce; /* offset 0x088 */
- unsigned int cm2csdelay; /* offset 0x08C */
+ unsigned int resv5[2];
unsigned int cm2dldiff; /* offset 0x090 */
unsigned int cm2iclkout; /* offset 0x094 */
- unsigned int resv3[12];
+ unsigned int resv6[12];
unsigned int dt0rdsratio0; /* offset 0x0C8 */
- unsigned int dt0rdsratio1; /* offset 0x0CC */
- unsigned int resv4[3];
+ unsigned int resv7[4];
unsigned int dt0wdsratio0; /* offset 0x0DC */
- unsigned int dt0wdsratio1; /* offset 0x0E0 */
- unsigned int resv5[3];
+ unsigned int resv8[4];
unsigned int dt0wiratio0; /* offset 0x0F0 */
- unsigned int dt0wiratio1; /* offset 0x0F4 */
+ unsigned int resv9;
+ unsigned int dt0wimode0; /* offset 0x0F8 */
unsigned int dt0giratio0; /* offset 0x0FC */
- unsigned int dt0giratio1; /* offset 0x100 */
- unsigned int resv6[1];
+ unsigned int resv10;
+ unsigned int dt0gimode0; /* offset 0x104 */
unsigned int dt0fwsratio0; /* offset 0x108 */
- unsigned int dt0fwsratio1; /* offset 0x10C */
- unsigned int resv7[4];
+ unsigned int resv11[4];
+ unsigned int dt0dqoffset; /* offset 0x11C */
unsigned int dt0wrsratio0; /* offset 0x120 */
- unsigned int dt0wrsratio1; /* offset 0x124 */
- unsigned int resv8[3];
+ unsigned int resv12[4];
unsigned int dt0rdelays0; /* offset 0x134 */
unsigned int dt0dldiff0; /* offset 0x138 */
- unsigned int resv9[39];
- unsigned int dt1rdelays0; /* offset 0x1D8 */
};
/**
*/
struct ddr_data {
unsigned long datardsratio0;
- unsigned long datardsratio1;
unsigned long datawdsratio0;
- unsigned long datawdsratio1;
unsigned long datawiratio0;
- unsigned long datawiratio1;
unsigned long datagiratio0;
- unsigned long datagiratio1;
unsigned long datafwsratio0;
- unsigned long datafwsratio1;
unsigned long datawrsratio0;
- unsigned long datawrsratio1;
+ unsigned long datauserank0delay;
unsigned long datadldiff0;
};
/**
* Configure DDR CMD control registers
*/
-int config_cmd_ctrl(struct cmd_control *cmd);
+void config_cmd_ctrl(const struct cmd_control *cmd);
/**
* Configure DDR DATA registers
*/
-int config_ddr_data(int data_macrono, struct ddr_data *data);
+void config_ddr_data(int data_macrono, const struct ddr_data *data);
/**
* This structure represents the DDR io control on AM33XX devices.
unsigned int dt1ioctl;
};
-/**
- * Encapsulates DDR CMD & DATA io control registers.
- */
-struct ddr_ioctrl {
- unsigned long cmd1ctl;
- unsigned long cmd2ctl;
- unsigned long cmd3ctl;
- unsigned long data1ctl;
- unsigned long data2ctl;
-};
-
/**
* Configure DDR io control registers
*/
-int config_io_ctrl(struct ddr_ioctrl *ioctrl);
+void config_io_ctrl(unsigned long val);
struct ddr_ctrl {
unsigned int ddrioctrl;
unsigned int ddrckectrl;
};
-void config_ddr(void);
+void config_ddr(short ddr_type);
#endif /* _DDR_DEFS_H */
--- /dev/null
+/*
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#ifndef _GPIO_AM33xx_H
+#define _GPIO_AM33xx_H
+
+#include <asm/omap_gpio.h>
+
+#define AM33XX_GPIO0_BASE 0x44E07000
+#define AM33XX_GPIO1_BASE 0x4804C000
+#define AM33XX_GPIO2_BASE 0x481AC000
+#define AM33XX_GPIO3_BASE 0x481AE000
+
+#endif /* _GPIO_AM33xx_H */
#ifndef __AM33XX_HARDWARE_H
#define __AM33XX_HARDWARE_H
+#include <asm/arch/omap.h>
+
/* Module base addresses */
-#define LOW_LEVEL_SRAM_STACK 0x4030B7FC
#define UART0_BASE 0x44E09000
/* DM Timer base addresses */
/* Control Module Base Address */
#define CTRL_BASE 0x44E10000
+#define CTRL_DEVICE_BASE 0x44E10600
/* PRCM Base Address */
#define PRCM_BASE 0x44E00000
/* EMIF Base address */
#define EMIF4_0_CFG_BASE 0x4C000000
#define EMIF4_1_CFG_BASE 0x4D000000
-#define DMM_BASE 0x4E000000
/* PLL related registers */
#define CM_PER 0x44E00000
#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
+/* CPSW Config space */
+#define AM335X_CPSW_BASE 0x4A100000
+#define AM335X_CPSW_MDIO_BASE 0x4A101000
+
#endif /* __AM33XX_HARDWARE_H */
* OMAP HSMMC register definitions
*/
#define OMAP_HSMMC1_BASE 0x48060100
-#define OMAP_HSMMC2_BASE 0x481D8000
-#define OMAP_HSMMC3_BASE 0x47C24000
+#define OMAP_HSMMC2_BASE 0x481D8100
typedef struct hsmmc {
unsigned char res1[0x10];
*/
#define NON_SECURE_SRAM_START 0x40304000
#define NON_SECURE_SRAM_END 0x4030E000
-#define LOW_LEVEL_SRAM_STACK 0x4030B7FC
/* ROM code defines */
/* Boot device */
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
+/*
+ * AM335x parts define a system EEPROM that defines certain sub-fields.
+ * We use these fields to in turn see what board we are on, and what
+ * that might require us to set or not set.
+ */
+#define HDR_NO_OF_MAC_ADDR 3
+#define HDR_ETH_ALEN 6
+#define HDR_NAME_LEN 8
+
+struct am335x_baseboard_id {
+ unsigned int magic;
+ char name[HDR_NAME_LEN];
+ char version[4];
+ char serial[12];
+ char config[32];
+ char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
+};
+
#define BOARD_REV_ID 0x0
u32 get_cpu_rev(void);
int print_cpuinfo(void);
#endif
+extern struct ctrl_stat *cstat;
u32 get_device_type(void);
void setup_clocks_for_console(void);
+void ddr_pll_config(unsigned int ddrpll_M);
+
+/*
+ * We have three pin mux functions that must exist. We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(struct am335x_baseboard_id *header);
#endif
#include <asm/arch/at91cap9_matrix.h>
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
#include <asm/arch/at91sam9g45_matrix.h>
+#elif defined(CONFIG_AT91SAM9X5)
+#include <asm/arch/at91sam9x5_matrix.h>
#else
#error "Unsupported AT91SAM9/CAP9 processor"
#endif
--- /dev/null
+/*
+ * Chip-specific header file for the AT91SAM9x5 family
+ *
+ * Copyright (C) 2012 Atmel Corporation.
+ *
+ * Definitions for the SoC:
+ * AT91SAM9x5
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __AT91SAM9X5_H__
+#define __AT91SAM9X5_H__
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS 1 /* System Controller Interrupt */
+#define ATMEL_ID_PIOAB 2 /* Parallel I/O Controller A and B */
+#define ATMEL_ID_PIOCD 3 /* Parallel I/O Controller C and D */
+#define ATMEL_ID_SMD 4 /* SMD Soft Modem (SMD) */
+#define ATMEL_ID_USART0 5 /* USART 0 */
+#define ATMEL_ID_USART1 6 /* USART 1 */
+#define ATMEL_ID_USART2 7 /* USART 2 */
+#define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */
+#define ATMEL_ID_TWI1 10 /* Two-Wire Interface 1 */
+#define ATMEL_ID_TWI2 11 /* Two-Wire Interface 2 */
+#define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */
+#define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1 14 /* Serial Peripheral Interface 1 */
+#define ATMEL_ID_UART0 15 /* UART 0 */
+#define ATMEL_ID_UART1 16 /* UART 1 */
+#define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+#define ATMEL_ID_PWM 18 /* Pulse Width Modulation Controller */
+#define ATMEL_ID_ADC 19 /* ADC Controller */
+#define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */
+#define ATMEL_ID_DMAC1 21 /* DMA Controller 1 */
+#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */
+#define ATMEL_ID_UDPHS 23 /* USB Device High Speed */
+#define ATMEL_ID_EMAC0 24 /* Ethernet MAC0 */
+#define ATMEL_ID_LCDC 25 /* LCD Controller */
+#define ATMEL_ID_HSMCI1 26 /* High Speed Multimedia Card Interface 1 */
+#define ATMEL_ID_EMAC1 27 /* Ethernet MAC1 */
+#define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */
+#define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller */
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define ATMEL_BASE_SPI0 0xf0000000
+#define ATMEL_BASE_SPI1 0xf0004000
+#define ATMEL_BASE_HSMCI0 0xf0008000
+#define ATMEL_BASE_HSMCI1 0xf000c000
+#define ATMEL_BASE_SSC 0xf0010000
+#define ATMEL_BASE_CAN0 0xf8000000
+#define ATMEL_BASE_CAN1 0xf8004000
+#define ATMEL_BASE_TC0 0xf8008000
+#define ATMEL_BASE_TC1 0xf8008040
+#define ATMEL_BASE_TC2 0xf8008080
+#define ATMEL_BASE_TC3 0xf800c000
+#define ATMEL_BASE_TC4 0xf800c040
+#define ATMEL_BASE_TC5 0xf800c080
+#define ATMEL_BASE_TWI0 0xf8010000
+#define ATMEL_BASE_TWI1 0xf8014000
+#define ATMEL_BASE_TWI2 0xf8018000
+#define ATMEL_BASE_USART0 0xf801c000
+#define ATMEL_BASE_USART1 0xf8020000
+#define ATMEL_BASE_USART2 0xf8024000
+#define ATMEL_BASE_USART3 0xf8028000
+#define ATMEL_BASE_EMAC0 0xf802c000
+#define ATMEL_BASE_EMAC1 0xf8030000
+#define ATMEL_BASE_PWM 0xf8034000
+#define ATMEL_BASE_LCDC 0xf8038000
+#define ATMEL_BASE_UDPHS 0xf803c000
+#define ATMEL_BASE_UART0 0xf8040000
+#define ATMEL_BASE_UART1 0xf8044000
+#define ATMEL_BASE_ISI 0xf8048000
+#define ATMEL_BASE_ADC 0xf804c000
+#define ATMEL_BASE_SYS 0xffffc000
+
+/*
+ * System Peripherals
+ */
+#define ATMEL_BASE_MATRIX 0xffffde00
+#define ATMEL_BASE_PMECC 0xffffe000
+#define ATMEL_BASE_PMERRLOC 0xffffe600
+#define ATMEL_BASE_DDRSDRC 0xffffe800
+#define ATMEL_BASE_SMC 0xffffea00
+#define ATMEL_BASE_DMAC0 0xffffec00
+#define ATMEL_BASE_DMAC1 0xffffee00
+#define ATMEL_BASE_AIC 0xfffff000
+#define ATMEL_BASE_DBGU 0xfffff200
+#define ATMEL_BASE_PIOA 0xfffff400
+#define ATMEL_BASE_PIOB 0xfffff600
+#define ATMEL_BASE_PIOC 0xfffff800
+#define ATMEL_BASE_PIOD 0xfffffa00
+#define ATMEL_BASE_PMC 0xfffffc00
+#define ATMEL_BASE_RSTC 0xfffffe00
+#define ATMEL_BASE_SHDWC 0xfffffe10
+#define ATMEL_BASE_PIT 0xfffffe30
+#define ATMEL_BASE_WDT 0xfffffe40
+#define ATMEL_BASE_GPBR 0xfffffe60
+#define ATMEL_BASE_RTC 0xfffffeb0
+
+/*
+ * Internal Memory.
+ */
+#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
+#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
+#define ATMEL_BASE_SMD 0x00400000 /* SMD Controller */
+#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */
+#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */
+#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
+
+/* 9x5 series chip id definitions */
+#define ARCH_ID_AT91SAM9X5 0x819a05a0
+#define ARCH_ID_VERSION_MASK 0x1f
+#define ARCH_EXID_AT91SAM9G15 0x00000000
+#define ARCH_EXID_AT91SAM9G35 0x00000001
+#define ARCH_EXID_AT91SAM9X35 0x00000002
+#define ARCH_EXID_AT91SAM9G25 0x00000003
+#define ARCH_EXID_AT91SAM9X25 0x00000004
+
+#define cpu_is_at91sam9x5() (get_chip_id() == ARCH_ID_AT91SAM9X5)
+#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \
+ (get_extension_chip_id() == ARCH_EXID_AT91SAM9G15))
+#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \
+ (get_extension_chip_id() == ARCH_EXID_AT91SAM9G25))
+#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \
+ (get_extension_chip_id() == ARCH_EXID_AT91SAM9G35))
+#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \
+ (get_extension_chip_id() == ARCH_EXID_AT91SAM9X25))
+#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \
+ (get_extension_chip_id() == ARCH_EXID_AT91SAM9X35))
+
+/*
+ * Cpu Name
+ */
+#define CONFIG_SYS_AT91_G15_CPU_NAME "AT91SAM9G15"
+#define CONFIG_SYS_AT91_G25_CPU_NAME "AT91SAM9G25"
+#define CONFIG_SYS_AT91_G35_CPU_NAME "AT91SAM9G35"
+#define CONFIG_SYS_AT91_X25_CPU_NAME "AT91SAM9X25"
+#define CONFIG_SYS_AT91_X35_CPU_NAME "AT91SAM9X35"
+#define CONFIG_SYS_AT91_UNKNOWN_CPU "Unknown CPU type"
+#define ATMEL_CPU_NAME get_cpu_name()
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS 4
+#define CPU_HAS_PIO3
+#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
+
+/*
+ * at91sam9x5 specific prototypes
+ */
+#ifndef __ASSEMBLY__
+unsigned int get_chip_id(void);
+unsigned int get_extension_chip_id(void);
+unsigned int has_emac1(void);
+unsigned int has_emac0(void);
+unsigned int has_lcdc(void);
+char *get_cpu_name(void);
+#endif
+
+#endif
--- /dev/null
+/*
+ * Matrix-centric header file for the AT91SAM9X5 family
+ *
+ * Copyright (C) 2012 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9X5 preliminary datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __AT91SAM9X5_MATRIX_H__
+#define __AT91SAM9X5_MATRIX_H__
+
+#ifndef __ASSEMBLY__
+
+struct at91_matrix {
+ u32 mcfg[16];
+ u32 scfg[16];
+ u32 pras[16][2];
+ u32 mrcr; /* 0x100 Master Remap Control */
+ u32 filler[7];
+ u32 ebicsa;
+ u32 filler4[47];
+ u32 wpmr;
+ u32 wpsr;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
+#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
+#define AT91_MATRIX_ULBT_128 (7 << 0)
+
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
+
+#define AT91_MATRIX_M0PR_SHIFT 0
+#define AT91_MATRIX_M1PR_SHIFT 4
+#define AT91_MATRIX_M2PR_SHIFT 8
+#define AT91_MATRIX_M3PR_SHIFT 12
+#define AT91_MATRIX_M4PR_SHIFT 16
+#define AT91_MATRIX_M5PR_SHIFT 20
+#define AT91_MATRIX_M6PR_SHIFT 24
+#define AT91_MATRIX_M7PR_SHIFT 28
+
+#define AT91_MATRIX_M8PR_SHIFT 0 /* register B */
+#define AT91_MATRIX_M9PR_SHIFT 4 /* register B */
+#define AT91_MATRIX_M10PR_SHIFT 8 /* register B */
+#define AT91_MATRIX_M11PR_SHIFT 12 /* register B */
+
+#define AT91_MATRIX_RCB0 (1 << 0)
+#define AT91_MATRIX_RCB1 (1 << 1)
+#define AT91_MATRIX_RCB2 (1 << 2)
+#define AT91_MATRIX_RCB3 (1 << 3)
+#define AT91_MATRIX_RCB4 (1 << 4)
+#define AT91_MATRIX_RCB5 (1 << 5)
+#define AT91_MATRIX_RCB6 (1 << 6)
+#define AT91_MATRIX_RCB7 (1 << 7)
+#define AT91_MATRIX_RCB8 (1 << 8)
+#define AT91_MATRIX_RCB9 (1 << 9)
+#define AT91_MATRIX_RCB10 (1 << 10)
+
+#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
+#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
+#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
+#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
+#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
+#define AT91_MATRIX_EBI_DBPD_ON (0 << 9)
+#define AT91_MATRIX_EBI_DBPD_OFF (1 << 9)
+#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
+#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
+#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
+#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
+#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
+#define AT91_MATRIX_MP_OFF (0 << 25)
+#define AT91_MATRIX_MP_ON (1 << 25)
+
+#endif
# include <asm/arch/at91sam9rl.h>
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
# include <asm/arch/at91sam9g45.h>
+#elif defined(CONFIG_AT91SAM9X5)
+# include <asm/arch/at91sam9x5.h>
#elif defined(CONFIG_AT91CAP9)
# include <asm/arch/at91cap9.h>
#elif defined(CONFIG_AT91X40)
--- /dev/null
+/*
+ * Copyright (C) 2012 Vikram Narayananan
+ * <vikram186@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BCM2835_GPIO_H_
+#define _BCM2835_GPIO_H_
+
+#define BCM2835_GPIO_BASE 0x20200000
+#define BCM2835_GPIO_COUNT 54
+
+#define BCM2835_GPIO_FSEL_MASK 0x7
+#define BCM2835_GPIO_INPUT 0x0
+#define BCM2835_GPIO_OUTPUT 0x1
+#define BCM2835_GPIO_ALT0 0x4
+#define BCM2835_GPIO_ALT1 0x5
+#define BCM2835_GPIO_ALT2 0x6
+#define BCM2835_GPIO_ALT3 0x7
+#define BCM2835_GPIO_ALT4 0x3
+#define BCM2835_GPIO_ALT5 0x2
+
+#define BCM2835_GPIO_COMMON_BANK(gpio) ((gpio < 32) ? 0 : 1)
+#define BCM2835_GPIO_COMMON_SHIFT(gpio) (gpio & 0x1f)
+
+#define BCM2835_GPIO_FSEL_BANK(gpio) (gpio / 10)
+#define BCM2835_GPIO_FSEL_SHIFT(gpio) ((gpio % 10) * 3)
+
+struct bcm2835_gpio_regs {
+ u32 gpfsel[6];
+ u32 reserved1;
+ u32 gpset[2];
+ u32 reserved2;
+ u32 gpclr[2];
+ u32 reserved3;
+ u32 gplev[2];
+ u32 reserved4;
+ u32 gpeds[2];
+ u32 reserved5;
+ u32 gpren[2];
+ u32 reserved6;
+ u32 gpfen[2];
+ u32 reserved7;
+ u32 gphen[2];
+ u32 reserved8;
+ u32 gplen[2];
+ u32 reserved9;
+ u32 gparen[2];
+ u32 reserved10;
+ u32 gppud;
+ u32 gppudclk[2];
+};
+
+#endif /* _BCM2835_GPIO_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BCM2835_TIMER_H
+#define _BCM2835_TIMER_H
+
+#define BCM2835_TIMER_PHYSADDR 0x20003000
+
+struct bcm2835_timer_regs {
+ u32 cs;
+ u32 clo;
+ u32 chi;
+ u32 c0;
+ u32 c1;
+ u32 c2;
+ u32 c3;
+};
+
+#define BCM2835_TIMER_CS_M3 (1 << 3)
+#define BCM2835_TIMER_CS_M2 (1 << 2)
+#define BCM2835_TIMER_CS_M1 (1 << 1)
+#define BCM2835_TIMER_CS_M0 (1 << 0)
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BCM2835_TIMER_H
+#define _BCM2835_TIMER_H
+
+#define BCM2835_WDOG_PHYSADDR 0x20100000
+
+struct bcm2835_wdog_regs {
+ u32 unknown0[7];
+ u32 rstc;
+ u32 unknown1;
+ u32 wdog;
+};
+
+#define BCM2835_WDOG_PASSWORD 0x5a000000
+
+#define BCM2835_WDOG_RSTC_WRCFG_MASK 0x00000030
+#define BCM2835_WDOG_RSTC_WRCFG_FULL_RESET 0x00000020
+
+#define BCM2835_WDOG_WDOG_TIMEOUT_MASK 0x0000ffff
+
+#endif
/*
- * da8xx.h -- TI's DA8xx platform specific usb wrapper definitions.
+ * da8xx-usb.h -- TI's DA8xx platform specific usb wrapper definitions.
*
* Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
*
#include <asm/arch/hardware.h>
#include <asm/arch/gpio.h>
-#include "musb_core.h"
/* Base address of da8xx usb0 wrapper */
#define DA8XX_USB_OTG_BASE 0x01E00000
#define CFGCHIP2_REFFREQ_48MHZ (3 << 0)
#define DA8XX_USB_VBUS_GPIO (1 << 15)
+
+int usb_phy_on(void);
+void usb_phy_off(void);
+
#endif /* __DA8XX_MUSB_H__ */
void lpsc_on(unsigned int id);
void lpsc_syncreset(unsigned int id);
+void lpsc_disable(unsigned int id);
void dsp_on(void);
void davinci_enable_uart0(void);
#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
#define DAVINCI_PLLC_DIV_MASK 0x1f
-#define ASYNC3 get_async3_src()
-#define PLL1_SYSCLK2 ((1 << 16) | 0x2)
-#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3)
-/* Clock IDs */
+/*
+ * A clock ID is a 32-bit number where bit 16 represents the PLL controller
+ * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor,
+ * counting from 1. Clock IDs may be passed to clk_get().
+ */
+
+/* flags to select PLL controller */
+#define DAVINCI_PLLC0_FLAG (0)
+#define DAVINCI_PLLC1_FLAG (1 << 16)
+
enum davinci_clk_ids {
- DAVINCI_SPI0_CLKID = 2,
- DAVINCI_UART2_CLKID = 2,
- DAVINCI_MMC_CLKID = 2,
- DAVINCI_MDIO_CLKID = 4,
- DAVINCI_ARM_CLKID = 6,
- DAVINCI_PLLM_CLKID = 0xff,
- DAVINCI_PLLC_CLKID = 0x100,
- DAVINCI_AUXCLK_CLKID = 0x101
+ /*
+ * Clock IDs for PLL outputs. Each may be switched on/off
+ * independently, and each may map to one or more peripherals.
+ */
+ DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2,
+ DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4,
+ DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6,
+ DAVINCI_PLL1_SYSCLK1 = DAVINCI_PLLC1_FLAG | 1,
+ DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2,
+
+ /* map peripherals to clock IDs */
+ DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6,
+ DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1,
+ DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
+ DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
+ DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
+ DAVINCI_MMCSD_CLKID = DAVINCI_PLL0_SYSCLK2,
+
+ /* special clock ID - output of PLL multiplier */
+ DAVINCI_PLLM_CLKID = 0x0FF,
+
+ /* special clock ID - output of PLL post divisor */
+ DAVINCI_PLLC_CLKID = 0x100,
+
+ /* special clock ID - PLL bypass */
+ DAVINCI_AUXCLK_CLKID = 0x101,
};
+#define DAVINCI_UART2_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
+ : get_async3_src())
+
+#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
+ : get_async3_src())
+
int clk_get(enum davinci_clk_ids id);
/* Boot config */
((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
#define DDR_SLEW_CMOSEN_BIT 4
+#define DDR_SLEW_DDR_PDENA_BIT 5
#define VTP_POWERDWN (1 << 6)
#define VTP_LOCK (1 << 7)
return ((part_no == 0xb7d1) ? 1 : 0);
}
-static inline int get_async3_src(void)
+static inline enum davinci_clk_ids get_async3_src(void)
{
return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
- PLL1_SYSCLK2 : 2;
+ DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
}
#endif /* CONFIG_SOC_DA8XX */
extern const struct pinmux_config spi1_pins_scs0[1];
/* UART pin muxer settings */
+extern const struct pinmux_config uart0_pins_txrx[2];
extern const struct pinmux_config uart1_pins_txrx[2];
extern const struct pinmux_config uart2_pins_txrx[2];
extern const struct pinmux_config uart2_pins_rtscts[2];
extern const struct pinmux_config emifa_pins_nand[12];
extern const struct pinmux_config emifa_pins_nor[43];
+/* MMC pin muxer settings */
+extern const struct pinmux_config mmc0_pins[6];
+
#endif
#define EPLL 2
#define HPLL 3
#define VPLL 4
+#define BPLL 5
unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
unsigned int clkout_cmu_cpu_div_stat;
unsigned char res8[0x5f8];
unsigned int armclk_stopctrl;
- unsigned int atclk_stopctrl;
- unsigned char res9[0x8];
+ unsigned char res9[0x0c];
unsigned int parityfail_status;
unsigned int parityfail_clear;
unsigned char res10[0x8];
unsigned char res19[0xf8];
unsigned int div_core0;
unsigned int div_core1;
- unsigned char res20[0xf8];
+ unsigned int div_sysrgt;
+ unsigned char res20[0xf4];
unsigned int div_stat_core0;
unsigned int div_stat_core1;
- unsigned char res21[0x2f8];
+ unsigned int div_stat_sysrgt;
+ unsigned char res21[0x2f4];
unsigned int gate_ip_core;
- unsigned char res22[0xfc];
+ unsigned int gate_ip_sysrgt;
+ unsigned char res22[0x8];
+ unsigned int c2c_monitor;
+ unsigned char res23[0xec];
unsigned int clkout_cmu_core;
unsigned int clkout_cmu_core_div_stat;
- unsigned char res23[0x5f8];
+ unsigned char res24[0x5f8];
unsigned int dcgidx_map0;
unsigned int dcgidx_map1;
unsigned int dcgidx_map2;
- unsigned char res24[0x14];
+ unsigned char res25[0x14];
unsigned int dcgperf_map0;
unsigned int dcgperf_map1;
- unsigned char res25[0x18];
+ unsigned char res26[0x18];
unsigned int dvcidx_map;
- unsigned char res26[0x1c];
+ unsigned char res27[0x1c];
unsigned int freq_cpu;
unsigned int freq_dpm;
- unsigned char res27[0x18];
+ unsigned char res28[0x18];
unsigned int dvsemclk_en;
unsigned int maxperf;
- unsigned char res28[0x3478];
+ unsigned char res29[0xf78];
+ unsigned int c2c_config;
+ unsigned char res30[0x24fc];
unsigned int div_acp;
- unsigned char res29[0xfc];
+ unsigned char res31[0xfc];
unsigned int div_stat_acp;
- unsigned char res30[0x1fc];
+ unsigned char res32[0x1fc];
unsigned int gate_ip_acp;
- unsigned char res31[0x1fc];
+ unsigned char res33[0xfc];
+ unsigned int div_syslft;
+ unsigned char res34[0xc];
+ unsigned int div_stat_syslft;
+ unsigned char res35[0x1c];
+ unsigned int gate_ip_syslft;
+ unsigned char res36[0xcc];
unsigned int clkout_cmu_acp;
unsigned int clkout_cmu_acp_div_stat;
- unsigned char res32[0x38f8];
+ unsigned char res37[0x8];
+ unsigned int ufmc_config;
+ unsigned char res38[0x38ec];
unsigned int div_isp0;
unsigned int div_isp1;
unsigned int div_isp2;
- unsigned char res33[0xf4];
+ unsigned char res39[0xf4];
unsigned int div_stat_isp0;
unsigned int div_stat_isp1;
unsigned int div_stat_isp2;
- unsigned char res34[0x3f4];
+ unsigned char res40[0x3f4];
unsigned int gate_ip_isp0;
unsigned int gate_ip_isp1;
- unsigned char res35[0xf8];
+ unsigned char res41[0xf8];
unsigned int gate_sclk_isp;
- unsigned char res36[0xc];
+ unsigned char res42[0xc];
unsigned int mcuisp_pwr_ctrl;
- unsigned char res37[0xec];
+ unsigned char res43[0xec];
unsigned int clkout_cmu_isp;
unsigned int clkout_cmu_isp_div_stat;
- unsigned char res38[0x3618];
+ unsigned char res44[0x3618];
unsigned int cpll_lock;
- unsigned char res39[0xc];
+ unsigned char res45[0xc];
unsigned int epll_lock;
- unsigned char res40[0xc];
+ unsigned char res46[0xc];
unsigned int vpll_lock;
- unsigned char res41[0xdc];
+ unsigned char res47[0xc];
+ unsigned int gpll_lock;
+ unsigned char res48[0xcc];
unsigned int cpll_con0;
unsigned int cpll_con1;
- unsigned char res42[0x8];
+ unsigned char res49[0x8];
unsigned int epll_con0;
unsigned int epll_con1;
unsigned int epll_con2;
- unsigned char res43[0x4];
+ unsigned char res50[0x4];
unsigned int vpll_con0;
unsigned int vpll_con1;
unsigned int vpll_con2;
- unsigned char res44[0xc4];
+ unsigned char res51[0x4];
+ unsigned int gpll_con0;
+ unsigned int gpll_con1;
+ unsigned char res52[0xb8];
unsigned int src_top0;
unsigned int src_top1;
unsigned int src_top2;
unsigned int src_top3;
unsigned int src_gscl;
- unsigned int src_disp0_0;
- unsigned int src_disp0_1;
+ unsigned char res53[0x8];
unsigned int src_disp1_0;
- unsigned int src_disp1_1;
- unsigned char res46[0xc];
+ unsigned char res54[0x10];
unsigned int src_mau;
unsigned int src_fsys;
- unsigned char res47[0x8];
+ unsigned int src_gen;
+ unsigned char res55[0x4];
unsigned int src_peric0;
unsigned int src_peric1;
- unsigned char res48[0x18];
+ unsigned char res56[0x18];
unsigned int sclk_src_isp;
- unsigned char res49[0x9c];
+ unsigned char res57[0x9c];
unsigned int src_mask_top;
- unsigned char res50[0xc];
+ unsigned char res58[0xc];
unsigned int src_mask_gscl;
- unsigned int src_mask_disp0_0;
- unsigned int src_mask_disp0_1;
+ unsigned char res59[0x8];
unsigned int src_mask_disp1_0;
- unsigned int src_mask_disp1_1;
- unsigned int src_mask_maudio;
- unsigned char res52[0x8];
+ unsigned char res60[0x4];
+ unsigned int src_mask_mau;
+ unsigned char res61[0x8];
unsigned int src_mask_fsys;
- unsigned char res53[0xc];
+ unsigned int src_mask_gen;
+ unsigned char res62[0x8];
unsigned int src_mask_peric0;
unsigned int src_mask_peric1;
- unsigned char res54[0x18];
+ unsigned char res63[0x18];
unsigned int src_mask_isp;
- unsigned char res55[0x9c];
+ unsigned char res67[0x9c];
unsigned int mux_stat_top0;
unsigned int mux_stat_top1;
unsigned int mux_stat_top2;
unsigned int mux_stat_top3;
- unsigned char res56[0xf0];
+ unsigned char res68[0xf0];
unsigned int div_top0;
unsigned int div_top1;
- unsigned char res57[0x8];
+ unsigned char res69[0x8];
unsigned int div_gscl;
- unsigned int div_disp0_0;
- unsigned int div_disp0_1;
+ unsigned char res70[0x8];
unsigned int div_disp1_0;
- unsigned int div_disp1_1;
- unsigned char res59[0x8];
+ unsigned char res71[0xc];
unsigned int div_gen;
- unsigned char res60[0x4];
+ unsigned char res72[0x4];
unsigned int div_mau;
unsigned int div_fsys0;
unsigned int div_fsys1;
unsigned int div_fsys2;
- unsigned int div_fsys3;
+ unsigned char res73[0x4];
unsigned int div_peric0;
unsigned int div_peric1;
unsigned int div_peric2;
unsigned int div_peric3;
unsigned int div_peric4;
unsigned int div_peric5;
- unsigned char res61[0x10];
+ unsigned char res74[0x10];
unsigned int sclk_div_isp;
- unsigned char res62[0xc];
+ unsigned char res75[0xc];
unsigned int div2_ratio0;
unsigned int div2_ratio1;
- unsigned char res63[0x8];
+ unsigned char res76[0x8];
unsigned int div4_ratio;
- unsigned char res64[0x6c];
+ unsigned char res77[0x6c];
unsigned int div_stat_top0;
unsigned int div_stat_top1;
- unsigned char res65[0x8];
+ unsigned char res78[0x8];
unsigned int div_stat_gscl;
- unsigned int div_stat_disp0_0;
- unsigned int div_stat_disp0_1;
+ unsigned char res79[0x8];
unsigned int div_stat_disp1_0;
- unsigned int div_stat_disp1_1;
- unsigned char res67[0x8];
+ unsigned char res80[0xc];
unsigned int div_stat_gen;
- unsigned char res68[0x4];
- unsigned int div_stat_maudio;
+ unsigned char res81[0x4];
+ unsigned int div_stat_mau;
unsigned int div_stat_fsys0;
unsigned int div_stat_fsys1;
unsigned int div_stat_fsys2;
- unsigned int div_stat_fsys3;
+ unsigned char res82[0x4];
unsigned int div_stat_peric0;
unsigned int div_stat_peric1;
unsigned int div_stat_peric2;
unsigned int div_stat_peric3;
unsigned int div_stat_peric4;
unsigned int div_stat_peric5;
- unsigned char res69[0x10];
+ unsigned char res83[0x10];
unsigned int sclk_div_stat_isp;
- unsigned char res70[0xc];
+ unsigned char res84[0xc];
unsigned int div2_stat0;
unsigned int div2_stat1;
- unsigned char res71[0x8];
+ unsigned char res85[0x8];
unsigned int div4_stat;
- unsigned char res72[0x180];
- unsigned int gate_top_sclk_disp0;
+ unsigned char res86[0x184];
unsigned int gate_top_sclk_disp1;
unsigned int gate_top_sclk_gen;
- unsigned char res74[0xc];
+ unsigned char res87[0xc];
unsigned int gate_top_sclk_mau;
unsigned int gate_top_sclk_fsys;
- unsigned char res75[0xc];
+ unsigned char res88[0xc];
unsigned int gate_top_sclk_peric;
- unsigned char res76[0x1c];
+ unsigned char res89[0x1c];
unsigned int gate_top_sclk_isp;
- unsigned char res77[0xac];
+ unsigned char res90[0xac];
unsigned int gate_ip_gscl;
- unsigned int gate_ip_disp0;
+ unsigned char res91[0x4];
unsigned int gate_ip_disp1;
unsigned int gate_ip_mfc;
unsigned int gate_ip_g3d;
unsigned int gate_ip_gen;
- unsigned char res79[0xc];
+ unsigned char res92[0xc];
unsigned int gate_ip_fsys;
- unsigned char res80[0x4];
- unsigned int gate_ip_gps;
+ unsigned char res93[0x8];
unsigned int gate_ip_peric;
- unsigned char res81[0xc];
+ unsigned char res94[0xc];
unsigned int gate_ip_peris;
- unsigned char res82[0x1c];
+ unsigned char res95[0x1c];
unsigned int gate_block;
- unsigned char res83[0x7c];
+ unsigned char res96[0x1c];
+ unsigned int mcuiop_pwr_ctrl;
+ unsigned char res97[0x5c];
unsigned int clkout_cmu_top;
unsigned int clkout_cmu_top_div_stat;
- unsigned char res84[0x37f8];
+ unsigned char res98[0x37f8];
unsigned int src_lex;
- unsigned char res85[0x2fc];
+ unsigned char res99[0x1fc];
+ unsigned int mux_stat_lex;
+ unsigned char res100[0xfc];
unsigned int div_lex;
- unsigned char res86[0xfc];
+ unsigned char res101[0xfc];
unsigned int div_stat_lex;
- unsigned char res87[0x1fc];
+ unsigned char res102[0x1fc];
unsigned int gate_ip_lex;
- unsigned char res88[0x1fc];
+ unsigned char res103[0x1fc];
unsigned int clkout_cmu_lex;
unsigned int clkout_cmu_lex_div_stat;
- unsigned char res89[0x3af8];
+ unsigned char res104[0x3af8];
unsigned int div_r0x;
- unsigned char res90[0xfc];
+ unsigned char res105[0xfc];
unsigned int div_stat_r0x;
- unsigned char res91[0x1fc];
+ unsigned char res106[0x1fc];
unsigned int gate_ip_r0x;
- unsigned char res92[0x1fc];
+ unsigned char res107[0x1fc];
unsigned int clkout_cmu_r0x;
unsigned int clkout_cmu_r0x_div_stat;
- unsigned char res94[0x3af8];
+ unsigned char res108[0x3af8];
unsigned int div_r1x;
- unsigned char res95[0xfc];
+ unsigned char res109[0xfc];
unsigned int div_stat_r1x;
- unsigned char res96[0x1fc];
+ unsigned char res110[0x1fc];
unsigned int gate_ip_r1x;
- unsigned char res97[0x1fc];
+ unsigned char res111[0x1fc];
unsigned int clkout_cmu_r1x;
unsigned int clkout_cmu_r1x_div_stat;
- unsigned char res98[0x3608];
+ unsigned char res112[0x3608];
unsigned int bpll_lock;
- unsigned char res99[0xfc];
+ unsigned char res113[0xfc];
unsigned int bpll_con0;
unsigned int bpll_con1;
- unsigned char res100[0xe8];
+ unsigned char res114[0xe8];
unsigned int src_cdrex;
- unsigned char res101[0x1fc];
+ unsigned char res115[0x1fc];
unsigned int mux_stat_cdrex;
- unsigned char res102[0xfc];
+ unsigned char res116[0xfc];
unsigned int div_cdrex;
- unsigned int div_cdrex2;
- unsigned char res103[0xf8];
+ unsigned char res117[0xfc];
unsigned int div_stat_cdrex;
- unsigned char res104[0x2fc];
+ unsigned char res118[0x2fc];
unsigned int gate_ip_cdrex;
- unsigned char res105[0xc];
- unsigned int c2c_monitor;
- unsigned int dmc_pwr_ctrl;
- unsigned char res106[0x4];
+ unsigned char res119[0x10];
+ unsigned int dmc_freq_ctrl;
+ unsigned char res120[0x4];
unsigned int drex2_pause;
- unsigned char res107[0xe0];
+ unsigned char res121[0xe0];
unsigned int clkout_cmu_cdrex;
unsigned int clkout_cmu_cdrex_div_stat;
- unsigned char res108[0x8];
+ unsigned char res122[0x8];
unsigned int lpddr3phy_ctrl;
- unsigned char res109[0xf5f8];
+ unsigned int lpddr3phy_con0;
+ unsigned int lpddr3phy_con1;
+ unsigned int lpddr3phy_con2;
+ unsigned int lpddr3phy_con3;
+ unsigned int pll_div2_sel;
+ unsigned char res123[0xf5d8];
};
#endif
+#define MPLL_FOUT_SEL_SHIFT 4
+#define MPLL_FOUT_SEL_MASK 0x1
+#define BPLL_FOUT_SEL_SHIFT 0
+#define BPLL_FOUT_SEL_MASK 0x1
#endif
#define EXYNOS4_USBPHY_CONTROL 0x10020704
#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS5 */
#define EXYNOS5_I2C_SPACING 0x10000
#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
#define EXYNOS5_GPIO_PART2_BASE 0x13400000
#define EXYNOS5_FIMD_BASE 0x14400000
+#define EXYNOS5_DP_BASE 0x145B0000
#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
SAMSUNG_BASE(adc, ADC_BASE)
SAMSUNG_BASE(clock, CLOCK_BASE)
+SAMSUNG_BASE(dp, DP_BASE)
SAMSUNG_BASE(sysreg, SYSREG_BASE)
SAMSUNG_BASE(fimd, FIMD_BASE)
SAMSUNG_BASE(i2c, I2C_BASE)
unsigned int phy_con41;
unsigned int phy_con42;
};
+
+enum ddr_mode {
+ DDR_MODE_DDR2,
+ DDR_MODE_DDR3,
+ DDR_MODE_LPDDR2,
+ DDR_MODE_LPDDR3,
+
+ DDR_MODE_COUNT,
+};
+
+enum mem_manuf {
+ MEM_MANUF_AUTODETECT,
+ MEM_MANUF_ELPIDA,
+ MEM_MANUF_SAMSUNG,
+
+ MEM_MANUF_COUNT,
+};
+
+/* CONCONTROL register fields */
+#define CONCONTROL_DFI_INIT_START_SHIFT 28
+#define CONCONTROL_RD_FETCH_SHIFT 12
+#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
+#define CONCONTROL_AREF_EN_SHIFT 5
+
+/* PRECHCONFIG register field */
+#define PRECHCONFIG_TP_CNT_SHIFT 24
+
+/* PWRDNCONFIG register field */
+#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0
+#define PWRDNCONFIG_DSREF_CYC_SHIFT 16
+
+/* PHY_CON0 register fields */
+#define PHY_CON0_T_WRRDCMD_SHIFT 17
+#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
+#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
+
+/* PHY_CON1 register fields */
+#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0
+
+/* PHY_CON12 register fields */
+#define PHY_CON12_CTRL_START_POINT_SHIFT 24
+#define PHY_CON12_CTRL_INC_SHIFT 16
+#define PHY_CON12_CTRL_FORCE_SHIFT 8
+#define PHY_CON12_CTRL_START_SHIFT 6
+#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT)
+#define PHY_CON12_CTRL_DLL_ON_SHIFT 5
+#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
+#define PHY_CON12_CTRL_REF_SHIFT 1
+
+/* PHY_CON16 register fields */
+#define PHY_CON16_ZQ_MODE_DDS_SHIFT 24
+#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
+#define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19)
+
+/* PHY_CON42 register fields */
+#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
+#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
+
+#define PHY_CON42_CTRL_RDLAT_SHIFT 0
+#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
+
#endif
#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_DP_H_
+#define __ASM_ARM_ARCH_DP_H_
+
+#ifndef __ASSEMBLY__
+
+struct exynos_dp {
+ unsigned char res1[0x10];
+ unsigned int tx_version;
+ unsigned int tx_sw_reset;
+ unsigned int func_en1;
+ unsigned int func_en2;
+ unsigned int video_ctl1;
+ unsigned int video_ctl2;
+ unsigned int video_ctl3;
+ unsigned int video_ctl4;
+ unsigned int color_blue_cb;
+ unsigned int color_green_y;
+ unsigned int color_red_cr;
+ unsigned int video_ctl8;
+ unsigned char res2[0x4];
+ unsigned int video_ctl10;
+ unsigned int total_ln_cfg_l;
+ unsigned int total_ln_cfg_h;
+ unsigned int active_ln_cfg_l;
+ unsigned int active_ln_cfg_h;
+ unsigned int vfp_cfg;
+ unsigned int vsw_cfg;
+ unsigned int vbp_cfg;
+ unsigned int total_pix_cfg_l;
+ unsigned int total_pix_cfg_h;
+ unsigned int active_pix_cfg_l;
+ unsigned int active_pix_cfg_h;
+ unsigned int hfp_cfg_l;
+ unsigned int hfp_cfg_h;
+ unsigned int hsw_cfg_l;
+ unsigned int hsw_cfg_h;
+ unsigned int hbp_cfg_l;
+ unsigned int hbp_cfg_h;
+ unsigned int video_status;
+ unsigned int total_ln_sta_l;
+ unsigned int total_ln_sta_h;
+ unsigned int active_ln_sta_l;
+ unsigned int active_ln_sta_h;
+
+ unsigned int vfp_sta;
+ unsigned int vsw_sta;
+ unsigned int vbp_sta;
+
+ unsigned int total_pix_sta_l;
+ unsigned int total_pix_sta_h;
+ unsigned int active_pix_sta_l;
+ unsigned int active_pix_sta_h;
+
+ unsigned int hfp_sta_l;
+ unsigned int hfp_sta_h;
+ unsigned int hsw_sta_l;
+ unsigned int hsw_sta_h;
+ unsigned int hbp_sta_l;
+ unsigned int hbp_sta_h;
+
+ unsigned char res3[0x288];
+
+ unsigned int lane_map;
+ unsigned char res4[0x10];
+ unsigned int analog_ctl1;
+ unsigned int analog_ctl2;
+ unsigned int analog_ctl3;
+
+ unsigned int pll_filter_ctl1;
+ unsigned int amp_tuning_ctl;
+ unsigned char res5[0xc];
+
+ unsigned int aux_hw_retry_ctl;
+ unsigned char res6[0x2c];
+ unsigned int int_state;
+ unsigned int common_int_sta1;
+ unsigned int common_int_sta2;
+ unsigned int common_int_sta3;
+ unsigned int common_int_sta4;
+ unsigned char res7[0x8];
+
+ unsigned int int_sta;
+ unsigned char res8[0x1c];
+ unsigned int int_ctl;
+ unsigned char res9[0x200];
+ unsigned int sys_ctl1;
+ unsigned int sys_ctl2;
+ unsigned int sys_ctl3;
+ unsigned int sys_ctl4;
+ unsigned int vid_ctl;
+ unsigned char res10[0x2c];
+ unsigned int pkt_send_ctl;
+ unsigned char res[0x4];
+ unsigned int hdcp_ctl;
+ unsigned char res11[0x34];
+ unsigned int link_bw_set;
+
+ unsigned int lane_count_set;
+ unsigned int training_ptn_set;
+ unsigned int ln0_link_training_ctl;
+ unsigned int ln1_link_training_ctl;
+ unsigned int ln2_link_training_ctl;
+ unsigned int ln3_link_training_ctl;
+ unsigned int dn_spread_ctl;
+ unsigned int hw_link_training_ctl;
+ unsigned char res12[0x1c];
+
+ unsigned int debug_ctl;
+ unsigned int hpd_deglitch_l;
+ unsigned int hpd_deglitch_h;
+
+ unsigned char res13[0x14];
+ unsigned int link_debug_ctl;
+
+ unsigned char res14[0x1c];
+
+ unsigned int m_vid0;
+ unsigned int m_vid1;
+ unsigned int m_vid2;
+ unsigned int n_vid0;
+ unsigned int n_vid1;
+ unsigned int n_vid2;
+ unsigned int m_vid_mon;
+ unsigned int pll_ctl;
+ unsigned int phy_pd;
+ unsigned int phy_test;
+ unsigned char res15[0x8];
+
+ unsigned int video_fifo_thrd;
+ unsigned char res16[0x8];
+ unsigned int audio_margin;
+
+ unsigned int dn_spread_ctl1;
+ unsigned int dn_spread_ctl2;
+ unsigned char res17[0x18];
+ unsigned int m_cal_ctl;
+ unsigned int m_vid_gen_filter_th;
+ unsigned char res18[0x10];
+ unsigned int m_aud_gen_filter_th;
+ unsigned char res50[0x4];
+
+ unsigned int aux_ch_sta;
+ unsigned int aux_err_num;
+ unsigned int aux_ch_defer_ctl;
+ unsigned int aux_rx_comm;
+ unsigned int buffer_data_ctl;
+
+ unsigned int aux_ch_ctl1;
+ unsigned int aux_addr_7_0;
+ unsigned int aux_addr_15_8;
+ unsigned int aux_addr_19_16;
+ unsigned int aux_ch_ctl2;
+ unsigned char res19[0x18];
+ unsigned int buf_data0;
+ unsigned char res20[0x3c];
+
+ unsigned int soc_general_ctl;
+ unsigned char res21[0x8c];
+ unsigned int crc_con;
+ unsigned int crc_result;
+ unsigned char res22[0x8];
+
+ unsigned int common_int_mask1;
+ unsigned int common_int_mask2;
+ unsigned int common_int_mask3;
+ unsigned int common_int_mask4;
+ unsigned int int_sta_mask1;
+ unsigned int int_sta_mask2;
+ unsigned int int_sta_mask3;
+ unsigned int int_sta_mask4;
+ unsigned int int_sta_mask;
+ unsigned int crc_result2;
+ unsigned int scrambler_reset_cnt;
+
+ unsigned int pn_inv;
+ unsigned int psr_config;
+ unsigned int psr_command0;
+ unsigned int psr_command1;
+ unsigned int psr_crc_mon0;
+ unsigned int psr_crc_mon1;
+
+ unsigned char res24[0x30];
+ unsigned int phy_bist_ctrl;
+ unsigned char res25[0xc];
+ unsigned int phy_ctrl;
+ unsigned char res26[0x1c];
+ unsigned int test_pattern_gen_en;
+ unsigned int test_pattern_gen_ctrl;
+};
+
+#endif /* __ASSEMBLY__ */
+
+/* For DP VIDEO CTL 1 */
+#define VIDEO_EN_MASK (0x01 << 7)
+#define VIDEO_MUTE_MASK (0x01 << 6)
+
+/* For DP VIDEO CTL 4 */
+#define VIDEO_BIST_MASK (0x1 << 3)
+
+/* EXYNOS_DP_ANALOG_CTL_1 */
+#define SEL_BG_NEW_BANDGAP (0x0 << 6)
+#define SEL_BG_INTERNAL_RESISTOR (0x1 << 6)
+#define TX_TERMINAL_CTRL_73_OHM (0x0 << 4)
+#define TX_TERMINAL_CTRL_61_OHM (0x1 << 4)
+#define TX_TERMINAL_CTRL_50_OHM (0x2 << 4)
+#define TX_TERMINAL_CTRL_45_OHM (0x3 << 4)
+#define SWING_A_30PER_G_INCREASE (0x1 << 3)
+#define SWING_A_30PER_G_NORMAL (0x0 << 3)
+
+/* EXYNOS_DP_ANALOG_CTL_2 */
+#define CPREG_BLEED (0x1 << 4)
+#define SEL_24M (0x1 << 3)
+#define TX_DVDD_BIT_1_0000V (0x3 << 0)
+#define TX_DVDD_BIT_1_0625V (0x4 << 0)
+#define TX_DVDD_BIT_1_1250V (0x5 << 0)
+
+/* EXYNOS_DP_ANALOG_CTL_3 */
+#define DRIVE_DVDD_BIT_1_0000V (0x3 << 5)
+#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
+#define DRIVE_DVDD_BIT_1_1250V (0x5 << 5)
+#define SEL_CURRENT_DEFAULT (0x0 << 3)
+#define VCO_BIT_000_MICRO (0x0 << 0)
+#define VCO_BIT_200_MICRO (0x1 << 0)
+#define VCO_BIT_300_MICRO (0x2 << 0)
+#define VCO_BIT_400_MICRO (0x3 << 0)
+#define VCO_BIT_500_MICRO (0x4 << 0)
+#define VCO_BIT_600_MICRO (0x5 << 0)
+#define VCO_BIT_700_MICRO (0x6 << 0)
+#define VCO_BIT_900_MICRO (0x7 << 0)
+
+/* EXYNOS_DP_PLL_FILTER_CTL_1 */
+#define PD_RING_OSC (0x1 << 6)
+#define AUX_TERMINAL_CTRL_52_OHM (0x3 << 4)
+#define AUX_TERMINAL_CTRL_69_OHM (0x2 << 4)
+#define AUX_TERMINAL_CTRL_102_OHM (0x1 << 4)
+#define AUX_TERMINAL_CTRL_200_OHM (0x0 << 4)
+#define TX_CUR1_1X (0x0 << 2)
+#define TX_CUR1_2X (0x1 << 2)
+#define TX_CUR1_3X (0x2 << 2)
+#define TX_CUR_1_MA (0x0 << 0)
+#define TX_CUR_2_MA (0x1 << 0)
+#define TX_CUR_3_MA (0x2 << 0)
+#define TX_CUR_4_MA (0x3 << 0)
+
+/* EXYNOS_DP_PLL_FILTER_CTL_2 */
+#define CH3_AMP_0_MV (0x3 << 12)
+#define CH2_AMP_0_MV (0x3 << 8)
+#define CH1_AMP_0_MV (0x3 << 4)
+#define CH0_AMP_0_MV (0x3 << 0)
+
+/* EXYNOS_DP_PLL_CTL */
+#define DP_PLL_PD (0x1 << 7)
+#define DP_PLL_RESET (0x1 << 6)
+#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4)
+#define DP_PLL_REF_BIT_1_1250V (0x5 << 0)
+#define DP_PLL_REF_BIT_1_2500V (0x7 << 0)
+
+/* EXYNOS_DP_INT_CTL */
+#define SOFT_INT_CTRL (0x1 << 2)
+#define INT_POL (0x1 << 0)
+
+/* DP TX SW RESET */
+#define RESET_DP_TX (0x01 << 0)
+
+/* DP FUNC_EN_1 */
+#define MASTER_VID_FUNC_EN_N (0x1 << 7)
+#define SLAVE_VID_FUNC_EN_N (0x1 << 5)
+#define AUD_FIFO_FUNC_EN_N (0x1 << 4)
+#define AUD_FUNC_EN_N (0x1 << 3)
+#define HDCP_FUNC_EN_N (0x1 << 2)
+#define CRC_FUNC_EN_N (0x1 << 1)
+#define SW_FUNC_EN_N (0x1 << 0)
+
+/* DP FUNC_EN_2 */
+#define SSC_FUNC_EN_N (0x1 << 7)
+#define AUX_FUNC_EN_N (0x1 << 2)
+#define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
+#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
+
+/* EXYNOS_DP_PHY_PD */
+#define PHY_PD (0x1 << 5)
+#define AUX_PD (0x1 << 4)
+#define CH3_PD (0x1 << 3)
+#define CH2_PD (0x1 << 2)
+#define CH1_PD (0x1 << 1)
+#define CH0_PD (0x1 << 0)
+
+/* EXYNOS_DP_COMMON_INT_STA_1 */
+#define VSYNC_DET (0x1 << 7)
+#define PLL_LOCK_CHG (0x1 << 6)
+#define SPDIF_ERR (0x1 << 5)
+#define SPDIF_UNSTBL (0x1 << 4)
+#define VID_FORMAT_CHG (0x1 << 3)
+#define AUD_CLK_CHG (0x1 << 2)
+#define VID_CLK_CHG (0x1 << 1)
+#define SW_INT (0x1 << 0)
+
+/* EXYNOS_DP_DEBUG_CTL */
+#define PLL_LOCK (0x1 << 4)
+#define F_PLL_LOCK (0x1 << 3)
+#define PLL_LOCK_CTRL (0x1 << 2)
+
+/* EXYNOS_DP_FUNC_EN_2 */
+#define SSC_FUNC_EN_N (0x1 << 7)
+#define AUX_FUNC_EN_N (0x1 << 2)
+#define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
+#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
+
+/* EXYNOS_DP_COMMON_INT_STA_4 */
+#define PSR_ACTIVE (0x1 << 7)
+#define PSR_INACTIVE (0x1 << 6)
+#define SPDIF_BI_PHASE_ERR (0x1 << 5)
+#define HOTPLUG_CHG (0x1 << 2)
+#define HPD_LOST (0x1 << 1)
+#define PLUG (0x1 << 0)
+
+/* EXYNOS_DP_INT_STA */
+#define INT_HPD (0x1 << 6)
+#define HW_TRAINING_FINISH (0x1 << 5)
+#define RPLY_RECEIV (0x1 << 1)
+#define AUX_ERR (0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_3 */
+#define HPD_STATUS (0x1 << 6)
+#define F_HPD (0x1 << 5)
+#define HPD_CTRL (0x1 << 4)
+#define HDCP_RDY (0x1 << 3)
+#define STRM_VALID (0x1 << 2)
+#define F_VALID (0x1 << 1)
+#define VALID_CTRL (0x1 << 0)
+
+/* EXYNOS_DP_AUX_HW_RETRY_CTL */
+#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8)
+#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3)
+#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3)
+#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3)
+#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
+#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
+#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0)
+
+/* EXYNOS_DP_AUX_CH_DEFER_CTL */
+#define DEFER_CTRL_EN (0x1 << 7)
+#define DEFER_COUNT(x) (((x) & 0x7f) << 0)
+
+#define COMMON_INT_MASK_1 (0)
+#define COMMON_INT_MASK_2 (0)
+#define COMMON_INT_MASK_3 (0)
+#define COMMON_INT_MASK_4 (0)
+#define INT_STA_MASK (0)
+
+/* EXYNOS_DP_BUFFER_DATA_CTL */
+#define BUF_CLR (0x1 << 7)
+#define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0)
+
+/* EXYNOS_DP_AUX_ADDR_7_0 */
+#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
+
+/* EXYNOS_DP_AUX_ADDR_15_8 */
+#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
+
+/* EXYNOS_DP_AUX_ADDR_19_16 */
+#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
+
+/* EXYNOS_DP_AUX_CH_CTL_1 */
+#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
+#define AUX_TX_COMM_MASK (0xf << 0)
+#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
+#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3)
+#define AUX_TX_COMM_MOT (0x1 << 2)
+#define AUX_TX_COMM_WRITE (0x0 << 0)
+#define AUX_TX_COMM_READ (0x1 << 0)
+
+/* EXYNOS_DP_AUX_CH_CTL_2 */
+#define ADDR_ONLY (0x1 << 1)
+#define AUX_EN (0x1 << 0)
+
+/* EXYNOS_DP_AUX_CH_STA */
+#define AUX_BUSY (0x1 << 4)
+#define AUX_STATUS_MASK (0xf << 0)
+
+/* EXYNOS_DP_AUX_RX_COMM */
+#define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
+#define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
+
+/* EXYNOS_DP_PHY_TEST */
+#define MACRO_RST (0x1 << 5)
+#define CH1_TEST (0x1 << 1)
+#define CH0_TEST (0x1 << 0)
+
+/* EXYNOS_DP_TRAINING_PTN_SET */
+#define SCRAMBLER_TYPE (0x1 << 9)
+#define HW_LINK_TRAINING_PATTERN (0x1 << 8)
+#define SCRAMBLING_DISABLE (0x1 << 5)
+#define SCRAMBLING_ENABLE (0x0 << 5)
+#define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2)
+#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2)
+#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
+#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2)
+#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0)
+#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
+#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
+#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0)
+
+/* EXYNOS_DP_TOTAL_LINE_CFG */
+#define TOTAL_LINE_CFG_L(x) ((x) & 0xff)
+#define TOTAL_LINE_CFG_H(x) ((((x) >> 8)) & 0xff)
+#define ACTIVE_LINE_CFG_L(x) ((x) & 0xff)
+#define ACTIVE_LINE_CFG_H(x) (((x) >> 8) & 0xff)
+#define TOTAL_PIXEL_CFG_L(x) ((x) & 0xff)
+#define TOTAL_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff)
+#define ACTIVE_PIXEL_CFG_L(x) ((x) & 0xff)
+#define ACTIVE_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff)
+
+#define H_F_PORCH_CFG_L(x) ((x) & 0xff)
+#define H_F_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
+#define H_SYNC_PORCH_CFG_L(x) ((x) & 0xff)
+#define H_SYNC_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
+#define H_B_PORCH_CFG_L(x) ((x) & 0xff)
+#define H_B_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
+
+/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
+#define MAX_PRE_EMPHASIS_REACH_0 (0x1 << 5)
+#define PRE_EMPHASIS_SET_0_SET(x) (((x) & 0x3) << 3)
+#define PRE_EMPHASIS_SET_0_GET(x) (((x) >> 3) & 0x3)
+#define PRE_EMPHASIS_SET_0_MASK (0x3 << 3)
+#define PRE_EMPHASIS_SET_0_SHIFT (3)
+#define PRE_EMPHASIS_SET_0_LEVEL_3 (0x3 << 3)
+#define PRE_EMPHASIS_SET_0_LEVEL_2 (0x2 << 3)
+#define PRE_EMPHASIS_SET_0_LEVEL_1 (0x1 << 3)
+#define PRE_EMPHASIS_SET_0_LEVEL_0 (0x0 << 3)
+#define MAX_DRIVE_CURRENT_REACH_0 (0x1 << 2)
+#define DRIVE_CURRENT_SET_0_MASK (0x3 << 0)
+#define DRIVE_CURRENT_SET_0_SET(x) (((x) & 0x3) << 0)
+#define DRIVE_CURRENT_SET_0_GET(x) (((x) >> 0) & 0x3)
+#define DRIVE_CURRENT_SET_0_LEVEL_3 (0x3 << 0)
+#define DRIVE_CURRENT_SET_0_LEVEL_2 (0x2 << 0)
+#define DRIVE_CURRENT_SET_0_LEVEL_1 (0x1 << 0)
+#define DRIVE_CURRENT_SET_0_LEVEL_0 (0x0 << 0)
+
+/* EXYNOS_DP_LN1_LINK_TRAINING_CTL */
+#define MAX_PRE_EMPHASIS_REACH_1 (0x1 << 5)
+#define PRE_EMPHASIS_SET_1_SET(x) (((x) & 0x3) << 3)
+#define PRE_EMPHASIS_SET_1_GET(x) (((x) >> 3) & 0x3)
+#define PRE_EMPHASIS_SET_1_MASK (0x3 << 3)
+#define PRE_EMPHASIS_SET_1_SHIFT (3)
+#define PRE_EMPHASIS_SET_1_LEVEL_3 (0x3 << 3)
+#define PRE_EMPHASIS_SET_1_LEVEL_2 (0x2 << 3)
+#define PRE_EMPHASIS_SET_1_LEVEL_1 (0x1 << 3)
+#define PRE_EMPHASIS_SET_1_LEVEL_0 (0x0 << 3)
+#define MAX_DRIVE_CURRENT_REACH_1 (0x1 << 2)
+#define DRIVE_CURRENT_SET_1_MASK (0x3 << 0)
+#define DRIVE_CURRENT_SET_1_SET(x) (((x) & 0x3) << 0)
+#define DRIVE_CURRENT_SET_1_GET(x) (((x) >> 0) & 0x3)
+#define DRIVE_CURRENT_SET_1_LEVEL_3 (0x3 << 0)
+#define DRIVE_CURRENT_SET_1_LEVEL_2 (0x2 << 0)
+#define DRIVE_CURRENT_SET_1_LEVEL_1 (0x1 << 0)
+#define DRIVE_CURRENT_SET_1_LEVEL_0 (0x0 << 0)
+
+/* EXYNOS_DP_LN2_LINK_TRAINING_CTL */
+#define MAX_PRE_EMPHASIS_REACH_2 (0x1 << 5)
+#define PRE_EMPHASIS_SET_2_SET(x) (((x) & 0x3) << 3)
+#define PRE_EMPHASIS_SET_2_GET(x) (((x) >> 3) & 0x3)
+#define PRE_EMPHASIS_SET_2_MASK (0x3 << 3)
+#define PRE_EMPHASIS_SET_2_SHIFT (3)
+#define PRE_EMPHASIS_SET_2_LEVEL_3 (0x3 << 3)
+#define PRE_EMPHASIS_SET_2_LEVEL_2 (0x2 << 3)
+#define PRE_EMPHASIS_SET_2_LEVEL_1 (0x1 << 3)
+#define PRE_EMPHASIS_SET_2_LEVEL_0 (0x0 << 3)
+#define MAX_DRIVE_CURRENT_REACH_2 (0x1 << 2)
+#define DRIVE_CURRENT_SET_2_MASK (0x3 << 0)
+#define DRIVE_CURRENT_SET_2_SET(x) (((x) & 0x3) << 0)
+#define DRIVE_CURRENT_SET_2_GET(x) (((x) >> 0) & 0x3)
+#define DRIVE_CURRENT_SET_2_LEVEL_3 (0x3 << 0)
+#define DRIVE_CURRENT_SET_2_LEVEL_2 (0x2 << 0)
+#define DRIVE_CURRENT_SET_2_LEVEL_1 (0x1 << 0)
+#define DRIVE_CURRENT_SET_2_LEVEL_0 (0x0 << 0)
+
+/* EXYNOS_DP_LN3_LINK_TRAINING_CTL */
+#define MAX_PRE_EMPHASIS_REACH_3 (0x1 << 5)
+#define PRE_EMPHASIS_SET_3_SET(x) (((x) & 0x3) << 3)
+#define PRE_EMPHASIS_SET_3_GET(x) (((x) >> 3) & 0x3)
+#define PRE_EMPHASIS_SET_3_MASK (0x3 << 3)
+#define PRE_EMPHASIS_SET_3_SHIFT (3)
+#define PRE_EMPHASIS_SET_3_LEVEL_3 (0x3 << 3)
+#define PRE_EMPHASIS_SET_3_LEVEL_2 (0x2 << 3)
+#define PRE_EMPHASIS_SET_3_LEVEL_1 (0x1 << 3)
+#define PRE_EMPHASIS_SET_3_LEVEL_0 (0x0 << 3)
+#define MAX_DRIVE_CURRENT_REACH_3 (0x1 << 2)
+#define DRIVE_CURRENT_SET_3_MASK (0x3 << 0)
+#define DRIVE_CURRENT_SET_3_SET(x) (((x) & 0x3) << 0)
+#define DRIVE_CURRENT_SET_3_GET(x) (((x) >> 0) & 0x3)
+#define DRIVE_CURRENT_SET_3_LEVEL_3 (0x3 << 0)
+#define DRIVE_CURRENT_SET_3_LEVEL_2 (0x2 << 0)
+#define DRIVE_CURRENT_SET_3_LEVEL_1 (0x1 << 0)
+#define DRIVE_CURRENT_SET_3_LEVEL_0 (0x0 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_10 */
+#define FORMAT_SEL (0x1 << 4)
+#define INTERACE_SCAN_CFG (0x1 << 2)
+#define INTERACE_SCAN_CFG_SHIFT (2)
+#define VSYNC_POLARITY_CFG (0x1 << 1)
+#define V_S_POLARITY_CFG_SHIFT (1)
+#define HSYNC_POLARITY_CFG (0x1 << 0)
+#define H_S_POLARITY_CFG_SHIFT (0)
+
+/* EXYNOS_DP_SOC_GENERAL_CTL */
+#define AUDIO_MODE_SPDIF_MODE (0x1 << 8)
+#define AUDIO_MODE_MASTER_MODE (0x0 << 8)
+#define MASTER_VIDEO_INTERLACE_EN (0x1 << 4)
+#define VIDEO_MASTER_CLK_SEL (0x1 << 2)
+#define VIDEO_MASTER_MODE_EN (0x1 << 1)
+#define VIDEO_MODE_MASK (0x1 << 0)
+#define VIDEO_MODE_SLAVE_MODE (0x1 << 0)
+#define VIDEO_MODE_MASTER_MODE (0x0 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_1 */
+#define VIDEO_EN (0x1 << 7)
+#define HDCP_VIDEO_MUTE (0x1 << 6)
+
+/* EXYNOS_DP_VIDEO_CTL_2 */
+#define IN_D_RANGE_MASK (0x1 << 7)
+#define IN_D_RANGE_SHIFT (7)
+#define IN_D_RANGE_CEA (0x1 << 7)
+#define IN_D_RANGE_VESA (0x0 << 7)
+#define IN_BPC_MASK (0x7 << 4)
+#define IN_BPC_SHIFT (4)
+#define IN_BPC_12_BITS (0x3 << 4)
+#define IN_BPC_10_BITS (0x2 << 4)
+#define IN_BPC_8_BITS (0x1 << 4)
+#define IN_BPC_6_BITS (0x0 << 4)
+#define IN_COLOR_F_MASK (0x3 << 0)
+#define IN_COLOR_F_SHIFT (0)
+#define IN_COLOR_F_YCBCR444 (0x2 << 0)
+#define IN_COLOR_F_YCBCR422 (0x1 << 0)
+#define IN_COLOR_F_RGB (0x0 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_3 */
+#define IN_YC_COEFFI_MASK (0x1 << 7)
+#define IN_YC_COEFFI_SHIFT (7)
+#define IN_YC_COEFFI_ITU709 (0x1 << 7)
+#define IN_YC_COEFFI_ITU601 (0x0 << 7)
+#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4)
+#define VID_CHK_UPDATE_TYPE_SHIFT (4)
+#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
+#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
+
+/* EXYNOS_DP_TEST_PATTERN_GEN_EN */
+#define TEST_PATTERN_GEN_EN (0x1 << 0)
+#define TEST_PATTERN_GEN_DIS (0x0 << 0)
+
+/* EXYNOS_DP_TEST_PATTERN_GEN_CTRL */
+#define TEST_PATTERN_MODE_COLOR_SQUARE (0x3 << 0)
+#define TEST_PATTERN_MODE_BALCK_WHITE_V_LINES (0x2 << 0)
+#define TEST_PATTERN_MODE_COLOR_RAMP (0x1 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_4 */
+#define BIST_EN (0x1 << 3)
+#define BIST_WIDTH_MASK (0x1 << 2)
+#define BIST_WIDTH_BAR_32_PIXEL (0x0 << 2)
+#define BIST_WIDTH_BAR_64_PIXEL (0x1 << 2)
+#define BIST_TYPE_MASK (0x3 << 0)
+#define BIST_TYPE_COLOR_BAR (0x0 << 0)
+#define BIST_TYPE_WHITE_GRAY_BLACK_BAR (0x1 << 0)
+#define BIST_TYPE_MOBILE_WHITE_BAR (0x2 << 0)
+
+/* EXYNOS_DP_SYS_CTL_1 */
+#define DET_STA (0x1 << 2)
+#define FORCE_DET (0x1 << 1)
+#define DET_CTRL (0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_2 */
+#define CHA_CRI(x) (((x) & 0xf) << 4)
+#define CHA_STA (0x1 << 2)
+#define FORCE_CHA (0x1 << 1)
+#define CHA_CTRL (0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_3 */
+#define HPD_STATUS (0x1 << 6)
+#define F_HPD (0x1 << 5)
+#define HPD_CTRL (0x1 << 4)
+#define HDCP_RDY (0x1 << 3)
+#define STRM_VALID (0x1 << 2)
+#define F_VALID (0x1 << 1)
+#define VALID_CTRL (0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_4 */
+#define FIX_M_AUD (0x1 << 4)
+#define ENHANCED (0x1 << 3)
+#define FIX_M_VID (0x1 << 2)
+#define M_VID_UPDATE_CTRL (0x3 << 0)
+
+/* EXYNOS_M_VID_X */
+#define M_VID0_CFG(x) ((x) & 0xff)
+#define M_VID1_CFG(x) (((x) >> 8) & 0xff)
+#define M_VID2_CFG(x) (((x) >> 16) & 0xff)
+
+/* EXYNOS_M_VID_X */
+#define N_VID0_CFG(x) ((x) & 0xff)
+#define N_VID1_CFG(x) (((x) >> 8) & 0xff)
+#define N_VID2_CFG(x) (((x) >> 16) & 0xff)
+
+/* DPCD_TRAINING_PATTERN_SET */
+#define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
+#define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
+#define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
+#define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
+#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
+
+/* Definition for DPCD Register */
+#define DPCD_DPCD_REV (0x0000)
+#define DPCD_MAX_LINK_RATE (0x0001)
+#define DPCD_MAX_LANE_COUNT (0x0002)
+#define DPCD_LINK_BW_SET (0x0100)
+#define DPCD_LANE_COUNT_SET (0x0101)
+#define DPCD_TRAINING_PATTERN_SET (0x0102)
+#define DPCD_TRAINING_LANE0_SET (0x0103)
+#define DPCD_LANE0_1_STATUS (0x0202)
+#define DPCD_LN_ALIGN_UPDATED (0x0204)
+#define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206)
+#define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207)
+#define DPCD_TEST_REQUEST (0x0218)
+#define DPCD_TEST_RESPONSE (0x0260)
+#define DPCD_TEST_EDID_CHECKSUM (0x0261)
+#define DPCD_SINK_POWER_STATE (0x0600)
+
+/* DPCD_TEST_REQUEST */
+#define DPCD_TEST_EDID_READ (0x1 << 2)
+
+/* DPCD_TEST_RESPONSE */
+#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
+
+/* DPCD_SINK_POWER_STATE */
+#define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
+#define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
+
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR (0x50)
+#define I2C_E_EDID_DEVICE_ADDR (0x30)
+#define EDID_BLOCK_LENGTH (0x80)
+#define EDID_HEADER_PATTERN (0x00)
+#define EDID_EXTENSION_FLAG (0x7e)
+#define EDID_CHECKSUM (0x7f)
+
+/* DPCD_LANE0_1_STATUS */
+#define DPCD_LANE1_SYMBOL_LOCKED (0x1 << 6)
+#define DPCD_LANE1_CHANNEL_EQ_DONE (0x1 << 5)
+#define DPCD_LANE1_CR_DONE (0x1 << 4)
+#define DPCD_LANE0_SYMBOL_LOCKED (0x1 << 2)
+#define DPCD_LANE0_CHANNEL_EQ_DONE (0x1 << 1)
+#define DPCD_LANE0_CR_DONE (0x1 << 0)
+
+/* DPCD_ADJUST_REQUEST_LANE0_1 */
+#define DPCD_PRE_EMPHASIS_LANE1_MASK (0x3 << 6)
+#define DPCD_PRE_EMPHASIS_LANE1(x) (((x) >> 6) & 0x3)
+#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_3 (0x3 << 6)
+#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_2 (0x2 << 6)
+#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_1 (0x1 << 6)
+#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_0 (0x0 << 6)
+#define DPCD_VOLTAGE_SWING_LANE1_MASK (0x3 << 4)
+#define DPCD_VOLTAGE_SWING_LANE1(x) (((x) >> 4) & 0x3)
+#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_3 (0x3 << 4)
+#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_2 (0x2 << 4)
+#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_1 (0x1 << 4)
+#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_0 (0x0 << 4)
+#define DPCD_PRE_EMPHASIS_LANE0_MASK (0x3 << 2)
+#define DPCD_PRE_EMPHASIS_LANE0(x) (((x) >> 2) & 0x3)
+#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_3 (0x3 << 2)
+#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_2 (0x2 << 2)
+#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_1 (0x1 << 2)
+#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_0 (0x0 << 2)
+#define DPCD_VOLTAGE_SWING_LANE0_MASK (0x3 << 0)
+#define DPCD_VOLTAGE_SWING_LANE0(x) (((x) >> 0) & 0x3)
+#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_3 (0x3 << 0)
+#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_2 (0x2 << 0)
+#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_1 (0x1 << 0)
+#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_0 (0x0 << 0)
+
+/* DPCD_ADJUST_REQUEST_LANE2_3 */
+#define DPCD_PRE_EMPHASIS_LANE2_MASK (0x3 << 6)
+#define DPCD_PRE_EMPHASIS_LANE2(x) (((x) >> 6) & 0x3)
+#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_3 (0x3 << 6)
+#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_2 (0x2 << 6)
+#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_1 (0x1 << 6)
+#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_0 (0x0 << 6)
+#define DPCD_VOLTAGE_SWING_LANE2_MASK (0x3 << 4)
+#define DPCD_VOLTAGE_SWING_LANE2(x) (((x) >> 4) & 0x3)
+#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_3 (0x3 << 4)
+#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_2 (0x2 << 4)
+#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_1 (0x1 << 4)
+#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_0 (0x0 << 4)
+#define DPCD_PRE_EMPHASIS_LANE3_MASK (0x3 << 2)
+#define DPCD_PRE_EMPHASIS_LANE3(x) (((x) >> 2) & 0x3)
+#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_3 (0x3 << 2)
+#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_2 (0x2 << 2)
+#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_1 (0x1 << 2)
+#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_0 (0x0 << 2)
+#define DPCD_VOLTAGE_SWING_LANE3_MASK (0x3 << 0)
+#define DPCD_VOLTAGE_SWING_LANE3(x) (((x) >> 0) & 0x3)
+#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_3 (0x3 << 0)
+#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_2 (0x2 << 0)
+#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_1 (0x1 << 0)
+#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_0 (0x0 << 0)
+
+/* DPCD_LANE_COUNT_SET */
+#define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
+#define DPCD_LN_COUNT_SET(x) ((x) & 0x1f)
+
+/* DPCD_LANE_ALIGN__STATUS_UPDATED */
+#define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
+#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
+#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
+
+/* DPCD_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_3 (0x3 << 3)
+#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_2 (0x2 << 3)
+#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_1 (0x1 << 3)
+#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 (0x0 << 3)
+#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_3 (0x3 << 0)
+#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_2 (0x2 << 0)
+#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_1 (0x1 << 0)
+#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0 (0x0 << 0)
+
+#define DPCD_REQ_ADJ_SWING (0x00)
+#define DPCD_REQ_ADJ_EMPHASIS (0x01)
+
+#define DP_LANE_STAT_CR_DONE (0x01 << 0)
+#define DP_LANE_STAT_CE_DONE (0x01 << 1)
+#define DP_LANE_STAT_SYM_LOCK (0x01 << 2)
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _DP_INFO_H
+#define _DP_INFO_H
+
+#define msleep(a) udelay(a * 1000)
+
+#define DP_TIMEOUT_LOOP_COUNT 100
+#define MAX_CR_LOOP 5
+#define MAX_EQ_LOOP 4
+
+#define EXYNOS_DP_SUCCESS 0
+
+enum {
+ DP_DISABLE,
+ DP_ENABLE,
+};
+
+struct edp_disp_info {
+ char *name;
+ unsigned int h_total;
+ unsigned int h_res;
+ unsigned int h_sync_width;
+ unsigned int h_back_porch;
+ unsigned int h_front_porch;
+ unsigned int v_total;
+ unsigned int v_res;
+ unsigned int v_sync_width;
+ unsigned int v_back_porch;
+ unsigned int v_front_porch;
+
+ unsigned int v_sync_rate;
+};
+
+struct edp_link_train_info {
+ unsigned int lt_status;
+
+ unsigned int ep_loop;
+ unsigned int cr_loop[4];
+
+};
+
+struct edp_video_info {
+ unsigned int master_mode;
+ unsigned int bist_mode;
+ unsigned int bist_pattern;
+
+ unsigned int h_sync_polarity;
+ unsigned int v_sync_polarity;
+ unsigned int interlaced;
+
+ unsigned int color_space;
+ unsigned int dynamic_range;
+ unsigned int ycbcr_coeff;
+ unsigned int color_depth;
+};
+
+struct edp_device_info {
+ struct edp_disp_info disp_info;
+ struct edp_link_train_info lt_info;
+ struct edp_video_info video_info;
+
+ /*below info get from panel during training*/
+ unsigned char lane_bw;
+ unsigned char lane_cnt;
+ unsigned char dpcd_rev;
+ /*support enhanced frame cap */
+ unsigned char dpcd_efc;
+};
+
+enum analog_power_block {
+ AUX_BLOCK,
+ CH0_BLOCK,
+ CH1_BLOCK,
+ CH2_BLOCK,
+ CH3_BLOCK,
+ ANALOG_TOTAL,
+ POWER_ALL
+};
+
+enum pll_status {
+ PLL_UNLOCKED = 0,
+ PLL_LOCKED
+};
+
+enum {
+ COLOR_RGB,
+ COLOR_YCBCR422,
+ COLOR_YCBCR444
+};
+
+enum {
+ VESA,
+ CEA
+};
+
+enum {
+ COLOR_YCBCR601,
+ COLOR_YCBCR709
+};
+
+enum {
+ COLOR_6,
+ COLOR_8,
+ COLOR_10,
+ COLOR_12
+};
+
+enum {
+ DP_LANE_BW_1_62 = 0x06,
+ DP_LANE_BW_2_70 = 0x0a,
+};
+
+enum {
+ DP_LANE_CNT_1 = 1,
+ DP_LANE_CNT_2 = 2,
+ DP_LANE_CNT_4 = 4,
+};
+
+enum {
+ DP_DPCD_REV_10 = 0x10,
+ DP_DPCD_REV_11 = 0x11,
+};
+
+enum {
+ DP_LT_NONE,
+ DP_LT_START,
+ DP_LT_CR,
+ DP_LT_ET,
+ DP_LT_FINISHED,
+ DP_LT_FAIL,
+};
+
+enum {
+ PRE_EMPHASIS_LEVEL_0,
+ PRE_EMPHASIS_LEVEL_1,
+ PRE_EMPHASIS_LEVEL_2,
+ PRE_EMPHASIS_LEVEL_3,
+};
+
+enum {
+ PRBS7,
+ D10_2,
+ TRAINING_PTN1,
+ TRAINING_PTN2,
+ DP_NONE
+};
+
+enum {
+ VOLTAGE_LEVEL_0,
+ VOLTAGE_LEVEL_1,
+ VOLTAGE_LEVEL_2,
+ VOLTAGE_LEVEL_3,
+};
+
+enum pattern_type {
+ NO_PATTERN,
+ COLOR_RAMP,
+ BALCK_WHITE_V_LINES,
+ COLOR_SQUARE,
+ INVALID_PATTERN,
+ COLORBAR_32,
+ COLORBAR_64,
+ WHITE_GRAY_BALCKBAR_32,
+ WHITE_GRAY_BALCKBAR_64,
+ MOBILE_WHITEBAR_32,
+ MOBILE_WHITEBAR_64
+};
+
+enum {
+ CALCULATED_M,
+ REGISTER_M
+};
+
+enum {
+ VIDEO_TIMING_FROM_CAPTURE,
+ VIDEO_TIMING_FROM_REGISTER
+};
+
+
+struct exynos_dp_platform_data {
+ struct edp_device_info *edp_dev_info;
+ void (*phy_enable)(unsigned int);
+};
+
+#ifdef CONFIG_EXYNOS_DP
+unsigned int exynos_init_dp(void);
+#else
+unsigned int exynos_init_dp(void)
+{
+ return 0;
+}
+#endif
+
+#endif /* _DP_INFO_H */
#define __ASM_ARM_ARCH_FB_H_
#ifndef __ASSEMBLY__
-struct exynos4_fb {
+struct exynos_fb {
unsigned int vidcon0;
unsigned int vidcon1;
unsigned int vidcon2;
unsigned char res15[156];
unsigned int dualrgb;
+ unsigned char res16[16];
+ unsigned int dp_mie_clkcon;
};
#endif
+/* LCD IF register offset */
+#define EXYNOS4_LCD_IF_BASE_OFFSET 0x0
+#define EXYNOS5_LCD_IF_BASE_OFFSET 0x20000
+
+static inline unsigned int exynos_fimd_get_base_offset(void)
+{
+ if (cpu_is_exynos5())
+ return EXYNOS5_LCD_IF_BASE_OFFSET;
+ else
+ return EXYNOS4_LCD_IF_BASE_OFFSET;
+}
+
/*
* Register offsets
*/
/* VIDTCON2 */
#define EXYNOS_VIDTCON2_LINEVAL(x) (((x) & 0x7ff) << 11)
#define EXYNOS_VIDTCON2_HOZVAL(x) (((x) & 0x7ff) << 0)
+#define EXYNOS_VIDTCON2_LINEVAL_E(x) ((((x) & 0x800) >> 11) << 23)
+#define EXYNOS_VIDTCON2_HOZVAL_E(x) ((((x) & 0x800) >> 11) << 22)
/* Window 0~4 Control - WINCONx */
#define EXYNOS_WINCON_DATAPATH_DMA (0 << 22)
#define EXYNOS_VIDOSD_TOP_Y(x) (((x) & 0x7ff) << 0)
#define EXYNOS_VIDOSD_RIGHT_X(x) (((x) & 0x7ff) << 11)
#define EXYNOS_VIDOSD_BOTTOM_Y(x) (((x) & 0x7ff) << 0)
+#define EXYNOS_VIDOSD_RIGHT_X_E(x) (((x) & 0x1) << 23)
+#define EXYNOS_VIDOSD_BOTTOM_Y_E(x) (((x) & 0x1) << 22)
/* VIDOSD0C, VIDOSDxD */
#define EXYNOS_VIDOSD_SIZE(x) (((x) & 0xffffff) << 0)
/* Buffer Size */
#define EXYNOS_VIDADDR_OFFSIZE(x) (((x) & 0x1fff) << 13)
#define EXYNOS_VIDADDR_PAGEWIDTH(x) (((x) & 0x1fff) << 0)
+#define EXYNOS_VIDADDR_OFFSIZE_E(x) ((((x) & 0x2000) >> 13) << 27)
+#define EXYNOS_VIDADDR_PAGEWIDTH_E(x) ((((x) & 0x2000) >> 13) << 26)
/* WIN Color Map */
#define EXYNOS_WINMAP_COLOR(x) ((x) & 0xffffff)
#define EXYNOS_I80START_TRIG (1 << 1)
#define EXYNOS_I80STATUS_TRIG_DONE (1 << 2)
+/* DP_MIE_CLKCON */
+#define EXYNOS_DP_MIE_DISABLE (0 << 0)
+#define EXYNOS_DP_CLK_ENABLE (1 << 1)
+#define EXYNOS_MIE_CLK_ENABLE (3 << 0)
+
#endif /* _REGS_FB_H */
struct s5p_gpio_bank y4;
struct s5p_gpio_bank y5;
struct s5p_gpio_bank y6;
- struct s5p_gpio_bank res1[0x980];
+ struct s5p_gpio_bank res1[0x3];
+ struct s5p_gpio_bank c4;
+ struct s5p_gpio_bank res2[0x48];
struct s5p_gpio_bank x0;
struct s5p_gpio_bank x1;
struct s5p_gpio_bank x2;
struct exynos5_gpio_part3 {
struct s5p_gpio_bank v0;
struct s5p_gpio_bank v1;
+ struct s5p_gpio_bank res1[0x1];
struct s5p_gpio_bank v2;
struct s5p_gpio_bank v3;
- struct s5p_gpio_bank res1[0x20];
+ struct s5p_gpio_bank res2[0x1];
struct s5p_gpio_bank v4;
};
#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0)
#define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0)
+
+void set_dp_phy_ctrl(unsigned int enable);
+
+#define EXYNOS_DP_PHY_ENABLE (1 << 0)
+
#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PWM_BACKLIGHT_H_
+#define _PWM_BACKLIGHT_H_
+
+struct pwm_backlight_data {
+ int pwm_id;
+ int period;
+ int max_brightness;
+ int brightness;
+};
+
+extern int exynos_pwm_backlight_init(struct pwm_backlight_data *pd);
+
+#endif /* _PWM_BACKLIGHT_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_SPL_H__
+#define __ASM_ARCH_EXYNOS_SPL_H__
+
+#include <asm/arch-exynos/dmc.h>
+
+enum boot_mode {
+ /*
+ * Assign the OM pin values for respective boot modes.
+ * Exynos4 does not support spi boot and the mmc boot OM
+ * pin values are the same across Exynos4 and Exynos5.
+ */
+ BOOT_MODE_MMC = 4,
+ BOOT_MODE_SERIAL = 20,
+ /* Boot based on Operating Mode pin settings */
+ BOOT_MODE_OM = 32,
+ BOOT_MODE_USB, /* Boot using USB download */
+};
+
+#ifndef __ASSEMBLY__
+/* Parameters of early board initialization in SPL */
+struct spl_machine_param {
+ /* Add fields as and when required */
+ u32 signature;
+ u32 version; /* Version number */
+ u32 size; /* Size of block */
+ /**
+ * Parameters we expect, in order, terminated with \0. Each parameter
+ * is a single character representing one 32-bit word in this
+ * structure.
+ *
+ * Valid characters in this string are:
+ *
+ * Code Name
+ * v mem_iv_size
+ * m mem_type
+ * u uboot_size
+ * b boot_source
+ * f frequency_mhz (memory frequency in MHz)
+ * a ARM clock frequency in MHz
+ * s serial base address
+ * i i2c base address for early access (meant for PMIC)
+ * r board rev GPIO numbers used to read board revision
+ * (lower halfword=bit 0, upper=bit 1)
+ * M Memory Manufacturer name
+ * \0 termination
+ */
+ char params[12]; /* Length must be word-aligned */
+ u32 mem_iv_size; /* Memory channel interleaving size */
+ enum ddr_mode mem_type; /* Type of on-board memory */
+ /*
+ * U-boot size - The iROM mmc copy function used by the SPL takes a
+ * block count paramter to describe the u-boot size unlike the spi
+ * boot copy function which just uses the u-boot size directly. Align
+ * the u-boot size to block size (512 bytes) when populating the SPL
+ * table only for mmc boot.
+ */
+ u32 uboot_size;
+ enum boot_mode boot_source; /* Boot device */
+ enum mem_manuf mem_manuf; /* Memory Manufacturer */
+ unsigned frequency_mhz; /* Frequency of memory in MHz */
+ unsigned arm_freq_mhz; /* ARM Frequency in MHz */
+ u32 serial_base; /* Serial base address */
+ u32 i2c_base; /* i2c base address */
+} __attribute__((__packed__));
+#endif
+
+/**
+ * Validate signature and return a pointer to the parameter table. If the
+ * signature is invalid, call panic() and never return.
+ *
+ * @return pointer to the parameter table if signature matched or never return.
+ */
+struct spl_machine_param *spl_get_machine_params(void);
+
+#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */
#ifndef _IMX_REGS_H
#define _IMX_REGS_H
+
+#define ARCH_MXC
+
/* ------------------------------------------------------------------------
* Motorola IMX system registers
* ------------------------------------------------------------------------
#ifndef __ASM_ARCH_MX25_GPIO_H
#define __ASM_ARCH_MX25_GPIO_H
-/* Converts a GPIO port number and the internal bit position
- * to the GPIO number
- */
-#define MXC_GPIO_PORT_TO_NUM(port, bit) (((port - 1) << 5) + (bit & 0x1f))
-
-/* GPIO registers */
-struct gpio_regs {
- u32 gpio_dr; /* data */
- u32 gpio_dir; /* direction */
- u32 psr; /* pad satus */
- u32 icr1; /* interrupt config 1 */
- u32 icr2; /* interrupt config 2 */
- u32 imr; /* interrupt mask */
- u32 isr; /* interrupt status */
- u32 edge_sel; /* edge select */
-};
+#include <asm/imx-common/gpio.h>
#endif
#endif
+#define ARCH_MXC
+
/* AIPS 1 */
#define IMX_AIPS1_BASE (0x43F00000)
#define IMX_MAX_BASE (0x43F04000)
--- /dev/null
+/*
+ * Copyright (C) 2012
+ * Philippe Reynes <tremyfr@yahoo.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __ASM_ARCH_MX27_GPIO_H
+#define __ASM_ARCH_MX27_GPIO_H
+
+/* GPIO registers */
+struct gpio_regs {
+ u32 gpio_dir; /* DDIR */
+ u32 ocr1;
+ u32 ocr2;
+ u32 iconfa1;
+ u32 iconfa2;
+ u32 iconfb1;
+ u32 iconfb2;
+ u32 gpio_dr; /* DR */
+ u32 gius;
+ u32 gpio_psr; /* SSR */
+ u32 icr1;
+ u32 icr2;
+ u32 imr;
+ u32 isr;
+ u32 gpr;
+ u32 swr;
+ u32 puen;
+ u32 res[0x2f];
+};
+
+/* This structure is used by the function imx_gpio_mode */
+struct gpio_port_regs {
+ struct gpio_regs port[6];
+};
+
+#endif
#ifndef _IMX_REGS_H
#define _IMX_REGS_H
+#include <asm/arch/regs-rtc.h>
+
#ifndef __ASSEMBLY__
extern void imx_gpio_mode (int gpio_mode);
#define PORTE 4
#define PORTF 5
-struct gpio_regs {
- struct {
- u32 ddir;
- u32 ocr1;
- u32 ocr2;
- u32 iconfa1;
- u32 iconfa2;
- u32 iconfb1;
- u32 iconfb2;
- u32 dr;
- u32 gius;
- u32 ssr;
- u32 icr1;
- u32 icr2;
- u32 imr;
- u32 isr;
- u32 gpr;
- u32 swr;
- u32 puen;
- u32 res[0x2f];
- } port[6];
-};
-
/* IIM Control Registers */
struct iim_regs {
u32 iim_stat;
#endif
+#define ARCH_MXC
+
#define IMX_IO_BASE 0x10000000
#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE)
#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE)
#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE)
+#define IMX_RTC_BASE (0x07000 + IMX_IO_BASE)
#define UART1_BASE (0x0a000 + IMX_IO_BASE)
#define UART2_BASE (0x0b000 + IMX_IO_BASE)
#define UART3_BASE (0x0c000 + IMX_IO_BASE)
#define TSTAT_CAPT (1 << 1) /* Capture event */
#define TSTAT_COMP 1 /* Compare event */
+#define GPIO1_BASE_ADDR 0x10015000
+#define GPIO2_BASE_ADDR 0x10015100
+#define GPIO3_BASE_ADDR 0x10015200
+#define GPIO4_BASE_ADDR 0x10015300
+#define GPIO5_BASE_ADDR 0x10015400
+#define GPIO6_BASE_ADDR 0x10015500
+
#define GPIO_PIN_MASK 0x1f
#define GPIO_PORT_SHIFT 5
--- /dev/null
+/*
+ * Freescale i.MX27 RTC Register Definitions
+ *
+ * Copyright (C) 2012 Philippe Reynes <tremyfr@yahoo.fr>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX27_REGS_RTC_H__
+#define __MX27_REGS_RTC_H__
+
+#ifndef __ASSEMBLY__
+struct rtc_regs {
+ u32 hourmin;
+ u32 seconds;
+ u32 alrm_hm;
+ u32 alrm_sec;
+ u32 rtcctl;
+ u32 rtcisr;
+ u32 rtcienr;
+ u32 stpwch;
+ u32 dayr;
+ u32 dayalarm;
+};
+#endif /* __ASSEMBLY__*/
+
+#endif /* __MX28_REGS_RTC_H__ */
#ifndef __ASM_ARCH_MX31_GPIO_H
#define __ASM_ARCH_MX31_GPIO_H
-/* GPIO Registers */
-struct gpio_regs {
- u32 gpio_dr;
- u32 gpio_dir;
- u32 gpio_psr;
-};
+#include <asm/imx-common/gpio.h>
#endif
#endif
+#define ARCH_MXC
+
#define __REG(x) (*((volatile u32 *)(x)))
#define __REG16(x) (*((volatile u16 *)(x)))
#define __REG8(x) (*((volatile u8 *)(x)))
#define IPU_CONF_PF_EN (1<<3)
#define IPU_CONF_ROT_EN (1<<2)
#define IPU_CONF_IC_EN (1<<1)
-#define IPU_CONF_SCI_EN (1<<0)
+#define IPU_CONF_CSI_EN (1<<0)
#define ARM_PPMRR 0x40000015
#define __ASM_ARCH_CLOCK_H
enum mxc_clock {
- MXC_ARM_CLK = 0,
+ MXC_ARM_CLK,
MXC_AHB_CLK,
MXC_IPG_CLK,
MXC_IPG_PERCLK,
MXC_FEC_CLK,
};
-unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
+enum mxc_main_clock {
+ CPU_CLK,
+ AHB_CLK,
+ IPG_CLK,
+ IPG_PER_CLK,
+ NFC_CLK,
+ USB_CLK,
+ HSP_CLK,
+};
+
+enum mxc_peri_clock {
+ UART1_BAUD,
+ UART2_BAUD,
+ UART3_BAUD,
+ SSI1_BAUD,
+ SSI2_BAUD,
+ CSI_BAUD,
+ MSHC_CLK,
+ ESDHC1_CLK,
+ ESDHC2_CLK,
+ ESDHC3_CLK,
+ SPDIF_CLK,
+ SPI1_CLK,
+ SPI2_CLK,
+};
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12)
#define MXC_CCM_CGR0_ECT_OFFSET 14
#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14)
-#define MXC_CCM_CGR0_EDI0_OFFSET 16
-#define MXC_CCM_CGR0_EDI0_MASK (0x3 << 16)
+#define MXC_CCM_CGR0_EDIO_OFFSET 16
+#define MXC_CCM_CGR0_EDIO_MASK (0x3 << 16)
#define MXC_CCM_CGR0_EMI_OFFSET 18
#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18)
#define MXC_CCM_CGR0_EPIT1_OFFSET 20
#ifndef __ASM_ARCH_MX35_GPIO_H
#define __ASM_ARCH_MX35_GPIO_H
-/* GPIO registers */
-struct gpio_regs {
- u32 gpio_dr; /* data */
- u32 gpio_dir; /* direction */
- u32 psr; /* pad satus */
- u32 icr1; /* interrupt config 1 */
- u32 icr2; /* interrupt config 2 */
- u32 imr; /* interrupt mask */
- u32 isr; /* interrupt status */
- u32 edge_sel; /* edge select */
-};
+#include <asm/imx-common/gpio.h>
#endif
#ifndef __ASM_ARCH_MX35_H
#define __ASM_ARCH_MX35_H
+#define ARCH_MXC
+
/*
* IRAM
*/
#define MMC_SDHC2_BASE_ADDR 0x53FB8000
#define MMC_SDHC3_BASE_ADDR 0x53FBC000
#define IPU_CTRL_BASE_ADDR 0x53FC0000
-#define GPIO3_BASE_ADDR 0x53FA4000
#define GPIO1_BASE_ADDR 0x53FCC000
#define GPIO2_BASE_ADDR 0x53FD0000
#define SDMA_BASE_ADDR 0x53FD4000
#define IPU_CONF_PF_EN (1<<3)
#define IPU_CONF_ROT_EN (1<<2)
#define IPU_CONF_IC_EN (1<<1)
-#define IPU_CONF_SCI_EN (1<<0)
+#define IPU_CONF_CSI_EN (1<<0)
/*
* CSPI register definitions
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
-enum mxc_main_clocks {
- CPU_CLK,
- AHB_CLK,
- IPG_CLK,
- IPG_PER_CLK,
- NFC_CLK,
- USB_CLK,
- HSP_CLK,
-};
-
-enum mxc_peri_clocks {
- UART1_BAUD,
- UART2_BAUD,
- UART3_BAUD,
- SSI1_BAUD,
- SSI2_BAUD,
- CSI_BAUD,
- MSHC_CLK,
- ESDHC1_CLK,
- ESDHC2_CLK,
- ESDHC3_CLK,
- SPDIF_CLK,
- SPI1_CLK,
- SPI2_CLK,
-};
-
/* Clock Control Module (CCM) registers */
struct ccm_regs {
u32 ccmr; /* Control */
MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780),
MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784),
MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788),
-
- MX35_PIN_RTS2_UART3_RXD_MUX = _MXC_BUILD_NON_GPIO_PIN(0x1a0, 0x5e4),
- MX35_PIN_CTS2_UART3_TXD_MUX = _MXC_BUILD_NON_GPIO_PIN(0x1a4, 0x5e8),
} iomux_pin_name_t;
#endif
u32 get_cpu_rev(void);
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
-void sdelay(unsigned long);
#endif
MXC_PERIPH_CLK,
};
-unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
-
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
#ifndef __ASM_ARCH_MX5_GPIO_H
#define __ASM_ARCH_MX5_GPIO_H
-/* GPIO registers */
-struct gpio_regs {
- u32 gpio_dr;
- u32 gpio_dir;
- u32 gpio_psr;
-};
+#include <asm/imx-common/gpio.h>
#endif
#ifndef __ASM_ARCH_MX5_IMX_REGS_H__
#define __ASM_ARCH_MX5_IMX_REGS_H__
+#define ARCH_MXC
+
#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
#define IPU_SOC_BASE_ADDR 0x40000000
u32 simr;
};
+struct srtc_regs {
+ u32 lpscmr; /* 0x00 */
+ u32 lpsclr; /* 0x04 */
+ u32 lpsar; /* 0x08 */
+ u32 lpsmcr; /* 0x0c */
+ u32 lpcr; /* 0x10 */
+ u32 lpsr; /* 0x14 */
+ u32 lppdr; /* 0x18 */
+ u32 lpgr; /* 0x1c */
+ u32 hpcmr; /* 0x20 */
+ u32 hpclr; /* 0x24 */
+ u32 hpamr; /* 0x28 */
+ u32 hpalr; /* 0x2c */
+ u32 hpcr; /* 0x30 */
+ u32 hpisr; /* 0x34 */
+ u32 hpienr; /* 0x38 */
+};
+
/* CSPI registers */
struct cspi_regs {
u32 rxdata;
--- /dev/null
+/*
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2009-2012 Genesi USA, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * The vast majority of this file is taken from the Linux kernel at
+ * commit 5d23b39
+ */
+
+#ifndef __IOMUX_MX51_H__
+#define __IOMUX_MX51_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+#define PAD_CTL_DVS (1 << 13)
+#define PAD_CTL_INPUT_DDR (1 << 9)
+#define PAD_CTL_HYS (1 << 8)
+
+#define PAD_CTL_PKE (1 << 7)
+#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
+#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
+
+#define PAD_CTL_ODE (1 << 3)
+
+#define PAD_CTL_DSE_LOW (0 << 1)
+#define PAD_CTL_DSE_MED (1 << 1)
+#define PAD_CTL_DSE_HIGH (2 << 1)
+#define PAD_CTL_DSE_MAX (3 << 1)
+
+#define PAD_CTL_SRE_FAST (1 << 0)
+#define PAD_CTL_SRE_SLOW (0 << 0)
+
+/* Pad control groupings */
+#define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_HYS)
+#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_HYS)
+#define MX51_USBH1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_HYS | PAD_CTL_PUE)
+#define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
+#define MX51_SDHCI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
+ PAD_CTL_SRE_FAST | PAD_CTL_DVS)
+#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
+
+#define __NA_ 0x000
+
+/*
+ * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/* PAD MUX ALT INPSE PATH PADCTRL */
+enum {
+ MX51_PAD_EIM_D16__USBH2_DATA0 = IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_D17__USBH2_DATA1 = IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_D18__USBH2_DATA2 = IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_D19__USBH2_DATA3 = IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_D20__USBH2_DATA4 = IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_D27__GPIO2_9 = IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A24__USBH2_CLK = IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_A25__USBH2_DIR = IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_A26__GPIO2_20 = IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS0__GPIO2_25 = IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_CS2__SD1_CD = IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+ MX51_PAD_EIM_CS3__GPIO2_28 = IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_CS4__GPIO2_29 = IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_WE_B__PATA_DIOW = IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RE_B__PATA_DIOR = IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_ALE__PATA_BUFFER_EN = IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CLE__PATA_RESET_B = IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_WP_B__PATA_DMACK = IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RB0__PATA_DMARQ = IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RB1__PATA_IORDY = IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO_NAND__PATA_INTRQ = IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS2__PATA_CS_0 = IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS3__PATA_CS_1 = IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS4__PATA_DA_0 = IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS5__PATA_DA_1 = IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS6__PATA_DA_2 = IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D15__PATA_DATA15 = IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D14__PATA_DATA14 = IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D13__PATA_DATA13 = IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D12__PATA_DATA12 = IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D11__PATA_DATA11 = IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D10__PATA_DATA10 = IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D9__PATA_DATA9 = IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D8__PATA_DATA8 = IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D7__PATA_DATA7 = IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D6__PATA_DATA6 = IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D5__PATA_DATA5 = IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D4__PATA_DATA4 = IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D3__PATA_DATA3 = IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D2__PATA_DATA2 = IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D1__PATA_DATA1 = IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D0__PATA_DATA0 = IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_CSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_CSPI1_SS0__GPIO4_24 = IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSPI1_SS1__GPIO4_25 = IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_USBH1_CLK__USBH1_CLK = IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+ MX51_PAD_USBH1_DIR__USBH1_DIR = IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+ MX51_PAD_USBH1_STP__USBH1_STP = IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+ MX51_PAD_USBH1_STP__GPIO1_27 = IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_USBH1_NXT__USBH1_NXT = IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+ MX51_PAD_USBH1_DATA0__USBH1_DATA0 = IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+ MX51_PAD_USBH1_DATA1__USBH1_DATA1 = IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+ MX51_PAD_USBH1_DATA2__USBH1_DATA2 = IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+ MX51_PAD_USBH1_DATA3__USBH1_DATA3 = IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+ MX51_PAD_USBH1_DATA4__USBH1_DATA4 = IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+ MX51_PAD_USBH1_DATA5__USBH1_DATA5 = IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+ MX51_PAD_USBH1_DATA6__USBH1_DATA6 = IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+ MX51_PAD_USBH1_DATA7__USBH1_DATA7 = IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+ MX51_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+ MX51_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
+ MX51_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+ MX51_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+ MX51_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+ MX51_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+ MX51_PAD_GPIO1_0__SD1_CD = IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+ MX51_PAD_GPIO1_1__SD1_WP = IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+ MX51_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+ MX51_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
+ MX51_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+ MX51_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+ MX51_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+ MX51_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+ MX51_PAD_GPIO1_3__GPIO1_3 = IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_GPIO1_5__GPIO1_5 = IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_GPIO1_6__GPIO1_6 = IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_GPIO1_7__SD2_WP = IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+ MX51_PAD_GPIO1_8__SD2_CD = IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX51_H__ */
#ifndef __ASM_ARCH_MX6_GPIO_H
#define __ASM_ARCH_MX6_GPIO_H
-/* GPIO registers */
-struct gpio_regs {
- u32 gpio_dr;
- u32 gpio_dir;
- u32 gpio_psr;
-};
+#include <asm/imx-common/gpio.h>
#endif /* __ASM_ARCH_MX6_GPIO_H */
#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
#define __ASM_ARCH_MX6_IMX_REGS_H__
+#define ARCH_MXC
+
#define CONFIG_SYS_CACHELINE_SIZE 32
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define IMX_IIM_BASE OCOTP_BASE_ADDR
#define FEC_QUIRK_ENET_MAC
-#define GPIO_NUMBER(port, index) ((((port)-1)*32)+((index)&31))
-
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
u32 daisy[104]; /* 0x7b0..94c */
};
+struct src_regs {
+ u32 scr; /* 0x00 */
+ u32 sbmr1; /* 0x04 */
+ u32 srsr; /* 0x08 */
+ u32 reserved1; /* 0x0c */
+ u32 reserved2; /* 0x10 */
+ u32 sisr; /* 0x14 */
+ u32 simr; /* 0x18 */
+ u32 sbmr2; /* 0x1c */
+ u32 gpr1; /* 0x20 */
+ u32 gpr2; /* 0x24 */
+ u32 gpr3; /* 0x28 */
+ u32 gpr4; /* 0x2c */
+ u32 gpr5; /* 0x30 */
+ u32 gpr6; /* 0x34 */
+ u32 gpr7; /* 0x38 */
+ u32 gpr8; /* 0x3c */
+ u32 gpr9; /* 0x40 */
+ u32 gpr10; /* 0x44 */
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
--- /dev/null
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_IOMUX_H__
+#define __ASM_ARCH_IOMUX_H__
+/*
+ * IOMUXC_GPR13 bit fields
+ */
+#define IOMUXC_GPR13_SDMA_STOP_REQ (1<<30)
+#define IOMUXC_GPR13_CAN2_STOP_REQ (1<<29)
+#define IOMUXC_GPR13_CAN1_STOP_REQ (1<<28)
+#define IOMUXC_GPR13_ENET_STOP_REQ (1<<27)
+#define IOMUXC_GPR13_SATA_PHY_8_MASK (7<<24)
+#define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f<<19)
+#define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16
+#define IOMUXC_GPR13_SATA_PHY_6_MASK (7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+#define IOMUXC_GPR13_SATA_SPEED_MASK (1<<15)
+#define IOMUXC_GPR13_SATA_PHY_5_MASK (1<<14)
+#define IOMUXC_GPR13_SATA_PHY_4_MASK (7<<11)
+#define IOMUXC_GPR13_SATA_PHY_3_MASK (0x1f<<7)
+#define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2)
+#define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0)
+
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0b000<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (0b001<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (0b010<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (0b011<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (0b100<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (0b101<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (0b110<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (0b111<<24)
+
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010<<19)
+
+#define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15)
+#define IOMUXC_GPR13_SATA_SPEED_3G (1<<15)
+
+#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED (0<<14)
+#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED (1<<14)
+
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16 (0<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16 (1<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 (2<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16 (3<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11)
+
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0b0000<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (0b0001<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (0b0010<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (0b0011<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (0b0100<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (0b0101<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (0b0110<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (0b0111<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (0b1000<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (0b1001<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0b1010<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0b1011<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0b1100<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0b1101<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0b1110<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0b1111<<7)
+
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0b00000<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (0b00001<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (0b00010<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (0b00011<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (0b00100<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (0b00101<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (0b00110<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (0b00111<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (0b01000<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (0b01001<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0b01010<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0b01011<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0b01100<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0b01101<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0b01110<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0b01111<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0b10000<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0b10001<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0b10010<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0b10011<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0b10100<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0b10101<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0b10110<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0b10111<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0b11000<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0b11001<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0b11010<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0b11011<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0b11100<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0b11101<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0b11110<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0b11111<<2)
+
+#define IOMUXC_GPR13_SATA_PHY_1_FAST 0
+#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1
+#define IOMUXC_GPR13_SATA_PHY_1_SLOW 2
+
+#define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \
+ |IOMUXC_GPR13_SATA_PHY_7_MASK \
+ |IOMUXC_GPR13_SATA_PHY_6_MASK \
+ |IOMUXC_GPR13_SATA_SPEED_MASK \
+ |IOMUXC_GPR13_SATA_PHY_5_MASK \
+ |IOMUXC_GPR13_SATA_PHY_4_MASK \
+ |IOMUXC_GPR13_SATA_PHY_3_MASK \
+ |IOMUXC_GPR13_SATA_PHY_2_MASK \
+ |IOMUXC_GPR13_SATA_PHY_1_MASK)
+#endif /* __ASM_ARCH_IOMUX_H__ */
#define __DMA_H__
#include <linux/list.h>
+#include <linux/compiler.h>
#ifndef CONFIG_ARCH_DMA_PIO_WORDS
#define DMA_PIO_WORDS 15
dma_addr_t address;
void *buffer;
struct list_head node;
-};
+} __aligned(MXS_DMA_ALIGNMENT);
/**
* MXS DMA channel
#include <asm/arch/regs-apbh.h>
#include <asm/arch/regs-base.h>
#include <asm/arch/regs-bch.h>
-#include <asm/arch/regs-clkctrl.h>
+#include <asm/arch/regs-clkctrl-mx28.h>
#include <asm/arch/regs-digctl.h>
#include <asm/arch/regs-gpmi.h>
#include <asm/arch/regs-i2c.h>
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mx28_apbh_regs {
- mx28_reg_32(hw_apbh_ctrl0)
- mx28_reg_32(hw_apbh_ctrl1)
- mx28_reg_32(hw_apbh_ctrl2)
- mx28_reg_32(hw_apbh_channel_ctrl)
- mx28_reg_32(hw_apbh_devsel)
- mx28_reg_32(hw_apbh_dma_burst_size)
- mx28_reg_32(hw_apbh_debug)
+struct mxs_apbh_regs {
+ mxs_reg_32(hw_apbh_ctrl0)
+ mxs_reg_32(hw_apbh_ctrl1)
+ mxs_reg_32(hw_apbh_ctrl2)
+ mxs_reg_32(hw_apbh_channel_ctrl)
+ mxs_reg_32(hw_apbh_devsel)
+ mxs_reg_32(hw_apbh_dma_burst_size)
+ mxs_reg_32(hw_apbh_debug)
uint32_t reserved[36];
union {
struct {
- mx28_reg_32(hw_apbh_ch_curcmdar)
- mx28_reg_32(hw_apbh_ch_nxtcmdar)
- mx28_reg_32(hw_apbh_ch_cmd)
- mx28_reg_32(hw_apbh_ch_bar)
- mx28_reg_32(hw_apbh_ch_sema)
- mx28_reg_32(hw_apbh_ch_debug1)
- mx28_reg_32(hw_apbh_ch_debug2)
+ mxs_reg_32(hw_apbh_ch_curcmdar)
+ mxs_reg_32(hw_apbh_ch_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch_cmd)
+ mxs_reg_32(hw_apbh_ch_bar)
+ mxs_reg_32(hw_apbh_ch_sema)
+ mxs_reg_32(hw_apbh_ch_debug1)
+ mxs_reg_32(hw_apbh_ch_debug2)
} ch[16];
struct {
- mx28_reg_32(hw_apbh_ch0_curcmdar)
- mx28_reg_32(hw_apbh_ch0_nxtcmdar)
- mx28_reg_32(hw_apbh_ch0_cmd)
- mx28_reg_32(hw_apbh_ch0_bar)
- mx28_reg_32(hw_apbh_ch0_sema)
- mx28_reg_32(hw_apbh_ch0_debug1)
- mx28_reg_32(hw_apbh_ch0_debug2)
- mx28_reg_32(hw_apbh_ch1_curcmdar)
- mx28_reg_32(hw_apbh_ch1_nxtcmdar)
- mx28_reg_32(hw_apbh_ch1_cmd)
- mx28_reg_32(hw_apbh_ch1_bar)
- mx28_reg_32(hw_apbh_ch1_sema)
- mx28_reg_32(hw_apbh_ch1_debug1)
- mx28_reg_32(hw_apbh_ch1_debug2)
- mx28_reg_32(hw_apbh_ch2_curcmdar)
- mx28_reg_32(hw_apbh_ch2_nxtcmdar)
- mx28_reg_32(hw_apbh_ch2_cmd)
- mx28_reg_32(hw_apbh_ch2_bar)
- mx28_reg_32(hw_apbh_ch2_sema)
- mx28_reg_32(hw_apbh_ch2_debug1)
- mx28_reg_32(hw_apbh_ch2_debug2)
- mx28_reg_32(hw_apbh_ch3_curcmdar)
- mx28_reg_32(hw_apbh_ch3_nxtcmdar)
- mx28_reg_32(hw_apbh_ch3_cmd)
- mx28_reg_32(hw_apbh_ch3_bar)
- mx28_reg_32(hw_apbh_ch3_sema)
- mx28_reg_32(hw_apbh_ch3_debug1)
- mx28_reg_32(hw_apbh_ch3_debug2)
- mx28_reg_32(hw_apbh_ch4_curcmdar)
- mx28_reg_32(hw_apbh_ch4_nxtcmdar)
- mx28_reg_32(hw_apbh_ch4_cmd)
- mx28_reg_32(hw_apbh_ch4_bar)
- mx28_reg_32(hw_apbh_ch4_sema)
- mx28_reg_32(hw_apbh_ch4_debug1)
- mx28_reg_32(hw_apbh_ch4_debug2)
- mx28_reg_32(hw_apbh_ch5_curcmdar)
- mx28_reg_32(hw_apbh_ch5_nxtcmdar)
- mx28_reg_32(hw_apbh_ch5_cmd)
- mx28_reg_32(hw_apbh_ch5_bar)
- mx28_reg_32(hw_apbh_ch5_sema)
- mx28_reg_32(hw_apbh_ch5_debug1)
- mx28_reg_32(hw_apbh_ch5_debug2)
- mx28_reg_32(hw_apbh_ch6_curcmdar)
- mx28_reg_32(hw_apbh_ch6_nxtcmdar)
- mx28_reg_32(hw_apbh_ch6_cmd)
- mx28_reg_32(hw_apbh_ch6_bar)
- mx28_reg_32(hw_apbh_ch6_sema)
- mx28_reg_32(hw_apbh_ch6_debug1)
- mx28_reg_32(hw_apbh_ch6_debug2)
- mx28_reg_32(hw_apbh_ch7_curcmdar)
- mx28_reg_32(hw_apbh_ch7_nxtcmdar)
- mx28_reg_32(hw_apbh_ch7_cmd)
- mx28_reg_32(hw_apbh_ch7_bar)
- mx28_reg_32(hw_apbh_ch7_sema)
- mx28_reg_32(hw_apbh_ch7_debug1)
- mx28_reg_32(hw_apbh_ch7_debug2)
- mx28_reg_32(hw_apbh_ch8_curcmdar)
- mx28_reg_32(hw_apbh_ch8_nxtcmdar)
- mx28_reg_32(hw_apbh_ch8_cmd)
- mx28_reg_32(hw_apbh_ch8_bar)
- mx28_reg_32(hw_apbh_ch8_sema)
- mx28_reg_32(hw_apbh_ch8_debug1)
- mx28_reg_32(hw_apbh_ch8_debug2)
- mx28_reg_32(hw_apbh_ch9_curcmdar)
- mx28_reg_32(hw_apbh_ch9_nxtcmdar)
- mx28_reg_32(hw_apbh_ch9_cmd)
- mx28_reg_32(hw_apbh_ch9_bar)
- mx28_reg_32(hw_apbh_ch9_sema)
- mx28_reg_32(hw_apbh_ch9_debug1)
- mx28_reg_32(hw_apbh_ch9_debug2)
- mx28_reg_32(hw_apbh_ch10_curcmdar)
- mx28_reg_32(hw_apbh_ch10_nxtcmdar)
- mx28_reg_32(hw_apbh_ch10_cmd)
- mx28_reg_32(hw_apbh_ch10_bar)
- mx28_reg_32(hw_apbh_ch10_sema)
- mx28_reg_32(hw_apbh_ch10_debug1)
- mx28_reg_32(hw_apbh_ch10_debug2)
- mx28_reg_32(hw_apbh_ch11_curcmdar)
- mx28_reg_32(hw_apbh_ch11_nxtcmdar)
- mx28_reg_32(hw_apbh_ch11_cmd)
- mx28_reg_32(hw_apbh_ch11_bar)
- mx28_reg_32(hw_apbh_ch11_sema)
- mx28_reg_32(hw_apbh_ch11_debug1)
- mx28_reg_32(hw_apbh_ch11_debug2)
- mx28_reg_32(hw_apbh_ch12_curcmdar)
- mx28_reg_32(hw_apbh_ch12_nxtcmdar)
- mx28_reg_32(hw_apbh_ch12_cmd)
- mx28_reg_32(hw_apbh_ch12_bar)
- mx28_reg_32(hw_apbh_ch12_sema)
- mx28_reg_32(hw_apbh_ch12_debug1)
- mx28_reg_32(hw_apbh_ch12_debug2)
- mx28_reg_32(hw_apbh_ch13_curcmdar)
- mx28_reg_32(hw_apbh_ch13_nxtcmdar)
- mx28_reg_32(hw_apbh_ch13_cmd)
- mx28_reg_32(hw_apbh_ch13_bar)
- mx28_reg_32(hw_apbh_ch13_sema)
- mx28_reg_32(hw_apbh_ch13_debug1)
- mx28_reg_32(hw_apbh_ch13_debug2)
- mx28_reg_32(hw_apbh_ch14_curcmdar)
- mx28_reg_32(hw_apbh_ch14_nxtcmdar)
- mx28_reg_32(hw_apbh_ch14_cmd)
- mx28_reg_32(hw_apbh_ch14_bar)
- mx28_reg_32(hw_apbh_ch14_sema)
- mx28_reg_32(hw_apbh_ch14_debug1)
- mx28_reg_32(hw_apbh_ch14_debug2)
- mx28_reg_32(hw_apbh_ch15_curcmdar)
- mx28_reg_32(hw_apbh_ch15_nxtcmdar)
- mx28_reg_32(hw_apbh_ch15_cmd)
- mx28_reg_32(hw_apbh_ch15_bar)
- mx28_reg_32(hw_apbh_ch15_sema)
- mx28_reg_32(hw_apbh_ch15_debug1)
- mx28_reg_32(hw_apbh_ch15_debug2)
+ mxs_reg_32(hw_apbh_ch0_curcmdar)
+ mxs_reg_32(hw_apbh_ch0_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch0_cmd)
+ mxs_reg_32(hw_apbh_ch0_bar)
+ mxs_reg_32(hw_apbh_ch0_sema)
+ mxs_reg_32(hw_apbh_ch0_debug1)
+ mxs_reg_32(hw_apbh_ch0_debug2)
+ mxs_reg_32(hw_apbh_ch1_curcmdar)
+ mxs_reg_32(hw_apbh_ch1_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch1_cmd)
+ mxs_reg_32(hw_apbh_ch1_bar)
+ mxs_reg_32(hw_apbh_ch1_sema)
+ mxs_reg_32(hw_apbh_ch1_debug1)
+ mxs_reg_32(hw_apbh_ch1_debug2)
+ mxs_reg_32(hw_apbh_ch2_curcmdar)
+ mxs_reg_32(hw_apbh_ch2_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch2_cmd)
+ mxs_reg_32(hw_apbh_ch2_bar)
+ mxs_reg_32(hw_apbh_ch2_sema)
+ mxs_reg_32(hw_apbh_ch2_debug1)
+ mxs_reg_32(hw_apbh_ch2_debug2)
+ mxs_reg_32(hw_apbh_ch3_curcmdar)
+ mxs_reg_32(hw_apbh_ch3_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch3_cmd)
+ mxs_reg_32(hw_apbh_ch3_bar)
+ mxs_reg_32(hw_apbh_ch3_sema)
+ mxs_reg_32(hw_apbh_ch3_debug1)
+ mxs_reg_32(hw_apbh_ch3_debug2)
+ mxs_reg_32(hw_apbh_ch4_curcmdar)
+ mxs_reg_32(hw_apbh_ch4_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch4_cmd)
+ mxs_reg_32(hw_apbh_ch4_bar)
+ mxs_reg_32(hw_apbh_ch4_sema)
+ mxs_reg_32(hw_apbh_ch4_debug1)
+ mxs_reg_32(hw_apbh_ch4_debug2)
+ mxs_reg_32(hw_apbh_ch5_curcmdar)
+ mxs_reg_32(hw_apbh_ch5_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch5_cmd)
+ mxs_reg_32(hw_apbh_ch5_bar)
+ mxs_reg_32(hw_apbh_ch5_sema)
+ mxs_reg_32(hw_apbh_ch5_debug1)
+ mxs_reg_32(hw_apbh_ch5_debug2)
+ mxs_reg_32(hw_apbh_ch6_curcmdar)
+ mxs_reg_32(hw_apbh_ch6_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch6_cmd)
+ mxs_reg_32(hw_apbh_ch6_bar)
+ mxs_reg_32(hw_apbh_ch6_sema)
+ mxs_reg_32(hw_apbh_ch6_debug1)
+ mxs_reg_32(hw_apbh_ch6_debug2)
+ mxs_reg_32(hw_apbh_ch7_curcmdar)
+ mxs_reg_32(hw_apbh_ch7_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch7_cmd)
+ mxs_reg_32(hw_apbh_ch7_bar)
+ mxs_reg_32(hw_apbh_ch7_sema)
+ mxs_reg_32(hw_apbh_ch7_debug1)
+ mxs_reg_32(hw_apbh_ch7_debug2)
+ mxs_reg_32(hw_apbh_ch8_curcmdar)
+ mxs_reg_32(hw_apbh_ch8_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch8_cmd)
+ mxs_reg_32(hw_apbh_ch8_bar)
+ mxs_reg_32(hw_apbh_ch8_sema)
+ mxs_reg_32(hw_apbh_ch8_debug1)
+ mxs_reg_32(hw_apbh_ch8_debug2)
+ mxs_reg_32(hw_apbh_ch9_curcmdar)
+ mxs_reg_32(hw_apbh_ch9_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch9_cmd)
+ mxs_reg_32(hw_apbh_ch9_bar)
+ mxs_reg_32(hw_apbh_ch9_sema)
+ mxs_reg_32(hw_apbh_ch9_debug1)
+ mxs_reg_32(hw_apbh_ch9_debug2)
+ mxs_reg_32(hw_apbh_ch10_curcmdar)
+ mxs_reg_32(hw_apbh_ch10_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch10_cmd)
+ mxs_reg_32(hw_apbh_ch10_bar)
+ mxs_reg_32(hw_apbh_ch10_sema)
+ mxs_reg_32(hw_apbh_ch10_debug1)
+ mxs_reg_32(hw_apbh_ch10_debug2)
+ mxs_reg_32(hw_apbh_ch11_curcmdar)
+ mxs_reg_32(hw_apbh_ch11_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch11_cmd)
+ mxs_reg_32(hw_apbh_ch11_bar)
+ mxs_reg_32(hw_apbh_ch11_sema)
+ mxs_reg_32(hw_apbh_ch11_debug1)
+ mxs_reg_32(hw_apbh_ch11_debug2)
+ mxs_reg_32(hw_apbh_ch12_curcmdar)
+ mxs_reg_32(hw_apbh_ch12_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch12_cmd)
+ mxs_reg_32(hw_apbh_ch12_bar)
+ mxs_reg_32(hw_apbh_ch12_sema)
+ mxs_reg_32(hw_apbh_ch12_debug1)
+ mxs_reg_32(hw_apbh_ch12_debug2)
+ mxs_reg_32(hw_apbh_ch13_curcmdar)
+ mxs_reg_32(hw_apbh_ch13_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch13_cmd)
+ mxs_reg_32(hw_apbh_ch13_bar)
+ mxs_reg_32(hw_apbh_ch13_sema)
+ mxs_reg_32(hw_apbh_ch13_debug1)
+ mxs_reg_32(hw_apbh_ch13_debug2)
+ mxs_reg_32(hw_apbh_ch14_curcmdar)
+ mxs_reg_32(hw_apbh_ch14_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch14_cmd)
+ mxs_reg_32(hw_apbh_ch14_bar)
+ mxs_reg_32(hw_apbh_ch14_sema)
+ mxs_reg_32(hw_apbh_ch14_debug1)
+ mxs_reg_32(hw_apbh_ch14_debug2)
+ mxs_reg_32(hw_apbh_ch15_curcmdar)
+ mxs_reg_32(hw_apbh_ch15_nxtcmdar)
+ mxs_reg_32(hw_apbh_ch15_cmd)
+ mxs_reg_32(hw_apbh_ch15_bar)
+ mxs_reg_32(hw_apbh_ch15_sema)
+ mxs_reg_32(hw_apbh_ch15_debug1)
+ mxs_reg_32(hw_apbh_ch15_debug2)
};
};
- mx28_reg_32(hw_apbh_version)
+ mxs_reg_32(hw_apbh_version)
};
#endif
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mx28_bch_regs {
- mx28_reg_32(hw_bch_ctrl)
- mx28_reg_32(hw_bch_status0)
- mx28_reg_32(hw_bch_mode)
- mx28_reg_32(hw_bch_encodeptr)
- mx28_reg_32(hw_bch_dataptr)
- mx28_reg_32(hw_bch_metaptr)
+struct mxs_bch_regs {
+ mxs_reg_32(hw_bch_ctrl)
+ mxs_reg_32(hw_bch_status0)
+ mxs_reg_32(hw_bch_mode)
+ mxs_reg_32(hw_bch_encodeptr)
+ mxs_reg_32(hw_bch_dataptr)
+ mxs_reg_32(hw_bch_metaptr)
uint32_t reserved[4];
- mx28_reg_32(hw_bch_layoutselect)
- mx28_reg_32(hw_bch_flash0layout0)
- mx28_reg_32(hw_bch_flash0layout1)
- mx28_reg_32(hw_bch_flash1layout0)
- mx28_reg_32(hw_bch_flash1layout1)
- mx28_reg_32(hw_bch_flash2layout0)
- mx28_reg_32(hw_bch_flash2layout1)
- mx28_reg_32(hw_bch_flash3layout0)
- mx28_reg_32(hw_bch_flash3layout1)
- mx28_reg_32(hw_bch_dbgkesread)
- mx28_reg_32(hw_bch_dbgcsferead)
- mx28_reg_32(hw_bch_dbgsyndegread)
- mx28_reg_32(hw_bch_dbgahbmread)
- mx28_reg_32(hw_bch_blockname)
- mx28_reg_32(hw_bch_version)
+ mxs_reg_32(hw_bch_layoutselect)
+ mxs_reg_32(hw_bch_flash0layout0)
+ mxs_reg_32(hw_bch_flash0layout1)
+ mxs_reg_32(hw_bch_flash1layout0)
+ mxs_reg_32(hw_bch_flash1layout1)
+ mxs_reg_32(hw_bch_flash2layout0)
+ mxs_reg_32(hw_bch_flash2layout1)
+ mxs_reg_32(hw_bch_flash3layout0)
+ mxs_reg_32(hw_bch_flash3layout1)
+ mxs_reg_32(hw_bch_dbgkesread)
+ mxs_reg_32(hw_bch_dbgcsferead)
+ mxs_reg_32(hw_bch_dbgsyndegread)
+ mxs_reg_32(hw_bch_dbgahbmread)
+ mxs_reg_32(hw_bch_blockname)
+ mxs_reg_32(hw_bch_version)
};
#endif
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mx28_clkctrl_regs {
- mx28_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
- mx28_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */
- mx28_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */
- mx28_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */
- mx28_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */
- mx28_reg_32(hw_clkctrl_cpu) /* 0x50 */
- mx28_reg_32(hw_clkctrl_hbus) /* 0x60 */
- mx28_reg_32(hw_clkctrl_xbus) /* 0x70 */
- mx28_reg_32(hw_clkctrl_xtal) /* 0x80 */
- mx28_reg_32(hw_clkctrl_ssp0) /* 0x90 */
- mx28_reg_32(hw_clkctrl_ssp1) /* 0xa0 */
- mx28_reg_32(hw_clkctrl_ssp2) /* 0xb0 */
- mx28_reg_32(hw_clkctrl_ssp3) /* 0xc0 */
- mx28_reg_32(hw_clkctrl_gpmi) /* 0xd0 */
- mx28_reg_32(hw_clkctrl_spdif) /* 0xe0 */
- mx28_reg_32(hw_clkctrl_emi) /* 0xf0 */
- mx28_reg_32(hw_clkctrl_saif0) /* 0x100 */
- mx28_reg_32(hw_clkctrl_saif1) /* 0x110 */
- mx28_reg_32(hw_clkctrl_lcdif) /* 0x120 */
- mx28_reg_32(hw_clkctrl_etm) /* 0x130 */
- mx28_reg_32(hw_clkctrl_enet) /* 0x140 */
- mx28_reg_32(hw_clkctrl_hsadc) /* 0x150 */
- mx28_reg_32(hw_clkctrl_flexcan) /* 0x160 */
+struct mxs_clkctrl_regs {
+ mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
+ mxs_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */
+ mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */
+ mxs_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */
+ mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */
+ mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */
+ mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */
+ mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */
+ mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */
+ mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */
+ mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */
+ mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */
+ mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */
+ mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */
+ mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */
+ mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */
+ mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */
+ mxs_reg_32(hw_clkctrl_saif1) /* 0x110 */
+ mxs_reg_32(hw_clkctrl_lcdif) /* 0x120 */
+ mxs_reg_32(hw_clkctrl_etm) /* 0x130 */
+ mxs_reg_32(hw_clkctrl_enet) /* 0x140 */
+ mxs_reg_32(hw_clkctrl_hsadc) /* 0x150 */
+ mxs_reg_32(hw_clkctrl_flexcan) /* 0x160 */
uint32_t reserved[16];
- mx28_reg_8(hw_clkctrl_frac0) /* 0x1b0 */
- mx28_reg_8(hw_clkctrl_frac1) /* 0x1c0 */
- mx28_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */
- mx28_reg_32(hw_clkctrl_reset) /* 0x1e0 */
- mx28_reg_32(hw_clkctrl_status) /* 0x1f0 */
- mx28_reg_32(hw_clkctrl_version) /* 0x200 */
+ mxs_reg_8(hw_clkctrl_frac0) /* 0x1b0 */
+ mxs_reg_8(hw_clkctrl_frac1) /* 0x1c0 */
+ mxs_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */
+ mxs_reg_32(hw_clkctrl_reset) /* 0x1e0 */
+ mxs_reg_32(hw_clkctrl_status) /* 0x1f0 */
+ mxs_reg_32(hw_clkctrl_version) /* 0x200 */
};
#endif
/*
- * Freescale i.MX28 Register Accessors
+ * Freescale i.MXS Register Accessors
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
*/
-#ifndef __MX28_REGS_COMMON_H__
-#define __MX28_REGS_COMMON_H__
+#ifndef __MXS_REGS_COMMON_H__
+#define __MXS_REGS_COMMON_H__
/*
- * The i.MX28 has interesting feature when it comes to register access. There
+ * The i.MXS has interesting feature when it comes to register access. There
* are four kinds of access to one particular register. Those are:
*
* 1) Common read/write access. To use this mode, just write to the address of
*
*/
-#define __mx28_reg_8(name) \
+#define __mxs_reg_8(name) \
uint8_t name[4]; \
uint8_t name##_set[4]; \
uint8_t name##_clr[4]; \
uint8_t name##_tog[4]; \
-#define __mx28_reg_32(name) \
+#define __mxs_reg_32(name) \
uint32_t name; \
uint32_t name##_set; \
uint32_t name##_clr; \
uint32_t name##_tog;
-struct mx28_register_8 {
- __mx28_reg_8(reg)
+struct mxs_register_8 {
+ __mxs_reg_8(reg)
};
-struct mx28_register_32 {
- __mx28_reg_32(reg)
+struct mxs_register_32 {
+ __mxs_reg_32(reg)
};
-#define mx28_reg_8(name) \
+#define mxs_reg_8(name) \
union { \
- struct { __mx28_reg_8(name) }; \
- struct mx28_register_8 name##_reg; \
+ struct { __mxs_reg_8(name) }; \
+ struct mxs_register_8 name##_reg; \
};
-#define mx28_reg_32(name) \
+#define mxs_reg_32(name) \
union { \
- struct { __mx28_reg_32(name) }; \
- struct mx28_register_32 name##_reg; \
+ struct { __mxs_reg_32(name) }; \
+ struct mxs_register_32 name##_reg; \
};
-#endif /* __MX28_REGS_COMMON_H__ */
+#endif /* __MXS_REGS_COMMON_H__ */
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mx28_digctl_regs {
- mx28_reg_32(hw_digctl_ctrl) /* 0x000 */
- mx28_reg_32(hw_digctl_status) /* 0x010 */
- mx28_reg_32(hw_digctl_hclkcount) /* 0x020 */
- mx28_reg_32(hw_digctl_ramctrl) /* 0x030 */
- mx28_reg_32(hw_digctl_emi_status) /* 0x040 */
- mx28_reg_32(hw_digctl_read_margin) /* 0x050 */
+struct mxs_digctl_regs {
+ mxs_reg_32(hw_digctl_ctrl) /* 0x000 */
+ mxs_reg_32(hw_digctl_status) /* 0x010 */
+ mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */
+ mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */
+ mxs_reg_32(hw_digctl_emi_status) /* 0x040 */
+ mxs_reg_32(hw_digctl_read_margin) /* 0x050 */
uint32_t hw_digctl_writeonce; /* 0x060 */
uint32_t reserved_writeonce[3];
- mx28_reg_32(hw_digctl_bist_ctl) /* 0x070 */
- mx28_reg_32(hw_digctl_bist_status) /* 0x080 */
+ mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */
+ mxs_reg_32(hw_digctl_bist_status) /* 0x080 */
uint32_t hw_digctl_entropy; /* 0x090 */
uint32_t reserved_entropy[3];
uint32_t hw_digctl_entropy_latched; /* 0x0a0 */
uint32_t reserved1[4];
- mx28_reg_32(hw_digctl_microseconds) /* 0x0c0 */
+ mxs_reg_32(hw_digctl_microseconds) /* 0x0c0 */
uint32_t hw_digctl_dbgrd; /* 0x0d0 */
uint32_t reserved_hw_digctl_dbgrd[3];
uint32_t hw_digctl_dbg; /* 0x0e0 */
uint32_t reserved2[4];
- mx28_reg_32(hw_digctl_usb_loopback) /* 0x100 */
- mx28_reg_32(hw_digctl_ocram_status0) /* 0x110 */
- mx28_reg_32(hw_digctl_ocram_status1) /* 0x120 */
- mx28_reg_32(hw_digctl_ocram_status2) /* 0x130 */
- mx28_reg_32(hw_digctl_ocram_status3) /* 0x140 */
- mx28_reg_32(hw_digctl_ocram_status4) /* 0x150 */
- mx28_reg_32(hw_digctl_ocram_status5) /* 0x160 */
- mx28_reg_32(hw_digctl_ocram_status6) /* 0x170 */
- mx28_reg_32(hw_digctl_ocram_status7) /* 0x180 */
- mx28_reg_32(hw_digctl_ocram_status8) /* 0x190 */
- mx28_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */
- mx28_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */
- mx28_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */
- mx28_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */
- mx28_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */
+ mxs_reg_32(hw_digctl_usb_loopback) /* 0x100 */
+ mxs_reg_32(hw_digctl_ocram_status0) /* 0x110 */
+ mxs_reg_32(hw_digctl_ocram_status1) /* 0x120 */
+ mxs_reg_32(hw_digctl_ocram_status2) /* 0x130 */
+ mxs_reg_32(hw_digctl_ocram_status3) /* 0x140 */
+ mxs_reg_32(hw_digctl_ocram_status4) /* 0x150 */
+ mxs_reg_32(hw_digctl_ocram_status5) /* 0x160 */
+ mxs_reg_32(hw_digctl_ocram_status6) /* 0x170 */
+ mxs_reg_32(hw_digctl_ocram_status7) /* 0x180 */
+ mxs_reg_32(hw_digctl_ocram_status8) /* 0x190 */
+ mxs_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */
+ mxs_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */
+ mxs_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */
+ mxs_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */
+ mxs_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */
uint32_t reserved3[36];
uint32_t reserved_hw_digctl_scratch1[3];
uint32_t hw_digctl_armcache; /* 0x2a0 */
uint32_t reserved_hw_digctl_armcache[3];
- mx28_reg_32(hw_digctl_debug_trap) /* 0x2b0 */
+ mxs_reg_32(hw_digctl_debug_trap) /* 0x2b0 */
uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */
uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3];
uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */
};
#endif
+/* Product code identification */
+#define HW_DIGCTL_CHIPID_MASK (0xffff << 16)
+#define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16)
+
#endif /* __MX28_REGS_DIGCTL_H__ */
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mx28_gpmi_regs {
- mx28_reg_32(hw_gpmi_ctrl0)
- mx28_reg_32(hw_gpmi_compare)
- mx28_reg_32(hw_gpmi_eccctrl)
- mx28_reg_32(hw_gpmi_ecccount)
- mx28_reg_32(hw_gpmi_payload)
- mx28_reg_32(hw_gpmi_auxiliary)
- mx28_reg_32(hw_gpmi_ctrl1)
- mx28_reg_32(hw_gpmi_timing0)
- mx28_reg_32(hw_gpmi_timing1)
+struct mxs_gpmi_regs {
+ mxs_reg_32(hw_gpmi_ctrl0)
+ mxs_reg_32(hw_gpmi_compare)
+ mxs_reg_32(hw_gpmi_eccctrl)
+ mxs_reg_32(hw_gpmi_ecccount)
+ mxs_reg_32(hw_gpmi_payload)
+ mxs_reg_32(hw_gpmi_auxiliary)
+ mxs_reg_32(hw_gpmi_ctrl1)
+ mxs_reg_32(hw_gpmi_timing0)
+ mxs_reg_32(hw_gpmi_timing1)
uint32_t reserved[4];
- mx28_reg_32(hw_gpmi_data)
- mx28_reg_32(hw_gpmi_stat)
- mx28_reg_32(hw_gpmi_debug)
- mx28_reg_32(hw_gpmi_version)
+ mxs_reg_32(hw_gpmi_data)
+ mxs_reg_32(hw_gpmi_stat)
+ mxs_reg_32(hw_gpmi_debug)
+ mxs_reg_32(hw_gpmi_version)
};
#endif
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mx28_i2c_regs {
- mx28_reg_32(hw_i2c_ctrl0)
- mx28_reg_32(hw_i2c_timing0)
- mx28_reg_32(hw_i2c_timing1)
- mx28_reg_32(hw_i2c_timing2)
- mx28_reg_32(hw_i2c_ctrl1)
- mx28_reg_32(hw_i2c_stat)
- mx28_reg_32(hw_i2c_queuectrl)
- mx28_reg_32(hw_i2c_queuestat)
- mx28_reg_32(hw_i2c_queuecmd)
- mx28_reg_32(hw_i2c_queuedata)
- mx28_reg_32(hw_i2c_data)
- mx28_reg_32(hw_i2c_debug0)
- mx28_reg_32(hw_i2c_debug1)
- mx28_reg_32(hw_i2c_version)
+struct mxs_i2c_regs {
+ mxs_reg_32(hw_i2c_ctrl0)
+ mxs_reg_32(hw_i2c_timing0)
+ mxs_reg_32(hw_i2c_timing1)
+ mxs_reg_32(hw_i2c_timing2)
+ mxs_reg_32(hw_i2c_ctrl1)
+ mxs_reg_32(hw_i2c_stat)
+ mxs_reg_32(hw_i2c_queuectrl)
+ mxs_reg_32(hw_i2c_queuestat)
+ mxs_reg_32(hw_i2c_queuecmd)
+ mxs_reg_32(hw_i2c_queuedata)
+ mxs_reg_32(hw_i2c_data)
+ mxs_reg_32(hw_i2c_debug0)
+ mxs_reg_32(hw_i2c_debug1)
+ mxs_reg_32(hw_i2c_version)
};
#endif
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mx28_lcdif_regs {
- mx28_reg_32(hw_lcdif_ctrl) /* 0x00 */
- mx28_reg_32(hw_lcdif_ctrl1) /* 0x10 */
- mx28_reg_32(hw_lcdif_ctrl2) /* 0x20 */
- mx28_reg_32(hw_lcdif_transfer_count) /* 0x30 */
- mx28_reg_32(hw_lcdif_cur_buf) /* 0x40 */
- mx28_reg_32(hw_lcdif_next_buf) /* 0x50 */
- mx28_reg_32(hw_lcdif_timing) /* 0x60 */
- mx28_reg_32(hw_lcdif_vdctrl0) /* 0x70 */
- mx28_reg_32(hw_lcdif_vdctrl1) /* 0x80 */
- mx28_reg_32(hw_lcdif_vdctrl2) /* 0x90 */
- mx28_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */
- mx28_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */
- mx28_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */
- mx28_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */
- mx28_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */
- mx28_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */
- mx28_reg_32(hw_lcdif_dvictrl4) /* 0x100 */
- mx28_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */
- mx28_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */
- mx28_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
- mx28_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
- mx28_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
- mx28_reg_32(hw_lcdif_csc_offset) /* 0x160 */
- mx28_reg_32(hw_lcdif_csc_limit) /* 0x170 */
- mx28_reg_32(hw_lcdif_data) /* 0x180 */
- mx28_reg_32(hw_lcdif_bm_error_stat) /* 0x190 */
- mx28_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
- mx28_reg_32(hw_lcdif_lcdif_stat) /* 0x1b0 */
- mx28_reg_32(hw_lcdif_version) /* 0x1c0 */
- mx28_reg_32(hw_lcdif_debug0) /* 0x1d0 */
- mx28_reg_32(hw_lcdif_debug1) /* 0x1e0 */
- mx28_reg_32(hw_lcdif_debug2) /* 0x1f0 */
+struct mxs_lcdif_regs {
+ mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
+ mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
+ mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
+ mxs_reg_32(hw_lcdif_transfer_count) /* 0x30 */
+ mxs_reg_32(hw_lcdif_cur_buf) /* 0x40 */
+ mxs_reg_32(hw_lcdif_next_buf) /* 0x50 */
+ mxs_reg_32(hw_lcdif_timing) /* 0x60 */
+ mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */
+ mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */
+ mxs_reg_32(hw_lcdif_vdctrl2) /* 0x90 */
+ mxs_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */
+ mxs_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */
+ mxs_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */
+ mxs_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */
+ mxs_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */
+ mxs_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */
+ mxs_reg_32(hw_lcdif_dvictrl4) /* 0x100 */
+ mxs_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */
+ mxs_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */
+ mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
+ mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
+ mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
+ mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
+ mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
+ mxs_reg_32(hw_lcdif_data) /* 0x180 */
+ mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x190 */
+ mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
+ mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1b0 */
+ mxs_reg_32(hw_lcdif_version) /* 0x1c0 */
+ mxs_reg_32(hw_lcdif_debug0) /* 0x1d0 */
+ mxs_reg_32(hw_lcdif_debug1) /* 0x1e0 */
+ mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
};
#endif
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mx28_lradc_regs {
- mx28_reg_32(hw_lradc_ctrl0);
- mx28_reg_32(hw_lradc_ctrl1);
- mx28_reg_32(hw_lradc_ctrl2);
- mx28_reg_32(hw_lradc_ctrl3);
- mx28_reg_32(hw_lradc_status);
- mx28_reg_32(hw_lradc_ch0);
- mx28_reg_32(hw_lradc_ch1);
- mx28_reg_32(hw_lradc_ch2);
- mx28_reg_32(hw_lradc_ch3);
- mx28_reg_32(hw_lradc_ch4);
- mx28_reg_32(hw_lradc_ch5);
- mx28_reg_32(hw_lradc_ch6);
- mx28_reg_32(hw_lradc_ch7);
- mx28_reg_32(hw_lradc_delay0);
- mx28_reg_32(hw_lradc_delay1);
- mx28_reg_32(hw_lradc_delay2);
- mx28_reg_32(hw_lradc_delay3);
- mx28_reg_32(hw_lradc_debug0);
- mx28_reg_32(hw_lradc_debug1);
- mx28_reg_32(hw_lradc_conversion);
- mx28_reg_32(hw_lradc_ctrl4);
- mx28_reg_32(hw_lradc_treshold0);
- mx28_reg_32(hw_lradc_treshold1);
- mx28_reg_32(hw_lradc_version);
+struct mxs_lradc_regs {
+ mxs_reg_32(hw_lradc_ctrl0);
+ mxs_reg_32(hw_lradc_ctrl1);
+ mxs_reg_32(hw_lradc_ctrl2);
+ mxs_reg_32(hw_lradc_ctrl3);
+ mxs_reg_32(hw_lradc_status);
+ mxs_reg_32(hw_lradc_ch0);
+ mxs_reg_32(hw_lradc_ch1);
+ mxs_reg_32(hw_lradc_ch2);
+ mxs_reg_32(hw_lradc_ch3);
+ mxs_reg_32(hw_lradc_ch4);
+ mxs_reg_32(hw_lradc_ch5);
+ mxs_reg_32(hw_lradc_ch6);
+ mxs_reg_32(hw_lradc_ch7);
+ mxs_reg_32(hw_lradc_delay0);
+ mxs_reg_32(hw_lradc_delay1);
+ mxs_reg_32(hw_lradc_delay2);
+ mxs_reg_32(hw_lradc_delay3);
+ mxs_reg_32(hw_lradc_debug0);
+ mxs_reg_32(hw_lradc_debug1);
+ mxs_reg_32(hw_lradc_conversion);
+ mxs_reg_32(hw_lradc_ctrl4);
+ mxs_reg_32(hw_lradc_treshold0);
+ mxs_reg_32(hw_lradc_treshold1);
+ mxs_reg_32(hw_lradc_version);
};
#endif
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mx28_ocotp_regs {
- mx28_reg_32(hw_ocotp_ctrl) /* 0x0 */
- mx28_reg_32(hw_ocotp_data) /* 0x10 */
- mx28_reg_32(hw_ocotp_cust0) /* 0x20 */
- mx28_reg_32(hw_ocotp_cust1) /* 0x30 */
- mx28_reg_32(hw_ocotp_cust2) /* 0x40 */
- mx28_reg_32(hw_ocotp_cust3) /* 0x50 */
- mx28_reg_32(hw_ocotp_crypto0) /* 0x60 */
- mx28_reg_32(hw_ocotp_crypto1) /* 0x70 */
- mx28_reg_32(hw_ocotp_crypto2) /* 0x80 */
- mx28_reg_32(hw_ocotp_crypto3) /* 0x90 */
- mx28_reg_32(hw_ocotp_hwcap0) /* 0xa0 */
- mx28_reg_32(hw_ocotp_hwcap1) /* 0xb0 */
- mx28_reg_32(hw_ocotp_hwcap2) /* 0xc0 */
- mx28_reg_32(hw_ocotp_hwcap3) /* 0xd0 */
- mx28_reg_32(hw_ocotp_hwcap4) /* 0xe0 */
- mx28_reg_32(hw_ocotp_hwcap5) /* 0xf0 */
- mx28_reg_32(hw_ocotp_swcap) /* 0x100 */
- mx28_reg_32(hw_ocotp_custcap) /* 0x110 */
- mx28_reg_32(hw_ocotp_lock) /* 0x120 */
- mx28_reg_32(hw_ocotp_ops0) /* 0x130 */
- mx28_reg_32(hw_ocotp_ops1) /* 0x140 */
- mx28_reg_32(hw_ocotp_ops2) /* 0x150 */
- mx28_reg_32(hw_ocotp_ops3) /* 0x160 */
- mx28_reg_32(hw_ocotp_un0) /* 0x170 */
- mx28_reg_32(hw_ocotp_un1) /* 0x180 */
- mx28_reg_32(hw_ocotp_un2) /* 0x190 */
- mx28_reg_32(hw_ocotp_rom0) /* 0x1a0 */
- mx28_reg_32(hw_ocotp_rom1) /* 0x1b0 */
- mx28_reg_32(hw_ocotp_rom2) /* 0x1c0 */
- mx28_reg_32(hw_ocotp_rom3) /* 0x1d0 */
- mx28_reg_32(hw_ocotp_rom4) /* 0x1e0 */
- mx28_reg_32(hw_ocotp_rom5) /* 0x1f0 */
- mx28_reg_32(hw_ocotp_rom6) /* 0x200 */
- mx28_reg_32(hw_ocotp_rom7) /* 0x210 */
- mx28_reg_32(hw_ocotp_srk0) /* 0x220 */
- mx28_reg_32(hw_ocotp_srk1) /* 0x230 */
- mx28_reg_32(hw_ocotp_srk2) /* 0x240 */
- mx28_reg_32(hw_ocotp_srk3) /* 0x250 */
- mx28_reg_32(hw_ocotp_srk4) /* 0x260 */
- mx28_reg_32(hw_ocotp_srk5) /* 0x270 */
- mx28_reg_32(hw_ocotp_srk6) /* 0x280 */
- mx28_reg_32(hw_ocotp_srk7) /* 0x290 */
- mx28_reg_32(hw_ocotp_version) /* 0x2a0 */
+struct mxs_ocotp_regs {
+ mxs_reg_32(hw_ocotp_ctrl) /* 0x0 */
+ mxs_reg_32(hw_ocotp_data) /* 0x10 */
+ mxs_reg_32(hw_ocotp_cust0) /* 0x20 */
+ mxs_reg_32(hw_ocotp_cust1) /* 0x30 */
+ mxs_reg_32(hw_ocotp_cust2) /* 0x40 */
+ mxs_reg_32(hw_ocotp_cust3) /* 0x50 */
+ mxs_reg_32(hw_ocotp_crypto0) /* 0x60 */
+ mxs_reg_32(hw_ocotp_crypto1) /* 0x70 */
+ mxs_reg_32(hw_ocotp_crypto2) /* 0x80 */
+ mxs_reg_32(hw_ocotp_crypto3) /* 0x90 */
+ mxs_reg_32(hw_ocotp_hwcap0) /* 0xa0 */
+ mxs_reg_32(hw_ocotp_hwcap1) /* 0xb0 */
+ mxs_reg_32(hw_ocotp_hwcap2) /* 0xc0 */
+ mxs_reg_32(hw_ocotp_hwcap3) /* 0xd0 */
+ mxs_reg_32(hw_ocotp_hwcap4) /* 0xe0 */
+ mxs_reg_32(hw_ocotp_hwcap5) /* 0xf0 */
+ mxs_reg_32(hw_ocotp_swcap) /* 0x100 */
+ mxs_reg_32(hw_ocotp_custcap) /* 0x110 */
+ mxs_reg_32(hw_ocotp_lock) /* 0x120 */
+ mxs_reg_32(hw_ocotp_ops0) /* 0x130 */
+ mxs_reg_32(hw_ocotp_ops1) /* 0x140 */
+ mxs_reg_32(hw_ocotp_ops2) /* 0x150 */
+ mxs_reg_32(hw_ocotp_ops3) /* 0x160 */
+ mxs_reg_32(hw_ocotp_un0) /* 0x170 */
+ mxs_reg_32(hw_ocotp_un1) /* 0x180 */
+ mxs_reg_32(hw_ocotp_un2) /* 0x190 */
+ mxs_reg_32(hw_ocotp_rom0) /* 0x1a0 */
+ mxs_reg_32(hw_ocotp_rom1) /* 0x1b0 */
+ mxs_reg_32(hw_ocotp_rom2) /* 0x1c0 */
+ mxs_reg_32(hw_ocotp_rom3) /* 0x1d0 */
+ mxs_reg_32(hw_ocotp_rom4) /* 0x1e0 */
+ mxs_reg_32(hw_ocotp_rom5) /* 0x1f0 */
+ mxs_reg_32(hw_ocotp_rom6) /* 0x200 */
+ mxs_reg_32(hw_ocotp_rom7) /* 0x210 */
+ mxs_reg_32(hw_ocotp_srk0) /* 0x220 */
+ mxs_reg_32(hw_ocotp_srk1) /* 0x230 */
+ mxs_reg_32(hw_ocotp_srk2) /* 0x240 */
+ mxs_reg_32(hw_ocotp_srk3) /* 0x250 */
+ mxs_reg_32(hw_ocotp_srk4) /* 0x260 */
+ mxs_reg_32(hw_ocotp_srk5) /* 0x270 */
+ mxs_reg_32(hw_ocotp_srk6) /* 0x280 */
+ mxs_reg_32(hw_ocotp_srk7) /* 0x290 */
+ mxs_reg_32(hw_ocotp_version) /* 0x2a0 */
};
#endif
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mx28_pinctrl_regs {
- mx28_reg_32(hw_pinctrl_ctrl) /* 0x0 */
+struct mxs_pinctrl_regs {
+ mxs_reg_32(hw_pinctrl_ctrl) /* 0x0 */
uint32_t reserved1[60];
- mx28_reg_32(hw_pinctrl_muxsel0) /* 0x100 */
- mx28_reg_32(hw_pinctrl_muxsel1) /* 0x110 */
- mx28_reg_32(hw_pinctrl_muxsel2) /* 0x120 */
- mx28_reg_32(hw_pinctrl_muxsel3) /* 0x130 */
- mx28_reg_32(hw_pinctrl_muxsel4) /* 0x140 */
- mx28_reg_32(hw_pinctrl_muxsel5) /* 0x150 */
- mx28_reg_32(hw_pinctrl_muxsel6) /* 0x160 */
- mx28_reg_32(hw_pinctrl_muxsel7) /* 0x170 */
- mx28_reg_32(hw_pinctrl_muxsel8) /* 0x180 */
- mx28_reg_32(hw_pinctrl_muxsel9) /* 0x190 */
- mx28_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */
- mx28_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */
- mx28_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */
- mx28_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */
+ mxs_reg_32(hw_pinctrl_muxsel0) /* 0x100 */
+ mxs_reg_32(hw_pinctrl_muxsel1) /* 0x110 */
+ mxs_reg_32(hw_pinctrl_muxsel2) /* 0x120 */
+ mxs_reg_32(hw_pinctrl_muxsel3) /* 0x130 */
+ mxs_reg_32(hw_pinctrl_muxsel4) /* 0x140 */
+ mxs_reg_32(hw_pinctrl_muxsel5) /* 0x150 */
+ mxs_reg_32(hw_pinctrl_muxsel6) /* 0x160 */
+ mxs_reg_32(hw_pinctrl_muxsel7) /* 0x170 */
+ mxs_reg_32(hw_pinctrl_muxsel8) /* 0x180 */
+ mxs_reg_32(hw_pinctrl_muxsel9) /* 0x190 */
+ mxs_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */
+ mxs_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */
+ mxs_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */
+ mxs_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */
uint32_t reserved2[72];
- mx28_reg_32(hw_pinctrl_drive0) /* 0x300 */
- mx28_reg_32(hw_pinctrl_drive1) /* 0x310 */
- mx28_reg_32(hw_pinctrl_drive2) /* 0x320 */
- mx28_reg_32(hw_pinctrl_drive3) /* 0x330 */
- mx28_reg_32(hw_pinctrl_drive4) /* 0x340 */
- mx28_reg_32(hw_pinctrl_drive5) /* 0x350 */
- mx28_reg_32(hw_pinctrl_drive6) /* 0x360 */
- mx28_reg_32(hw_pinctrl_drive7) /* 0x370 */
- mx28_reg_32(hw_pinctrl_drive8) /* 0x380 */
- mx28_reg_32(hw_pinctrl_drive9) /* 0x390 */
- mx28_reg_32(hw_pinctrl_drive10) /* 0x3a0 */
- mx28_reg_32(hw_pinctrl_drive11) /* 0x3b0 */
- mx28_reg_32(hw_pinctrl_drive12) /* 0x3c0 */
- mx28_reg_32(hw_pinctrl_drive13) /* 0x3d0 */
- mx28_reg_32(hw_pinctrl_drive14) /* 0x3e0 */
- mx28_reg_32(hw_pinctrl_drive15) /* 0x3f0 */
- mx28_reg_32(hw_pinctrl_drive16) /* 0x400 */
- mx28_reg_32(hw_pinctrl_drive17) /* 0x410 */
- mx28_reg_32(hw_pinctrl_drive18) /* 0x420 */
- mx28_reg_32(hw_pinctrl_drive19) /* 0x430 */
+ mxs_reg_32(hw_pinctrl_drive0) /* 0x300 */
+ mxs_reg_32(hw_pinctrl_drive1) /* 0x310 */
+ mxs_reg_32(hw_pinctrl_drive2) /* 0x320 */
+ mxs_reg_32(hw_pinctrl_drive3) /* 0x330 */
+ mxs_reg_32(hw_pinctrl_drive4) /* 0x340 */
+ mxs_reg_32(hw_pinctrl_drive5) /* 0x350 */
+ mxs_reg_32(hw_pinctrl_drive6) /* 0x360 */
+ mxs_reg_32(hw_pinctrl_drive7) /* 0x370 */
+ mxs_reg_32(hw_pinctrl_drive8) /* 0x380 */
+ mxs_reg_32(hw_pinctrl_drive9) /* 0x390 */
+ mxs_reg_32(hw_pinctrl_drive10) /* 0x3a0 */
+ mxs_reg_32(hw_pinctrl_drive11) /* 0x3b0 */
+ mxs_reg_32(hw_pinctrl_drive12) /* 0x3c0 */
+ mxs_reg_32(hw_pinctrl_drive13) /* 0x3d0 */
+ mxs_reg_32(hw_pinctrl_drive14) /* 0x3e0 */
+ mxs_reg_32(hw_pinctrl_drive15) /* 0x3f0 */
+ mxs_reg_32(hw_pinctrl_drive16) /* 0x400 */
+ mxs_reg_32(hw_pinctrl_drive17) /* 0x410 */
+ mxs_reg_32(hw_pinctrl_drive18) /* 0x420 */
+ mxs_reg_32(hw_pinctrl_drive19) /* 0x430 */
uint32_t reserved3[112];
- mx28_reg_32(hw_pinctrl_pull0) /* 0x600 */
- mx28_reg_32(hw_pinctrl_pull1) /* 0x610 */
- mx28_reg_32(hw_pinctrl_pull2) /* 0x620 */
- mx28_reg_32(hw_pinctrl_pull3) /* 0x630 */
- mx28_reg_32(hw_pinctrl_pull4) /* 0x640 */
- mx28_reg_32(hw_pinctrl_pull5) /* 0x650 */
- mx28_reg_32(hw_pinctrl_pull6) /* 0x660 */
+ mxs_reg_32(hw_pinctrl_pull0) /* 0x600 */
+ mxs_reg_32(hw_pinctrl_pull1) /* 0x610 */
+ mxs_reg_32(hw_pinctrl_pull2) /* 0x620 */
+ mxs_reg_32(hw_pinctrl_pull3) /* 0x630 */
+ mxs_reg_32(hw_pinctrl_pull4) /* 0x640 */
+ mxs_reg_32(hw_pinctrl_pull5) /* 0x650 */
+ mxs_reg_32(hw_pinctrl_pull6) /* 0x660 */
uint32_t reserved4[36];
- mx28_reg_32(hw_pinctrl_dout0) /* 0x700 */
- mx28_reg_32(hw_pinctrl_dout1) /* 0x710 */
- mx28_reg_32(hw_pinctrl_dout2) /* 0x720 */
- mx28_reg_32(hw_pinctrl_dout3) /* 0x730 */
- mx28_reg_32(hw_pinctrl_dout4) /* 0x740 */
+ mxs_reg_32(hw_pinctrl_dout0) /* 0x700 */
+ mxs_reg_32(hw_pinctrl_dout1) /* 0x710 */
+ mxs_reg_32(hw_pinctrl_dout2) /* 0x720 */
+ mxs_reg_32(hw_pinctrl_dout3) /* 0x730 */
+ mxs_reg_32(hw_pinctrl_dout4) /* 0x740 */
uint32_t reserved5[108];
- mx28_reg_32(hw_pinctrl_din0) /* 0x900 */
- mx28_reg_32(hw_pinctrl_din1) /* 0x910 */
- mx28_reg_32(hw_pinctrl_din2) /* 0x920 */
- mx28_reg_32(hw_pinctrl_din3) /* 0x930 */
- mx28_reg_32(hw_pinctrl_din4) /* 0x940 */
+ mxs_reg_32(hw_pinctrl_din0) /* 0x900 */
+ mxs_reg_32(hw_pinctrl_din1) /* 0x910 */
+ mxs_reg_32(hw_pinctrl_din2) /* 0x920 */
+ mxs_reg_32(hw_pinctrl_din3) /* 0x930 */
+ mxs_reg_32(hw_pinctrl_din4) /* 0x940 */
uint32_t reserved6[108];
- mx28_reg_32(hw_pinctrl_doe0) /* 0xb00 */
- mx28_reg_32(hw_pinctrl_doe1) /* 0xb10 */
- mx28_reg_32(hw_pinctrl_doe2) /* 0xb20 */
- mx28_reg_32(hw_pinctrl_doe3) /* 0xb30 */
- mx28_reg_32(hw_pinctrl_doe4) /* 0xb40 */
+ mxs_reg_32(hw_pinctrl_doe0) /* 0xb00 */
+ mxs_reg_32(hw_pinctrl_doe1) /* 0xb10 */
+ mxs_reg_32(hw_pinctrl_doe2) /* 0xb20 */
+ mxs_reg_32(hw_pinctrl_doe3) /* 0xb30 */
+ mxs_reg_32(hw_pinctrl_doe4) /* 0xb40 */
uint32_t reserved7[300];
- mx28_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */
- mx28_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */
- mx28_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */
- mx28_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */
- mx28_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */
+ mxs_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */
+ mxs_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */
+ mxs_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */
+ mxs_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */
+ mxs_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */
uint32_t reserved8[44];
- mx28_reg_32(hw_pinctrl_irqen0) /* 0x1100 */
- mx28_reg_32(hw_pinctrl_irqen1) /* 0x1110 */
- mx28_reg_32(hw_pinctrl_irqen2) /* 0x1120 */
- mx28_reg_32(hw_pinctrl_irqen3) /* 0x1130 */
- mx28_reg_32(hw_pinctrl_irqen4) /* 0x1140 */
+ mxs_reg_32(hw_pinctrl_irqen0) /* 0x1100 */
+ mxs_reg_32(hw_pinctrl_irqen1) /* 0x1110 */
+ mxs_reg_32(hw_pinctrl_irqen2) /* 0x1120 */
+ mxs_reg_32(hw_pinctrl_irqen3) /* 0x1130 */
+ mxs_reg_32(hw_pinctrl_irqen4) /* 0x1140 */
uint32_t reserved9[44];
- mx28_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */
- mx28_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */
- mx28_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */
- mx28_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */
- mx28_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */
+ mxs_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */
+ mxs_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */
+ mxs_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */
+ mxs_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */
+ mxs_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */
uint32_t reserved10[44];
- mx28_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */
- mx28_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */
- mx28_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */
- mx28_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */
- mx28_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */
+ mxs_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */
+ mxs_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */
+ mxs_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */
+ mxs_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */
+ mxs_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */
uint32_t reserved11[44];
- mx28_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */
- mx28_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */
- mx28_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */
- mx28_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */
- mx28_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */
+ mxs_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */
+ mxs_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */
+ mxs_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */
+ mxs_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */
+ mxs_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */
uint32_t reserved12[380];
- mx28_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */
+ mxs_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */
uint32_t reserved13[76];
- mx28_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */
+ mxs_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */
};
#endif
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mx28_power_regs {
- mx28_reg_32(hw_power_ctrl)
- mx28_reg_32(hw_power_5vctrl)
- mx28_reg_32(hw_power_minpwr)
- mx28_reg_32(hw_power_charge)
+struct mxs_power_regs {
+ mxs_reg_32(hw_power_ctrl)
+ mxs_reg_32(hw_power_5vctrl)
+ mxs_reg_32(hw_power_minpwr)
+ mxs_reg_32(hw_power_charge)
uint32_t hw_power_vdddctrl;
uint32_t reserved_vddd[3];
uint32_t hw_power_vddactrl;
uint32_t reserved_misc[3];
uint32_t hw_power_dclimits;
uint32_t reserved_dclimits[3];
- mx28_reg_32(hw_power_loopctrl)
+ mxs_reg_32(hw_power_loopctrl)
uint32_t hw_power_sts;
uint32_t reserved_sts[3];
- mx28_reg_32(hw_power_speed)
+ mxs_reg_32(hw_power_speed)
uint32_t hw_power_battmonitor;
uint32_t reserved_battmonitor[3];
uint32_t reserved[4];
- mx28_reg_32(hw_power_reset)
- mx28_reg_32(hw_power_debug)
- mx28_reg_32(hw_power_thermal)
- mx28_reg_32(hw_power_usb1ctrl)
- mx28_reg_32(hw_power_special)
- mx28_reg_32(hw_power_version)
- mx28_reg_32(hw_power_anaclkctrl)
- mx28_reg_32(hw_power_refctrl)
+ mxs_reg_32(hw_power_reset)
+ mxs_reg_32(hw_power_debug)
+ mxs_reg_32(hw_power_thermal)
+ mxs_reg_32(hw_power_usb1ctrl)
+ mxs_reg_32(hw_power_special)
+ mxs_reg_32(hw_power_version)
+ mxs_reg_32(hw_power_anaclkctrl)
+ mxs_reg_32(hw_power_refctrl)
};
#endif
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mx28_rtc_regs {
- mx28_reg_32(hw_rtc_ctrl)
- mx28_reg_32(hw_rtc_stat)
- mx28_reg_32(hw_rtc_milliseconds)
- mx28_reg_32(hw_rtc_seconds)
- mx28_reg_32(hw_rtc_rtc_alarm)
- mx28_reg_32(hw_rtc_watchdog)
- mx28_reg_32(hw_rtc_persistent0)
- mx28_reg_32(hw_rtc_persistent1)
- mx28_reg_32(hw_rtc_persistent2)
- mx28_reg_32(hw_rtc_persistent3)
- mx28_reg_32(hw_rtc_persistent4)
- mx28_reg_32(hw_rtc_persistent5)
- mx28_reg_32(hw_rtc_debug)
- mx28_reg_32(hw_rtc_version)
+struct mxs_rtc_regs {
+ mxs_reg_32(hw_rtc_ctrl)
+ mxs_reg_32(hw_rtc_stat)
+ mxs_reg_32(hw_rtc_milliseconds)
+ mxs_reg_32(hw_rtc_seconds)
+ mxs_reg_32(hw_rtc_rtc_alarm)
+ mxs_reg_32(hw_rtc_watchdog)
+ mxs_reg_32(hw_rtc_persistent0)
+ mxs_reg_32(hw_rtc_persistent1)
+ mxs_reg_32(hw_rtc_persistent2)
+ mxs_reg_32(hw_rtc_persistent3)
+ mxs_reg_32(hw_rtc_persistent4)
+ mxs_reg_32(hw_rtc_persistent5)
+ mxs_reg_32(hw_rtc_debug)
+ mxs_reg_32(hw_rtc_version)
};
#endif
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mx28_ssp_regs {
- mx28_reg_32(hw_ssp_ctrl0)
- mx28_reg_32(hw_ssp_cmd0)
- mx28_reg_32(hw_ssp_cmd1)
- mx28_reg_32(hw_ssp_xfer_size)
- mx28_reg_32(hw_ssp_block_size)
- mx28_reg_32(hw_ssp_compref)
- mx28_reg_32(hw_ssp_compmask)
- mx28_reg_32(hw_ssp_timing)
- mx28_reg_32(hw_ssp_ctrl1)
- mx28_reg_32(hw_ssp_data)
- mx28_reg_32(hw_ssp_sdresp0)
- mx28_reg_32(hw_ssp_sdresp1)
- mx28_reg_32(hw_ssp_sdresp2)
- mx28_reg_32(hw_ssp_sdresp3)
- mx28_reg_32(hw_ssp_ddr_ctrl)
- mx28_reg_32(hw_ssp_dll_ctrl)
- mx28_reg_32(hw_ssp_status)
- mx28_reg_32(hw_ssp_dll_sts)
- mx28_reg_32(hw_ssp_debug)
- mx28_reg_32(hw_ssp_version)
+struct mxs_ssp_regs {
+ mxs_reg_32(hw_ssp_ctrl0)
+ mxs_reg_32(hw_ssp_cmd0)
+ mxs_reg_32(hw_ssp_cmd1)
+ mxs_reg_32(hw_ssp_xfer_size)
+ mxs_reg_32(hw_ssp_block_size)
+ mxs_reg_32(hw_ssp_compref)
+ mxs_reg_32(hw_ssp_compmask)
+ mxs_reg_32(hw_ssp_timing)
+ mxs_reg_32(hw_ssp_ctrl1)
+ mxs_reg_32(hw_ssp_data)
+ mxs_reg_32(hw_ssp_sdresp0)
+ mxs_reg_32(hw_ssp_sdresp1)
+ mxs_reg_32(hw_ssp_sdresp2)
+ mxs_reg_32(hw_ssp_sdresp3)
+ mxs_reg_32(hw_ssp_ddr_ctrl)
+ mxs_reg_32(hw_ssp_dll_ctrl)
+ mxs_reg_32(hw_ssp_status)
+ mxs_reg_32(hw_ssp_dll_sts)
+ mxs_reg_32(hw_ssp_debug)
+ mxs_reg_32(hw_ssp_version)
};
#endif
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
-struct mx28_timrot_regs {
- mx28_reg_32(hw_timrot_rotctrl)
- mx28_reg_32(hw_timrot_rotcount)
- mx28_reg_32(hw_timrot_timctrl0)
- mx28_reg_32(hw_timrot_running_count0)
- mx28_reg_32(hw_timrot_fixed_count0)
- mx28_reg_32(hw_timrot_match_count0)
- mx28_reg_32(hw_timrot_timctrl1)
- mx28_reg_32(hw_timrot_running_count1)
- mx28_reg_32(hw_timrot_fixed_count1)
- mx28_reg_32(hw_timrot_match_count1)
- mx28_reg_32(hw_timrot_timctrl2)
- mx28_reg_32(hw_timrot_running_count2)
- mx28_reg_32(hw_timrot_fixed_count2)
- mx28_reg_32(hw_timrot_match_count2)
- mx28_reg_32(hw_timrot_timctrl3)
- mx28_reg_32(hw_timrot_running_count3)
- mx28_reg_32(hw_timrot_fixed_count3)
- mx28_reg_32(hw_timrot_match_count3)
- mx28_reg_32(hw_timrot_version)
+struct mxs_timrot_regs {
+ mxs_reg_32(hw_timrot_rotctrl)
+ mxs_reg_32(hw_timrot_rotcount)
+ mxs_reg_32(hw_timrot_timctrl0)
+ mxs_reg_32(hw_timrot_running_count0)
+ mxs_reg_32(hw_timrot_fixed_count0)
+ mxs_reg_32(hw_timrot_match_count0)
+ mxs_reg_32(hw_timrot_timctrl1)
+ mxs_reg_32(hw_timrot_running_count1)
+ mxs_reg_32(hw_timrot_fixed_count1)
+ mxs_reg_32(hw_timrot_match_count1)
+ mxs_reg_32(hw_timrot_timctrl2)
+ mxs_reg_32(hw_timrot_running_count2)
+ mxs_reg_32(hw_timrot_fixed_count2)
+ mxs_reg_32(hw_timrot_match_count2)
+ mxs_reg_32(hw_timrot_timctrl3)
+ mxs_reg_32(hw_timrot_running_count3)
+ mxs_reg_32(hw_timrot_fixed_count3)
+ mxs_reg_32(hw_timrot_match_count3)
+ mxs_reg_32(hw_timrot_version)
};
#endif
#ifndef __REGS_USB_H__
#define __REGS_USB_H__
-struct mx28_usb_regs {
+struct mxs_usb_regs {
uint32_t hw_usbctrl_id; /* 0x000 */
uint32_t hw_usbctrl_hwgeneral; /* 0x004 */
uint32_t hw_usbctrl_hwhost; /* 0x008 */
#ifndef __REGS_USBPHY_H__
#define __REGS_USBPHY_H__
-struct mx28_usbphy_regs {
- mx28_reg_32(hw_usbphy_pwd)
- mx28_reg_32(hw_usbphy_tx)
- mx28_reg_32(hw_usbphy_rx)
- mx28_reg_32(hw_usbphy_ctrl)
- mx28_reg_32(hw_usbphy_status)
- mx28_reg_32(hw_usbphy_debug)
- mx28_reg_32(hw_usbphy_debug0_status)
- mx28_reg_32(hw_usbphy_debug1)
- mx28_reg_32(hw_usbphy_version)
- mx28_reg_32(hw_usbphy_ip)
+struct mxs_usbphy_regs {
+ mxs_reg_32(hw_usbphy_pwd)
+ mxs_reg_32(hw_usbphy_tx)
+ mxs_reg_32(hw_usbphy_rx)
+ mxs_reg_32(hw_usbphy_ctrl)
+ mxs_reg_32(hw_usbphy_status)
+ mxs_reg_32(hw_usbphy_debug)
+ mxs_reg_32(hw_usbphy_debug0_status)
+ mxs_reg_32(hw_usbphy_debug1)
+ mxs_reg_32(hw_usbphy_version)
+ mxs_reg_32(hw_usbphy_ip)
};
#define USBPHY_PWD_RXPWDRX (1 << 20)
/*
- * Freescale i.MX28 MX28 specific functions
+ * Freescale i.MX23/i.MX28 specific functions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
*/
-#ifndef __MX28_H__
-#define __MX28_H__
+#ifndef __SYS_PROTO_H__
+#define __SYS_PROTO_H__
-int mx28_reset_block(struct mx28_register_32 *reg);
-int mx28_wait_mask_set(struct mx28_register_32 *reg,
+int mxs_reset_block(struct mxs_register_32 *reg);
+int mxs_wait_mask_set(struct mxs_register_32 *reg,
uint32_t mask,
- int timeout);
-int mx28_wait_mask_clr(struct mx28_register_32 *reg,
+ unsigned int timeout);
+int mxs_wait_mask_clr(struct mxs_register_32 *reg,
uint32_t mask,
- int timeout);
+ unsigned int timeout);
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int));
#ifdef CONFIG_SPL_BUILD
#include <asm/arch/iomux-mx28.h>
-void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
+void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size);
#endif
-struct mx28_pair {
+struct mxs_pair {
uint8_t boot_pads;
uint8_t boot_mask;
const char *mode;
};
-static const struct mx28_pair mx28_boot_modes[] = {
+static const struct mxs_pair mxs_boot_modes[] = {
{ 0x00, 0x0f, "USB #0" },
{ 0x01, 0x1f, "I2C #0, master, 3V3" },
{ 0x11, 0x1f, "I2C #0, master, 1V8" },
{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
};
-struct mx28_spl_data {
+struct mxs_spl_data {
uint8_t boot_mode_idx;
uint32_t mem_dram_size;
};
-int mx28_dram_init(void);
+int mxs_dram_init(void);
-#endif /* __MX28_H__ */
+#endif /* __SYS_PROTO_H__ */
#define NUMONYX_RASWIDTH_165 15
#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165)
+/* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */
+#define NUMONYX_TDAL_200 6 /* Twr/Tck + Trp/tck */
+ /* 15/5 + 15/5 = 3 + 3 -> 6 */
+#define NUMONYX_TDPL_200 3 /* 15/5 = 3 -> 3 (Twr) */
+#define NUMONYX_TRRD_200 2 /* 10/5 = 2 */
+#define NUMONYX_TRCD_200 4 /* 16.2/5 = 3.24 -> 4 */
+#define NUMONYX_TRP_200 3 /* 15/5 = 3 */
+#define NUMONYX_TRAS_200 8 /* 40/5 = 8 */
+#define NUMONYX_TRC_200 11 /* 55/5 = 11 */
+#define NUMONYX_TRFC_200 28 /* 140/5 = 28 */
+
+#define NUMONYX_V_ACTIMA_200 \
+ ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200, \
+ NUMONYX_TRAS_200, NUMONYX_TRP_200, \
+ NUMONYX_TRCD_200, NUMONYX_TRRD_200, \
+ NUMONYX_TDPL_200, NUMONYX_TDAL_200)
+
+#define NUMONYX_TWTR_200 2
+#define NUMONYX_TCKE_200 2
+#define NUMONYX_TXP_200 3
+#define NUMONYX_XSR_200 40
+
+#define NUMONYX_V_ACTIMB_200 \
+ ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200, \
+ NUMONYX_TXP_200, NUMONYX_XSR_200)
+
+#define NUMONYX_RASWIDTH_200 15
+#define NUMONYX_V_MCFG_200(size) MCFG((size), NUMONYX_RASWIDTH_200)
+
/*
* GPMC settings -
* Definitions is as per the following format
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4030D000
/* Temporary SRAM stack used while low level init is done */
-#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
/* SRAM scratch space entries */
#define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR
#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000
-/* Temporary SRAM stack used while low level init is done */
-#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
/*
#define HALT_COP_EVENT_IRQ_1 (1 << 11)
#define HALT_COP_EVENT_FIQ_1 (1 << 9)
-/* Start up the tegra2 SOC */
-void tegra2_start(void);
+/* Start up the tegra20 SOC */
+void tegra20_start(void);
/* This is the main entry into U-Boot, used by the Cortex-A9 */
extern void _start(void);
* MA 02111-1307 USA
*/
-/* Tegra2 high-level function multiplexing */
+/* Tegra20 high-level function multiplexing */
#ifndef __FUNCMUX_H
#define __FUNCMUX_H
#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
/* CHIPID field returned from APB_MISC_GP_HIDREV register */
-#define CHIPID_TEGRA2 0x20
+#define CHIPID_TEGRA20 0x20
#endif
};
/*
- * Tegra2-specific GPIO API
+ * Tegra20-specific GPIO API
*/
void gpio_info(void);
--- /dev/null
+/*
+* (C) Copyright 2010-2011
+* NVIDIA Corporation <www.nvidia.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#ifndef __TEGRA2_HW_H
+#define __TEGRA2_HW_H
+
+/* include tegra specific hardware definitions */
+
+#endif /* __TEGRA2_HW_H */
* MA 02111-1307 USA
*/
-#ifndef _TEGRA2_MMC_H_
-#define _TEGRA2_MMC_H_
+#ifndef _TEGRA20_MMC_H_
+#define _TEGRA20_MMC_H_
-int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
+int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
-#endif /* TEGRA2_MMC_H_ */
+#endif /* TEGRA20_MMC_H_ */
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
-struct tegra2_sysinfo {
+struct tegra20_sysinfo {
char *board_string;
};
void invalidate_dcache(void);
-extern const struct tegra2_sysinfo sysinfo;
+extern const struct tegra20_sysinfo sysinfo;
#endif
* MA 02111-1307 USA
*/
-#ifndef _TEGRA2_H_
-#define _TEGRA2_H_
+#ifndef _TEGRA20_H_
+#define _TEGRA20_H_
#define NV_PA_SDRAM_BASE 0x00000000
#define NV_PA_ARM_PERIPHBASE 0x50040000
#define NV_PA_GPIO_BASE 0x6000D000
#define NV_PA_EVP_BASE 0x6000F000
#define NV_PA_APB_MISC_BASE 0x70000000
-#define TEGRA2_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
+#define TEGRA20_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
-#define TEGRA2_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
-#define TEGRA2_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
-#define TEGRA2_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
+#define TEGRA20_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
+#define TEGRA20_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
+#define TEGRA20_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
#define NV_PA_CSITE_BASE 0x70040000
#define TEGRA_USB1_BASE 0xC5000000
#define TEGRA_USB3_BASE 0xC5008000
#define TEGRA_USB_ADDR_MASK 0xFFFFC000
-#define TEGRA2_SDRC_CS0 NV_PA_SDRAM_BASE
+#define TEGRA20_SDRC_CS0 NV_PA_SDRAM_BASE
#define LOW_LEVEL_SRAM_STACK 0x4000FFFC
#define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000)
#define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096)
};
#else /* __ASSEMBLY__ */
-#define PRM_RSTCTRL TEGRA2_PMC_BASE
+#define PRM_RSTCTRL TEGRA20_PMC_BASE
#endif
-#endif /* TEGRA2_H */
+#endif /* TEGRA20_H */
/*
- * NVIDIA Tegra2 I2C controller
+ * NVIDIA Tegra20 I2C controller
*
* Copyright 2010-2011 NVIDIA Corporation
*
/*
- * NVIDIA Tegra2 SPI-FLASH controller
+ * NVIDIA Tegra20 SPI-FLASH controller
*
* Copyright 2010-2012 NVIDIA Corporation
*
#define SPI_STAT_CUR_BLKCNT (1 << 15)
#define SPI_TIMEOUT 1000
-#define TEGRA2_SPI_MAX_FREQ 52000000
+#define TEGRA20_SPI_MAX_FREQ 52000000
#endif /* _TEGRA_SPI_H_ */
* MA 02111-1307 USA
*/
-/* Tegra2 timer functions */
+/* Tegra20 timer functions */
-#ifndef _TEGRA2_TIMER_H
-#define _TEGRA2_TIMER_H
+#ifndef _TEGRA20_TIMER_H
+#define _TEGRA20_TIMER_H
/* returns the current monotonic timer value in microseconds */
unsigned long timer_get_us(void);
extern void u8500_clock_enable(int periph, int kern, int cluster);
-static inline void u8500_prcmu_enable(unsigned int *reg)
-{
- writel(readl(reg) | (1 << 8), reg);
-}
+void db8500_clocks_init(void);
#endif /* __ASM_ARCH_CLOCK */
--- /dev/null
+/*
+ * Structures and registers for GPIO access in the Nomadik SoC
+ *
+ * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
+ * The purpose is that GPIO config found in kernel should work by simply
+ * copy-paste it to U-boot.
+ *
+ * Ported to U-boot by:
+ * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com>
+ * Copyright (C) 2008 STMicroelectronics
+ * Author: Prafulla WADASKAR <prafulla.wadaskar@st.com>
+ * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DB8500_GPIO_H__
+#define __DB8500_GPIO_H__
+
+/* Alternate functions: function C is set in hw by setting both A and B */
+enum db8500_gpio_alt {
+ DB8500_GPIO_ALT_GPIO = 0,
+ DB8500_GPIO_ALT_A = 1,
+ DB8500_GPIO_ALT_B = 2,
+ DB8500_GPIO_ALT_C = (DB8500_GPIO_ALT_A | DB8500_GPIO_ALT_B)
+};
+
+enum db8500_gpio_pull {
+ DB8500_GPIO_PULL_NONE,
+ DB8500_GPIO_PULL_UP,
+ DB8500_GPIO_PULL_DOWN
+};
+
+void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull);
+void db8500_gpio_make_input(unsigned gpio);
+int db8500_gpio_get_input(unsigned gpio);
+void db8500_gpio_make_output(unsigned gpio, int val);
+void db8500_gpio_set_output(unsigned gpio, int val);
+
+#endif /* __DB8500_GPIO_H__ */
--- /dev/null
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
+ * The purpose is that GPIO config found in kernel should work by simply
+ * copy-paste it to U-boot. Ported 2010 to U-boot by:
+ * Author: Joakim Axelsson <joakim.axelsson AT stericsson.com>
+ *
+ * License terms: GNU General Public License, version 2
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ *
+ *
+ * Based on arch/arm/mach-pxa/include/mach/mfp.h:
+ * Copyright (C) 2007 Marvell International Ltd.
+ * eric miao <eric.miao@marvell.com>
+ */
+
+#ifndef __DB8500_PINCFG_H
+#define __DB8500_PINCFG_H
+
+#include "db8500_gpio.h"
+
+/*
+ * U-boot info:
+ * SLPM (sleep mode) config will be ignored by U-boot but it is still
+ * possible to configure it in order to keep cut-n-paste compability
+ * with Linux kernel config.
+ *
+ * pin configurations are represented by 32-bit integers:
+ *
+ * bit 0.. 8 - Pin Number (512 Pins Maximum)
+ * bit 9..10 - Alternate Function Selection
+ * bit 11..12 - Pull up/down state
+ * bit 13 - Sleep mode behaviour (not used in U-boot)
+ * bit 14 - Direction
+ * bit 15 - Value (if output)
+ * bit 16..18 - SLPM pull up/down state (not used in U-boot)
+ * bit 19..20 - SLPM direction (not used in U-boot)
+ * bit 21..22 - SLPM Value (if output) (not used in U-boot)
+ *
+ * to facilitate the definition, the following macros are provided
+ *
+ * PIN_CFG_DEFAULT - default config (0):
+ * pull up/down = disabled
+ * sleep mode = input/wakeup
+ * direction = input
+ * value = low
+ * SLPM direction = same as normal
+ * SLPM pull = same as normal
+ * SLPM value = same as normal
+ *
+ * PIN_CFG - default config with alternate function
+ * PIN_CFG_PULL - default config with alternate function and pull up/down
+ */
+
+/* Sleep mode */
+enum db8500_gpio_slpm {
+ DB8500_GPIO_SLPM_INPUT,
+ DB8500_GPIO_SLPM_WAKEUP_ENABLE = DB8500_GPIO_SLPM_INPUT,
+ DB8500_GPIO_SLPM_NOCHANGE,
+ DB8500_GPIO_SLPM_WAKEUP_DISABLE = DB8500_GPIO_SLPM_NOCHANGE,
+};
+
+#define PIN_NUM_MASK 0x1ff
+#define PIN_NUM(x) ((x) & PIN_NUM_MASK)
+
+#define PIN_ALT_SHIFT 9
+#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
+#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
+#define PIN_GPIO (DB8500_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
+#define PIN_ALT_A (DB8500_GPIO_ALT_A << PIN_ALT_SHIFT)
+#define PIN_ALT_B (DB8500_GPIO_ALT_B << PIN_ALT_SHIFT)
+#define PIN_ALT_C (DB8500_GPIO_ALT_C << PIN_ALT_SHIFT)
+
+#define PIN_PULL_SHIFT 11
+#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
+#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
+#define PIN_PULL_NONE (DB8500_GPIO_PULL_NONE << PIN_PULL_SHIFT)
+#define PIN_PULL_UP (DB8500_GPIO_PULL_UP << PIN_PULL_SHIFT)
+#define PIN_PULL_DOWN (DB8500_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
+
+#define PIN_SLPM_SHIFT 13
+#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
+#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
+#define PIN_SLPM_MAKE_INPUT (DB8500_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
+#define PIN_SLPM_NOCHANGE (DB8500_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
+/* These two replace the above in DB8500v2+ */
+#define PIN_SLPM_WAKEUP_ENABLE \
+ (DB8500_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
+#define PIN_SLPM_WAKEUP_DISABLE \
+ (DB8500_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
+
+#define PIN_DIR_SHIFT 14
+#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
+#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
+#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
+#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
+
+#define PIN_VAL_SHIFT 15
+#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
+#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
+#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
+#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
+
+#define PIN_SLPM_PULL_SHIFT 16
+#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL(x) \
+ (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_NONE \
+ ((1 + DB8500_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_UP \
+ ((1 + DB8500_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_DOWN \
+ ((1 + DB8500_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
+
+#define PIN_SLPM_DIR_SHIFT 19
+#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR(x) \
+ (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
+
+#define PIN_SLPM_VAL_SHIFT 21
+#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL(x) \
+ (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
+
+/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
+#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
+#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
+#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
+#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
+#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
+
+#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
+#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
+#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
+#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
+#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
+
+#define PIN_CFG_DEFAULT (0)
+
+#define PIN_CFG(num, alt) \
+ (PIN_CFG_DEFAULT |\
+ (PIN_NUM(num) | PIN_##alt))
+
+#define PIN_CFG_INPUT(num, alt, pull) \
+ (PIN_CFG_DEFAULT |\
+ (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
+
+#define PIN_CFG_OUTPUT(num, alt, val) \
+ (PIN_CFG_DEFAULT |\
+ (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
+
+#define PIN_CFG_PULL(num, alt, pull) \
+ ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\
+ (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull))
+
+/**
+ * db8500_gpio_config_pins - configure several pins at once
+ * @cfgs: array of pin configurations
+ * @num: number of elments in the array
+ *
+ * Configures several GPIO pins.
+ */
+void db8500_gpio_config_pins(unsigned long *cfgs, size_t num);
+
+#endif
/* Per4 */
#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
-#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000)
+#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
/* Per3 */
#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
/* Last page of Boot ROM */
-#define U8500_BOOTROM_BASE 0x9001f000
-#define U8500_BOOTROM_ASIC_ID_OFFSET 0x0ff4
+#define U8500_BOOTROM_BASE 0x90000000
+#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOTROM_BASE + 0x1FFF4)
+#define U8500_ASIC_ID_LOC_V2 (U8500_BOOTROM_BASE + 0x1DBF4)
+
+/* AB8500 specifics */
+
+/* address bank */
+#define AB8500_REGU_CTRL2 0x0004
+#define AB8500_MISC 0x0010
+
+/* registers */
+#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A
+#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421
+#define AB8500_REV_REG 0x1080
+
+#define AB8500_GPIO_SEL2_REG 0x1001
+#define AB8500_GPIO_DIR2_REG 0x1011
+#define AB8500_GPIO_DIR4_REG 0x1013
+#define AB8500_GPIO_SEL4_REG 0x1003
+#define AB8500_GPIO_OUT2_REG 0x1021
+#define AB8500_GPIO_OUT4_REG 0x1023
+
+#define LDO_VAUX3_ENABLE_MASK 0x3
+#define LDO_VAUX3_ENABLE_VAL 0x1
+#define LDO_VAUX3_SEL_MASK 0xf
+#define LDO_VAUX3_SEL_2V9 0xd
+#define LDO_VAUX3_V2_SEL_MASK 0x7
+#define LDO_VAUX3_V2_SEL_2V91 0x7
+
#endif /* __ASM_ARCH_HARDWARE_H */
#define I2C_RD_OK 2
#define I2CWRITE 0
-#define _PRCMU_TCDM_BASE U8500_PRCMU_TCDM_BASE
-#define PRCM_XP70_CUR_PWR_STATE (_PRCMU_TCDM_BASE + 0xFFC) /* 4 BYTES */
-
-#define PRCM_REQ_MB5 (_PRCMU_TCDM_BASE + 0xE44) /* 4 bytes */
-#define PRCM_ACK_MB5 (_PRCMU_TCDM_BASE + 0xDF4) /* 4 bytes */
+#define PRCMU_BASE U8500_PRCMU_BASE
+#define PRCMU_BASE_TCDM U8500_PRCMU_TCDM_BASE
+#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018)
+#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C)
+#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020)
+#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024)
+#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C)
+#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030)
+#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034)
+#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038)
+#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C)
+#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040)
+#define PRCM_MBOX_CPU_VAL (PRCMU_BASE + 0x0FC)
+#define PRCM_MBOX_CPU_SET (PRCMU_BASE + 0x100)
+#define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C)
+#define PRCM_ARM_IT1_VAL (PRCMU_BASE + 0x494)
+#define PRCM_TCR (PRCMU_BASE + 0x1C8)
+#define PRCM_REQ_MB5 (PRCMU_BASE_TCDM + 0xE44)
+#define PRCM_ACK_MB5 (PRCMU_BASE_TCDM + 0xDF4)
+#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE_TCDM + 0xFFC)
/* Mailbox 5 Requests */
#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0)
#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1)
#define REQ_MB5 5
-extern int prcmu_i2c_read(u8 reg, u16 slave);
-extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data);
+#define ab8500_read prcmu_i2c_read
+#define ab8500_write prcmu_i2c_write
+
+int prcmu_i2c_read(u8 reg, u16 slave);
+int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data);
+
+void u8500_prcmu_enable(u32 *reg);
+void db8500_prcmu_init(void);
#endif /* __MACH_PRCMU_FW_V1_H */
#define _SYS_PROTO_H_
void gpio_init(void);
+int u8500_mmc_power_init(void);
#endif /* _SYS_PROTO_H_ */
#define EMIF1_BASE 0x4c000000
#define EMIF2_BASE 0x4d000000
-/* Registers shifts and masks */
+/* Registers shifts, masks and values */
/* EMIF_MOD_ID_REV */
#define EMIF_REG_SCHEME_SHIFT 30
/* SDRAM_CONFIG */
#define EMIF_REG_SDRAM_TYPE_SHIFT 29
#define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29)
+#define EMIF_REG_SDRAM_TYPE_DDR1 0
+#define EMIF_REG_SDRAM_TYPE_LPDDR1 1
+#define EMIF_REG_SDRAM_TYPE_DDR2 2
+#define EMIF_REG_SDRAM_TYPE_DDR3 3
+#define EMIF_REG_SDRAM_TYPE_LPDDR2_S4 4
+#define EMIF_REG_SDRAM_TYPE_LPDDR2_S2 5
#define EMIF_REG_IBANK_POS_SHIFT 27
#define EMIF_REG_IBANK_POS_MASK (0x3 << 27)
#define EMIF_REG_DDR_TERM_SHIFT 24
--- /dev/null
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_BOOT_MODE_H
+#define _ASM_BOOT_MODE_H
+#define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \
+ ((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1)
+
+struct boot_mode {
+ const char *name;
+ unsigned cfg_val;
+};
+
+void add_board_boot_modes(const struct boot_mode *p);
+void boot_mode_apply(unsigned cfg_val);
+extern const struct boot_mode soc_boot_modes[];
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __ASM_ARCH_IMX_GPIO_H
+#define __ASM_ARCH_IMX_GPIO_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+/* GPIO registers */
+struct gpio_regs {
+ u32 gpio_dr; /* data */
+ u32 gpio_dir; /* direction */
+ u32 gpio_psr; /* pad satus */
+};
+#endif
+
+#define IMX_GPIO_NR(port, index) ((((port)-1)*32)+((index)&31))
+
+#endif
int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
-/*
- * IOMUXC_GPR13 bit fields
- */
-#define IOMUXC_GPR13_SDMA_STOP_REQ (1<<30)
-#define IOMUXC_GPR13_CAN2_STOP_REQ (1<<29)
-#define IOMUXC_GPR13_CAN1_STOP_REQ (1<<28)
-#define IOMUXC_GPR13_ENET_STOP_REQ (1<<27)
-#define IOMUXC_GPR13_SATA_PHY_8_MASK (7<<24)
-#define IOMUXC_GPR13_SATA_PHY_7_MASK (0x1f<<19)
-#define IOMUXC_GPR13_SATA_PHY_6_SHIFT 16
-#define IOMUXC_GPR13_SATA_PHY_6_MASK (7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
-#define IOMUXC_GPR13_SATA_SPEED_MASK (1<<15)
-#define IOMUXC_GPR13_SATA_PHY_5_MASK (1<<14)
-#define IOMUXC_GPR13_SATA_PHY_4_MASK (7<<11)
-#define IOMUXC_GPR13_SATA_PHY_3_MASK (0x1f<<7)
-#define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2)
-#define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0)
-
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0b000<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (0b001<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (0b010<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (0b011<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (0b100<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (0b101<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (0b110<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (0b111<<24)
-
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010<<19)
-
-#define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15)
-#define IOMUXC_GPR13_SATA_SPEED_3G (1<<15)
-
-#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED (0<<14)
-#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED (1<<14)
-
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16 (0<<11)
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16 (1<<11)
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16 (2<<11)
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16 (3<<11)
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11)
-#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11)
-
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0b0000<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (0b0001<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (0b0010<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (0b0011<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (0b0100<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (0b0101<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (0b0110<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (0b0111<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (0b1000<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (0b1001<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0b1010<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0b1011<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0b1100<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0b1101<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0b1110<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0b1111<<7)
-
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0b00000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (0b00001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (0b00010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (0b00011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (0b00100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (0b00101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (0b00110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (0b00111<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (0b01000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (0b01001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0b01010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0b01011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0b01100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0b01101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0b01110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0b01111<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0b10000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0b10001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0b10010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0b10011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0b10100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0b10101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0b10110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0b10111<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0b11000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0b11001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0b11010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0b11011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0b11100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0b11101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0b11110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0b11111<<2)
-
-#define IOMUXC_GPR13_SATA_PHY_1_FAST 0
-#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1
-#define IOMUXC_GPR13_SATA_PHY_1_SLOW 2
-
-#define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \
- |IOMUXC_GPR13_SATA_PHY_7_MASK \
- |IOMUXC_GPR13_SATA_PHY_6_MASK \
- |IOMUXC_GPR13_SATA_SPEED_MASK \
- |IOMUXC_GPR13_SATA_PHY_5_MASK \
- |IOMUXC_GPR13_SATA_PHY_4_MASK \
- |IOMUXC_GPR13_SATA_PHY_3_MASK \
- |IOMUXC_GPR13_SATA_PHY_2_MASK \
- |IOMUXC_GPR13_SATA_PHY_1_MASK)
-
#endif /* __MACH_IOMUX_V3_H__*/
#elif defined(CONFIG_AM33XX) /* AM33XX */
#define BOOT_DEVICE_NAND 5
#define BOOT_DEVICE_MMC1 8
-#define BOOT_DEVICE_MMC2 0
+#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
#define BOOT_DEVICE_UART 65
#define BOOT_DEVICE_MMC2_2 0xFF
#endif
LIB = $(obj)lib$(ARCH).o
LIBGCC = $(obj)libgcc.o
-ifndef CONFIG_SPL_BUILD
GLSOBJS += _ashldi3.o
GLSOBJS += _ashrdi3.o
GLSOBJS += _divsi3.o
GLCOBJS += div0.o
+ifndef CONFIG_SPL_BUILD
COBJS-y += board.o
COBJS-y += bootm.o
COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
int board_init(void)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- /* Enable Ctrlc */
- console_init_f();
/* Correct IRDA resistor problem / Set PA23_TXD in Output */
writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer);
writel(pin, &pio->piod.odr);
writel(pin, &pio->piod.owdr);
- /* Enable Ctrlc */
- console_init_f();
-
gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC;
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
static void setup_iomux_uart3(void)
{
- mxc_request_iomux(MX35_PIN_RTS2_UART3_RXD_MUX, MUX_CONFIG_ALT7);
- mxc_request_iomux(MX35_PIN_CTS2_UART3_TXD_MUX, MUX_CONFIG_ALT7);
+ mxc_request_iomux(MX35_PIN_RTS2, MUX_CONFIG_ALT7);
+ mxc_request_iomux(MX35_PIN_CTS2, MUX_CONFIG_ALT7);
}
static void setup_iomux_i2c(void)
/* enable clocks */
writel(readl(&ccm->cgr0) |
MXC_CCM_CGR0_EMI_MASK |
- MXC_CCM_CGR0_EDI0_MASK |
+ MXC_CCM_CGR0_EDIO_MASK |
MXC_CCM_CGR0_EPIT1_MASK,
&ccm->cgr0);
* MA 02111-1307 USA
*/
#include <common.h>
+#include <malloc.h>
+#include <errno.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/systimer.h>
int cpu_mmc_init(bd_t *bis)
{
int rc = 0;
+ (void) bis;
#ifdef CONFIG_ARM_PL180_MMCI
- rc = arm_pl180_mmci_init();
+ struct pl180_mmc_host *host;
+
+ host = malloc(sizeof(struct pl180_mmc_host));
+ if (!host)
+ return -ENOMEM;
+ memset(host, 0, sizeof(*host));
+
+ strcpy(host->name, "MMC");
+ host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
+ host->pwr_init = INIT_PWR;
+ host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
+ host->voltages = VOLTAGE_WINDOW_MMC;
+ host->caps = 0;
+ host->clock_in = ARM_MCLK;
+ host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
+ host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
+ rc = arm_pl180_mmci_init(host);
#endif
return rc;
}
int board_init(void)
{
- /* Enable Ctrlc */
- console_init_f();
-
#ifdef CONFIG_AT91SAM9G10EK
/* arch number of AT91SAM9G10EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
int board_init(void)
{
- /* Enable Ctrlc */
- console_init_f();
-
/* arch number of AT91SAM9263EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
/* adress of boot parameters */
int board_init(void)
{
- /* Enable Ctrlc */
- console_init_f();
-
/* arch number of AT91SAM9M10G45EK-Board */
#ifdef CONFIG_AT91SAM9M10G45EK
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
int board_init(void)
{
- /* Enable Ctrlc */
- console_init_f();
-
/* arch number of AT91SAM9RLEK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
/* adress of boot parameters */
--- /dev/null
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2012
+# Bo Shen <voice.shen@atmel.com>
+# Atmel corporation <www.atmel.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += at91sam9x5ek.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9x5_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <atmel_hlcdc.h>
+#ifdef CONFIG_MACB
+#include <net.h>
+#endif
+#include <netdev.h>
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+#endif
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+#ifdef CONFIG_CMD_NAND
+static void at91sam9x5ek_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+ /* NAND flash on D16 */
+ csa |= AT91_MATRIX_NFD0_ON_D16;
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(1),
+ &smc->cs[3].mode);
+
+ writel(1 << ATMEL_ID_PIOCD, &pmc->pcer);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+ at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
+ at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
+ at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
+ at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
+ at91_set_a_periph(AT91_PIO_PORTD, 6, 1);
+ at91_set_a_periph(AT91_PIO_PORTD, 7, 1);
+ at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
+ at91_set_a_periph(AT91_PIO_PORTD, 9, 1);
+ at91_set_a_periph(AT91_PIO_PORTD, 10, 1);
+ at91_set_a_periph(AT91_PIO_PORTD, 11, 1);
+ at91_set_a_periph(AT91_PIO_PORTD, 12, 1);
+ at91_set_a_periph(AT91_PIO_PORTD, 13, 1);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+#ifdef CONFIG_MACB
+ if (has_emac0())
+ rc = macb_eth_initialize(0,
+ (void *)ATMEL_BASE_EMAC0, 0x00);
+ if (has_emac1())
+ rc = macb_eth_initialize(1,
+ (void *)ATMEL_BASE_EMAC1, 0x00);
+#endif
+ return rc;
+}
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ .vl_col = 800,
+ .vl_row = 480,
+ .vl_clk = 24000000,
+ .vl_sync = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL,
+ .vl_bpix = LCD_BPP,
+ .vl_tft = 1,
+ .vl_clk_pol = 1,
+ .vl_hsync_len = 128,
+ .vl_left_margin = 64,
+ .vl_right_margin = 64,
+ .vl_vsync_len = 2,
+ .vl_upper_margin = 22,
+ .vl_lower_margin = 21,
+ .mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+ if (has_lcdc())
+ at91_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */
+}
+
+void lcd_disable(void)
+{
+ if (has_lcdc())
+ at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */
+}
+
+static void at91sam9x5ek_lcd_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ if (has_lcdc()) {
+ at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */
+ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */
+ at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
+ at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */
+
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
+ at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
+ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
+ at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
+ at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
+ at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
+ at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
+ at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
+ at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
+ at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
+ at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
+ at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
+ at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
+
+ writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+ }
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size;
+ int i;
+ char temp[32];
+
+ if (has_lcdc()) {
+ lcd_printf("%s\n", U_BOOT_VERSION);
+ lcd_printf("(C) 2012 ATMEL Corp\n");
+ lcd_printf("at91support@atmel.com\n");
+ lcd_printf("%s CPU at %s MHz\n",
+ get_cpu_name(),
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+ nand_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+ lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
+ dram_size >> 20,
+ nand_size >> 20);
+ }
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 1:
+ at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
+ break;
+ case 0:
+ default:
+ at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 1:
+ at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
+ break;
+ case 0:
+ default:
+ at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
+ break;
+ }
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+int board_early_init_f(void)
+{
+ at91_seriald_hw_init();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* arch number of AT91SAM9X5EK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ at91sam9x5ek_nand_hw_init();
+#endif
+
+#ifdef CONFIG_ATMEL_SPI
+ at91_spi0_hw_init(1 << 0);
+ at91_spi0_hw_init(1 << 4);
+#endif
+
+#ifdef CONFIG_MACB
+ at91_macb_hw_init();
+#endif
+
+#ifdef CONFIG_LCD
+ at91sam9x5ek_lcd_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
--- /dev/null
+CONFIG_SYS_TEXT_BASE = 0x26f00000
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/board.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
pin_mux_mmc();
/* init dev 0, SD slot, with 4-bit bus */
- tegra2_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
+ tegra20_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
return 0;
}
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
-endif
LIB = $(obj)lib$(BOARD).o
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
-endif
LIB = $(obj)lib$(BOARD).o
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
-endif
LIB = $(obj)lib$(BOARD).o
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+ifndef CONFIG_SPL_BUILD
+COBJS := apx4devkit.o
+else
+COBJS := spl_boot.o
+endif
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Bluegiga APX4 Development Kit
+ *
+ * Copyright (C) 2012 Bluegiga Technologies Oy
+ *
+ * Authors:
+ * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
+ * Lauri Hintsala <lauri.hintsala@bluegiga.com>
+ *
+ * Based on m28evk.c:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Functions */
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mx28_set_ioclk(MXC_IOCLK0, 480000);
+ /* IO1 clock at 480MHz */
+ mx28_set_ioclk(MXC_IOCLK1, 480000);
+
+ /* SSP0 clock at 96MHz */
+ mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ return mxs_dram_init();
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ return mxsmmc_initialize(bis, 0, NULL);
+}
+#endif
+
+
+#ifdef CONFIG_CMD_NET
+
+#define MII_PHY_CTRL2 0x1f
+int fecmxc_mii_postcall(int phy)
+{
+ /* change PHY RMII clock to 50MHz */
+ miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+ struct eth_device *dev;
+
+ ret = cpu_eth_init(bis);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC clocks\n");
+ return ret;
+ }
+
+ ret = fecmxc_initialize(bis);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC\n");
+ return ret;
+ }
+
+ dev = eth_get_dev_by_name("FEC");
+ if (!dev) {
+ printf("FEC MXS: Unable to get FEC device entry\n");
+ return -EINVAL;
+ }
+
+ ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+ if (ret) {
+ printf("FEC MXS: Unable to register FEC MII postcall\n");
+ return ret;
+ }
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+#define MXS_OCOTP_MAX_TIMEOUT 1000000
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ struct mxs_ocotp_regs *ocotp_regs =
+ (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
+
+ serialnr->high = 0;
+ serialnr->low = 0;
+
+ writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
+
+ if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
+ MXS_OCOTP_MAX_TIMEOUT)) {
+ printf("MXS: Can't get serial number from OCOTP\n");
+ return;
+ }
+
+ serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3);
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+ if (getenv("revision#") != NULL)
+ return simple_strtoul(getenv("revision#"), NULL, 10);
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * Bluegiga APX4 Development Kit
+ *
+ * Copyright (C) 2012 Bluegiga Technologies Oy
+ *
+ * Authors:
+ * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
+ * Lauri Hintsala <lauri.hintsala@bluegiga.com>
+ *
+ * Based on spl_boot.c:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* DUART */
+ MX28_PAD_PWM0__DUART_RX,
+ MX28_PAD_PWM1__DUART_TX,
+
+ /* LED */
+ MX28_PAD_PWM3__GPIO_3_28,
+
+ /* MMC0 */
+ MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+ (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL),
+ MX28_PAD_SSP0_SCK__SSP0_SCK |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
+ /* GPMI NAND */
+ MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDN__GPMI_RDN |
+ (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+ MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+
+ /* FEC0 */
+ MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+
+ /* I2C */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+ /* EMI */
+ MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+};
+
+void board_init_ll(void)
+{
+ mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+
+ /* switch LED on */
+ gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
+}
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ /*
+ * All address lines are routed from CPU to memory chip.
+ * ADDR_PINS field is set to zero.
+ */
+ dram_vals[0x74 >> 2] = 0x0f02000a;
+
+ /* Used memory has 4 banks. EIGHT_BANK_MODE bit is disabled. */
+ dram_vals[0x7c >> 2] = 0x00000101;
+}
int board_init(void)
{
- /* Enable Ctrlc */
- console_init_f();
-
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
int board_init(void)
{
- /* Enable Ctrlc */
- console_init_f();
-
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
/*
* Routine: board_init
- * Description: Early hardware init.
+ * Description: hardware init.
*/
int board_init(void)
{
rc1 = handle_mac_address();
if (rc1)
- printf("CM-T3x: No MAC address found\n");
+ printf("No MAC address found! ");
rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
if (rc1 > 0)
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../../nvidia/common)
-endif
LIB = $(obj)lib$(BOARD).o
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/mmc.h>
#include <asm/gpio.h>
debug("board_mmc_init: init eMMC\n");
/* init dev 0, eMMC chip, with 4-bit bus */
/* The board has an 8-bit bus, but 8-bit doesn't work yet */
- tegra2_mmc_init(0, 4, -1, -1);
+ tegra20_mmc_init(0, 4, -1, -1);
debug("board_mmc_init: init SD slot\n");
/* init dev 3, SD slot, with 4-bit bus */
- tegra2_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
+ tegra20_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
return 0;
}
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../../nvidia/common)
-endif
LIB = $(obj)lib$(BOARD).o
#include <common.h>
#include <i2c.h>
#include <asm/io.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
pin_mux_mmc();
/* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */
- tegra2_mmc_init(0, 4, -1, GPIO_PP1);
+ tegra20_mmc_init(0, 4, -1, GPIO_PP1);
/* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */
- tegra2_mmc_init(3, 4, -1, -1);
+ tegra20_mmc_init(3, 4, -1, -1);
return 0;
}
#include <asm/errno.h>
#include <hwconfig.h>
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_DRIVER_TI_EMAC
return 0;
}
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
+
+ /* Add slot-0 to mmc subsystem */
+ return davinci_mmc_init(bis, &mmc_sd0);
+}
+#endif
+
static const struct pinmux_config gpio_pins[] = {
#ifdef CONFIG_USE_NOR
/* GP0[11] is required for NOR to work on Rev 3 EVMs */
{ pinmux(0), 8, 4 }, /* GP0[11] */
#endif
+#ifdef CONFIG_DAVINCI_MMC
+ /* GP0[11] is required for SD to work on Rev 3 EVMs */
+ { pinmux(0), 8, 4 }, /* GP0[11] */
+#endif
};
const struct pinmux_resource pinmuxes[] = {
PINMUX_ITEM(emifa_pins_nor),
#endif
PINMUX_ITEM(gpio_pins),
+#ifdef CONFIG_DAVINCI_MMC
+ PINMUX_ITEM(mmc0_pins),
+#endif
};
const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
{ DAVINCI_LPSC_EMAC }, /* image download */
{ DAVINCI_LPSC_UART2 }, /* console */
{ DAVINCI_LPSC_GPIO },
+#ifdef CONFIG_DAVINCI_MMC
+ { DAVINCI_LPSC_MMC_SD },
+#endif
};
const int lpsc_size = ARRAY_SIZE(lpsc);
int board_init(void)
{
-#ifdef CONFIG_USE_NOR
+#if defined(CONFIG_USE_NOR) || defined(CONFIG_DAVINCI_MMC)
u32 val;
#endif
* NAND CS setup - cycle counts based on da850evm NAND timings in the
* Linux kernel @ 25MHz EMIFA
*/
- writel((DAVINCI_ABCR_WSETUP(0) |
- DAVINCI_ABCR_WSTROBE(1) |
- DAVINCI_ABCR_WHOLD(0) |
- DAVINCI_ABCR_RSETUP(0) |
- DAVINCI_ABCR_RSTROBE(1) |
+ writel((DAVINCI_ABCR_WSETUP(2) |
+ DAVINCI_ABCR_WSTROBE(2) |
+ DAVINCI_ABCR_WHOLD(1) |
+ DAVINCI_ABCR_RSETUP(1) |
+ DAVINCI_ABCR_RSTROBE(4) |
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(1) |
DAVINCI_ABCR_ASIZE_8BIT),
writel(val, GPIO_BANK0_REG_CLR_ADDR);
#endif
+#ifdef CONFIG_DAVINCI_MMC
+ /* Set the GPIO direction as output */
+ clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
+
+ /* Set the output as high */
+ val = readl(GPIO_BANK0_REG_SET_ADDR);
+ val |= (0x01 << 11);
+ writel(val, GPIO_BANK0_REG_SET_ADDR);
+#endif
+
#ifdef CONFIG_DRIVER_TI_EMAC
davinci_emac_mii_mode_sel(HAS_RMII);
#endif /* CONFIG_DRIVER_TI_EMAC */
--- /dev/null
+# PLL0CFG0 PLL0CFG1
+PLL0 0x00180001 0x00000205
+# PLL1CFG0 PLL1CFG1 DRPYC1R SDCR SDTIMR1 SDTIMR2 SDRCR CLK2XSRC
+DDR2 0x15010001 0x00000002 0x00000043 0x00134632 0x26492a09 0x7d13c722 0x00000249 0x00000000
* Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. <nsekhar@ti.com>
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
* Copyright (C) 2004 Texas Instruments.
+ * Copyright (C) 2012 Sughosh Ganu <urwithsughosh@gmail.com>.
*
* ----------------------------------------------------------------------------
* This program is free software; you can redistribute it and/or modify
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
#include <asm/arch/pinmux_defs.h>
+#include <asm/arch/da8xx-usb.h>
#include <ns16550.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+int usb_phy_on(void)
+{
+ u32 timeout;
+ u32 cfgchip2;
+
+ cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
+
+ cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN |
+ CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ |
+ CFGCHIP2_USB1PHYCLKMUX);
+ cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON |
+ CFGCHIP2_REFFREQ_24MHZ | CFGCHIP2_USB2PHYCLKMUX |
+ CFGCHIP2_USB1SUSPENDM;
+
+ writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
+
+ /* wait until the usb phy pll locks */
+ timeout = DA8XX_USB_OTG_TIMEOUT;
+ while (timeout--)
+ if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD)
+ return 1;
+
+ /* USB phy was not turned on */
+ return 0;
+}
+
+void usb_phy_off(void)
+{
+ u32 cfgchip2;
+
+ /*
+ * Power down the on-chip PHY.
+ */
+ cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
+ cfgchip2 &= ~(CFGCHIP2_PHY_PLLON | CFGCHIP2_USB1SUSPENDM);
+ cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | CFGCHIP2_RESET;
+ writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
+}
/* SSP0 clock at 96MHz */
mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
- /* SSP2 clock at 96MHz */
- mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
+ /* SSP2 clock at 160MHz */
+ mx28_set_sspclk(MXC_SSPCLK2, 160000, 0);
#ifdef CONFIG_CMD_USB
mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
int dram_init(void)
{
- return mx28_dram_init();
+ return mxs_dram_init();
}
#ifdef CONFIG_CMD_MMC
int board_eth_init(bd_t *bis)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct eth_device *dev;
int ret;
void board_init_ll(void)
{
- mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+ mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
}
+++ /dev/null
-/*
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
-#include <asm/gpio.h>
-#include <asm/errno.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/crm_regs.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <pmic.h>
-#include <fsl_pmic.h>
-#include <mc13892.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Compile-time error checking
- */
-#ifndef CONFIG_MXC_SPI
-#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
-#endif
-
-/*
- * Shared variables / local defines
- */
-/* LED */
-#define EFIKAMX_LED_BLUE 0x1
-#define EFIKAMX_LED_GREEN 0x2
-#define EFIKAMX_LED_RED 0x4
-
-void efikamx_toggle_led(uint32_t mask);
-
-/* Board revisions */
-#define EFIKAMX_BOARD_REV_11 0x1
-#define EFIKAMX_BOARD_REV_12 0x2
-#define EFIKAMX_BOARD_REV_13 0x3
-#define EFIKAMX_BOARD_REV_14 0x4
-
-#define EFIKASB_BOARD_REV_13 0x1
-#define EFIKASB_BOARD_REV_20 0x2
-
-/*
- * Board identification
- */
-u32 get_efikamx_rev(void)
-{
- u32 rev = 0;
- /*
- * Retrieve board ID:
- * rev1.1: 1,1,1
- * rev1.2: 1,1,0
- * rev1.3: 1,0,1
- * rev1.4: 1,0,0
- */
- mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
- /* set to 1 in order to get correct value on board rev1.1 */
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
-
- mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0;
-
- mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1;
-
- mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2;
-
- return (~rev & 0x7) + 1;
-}
-
-inline u32 get_efikasb_rev(void)
-{
- u32 rev = 0;
-
- mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS3, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3))) << 0;
-
- mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS4, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4))) << 1;
-
- return rev;
-}
-
-inline uint32_t get_efika_rev(void)
-{
- if (machine_is_efikamx())
- return get_efikamx_rev();
- else
- return get_efikasb_rev();
-}
-
-u32 get_board_rev(void)
-{
- return get_cpu_rev() | (get_efika_rev() << 8);
-}
-
-/*
- * DRAM initialization
- */
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-/*
- * UART configuration
- */
-static void setup_iomux_uart(void)
-{
- unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
- PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
-
- mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
- mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
-}
-
-/*
- * SPI configuration
- */
-#ifdef CONFIG_MXC_SPI
-static void setup_iomux_spi(void)
-{
- /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
- mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-
- /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-
- /* Configure SS0 as a GPIO */
- mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
-
- /* Configure SS1 as a GPIO */
- mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
-
- /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-}
-#else
-static inline void setup_iomux_spi(void) { }
-#endif
-
-/*
- * PMIC configuration
- */
-#ifdef CONFIG_MXC_SPI
-static void power_init(void)
-{
- unsigned int val;
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
- struct pmic *p;
-
- pmic_init();
- p = get_pmic();
-
- /* Write needed to Power Gate 2 register */
- pmic_reg_read(p, REG_POWER_MISC, &val);
- val &= ~PWGT2SPIEN;
- pmic_reg_write(p, REG_POWER_MISC, val);
-
- /* Externally powered */
- pmic_reg_read(p, REG_CHARGE, &val);
- val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
- pmic_reg_write(p, REG_CHARGE, val);
-
- /* power up the system first */
- pmic_reg_write(p, REG_POWER_MISC, PWUP);
-
- /* Set core voltage to 1.1V */
- pmic_reg_read(p, REG_SW_0, &val);
- val = (val & ~SWx_VOLT_MASK) | SWx_1_200V;
- pmic_reg_write(p, REG_SW_0, val);
-
- /* Setup VCC (SW2) to 1.25 */
- pmic_reg_read(p, REG_SW_1, &val);
- val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
- pmic_reg_write(p, REG_SW_1, val);
-
- /* Setup 1V2_DIG1 (SW3) to 1.25 */
- pmic_reg_read(p, REG_SW_2, &val);
- val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
- pmic_reg_write(p, REG_SW_2, val);
- udelay(50);
-
- /* Raise the core frequency to 800MHz */
- writel(0x0, &mxc_ccm->cacrr);
-
- /* Set switchers in Auto in NORMAL mode & STANDBY mode */
- /* Setup the switcher mode for SW1 & SW2*/
- pmic_reg_read(p, REG_SW_4, &val);
- val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
- (SWMODE_MASK << SWMODE2_SHIFT)));
- val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
- (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
- pmic_reg_write(p, REG_SW_4, val);
-
- /* Setup the switcher mode for SW3 & SW4 */
- pmic_reg_read(p, REG_SW_5, &val);
- val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
- (SWMODE_MASK << SWMODE4_SHIFT)));
- val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
- (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
- pmic_reg_write(p, REG_SW_5, val);
-
- /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
- pmic_reg_read(p, REG_SETTING_0, &val);
- val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
- val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6;
- pmic_reg_write(p, REG_SETTING_0, val);
-
- /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
- pmic_reg_read(p, REG_SETTING_1, &val);
- val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
- val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15;
- pmic_reg_write(p, REG_SETTING_1, val);
-
- /* Enable VGEN1, VGEN2, VDIG, VPLL */
- pmic_reg_read(p, REG_MODE_0, &val);
- val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN;
- pmic_reg_write(p, REG_MODE_0, val);
-
- /* Configure VGEN3 and VCAM regulators to use external PNP */
- val = VGEN3CONFIG | VCAMCONFIG;
- pmic_reg_write(p, REG_MODE_1, val);
- udelay(200);
-
- /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
- val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
- VVIDEOEN | VAUDIOEN | VSDEN;
- pmic_reg_write(p, REG_MODE_1, val);
-
- pmic_reg_read(p, REG_POWER_CTL2, &val);
- val |= WDIRESET;
- pmic_reg_write(p, REG_POWER_CTL2, val);
-
- udelay(2500);
-}
-#else
-static inline void power_init(void) { }
-#endif
-
-/*
- * MMC configuration
- */
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR, 1},
- {MMC_SDHC2_BASE_ADDR, 1},
-};
-
-static inline uint32_t efika_mmc_cd(void)
-{
- if (machine_is_efikamx())
- return MX51_PIN_GPIO1_0;
- else
- return MX51_PIN_EIM_CS2;
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- uint32_t cd = efika_mmc_cd();
- int ret;
-
- if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
- ret = !gpio_get_value(IOMUX_TO_GPIO(cd));
- else
- ret = !gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int ret;
- uint32_t cd = efika_mmc_cd();
-
- /* SDHC1 is used on all revisions, setup control pins first */
- mxc_request_iomux(cd,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(cd,
- PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
- PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
- PAD_CTL_ODE_OPENDRAIN_NONE |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_GPIO1_1,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
- PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
- PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
- PAD_CTL_SRE_FAST);
-
- gpio_direction_input(IOMUX_TO_GPIO(cd));
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1));
-
- /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
- if (machine_is_efikasb() || (machine_is_efikamx() &&
- (get_efika_rev() < EFIKAMX_BOARD_REV_12))) {
- /* SDHC1 IOMUX */
- mxc_request_iomux(MX51_PIN_SD1_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
-
- /* SDHC2 IOMUX */
- mxc_request_iomux(MX51_PIN_SD2_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD2_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- /* SDHC2 Control lines IOMUX */
- mxc_request_iomux(MX51_PIN_GPIO1_7,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_7,
- PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
- PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
- PAD_CTL_ODE_OPENDRAIN_NONE |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_GPIO1_8,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_8,
- PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
- PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
- PAD_CTL_SRE_FAST);
-
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7));
-
- ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
- if (!ret)
- ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
- } else { /* New boards use only SDHC1 */
- /* SDHC1 IOMUX */
- mxc_request_iomux(MX51_PIN_SD1_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
- }
-
- return ret;
-}
-#endif
-
-/*
- * ATA
- */
-#ifdef CONFIG_MX51_PATA
-#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH)
-void setup_iomux_ata(void)
-{
- mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG);
-}
-#else
-static inline void setup_iomux_ata(void) { }
-#endif
-
-/*
- * EHCI USB
- */
-#ifdef CONFIG_CMD_USB
-extern void setup_iomux_usb(void);
-#else
-static inline void setup_iomux_usb(void) { }
-#endif
-
-/*
- * LED configuration
- */
-void setup_iomux_led(void)
-{
- if (machine_is_efikamx()) {
- /* Blue LED */
- mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3);
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0);
-
- /* Green LED */
- mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3);
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0);
-
- /* Red LED */
- mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3);
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0);
- } else {
- /* CAPS-LOCK LED */
- mxc_request_iomux(MX51_PIN_EIM_CS0, IOMUX_CONFIG_GPIO);
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), 0);
-
- /* ALARM-LED LED */
- mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_GPIO);
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0);
- }
-}
-
-void efikamx_toggle_led(uint32_t mask)
-{
- if (machine_is_efikamx()) {
- gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
- mask & EFIKAMX_LED_BLUE);
- gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
- mask & EFIKAMX_LED_GREEN);
- gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
- mask & EFIKAMX_LED_RED);
- } else {
- gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0),
- mask & EFIKAMX_LED_BLUE);
- gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3),
- !(mask & EFIKAMX_LED_GREEN));
- }
-}
-
-/*
- * Board initialization
- */
-static void init_drive_strength(void)
-{
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
-
- /* Setting pad options */
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-}
-
-int board_early_init_f(void)
-{
- init_drive_strength();
-
- setup_iomux_uart();
- setup_iomux_spi();
- setup_iomux_led();
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-int board_late_init(void)
-{
- setup_iomux_spi();
-
- power_init();
-
- setup_iomux_led();
- setup_iomux_ata();
- setup_iomux_usb();
-
- if (machine_is_efikasb())
- setenv("preboot", "usb reset ; setenv stdin usbkbd\0");
-
- setup_iomux_led();
-
- efikamx_toggle_led(EFIKAMX_LED_BLUE);
-
- return 0;
-}
-
-int checkboard(void)
-{
- u32 rev = get_efika_rev();
-
- if (machine_is_efikamx()) {
- printf("Board: Efika MX, rev1.%i\n", rev & 0xf);
- return 0;
- } else {
- switch (rev) {
- case EFIKASB_BOARD_REV_13:
- printf("Board: Efika SB rev1.3\n");
- break;
- case EFIKASB_BOARD_REV_20:
- printf("Board: Efika SB rev2.0\n");
- break;
- default:
- printf("Board: Efika SB, rev Unknown\n");
- break;
- }
- }
-
- return 0;
-}
return ptr;
}
-static int enbw_cmc_config_switch(unsigned long addr)
+static struct spi_slave *enbw_cmc_init_spi(void)
{
struct spi_slave *spi;
- char *ptr = (char *)addr;
- int value, reg;
int ret;
- int bus, cs, max_hz, spi_mode;
-
- debug("configure switch with file on addr: 0x%lx\n", addr);
- bus = 0;
- cs = 0;
- max_hz = 1000000;
- spi_mode = 0;
-
- spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ spi = spi_setup_slave(0, 0, 1000000, 0);
if (!spi) {
printf("Failed to set up slave\n");
- return -EINVAL;
+ return NULL;
}
ret = spi_claim_bus(spi);
ret = enbw_cmc_switch_read_ident(spi);
if (ret)
- goto err_claim_bus;
+ goto err_read;
+
+ return spi;
+err_read:
+ spi_release_bus(spi);
+err_claim_bus:
+ spi_free_slave(spi);
+ return NULL;
+}
+
+static int enbw_cmc_config_switch(unsigned long addr)
+{
+ struct spi_slave *spi;
+ char *ptr = (char *)addr;
+ int value, reg;
+ int ret = 0;
+
+ debug("configure switch with file on addr: 0x%lx\n", addr);
+
+ spi = enbw_cmc_init_spi();
+ if (!spi)
+ return -EINVAL;
- ptr = (char *)addr;
while (ptr != NULL) {
ptr = enbw_cmc_getvalue(ptr, ®);
if (ptr != NULL) {
ptr = enbw_cmc_getvalue(ptr, &value);
if ((ptr != NULL) && (value >= 0))
- if (enbw_cmc_switch_write(spi, reg, value))
- goto err_read;
+ if (enbw_cmc_switch_write(spi, reg, value)) {
+ /* error writing to switch */
+ ptr = NULL;
+ ret = -EINVAL;
+ }
}
}
- return 0;
-err_read:
spi_release_bus(spi);
-err_claim_bus:
spi_free_slave(spi);
- return -EINVAL;
+ return ret;
}
static int do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
*/
int board_eth_init(bd_t *bis)
{
+ struct spi_slave *spi;
const char *s;
- size_t len;
+ size_t len = 0;
+ int config = 1;
davinci_emac_mii_mode_sel(0);
if (len) {
unsigned long addr = simple_strtoul(s, NULL, 16);
- enbw_cmc_config_switch(addr);
+ config = enbw_cmc_config_switch(addr);
}
+ if (config) {
+ /*
+ * no valid config file -> do we have some args in
+ * hwconfig ?
+ */
+ if ((hwconfig_subarg("switch", "lan", &len)) ||
+ (hwconfig_subarg("switch", "lmn", &len))) {
+ /* If so start switch */
+ spi = enbw_cmc_init_spi();
+ if (spi) {
+ if (enbw_cmc_switch_write(spi, 1, 0))
+ config = 0;
+ udelay(10000);
+ if (enbw_cmc_switch_write(spi, 1, 1))
+ config = 0;
+ spi_release_bus(spi);
+ spi_free_slave(spi);
+ }
+ } else {
+ config = 0;
+ }
+ }
if (!davinci_emac_initialize()) {
printf("Error: Ethernet init failed!\n");
return -1;
}
- if (hwconfig_subarg_cmp("switch", "lan", "on"))
- /* Switch port lan on */
- enbw_cmc_switch(1, 1);
- else
- enbw_cmc_switch(1, 0);
+ if (config) {
+ if (hwconfig_subarg_cmp("switch", "lan", "on"))
+ /* Switch port lan on */
+ enbw_cmc_switch(1, 1);
+ else
+ enbw_cmc_switch(1, 0);
- if (hwconfig_subarg_cmp("switch", "pwl", "on"))
- /* Switch port pwl on */
- enbw_cmc_switch(2, 1);
- else
- enbw_cmc_switch(2, 0);
+ if (hwconfig_subarg_cmp("switch", "lmn", "on"))
+ /* Switch port pwl on */
+ enbw_cmc_switch(2, 1);
+ else
+ enbw_cmc_switch(2, 0);
+ }
return 0;
}
}
#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR, 1 };
+struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR };
int board_mmc_getcd(struct mmc *mmc)
{
int board_init(void)
{
- /* Enable Ctrlc */
- console_init_f();
/* arch number of CPUAT91-Board */
gd->bd->bi_arch_number = MACH_TYPE_CPUAT91;
/* adress of boot parameters */
void board_init_ll(void)
{
- mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+ mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
}
int dram_init(void)
{
- return mx28_dram_init();
+ return mxs_dram_init();
}
int board_init(void)
int board_eth_init(bd_t *bis)
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct eth_device *dev;
int ret;
+++ /dev/null
-sources {
- u_boot_spl="spl/u-boot-spl.bin";
- u_boot="u-boot.bin";
-}
-
-section (0) {
- load u_boot_spl > 0x0000;
- load ivt (entry = 0x0014) > 0x8000;
- hab call 0x8000;
-
- load u_boot > 0x40000100;
- load ivt (entry = 0x40000100) > 0x8000;
- hab call 0x8000;
-}
/* enable clocks */
writel(readl(&ccm->cgr0) |
MXC_CCM_CGR0_EMI_MASK |
- MXC_CCM_CGR0_EDI0_MASK |
+ MXC_CCM_CGR0_EDIO_MASK |
MXC_CCM_CGR0_EPIT1_MASK,
&ccm->cgr0);
#include <linux/fb.h>
#include <ipu_pixfmt.h>
-#define MX51EVK_LCD_3V3 (3 * 32 + 9) /* GPIO4_9 */
-#define MX51EVK_LCD_5V (3 * 32 + 10) /* GPIO4_10 */
-#define MX51EVK_LCD_BACKLIGHT (2 * 32 + 4) /* GPIO3_4 */
+#define MX51EVK_LCD_3V3 IMX_GPIO_NR(4, 9)
+#define MX51EVK_LCD_5V IMX_GPIO_NR(4, 10)
+#define MX51EVK_LCD_BACKLIGHT IMX_GPIO_NR(3, 4)
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR, 1},
- {MMC_SDHC2_BASE_ADDR, 1},
+ {MMC_SDHC1_BASE_ADDR},
+ {MMC_SDHC2_BASE_ADDR},
};
#endif
pmic_reg_write(p, REG_MODE_1, val);
mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
- gpio_direction_output(46, 0);
+ gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
udelay(500);
- gpio_set_value(46, 1);
+ gpio_set_value(IMX_GPIO_NR(2, 14), 1);
}
#ifdef CONFIG_FSL_ESDHC
int ret;
mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1);
- gpio_direction_input(0);
+ gpio_direction_input(IMX_GPIO_NR(1, 0));
mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
- gpio_direction_input(6);
+ gpio_direction_input(IMX_GPIO_NR(1, 6));
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
- ret = !gpio_get_value(0);
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
else
- ret = !gpio_get_value(6);
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
return ret;
}
setup_iomux_spi();
power_init();
#endif
- setenv("stdout", "serial");
return 0;
}
#endif
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
int checkboard(void)
{
puts("Board: MX51EVK\n");
#include <fsl_esdhc.h>
#include <asm/gpio.h>
-#define ETHERNET_INT (1 * 32 + 31) /* GPIO2_31 */
+#define ETHERNET_INT IMX_GPIO_NR(2, 31)
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR, 1 },
- {MMC_SDHC2_BASE_ADDR, 1 },
+ {MMC_SDHC1_BASE_ADDR},
+ {MMC_SDHC2_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
int ret;
mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
- gpio_direction_input(1);
+ gpio_direction_input(IMX_GPIO_NR(1, 1));
mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1);
- gpio_direction_input(4);
+ gpio_direction_input(IMX_GPIO_NR(1, 4));
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
- ret = !gpio_get_value(1); /* GPIO1_1 */
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
else
- ret = !gpio_get_value(4); /* GPIO1_4 */
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
return ret;
}
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/errno.h>
+#include <asm/imx-common/boot_mode.h>
#include <netdev.h>
#include <i2c.h>
#include <mmc.h>
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR, 1},
- {MMC_SDHC3_BASE_ADDR, 1},
+ {MMC_SDHC1_BASE_ADDR},
+ {MMC_SDHC3_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
int ret;
mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
- gpio_direction_input(75);
+ gpio_direction_input(IMX_GPIO_NR(3, 11));
mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
- gpio_direction_input(77);
+ gpio_direction_input(IMX_GPIO_NR(3, 13));
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
- ret = !gpio_get_value(77); /* GPIO3_13 */
+ ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
else
- ret = !gpio_get_value(75); /* GPIO3_11 */
+ ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
return ret;
}
return 0;
}
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
+ {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
+ {NULL, 0},
+};
+#endif
+
int board_late_init(void)
{
setup_i2c(1);
power_init();
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
return 0;
}
#include <linux/fb.h>
#include <ipu_pixfmt.h>
-#define MX53LOCO_LCD_POWER (2 * 32 + 24) /* GPIO3_24 */
+#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR, 1},
- {MMC_SDHC3_BASE_ADDR, 1},
+ {MMC_SDHC1_BASE_ADDR},
+ {MMC_SDHC3_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
int ret;
mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
- gpio_direction_input(75);
+ gpio_direction_input(IMX_GPIO_NR(3, 11));
mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
- gpio_direction_input(77);
+ gpio_direction_input(IMX_GPIO_NR(3, 13));
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
- ret = !gpio_get_value(77); /* GPIO3_13 */
+ ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
else
- ret = !gpio_get_value(75); /* GPIO3_11 */
+ ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
return ret;
}
return 0;
}
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
{
- setenv("stdout", "serial");
-
- return 0;
+ return 1;
}
-#endif
int board_init(void)
{
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[1] = {
- {MMC_SDHC1_BASE_ADDR, 1},
+ {MMC_SDHC1_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
{
mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
- gpio_direction_input(77);
- return !gpio_get_value(77); /* GPIO3_13 */
+ gpio_direction_input(IMX_GPIO_NR(3, 13));
+ return !gpio_get_value(IMX_GPIO_NR(3, 13));
}
int board_mmc_init(bd_t *bis)
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC3_BASE_ADDR, 1},
- {USDHC4_BASE_ADDR, 1},
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
int ret;
if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
- gpio_direction_input(171); /*GPIO6_11*/
- ret = !gpio_get_value(171);
+ gpio_direction_input(IMX_GPIO_NR(6, 11));
+ ret = !gpio_get_value(IMX_GPIO_NR(6, 11));
} else /* Don't have the CD GPIO pin on board */
ret = 1;
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
#include <asm/arch/mx6x_pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <micrel.h>
.scl = {
.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
.gpio_mode = MX6Q_PAD_EIM_D21__GPIO_3_21 | PC,
- .gp = GPIO_NUMBER(3, 21)
+ .gp = IMX_GPIO_NR(3, 21)
},
.sda = {
.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
.gpio_mode = MX6Q_PAD_EIM_D28__GPIO_3_28 | PC,
- .gp = GPIO_NUMBER(3, 28)
+ .gp = IMX_GPIO_NR(3, 28)
}
};
.scl = {
.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO_4_12 | PC,
- .gp = GPIO_NUMBER(4, 12)
+ .gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO_4_13 | PC,
- .gp = GPIO_NUMBER(4, 13)
+ .gp = IMX_GPIO_NR(4, 13)
}
};
.scl = {
.i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL | PC,
.gpio_mode = MX6Q_PAD_GPIO_5__GPIO_1_5 | PC,
- .gp = GPIO_NUMBER(1, 5)
+ .gp = IMX_GPIO_NR(1, 5)
},
.sda = {
.i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA | PC,
.gpio_mode = MX6Q_PAD_GPIO_16__GPIO_7_11 | PC,
- .gp = GPIO_NUMBER(7, 11)
+ .gp = IMX_GPIO_NR(7, 11)
}
};
imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
/* Reset USB hub */
- gpio_direction_output(GPIO_NUMBER(7, 12), 0);
+ gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
mdelay(2);
- gpio_set_value(GPIO_NUMBER(7, 12), 1);
+ gpio_set_value(IMX_GPIO_NR(7, 12), 1);
return 0;
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC3_BASE_ADDR, 1},
- {USDHC4_BASE_ADDR, 1},
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
};
static struct button_key const buttons[] = {
- {"back", GPIO_NUMBER(2, 2), 'B'},
- {"home", GPIO_NUMBER(2, 4), 'H'},
- {"menu", GPIO_NUMBER(2, 1), 'M'},
- {"search", GPIO_NUMBER(2, 3), 'S'},
- {"volup", GPIO_NUMBER(7, 13), 'V'},
- {"voldown", GPIO_NUMBER(4, 5), 'v'},
+ {"back", IMX_GPIO_NR(2, 2), 'B'},
+ {"home", IMX_GPIO_NR(2, 4), 'H'},
+ {"menu", IMX_GPIO_NR(2, 1), 'M'},
+ {"search", IMX_GPIO_NR(2, 3), 'S'},
+ {"volup", IMX_GPIO_NR(7, 13), 'V'},
+ {"voldown", IMX_GPIO_NR(4, 5), 'v'},
};
/*
}
#endif
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
int misc_init_r(void)
{
#ifdef CONFIG_PREBOOT
preboot_keys();
#endif
+
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
return 0;
}
#include <usb/ulpi.h>
#include <errno.h>
-#include "../../drivers/usb/host/ehci.h"
+#include "../../../drivers/usb/host/ehci.h"
/* USB pin configuration */
#define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
--- /dev/null
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2009-2012 Genesi USA, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx51.h>
+#include <asm/gpio.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <pmic.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Compile-time error checking
+ */
+#ifndef CONFIG_MXC_SPI
+#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
+#endif
+
+/*
+ * Board revisions
+ *
+ * Note that we get these revisions here for convenience, but we only set
+ * up for the production model Smarttop (1.3) and Smartbook (2.0).
+ *
+ */
+#define EFIKAMX_BOARD_REV_11 0x1
+#define EFIKAMX_BOARD_REV_12 0x2
+#define EFIKAMX_BOARD_REV_13 0x3
+#define EFIKAMX_BOARD_REV_14 0x4
+
+#define EFIKASB_BOARD_REV_13 0x1
+#define EFIKASB_BOARD_REV_20 0x2
+
+/*
+ * Board identification
+ */
+static u32 get_mx_rev(void)
+{
+ u32 rev = 0;
+ /*
+ * Retrieve board ID:
+ *
+ * gpio: 16 17 11
+ * ==============
+ * r1.1: 1+ 1 1
+ * r1.2: 1 1 0
+ * r1.3: 1 0 1
+ * r1.4: 1 0 0
+ *
+ * + note: r1.1 does not strap this pin properly so it needs to
+ * be hacked or ignored.
+ */
+
+ /* set to 1 in order to get correct value on board rev 1.1 */
+ gpio_direction_output(IMX_GPIO_NR(3, 16), 1);
+ gpio_direction_input(IMX_GPIO_NR(3, 11));
+ gpio_direction_input(IMX_GPIO_NR(3, 16));
+ gpio_direction_input(IMX_GPIO_NR(3, 17));
+
+ rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0;
+ rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1;
+ rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2;
+
+ return (~rev & 0x7) + 1;
+}
+
+static iomux_v3_cfg_t efikasb_revision_pads[] = {
+ MX51_PAD_EIM_CS3__GPIO2_28,
+ MX51_PAD_EIM_CS4__GPIO2_29,
+};
+
+static inline u32 get_sb_rev(void)
+{
+ u32 rev = 0;
+
+ imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads,
+ ARRAY_SIZE(efikasb_revision_pads));
+ gpio_direction_input(IMX_GPIO_NR(2, 28));
+ gpio_direction_input(IMX_GPIO_NR(2, 29));
+
+ rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0;
+ rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1;
+
+ return rev;
+}
+
+inline uint32_t get_efikamx_rev(void)
+{
+ if (machine_is_efikamx())
+ return get_mx_rev();
+ else if (machine_is_efikasb())
+ return get_sb_rev();
+}
+
+u32 get_board_rev(void)
+{
+ return get_cpu_rev() | (get_efikamx_rev() << 8);
+}
+
+/*
+ * DRAM initialization
+ */
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+/*
+ * UART configuration
+ */
+static iomux_v3_cfg_t efikamx_uart_pads[] = {
+ MX51_PAD_UART1_RXD__UART1_RXD,
+ MX51_PAD_UART1_TXD__UART1_TXD,
+ MX51_PAD_UART1_RTS__UART1_RTS,
+ MX51_PAD_UART1_CTS__UART1_CTS,
+};
+
+/*
+ * SPI configuration
+ */
+static iomux_v3_cfg_t efikamx_spi_pads[] = {
+ MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
+ MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
+ MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
+ MX51_PAD_CSPI1_SS0__GPIO4_24,
+ MX51_PAD_CSPI1_SS1__GPIO4_25,
+ MX51_PAD_GPIO1_6__GPIO1_6,
+};
+
+#define EFIKAMX_SPI_SS0 IMX_GPIO_NR(4, 24)
+#define EFIKAMX_SPI_SS1 IMX_GPIO_NR(4, 25)
+#define EFIKAMX_PMIC_IRQ IMX_GPIO_NR(1, 6)
+
+/*
+ * PMIC configuration
+ */
+#ifdef CONFIG_MXC_SPI
+static void power_init(void)
+{
+ unsigned int val;
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+ struct pmic *p;
+
+ pmic_init();
+ p = get_pmic();
+
+ /* Write needed to Power Gate 2 register */
+ pmic_reg_read(p, REG_POWER_MISC, &val);
+ val &= ~PWGT2SPIEN;
+ pmic_reg_write(p, REG_POWER_MISC, val);
+
+ /* Externally powered */
+ pmic_reg_read(p, REG_CHARGE, &val);
+ val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
+ pmic_reg_write(p, REG_CHARGE, val);
+
+ /* power up the system first */
+ pmic_reg_write(p, REG_POWER_MISC, PWUP);
+
+ /* Set core voltage to 1.1V */
+ pmic_reg_read(p, REG_SW_0, &val);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
+ pmic_reg_write(p, REG_SW_0, val);
+
+ /* Setup VCC (SW2) to 1.25 */
+ pmic_reg_read(p, REG_SW_1, &val);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+ pmic_reg_write(p, REG_SW_1, val);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.25 */
+ pmic_reg_read(p, REG_SW_2, &val);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+ pmic_reg_write(p, REG_SW_2, val);
+ udelay(50);
+
+ /* Raise the core frequency to 800MHz */
+ writel(0x0, &mxc_ccm->cacrr);
+
+ /* Set switchers in Auto in NORMAL mode & STANDBY mode */
+ /* Setup the switcher mode for SW1 & SW2*/
+ pmic_reg_read(p, REG_SW_4, &val);
+ val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+ (SWMODE_MASK << SWMODE2_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+ pmic_reg_write(p, REG_SW_4, val);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ pmic_reg_read(p, REG_SW_5, &val);
+ val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
+ (SWMODE_MASK << SWMODE4_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
+ pmic_reg_write(p, REG_SW_5, val);
+
+ /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
+ pmic_reg_read(p, REG_SETTING_0, &val);
+ val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
+ val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6;
+ pmic_reg_write(p, REG_SETTING_0, val);
+
+ /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
+ pmic_reg_read(p, REG_SETTING_1, &val);
+ val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
+ val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15;
+ pmic_reg_write(p, REG_SETTING_1, val);
+
+ /* Enable VGEN1, VGEN2, VDIG, VPLL */
+ pmic_reg_read(p, REG_MODE_0, &val);
+ val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN;
+ pmic_reg_write(p, REG_MODE_0, val);
+
+ /* Configure VGEN3 and VCAM regulators to use external PNP */
+ val = VGEN3CONFIG | VCAMCONFIG;
+ pmic_reg_write(p, REG_MODE_1, val);
+ udelay(200);
+
+ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
+ VVIDEOEN | VAUDIOEN | VSDEN;
+ pmic_reg_write(p, REG_MODE_1, val);
+
+ pmic_reg_read(p, REG_POWER_CTL2, &val);
+ val |= WDIRESET;
+ pmic_reg_write(p, REG_POWER_CTL2, val);
+
+ udelay(2500);
+}
+#else
+static inline void power_init(void) { }
+#endif
+
+/*
+ * MMC configuration
+ */
+#ifdef CONFIG_FSL_ESDHC
+
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {MMC_SDHC1_BASE_ADDR},
+ {MMC_SDHC2_BASE_ADDR},
+};
+
+static iomux_v3_cfg_t efikamx_sdhc1_pads[] = {
+ MX51_PAD_SD1_CMD__SD1_CMD,
+ MX51_PAD_SD1_CLK__SD1_CLK,
+ MX51_PAD_SD1_DATA0__SD1_DATA0,
+ MX51_PAD_SD1_DATA1__SD1_DATA1,
+ MX51_PAD_SD1_DATA2__SD1_DATA2,
+ MX51_PAD_SD1_DATA3__SD1_DATA3,
+ MX51_PAD_GPIO1_1__SD1_WP,
+};
+
+#define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1, 1)
+
+static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = {
+ MX51_PAD_GPIO1_0__SD1_CD,
+ MX51_PAD_EIM_CS2__SD1_CD,
+};
+
+#define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0)
+#define EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27)
+
+static iomux_v3_cfg_t efikasb_sdhc2_pads[] = {
+ MX51_PAD_SD2_CMD__SD2_CMD,
+ MX51_PAD_SD2_CLK__SD2_CLK,
+ MX51_PAD_SD2_DATA0__SD2_DATA0,
+ MX51_PAD_SD2_DATA1__SD2_DATA1,
+ MX51_PAD_SD2_DATA2__SD2_DATA2,
+ MX51_PAD_SD2_DATA3__SD2_DATA3,
+ MX51_PAD_GPIO1_7__SD2_WP,
+ MX51_PAD_GPIO1_8__SD2_CD,
+};
+
+#define EFIKASB_SDHC2_CD IMX_GPIO_NR(1, 8)
+#define EFIKASB_SDHC2_WP IMX_GPIO_NR(1, 7)
+
+static inline uint32_t efikamx_mmc_getcd(u32 base)
+{
+ if (base == MMC_SDHC1_BASE_ADDR)
+ if (machine_is_efikamx())
+ return EFIKAMX_SDHC1_CD;
+ else
+ return EFIKASB_SDHC1_CD;
+ else
+ return EFIKASB_SDHC2_CD;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
+ int ret = !gpio_get_value(cd);
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ /*
+ * All Efika MX boards use eSDHC1 with a common write-protect GPIO
+ */
+ imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads,
+ ARRAY_SIZE(efikamx_sdhc1_pads));
+ gpio_direction_input(EFIKAMX_SDHC1_WP);
+
+ /*
+ * Smartbook and Smarttop differ on the location of eSDHC1
+ * carrier-detect GPIO
+ */
+ if (machine_is_efikamx()) {
+ imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);
+ gpio_direction_input(EFIKAMX_SDHC1_CD);
+ } else if (machine_is_efikasb()) {
+ imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);
+ gpio_direction_input(EFIKASB_SDHC1_CD);
+ }
+
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+
+ if (machine_is_efikasb()) {
+
+ imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads,
+ ARRAY_SIZE(efikasb_sdhc2_pads));
+ gpio_direction_input(EFIKASB_SDHC2_CD);
+ gpio_direction_input(EFIKASB_SDHC2_WP);
+ if (!ret)
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
+ }
+
+ return ret;
+}
+#endif
+
+/*
+ * PATA
+ */
+static iomux_v3_cfg_t efikamx_pata_pads[] = {
+ MX51_PAD_NANDF_WE_B__PATA_DIOW,
+ MX51_PAD_NANDF_RE_B__PATA_DIOR,
+ MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
+ MX51_PAD_NANDF_CLE__PATA_RESET_B,
+ MX51_PAD_NANDF_WP_B__PATA_DMACK,
+ MX51_PAD_NANDF_RB0__PATA_DMARQ,
+ MX51_PAD_NANDF_RB1__PATA_IORDY,
+ MX51_PAD_GPIO_NAND__PATA_INTRQ,
+ MX51_PAD_NANDF_CS2__PATA_CS_0,
+ MX51_PAD_NANDF_CS3__PATA_CS_1,
+ MX51_PAD_NANDF_CS4__PATA_DA_0,
+ MX51_PAD_NANDF_CS5__PATA_DA_1,
+ MX51_PAD_NANDF_CS6__PATA_DA_2,
+ MX51_PAD_NANDF_D15__PATA_DATA15,
+ MX51_PAD_NANDF_D14__PATA_DATA14,
+ MX51_PAD_NANDF_D13__PATA_DATA13,
+ MX51_PAD_NANDF_D12__PATA_DATA12,
+ MX51_PAD_NANDF_D11__PATA_DATA11,
+ MX51_PAD_NANDF_D10__PATA_DATA10,
+ MX51_PAD_NANDF_D9__PATA_DATA9,
+ MX51_PAD_NANDF_D8__PATA_DATA8,
+ MX51_PAD_NANDF_D7__PATA_DATA7,
+ MX51_PAD_NANDF_D6__PATA_DATA6,
+ MX51_PAD_NANDF_D5__PATA_DATA5,
+ MX51_PAD_NANDF_D4__PATA_DATA4,
+ MX51_PAD_NANDF_D3__PATA_DATA3,
+ MX51_PAD_NANDF_D2__PATA_DATA2,
+ MX51_PAD_NANDF_D1__PATA_DATA1,
+ MX51_PAD_NANDF_D0__PATA_DATA0,
+};
+
+/*
+ * EHCI USB
+ */
+#ifdef CONFIG_CMD_USB
+extern void setup_iomux_usb(void);
+#else
+static inline void setup_iomux_usb(void) { }
+#endif
+
+/*
+ * LED configuration
+ *
+ * Smarttop LED pad config is done in the DCD
+ *
+ */
+#define EFIKAMX_LED_BLUE IMX_GPIO_NR(3, 13)
+#define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14)
+#define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15)
+
+static iomux_v3_cfg_t efikasb_led_pads[] = {
+ MX51_PAD_GPIO1_3__GPIO1_3,
+ MX51_PAD_EIM_CS0__GPIO2_25,
+};
+
+#define EFIKASB_CAPSLOCK_LED IMX_GPIO_NR(2, 25)
+#define EFIKASB_MESSAGE_LED IMX_GPIO_NR(1, 3) /* Note: active low */
+
+/*
+ * Board initialization
+ */
+int board_early_init_f(void)
+{
+ if (machine_is_efikasb()) {
+ imx_iomux_v3_setup_multiple_pads(efikasb_led_pads,
+ ARRAY_SIZE(efikasb_led_pads));
+ gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);
+ gpio_direction_output(EFIKASB_MESSAGE_LED, 1);
+ } else if (machine_is_efikamx()) {
+ /*
+ * Set up GPIO directions for LEDs.
+ * IOMUX has been done in the DCD already.
+ * Turn the red LED on for pre-relocation code.
+ */
+ gpio_direction_output(EFIKAMX_LED_BLUE, 0);
+ gpio_direction_output(EFIKAMX_LED_GREEN, 0);
+ gpio_direction_output(EFIKAMX_LED_RED, 1);
+ }
+
+ /*
+ * Both these pad configurations for UART and SPI are kind of redundant
+ * since they are the Power-On Defaults for the i.MX51. But, it seems we
+ * should make absolutely sure that they are set up correctly.
+ */
+ imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads,
+ ARRAY_SIZE(efikamx_uart_pads));
+ imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads,
+ ARRAY_SIZE(efikamx_spi_pads));
+
+ /* not technically required for U-Boot operation but do it anyway. */
+ gpio_direction_input(EFIKAMX_PMIC_IRQ);
+ /* Deselect both CS for now, otherwise NOR doesn't probe properly. */
+ gpio_direction_output(EFIKAMX_SPI_SS0, 0);
+ gpio_direction_output(EFIKAMX_SPI_SS1, 1);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ if (machine_is_efikamx()) {
+ /*
+ * Set up Blue LED for "In U-Boot" status.
+ * We're all relocated and ready to U-Boot!
+ */
+ gpio_set_value(EFIKAMX_LED_RED, 0);
+ gpio_set_value(EFIKAMX_LED_GREEN, 0);
+ gpio_set_value(EFIKAMX_LED_BLUE, 1);
+ }
+
+ power_init();
+
+ imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads,
+ ARRAY_SIZE(efikamx_pata_pads));
+ setup_iomux_usb();
+
+ if (machine_is_efikasb())
+ setenv("preboot", "usb reset ; setenv stdin usbkbd\0");
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ u32 rev = get_efikamx_rev();
+
+ printf("Board: Genesi Efika MX ");
+ if (machine_is_efikamx())
+ printf("Smarttop (1.%i)\n", rev & 0xf);
+ else if (machine_is_efikasb())
+ printf("Smartbook\n");
+
+ return 0;
+}
#
+# Copyright (C) 2009 Pegatron Corporation
# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+# Copyright (C) 2009-2012 Genesi USA, Inc.
#
# BASED ON: imx51evk
#
# Address absolute address of the register
# value value to be stored in the register
-# Setting IOMUXC
-DATA 4 0x73fa88a0 0x000
-DATA 4 0x73fa850c 0x20c5
-DATA 4 0x73fa8510 0x20c5
-DATA 4 0x73fa883c 0x5
-DATA 4 0x73fa8848 0x5
-DATA 4 0x73fa84b8 0xe7
-DATA 4 0x73fa84bc 0x45
-DATA 4 0x73fa84c0 0x45
-DATA 4 0x73fa84c4 0x45
-DATA 4 0x73fa84c8 0x45
-DATA 4 0x73fa8820 0x0
-DATA 4 0x73fa84a4 0x5
-DATA 4 0x73fa84a8 0x5
-DATA 4 0x73fa84ac 0xe5
-DATA 4 0x73fa84b0 0xe5
-DATA 4 0x73fa84b4 0xe5
-DATA 4 0x73fa84cc 0xe5
-DATA 4 0x73fa84d0 0xe4
+# Essential GPIO settings to be done as early as possible
+# PCBIDn pad settings are all the defaults except #2 which needs HVE off
+DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16
+DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17
+DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11
+DATA 4 0x73fa8504 0xe4 # PCBID2 PAD ~HVE
+DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13
+DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14
+DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15
-DATA 4 0x73fa882c 0x4
-DATA 4 0x73fa88a4 0x4
-DATA 4 0x73fa88ac 0x4
-DATA 4 0x73fa88b8 0x4
+# DDR bus IOMUX PAD settings
+DATA 4 0x73fa850c 0x20c5 # SDODT1
+DATA 4 0x73fa8510 0x20c5 # SDODT0
+DATA 4 0x73fa84ac 0xc5 # SDWE
+DATA 4 0x73fa84b0 0xc5 # SDCKE0
+DATA 4 0x73fa84b4 0xc5 # SDCKE1
+DATA 4 0x73fa84cc 0xc5 # DRAM_CS0
+DATA 4 0x73fa84d0 0xc5 # DRAM_CS1
+DATA 4 0x73fa882c 0x2 # DRAM_B4
+DATA 4 0x73fa88a4 0x2 # DRAM_B0
+DATA 4 0x73fa88ac 0x2 # DRAM_B1
+DATA 4 0x73fa88b8 0x2 # DRAM_B2
+DATA 4 0x73fa84d4 0xc5 # DRAM_DQM0
+DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1
+DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2
+DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
# Setting DDR for micron
# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
#
+# Copyright (C) 2009 Pegatron Corporation
# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+# Copyright (C) 2009-2012 Genesi USA, Inc.
#
# BASED ON: imx51evk
#
# Address absolute address of the register
# value value to be stored in the register
-# Setting IOMUXC
-DATA 4 0x73fa88a0 0x200
-DATA 4 0x73fa850c 0x20c3
-DATA 4 0x73fa8510 0x20c3
-DATA 4 0x73fa883c 0x2
-DATA 4 0x73fa8848 0x2
-DATA 4 0x73fa84b8 0xe7
-DATA 4 0x73fa84bc 0x45
-DATA 4 0x73fa84c0 0x45
-DATA 4 0x73fa84c4 0x45
-DATA 4 0x73fa84c8 0x45
-DATA 4 0x73fa8820 0x0
-DATA 4 0x73fa84a4 0x5
-DATA 4 0x73fa84a8 0x5
-DATA 4 0x73fa84ac 0xe3
-DATA 4 0x73fa84b0 0xe3
-DATA 4 0x73fa84b4 0xe3
-DATA 4 0x73fa84cc 0xe3
-DATA 4 0x73fa84d0 0xe2
-
-DATA 4 0x73fa882c 0x4
-DATA 4 0x73fa88a4 0x4
-DATA 4 0x73fa88ac 0x4
-DATA 4 0x73fa88b8 0x4
+# DDR bus IOMUX PAD settings
+DATA 4 0x73fa88a0 0x200 # GRP_INMODE1
+DATA 4 0x73fa850c 0x20c5 # SDODT1
+DATA 4 0x73fa8510 0x20c5 # SDODT0
+DATA 4 0x73fa8848 0x4 # DDR_A1
+DATA 4 0x73fa84b8 0xe7 # DRAM_SDCLK
+DATA 4 0x73fa84bc 0x45 # DRAM_SDQS0
+DATA 4 0x73fa84c0 0x45 # DRAM_SDQS1
+DATA 4 0x73fa84c4 0x45 # DRAM_SDQS2
+DATA 4 0x73fa84c8 0x45 # DRAM_SDQS3
+DATA 4 0x73fa8820 0x0 # DDRPKS
+DATA 4 0x73fa84ac 0xe5 # SDWE
+DATA 4 0x73fa84b0 0xe5 # SDCKE0
+DATA 4 0x73fa84b4 0xe5 # SDCKE1
+DATA 4 0x73fa84cc 0xe5 # DRAM_CS0
+DATA 4 0x73fa84d0 0xe4 # DRAM_CS1
# Setting DDR for micron
# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
DATA 4 0x83fd9014 0x00008014
DATA 4 0x83fd9014 0x0632801c
DATA 4 0x83fd9014 0x0380801d
-DATA 4 0x83fd9014 0x0040801d
+DATA 4 0x83fd9014 0x0042801d
DATA 4 0x83fd9014 0x00008004
# Write to CTL0
DECLARE_GLOBAL_DATA_PTR;
+#define HOT_WATER_BUTTON 38
+
#ifdef CONFIG_USB_EHCI
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
return 0;
}
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ if (gpio_request(HOT_WATER_BUTTON, "hot-water-button") < 0) {
+ puts("Failed to get hot-water-button pin\n");
+ return -ENODEV;
+ }
+ gpio_direction_input(HOT_WATER_BUTTON);
+
+ /*
+ * if hot-water-button is pressed
+ * change bootcmd
+ */
+ if (gpio_get_value(HOT_WATER_BUTTON))
+ return 0;
+
+ setenv("bootcmd", "run swupdate");
+ return 0;
+}
+#endif
+
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
/* HSUSB2_dat3 */\
/* CCDC */\
MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_HD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M4)) \
+ /* CCDC_FIELD: gpio_95, uP-TXD4 */ \
+ MUX_VAL(CP(CCDC_FIELD), (IDIS | PTD | DIS | M2)) \
+ /* CCDC_HD: gpio_96, uP-RTS4# */ \
+ MUX_VAL(CP(CCDC_HD), (IDIS | PTD | DIS | M2)) \
+ /* CCDC_VD: gpio_97, uP-CTS4# */ \
+ MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M2)) \
+ /* CCDC_WEN: gpio_98, uP-RXD4 */ \
+ MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M2)) \
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \
return 0;
}
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: omap_rev_string
+ * Description: For SPL builds output board rev
+ */
+void omap_rev_string(void)
+{
+}
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
+ u32 *mr)
+{
+ *mr = MICRON_V_MR_165;
+#ifdef CONFIG_BOOT_NAND
+ *mcfg = MICRON_V_MCFG_200(256 << 20);
+ *ctrla = MICRON_V_ACTIMA_200;
+ *ctrlb = MICRON_V_ACTIMB_200;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+#else
+ if (get_cpu_family() == CPU_OMAP34XX) {
+ *mcfg = NUMONYX_V_MCFG_165(256 << 20);
+ *ctrla = NUMONYX_V_ACTIMA_165;
+ *ctrlb = NUMONYX_V_ACTIMB_165;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+
+ } else {
+ *mcfg = NUMONYX_V_MCFG_200(256 << 20);
+ *ctrla = NUMONYX_V_ACTIMA_200;
+ *ctrlb = NUMONYX_V_ACTIMB_200;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ }
+#endif
+}
+#endif
+
/*
* Routine: setup_net_chip
* Description: Setting up the configuration GPMC registers specific to the
}
#endif
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0, 0, 0);
const omap3_sysinfo sysinfo = {
DDR_STACKED,
"IGEP v2 board",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
"ONENAND",
+#else
+ "NAND",
+#endif
};
static void setup_net_chip(void);
return 0;
}
-#ifdef CONFIG_GENERIC_MMC
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: omap_rev_string
+ * Description: For SPL builds output board rev
+ */
+void omap_rev_string(void)
+{
+}
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
+ u32 *mr)
+{
+ *mr = MICRON_V_MR_165;
+#ifdef CONFIG_BOOT_NAND
+ *mcfg = MICRON_V_MCFG_200(256 << 20);
+ *ctrla = MICRON_V_ACTIMA_200;
+ *ctrlb = MICRON_V_ACTIMB_200;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+#else
+ if (get_cpu_family() == CPU_OMAP34XX) {
+ *mcfg = NUMONYX_V_MCFG_165(256 << 20);
+ *ctrla = NUMONYX_V_ACTIMA_165;
+ *ctrlb = NUMONYX_V_ACTIMB_165;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+
+ } else {
+ *mcfg = NUMONYX_V_MCFG_200(256 << 20);
+ *ctrla = NUMONYX_V_ACTIMA_200;
+ *ctrlb = NUMONYX_V_ACTIMB_200;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ }
+#endif
+}
+#endif
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0, 0, 0);
const omap3_sysinfo sysinfo = {
DDR_STACKED,
"OMAP3 IGEP module",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
"ONENAND",
+#else
+ "NAND",
+#endif
};
/*
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FEC_MXC
+#define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7)
+#define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9)
+
void tx25_fec_init(void)
{
struct iomuxc_mux_ctl *muxctl;
struct iomuxc_pad_ctl *padctl;
- u32 val;
u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
- struct gpio_regs *gpio4 = (struct gpio_regs *)IMX_GPIO4_BASE;
- struct gpio_regs *gpio3 = (struct gpio_regs *)IMX_GPIO3_BASE;
u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode;
debug("tx25_fec_init\n");
writel(0x0, &padctl->pad_d11);
/* drop PHY power and assert reset (low) */
- val = readl(&gpio4->gpio_dr) & ~((1 << 7) | (1 << 9));
- writel(val, &gpio4->gpio_dr);
- val = readl(&gpio4->gpio_dir) | (1 << 7) | (1 << 9);
- writel(val, &gpio4->gpio_dir);
+ gpio_direction_output(GPIO_FEC_RESET_B, 0);
+ gpio_direction_output(GPIO_FEC_ENABLE_B, 0);
mdelay(5);
debug("resetting phy\n");
/* turn on PHY power leaving reset asserted */
- val = readl(&gpio4->gpio_dr) | 1 << 9;
- writel(val, &gpio4->gpio_dr);
+ gpio_set_value(GPIO_FEC_ENABLE_B, 1);
mdelay(10);
/*
* set each to 1 and make each an output
*/
- val = readl(&gpio3->gpio_dr) | (1 << 10) | (1 << 11) | (1 << 12);
- writel(val, &gpio3->gpio_dr);
- val = readl(&gpio3->gpio_dir) | (1 << 10) | (1 << 11) | (1 << 12);
- writel(val, &gpio3->gpio_dir);
+ gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
+ gpio_direction_output(IMX_GPIO_NR(3, 11), 1);
+ gpio_direction_output(IMX_GPIO_NR(3, 12), 1);
mdelay(22); /* this value came from RedBoot */
/*
* deassert PHY reset
*/
- val = readl(&gpio4->gpio_dr) | 1 << 7;
- writel(val, &gpio4->gpio_dr);
- writel(val, &gpio4->gpio_dr);
+ gpio_set_value(GPIO_FEC_RESET_B, 1);
mdelay(5);
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
+#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
- struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
#if defined(CONFIG_SYS_NAND_LARGEPAGE)
struct system_control_regs *sc_regs =
(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
#ifdef CONFIG_FEC_MXC
mx27_fec_init_pins();
imx_gpio_mode((GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31));
- writel(readl(®s->port[PORTC].dr) | (1 << 31),
- ®s->port[PORTC].dr);
+ gpio_set_value(GPIO_PORTC | 31, 1);
#endif
#ifdef CONFIG_MXC_MMC
#if defined(CONFIG_MAGNESIUM)
#include <ns16550.h>
#include <linux/compiler.h>
#include <asm/io.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/board.h>
DECLARE_GLOBAL_DATA_PTR;
-const struct tegra2_sysinfo sysinfo = {
- CONFIG_TEGRA2_BOARD_STRING
+const struct tegra20_sysinfo sysinfo = {
+ CONFIG_TEGRA20_BOARD_STRING
};
+#ifndef CONFIG_SPL_BUILD
/*
* Routine: timer_init
* Description: init the timestamp and lastinc value
{
return 0;
}
+#endif
void __pin_mux_usb(void)
{
*/
static void power_det_init(void)
{
-#if defined(CONFIG_TEGRA2)
- struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+#if defined(CONFIG_TEGRA20)
+ struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
/* turn off power detects */
writel(0, &pmc->pmc_pwr_det_latch);
board_usb_init(gd->fdt_blob);
#endif
-#ifdef CONFIG_TEGRA2_LP0
+#ifdef CONFIG_TEGRA20_LP0
+ /* save Sdram params to PMC 2, 4, and 24 for WB0 */
+ warmboot_save_sdram_params();
+
/* prepare the WB code to LP0 location */
warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
#endif
#include <asm/arch/emc.h>
#include <asm/arch/pmu.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/uart-spi-switch.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <asm/arch/tegra_spi.h>
/include/ ARCH_CPU_DTS
/ {
- model = "NVIDIA Tegra2 Harmony evaluation board";
+ model = "NVIDIA Tegra20 Harmony evaluation board";
compatible = "nvidia,harmony", "nvidia,tegra20";
aliases {
/include/ ARCH_CPU_DTS
/ {
- model = "NVIDIA Tegra2 Ventana evaluation board";
+ model = "NVIDIA Tegra20 Ventana evaluation board";
compatible = "nvidia,ventana", "nvidia,tegra20";
aliases {
/include/ ARCH_CPU_DTS
/ {
- model = "NVIDIA Tegra2 Whistler evaluation board";
+ model = "NVIDIA Tegra20 Whistler evaluation board";
compatible = "nvidia,whistler", "nvidia,tegra20";
aliases {
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
debug("board_mmc_init: init SD slot J26\n");
/* init dev 0, SD slot J26, with 4-bit bus */
/* The board has an 8-bit bus, but 8-bit doesn't work yet */
- tegra2_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
+ tegra20_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
debug("board_mmc_init: init SD slot J5\n");
/* init dev 2, SD slot J5, with 4-bit bus */
- tegra2_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
+ tegra20_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
return 0;
}
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
debug("board_mmc_init: init eMMC\n");
/* init dev 0, eMMC chip, with 4-bit bus */
/* The board has an 8-bit bus, but 8-bit doesn't work yet */
- tegra2_mmc_init(0, 4, -1, -1);
+ tegra20_mmc_init(0, 4, -1, -1);
debug("board_mmc_init: init SD slot\n");
/* init dev 1, SD slot, with 4-bit bus */
- tegra2_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
+ tegra20_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
return 0;
}
#include <common.h>
#include <i2c.h>
#include <asm/io.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
pin_mux_mmc();
/* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */
- tegra2_mmc_init(0, 8, -1, -1);
+ tegra20_mmc_init(0, 8, -1, -1);
/* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */
- tegra2_mmc_init(1, 8, -1, -1);
+ tegra20_mmc_init(1, 8, -1, -1);
return 0;
}
--- /dev/null
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# version 2 as published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = 0x100;
+
+ return 0;
+}
SOBJS := lowlevel_init.o
COBJS := clock_init.o
-COBJS += dmc_init.o
+COBJS += dmc_common.o dmc_init_ddr3.o
COBJS += tzpc_init.o
+COBJS += smdk5250_spl.o
ifndef CONFIG_SPL_BUILD
COBJS += smdk5250.o
* MA 02111-1307 USA
*/
+#include <common.h>
#include <config.h>
-#include <version.h>
#include <asm/io.h>
+#include <asm/arch/clk.h>
#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
+#include <asm/arch/spl.h>
+
+#include "clock_init.h"
#include "setup.h"
-void system_clock_init()
+DECLARE_GLOBAL_DATA_PTR;
+
+struct arm_clk_ratios arm_clk_ratios[] = {
+ {
+ .arm_freq_mhz = 600,
+
+ .apll_mdiv = 0xc8,
+ .apll_pdiv = 0x4,
+ .apll_sdiv = 0x1,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x1,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x2,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x1,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 800,
+
+ .apll_mdiv = 0x64,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x1,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x3,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x2,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1000,
+
+ .apll_mdiv = 0x7d,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x1,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x4,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x2,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1200,
+
+ .apll_mdiv = 0x96,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x5,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x3,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1400,
+
+ .apll_mdiv = 0xaf,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x6,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x3,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1700,
+
+ .apll_mdiv = 0x1a9,
+ .apll_pdiv = 0x6,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x6,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x3,
+ .arm_ratio = 0x0,
+ }
+};
+struct mem_timings mem_timings[] = {
+ {
+ .mem_manuf = MEM_MANUF_ELPIDA,
+ .mem_type = DDR_MODE_DDR3,
+ .frequency_mhz = 800,
+ .mpll_mdiv = 0xc8,
+ .mpll_pdiv = 0x3,
+ .mpll_sdiv = 0x0,
+ .cpll_mdiv = 0xde,
+ .cpll_pdiv = 0x4,
+ .cpll_sdiv = 0x2,
+ .gpll_mdiv = 0x215,
+ .gpll_pdiv = 0xc,
+ .gpll_sdiv = 0x1,
+ .epll_mdiv = 0x60,
+ .epll_pdiv = 0x3,
+ .epll_sdiv = 0x3,
+ .vpll_mdiv = 0x96,
+ .vpll_pdiv = 0x3,
+ .vpll_sdiv = 0x2,
+
+ .bpll_mdiv = 0x64,
+ .bpll_pdiv = 0x3,
+ .bpll_sdiv = 0x0,
+ .pclk_cdrex_ratio = 0x5,
+ .direct_cmd_msr = {
+ 0x00020018, 0x00030000, 0x00010042, 0x00000d70
+ },
+ .timing_ref = 0x000000bb,
+ .timing_row = 0x8c36650e,
+ .timing_data = 0x3630580b,
+ .timing_power = 0x41000a44,
+ .phy0_dqs = 0x08080808,
+ .phy1_dqs = 0x08080808,
+ .phy0_dq = 0x08080808,
+ .phy1_dq = 0x08080808,
+ .phy0_tFS = 0x4,
+ .phy1_tFS = 0x4,
+ .phy0_pulld_dqs = 0xf,
+ .phy1_pulld_dqs = 0xf,
+
+ .lpddr3_ctrl_phy_reset = 0x1,
+ .ctrl_start_point = 0x10,
+ .ctrl_inc = 0x10,
+ .ctrl_start = 0x1,
+ .ctrl_dll_on = 0x1,
+ .ctrl_ref = 0x8,
+
+ .ctrl_force = 0x1a,
+ .ctrl_rdlat = 0x0b,
+ .ctrl_bstlen = 0x08,
+
+ .fp_resync = 0x8,
+ .iv_size = 0x7,
+ .dfi_init_start = 1,
+ .aref_en = 1,
+
+ .rd_fetch = 0x3,
+
+ .zq_mode_dds = 0x7,
+ .zq_mode_term = 0x1,
+ .zq_mode_noterm = 0,
+
+ /*
+ * Dynamic Clock: Always Running
+ * Memory Burst length: 8
+ * Number of chips: 1
+ * Memory Bus width: 32 bit
+ * Memory Type: DDR3
+ * Additional Latancy for PLL: 0 Cycle
+ */
+ .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
+ DMC_MEMCONTROL_DPWRDN_DISABLE |
+ DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
+ DMC_MEMCONTROL_TP_DISABLE |
+ DMC_MEMCONTROL_DSREF_ENABLE |
+ DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
+ DMC_MEMCONTROL_MEM_TYPE_DDR3 |
+ DMC_MEMCONTROL_MEM_WIDTH_32BIT |
+ DMC_MEMCONTROL_NUM_CHIP_1 |
+ DMC_MEMCONTROL_BL_8 |
+ DMC_MEMCONTROL_PZQ_DISABLE |
+ DMC_MEMCONTROL_MRR_BYTE_7_0,
+ .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
+ DMC_MEMCONFIGx_CHIP_COL_10 |
+ DMC_MEMCONFIGx_CHIP_ROW_15 |
+ DMC_MEMCONFIGx_CHIP_BANK_8,
+ .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
+ .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
+ .prechconfig_tp_cnt = 0xff,
+ .dpwrdn_cyc = 0xff,
+ .dsref_cyc = 0xffff,
+ .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
+ DMC_CONCONTROL_TIMEOUT_LEVEL0 |
+ DMC_CONCONTROL_RD_FETCH_DISABLE |
+ DMC_CONCONTROL_EMPTY_DISABLE |
+ DMC_CONCONTROL_AREF_EN_DISABLE |
+ DMC_CONCONTROL_IO_PD_CON_DISABLE,
+ .dmc_channels = 2,
+ .chips_per_channel = 2,
+ .chips_to_configure = 1,
+ .send_zq_init = 1,
+ .impedance = IMP_OUTPUT_DRV_30_OHM,
+ .gate_leveling_enable = 0,
+ }, {
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+ .mem_type = DDR_MODE_DDR3,
+ .frequency_mhz = 800,
+ .mpll_mdiv = 0xc8,
+ .mpll_pdiv = 0x3,
+ .mpll_sdiv = 0x0,
+ .cpll_mdiv = 0xde,
+ .cpll_pdiv = 0x4,
+ .cpll_sdiv = 0x2,
+ .gpll_mdiv = 0x215,
+ .gpll_pdiv = 0xc,
+ .gpll_sdiv = 0x1,
+ .epll_mdiv = 0x60,
+ .epll_pdiv = 0x3,
+ .epll_sdiv = 0x3,
+ .vpll_mdiv = 0x96,
+ .vpll_pdiv = 0x3,
+ .vpll_sdiv = 0x2,
+
+ .bpll_mdiv = 0x64,
+ .bpll_pdiv = 0x3,
+ .bpll_sdiv = 0x0,
+ .pclk_cdrex_ratio = 0x5,
+ .direct_cmd_msr = {
+ 0x00020018, 0x00030000, 0x00010000, 0x00000d70
+ },
+ .timing_ref = 0x000000bb,
+ .timing_row = 0x8c36650e,
+ .timing_data = 0x3630580b,
+ .timing_power = 0x41000a44,
+ .phy0_dqs = 0x08080808,
+ .phy1_dqs = 0x08080808,
+ .phy0_dq = 0x08080808,
+ .phy1_dq = 0x08080808,
+ .phy0_tFS = 0x8,
+ .phy1_tFS = 0x8,
+ .phy0_pulld_dqs = 0xf,
+ .phy1_pulld_dqs = 0xf,
+
+ .lpddr3_ctrl_phy_reset = 0x1,
+ .ctrl_start_point = 0x10,
+ .ctrl_inc = 0x10,
+ .ctrl_start = 0x1,
+ .ctrl_dll_on = 0x1,
+ .ctrl_ref = 0x8,
+
+ .ctrl_force = 0x1a,
+ .ctrl_rdlat = 0x0b,
+ .ctrl_bstlen = 0x08,
+
+ .fp_resync = 0x8,
+ .iv_size = 0x7,
+ .dfi_init_start = 1,
+ .aref_en = 1,
+
+ .rd_fetch = 0x3,
+
+ .zq_mode_dds = 0x5,
+ .zq_mode_term = 0x1,
+ .zq_mode_noterm = 1,
+
+ /*
+ * Dynamic Clock: Always Running
+ * Memory Burst length: 8
+ * Number of chips: 1
+ * Memory Bus width: 32 bit
+ * Memory Type: DDR3
+ * Additional Latancy for PLL: 0 Cycle
+ */
+ .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
+ DMC_MEMCONTROL_DPWRDN_DISABLE |
+ DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
+ DMC_MEMCONTROL_TP_DISABLE |
+ DMC_MEMCONTROL_DSREF_ENABLE |
+ DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
+ DMC_MEMCONTROL_MEM_TYPE_DDR3 |
+ DMC_MEMCONTROL_MEM_WIDTH_32BIT |
+ DMC_MEMCONTROL_NUM_CHIP_1 |
+ DMC_MEMCONTROL_BL_8 |
+ DMC_MEMCONTROL_PZQ_DISABLE |
+ DMC_MEMCONTROL_MRR_BYTE_7_0,
+ .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED |
+ DMC_MEMCONFIGx_CHIP_COL_10 |
+ DMC_MEMCONFIGx_CHIP_ROW_15 |
+ DMC_MEMCONFIGx_CHIP_BANK_8,
+ .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
+ .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
+ .prechconfig_tp_cnt = 0xff,
+ .dpwrdn_cyc = 0xff,
+ .dsref_cyc = 0xffff,
+ .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
+ DMC_CONCONTROL_TIMEOUT_LEVEL0 |
+ DMC_CONCONTROL_RD_FETCH_DISABLE |
+ DMC_CONCONTROL_EMPTY_DISABLE |
+ DMC_CONCONTROL_AREF_EN_DISABLE |
+ DMC_CONCONTROL_IO_PD_CON_DISABLE,
+ .dmc_channels = 2,
+ .chips_per_channel = 2,
+ .chips_to_configure = 1,
+ .send_zq_init = 1,
+ .impedance = IMP_OUTPUT_DRV_40_OHM,
+ .gate_leveling_enable = 1,
+ }
+};
+
+/**
+ * Get the required memory type and speed (SPL version).
+ *
+ * In SPL we have no device tree, so we use the machine parameters
+ *
+ * @param mem_type Returns memory type
+ * @param frequency_mhz Returns memory speed in MHz
+ * @param arm_freq Returns ARM clock speed in MHz
+ * @param mem_manuf Return Memory Manufacturer name
+ * @return 0 if all ok
+ */
+static int clock_get_mem_selection(enum ddr_mode *mem_type,
+ unsigned *frequency_mhz, unsigned *arm_freq,
+ enum mem_manuf *mem_manuf)
{
- struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+ struct spl_machine_param *params;
- /*
- * MUX_APLL_SEL[0]: FINPLL = 0
- * MUX_CPU_SEL[6]: MOUTAPLL = 0
- * MUX_HPM_SEL[20]: MOUTAPLL = 0
- */
- writel(0x0, &clk->src_cpu);
+ params = spl_get_machine_params();
+ *mem_type = params->mem_type;
+ *frequency_mhz = params->frequency_mhz;
+ *arm_freq = params->arm_freq_mhz;
+ *mem_manuf = params->mem_manuf;
- /* MUX_MPLL_SEL[8]: FINPLL = 0 */
- writel(0x0, &clk->src_core1);
+ return 0;
+}
- /*
- * VPLLSRC_SEL[0]: FINPLL = 0
- * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: FINPLL = 0
- */
- writel(0x0, &clk->src_top2);
+/* Get the ratios for setting ARM clock */
+struct arm_clk_ratios *get_arm_ratios(void)
+{
+ struct arm_clk_ratios *arm_ratio;
+ enum ddr_mode mem_type;
+ enum mem_manuf mem_manuf;
+ unsigned frequency_mhz, arm_freq;
+ int i;
+
+ if (clock_get_mem_selection(&mem_type, &frequency_mhz,
+ &arm_freq, &mem_manuf))
+ ;
+ for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
+ i++, arm_ratio++) {
+ if (arm_ratio->arm_freq_mhz == arm_freq)
+ return arm_ratio;
+ }
+
+ /* will hang if failed to find clock ratio */
+ while (1)
+ ;
+
+ return NULL;
+}
- /* MUX_BPLL_SEL[0]: FINPLL = 0 */
- writel(0x0, &clk->src_cdrex);
+struct mem_timings *clock_get_mem_timings(void)
+{
+ struct mem_timings *mem;
+ enum ddr_mode mem_type;
+ enum mem_manuf mem_manuf;
+ unsigned frequency_mhz, arm_freq;
+ int i;
+
+ if (!clock_get_mem_selection(&mem_type, &frequency_mhz,
+ &arm_freq, &mem_manuf)) {
+ for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
+ i++, mem++) {
+ if (mem->mem_type == mem_type &&
+ mem->frequency_mhz == frequency_mhz &&
+ mem->mem_manuf == mem_manuf)
+ return mem;
+ }
+ }
+
+ /* will hang if failed to find memory timings */
+ while (1)
+ ;
+
+ return NULL;
+}
- /* MUX_ACLK_* Clock Selection */
- writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+void system_clock_init()
+{
+ struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+ struct mem_timings *mem;
+ struct arm_clk_ratios *arm_clk_ratio;
+ u32 val, tmp;
+
+ mem = clock_get_mem_timings();
+ arm_clk_ratio = get_arm_ratios();
+
+ clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
+ do {
+ val = readl(&clk->mux_stat_cpu);
+ } while ((val | MUX_APLL_SEL_MASK) != val);
+
+ clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
+ do {
+ val = readl(&clk->mux_stat_core1);
+ } while ((val | MUX_MPLL_SEL_MASK) != val);
+
+ clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK);
+ clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK);
+ clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK);
+ clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK);
+ tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
+ | MUX_GPLL_SEL_MASK;
+ do {
+ val = readl(&clk->mux_stat_top2);
+ } while ((val | tmp) != val);
+
+ clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
+ do {
+ val = readl(&clk->mux_stat_cdrex);
+ } while ((val | MUX_BPLL_SEL_MASK) != val);
- /* MUX_ACLK_* Clock Selection */
- writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+ /* PLL locktime */
+ writel(APLL_LOCK_VAL, &clk->apll_lock);
- /* MUX_ACLK_* Clock Selection */
- writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
+ writel(MPLL_LOCK_VAL, &clk->mpll_lock);
- /* MUX_PWI_SEL[19:16]: SCLKMPLL = 6 */
- writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
+ writel(BPLL_LOCK_VAL, &clk->bpll_lock);
- /* MUX_ATCLK_LEX[0]: ACLK_200 = 0 */
- writel(CLK_SRC_LEX_VAL, &clk->src_lex);
+ writel(CPLL_LOCK_VAL, &clk->cpll_lock);
- /* UART [0-5]: SCLKMPLL = 6 */
- writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
+ writel(GPLL_LOCK_VAL, &clk->gpll_lock);
- /* Set Clock Ratios */
- writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
+ writel(EPLL_LOCK_VAL, &clk->epll_lock);
+
+ writel(VPLL_LOCK_VAL, &clk->vpll_lock);
+
+ writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
+
+ writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
+ do {
+ val = readl(&clk->mux_stat_cpu);
+ } while ((val | HPM_SEL_SCLK_MPLL) != val);
+
+ val = arm_clk_ratio->arm2_ratio << 28
+ | arm_clk_ratio->apll_ratio << 24
+ | arm_clk_ratio->pclk_dbg_ratio << 20
+ | arm_clk_ratio->atb_ratio << 16
+ | arm_clk_ratio->periph_ratio << 12
+ | arm_clk_ratio->acp_ratio << 8
+ | arm_clk_ratio->cpud_ratio << 4
+ | arm_clk_ratio->arm_ratio;
+ writel(val, &clk->div_cpu0);
+ do {
+ val = readl(&clk->div_stat_cpu0);
+ } while (0 != val);
- /* Set COPY and HPM Ratio */
writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+ do {
+ val = readl(&clk->div_stat_cpu1);
+ } while (0 != val);
- /* CORED_RATIO, COREP_RATIO */
- writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
+ /* Set APLL */
+ writel(APLL_CON1_VAL, &clk->apll_con1);
+ val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
+ arm_clk_ratio->apll_sdiv);
+ writel(val, &clk->apll_con0);
+ while (readl(&clk->apll_con0) & APLL_CON0_LOCKED)
+ ;
- /* PWI_RATIO[11:8], DVSEM_RATIO[22:16], DPM_RATIO[24:20] */
- writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
+ /* Set MPLL */
+ writel(MPLL_CON1_VAL, &clk->mpll_con1);
+ val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
+ writel(val, &clk->mpll_con0);
+ while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED)
+ ;
- /* ACLK_*_RATIO */
- writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
+ /* Set BPLL */
+ writel(BPLL_CON1_VAL, &clk->bpll_con1);
+ val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
+ writel(val, &clk->bpll_con0);
+ while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED)
+ ;
- /* ACLK_*_RATIO */
- writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
+ /* Set CPLL */
+ writel(CPLL_CON1_VAL, &clk->cpll_con1);
+ val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
+ writel(val, &clk->cpll_con0);
+ while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED)
+ ;
+
+ /* Set GPLL */
+ writel(GPLL_CON1_VAL, &clk->gpll_con1);
+ val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
+ writel(val, &clk->gpll_con0);
+ while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED)
+ ;
- /* CDREX Ratio */
- writel(CLK_DIV_CDREX_INIT_VAL, &clk->div_cdrex);
+ /* Set EPLL */
+ writel(EPLL_CON2_VAL, &clk->epll_con2);
+ writel(EPLL_CON1_VAL, &clk->epll_con1);
+ val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
+ writel(val, &clk->epll_con0);
+ while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED)
+ ;
- /* MCLK_EFPHY_RATIO[3:0] */
- writel(CLK_DIV_CDREX2_VAL, &clk->div_cdrex2);
+ /* Set VPLL */
+ writel(VPLL_CON2_VAL, &clk->vpll_con2);
+ writel(VPLL_CON1_VAL, &clk->vpll_con1);
+ val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
+ writel(val, &clk->vpll_con0);
+ while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED)
+ ;
- /* {PCLK[4:6]|ATCLK[10:8]}_RATIO */
- writel(CLK_DIV_LEX_VAL, &clk->div_lex);
+ writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
+ writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
+ while (readl(&clk->div_stat_core0) != 0)
+ ;
- /* PCLK_R0X_RATIO[3:0] */
- writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
+ writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
+ while (readl(&clk->div_stat_core1) != 0)
+ ;
- /* PCLK_R1X_RATIO[3:0] */
- writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
+ writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
+ while (readl(&clk->div_stat_sysrgt) != 0)
+ ;
- /* SATA[24]: SCLKMPLL=0, MMC[0-4]: SCLKMPLL = 6 */
- writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
+ writel(CLK_DIV_ACP_VAL, &clk->div_acp);
+ while (readl(&clk->div_stat_acp) != 0)
+ ;
- /* UART[0-4] */
- writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
+ writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
+ while (readl(&clk->div_stat_syslft) != 0)
+ ;
- /* PWM_RATIO[3:0] */
- writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
+ writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+ writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+ writel(TOP2_VAL, &clk->src_top2);
+ writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
- /* SATA_RATIO, USB_DRD_RATIO */
- writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
+ writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
+ while (readl(&clk->div_stat_top0))
+ ;
- /* MMC[0-1] */
- writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+ writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
+ while (readl(&clk->div_stat_top1))
+ ;
- /* MMC[2-3] */
- writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+ writel(CLK_SRC_LEX_VAL, &clk->src_lex);
+ while (1) {
+ val = readl(&clk->mux_stat_lex);
+ if (val == (val | 1))
+ break;
+ }
- /* MMC[4] */
- writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
+ writel(CLK_DIV_LEX_VAL, &clk->div_lex);
+ while (readl(&clk->div_stat_lex))
+ ;
- /* ACLK|PLCK_ACP_RATIO */
- writel(CLK_DIV_ACP_VAL, &clk->div_acp);
+ writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
+ while (readl(&clk->div_stat_r0x))
+ ;
- /* ISPDIV0_RATIO, ISPDIV1_RATIO */
- writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
+ writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
+ while (readl(&clk->div_stat_r0x))
+ ;
- /* MCUISPDIV0_RATIO, MCUISPDIV1_RATIO */
- writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
+ writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
+ while (readl(&clk->div_stat_r1x))
+ ;
- /* MPWMDIV_RATIO */
- writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
+ writel(CLK_REG_DISABLE, &clk->src_cdrex);
- /* PLL locktime */
- writel(APLL_LOCK_VAL, &clk->apll_lock);
+ writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
+ while (readl(&clk->div_stat_cdrex))
+ ;
- writel(MPLL_LOCK_VAL, &clk->mpll_lock);
+ val = readl(&clk->src_cpu);
+ val |= CLK_SRC_CPU_VAL;
+ writel(val, &clk->src_cpu);
- writel(BPLL_LOCK_VAL, &clk->bpll_lock);
+ val = readl(&clk->src_top2);
+ val |= CLK_SRC_TOP2_VAL;
+ writel(val, &clk->src_top2);
- writel(CPLL_LOCK_VAL, &clk->cpll_lock);
+ val = readl(&clk->src_core1);
+ val |= CLK_SRC_CORE1_VAL;
+ writel(val, &clk->src_core1);
- writel(EPLL_LOCK_VAL, &clk->epll_lock);
+ writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
+ writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
+ while (readl(&clk->div_stat_fsys0))
+ ;
+
+ writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
+ writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
+ writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
+ writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
+ writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
+ writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
+ writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
+ writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
- writel(VPLL_LOCK_VAL, &clk->vpll_lock);
+ writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
+ writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
- sdelay(0x10000);
+ writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
+ writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
+ writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
+ writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
- /* Set APLL */
- writel(APLL_CON1_VAL, &clk->apll_con1);
- writel(APLL_CON0_VAL, &clk->apll_con0);
- sdelay(0x30000);
+ writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
+ writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
+ writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
+ writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
+ writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
- /* Set MPLL */
- writel(MPLL_CON1_VAL, &clk->mpll_con1);
- writel(MPLL_CON0_VAL, &clk->mpll_con0);
- sdelay(0x30000);
- writel(BPLL_CON1_VAL, &clk->bpll_con1);
- writel(BPLL_CON0_VAL, &clk->bpll_con0);
- sdelay(0x30000);
+ /* FIMD1 SRC CLK SELECTION */
+ writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
- /* Set CPLL */
- writel(CPLL_CON1_VAL, &clk->cpll_con1);
- writel(CPLL_CON0_VAL, &clk->cpll_con0);
- sdelay(0x30000);
+ val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
+ | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
+ | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
+ | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
+ writel(val, &clk->div_fsys2);
+}
- /* Set EPLL */
- writel(EPLL_CON2_VAL, &clk->epll_con2);
- writel(EPLL_CON1_VAL, &clk->epll_con1);
- writel(EPLL_CON0_VAL, &clk->epll_con0);
- sdelay(0x30000);
+void clock_init_dp_clock(void)
+{
+ struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
- /* Set VPLL */
- writel(VPLL_CON2_VAL, &clk->vpll_con2);
- writel(VPLL_CON1_VAL, &clk->vpll_con1);
- writel(VPLL_CON0_VAL, &clk->vpll_con0);
- sdelay(0x30000);
+ /* DP clock enable */
+ setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
- /* Set MPLL */
- /* After Initiallising th PLL select the sources accordingly */
- /* MUX_APLL_SEL[0]: MOUTAPLLFOUT = 1 */
- writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
-
- /* MUX_MPLL_SEL[8]: MOUTMPLLFOUT = 1 */
- writel(CLK_SRC_CORE1_VAL, &clk->src_core1);
-
- /* MUX_BPLL_SEL[0]: FOUTBPLL = 1*/
- writel(CLK_SRC_CDREX_INIT_VAL, &clk->src_cdrex);
-
- /*
- * VPLLSRC_SEL[0]: FINPLL = 0
- * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: MOUT{CPLL|EPLL|VPLL} = 1
- * MUX_{MPLL[20]}|{BPLL[24]}_USER_SEL: FOUT{MPLL|BPLL} = 1
- */
- writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
+ /* We run DP at 267 Mhz */
+ setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
}
--- /dev/null
+/*
+ * Clock initialization routines
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EXYNOS_CLOCK_INIT_H
+#define __EXYNOS_CLOCK_INIT_H
+
+enum {
+ MEM_TIMINGS_MSR_COUNT = 4,
+};
+
+/* These are the ratio's for configuring ARM clock */
+struct arm_clk_ratios {
+ unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */
+
+ unsigned apll_mdiv;
+ unsigned apll_pdiv;
+ unsigned apll_sdiv;
+
+ unsigned arm2_ratio;
+ unsigned apll_ratio;
+ unsigned pclk_dbg_ratio;
+ unsigned atb_ratio;
+ unsigned periph_ratio;
+ unsigned acp_ratio;
+ unsigned cpud_ratio;
+ unsigned arm_ratio;
+};
+
+/* These are the memory timings for a particular memory type and speed */
+struct mem_timings {
+ enum mem_manuf mem_manuf; /* Memory manufacturer */
+ enum ddr_mode mem_type; /* Memory type */
+ unsigned frequency_mhz; /* Frequency of memory in MHz */
+
+ /* Here follow the timing parameters for the selected memory */
+ unsigned apll_mdiv;
+ unsigned apll_pdiv;
+ unsigned apll_sdiv;
+ unsigned mpll_mdiv;
+ unsigned mpll_pdiv;
+ unsigned mpll_sdiv;
+ unsigned cpll_mdiv;
+ unsigned cpll_pdiv;
+ unsigned cpll_sdiv;
+ unsigned gpll_mdiv;
+ unsigned gpll_pdiv;
+ unsigned gpll_sdiv;
+ unsigned epll_mdiv;
+ unsigned epll_pdiv;
+ unsigned epll_sdiv;
+ unsigned vpll_mdiv;
+ unsigned vpll_pdiv;
+ unsigned vpll_sdiv;
+ unsigned bpll_mdiv;
+ unsigned bpll_pdiv;
+ unsigned bpll_sdiv;
+ unsigned pclk_cdrex_ratio;
+ unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
+
+ unsigned timing_ref;
+ unsigned timing_row;
+ unsigned timing_data;
+ unsigned timing_power;
+
+ /* DQS, DQ, DEBUG offsets */
+ unsigned phy0_dqs;
+ unsigned phy1_dqs;
+ unsigned phy0_dq;
+ unsigned phy1_dq;
+ unsigned phy0_tFS;
+ unsigned phy1_tFS;
+ unsigned phy0_pulld_dqs;
+ unsigned phy1_pulld_dqs;
+
+ unsigned lpddr3_ctrl_phy_reset;
+ unsigned ctrl_start_point;
+ unsigned ctrl_inc;
+ unsigned ctrl_start;
+ unsigned ctrl_dll_on;
+ unsigned ctrl_ref;
+
+ unsigned ctrl_force;
+ unsigned ctrl_rdlat;
+ unsigned ctrl_bstlen;
+
+ unsigned fp_resync;
+ unsigned iv_size;
+ unsigned dfi_init_start;
+ unsigned aref_en;
+
+ unsigned rd_fetch;
+
+ unsigned zq_mode_dds;
+ unsigned zq_mode_term;
+ unsigned zq_mode_noterm; /* 1 to allow termination disable */
+
+ unsigned memcontrol;
+ unsigned memconfig;
+
+ unsigned membaseconfig0;
+ unsigned membaseconfig1;
+ unsigned prechconfig_tp_cnt;
+ unsigned dpwrdn_cyc;
+ unsigned dsref_cyc;
+ unsigned concontrol;
+ /* Channel and Chip Selection */
+ uint8_t dmc_channels; /* number of memory channels */
+ uint8_t chips_per_channel; /* number of chips per channel */
+ uint8_t chips_to_configure; /* number of chips to configure */
+ uint8_t send_zq_init; /* 1 to send this command */
+ unsigned impedance; /* drive strength impedeance */
+ uint8_t gate_leveling_enable; /* check gate leveling is enabled */
+};
+
+/**
+ * Get the correct memory timings for our selected memory type and speed.
+ *
+ * This function can be called from SPL or the main U-Boot.
+ *
+ * @return pointer to the memory timings that we should use
+ */
+struct mem_timings *clock_get_mem_timings(void);
+
+/*
+ * Initialize clock for the device
+ */
+void system_clock_init(void);
+#endif
--- /dev/null
+/*
+ * Mem setup common file for different types of DDR present on SMDK5250 boards.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/spl.h>
+
+#include "clock_init.h"
+#include "setup.h"
+
+#define ZQ_INIT_TIMEOUT 10000
+
+int dmc_config_zq(struct mem_timings *mem,
+ struct exynos5_phy_control *phy0_ctrl,
+ struct exynos5_phy_control *phy1_ctrl)
+{
+ unsigned long val = 0;
+ int i;
+
+ /*
+ * ZQ Calibration:
+ * Select Driver Strength,
+ * long calibration for manual calibration
+ */
+ val = PHY_CON16_RESET_VAL;
+ val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT;
+ val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT;
+ val |= ZQ_CLK_DIV_EN;
+ writel(val, &phy0_ctrl->phy_con16);
+ writel(val, &phy1_ctrl->phy_con16);
+
+ /* Disable termination */
+ if (mem->zq_mode_noterm)
+ val |= PHY_CON16_ZQ_MODE_NOTERM_MASK;
+ writel(val, &phy0_ctrl->phy_con16);
+ writel(val, &phy1_ctrl->phy_con16);
+
+ /* ZQ_MANUAL_START: Enable */
+ val |= ZQ_MANUAL_STR;
+ writel(val, &phy0_ctrl->phy_con16);
+ writel(val, &phy1_ctrl->phy_con16);
+
+ /* ZQ_MANUAL_START: Disable */
+ val &= ~ZQ_MANUAL_STR;
+
+ /*
+ * Since we are manaully calibrating the ZQ values,
+ * we are looping for the ZQ_init to complete.
+ */
+ i = ZQ_INIT_TIMEOUT;
+ while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
+ sdelay(100);
+ i--;
+ }
+ if (!i)
+ return -1;
+ writel(val, &phy0_ctrl->phy_con16);
+
+ i = ZQ_INIT_TIMEOUT;
+ while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
+ sdelay(100);
+ i--;
+ }
+ if (!i)
+ return -1;
+ writel(val, &phy1_ctrl->phy_con16);
+
+ return 0;
+}
+
+void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode)
+{
+ unsigned long val;
+
+ if (mode == DDR_MODE_DDR3) {
+ val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE;
+ writel(val, &dmc->phycontrol0);
+ }
+
+ /* Update DLL Information: Force DLL Resyncronization */
+ val = readl(&dmc->phycontrol0);
+ val |= FP_RSYNC;
+ writel(val, &dmc->phycontrol0);
+
+ /* Reset Force DLL Resyncronization */
+ val = readl(&dmc->phycontrol0);
+ val &= ~FP_RSYNC;
+ writel(val, &dmc->phycontrol0);
+}
+
+void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
+{
+ int channel, chip;
+
+ for (channel = 0; channel < mem->dmc_channels; channel++) {
+ unsigned long mask;
+
+ mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
+ for (chip = 0; chip < mem->chips_to_configure; chip++) {
+ int i;
+
+ mask |= chip << DIRECT_CMD_CHIP_SHIFT;
+
+ /* Sending NOP command */
+ writel(DIRECT_CMD_NOP | mask, &dmc->directcmd);
+
+ /*
+ * TODO(alim.akhtar@samsung.com): Do we need these
+ * delays? This one and the next were not there for
+ * DDR3.
+ */
+ sdelay(0x10000);
+
+ /* Sending EMRS/MRS commands */
+ for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
+ writel(mem->direct_cmd_msr[i] | mask,
+ &dmc->directcmd);
+ sdelay(0x10000);
+ }
+
+ if (mem->send_zq_init) {
+ /* Sending ZQINIT command */
+ writel(DIRECT_CMD_ZQINIT | mask,
+ &dmc->directcmd);
+
+ sdelay(10000);
+ }
+ }
+ }
+}
+
+void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
+{
+ int channel, chip;
+
+ for (channel = 0; channel < mem->dmc_channels; channel++) {
+ unsigned long mask;
+
+ mask = channel << DIRECT_CMD_CHANNEL_SHIFT;
+ for (chip = 0; chip < mem->chips_per_channel; chip++) {
+ mask |= chip << DIRECT_CMD_CHIP_SHIFT;
+
+ /* PALL (all banks precharge) CMD */
+ writel(DIRECT_CMD_PALL | mask, &dmc->directcmd);
+ sdelay(0x10000);
+ }
+ }
+}
+
+void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
+{
+ writel(mem->memconfig, &dmc->memconfig0);
+ writel(mem->memconfig, &dmc->memconfig1);
+ writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
+ writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
+}
+
+void mem_ctrl_init()
+{
+ struct spl_machine_param *param = spl_get_machine_params();
+ struct mem_timings *mem;
+ int ret;
+
+ mem = clock_get_mem_timings();
+
+ /* If there are any other memory variant, add their init call below */
+ if (param->mem_type == DDR_MODE_DDR3) {
+ ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size);
+ if (ret) {
+ /* will hang if failed to init memory control */
+ while (1)
+ ;
+ }
+ } else {
+ /* will hang if unknow memory type */
+ while (1)
+ ;
+ }
+}
+++ /dev/null
-/*
- * Memory setup for SMDK5250 board based on EXYNOS5
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/io.h>
-#include <asm/arch/dmc.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include "setup.h"
-
-/* APLL : 1GHz */
-/* MCLK_CDREX: MCLK_CDREX_533*/
-/* LPDDR support: LPDDR2 */
-static void reset_phy_ctrl(void);
-static void config_zq(struct exynos5_phy_control *,
- struct exynos5_phy_control *);
-static void update_reset_dll(struct exynos5_dmc *);
-static void config_cdrex(void);
-static void config_mrs(struct exynos5_dmc *);
-static void sec_sdram_phy_init(struct exynos5_dmc *);
-static void config_prech(struct exynos5_dmc *);
-static void config_rdlvl(struct exynos5_dmc *,
- struct exynos5_phy_control *,
- struct exynos5_phy_control *);
-static void config_memory(struct exynos5_dmc *);
-
-static void config_offsets(unsigned int,
- struct exynos5_phy_control *,
- struct exynos5_phy_control *);
-
-static void reset_phy_ctrl(void)
-{
- struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
-
- writel(PHY_RESET_VAL, &clk->lpddr3phy_ctrl);
- sdelay(0x10000);
-}
-
-static void config_zq(struct exynos5_phy_control *phy0_ctrl,
- struct exynos5_phy_control *phy1_ctrl)
-{
- unsigned long val = 0;
- /*
- * ZQ Calibration:
- * Select Driver Strength,
- * long calibration for manual calibration
- */
- val = PHY_CON16_RESET_VAL;
- SET_ZQ_MODE_DDS_VAL(val);
- SET_ZQ_MODE_TERM_VAL(val);
- val |= ZQ_CLK_DIV_EN;
- writel(val, &phy0_ctrl->phy_con16);
- writel(val, &phy1_ctrl->phy_con16);
-
- /* Disable termination */
- val |= ZQ_MODE_NOTERM;
- writel(val, &phy0_ctrl->phy_con16);
- writel(val, &phy1_ctrl->phy_con16);
-
- /* ZQ_MANUAL_START: Enable */
- val |= ZQ_MANUAL_STR;
- writel(val, &phy0_ctrl->phy_con16);
- writel(val, &phy1_ctrl->phy_con16);
- sdelay(0x10000);
-
- /* ZQ_MANUAL_START: Disable */
- val &= ~ZQ_MANUAL_STR;
- writel(val, &phy0_ctrl->phy_con16);
- writel(val, &phy1_ctrl->phy_con16);
-}
-
-static void update_reset_dll(struct exynos5_dmc *dmc)
-{
- unsigned long val;
- /*
- * Update DLL Information:
- * Force DLL Resyncronization
- */
- val = readl(&dmc->phycontrol0);
- val |= FP_RSYNC;
- writel(val, &dmc->phycontrol0);
-
- /* Reset Force DLL Resyncronization */
- val = readl(&dmc->phycontrol0);
- val &= ~FP_RSYNC;
- writel(val, &dmc->phycontrol0);
-}
-
-static void config_mrs(struct exynos5_dmc *dmc)
-{
- unsigned long channel, chip, mask = 0, val;
-
- for (channel = 0; channel < CONFIG_DMC_CHANNELS; channel++) {
- SET_CMD_CHANNEL(mask, channel);
- for (chip = 0; chip < CONFIG_CHIPS_PER_CHANNEL; chip++) {
- /*
- * NOP CMD:
- * Assert and hold CKE to logic high level
- */
- SET_CMD_CHIP(mask, chip);
- val = DIRECT_CMD_NOP | mask;
- writel(val, &dmc->directcmd);
- sdelay(0x10000);
-
- /* EMRS, MRS Cmds(Mode Reg Settings) Using Direct Cmd */
- val = DIRECT_CMD_MRS1 | mask;
- writel(val, &dmc->directcmd);
- sdelay(0x10000);
-
- val = DIRECT_CMD_MRS2 | mask;
- writel(val, &dmc->directcmd);
- sdelay(0x10000);
-
- /* MCLK_CDREX_533 */
- val = DIRECT_CMD_MRS3 | mask;
- writel(val, &dmc->directcmd);
- sdelay(0x10000);
-
- val = DIRECT_CMD_MRS4 | mask;
- writel(val, &dmc->directcmd);
- sdelay(0x10000);
- }
- }
-}
-
-static void config_prech(struct exynos5_dmc *dmc)
-{
- unsigned long channel, chip, mask = 0, val;
-
- for (channel = 0; channel < CONFIG_DMC_CHANNELS; channel++) {
- SET_CMD_CHANNEL(mask, channel);
- for (chip = 0; chip < CONFIG_CHIPS_PER_CHANNEL; chip++) {
- SET_CMD_CHIP(mask, chip);
- /* PALL (all banks precharge) CMD */
- val = DIRECT_CMD_PALL | mask;
- writel(val, &dmc->directcmd);
- sdelay(0x10000);
- }
- }
-}
-
-static void sec_sdram_phy_init(struct exynos5_dmc *dmc)
-{
- unsigned long val;
- val = readl(&dmc->concontrol);
- val |= DFI_INIT_START;
- writel(val, &dmc->concontrol);
- sdelay(0x10000);
-
- val = readl(&dmc->concontrol);
- val &= ~DFI_INIT_START;
- writel(val, &dmc->concontrol);
-}
-
-static void config_offsets(unsigned int state,
- struct exynos5_phy_control *phy0_ctrl,
- struct exynos5_phy_control *phy1_ctrl)
-{
- unsigned long val;
- /* Set Offsets to read DQS */
- val = (state == SET) ? SET_DQS_OFFSET_VAL : RESET_DQS_OFFSET_VAL;
- writel(val, &phy0_ctrl->phy_con4);
- writel(val, &phy1_ctrl->phy_con4);
-
- /* Set Offsets to read DQ */
- val = (state == SET) ? SET_DQ_OFFSET_VAL : RESET_DQ_OFFSET_VAL;
- writel(val, &phy0_ctrl->phy_con6);
- writel(val, &phy1_ctrl->phy_con6);
-
- /* Debug Offset */
- val = (state == SET) ? SET_DEBUG_OFFSET_VAL : RESET_DEBUG_OFFSET_VAL;
- writel(val, &phy0_ctrl->phy_con10);
- writel(val, &phy1_ctrl->phy_con10);
-}
-
-static void config_cdrex(void)
-{
- struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
- writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
- writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
- sdelay(0x30000);
-}
-
-static void config_ctrl_dll_on(unsigned int state,
- unsigned int ctrl_force_val,
- struct exynos5_phy_control *phy0_ctrl,
- struct exynos5_phy_control *phy1_ctrl)
-{
- unsigned long val;
- val = readl(&phy0_ctrl->phy_con12);
- CONFIG_CTRL_DLL_ON(val, state);
- SET_CTRL_FORCE_VAL(val, ctrl_force_val);
- writel(val, &phy0_ctrl->phy_con12);
-
- val = readl(&phy1_ctrl->phy_con12);
- CONFIG_CTRL_DLL_ON(val, state);
- SET_CTRL_FORCE_VAL(val, ctrl_force_val);
- writel(val, &phy1_ctrl->phy_con12);
-}
-
-static void config_ctrl_start(unsigned int state,
- struct exynos5_phy_control *phy0_ctrl,
- struct exynos5_phy_control *phy1_ctrl)
-{
- unsigned long val;
- val = readl(&phy0_ctrl->phy_con12);
- CONFIG_CTRL_START(val, state);
- writel(val, &phy0_ctrl->phy_con12);
-
- val = readl(&phy1_ctrl->phy_con12);
- CONFIG_CTRL_START(val, state);
- writel(val, &phy1_ctrl->phy_con12);
-}
-
-#if defined(CONFIG_RD_LVL)
-static void config_rdlvl(struct exynos5_dmc *dmc,
- struct exynos5_phy_control *phy0_ctrl,
- struct exynos5_phy_control *phy1_ctrl)
-{
- unsigned long val;
-
- /* Disable CTRL_DLL_ON and set ctrl_force */
- config_ctrl_dll_on(RESET, 0x2D, phy0_ctrl, phy1_ctrl);
-
- /*
- * Set ctrl_gateadj, ctrl_readadj
- * ctrl_gateduradj, rdlvl_pass_adj
- * rdlvl_rddataPadj
- */
- val = SET_RDLVL_RDDATAPADJ;
- writel(val, &phy0_ctrl->phy_con1);
- writel(val, &phy1_ctrl->phy_con1);
-
- /* LPDDR2 Address */
- writel(LPDDR2_ADDR, &phy0_ctrl->phy_con22);
- writel(LPDDR2_ADDR, &phy1_ctrl->phy_con22);
-
- /* Enable Byte Read Leveling set ctrl_ddr_mode */
- val = readl(&phy0_ctrl->phy_con0);
- val |= BYTE_RDLVL_EN;
- writel(val, &phy0_ctrl->phy_con0);
- val = readl(&phy1_ctrl->phy_con0);
- val |= BYTE_RDLVL_EN;
- writel(val, &phy1_ctrl->phy_con0);
-
- /* rdlvl_en: Use levelling offset instead ctrl_shiftc */
- val = PHY_CON2_RESET_VAL | RDLVL_EN;
- writel(val, &phy0_ctrl->phy_con2);
- writel(val, &phy1_ctrl->phy_con2);
- sdelay(0x10000);
-
- /* Enable Data Eye Training */
- val = readl(&dmc->rdlvl_config);
- val |= CTRL_RDLVL_DATA_EN;
- writel(val, &dmc->rdlvl_config);
- sdelay(0x10000);
-
- /* Disable Data Eye Training */
- val = readl(&dmc->rdlvl_config);
- val &= ~CTRL_RDLVL_DATA_EN;
- writel(val, &dmc->rdlvl_config);
-
- /* RdDeSkew_clear: Clear */
- val = readl(&phy0_ctrl->phy_con2);
- val |= RDDSKEW_CLEAR;
- writel(val, &phy0_ctrl->phy_con2);
- val = readl(&phy1_ctrl->phy_con2);
- val |= RDDSKEW_CLEAR;
- writel(val, &phy1_ctrl->phy_con2);
-
- /* Enable CTRL_DLL_ON */
- config_ctrl_dll_on(SET, 0x0, phy0_ctrl, phy1_ctrl);
-
- update_reset_dll(dmc);
- sdelay(0x10000);
-
- /* ctrl_atgte: ctrl_gate_p*, ctrl_read_p* generated by PHY */
- val = readl(&phy0_ctrl->phy_con0);
- val &= ~CTRL_ATGATE;
- writel(val, &phy0_ctrl->phy_con0);
- val = readl(&phy1_ctrl->phy_con0);
- val &= ~CTRL_ATGATE;
- writel(val, &phy1_ctrl->phy_con0);
-}
-#endif
-
-static void config_memory(struct exynos5_dmc *dmc)
-{
- /*
- * Memory Configuration Chip 0
- * Address Mapping: Interleaved
- * Number of Column address Bits: 10 bits
- * Number of Rows Address Bits: 14
- * Number of Banks: 8
- */
- writel(DMC_MEMCONFIG0_VAL, &dmc->memconfig0);
-
- /*
- * Memory Configuration Chip 1
- * Address Mapping: Interleaved
- * Number of Column address Bits: 10 bits
- * Number of Rows Address Bits: 14
- * Number of Banks: 8
- */
- writel(DMC_MEMCONFIG1_VAL, &dmc->memconfig1);
-
- /*
- * Chip0: AXI
- * AXI Base Address: 0x40000000
- * AXI Base Address Mask: 0x780
- */
- writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
-
- /*
- * Chip1: AXI
- * AXI Base Address: 0x80000000
- * AXI Base Address Mask: 0x780
- */
- writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
-}
-
-void mem_ctrl_init()
-{
- struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
- struct exynos5_dmc *dmc;
- unsigned long val;
-
- phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
- phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
- dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
-
- /* Reset PHY Controllor: PHY_RESET[0] */
- reset_phy_ctrl();
-
- /*set Read Latancy and Burst Length for PHY0 and PHY1 */
- writel(PHY_CON42_VAL, &phy0_ctrl->phy_con42);
- writel(PHY_CON42_VAL, &phy1_ctrl->phy_con42);
-
- /* ZQ Cofiguration */
- config_zq(phy0_ctrl, phy1_ctrl);
-
- /* Operation Mode : LPDDR2 */
- val = PHY_CON0_RESET_VAL;
- SET_CTRL_DDR_MODE(val, DDR_MODE_LPDDR2);
- writel(val, &phy0_ctrl->phy_con0);
- writel(val, &phy1_ctrl->phy_con0);
-
- /* DQS, DQ: Signal, for LPDDR2: Always Set */
- val = CTRL_PULLD_DQ | CTRL_PULLD_DQS;
- writel(val, &phy0_ctrl->phy_con14);
- writel(val, &phy1_ctrl->phy_con14);
-
- /* Init SEC SDRAM PHY */
- sec_sdram_phy_init(dmc);
- sdelay(0x10000);
-
- update_reset_dll(dmc);
-
- /*
- * Dynamic Clock: Always Running
- * Memory Burst length: 4
- * Number of chips: 2
- * Memory Bus width: 32 bit
- * Memory Type: LPDDR2-S4
- * Additional Latancy for PLL: 1 Cycle
- */
- writel(DMC_MEMCONTROL_VAL, &dmc->memcontrol);
-
- config_memory(dmc);
-
- /* Precharge Configuration */
- writel(DMC_PRECHCONFIG_VAL, &dmc->prechconfig);
-
- /* Power Down mode Configuration */
- writel(DMC_PWRDNCONFIG_VAL, &dmc->pwrdnconfig);
-
- /* Periodic Refrese Interval */
- writel(DMC_TIMINGREF_VAL, &dmc->timingref);
-
- /*
- * TimingRow, TimingData, TimingPower Setting:
- * Values as per Memory AC Parameters
- */
- writel(DMC_TIMINGROW_VAL, &dmc->timingrow);
-
- writel(DMC_TIMINGDATA_VAL, &dmc->timingdata);
-
- writel(DMC_TIMINGPOWER_VAL, &dmc->timingpower);
-
- /* Memory Channel Inteleaving Size: 128 Bytes */
- writel(CONFIG_IV_SIZE, &dmc->ivcontrol);
-
- /* Set DQS, DQ and DEBUG offsets */
- config_offsets(SET, phy0_ctrl, phy1_ctrl);
-
- /* Disable CTRL_DLL_ON and set ctrl_force */
- config_ctrl_dll_on(RESET, 0x7F, phy0_ctrl, phy1_ctrl);
- sdelay(0x10000);
-
- update_reset_dll(dmc);
-
- /* Config MRS(Mode Register Settingg) */
- config_mrs(dmc);
-
- config_cdrex();
-
- /* Reset DQS DQ and DEBUG offsets */
- config_offsets(RESET, phy0_ctrl, phy1_ctrl);
-
- /* Enable CTRL_DLL_ON */
- config_ctrl_dll_on(SET, 0x0, phy0_ctrl, phy1_ctrl);
-
- /* Stop DLL Locking */
- config_ctrl_start(RESET, phy0_ctrl, phy1_ctrl);
- sdelay(0x10000);
-
- /* Start DLL Locking */
- config_ctrl_start(SET, phy0_ctrl, phy1_ctrl);
- sdelay(0x10000);
-
- update_reset_dll(dmc);
-
-#if defined(CONFIG_RD_LVL)
- config_rdlvl(dmc, phy0_ctrl, phy1_ctrl);
-#endif
- config_prech(dmc);
-
- /*
- * Dynamic Clock: Stops During Idle Period
- * Dynamic Power Down: Enable
- * Dynamic Self refresh: Enable
- */
- val = readl(&dmc->memcontrol);
- val |= CLK_STOP_EN | DPWRDN_EN | DSREF_EN;
- writel(val, &dmc->memcontrol);
-
- /* Start Auto refresh */
- val = readl(&dmc->concontrol);
- val |= AREF_EN;
- writel(val, &dmc->concontrol);
-}
--- /dev/null
+/*
+ * DDR3 mem setup file for SMDK5250 board based on EXYNOS5
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dmc.h>
+#include "setup.h"
+#include "clock_init.h"
+
+#define RDLVL_COMPLETE_TIMEOUT 10000
+
+static void reset_phy_ctrl(void)
+{
+ struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+
+ writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
+ writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
+}
+
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
+{
+ unsigned int val;
+ struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
+ struct exynos5_dmc *dmc;
+ int i;
+
+ phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
+ phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
+ dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
+
+ reset_phy_ctrl();
+
+ /* Set Impedance Output Driver */
+ val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |
+ (mem->impedance << CA_CKE_DRVR_DS_OFFSET) |
+ (mem->impedance << CA_CS_DRVR_DS_OFFSET) |
+ (mem->impedance << CA_ADR_DRVR_DS_OFFSET);
+ writel(val, &phy0_ctrl->phy_con39);
+ writel(val, &phy1_ctrl->phy_con39);
+
+ /* Set Read Latency and Burst Length for PHY0 and PHY1 */
+ val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
+ (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
+ writel(val, &phy0_ctrl->phy_con42);
+ writel(val, &phy1_ctrl->phy_con42);
+
+ /* ZQ Calibration */
+ if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl))
+ return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
+
+ /* DQ Signal */
+ writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14);
+ writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14);
+
+ writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
+ | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),
+ &dmc->concontrol);
+
+ update_reset_dll(dmc, DDR_MODE_DDR3);
+
+ /* DQS Signal */
+ writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);
+ writel(mem->phy1_dqs, &phy1_ctrl->phy_con4);
+
+ writel(mem->phy0_dq, &phy0_ctrl->phy_con6);
+ writel(mem->phy1_dq, &phy1_ctrl->phy_con6);
+
+ writel(mem->phy0_tFS, &phy0_ctrl->phy_con10);
+ writel(mem->phy1_tFS, &phy1_ctrl->phy_con10);
+
+ val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) |
+ (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
+ (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
+ (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
+ writel(val, &phy0_ctrl->phy_con12);
+ writel(val, &phy1_ctrl->phy_con12);
+
+ /* Start DLL locking */
+ writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
+ &phy0_ctrl->phy_con12);
+ writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
+ &phy1_ctrl->phy_con12);
+
+ update_reset_dll(dmc, DDR_MODE_DDR3);
+
+ writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
+ &dmc->concontrol);
+
+ /* Memory Channel Inteleaving Size */
+ writel(mem->iv_size, &dmc->ivcontrol);
+
+ writel(mem->memconfig, &dmc->memconfig0);
+ writel(mem->memconfig, &dmc->memconfig1);
+ writel(mem->membaseconfig0, &dmc->membaseconfig0);
+ writel(mem->membaseconfig1, &dmc->membaseconfig1);
+
+ /* Precharge Configuration */
+ writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
+ &dmc->prechconfig);
+
+ /* Power Down mode Configuration */
+ writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
+ mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
+ &dmc->pwrdnconfig);
+
+ /* TimingRow, TimingData, TimingPower and Timingaref
+ * values as per Memory AC parameters
+ */
+ writel(mem->timing_ref, &dmc->timingref);
+ writel(mem->timing_row, &dmc->timingrow);
+ writel(mem->timing_data, &dmc->timingdata);
+ writel(mem->timing_power, &dmc->timingpower);
+
+ /* Send PALL command */
+ dmc_config_prech(mem, dmc);
+
+ /* Send NOP, MRS and ZQINIT commands */
+ dmc_config_mrs(mem, dmc);
+
+ if (mem->gate_leveling_enable) {
+ val = PHY_CON0_RESET_VAL;
+ val |= P0_CMD_EN;
+ writel(val, &phy0_ctrl->phy_con0);
+ writel(val, &phy1_ctrl->phy_con0);
+
+ val = PHY_CON2_RESET_VAL;
+ val |= INIT_DESKEW_EN;
+ writel(val, &phy0_ctrl->phy_con2);
+ writel(val, &phy1_ctrl->phy_con2);
+
+ val = PHY_CON0_RESET_VAL;
+ val |= P0_CMD_EN;
+ val |= BYTE_RDLVL_EN;
+ writel(val, &phy0_ctrl->phy_con0);
+ writel(val, &phy1_ctrl->phy_con0);
+
+ val = (mem->ctrl_start_point <<
+ PHY_CON12_CTRL_START_POINT_SHIFT) |
+ (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
+ (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
+ (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
+ (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
+ writel(val, &phy0_ctrl->phy_con12);
+ writel(val, &phy1_ctrl->phy_con12);
+
+ val = PHY_CON2_RESET_VAL;
+ val |= INIT_DESKEW_EN;
+ val |= RDLVL_GATE_EN;
+ writel(val, &phy0_ctrl->phy_con2);
+ writel(val, &phy1_ctrl->phy_con2);
+
+ val = PHY_CON0_RESET_VAL;
+ val |= P0_CMD_EN;
+ val |= BYTE_RDLVL_EN;
+ val |= CTRL_SHGATE;
+ writel(val, &phy0_ctrl->phy_con0);
+ writel(val, &phy1_ctrl->phy_con0);
+
+ val = PHY_CON1_RESET_VAL;
+ val &= ~(CTRL_GATEDURADJ_MASK);
+ writel(val, &phy0_ctrl->phy_con1);
+ writel(val, &phy1_ctrl->phy_con1);
+
+ writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
+ i = RDLVL_COMPLETE_TIMEOUT;
+ while ((readl(&dmc->phystatus) &
+ (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
+ (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
+ /*
+ * TODO(waihong): Comment on how long this take to
+ * timeout
+ */
+ sdelay(100);
+ i--;
+ }
+ if (!i)
+ return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
+ writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config);
+
+ writel(0, &phy0_ctrl->phy_con14);
+ writel(0, &phy1_ctrl->phy_con14);
+
+ val = (mem->ctrl_start_point <<
+ PHY_CON12_CTRL_START_POINT_SHIFT) |
+ (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
+ (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
+ (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
+ (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
+ (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
+ writel(val, &phy0_ctrl->phy_con12);
+ writel(val, &phy1_ctrl->phy_con12);
+
+ update_reset_dll(dmc, DDR_MODE_DDR3);
+ }
+
+ /* Send PALL command */
+ dmc_config_prech(mem, dmc);
+
+ writel(mem->memcontrol, &dmc->memcontrol);
+
+ /* Set DMC Concontrol and enable auto-refresh counter */
+ writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
+ | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
+ return 0;
+}
/*
- * Machine Specific Values for SMDK5250 board based on S5PC520
+ * Machine Specific Values for SMDK5250 board based on EXYNOS5
*
* Copyright (C) 2012 Samsung Electronics
*
#define _SMDK5250_SETUP_H
#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-
-/* GPIO Offsets for UART: GPIO Contol Register */
-#define EXYNOS5_GPIO_A0_CON_OFFSET 0x0
-#define EXYNOS5_GPIO_A1_CON_OFFSET 0x20
+#include <asm/arch/dmc.h>
/* TZPC : Register Offsets */
#define TZPC0_BASE 0x10100000
#define TZPC8_BASE 0x10180000
#define TZPC9_BASE 0x10190000
-/* CLK_SRC_CPU */
-/* 0 = MOUTAPLL, 1 = SCLKMPLL */
-#define MUX_HPM_SEL 0
-#define MUX_CPU_SEL 0
-#define MUX_APLL_SEL 1
-#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
- | (MUX_CPU_SEL << 16) \
- | (MUX_APLL_SEL))
-
-/* CLK_DIV_CPU0 */
-#define ARM2_RATIO 0x0
-#define APLL_RATIO 0x1
-#define PCLK_DBG_RATIO 0x1
-#define ATB_RATIO 0x4
-#define PERIPH_RATIO 0x7
-#define ACP_RATIO 0x7
-#define CPUD_RATIO 0x2
-#define ARM_RATIO 0x0
-#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
- | (APLL_RATIO << 24) \
- | (PCLK_DBG_RATIO << 20) \
- | (ATB_RATIO << 16) \
- | (PERIPH_RATIO << 12) \
- | (ACP_RATIO << 8) \
- | (CPUD_RATIO << 4) \
- | (ARM_RATIO))
-
-/* CLK_DIV_CPU1 */
-#define HPM_RATIO 0x4
-#define COPY_RATIO 0x0
-#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
- | (COPY_RATIO))
-
-#define APLL_MDIV 0x7D
-#define APLL_PDIV 0x3
-#define APLL_SDIV 0x0
-
-#define MPLL_MDIV 0x64
-#define MPLL_PDIV 0x3
-#define MPLL_SDIV 0x0
-
-#define CPLL_MDIV 0x96
-#define CPLL_PDIV 0x4
-#define CPLL_SDIV 0x0
-
-/* APLL_CON1 */
+/* APLL_CON1 */
#define APLL_CON1_VAL (0x00203800)
-/* MPLL_CON1 */
-#define MPLL_CON1_VAL (0x00203800)
+/* MPLL_CON1 */
+#define MPLL_CON1_VAL (0x00203800)
-/* CPLL_CON1 */
+/* CPLL_CON1 */
#define CPLL_CON1_VAL (0x00203800)
-#define EPLL_MDIV 0x60
-#define EPLL_PDIV 0x3
-#define EPLL_SDIV 0x3
+/* GPLL_CON1 */
+#define GPLL_CON1_VAL (0x00203800)
+/* EPLL_CON1, CON2 */
#define EPLL_CON1_VAL 0x00000000
#define EPLL_CON2_VAL 0x00000080
-#define VPLL_MDIV 0x96
-#define VPLL_PDIV 0x3
-#define VPLL_SDIV 0x2
-
+/* VPLL_CON1, CON2 */
#define VPLL_CON1_VAL 0x00000000
#define VPLL_CON2_VAL 0x00000080
-#define BPLL_MDIV 0x215
-#define BPLL_PDIV 0xC
-#define BPLL_SDIV 0x1
-
+/* BPLL_CON1 */
#define BPLL_CON1_VAL 0x00203800
/* Set PLL */
#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
-#define APLL_CON0_VAL set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV)
-#define MPLL_CON0_VAL set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
-#define CPLL_CON0_VAL set_pll(CPLL_MDIV, CPLL_PDIV, CPLL_SDIV)
-#define EPLL_CON0_VAL set_pll(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
-#define VPLL_CON0_VAL set_pll(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
-#define BPLL_CON0_VAL set_pll(BPLL_MDIV, BPLL_PDIV, BPLL_SDIV)
+/* CLK_SRC_CPU */
+/* 0 = MOUTAPLL, 1 = SCLKMPLL */
+#define MUX_HPM_SEL 0
+#define MUX_CPU_SEL 0
+#define MUX_APLL_SEL 1
+
+#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
+ | (MUX_CPU_SEL << 16) \
+ | (MUX_APLL_SEL))
+
+/* MEMCONTROL register bit fields */
+#define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
+#define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
+#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
+#define DMC_MEMCONTROL_TP_DISABLE (0 << 4)
+#define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
+#define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)
+#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
+
+#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)
+#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)
+#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
+
+#define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
+
+#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)
+#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
+
+#define DMC_MEMCONTROL_BL_8 (3 << 20)
+#define DMC_MEMCONTROL_BL_4 (2 << 20)
+
+#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
+
+#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
+
+/* MEMCONFIG0 register bit fields */
+#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12)
+#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8)
+#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4)
+#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4)
+#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0)
+
+#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16)
+#define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0)
+#define DMC_MEMBASECONFIG_VAL(x) ( \
+ DMC_MEMBASECONFIGx_CHIP_BASE(x) | \
+ DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \
+)
+
+#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
+#define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
+
+#define DMC_PRECHCONFIG_VAL 0xFF000000
+#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
+
+#define DMC_CONCONTROL_RESET_VAL 0x0FFF0000
+#define DFI_INIT_START (1 << 28)
+#define EMPTY (1 << 8)
+#define AREF_EN (1 << 5)
+
+#define DFI_INIT_COMPLETE_CHO (1 << 2)
+#define DFI_INIT_COMPLETE_CH1 (1 << 3)
+
+#define RDLVL_COMPLETE_CHO (1 << 14)
+#define RDLVL_COMPLETE_CH1 (1 << 15)
+
+#define CLK_STOP_EN (1 << 0)
+#define DPWRDN_EN (1 << 1)
+#define DSREF_EN (1 << 5)
+
+/* COJCONTROL register bit fields */
+#define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
+#define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
+#define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
+#define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
+#define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
+#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
+#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
+
+/* CLK_DIV_CPU0_VAL */
+#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
+ | (APLL_RATIO << 24) \
+ | (PCLK_DBG_RATIO << 20) \
+ | (ATB_RATIO << 16) \
+ | (PERIPH_RATIO << 12) \
+ | (ACP_RATIO << 8) \
+ | (CPUD_RATIO << 4) \
+ | (ARM_RATIO))
+
+
+/* CLK_FSYS */
+#define CLK_SRC_FSYS0_VAL 0x66666
+#define CLK_DIV_FSYS0_VAL 0x0BB00000
+
+/* CLK_DIV_CPU1 */
+#define HPM_RATIO 0x2
+#define COPY_RATIO 0x0
+
+/* CLK_DIV_CPU1 = 0x00000003 */
+#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
+ | (COPY_RATIO))
/* CLK_SRC_CORE0 */
-#define CLK_SRC_CORE0_VAL 0x00060000
+#define CLK_SRC_CORE0_VAL 0x00000000
/* CLK_SRC_CORE1 */
-#define CLK_SRC_CORE1_VAL 0x100
+#define CLK_SRC_CORE1_VAL 0x100
/* CLK_DIV_CORE0 */
-#define CLK_DIV_CORE0_VAL 0x120000
+#define CLK_DIV_CORE0_VAL 0x00120000
/* CLK_DIV_CORE1 */
-#define CLK_DIV_CORE1_VAL 0x07070700
+#define CLK_DIV_CORE1_VAL 0x07070700
+
+/* CLK_DIV_SYSRGT */
+#define CLK_DIV_SYSRGT_VAL 0x00000111
+
+/* CLK_DIV_ACP */
+#define CLK_DIV_ACP_VAL 0x12
+
+/* CLK_DIV_SYSLFT */
+#define CLK_DIV_SYSLFT_VAL 0x00000311
/* CLK_SRC_CDREX */
-#define CLK_SRC_CDREX_INIT_VAL 0x1
-#define CLK_SRC_CDREX_VAL 0x111
+#define CLK_SRC_CDREX_VAL 0x1
/* CLK_DIV_CDREX */
-#define CLK_DIV_CDREX_INIT_VAL 0x71771111
-
-#define MCLK_CDREX2_RATIO 0x0
-#define ACLK_EFCON_RATIO 0x1
-#define MCLK_DPHY_RATIO 0x0
-#define MCLK_CDREX_RATIO 0x0
+#define MCLK_CDREX2_RATIO 0x0
+#define ACLK_EFCON_RATIO 0x1
+#define MCLK_DPHY_RATIO 0x1
+#define MCLK_CDREX_RATIO 0x1
#define ACLK_C2C_200_RATIO 0x1
#define C2C_CLK_400_RATIO 0x1
-#define PCLK_CDREX_RATIO 0x3
+#define PCLK_CDREX_RATIO 0x1
#define ACLK_CDREX_RATIO 0x1
-#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 20) \
- | (MCLK_CDREX_RATIO << 16) \
- | (ACLK_C2C_200_RATIO << 12) \
- | (C2C_CLK_400_RATIO << 8) \
- | (PCLK_CDREX_RATIO << 4) \
- | (ACLK_CDREX_RATIO))
-#define MCLK_EFPHY_RATIO 0x4
-#define CLK_DIV_CDREX2_VAL MCLK_EFPHY_RATIO
+#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \
+ | (C2C_CLK_400_RATIO << 6) \
+ | (PCLK_CDREX_RATIO << 4) \
+ | (ACLK_CDREX_RATIO))
-/* CLK_DIV_ACP */
-#define CLK_DIV_ACP_VAL 0x12
-
-/* CLK_SRC_TOP0 */
-#define MUX_ACLK_300_GSCL_SEL 0x1
-#define MUX_ACLK_300_GSCL_MID_SEL 0x0
-#define MUX_ACLK_400_SEL 0x0
-#define MUX_ACLK_333_SEL 0x0
-#define MUX_ACLK_300_DISP1_SEL 0x1
-#define MUX_ACLK_300_DISP1_MID_SEL 0x0
-#define MUX_ACLK_200_SEL 0x0
-#define MUX_ACLK_166_SEL 0x0
-#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
- | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
- | (MUX_ACLK_400_SEL << 20) \
- | (MUX_ACLK_333_SEL << 16) \
- | (MUX_ACLK_300_DISP1_SEL << 15) \
+/* CLK_SRC_TOP0 */
+#define MUX_ACLK_300_GSCL_SEL 0x0
+#define MUX_ACLK_300_GSCL_MID_SEL 0x0
+#define MUX_ACLK_400_G3D_MID_SEL 0x0
+#define MUX_ACLK_333_SEL 0x0
+#define MUX_ACLK_300_DISP1_SEL 0x0
+#define MUX_ACLK_300_DISP1_MID_SEL 0x0
+#define MUX_ACLK_200_SEL 0x0
+#define MUX_ACLK_166_SEL 0x0
+#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
+ | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
+ | (MUX_ACLK_400_G3D_MID_SEL << 20) \
+ | (MUX_ACLK_333_SEL << 16) \
+ | (MUX_ACLK_300_DISP1_SEL << 15) \
| (MUX_ACLK_300_DISP1_MID_SEL << 14) \
- | (MUX_ACLK_200_SEL << 12) \
+ | (MUX_ACLK_200_SEL << 12) \
| (MUX_ACLK_166_SEL << 8))
-/* CLK_SRC_TOP1 */
-#define MUX_ACLK_400_ISP_SEL 0x0
-#define MUX_ACLK_400_IOP_SEL 0x0
-#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
-#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_ISP_SEL << 24) \
- |(MUX_ACLK_400_IOP_SEL << 20) \
- |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16))
+/* CLK_SRC_TOP1 */
+#define MUX_ACLK_400_G3D_SEL 0x1
+#define MUX_ACLK_400_ISP_SEL 0x0
+#define MUX_ACLK_400_IOP_SEL 0x0
+#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
+#define MUX_ACLK_300_GSCL_MID1_SEL 0x0
+#define MUX_ACLK_300_DISP1_MID1_SEL 0x0
+#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \
+ |(MUX_ACLK_400_ISP_SEL << 24) \
+ |(MUX_ACLK_400_IOP_SEL << 20) \
+ |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
+ |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
+ |(MUX_ACLK_300_DISP1_MID1_SEL << 8))
/* CLK_SRC_TOP2 */
-#define MUX_BPLL_USER_SEL 0x1
-#define MUX_MPLL_USER_SEL 0x1
-#define MUX_VPLL_SEL 0x0
-#define MUX_EPLL_SEL 0x0
-#define MUX_CPLL_SEL 0x0
-#define VPLLSRC_SEL 0x0
-#define CLK_SRC_TOP2_VAL ((MUX_BPLL_USER_SEL << 24) \
- | (MUX_MPLL_USER_SEL << 20) \
- | (MUX_VPLL_SEL << 16) \
- | (MUX_EPLL_SEL << 12) \
- | (MUX_CPLL_SEL << 8) \
+#define MUX_GPLL_SEL 0x1
+#define MUX_BPLL_USER_SEL 0x0
+#define MUX_MPLL_USER_SEL 0x0
+#define MUX_VPLL_SEL 0x1
+#define MUX_EPLL_SEL 0x1
+#define MUX_CPLL_SEL 0x1
+#define VPLLSRC_SEL 0x0
+#define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
+ | (MUX_BPLL_USER_SEL << 24) \
+ | (MUX_MPLL_USER_SEL << 20) \
+ | (MUX_VPLL_SEL << 16) \
+ | (MUX_EPLL_SEL << 12) \
+ | (MUX_CPLL_SEL << 8) \
| (VPLLSRC_SEL))
/* CLK_SRC_TOP3 */
-#define MUX_ACLK_333_SUB_SEL 0x1
-#define MUX_ACLK_400_SUB_SEL 0x1
-#define MUX_ACLK_266_ISP_SUB_SEL 0x1
-#define MUX_ACLK_266_GPS_SUB_SEL 0x1
-#define MUX_ACLK_300_GSCL_SUB_SEL 0x1
-#define MUX_ACLK_266_GSCL_SUB_SEL 0x1
-#define MUX_ACLK_300_DISP1_SUB_SEL 0x1
-#define MUX_ACLK_200_DISP1_SUB_SEL 0x1
-#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
- | (MUX_ACLK_400_SUB_SEL << 20) \
- | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
- | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
- | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
- | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
- | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
- | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
-
-/* CLK_DIV_TOP0 */
-#define ACLK_300_RATIO 0x0
-#define ACLK_400_RATIO 0x3
-#define ACLK_333_RATIO 0x2
+#define MUX_ACLK_333_SUB_SEL 0x1
+#define MUX_ACLK_400_SUB_SEL 0x1
+#define MUX_ACLK_266_ISP_SUB_SEL 0x1
+#define MUX_ACLK_266_GPS_SUB_SEL 0x0
+#define MUX_ACLK_300_GSCL_SUB_SEL 0x1
+#define MUX_ACLK_266_GSCL_SUB_SEL 0x1
+#define MUX_ACLK_300_DISP1_SUB_SEL 0x1
+#define MUX_ACLK_200_DISP1_SUB_SEL 0x1
+#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
+ | (MUX_ACLK_400_SUB_SEL << 20) \
+ | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
+ | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
+ | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
+ | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
+ | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
+ | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
+
+/* CLK_DIV_TOP0 */
+#define ACLK_300_DISP1_RATIO 0x2
+#define ACLK_400_G3D_RATIO 0x0
+#define ACLK_333_RATIO 0x0
#define ACLK_266_RATIO 0x2
#define ACLK_200_RATIO 0x3
-#define ACLK_166_RATIO 0x5
+#define ACLK_166_RATIO 0x1
#define ACLK_133_RATIO 0x1
#define ACLK_66_RATIO 0x5
-#define CLK_DIV_TOP0_VAL ((ACLK_300_RATIO << 28) \
- | (ACLK_400_RATIO << 24) \
- | (ACLK_333_RATIO << 20) \
- | (ACLK_266_RATIO << 16) \
- | (ACLK_200_RATIO << 12) \
- | (ACLK_166_RATIO << 8) \
- | (ACLK_133_RATIO << 4) \
+
+#define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
+ | (ACLK_400_G3D_RATIO << 24) \
+ | (ACLK_333_RATIO << 20) \
+ | (ACLK_266_RATIO << 16) \
+ | (ACLK_200_RATIO << 12) \
+ | (ACLK_166_RATIO << 8) \
+ | (ACLK_133_RATIO << 4) \
| (ACLK_66_RATIO))
-/* CLK_DIV_TOP1 */
-#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
-#define ACLK_66_PRE_RATIO 0x1
-#define ACLK_400_ISP_RATIO 0x1
-#define ACLK_400_IOP_RATIO 0x1
-#define ACLK_300_GSCL_RATIO 0x0
-#define ACLK_266_GPS_RATIO 0x7
-
-#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
- | (ACLK_66_PRE_RATIO << 24) \
- | (ACLK_400_ISP_RATIO << 20) \
- | (ACLK_400_IOP_RATIO << 16) \
- | (ACLK_300_GSCL_RATIO << 12) \
- | (ACLK_266_GPS_RATIO << 8))
-
-/* APLL_LOCK */
-#define APLL_LOCK_VAL (0x3E8)
-/* MPLL_LOCK */
-#define MPLL_LOCK_VAL (0x2F1)
-/* CPLL_LOCK */
-#define CPLL_LOCK_VAL (0x3E8)
-/* EPLL_LOCK */
-#define EPLL_LOCK_VAL (0x2321)
-/* VPLL_LOCK */
-#define VPLL_LOCK_VAL (0x2321)
-/* BPLL_LOCK */
-#define BPLL_LOCK_VAL (0x3E8)
+/* CLK_DIV_TOP1 */
+#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
+#define ACLK_66_PRE_RATIO 0x1
+#define ACLK_400_ISP_RATIO 0x1
+#define ACLK_400_IOP_RATIO 0x1
+#define ACLK_300_GSCL_RATIO 0x2
+
+#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
+ | (ACLK_66_PRE_RATIO << 24) \
+ | (ACLK_400_ISP_RATIO << 20) \
+ | (ACLK_400_IOP_RATIO << 16) \
+ | (ACLK_300_GSCL_RATIO << 12))
+
+/* APLL_LOCK */
+#define APLL_LOCK_VAL (0x546)
+/* MPLL_LOCK */
+#define MPLL_LOCK_VAL (0x546)
+/* CPLL_LOCK */
+#define CPLL_LOCK_VAL (0x546)
+/* GPLL_LOCK */
+#define GPLL_LOCK_VAL (0x546)
+/* EPLL_LOCK */
+#define EPLL_LOCK_VAL (0x3A98)
+/* VPLL_LOCK */
+#define VPLL_LOCK_VAL (0x3A98)
+/* BPLL_LOCK */
+#define BPLL_LOCK_VAL (0x546)
+
+#define MUX_APLL_SEL_MASK (1 << 0)
+#define MUX_MPLL_SEL_MASK (1 << 8)
+#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
+#define MUX_CPLL_SEL_MASK (1 << 8)
+#define MUX_EPLL_SEL_MASK (1 << 12)
+#define MUX_VPLL_SEL_MASK (1 << 16)
+#define MUX_GPLL_SEL_MASK (1 << 28)
+#define MUX_BPLL_SEL_MASK (1 << 0)
+#define MUX_HPM_SEL_MASK (1 << 20)
+#define HPM_SEL_SCLK_MPLL (1 << 21)
+#define APLL_CON0_LOCKED (1 << 29)
+#define MPLL_CON0_LOCKED (1 << 29)
+#define BPLL_CON0_LOCKED (1 << 29)
+#define CPLL_CON0_LOCKED (1 << 29)
+#define EPLL_CON0_LOCKED (1 << 29)
+#define GPLL_CON0_LOCKED (1 << 29)
+#define VPLL_CON0_LOCKED (1 << 29)
+#define CLK_REG_DISABLE 0x0
+#define TOP2_VAL 0x0110000
/* CLK_SRC_PERIC0 */
+#define PWM_SEL 0
+#define UART3_SEL 6
+#define UART2_SEL 6
+#define UART1_SEL 6
+#define UART0_SEL 6
+/* SRC_CLOCK = SCLK_MPLL */
+#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
+ | (UART3_SEL << 12) \
+ | (UART2_SEL << 8) \
+ | (UART1_SEL << 4) \
+ | (UART0_SEL))
+
+/* CLK_SRC_PERIC1 */
/* SRC_CLOCK = SCLK_MPLL */
-#define PWM_SEL 0
-#define UART4_SEL 6
-#define UART3_SEL 6
-#define UART2_SEL 6
-#define UART1_SEL 6
-#define UART0_SEL 6
-#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
- | (UART4_SEL << 16) \
- | (UART3_SEL << 12) \
- | (UART2_SEL << 8) \
- | (UART1_SEL << 4) \
- | (UART0_SEL << 0))
-
-#define CLK_SRC_FSYS_VAL 0x66666
-#define CLK_DIV_FSYS0_VAL 0x0BB00000
-#define CLK_DIV_FSYS1_VAL 0x000f000f
-#define CLK_DIV_FSYS2_VAL 0x020f020f
-#define CLK_DIV_FSYS3_VAL 0x000f
-
-/* CLK_DIV_PERIC0 */
-#define UART5_RATIO 8
-#define UART4_RATIO 8
-#define UART3_RATIO 8
-#define UART2_RATIO 8
-#define UART1_RATIO 8
-#define UART0_RATIO 8
-#define CLK_DIV_PERIC0_VAL ((UART4_RATIO << 16) \
- | (UART3_RATIO << 12) \
- | (UART2_RATIO << 8) \
- | (UART1_RATIO << 4) \
- | (UART0_RATIO << 0))
+#define SPI0_SEL 6
+#define SPI1_SEL 6
+#define SPI2_SEL 6
+#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \
+ | (SPI1_SEL << 20) \
+ | (SPI0_SEL << 16))
+
+/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
+#define SPI0_ISP_SEL 6
+#define SPI1_ISP_SEL 6
+#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
+ | (SPI0_ISP_SEL << 0)
+
+/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
+#define SPI0_ISP_RATIO 0xf
+#define SPI1_ISP_RATIO 0xf
+#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
+ | (SPI0_ISP_RATIO << 0)
+
+/* CLK_DIV_PERIL0 */
+#define UART5_RATIO 7
+#define UART4_RATIO 7
+#define UART3_RATIO 7
+#define UART2_RATIO 7
+#define UART1_RATIO 7
+#define UART0_RATIO 7
+
+#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
+ | (UART2_RATIO << 8) \
+ | (UART1_RATIO << 4) \
+ | (UART0_RATIO))
+/* CLK_DIV_PERIC1 */
+#define SPI1_RATIO 0x7
+#define SPI0_RATIO 0xf
+#define SPI1_SUB_RATIO 0x0
+#define SPI0_SUB_RATIO 0x0
+#define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \
+ | ((SPI1_RATIO << 16) \
+ | (SPI0_SUB_RATIO << 8) \
+ | (SPI0_RATIO << 0)))
+
+/* CLK_DIV_PERIC2 */
+#define SPI2_RATIO 0xf
+#define SPI2_SUB_RATIO 0x0
+#define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \
+ | (SPI2_RATIO << 0))
/* CLK_DIV_PERIC3 */
#define PWM_RATIO 8
#define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
+/* CLK_DIV_FSYS2 */
+#define MMC2_RATIO_MASK 0xf
+#define MMC2_RATIO_VAL 0x3
+#define MMC2_RATIO_OFFSET 0
+
+#define MMC2_PRE_RATIO_MASK 0xff
+#define MMC2_PRE_RATIO_VAL 0x9
+#define MMC2_PRE_RATIO_OFFSET 8
+
+#define MMC3_RATIO_MASK 0xf
+#define MMC3_RATIO_VAL 0x1
+#define MMC3_RATIO_OFFSET 16
+
+#define MMC3_PRE_RATIO_MASK 0xff
+#define MMC3_PRE_RATIO_VAL 0x0
+#define MMC3_PRE_RATIO_OFFSET 24
+
/* CLK_SRC_LEX */
-#define CLK_SRC_LEX_VAL 0x0
+#define CLK_SRC_LEX_VAL 0x0
/* CLK_DIV_LEX */
-#define CLK_DIV_LEX_VAL 0x10
+#define CLK_DIV_LEX_VAL 0x10
/* CLK_DIV_R0X */
-#define CLK_DIV_R0X_VAL 0x10
+#define CLK_DIV_R0X_VAL 0x10
/* CLK_DIV_L0X */
-#define CLK_DIV_R1X_VAL 0x10
+#define CLK_DIV_R1X_VAL 0x10
-/* SCLK_SRC_ISP */
-#define SCLK_SRC_ISP_VAL 0x600
/* CLK_DIV_ISP0 */
-#define CLK_DIV_ISP0_VAL 0x31
+#define CLK_DIV_ISP0_VAL 0x31
/* CLK_DIV_ISP1 */
-#define CLK_DIV_ISP1_VAL 0x0
+#define CLK_DIV_ISP1_VAL 0x0
/* CLK_DIV_ISP2 */
-#define CLK_DIV_ISP2_VAL 0x1
+#define CLK_DIV_ISP2_VAL 0x1
+
+/* CLK_SRC_DISP1_0 */
+#define CLK_SRC_DISP1_0_VAL 0x6
+
+/*
+ * DIV_DISP1_0
+ * For DP, divisor should be 2
+ */
+#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
-#define MPLL_DEC (MPLL_MDIV * MPLL_MDIV / (MPLL_PDIV * 2^(MPLL_SDIV-1)))
+/* CLK_GATE_IP_DISP1 */
+#define CLK_GATE_DP1_ALLOW (1 << 4)
/*
* TZPC Register Value :
*/
#define DECPROTXSET 0xFF
-/* DMC Init */
-#define SET 1
-#define RESET 0
-/* (Memory Interleaving Size = 1 << IV_SIZE) */
-#define CONFIG_IV_SIZE 0x07
+#define DDR3PHY_CTRL_PHY_RESET (1 << 0)
+#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
-#define PHY_RESET_VAL (0 << 0)
+#define PHY_CON0_RESET_VAL 0x17020a40
+#define P0_CMD_EN (1 << 14)
+#define BYTE_RDLVL_EN (1 << 13)
+#define CTRL_SHGATE (1 << 8)
+
+#define PHY_CON1_RESET_VAL 0x09210100
+#define CTRL_GATEDURADJ_MASK (0xf << 20)
+
+#define PHY_CON2_RESET_VAL 0x00010004
+#define INIT_DESKEW_EN (1 << 6)
+#define RDLVL_GATE_EN (1 << 24)
/*ZQ Configurations */
#define PHY_CON16_RESET_VAL 0x08000304
-#define ZQ_MODE_DDS_VAL (0x5 << 24)
-#define ZQ_MODE_TERM_VAL (0x5 << 21)
-#define SET_ZQ_MODE_DDS_VAL(x) (x = (x & ~(0x7 << 24)) | ZQ_MODE_DDS_VAL)
-#define SET_ZQ_MODE_TERM_VAL(x) (x = (x & ~(0x7 << 21)) | ZQ_MODE_TERM_VAL)
-
-#define ZQ_MODE_NOTERM (1 << 19)
#define ZQ_CLK_DIV_EN (1 << 18)
#define ZQ_MANUAL_STR (1 << 1)
+#define ZQ_DONE (1 << 0)
+
+#define CTRL_RDLVL_GATE_ENABLE 1
+#define CTRL_RDLVL_GATE_DISABLE 1
+
+/* Direct Command */
+#define DIRECT_CMD_NOP 0x07000000
+#define DIRECT_CMD_PALL 0x01000000
+#define DIRECT_CMD_ZQINIT 0x0a000000
+#define DIRECT_CMD_CHANNEL_SHIFT 28
+#define DIRECT_CMD_CHIP_SHIFT 20
+
+/* DMC PHY Control0 register */
+#define PHY_CONTROL0_RESET_VAL 0x0
+#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
+#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
+#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
+#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
+
+/* Driver strength for CK, CKE, CS & CA */
+#define IMP_OUTPUT_DRV_40_OHM 0x5
+#define IMP_OUTPUT_DRV_30_OHM 0x7
+#define CA_CK_DRVR_DS_OFFSET 9
+#define CA_CKE_DRVR_DS_OFFSET 6
+#define CA_CS_DRVR_DS_OFFSET 3
+#define CA_ADR_DRVR_DS_OFFSET 0
+
+#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
+#define PHY_CON42_CTRL_RDLAT_SHIFT 0
+
+struct mem_timings;
+
+/* Errors that we can encourter in low-level setup */
+enum {
+ SETUP_ERR_OK,
+ SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
+ SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
+};
-/* Channel and Chip Selection */
-#define CONFIG_DMC_CHANNELS 2
-#define CONFIG_CHIPS_PER_CHANNEL 2
-
-#define SET_CMD_CHANNEL(x, y) (x = (x & ~(1 << 28)) | y << 28)
-#define SET_CMD_CHIP(x, y) (x = (x & ~(1 << 20)) | y << 20)
-
-/* Diret Command */
-#define DIRECT_CMD_NOP 0x07000000
-#define DIRECT_CMD_MRS1 0x00071C00
-#define DIRECT_CMD_MRS2 0x00010BFC
-#define DIRECT_CMD_MRS3 0x00000708
-#define DIRECT_CMD_MRS4 0x00000818
-#define DIRECT_CMD_PALL 0x01000000
-
-/* DLL Resync */
-#define FP_RSYNC (1 << 3)
-
-#define CONFIG_CTRL_DLL_ON(x, y) (x = (x & ~(1 << 5)) | y << 5)
-#define CONFIG_CTRL_START(x, y) (x = (x & ~(1 << 6)) | y << 6)
-#define SET_CTRL_FORCE_VAL(x, y) (x = (x & ~(0x7F << 8)) | y << 8)
+/*
+ * Memory variant specific initialization code
+ *
+ * @param mem Memory timings for this memory type.
+ * @param mem_iv_size Memory interleaving size is a configurable parameter
+ * which the DMC uses to decide how to split a memory
+ * chunk into smaller chunks to support concurrent
+ * accesses; may vary across boards.
+ * @return 0 if ok, SETUP_ERR_... if there is a problem
+ */
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size);
-/* RDLVL */
-#define PHY_CON0_RESET_VAL 0x17023240
-#define DDR_MODE_LPDDR2 0x2
-#define BYTE_RDLVL_EN (1 << 13)
-#define CTRL_ATGATE (1 << 6)
-#define SET_CTRL_DDR_MODE(x, y) (x = (x & ~(0x3 << 11)) | y << 11)
+/*
+ * Configure ZQ I/O interface
+ *
+ * @param mem Memory timings for this memory type.
+ * @param phy0_ctrl Pointer to struct containing PHY0 control reg
+ * @param phy1_ctrl Pointer to struct containing PHY1 control reg
+ * @return 0 if ok, -1 on error
+ */
+int dmc_config_zq(struct mem_timings *mem,
+ struct exynos5_phy_control *phy0_ctrl,
+ struct exynos5_phy_control *phy1_ctrl);
-#define PHY_CON1_RESET_VAL 0x9210100
-#define RDLVL_RDDATAPADJ 0x1
-#define SET_RDLVL_RDDATAPADJ ((PHY_CON1_RESET_VAL & ~(0xFFFF << 0))\
- | RDLVL_RDDATAPADJ << 0)
+/*
+ * Send NOP and MRS/EMRS Direct commands
+ *
+ * @param mem Memory timings for this memory type.
+ * @param dmc Pointer to struct of DMC registers
+ */
+void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc);
-#define PHY_CON2_RESET_VAL 0x00010004
-#define RDLVL_EN (1 << 25)
-#define RDDSKEW_CLEAR (1 << 13)
-
-#define CTRL_RDLVL_DATA_EN (1 << 1)
-#define LPDDR2_ADDR 0x00000208
-
-#define DMC_MEMCONFIG0_VAL 0x00001323
-#define DMC_MEMCONFIG1_VAL 0x00001323
-#define DMC_MEMBASECONFIG0_VAL 0x00400780
-#define DMC_MEMBASECONFIG1_VAL 0x00800780
-#define DMC_MEMCONTROL_VAL 0x00212500
-#define DMC_PRECHCONFIG_VAL 0xFF000000
-#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
-#define DMC_TIMINGREF_VAL 0x0000005D
-#define DMC_TIMINGROW_VAL 0x2336544C
-#define DMC_TIMINGDATA_VAL 0x24202408
-#define DMC_TIMINGPOWER_VAL 0x38260235
-
-#define CTRL_BSTLEN 0x04
-#define CTRL_RDLAT 0x08
-#define PHY_CON42_VAL (CTRL_BSTLEN << 8 | CTRL_RDLAT << 0)
-
-/* DQS, DQ, DEBUG offsets */
-#define SET_DQS_OFFSET_VAL 0x7F7F7F7F
-#define SET_DQ_OFFSET_VAL 0x7F7F7F7F
-#define SET_DEBUG_OFFSET_VAL 0x7F
-
-#define RESET_DQS_OFFSET_VAL 0x08080808
-#define RESET_DQ_OFFSET_VAL 0x08080808
-#define RESET_DEBUG_OFFSET_VAL 0x8
-
-#define CTRL_PULLD_DQ (0x0F << 8)
-#define CTRL_PULLD_DQS (0x0F << 0)
+/*
+ * Send PALL Direct commands
+ *
+ * @param mem Memory timings for this memory type.
+ * @param dmc Pointer to struct of DMC registers
+ */
+void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc);
-#define DFI_INIT_START (1 << 28)
+/*
+ * Configure the memconfig and membaseconfig registers
+ *
+ * @param mem Memory timings for this memory type.
+ * @param exynos5_dmc Pointer to struct of DMC registers
+ */
+void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
-#define CLK_STOP_EN (1 << 0)
-#define DPWRDN_EN (1 << 1)
-#define DSREF_EN (1 << 5)
+/*
+ * Reset the DLL. This function is common between DDR3 and LPDDR2.
+ * However, the reset value is different. So we are passing a flag
+ * ddr_mode to distinguish between LPDDR2 and DDR3.
+ *
+ * @param exynos5_dmc Pointer to struct of DMC registers
+ * @param ddr_mode Type of DDR memory
+ */
+void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);
-#define AREF_EN (1 << 5)
void sdelay(unsigned long);
void mem_ctrl_init(void);
void system_clock_init(void);
void tzpc_init(void);
-
#endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Based on arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ arch/arm/cpu/armv7/start.o (.text)
+ *(.text*)
+ } >.sram
+ . = ALIGN(4);
+
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+ . = ALIGN(4);
+
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+ . = ALIGN(4);
+
+ /* Align .machine_param on 256 byte boundary for easier searching */
+ .machine_param ALIGN(0x100) : { *(.machine_param) } >.sram
+ . = ALIGN(4);
+
+ __image_copy_end = .;
+ _end = .;
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } >.sram
+}
{
int err;
- err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
if (err) {
- debug("SDMMC2 not configured\n");
+ debug("SDMMC0 not configured\n");
return err;
}
- err = s5p_mmc_init(2, 4);
+ err = s5p_mmc_init(0, 8);
return err;
}
#endif
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/clk.h>
+
+#define SIGNATURE 0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+ __attribute__((section(".machine_param"))) = {
+ .signature = SIGNATURE,
+ .version = 1,
+ .params = "vmubfasirM",
+ .size = sizeof(machine_param),
+
+ .mem_iv_size = 0x1f,
+ .mem_type = DDR_MODE_DDR3,
+
+ /*
+ * Set uboot_size to 0x100000 bytes.
+ *
+ * This is an overly conservative value chosen to accommodate all
+ * possible U-Boot image. You are advised to set this value to a
+ * smaller realistic size via scripts that modifies the .machine_param
+ * section of output U-Boot image.
+ */
+ .uboot_size = 0x100000,
+
+ .boot_source = BOOT_MODE_OM,
+ .frequency_mhz = 800,
+ .arm_freq_mhz = 1700,
+ .serial_base = 0x12c30000,
+ .i2c_base = 0x12c60000,
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+ if (machine_param.signature != SIGNATURE) {
+ /* Will hang if SIGNATURE dont match */
+ while (1)
+ ;
+ }
+
+ return &machine_param;
+}
#
-# (C) Copyright 2009
-# ISEE 2007 SL, <www.iseebcn.com>
-#
-# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
+# (C) Copyright 2000-2012
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+ifndef CONFIG_SPL_BUILD
+COBJS := sc_sps_1.o
+else
+COBJS := spl_boot.o
+endif
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * SchulerControl GmbH, SC_SPS_1 module
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mx28_set_ioclk(MXC_IOCLK0, 480000);
+ /* IO1 clock at 480MHz */
+ mx28_set_ioclk(MXC_IOCLK1, 480000);
+
+ /* SSP0 clock at 96MHz */
+ mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
+ /* SSP2 clock at 96MHz */
+ mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
+
+#ifdef CONFIG_CMD_USB
+ mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT);
+ mxs_iomux_setup_pad(MX28_PAD_AUART2_TX__GPIO_3_9 |
+ MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
+ gpio_direction_output(MX28_PAD_AUART2_TX__GPIO_3_9, 1);
+#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ return mxs_dram_init();
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ return mxsmmc_initialize(bis, 0, NULL);
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ int ret;
+
+ ret = cpu_eth_init(bis);
+
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
+ CLKCTRL_ENET_TIME_SEL_MASK,
+ CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN);
+
+ ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC0\n");
+ return ret;
+ }
+
+ ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC1\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+#endif
--- /dev/null
+/*
+ * SchulerControl GmbH, SC_SPS_1 module setup
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* -- Strick 3 -- */
+
+ /* FEC Ethernet */
+ MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
+
+ MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* ENET INT */
+
+ MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+
+ /* -- Strick 4 -- */
+
+ /* EMI */
+ MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+
+ /* -- Strick 5 -- */
+
+ /* MMC0 */
+ MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+ (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+ MX28_PAD_SSP0_SCK__SSP0_SCK |
+ (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+
+ /* SPI2 (for flash) */
+ MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_SS0__SSP2_D3 |
+ (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+
+ /* -- Strick 6 -- */
+
+ /* I2C */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+ /* AUART0 */
+ MX28_PAD_AUART0_TX__AUART0_TX,
+ MX28_PAD_AUART0_RX__AUART0_RX,
+
+ /* MEGA interface */
+
+ /* Debug UART */
+ MX28_PAD_PWM0__DUART_RX,
+ MX28_PAD_PWM1__DUART_TX,
+
+ /* LED */
+ MX28_PAD_GPMI_D00__GPIO_0_0 | MUX_CONFIG_LED,
+ MX28_PAD_GPMI_D03__GPIO_0_3 | MUX_CONFIG_LED,
+ MX28_PAD_GPMI_D06__GPIO_0_6 | MUX_CONFIG_LED,
+};
+
+void board_init_ll(void)
+{
+ mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+}
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ dram_vals[0x74 >> 2] = 0x0f02010a;
+}
--- /dev/null
+#
+# Copyright (C) ST-Ericsson SA 2009
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+CFLAGS += -D__RELEASE -D__STN_8500
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := snowball.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
+ * The purpose is that GPIO config found in kernel should work by simply
+ * copy-paste it to U-boot.
+ *
+ * Ported to U-boot by:
+ * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com>
+ **
+ * License terms: GNU General Public License, version 2
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com>
+ */
+
+#ifndef __DB8500_PINS_H
+#define __DB8500_PINS_H
+
+#include <asm/arch/db8500_pincfg.h>
+
+#define GPIO0_GPIO PIN_CFG(0, GPIO)
+#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A)
+#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B)
+#define GPIO0_IP_TDO PIN_CFG(0, ALT_C)
+
+#define GPIO1_GPIO PIN_CFG(1, GPIO)
+#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A)
+#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B)
+#define GPIO1_IP_TDI PIN_CFG(1, ALT_C)
+
+#define GPIO2_GPIO PIN_CFG(2, GPIO)
+#define GPIO2_U0_RXD PIN_CFG(2, ALT_A)
+#define GPIO2_NONE PIN_CFG(2, ALT_B)
+#define GPIO2_IP_TMS PIN_CFG(2, ALT_C)
+
+#define GPIO3_GPIO PIN_CFG(3, GPIO)
+#define GPIO3_U0_TXD PIN_CFG(3, ALT_A)
+#define GPIO3_NONE PIN_CFG(3, ALT_B)
+#define GPIO3_IP_TCK PIN_CFG(3, ALT_C)
+
+#define GPIO4_GPIO PIN_CFG(4, GPIO)
+#define GPIO4_U1_RXD PIN_CFG(4, ALT_A)
+#define GPIO4_I2C4_SCL PIN_CFG_PULL(4, ALT_B, UP)
+#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C)
+
+#define GPIO5_GPIO PIN_CFG(5, GPIO)
+#define GPIO5_U1_TXD PIN_CFG(5, ALT_A)
+#define GPIO5_I2C4_SDA PIN_CFG_PULL(5, ALT_B, UP)
+#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C)
+
+#define GPIO6_GPIO PIN_CFG(6, GPIO)
+#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A)
+#define GPIO6_I2C1_SCL PIN_CFG_PULL(6, ALT_B, UP)
+#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C)
+
+#define GPIO7_GPIO PIN_CFG(7, GPIO)
+#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A)
+#define GPIO7_I2C1_SDA PIN_CFG_PULL(7, ALT_B, UP)
+#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C)
+
+#define GPIO8_GPIO PIN_CFG(8, GPIO)
+#define GPIO8_IPI2C_SDA PIN_CFG_PULL(8, ALT_A, UP)
+#define GPIO8_I2C2_SDA PIN_CFG_PULL(8, ALT_B, UP)
+
+#define GPIO9_GPIO PIN_CFG(9, GPIO)
+#define GPIO9_IPI2C_SCL PIN_CFG_PULL(9, ALT_A, UP)
+#define GPIO9_I2C2_SCL PIN_CFG_PULL(9, ALT_B, UP)
+
+#define GPIO10_GPIO PIN_CFG(10, GPIO)
+#define GPIO10_IPI2C_SDA PIN_CFG_PULL(10, ALT_A, UP)
+#define GPIO10_I2C2_SDA PIN_CFG_PULL(10, ALT_B, UP)
+#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C)
+
+#define GPIO11_GPIO PIN_CFG(11, GPIO)
+#define GPIO11_IPI2C_SCL PIN_CFG_PULL(11, ALT_A, UP)
+#define GPIO11_I2C2_SCL PIN_CFG_PULL(11, ALT_B, UP)
+#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C)
+
+#define GPIO12_GPIO PIN_CFG(12, GPIO)
+#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A)
+#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B)
+
+#define GPIO13_GPIO PIN_CFG(13, GPIO)
+#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A)
+
+#define GPIO14_GPIO PIN_CFG(14, GPIO)
+#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A)
+
+#define GPIO15_GPIO PIN_CFG(15, GPIO)
+#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A)
+#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B)
+
+#define GPIO16_GPIO PIN_CFG(16, GPIO)
+#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A)
+#define GPIO16_I2C1_SCL PIN_CFG_PULL(16, ALT_B, UP)
+#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C)
+
+#define GPIO17_GPIO PIN_CFG(17, GPIO)
+#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A)
+#define GPIO17_I2C1_SDA PIN_CFG_PULL(17, ALT_B, UP)
+#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C)
+
+#define GPIO18_GPIO PIN_CFG(18, GPIO)
+#define GPIO18_MC0_CMDDIR PIN_CFG(18, ALT_A)
+#define GPIO18_U2_RXD PIN_CFG(18, ALT_B)
+#define GPIO18_MS_IEP PIN_CFG(18, ALT_C)
+
+#define GPIO19_GPIO PIN_CFG(19, GPIO)
+#define GPIO19_MC0_DAT0DIR PIN_CFG(19, ALT_A)
+#define GPIO19_U2_TXD PIN_CFG(19, ALT_B)
+#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C)
+
+#define GPIO20_GPIO PIN_CFG(20, GPIO)
+#define GPIO20_MC0_DAT2DIR PIN_CFG(20, ALT_A)
+#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B)
+#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C)
+
+#define GPIO21_GPIO PIN_CFG(21, GPIO)
+#define GPIO21_MC0_DAT31DIR PIN_CFG(21, ALT_A)
+#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B)
+#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C)
+
+#define GPIO22_GPIO PIN_CFG(22, GPIO)
+#define GPIO22_MC0_FBCLK PIN_CFG(22, ALT_A)
+#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B)
+#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C)
+
+#define GPIO23_GPIO PIN_CFG(23, GPIO)
+#define GPIO23_MC0_CLK PIN_CFG(23, ALT_A)
+#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B)
+#define GPIO23_MS_CLK PIN_CFG(23, ALT_C)
+
+#define GPIO24_GPIO PIN_CFG(24, GPIO)
+#define GPIO24_MC0_CMD PIN_CFG(24, ALT_A)
+#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B)
+#define GPIO24_MS_BS PIN_CFG(24, ALT_C)
+
+#define GPIO25_GPIO PIN_CFG(25, GPIO)
+#define GPIO25_MC0_DAT0 PIN_CFG(25, ALT_A)
+#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B)
+#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C)
+
+#define GPIO26_GPIO PIN_CFG(26, GPIO)
+#define GPIO26_MC0_DAT1 PIN_CFG(26, ALT_A)
+#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B)
+#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C)
+
+#define GPIO27_GPIO PIN_CFG(27, GPIO)
+#define GPIO27_MC0_DAT2 PIN_CFG(27, ALT_A)
+#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B)
+#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C)
+
+#define GPIO28_GPIO PIN_CFG(28, GPIO)
+#define GPIO28_MC0_DAT3 PIN_CFG(28, ALT_A)
+#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B)
+#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C)
+
+#define GPIO29_GPIO PIN_CFG(29, GPIO)
+#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A)
+#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B)
+#define GPIO29_U2_RXD PIN_CFG(29, ALT_C)
+
+#define GPIO30_GPIO PIN_CFG(30, GPIO)
+#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A)
+#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B)
+#define GPIO30_U2_TXD PIN_CFG(30, ALT_C)
+
+#define GPIO31_GPIO PIN_CFG(31, GPIO)
+#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A)
+#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B)
+#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C)
+
+#define GPIO32_GPIO PIN_CFG(32, GPIO)
+#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A)
+#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B)
+#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C)
+
+#define GPIO33_GPIO PIN_CFG(33, GPIO)
+#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A)
+#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B)
+#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C)
+
+#define GPIO34_GPIO PIN_CFG(34, GPIO)
+#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A)
+#define GPIO34_NONE PIN_CFG(34, ALT_B)
+#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C)
+
+#define GPIO35_GPIO PIN_CFG(35, GPIO)
+#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A)
+#define GPIO35_NONE PIN_CFG(35, ALT_B)
+#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C)
+
+#define GPIO36_GPIO PIN_CFG(36, GPIO)
+#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A)
+#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B)
+#define GPIO36_U0_RIn PIN_CFG(36, ALT_C)
+
+#define GPIO64_GPIO PIN_CFG(64, GPIO)
+#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A)
+#define GPIO64_KP_O1 PIN_CFG(64, ALT_B)
+#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C)
+
+#define GPIO65_GPIO PIN_CFG(65, GPIO)
+#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A)
+#define GPIO65_KP_O0 PIN_CFG(65, ALT_B)
+#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C)
+
+#define GPIO66_GPIO PIN_CFG(66, GPIO)
+#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A)
+#define GPIO66_KP_I1 PIN_CFG(66, ALT_B)
+#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C)
+
+#define GPIO67_GPIO PIN_CFG(67, GPIO)
+#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A)
+#define GPIO67_KP_I0 PIN_CFG(67, ALT_B)
+#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C)
+
+#define GPIO68_GPIO PIN_CFG(68, GPIO)
+#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A)
+#define GPIO68_KP_O7 PIN_CFG(68, ALT_B)
+#define GPIO68_SM_CLE PIN_CFG(68, ALT_C)
+
+#define GPIO69_GPIO PIN_CFG(69, GPIO)
+#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A)
+#define GPIO69_KP_I7 PIN_CFG(69, ALT_B)
+#define GPIO69_SM_ALE PIN_CFG(69, ALT_C)
+
+#define GPIO70_GPIO PIN_CFG(70, GPIO)
+#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A)
+#define GPIO70_KP_O5 PIN_CFG(70, ALT_B)
+#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C)
+
+#define GPIO71_GPIO PIN_CFG(71, GPIO)
+#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A)
+#define GPIO71_KP_O4 PIN_CFG(71, ALT_B)
+#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C)
+
+#define GPIO72_GPIO PIN_CFG(72, GPIO)
+#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A)
+#define GPIO72_KP_O3 PIN_CFG(72, ALT_B)
+#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C)
+
+#define GPIO73_GPIO PIN_CFG(73, GPIO)
+#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A)
+#define GPIO73_KP_O2 PIN_CFG(73, ALT_B)
+#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C)
+
+#define GPIO74_GPIO PIN_CFG(74, GPIO)
+#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A)
+#define GPIO74_KP_I5 PIN_CFG(74, ALT_B)
+#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C)
+
+#define GPIO75_GPIO PIN_CFG(75, GPIO)
+#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A)
+#define GPIO75_KP_I4 PIN_CFG(75, ALT_B)
+#define GPIO75_U2_RXD PIN_CFG(75, ALT_C)
+
+#define GPIO76_GPIO PIN_CFG(76, GPIO)
+#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A)
+#define GPIO76_KP_I3 PIN_CFG(76, ALT_B)
+#define GPIO76_U2_TXD PIN_CFG(76, ALT_C)
+
+#define GPIO77_GPIO PIN_CFG(77, GPIO)
+#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A)
+#define GPIO77_KP_I2 PIN_CFG(77, ALT_B)
+#define GPIO77_NONE PIN_CFG(77, ALT_C)
+
+#define GPIO78_GPIO PIN_CFG(78, GPIO)
+#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A)
+#define GPIO78_KP_O6 PIN_CFG(78, ALT_B)
+#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C)
+
+#define GPIO79_GPIO PIN_CFG(79, GPIO)
+#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A)
+#define GPIO79_KP_I6 PIN_CFG(79, ALT_B)
+#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C)
+
+#define GPIO80_GPIO PIN_CFG(80, GPIO)
+#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A)
+#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B)
+#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C)
+
+#define GPIO81_GPIO PIN_CFG(81, GPIO)
+#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A)
+#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B)
+#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C)
+
+#define GPIO82_GPIO PIN_CFG(82, GPIO)
+#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A)
+#define GPIO82_KP_O5 PIN_CFG(82, ALT_B)
+
+#define GPIO83_GPIO PIN_CFG(83, GPIO)
+#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A)
+#define GPIO83_KP_O4 PIN_CFG(83, ALT_B)
+
+#define GPIO84_GPIO PIN_CFG_PULL(84, GPIO, UP)
+#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A)
+#define GPIO84_KP_I5 PIN_CFG(84, ALT_B)
+
+#define GPIO85_GPIO PIN_CFG(85, GPIO)
+#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A)
+#define GPIO85_KP_I4 PIN_CFG(85, ALT_B)
+
+#define GPIO86_GPIO PIN_CFG(86, GPIO)
+#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A)
+#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B)
+#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C)
+
+#define GPIO87_GPIO PIN_CFG(87, GPIO)
+#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A)
+#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B)
+#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C)
+
+#define GPIO88_GPIO PIN_CFG(88, GPIO)
+#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A)
+#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B)
+#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C)
+
+#define GPIO89_GPIO PIN_CFG(89, GPIO)
+#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A)
+#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B)
+#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C)
+
+#define GPIO90_GPIO PIN_CFG(90, GPIO)
+#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A)
+#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B)
+#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C)
+
+#define GPIO91_GPIO PIN_CFG(91, GPIO)
+#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A)
+#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B)
+#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C)
+
+#define GPIO92_GPIO PIN_CFG(92, GPIO)
+#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A)
+#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B)
+#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C)
+
+#define GPIO93_GPIO PIN_CFG(93, GPIO)
+#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A)
+#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B)
+#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C)
+
+#define GPIO94_GPIO PIN_CFG(94, GPIO)
+#define GPIO94_KP_O7 PIN_CFG(94, ALT_A)
+#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B)
+#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C)
+
+#define GPIO95_GPIO PIN_CFG(95, GPIO)
+#define GPIO95_KP_I7 PIN_CFG(95, ALT_A)
+#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B)
+#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C)
+
+#define GPIO96_GPIO PIN_CFG(96, GPIO)
+#define GPIO96_KP_O6 PIN_CFG(96, ALT_A)
+#define GPIO96_SM_OEn PIN_CFG(96, ALT_B)
+#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C)
+
+#define GPIO97_GPIO PIN_CFG(97, GPIO)
+#define GPIO97_KP_I6 PIN_CFG(97, ALT_A)
+#define GPIO97_SM_WEn PIN_CFG(97, ALT_B)
+#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C)
+
+#define GPIO128_GPIO PIN_CFG(128, GPIO)
+#define GPIO128_MC2_CLK PIN_CFG(128, ALT_A)
+#define GPIO128_SM_CKO PIN_CFG(128, ALT_B)
+
+#define GPIO129_GPIO PIN_CFG(129, GPIO)
+#define GPIO129_MC2_CMD PIN_CFG(129, ALT_A)
+#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B)
+
+#define GPIO130_GPIO PIN_CFG(130, GPIO)
+#define GPIO130_MC2_FBCLK PIN_CFG(130, ALT_A)
+#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B)
+#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C)
+
+#define GPIO131_GPIO PIN_CFG(131, GPIO)
+#define GPIO131_MC2_DAT0 PIN_CFG(131, ALT_A)
+#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B)
+
+#define GPIO132_GPIO PIN_CFG(132, GPIO)
+#define GPIO132_MC2_DAT1 PIN_CFG(132, ALT_A)
+#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B)
+
+#define GPIO133_GPIO PIN_CFG(133, GPIO)
+#define GPIO133_MC2_DAT2 PIN_CFG(133, ALT_A)
+#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B)
+
+#define GPIO134_GPIO PIN_CFG(134, GPIO)
+#define GPIO134_MC2_DAT3 PIN_CFG(134, ALT_A)
+#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B)
+
+#define GPIO135_GPIO PIN_CFG(135, GPIO)
+#define GPIO135_MC2_DAT4 PIN_CFG(135, ALT_A)
+#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B)
+
+#define GPIO136_GPIO PIN_CFG(136, GPIO)
+#define GPIO136_MC2_DAT5 PIN_CFG(136, ALT_A)
+#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B)
+
+#define GPIO137_GPIO PIN_CFG(137, GPIO)
+#define GPIO137_MC2_DAT6 PIN_CFG(137, ALT_A)
+#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B)
+
+#define GPIO138_GPIO PIN_CFG(138, GPIO)
+#define GPIO138_MC2_DAT7 PIN_CFG(138, ALT_A)
+#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B)
+
+#define GPIO139_GPIO PIN_CFG(139, GPIO)
+#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A)
+#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B)
+#define GPIO139_KP_O8 PIN_CFG(139, ALT_C)
+
+#define GPIO140_GPIO PIN_CFG(140, GPIO)
+#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A)
+#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B)
+#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C)
+
+#define GPIO141_GPIO PIN_CFG(141, GPIO)
+#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A)
+#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B)
+#define GPIO141_KP_O9 PIN_CFG(141, ALT_C)
+
+#define GPIO142_GPIO PIN_CFG(142, GPIO)
+#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A)
+#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B)
+#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C)
+
+#define GPIO143_GPIO PIN_CFG(143, GPIO)
+#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A)
+
+#define GPIO144_GPIO PIN_CFG(144, GPIO)
+#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A)
+
+#define GPIO145_GPIO PIN_CFG(145, GPIO)
+#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A)
+
+#define GPIO146_GPIO PIN_CFG(146, GPIO)
+#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A)
+
+#define GPIO147_GPIO PIN_CFG(147, GPIO)
+#define GPIO147_I2C0_SCL PIN_CFG_PULL(147, ALT_A, UP)
+
+#define GPIO148_GPIO PIN_CFG(148, GPIO)
+#define GPIO148_I2C0_SDA PIN_CFG_PULL(148, ALT_A, UP)
+
+#define GPIO149_GPIO PIN_CFG(149, GPIO)
+#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A)
+#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B)
+#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C)
+
+#define GPIO150_GPIO PIN_CFG(150, GPIO)
+#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A)
+#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B)
+
+#define GPIO151_GPIO PIN_CFG(151, GPIO)
+#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A)
+#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B)
+#define GPIO151_KP_O8 PIN_CFG(151, ALT_C)
+
+#define GPIO152_GPIO PIN_CFG(152, GPIO)
+#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A)
+#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B)
+#define GPIO152_KP_O9 PIN_CFG(152, ALT_C)
+
+#define GPIO153_GPIO PIN_CFG(153, GPIO)
+#define GPIO153_KP_I7 PIN_CFG_PULL(153, ALT_A, DOWN)
+#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B)
+#define GPIO153_U2_RXD PIN_CFG(153, ALT_C)
+
+#define GPIO154_GPIO PIN_CFG(154, GPIO)
+#define GPIO154_KP_I6 PIN_CFG_PULL(154, ALT_A, DOWN)
+#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B)
+#define GPIO154_U2_TXD PIN_CFG(154, ALT_C)
+
+#define GPIO155_GPIO PIN_CFG(155, GPIO)
+#define GPIO155_KP_I5 PIN_CFG_PULL(155, ALT_A, DOWN)
+#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B)
+#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C)
+
+#define GPIO156_GPIO PIN_CFG(156, GPIO)
+#define GPIO156_KP_I4 PIN_CFG_PULL(156, ALT_A, DOWN)
+#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B)
+#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C)
+
+#define GPIO157_GPIO PIN_CFG(157, GPIO)
+#define GPIO157_KP_O7 PIN_CFG_PULL(157, ALT_A, UP)
+#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B)
+#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C)
+
+#define GPIO158_GPIO PIN_CFG(158, GPIO)
+#define GPIO158_KP_O6 PIN_CFG_PULL(158, ALT_A, UP)
+#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B)
+#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C)
+
+#define GPIO159_GPIO PIN_CFG(159, GPIO)
+#define GPIO159_KP_O5 PIN_CFG_PULL(159, ALT_A, UP)
+#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B)
+#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C)
+
+#define GPIO160_GPIO PIN_CFG(160, GPIO)
+#define GPIO160_KP_O4 PIN_CFG_PULL(160, ALT_A, UP)
+#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B)
+#define GPIO160_NONE PIN_CFG(160, ALT_C)
+
+#define GPIO161_GPIO PIN_CFG(161, GPIO)
+#define GPIO161_KP_I3 PIN_CFG_PULL(161, ALT_A, DOWN)
+#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B)
+#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C)
+
+#define GPIO162_GPIO PIN_CFG(162, GPIO)
+#define GPIO162_KP_I2 PIN_CFG_PULL(162, ALT_A, DOWN)
+#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B)
+#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C)
+
+#define GPIO163_GPIO PIN_CFG(163, GPIO)
+#define GPIO163_KP_I1 PIN_CFG_PULL(163, ALT_A, DOWN)
+#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B)
+#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C)
+
+#define GPIO164_GPIO PIN_CFG(164, GPIO)
+#define GPIO164_KP_I0 PIN_CFG_PULL(164, ALT_A, UP)
+#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B)
+#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C)
+
+#define GPIO165_GPIO PIN_CFG(165, GPIO)
+#define GPIO165_KP_O3 PIN_CFG_PULL(165, ALT_A, UP)
+#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B)
+#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C)
+
+#define GPIO166_GPIO PIN_CFG(166, GPIO)
+#define GPIO166_KP_O2 PIN_CFG_PULL(166, ALT_A, UP)
+#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B)
+#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C)
+
+#define GPIO167_GPIO PIN_CFG(167, GPIO)
+#define GPIO167_KP_O1 PIN_CFG_PULL(167, ALT_A, UP)
+#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B)
+#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C)
+
+#define GPIO168_GPIO PIN_CFG(168, GPIO)
+#define GPIO168_KP_O0 PIN_CFG_PULL(168, ALT_A, UP)
+#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B)
+#define GPIO168_NONE PIN_CFG(168, ALT_C)
+
+#define GPIO169_GPIO PIN_CFG(169, GPIO)
+#define GPIO169_RF_PURn PIN_CFG(169, ALT_A)
+#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B)
+#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C)
+
+#define GPIO170_GPIO PIN_CFG(170, GPIO)
+#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A)
+#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B)
+#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C)
+
+#define GPIO171_GPIO PIN_CFG(171, GPIO)
+#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A)
+#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B)
+#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C)
+
+#define GPIO192_GPIO PIN_CFG(192, GPIO)
+#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A)
+
+#define GPIO193_GPIO PIN_CFG(193, GPIO)
+#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A)
+
+#define GPIO194_GPIO PIN_CFG(194, GPIO)
+#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A)
+
+#define GPIO195_GPIO PIN_CFG(195, GPIO)
+#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A)
+
+#define GPIO196_GPIO PIN_CFG(196, GPIO)
+#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A)
+
+#define GPIO197_GPIO PIN_CFG(197, GPIO)
+#define GPIO197_MC4_DAT3 PIN_CFG(197, ALT_A)
+
+#define GPIO198_GPIO PIN_CFG(198, GPIO)
+#define GPIO198_MC4_DAT2 PIN_CFG(198, ALT_A)
+
+#define GPIO199_GPIO PIN_CFG(199, GPIO)
+#define GPIO199_MC4_DAT1 PIN_CFG(199, ALT_A)
+
+#define GPIO200_GPIO PIN_CFG(200, GPIO)
+#define GPIO200_MC4_DAT0 PIN_CFG(200, ALT_A)
+
+#define GPIO201_GPIO PIN_CFG(201, GPIO)
+#define GPIO201_MC4_CMD PIN_CFG(201, ALT_A)
+
+#define GPIO202_GPIO PIN_CFG(202, GPIO)
+#define GPIO202_MC4_FBCLK PIN_CFG(202, ALT_A)
+#define GPIO202_PWL PIN_CFG(202, ALT_B)
+#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C)
+
+#define GPIO203_GPIO PIN_CFG(203, GPIO)
+#define GPIO203_MC4_CLK PIN_CFG(203, ALT_A)
+
+#define GPIO204_GPIO PIN_CFG(204, GPIO)
+#define GPIO204_MC4_DAT7 PIN_CFG(204, ALT_A)
+
+#define GPIO205_GPIO PIN_CFG(205, GPIO)
+#define GPIO205_MC4_DAT6 PIN_CFG(205, ALT_A)
+
+#define GPIO206_GPIO PIN_CFG(206, GPIO)
+#define GPIO206_MC4_DAT5 PIN_CFG(206, ALT_A)
+
+#define GPIO207_GPIO PIN_CFG(207, GPIO)
+#define GPIO207_MC4_DAT4 PIN_CFG(207, ALT_A)
+
+#define GPIO208_GPIO PIN_CFG(208, GPIO)
+#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A)
+
+#define GPIO209_GPIO PIN_CFG(209, GPIO)
+#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A)
+#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B)
+
+#define GPIO210_GPIO PIN_CFG(210, GPIO)
+#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A)
+
+#define GPIO211_GPIO PIN_CFG(211, GPIO)
+#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A)
+
+#define GPIO212_GPIO PIN_CFG(212, GPIO)
+#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A)
+#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B)
+
+#define GPIO213_GPIO PIN_CFG(213, GPIO)
+#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A)
+#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B)
+
+#define GPIO214_GPIO PIN_CFG(214, GPIO)
+#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A)
+#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B)
+
+#define GPIO215_GPIO PIN_CFG(215, GPIO)
+#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A)
+#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B)
+#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C)
+
+#define GPIO216_GPIO PIN_CFG(216, GPIO)
+#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A)
+#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B)
+#define GPIO216_I2C3_SDA PIN_CFG_PULL(216, ALT_C, UP)
+
+#define GPIO217_GPIO PIN_CFG(217, GPIO)
+#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A)
+#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B)
+#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C)
+
+#define GPIO218_GPIO PIN_CFG(218, GPIO)
+#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A)
+#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B)
+#define GPIO218_I2C3_SCL PIN_CFG_PULL(218, ALT_C, UP)
+
+#define GPIO219_GPIO PIN_CFG(219, GPIO)
+#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A)
+#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B)
+
+#define GPIO220_GPIO PIN_CFG(220, GPIO)
+#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A)
+#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B)
+#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C)
+
+#define GPIO221_GPIO PIN_CFG(221, GPIO)
+#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A)
+#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B)
+
+#define GPIO222_GPIO PIN_CFG(222, GPIO)
+#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A)
+#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B)
+
+#define GPIO223_GPIO PIN_CFG(223, GPIO)
+#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A)
+#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B)
+#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C)
+
+#define GPIO224_GPIO PIN_CFG(224, GPIO)
+#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A)
+#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B)
+#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C)
+
+#define GPIO225_GPIO PIN_CFG(225, GPIO)
+#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A)
+#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B)
+#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C)
+
+#define GPIO226_GPIO PIN_CFG(226, GPIO)
+#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A)
+#define GPIO226_PWL PIN_CFG(226, ALT_B)
+#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C)
+
+#define GPIO227_GPIO PIN_CFG(227, GPIO)
+#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A)
+
+#define GPIO228_GPIO PIN_CFG(228, GPIO)
+#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A)
+
+#define GPIO229_GPIO PIN_CFG(229, GPIO)
+#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A)
+#define GPIO229_PWL PIN_CFG(229, ALT_B)
+#define GPIO229_I2C3_SDA PIN_CFG_PULL(229, ALT_C, UP)
+
+#define GPIO230_GPIO PIN_CFG(230, GPIO)
+#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A)
+#define GPIO230_PWL PIN_CFG(230, ALT_B)
+#define GPIO230_I2C3_SCL PIN_CFG_PULL(230, ALT_C, UP)
+
+#define GPIO256_GPIO PIN_CFG(256, GPIO)
+#define GPIO256_USB_NXT PIN_CFG(256, ALT_A)
+
+#define GPIO257_GPIO PIN_CFG(257, GPIO)
+#define GPIO257_USB_STP PIN_CFG(257, ALT_A)
+
+#define GPIO258_GPIO PIN_CFG(258, GPIO)
+#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A)
+#define GPIO258_NONE PIN_CFG(258, ALT_B)
+#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C)
+
+#define GPIO259_GPIO PIN_CFG(259, GPIO)
+#define GPIO259_USB_DIR PIN_CFG(259, ALT_A)
+
+#define GPIO260_GPIO PIN_CFG(260, GPIO)
+#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A)
+
+#define GPIO261_GPIO PIN_CFG(261, GPIO)
+#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A)
+
+#define GPIO262_GPIO PIN_CFG(262, GPIO)
+#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A)
+
+#define GPIO263_GPIO PIN_CFG(263, GPIO)
+#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A)
+
+#define GPIO264_GPIO PIN_CFG(264, GPIO)
+#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A)
+
+#define GPIO265_GPIO PIN_CFG(265, GPIO)
+#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A)
+
+#define GPIO266_GPIO PIN_CFG(266, GPIO)
+#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A)
+
+#define GPIO267_GPIO PIN_CFG(267, GPIO)
+#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A)
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/db8500_pincfg.h>
+#include <asm/arch/prcmu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+
+#ifdef CONFIG_MMC
+#include "../../../drivers/mmc/arm_pl180_mmci.h"
+#endif
+#include "db8500_pins.h"
+
+/*
+ * Get a global data pointer
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Memory controller register
+ */
+#define DMC_BASE_ADDR 0x80156000
+#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184)
+
+/*
+ * GPIO pin config common for MOP500/HREF boards
+ */
+unsigned long gpio_cfg_common[] = {
+ /* I2C */
+ GPIO147_I2C0_SCL,
+ GPIO148_I2C0_SDA,
+ GPIO16_I2C1_SCL,
+ GPIO17_I2C1_SDA,
+ GPIO10_I2C2_SDA,
+ GPIO11_I2C2_SCL,
+ GPIO229_I2C3_SDA,
+ GPIO230_I2C3_SCL,
+
+ /* SSP0, to AB8500 */
+ GPIO143_SSP0_CLK,
+ GPIO144_SSP0_FRM,
+ GPIO145_SSP0_RXD | PIN_PULL_DOWN,
+ GPIO146_SSP0_TXD,
+
+ /* MMC0 (MicroSD card) */
+ GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH,
+ GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH,
+ GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH,
+ GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH,
+ GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL,
+ GPIO23_MC0_CLK | PIN_OUTPUT_LOW,
+ GPIO24_MC0_CMD | PIN_INPUT_PULLUP,
+ GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP,
+ GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP,
+ GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP,
+ GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP,
+
+ /* MMC4 (On-board eMMC) */
+ GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP,
+ GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP,
+ GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP,
+ GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP,
+ GPIO201_MC4_CMD | PIN_INPUT_PULLUP,
+ GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL,
+ GPIO203_MC4_CLK | PIN_OUTPUT_LOW,
+ GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP,
+ GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP,
+ GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP,
+ GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP,
+
+ /* UART2, console */
+ GPIO29_U2_RXD | PIN_INPUT_PULLUP,
+ GPIO30_U2_TXD | PIN_OUTPUT_HIGH,
+ GPIO31_U2_CTSn | PIN_INPUT_PULLUP,
+ GPIO32_U2_RTSn | PIN_OUTPUT_HIGH,
+
+ /*
+ * USB, pin 256-267 USB, Is probably already setup correctly from
+ * BootROM/boot stages, but we don't trust that and set it up anyway
+ */
+ GPIO256_USB_NXT,
+ GPIO257_USB_STP,
+ GPIO258_USB_XCLK,
+ GPIO259_USB_DIR,
+ GPIO260_USB_DAT7,
+ GPIO261_USB_DAT6,
+ GPIO262_USB_DAT5,
+ GPIO263_USB_DAT4,
+ GPIO264_USB_DAT3,
+ GPIO265_USB_DAT2,
+ GPIO266_USB_DAT1,
+ GPIO267_USB_DAT0,
+};
+
+unsigned long gpio_cfg_snowball[] = {
+ /* MMC0 (MicroSD card) */
+ GPIO217_GPIO | PIN_OUTPUT_HIGH, /* MMC_EN */
+ GPIO218_GPIO | PIN_INPUT_NOPULL, /* MMC_CD */
+ GPIO228_GPIO | PIN_OUTPUT_HIGH, /* SD_SEL */
+
+ /* eMMC */
+ GPIO167_GPIO | PIN_OUTPUT_HIGH, /* RSTn_MLC */
+
+ /* LAN */
+ GPIO131_SM_ADQ8,
+ GPIO132_SM_ADQ9,
+ GPIO133_SM_ADQ10,
+ GPIO134_SM_ADQ11,
+ GPIO135_SM_ADQ12,
+ GPIO136_SM_ADQ13,
+ GPIO137_SM_ADQ14,
+ GPIO138_SM_ADQ15,
+
+ /* RSTn_LAN */
+ GPIO141_GPIO | PIN_OUTPUT_HIGH,
+};
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /*
+ * Setup board (bd) and board-info (bi).
+ * bi_arch_number: Unique id for this board. It will passed in r1 to
+ * Linux startup code and is the machine_id.
+ * bi_boot_params: Where this board expects params.
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_SNOWBALL;
+ gd->bd->bi_boot_params = 0x00000100;
+
+ /* Configure GPIO pins needed by U-boot */
+ db8500_gpio_config_pins(gpio_cfg_common, ARRAY_SIZE(gpio_cfg_common));
+
+ db8500_gpio_config_pins(gpio_cfg_snowball,
+ ARRAY_SIZE(gpio_cfg_snowball));
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->ram_size = gd->bd->bi_dram[0].size =
+ get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+
+ return 0;
+}
+
+static int raise_ab8500_gpio16(void)
+{
+ int ret;
+
+ /* selection */
+ ret = ab8500_read(AB8500_MISC, AB8500_GPIO_SEL2_REG);
+ if (ret < 0)
+ goto out;
+
+ ret |= 0x80;
+ ret = ab8500_write(AB8500_MISC, AB8500_GPIO_SEL2_REG, ret);
+ if (ret < 0)
+ goto out;
+
+ /* direction */
+ ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR2_REG);
+ if (ret < 0)
+ goto out;
+
+ ret |= 0x80;
+ ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR2_REG, ret);
+ if (ret < 0)
+ goto out;
+
+ /* out */
+ ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT2_REG);
+ if (ret < 0)
+ goto out;
+
+ ret |= 0x80;
+ ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT2_REG, ret);
+
+out:
+ return ret;
+}
+
+static int raise_ab8500_gpio26(void)
+{
+ int ret;
+
+ /* selection */
+ ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR4_REG);
+ if (ret < 0)
+ goto out;
+
+ ret |= 0x2;
+ ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR4_REG, ret);
+ if (ret < 0)
+ goto out;
+
+ /* out */
+ ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT4_REG);
+ if (ret < 0)
+ goto out;
+
+ ret |= 0x2;
+ ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT4_REG, ret);
+
+out:
+ return ret;
+}
+
+int board_late_init(void)
+{
+ /* enable 3V3 for LAN controller */
+ if (raise_ab8500_gpio26() >= 0) {
+ /* Turn on FSMC device */
+ writel(0x1, 0x8000f000);
+ writel(0x1, 0x8000f008);
+
+ /* setup FSMC for LAN controler */
+ writel(0x305b, 0x80000000);
+
+ /* run at the highest possible speed */
+ writel(0x01010210, 0x80000004);
+ } else
+ printf("error: can't raise GPIO26\n");
+
+ /* enable 3v6 for GBF chip */
+ if ((raise_ab8500_gpio16() < 0))
+ printf("error: cant' raise GPIO16\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_MMC
+/*
+ * emmc_host_init - initialize the emmc controller.
+ * Configure GPIO settings, set initial clock and power for emmc slot.
+ * Initialize mmc struct and register with mmc framework.
+ */
+static int emmc_host_init(void)
+{
+ struct pl180_mmc_host *host;
+
+ host = malloc(sizeof(struct pl180_mmc_host));
+ if (!host)
+ return -ENOMEM;
+ memset(host, 0, sizeof(*host));
+
+ host->base = (struct sdi_registers *)CFG_EMMC_BASE;
+ host->pwr_init = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON;
+ host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 |
+ SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN;
+ strcpy(host->name, "EMMC");
+ host->caps = MMC_MODE_8BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
+ host->voltages = VOLTAGE_WINDOW_MMC;
+ host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2);
+ host->clock_max = ARM_MCLK / 2;
+ host->clock_in = ARM_MCLK;
+ host->version2 = 1;
+
+ return arm_pl180_mmci_init(host);
+}
+
+/*
+ * mmc_host_init - initialize the external mmc controller.
+ * Configure GPIO settings, set initial clock and power for mmc slot.
+ * Initialize mmc struct and register with mmc framework.
+ */
+static int mmc_host_init(void)
+{
+ struct pl180_mmc_host *host;
+ u32 sdi_u32;
+
+ host = malloc(sizeof(struct pl180_mmc_host));
+ if (!host)
+ return -ENOMEM;
+ memset(host, 0, sizeof(*host));
+
+ host->base = (struct sdi_registers *)CFG_MMC_BASE;
+ sdi_u32 = 0xBF;
+ writel(sdi_u32, &host->base->power);
+ host->pwr_init = 0xBF;
+ host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 |
+ SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN;
+ strcpy(host->name, "MMC");
+ host->caps = MMC_MODE_8BIT;
+ host->b_max = 0;
+ host->voltages = VOLTAGE_WINDOW_SD;
+ host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2);
+ host->clock_max = ARM_MCLK / 2;
+ host->clock_in = ARM_MCLK;
+ host->version2 = 1;
+
+ return arm_pl180_mmci_init(host);
+}
+
+/*
+ * board_mmc_init - initialize all the mmc/sd host controllers.
+ * Called by generic mmc framework.
+ */
+int board_mmc_init(bd_t *bis)
+{
+ int error;
+
+ (void) bis;
+
+ error = emmc_host_init();
+ if (error) {
+ printf("emmc_host_init() %d\n", error);
+ return -1;
+ }
+
+ u8500_mmc_power_init();
+
+ error = mmc_host_init();
+ if (error) {
+ printf("mmc_host_init() %d\n", error);
+ return -1;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_MMC */
CFLAGS += -D__RELEASE -D__STN_8500
LIB = $(obj)lib$(BOARD).o
-COBJS := u8500_href.o gpio.o prcmu.o
+COBJS := u8500_href.o gpio.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
#include <config.h>
#include <common.h>
+#include <malloc.h>
#include <i2c.h>
#include <asm/types.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/prcmu.h>
#ifdef CONFIG_MMC
-#include "prcmu-fw.h"
#include "../../../drivers/mmc/arm_pl180_mmci.h"
#endif
* SGA: Smart Graphic accelerator
* B2R2: Graphic blitter
*/
-#define PRCMU_BASE CFG_PRCMU_BASE /* 0x80157000 for U8500 */
#define PRCM_ARMCLKFIX_MGT_REG (PRCMU_BASE + 0x000)
#define PRCM_ACLK_MGT_REG (PRCMU_BASE + 0x004)
#define PRCM_SVAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x008)
}
#endif
-static unsigned int read_asicid(void)
-{
- unsigned int *address = (void *)U8500_BOOTROM_BASE
- + U8500_BOOTROM_ASIC_ID_OFFSET;
- return readl(address);
-}
-
-int cpu_is_u8500v11(void)
-{
- return read_asicid() == 0x008500A1;
-}
-
/*
* Miscellaneous platform dependent initialisations
*/
};
#ifdef CONFIG_BOARD_LATE_INIT
-#ifdef CONFIG_MMC
-
-#define LDO_VAUX3_MASK 0x3
-#define LDO_VAUX3_ENABLE 0x1
-#define VAUX3_VOLTAGE_2_9V 0xd
-
-#define AB8500_REGU_CTRL2 0x4
-#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A
-#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421
-
-static int hrefplus_mmc_power_init(void)
-{
- int ret;
- int val;
-
- if (!cpu_is_u8500v11())
- return 0;
-
- /*
- * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD
- * card to work. This is done by enabling the regulators in the AB8500
- * via PRCMU I2C transactions.
- *
- * This code is derived from the handling of AB8500_LDO_VAUX3 in
- * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux.
- *
- * Turn off and delay is required to have it work across soft reboots.
- */
-
- ret = prcmu_i2c_read(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG);
- if (ret < 0)
- goto out;
-
- val = ret;
-
- /* Turn off */
- ret = prcmu_i2c_write(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG,
- val & ~LDO_VAUX3_MASK);
- if (ret < 0)
- goto out;
-
- udelay(10 * 1000);
-
- /* Set the voltage to 2.9V */
- ret = prcmu_i2c_write(AB8500_REGU_CTRL2,
- AB8500_REGU_VRF1VAUX3_SEL_REG,
- VAUX3_VOLTAGE_2_9V);
- if (ret < 0)
- goto out;
-
- val = val & ~LDO_VAUX3_MASK;
- val = val | LDO_VAUX3_ENABLE;
-
- /* Turn on the supply */
- ret = prcmu_i2c_write(AB8500_REGU_CTRL2,
- AB8500_REGU_VRF1VAUX3_REGU_REG, val);
-
-out:
- return ret;
-}
-#endif
/*
* called after all initialisation were done, but before the generic
* mmc_initialize().
setenv("board_id", "1");
}
#ifdef CONFIG_MMC
- hrefplus_mmc_power_init();
+ u8500_mmc_power_init();
/*
* config extended GPIO pins for level shifter and
int board_mmc_init(bd_t *bd)
{
+ struct pl180_mmc_host *host;
+
if (u8500_mmci_board_init())
return -ENODEV;
- if (arm_pl180_mmci_init())
- return -ENODEV;
- return 0;
+ host = malloc(sizeof(struct pl180_mmc_host));
+ if (!host)
+ return -ENOMEM;
+ memset(host, 0, sizeof(*host));
+
+ strcpy(host->name, "MMC");
+ host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
+ host->pwr_init = INIT_PWR;
+ host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
+ host->voltages = VOLTAGE_WINDOW_MMC;
+ host->caps = 0;
+ host->clock_in = ARM_MCLK;
+ host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
+ host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
+
+ return arm_pl180_mmci_init(host);
}
#endif
/* Setup of core volatage selection pin to run at 1.4V */
writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */
- gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 15), 1);
+ gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
/* Setup of input daisy chains for SD card pins*/
writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd);
/* Setup of digital output for USB power and OC */
writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */
- gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 28), 1);
+ gpio_direction_output(IMX_GPIO_NR(1, 28), 1);
writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */
- gpio_direction_input(MXC_GPIO_PORT_TO_NUM(1, 18));
+ gpio_direction_input(IMX_GPIO_NR(1, 18));
/* Setup of digital output control pins */
writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */
writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */
/* Switch both output drivers off */
- gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 7), 0);
- gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 6), 0);
+ gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
+ gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
/* Setup of key input pin GPIO2[29]*/
writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0);
writel(0, &padctl->pad_kpp_row0); /* Key pull up off */
- gpio_direction_input(MXC_GPIO_PORT_TO_NUM(2, 29));
+ gpio_direction_input(IMX_GPIO_NR(2, 29));
/* Setup of status LED outputs */
writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */
writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */
/* Switch both LEDs off */
- gpio_direction_output(MXC_GPIO_PORT_TO_NUM(4, 21), 0);
- gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 29), 0);
+ gpio_direction_output(IMX_GPIO_NR(4, 21), 0);
+ gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
/* Setup of CAN1 and CAN2 signals */
writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */
writel(gpio_mux_mode2, &muxctl->pad_uart2_cts);
/* assert PHY reset (low) */
- gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 16), 0);
+ gpio_direction_output(IMX_GPIO_NR(3, 16), 0);
udelay(5000);
/* deassert PHY reset */
- gpio_set_value(MXC_GPIO_PORT_TO_NUM(3, 16), 1);
+ gpio_set_value(IMX_GPIO_NR(3, 16), 1);
udelay(5000);
#endif
e = getenv("gs_base_board");
if (e != NULL) {
if (strcmp(e, "G283") == 0) {
- int key = gpio_get_value(MXC_GPIO_PORT_TO_NUM(2, 29));
+ int key = gpio_get_value(IMX_GPIO_NR(2, 29));
if (key) {
/* Switch on both LEDs to inidcate boot mode */
- gpio_set_value(MXC_GPIO_PORT_TO_NUM(1, 29), 0);
- gpio_set_value(MXC_GPIO_PORT_TO_NUM(4, 21), 0);
+ gpio_set_value(IMX_GPIO_NR(1, 29), 0);
+ gpio_set_value(IMX_GPIO_NR(4, 21), 0);
setenv("preboot", "run gs_slow_boot");
} else
--- /dev/null
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2012
+# Markus Hubig <mhubig@imko.de>
+# IMKO GmbH <www.imko.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += stamp9g20.o
+COBJS-y += led.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ * (C) Copyright 2009
+ * Eric Benard <eric@eukrea.com>
+ *
+ * (C) Copyright 2012
+ * Markus Hubig <mhubig@imko.de>
+ * IMKO GmbH <www.imko.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pmc.h>
+#include <status_led.h>
+
+static unsigned int saved_state[3] = {STATUS_LED_OFF,
+ STATUS_LED_OFF, STATUS_LED_OFF};
+
+void coloured_LED_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable the clock */
+ writel(ATMEL_ID_PIOC, &pmc->pcer);
+
+ at91_set_gpio_output(CONFIG_RED_LED, 1);
+ at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+ at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+
+ at91_set_gpio_value(CONFIG_RED_LED, 0);
+ at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+ at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
+}
+
+void red_led_on(void)
+{
+ at91_set_gpio_value(CONFIG_RED_LED, 1);
+ saved_state[STATUS_LED_RED] = STATUS_LED_ON;
+}
+
+void red_led_off(void)
+{
+ at91_set_gpio_value(CONFIG_RED_LED, 0);
+ saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
+}
+
+void green_led_on(void)
+{
+ at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+ saved_state[STATUS_LED_GREEN] = STATUS_LED_ON;
+}
+
+void green_led_off(void)
+{
+ at91_set_gpio_value(CONFIG_GREEN_LED, 0);
+ saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF;
+}
+
+void yellow_led_on(void)
+{
+ at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+ saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON;
+}
+
+void yellow_led_off(void)
+{
+ at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
+ saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF;
+}
+
+void __led_init(led_id_t mask, int state)
+{
+ __led_set(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+ if (STATUS_LED_RED == mask) {
+ if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
+ red_led_off();
+ else
+ red_led_on();
+
+ } else if (STATUS_LED_GREEN == mask) {
+ if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
+ green_led_off();
+ else
+ green_led_on();
+
+ } else if (STATUS_LED_YELLOW == mask) {
+ if (STATUS_LED_ON == saved_state[STATUS_LED_YELLOW])
+ yellow_led_off();
+ else
+ yellow_led_on();
+ }
+}
+
+void __led_set(led_id_t mask, int state)
+{
+ if (STATUS_LED_RED == mask) {
+ if (STATUS_LED_ON == state)
+ red_led_on();
+ else
+ red_led_off();
+
+ } else if (STATUS_LED_GREEN == mask) {
+ if (STATUS_LED_ON == state)
+ green_led_on();
+ else
+ green_led_off();
+
+ } else if (STATUS_LED_YELLOW == mask) {
+ if (STATUS_LED_ON == state)
+ yellow_led_on();
+ else
+ yellow_led_off();
+ }
+}
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Achim Ehrlich <aehrlich@taskit.de>
+ * taskit GmbH <www.taskit.de>
+ *
+ * (C) Copyright 2012-
+ * Markus Hubig <mhubig@imko.de>
+ * IMKO GmbH <www.imko.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <watchdog.h>
+
+#ifdef CONFIG_MACB
+# include <net.h>
+# include <netdev.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void stamp9G20_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ /* Assign CS3 to NAND/SmartMedia Interface */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+
+#ifdef CONFIG_MACB
+static void stamp9G20_macb_hw_init(void)
+{
+ struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+ struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
+ unsigned long erstl;
+
+ /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
+ at91_set_gpio_output(AT91_PIN_PA26, 0);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA17) => PHY normal mode (not Test mode)
+ * ERX0 (PA14) => PHY ADDR0
+ * ERX1 (PA15) => PHY ADDR1
+ * ERX2 (PA25) => PHY ADDR2
+ * ERX3 (PA26) => PHY ADDR3
+ * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA18) |
+ pin_to_mask(AT91_PIN_PA28),
+ &pioa->pudr);
+
+ erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
+
+ /* Need to reset PHY -> 500ms reset */
+ writel(AT91_RSTC_KEY | (AT91_RSTC_MR_ERSTL(13) &
+ ~AT91_RSTC_MR_URSTEN), &rstc->mr);
+ writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
+
+ /* Wait for end of hardware reset */
+ unsigned long start = get_timer(0);
+ unsigned long timeout = 1000; /* 1000ms */
+
+ while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
+
+ /* avoid shutdown by watchdog */
+ WATCHDOG_RESET();
+ mdelay(10);
+
+ /* timeout for not getting stuck in an endless loop */
+ if (get_timer(start) >= timeout) {
+ puts("*** ERROR: Timeout waiting for PHY reset!\n");
+ break;
+ };
+ };
+
+ /* Restore NRST value */
+ writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
+ &rstc->mr);
+
+ /* Re-enable pull-up */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA18) |
+ pin_to_mask(AT91_PIN_PA28),
+ &pioa->puer);
+
+ /* Initialize EMAC=MACB hardware */
+ at91_macb_hw_init();
+}
+#endif /* CONFIG_MACB */
+
+int board_early_init_f(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable clocks for all PIOs */
+ writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+ (1 << ATMEL_ID_PIOC), &pmc->pcer);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ /* Enable the serial interface */
+ at91_set_gpio_output(AT91_PIN_PC9, 1);
+ at91_seriald_hw_init();
+
+ stamp9G20_nand_hw_init();
+#ifdef CONFIG_MACB
+ stamp9G20_macb_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#ifdef CONFIG_MACB
+int board_eth_init(bd_t *bis)
+{
+ return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
+}
+#endif /* CONFIG_MACB */
LIB = $(obj)lib$(BOARD).o
-COBJS := evm.o mux.o
+ifdef CONFIG_SPL_BUILD
+COBJS := mux.o
+endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
+++ /dev/null
-/*
- * evm.c
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/common_def.h>
-#include <serial.h>
-#include <i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_RESET (0x1 << 1)
-#define UART_CLK_RUNNING_MASK 0x1
-#define UART_SMART_IDLE_EN (0x1 << 0x3)
-
-/*
- * Basic board specific setup
- */
-int board_init(void)
-{
- enable_uart0_pin_mux();
-
-#ifdef CONFIG_I2C
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
- gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
-
- return 0;
-}
* GNU General Public License for more details.
*/
-#include <config.h>
-#include <asm/arch/common_def.h>
+#include <common.h>
+#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
+#include <i2c.h>
#define MUX_CFG(value, offset) \
__raw_writel(value, (CTRL_BASE + offset));
{-1},
};
-#ifdef CONFIG_MMC
static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
{-1},
};
-#endif
+
+static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
+ {-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
+ {-1},
+};
static struct module_pin_mux i2c0_pin_mux[] = {
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
{-1},
};
+static struct module_pin_mux i2c1_pin_mux[] = {
+ {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux spi0_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
+ {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
+ PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
+ {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
+ {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
+ PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
+ {-1},
+};
+
+static struct module_pin_mux gpio0_7_pin_mux[] = {
+ {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
+ {-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
+ {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
+ {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
+ {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
+ {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
+ {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
+ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
+ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
+ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
+ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
+ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
+ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
+ {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
+ {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
+ {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
+ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
+ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
+ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
+ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
+ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
/*
* Configure the pin mux for the module
*/
configure_module_pin_mux(uart0_pin_mux);
}
-#ifdef CONFIG_MMC
-void enable_mmc0_pin_mux(void)
-{
- configure_module_pin_mux(mmc0_pin_mux);
-}
-#endif
void enable_i2c0_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
}
+
+/*
+ * The AM335x GP EVM, if daughter card(s) are connected, can have 8
+ * different profiles. These profiles determine what peripherals are
+ * valid and need pinmux to be configured.
+ */
+#define PROFILE_NONE 0x0
+#define PROFILE_0 (1 << 0)
+#define PROFILE_1 (1 << 1)
+#define PROFILE_2 (1 << 2)
+#define PROFILE_3 (1 << 3)
+#define PROFILE_4 (1 << 4)
+#define PROFILE_5 (1 << 5)
+#define PROFILE_6 (1 << 6)
+#define PROFILE_7 (1 << 7)
+#define PROFILE_MASK 0x7
+#define PROFILE_ALL 0xFF
+
+/* CPLD registers */
+#define I2C_CPLD_ADDR 0x35
+#define CFG_REG 0x10
+
+static unsigned short detect_daughter_board_profile(void)
+{
+ unsigned short val;
+
+ if (i2c_probe(I2C_CPLD_ADDR))
+ return PROFILE_NONE;
+
+ if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
+ return PROFILE_NONE;
+
+ return (1 << (val & PROFILE_MASK));
+}
+
+void enable_board_pin_mux(struct am335x_baseboard_id *header)
+{
+ /* Do board-specific muxes. */
+ if (!strncmp(header->name, "A335BONE", HDR_NAME_LEN)) {
+ /* Beaglebone pinmux */
+ configure_module_pin_mux(i2c1_pin_mux);
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(mmc1_pin_mux);
+ } else if (!strncmp(header->config, "SKU#01", 6)) {
+ /* General Purpose EVM */
+ unsigned short profile = detect_daughter_board_profile();
+ configure_module_pin_mux(rgmii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+ /* In profile #2 i2c1 and spi0 conflict. */
+ if (profile & ~PROFILE_2)
+ configure_module_pin_mux(i2c1_pin_mux);
+ else if (profile == PROFILE_2) {
+ configure_module_pin_mux(mmc1_pin_mux);
+ configure_module_pin_mux(spi0_pin_mux);
+ }
+ } else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) {
+ /* Starter Kit EVM */
+ configure_module_pin_mux(i2c1_pin_mux);
+ configure_module_pin_mux(gpio0_7_pin_mux);
+ configure_module_pin_mux(rgmii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux_sk_evm);
+ } else {
+ puts("Unknown board, cannot configure pinmux.");
+ hang();
+ }
+}
#include <asm/ehci-omap.h>
#endif
-#define pr_debug(fmt, args...) debug(fmt, ##args)
-
#define TWL4030_I2C_BUS 0
#define EXPANSION_EEPROM_I2C_BUS 1
#define EXPANSION_EEPROM_I2C_ADDRESS 0x50
* GPIO173, GPIO172, GPIO171: 1 0 1 => C4
* GPIO173, GPIO172, GPIO171: 0 0 0 => xM
*/
-int get_board_revision(void)
+static int get_board_revision(void)
{
int revision;
* bus 1 for the availability of an AT24C01B serial EEPROM.
* returns the device_vendor field from the EEPROM
*/
-unsigned int get_expansion_id(void)
+static unsigned int get_expansion_id(void)
{
i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
return expansion_config.device_vendor;
}
+#ifdef CONFIG_VIDEO_OMAP3
/*
* Configure DSS to display background color on DVID
* Configure VENC to display color bar on S-Video
*/
-void beagle_display_init(void)
+static void beagle_display_init(void)
{
omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH);
switch (get_board_revision()) {
break;
}
}
+#endif
/*
* Routine: misc_init_r
dieid_num_r();
+#ifdef CONFIG_VIDEO_OMAP3
beagle_dvi_pup();
beagle_display_init();
omap3_dss_enable();
+#endif
return 0;
}
}
struct fsl_esdhc_cfg esdhc_cfg[1] = {
- {MMC_SDHC1_BASE_ADDR, 1},
+ {MMC_SDHC1_BASE_ADDR},
};
int get_mmc_getcd(u8 *cd, struct mmc *mmc)
udelay(2000);
#endif
- setenv("stdout", "serial");
-
return 0;
}
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
int checkboard(void)
{
puts("Board: TTControl Vision II CPU V\n");
apollon arm arm1136 apollon - omap24xx
omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
+rpi_b arm arm1176 rpi_b raspberrypi bcm2835
integratorap_cm720t arm arm720t integrator armltd - integratorap:CM720T
integratorap_cm920t arm arm920t integrator armltd - integratorap:CM920T
integratorcp_cm920t arm arm920t integrator armltd - integratorcp:CM920T
at91sam9m10g45ek_nandflash arm arm926ejs at91sam9m10g45ek atmel at91 at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH
at91sam9rlek_dataflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH
at91sam9rlek_nandflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH
+at91sam9x5ek_nandflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH
+at91sam9x5ek_spiflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH
at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0
at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1
at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH
pm9261 arm arm926ejs pm9261 ronetix at91 pm9261:AT91SAM9261
pm9263 arm arm926ejs pm9263 ronetix at91 pm9263:AT91SAM9263
pm9g45 arm arm926ejs pm9g45 ronetix at91 pm9g45:AT91SAM9G45
+portuxg20 arm arm926ejs stamp9g20 taskit at91 stamp9g20:AT91SAM9G20,PORTUXG20
+stamp9g20 arm arm926ejs stamp9g20 taskit at91 stamp9g20:AT91SAM9G20
cam_enc_4xx arm arm926ejs cam_enc_4xx ait davinci cam_enc_4xx
da830evm arm arm926ejs da8xxevm davinci davinci
da850_am18xxevm arm arm926ejs da8xxevm davinci davinci da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50
da850evm arm arm926ejs da8xxevm davinci davinci da850evm:MAC_ADDR_IN_SPIFLASH
+da850evm_direct_nor arm arm926ejs da8xxevm davinci davinci da850evm:MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT
davinci_dm355evm arm arm926ejs dm355evm davinci davinci
davinci_dm355leopard arm arm926ejs dm355leopard davinci davinci
davinci_dm365evm arm arm926ejs dm365evm davinci davinci
zmx25 arm arm926ejs zmx25 syteco mx25
imx27lite arm arm926ejs imx27lite logicpd mx27
magnesium arm arm926ejs imx27lite logicpd mx27
-m28evk arm arm926ejs - denx mx28
-mx28evk arm arm926ejs - freescale mx28
+apx4devkit arm arm926ejs apx4devkit bluegiga mxs apx4devkit
+m28evk arm arm926ejs m28evk denx mxs m28evk
+mx28evk arm arm926ejs mx28evk freescale mxs mx28evk
+sc_sps_1 arm arm926ejs sc_sps_1 schulercontrol mxs
nhk8815 arm arm926ejs nhk8815 st nomadik
nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND
omap5912osk arm arm926ejs - ti omap
ca9x4_ct_vxp arm armv7 vexpress armltd
am335x_evm arm armv7 am335x ti am33xx
highbank arm armv7 highbank - highbank
-efikamx arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/efikamx/imximage_mx.cfg
-efikasb arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/efikamx/imximage_sb.cfg
+mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
+mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
mx53ard arm armv7 mx53ard freescale mx5 mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg
mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg
omap3_overo arm armv7 overo - omap3
omap3_pandora arm armv7 pandora - omap3
dig297 arm armv7 dig297 comelit omap3
-igep0020 arm armv7 igep0020 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020
-igep0030 arm armv7 igep0030 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030
+igep0020 arm armv7 igep0020 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND
+igep0020_nand arm armv7 igep0020 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND
+igep0030 arm armv7 igep0030 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND
+igep0030_nand arm armv7 igep0030 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND
am3517_evm arm armv7 am3517evm logicpd omap3
mt_ventoux arm armv7 mt_ventoux teejet omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
smdk5250 arm armv7 smdk5250 samsung exynos
smdkv310 arm armv7 smdkv310 samsung exynos
trats arm armv7 trats samsung exynos
-harmony arm armv7 harmony nvidia tegra2
-seaboard arm armv7 seaboard nvidia tegra2
-ventana arm armv7 ventana nvidia tegra2
-whistler arm armv7 whistler nvidia tegra2
+harmony arm armv7:arm720t harmony nvidia tegra20
+seaboard arm armv7:arm720t seaboard nvidia tegra20
+ventana arm armv7:arm720t ventana nvidia tegra20
+whistler arm armv7:arm720t whistler nvidia tegra20
u8500_href arm armv7 u8500 st-ericsson u8500
+snowball arm armv7 snowball st-ericsson u8500
actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2
actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB
actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8
zipitz2 arm pxa
colibri_pxa270 arm pxa - toradex
jornada arm sa1100
-plutux arm armv7 plutux avionic-design tegra2
-medcom arm armv7 medcom avionic-design tegra2
-tec arm armv7 tec avionic-design tegra2
-paz00 arm armv7 paz00 compal tegra2
-trimslice arm armv7 trimslice compulab tegra2
+plutux arm armv7:arm720t plutux avionic-design tegra20
+medcom arm armv7:arm720t medcom avionic-design tegra20
+tec arm armv7:arm720t tec avionic-design tegra20
+paz00 arm armv7:arm720t paz00 compal tegra20
+trimslice arm armv7:arm720t trimslice compulab tegra20
atngw100 avr32 at32ap - atmel at32ap700x
atstk1002 avr32 at32ap atstk1000 atmel at32ap700x
atstk1003 avr32 at32ap atstk1000 atmel at32ap700x
# Include the make variables (CC, etc...)
#
AS = $(CROSS_COMPILE)as
-LD = $(CROSS_COMPILE)ld
+
+# Always use GNU ld
+LD = $(shell if $(CROSS_COMPILE)ld.bfd -v > /dev/null 2>&1; \
+ then echo "$(CROSS_COMPILE)ld.bfd"; else echo "$(CROSS_COMPILE)ld"; fi;)
+
CC = $(CROSS_COMPILE)gcc
CPP = $(CC) -E
AR = $(CROSS_COMPILE)ar
--- /dev/null
+How to enable PMECC(Programmable Multibit ECC) for nand on Atmel SoCs
+-----------------------------------------------------------
+2012-08-22 Josh Wu <josh.wu@atmel.com>
+
+The Programmable Multibit ECC (PMECC) controller is a programmable binary
+BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller
+can be used to support both SLC and MLC NAND Flash devices. It supports to
+generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector (512 or
+1024 bytes) of data.
+
+Following Atmel AT91 products support PMECC.
+- AT91SAM9X25, X35, G25, G15, G35 (tested)
+- AT91SAM9N12 (not tested, Should work)
+
+As soon as your nand flash software ECC works, you can enable PMECC.
+
+To use PMECC in this driver, the user needs to set:
+ 1. the PMECC correction error bits capability: CONFIG_PMECC_CAP.
+ It can be 2, 4, 8, 12 or 24.
+ 2. The PMECC sector size: CONFIG_PMECC_SECTOR_SIZE.
+ It only can be 512 or 1024.
+ 3. The PMECC index lookup table's offsets in ROM code: CONFIG_PMECC_INDEX_TABLE_OFFSET.
+ In the chip datasheet section "Boot Stragegies", you can find
+ two Galois Field Table in the ROM code. One table is for 512-bytes
+ sector. Another is for 1024-byte sector. Each Galois Field includes
+ two sub-table: indext table & alpha table.
+ In the beginning of each Galois Field Table is the index table,
+ Alpha table is in the following.
+ So the index table's offset is same as the Galois Field Table.
+
+ Please set CONFIG_PMECC_INDEX_TABLE_OFFSET correctly according the
+ Galois Field Table's offset base on the sector size you used.
+
+Take AT91SAM9X5EK as an example, the board definition file likes:
+
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC 1
+#define CONFIG_ATMEL_NAND_HW_PMECC 1
+#define CONFIG_PMECC_CAP 2
+#define CONFIG_PMECC_SECTOR_SIZE 512
+#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000
+
+NOTE: If you use 1024 as the sector size, then need set 0x10000 as the
+ CONFIG_PMECC_INDEX_TABLE_OFFSET
Files of the M28/M28EVK port
----------------------------
-arch/arm/cpu/arm926ejs/mx28/ - The CPU support code for the Freescale i.MX28
-arch/arm/include/asm/arch-mx28/ - Header files for the Freescale i.MX28
+arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28
+arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28
board/denx/m28evk/ - M28EVK board specific files
include/configs/m28evk.h - M28EVK configuration file
Files of the MX28EVK port
--------------------------
-arch/arm/cpu/arm926ejs/mx28/ - The CPU support code for the Freescale i.MX28
-arch/arm/include/asm/arch-mx28/ - Header files for the Freescale i.MX28
+arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28
+arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28
board/freescale/mx28evk/ - MX28EVK board specific files
include/configs/mx28evk.h - MX28EVK configuration file
# Maintainer aliases. Use the same alias here as patchwork to keep
# things simple and easy to look up/coordinate.
alias aaribaud Albert Aribaud <albert.u.boot@aribaud.net>
+alias abiessmann Andreas Bießmann <andreas.devel@googlemail.com>
alias afleming Andy Fleming <afleming@freescale.com>
alias ag Anatolij Gustschin <agust@denx.de>
alias galak Kumar Gala <galak@kernel.crashing.org>
alias arches arch
alias arm uboot, aaribaud
-alias at91 uboot, reinhardm
+alias at91 uboot, abiessmann
alias davinci ti
alias imx uboot, sbabic
alias kirkwood uboot, prafulla
alias samsung uboot, prom
alias tegra uboot, Simon Glass <sjg@chromium.org>, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com>
alias tegra2 tegra
-alias ti uboot, Sandeep Paulraj <s-paulraj@ti.com>, Tom Rini <trini@ti.com>
+alias ti uboot, Tom Rini <trini@ti.com>
-alias avr32 uboot, Andreas Bießmann <andreas.devel@googlemail.com>
+alias avr32 uboot, abiessmann
alias bfin uboot, vapier
alias blackfin bfin
*/
static int mxs_dma_read_semaphore(int channel)
{
- struct mx28_apbh_regs *apbh_regs =
- (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ struct mxs_apbh_regs *apbh_regs =
+ (struct mxs_apbh_regs *)MXS_APBH_BASE;
uint32_t tmp;
int ret;
*/
static int mxs_dma_enable(int channel)
{
- struct mx28_apbh_regs *apbh_regs =
- (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ struct mxs_apbh_regs *apbh_regs =
+ (struct mxs_apbh_regs *)MXS_APBH_BASE;
unsigned int sem;
struct mxs_dma_chan *pchan;
struct mxs_dma_desc *pdesc;
static int mxs_dma_disable(int channel)
{
struct mxs_dma_chan *pchan;
- struct mx28_apbh_regs *apbh_regs =
- (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ struct mxs_apbh_regs *apbh_regs =
+ (struct mxs_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(channel);
*/
static int mxs_dma_reset(int channel)
{
- struct mx28_apbh_regs *apbh_regs =
- (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ struct mxs_apbh_regs *apbh_regs =
+ (struct mxs_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(channel);
*/
static int mxs_dma_enable_irq(int channel, int enable)
{
- struct mx28_apbh_regs *apbh_regs =
- (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ struct mxs_apbh_regs *apbh_regs =
+ (struct mxs_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(channel);
*/
static int mxs_dma_ack_irq(int channel)
{
- struct mx28_apbh_regs *apbh_regs =
- (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ struct mxs_apbh_regs *apbh_regs =
+ (struct mxs_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(channel);
*/
static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
{
- struct mx28_apbh_regs *apbh_regs =
- (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ struct mxs_apbh_regs *apbh_regs =
+ (struct mxs_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(chan);
if (ret)
return ret;
- if (mx28_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,
+ if (mxs_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,
1 << chan, timeout)) {
ret = -ETIMEDOUT;
mxs_dma_reset(chan);
*/
int mxs_dma_go(int chan)
{
- uint32_t timeout = 10000;
+ uint32_t timeout = 10000000;
int ret;
LIST_HEAD(tmp_desc_list);
*/
void mxs_dma_init(void)
{
- struct mx28_apbh_regs *apbh_regs =
- (struct mx28_apbh_regs *)MXS_APBH_BASE;
+ struct mxs_apbh_regs *apbh_regs =
+ (struct mxs_apbh_regs *)MXS_APBH_BASE;
- mx28_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
+ mxs_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
#ifdef CONFIG_APBH_DMA_BURST8
writel(APBH_CTRL0_AHB_BURST8_EN,
COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
COBJS-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o
+COBJS-$(CONFIG_OMAP_GPIO) += omap_gpio.o
+COBJS-$(CONFIG_DB8500_GPIO) += db8500_gpio.o
+COBJS-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * Copyright (C) 2012 Vikram Narayananan
+ * <vikram186@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+inline int gpio_is_valid(unsigned gpio)
+{
+ return (gpio < BCM2835_GPIO_COUNT);
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+ return !gpio_is_valid(gpio);
+}
+
+int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ struct bcm2835_gpio_regs *reg =
+ (struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE;
+ unsigned val;
+
+ val = readl(®->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
+ val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio));
+ val |= (BCM2835_GPIO_INPUT << BCM2835_GPIO_FSEL_SHIFT(gpio));
+ writel(val, ®->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
+
+ return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ struct bcm2835_gpio_regs *reg =
+ (struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE;
+ unsigned val;
+
+ gpio_set_value(gpio, value);
+
+ val = readl(®->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
+ val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio));
+ val |= (BCM2835_GPIO_OUTPUT << BCM2835_GPIO_FSEL_SHIFT(gpio));
+ writel(val, ®->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
+
+ return 0;
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ struct bcm2835_gpio_regs *reg =
+ (struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE;
+ unsigned val;
+
+ val = readl(®->gplev[BCM2835_GPIO_COMMON_BANK(gpio)]);
+
+ return (val >> BCM2835_GPIO_COMMON_SHIFT(gpio)) & 0x1;
+}
+
+int gpio_set_value(unsigned gpio, int value)
+{
+ struct bcm2835_gpio_regs *reg =
+ (struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE;
+ u32 *output_reg = value ? reg->gpset : reg->gpclr;
+
+ writel(1 << BCM2835_GPIO_COMMON_SHIFT(gpio),
+ &output_reg[BCM2835_GPIO_COMMON_BANK(gpio)]);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
+ * The purpose is that GPIO config found in kernel should work by simply
+ * copy-paste it to U-boot.
+ *
+ * Original Linux authors:
+ * Copyright (C) 2008,2009 STMicroelectronics
+ * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
+ * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
+ *
+ * Ported to U-boot by:
+ * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include <asm/arch/db8500_gpio.h>
+#include <asm/arch/db8500_pincfg.h>
+#include <linux/compiler.h>
+
+#define IO_ADDR(x) (void *) (x)
+
+/*
+ * The GPIO module in the db8500 Systems-on-Chip is an
+ * AMBA device, managing 32 pins and alternate functions. The logic block
+ * is currently only used in the db8500.
+ */
+
+#define GPIO_TOTAL_PINS 268
+#define GPIO_PINS_PER_BLOCK 32
+#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1)
+#define GPIO_BLOCK(pin) (((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1)
+#define GPIO_PIN_WITHIN_BLOCK(pin) ((pin)%(GPIO_PINS_PER_BLOCK))
+
+/* Register in the logic block */
+#define DB8500_GPIO_DAT 0x00
+#define DB8500_GPIO_DATS 0x04
+#define DB8500_GPIO_DATC 0x08
+#define DB8500_GPIO_PDIS 0x0c
+#define DB8500_GPIO_DIR 0x10
+#define DB8500_GPIO_DIRS 0x14
+#define DB8500_GPIO_DIRC 0x18
+#define DB8500_GPIO_SLPC 0x1c
+#define DB8500_GPIO_AFSLA 0x20
+#define DB8500_GPIO_AFSLB 0x24
+
+#define DB8500_GPIO_RIMSC 0x40
+#define DB8500_GPIO_FIMSC 0x44
+#define DB8500_GPIO_IS 0x48
+#define DB8500_GPIO_IC 0x4c
+#define DB8500_GPIO_RWIMSC 0x50
+#define DB8500_GPIO_FWIMSC 0x54
+#define DB8500_GPIO_WKS 0x58
+
+static void __iomem *get_gpio_addr(unsigned gpio)
+{
+ /* Our list of GPIO chips */
+ static void __iomem *gpio_addrs[GPIO_BLOCKS_COUNT] = {
+ IO_ADDR(CFG_GPIO_0_BASE),
+ IO_ADDR(CFG_GPIO_1_BASE),
+ IO_ADDR(CFG_GPIO_2_BASE),
+ IO_ADDR(CFG_GPIO_3_BASE),
+ IO_ADDR(CFG_GPIO_4_BASE),
+ IO_ADDR(CFG_GPIO_5_BASE),
+ IO_ADDR(CFG_GPIO_6_BASE),
+ IO_ADDR(CFG_GPIO_7_BASE),
+ IO_ADDR(CFG_GPIO_8_BASE)
+ };
+
+ return gpio_addrs[GPIO_BLOCK(gpio)];
+}
+
+static unsigned get_gpio_offset(unsigned gpio)
+{
+ return GPIO_PIN_WITHIN_BLOCK(gpio);
+}
+
+/* Can only be called from config_pin. Don't configure alt-mode directly */
+static void gpio_set_mode(unsigned gpio, enum db8500_gpio_alt mode)
+{
+ void __iomem *addr = get_gpio_addr(gpio);
+ unsigned offset = get_gpio_offset(gpio);
+ u32 bit = 1 << offset;
+ u32 afunc, bfunc;
+
+ afunc = readl(addr + DB8500_GPIO_AFSLA) & ~bit;
+ bfunc = readl(addr + DB8500_GPIO_AFSLB) & ~bit;
+ if (mode & DB8500_GPIO_ALT_A)
+ afunc |= bit;
+ if (mode & DB8500_GPIO_ALT_B)
+ bfunc |= bit;
+ writel(afunc, addr + DB8500_GPIO_AFSLA);
+ writel(bfunc, addr + DB8500_GPIO_AFSLB);
+}
+
+/**
+ * db8500_gpio_set_pull() - enable/disable pull up/down on a gpio
+ * @gpio: pin number
+ * @pull: one of DB8500_GPIO_PULL_DOWN, DB8500_GPIO_PULL_UP,
+ * and DB8500_GPIO_PULL_NONE
+ *
+ * Enables/disables pull up/down on a specified pin. This only takes effect if
+ * the pin is configured as an input (either explicitly or by the alternate
+ * function).
+ *
+ * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
+ * configured as an input. Otherwise, due to the way the controller registers
+ * work, this function will change the value output on the pin.
+ */
+void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull)
+{
+ void __iomem *addr = get_gpio_addr(gpio);
+ unsigned offset = get_gpio_offset(gpio);
+ u32 bit = 1 << offset;
+ u32 pdis;
+
+ pdis = readl(addr + DB8500_GPIO_PDIS);
+ if (pull == DB8500_GPIO_PULL_NONE)
+ pdis |= bit;
+ else
+ pdis &= ~bit;
+ writel(pdis, addr + DB8500_GPIO_PDIS);
+
+ if (pull == DB8500_GPIO_PULL_UP)
+ writel(bit, addr + DB8500_GPIO_DATS);
+ else if (pull == DB8500_GPIO_PULL_DOWN)
+ writel(bit, addr + DB8500_GPIO_DATC);
+}
+
+void db8500_gpio_make_input(unsigned gpio)
+{
+ void __iomem *addr = get_gpio_addr(gpio);
+ unsigned offset = get_gpio_offset(gpio);
+
+ writel(1 << offset, addr + DB8500_GPIO_DIRC);
+}
+
+int db8500_gpio_get_input(unsigned gpio)
+{
+ void __iomem *addr = get_gpio_addr(gpio);
+ unsigned offset = get_gpio_offset(gpio);
+ u32 bit = 1 << offset;
+
+ printf("db8500_gpio_get_input gpio=%u addr=%p offset=%u bit=%#x\n",
+ gpio, addr, offset, bit);
+
+ return (readl(addr + DB8500_GPIO_DAT) & bit) != 0;
+}
+
+void db8500_gpio_make_output(unsigned gpio, int val)
+{
+ void __iomem *addr = get_gpio_addr(gpio);
+ unsigned offset = get_gpio_offset(gpio);
+
+ writel(1 << offset, addr + DB8500_GPIO_DIRS);
+ db8500_gpio_set_output(gpio, val);
+}
+
+void db8500_gpio_set_output(unsigned gpio, int val)
+{
+ void __iomem *addr = get_gpio_addr(gpio);
+ unsigned offset = get_gpio_offset(gpio);
+
+ if (val)
+ writel(1 << offset, addr + DB8500_GPIO_DATS);
+ else
+ writel(1 << offset, addr + DB8500_GPIO_DATC);
+}
+
+/**
+ * config_pin - configure a pin's mux attributes
+ * @cfg: pin confguration
+ *
+ * Configures a pin's mode (alternate function or GPIO), its pull up status,
+ * and its sleep mode based on the specified configuration. The @cfg is
+ * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
+ * are constructed using, and can be further enhanced with, the macros in
+ * plat/pincfg.h.
+ *
+ * If a pin's mode is set to GPIO, it is configured as an input to avoid
+ * side-effects. The gpio can be manipulated later using standard GPIO API
+ * calls.
+ */
+static void config_pin(unsigned long cfg)
+{
+ int pin = PIN_NUM(cfg);
+ int pull = PIN_PULL(cfg);
+ int af = PIN_ALT(cfg);
+ int output = PIN_DIR(cfg);
+ int val = PIN_VAL(cfg);
+
+ if (output)
+ db8500_gpio_make_output(pin, val);
+ else {
+ db8500_gpio_make_input(pin);
+ db8500_gpio_set_pull(pin, pull);
+ }
+
+ gpio_set_mode(pin, af);
+}
+
+/**
+ * db8500_config_pins - configure several pins at once
+ * @cfgs: array of pin configurations
+ * @num: number of elments in the array
+ *
+ * Configures several pins using config_pin(). Refer to that function for
+ * further information.
+ */
+void db8500_gpio_config_pins(unsigned long *cfgs, size_t num)
+{
+ size_t i;
+
+ for (i = 0; i < num; i++)
+ config_pin(cfgs[i]);
+}
[0] = GPIO1_BASE_ADDR,
[1] = GPIO2_BASE_ADDR,
[2] = GPIO3_BASE_ADDR,
-#if defined(CONFIG_MX25) || defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
- defined(CONFIG_MX6Q)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+ defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
[3] = GPIO4_BASE_ADDR,
#endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
[4] = GPIO5_BASE_ADDR,
[5] = GPIO6_BASE_ADDR,
+#endif
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
[6] = GPIO7_BASE_ADDR,
#endif
};
regs = (struct gpio_regs *)gpio_ports[port];
- val = (readl(®s->gpio_dr) >> gpio) & 0x01;
+ val = (readl(®s->gpio_psr) >> gpio) & 0x01;
return val;
}
{
uint32_t bank = PAD_BANK(gpio);
uint32_t offset = PINCTRL_DIN(bank);
- struct mx28_register_32 *reg =
- (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
+ struct mxs_register_32 *reg =
+ (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
return (readl(®->reg) >> PAD_PIN(gpio)) & 1;
}
{
uint32_t bank = PAD_BANK(gpio);
uint32_t offset = PINCTRL_DOUT(bank);
- struct mx28_register_32 *reg =
- (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
+ struct mxs_register_32 *reg =
+ (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
if (value)
writel(1 << PAD_PIN(gpio), ®->reg_set);
{
uint32_t bank = PAD_BANK(gpio);
uint32_t offset = PINCTRL_DOE(bank);
- struct mx28_register_32 *reg =
- (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
+ struct mxs_register_32 *reg =
+ (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
writel(1 << PAD_PIN(gpio), ®->reg_clr);
{
uint32_t bank = PAD_BANK(gpio);
uint32_t offset = PINCTRL_DOE(bank);
- struct mx28_register_32 *reg =
- (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
+ struct mxs_register_32 *reg =
+ (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
writel(1 << PAD_PIN(gpio), ®->reg_set);
/*
- * NVIDIA Tegra2 GPIO handling.
+ * NVIDIA Tegra20 GPIO handling.
* (C) Copyright 2010-2012
* NVIDIA Corporation <www.nvidia.com>
*
#include <common.h>
#include <asm/io.h>
#include <asm/bitops.h>
-#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra20.h>
#include <asm/gpio.h>
enum {
- TEGRA2_CMD_INFO,
- TEGRA2_CMD_PORT,
- TEGRA2_CMD_OUTPUT,
- TEGRA2_CMD_INPUT,
+ TEGRA20_CMD_INFO,
+ TEGRA20_CMD_PORT,
+ TEGRA20_CMD_OUTPUT,
+ TEGRA20_CMD_INPUT,
};
static struct gpio_names {
void mxs_i2c_reset(void)
{
- struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+ struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
int ret;
- ret = mx28_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
+ ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
if (ret) {
debug("MXS I2C: Block reset timeout\n");
return;
void mxs_i2c_setup_read(uint8_t chip, int len)
{
- struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+ struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
void mxs_i2c_write(uchar chip, uint addr, int alen,
uchar *buf, int blen, int stop)
{
- struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+ struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
uint32_t data;
int i, remain, off;
int mxs_i2c_wait_for_ack(void)
{
- struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+ struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
uint32_t tmp;
int timeout = MXS_I2C_MAX_TIMEOUT;
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
- struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+ struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
uint32_t tmp = 0;
int ret;
int i;
void i2c_init(int speed, int slaveadd)
{
- struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE;
+ struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
mxs_i2c_reset();
bus_initialized[current_bus] = 1;
}
-static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value)
+static int i2c_read_byte(u8 devaddr, u16 regoffset, u8 alen, u8 *value)
{
int i2c_error = 0;
u16 status;
+ int i = 2 - alen;
+ u8 tmpbuf[2] = {(regoffset) >> 8, regoffset & 0xff};
+ u16 w;
/* wait until bus not busy */
wait_for_bb();
/* one byte only */
- writew(1, &i2c_base->cnt);
+ writew(alen, &i2c_base->cnt);
/* set slave address */
writew(devaddr, &i2c_base->sa);
/* no stop bit needed here */
goto read_exit;
}
if (status & I2C_STAT_XRDY) {
- /* Important: have to use byte access */
- writeb(regoffset, &i2c_base->data);
+ w = tmpbuf[i++];
+#if !(defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
+ defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX))
+ w |= tmpbuf[i++] << 8;
+#endif
+ writew(w, &i2c_base->data);
writew(I2C_STAT_XRDY, &i2c_base->stat);
}
if (status & I2C_STAT_ARDY) {
{
int i;
- if (alen > 1) {
+ if (alen > 2) {
printf("I2C read: addr len %d not supported\n", alen);
return 1;
}
- if (addr + len > 256) {
+ if (addr + len > (1 << 16)) {
puts("I2C read: address out of range\n");
return 1;
}
for (i = 0; i < len; i++) {
- if (i2c_read_byte(chip, addr + i, &buffer[i])) {
+ if (i2c_read_byte(chip, addr + i, alen, &buffer[i])) {
puts("I2C read: I/O error\n");
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
return 1;
int i;
u16 status;
int i2c_error = 0;
+ u16 w;
+ u8 tmpbuf[2] = {addr >> 8, addr & 0xff};
- if (alen > 1) {
+ if (alen > 2) {
printf("I2C write: addr len %d not supported\n", alen);
return 1;
}
- if (addr + len > 256) {
+ if (addr + len > (1 << 16)) {
printf("I2C write: address 0x%x + 0x%x out of range\n",
addr, len);
return 1;
writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
I2C_CON_STP, &i2c_base->con);
- /* Send address byte */
- status = wait_for_pin();
-
- if (status == 0 || status & I2C_STAT_NACK) {
- i2c_error = 1;
- printf("error waiting for i2c address ACK (status=0x%x)\n",
- status);
- goto write_exit;
- }
-
- if (status & I2C_STAT_XRDY) {
- writeb(addr & 0xFF, &i2c_base->data);
- writew(I2C_STAT_XRDY, &i2c_base->stat);
- } else {
- i2c_error = 1;
- printf("i2c bus not ready for transmit (status=0x%x)\n",
- status);
- goto write_exit;
- }
-
- /* address phase is over, now write data */
- for (i = 0; i < len; i++) {
+ /* Send address and data */
+ for (i = -alen; i < len; i++) {
status = wait_for_pin();
if (status == 0 || status & I2C_STAT_NACK) {
}
if (status & I2C_STAT_XRDY) {
- writeb(buffer[i], &i2c_base->data);
+ w = (i < 0) ? tmpbuf[2+i] : buffer[i];
+#if !(defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
+ defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX))
+ w |= ((++i < 0) ? tmpbuf[2+i] : buffer[i]) << 8;
+#endif
+ writew(w, &i2c_base->data);
writew(I2C_STAT_XRDY, &i2c_base->stat);
} else {
i2c_error = 1;
return error;
}
-static int tegra2_i2c_write_data(u32 addr, u8 *data, u32 len)
+static int tegra20_i2c_write_data(u32 addr, u8 *data, u32 len)
{
int error;
struct i2c_trans_info trans_info;
error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
if (error)
- debug("tegra2_i2c_write_data: Error (%d) !!!\n", error);
+ debug("tegra20_i2c_write_data: Error (%d) !!!\n", error);
return error;
}
-static int tegra2_i2c_read_data(u32 addr, u8 *data, u32 len)
+static int tegra20_i2c_read_data(u32 addr, u8 *data, u32 len)
{
int error;
struct i2c_trans_info trans_info;
error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
if (error)
- debug("tegra2_i2c_read_data: Error (%d) !!!\n", error);
+ debug("tegra20_i2c_read_data: Error (%d) !!!\n", error);
return error;
}
debug("\n");
/* Shift 7-bit address over for lower-level i2c functions */
- rc = tegra2_i2c_write_data(chip << 1, buffer, len);
+ rc = tegra20_i2c_write_data(chip << 1, buffer, len);
if (rc)
debug("i2c_write_data(): rc=%d\n", rc);
debug("inside i2c_read_data():\n");
/* Shift 7-bit address over for lower-level i2c functions */
- rc = tegra2_i2c_read_data(chip << 1, buffer, len);
+ rc = tegra20_i2c_read_data(chip << 1, buffer, len);
if (rc) {
debug("i2c_read_data(): rc=%d\n", rc);
return rc;
LIB := $(obj)libinput.o
COBJS-$(CONFIG_I8042_KBD) += i8042.o
-COBJS-$(CONFIG_TEGRA2_KEYBOARD) += tegra-kbc.o
+COBJS-$(CONFIG_TEGRA20_KEYBOARD) += tegra-kbc.o
ifdef CONFIG_PS2KBD
COBJS-y += keyboard.o pc_keyb.o
COBJS-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o
LIB := $(obj)libmmc.o
+ifdef CONFIG_SPL_MMC_LOAD
+COBJS-$(CONFIG_SPL_MMC_LOAD) += spl_mmc_load.o
+endif
+
COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
#include "arm_pl180_mmci.h"
#include <malloc.h>
-struct mmc_host {
- struct sdi_registers *base;
-};
-
static int wait_for_command_end(struct mmc *dev, struct mmc_cmd *cmd)
{
u32 hoststatus, statusmask;
- struct mmc_host *host = dev->priv;
+ struct pl180_mmc_host *host = dev->priv;
statusmask = SDI_STA_CTIMEOUT | SDI_STA_CCRCFAIL;
if ((cmd->resp_type & MMC_RSP_PRESENT))
writel(statusmask, &host->base->status_clear);
if (hoststatus & SDI_STA_CTIMEOUT) {
- printf("CMD%d time out\n", cmd->cmdidx);
- return -ETIMEDOUT;
+ debug("CMD%d time out\n", cmd->cmdidx);
+ return TIMEOUT;
} else if ((hoststatus & SDI_STA_CCRCFAIL) &&
(cmd->flags & MMC_RSP_CRC)) {
printf("CMD%d CRC error\n", cmd->cmdidx);
{
int result;
u32 sdi_cmd = 0;
- struct mmc_host *host = dev->priv;
+ struct pl180_mmc_host *host = dev->priv;
sdi_cmd = ((cmd->cmdidx & SDI_CMD_CMDINDEX_MASK) | SDI_CMD_CPSMEN);
{
u32 *tempbuff = dest;
u64 xfercount = blkcount * blksize;
- struct mmc_host *host = dev->priv;
+ struct pl180_mmc_host *host = dev->priv;
u32 status, status_err;
debug("read_bytes: blkcount=%u blksize=%u\n", blkcount, blksize);
u32 *tempbuff = src;
int i;
u64 xfercount = blkcount * blksize;
- struct mmc_host *host = dev->priv;
+ struct pl180_mmc_host *host = dev->priv;
u32 status, status_err;
debug("write_bytes: blkcount=%u blksize=%u\n", blkcount, blksize);
struct mmc_data *data)
{
int error = -ETIMEDOUT;
- struct mmc_host *host = dev->priv;
+ struct pl180_mmc_host *host = dev->priv;
u32 blksz = 0;
u32 data_ctrl = 0;
u32 data_len = (u32) (data->blocks * data->blocksize);
- blksz = (ffs(data->blocksize) - 1);
- data_ctrl |= ((blksz << 4) & SDI_DCTRL_DBLKSIZE_MASK);
- data_ctrl |= SDI_DCTRL_DTEN;
+ if (!host->version2) {
+ blksz = (ffs(data->blocksize) - 1);
+ data_ctrl |= ((blksz << 4) & SDI_DCTRL_DBLKSIZE_MASK);
+ } else {
+ blksz = data->blocksize;
+ data_ctrl |= (blksz << SDI_DCTRL_DBLOCKSIZE_V2_SHIFT);
+ }
+ data_ctrl |= SDI_DCTRL_DTEN | SDI_DCTRL_BUSYMODE;
writel(SDI_DTIMER_DEFAULT, &host->base->datatimer);
writel(data_len, &host->base->datalength);
writel(data_ctrl, &host->base->datactrl);
error = write_bytes(dev, (u32 *)data->src, (u32)data->blocks,
- (u32)data->blocksize);
+ (u32)data->blocksize);
}
return error;
/* MMC uses open drain drivers in the enumeration phase */
static int mmc_host_reset(struct mmc *dev)
{
- struct mmc_host *host = dev->priv;
- u32 sdi_u32 = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON;
+ struct pl180_mmc_host *host = dev->priv;
- writel(sdi_u32, &host->base->power);
+ writel(host->pwr_init, &host->base->power);
return 0;
}
static void host_set_ios(struct mmc *dev)
{
- struct mmc_host *host = dev->priv;
+ struct pl180_mmc_host *host = dev->priv;
u32 sdi_clkcr;
sdi_clkcr = readl(&host->base->clock);
/* Ramp up the clock rate */
if (dev->clock) {
u32 clkdiv = 0;
+ u32 tmp_clock;
- if (dev->clock >= dev->f_max)
+ if (dev->clock >= dev->f_max) {
+ clkdiv = 0;
dev->clock = dev->f_max;
+ } else {
+ clkdiv = (host->clock_in / dev->clock) - 2;
+ }
- clkdiv = ((ARM_MCLK / dev->clock) / 2) - 1;
+ tmp_clock = host->clock_in / (clkdiv + 2);
+ while (tmp_clock > dev->clock) {
+ clkdiv++;
+ tmp_clock = host->clock_in / (clkdiv + 2);
+ }
if (clkdiv > SDI_CLKCR_CLKDIV_MASK)
clkdiv = SDI_CLKCR_CLKDIV_MASK;
+ tmp_clock = host->clock_in / (clkdiv + 2);
+ dev->clock = tmp_clock;
sdi_clkcr &= ~(SDI_CLKCR_CLKDIV_MASK);
sdi_clkcr |= clkdiv;
}
case 4:
buswidth |= SDI_CLKCR_WIDBUS_4;
break;
+ case 8:
+ buswidth |= SDI_CLKCR_WIDBUS_8;
+ break;
default:
- printf("Invalid bus width\n");
+ printf("Invalid bus width: %d\n", dev->bus_width);
break;
}
sdi_clkcr &= ~(SDI_CLKCR_WIDBUS_MASK);
udelay(CLK_CHANGE_DELAY);
}
-struct mmc *alloc_mmc_struct(void)
-{
- struct mmc_host *host = NULL;
- struct mmc *mmc_device = NULL;
-
- host = malloc(sizeof(struct mmc_host));
- if (!host)
- return NULL;
-
- mmc_device = malloc(sizeof(struct mmc));
- if (!mmc_device)
- goto err;
-
- mmc_device->priv = host;
- return mmc_device;
-
-err:
- free(host);
- return NULL;
-}
-
/*
* mmc_host_init - initialize the mmc controller.
* Set initial clock and power for mmc slot.
* Initialize mmc struct and register with mmc framework.
*/
-static int arm_pl180_mmci_host_init(struct mmc *dev)
+int arm_pl180_mmci_init(struct pl180_mmc_host *host)
{
- struct mmc_host *host = dev->priv;
+ struct mmc *dev;
u32 sdi_u32;
- host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
+ dev = malloc(sizeof(struct mmc));
+ if (!dev)
+ return -ENOMEM;
- /* Initially set power-on, full voltage & MMCI read */
- sdi_u32 = INIT_PWR;
- writel(sdi_u32, &host->base->power);
+ memset(dev, 0, sizeof(struct mmc));
+ dev->priv = host;
- /* setting clk freq 505KHz */
- sdi_u32 = SDI_CLKCR_CLKDIV_INIT | SDI_CLKCR_CLKEN;
- writel(sdi_u32, &host->base->clock);
+ writel(host->pwr_init, &host->base->power);
+ writel(host->clkdiv_init, &host->base->clock);
udelay(CLK_CHANGE_DELAY);
/* Disable mmc interrupts */
sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
writel(sdi_u32, &host->base->mask0);
-
- sprintf(dev->name, "MMC");
- dev->clock = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT + 1));
+ strncpy(dev->name, host->name, sizeof(dev->name));
dev->send_cmd = host_request;
dev->set_ios = host_set_ios;
dev->init = mmc_host_reset;
dev->getcd = NULL;
- dev->host_caps = 0;
- dev->voltages = VOLTAGE_WINDOW_MMC;
- dev->f_min = dev->clock;
- dev->f_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
-
- return 0;
-}
-
-int arm_pl180_mmci_init(void)
-{
- int error;
- struct mmc *dev;
-
- dev = alloc_mmc_struct();
- if (!dev)
- return -1;
-
- error = arm_pl180_mmci_host_init(dev);
- if (error) {
- printf("mmci_host_init error - %d\n", error);
- return -1;
- }
-
- dev->b_max = 0;
-
+ dev->host_caps = host->caps;
+ dev->voltages = host->voltages;
+ dev->f_min = host->clock_min;
+ dev->f_max = host->clock_max;
+ dev->b_max = host->b_max;
mmc_register(dev);
debug("registered mmc interface number is:%d\n", dev->block_dev.dev);
#ifndef __ARM_PL180_MMCI_H__
#define __ARM_PL180_MMCI_H__
-int arm_pl180_mmci_init(void);
-
#define COMMAND_REG_DELAY 300
#define DATA_REG_DELAY 1000
#define CLK_CHANGE_DELAY 2000
#define SDI_CLKCR_WIDBUS_MASK 0x00001800
#define SDI_CLKCR_WIDBUS_1 0x00000000
#define SDI_CLKCR_WIDBUS_4 0x00000800
+/* V2 only */
+#define SDI_CLKCR_WIDBUS_8 0x00001000
+#define SDI_CLKCR_NEDGE 0x00002000
+#define SDI_CLKCR_HWFC_EN 0x00004000
-#define SDI_CLKCR_CLKDIV_INIT 0x000000C6 /* MCLK/(2*(0xC6+1)) => 505KHz */
+#define SDI_CLKCR_CLKDIV_INIT_V1 0x000000C6 /* MCLK/(2*(0xC6+1)) => 505KHz */
+#define SDI_CLKCR_CLKDIV_INIT_V2 0x000000FD
/* SDI command register bits */
#define SDI_CMD_CMDINDEX_MASK 0x000000FF
#define SDI_DCTRL_DBOOTMODEEN 0x00002000
#define SDI_DCTRL_BUSYMODE 0x00004000
#define SDI_DCTRL_DDR_MODE 0x00008000
+#define SDI_DCTRL_DBLOCKSIZE_V2_MASK 0x7fff0000
+#define SDI_DCTRL_DBLOCKSIZE_V2_SHIFT 16
#define SDI_FIFO_BURST_SIZE 8
u32 pcell_id3; /* 0xFFC*/
};
+struct pl180_mmc_host {
+ struct sdi_registers *base;
+ char name[32];
+ unsigned int b_max;
+ unsigned int voltages;
+ unsigned int caps;
+ unsigned int clock_in;
+ unsigned int clock_min;
+ unsigned int clock_max;
+ unsigned int clkdiv_init;
+ unsigned int pwr_init;
+ int version2;
+};
+
+int arm_pl180_mmci_init(struct pl180_mmc_host *);
+
#endif
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
udelay(1000);
+#ifndef ARCH_MXC
/* Enable cache snooping */
- if (cfg && !cfg->no_snoop)
- esdhc_write32(®s->scr, 0x00000040);
+ esdhc_write32(®s->scr, 0x00000040);
+#endif
esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
#include <asm/arch/sys_proto.h>
#include <asm/arch/dma.h>
-/*
- * CONFIG_MXS_MMC_DMA: This feature is highly experimental and has no
- * performance benefit unless you operate the platform with
- * data cache enabled. This is disabled by default, enable
- * only if you know what you're doing.
- */
-
struct mxsmmc_priv {
int id;
- struct mx28_ssp_regs *regs;
+ struct mxs_ssp_regs *regs;
uint32_t clkseq_bypass;
uint32_t *clkctrl_ssp;
uint32_t buswidth;
};
#define MXSMMC_MAX_TIMEOUT 10000
+#define MXSMMC_SMALL_TRANSFER 512
+
+static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
+{
+ struct mxs_ssp_regs *ssp_regs = priv->regs;
+ uint32_t *data_ptr;
+ int timeout = MXSMMC_MAX_TIMEOUT;
+ uint32_t reg;
+ uint32_t data_count = data->blocksize * data->blocks;
+
+ if (data->flags & MMC_DATA_READ) {
+ data_ptr = (uint32_t *)data->dest;
+ while (data_count && --timeout) {
+ reg = readl(&ssp_regs->hw_ssp_status);
+ if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
+ *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
+ data_count -= 4;
+ timeout = MXSMMC_MAX_TIMEOUT;
+ } else
+ udelay(1000);
+ }
+ } else {
+ data_ptr = (uint32_t *)data->src;
+ timeout *= 100;
+ while (data_count && --timeout) {
+ reg = readl(&ssp_regs->hw_ssp_status);
+ if (!(reg & SSP_STATUS_FIFO_FULL)) {
+ writel(*data_ptr++, &ssp_regs->hw_ssp_data);
+ data_count -= 4;
+ timeout = MXSMMC_MAX_TIMEOUT;
+ } else
+ udelay(1000);
+ }
+ }
+
+ return timeout ? 0 : COMM_ERR;
+}
+
+static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
+{
+ uint32_t data_count = data->blocksize * data->blocks;
+ uint32_t cache_data_count;
+ int dmach;
+ struct mxs_dma_desc *desc = priv->desc;
+
+ memset(desc, 0, sizeof(struct mxs_dma_desc));
+ desc->address = (dma_addr_t)desc;
+
+ if (data_count % ARCH_DMA_MINALIGN)
+ cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN);
+ else
+ cache_data_count = data_count;
+
+ if (data->flags & MMC_DATA_READ) {
+ priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
+ priv->desc->cmd.address = (dma_addr_t)data->dest;
+ } else {
+ priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
+ priv->desc->cmd.address = (dma_addr_t)data->src;
+
+ /* Flush data to DRAM so DMA can pick them up */
+ flush_dcache_range((uint32_t)priv->desc->cmd.address,
+ (uint32_t)(priv->desc->cmd.address + cache_data_count));
+ }
+
+ priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
+ (data_count << MXS_DMA_DESC_BYTES_OFFSET);
+
+ dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
+ mxs_dma_desc_append(dmach, priv->desc);
+ if (mxs_dma_go(dmach))
+ return COMM_ERR;
+
+ /* The data arrived into DRAM, invalidate cache over them */
+ if (data->flags & MMC_DATA_READ) {
+ invalidate_dcache_range((uint32_t)priv->desc->cmd.address,
+ (uint32_t)(priv->desc->cmd.address + cache_data_count));
+ }
+
+ return 0;
+}
/*
* Sends a command out on the bus. Takes the mmc pointer,
mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
- struct mx28_ssp_regs *ssp_regs = priv->regs;
+ struct mxs_ssp_regs *ssp_regs = priv->regs;
uint32_t reg;
int timeout;
- uint32_t data_count;
uint32_t ctrl0;
-#ifndef CONFIG_MXS_MMC_DMA
- uint32_t *data_ptr;
-#else
- uint32_t cache_data_count;
-#endif
+ int ret;
debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
ctrl0 |= SSP_CTRL0_LONG_RESP;
+ if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
+ writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
+ else
+ writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
+
/* Command index */
reg = readl(&ssp_regs->hw_ssp_cmd0);
reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
if (!data)
return 0;
- data_count = data->blocksize * data->blocks;
- timeout = MXSMMC_MAX_TIMEOUT;
-
-#ifdef CONFIG_MXS_MMC_DMA
- if (data_count % ARCH_DMA_MINALIGN)
- cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN);
- else
- cache_data_count = data_count;
-
- if (data->flags & MMC_DATA_READ) {
- priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
- priv->desc->cmd.address = (dma_addr_t)data->dest;
- } else {
- priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
- priv->desc->cmd.address = (dma_addr_t)data->src;
-
- /* Flush data to DRAM so DMA can pick them up */
- flush_dcache_range((uint32_t)priv->desc->cmd.address,
- (uint32_t)(priv->desc->cmd.address + cache_data_count));
- }
-
- priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
- (data_count << MXS_DMA_DESC_BYTES_OFFSET);
-
-
- mxs_dma_desc_append(MXS_DMA_CHANNEL_AHB_APBH_SSP0, priv->desc);
- if (mxs_dma_go(MXS_DMA_CHANNEL_AHB_APBH_SSP0)) {
- printf("MMC%d: DMA transfer failed\n", mmc->block_dev.dev);
- return COMM_ERR;
- }
-
- /* The data arrived into DRAM, invalidate cache over them */
- if (data->flags & MMC_DATA_READ) {
- invalidate_dcache_range((uint32_t)priv->desc->cmd.address,
- (uint32_t)(priv->desc->cmd.address + cache_data_count));
- }
-#else
- if (data->flags & MMC_DATA_READ) {
- data_ptr = (uint32_t *)data->dest;
- while (data_count && --timeout) {
- reg = readl(&ssp_regs->hw_ssp_status);
- if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
- *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
- data_count -= 4;
- timeout = MXSMMC_MAX_TIMEOUT;
- } else
- udelay(1000);
+ if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
+ ret = mxsmmc_send_cmd_pio(priv, data);
+ if (ret) {
+ printf("MMC%d: Data timeout with command %d "
+ "(status 0x%08x)!\n",
+ mmc->block_dev.dev, cmd->cmdidx, reg);
+ return ret;
}
} else {
- data_ptr = (uint32_t *)data->src;
- timeout *= 100;
- while (data_count && --timeout) {
- reg = readl(&ssp_regs->hw_ssp_status);
- if (!(reg & SSP_STATUS_FIFO_FULL)) {
- writel(*data_ptr++, &ssp_regs->hw_ssp_data);
- data_count -= 4;
- timeout = MXSMMC_MAX_TIMEOUT;
- } else
- udelay(1000);
+ ret = mxsmmc_send_cmd_dma(priv, data);
+ if (ret) {
+ printf("MMC%d: DMA transfer failed\n",
+ mmc->block_dev.dev);
+ return ret;
}
}
- if (!timeout) {
- printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n",
- mmc->block_dev.dev, cmd->cmdidx, reg);
- return COMM_ERR;
- }
-#endif
-
/* Check data errors */
reg = readl(&ssp_regs->hw_ssp_status);
if (reg &
static void mxsmmc_set_ios(struct mmc *mmc)
{
struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
- struct mx28_ssp_regs *ssp_regs = priv->regs;
+ struct mxs_ssp_regs *ssp_regs = priv->regs;
/* Set the clock speed */
if (mmc->clock)
static int mxsmmc_init(struct mmc *mmc)
{
struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
- struct mx28_ssp_regs *ssp_regs = priv->regs;
+ struct mxs_ssp_regs *ssp_regs = priv->regs;
/* Reset SSP */
- mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
+ mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
/* 8 bits word length in MMC mode */
clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
- SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK,
- SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
- SSP_CTRL1_DMA_ENABLE);
+ SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK |
+ SSP_CTRL1_DMA_ENABLE,
+ SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
/* Set initial bit clock 400 KHz */
mx28_set_ssp_busclock(priv->id, 400);
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
{
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mmc *mmc = NULL;
struct mxsmmc_priv *priv = NULL;
int ret;
priv->id = id;
switch (id) {
case 0:
- priv->regs = (struct mx28_ssp_regs *)MXS_SSP0_BASE;
+ priv->regs = (struct mxs_ssp_regs *)MXS_SSP0_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0;
break;
case 1:
- priv->regs = (struct mx28_ssp_regs *)MXS_SSP1_BASE;
+ priv->regs = (struct mxs_ssp_regs *)MXS_SSP1_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1;
break;
case 2:
- priv->regs = (struct mx28_ssp_regs *)MXS_SSP2_BASE;
+ priv->regs = (struct mxs_ssp_regs *)MXS_SSP2_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2;
break;
case 3:
- priv->regs = (struct mx28_ssp_regs *)MXS_SSP3_BASE;
+ priv->regs = (struct mxs_ssp_regs *)MXS_SSP3_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3;
break;
--- /dev/null
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void mmc_load_image(struct mmc *mmc)
+{
+ s32 err;
+ void (*uboot)(void) __noreturn;
+
+ err = mmc->block_dev.block_read(0, CONFIG_SYS_MMC_U_BOOT_OFFS,
+ CONFIG_SYS_MMC_U_BOOT_SIZE/512,
+ (u32 *)CONFIG_SYS_TEXT_BASE);
+
+ if (err <= 0) {
+ printf("spl: error reading image %s, err - %d\n",
+ "u-boot.img", err);
+ hang();
+ }
+ uboot = (void *) CONFIG_SYS_TEXT_BASE;
+ (*uboot)();
+}
+
+void spl_mmc_load(void)
+{
+ struct mmc *mmc;
+ int err;
+ void (mmc_load_image)(struct mmc *mmc) __noreturn;
+
+ mmc_initialize(gd->bd);
+ mmc = find_mmc_device(0);
+ if (!mmc) {
+ puts("spl: mmc device not found!!\n");
+ hang();
+ } else {
+ puts("spl: mmc device found\n");
+ }
+ err = mmc_init(mmc);
+ if (err) {
+ printf("spl: mmc init failed: err - %d\n", err);
+ hang();
+ }
+ mmc_load_image(mmc);
+}
* @param host Structure to fill in (base, reg, mmc_id)
* @param dev_index Device index (0-3)
*/
-static void tegra2_get_setup(struct mmc_host *host, int dev_index)
+static void tegra20_get_setup(struct mmc_host *host, int dev_index)
{
- debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index);
+ debug("tegra20_get_base_mmc: dev_index = %d\n", dev_index);
switch (dev_index) {
case 1:
- host->base = TEGRA2_SDMMC3_BASE;
+ host->base = TEGRA20_SDMMC3_BASE;
host->mmc_id = PERIPH_ID_SDMMC3;
break;
case 2:
- host->base = TEGRA2_SDMMC2_BASE;
+ host->base = TEGRA20_SDMMC2_BASE;
host->mmc_id = PERIPH_ID_SDMMC2;
break;
case 3:
- host->base = TEGRA2_SDMMC1_BASE;
+ host->base = TEGRA20_SDMMC1_BASE;
host->mmc_id = PERIPH_ID_SDMMC1;
break;
case 0:
default:
- host->base = TEGRA2_SDMMC4_BASE;
+ host->base = TEGRA20_SDMMC4_BASE;
host->mmc_id = PERIPH_ID_SDMMC4;
break;
}
- host->reg = (struct tegra2_mmc *)host->base;
+ host->reg = (struct tegra20_mmc *)host->base;
}
static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
debug(" mmc_change_clock called\n");
/*
- * Change Tegra2 SDMMCx clock divisor here. Source is 216MHz,
+ * Change Tegra20 SDMMCx clock divisor here. Source is 216MHz,
* PLLP_OUT0
*/
if (clock == 0)
return 0;
}
-int tegra2_mmc_getcd(struct mmc *mmc)
+int tegra20_mmc_getcd(struct mmc *mmc)
{
struct mmc_host *host = (struct mmc_host *)mmc->priv;
- debug("tegra2_mmc_getcd called\n");
+ debug("tegra20_mmc_getcd called\n");
if (host->cd_gpio >= 0)
return !gpio_get_value(host->cd_gpio);
return 1;
}
-int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
+int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
{
struct mmc_host *host;
char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
struct mmc *mmc;
- debug(" tegra2_mmc_init: index %d, bus width %d "
+ debug(" tegra20_mmc_init: index %d, bus width %d "
"pwr_gpio %d cd_gpio %d\n",
dev_index, bus_width, pwr_gpio, cd_gpio);
host->clock = 0;
host->pwr_gpio = pwr_gpio;
host->cd_gpio = cd_gpio;
- tegra2_get_setup(host, dev_index);
+ tegra20_get_setup(host, dev_index);
clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
mmc = &mmc_dev[dev_index];
- sprintf(mmc->name, "Tegra2 SD/MMC");
+ sprintf(mmc->name, "Tegra20 SD/MMC");
mmc->priv = host;
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_core_init;
- mmc->getcd = tegra2_mmc_getcd;
+ mmc->getcd = tegra20_mmc_getcd;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
if (bus_width == 8)
* max freq is highest HS eMMC clock as per the SD/MMC spec
* (actually 52MHz)
* Both of these are the closest equivalents w/216MHz source
- * clock and Tegra2 SDMMC divisors.
+ * clock and Tegra20 SDMMC divisors.
*/
mmc->f_min = 375000;
mmc->f_max = 48000000;
#ifndef __TEGRA_MMC_H_
#define __TEGRA_MMC_H_
-#define TEGRA2_SDMMC1_BASE 0xC8000000
-#define TEGRA2_SDMMC2_BASE 0xC8000200
-#define TEGRA2_SDMMC3_BASE 0xC8000400
-#define TEGRA2_SDMMC4_BASE 0xC8000600
+#define TEGRA20_SDMMC1_BASE 0xC8000000
+#define TEGRA20_SDMMC2_BASE 0xC8000200
+#define TEGRA20_SDMMC3_BASE 0xC8000400
+#define TEGRA20_SDMMC4_BASE 0xC8000600
#ifndef __ASSEMBLY__
-struct tegra2_mmc {
+struct tegra20_mmc {
unsigned int sysad; /* _SYSTEM_ADDRESS_0 */
unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
struct mmc_host {
- struct tegra2_mmc *reg;
+ struct tegra20_mmc *reg;
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
unsigned int base; /* Base address, SDMMC1/2/3/4 */
*
* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
*
+ * Add Programmable Multibit ECC support for various AT91 SoC
+ * (C) Copyright 2012 ATMEL, Hong Xu
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#include <asm/arch/at91_pio.h>
#include <nand.h>
+#include <watchdog.h>
#ifdef CONFIG_ATMEL_NAND_HWECC
#include "atmel_nand_ecc.h" /* Hardware ECC registers */
+#ifdef CONFIG_ATMEL_NAND_HW_PMECC
+
+struct atmel_nand_host {
+ struct pmecc_regs __iomem *pmecc;
+ struct pmecc_errloc_regs __iomem *pmerrloc;
+ void __iomem *pmecc_rom_base;
+
+ u8 pmecc_corr_cap;
+ u16 pmecc_sector_size;
+ u32 pmecc_index_table_offset;
+
+ int pmecc_bytes_per_sector;
+ int pmecc_sector_number;
+ int pmecc_degree; /* Degree of remainders */
+ int pmecc_cw_len; /* Length of codeword */
+
+ /* lookup table for alpha_to and index_of */
+ void __iomem *pmecc_alpha_to;
+ void __iomem *pmecc_index_of;
+
+ /* data for pmecc computation */
+ int16_t pmecc_smu[(CONFIG_PMECC_CAP + 2) * (2 * CONFIG_PMECC_CAP + 1)];
+ int16_t pmecc_partial_syn[2 * CONFIG_PMECC_CAP + 1];
+ int16_t pmecc_si[2 * CONFIG_PMECC_CAP + 1];
+ int16_t pmecc_lmu[CONFIG_PMECC_CAP + 1]; /* polynomal order */
+ int pmecc_mu[CONFIG_PMECC_CAP + 1];
+ int pmecc_dmu[CONFIG_PMECC_CAP + 1];
+ int pmecc_delta[CONFIG_PMECC_CAP + 1];
+};
+
+static struct atmel_nand_host pmecc_host;
+static struct nand_ecclayout atmel_pmecc_oobinfo;
+
+/*
+ * Return number of ecc bytes per sector according to sector size and
+ * correction capability
+ *
+ * Following table shows what at91 PMECC supported:
+ * Correction Capability Sector_512_bytes Sector_1024_bytes
+ * ===================== ================ =================
+ * 2-bits 4-bytes 4-bytes
+ * 4-bits 7-bytes 7-bytes
+ * 8-bits 13-bytes 14-bytes
+ * 12-bits 20-bytes 21-bytes
+ * 24-bits 39-bytes 42-bytes
+ */
+static int pmecc_get_ecc_bytes(int cap, int sector_size)
+{
+ int m = 12 + sector_size / 512;
+ return (m * cap + 7) / 8;
+}
+
+static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
+ int oobsize, int ecc_len)
+{
+ int i;
+
+ layout->eccbytes = ecc_len;
+
+ /* ECC will occupy the last ecc_len bytes continuously */
+ for (i = 0; i < ecc_len; i++)
+ layout->eccpos[i] = oobsize - ecc_len + i;
+
+ layout->oobfree[0].offset = 2;
+ layout->oobfree[0].length =
+ oobsize - ecc_len - layout->oobfree[0].offset;
+}
+
+static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
+{
+ int table_size;
+
+ table_size = host->pmecc_sector_size == 512 ?
+ PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
+
+ /* the ALPHA lookup table is right behind the INDEX lookup table. */
+ return host->pmecc_rom_base + host->pmecc_index_table_offset +
+ table_size * sizeof(int16_t);
+}
+
+static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct atmel_nand_host *host = nand_chip->priv;
+ int i;
+ uint32_t value;
+
+ /* Fill odd syndromes */
+ for (i = 0; i < host->pmecc_corr_cap; i++) {
+ value = readl(&host->pmecc->rem_port[sector].rem[i / 2]);
+ if (i & 1)
+ value >>= 16;
+ value &= 0xffff;
+ host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
+ }
+}
+
+static void pmecc_substitute(struct mtd_info *mtd)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct atmel_nand_host *host = nand_chip->priv;
+ int16_t __iomem *alpha_to = host->pmecc_alpha_to;
+ int16_t __iomem *index_of = host->pmecc_index_of;
+ int16_t *partial_syn = host->pmecc_partial_syn;
+ const int cap = host->pmecc_corr_cap;
+ int16_t *si;
+ int i, j;
+
+ /* si[] is a table that holds the current syndrome value,
+ * an element of that table belongs to the field
+ */
+ si = host->pmecc_si;
+
+ memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
+
+ /* Computation 2t syndromes based on S(x) */
+ /* Odd syndromes */
+ for (i = 1; i < 2 * cap; i += 2) {
+ for (j = 0; j < host->pmecc_degree; j++) {
+ if (partial_syn[i] & (0x1 << j))
+ si[i] = readw(alpha_to + i * j) ^ si[i];
+ }
+ }
+ /* Even syndrome = (Odd syndrome) ** 2 */
+ for (i = 2, j = 1; j <= cap; i = ++j << 1) {
+ if (si[j] == 0) {
+ si[i] = 0;
+ } else {
+ int16_t tmp;
+
+ tmp = readw(index_of + si[j]);
+ tmp = (tmp * 2) % host->pmecc_cw_len;
+ si[i] = readw(alpha_to + tmp);
+ }
+ }
+}
+
+/*
+ * This function defines a Berlekamp iterative procedure for
+ * finding the value of the error location polynomial.
+ * The input is si[], initialize by pmecc_substitute().
+ * The output is smu[][].
+ *
+ * This function is written according to chip datasheet Chapter:
+ * Find the Error Location Polynomial Sigma(x) of Section:
+ * Programmable Multibit ECC Control (PMECC).
+ */
+static void pmecc_get_sigma(struct mtd_info *mtd)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct atmel_nand_host *host = nand_chip->priv;
+
+ int16_t *lmu = host->pmecc_lmu;
+ int16_t *si = host->pmecc_si;
+ int *mu = host->pmecc_mu;
+ int *dmu = host->pmecc_dmu; /* Discrepancy */
+ int *delta = host->pmecc_delta; /* Delta order */
+ int cw_len = host->pmecc_cw_len;
+ const int16_t cap = host->pmecc_corr_cap;
+ const int num = 2 * cap + 1;
+ int16_t __iomem *index_of = host->pmecc_index_of;
+ int16_t __iomem *alpha_to = host->pmecc_alpha_to;
+ int i, j, k;
+ uint32_t dmu_0_count, tmp;
+ int16_t *smu = host->pmecc_smu;
+
+ /* index of largest delta */
+ int ro;
+ int largest;
+ int diff;
+
+ /* Init the Sigma(x) */
+ memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
+
+ dmu_0_count = 0;
+
+ /* First Row */
+
+ /* Mu */
+ mu[0] = -1;
+
+ smu[0] = 1;
+
+ /* discrepancy set to 1 */
+ dmu[0] = 1;
+ /* polynom order set to 0 */
+ lmu[0] = 0;
+ /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
+ delta[0] = -1;
+
+ /* Second Row */
+
+ /* Mu */
+ mu[1] = 0;
+ /* Sigma(x) set to 1 */
+ smu[num] = 1;
+
+ /* discrepancy set to S1 */
+ dmu[1] = si[1];
+
+ /* polynom order set to 0 */
+ lmu[1] = 0;
+
+ /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
+ delta[1] = 0;
+
+ for (i = 1; i <= cap; i++) {
+ mu[i + 1] = i << 1;
+ /* Begin Computing Sigma (Mu+1) and L(mu) */
+ /* check if discrepancy is set to 0 */
+ if (dmu[i] == 0) {
+ dmu_0_count++;
+
+ tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
+ if ((cap - (lmu[i] >> 1) - 1) & 0x1)
+ tmp += 2;
+ else
+ tmp += 1;
+
+ if (dmu_0_count == tmp) {
+ for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
+ smu[(cap + 1) * num + j] =
+ smu[i * num + j];
+
+ lmu[cap + 1] = lmu[i];
+ return;
+ }
+
+ /* copy polynom */
+ for (j = 0; j <= lmu[i] >> 1; j++)
+ smu[(i + 1) * num + j] = smu[i * num + j];
+
+ /* copy previous polynom order to the next */
+ lmu[i + 1] = lmu[i];
+ } else {
+ ro = 0;
+ largest = -1;
+ /* find largest delta with dmu != 0 */
+ for (j = 0; j < i; j++) {
+ if ((dmu[j]) && (delta[j] > largest)) {
+ largest = delta[j];
+ ro = j;
+ }
+ }
+
+ /* compute difference */
+ diff = (mu[i] - mu[ro]);
+
+ /* Compute degree of the new smu polynomial */
+ if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
+ lmu[i + 1] = lmu[i];
+ else
+ lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
+
+ /* Init smu[i+1] with 0 */
+ for (k = 0; k < num; k++)
+ smu[(i + 1) * num + k] = 0;
+
+ /* Compute smu[i+1] */
+ for (k = 0; k <= lmu[ro] >> 1; k++) {
+ int16_t a, b, c;
+
+ if (!(smu[ro * num + k] && dmu[i]))
+ continue;
+ a = readw(index_of + dmu[i]);
+ b = readw(index_of + dmu[ro]);
+ c = readw(index_of + smu[ro * num + k]);
+ tmp = a + (cw_len - b) + c;
+ a = readw(alpha_to + tmp % cw_len);
+ smu[(i + 1) * num + (k + diff)] = a;
+ }
+
+ for (k = 0; k <= lmu[i] >> 1; k++)
+ smu[(i + 1) * num + k] ^= smu[i * num + k];
+ }
+
+ /* End Computing Sigma (Mu+1) and L(mu) */
+ /* In either case compute delta */
+ delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
+
+ /* Do not compute discrepancy for the last iteration */
+ if (i >= cap)
+ continue;
+
+ for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
+ tmp = 2 * (i - 1);
+ if (k == 0) {
+ dmu[i + 1] = si[tmp + 3];
+ } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
+ int16_t a, b, c;
+ a = readw(index_of +
+ smu[(i + 1) * num + k]);
+ b = si[2 * (i - 1) + 3 - k];
+ c = readw(index_of + b);
+ tmp = a + c;
+ tmp %= cw_len;
+ dmu[i + 1] = readw(alpha_to + tmp) ^
+ dmu[i + 1];
+ }
+ }
+ }
+}
+
+static int pmecc_err_location(struct mtd_info *mtd)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct atmel_nand_host *host = nand_chip->priv;
+ const int cap = host->pmecc_corr_cap;
+ const int num = 2 * cap + 1;
+ int sector_size = host->pmecc_sector_size;
+ int err_nbr = 0; /* number of error */
+ int roots_nbr; /* number of roots */
+ int i;
+ uint32_t val;
+ int16_t *smu = host->pmecc_smu;
+ int timeout = PMECC_MAX_TIMEOUT_US;
+
+ writel(PMERRLOC_DISABLE, &host->pmerrloc->eldis);
+
+ for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
+ writel(smu[(cap + 1) * num + i], &host->pmerrloc->sigma[i]);
+ err_nbr++;
+ }
+
+ val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
+ if (sector_size == 1024)
+ val |= PMERRLOC_ELCFG_SECTOR_1024;
+
+ writel(val, &host->pmerrloc->elcfg);
+ writel(sector_size * 8 + host->pmecc_degree * cap,
+ &host->pmerrloc->elen);
+
+ while (--timeout) {
+ if (readl(&host->pmerrloc->elisr) & PMERRLOC_CALC_DONE)
+ break;
+ WATCHDOG_RESET();
+ udelay(1);
+ }
+
+ if (!timeout) {
+ printk(KERN_ERR "atmel_nand : Timeout to calculate PMECC error location\n");
+ return -1;
+ }
+
+ roots_nbr = (readl(&host->pmerrloc->elisr) & PMERRLOC_ERR_NUM_MASK)
+ >> 8;
+ /* Number of roots == degree of smu hence <= cap */
+ if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
+ return err_nbr - 1;
+
+ /* Number of roots does not match the degree of smu
+ * unable to correct error */
+ return -1;
+}
+
+static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
+ int sector_num, int extra_bytes, int err_nbr)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct atmel_nand_host *host = nand_chip->priv;
+ int i = 0;
+ int byte_pos, bit_pos, sector_size, pos;
+ uint32_t tmp;
+ uint8_t err_byte;
+
+ sector_size = host->pmecc_sector_size;
+
+ while (err_nbr) {
+ tmp = readl(&host->pmerrloc->el[i]) - 1;
+ byte_pos = tmp / 8;
+ bit_pos = tmp % 8;
+
+ if (byte_pos >= (sector_size + extra_bytes))
+ BUG(); /* should never happen */
+
+ if (byte_pos < sector_size) {
+ err_byte = *(buf + byte_pos);
+ *(buf + byte_pos) ^= (1 << bit_pos);
+
+ pos = sector_num * host->pmecc_sector_size + byte_pos;
+ printk(KERN_INFO "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
+ pos, bit_pos, err_byte, *(buf + byte_pos));
+ } else {
+ /* Bit flip in OOB area */
+ tmp = sector_num * host->pmecc_bytes_per_sector
+ + (byte_pos - sector_size);
+ err_byte = ecc[tmp];
+ ecc[tmp] ^= (1 << bit_pos);
+
+ pos = tmp + nand_chip->ecc.layout->eccpos[0];
+ printk(KERN_INFO "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
+ pos, bit_pos, err_byte, ecc[tmp]);
+ }
+
+ i++;
+ err_nbr--;
+ }
+
+ return;
+}
+
+static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
+ u8 *ecc)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct atmel_nand_host *host = nand_chip->priv;
+ int i, err_nbr, eccbytes;
+ uint8_t *buf_pos;
+
+ eccbytes = nand_chip->ecc.bytes;
+ for (i = 0; i < eccbytes; i++)
+ if (ecc[i] != 0xff)
+ goto normal_check;
+ /* Erased page, return OK */
+ return 0;
+
+normal_check:
+ for (i = 0; i < host->pmecc_sector_number; i++) {
+ err_nbr = 0;
+ if (pmecc_stat & 0x1) {
+ buf_pos = buf + i * host->pmecc_sector_size;
+
+ pmecc_gen_syndrome(mtd, i);
+ pmecc_substitute(mtd);
+ pmecc_get_sigma(mtd);
+
+ err_nbr = pmecc_err_location(mtd);
+ if (err_nbr == -1) {
+ printk(KERN_ERR "PMECC: Too many errors\n");
+ mtd->ecc_stats.failed++;
+ return -EIO;
+ } else {
+ pmecc_correct_data(mtd, buf_pos, ecc, i,
+ host->pmecc_bytes_per_sector, err_nbr);
+ mtd->ecc_stats.corrected += err_nbr;
+ }
+ }
+ pmecc_stat >>= 1;
+ }
+
+ return 0;
+}
+
+static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
+ struct nand_chip *chip, uint8_t *buf, int page)
+{
+ struct atmel_nand_host *host = chip->priv;
+ int eccsize = chip->ecc.size;
+ uint8_t *oob = chip->oob_poi;
+ uint32_t *eccpos = chip->ecc.layout->eccpos;
+ uint32_t stat;
+ int timeout = PMECC_MAX_TIMEOUT_US;
+
+ pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
+ pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
+ pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
+ & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
+
+ pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
+ pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
+
+ chip->read_buf(mtd, buf, eccsize);
+ chip->read_buf(mtd, oob, mtd->oobsize);
+
+ while (--timeout) {
+ if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
+ break;
+ WATCHDOG_RESET();
+ udelay(1);
+ }
+
+ if (!timeout) {
+ printk(KERN_ERR "atmel_nand : Timeout to read PMECC page\n");
+ return -1;
+ }
+
+ stat = pmecc_readl(host->pmecc, isr);
+ if (stat != 0)
+ if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
+ return -EIO;
+
+ return 0;
+}
+
+static void atmel_nand_pmecc_write_page(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf)
+{
+ struct atmel_nand_host *host = chip->priv;
+ uint32_t *eccpos = chip->ecc.layout->eccpos;
+ int i, j;
+ int timeout = PMECC_MAX_TIMEOUT_US;
+
+ pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
+ pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
+
+ pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
+ PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
+
+ pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
+ pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
+
+ chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
+
+ while (--timeout) {
+ if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
+ break;
+ WATCHDOG_RESET();
+ udelay(1);
+ }
+
+ if (!timeout) {
+ printk(KERN_ERR "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
+ return;
+ }
+
+ for (i = 0; i < host->pmecc_sector_number; i++) {
+ for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
+ int pos;
+
+ pos = i * host->pmecc_bytes_per_sector + j;
+ chip->oob_poi[eccpos[pos]] =
+ readb(&host->pmecc->ecc_port[i].ecc[j]);
+ }
+ }
+ chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+}
+
+static void atmel_pmecc_core_init(struct mtd_info *mtd)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+ struct atmel_nand_host *host = nand_chip->priv;
+ uint32_t val = 0;
+ struct nand_ecclayout *ecc_layout;
+
+ pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
+ pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
+
+ switch (host->pmecc_corr_cap) {
+ case 2:
+ val = PMECC_CFG_BCH_ERR2;
+ break;
+ case 4:
+ val = PMECC_CFG_BCH_ERR4;
+ break;
+ case 8:
+ val = PMECC_CFG_BCH_ERR8;
+ break;
+ case 12:
+ val = PMECC_CFG_BCH_ERR12;
+ break;
+ case 24:
+ val = PMECC_CFG_BCH_ERR24;
+ break;
+ }
+
+ if (host->pmecc_sector_size == 512)
+ val |= PMECC_CFG_SECTOR512;
+ else if (host->pmecc_sector_size == 1024)
+ val |= PMECC_CFG_SECTOR1024;
+
+ switch (host->pmecc_sector_number) {
+ case 1:
+ val |= PMECC_CFG_PAGE_1SECTOR;
+ break;
+ case 2:
+ val |= PMECC_CFG_PAGE_2SECTORS;
+ break;
+ case 4:
+ val |= PMECC_CFG_PAGE_4SECTORS;
+ break;
+ case 8:
+ val |= PMECC_CFG_PAGE_8SECTORS;
+ break;
+ }
+
+ val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
+ | PMECC_CFG_AUTO_DISABLE);
+ pmecc_writel(host->pmecc, cfg, val);
+
+ ecc_layout = nand_chip->ecc.layout;
+ pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
+ pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
+ pmecc_writel(host->pmecc, eaddr,
+ ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
+ /* See datasheet about PMECC Clock Control Register */
+ pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
+ pmecc_writel(host->pmecc, idr, 0xff);
+ pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
+}
+
+static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
+ struct mtd_info *mtd)
+{
+ struct atmel_nand_host *host;
+ int cap, sector_size;
+
+ host = nand->priv = &pmecc_host;
+
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.calculate = NULL;
+ nand->ecc.correct = NULL;
+ nand->ecc.hwctl = NULL;
+
+ cap = host->pmecc_corr_cap = CONFIG_PMECC_CAP;
+ sector_size = host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
+ host->pmecc_index_table_offset = CONFIG_PMECC_INDEX_TABLE_OFFSET;
+
+ printk(KERN_INFO "Initialize PMECC params, cap: %d, sector: %d\n",
+ cap, sector_size);
+
+ host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
+ host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
+ ATMEL_BASE_PMERRLOC;
+ host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
+
+ /* ECC is calculated for the whole page (1 step) */
+ nand->ecc.size = mtd->writesize;
+
+ /* set ECC page size and oob layout */
+ switch (mtd->writesize) {
+ case 2048:
+ case 4096:
+ host->pmecc_degree = PMECC_GF_DIMENSION_13;
+ host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
+ host->pmecc_sector_number = mtd->writesize / sector_size;
+ host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
+ cap, sector_size);
+ host->pmecc_alpha_to = pmecc_get_alpha_to(host);
+ host->pmecc_index_of = host->pmecc_rom_base +
+ host->pmecc_index_table_offset;
+
+ nand->ecc.steps = 1;
+ nand->ecc.bytes = host->pmecc_bytes_per_sector *
+ host->pmecc_sector_number;
+ if (nand->ecc.bytes > mtd->oobsize - 2) {
+ printk(KERN_ERR "No room for ECC bytes\n");
+ return -EINVAL;
+ }
+ pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
+ mtd->oobsize,
+ nand->ecc.bytes);
+ nand->ecc.layout = &atmel_pmecc_oobinfo;
+ break;
+ case 512:
+ case 1024:
+ /* TODO */
+ printk(KERN_ERR "Unsupported page size for PMECC, use Software ECC\n");
+ default:
+ /* page size not handled by HW ECC */
+ /* switching back to soft ECC */
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->ecc.read_page = NULL;
+ nand->ecc.postpad = 0;
+ nand->ecc.prepad = 0;
+ nand->ecc.bytes = 0;
+ return 0;
+ }
+
+ nand->ecc.read_page = atmel_nand_pmecc_read_page;
+ nand->ecc.write_page = atmel_nand_pmecc_write_page;
+
+ atmel_pmecc_core_init(mtd);
+
+ return 0;
+}
+
+#else
+
/* oob layout for large page size
* bad block info is on bytes 0 and 1
* the bytes have to be consecutives to avoid
static int atmel_nand_calculate(struct mtd_info *mtd,
const u_char *dat, unsigned char *ecc_code)
{
- struct nand_chip *nand_chip = mtd->priv;
unsigned int ecc_value;
/* get the first 2 ECC bytes */
u_char *read_ecc, u_char *isnull)
{
struct nand_chip *nand_chip = mtd->priv;
- unsigned int ecc_status, ecc_parity, ecc_mode;
+ unsigned int ecc_status;
unsigned int ecc_word, ecc_bit;
/* get the status from the Status Register */
static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
{
}
-#endif
+
+int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
+{
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.calculate = atmel_nand_calculate;
+ nand->ecc.correct = atmel_nand_correct;
+ nand->ecc.hwctl = atmel_nand_hwctl;
+ nand->ecc.read_page = atmel_nand_read_page;
+ nand->ecc.bytes = 4;
+
+ if (nand->ecc.mode == NAND_ECC_HW) {
+ /* ECC is calculated for the whole page (1 step) */
+ nand->ecc.size = mtd->writesize;
+
+ /* set ECC page size and oob layout */
+ switch (mtd->writesize) {
+ case 512:
+ nand->ecc.layout = &atmel_oobinfo_small;
+ ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
+ ATMEL_ECC_PAGESIZE_528);
+ break;
+ case 1024:
+ nand->ecc.layout = &atmel_oobinfo_large;
+ ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
+ ATMEL_ECC_PAGESIZE_1056);
+ break;
+ case 2048:
+ nand->ecc.layout = &atmel_oobinfo_large;
+ ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
+ ATMEL_ECC_PAGESIZE_2112);
+ break;
+ case 4096:
+ nand->ecc.layout = &atmel_oobinfo_large;
+ ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
+ ATMEL_ECC_PAGESIZE_4224);
+ break;
+ default:
+ /* page size not handled by HW ECC */
+ /* switching back to soft ECC */
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->ecc.calculate = NULL;
+ nand->ecc.correct = NULL;
+ nand->ecc.hwctl = NULL;
+ nand->ecc.read_page = NULL;
+ nand->ecc.postpad = 0;
+ nand->ecc.prepad = 0;
+ nand->ecc.bytes = 0;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+#endif /* CONFIG_ATMEL_NAND_HW_PMECC */
+
+#endif /* CONFIG_ATMEL_NAND_HWECC */
static void at91_nand_hwcontrol(struct mtd_info *mtd,
int cmd, unsigned int ctrl)
}
#endif
-int board_nand_init(struct nand_chip *nand)
-{
-#ifdef CONFIG_ATMEL_NAND_HWECC
- static int chip_nr = 0;
- struct mtd_info *mtd;
+#ifndef CONFIG_SYS_NAND_BASE_LIST
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#endif
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
+
+int atmel_nand_chip_init(int devnum, ulong base_addr)
+{
+ int ret;
+ struct mtd_info *mtd = &nand_info[devnum];
+ struct nand_chip *nand = &nand_chip[devnum];
+
+ mtd->priv = nand;
+ nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CONFIG_SYS_NAND_DBW_16
#endif
nand->chip_delay = 20;
-#ifdef CONFIG_ATMEL_NAND_HWECC
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.calculate = atmel_nand_calculate;
- nand->ecc.correct = atmel_nand_correct;
- nand->ecc.hwctl = atmel_nand_hwctl;
- nand->ecc.read_page = atmel_nand_read_page;
- nand->ecc.bytes = 4;
-#endif
+ ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
+ if (ret)
+ return ret;
#ifdef CONFIG_ATMEL_NAND_HWECC
- mtd = &nand_info[chip_nr++];
- mtd->priv = nand;
-
- /* Detect NAND chips */
- if (nand_scan_ident(mtd, 1, NULL)) {
- printk(KERN_WARNING "NAND Flash not found !\n");
- return -ENXIO;
- }
+#ifdef CONFIG_ATMEL_NAND_HW_PMECC
+ ret = atmel_pmecc_nand_init_params(nand, mtd);
+#else
+ ret = atmel_hwecc_nand_init_param(nand, mtd);
+#endif
+ if (ret)
+ return ret;
+#endif
- if (nand->ecc.mode == NAND_ECC_HW) {
- /* ECC is calculated for the whole page (1 step) */
- nand->ecc.size = mtd->writesize;
+ ret = nand_scan_tail(mtd);
+ if (!ret)
+ nand_register(devnum);
- /* set ECC page size and oob layout */
- switch (mtd->writesize) {
- case 512:
- nand->ecc.layout = &atmel_oobinfo_small;
- ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_528);
- break;
- case 1024:
- nand->ecc.layout = &atmel_oobinfo_large;
- ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_1056);
- break;
- case 2048:
- nand->ecc.layout = &atmel_oobinfo_large;
- ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_2112);
- break;
- case 4096:
- nand->ecc.layout = &atmel_oobinfo_large;
- ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_4224);
- break;
- default:
- /* page size not handled by HW ECC */
- /* switching back to soft ECC */
- nand->ecc.mode = NAND_ECC_SOFT;
- nand->ecc.calculate = NULL;
- nand->ecc.correct = NULL;
- nand->ecc.hwctl = NULL;
- nand->ecc.read_page = NULL;
- nand->ecc.postpad = 0;
- nand->ecc.prepad = 0;
- nand->ecc.bytes = 0;
- break;
- }
- }
-#endif
+ return ret;
+}
- return 0;
+void board_nand_init(void)
+{
+ int i;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ if (atmel_nand_chip_init(i, base_addr[i]))
+ printk(KERN_ERR "atmel_nand: Fail to initialize #%d chip",
+ i);
}
#define ATMEL_ECC_NPR 0x10 /* NParity register */
#define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */
+/* Register access macros for PMECC */
+#define pmecc_readl(addr, reg) \
+ readl(&addr->reg)
+
+#define pmecc_writel(addr, reg, value) \
+ writel((value), &addr->reg)
+
+/* PMECC Register Definitions */
+#define PMECC_MAX_SECTOR_NUM 8
+struct pmecc_regs {
+ u32 cfg; /* 0x00 PMECC Configuration Register */
+ u32 sarea; /* 0x04 PMECC Spare Area Size Register */
+ u32 saddr; /* 0x08 PMECC Start Address Register */
+ u32 eaddr; /* 0x0C PMECC End Address Register */
+ u32 clk; /* 0x10 PMECC Clock Control Register */
+ u32 ctrl; /* 0x14 PMECC Control Register */
+ u32 sr; /* 0x18 PMECC Status Register */
+ u32 ier; /* 0x1C PMECC Interrupt Enable Register */
+ u32 idr; /* 0x20 PMECC Interrupt Disable Register */
+ u32 imr; /* 0x24 PMECC Interrupt Mask Register */
+ u32 isr; /* 0x28 PMECC Interrupt Status Register */
+ u32 reserved0[5]; /* 0x2C-0x3C Reserved */
+
+ /* 0x40 + sector_num * (0x40), Redundancy Registers */
+ struct {
+ u8 ecc[44]; /* PMECC Generated Redundancy Byte Per Sector */
+ u32 reserved1[5];
+ } ecc_port[PMECC_MAX_SECTOR_NUM];
+
+ /* 0x240 + sector_num * (0x40) Remainder Registers */
+ struct {
+ u32 rem[12];
+ u32 reserved2[4];
+ } rem_port[PMECC_MAX_SECTOR_NUM];
+ u32 reserved3[16]; /* 0x440-0x47C Reserved */
+};
+
+/* For PMECC Configuration Register */
+#define PMECC_CFG_BCH_ERR2 (0 << 0)
+#define PMECC_CFG_BCH_ERR4 (1 << 0)
+#define PMECC_CFG_BCH_ERR8 (2 << 0)
+#define PMECC_CFG_BCH_ERR12 (3 << 0)
+#define PMECC_CFG_BCH_ERR24 (4 << 0)
+
+#define PMECC_CFG_SECTOR512 (0 << 4)
+#define PMECC_CFG_SECTOR1024 (1 << 4)
+
+#define PMECC_CFG_PAGE_1SECTOR (0 << 8)
+#define PMECC_CFG_PAGE_2SECTORS (1 << 8)
+#define PMECC_CFG_PAGE_4SECTORS (2 << 8)
+#define PMECC_CFG_PAGE_8SECTORS (3 << 8)
+
+#define PMECC_CFG_READ_OP (0 << 12)
+#define PMECC_CFG_WRITE_OP (1 << 12)
+
+#define PMECC_CFG_SPARE_ENABLE (1 << 16)
+#define PMECC_CFG_SPARE_DISABLE (0 << 16)
+
+#define PMECC_CFG_AUTO_ENABLE (1 << 20)
+#define PMECC_CFG_AUTO_DISABLE (0 << 20)
+
+/* For PMECC Clock Control Register */
+#define PMECC_CLK_133MHZ (2 << 0)
+
+/* For PMECC Control Register */
+#define PMECC_CTRL_RST (1 << 0)
+#define PMECC_CTRL_DATA (1 << 1)
+#define PMECC_CTRL_USER (1 << 2)
+#define PMECC_CTRL_ENABLE (1 << 4)
+#define PMECC_CTRL_DISABLE (1 << 5)
+
+/* For PMECC Status Register */
+#define PMECC_SR_BUSY (1 << 0)
+#define PMECC_SR_ENABLE (1 << 4)
+
+/* PMERRLOC Register Definitions */
+struct pmecc_errloc_regs {
+ u32 elcfg; /* 0x00 Error Location Configuration Register */
+ u32 elprim; /* 0x04 Error Location Primitive Register */
+ u32 elen; /* 0x08 Error Location Enable Register */
+ u32 eldis; /* 0x0C Error Location Disable Register */
+ u32 elsr; /* 0x10 Error Location Status Register */
+ u32 elier; /* 0x14 Error Location Interrupt Enable Register */
+ u32 elidr; /* 0x08 Error Location Interrupt Disable Register */
+ u32 elimr; /* 0x0C Error Location Interrupt Mask Register */
+ u32 elisr; /* 0x20 Error Location Interrupt Status Register */
+ u32 reserved0; /* 0x24 Reserved */
+ u32 sigma[25]; /* 0x28-0x88 Error Location Sigma Registers */
+ u32 el[24]; /* 0x8C-0xE8 Error Location Registers */
+ u32 reserved1[5]; /* 0xEC-0xFC Reserved */
+};
+
+/* For Error Location Configuration Register */
+#define PMERRLOC_ELCFG_SECTOR_512 (0 << 0)
+#define PMERRLOC_ELCFG_SECTOR_1024 (1 << 0)
+#define PMERRLOC_ELCFG_NUM_ERRORS(n) ((n) << 16)
+
+/* For Error Location Disable Register */
+#define PMERRLOC_DISABLE (1 << 0)
+
+/* For Error Location Interrupt Status Register */
+#define PMERRLOC_ERR_NUM_MASK (0x1f << 8)
+#define PMERRLOC_CALC_DONE (1 << 0)
+
+/* Galois field dimension */
+#define PMECC_GF_DIMENSION_13 13
+#define PMECC_GF_DIMENSION_14 14
+
+#define PMECC_INDEX_TABLE_SIZE_512 0x2000
+#define PMECC_INDEX_TABLE_SIZE_1024 0x4000
+
+#define PMECC_MAX_TIMEOUT_US (100 * 1000)
+
#endif
*/
static int mxs_nand_wait_for_bch_complete(void)
{
- struct mx28_bch_regs *bch_regs = (struct mx28_bch_regs *)MXS_BCH_BASE;
+ struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
int timeout = MXS_NAND_BCH_TIMEOUT;
int ret;
- ret = mx28_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
+ ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
BCH_CTRL_COMPLETE_IRQ, timeout);
writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
{
struct nand_chip *chip = mtd->priv;
struct mxs_nand_info *nand_info = chip->priv;
- struct mx28_gpmi_regs *gpmi_regs =
- (struct mx28_gpmi_regs *)MXS_GPMI_BASE;
+ struct mxs_gpmi_regs *gpmi_regs =
+ (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
uint32_t tmp;
tmp = readl(&gpmi_regs->hw_gpmi_stat);
{
struct nand_chip *nand = mtd->priv;
struct mxs_nand_info *nand_info = nand->priv;
- struct mx28_bch_regs *bch_regs = (struct mx28_bch_regs *)MXS_BCH_BASE;
+ struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
uint32_t tmp;
/* Configure BCH and set NFC geometry */
- mx28_reset_block(&bch_regs->hw_bch_ctrl_reg);
+ mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
/* Configure layout 0 */
tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
*/
int mxs_nand_init(struct mxs_nand_info *info)
{
- struct mx28_gpmi_regs *gpmi_regs =
- (struct mx28_gpmi_regs *)MXS_GPMI_BASE;
+ struct mxs_gpmi_regs *gpmi_regs =
+ (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
int i = 0, j;
info->desc = malloc(sizeof(struct mxs_dma_desc *) *
}
/* Reset the GPMI block. */
- mx28_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
+ mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
/*
* Choose NAND mode, set IRQ polarity, disable write protection and
nand->ecc.mode = NAND_ECC_SOFT;
/* Use mtd default settings */
nand->ecc.layout = NULL;
+ nand->ecc.size = 0;
printf("SW ECC selected\n");
}
COBJS-$(CONFIG_SMC911X) += smc911x.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
COBJS-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
+COBJS-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
COBJS-$(CONFIG_FMAN_ENET) += fsl_mdio.o
COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o
COBJS-$(CONFIG_ULI526X) += uli526x.o
--- /dev/null
+/*
+ * CPSW Ethernet Switch Driver
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include <net.h>
+#include <netdev.h>
+#include <cpsw.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <phy.h>
+
+#define BITMASK(bits) (BIT(bits) - 1)
+#define PHY_REG_MASK 0x1f
+#define PHY_ID_MASK 0x1f
+#define NUM_DESCS (PKTBUFSRX * 2)
+#define PKT_MIN 60
+#define PKT_MAX (1500 + 14 + 4 + 4)
+#define CLEAR_BIT 1
+#define GIGABITEN BIT(7)
+#define FULLDUPLEXEN BIT(0)
+#define MIIEN BIT(15)
+
+/* DMA Registers */
+#define CPDMA_TXCONTROL 0x004
+#define CPDMA_RXCONTROL 0x014
+#define CPDMA_SOFTRESET 0x01c
+#define CPDMA_RXFREE 0x0e0
+#define CPDMA_TXHDP_VER1 0x100
+#define CPDMA_TXHDP_VER2 0x200
+#define CPDMA_RXHDP_VER1 0x120
+#define CPDMA_RXHDP_VER2 0x220
+#define CPDMA_TXCP_VER1 0x140
+#define CPDMA_TXCP_VER2 0x240
+#define CPDMA_RXCP_VER1 0x160
+#define CPDMA_RXCP_VER2 0x260
+
+#define CPDMA_RAM_ADDR 0x4a102000
+
+/* Descriptor mode bits */
+#define CPDMA_DESC_SOP BIT(31)
+#define CPDMA_DESC_EOP BIT(30)
+#define CPDMA_DESC_OWNER BIT(29)
+#define CPDMA_DESC_EOQ BIT(28)
+
+/*
+ * This timeout definition is a worst-case ultra defensive measure against
+ * unexpected controller lock ups. Ideally, we should never ever hit this
+ * scenario in practice.
+ */
+#define MDIO_TIMEOUT 100 /* msecs */
+#define CPDMA_TIMEOUT 100 /* msecs */
+
+struct cpsw_mdio_regs {
+ u32 version;
+ u32 control;
+#define CONTROL_IDLE BIT(31)
+#define CONTROL_ENABLE BIT(30)
+
+ u32 alive;
+ u32 link;
+ u32 linkintraw;
+ u32 linkintmasked;
+ u32 __reserved_0[2];
+ u32 userintraw;
+ u32 userintmasked;
+ u32 userintmaskset;
+ u32 userintmaskclr;
+ u32 __reserved_1[20];
+
+ struct {
+ u32 access;
+ u32 physel;
+#define USERACCESS_GO BIT(31)
+#define USERACCESS_WRITE BIT(30)
+#define USERACCESS_ACK BIT(29)
+#define USERACCESS_READ (0)
+#define USERACCESS_DATA (0xffff)
+ } user[0];
+};
+
+struct cpsw_regs {
+ u32 id_ver;
+ u32 control;
+ u32 soft_reset;
+ u32 stat_port_en;
+ u32 ptype;
+};
+
+struct cpsw_slave_regs {
+ u32 max_blks;
+ u32 blk_cnt;
+ u32 flow_thresh;
+ u32 port_vlan;
+ u32 tx_pri_map;
+ u32 gap_thresh;
+ u32 sa_lo;
+ u32 sa_hi;
+};
+
+struct cpsw_host_regs {
+ u32 max_blks;
+ u32 blk_cnt;
+ u32 flow_thresh;
+ u32 port_vlan;
+ u32 tx_pri_map;
+ u32 cpdma_tx_pri_map;
+ u32 cpdma_rx_chan_map;
+};
+
+struct cpsw_sliver_regs {
+ u32 id_ver;
+ u32 mac_control;
+ u32 mac_status;
+ u32 soft_reset;
+ u32 rx_maxlen;
+ u32 __reserved_0;
+ u32 rx_pause;
+ u32 tx_pause;
+ u32 __reserved_1;
+ u32 rx_pri_map;
+};
+
+#define ALE_ENTRY_BITS 68
+#define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
+
+/* ALE Registers */
+#define ALE_CONTROL 0x08
+#define ALE_UNKNOWNVLAN 0x18
+#define ALE_TABLE_CONTROL 0x20
+#define ALE_TABLE 0x34
+#define ALE_PORTCTL 0x40
+
+#define ALE_TABLE_WRITE BIT(31)
+
+#define ALE_TYPE_FREE 0
+#define ALE_TYPE_ADDR 1
+#define ALE_TYPE_VLAN 2
+#define ALE_TYPE_VLAN_ADDR 3
+
+#define ALE_UCAST_PERSISTANT 0
+#define ALE_UCAST_UNTOUCHED 1
+#define ALE_UCAST_OUI 2
+#define ALE_UCAST_TOUCHED 3
+
+#define ALE_MCAST_FWD 0
+#define ALE_MCAST_BLOCK_LEARN_FWD 1
+#define ALE_MCAST_FWD_LEARN 2
+#define ALE_MCAST_FWD_2 3
+
+enum cpsw_ale_port_state {
+ ALE_PORT_STATE_DISABLE = 0x00,
+ ALE_PORT_STATE_BLOCK = 0x01,
+ ALE_PORT_STATE_LEARN = 0x02,
+ ALE_PORT_STATE_FORWARD = 0x03,
+};
+
+/* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
+#define ALE_SECURE 1
+#define ALE_BLOCKED 2
+
+struct cpsw_slave {
+ struct cpsw_slave_regs *regs;
+ struct cpsw_sliver_regs *sliver;
+ int slave_num;
+ u32 mac_control;
+ struct cpsw_slave_data *data;
+};
+
+struct cpdma_desc {
+ /* hardware fields */
+ u32 hw_next;
+ u32 hw_buffer;
+ u32 hw_len;
+ u32 hw_mode;
+ /* software fields */
+ u32 sw_buffer;
+ u32 sw_len;
+};
+
+struct cpdma_chan {
+ struct cpdma_desc *head, *tail;
+ void *hdp, *cp, *rxfree;
+};
+
+#define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)
+#define desc_read(desc, fld) __raw_readl(&(desc)->fld)
+#define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld))
+
+#define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
+#define chan_read(chan, fld) __raw_readl((chan)->fld)
+#define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
+
+#define for_each_slave(slave, priv) \
+ for (slave = (priv)->slaves; slave != (priv)->slaves + \
+ (priv)->data.slaves; slave++)
+
+struct cpsw_priv {
+ struct eth_device *dev;
+ struct cpsw_platform_data data;
+ int host_port;
+
+ struct cpsw_regs *regs;
+ void *dma_regs;
+ struct cpsw_host_regs *host_port_regs;
+ void *ale_regs;
+
+ struct cpdma_desc *descs;
+ struct cpdma_desc *desc_free;
+ struct cpdma_chan rx_chan, tx_chan;
+
+ struct cpsw_slave *slaves;
+ struct phy_device *phydev;
+ struct mii_dev *bus;
+};
+
+static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
+{
+ int idx;
+
+ idx = start / 32;
+ start -= idx * 32;
+ idx = 2 - idx; /* flip */
+ return (ale_entry[idx] >> start) & BITMASK(bits);
+}
+
+static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
+ u32 value)
+{
+ int idx;
+
+ value &= BITMASK(bits);
+ idx = start / 32;
+ start -= idx * 32;
+ idx = 2 - idx; /* flip */
+ ale_entry[idx] &= ~(BITMASK(bits) << start);
+ ale_entry[idx] |= (value << start);
+}
+
+#define DEFINE_ALE_FIELD(name, start, bits) \
+static inline int cpsw_ale_get_##name(u32 *ale_entry) \
+{ \
+ return cpsw_ale_get_field(ale_entry, start, bits); \
+} \
+static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
+{ \
+ cpsw_ale_set_field(ale_entry, start, bits, value); \
+}
+
+DEFINE_ALE_FIELD(entry_type, 60, 2)
+DEFINE_ALE_FIELD(mcast_state, 62, 2)
+DEFINE_ALE_FIELD(port_mask, 66, 3)
+DEFINE_ALE_FIELD(ucast_type, 62, 2)
+DEFINE_ALE_FIELD(port_num, 66, 2)
+DEFINE_ALE_FIELD(blocked, 65, 1)
+DEFINE_ALE_FIELD(secure, 64, 1)
+DEFINE_ALE_FIELD(mcast, 40, 1)
+
+/* The MAC address field in the ALE entry cannot be macroized as above */
+static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
+{
+ int i;
+
+ for (i = 0; i < 6; i++)
+ addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
+}
+
+static inline void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr)
+{
+ int i;
+
+ for (i = 0; i < 6; i++)
+ cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
+}
+
+static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
+{
+ int i;
+
+ __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
+
+ for (i = 0; i < ALE_ENTRY_WORDS; i++)
+ ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
+
+ return idx;
+}
+
+static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
+{
+ int i;
+
+ for (i = 0; i < ALE_ENTRY_WORDS; i++)
+ __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
+
+ __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
+
+ return idx;
+}
+
+static int cpsw_ale_match_addr(struct cpsw_priv *priv, u8* addr)
+{
+ u32 ale_entry[ALE_ENTRY_WORDS];
+ int type, idx;
+
+ for (idx = 0; idx < priv->data.ale_entries; idx++) {
+ u8 entry_addr[6];
+
+ cpsw_ale_read(priv, idx, ale_entry);
+ type = cpsw_ale_get_entry_type(ale_entry);
+ if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
+ continue;
+ cpsw_ale_get_addr(ale_entry, entry_addr);
+ if (memcmp(entry_addr, addr, 6) == 0)
+ return idx;
+ }
+ return -ENOENT;
+}
+
+static int cpsw_ale_match_free(struct cpsw_priv *priv)
+{
+ u32 ale_entry[ALE_ENTRY_WORDS];
+ int type, idx;
+
+ for (idx = 0; idx < priv->data.ale_entries; idx++) {
+ cpsw_ale_read(priv, idx, ale_entry);
+ type = cpsw_ale_get_entry_type(ale_entry);
+ if (type == ALE_TYPE_FREE)
+ return idx;
+ }
+ return -ENOENT;
+}
+
+static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
+{
+ u32 ale_entry[ALE_ENTRY_WORDS];
+ int type, idx;
+
+ for (idx = 0; idx < priv->data.ale_entries; idx++) {
+ cpsw_ale_read(priv, idx, ale_entry);
+ type = cpsw_ale_get_entry_type(ale_entry);
+ if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
+ continue;
+ if (cpsw_ale_get_mcast(ale_entry))
+ continue;
+ type = cpsw_ale_get_ucast_type(ale_entry);
+ if (type != ALE_UCAST_PERSISTANT &&
+ type != ALE_UCAST_OUI)
+ return idx;
+ }
+ return -ENOENT;
+}
+
+static int cpsw_ale_add_ucast(struct cpsw_priv *priv, u8 *addr,
+ int port, int flags)
+{
+ u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ int idx;
+
+ cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
+ cpsw_ale_set_addr(ale_entry, addr);
+ cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
+ cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
+ cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
+ cpsw_ale_set_port_num(ale_entry, port);
+
+ idx = cpsw_ale_match_addr(priv, addr);
+ if (idx < 0)
+ idx = cpsw_ale_match_free(priv);
+ if (idx < 0)
+ idx = cpsw_ale_find_ageable(priv);
+ if (idx < 0)
+ return -ENOMEM;
+
+ cpsw_ale_write(priv, idx, ale_entry);
+ return 0;
+}
+
+static int cpsw_ale_add_mcast(struct cpsw_priv *priv, u8 *addr, int port_mask)
+{
+ u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
+ int idx, mask;
+
+ idx = cpsw_ale_match_addr(priv, addr);
+ if (idx >= 0)
+ cpsw_ale_read(priv, idx, ale_entry);
+
+ cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
+ cpsw_ale_set_addr(ale_entry, addr);
+ cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
+
+ mask = cpsw_ale_get_port_mask(ale_entry);
+ port_mask |= mask;
+ cpsw_ale_set_port_mask(ale_entry, port_mask);
+
+ if (idx < 0)
+ idx = cpsw_ale_match_free(priv);
+ if (idx < 0)
+ idx = cpsw_ale_find_ageable(priv);
+ if (idx < 0)
+ return -ENOMEM;
+
+ cpsw_ale_write(priv, idx, ale_entry);
+ return 0;
+}
+
+static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
+{
+ u32 tmp, mask = BIT(bit);
+
+ tmp = __raw_readl(priv->ale_regs + ALE_CONTROL);
+ tmp &= ~mask;
+ tmp |= val ? mask : 0;
+ __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
+}
+
+#define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val)
+#define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val)
+#define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val)
+
+static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
+ int val)
+{
+ int offset = ALE_PORTCTL + 4 * port;
+ u32 tmp, mask = 0x3;
+
+ tmp = __raw_readl(priv->ale_regs + offset);
+ tmp &= ~mask;
+ tmp |= val & mask;
+ __raw_writel(tmp, priv->ale_regs + offset);
+}
+
+static struct cpsw_mdio_regs *mdio_regs;
+
+/* wait until hardware is ready for another user access */
+static inline u32 wait_for_user_access(void)
+{
+ u32 reg = 0;
+ int timeout = MDIO_TIMEOUT;
+
+ while (timeout-- &&
+ ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO))
+ udelay(10);
+
+ if (timeout == -1) {
+ printf("wait_for_user_access Timeout\n");
+ return -ETIMEDOUT;
+ }
+ return reg;
+}
+
+/* wait until hardware state machine is idle */
+static inline void wait_for_idle(void)
+{
+ int timeout = MDIO_TIMEOUT;
+
+ while (timeout-- &&
+ ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0))
+ udelay(10);
+
+ if (timeout == -1)
+ printf("wait_for_idle Timeout\n");
+}
+
+static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
+ int dev_addr, int phy_reg)
+{
+ unsigned short data;
+ u32 reg;
+
+ if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
+ return -EINVAL;
+
+ wait_for_user_access();
+ reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
+ (phy_id << 16));
+ __raw_writel(reg, &mdio_regs->user[0].access);
+ reg = wait_for_user_access();
+
+ data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
+ return data;
+}
+
+static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
+ int phy_reg, u16 data)
+{
+ u32 reg;
+
+ if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
+ return -EINVAL;
+
+ wait_for_user_access();
+ reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
+ (phy_id << 16) | (data & USERACCESS_DATA));
+ __raw_writel(reg, &mdio_regs->user[0].access);
+ wait_for_user_access();
+
+ return 0;
+}
+
+static void cpsw_mdio_init(char *name, u32 mdio_base, u32 div)
+{
+ struct mii_dev *bus = mdio_alloc();
+
+ mdio_regs = (struct cpsw_mdio_regs *)mdio_base;
+
+ /* set enable and clock divider */
+ __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control);
+
+ /*
+ * wait for scan logic to settle:
+ * the scan time consists of (a) a large fixed component, and (b) a
+ * small component that varies with the mii bus frequency. These
+ * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
+ * silicon. Since the effect of (b) was found to be largely
+ * negligible, we keep things simple here.
+ */
+ udelay(1000);
+
+ bus->read = cpsw_mdio_read;
+ bus->write = cpsw_mdio_write;
+ sprintf(bus->name, name);
+
+ mdio_register(bus);
+}
+
+/* Set a self-clearing bit in a register, and wait for it to clear */
+static inline void setbit_and_wait_for_clear32(void *addr)
+{
+ __raw_writel(CLEAR_BIT, addr);
+ while (__raw_readl(addr) & CLEAR_BIT)
+ ;
+}
+
+#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
+ ((mac)[2] << 16) | ((mac)[3] << 24))
+#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
+
+static void cpsw_set_slave_mac(struct cpsw_slave *slave,
+ struct cpsw_priv *priv)
+{
+ __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
+ __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
+}
+
+static void cpsw_slave_update_link(struct cpsw_slave *slave,
+ struct cpsw_priv *priv, int *link)
+{
+ struct phy_device *phy = priv->phydev;
+ u32 mac_control = 0;
+
+ phy_startup(phy);
+ *link = phy->link;
+
+ if (*link) { /* link up */
+ mac_control = priv->data.mac_control;
+ if (phy->speed == 1000)
+ mac_control |= GIGABITEN;
+ if (phy->duplex == DUPLEX_FULL)
+ mac_control |= FULLDUPLEXEN;
+ if (phy->speed == 100)
+ mac_control |= MIIEN;
+ }
+
+ if (mac_control == slave->mac_control)
+ return;
+
+ if (mac_control) {
+ printf("link up on port %d, speed %d, %s duplex\n",
+ slave->slave_num, phy->speed,
+ (phy->duplex == DUPLEX_FULL) ? "full" : "half");
+ } else {
+ printf("link down on port %d\n", slave->slave_num);
+ }
+
+ __raw_writel(mac_control, &slave->sliver->mac_control);
+ slave->mac_control = mac_control;
+}
+
+static int cpsw_update_link(struct cpsw_priv *priv)
+{
+ int link = 0;
+ struct cpsw_slave *slave;
+
+ for_each_slave(slave, priv)
+ cpsw_slave_update_link(slave, priv, &link);
+
+ return link;
+}
+
+static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
+{
+ if (priv->host_port == 0)
+ return slave_num + 1;
+ else
+ return slave_num;
+}
+
+static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
+{
+ u32 slave_port;
+
+ setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
+
+ /* setup priority mapping */
+ __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
+ __raw_writel(0x33221100, &slave->regs->tx_pri_map);
+
+ /* setup max packet size, and mac address */
+ __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
+ cpsw_set_slave_mac(slave, priv);
+
+ slave->mac_control = 0; /* no link yet */
+
+ /* enable forwarding */
+ slave_port = cpsw_get_slave_port(priv, slave->slave_num);
+ cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
+
+ cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port);
+}
+
+static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
+{
+ struct cpdma_desc *desc = priv->desc_free;
+
+ if (desc)
+ priv->desc_free = desc_read_ptr(desc, hw_next);
+ return desc;
+}
+
+static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
+{
+ if (desc) {
+ desc_write(desc, hw_next, priv->desc_free);
+ priv->desc_free = desc;
+ }
+}
+
+static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
+ void *buffer, int len)
+{
+ struct cpdma_desc *desc, *prev;
+ u32 mode;
+
+ desc = cpdma_desc_alloc(priv);
+ if (!desc)
+ return -ENOMEM;
+
+ if (len < PKT_MIN)
+ len = PKT_MIN;
+
+ mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
+
+ desc_write(desc, hw_next, 0);
+ desc_write(desc, hw_buffer, buffer);
+ desc_write(desc, hw_len, len);
+ desc_write(desc, hw_mode, mode | len);
+ desc_write(desc, sw_buffer, buffer);
+ desc_write(desc, sw_len, len);
+
+ if (!chan->head) {
+ /* simple case - first packet enqueued */
+ chan->head = desc;
+ chan->tail = desc;
+ chan_write(chan, hdp, desc);
+ goto done;
+ }
+
+ /* not the first packet - enqueue at the tail */
+ prev = chan->tail;
+ desc_write(prev, hw_next, desc);
+ chan->tail = desc;
+
+ /* next check if EOQ has been triggered already */
+ if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
+ chan_write(chan, hdp, desc);
+
+done:
+ if (chan->rxfree)
+ chan_write(chan, rxfree, 1);
+ return 0;
+}
+
+static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
+ void **buffer, int *len)
+{
+ struct cpdma_desc *desc = chan->head;
+ u32 status;
+
+ if (!desc)
+ return -ENOENT;
+
+ status = desc_read(desc, hw_mode);
+
+ if (len)
+ *len = status & 0x7ff;
+
+ if (buffer)
+ *buffer = desc_read_ptr(desc, sw_buffer);
+
+ if (status & CPDMA_DESC_OWNER) {
+ if (chan_read(chan, hdp) == 0) {
+ if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
+ chan_write(chan, hdp, desc);
+ }
+
+ return -EBUSY;
+ }
+
+ chan->head = desc_read_ptr(desc, hw_next);
+ chan_write(chan, cp, desc);
+
+ cpdma_desc_free(priv, desc);
+ return 0;
+}
+
+static int cpsw_init(struct eth_device *dev, bd_t *bis)
+{
+ struct cpsw_priv *priv = dev->priv;
+ struct cpsw_slave *slave;
+ int i, ret;
+
+ /* soft reset the controller and initialize priv */
+ setbit_and_wait_for_clear32(&priv->regs->soft_reset);
+
+ /* initialize and reset the address lookup engine */
+ cpsw_ale_enable(priv, 1);
+ cpsw_ale_clear(priv, 1);
+ cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
+
+ /* setup host port priority mapping */
+ __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
+ __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
+
+ /* disable priority elevation and enable statistics on all ports */
+ __raw_writel(0, &priv->regs->ptype);
+
+ /* enable statistics collection only on the host port */
+ __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
+
+ cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
+
+ cpsw_ale_add_ucast(priv, priv->dev->enetaddr, priv->host_port,
+ ALE_SECURE);
+ cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << priv->host_port);
+
+ for_each_slave(slave, priv)
+ cpsw_slave_init(slave, priv);
+
+ cpsw_update_link(priv);
+
+ /* init descriptor pool */
+ for (i = 0; i < NUM_DESCS; i++) {
+ desc_write(&priv->descs[i], hw_next,
+ (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
+ }
+ priv->desc_free = &priv->descs[0];
+
+ /* initialize channels */
+ if (priv->data.version == CPSW_CTRL_VERSION_2) {
+ memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
+ priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
+ priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
+ priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
+
+ memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
+ priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
+ priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
+ } else {
+ memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
+ priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
+ priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
+ priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
+
+ memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
+ priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
+ priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
+ }
+
+ /* clear dma state */
+ setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
+
+ if (priv->data.version == CPSW_CTRL_VERSION_2) {
+ for (i = 0; i < priv->data.channels; i++) {
+ __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
+ * i);
+ }
+ } else {
+ for (i = 0; i < priv->data.channels; i++) {
+ __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
+ * i);
+ __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
+ * i);
+
+ }
+ }
+
+ __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
+ __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
+
+ /* submit rx descs */
+ for (i = 0; i < PKTBUFSRX; i++) {
+ ret = cpdma_submit(priv, &priv->rx_chan, NetRxPackets[i],
+ PKTSIZE);
+ if (ret < 0) {
+ printf("error %d submitting rx desc\n", ret);
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static void cpsw_halt(struct eth_device *dev)
+{
+ struct cpsw_priv *priv = dev->priv;
+
+ writel(0, priv->dma_regs + CPDMA_TXCONTROL);
+ writel(0, priv->dma_regs + CPDMA_RXCONTROL);
+
+ /* soft reset the controller and initialize priv */
+ setbit_and_wait_for_clear32(&priv->regs->soft_reset);
+
+ /* clear dma state */
+ setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
+
+ priv->data.control(0);
+}
+
+static int cpsw_send(struct eth_device *dev, void *packet, int length)
+{
+ struct cpsw_priv *priv = dev->priv;
+ void *buffer;
+ int len;
+ int timeout = CPDMA_TIMEOUT;
+
+ if (!cpsw_update_link(priv))
+ return -EIO;
+
+ flush_dcache_range((unsigned long)packet,
+ (unsigned long)packet + length);
+
+ /* first reap completed packets */
+ while (timeout-- &&
+ (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0))
+ ;
+
+ if (timeout == -1) {
+ printf("cpdma_process timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ return cpdma_submit(priv, &priv->tx_chan, packet, length);
+}
+
+static int cpsw_recv(struct eth_device *dev)
+{
+ struct cpsw_priv *priv = dev->priv;
+ void *buffer;
+ int len;
+
+ cpsw_update_link(priv);
+
+ while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) {
+ invalidate_dcache_range((unsigned long)buffer,
+ (unsigned long)buffer + PKTSIZE_ALIGN);
+ NetReceive(buffer, len);
+ cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE);
+ }
+
+ return 0;
+}
+
+static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
+ struct cpsw_priv *priv)
+{
+ void *regs = priv->regs;
+ struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
+ slave->slave_num = slave_num;
+ slave->data = data;
+ slave->regs = regs + data->slave_reg_ofs;
+ slave->sliver = regs + data->sliver_reg_ofs;
+}
+
+static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
+{
+ struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv;
+ struct phy_device *phydev;
+ u32 supported = (SUPPORTED_10baseT_Half |
+ SUPPORTED_10baseT_Full |
+ SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full |
+ SUPPORTED_1000baseT_Full);
+
+ phydev = phy_connect(priv->bus, 0, dev, slave->data->phy_if);
+
+ phydev->supported &= supported;
+ phydev->advertising = phydev->supported;
+
+ priv->phydev = phydev;
+ phy_config(phydev);
+
+ return 1;
+}
+
+int cpsw_register(struct cpsw_platform_data *data)
+{
+ struct cpsw_priv *priv;
+ struct cpsw_slave *slave;
+ void *regs = (void *)data->cpsw_base;
+ struct eth_device *dev;
+
+ dev = calloc(sizeof(*dev), 1);
+ if (!dev)
+ return -ENOMEM;
+
+ priv = calloc(sizeof(*priv), 1);
+ if (!priv) {
+ free(dev);
+ return -ENOMEM;
+ }
+
+ priv->data = *data;
+ priv->dev = dev;
+
+ priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
+ if (!priv->slaves) {
+ free(dev);
+ free(priv);
+ return -ENOMEM;
+ }
+
+ priv->descs = (void *)CPDMA_RAM_ADDR;
+ priv->host_port = data->host_port_num;
+ priv->regs = regs;
+ priv->host_port_regs = regs + data->host_port_reg_ofs;
+ priv->dma_regs = regs + data->cpdma_reg_ofs;
+ priv->ale_regs = regs + data->ale_reg_ofs;
+
+ int idx = 0;
+
+ for_each_slave(slave, priv) {
+ cpsw_slave_setup(slave, idx, priv);
+ idx = idx + 1;
+ }
+
+ strcpy(dev->name, "cpsw");
+ dev->iobase = 0;
+ dev->init = cpsw_init;
+ dev->halt = cpsw_halt;
+ dev->send = cpsw_send;
+ dev->recv = cpsw_recv;
+ dev->priv = priv;
+
+ eth_register(dev);
+
+ cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div);
+ priv->bus = miiphy_get_dev_by_name(dev->name);
+ for_each_slave(slave, priv)
+ cpsw_phy_init(dev, slave);
+
+ return 1;
+}
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
- defined(CONFIG_AT91SAM9XE)
+ defined(CONFIG_AT91SAM9XE) || defined(CONFIG_AT91SAM9X5)
macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, 0);
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
- defined(CONFIG_AT91SAM9XE)
+ defined(CONFIG_AT91SAM9XE) || defined(CONFIG_AT91SAM9X5)
macb_writel(macb, USRIO, MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, MACB_BIT(MII));
void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
{
pci_addr_t pci_bus_addr;
- u32 bar_response;
+ pci_addr_t bar_response;
/* read BAR address */
pci_read_config_dword(pdev, bar, &bar_response);
- pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
+ pci_bus_addr = bar_response & ~0xf;
/*
* Pass "0" as the length argument to pci_bus_to_virt. The arg
*phose = hose;
}
-struct pci_controller *pci_bus_to_hose (int bus)
+struct pci_controller *pci_bus_to_hose(int bus)
{
struct pci_controller *hose;
- for (hose = hose_head; hose; hose = hose->next)
+ for (hose = hose_head; hose; hose = hose->next) {
if (bus >= hose->first_busno && bus <= hose->last_busno)
return hose;
+ }
printf("pci_bus_to_hose() failed\n");
return NULL;
pci_dev_t bdf;
int i, bus, found_multi = 0;
- for (hose = hose_head; hose; hose = hose->next)
- {
+ for (hose = hose_head; hose; hose = hose->next) {
#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
#else
for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
#endif
- for (bdf = PCI_BDF(bus,0,0);
+ for (bdf = PCI_BDF(bus, 0, 0);
#if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
- bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
+ bdf < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
+ PCI_MAX_PCI_FUNCTIONS - 1);
#else
- bdf < PCI_BDF(bus+1,0,0);
+ bdf < PCI_BDF(bus + 1, 0, 0);
#endif
- bdf += PCI_BDF(0,0,1))
- {
+ bdf += PCI_BDF(0, 0, 1)) {
if (!PCI_FUNC(bdf)) {
pci_read_config_byte(bdf,
PCI_HEADER_TYPE,
PCI_DEVICE_ID,
&device);
- for (i=0; ids[i].vendor != 0; i++)
+ for (i = 0; ids[i].vendor != 0; i++) {
if (vendor == ids[i].vendor &&
- device == ids[i].device)
- {
+ device == ids[i].device) {
if (index <= 0)
return bdf;
index--;
}
+ }
}
}
- return (-1);
+ return -1;
}
pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
*
*/
-int __pci_hose_phys_to_bus (struct pci_controller *hose,
+int __pci_hose_phys_to_bus(struct pci_controller *hose,
phys_addr_t phys_addr,
unsigned long flags,
unsigned long skip_mask,
int ret;
if (!hose) {
- puts ("pci_hose_phys_to_bus: invalid hose\n");
+ puts("pci_hose_phys_to_bus: invalid hose\n");
return bus_addr;
}
- /* if PCI_REGION_MEM is set we do a two pass search with preference
- * on matches that don't have PCI_REGION_SYS_MEMORY set */
+ /*
+ * if PCI_REGION_MEM is set we do a two pass search with preference
+ * on matches that don't have PCI_REGION_SYS_MEMORY set
+ */
if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
ret = __pci_hose_phys_to_bus(hose, phys_addr,
flags, PCI_REGION_SYS_MEMORY, &bus_addr);
ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
if (ret)
- puts ("pci_hose_phys_to_bus: invalid physical address\n");
+ puts("pci_hose_phys_to_bus: invalid physical address\n");
return bus_addr;
}
-int __pci_hose_bus_to_phys (struct pci_controller *hose,
+int __pci_hose_bus_to_phys(struct pci_controller *hose,
pci_addr_t bus_addr,
unsigned long flags,
unsigned long skip_mask,
int ret;
if (!hose) {
- puts ("pci_hose_bus_to_phys: invalid hose\n");
+ puts("pci_hose_bus_to_phys: invalid hose\n");
return phys_addr;
}
- /* if PCI_REGION_MEM is set we do a two pass search with preference
- * on matches that don't have PCI_REGION_SYS_MEMORY set */
+ /*
+ * if PCI_REGION_MEM is set we do a two pass search with preference
+ * on matches that don't have PCI_REGION_SYS_MEMORY set
+ */
if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
ret = __pci_hose_bus_to_phys(hose, bus_addr,
flags, PCI_REGION_SYS_MEMORY, &phys_addr);
ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
if (ret)
- puts ("pci_hose_bus_to_phys: invalid physical address\n");
+ puts("pci_hose_bus_to_phys: invalid physical address\n");
return phys_addr;
}
pci_addr_t mem,
unsigned long command)
{
- unsigned int bar_response, old_command;
+ pci_addr_t bar_response;
+ unsigned int old_command;
pci_addr_t bar_value;
pci_size_t bar_size;
unsigned char pin;
int bar, found_mem64;
- debug ("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n",
- io, (u64)mem, command);
+ debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
+ (u64)mem, command);
- pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
+ pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
- pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
- pci_hose_read_config_dword (hose, dev, bar, &bar_response);
+ pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
+ pci_hose_read_config_dword(hose, dev, bar, &bar_response);
if (!bar_response)
continue;
PCI_BASE_ADDRESS_MEM_TYPE_64) {
u32 bar_response_upper;
u64 bar64;
- pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
- pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
+ pci_hose_write_config_dword(hose, dev, bar + 4,
+ 0xffffffff);
+ pci_hose_read_config_dword(hose, dev, bar + 4,
+ &bar_response_upper);
bar64 = ((u64)bar_response_upper << 32) | bar_response;
if (found_mem64) {
bar += 4;
#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
+ pci_hose_write_config_dword(hose, dev, bar,
+ (u32)(bar_value >> 32));
#else
- pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
+ pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
#endif
}
}
/* Configure Cache Line Size Register */
- pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
/* Configure Latency Timer */
- pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
/* Disable interrupt line, if device says it wants to use interrupts */
- pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
+ pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
if (pin != 0) {
- pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff);
}
- pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
- pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
+ pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
+ pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
(old_command & 0xffff0000) | command);
return 0;
pci_dev_t dev,
struct pci_config_table *entry)
{
- pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
+ pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
+ entry->priv[2]);
}
void pci_cfgfunc_do_nothing(struct pci_controller *hose,
}
/*
- *
- */
-
-/* HJF: Changed this to return int. I think this is required
+ * HJF: Changed this to return int. I think this is required
* to get the correct result when scanning bridges
*/
extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
int pci_hose_scan_bus(struct pci_controller *hose, int bus)
{
- unsigned int sub_bus, found_multi=0;
+ unsigned int sub_bus, found_multi = 0;
unsigned short vendor, device, class;
unsigned char header_type;
+#ifndef CONFIG_PCI_PNP
struct pci_config_table *cfg;
+#endif
pci_dev_t dev;
#ifdef CONFIG_PCI_SCAN_SHOW
static int indent = 0;
sub_bus = bus;
for (dev = PCI_BDF(bus,0,0);
- dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
- dev += PCI_BDF(0,0,1)) {
+ dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
+ PCI_MAX_PCI_FUNCTIONS - 1);
+ dev += PCI_BDF(0, 0, 1)) {
if (pci_skip_dev(hose, dev))
continue;
if (!PCI_FUNC(dev))
found_multi = header_type & 0x80;
- debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
- PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
+ debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
+ PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
}
#endif
+#ifdef CONFIG_PCI_PNP
+ sub_bus = max(pciauto_config_device(hose, dev), sub_bus);
+#else
cfg = pci_find_config(hose, class, vendor, device,
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
if (cfg) {
cfg->config_device(hose, dev, cfg);
sub_bus = max(sub_bus, hose->current_busno);
-#ifdef CONFIG_PCI_PNP
- } else {
- int n = pciauto_config_device(hose, dev);
-
- sub_bus = max(sub_bus, n);
-#endif
}
+#endif
#ifdef CONFIG_PCI_SCAN_SHOW
indent--;
}
#endif /* CONFIG_PCI_BOOTDELAY */
- /* Start scan at current_busno.
+ /*
+ * Start scan at current_busno.
* PCIe will start scan at first_busno+1.
*/
- /* For legacy support, ensure current>=first */
+ /* For legacy support, ensure current >= first */
if (hose->first_busno > hose->current_busno)
hose->current_busno = hose->first_busno;
#ifdef CONFIG_PCI_PNP
*
*/
-void pciauto_region_init(struct pci_region* res)
+void pciauto_region_init(struct pci_region *res)
{
/*
* Avoid allocating PCI resources from address 0 -- this is illegal
res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
}
-int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar)
+int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
+ pci_addr_t *bar)
{
pci_addr_t addr;
struct pci_region *prefetch,
struct pci_region *io)
{
- unsigned int bar_response;
- pci_addr_t bar_value;
+ pci_addr_t bar_response;
pci_size_t bar_size;
- unsigned int cmdstat = 0;
- struct pci_region *bar_res;
+ u16 cmdstat = 0;
int bar, bar_nr = 0;
+#ifndef CONFIG_PCI_ENUM_ONLY
+ pci_addr_t bar_value;
+ struct pci_region *bar_res;
int found_mem64 = 0;
+#endif
- pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+ pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
- for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
+ for (bar = PCI_BASE_ADDRESS_0;
+ bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
/* Tickle the BAR and get the response */
+#ifndef CONFIG_PCI_ENUM_ONLY
pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
+#endif
pci_hose_read_config_dword(hose, dev, bar, &bar_response);
/* If BAR is not implemented go to the next BAR */
if (!bar_response)
continue;
+#ifndef CONFIG_PCI_ENUM_ONLY
found_mem64 = 0;
+#endif
/* Check the BAR type and set our address mask */
if (bar_response & PCI_BASE_ADDRESS_SPACE) {
bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
& 0xffff) + 1;
+#ifndef CONFIG_PCI_ENUM_ONLY
bar_res = io;
+#endif
DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
} else {
- if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
+ if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
PCI_BASE_ADDRESS_MEM_TYPE_64) {
u32 bar_response_upper;
u64 bar64;
- pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
- pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
+
+#ifndef CONFIG_PCI_ENUM_ONLY
+ pci_hose_write_config_dword(hose, dev, bar + 4,
+ 0xffffffff);
+#endif
+ pci_hose_read_config_dword(hose, dev, bar + 4,
+ &bar_response_upper);
bar64 = ((u64)bar_response_upper << 32) | bar_response;
bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
+#ifndef CONFIG_PCI_ENUM_ONLY
found_mem64 = 1;
+#endif
} else {
bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
}
+#ifndef CONFIG_PCI_ENUM_ONLY
if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
bar_res = prefetch;
else
bar_res = mem;
+#endif
DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
}
+#ifndef CONFIG_PCI_ENUM_ONLY
if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
/* Write it out and update our limit */
pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
#endif
}
- cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
- PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
}
+#endif
+ cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
+ PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
DEBUGF("\n");
bar_nr++;
}
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
CONFIG_SYS_PCI_CACHE_LINE_SIZE);
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
struct pci_region *pci_mem = hose->pci_mem;
struct pci_region *pci_prefetch = hose->pci_prefetch;
struct pci_region *pci_io = hose->pci_io;
- unsigned int cmdstat;
+ u16 cmdstat;
- pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+ pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
/* Configure bus number registers */
pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
}
/* Enable memory and I/O accesses, enable bus master */
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND,
+ cmdstat | PCI_COMMAND_MASTER);
}
void pciauto_postscan_setup_bridge(struct pci_controller *hose,
pciauto_region_align(pci_mem, 0x100000);
pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
- (pci_mem->bus_lower-1) >> 16);
+ (pci_mem->bus_lower - 1) >> 16);
}
if (pci_prefetch) {
pciauto_region_align(pci_prefetch, 0x100000);
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
- (pci_prefetch->bus_lower-1) >> 16);
+ (pci_prefetch->bus_lower - 1) >> 16);
}
if (pci_io) {
pciauto_region_align(pci_io, 0x1000);
pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
- ((pci_io->bus_lower-1) & 0x0000f000) >> 8);
+ ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
- ((pci_io->bus_lower-1) & 0xffff0000) >> 16);
+ ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
}
}
hose->pci_io = hose->pci_mem = NULL;
- for (i=0; i<hose->region_count; i++) {
+ for (i = 0; i < hose->region_count; i++) {
switch(hose->regions[i].flags) {
case PCI_REGION_IO:
if (!hose->pci_io ||
}
}
-/* HJF: Changed this to return int. I think this is required
+/*
+ * HJF: Changed this to return int. I think this is required
* to get the correct result when scanning bridges
*/
int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
- switch(class) {
- case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
- DEBUGF("PCI AutoConfig: Found PowerPC device\n");
- pciauto_setup_device(hose, dev, 6, hose->pci_mem,
- hose->pci_prefetch, hose->pci_io);
- break;
-
+ switch (class) {
case PCI_CLASS_BRIDGE_PCI:
hose->current_busno++;
- pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
+ pciauto_setup_device(hose, dev, 2, hose->pci_mem,
+ hose->pci_prefetch, hose->pci_io);
DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
return sub_bus;
}
- pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
+ pciauto_setup_device(hose, dev, 6, hose->pci_mem,
+ hose->pci_prefetch, hose->pci_io);
break;
case PCI_CLASS_BRIDGE_CARDBUS:
- /* just do a minimal setup of the bridge, let the OS take care of the rest */
- pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
+ /*
+ * just do a minimal setup of the bridge,
+ * let the OS take care of the rest
+ */
+ pciauto_setup_device(hose, dev, 0, hose->pci_mem,
+ hose->pci_prefetch, hose->pci_io);
- DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
+ DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
+ PCI_DEV(dev));
hose->current_busno++;
break;
* the PIMMR window to be allocated (BAR0 - 1MB size)
*/
DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
- pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
+ pciauto_setup_device(hose, dev, 0, hose->pci_mem,
+ hose->pci_prefetch, hose->pci_io);
break;
#endif
+
+ case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
+ DEBUGF("PCI AutoConfig: Found PowerPC device\n");
+
default:
- pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
+ pciauto_setup_device(hose, dev, 6, hose->pci_mem,
+ hose->pci_prefetch, hose->pci_io);
break;
}
COBJS-$(CONFIG_RTC_DS174x) += ds174x.o
COBJS-$(CONFIG_RTC_DS3231) += ds3231.o
COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o
+COBJS-$(CONFIG_RTC_IMXDI) += imxdi.o
COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o
COBJS-$(CONFIG_RTC_M41T11) += m41t11.o
COBJS-$(CONFIG_RTC_M41T60) += m41t60.o
COBJS-$(CONFIG_RTC_MPC5200) += mpc5xxx.o
COBJS-$(CONFIG_RTC_MPC8xx) += mpc8xx.o
COBJS-$(CONFIG_RTC_MV) += mvrtc.o
+COBJS-$(CONFIG_RTC_MX27) += mx27rtc.o
COBJS-$(CONFIG_RTC_MXS) += mxsrtc.o
COBJS-$(CONFIG_RTC_PCF8563) += pcf8563.o
COBJS-$(CONFIG_RTC_PL031) += pl031.o
--- /dev/null
+/*
+ * (C) Copyright 2009-2012 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on the Linux rtc-imxdi.c driver, which is:
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2010 Orex Computed Radiography
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Date & Time support for Freescale i.MX DryIce RTC
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/compat.h>
+#include <rtc.h>
+
+#if defined(CONFIG_CMD_DATE)
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/* DryIce Register Definitions */
+
+struct imxdi_regs {
+ u32 dtcmr; /* Time Counter MSB Reg */
+ u32 dtclr; /* Time Counter LSB Reg */
+ u32 dcamr; /* Clock Alarm MSB Reg */
+ u32 dcalr; /* Clock Alarm LSB Reg */
+ u32 dcr; /* Control Reg */
+ u32 dsr; /* Status Reg */
+ u32 dier; /* Interrupt Enable Reg */
+};
+
+#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
+
+#define DCR_TCE (1 << 3) /* Time Counter Enable */
+
+#define DSR_WBF (1 << 10) /* Write Busy Flag */
+#define DSR_WNF (1 << 9) /* Write Next Flag */
+#define DSR_WCF (1 << 8) /* Write Complete Flag */
+#define DSR_WEF (1 << 7) /* Write Error Flag */
+#define DSR_CAF (1 << 4) /* Clock Alarm Flag */
+#define DSR_NVF (1 << 1) /* Non-Valid Flag */
+#define DSR_SVF (1 << 0) /* Security Violation Flag */
+
+#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */
+#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */
+#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */
+#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
+
+/* Driver Private Data */
+
+struct imxdi_data {
+ struct imxdi_regs __iomem *regs;
+ int init_done;
+};
+
+static struct imxdi_data data;
+
+/*
+ * This function attempts to clear the dryice write-error flag.
+ *
+ * A dryice write error is similar to a bus fault and should not occur in
+ * normal operation. Clearing the flag requires another write, so the root
+ * cause of the problem may need to be fixed before the flag can be cleared.
+ */
+static void clear_write_error(void)
+{
+ int cnt;
+
+ puts("### Warning: RTC - Register write error!\n");
+
+ /* clear the write error flag */
+ __raw_writel(DSR_WEF, &data.regs->dsr);
+
+ /* wait for it to take effect */
+ for (cnt = 0; cnt < 1000; cnt++) {
+ if ((__raw_readl(&data.regs->dsr) & DSR_WEF) == 0)
+ return;
+ udelay(10);
+ }
+ puts("### Error: RTC - Cannot clear write-error flag!\n");
+}
+
+/*
+ * Write a dryice register and wait until it completes.
+ *
+ * Use interrupt flags to determine when the write has completed.
+ */
+#define DI_WRITE_WAIT(val, reg) \
+( \
+ /* do the register write */ \
+ __raw_writel((val), &data.regs->reg), \
+ \
+ di_write_wait((val), #reg) \
+)
+static int di_write_wait(u32 val, const char *reg)
+{
+ int cnt;
+ int ret = 0;
+ int rc = 0;
+
+ /* wait for the write to finish */
+ for (cnt = 0; cnt < 100; cnt++) {
+ if ((__raw_readl(&data.regs->dsr) & (DSR_WCF | DSR_WEF)) != 0) {
+ ret = 1;
+ break;
+ }
+ udelay(10);
+ }
+ if (ret == 0)
+ printf("### Warning: RTC - Write-wait timeout "
+ "val = 0x%.8x reg = %s\n", val, reg);
+
+ /* check for write error */
+ if (__raw_readl(&data.regs->dsr) & DSR_WEF) {
+ clear_write_error();
+ rc = -1;
+ }
+
+ return rc;
+}
+
+/*
+ * Initialize dryice hardware
+ */
+static int di_init(void)
+{
+ int rc = 0;
+
+ data.regs = (struct imxdi_regs __iomem *)IMX_DRYICE_BASE;
+
+ /* mask all interrupts */
+ __raw_writel(0, &data.regs->dier);
+
+ /* put dryice into valid state */
+ if (__raw_readl(&data.regs->dsr) & DSR_NVF) {
+ rc = DI_WRITE_WAIT(DSR_NVF | DSR_SVF, dsr);
+ if (rc)
+ goto err;
+ }
+
+ /* initialize alarm */
+ rc = DI_WRITE_WAIT(DCAMR_UNSET, dcamr);
+ if (rc)
+ goto err;
+ rc = DI_WRITE_WAIT(0, dcalr);
+ if (rc)
+ goto err;
+
+ /* clear alarm flag */
+ if (__raw_readl(&data.regs->dsr) & DSR_CAF) {
+ rc = DI_WRITE_WAIT(DSR_CAF, dsr);
+ if (rc)
+ goto err;
+ }
+
+ /* the timer won't count if it has never been written to */
+ if (__raw_readl(&data.regs->dtcmr) == 0) {
+ rc = DI_WRITE_WAIT(0, dtcmr);
+ if (rc)
+ goto err;
+ }
+
+ /* start keeping time */
+ if (!(__raw_readl(&data.regs->dcr) & DCR_TCE)) {
+ rc = DI_WRITE_WAIT(__raw_readl(&data.regs->dcr) | DCR_TCE, dcr);
+ if (rc)
+ goto err;
+ }
+
+ data.init_done = 1;
+ return 0;
+
+err:
+ return rc;
+}
+
+int rtc_get(struct rtc_time *tmp)
+{
+ unsigned long now;
+ int rc = 0;
+
+ if (!data.init_done) {
+ rc = di_init();
+ if (rc)
+ goto err;
+ }
+
+ now = __raw_readl(&data.regs->dtcmr);
+ to_tm(now, tmp);
+
+err:
+ return rc;
+}
+
+int rtc_set(struct rtc_time *tmp)
+{
+ unsigned long now;
+ int rc;
+
+ if (!data.init_done) {
+ rc = di_init();
+ if (rc)
+ goto err;
+ }
+
+ now = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+ /* zero the fractional part first */
+ rc = DI_WRITE_WAIT(0, dtclr);
+ if (rc == 0)
+ rc = DI_WRITE_WAIT(now, dtcmr);
+
+err:
+ return rc;
+}
+
+void rtc_reset(void)
+{
+ di_init();
+}
+
+#endif
--- /dev/null
+/*
+ * Freescale i.MX27 RTC Driver
+ *
+ * Copyright (C) 2012 Philippe Reynes <tremyfr@yahoo.fr>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <rtc.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+#define HOUR_SHIFT 8
+#define HOUR_MASK 0x1f
+#define MIN_SHIFT 0
+#define MIN_MASK 0x3f
+
+int rtc_get(struct rtc_time *time)
+{
+ struct rtc_regs *rtc_regs = (struct rtc_regs *)IMX_RTC_BASE;
+ uint32_t day, hour, min, sec;
+
+ day = readl(&rtc_regs->dayr);
+ hour = readl(&rtc_regs->hourmin);
+ sec = readl(&rtc_regs->seconds);
+
+ min = (hour >> MIN_SHIFT) & MIN_MASK;
+ hour = (hour >> HOUR_SHIFT) & HOUR_MASK;
+
+ sec += min * 60 + hour * 3600 + day * 24 * 3600;
+
+ to_tm(sec, time);
+
+ return 0;
+}
+
+int rtc_set(struct rtc_time *time)
+{
+ struct rtc_regs *rtc_regs = (struct rtc_regs *)IMX_RTC_BASE;
+ uint32_t day, hour, min, sec;
+
+ sec = mktime(time->tm_year, time->tm_mon, time->tm_mday,
+ time->tm_hour, time->tm_min, time->tm_sec);
+
+ day = sec / (24 * 3600);
+ sec = sec % (24 * 3600);
+ hour = sec / 3600;
+ sec = sec % 3600;
+ min = sec / 60;
+ sec = sec % 60;
+
+ hour = (hour & HOUR_MASK) << HOUR_SHIFT;
+ hour |= (min & MIN_MASK) << MIN_SHIFT;
+
+ writel(day, &rtc_regs->dayr);
+ writel(hour, &rtc_regs->hourmin);
+ writel(sec, &rtc_regs->seconds);
+
+ return 0;
+}
+
+void rtc_reset(void)
+{
+ struct rtc_regs *rtc_regs = (struct rtc_regs *)IMX_RTC_BASE;
+
+ writel(0, &rtc_regs->dayr);
+ writel(0, &rtc_regs->hourmin);
+ writel(0, &rtc_regs->seconds);
+}
/* Set time in seconds since 1970-01-01 */
int mxs_rtc_set_time(uint32_t secs)
{
- struct mx28_rtc_regs *rtc_regs = (struct mx28_rtc_regs *)MXS_RTC_BASE;
+ struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE;
int ret;
writel(secs, &rtc_regs->hw_rtc_seconds);
* is taken from the linux kernel driver for the STMP37xx RTC since
* documentation doesn't mention it.
*/
- ret = mx28_wait_mask_clr(&rtc_regs->hw_rtc_stat_reg,
+ ret = mxs_wait_mask_clr(&rtc_regs->hw_rtc_stat_reg,
0x80 << RTC_STAT_STALE_REGS_OFFSET, MXS_RTC_MAX_TIMEOUT);
if (ret)
int rtc_get(struct rtc_time *time)
{
- struct mx28_rtc_regs *rtc_regs = (struct mx28_rtc_regs *)MXS_RTC_BASE;
+ struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE;
uint32_t secs;
secs = readl(&rtc_regs->hw_rtc_seconds);
void rtc_reset(void)
{
- struct mx28_rtc_regs *rtc_regs = (struct mx28_rtc_regs *)MXS_RTC_BASE;
+ struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE;
int ret;
/* Set time to 1970-01-01 */
mxs_rtc_set_time(0);
/* Reset the RTC block */
- ret = mx28_reset_block(&rtc_regs->hw_rtc_ctrl_reg);
+ ret = mxs_reset_block(&rtc_regs->hw_rtc_ctrl_reg);
if (ret)
printf("MXS RTC: Block reset timeout\n");
}
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
+ /*
+ * Just in case: drain transmitter register
+ * 1000us is enough for baudrate >= 9600
+ */
+ if (!(readl(&usart->csr) & USART3_BIT(TXEMPTY)))
+ __udelay(1000);
+
writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
serial_setbrg();
- writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
| USART3_BF(USCLKS, USART3_USCLKS_MCK)
| USART3_BF(CHRL, USART3_CHRL_8)
| USART3_BF(PAR, USART3_PAR_NONE)
| USART3_BF(NBSTOP, USART3_NBSTOP_1)),
&usart->mr);
+ writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
+ /* 100us is enough for the new settings to be settled */
+ __udelay(100);
return 0;
}
serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
serial_out(UART_LCRVAL, &com_port->lcr);
#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
- defined(CONFIG_AM33XX)
+ defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX)
#if defined(CONFIG_APTIX)
/* /13 mode so Aptix 6MHz can hit 115200 */
};
#define PORT serial_ports[port-1]
-#if defined(CONFIG_CONS_INDEX)
-#define CONSOLE (serial_ports[CONFIG_CONS_INDEX-1])
-#endif
#if defined(CONFIG_SERIAL_MULTI)
writel(lcr, ®s->fr);
writel(lcr, ®s->pl011_rlcr);
+ /* lcrh needs to be set again for change to be effective */
+ writel(lcr, ®s->pl011_lcrh);
}
#endif
/* Finally, enable the UART */
as->slave.cs = cs;
as->regs = regs;
as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS
+#if defined(CONFIG_AT91SAM9X5)
+ | ATMEL_SPI_MR_WDRBT
+#endif
| ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf);
spi_writel(as, CSR(cs), csrx);
#define ATMEL_SPI_MR_PCSDEC (1 << 2)
#define ATMEL_SPI_MR_FDIV (1 << 3)
#define ATMEL_SPI_MR_MODFDIS (1 << 4)
+#define ATMEL_SPI_MR_WDRBT (1 << 5)
#define ATMEL_SPI_MR_LLB (1 << 7)
#define ATMEL_SPI_MR_PCS(x) (((x) & 15) << 16)
#define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24)
clk_src = mxc_get_clock(MXC_CSPI_CLK);
- div = clk_src / max_hz;
+ div = DIV_ROUND_UP(clk_src, max_hz);
div = get_cspi_div(div);
debug("clk %d Hz, div %d, real clk %d Hz\n",
* The following computation is taken directly from Freescale's code.
*/
if (clk_src > max_hz) {
- pre_div = clk_src / max_hz;
+ pre_div = DIV_ROUND_UP(clk_src, max_hz);
if (pre_div > 16) {
post_div = pre_div / 16;
pre_div = 15;
if (bus >= ARRAY_SIZE(spi_bases))
return NULL;
- mxcs = malloc(sizeof(struct mxc_spi_slave));
+ mxcs = calloc(sizeof(struct mxc_spi_slave), 1);
if (!mxcs) {
puts("mxc_spi: SPI Slave not allocated !\n");
return NULL;
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/dma.h>
#define MXS_SPI_MAX_TIMEOUT 1000000
#define MXS_SPI_PORT_OFFSET 0x2000
#define MXS_SSP_CHIPSELECT_MASK 0x00300000
#define MXS_SSP_CHIPSELECT_SHIFT 20
+#define MXSSSP_SMALL_TRANSFER 512
+
+/*
+ * CONFIG_MXS_SPI_DMA_ENABLE: Experimental mixed PIO/DMA support for MXS SPI
+ * host. Use with utmost caution!
+ *
+ * Enabling this is not yet recommended since this
+ * still doesn't support transfers to/from unaligned
+ * addresses. Therefore this driver will not work
+ * for example with saving environment. This is
+ * caused by DMA alignment constraints on MXS.
+ */
+
struct mxs_spi_slave {
struct spi_slave slave;
uint32_t max_khz;
uint32_t mode;
- struct mx28_ssp_regs *regs;
+ struct mxs_ssp_regs *regs;
};
static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
{
struct mxs_spi_slave *mxs_slave;
uint32_t addr;
- struct mx28_ssp_regs *ssp_regs;
+ struct mxs_ssp_regs *ssp_regs;
int reg;
if (!spi_cs_is_valid(bus, cs)) {
return NULL;
}
- mxs_slave = malloc(sizeof(struct mxs_spi_slave));
+ mxs_slave = calloc(sizeof(struct mxs_spi_slave), 1);
if (!mxs_slave)
return NULL;
+ if (mxs_dma_init_channel(bus))
+ goto err_init;
+
addr = MXS_SSP0_BASE + (bus * MXS_SPI_PORT_OFFSET);
mxs_slave->slave.bus = bus;
mxs_slave->slave.cs = cs;
mxs_slave->max_khz = max_hz / 1000;
mxs_slave->mode = mode;
- mxs_slave->regs = (struct mx28_ssp_regs *)addr;
+ mxs_slave->regs = (struct mxs_ssp_regs *)addr;
ssp_regs = mxs_slave->regs;
reg = readl(&ssp_regs->hw_ssp_ctrl0);
writel(reg, &ssp_regs->hw_ssp_ctrl0);
return &mxs_slave->slave;
+
+err_init:
+ free(mxs_slave);
+ return NULL;
}
void spi_free_slave(struct spi_slave *slave)
int spi_claim_bus(struct spi_slave *slave)
{
struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
- struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
+ struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
uint32_t reg = 0;
- mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
+ mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
{
}
-static void mxs_spi_start_xfer(struct mx28_ssp_regs *ssp_regs)
+static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
{
writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
}
-static void mxs_spi_end_xfer(struct mx28_ssp_regs *ssp_regs)
+static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
{
writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
+static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
+ char *data, int length, int write, unsigned long flags)
{
- struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
- struct mx28_ssp_regs *ssp_regs = mxs_slave->regs;
- int len = bitlen / 8;
- const char *tx = dout;
- char *rx = din;
- char dummy;
-
- if (bitlen == 0) {
- if (flags & SPI_XFER_END) {
- rx = &dummy;
- len = 1;
- } else
- return 0;
- }
-
- if (!rx && !tx)
- return 0;
+ struct mxs_ssp_regs *ssp_regs = slave->regs;
if (flags & SPI_XFER_BEGIN)
mxs_spi_start_xfer(ssp_regs);
- while (len--) {
+ while (length--) {
/* We transfer 1 byte */
writel(1, &ssp_regs->hw_ssp_xfer_size);
- if ((flags & SPI_XFER_END) && !len)
+ if ((flags & SPI_XFER_END) && !length)
mxs_spi_end_xfer(ssp_regs);
- if (tx)
+ if (write)
writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
else
writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
- if (mx28_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
+ if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
printf("MXS SPI: Timeout waiting for start\n");
return -ETIMEDOUT;
}
- if (tx)
- writel(*tx++, &ssp_regs->hw_ssp_data);
+ if (write)
+ writel(*data++, &ssp_regs->hw_ssp_data);
writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
- if (rx) {
- if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
+ if (!write) {
+ if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
printf("MXS SPI: Timeout waiting for data\n");
return -ETIMEDOUT;
}
- *rx = readl(&ssp_regs->hw_ssp_data);
- rx++;
+ *data = readl(&ssp_regs->hw_ssp_data);
+ data++;
}
- if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
+ if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
printf("MXS SPI: Timeout waiting for finish\n");
return -ETIMEDOUT;
return 0;
}
+
+static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
+ char *data, int length, int write, unsigned long flags)
+{
+ const int xfer_max_sz = 0xff00;
+ const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
+ struct mxs_ssp_regs *ssp_regs = slave->regs;
+ struct mxs_dma_desc *dp;
+ uint32_t ctrl0;
+ uint32_t cache_data_count;
+ int dmach;
+ int tl;
+
+ ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
+
+ memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
+
+ ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
+ ctrl0 |= SSP_CTRL0_DATA_XFER;
+
+ if (flags & SPI_XFER_BEGIN)
+ ctrl0 |= SSP_CTRL0_LOCK_CS;
+ if (!write)
+ ctrl0 |= SSP_CTRL0_READ;
+
+ writel(length, &ssp_regs->hw_ssp_xfer_size);
+
+ if (length % ARCH_DMA_MINALIGN)
+ cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
+ else
+ cache_data_count = length;
+
+ if (write)
+ /* Flush data to DRAM so DMA can pick them up */
+ flush_dcache_range((uint32_t)data,
+ (uint32_t)(data + cache_data_count));
+
+ dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
+
+ dp = desc;
+ while (length) {
+ dp->address = (dma_addr_t)dp;
+ dp->cmd.address = (dma_addr_t)data;
+
+ /*
+ * This is correct, even though it does indeed look insane.
+ * I hereby have to, wholeheartedly, thank Freescale Inc.,
+ * for always inventing insane hardware and keeping me busy
+ * and employed ;-)
+ */
+ if (write)
+ dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
+ else
+ dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
+
+ /*
+ * The DMA controller can transfer large chunks (64kB) at
+ * time by setting the transfer length to 0. Setting tl to
+ * 0x10000 will overflow below and make .data contain 0.
+ * Otherwise, 0xff00 is the transfer maximum.
+ */
+ if (length >= 0x10000)
+ tl = 0x10000;
+ else
+ tl = min(length, xfer_max_sz);
+
+ dp->cmd.data |=
+ (tl << MXS_DMA_DESC_BYTES_OFFSET) |
+ (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
+ MXS_DMA_DESC_HALT_ON_TERMINATE |
+ MXS_DMA_DESC_TERMINATE_FLUSH;
+ dp->cmd.pio_words[0] = ctrl0;
+
+ data += tl;
+ length -= tl;
+
+ mxs_dma_desc_append(dmach, dp);
+
+ dp++;
+ }
+
+ dp->address = (dma_addr_t)dp;
+ dp->cmd.address = (dma_addr_t)0;
+ dp->cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER |
+ (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
+ MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
+ if (flags & SPI_XFER_END) {
+ ctrl0 &= ~SSP_CTRL0_LOCK_CS;
+ dp->cmd.pio_words[0] = ctrl0 | SSP_CTRL0_IGNORE_CRC;
+ }
+ mxs_dma_desc_append(dmach, dp);
+
+ if (mxs_dma_go(dmach))
+ return -EINVAL;
+
+ /* The data arrived into DRAM, invalidate cache over them */
+ if (!write) {
+ invalidate_dcache_range((uint32_t)data,
+ (uint32_t)(data + cache_data_count));
+ }
+
+ return 0;
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
+ struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
+ int len = bitlen / 8;
+ char dummy;
+ int write = 0;
+ char *data = NULL;
+
+#ifdef CONFIG_MXS_SPI_DMA_ENABLE
+ int dma = 1;
+#else
+ int dma = 0;
+#endif
+
+ if (bitlen == 0) {
+ if (flags & SPI_XFER_END) {
+ din = (void *)&dummy;
+ len = 1;
+ } else
+ return 0;
+ }
+
+ /* Half-duplex only */
+ if (din && dout)
+ return -EINVAL;
+ /* No data */
+ if (!din && !dout)
+ return 0;
+
+ if (dout) {
+ data = (char *)dout;
+ write = 1;
+ } else if (din) {
+ data = (char *)din;
+ write = 0;
+ }
+
+ /*
+ * Check for alignment, if the buffer is aligned, do DMA transfer,
+ * PIO otherwise. This is a temporary workaround until proper bounce
+ * buffer is in place.
+ */
+ if (dma) {
+ if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
+ dma = 0;
+ if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
+ dma = 0;
+ }
+
+ if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
+ writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
+ return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
+ } else {
+ writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
+ return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
+ }
+}
case 0:
ds->regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
break;
+#ifdef OMAP3_MCSPI2_BASE
case 1:
ds->regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
break;
+#endif
+#ifdef OMAP3_MCSPI3_BASE
case 2:
ds->regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
break;
+#endif
+#ifdef OMAP3_MCSPI4_BASE
case 3:
ds->regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
break;
+#endif
default:
printf("SPI error: unsupported bus %i. \
Supported busses 0 - 3\n", bus);
/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
* REVISIT: this controller could support SPI_3WIRE mode.
*/
+#ifdef CONFIG_AM33XX
+ /*
+ * The reference design on AM33xx has D0 and D1 wired up opposite
+ * of how it has been done on previous platforms. We assume that
+ * custom hardware will also follow this convention.
+ */
+ conf &= OMAP3_MCSPI_CHCONF_DPE0;
+ conf |= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
+#else
conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
conf |= OMAP3_MCSPI_CHCONF_DPE0;
+#endif
/* wordlength */
conf &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
#ifndef _OMAP3_SPI_H_
#define _OMAP3_SPI_H_
+#ifdef CONFIG_AM33XX
+#define OMAP3_MCSPI1_BASE 0x48030100
+#define OMAP3_MCSPI2_BASE 0x481A0100
+#else
#define OMAP3_MCSPI1_BASE 0x48098000
#define OMAP3_MCSPI2_BASE 0x4809A000
#define OMAP3_MCSPI3_BASE 0x480B8000
#define OMAP3_MCSPI4_BASE 0x480BA000
+#endif
#define OMAP3_MCSPI_MAX_FREQ 48000000
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
- /* Tegra2 SPI-Flash - only 1 device ('bus/cs') */
+ /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
if (bus != 0 || cs != 0)
return 0;
else
return NULL;
}
- if (max_hz > TEGRA2_SPI_MAX_FREQ) {
+ if (max_hz > TEGRA20_SPI_MAX_FREQ) {
printf("SPI error: unsupported frequency %d Hz. Max frequency"
- " is %d Hz\n", max_hz, TEGRA2_SPI_MAX_FREQ);
+ " is %d Hz\n", max_hz, TEGRA20_SPI_MAX_FREQ);
return NULL;
}
spi->slave.bus = bus;
spi->slave.cs = cs;
spi->freq = max_hz;
- spi->regs = (struct spi_tegra *)TEGRA2_SPI_BASE;
+ spi->regs = (struct spi_tegra *)TEGRA20_SPI_BASE;
spi->mode = mode;
return &spi->slave;
debug("spi_init: COMMAND = %08x\n", readl(®s->command));
/*
- * SPI pins on Tegra2 are muxed - change pinmux later due to UART
+ * SPI pins on Tegra20 are muxed - change pinmux later due to UART
* issue.
*/
pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
# ohci
COBJS-$(CONFIG_USB_OHCI_NEW) += ohci-hcd.o
COBJS-$(CONFIG_USB_ATMEL) += ohci-at91.o
+COBJS-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o
COBJS-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
COBJS-$(CONFIG_USB_S3C64XX) += s3c64xx-hcd.o
#include <asm/io.h>
#include <asm/arch/regs-common.h>
#include <asm/arch/regs-base.h>
-#include <asm/arch/regs-clkctrl.h>
+#include <asm/arch/regs-clkctrl-mx28.h>
#include <asm/arch/regs-usb.h>
#include <asm/arch/regs-usbphy.h>
#endif
static struct ehci_mxs {
- struct mx28_usb_regs *usb_regs;
- struct mx28_usbphy_regs *phy_regs;
+ struct mxs_usb_regs *usb_regs;
+ struct mxs_usbphy_regs *phy_regs;
} ehci_mxs;
int mxs_ehci_get_port(struct ehci_mxs *mxs_usb, int port)
return -1;
}
- mxs_usb->usb_regs = (struct mx28_usb_regs *)usb_base;
- mxs_usb->phy_regs = (struct mx28_usbphy_regs *)phy_base;
+ mxs_usb->usb_regs = (struct mxs_usb_regs *)usb_base;
+ mxs_usb->phy_regs = (struct mxs_usbphy_regs *)phy_base;
return 0;
}
int ret;
uint32_t usb_base, cap_base;
- struct mx28_register_32 *digctl_ctrl =
- (struct mx28_register_32 *)HW_DIGCTL_CTRL;
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_register_32 *digctl_ctrl =
+ (struct mxs_register_32 *)HW_DIGCTL_CTRL;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
if (ret)
{
int ret;
uint32_t tmp;
- struct mx28_register_32 *digctl_ctrl =
- (struct mx28_register_32 *)HW_DIGCTL_CTRL;
- struct mx28_clkctrl_regs *clkctrl_regs =
- (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct mxs_register_32 *digctl_ctrl =
+ (struct mxs_register_32 *)HW_DIGCTL_CTRL;
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
if (ret)
--- /dev/null
+/*
+ * Copyright (C) 2012 Sughosh Ganu <urwithsughosh@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+
+#include <asm/arch/da8xx-usb.h>
+
+int usb_cpu_init(void)
+{
+ /* enable psc for usb2.0 */
+ lpsc_on(DAVINCI_LPSC_USB20);
+
+ /* enable psc for usb1.0 */
+ lpsc_on(DAVINCI_LPSC_USB11);
+
+ /* start the on-chip usb phy and its pll */
+ if (usb_phy_on())
+ return 0;
+
+ return 1;
+}
+
+int usb_cpu_stop(void)
+{
+ usb_phy_off();
+
+ /* turn off the usb clock and assert the module reset */
+ lpsc_disable(DAVINCI_LPSC_USB11);
+ lpsc_disable(DAVINCI_LPSC_USB20);
+
+ return 0;
+}
+
+int usb_cpu_init_fail(void)
+{
+ return usb_cpu_stop();
+}
*/
#include <common.h>
-#include "da8xx.h"
+#include "musb_core.h"
+#include <asm/arch/da8xx-usb.h>
/* MUSB platform configuration */
struct musb_config musb_cfg = {
COBJS-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o
+COBJS-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o
COBJS-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o
COBJS-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
exynos_mipi_dsi_lowlevel.o
+COBJS-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o
COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <linux/err.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dp_info.h>
+#include <asm/arch/dp.h>
+
+#include "exynos_dp_lowlevel.h"
+
+static struct exynos_dp_platform_data *dp_pd;
+
+static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
+{
+ disp_info->h_total = disp_info->h_res + disp_info->h_sync_width +
+ disp_info->h_back_porch + disp_info->h_front_porch;
+ disp_info->v_total = disp_info->v_res + disp_info->v_sync_width +
+ disp_info->v_back_porch + disp_info->v_front_porch;
+
+ return;
+}
+
+static int exynos_dp_init_dp(void)
+{
+ int ret;
+ exynos_dp_reset();
+
+ /* SW defined function Normal operation */
+ exynos_dp_enable_sw_func(DP_ENABLE);
+
+ ret = exynos_dp_init_analog_func();
+ if (ret != EXYNOS_DP_SUCCESS)
+ return ret;
+
+ exynos_dp_init_hpd();
+ exynos_dp_init_aux();
+
+ return ret;
+}
+
+static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
+{
+ int i;
+ unsigned char sum = 0;
+
+ for (i = 0; i < EDID_BLOCK_LENGTH; i++)
+ sum = sum + edid_data[i];
+
+ return sum;
+}
+
+static unsigned int exynos_dp_read_edid(void)
+{
+ unsigned char edid[EDID_BLOCK_LENGTH * 2];
+ unsigned int extend_block = 0;
+ unsigned char sum;
+ unsigned char test_vector;
+ int retval;
+
+ /*
+ * EDID device address is 0x50.
+ * However, if necessary, you must have set upper address
+ * into E-EDID in I2C device, 0x30.
+ */
+
+ /* Read Extension Flag, Number of 128-byte EDID extension blocks */
+ exynos_dp_read_byte_from_i2c(I2C_EDID_DEVICE_ADDR, EDID_EXTENSION_FLAG,
+ &extend_block);
+
+ if (extend_block > 0) {
+ printf("DP EDID data includes a single extension!\n");
+
+ /* Read EDID data */
+ retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
+ EDID_HEADER_PATTERN,
+ EDID_BLOCK_LENGTH,
+ &edid[EDID_HEADER_PATTERN]);
+ if (retval != 0) {
+ printf("DP EDID Read failed!\n");
+ return -1;
+ }
+ sum = exynos_dp_calc_edid_check_sum(edid);
+ if (sum != 0) {
+ printf("DP EDID bad checksum!\n");
+ return -1;
+ }
+
+ /* Read additional EDID data */
+ retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
+ EDID_BLOCK_LENGTH,
+ EDID_BLOCK_LENGTH,
+ &edid[EDID_BLOCK_LENGTH]);
+ if (retval != 0) {
+ printf("DP EDID Read failed!\n");
+ return -1;
+ }
+ sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
+ if (sum != 0) {
+ printf("DP EDID bad checksum!\n");
+ return -1;
+ }
+
+ exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
+ &test_vector);
+ if (test_vector & DPCD_TEST_EDID_READ) {
+ exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
+ edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
+ exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
+ DPCD_TEST_EDID_CHECKSUM_WRITE);
+ }
+ } else {
+ debug("DP EDID data does not include any extensions.\n");
+
+ /* Read EDID data */
+ retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
+ EDID_HEADER_PATTERN,
+ EDID_BLOCK_LENGTH,
+ &edid[EDID_HEADER_PATTERN]);
+
+ if (retval != 0) {
+ printf("DP EDID Read failed!\n");
+ return -1;
+ }
+ sum = exynos_dp_calc_edid_check_sum(edid);
+ if (sum != 0) {
+ printf("DP EDID bad checksum!\n");
+ return -1;
+ }
+
+ exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
+ &test_vector);
+ if (test_vector & DPCD_TEST_EDID_READ) {
+ exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
+ edid[EDID_CHECKSUM]);
+ exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
+ DPCD_TEST_EDID_CHECKSUM_WRITE);
+ }
+ }
+
+ debug("DP EDID Read success!\n");
+
+ return 0;
+}
+
+static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
+{
+ unsigned char buf[12];
+ unsigned int ret;
+ unsigned char temp;
+ unsigned char retry_cnt;
+ unsigned char dpcd_rev[16];
+ unsigned char lane_bw[16];
+ unsigned char lane_cnt[16];
+
+ memset(dpcd_rev, 0, 16);
+ memset(lane_bw, 0, 16);
+ memset(lane_cnt, 0, 16);
+ memset(buf, 0, 12);
+
+ retry_cnt = 5;
+ while (retry_cnt) {
+ /* Read DPCD 0x0000-0x000b */
+ ret = exynos_dp_read_bytes_from_dpcd(DPCD_DPCD_REV, 12,
+ buf);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ if (retry_cnt == 0) {
+ printf("DP read_byte_from_dpcd() failed\n");
+ return ret;
+ }
+ retry_cnt--;
+ } else
+ break;
+ }
+
+ /* */
+ temp = buf[DPCD_DPCD_REV];
+ if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11)
+ edp_info->dpcd_rev = temp;
+ else {
+ printf("DP Wrong DPCD Rev : %x\n", temp);
+ return -ENODEV;
+ }
+
+ temp = buf[DPCD_MAX_LINK_RATE];
+ if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70)
+ edp_info->lane_bw = temp;
+ else {
+ printf("DP Wrong MAX LINK RATE : %x\n", temp);
+ return -EINVAL;
+ }
+
+ /*Refer VESA Display Port Stnadard Ver1.1a Page 120 */
+ if (edp_info->dpcd_rev == DP_DPCD_REV_11) {
+ temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
+ if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
+ edp_info->dpcd_efc = 1;
+ else
+ edp_info->dpcd_efc = 0;
+ } else {
+ temp = buf[DPCD_MAX_LANE_COUNT];
+ edp_info->dpcd_efc = 0;
+ }
+
+ if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 ||
+ temp == DP_LANE_CNT_4) {
+ edp_info->lane_cnt = temp;
+ } else {
+ printf("DP Wrong MAX LANE COUNT : %x\n", temp);
+ return -EINVAL;
+ }
+
+ ret = exynos_dp_read_edid();
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP exynos_dp_read_edid() failed\n");
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static void exynos_dp_init_training(void)
+{
+ /*
+ * MACRO_RST must be applied after the PLL_LOCK to avoid
+ * the DP inter pair skew issue for at least 10 us
+ */
+ exynos_dp_reset_macro();
+
+ /* All DP analog module power up */
+ exynos_dp_set_analog_power_down(POWER_ALL, 0);
+}
+
+static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
+{
+ unsigned char buf[5];
+ unsigned int ret = 0;
+
+ debug("DP: %s was called\n", __func__);
+
+ edp_info->lt_info.lt_status = DP_LT_CR;
+ edp_info->lt_info.ep_loop = 0;
+ edp_info->lt_info.cr_loop[0] = 0;
+ edp_info->lt_info.cr_loop[1] = 0;
+ edp_info->lt_info.cr_loop[2] = 0;
+ edp_info->lt_info.cr_loop[3] = 0;
+
+ /* Set sink to D0 (Sink Not Ready) mode. */
+ ret = exynos_dp_write_byte_to_dpcd(DPCD_SINK_POWER_STATE,
+ DPCD_SET_POWER_STATE_D0);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP write_dpcd_byte failed\n");
+ return ret;
+ }
+
+ /* Set link rate and count as you want to establish*/
+ exynos_dp_set_link_bandwidth(edp_info->lane_bw);
+ exynos_dp_set_lane_count(edp_info->lane_cnt);
+
+ /* Setup RX configuration */
+ buf[0] = edp_info->lane_bw;
+ buf[1] = edp_info->lane_cnt;
+
+ ret = exynos_dp_write_bytes_to_dpcd(DPCD_LINK_BW_SET, 2,
+ buf);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP write_dpcd_byte failed\n");
+ return ret;
+ }
+
+ exynos_dp_set_lane_pre_emphasis(PRE_EMPHASIS_LEVEL_0,
+ edp_info->lane_cnt);
+
+ /* Set training pattern 1 */
+ exynos_dp_set_training_pattern(TRAINING_PTN1);
+
+ /* Set RX training pattern */
+ buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1;
+
+ buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
+ DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
+ buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
+ DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
+ buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
+ DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
+ buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
+ DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
+
+ ret = exynos_dp_write_bytes_to_dpcd(DPCD_TRAINING_PATTERN_SET,
+ 5, buf);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP write_dpcd_byte failed\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+static unsigned int exynos_dp_training_pattern_dis(void)
+{
+ unsigned int ret = EXYNOS_DP_SUCCESS;
+
+ exynos_dp_set_training_pattern(DP_NONE);
+
+ ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
+ DPCD_TRAINING_PATTERN_DISABLED);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP requst_link_traninig_req failed\n");
+ return -EAGAIN;
+ }
+
+ return ret;
+}
+
+static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
+{
+ unsigned char data;
+ unsigned int ret = EXYNOS_DP_SUCCESS;
+
+ ret = exynos_dp_read_byte_from_dpcd(DPCD_LANE_COUNT_SET,
+ &data);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP read_from_dpcd failed\n");
+ return -EAGAIN;
+ }
+
+ if (enable)
+ data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data);
+ else
+ data = DPCD_LN_COUNT_SET(data);
+
+ ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET,
+ data);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP write_to_dpcd failed\n");
+ return -EAGAIN;
+
+ }
+
+ return ret;
+}
+
+static unsigned int exynos_dp_set_enhanced_mode(unsigned char enhance_mode)
+{
+ unsigned int ret = EXYNOS_DP_SUCCESS;
+
+ ret = exynos_dp_enable_rx_to_enhanced_mode(enhance_mode);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP rx_enhance_mode failed\n");
+ return -EAGAIN;
+ }
+
+ exynos_dp_enable_enhanced_mode(enhance_mode);
+
+ return ret;
+}
+
+static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info,
+ unsigned char *status)
+{
+ unsigned int ret, i;
+ unsigned char buf[2];
+ unsigned char lane_stat[DP_LANE_CNT_4] = {0,};
+ unsigned char shift_val[DP_LANE_CNT_4] = {0,};
+
+ shift_val[0] = 0;
+ shift_val[1] = 4;
+ shift_val[2] = 0;
+ shift_val[3] = 4;
+
+ ret = exynos_dp_read_bytes_from_dpcd(DPCD_LANE0_1_STATUS, 2, buf);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP read lane status failed\n");
+ return ret;
+ }
+
+ for (i = 0; i < edp_info->lane_cnt; i++) {
+ lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f;
+ if (lane_stat[0] != lane_stat[i]) {
+ printf("Wrong lane status\n");
+ return -EINVAL;
+ }
+ }
+
+ *status = lane_stat[0];
+
+ return ret;
+}
+
+static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
+ unsigned char *sw, unsigned char *em)
+{
+ unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned char buf;
+ unsigned int dpcd_addr;
+ unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
+
+ /*lane_num value is used as arry index, so this range 0 ~ 3 */
+ dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
+
+ ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP read adjust request failed\n");
+ return -EAGAIN;
+ }
+
+ *sw = ((buf >> shift_val[lane_num]) & 0x03);
+ *em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2;
+
+ return ret;
+}
+
+static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info)
+{
+ int ret;
+
+ ret = exynos_dp_training_pattern_dis();
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP training_patter_disable() failed\n");
+ edp_info->lt_info.lt_status = DP_LT_FAIL;
+ }
+
+ ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP set_enhanced_mode() failed\n");
+ edp_info->lt_info.lt_status = DP_LT_FAIL;
+ }
+
+ return ret;
+}
+
+static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info)
+{
+ int ret;
+
+ if (edp_info->lane_bw == DP_LANE_BW_2_70) {
+ edp_info->lane_bw = DP_LANE_BW_1_62;
+ printf("DP Change lane bw to 1.62Gbps\n");
+ edp_info->lt_info.lt_status = DP_LT_START;
+ ret = EXYNOS_DP_SUCCESS;
+ } else {
+ ret = exynos_dp_training_pattern_dis();
+ if (ret != EXYNOS_DP_SUCCESS)
+ printf("DP training_patter_disable() failed\n");
+
+ ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
+ if (ret != EXYNOS_DP_SUCCESS)
+ printf("DP set_enhanced_mode() failed\n");
+
+ edp_info->lt_info.lt_status = DP_LT_FAIL;
+ }
+
+ return ret;
+}
+
+static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
+ *edp_info)
+{
+ unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned char lane_stat;
+ unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
+ unsigned int i;
+ unsigned char adj_req_sw;
+ unsigned char adj_req_em;
+ unsigned char buf[5];
+
+ debug("DP: %s was called\n", __func__);
+ mdelay(1);
+
+ ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP read lane status failed\n");
+ edp_info->lt_info.lt_status = DP_LT_FAIL;
+ return ret;
+ }
+
+ if (lane_stat & DP_LANE_STAT_CR_DONE) {
+ debug("DP clock Recovery training succeed\n");
+ exynos_dp_set_training_pattern(TRAINING_PTN2);
+
+ for (i = 0; i < edp_info->lane_cnt; i++) {
+ ret = exynos_dp_read_dpcd_adj_req(i, &adj_req_sw,
+ &adj_req_em);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ edp_info->lt_info.lt_status = DP_LT_FAIL;
+ return ret;
+ }
+
+ lt_ctl_val[i] = 0;
+ lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
+
+ if ((adj_req_sw == VOLTAGE_LEVEL_3)
+ || (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
+ lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
+ MAX_PRE_EMPHASIS_REACH_3;
+ }
+ exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
+ }
+
+ buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2;
+ buf[1] = lt_ctl_val[0];
+ buf[2] = lt_ctl_val[1];
+ buf[3] = lt_ctl_val[2];
+ buf[4] = lt_ctl_val[3];
+
+ ret = exynos_dp_write_bytes_to_dpcd(
+ DPCD_TRAINING_PATTERN_SET, 5, buf);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP write traning pattern1 failed\n");
+ edp_info->lt_info.lt_status = DP_LT_FAIL;
+ return ret;
+ } else
+ edp_info->lt_info.lt_status = DP_LT_ET;
+ } else {
+ for (i = 0; i < edp_info->lane_cnt; i++) {
+ lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(i);
+ ret = exynos_dp_read_dpcd_adj_req(i,
+ &adj_req_sw, &adj_req_em);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP read adj req failed\n");
+ edp_info->lt_info.lt_status = DP_LT_FAIL;
+ return ret;
+ }
+
+ if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
+ (adj_req_em == PRE_EMPHASIS_LEVEL_3))
+ ret = exynos_dp_reduce_link_rate(edp_info);
+
+ if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) ==
+ adj_req_sw) &&
+ (PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) ==
+ adj_req_em)) {
+ edp_info->lt_info.cr_loop[i]++;
+ if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP)
+ ret = exynos_dp_reduce_link_rate(
+ edp_info);
+ }
+
+ lt_ctl_val[i] = 0;
+ lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
+
+ if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
+ (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
+ lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
+ MAX_PRE_EMPHASIS_REACH_3;
+ }
+ exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
+ }
+
+ ret = exynos_dp_write_bytes_to_dpcd(
+ DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP write traning pattern2 failed\n");
+ edp_info->lt_info.lt_status = DP_LT_FAIL;
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
+ *edp_info)
+{
+ unsigned int ret = EXYNOS_DP_SUCCESS;
+ unsigned char lane_stat, adj_req_sw, adj_req_em, i;
+ unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
+ unsigned char interlane_aligned = 0;
+ unsigned char f_bw;
+ unsigned char f_lane_cnt;
+ unsigned char sink_stat;
+
+ mdelay(1);
+
+ ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP read lane status failed\n");
+ edp_info->lt_info.lt_status = DP_LT_FAIL;
+ return ret;
+ }
+
+ debug("DP lane stat : %x\n", lane_stat);
+
+ if (lane_stat & DP_LANE_STAT_CR_DONE) {
+ ret = exynos_dp_read_byte_from_dpcd(DPCD_LN_ALIGN_UPDATED,
+ &sink_stat);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ edp_info->lt_info.lt_status = DP_LT_FAIL;
+
+ return ret;
+ }
+
+ interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE);
+
+ for (i = 0; i < edp_info->lane_cnt; i++) {
+ ret = exynos_dp_read_dpcd_adj_req(i,
+ &adj_req_sw, &adj_req_em);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP read adj req 1 failed\n");
+ edp_info->lt_info.lt_status = DP_LT_FAIL;
+
+ return ret;
+ }
+
+ lt_ctl_val[i] = 0;
+ lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
+
+ if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
+ (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
+ lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3;
+ lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3;
+ }
+ }
+
+ if (((lane_stat&DP_LANE_STAT_CE_DONE) &&
+ (lane_stat&DP_LANE_STAT_SYM_LOCK))
+ && (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) {
+ debug("DP Equalizer training succeed\n");
+
+ f_bw = exynos_dp_get_link_bandwidth();
+ f_lane_cnt = exynos_dp_get_lane_count();
+
+ debug("DP final BandWidth : %x\n", f_bw);
+ debug("DP final Lane Count : %x\n", f_lane_cnt);
+
+ edp_info->lt_info.lt_status = DP_LT_FINISHED;
+
+ exynos_dp_equalizer_err_link(edp_info);
+
+ } else {
+ edp_info->lt_info.ep_loop++;
+
+ if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) {
+ if (edp_info->lane_bw == DP_LANE_BW_2_70) {
+ ret = exynos_dp_reduce_link_rate(
+ edp_info);
+ } else {
+ edp_info->lt_info.lt_status =
+ DP_LT_FAIL;
+ exynos_dp_equalizer_err_link(edp_info);
+ }
+ } else {
+ for (i = 0; i < edp_info->lane_cnt; i++)
+ exynos_dp_set_lanex_pre_emphasis(
+ lt_ctl_val[i], i);
+
+ ret = exynos_dp_write_bytes_to_dpcd(
+ DPCD_TRAINING_LANE0_SET,
+ 4, lt_ctl_val);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP set lt pattern failed\n");
+ edp_info->lt_info.lt_status =
+ DP_LT_FAIL;
+ exynos_dp_equalizer_err_link(edp_info);
+ }
+ }
+ }
+ } else if (edp_info->lane_bw == DP_LANE_BW_2_70) {
+ ret = exynos_dp_reduce_link_rate(edp_info);
+ } else {
+ edp_info->lt_info.lt_status = DP_LT_FAIL;
+ exynos_dp_equalizer_err_link(edp_info);
+ }
+
+ return ret;
+}
+
+static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info)
+{
+ unsigned int ret = 0;
+ int training_finished;
+
+ /* Turn off unnecessary lane */
+ if (edp_info->lane_cnt == 1)
+ exynos_dp_set_analog_power_down(CH1_BLOCK, 1);
+
+ training_finished = 0;
+
+ edp_info->lt_info.lt_status = DP_LT_START;
+
+ /* Process here */
+ while (!training_finished) {
+ switch (edp_info->lt_info.lt_status) {
+ case DP_LT_START:
+ ret = exynos_dp_link_start(edp_info);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP LT:link start failed\n");
+ return ret;
+ }
+ break;
+ case DP_LT_CR:
+ ret = exynos_dp_process_clock_recovery(edp_info);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP LT:clock recovery failed\n");
+ return ret;
+ }
+ break;
+ case DP_LT_ET:
+ ret = exynos_dp_process_equalizer_training(edp_info);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP LT:equalizer training failed\n");
+ return ret;
+ }
+ break;
+ case DP_LT_FINISHED:
+ training_finished = 1;
+ break;
+ case DP_LT_FAIL:
+ return -1;
+ }
+ }
+
+ return ret;
+}
+
+static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info)
+{
+ unsigned int ret;
+
+ exynos_dp_init_training();
+
+ ret = exynos_dp_sw_link_training(edp_info);
+ if (ret != EXYNOS_DP_SUCCESS)
+ printf("DP dp_sw_link_traning() failed\n");
+
+ return ret;
+}
+
+static void exynos_dp_enable_scramble(unsigned int enable)
+{
+ unsigned char data;
+
+ if (enable) {
+ exynos_dp_enable_scrambling(DP_ENABLE);
+
+ exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
+ &data);
+ exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
+ (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
+ } else {
+ exynos_dp_enable_scrambling(DP_DISABLE);
+ exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
+ &data);
+ exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
+ (u8)(data | DPCD_SCRAMBLING_DISABLED));
+ }
+}
+
+static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
+{
+ unsigned int ret = 0;
+ unsigned int retry_cnt;
+
+ mdelay(1);
+
+ if (edp_info->video_info.master_mode) {
+ printf("DP does not support master mode\n");
+ return -ENODEV;
+ } else {
+ /* debug slave */
+ exynos_dp_config_video_slave_mode(&edp_info->video_info);
+ }
+
+ exynos_dp_set_video_color_format(&edp_info->video_info);
+
+ if (edp_info->video_info.bist_mode) {
+ if (exynos_dp_config_video_bist(edp_info) != 0)
+ return -1;
+ }
+
+ ret = exynos_dp_get_pll_lock_status();
+ if (ret != PLL_LOCKED) {
+ printf("DP PLL is not locked yet\n");
+ return -EIO;
+ }
+
+ if (edp_info->video_info.master_mode == 0) {
+ retry_cnt = 10;
+ while (retry_cnt) {
+ ret = exynos_dp_is_slave_video_stream_clock_on();
+ if (ret != EXYNOS_DP_SUCCESS) {
+ if (retry_cnt == 0) {
+ printf("DP stream_clock_on failed\n");
+ return ret;
+ }
+ retry_cnt--;
+ mdelay(1);
+ } else
+ break;
+ }
+ }
+
+ /* Set to use the register calculated M/N video */
+ exynos_dp_set_video_cr_mn(CALCULATED_M, 0, 0);
+
+ /* For video bist, Video timing must be generated by register */
+ exynos_dp_set_video_timing_mode(VIDEO_TIMING_FROM_CAPTURE);
+
+ /* Enable video bist */
+ if (edp_info->video_info.bist_pattern != COLOR_RAMP &&
+ edp_info->video_info.bist_pattern != BALCK_WHITE_V_LINES &&
+ edp_info->video_info.bist_pattern != COLOR_SQUARE)
+ exynos_dp_enable_video_bist(edp_info->video_info.bist_mode);
+ else
+ exynos_dp_enable_video_bist(DP_DISABLE);
+
+ /* Disable video mute */
+ exynos_dp_enable_video_mute(DP_DISABLE);
+
+ /* Configure video Master or Slave mode */
+ exynos_dp_enable_video_master(edp_info->video_info.master_mode);
+
+ /* Enable video */
+ exynos_dp_start_video();
+
+ if (edp_info->video_info.master_mode == 0) {
+ retry_cnt = 100;
+ while (retry_cnt) {
+ ret = exynos_dp_is_video_stream_on();
+ if (ret != EXYNOS_DP_SUCCESS) {
+ if (retry_cnt == 0) {
+ printf("DP Timeout of video stream\n");
+ return ret;
+ }
+ retry_cnt--;
+ mdelay(5);
+ } else
+ break;
+ }
+ }
+
+ return ret;
+}
+
+unsigned int exynos_init_dp(void)
+{
+ unsigned int ret;
+ struct edp_device_info *edp_info;
+ struct edp_disp_info disp_info;
+
+ edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL);
+ if (!edp_info) {
+ debug("failed to allocate edp device object.\n");
+ return -EFAULT;
+ }
+
+ edp_info = dp_pd->edp_dev_info;
+ if (edp_info == NULL) {
+ debug("failed to get edp_info data.\n");
+ return -EFAULT;
+ }
+ disp_info = edp_info->disp_info;
+
+ exynos_dp_disp_info(&edp_info->disp_info);
+
+ if (dp_pd->phy_enable)
+ dp_pd->phy_enable(1);
+
+ ret = exynos_dp_init_dp();
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP exynos_dp_init_dp() failed\n");
+ return ret;
+ }
+
+ ret = exynos_dp_handle_edid(edp_info);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("EDP handle_edid fail\n");
+ return ret;
+ }
+
+ ret = exynos_dp_set_link_train(edp_info);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP link training fail\n");
+ return ret;
+ }
+
+ exynos_dp_enable_scramble(DP_ENABLE);
+ exynos_dp_enable_rx_to_enhanced_mode(DP_ENABLE);
+ exynos_dp_enable_enhanced_mode(DP_ENABLE);
+
+ exynos_dp_set_link_bandwidth(edp_info->lane_bw);
+ exynos_dp_set_lane_count(edp_info->lane_cnt);
+
+ exynos_dp_init_video();
+ ret = exynos_dp_config_video(edp_info);
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("Exynos DP init failed\n");
+ return ret;
+ }
+
+ printf("Exynos DP init done\n");
+
+ return ret;
+}
+
+void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd)
+{
+ if (pd == NULL) {
+ debug("pd is NULL\n");
+ return;
+ }
+
+ dp_pd = pd;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <linux/err.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dp_info.h>
+#include <asm/arch/dp.h>
+
+static void exynos_dp_enable_video_input(unsigned int enable)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = readl(&dp_regs->video_ctl1);
+ reg &= ~VIDEO_EN_MASK;
+
+ /* enable video input*/
+ if (enable)
+ reg |= VIDEO_EN_MASK;
+
+ writel(reg, &dp_regs->video_ctl1);
+
+ return;
+}
+
+void exynos_dp_enable_video_bist(unsigned int enable)
+{
+ /*enable video bist*/
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = readl(&dp_regs->video_ctl4);
+ reg &= ~VIDEO_BIST_MASK;
+
+ /*enable video bist*/
+ if (enable)
+ reg |= VIDEO_BIST_MASK;
+
+ writel(reg, &dp_regs->video_ctl4);
+
+ return;
+}
+
+void exynos_dp_enable_video_mute(unsigned int enable)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = readl(&dp_regs->video_ctl1);
+ reg &= ~(VIDEO_MUTE_MASK);
+ if (enable)
+ reg |= VIDEO_MUTE_MASK;
+
+ writel(reg, &dp_regs->video_ctl1);
+
+ return;
+}
+
+
+static void exynos_dp_init_analog_param(void)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /*
+ * Set termination
+ * Normal bandgap, Normal swing, Tx terminal registor 61 ohm
+ * 24M Phy clock, TX digital logic power is 100:1.0625V
+ */
+ reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM |
+ SWING_A_30PER_G_NORMAL;
+ writel(reg, &dp_regs->analog_ctl1);
+
+ reg = SEL_24M | TX_DVDD_BIT_1_0625V;
+ writel(reg, &dp_regs->analog_ctl2);
+
+ /*
+ * Set power source for internal clk driver to 1.0625v.
+ * Select current reference of TX driver current to 00:Ipp/2+Ic/2.
+ * Set VCO range of PLL +- 0uA
+ */
+ reg = DRIVE_DVDD_BIT_1_0625V | SEL_CURRENT_DEFAULT | VCO_BIT_000_MICRO;
+ writel(reg, &dp_regs->analog_ctl3);
+
+ /*
+ * Set AUX TX terminal resistor to 102 ohm
+ * Set AUX channel amplitude control
+ */
+ reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA;
+ writel(reg, &dp_regs->pll_filter_ctl1);
+
+ /*
+ * PLL loop filter bandwidth
+ * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
+ * PLL digital power select: 1.2500V
+ */
+ reg = CH3_AMP_0_MV | CH2_AMP_0_MV | CH1_AMP_0_MV | CH0_AMP_0_MV;
+
+ writel(reg, &dp_regs->amp_tuning_ctl);
+
+ /*
+ * PLL loop filter bandwidth
+ * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
+ * PLL digital power select: 1.1250V
+ */
+ reg = DP_PLL_LOOP_BIT_DEFAULT | DP_PLL_REF_BIT_1_1250V;
+ writel(reg, &dp_regs->pll_ctl);
+}
+
+static void exynos_dp_init_interrupt(void)
+{
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+ /* Set interrupt registers to initial states */
+
+ /*
+ * Disable interrupt
+ * INT pin assertion polarity. It must be configured
+ * correctly according to ICU setting.
+ * 1 = assert high, 0 = assert low
+ */
+ writel(INT_POL, &dp_regs->int_ctl);
+
+ /* Clear pending regisers */
+ writel(0xff, &dp_regs->common_int_sta1);
+ writel(0xff, &dp_regs->common_int_sta2);
+ writel(0xff, &dp_regs->common_int_sta3);
+ writel(0xff, &dp_regs->common_int_sta4);
+ writel(0xff, &dp_regs->int_sta);
+
+ /* 0:mask,1: unmask */
+ writel(0x00, &dp_regs->int_sta_mask1);
+ writel(0x00, &dp_regs->int_sta_mask2);
+ writel(0x00, &dp_regs->int_sta_mask3);
+ writel(0x00, &dp_regs->int_sta_mask4);
+ writel(0x00, &dp_regs->int_sta_mask);
+}
+
+void exynos_dp_reset(void)
+{
+ unsigned int reg_func_1;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /*dp tx sw reset*/
+ writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
+
+ exynos_dp_enable_video_input(DP_DISABLE);
+ exynos_dp_enable_video_bist(DP_DISABLE);
+ exynos_dp_enable_video_mute(DP_DISABLE);
+
+ /* software reset */
+ reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
+ AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
+ HDCP_FUNC_EN_N | SW_FUNC_EN_N;
+
+ writel(reg_func_1, &dp_regs->func_en1);
+ writel(reg_func_1, &dp_regs->func_en2);
+
+ mdelay(1);
+
+ exynos_dp_init_analog_param();
+ exynos_dp_init_interrupt();
+
+ return;
+}
+
+void exynos_dp_enable_sw_func(unsigned int enable)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = readl(&dp_regs->func_en1);
+ reg &= ~(SW_FUNC_EN_N);
+
+ if (!enable)
+ reg |= SW_FUNC_EN_N;
+
+ writel(reg, &dp_regs->func_en1);
+
+ return;
+}
+
+unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = readl(&dp_regs->phy_pd);
+ switch (block) {
+ case AUX_BLOCK:
+ reg &= ~(AUX_PD);
+ if (enable)
+ reg |= AUX_PD;
+ break;
+ case CH0_BLOCK:
+ reg &= ~(CH0_PD);
+ if (enable)
+ reg |= CH0_PD;
+ break;
+ case CH1_BLOCK:
+ reg &= ~(CH1_PD);
+ if (enable)
+ reg |= CH1_PD;
+ break;
+ case CH2_BLOCK:
+ reg &= ~(CH2_PD);
+ if (enable)
+ reg |= CH2_PD;
+ break;
+ case CH3_BLOCK:
+ reg &= ~(CH3_PD);
+ if (enable)
+ reg |= CH3_PD;
+ break;
+ case ANALOG_TOTAL:
+ reg &= ~PHY_PD;
+ if (enable)
+ reg |= PHY_PD;
+ break;
+ case POWER_ALL:
+ reg &= ~(PHY_PD | AUX_PD | CH0_PD | CH1_PD | CH2_PD |
+ CH3_PD);
+ if (enable)
+ reg |= (PHY_PD | AUX_PD | CH0_PD | CH1_PD |
+ CH2_PD | CH3_PD);
+ break;
+ default:
+ printf("DP undefined block number : %d\n", block);
+ return -1;
+ }
+
+ writel(reg, &dp_regs->phy_pd);
+
+ return 0;
+}
+
+unsigned int exynos_dp_get_pll_lock_status(void)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = readl(&dp_regs->debug_ctl);
+
+ if (reg & PLL_LOCK)
+ return PLL_LOCKED;
+ else
+ return PLL_UNLOCKED;
+}
+
+static void exynos_dp_set_pll_power(unsigned int enable)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = readl(&dp_regs->pll_ctl);
+ reg &= ~(DP_PLL_PD);
+
+ if (!enable)
+ reg |= DP_PLL_PD;
+
+ writel(reg, &dp_regs->pll_ctl);
+}
+
+int exynos_dp_init_analog_func(void)
+{
+ int ret = EXYNOS_DP_SUCCESS;
+ unsigned int retry_cnt = 10;
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /*Power On All Analog block */
+ exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
+
+ reg = PLL_LOCK_CHG;
+ writel(reg, &dp_regs->common_int_sta1);
+
+ reg = readl(&dp_regs->debug_ctl);
+ reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
+ writel(reg, &dp_regs->debug_ctl);
+
+ /*Assert DP PLL Reset*/
+ reg = readl(&dp_regs->pll_ctl);
+ reg |= DP_PLL_RESET;
+ writel(reg, &dp_regs->pll_ctl);
+
+ mdelay(1);
+
+ /*Deassert DP PLL Reset*/
+ reg = readl(&dp_regs->pll_ctl);
+ reg &= ~(DP_PLL_RESET);
+ writel(reg, &dp_regs->pll_ctl);
+
+ exynos_dp_set_pll_power(DP_ENABLE);
+
+ while (exynos_dp_get_pll_lock_status() == PLL_UNLOCKED) {
+ mdelay(1);
+ retry_cnt--;
+ if (retry_cnt == 0) {
+ printf("DP dp's pll lock failed : retry : %d\n",
+ retry_cnt);
+ return -EINVAL;
+ }
+ }
+
+ debug("dp's pll lock success(%d)\n", retry_cnt);
+
+ /* Enable Serdes FIFO function and Link symbol clock domain module */
+ reg = readl(&dp_regs->func_en2);
+ reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
+ | AUX_FUNC_EN_N);
+ writel(reg, &dp_regs->func_en2);
+
+ return ret;
+}
+
+void exynos_dp_init_hpd(void)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* Clear interrupts releated to Hot Plug Dectect */
+ reg = HOTPLUG_CHG | HPD_LOST | PLUG;
+ writel(reg, &dp_regs->common_int_sta4);
+
+ reg = INT_HPD;
+ writel(reg, &dp_regs->int_sta);
+
+ reg = readl(&dp_regs->sys_ctl3);
+ reg &= ~(F_HPD | HPD_CTRL);
+ writel(reg, &dp_regs->sys_ctl3);
+
+ return;
+}
+
+static inline void exynos_dp_reset_aux(void)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* Disable AUX channel module */
+ reg = readl(&dp_regs->func_en2);
+ reg |= AUX_FUNC_EN_N;
+ writel(reg, &dp_regs->func_en2);
+
+ return;
+}
+
+void exynos_dp_init_aux(void)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* Clear inerrupts related to AUX channel */
+ reg = RPLY_RECEIV | AUX_ERR;
+ writel(reg, &dp_regs->int_sta);
+
+ exynos_dp_reset_aux();
+
+ /* Disable AUX transaction H/W retry */
+ reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
+ AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+ writel(reg, &dp_regs->aux_hw_retry_ctl);
+
+ /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
+ reg = DEFER_CTRL_EN | DEFER_COUNT(1);
+ writel(reg, &dp_regs->aux_ch_defer_ctl);
+
+ /* Enable AUX channel module */
+ reg = readl(&dp_regs->func_en2);
+ reg &= ~AUX_FUNC_EN_N;
+ writel(reg, &dp_regs->func_en2);
+
+ return;
+}
+
+void exynos_dp_config_interrupt(void)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* 0: mask, 1: unmask */
+ reg = COMMON_INT_MASK_1;
+ writel(reg, &dp_regs->common_int_mask1);
+
+ reg = COMMON_INT_MASK_2;
+ writel(reg, &dp_regs->common_int_mask2);
+
+ reg = COMMON_INT_MASK_3;
+ writel(reg, &dp_regs->common_int_mask3);
+
+ reg = COMMON_INT_MASK_4;
+ writel(reg, &dp_regs->common_int_mask4);
+
+ reg = INT_STA_MASK;
+ writel(reg, &dp_regs->int_sta_mask);
+
+ return;
+}
+
+unsigned int exynos_dp_get_plug_in_status(void)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = readl(&dp_regs->sys_ctl3);
+ if (reg & HPD_STATUS)
+ return 0;
+
+ return -1;
+}
+
+unsigned int exynos_dp_detect_hpd(void)
+{
+ int timeout_loop = DP_TIMEOUT_LOOP_COUNT;
+
+ mdelay(2);
+
+ while (exynos_dp_get_plug_in_status() != 0) {
+ if (timeout_loop == 0)
+ return -EINVAL;
+ mdelay(10);
+ timeout_loop--;
+ }
+
+ return EXYNOS_DP_SUCCESS;
+}
+
+unsigned int exynos_dp_start_aux_transaction(void)
+{
+ unsigned int reg;
+ unsigned int ret = 0;
+ unsigned int retry_cnt;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* Enable AUX CH operation */
+ reg = readl(&dp_regs->aux_ch_ctl2);
+ reg |= AUX_EN;
+ writel(reg, &dp_regs->aux_ch_ctl2);
+
+ retry_cnt = 10;
+ while (retry_cnt) {
+ reg = readl(&dp_regs->int_sta);
+ if (!(reg & RPLY_RECEIV)) {
+ if (retry_cnt == 0) {
+ printf("DP Reply Timeout!!\n");
+ ret = -EAGAIN;
+ return ret;
+ }
+ mdelay(1);
+ retry_cnt--;
+ } else
+ break;
+ }
+
+ /* Clear interrupt source for AUX CH command reply */
+ writel(reg, &dp_regs->int_sta);
+
+ /* Clear interrupt source for AUX CH access error */
+ reg = readl(&dp_regs->int_sta);
+ if (reg & AUX_ERR) {
+ printf("DP Aux Access Error\n");
+ writel(AUX_ERR, &dp_regs->int_sta);
+ ret = -EAGAIN;
+ return ret;
+ }
+
+ /* Check AUX CH error access status */
+ reg = readl(&dp_regs->aux_ch_sta);
+ if ((reg & AUX_STATUS_MASK) != 0) {
+ debug("DP AUX CH error happens: %x\n", reg & AUX_STATUS_MASK);
+ ret = -EAGAIN;
+ return ret;
+ }
+
+ return EXYNOS_DP_SUCCESS;
+}
+
+unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
+ unsigned char data)
+{
+ unsigned int reg, ret;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* Clear AUX CH data buffer */
+ reg = BUF_CLR;
+ writel(reg, &dp_regs->buffer_data_ctl);
+
+ /* Select DPCD device address */
+ reg = AUX_ADDR_7_0(reg_addr);
+ writel(reg, &dp_regs->aux_addr_7_0);
+ reg = AUX_ADDR_15_8(reg_addr);
+ writel(reg, &dp_regs->aux_addr_15_8);
+ reg = AUX_ADDR_19_16(reg_addr);
+ writel(reg, &dp_regs->aux_addr_19_16);
+
+ /* Write data buffer */
+ reg = (unsigned int)data;
+ writel(reg, &dp_regs->buf_data0);
+
+ /*
+ * Set DisplayPort transaction and write 1 byte
+ * If bit 3 is 1, DisplayPort transaction.
+ * If Bit 3 is 0, I2C transaction.
+ */
+ reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+ writel(reg, &dp_regs->aux_ch_ctl1);
+
+ /* Start AUX transaction */
+ ret = exynos_dp_start_aux_transaction();
+ if (ret != EXYNOS_DP_SUCCESS) {
+ printf("DP Aux transaction failed\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
+ unsigned char *data)
+{
+ unsigned int reg;
+ int retval;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* Clear AUX CH data buffer */
+ reg = BUF_CLR;
+ writel(reg, &dp_regs->buffer_data_ctl);
+
+ /* Select DPCD device address */
+ reg = AUX_ADDR_7_0(reg_addr);
+ writel(reg, &dp_regs->aux_addr_7_0);
+ reg = AUX_ADDR_15_8(reg_addr);
+ writel(reg, &dp_regs->aux_addr_15_8);
+ reg = AUX_ADDR_19_16(reg_addr);
+ writel(reg, &dp_regs->aux_addr_19_16);
+
+ /*
+ * Set DisplayPort transaction and read 1 byte
+ * If bit 3 is 1, DisplayPort transaction.
+ * If Bit 3 is 0, I2C transaction.
+ */
+ reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+ writel(reg, &dp_regs->aux_ch_ctl1);
+
+ /* Start AUX transaction */
+ retval = exynos_dp_start_aux_transaction();
+ if (!retval)
+ debug("DP Aux Transaction fail!\n");
+
+ /* Read data buffer */
+ reg = readl(&dp_regs->buf_data0);
+ *data = (unsigned char)(reg & 0xff);
+
+ return retval;
+}
+
+unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
+ unsigned int count,
+ unsigned char data[])
+{
+ unsigned int reg;
+ unsigned int start_offset;
+ unsigned int cur_data_count;
+ unsigned int cur_data_idx;
+ unsigned int retry_cnt;
+ unsigned int ret = 0;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* Clear AUX CH data buffer */
+ reg = BUF_CLR;
+ writel(reg, &dp_regs->buffer_data_ctl);
+
+ start_offset = 0;
+ while (start_offset < count) {
+ /* Buffer size of AUX CH is 16 * 4bytes */
+ if ((count - start_offset) > 16)
+ cur_data_count = 16;
+ else
+ cur_data_count = count - start_offset;
+
+ retry_cnt = 5;
+ while (retry_cnt) {
+ /* Select DPCD device address */
+ reg = AUX_ADDR_7_0(reg_addr + start_offset);
+ writel(reg, &dp_regs->aux_addr_7_0);
+ reg = AUX_ADDR_15_8(reg_addr + start_offset);
+ writel(reg, &dp_regs->aux_addr_15_8);
+ reg = AUX_ADDR_19_16(reg_addr + start_offset);
+ writel(reg, &dp_regs->aux_addr_19_16);
+
+ for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+ cur_data_idx++) {
+ reg = data[start_offset + cur_data_idx];
+ writel(reg, (unsigned int)&dp_regs->buf_data0 +
+ (4 * cur_data_idx));
+ }
+ /*
+ * Set DisplayPort transaction and write
+ * If bit 3 is 1, DisplayPort transaction.
+ * If Bit 3 is 0, I2C transaction.
+ */
+ reg = AUX_LENGTH(cur_data_count) |
+ AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+ writel(reg, &dp_regs->aux_ch_ctl1);
+
+ /* Start AUX transaction */
+ ret = exynos_dp_start_aux_transaction();
+ if (ret != EXYNOS_DP_SUCCESS) {
+ if (retry_cnt == 0) {
+ printf("DP Aux Transaction failed\n");
+ return ret;
+ }
+ retry_cnt--;
+ } else
+ break;
+ }
+ start_offset += cur_data_count;
+ }
+
+ return ret;
+}
+
+unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr,
+ unsigned int count,
+ unsigned char data[])
+{
+ unsigned int reg;
+ unsigned int start_offset;
+ unsigned int cur_data_count;
+ unsigned int cur_data_idx;
+ unsigned int retry_cnt;
+ unsigned int ret = 0;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* Clear AUX CH data buffer */
+ reg = BUF_CLR;
+ writel(reg, &dp_regs->buffer_data_ctl);
+
+ start_offset = 0;
+ while (start_offset < count) {
+ /* Buffer size of AUX CH is 16 * 4bytes */
+ if ((count - start_offset) > 16)
+ cur_data_count = 16;
+ else
+ cur_data_count = count - start_offset;
+
+ retry_cnt = 5;
+ while (retry_cnt) {
+ /* Select DPCD device address */
+ reg = AUX_ADDR_7_0(reg_addr + start_offset);
+ writel(reg, &dp_regs->aux_addr_7_0);
+ reg = AUX_ADDR_15_8(reg_addr + start_offset);
+ writel(reg, &dp_regs->aux_addr_15_8);
+ reg = AUX_ADDR_19_16(reg_addr + start_offset);
+ writel(reg, &dp_regs->aux_addr_19_16);
+ /*
+ * Set DisplayPort transaction and read
+ * If bit 3 is 1, DisplayPort transaction.
+ * If Bit 3 is 0, I2C transaction.
+ */
+ reg = AUX_LENGTH(cur_data_count) |
+ AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+ writel(reg, &dp_regs->aux_ch_ctl1);
+
+ /* Start AUX transaction */
+ ret = exynos_dp_start_aux_transaction();
+ if (ret != EXYNOS_DP_SUCCESS) {
+ if (retry_cnt == 0) {
+ printf("DP Aux Transaction failed\n");
+ return ret;
+ }
+ retry_cnt--;
+ } else
+ break;
+ }
+
+ for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+ cur_data_idx++) {
+ reg = readl((unsigned int)&dp_regs->buf_data0 +
+ 4 * cur_data_idx);
+ data[start_offset + cur_data_idx] = (unsigned char)reg;
+ }
+
+ start_offset += cur_data_count;
+ }
+
+ return ret;
+}
+
+int exynos_dp_select_i2c_device(unsigned int device_addr,
+ unsigned int reg_addr)
+{
+ unsigned int reg;
+ int retval;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* Set EDID device address */
+ reg = device_addr;
+ writel(reg, &dp_regs->aux_addr_7_0);
+ writel(0x0, &dp_regs->aux_addr_15_8);
+ writel(0x0, &dp_regs->aux_addr_19_16);
+
+ /* Set offset from base address of EDID device */
+ writel(reg_addr, &dp_regs->buf_data0);
+
+ /*
+ * Set I2C transaction and write address
+ * If bit 3 is 1, DisplayPort transaction.
+ * If Bit 3 is 0, I2C transaction.
+ */
+ reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
+ AUX_TX_COMM_WRITE;
+ writel(reg, &dp_regs->aux_ch_ctl1);
+
+ /* Start AUX transaction */
+ retval = exynos_dp_start_aux_transaction();
+ if (retval != 0)
+ printf("%s: DP Aux Transaction fail!\n", __func__);
+
+ return retval;
+}
+
+int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
+ unsigned int reg_addr,
+ unsigned int *data)
+{
+ unsigned int reg;
+ int i;
+ int retval;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ for (i = 0; i < 10; i++) {
+ /* Clear AUX CH data buffer */
+ reg = BUF_CLR;
+ writel(reg, &dp_regs->buffer_data_ctl);
+
+ /* Select EDID device */
+ retval = exynos_dp_select_i2c_device(device_addr, reg_addr);
+ if (retval != 0) {
+ printf("DP Select EDID device fail. retry !\n");
+ continue;
+ }
+
+ /*
+ * Set I2C transaction and read data
+ * If bit 3 is 1, DisplayPort transaction.
+ * If Bit 3 is 0, I2C transaction.
+ */
+ reg = AUX_TX_COMM_I2C_TRANSACTION |
+ AUX_TX_COMM_READ;
+ writel(reg, &dp_regs->aux_ch_ctl1);
+
+ /* Start AUX transaction */
+ retval = exynos_dp_start_aux_transaction();
+ if (retval != EXYNOS_DP_SUCCESS)
+ printf("%s: DP Aux Transaction fail!\n", __func__);
+ }
+
+ /* Read data */
+ if (retval == 0)
+ *data = readl(&dp_regs->buf_data0);
+
+ return retval;
+}
+
+int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
+ unsigned int reg_addr, unsigned int count, unsigned char edid[])
+{
+ unsigned int reg;
+ unsigned int i, j;
+ unsigned int cur_data_idx;
+ unsigned int defer = 0;
+ int retval = 0;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ for (i = 0; i < count; i += 16) { /* use 16 burst */
+ for (j = 0; j < 100; j++) {
+ /* Clear AUX CH data buffer */
+ reg = BUF_CLR;
+ writel(reg, &dp_regs->buffer_data_ctl);
+
+ /* Set normal AUX CH command */
+ reg = readl(&dp_regs->aux_ch_ctl2);
+ reg &= ~ADDR_ONLY;
+ writel(reg, &dp_regs->aux_ch_ctl2);
+
+ /*
+ * If Rx sends defer, Tx sends only reads
+ * request without sending addres
+ */
+ if (!defer)
+ retval =
+ exynos_dp_select_i2c_device(device_addr,
+ reg_addr + i);
+ else
+ defer = 0;
+
+ if (retval == EXYNOS_DP_SUCCESS) {
+ /*
+ * Set I2C transaction and write data
+ * If bit 3 is 1, DisplayPort transaction.
+ * If Bit 3 is 0, I2C transaction.
+ */
+ reg = AUX_LENGTH(16) |
+ AUX_TX_COMM_I2C_TRANSACTION |
+ AUX_TX_COMM_READ;
+ writel(reg, &dp_regs->aux_ch_ctl1);
+
+ /* Start AUX transaction */
+ retval = exynos_dp_start_aux_transaction();
+ if (retval == 0)
+ break;
+ else
+ printf("DP Aux Transaction fail!\n");
+ }
+ /* Check if Rx sends defer */
+ reg = readl(&dp_regs->aux_rx_comm);
+ if (reg == AUX_RX_COMM_AUX_DEFER ||
+ reg == AUX_RX_COMM_I2C_DEFER) {
+ printf("DP Defer: %d\n\n", reg);
+ defer = 1;
+ }
+ }
+
+ for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
+ reg = readl((unsigned int)&dp_regs->buf_data0
+ + 4 * cur_data_idx);
+ edid[i + cur_data_idx] = (unsigned char)reg;
+ }
+ }
+
+ return retval;
+}
+
+void exynos_dp_reset_macro(void)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = readl(&dp_regs->phy_test);
+ reg |= MACRO_RST;
+ writel(reg, &dp_regs->phy_test);
+
+ /* 10 us is the minimum Macro reset time. */
+ mdelay(1);
+
+ reg &= ~MACRO_RST;
+ writel(reg, &dp_regs->phy_test);
+}
+
+void exynos_dp_set_link_bandwidth(unsigned char bwtype)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = (unsigned int)bwtype;
+
+ /* Set bandwidth to 2.7G or 1.62G */
+ if ((bwtype == DP_LANE_BW_1_62) || (bwtype == DP_LANE_BW_2_70))
+ writel(reg, &dp_regs->link_bw_set);
+}
+
+unsigned char exynos_dp_get_link_bandwidth(void)
+{
+ unsigned char ret;
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = readl(&dp_regs->link_bw_set);
+ ret = (unsigned char)reg;
+
+ return ret;
+}
+
+void exynos_dp_set_lane_count(unsigned char count)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = (unsigned int)count;
+
+ if ((count == DP_LANE_CNT_1) || (count == DP_LANE_CNT_2) ||
+ (count == DP_LANE_CNT_4))
+ writel(reg, &dp_regs->lane_count_set);
+}
+
+unsigned int exynos_dp_get_lane_count(void)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = readl(&dp_regs->lane_count_set);
+
+ return reg;
+}
+
+unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
+{
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+ unsigned int reg_list[DP_LANE_CNT_4] = {
+ (unsigned int)&dp_regs->ln0_link_training_ctl,
+ (unsigned int)&dp_regs->ln1_link_training_ctl,
+ (unsigned int)&dp_regs->ln2_link_training_ctl,
+ (unsigned int)&dp_regs->ln3_link_training_ctl,
+ };
+
+ return readl(reg_list[lanecnt]);
+}
+
+void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
+ unsigned char lanecnt)
+{
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+ unsigned int reg_list[DP_LANE_CNT_4] = {
+ (unsigned int)&dp_regs->ln0_link_training_ctl,
+ (unsigned int)&dp_regs->ln1_link_training_ctl,
+ (unsigned int)&dp_regs->ln2_link_training_ctl,
+ (unsigned int)&dp_regs->ln3_link_training_ctl,
+ };
+
+ writel(request_val, reg_list[lanecnt]);
+}
+
+void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt)
+{
+ unsigned char i;
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+ unsigned int reg_list[DP_LANE_CNT_4] = {
+ (unsigned int)&dp_regs->ln0_link_training_ctl,
+ (unsigned int)&dp_regs->ln1_link_training_ctl,
+ (unsigned int)&dp_regs->ln2_link_training_ctl,
+ (unsigned int)&dp_regs->ln3_link_training_ctl,
+ };
+ unsigned int reg_shift[DP_LANE_CNT_4] = {
+ PRE_EMPHASIS_SET_0_SHIFT,
+ PRE_EMPHASIS_SET_1_SHIFT,
+ PRE_EMPHASIS_SET_2_SHIFT,
+ PRE_EMPHASIS_SET_3_SHIFT
+ };
+
+ for (i = 0; i < lanecnt; i++) {
+ reg = level << reg_shift[i];
+ writel(reg, reg_list[i]);
+ }
+}
+
+void exynos_dp_set_training_pattern(unsigned int pattern)
+{
+ unsigned int reg = 0;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ switch (pattern) {
+ case PRBS7:
+ reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
+ break;
+ case D10_2:
+ reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
+ break;
+ case TRAINING_PTN1:
+ reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
+ break;
+ case TRAINING_PTN2:
+ reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
+ break;
+ case DP_NONE:
+ reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE |
+ SW_TRAINING_PATTERN_SET_NORMAL;
+ break;
+ default:
+ break;
+ }
+
+ writel(reg, &dp_regs->training_ptn_set);
+}
+
+void exynos_dp_enable_enhanced_mode(unsigned char enable)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = readl(&dp_regs->sys_ctl4);
+ reg &= ~ENHANCED;
+
+ if (enable)
+ reg |= ENHANCED;
+
+ writel(reg, &dp_regs->sys_ctl4);
+}
+
+void exynos_dp_enable_scrambling(unsigned int enable)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = readl(&dp_regs->training_ptn_set);
+ reg &= ~(SCRAMBLING_DISABLE);
+
+ if (!enable)
+ reg |= SCRAMBLING_DISABLE;
+
+ writel(reg, &dp_regs->training_ptn_set);
+}
+
+int exynos_dp_init_video(void)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */
+ reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
+ writel(reg, &dp_regs->common_int_sta1);
+
+ /* I_STRM__CLK detect : DE_CTL : Auto detect */
+ reg &= ~DET_CTRL;
+ writel(reg, &dp_regs->sys_ctl1);
+
+ return 0;
+}
+
+void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* Video Slave mode setting */
+ reg = readl(&dp_regs->func_en1);
+ reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+ reg |= MASTER_VID_FUNC_EN_N;
+ writel(reg, &dp_regs->func_en1);
+
+ /* Configure Interlaced for slave mode video */
+ reg = readl(&dp_regs->video_ctl10);
+ reg &= ~INTERACE_SCAN_CFG;
+ reg |= (video_info->interlaced << INTERACE_SCAN_CFG_SHIFT);
+ writel(reg, &dp_regs->video_ctl10);
+
+ /* Configure V sync polarity for slave mode video */
+ reg = readl(&dp_regs->video_ctl10);
+ reg &= ~VSYNC_POLARITY_CFG;
+ reg |= (video_info->v_sync_polarity << V_S_POLARITY_CFG_SHIFT);
+ writel(reg, &dp_regs->video_ctl10);
+
+ /* Configure H sync polarity for slave mode video */
+ reg = readl(&dp_regs->video_ctl10);
+ reg &= ~HSYNC_POLARITY_CFG;
+ reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
+ writel(reg, &dp_regs->video_ctl10);
+
+ /*Set video mode to slave mode */
+ reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
+ writel(reg, &dp_regs->soc_general_ctl);
+}
+
+void exynos_dp_set_video_color_format(struct edp_video_info *video_info)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* Configure the input color depth, color space, dynamic range */
+ reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) |
+ (video_info->color_depth << IN_BPC_SHIFT) |
+ (video_info->color_space << IN_COLOR_F_SHIFT);
+ writel(reg, &dp_regs->video_ctl2);
+
+ /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
+ reg = readl(&dp_regs->video_ctl3);
+ reg &= ~IN_YC_COEFFI_MASK;
+ if (video_info->ycbcr_coeff)
+ reg |= IN_YC_COEFFI_ITU709;
+ else
+ reg |= IN_YC_COEFFI_ITU601;
+ writel(reg, &dp_regs->video_ctl3);
+}
+
+int exynos_dp_config_video_bist(struct edp_device_info *edp_info)
+{
+ unsigned int reg;
+ unsigned int bist_type = 0;
+ struct edp_video_info video_info = edp_info->video_info;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* For master mode, you don't need to set the video format */
+ if (video_info.master_mode == 0) {
+ writel(TOTAL_LINE_CFG_L(edp_info->disp_info.v_total),
+ &dp_regs->total_ln_cfg_l);
+ writel(TOTAL_LINE_CFG_H(edp_info->disp_info.v_total),
+ &dp_regs->total_ln_cfg_h);
+ writel(ACTIVE_LINE_CFG_L(edp_info->disp_info.v_res),
+ &dp_regs->active_ln_cfg_l);
+ writel(ACTIVE_LINE_CFG_H(edp_info->disp_info.v_res),
+ &dp_regs->active_ln_cfg_h);
+ writel(edp_info->disp_info.v_sync_width,
+ &dp_regs->vsw_cfg);
+ writel(edp_info->disp_info.v_back_porch,
+ &dp_regs->vbp_cfg);
+ writel(edp_info->disp_info.v_front_porch,
+ &dp_regs->vfp_cfg);
+
+ writel(TOTAL_PIXEL_CFG_L(edp_info->disp_info.h_total),
+ &dp_regs->total_pix_cfg_l);
+ writel(TOTAL_PIXEL_CFG_H(edp_info->disp_info.h_total),
+ &dp_regs->total_pix_cfg_h);
+ writel(ACTIVE_PIXEL_CFG_L(edp_info->disp_info.h_res),
+ &dp_regs->active_pix_cfg_l);
+ writel(ACTIVE_PIXEL_CFG_H(edp_info->disp_info.h_res),
+ &dp_regs->active_pix_cfg_h);
+ writel(H_F_PORCH_CFG_L(edp_info->disp_info.h_front_porch),
+ &dp_regs->hfp_cfg_l);
+ writel(H_F_PORCH_CFG_H(edp_info->disp_info.h_front_porch),
+ &dp_regs->hfp_cfg_h);
+ writel(H_SYNC_PORCH_CFG_L(edp_info->disp_info.h_sync_width),
+ &dp_regs->hsw_cfg_l);
+ writel(H_SYNC_PORCH_CFG_H(edp_info->disp_info.h_sync_width),
+ &dp_regs->hsw_cfg_h);
+ writel(H_B_PORCH_CFG_L(edp_info->disp_info.h_back_porch),
+ &dp_regs->hbp_cfg_l);
+ writel(H_B_PORCH_CFG_H(edp_info->disp_info.h_back_porch),
+ &dp_regs->hbp_cfg_h);
+
+ /*
+ * Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1],
+ * HSYNC_P_CFG[0] properly
+ */
+ reg = (video_info.interlaced << INTERACE_SCAN_CFG_SHIFT |
+ video_info.v_sync_polarity << V_S_POLARITY_CFG_SHIFT |
+ video_info.h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
+ writel(reg, &dp_regs->video_ctl10);
+ }
+
+ /* BIST color bar width set--set to each bar is 32 pixel width */
+ switch (video_info.bist_pattern) {
+ case COLORBAR_32:
+ bist_type = BIST_WIDTH_BAR_32_PIXEL |
+ BIST_TYPE_COLOR_BAR;
+ break;
+ case COLORBAR_64:
+ bist_type = BIST_WIDTH_BAR_64_PIXEL |
+ BIST_TYPE_COLOR_BAR;
+ break;
+ case WHITE_GRAY_BALCKBAR_32:
+ bist_type = BIST_WIDTH_BAR_32_PIXEL |
+ BIST_TYPE_WHITE_GRAY_BLACK_BAR;
+ break;
+ case WHITE_GRAY_BALCKBAR_64:
+ bist_type = BIST_WIDTH_BAR_64_PIXEL |
+ BIST_TYPE_WHITE_GRAY_BLACK_BAR;
+ break;
+ case MOBILE_WHITEBAR_32:
+ bist_type = BIST_WIDTH_BAR_32_PIXEL |
+ BIST_TYPE_MOBILE_WHITE_BAR;
+ break;
+ case MOBILE_WHITEBAR_64:
+ bist_type = BIST_WIDTH_BAR_64_PIXEL |
+ BIST_TYPE_MOBILE_WHITE_BAR;
+ break;
+ default:
+ return -1;
+ }
+
+ reg = bist_type;
+ writel(reg, &dp_regs->video_ctl4);
+
+ return 0;
+}
+
+unsigned int exynos_dp_is_slave_video_stream_clock_on(void)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* Update Video stream clk detect status */
+ reg = readl(&dp_regs->sys_ctl1);
+ writel(reg, &dp_regs->sys_ctl1);
+
+ reg = readl(&dp_regs->sys_ctl1);
+
+ if (!(reg & DET_STA)) {
+ debug("DP Input stream clock not detected.\n");
+ return -EIO;
+ }
+
+ return EXYNOS_DP_SUCCESS;
+}
+
+void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
+ unsigned int n_value)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ if (type == REGISTER_M) {
+ reg = readl(&dp_regs->sys_ctl4);
+ reg |= FIX_M_VID;
+ writel(reg, &dp_regs->sys_ctl4);
+ reg = M_VID0_CFG(m_value);
+ writel(reg, &dp_regs->m_vid0);
+ reg = M_VID1_CFG(m_value);
+ writel(reg, &dp_regs->m_vid1);
+ reg = M_VID2_CFG(m_value);
+ writel(reg, &dp_regs->m_vid2);
+
+ reg = N_VID0_CFG(n_value);
+ writel(reg, &dp_regs->n_vid0);
+ reg = N_VID1_CFG(n_value);
+ writel(reg, &dp_regs->n_vid1);
+ reg = N_VID2_CFG(n_value);
+ writel(reg, &dp_regs->n_vid2);
+ } else {
+ reg = readl(&dp_regs->sys_ctl4);
+ reg &= ~FIX_M_VID;
+ writel(reg, &dp_regs->sys_ctl4);
+ }
+}
+
+void exynos_dp_set_video_timing_mode(unsigned int type)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = readl(&dp_regs->video_ctl10);
+ reg &= ~FORMAT_SEL;
+
+ if (type != VIDEO_TIMING_FROM_CAPTURE)
+ reg |= FORMAT_SEL;
+
+ writel(reg, &dp_regs->video_ctl10);
+}
+
+void exynos_dp_enable_video_master(unsigned int enable)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ reg = readl(&dp_regs->soc_general_ctl);
+ if (enable) {
+ reg &= ~VIDEO_MODE_MASK;
+ reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
+ } else {
+ reg &= ~VIDEO_MODE_MASK;
+ reg |= VIDEO_MODE_SLAVE_MODE;
+ }
+
+ writel(reg, &dp_regs->soc_general_ctl);
+}
+
+void exynos_dp_start_video(void)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* Enable Video input and disable Mute */
+ reg = readl(&dp_regs->video_ctl1);
+ reg |= VIDEO_EN;
+ writel(reg, &dp_regs->video_ctl1);
+}
+
+unsigned int exynos_dp_is_video_stream_on(void)
+{
+ unsigned int reg;
+ struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
+
+ /* Update STRM_VALID */
+ reg = readl(&dp_regs->sys_ctl3);
+ writel(reg, &dp_regs->sys_ctl3);
+
+ reg = readl(&dp_regs->sys_ctl3);
+ if (!(reg & STRM_VALID))
+ return -EIO;
+
+ return EXYNOS_DP_SUCCESS;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _EXYNOS_EDP_LOWLEVEL_H
+#define _EXYNOS_EDP_LOWLEVEL_H
+
+void exynos_dp_enable_video_bist(unsigned int enable);
+void exynos_dp_enable_video_mute(unsigned int enable);
+void exynos_dp_reset(void);
+void exynos_dp_enable_sw_func(unsigned int enable);
+unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable);
+unsigned int exynos_dp_get_pll_lock_status(void);
+int exynos_dp_init_analog_func(void);
+void exynos_dp_init_hpd(void);
+void exynos_dp_init_aux(void);
+void exynos_dp_config_interrupt(void);
+unsigned int exynos_dp_get_plug_in_status(void);
+unsigned int exynos_dp_detect_hpd(void);
+unsigned int exynos_dp_start_aux_transaction(void);
+unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
+ unsigned char data);
+unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
+ unsigned char *data);
+unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
+ unsigned int count,
+ unsigned char data[]);
+unsigned int exynos_dp_read_bytes_from_dpcd( unsigned int reg_addr,
+ unsigned int count,
+ unsigned char data[]);
+int exynos_dp_select_i2c_device( unsigned int device_addr,
+ unsigned int reg_addr);
+int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
+ unsigned int reg_addr, unsigned int *data);
+int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
+ unsigned int reg_addr, unsigned int count,
+ unsigned char edid[]);
+void exynos_dp_reset_macro(void);
+void exynos_dp_set_link_bandwidth(unsigned char bwtype);
+unsigned char exynos_dp_get_link_bandwidth(void);
+void exynos_dp_set_lane_count(unsigned char count);
+unsigned int exynos_dp_get_lane_count(void);
+unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt);
+void exynos_dp_set_lane_pre_emphasis(unsigned int level,
+ unsigned char lanecnt);
+void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
+ unsigned char lanecnt);
+void exynos_dp_set_training_pattern(unsigned int pattern);
+void exynos_dp_enable_enhanced_mode(unsigned char enable);
+void exynos_dp_enable_scrambling(unsigned int enable);
+int exynos_dp_init_video(void);
+void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info);
+void exynos_dp_set_video_color_format(struct edp_video_info *video_info);
+int exynos_dp_config_video_bist(struct edp_device_info *edp_info);
+unsigned int exynos_dp_is_slave_video_stream_clock_on(void);
+void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
+ unsigned int n_value);
+void exynos_dp_set_video_timing_mode(unsigned int type);
+void exynos_dp_enable_video_master(unsigned int enable);
+void exynos_dp_start_video(void);
+unsigned int exynos_dp_is_video_stream_on(void);
+
+#endif /* _EXYNOS_DP_LOWLEVEL_H */
#include <asm/arch/clock.h>
#include <asm/arch/clk.h>
#include <asm/arch/mipi_dsim.h>
+#include <asm/arch/dp_info.h>
#include <asm/arch/system.h>
#include "exynos_fb.h"
udelay(vid->power_on_delay);
+ if (vid->dp_enabled)
+ exynos_init_dp();
+
if (vid->reset_lcd) {
vid->reset_lcd();
udelay(vid->reset_delay);
if (panel_info.logo_on) {
memset(lcd_base, 0, panel_width * panel_height *
(NBITS(panel_info.vl_bpix) >> 3));
-
draw_logo();
}
static void exynos_fimd_set_dualrgb(unsigned int enabled)
{
- struct exynos4_fb *fimd_ctrl =
- (struct exynos4_fb *)samsung_get_base_fimd();
+ struct exynos_fb *fimd_ctrl =
+ (struct exynos_fb *)samsung_get_base_fimd();
unsigned int cfg = 0;
if (enabled) {
writel(cfg, &fimd_ctrl->dualrgb);
}
+static void exynos_fimd_set_dp_clkcon(unsigned int enabled)
+{
+
+ struct exynos_fb *fimd_ctrl =
+ (struct exynos_fb *)samsung_get_base_fimd();
+ unsigned int cfg = 0;
+
+ if (enabled)
+ cfg = EXYNOS_DP_CLK_ENABLE;
+
+ writel(cfg, &fimd_ctrl->dp_mie_clkcon);
+}
+
static void exynos_fimd_set_par(unsigned int win_id)
{
unsigned int cfg = 0;
- struct exynos4_fb *fimd_ctrl =
- (struct exynos4_fb *)samsung_get_base_fimd();
+ struct exynos_fb *fimd_ctrl =
+ (struct exynos_fb *)samsung_get_base_fimd();
/* set window control */
cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
EXYNOS_VIDOSD(win_id));
cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
- EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
+ EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1) |
+ EXYNOS_VIDOSD_RIGHT_X_E(1) |
+ EXYNOS_VIDOSD_BOTTOM_Y_E(0);
+
writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b +
EXYNOS_VIDOSD(win_id));
static void exynos_fimd_set_buffer_address(unsigned int win_id)
{
unsigned long start_addr, end_addr;
- struct exynos4_fb *fimd_ctrl =
- (struct exynos4_fb *)samsung_get_base_fimd();
+ struct exynos_fb *fimd_ctrl =
+ (struct exynos_fb *)samsung_get_base_fimd();
start_addr = (unsigned long)lcd_base_addr;
end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
unsigned int cfg = 0, div = 0, remainder, remainder_div;
unsigned long pixel_clock;
unsigned long long src_clock;
- struct exynos4_fb *fimd_ctrl =
- (struct exynos4_fb *)samsung_get_base_fimd();
+ struct exynos_fb *fimd_ctrl =
+ (struct exynos_fb *)samsung_get_base_fimd();
if (pvid->dual_lcd_enabled) {
pixel_clock = pvid->vl_freq *
cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
- if (pixel_clock > MAX_CLOCK)
- pixel_clock = MAX_CLOCK;
-
src_clock = (unsigned long long) get_lcd_clk();
/* get quotient and remainder. */
void exynos_set_trigger(void)
{
unsigned int cfg = 0;
- struct exynos4_fb *fimd_ctrl =
- (struct exynos4_fb *)samsung_get_base_fimd();
+ struct exynos_fb *fimd_ctrl =
+ (struct exynos_fb *)samsung_get_base_fimd();
cfg = readl(&fimd_ctrl->trigcon);
{
unsigned int cfg = 0;
int status;
- struct exynos4_fb *fimd_ctrl =
- (struct exynos4_fb *)samsung_get_base_fimd();
+ struct exynos_fb *fimd_ctrl =
+ (struct exynos_fb *)samsung_get_base_fimd();
cfg = readl(&fimd_ctrl->trigcon);
static void exynos_fimd_lcd_on(void)
{
unsigned int cfg = 0;
- struct exynos4_fb *fimd_ctrl =
- (struct exynos4_fb *)samsung_get_base_fimd();
+ struct exynos_fb *fimd_ctrl =
+ (struct exynos_fb *)samsung_get_base_fimd();
/* display on */
cfg = readl(&fimd_ctrl->vidcon0);
static void exynos_fimd_window_on(unsigned int win_id)
{
unsigned int cfg = 0;
- struct exynos4_fb *fimd_ctrl =
- (struct exynos4_fb *)samsung_get_base_fimd();
+ struct exynos_fb *fimd_ctrl =
+ (struct exynos_fb *)samsung_get_base_fimd();
/* enable window */
cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
void exynos_fimd_lcd_off(void)
{
unsigned int cfg = 0;
- struct exynos4_fb *fimd_ctrl =
- (struct exynos4_fb *)samsung_get_base_fimd();
+ struct exynos_fb *fimd_ctrl =
+ (struct exynos_fb *)samsung_get_base_fimd();
cfg = readl(&fimd_ctrl->vidcon0);
cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
void exynos_fimd_window_off(unsigned int win_id)
{
unsigned int cfg = 0;
- struct exynos4_fb *fimd_ctrl =
- (struct exynos4_fb *)samsung_get_base_fimd();
+ struct exynos_fb *fimd_ctrl =
+ (struct exynos_fb *)samsung_get_base_fimd();
cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
EXYNOS_WINCON(win_id));
writel(cfg, &fimd_ctrl->winshmap);
}
+
void exynos_fimd_lcd_init(vidinfo_t *vid)
{
unsigned int cfg = 0, rgb_mode;
- struct exynos4_fb *fimd_ctrl =
- (struct exynos4_fb *)samsung_get_base_fimd();
+ unsigned int offset;
+ struct exynos_fb *fimd_ctrl =
+ (struct exynos_fb *)samsung_get_base_fimd();
+
+ offset = exynos_fimd_get_base_offset();
/* store panel info to global variable */
pvid = vid;
if (!pvid->vl_dp)
cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
- writel(cfg, &fimd_ctrl->vidcon1);
+ writel(cfg, (unsigned int)&fimd_ctrl->vidcon1 + offset);
/* set timing */
cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1);
- writel(cfg, &fimd_ctrl->vidtcon0);
+ writel(cfg, (unsigned int)&fimd_ctrl->vidtcon0 + offset);
cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1);
- writel(cfg, &fimd_ctrl->vidtcon1);
+ writel(cfg, (unsigned int)&fimd_ctrl->vidtcon1 + offset);
/* set lcd size */
- cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1);
- cfg |= EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1);
+ cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1) |
+ EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1) |
+ EXYNOS_VIDTCON2_HOZVAL_E(pvid->vl_col - 1) |
+ EXYNOS_VIDTCON2_LINEVAL_E(pvid->vl_row - 1);
- writel(cfg, &fimd_ctrl->vidtcon2);
+ writel(cfg, (unsigned int)&fimd_ctrl->vidtcon2 + offset);
}
/* set display mode */
exynos_fimd_set_buffer_address(pvid->win_id);
/* set buffer size */
- cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8);
+ cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
+ EXYNOS_VIDADDR_PAGEWIDTH_E(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
+ EXYNOS_VIDADDR_OFFSIZE(0) |
+ EXYNOS_VIDADDR_OFFSIZE_E(0);
+
writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 +
EXYNOS_BUFFER_SIZE(pvid->win_id));
/* window on */
exynos_fimd_window_on(pvid->win_id);
+
+ exynos_fimd_set_dp_clkcon(pvid->dp_enabled);
}
unsigned long exynos_fimd_calc_fbsize(void)
--- /dev/null
+/*
+ * PWM BACKLIGHT driver for Board based on EXYNOS.
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * Derived from linux/drivers/video/backlight/pwm_backlight.c
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <common.h>
+#include <pwm.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pwm.h>
+#include <asm/arch/pwm_backlight.h>
+
+static struct pwm_backlight_data *pwm;
+
+static int exynos_pwm_backlight_update_status(void)
+{
+ int brightness = pwm->brightness;
+ int max = pwm->max_brightness;
+
+ if (brightness == 0) {
+ pwm_config(pwm->pwm_id, 0, pwm->period);
+ pwm_disable(pwm->pwm_id);
+ } else {
+ pwm_config(pwm->pwm_id,
+ brightness * pwm->period / max, pwm->period);
+ pwm_enable(pwm->pwm_id);
+ }
+ return 0;
+}
+
+int exynos_pwm_backlight_init(struct pwm_backlight_data *pd)
+{
+ pwm = pd;
+
+ exynos_pwm_backlight_update_status();
+
+ return 0;
+}
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000 /* the SX1 has 12MHz input clock */
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
/* input clock of PLL (VCMA9 has 12MHz input clock) */
#define CONFIG_SYS_CLK_FREQ 12000000
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_IDENT_STRING "\n(c) 2003 - 2011 by MPL AG Switzerland, " \
"MEV-10080-001 " VERSION_TAG
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
-#endif
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
/*
* CPU and Board Configuration Options
*/
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
#undef CONFIG_SKIP_LOWLEVEL_INIT
/*
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
-#endif
-
/*
* Size of malloc() pool
*/
115200, 230400 }
#define CONFIG_SERIAL_RTS_ACTIVE 1
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-
/* Expansion bus settings */
#define CONFIG_SYS_EXP_CS0 0xbd113842
115200, 230400 }
#define CONFIG_SERIAL_RTS_ACTIVE 1
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-
/* Expansion bus settings */
#define CONFIG_SYS_EXP_CS0 0xbd113042
115200, 230400 }
#define CONFIG_SERIAL_RTS_ACTIVE 1
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-
/* Expansion bus settings */
#define CONFIG_SYS_EXP_CS0 0xbd113442
115200, 230400 }
#define CONFIG_SERIAL_RTS_ACTIVE 1
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-
/* Expansion bus settings */
#define CONFIG_SYS_EXP_CS0 0xbd113003
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/*
* Size of malloc() pool
*/
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/*
* Size of malloc() pool
*/
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/*
* Size of malloc() pool
*/
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
#endif
#define __CONFIG_AM335X_EVM_H
#define CONFIG_AM33XX
-#define CONFIG_CMD_MEMORY /* for mtest */
-#undef CONFIG_GZIP
-#undef CONFIG_ZLIB
-#undef CONFIG_SYS_HUSH_PARSER
-#undef CONFIG_CMD_NET
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
-#define CONFIG_ENV_SIZE 0x400
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 * 1024))
+#define CONFIG_DMA_COHERENT
+#define CONFIG_DMA_COHERENT_SIZE (1 << 20)
+
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT "U-Boot# "
#define CONFIG_SYS_NO_FLASH
#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* commands to include */
+#include <config_cmd_default.h>
+
#define CONFIG_CMD_ASKENV
#define CONFIG_VERSION_VARIABLE
/* set to negative value for no autoboot */
#define CONFIG_BOOTDELAY 3
-#define CONFIG_SYS_AUTOLOAD "no"
-#define CONFIG_BOOTFILE "uImage"
#define CONFIG_EXTRA_ENV_SETTINGS \
- "verify=yes\0" \
- "ramdisk_file=ramdisk.gz\0" \
+ "loadaddr=0x80200000\0" \
+ "fdtaddr=0x80F80000\0" \
+ "rdaddr=0x81000000\0" \
+ "bootfile=/boot/uImage\0" \
+ "console=ttyO0,115200n8\0" \
+ "optargs=\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
+ "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+ "ramrootfstype=ext2\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "bootenv=uEnv.txt\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "ramargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${ramroot} " \
+ "rootfstype=${ramrootfstype}\0" \
+ "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+ "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+ "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "ramboot=echo Booting from ramdisk ...; " \
+ "run ramargs; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan ${mmcdev}; then " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loaduimage; then " \
+ "run mmcboot;" \
+ "fi;" \
+ "fi;" \
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
+#define CONFIG_SPI
+#define CONFIG_OMAP3_SPI
+#define CONFIG_MTD_DEVICE
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED (24000000)
+
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
-#define PHYS_DRAM_1_SIZE 0x10000000 /*(0x80000000 / 8) 256 MB */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
GENERATED_GBL_DATA_SIZE)
/* Platform/Board specific defs */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_I2C_MULTI_BUS
#define CONFIG_DRIVER_OMAP24XX_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+#define CONFIG_OMAP_GPIO
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
#define CONFIG_SPL
#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (46 * 1024)
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
-/* Unsupported features */
-#undef CONFIG_USE_IRQ
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
#endif /* ! __CONFIG_AM335X_EVM_H */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
#define CONFIG_SYS_CLK_FREQ V_SCLK
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE SZ_128K /* regular stack */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
--- /dev/null
+/*
+ * Copyright (C) 2012 Bluegiga Technologies Oy
+ *
+ * Authors:
+ * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
+ * Lauri Hintsala <lauri.hintsala@bluegiga.com>
+ *
+ * Based on m28evk.h:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* SoC configurations */
+#define CONFIG_MX28 /* i.MX28 SoC */
+#define CONFIG_MXS_GPIO /* GPIO control */
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+
+#define MACH_TYPE_APX4DEVKIT 3712
+#define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT
+
+#include <asm/arch/regs-base.h>
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MISC_INIT
+
+/* SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
+#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+
+/* U-Boot Commands */
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_USB
+
+/* Memory configurations */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x40000000 /* Base address */
+#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
+#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
+#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* Point initial SP in SRAM so SPL can use it too. */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
+#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/*
+ * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
+ * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
+ * binary. In case there was more of this mess, 0x100 bytes are skipped.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x40000100
+
+#define CONFIG_ENV_OVERWRITE
+
+/* U-Boot general configurations */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-Boot version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc. */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_OF_LIBFDT
+#define CONFIG_ENV_IS_IN_NAND
+
+/* Serial Driver */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 24000000
+#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* DMA */
+#define CONFIG_APBH_DMA
+
+/* MMC Driver */
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_ENV_SIZE (16 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_BOUNCE_BUFFER
+#define CONFIG_MXS_MMC
+#endif
+
+/* NAND Driver */
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_RANGE (384 * 1024)
+#define CONFIG_ENV_OFFSET 0x120000
+#define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+#endif
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x60000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=gpmi-nand"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=gpmi-nand:128k(bootstrap),1024k(boot),768k(env),-(root)"
+#else
+#define MTDPARTS_DEFAULT ""
+#endif
+
+/* Ethernet on SOC (FEC) */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NET_MULTI
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define IMX_FEC_BASE MXS_ENET0_BASE
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+#define CONFIG_FEC_XCV_TYPE RMII
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MXS
+#define CONFIG_EHCI_MXS_PORT 1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#endif
+
+/* I2C */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MXS
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
+#endif
+
+/* RTC */
+#if defined(CONFIG_CMD_DATE)
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51
+#endif
+
+/* Boot Linux */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTCOMMAND "run bootcmd_nand"
+#define CONFIG_LOADADDR 0x41000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SERIAL_TAG
+#define CONFIG_REVISION_TAG
+
+/* Extra Environments */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "verify=no\0" \
+ "bootcmd=run bootcmd_nand\0" \
+ "kernelargs=console=tty0 console=ttyAMA0,115200 consoleblank=0\0" \
+ "bootargs_nand=" \
+ "setenv bootargs ${kernelargs} ubi.mtd=3,2048 " \
+ "root=ubi0:rootfs rootfstype=ubifs ${mtdparts} rw\0" \
+ "bootcmd_nand=" \
+ "run bootargs_nand && ubi part root 2048 && " \
+ "ubifsmount rootfs && ubifsload 41000000 boot/uImage && " \
+ "bootm 41000000\0" \
+ "bootargs_mmc=" \
+ "setenv bootargs ${kernelargs} " \
+ "root=/dev/mmcblk0p2 rootwait ${mtdparts} rw\0" \
+ "bootcmd_mmc=" \
+ "run bootargs_mmc && mmc rescan && " \
+ "ext2load mmc 0:2 41000000 boot/uImage && bootm 41000000\0" \
+""
+
+#endif /* __CONFIG_H */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_STACKSIZE SZ_32K /* regular stack */
-#define CONFIG_STACKSIZE_IRQ SZ_4K /* Unsure if to big or to small*/
-#define CONFIG_STACKSIZE_FIQ SZ_4K /* Unsure if to big or to small*/
#endif /* __AT91RM9200EK_CONFIG_H__ */
/* Misc CPU related */
#define CONFIG_ARCH_CPU_INIT
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_STACKSIZE (32*1024) /* regular stack */
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
-
#endif
#include <asm/hardware.h>
-#define CONFIG_ARCH_CPU_INIT
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_STACKSIZE (32*1024) /* regular stack */
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
-
#endif
#define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */
#define CONFIG_ARCH_CPU_INIT
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
"update=" \
"protect off ${monitor_base} +${filesize};" \
"erase ${monitor_base} +${filesize};" \
- "cp.b ${load_addr} ${monitor_base} ${filesize};" \
+ "cp.b ${fileaddr} ${monitor_base} ${filesize};" \
"protect on ${monitor_base} +${filesize}\0"
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_STACKSIZE (32*1024) /* regular stack */
-
-#undef CONFIG_USE_IRQ
-
#endif
#define CONFIG_AT91SAM9M10G45EK
#define CONFIG_AT91FAMILY
-#define CONFIG_ARCH_CPU_INIT
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_STACKSIZE (32*1024) /* regular stack */
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
-
#endif
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_STACKSIZE (32*1024) /* regular stack */
-
-#undef CONFIG_USE_IRQ
-
#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ *
+ * Configuation settings for the AT91SAM9X5EK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+#include <asm/hardware.h>
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_AT91SAM9X5EK
+#define CONFIG_AT91FAMILY
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE ATMEL_BASE_DBGU
+#define CONFIG_USART_ID ATMEL_ID_SYS
+
+/* LCD */
+#define CONFIG_LCD
+#define LCD_BPP LCD_COLOR16
+#define LCD_OUTPUT_BPP 24
+#define CONFIG_LCD_LOGO
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_ATMEL_HLCD
+#define CONFIG_ATMEL_LCD_RGB565
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_SF
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* DataFlash */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#endif
+
+/* no NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_DBW_8 1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
+
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC 1
+#define CONFIG_ATMEL_NAND_HW_PMECC 1
+#define CONFIG_PMECC_CAP 2
+#define CONFIG_PMECC_SECTOR_SIZE 512
+#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_MACB_SEARCH_PHY
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END 0x26e00000
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0xc0000
+#define CONFIG_ENV_OFFSET_REDUND 0x100000
+#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND "nand read " \
+ "0x22000000 0x200000 0x300000; " \
+ "bootm 0x22000000"
+#else
+#ifdef CONFIG_SYS_USE_SPIFLASH
+/* bootstrap + u-boot + env + linux in spi flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x5000
+#define CONFIG_ENV_SIZE 0x3000
+#define CONFIG_ENV_SECT_SIZE 0x1000
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+#define CONFIG_BOOTCOMMAND "sf probe 0; " \
+ "sf read 0x22000000 0x100000 0x300000; " \
+ "bootm 0x22000000"
+#endif
+#endif
+
+#define CONFIG_BOOTARGS "mem=128M console=ttyS0,115200 " \
+ "mtdparts=atmel_nand:" \
+ "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \
+ "root=/dev/mtdblock1 rw " \
+ "rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_SYS_PROMPT "U-Boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) \
+ + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*
* DRAM Map
*/
#define LINUX_BOOT_PARAM_ADDR 0x60000200
#define CONFIG_BOOTDELAY 2
-/* Stack sizes are set up in start.S using the settings below */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
-#endif
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 0x60000000 /* SDRAM Bank #1 */
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20))
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define CONFIG_STACKSIZE (256*1024) /* regular stack */
/*
* Serial Driver info
#define CONFIG_MX_CYCLIC
/* U-Boot general configuration */
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_PROMPT "cam_enc_4xx> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_TIMESTAMP
/* U-Boot memory configuration */
-#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* physical address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* test 16MB RAM */
#define CONFIG_KS8695 1 /* it is a KS8695 CPU */
#define CONFIG_CM4008 1 /* it is an OpenGear CM4008 boad */
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_SYS_HZ (1000) /* 1ms resolution ticks */
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_KS8695 1 /* it is a KS8695 CPU */
#define CONFIG_CM41xx 1 /* it is an OpenGear CM41xx boad */
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_SYS_HZ (1000) /* 1ms resolution ticks */
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
*/
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP34XX /* which is a 34XX */
+#define CONFIG_OMAP_GPIO
#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
#define CONFIG_SYS_TEXT_BASE 0x80008000
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT 1
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */
#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
-#endif
-
/*
* DRAM Map
*/
#define CONFIG_AT91FAMILY
#define CONFIG_ARCH_CPU_INIT
-#undef CONFIG_USE_IRQ
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
GENERATED_GBL_DATA_SIZE)
-#define CONFIG_STACKSIZE (32 * 1024)
-
-#if defined(CONFIG_USE_IRQ)
-#error CONFIG_USE_IRQ not supported
-#endif
-
#endif
#define CONFIG_ARM920T
#define CONFIG_AT91RM9200
#define CONFIG_CPUAT91
-#undef CONFIG_USE_IRQ
#define USE_920T_MMU
#include <asm/hardware.h> /* needed for port definitions */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
GENERATED_GBL_DATA_SIZE)
-#define CONFIG_STACKSIZE (32 * 1024)
-#define CONFIG_STACKSIZE_IRQ (4 * 1024)
-#define CONFIG_STACKSIZE_FIQ (4 * 1024)
-
-
-#if defined(CONFIG_USE_IRQ)
-#error CONFIG_USE_IRQ not supported
-#endif
-
#define CONFIG_DEVICE_NULLDEV
#define CONFIG_SILENT_CONSOLE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
(32 << 20))
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define CONFIG_STACKSIZE (256*1024) /* regular stack */
/*
* Serial Driver info
/*
* U-Boot general configuration
*/
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#undef CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
* Board
*/
#define CONFIG_DRIVER_TI_EMAC
+/* check if direct NOR boot config is used */
+#ifndef CONFIG_DIRECT_NOR_BOOT
#define CONFIG_USE_SPIFLASH
+#endif
/*
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_TEXT_BASE 0xc1080000
#define CONFIG_SYS_DA850_PLL_INIT
#define CONFIG_SYS_DA850_DDR_INIT
+#ifdef CONFIG_DIRECT_NOR_BOOT
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DA8XX_GPIO
+#define CONFIG_SYS_TEXT_BASE 0x60000000
+#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
+#define CONFIG_DA850_LOWLEVEL
+#else
+#define CONFIG_SYS_TEXT_BASE 0xc1080000
+#endif
+
/*
* Memory Info
*/
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#ifdef CONFIG_USE_SPIFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
+#endif
+
/*
* I2C Configuration
*/
#define CONFIG_SYS_ALE_MASK 0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
+ CONFIG_SYS_NAND_U_BOOT_SIZE - \
+ CONFIG_SYS_MALLOC_LEN - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS { \
+ 24, 25, 26, 27, 28, \
+ 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
+ 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
+ 59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 10
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_LOAD
#endif
/*
#undef CONFIG_CMD_ENV
#endif
+/* SD/MMC configuration */
+#ifndef CONFIG_USE_NOR
+#define CONFIG_MMC
+#define CONFIG_DAVINCI_MMC_SD1
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#endif
+
+/*
+ * Enable MMC commands only when
+ * MMC support is present
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#endif
+
+#ifndef CONFIG_DIRECT_NOR_BOOT
/* defines for SPL */
#define CONFIG_SPL
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_STACK 0x8001ff00
#define CONFIG_SPL_TEXT_BASE 0x80000000
#define CONFIG_SPL_MAX_SIZE 32768
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
-#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
+#endif
+
+/* Load U-Boot Image From MMC */
+#ifdef CONFIG_SPL_MMC_LOAD
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SYS_MMC_U_BOOT_OFFS 0x75
+#define CONFIG_SYS_MMC_U_BOOT_SIZE 0x30000
+#undef CONFIG_SPL_SPI_LOAD
+#endif
/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+
+#ifdef CONFIG_DIRECT_NOR_BOOT
+#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
+#else
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_DIRECT_NOR_BOOT */
#endif /* __CONFIG_H */
#define CONFIG_MX_CYCLIC
/* U-Boot general configuration */
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_PROMPT "DM355 EVM # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_NET_RETRY_COUNT 10
/* U-Boot memory configuration */
-#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
#define CONFIG_MX_CYCLIC
/* U-Boot general configuration */
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_PROMPT "DM355 LEOPARD # "
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_NET_RETRY_COUNT 10
/* U-Boot memory configuration */
-#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
#define CONFIG_MX_CYCLIC
/* U-Boot general configuration */
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_PROMPT "DM36x EVM # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_TIMESTAMP
/* U-Boot memory configuration */
-#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE (256 << 20) /* DDR size 256MB */
#endif
/* U-Boot general configuration */
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_PROMPT "DM6467 EVM > " /* Monitor Command Prompt */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */
/* U-Boot general configuration */
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
-#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
* Memory configurations
*/
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_STACKSIZE SZ_32K
#define CONFIG_SYS_MALLOC_LEN SZ_1M
#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
+#define CONFIG_OMAP_GPIO
+
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
* 64 bytes before this address should be set aside for u-boot.img's
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/* The stack sizes are set up in start.S using the settings below */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
*/
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP34XX /* which is a 34XX */
+#define CONFIG_OMAP_GPIO
#define CONFIG_SYS_TEXT_BASE 0x80008000
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
-#endif
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
115200, 230400 }
#define CONFIG_SERIAL_RTS_ACTIVE 1
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-
/* Expansion bus settings */
#define CONFIG_SYS_EXP_CS0 0xbd113442
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define CONFIG_STACKSIZE (256*1024) /* regular stack */
/*
* Serial Driver info
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_STACKSIZE (32*1024) /* regular stack */
-
/*
* ARM asynchronous clock
*/
#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_STACKSIZE 0x00100000
#define CONFIG_SYS_LOAD_ADDR 0x00800000
#define CONFIG_SYS_MEMTEST_START 0x00400000
#define CONFIG_SYS_MEMTEST_END 0x007fffff
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define CONFIG_STACKSIZE (256*1024) /* regular stack */
/*
* Serial Driver info
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#define CONFIG_SYS_HZ 1000
-#undef CONFIG_USE_IRQ /* Running w/o interrupts */
/* 32kB internal SRAM */
#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
#define CONFIG_SRAM_SIZE (32 << 10)
-#define CONFIG_STACKSIZE (CONFIG_SRAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_STACKSIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/* 128MB SDRAM in 1 bank */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_HZ 1000
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/*
* Physical Memory Map
*/
#define __CONFIG_H
#include <asm/sizes.h>
-#include "tegra2-common.h"
+#include "tegra20-common.h"
/* Enable fdt support for Harmony. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra2-harmony
+#define CONFIG_DEFAULT_DEVICE_TREE tegra20-harmony
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
-#define V_PROMPT "Tegra2 (Harmony) # "
-#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Harmony"
+#define V_PROMPT "Tegra20 (Harmony) # "
+#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Harmony"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA2_ENABLE_UARTD
+#define CONFIG_TEGRA20_ENABLE_UARTD
/* UARTD: keyboard satellite board UART, default */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-#ifdef CONFIG_TEGRA2_ENABLE_UARTA
+#ifdef CONFIG_TEGRA20_ENABLE_UARTA
/* UARTA: debug board UART */
#define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE
#endif
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
-#include "tegra2-common-post.h"
+#include "tegra20-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_AIS_CONFIG_FILE "board/$(BOARDDIR)/hawkboard-ais-nand.cfg"
#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
DAVINCI_SYSCFG_SUSPSRC_EMAC | \
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024)
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define CONFIG_STACKSIZE (256*1024) /* regular stack */
/*
* Serial Driver info
#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0xe0000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1180000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
#endif /* CONFIG_SYS_USE_NAND */
+/* USB Configs */
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_OHCI_DA8XX
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x01E25000
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "hawkboard"
+
/*
* U-Boot general configuration
*/
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_EXT2
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#define CONFIG_SYS_LOAD_ADDR 0x800000
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
+#ifdef CONFIG_BOOT_ONENAND
#define CONFIG_CMD_ONENAND /* ONENAND support */
+#endif
+#ifdef CONFIG_BOOT_NAND
+#define CONFIG_CMD_NAND
+#endif
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
"usbtty=cdc_acm\0" \
"loadaddr=0x82000000\0" \
"usbtty=cdc_acm\0" \
- "console=ttyS2,115200n8\0" \
+ "console=ttyO2,115200n8\0" \
"mpurate=auto\0" \
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
"defaultdisplay=dvi\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
"nandroot=/dev/mtdblock4 rw\0" \
"nandrootfstype=jffs2\0" \
"mmcargs=setenv bootargs console=${console} " \
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/*
* Physical Memory Map
*
* FLASH and environment organization
*/
+#ifdef CONFIG_BOOT_ONENAND
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define CONFIG_ENV_IS_IN_ONENAND 1
#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
+#endif
+
+#ifdef CONFIG_BOOT_NAND
+#define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_BASE NAND_BASE
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
+#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
+#define CONFIG_ENV_ADDR NAND_ENV_OFFSET
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#endif
/*
* Size of malloc() pool
#define CONFIG_SMC911X_BASE 0x2C000000
#endif /* (CONFIG_CMD_NET) */
+/*
+ * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
+ * and older u-boot.bin with the new U-Boot SPL.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x80008000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
+/* SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_TEXT_BASE 0x40200800
+#define CONFIG_SPL_MAX_SIZE (54 * 1024)
+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+
+/* move malloc and bss high to prevent clashing with the main image */
+#define CONFIG_SYS_SPL_MALLOC_START 0x87000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
+
+/* MMC boot config */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+#ifdef CONFIG_BOOT_ONENAND
+#define CONFIG_SPL_ONENAND_SUPPORT
+
+/* OneNAND boot config */
+#define CONFIG_SYS_ONENAND_U_BOOT_OFFS 0x80000
+#define CONFIG_SYS_ONENAND_PAGE_SIZE 2048
+#define CONFIG_SPL_ONENAND_LOAD_ADDR 0x80000
+#define CONFIG_SPL_ONENAND_LOAD_SIZE \
+ (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
+
+#endif
+
+#ifdef CONFIG_BOOT_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
+ 10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+#endif
+
#endif /* __IGEP00X0_H */
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
-/* Stack sizes */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define CONFIG_SYS_MEMTEST_START 0xA0000000
#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
#define CONFIG_MXC_MMC
#define CONFIG_DOS_PARTITION
+/*
+ * GPIO
+ */
+#define CONFIG_MXC_GPIO
+
/*
* MTD partitions
*/
#define CONFIG_CMDLINE_EDITING 1
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_CMDLINE_EDITING
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/*
* Physical Memory Map
*/
#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_TEXT_BASE 0x10000000
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_SYS_MALLOC_LEN (10 << 20)
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 20)
-#define CONFIG_STACKSIZE (32*1024) /* regular stack */
-
/*
* Clock reset generator init
*/
#define CONFIG_SYS_DDR2_INIT_DRIC1_10 0x0005
#define CONFIG_SYS_DDR2_INIT_DRIC2_10 0x0002
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
-
#endif /* __CONFIG_H */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF
-#undef CONFIG_USE_IRQ
/* Console setting */
#define CONFIG_SYS_CPUSPEED 0x0a /* core clock 206MHz */
#define CONFIG_SYS_BAUDRATE_TABLE { 19200, 38400, 57600, 115200 }
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
#define CONFIG_NR_DRAM_BANKS 4
-#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
/*
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_TEXT_BASE 0x0
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_MMC_BASE 0xF0000000
#endif
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*
* Physical Memory Map
*/
#ifndef __M28EVK_CONFIG_H__
#define __M28EVK_CONFIG_H__
-#include <asm/arch/regs-base.h>
-
/*
* SoC configurations
*/
#define CONFIG_MACH_TYPE MACH_TYPE_M28EVK
+#include <asm/arch/regs-base.h>
+
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_MISC_INIT
*/
#define CONFIG_SPL
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
-#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mx28"
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
+#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
-#define CONFIG_STACKSIZE (128 * 1024) /* 128 KB stack */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
#ifdef CONFIG_CMD_SPI
#define CONFIG_HARD_SPI
#define CONFIG_MXS_SPI
+#define CONFIG_MXS_SPI_DMA_ENABLE
#define CONFIG_SPI_HALF_DUPLEX
#define CONFIG_DEFAULT_SPI_BUS 2
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SF_DEFAULT_CS 2
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_SF_DEFAULT_SPEED 24000000
+#define CONFIG_SF_DEFAULT_SPEED 40000000
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_BUS 2
-#define CONFIG_ENV_SPI_MAX_HZ 24000000
+#define CONFIG_ENV_SPI_MAX_HZ 40000000
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
#endif
#endif
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP34XX /* which is a 34XX */
#define CONFIG_OMAP3_MCX /* working with mcx */
+#define CONFIG_OMAP_GPIO
#define MACH_TYPE_MCX 3656
#define CONFIG_MACH_TYPE MACH_TYPE_MCX
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_GPIO
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_BOOTFILE "uImage"
+#define xstr(s) str(s)
+#define str(s) #s
+
+/* Setup MTD for NAND on the SOM */
+#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
+ "1m(u-boot),256k(env1)," \
+ "256k(env2),6m(kernel),6m(k_recovery)," \
+ "8m(fs_recovery),-(common_data)"
+
+#define CONFIG_HOSTNAME mcx
#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyO2,115200n8\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "root=/dev/mmcblk0p2 rw " \
- "rootfstype=ext3 rootwait\0" \
- "nandargs=setenv bootargs console=${console} " \
- "root=/dev/mtdblock4 rw " \
- "rootfstype=jffs2\0" \
- "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${loadaddr} 280000 400000; " \
- "bootm ${loadaddr}\0" \
+ "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \
+ "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \
+ "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
+ "addfb=setenv bootargs ${bootargs} vram=6M " \
+ "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:eth0:off\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "addtty=setenv bootargs ${bootargs} " \
+ "console=${consoledev},${baudrate}\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "baudrate=115200\0" \
+ "consoledev=ttyO2\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "loadaddr=0x82000000\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "load_k=tftp ${loadaddr} ${bootfile}\0" \
+ "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+ "loadmlo=tftp ${loadaddr} ${mlo}\0" \
+ "mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0" \
+ "mmcargs=root=/dev/mmcblk0p2 rw " \
+ "rootfstype=ext3 rootwait\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "run addip addtty addmtd addfb addeth addmisc;" \
+ "run loaduimage; " \
+ "bootm ${loadaddr}\0" \
+ "net_nfs=run load_k; " \
+ "run nfsargs; " \
+ "run addip addtty addmtd addfb addeth addmisc;" \
+ "bootm ${loadaddr}\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0" \
+ "uboot_addr=0x80000\0" \
+ "update=nandecc sw;nand erase ${uboot_addr} 100000;" \
+ "nand write ${loadaddr} ${uboot_addr} 80000\0" \
+ "updatemlo=nandecc hw;nand erase 0 20000;" \
+ "nand write ${loadaddr} 0 20000\0" \
+ "upd=if run load;then echo Updating u-boot;if run update;" \
+ "then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source ${loadaddr}\0" \
+ "nandargs=setenv bootargs ubi.mtd=7 " \
+ "root=ubi0:rootfs rootfstype=ubifs\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "ubi part nand0,4;" \
+ "ubi readvol ${loadaddr} kernel;" \
+ "run addip addtty addmtd addfb addeth addmisc;" \
+ "bootm ${loadaddr}\0" \
+ "swupdate_args=setenv bootargs ubi.mtd=6 root=ubi0:fs_recovery "\
+ "rootfstype=ubifs quiet loglevel=1 " \
+ "consoleblank=0 ${swupdate_misc}\0" \
+ "swupdate=echo Running Sw-Update...;" \
+ "if printenv mtdparts;then echo Starting SwUpdate...; " \
+ "else mtdparts default;fi; " \
+ "ubi part nand0,5;" \
+ "ubi readvol 0x82000000 kernel_recovery;" \
+ "run swupdate_args; " \
+ "setenv bootargs ${bootargs} " \
+ "${mtdparts} " \
+ "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
+ "omapdss.def_disp=lcd;" \
+ "bootm ${loadaddr}\0"
#define CONFIG_BOOTCOMMAND \
- "if mmc init; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run nandboot; " \
- "fi; " \
- "fi; " \
- "else run nandboot; fi"
+ "run nandboot"
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT V_PROMPT
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/*
* Physical Memory Map
*/
#define CONFIG_NAND_OMAP_GPMC
#define GPMC_NAND_ECC_LP_x16_LAYOUT
#define CONFIG_ENV_IS_IN_NAND
-#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
+/* Redundant Environment */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-
-/*
- * CFI FLASH driver setup
- */
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
+ 2 * CONFIG_SYS_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
#ifndef __CONFIG_H
#define __CONFIG_H
-#include "tegra2-common.h"
+#include "tegra20-common.h"
/* Enable fdt support for Medcom. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra2-medcom
+#define CONFIG_DEFAULT_DEVICE_TREE tegra20-medcom
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
-#define V_PROMPT "Tegra2 (Medcom) # "
-#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Medcom"
+#define V_PROMPT "Tegra20 (Medcom) # "
+#define CONFIG_TEGRA20_BOARD_STRING "Avionic Design Medcom"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA2_ENABLE_UARTD /* UARTD: debug UART */
+#define CONFIG_TEGRA20_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
-#include "tegra2-common-post.h"
+#include "tegra20-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_REVISION_TAG
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_MISC_INIT_R /* Call misc_init_r */
-#undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */
#define CONFIG_DISPLAY_BOARDINFO /* call checkboard() */
#define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
128*1024, 0x1000)
-#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
-
-#ifdef CONFIG_USE_IRQ
-# error CONFIG_USE_IRQ not supported
-#endif
-
#endif
#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
#define CONFIG_BOARD_EARLY_INIT_F /* call board_init_f for early inits */
#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
-#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */
#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
#define CONFIG_IMX 1 /* It's a Motorola MC9328 SoC */
#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/*
* Select serial console configuration
#define CONFIG_SYS_HZ 3686400
#define CONFIG_SYS_CPUSPEED 0x141
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE/2)
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
-/* Stack sizes */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/* Serial Info */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#ifndef __MX28EVK_CONFIG_H__
#define __MX28EVK_CONFIG_H__
-#include <asm/arch/regs-base.h>
-
/*
* SoC configurations
*/
#define CONFIG_MX28 /* i.MX28 SoC */
+
#define CONFIG_MXS_GPIO /* GPIO control */
#define CONFIG_SYS_HZ 1000 /* Ticks per second */
#define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK
+#include <asm/arch/regs-base.h>
+
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_MISC_INIT
*/
#define CONFIG_SPL
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
-#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mx28"
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
+#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */
-#define CONFIG_STACKSIZE (128 * 1024) /* 128 KB stack */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
#define CONFIG_SF_DEFAULT_SPEED 24000000
/* (redundant) environemnt in SPI flash */
-#undef CONFIG_ENV_IS_IN_SPI_FLASH
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SIZE 0x1000 /* 4KB */
#define CONFIG_CMDLINE_EDITING 1
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_CMDLINE_EDITING
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_HZ 1000
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/*
* Physical Memory Map
*/
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_VIDEO_IPUV3
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
-/* Stack sizes */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define CONFIG_CMD_NET
#define CONFIG_CMD_DATE
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
-/* Stack sizes */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
-/* Stack sizes */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define CONFIG_VIDEO_IPUV3
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
-/* Stack sizes */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE (128 * 1024)
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_MACH_TYPE 3769
#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS (0|(GPIO_NUMBER(3, 19)<<8))
+#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8))
#define CONFIG_SF_DEFAULT_SPEED 25000000
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
#endif
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE (128 * 1024)
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_TEXT_BASE 0x00000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + (1<<20))
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-# define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
-# define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
-#endif
-
#define CONFIG_SYS_MEMTEST_START 0x00000000
#define CONFIG_SYS_MEMTEST_END 0x0FFFFFFF
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024)
#define AHB_CLK_FREQ (CONFIG_SYS_CLK_FREQ/4)
#define BBUS_CLK_FREQ (CONFIG_SYS_CLK_FREQ/8)
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/*@TODO #define CONFIG_STATUS_LED*/
#define CONFIG_USE_IRQ
/*-----------------------------------------------------------------------
* Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
*/
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000 /* the OMAP1510 Innovator has 12MHz input clock */
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
#define CONFIG_SYS_CLK_FREQ V_SCLK
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */
#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE SZ_128K /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
-#endif
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
+#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT 1
"bootfile=uImage.beagle\0" \
"console=ttyO2,115200n8\0" \
"mpurate=auto\0" \
- "buddy=none "\
+ "buddy=none\0" \
"optargs=\0" \
"camera=none\0" \
"vram=12M\0" \
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_OMAP3_ID_NAND
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
*/
#define CONFIG_OMAP /* This is TI OMAP core */
#define CONFIG_OMAP34XX /* belonging to 34XX family */
+#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
#define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
-#undef CONFIG_USE_IRQ /* no support for IRQs */
-
/*
* Clock related definitions
*/
/* Size of malloc pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
-/*
- * Stack sizes
- * These values are used in start.S
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/*
* Physical Memory Map
* Note 1: CS1 may or may not be populated
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP34XX /* which is a 34XX */
#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */
-
-#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_OMAP_GPIO
#define CONFIG_SYS_TEXT_BASE 0x80400000
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/*
* Physical Memory Map
*/
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
+#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT 1
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP34XX /* which is a 34XX */
#define CONFIG_OMAP3_OVERO /* working with overo */
+#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_PANDORA 1 /* working with pandora */
+#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
-
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */
+#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using these settings
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP44XX 1 /* which is a 44XX */
#define CONFIG_OMAP4430 1 /* which is in a 4430 */
+#define CONFIG_OMAP_GPIO
/* Get CPU defs */
#include <asm/arch/cpu.h>
#define V_OSCK 38400000 /* Clock output from T2 */
#define V_SCLK V_OSCK
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT 1
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
-#endif
-
/*
* SDRAM Memory Map
* Even though we use two CS all the memory
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
+#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
GENERATED_GBL_DATA_SIZE)
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SPL
#define CONFIG_SPL_TEXT_BASE 0x40304350
#define CONFIG_SPL_MAX_SIZE (38 * 1024)
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
/*
* 64 bytes before this address should be set aside for u-boot.img's
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SYS_THUMB_BUILD
/* the OMAP5912 OSK has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1 /* Required for ramdisk support */
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_OMAP54XX /* which is a 54XX */
#define CONFIG_OMAP5430 /* which is in a 5430 */
#define CONFIG_5430EVM /* working with EVM */
+#define CONFIG_OMAP_GPIO
/* Get CPU defs */
#include <asm/arch/cpu.h>
#define V_OSCK 19200000 /* Clock output from T2 */
#define V_SCLK V_OSCK
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
-#endif
-
/*
* SDRAM Memory Map
* Even though we use two CS all the memory
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
-#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
+#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#define CONFIG_SPL
#define CONFIG_SPL_TEXT_BASE 0x40300350
#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */
-#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_CLK_FREQ 13000000
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_HZ 1000
-/* Stack sizes */
-#define CONFIG_STACKSIZE (256 << 10) /* 256KB */
-
/* ORIGEN has 4 bank of DRAM */
#define CONFIG_NR_DRAM_BANKS 4
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
#undef CONFIG_CMD_IMLS
#define CONFIG_IDENT_STRING " for ORIGEN"
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
#define CONFIG_CLK_1000_400_200
/* MIU (Memory Interleaving Unit) */
#define CONFIG_REVISION_TAG
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_MISC_INIT_R /* Call misc_init_r */
-#undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */
#define CONFIG_DISPLAY_BOARDINFO /* call checkboard() */
#define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
128*1024, 0x1000)
-#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
-
-#ifdef CONFIG_USE_IRQ
-# error CONFIG_USE_IRQ not supported
-#endif
-
#endif
#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*
* DRAM Map
*/
#define CONFIG_SYS_HZ 3686400 /* Timer @ 3686400 Hz */
#define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*
* DRAM Map
*/
#define __CONFIG_H
#include <asm/sizes.h>
-#include "tegra2-common.h"
+#include "tegra20-common.h"
/* Enable fdt support for Paz00. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra2-paz00
+#define CONFIG_DEFAULT_DEVICE_TREE tegra20-paz00
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
-#define V_PROMPT "Tegra2 (Paz00) MOD # "
-#define CONFIG_TEGRA2_BOARD_STRING "Compal Paz00"
+#define V_PROMPT "Tegra20 (Paz00) MOD # "
+#define CONFIG_TEGRA20_BOARD_STRING "Compal Paz00"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA2_ENABLE_UARTA
+#define CONFIG_TEGRA20_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
-#include "tegra2-common-post.h"
+#include "tegra20-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_IXP425_TIMER_CLK 66666666
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/***************************************************************
* Platform/Board specific defines start here.
***************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
-#include "tegra2-common.h"
+#include "tegra20-common.h"
/* Enable fdt support for Plutux. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra2-plutux
+#define CONFIG_DEFAULT_DEVICE_TREE tegra20-plutux
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
-#define V_PROMPT "Tegra2 (Plutux) # "
-#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Plutux"
+#define V_PROMPT "Tegra20 (Plutux) # "
+#define CONFIG_TEGRA20_BOARD_STRING "Avionic Design Plutux"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA2_ENABLE_UARTD /* UARTD: debug UART */
+#define CONFIG_TEGRA20_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
-#include "tegra2-common-post.h"
+#include "tegra20-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
#define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */
#define CONFIG_ARCH_CPU_INIT
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_SYS_TEXT_BASE 0
#define MACH_TYPE_PM9261 1187
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
GENERATED_GBL_DATA_SIZE)
-#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
-
#endif
#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263"
#define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
#define CONFIG_ARCH_CPU_INIT
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_SYS_TEXT_BASE 0
#define MACH_TYPE_PM9263 1475
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
GENERATED_GBL_DATA_SIZE)
-#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
-
#endif
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
GENERATED_GBL_DATA_SIZE)
-#define CONFIG_STACKSIZE (32*1024) /* regular stack */
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
-
#endif
#define CONFIG_DOS_PARTITION 1
#define CONFIG_BOARD_LATE_INIT
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_MMC_BASE 0xF0000000
#endif
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*
* Physical Memory Map
*/
#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
#define CONFIG_MISC_INIT_R
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
/*-----------------------------------------------------------------------
* Physical Memory Map
--- /dev/null
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+
+/* Architecture, CPU, etc.*/
+#define CONFIG_ARM1176
+#define CONFIG_BCM2835
+#define CONFIG_ARCH_CPU_INIT
+/*
+ * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
+ * so 2708 has historically been used rather than a dedicated 2835 ID.
+ */
+#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708
+
+/* Timer */
+#define CONFIG_SYS_HZ 1000000
+
+/* Memory layout */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_TEXT_BASE 0x00008000
+#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
+/*
+ * The board really has 256M. However, the VC (VideoCore co-processor) shares
+ * the RAM, and uses a configurable portion at the top. We tell U-Boot that a
+ * smaller amount of RAM is present in order to avoid stomping on the area
+ * the VC uses.
+ */
+#define CONFIG_SYS_SDRAM_SIZE SZ_128M
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_SDRAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_MALLOC_LEN SZ_4M
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x00200000
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* Devices */
+/* GPIO */
+#define CONFIG_BCM2835_GPIO
+
+/* Console UART */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 3000000
+#define CONFIG_PL01x_PORTS { (void *)0x20201000 }
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200
+
+/* Console configuration */
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Environment */
+#define CONFIG_ENV_SIZE SZ_16K
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_LOAD_ADDR 0x1000000
+
+/* Shell */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_MAXARGS 8
+#define CONFIG_SYS_PROMPT "U-Boot> "
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_AUTO_COMPLETE
+
+/* Commands */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_GPIO
+/* Some things don't make sense on this HW or yet */
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SAVEENV
+
+/* Device tree support for bootm/bootz */
+#define CONFIG_OF_LIBFDT
+/* ATAGs support for bootm/bootz */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+
+#endif
#define CONFIG_SYS_HZ 1000
-/* Stack sizes */
-#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
-
/* Goni has 3 banks of DRAM, but swap the bank */
#define CONFIG_NR_DRAM_BANKS 3
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */
#define CONFIG_SYS_HZ 1000
-/* Stack sizes */
-#define CONFIG_STACKSIZE (256 << 10) /* regular stack 256KB */
-
/* Universal has 2 banks of DRAM */
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
#define CONFIG_SYS_HZ 1000
#define CONFIG_ARCH_CPU_INIT
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
#endif
--- /dev/null
+/*
+ * SchulerControl GmbH, SC_SPS_1 module config
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __SC_SPS_1_H__
+#define __SC_SPS_1_H__
+
+/*
+ * SoC configurations
+ */
+#define CONFIG_MX28 /* i.MX28 SoC */
+#define CONFIG_MXS_GPIO /* GPIO control */
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+
+/*
+ * Define SC_SPS_1 machine type by hand until it lands in mach-types
+ */
+#define MACH_TYPE_SC_SPS_1 4172
+
+#define CONFIG_MACH_TYPE MACH_TYPE_SC_SPS_1
+
+#include <asm/arch/regs-base.h>
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ARCH_MISC_INIT
+
+#define CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_OF_LIBFDT
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
+#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_USB
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x40000000 /* Base address */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */
+#define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */
+#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
+#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* Point initial SP in SRAM so SPL can use it too. */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
+#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+/*
+ * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
+ * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
+ * binary. In case there was more of this mess, 0x100 bytes are skipped.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x40000100
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 24000000
+#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_APBH_DMA
+#define CONFIG_MMC
+#define CONFIG_MMC_BOUNCE_BUFFER
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXS_MMC
+#endif
+#define CONFIG_ENV_SIZE (16 * 1024)
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET (256 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_ETHPRIME "FEC0"
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_MULTI
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MXS
+#define CONFIG_EHCI_MXS_PORT 0
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200"
+#define CONFIG_BOOTCOMMAND "bootm "
+#define CONFIG_LOADADDR 0x42000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "update_sd_firmware_filename=u-boot.sd\0" \
+ "update_sd_firmware=" /* Update the SD firmware partition */ \
+ "if mmc rescan ; then " \
+ "if tftp ${update_sd_firmware_filename} ; then " \
+ "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
+ "setexpr fw_sz ${fw_sz} + 1 ; " \
+ "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
+ "fi ; " \
+ "fi\0"
+
+#endif /* __SC_SPS_1_H__ */
#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */
#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */
#define CONFIG_SCB9328 1 /* on a scb9328tronix board */
-#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
#define CONFIG_IMX_SERIAL
#define CONFIG_IMX_SERIAL1
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
-#define CONFIG_STACKSIZE (120<<10) /* stack size */
-
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
-#endif
-
/* SDRAM Setup Values
0x910a8300 Precharge Command CAS 3
0x910a8200 Precharge Command CAS 2
#include <asm/sizes.h>
/* LP0 suspend / resume */
-#define CONFIG_TEGRA2_LP0
+#define CONFIG_TEGRA20_LP0
#define CONFIG_AES
#define CONFIG_TEGRA_PMU
#define CONFIG_TPS6586X_POWER
#define CONFIG_TEGRA_CLOCK_SCALING
-#include "tegra2-common.h"
+#include "tegra20-common.h"
/* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra2-seaboard
+#define CONFIG_DEFAULT_DEVICE_TREE tegra20-seaboard
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
-#define V_PROMPT "Tegra2 (SeaBoard) # "
-#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Seaboard"
+#define V_PROMPT "Tegra20 (SeaBoard) # "
+#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Seaboard"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA2_ENABLE_UARTD
+#define CONFIG_TEGRA20_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
#define CONFIG_CMD_DHCP
/* Enable keyboard */
-#define CONFIG_TEGRA2_KEYBOARD
+#define CONFIG_TEGRA20_KEYBOARD
#define CONFIG_KEYBOARD
-#undef TEGRA2_DEVICE_SETTINGS
-#define TEGRA2_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \
+#undef TEGRA20_DEVICE_SETTINGS
+#define TEGRA20_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \
"stdout=serial\0" \
"stderr=serial\0"
-#include "tegra2-common-post.h"
+#include "tegra20-common-post.h"
#endif /* __CONFIG_H */
/* input clock of PLL (the SMDK2410 has 12MHz input clock) */
#define CONFIG_SYS_CLK_FREQ 12000000
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_LZO
#define CONFIG_LZMA
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
/* select serial console configuration */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_SERIAL1 /* use SERIAL 1 */
+#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_BAUDRATE 115200
#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
#define CONFIG_SPL
#define COPY_BL2_FNPTR_ADDR 0x02020030
+/* specific .lds file */
+#define CONFIG_SPL_LDSCRIPT "board/samsung/smdk5250/smdk5250-uboot-spl.lds"
+#define CONFIG_SPL_TEXT_BASE 0x02023400
+#define CONFIG_SPL_MAX_SIZE (14 * 1024)
+
#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
/* Miscellaneous configurable options */
#define CONFIG_RD_LVL
-/* Stack sizes */
-#define CONFIG_STACKSIZE (256 << 10) /* 256KB */
-
#define CONFIG_NR_DRAM_BANKS 8
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_HZ 1000
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE 0x40000 /* regular stack 256KB */
-
/**********************************
Support Clock Settings
**********************************
#define CONFIG_SYS_HZ 1000
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
-
/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
#define CONFIG_SYS_HZ 1000
-/* Stack sizes */
-#define CONFIG_STACKSIZE (256 << 10) /* 256KB */
-
/* SMDKV310 has 4 bank of DRAM */
#define CONFIG_NR_DRAM_BANKS 4
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
#undef CONFIG_CMD_IMLS
#define CONFIG_IDENT_STRING " for SMDKC210/V310"
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
#define CONFIG_CLK_1000_400_200
/* MIU (Memory Interleaving Unit) */
/* CPU */
#define CONFIG_ARCH_CPU_INIT
-#undef CONFIG_USE_IRQ
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
/* U-Boot memory settings */
#define CONFIG_SYS_MALLOC_LEN (1 << 20)
-#define CONFIG_STACKSIZE (256 << 10)
/* Command line configuration */
#include <config_cmd_default.h>
--- /dev/null
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * #define DEBUG 1
+ */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SNOWBALL
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_BOARD_LATE_INIT
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_U8500
+#define CONFIG_L2_OFF
+
+#define CONFIG_SYS_MEMTEST_START 0x00000000
+#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF
+#define CONFIG_SYS_HZ 1000 /* must be 1000 */
+
+/*-----------------------------------------------------------------------
+ * Size of environment and malloc() pool
+ */
+/*
+ * If you use U-Boot as crash kernel, make sure that it does not overwrite
+ * information saved by kexec during panic. Kexec expects the start
+ * address of the executable 32K above "crashkernel" address.
+ */
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (8*1024)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_ENV_OFFSET 0x0118000
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */
+
+/*
+ * PL011 Configuration
+ */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_SERIAL_RLCR
+#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT
+
+/*
+ * U8500 UART registers base for 3 serial devices
+ */
+#define CFG_UART0_BASE 0x80120000
+#define CFG_UART1_BASE 0x80121000
+#define CFG_UART2_BASE 0x80007000
+#define CFG_SERIAL0 CFG_UART0_BASE
+#define CFG_SERIAL1 CFG_UART1_BASE
+#define CFG_SERIAL2 CFG_UART2_BASE
+#define CONFIG_PL011_CLOCK 38400000
+#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \
+ (void *)CFG_SERIAL2 }
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Devices and file systems
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Commands
+ */
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_SOURCE
+
+#ifndef CONFIG_BOOTDELAY
+#define CONFIG_BOOTDELAY 1
+#endif
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+"mmc dev 1; " \
+ "if run loadbootscript; " \
+ "then run bootscript; " \
+ "else " \
+ "if run mmcload; " \
+ "then run mmcboot; " \
+ "else " \
+ "mmc dev 0; " \
+ "if run emmcloadbootscript; " \
+ "then run bootscript; " \
+ "else " \
+ "if run emmcload; " \
+ "then run emmcboot; " \
+ "else " \
+ "echo No media to boot from; " \
+ "fi; " \
+ "fi; " \
+ "fi; " \
+ "fi; "
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "loadaddr=0x00100000\0" \
+ "console=ttyAMA2,115200n8\0" \
+ "loadbootscript=fatload mmc 1:1 ${loadaddr} boot.scr\0" \
+ "emmcloadbootscript=fatload mmc 0:2 ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript " \
+ "from mmc ...; source ${loadaddr}\0" \
+ "memargs256=mem=96M@0 mem_modem=32M@96M mem=32M@128M " \
+ "hwmem=22M@160M pmem_hwb=42M@182M mem_mali=32@224M\0" \
+ "memargs512=mem=96M@0 mem_modem=32M@96M hwmem=32M@128M " \
+ "mem=64M@160M mem_mali=32M@224M " \
+ "pmem_hwb=128M@256M mem=128M@384M\0" \
+ "memargs1024=mem=128M@0 mali.mali_mem=32M@128M " \
+ "hwmem=168M@M160M mem=48M@328M " \
+ "mem_issw=1M@383M mem=640M@384M\0" \
+ "memargs=setenv bootargs ${bootargs} ${memargs1024}\0" \
+ "emmcload=fatload mmc 0:2 ${loadaddr} uImage\0" \
+ "mmcload=fatload mmc 1:1 ${loadaddr} uImage\0" \
+ "commonargs=setenv bootargs console=${console} " \
+ "vmalloc=300M\0" \
+ "emmcargs=setenv bootargs ${bootargs} " \
+ "root=/dev/mmcblk0p3 " \
+ "rootwait\0" \
+ "addcons=setenv bootargs ${bootargs} " \
+ "console=${console}\0" \
+ "emmcboot=echo Booting from eMMC ...; " \
+ "run commonargs emmcargs memargs; " \
+ "bootm ${loadaddr}\0" \
+ "mmcargs=setenv bootargs ${bootargs} " \
+ "root=/dev/mmcblk1p2 " \
+ "rootwait earlyprintk\0" \
+ "mmcboot=echo Booting from external MMC ...; " \
+ "run commonargs mmcargs memargs; " \
+ "bootm ${loadaddr}\0" \
+ "fdt_high=0x2BC00000\0" \
+ "stdout=serial,usbtty\0" \
+ "stdin=serial,usbtty\0" \
+ "stderr=serial,usbtty\0"
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "U8500 $ " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
+
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SETUP_MEMORY_TAGS 2
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */
+
+/*
+ * additions for new relocation code
+ */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_MAX_RAM_SIZE 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
+
+/* landing address before relocation */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0x0
+#endif
+
+/*
+ * MMC related configs
+ */
+#define CONFIG_ARM_PL180_MMCI
+#define MMC_BLOCK_SIZE 512
+#define CFG_EMMC_BASE 0x80114000
+#define CFG_MMC_BASE 0x80126000
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * base register values for U8500
+ */
+#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock */
+
+
+/*
+ * U8500 GPIO register base for 9 banks
+ */
+#define CONFIG_DB8500_GPIO
+#define CFG_GPIO_0_BASE 0x8012E000
+#define CFG_GPIO_1_BASE 0x8012E080
+#define CFG_GPIO_2_BASE 0x8000E000
+#define CFG_GPIO_3_BASE 0x8000E080
+#define CFG_GPIO_4_BASE 0x8000E100
+#define CFG_GPIO_5_BASE 0x8000E180
+#define CFG_GPIO_6_BASE 0x8011E000
+#define CFG_GPIO_7_BASE 0x8011E080
+#define CFG_GPIO_8_BASE 0xA03FE000
+
+#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */
+
+#endif /* __CONFIG_H */
#define CONFIG_SYS_FLASH_EMPTY_INFO
-/* Stack sizes */
-#define CONFIG_STACKSIZE (128*1024)
-
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024)
-#define CONFIG_STACKSIZE_FIQ (4*1024)
-#endif
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x00000000
--- /dev/null
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2010
+ * Achim Ehrlich <aehrlich@taskit.de>
+ * taskit GmbH <www.taskit.de>
+ *
+ * (C) Copyright 2012
+ * Markus Hubig <mhubig@imko.de>
+ * IMKO GmbH <www.imko.de>
+ *
+ * Configuation settings for the stamp9g20 CPU module.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
+ * program. Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+#define CONFIG_SYS_TEXT_BASE 0x23f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
+#define CONFIG_SYS_HZ 1000 /* 1ms resolution */
+
+/* misc settings */
+#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */
+#define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */
+#define CONFIG_INITRD_TAG /* pass initrd param to kernel */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
+#define CONFIG_BOARD_EARLY_INIT_f /* call board_early_init_f() */
+#define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */
+
+/* setting board specific options */
+#ifdef CONFIG_PORTUXG20
+# define CONFIG_MACH_TYPE MACH_TYPE_PORTUXG20
+# define CONFIG_MACB
+#else
+# define CONFIG_MACH_TYPE MACH_TYPE_STAMP9G20
+#endif
+
+/*
+ * SDRAM: 1 bank, 64 MB, base address 0x20000000
+ * Already initialized before u-boot gets started.
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE (64 << 20)
+
+/*
+ * Perform a SDRAM Memtest from the start of SDRAM
+ * till the beginning of the U-Boot position in RAM.
+ */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN \
+ ROUND(3 * CONFIG_ENV_SIZE + (128 << 10), 0x1000)
+
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above that
+ * address while providing maximum stack area below.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash settings */
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO /* enable the GPIO features */
+#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE ATMEL_BASE_DBGU
+#define CONFIG_USART_ID ATMEL_ID_SYS
+#define CONFIG_BAUDRATE 115200
+
+/* LED configuration */
+#define CONFIG_STATUS_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+
+/* The LED PINs */
+#define CONFIG_RED_LED AT91_PIN_PC5
+#define CONFIG_GREEN_LED AT91_PIN_PC4
+#define CONFIG_YELLOW_LED AT91_PIN_PC10
+
+#define STATUS_LED_RED 0
+#define STATUS_LED_GREEN 1
+#define STATUS_LED_YELLOW 2
+
+/* Red LED */
+#define STATUS_LED_BIT STATUS_LED_RED
+#define STATUS_LED_STATE STATUS_LED_OFF
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+
+/* Green LED */
+#define STATUS_LED_BIT1 STATUS_LED_GREEN
+#define STATUS_LED_STATE1 STATUS_LED_ON
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+
+/* Yellow LED */
+#define STATUS_LED_BIT2 STATUS_LED_YELLOW
+#define STATUS_LED_STATE2 STATUS_LED_OFF
+#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
+
+/* Boot status LED */
+#define STATUS_LED_BOOT STATUS_LED_GREEN
+
+/*
+ * Ethernet configuration
+ *
+ * PortuxG20 has always ethernet but for Stamp9G20 you
+ * can enable it here if your baseboard features ethernet.
+ */
+
+/* #define CONFIG_MACB */
+
+#ifdef CONFIG_MACB
+# define CONFIG_RMII /* use reduced MII inteface */
+# define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */
+
+/* BOOTP and DHCP options */
+# define CONFIG_BOOTP_BOOTFILESIZE
+# define CONFIG_BOOTP_BOOTPATH
+# define CONFIG_BOOTP_GATEWAY
+# define CONFIG_BOOTP_HOSTNAME
+# define CONFIG_NFSBOOTCOMMAND \
+ "setenv autoload yes; setenv autoboot yes; " \
+ "setenv bootargs ${basicargs} ${mtdparts} " \
+ "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \
+ "dhcp"
+#endif /* CONFIG_MACB */
+
+/* Enable the watchdog */
+#define CONFIG_AT91SAM9_WATCHDOG
+#define CONFIG_HW_WATCHDOG
+
+/* USB configuration */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+
+/* General Boot Parameter */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTCOMMAND "run flashboot"
+#define CONFIG_SYS_PROMPT "U-Boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * RAM Memory address where to put the
+ * Linux Kernel befor starting.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x22000000
+
+/*
+ * The NAND Flash partitions:
+ * ==========================================
+ * 0x0000000-0x001ffff -> 128k, bootstrap
+ * 0x0020000-0x005ffff -> 256k, u-boot
+ * 0x0060000-0x007ffff -> 128k, env1
+ * 0x0080000-0x009ffff -> 128k, env2 (backup)
+ * 0x0100000-0x06fffff -> 6M, kernel
+ * 0x0700000-0x8000000 -> 121M, RootFS
+ */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET ((128 + 256) << 10)
+#define CONFIG_ENV_OFFSET_REDUND ((128 + 256 + 128) << 10)
+#define CONFIG_ENV_SIZE (128 << 10)
+
+/*
+ * Predefined environment variables.
+ * Usefull to define some easy to use boot commands.
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ \
+ "basicargs=console=ttyS0,115200\0" \
+ \
+ "mtdparts=mtdparts=atmel_nand:128k(bootstrap)ro," \
+ "256k(uboot)ro,128k(env1)ro," \
+ "128k(env2)ro,6M(linux),-(root)rw\0" \
+ \
+ "flashboot=setenv bootargs ${basicargs} ${mtdparts} " \
+ "root=/dev/mtdblock5 rootfstype=jffs2; " \
+ "nand read 0x22000000 0x100000 0x600000; " \
+ "bootm 22000000\0" \
+ \
+ "sdboot=setenv bootargs ${basicargs} ${mtdparts} " \
+ "root=/dev/mmcblk0p1 rootwait; " \
+ "nand read 0x22000000 0x100000 0x600000; " \
+ "bootm 22000000"
+
+/* Command line & features configuration */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_LED
+
+#ifdef CONFIG_MACB
+# define CONFIG_CMD_PING
+# define CONFIG_CMD_DHCP
+#else
+# undef CONFIG_CMD_BOOTD
+# undef CONFIG_CMD_NET
+# undef CONFIG_CMD_NFS
+#endif /* CONFIG_MACB */
+
+#endif /* __CONFIG_H */
*/
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP34XX /* which is a 34XX */
+#define CONFIG_OMAP_GPIO
#define CONFIG_SYS_TEXT_BASE 0x80008000
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/*
* Physical Memory Map
*/
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#ifndef __CONFIG_H
#define __CONFIG_H
-#include "tegra2-common.h"
+#include "tegra20-common.h"
/* Enable fdt support for TEC. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra2-tec
+#define CONFIG_DEFAULT_DEVICE_TREE tegra20-tec
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
-#define V_PROMPT "Tegra2 (TEC) # "
-#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier"
+#define V_PROMPT "Tegra20 (TEC) # "
+#define CONFIG_TEGRA20_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier"
#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA2_ENABLE_UARTD /* UARTD: debug UART */
+#define CONFIG_TEGRA20_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
+#include "tegra20-common-post.h"
+
#endif /* __CONFIG_H */
* MA 02111-1307 USA
*/
-#ifndef __TEGRA2_COMMON_POST_H
-#define __TEGRA2_COMMON_POST_H
+#ifndef __TEGRA20_COMMON_POST_H
+#define __TEGRA20_COMMON_POST_H
#ifdef CONFIG_BOOTCOMMAND
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
- TEGRA2_DEVICE_SETTINGS \
+ TEGRA20_DEVICE_SETTINGS \
"fdt_load=0x01000000\0" \
"fdt_high=01100000\0" \
BOOTCMDS_COMMON
-#endif /* __TEGRA2_COMMON_POST_H */
+/* overrides for SPL build here */
+#ifdef CONFIG_SPL_BUILD
+
+/* remove devicetree support */
+#ifdef CONFIG_OF_CONTROL
+#undef CONFIG_OF_CONTROL
+#endif
+
+/* remove SERIAL_MULTI */
+#ifdef CONFIG_SERIAL_MULTI
+#undef CONFIG_SERIAL_MULTI
+#endif
+
+/* remove I2C support */
+#ifdef CONFIG_TEGRA_I2C
+#undef CONFIG_TEGRA_I2C
+#endif
+#ifdef CONFIG_CMD_I2C
+#undef CONFIG_CMD_I2C
+#endif
+
+/* remove MMC support */
+#ifdef CONFIG_MMC
+#undef CONFIG_MMC
+#endif
+#ifdef CONFIG_GENERIC_MMC
+#undef CONFIG_GENERIC_MMC
+#endif
+#ifdef CONFIG_TEGRA20_MMC
+#undef CONFIG_TEGRA20_MMC
+#endif
+#ifdef CONFIG_CMD_MMC
+#undef CONFIG_CMD_MMC
+#endif
+
+/* remove partitions/filesystems */
+#ifdef CONFIG_DOS_PARTITION
+#undef CONFIG_DOS_PARTITION
+#endif
+#ifdef CONFIG_EFI_PARTITION
+#undef CONFIG_EFI_PARTITION
+#endif
+#ifdef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_EXT2
+#endif
+#ifdef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FAT
+#endif
+
+/* remove USB */
+#ifdef CONFIG_USB_EHCI
+#undef CONFIG_USB_EHCI
+#endif
+#ifdef CONFIG_USB_EHCI_TEGRA
+#undef CONFIG_USB_EHCI_TEGRA
+#endif
+#ifdef CONFIG_USB_STORAGE
+#undef CONFIG_USB_STORAGE
+#endif
+#ifdef CONFIG_CMD_USB
+#undef CONFIG_CMD_USB
+#endif
+
+#endif /* CONFIG_SPL_BUILD */
+
+#endif /* __TEGRA20_COMMON_POST_H */
* MA 02111-1307 USA
*/
-#ifndef __TEGRA2_COMMON_H
-#define __TEGRA2_COMMON_H
+#ifndef __TEGRA20_COMMON_H
+#define __TEGRA20_COMMON_H
#include <asm/sizes.h>
/*
* High Level Configuration Options
*/
#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
-#define CONFIG_TEGRA2 /* in a NVidia Tegra2 core */
-#define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */
+#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
+#define CONFIG_TEGRA /* which is a Tegra generic machine */
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
#define CONFIG_SYS_CACHELINE_SIZE 32
-#define CONFIG_ARCH_CPU_INIT /* Fire up the A9 core */
-
-#include <asm/arch/tegra2.h> /* get chip and board defs */
+#include <asm/arch/tegra20.h> /* get chip and board defs */
/*
* Display CPU and Board information
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
-#ifdef CONFIG_TEGRA2_LP0
+#ifdef CONFIG_TEGRA20_LP0
#define TEGRA_LP0_ADDR 0x1C406000
#define TEGRA_LP0_SIZE 0x2000
#define TEGRA_LP0_VEC \
#define CONFIG_EHCI_IS_TDI
#define CONFIG_EHCI_DCACHE
-/* Total I2C ports on Tegra2 */
+/* Total I2C ports on Tegra20 */
#define TEGRA_I2C_NUM_CONTROLLERS 4
/* include default commands */
/* Environment information, boards can override if required */
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define TEGRA2_DEVICE_SETTINGS "stdin=serial\0" \
+#define TEGRA20_DEVICE_SETTINGS "stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0"
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-#define CONFIG_SYS_MEMTEST_START (TEGRA2_SDRC_CS0 + 0x600000)
+#define CONFIG_SYS_MEMTEST_START (TEGRA20_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
#define CONFIG_SYS_HZ 1000
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
#define CONFIG_STACKBASE 0x2800000 /* 40MB */
-#define CONFIG_STACKSIZE 0x20000 /* 128K regular stack*/
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 TEGRA2_SDRC_CS0
+#define PHYS_SDRAM_1 TEGRA20_SDRC_CS0
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_TEXT_BASE 0x00108000
+#define CONFIG_SYS_TEXT_BASE 0x0010c000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_ENTERRCM
#define CONFIG_CMD_BOOTZ
-#endif /* __TEGRA2_COMMON_H */
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_TEXT_BASE 0x00108000
+#define CONFIG_SPL_MAX_SIZE 0x00004000
+#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
+#define CONFIG_SPL_STACK 0x000ffffc
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
+
+#endif /* __TEGRA20_COMMON_H */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024)
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_STACKSIZE (256*1024)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_HZ 1000
#define CONFIG_ARCH_CPU_INIT
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
-#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
-
#endif
/* Misc CPU related */
#define CONFIG_ARCH_CPU_INIT
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN \
ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-#define CONFIG_STACKSIZE (32*1024)
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
#endif
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-/* Keep L2 Cache Disabled */
-#define CONFIG_SYS_L2CACHE_OFF
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE 0x10502000
+#endif
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_TEXT_BASE 0x63300000
"meminfo=crashkernel=32M@0x50000000\0" \
"nfsroot=/nfsroot/arm\0" \
"bootblock=" CONFIG_BOOTBLOCK "\0" \
+ "loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
"mmcdev=0\0" \
"mmcbootpart=2\0" \
"mmcrootpart=3\0" \
#define CONFIG_SYS_HZ 1000
-/* Stack sizes */
-#define CONFIG_STACKSIZE (256 << 10) /* regular stack 256KB */
-
/* TRATS has 2 banks of DRAM */
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/* The stack sizes are set up in start.S using the settings below */
-#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define __CONFIG_H
#include <asm/sizes.h>
-#include "tegra2-common.h"
+#include "tegra20-common.h"
/* Enable fdt support for TrimSlice. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra2-trimslice
+#define CONFIG_DEFAULT_DEVICE_TREE tegra20-trimslice
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
-#define V_PROMPT "Tegra2 (TrimSlice) # "
-#define CONFIG_TEGRA2_BOARD_STRING "Compulab Trimslice"
+#define V_PROMPT "Tegra20 (TrimSlice) # "
+#define CONFIG_TEGRA20_BOARD_STRING "Compulab Trimslice"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA2_ENABLE_UARTA
-#define CONFIG_TEGRA2_UARTA_GPU
+#define CONFIG_TEGRA20_ENABLE_UARTA
+#define CONFIG_TEGRA20_UARTA_GPU
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
-#include "tegra2-common-post.h"
+#include "tegra20-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_TEXT_BASE 0x0
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_MMC_BASE 0xF0000000
#endif
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*
* Physical Memory Map
*/
/* default load address, 1MB up the road */
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000)
-/* The stack sizes are set up in start.S using the settings below */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/* Size of malloc() pool, make sure possible frame buffer fits */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024)
/* 8MB DRAM test */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
-#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
/*
* Serial Info
#define CONFIG_SYS_I2C_GPIOE_ADDR 0x42 /* GPIO expander chip addr */
#define CONFIG_TC35892_GPIO
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
/*
* Physical Memory Map
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-#define CONFIG_STACKSIZE (256 << 10)
#define CONFIG_SYS_MALLOC_LEN (1 << 20)
#define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10)
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
#define __CONFIG_H
#include <asm/sizes.h>
-#include "tegra2-common.h"
+#include "tegra20-common.h"
/* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra2-ventana
+#define CONFIG_DEFAULT_DEVICE_TREE tegra20-ventana
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
-#define V_PROMPT "Tegra2 (Ventana) # "
-#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Ventana"
+#define V_PROMPT "Tegra20 (Ventana) # "
+#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Ventana"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA2_ENABLE_UARTD
+#define CONFIG_TEGRA20_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
-#include "tegra2-common-post.h"
+#include "tegra20-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
-#endif
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
-
/*
* Physical Memory Map
*/
#define CONFIG_VIDEO_IPUV3
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
/*--------------------------------------------------------------------------*/
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_ARM926EJS /* This is an ARM926EJS Core */
#define CONFIG_AT91FAMILY
#define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/
ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
-#define CONFIG_STACKSIZE (32*1024) /* regular stack */
-
#ifndef CONFIG_RAMLOAD
#define CONFIG_BOOTCOMMAND "run nfsboot"
#endif
"erase 10060000 1007FFFF;reset\0" \
" "
-/*--------------------------------------------------------------------------*/
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
-
#endif
#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */
#define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
/*
* DRAM Map
#define __CONFIG_H
#include <asm/sizes.h>
-#include "tegra2-common.h"
+#include "tegra20-common.h"
/* Enable fdt support for Whistler. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra2-whistler
+#define CONFIG_DEFAULT_DEVICE_TREE tegra20-whistler
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
-#define V_PROMPT "Tegra2 (Whistler) # "
-#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Whistler"
+#define V_PROMPT "Tegra20 (Whistler) # "
+#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Whistler"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA2_ENABLE_UARTA
-#define CONFIG_TEGRA2_UARTA_UAA_UAB
+#define CONFIG_TEGRA20_ENABLE_UARTA
+#define CONFIG_TEGRA20_UARTA_UAA_UAB
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
-#include "tegra2-common-post.h"
+#include "tegra20-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_XAENIAX 1 /* on a xaeniax board */
#define CONFIG_SYS_TEXT_BASE 0x0
-
#define CONFIG_BOARD_LATE_INIT
-
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector */
#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*
* SMSC91C111 Network Card
*/
#define CONFIG_SYS_TEXT_BASE 0x0
#undef CONFIG_BOARD_LATE_INIT
-#undef CONFIG_USE_IRQ
#undef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_PREBOOT
#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
/*
* SRAM Map
*/
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000)
-#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * CPSW Ethernet Switch Driver
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPSW_H_
+#define _CPSW_H_
+
+struct cpsw_slave_data {
+ u32 slave_reg_ofs;
+ u32 sliver_reg_ofs;
+ int phy_id;
+ int phy_if;
+};
+
+enum {
+ CPSW_CTRL_VERSION_1 = 0,
+ CPSW_CTRL_VERSION_2 /* am33xx like devices */
+};
+
+struct cpsw_platform_data {
+ u32 mdio_base;
+ u32 cpsw_base;
+ int mdio_div;
+ int channels; /* number of cpdma channels (symmetric) */
+ u32 cpdma_reg_ofs; /* cpdma register offset */
+ int slaves; /* number of slave cpgmac ports */
+ u32 ale_reg_ofs; /* address lookup engine reg offset */
+ int ale_entries; /* ale table size */
+ u32 host_port_reg_ofs; /* cpdma host port registers */
+ u32 hw_stats_reg_ofs; /* cpsw hw stats counters */
+ u32 mac_control;
+ struct cpsw_slave_data *slave_data;
+ void (*control)(int enabled);
+ u32 host_port_num;
+ u8 version;
+};
+
+int cpsw_register(struct cpsw_platform_data *data);
+
+#endif /* _CPSW_H_ */
*/
enum fdt_compat_id {
COMPAT_UNKNOWN,
- COMPAT_NVIDIA_TEGRA20_USB, /* Tegra2 USB port */
- COMPAT_NVIDIA_TEGRA20_I2C, /* Tegra2 i2c */
- COMPAT_NVIDIA_TEGRA20_DVC, /* Tegra2 dvc (really just i2c) */
- COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra2 memory controller */
- COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra2 memory timing table */
- COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra2 Keyboard */
+ COMPAT_NVIDIA_TEGRA20_USB, /* Tegra20 USB port */
+ COMPAT_NVIDIA_TEGRA20_I2C, /* Tegra20 i2c */
+ COMPAT_NVIDIA_TEGRA20_DVC, /* Tegra20 dvc (really just i2c) */
+ COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */
+ COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
+ COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra20 Keyboard */
COMPAT_COUNT,
};
struct fsl_esdhc_cfg {
u32 esdhc_base;
- u32 no_snoop;
};
/* Select the correct accessors depending on endianess */
unsigned int reset_delay;
unsigned int interface_mode;
unsigned int mipi_enabled;
+ unsigned int dp_enabled;
unsigned int cs_setup;
unsigned int wr_setup;
unsigned int wr_act;
#define _MMC_H_
#include <linux/list.h>
+#include <linux/compiler.h>
#define SD_VERSION_SD 0x20000
#define SD_VERSION_2 (SD_VERSION_SD | 0x20)
int board_mmc_getcd(struct mmc *mmc);
int mmc_switch_part(int dev_num, unsigned int part_num);
int mmc_getcd(struct mmc *mmc);
+void spl_mmc_load(void) __noreturn;
#ifdef CONFIG_GENERIC_MMC
#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI)
* at the same time, so do it here. When all drivers are
* converted, this will go away.
*/
-#if defined(CONFIG_NAND_FSL_ELBC)
+#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)
#define CONFIG_SYS_NAND_SELF_INIT
#endif
UART_REG(lsr); /* 5 */
UART_REG(msr); /* 6 */
UART_REG(spr); /* 7 */
+#ifdef CONFIG_SOC_DA8XX
+ UART_REG(reg8); /* 8 */
+ UART_REG(reg9); /* 9 */
+ UART_REG(revid1); /* A */
+ UART_REG(revid2); /* B */
+ UART_REG(pwr_mgmt); /* C */
+ UART_REG(mdr1); /* D */
+#else
UART_REG(mdr1); /* 8 */
UART_REG(reg9); /* 9 */
UART_REG(regA); /* A */
UART_REG(ssr); /* 11*/
UART_REG(reg12); /* 12*/
UART_REG(osc_12m_sel); /* 13*/
+#endif
};
#define thr rbr
#define PCI_DEVICE_ID_ATI_RS400_166 0x5a32
#define PCI_DEVICE_ID_ATI_RS400_200 0x5a33
#define PCI_DEVICE_ID_ATI_RS480 0x5950
+/* additional Radeon families */
+#define PCI_DEVICE_ID_ATI_EVERGREEN 0x9802
+#define PCI_DEVICE_ID_ATI_EVERGREEN2 0x9804
+#define PCI_DEVICE_ID_ATI_WRESTLER 0x9806
/* ATI IXP Chipset */
#define PCI_DEVICE_ID_ATI_IXP200_IDE 0x4349
#define PCI_DEVICE_ID_ATI_IXP200_SMBUS 0x4353
#define PCI_DEVICE_ID_ATI_IXP400_SATA 0x4379
#define PCI_DEVICE_ID_ATI_IXP400_SATA2 0x437a
#define PCI_DEVICE_ID_ATI_IXP600_SATA 0x4380
+#define PCI_DEVICE_ID_ATI_SBX00_PCI_BRIDGE 0x4384
#define PCI_DEVICE_ID_ATI_SBX00_SMBUS 0x4385
#define PCI_DEVICE_ID_ATI_IXP600_IDE 0x438c
#define PCI_DEVICE_ID_ATI_IXP700_SATA 0x4390
+#define PCI_DEVICE_ID_ATI_SBX00_SATA_AHCI 0x4391
+#define PCI_DEVICE_ID_ATI_SBX00_EHCI 0x4396
+#define PCI_DEVICE_ID_ATI_SBX00_OHCI 0x4397
#define PCI_DEVICE_ID_ATI_IXP700_IDE 0x439c
#define PCI_VENDOR_ID_VLSI 0x1004
#define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21
#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30
#define PCI_DEVICE_ID_INTEL_IOAT 0x1a38
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE 0x1c03
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6 0x1c02
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_HDA 0x1c20
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE 0x1e03
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA 0x1e20
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f
#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC 0x1d40
#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410
#define PCI_DEVICE_ID_INTEL_ICH7_30 0x27b0
#define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc
#define PCI_DEVICE_ID_INTEL_ICH7_31 0x27bd
+#define PCI_DEVICE_ID_INTEL_NM10_AHCI 0x27c1
#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da
#define PCI_DEVICE_ID_INTEL_ICH7_19 0x27dd
#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de
defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
- defined(CONFIG_TEGRA2) || defined(CONFIG_SYS_COREBOOT)
+ defined(CONFIG_TEGRA20) || defined(CONFIG_SYS_COREBOOT)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#if defined(CONFIG_SYS_NS16550_SERIAL)
#include <libfdt.h>
#include <fdtdec.h>
-/* we need the generic GPIO interface here */
-#include <asm-generic/gpio.h>
+#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
[ "${BOARD_NAME}" ] || BOARD_NAME="${1%_config}"
arch="$2"
-cpu="$3"
-tmp="${cpu#*:}"
-if [ "$tmp" != "$cpu" ] ; then
- spl_cpu=$tmp
- cpu="${cpu%:*}"
-fi
+cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $1}'`
+spl_cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $2}'`
if [ "$4" = "-" ] ; then
board=${BOARD_NAME}
else
#
# Create include file for Make
#
-echo "ARCH = ${arch}" > config.mk
-if [ ! -z "$spl_cpu" ] ; then
- echo 'ifeq ($(CONFIG_SPL_BUILD),y)' >> config.mk
- echo "CPU = ${spl_cpu}" >> config.mk
- echo "else" >> config.mk
- echo "CPU = ${cpu}" >> config.mk
- echo "endif" >> config.mk
-else
- echo "CPU = ${cpu}" >> config.mk
-fi
-echo "BOARD = ${board}" >> config.mk
-
-[ "${vendor}" ] && echo "VENDOR = ${vendor}" >> config.mk
-
-[ "${soc}" ] && echo "SOC = ${soc}" >> config.mk
+( echo "ARCH = ${arch}"
+ if [ ! -z "$spl_cpu" ] ; then
+ echo 'ifeq ($(CONFIG_SPL_BUILD),y)'
+ echo "CPU = ${spl_cpu}"
+ echo "else"
+ echo "CPU = ${cpu}"
+ echo "endif"
+ else
+ echo "CPU = ${cpu}"
+ fi
+ echo "BOARD = ${board}"
+
+ [ "${vendor}" ] && echo "VENDOR = ${vendor}"
+ [ "${soc}" ] && echo "SOC = ${soc}"
+ exit 0 ) > config.mk
# Assign board directory to BOARDIR variable
if [ -z "${vendor}" ] ; then
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
+ifeq ($(SOC),tegra20)
+LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
+endif
+
+# Add GCC lib
+ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
+PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o
+PLATFORM_LIBS := $(filter-out %/libgcc.o, $(filter-out -lgcc, $(PLATFORM_LIBS))) $(PLATFORM_LIBGCC)
+endif
+
START := $(addprefix $(SPLTREE)/,$(START))
LIBS := $(addprefix $(SPLTREE)/,$(sort $(LIBS-y)))
/envcrc
/gen_eth_addr
/img2srec
+/kwboot
/mkenvimage
/mkimage
/mpc86x_clk
# Lines which are allowed after a TEST= line
re_allowed_after_test = re.compile('^Signed-off-by:')
+# Signoffs
+re_signoff = re.compile('^Signed-off-by:')
+
# The start of the cover letter
re_cover = re.compile('^Cover-letter:')
re_series = re.compile('^Series-(\w*): *(.*)')
# Commit tags that we want to collect and keep
-re_tag = re.compile('^(Tested-by|Acked-by|Signed-off-by|Cc): (.*)')
+re_tag = re.compile('^(Tested-by|Acked-by|Cc): (.*)')
# The start of a new commit in the git log
re_commit = re.compile('^commit (.*)')
if is_blank:
# Blank line ends this change list
self.in_change = 0
+ elif line == '---' or re_signoff.match(line):
+ self.in_change = 0
+ out = self.ProcessLine(line)
else:
- self.series.AddChange(self.in_change, self.commit, line)
+ if self.is_log:
+ self.series.AddChange(self.in_change, self.commit, line)
self.skip_blank = False
# Detect Series-xxx tags
# Detect tags in the commit message
elif tag_match:
- # Onlly allow a single signoff tag
- if tag_match.group(1) == 'Signed-off-by':
- if self.signoff:
- self.warn.append('Patch has more than one Signed-off-by '
- 'tag')
- self.signoff += [line]
-
# Remove Tested-by self, since few will take much notice
- elif (tag_match.group(1) == 'Tested-by' and
+ if (tag_match.group(1) == 'Tested-by' and
tag_match.group(2).find(os.getenv('USER') + '@') != -1):
self.warn.append("Ignoring %s" % line)
elif tag_match.group(1) == 'Cc':
# Output the tags (signeoff first), then change list
out = []
- if self.signoff:
- out += self.signoff
log = self.series.MakeChangeLog(self.commit)
out += self.FormatTags(self.tags)
out += [line] + log
cc_list += gitutil.BuildEmailList(commit.tags)
cc_list += gitutil.BuildEmailList(commit.cc_list)
+ # Skip items in To list
+ if 'to' in self:
+ try:
+ map(cc_list.remove, gitutil.BuildEmailList(self.to))
+ except ValueError:
+ pass
+
for email in cc_list:
if email == None:
email = col.Color(col.YELLOW, "<alias '%s' not found>"
for this_commit, text in self.changes[change]:
if commit and this_commit != commit:
continue
- if text not in out:
- out.append(text)
+ out.append(text)
if out:
- out = ['Changes in v%d:' % change] + sorted(out)
+ out = ['Changes in v%d:' % change] + out
if need_blank:
out = [''] + out
final += out
col = terminal.Color()
if self.get('version'):
changes_copy = dict(self.changes)
- for version in range(2, int(self.version) + 1):
+ for version in range(1, int(self.version) + 1):
if self.changes.get(version):
del changes_copy[version]
else:
- str = 'Change log missing for v%d' % version
- print col.Color(col.RED, str)
+ if version > 1:
+ str = 'Change log missing for v%d' % version
+ print col.Color(col.RED, str)
for version in changes_copy:
str = 'Change log for unknown version v%d' % version
print col.Color(col.RED, str)
projects / karo-tx-uboot.git / commitdiff