Pass sdrc timing values through board_sdrc_timings structure

Instead of passing individual registers by value to board_get_mem_timings,
pass a board_mem_timings structure pointer for the board files to fill in.
Pass same structure pointer to write_sdrc_timings.  This saves about
90 bytes of space in SPL.

Signed-off-by: Peter Barada <peter.barada@logicpd.com>

diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index f6d9b97bb4dcb6df17380c675ecaf96d3afe08ae..e32bf118b182ca9b893dce64597c9d54d70b06ea 100644 (file)
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -113,18 +113,18 @@ u32 get_sdr_cs_offset(u32 cs)
  *  - Test CS to make sure it's OK for use
  */
 static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
-               u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr)
+                       struct board_sdrc_timings *timings)
 {
        /* Setup timings we got from the board. */
-       writel(mcfg, &sdrc_base->cs[cs].mcfg);
-       writel(ctrla, &sdrc_actim_base->ctrla);
-       writel(ctrlb, &sdrc_actim_base->ctrlb);
-       writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
+       writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);
+       writel(timings->ctrla, &sdrc_actim_base->ctrla);
+       writel(timings->ctrlb, &sdrc_actim_base->ctrlb);
+       writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
        writel(CMD_NOP, &sdrc_base->cs[cs].manual);
        writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
        writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
        writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-       writel(mr, &sdrc_base->cs[cs].mr);
+       writel(timings->mr, &sdrc_base->cs[cs].mr);
 
        /*
         * Test ram in this bank
@@ -143,7 +143,7 @@ static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
 void do_sdrc_init(u32 cs, u32 early)
 {
        struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
-       u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr;
+       struct board_sdrc_timings timings;
 
        sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
        sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
@@ -158,7 +158,7 @@ void do_sdrc_init(u32 cs, u32 early)
         * setup CS1.
         */
 #ifdef CONFIG_SPL_BUILD
-       get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr);
+       get_board_mem_timings(&timings);
 #endif
        if (early) {
                /* reset sdrc controller */
@@ -177,11 +177,9 @@ void do_sdrc_init(u32 cs, u32 early)
                writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
                sdelay(0x20000);
 #ifdef CONFIG_SPL_BUILD
-               write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb,
-                               rfr_ctrl, mr);
+               write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
                make_cs1_contiguous();
-               write_sdrc_timings(CS1, sdrc_actim_base1, mcfg, ctrla, ctrlb,
-                               rfr_ctrl, mr);
+               write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
 #endif
 
        }
@@ -193,14 +191,12 @@ void do_sdrc_init(u32 cs, u32 early)
         * so we may be asked now to setup CS1.
         */
        if (cs == CS1) {
-               mcfg = readl(&sdrc_base->cs[CS0].mcfg),
-               rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
-               ctrla = readl(&sdrc_actim_base0->ctrla),
-               ctrlb = readl(&sdrc_actim_base0->ctrlb);
-               mr = readl(&sdrc_base->cs[CS0].mr);
-               write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb,
-                               rfr_ctrl, mr);
-
+               timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),
+               timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
+               timings.ctrla = readl(&sdrc_actim_base0->ctrla);
+               timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);
+               timings.mr = readl(&sdrc_base->cs[CS0].mr);
+               write_sdrc_timings(cs, sdrc_actim_base1, &timings);
        }
 }
 

diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 9e52b12aa291ac3145a0a779909642919f553f82..d60f2addb2aa166c52301e24fc4f1e469d0d653b 100644 (file)
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -32,6 +32,15 @@ struct emu_hal_params {
        u32 param1;
 };
 
+/* Board SDRC timing values */
+struct board_sdrc_timings {
+       u32 mcfg;
+       u32 ctrla;
+       u32 ctrlb;
+       u32 rfr_ctrl;
+       u32 mr;
+};
+
 void prcm_init(void);
 void per_clocks_enable(void);
 void ehci_clocks_enable(void);
@@ -39,8 +48,8 @@ void ehci_clocks_enable(void);
 void memif_init(void);
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-               u32 *mr);
+
+void get_board_mem_timings(struct board_sdrc_timings *timings);
 void identify_nand_chip(int *mfr, int *id);
 void emif4_init(void);
 void gpmc_init(void);

diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c
index aaff2e868ba2e99e90e55afad877a9111838b058..56fe495277ee7d6ad84df39ab4494de81f2f6784 100644 (file)
--- a/board/corscience/tricorder/tricorder.c
+++ b/board/corscience/tricorder/tricorder.c
@@ -91,15 +91,14 @@ int board_mmc_init(bd_t *bis)
  * provides the timing values back to the function that configures
  * the memory.  We have either one or two banks of 128MB DDR.
  */
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-                               u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
        /* General SDRC config */
-       *mcfg = MICRON_V_MCFG_165(128 << 20);
-       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+       timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 
        /* AC timings */
-       *ctrla = MICRON_V_ACTIMA_165;
-       *ctrlb = MICRON_V_ACTIMB_165;
-       *mr = MICRON_V_MR_165;
+       timings->ctrla = MICRON_V_ACTIMA_165;
+       timings->ctrlb = MICRON_V_ACTIMB_165;
+       timings->mr = MICRON_V_MR_165;
 }

diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
index a8257a3005fab8d93d0b373afd15e64954d23ccb..a0f2aa3e4e2ad89e41de4cf52a0dca325662a708 100644 (file)
--- a/board/isee/igep0020/igep0020.c
+++ b/board/isee/igep0020/igep0020.c
@@ -72,27 +72,26 @@ void omap_rev_string(void)
  * Description: If we use SPL then there is no x-loader nor config header
  * so we have to setup the DDR timings ourself on both banks.
  */
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-               u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
-       *mr = MICRON_V_MR_165;
+       timings->mr = MICRON_V_MR_165;
 #ifdef CONFIG_BOOT_NAND
-       *mcfg = MICRON_V_MCFG_200(256 << 20);
-       *ctrla = MICRON_V_ACTIMA_200;
-       *ctrlb = MICRON_V_ACTIMB_200;
-       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+       timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+       timings->ctrla = MICRON_V_ACTIMA_200;
+       timings->ctrlb = MICRON_V_ACTIMB_200;
+       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 #else
        if (get_cpu_family() == CPU_OMAP34XX) {
-               *mcfg = NUMONYX_V_MCFG_165(256 << 20);
-               *ctrla = NUMONYX_V_ACTIMA_165;
-               *ctrlb = NUMONYX_V_ACTIMB_165;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
+               timings->ctrla = NUMONYX_V_ACTIMA_165;
+               timings->ctrlb = NUMONYX_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 
        } else {
-               *mcfg = NUMONYX_V_MCFG_200(256 << 20);
-               *ctrla = NUMONYX_V_ACTIMA_200;
-               *ctrlb = NUMONYX_V_ACTIMB_200;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+               timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
+               timings->ctrla = NUMONYX_V_ACTIMA_200;
+               timings->ctrlb = NUMONYX_V_ACTIMB_200;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
        }
 #endif
 }

diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c
index 107cb7f8e0581d0f8c7c5487773e6873eec70cfe..a41e752b8206da9c38b1c3e879ca3d08d597bd3d 100644 (file)
--- a/board/isee/igep0030/igep0030.c
+++ b/board/isee/igep0030/igep0030.c
@@ -59,27 +59,26 @@ void omap_rev_string(void)
  * Description: If we use SPL then there is no x-loader nor config header
  * so we have to setup the DDR timings ourself on both banks.
  */
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-                          u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
-       *mr = MICRON_V_MR_165;
+       timings->mr = MICRON_V_MR_165;
 #ifdef CONFIG_BOOT_NAND
-       *mcfg = MICRON_V_MCFG_200(256 << 20);
-       *ctrla = MICRON_V_ACTIMA_200;
-       *ctrlb = MICRON_V_ACTIMB_200;
-       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+       timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+       timings->ctrla = MICRON_V_ACTIMA_200;
+       timings->ctrlb = MICRON_V_ACTIMB_200;
+       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 #else
        if (get_cpu_family() == CPU_OMAP34XX) {
-               *mcfg = NUMONYX_V_MCFG_165(256 << 20);
-               *ctrla = NUMONYX_V_ACTIMA_165;
-               *ctrlb = NUMONYX_V_ACTIMB_165;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
+               timings->ctrla = NUMONYX_V_ACTIMA_165;
+               timings->ctrlb = NUMONYX_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 
        } else {
-               *mcfg = NUMONYX_V_MCFG_200(256 << 20);
-               *ctrla = NUMONYX_V_ACTIMA_200;
-               *ctrlb = NUMONYX_V_ACTIMB_200;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+               timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
+               timings->ctrla = NUMONYX_V_ACTIMA_200;
+               timings->ctrlb = NUMONYX_V_ACTIMB_200;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
        }
 #endif
 }

diff --git a/board/overo/overo.c b/board/overo/overo.c
index c6d50a07acabc18296474b5581c5c41026a86c99..fdf46a2aae92101bc2957eab45144f3a6c6571eb 100644 (file)
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -147,34 +147,33 @@ int get_board_revision(void)
  * Description: If we use SPL then there is no x-loader nor config header
  * so we have to setup the DDR timings ourself on both banks.
  */
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-               u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
-       *mr = MICRON_V_MR_165;
+       timings->mr = MICRON_V_MR_165;
        switch (get_board_revision()) {
        case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
-               *mcfg = MICRON_V_MCFG_165(128 << 20);
-               *ctrla = MICRON_V_ACTIMA_165;
-               *ctrlb = MICRON_V_ACTIMB_165;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+               timings->ctrla = MICRON_V_ACTIMA_165;
+               timings->ctrlb = MICRON_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                break;
        case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
-               *mcfg = MICRON_V_MCFG_165(256 << 20);
-               *ctrla = MICRON_V_ACTIMA_165;
-               *ctrlb = MICRON_V_ACTIMB_165;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = MICRON_V_MCFG_165(256 << 20);
+               timings->ctrla = MICRON_V_ACTIMA_165;
+               timings->ctrlb = MICRON_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                break;
        case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
-               *mcfg = HYNIX_V_MCFG_165(256 << 20);
-               *ctrla = HYNIX_V_ACTIMA_165;
-               *ctrlb = HYNIX_V_ACTIMB_165;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = HYNIX_V_MCFG_165(256 << 20);
+               timings->ctrla = HYNIX_V_ACTIMA_165;
+               timings->ctrlb = HYNIX_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                break;
        default:
-               *mcfg = MICRON_V_MCFG_165(128 << 20);
-               *ctrla = MICRON_V_ACTIMA_165;
-               *ctrlb = MICRON_V_ACTIMB_165;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+               timings->ctrla = MICRON_V_ACTIMA_165;
+               timings->ctrlb = MICRON_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
        }
 }
 #endif

diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 6175e1d1ac031ed1d5a41c3ff407d5027a00fc9e..4adf9827c5f26a6ef769e30290f1af3f9d616847 100644 (file)
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -139,8 +139,7 @@ static int get_board_revision(void)
  * Description: If we use SPL then there is no x-loader nor config header
  * so we have to setup the DDR timings ourself on both banks.
  */
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-               u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
        int pop_mfr, pop_id;
 
@@ -151,29 +150,29 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
         */
        identify_nand_chip(&pop_mfr, &pop_id);
 
-       *mr = MICRON_V_MR_165;
+       timings->mr = MICRON_V_MR_165;
        switch (get_board_revision()) {
        case REVISION_C4:
                if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
                        /* 512MB DDR */
-                       *mcfg = NUMONYX_V_MCFG_165(512 << 20);
-                       *ctrla = NUMONYX_V_ACTIMA_165;
-                       *ctrlb = NUMONYX_V_ACTIMB_165;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+                       timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+                       timings->ctrla = NUMONYX_V_ACTIMA_165;
+                       timings->ctrlb = NUMONYX_V_ACTIMB_165;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                        break;
                } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
                        /* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
-                       *mcfg = MICRON_V_MCFG_165(128 << 20);
-                       *ctrla = MICRON_V_ACTIMA_165;
-                       *ctrlb = MICRON_V_ACTIMB_165;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+                       timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+                       timings->ctrla = MICRON_V_ACTIMA_165;
+                       timings->ctrlb = MICRON_V_ACTIMB_165;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                        break;
                } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
                        /* Beagleboard Rev C5, 256MB DDR */
-                       *mcfg = MICRON_V_MCFG_200(256 << 20);
-                       *ctrla = MICRON_V_ACTIMA_200;
-                       *ctrlb = MICRON_V_ACTIMB_200;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+                       timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+                       timings->ctrla = MICRON_V_ACTIMA_200;
+                       timings->ctrlb = MICRON_V_ACTIMB_200;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
                        break;
                }
        case REVISION_XM_A:
@@ -181,24 +180,24 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
        case REVISION_XM_C:
                if (pop_mfr == 0) {
                        /* 256MB DDR */
-                       *mcfg = MICRON_V_MCFG_200(256 << 20);
-                       *ctrla = MICRON_V_ACTIMA_200;
-                       *ctrlb = MICRON_V_ACTIMB_200;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+                       timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+                       timings->ctrla = MICRON_V_ACTIMA_200;
+                       timings->ctrlb = MICRON_V_ACTIMB_200;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
                } else {
                        /* 512MB DDR */
-                       *mcfg = NUMONYX_V_MCFG_165(512 << 20);
-                       *ctrla = NUMONYX_V_ACTIMA_165;
-                       *ctrlb = NUMONYX_V_ACTIMB_165;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+                       timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+                       timings->ctrla = NUMONYX_V_ACTIMA_165;
+                       timings->ctrlb = NUMONYX_V_ACTIMB_165;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                }
                break;
        default:
                /* Assume 128MB and Micron/165MHz timings to be safe */
-               *mcfg = MICRON_V_MCFG_165(128 << 20);
-               *ctrla = MICRON_V_ACTIMA_165;
-               *ctrlb = MICRON_V_ACTIMB_165;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+               timings->ctrla = MICRON_V_ACTIMA_165;
+               timings->ctrlb = MICRON_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
        }
 }
 #endif

diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index 61fc7b55310f7748770c06ce457e623f6816988e..8a3aa0c5bfdad3234d424f0b98e34e58ab3b3791 100644 (file)
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -128,8 +128,7 @@ int board_init(void)
  * provides the timing values back to the function that configures
  * the memory.
  */
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-               u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
        int pop_mfr, pop_id;
 
@@ -142,17 +141,17 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
 
        if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
                /* 256MB DDR */
-               *mcfg = HYNIX_V_MCFG_200(256 << 20);
-               *ctrla = HYNIX_V_ACTIMA_200;
-               *ctrlb = HYNIX_V_ACTIMB_200;
+               timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+               timings->ctrla = HYNIX_V_ACTIMA_200;
+               timings->ctrlb = HYNIX_V_ACTIMB_200;
        } else {
                /* 128MB DDR */
-               *mcfg = MICRON_V_MCFG_165(128 << 20);
-               *ctrla = MICRON_V_ACTIMA_165;
-               *ctrlb = MICRON_V_ACTIMB_165;
+               timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+               timings->ctrla = MICRON_V_ACTIMA_165;
+               timings->ctrlb = MICRON_V_ACTIMB_165;
        }
-       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
-       *mr = MICRON_V_MR_165;
+       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+       timings->mr = MICRON_V_MR_165;
 }
 #endif
 

diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index 35f5e15fc24b61e132cdb7b6947a2f0d61e576cd..85685ee7c05193ae8b353ef45ec6874ba88dbac4 100644 (file)
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -188,16 +188,15 @@ int spl_start_uboot(void)
  * provides the timing values back to the function that configures
  * the memory.  We have either one or two banks of 128MB DDR.
  */
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-               u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
        /* General SDRC config */
-       *mcfg = MICRON_V_MCFG_165(128 << 20);
-       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+       timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 
        /* AC timings */
-       *ctrla = MICRON_V_ACTIMA_165;
-       *ctrlb = MICRON_V_ACTIMB_165;
+       timings->ctrla = MICRON_V_ACTIMA_165;
+       timings->ctrlb = MICRON_V_ACTIMB_165;
 
-       *mr = MICRON_V_MR_165;
+       timings->mr = MICRON_V_MR_165;
 }