#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
-#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE)
+#define I2C1_BASE_ADDR (0x17000 + IMX_IO_BASE)
#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
#define IMX_ETB_SLOT4_BASE (0x43F0C000)
#define IMX_ETB_SLOT5_BASE (0x43F10000)
#define IMX_ECT_CTIO_BASE (0x43F18000)
-#define IMX_I2C_BASE (0x43F80000)
-#define IMX_I2C3_BASE (0x43F84000)
+#define I2C1_BASE_ADDR (0x43F80000)
+#define I2C3_BASE_ADDR (0x43F84000)
#define IMX_CAN1_BASE (0x43F88000)
#define IMX_CAN2_BASE (0x43F8C000)
#define UART1_BASE (0x43F90000)
#define UART2_BASE (0x43F94000)
-#define IMX_I2C2_BASE (0x43F98000)
+#define I2C2_BASE_ADDR (0x43F98000)
#define IMX_OWIRE_BASE (0x43F9C000)
#define IMX_CSPI1_BASE (0x43FA4000)
#define IMX_KPP_BASE (0x43FA8000)
#define UART2_BASE (0x0b000 + IMX_IO_BASE)
#define UART3_BASE (0x0c000 + IMX_IO_BASE)
#define UART4_BASE (0x0d000 + IMX_IO_BASE)
-#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE)
+#define I2C1_BASE_ADDR (0x12000 + IMX_IO_BASE)
#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE)
#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE)
#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE)
#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE)
#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE)
-#define IMX_I2C2_BASE (0x1D000 + IMX_IO_BASE)
+#define I2C2_BASE_ADDR (0x1D000 + IMX_IO_BASE)
#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE)
#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE)
#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
#define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000)
-#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000)
+#define I2C1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000)
#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000)
#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000)
#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
u8 clk_idx = i2c_imx_get_clk(speed);
u8 idx = i2c_clk_div[clk_idx][1];
+ if (!base)
+ return -ENODEV;
+
/* Store divider value */
writeb(idx, &i2c_regs->ifdr);
int i;
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
+ if (!base)
+ return -ENODEV;
+
ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
if (ret < 0)
return ret;
int i;
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
+ if (!base)
+ return -ENODEV;
+
ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
if (ret < 0)
return ret;
return ret;
}
-static void * const i2c_bases[] = {
-#if defined(CONFIG_SOC_MX25)
- (void *)IMX_I2C_BASE,
- (void *)IMX_I2C2_BASE,
- (void *)IMX_I2C3_BASE
-#elif defined(CONFIG_SOC_MX27)
- (void *)IMX_I2C1_BASE,
- (void *)IMX_I2C2_BASE
-#elif defined(CONFIG_SOC_MX31) || defined(CONFIG_SOC_MX35) || \
- defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) || \
- defined(CONFIG_SOC_MX6) || defined(CONFIG_SOC_LS102XA)
- (void *)I2C1_BASE_ADDR,
- (void *)I2C2_BASE_ADDR,
- (void *)I2C3_BASE_ADDR,
-#if defined(CONFIG_SOC_MX6DL)
- (void *)I2C4_BASE_ADDR
+#if !defined(I2C2_BASE_ADDR)
+#define I2C2_BASE_ADDR NULL
#endif
-#elif defined(CONFIG_SOC_VF610)
- (void *)I2C0_BASE_ADDR
-#elif defined(CONFIG_FSL_LSCH3)
+
+#if !defined(I2C3_BASE_ADDR)
+#define I2C3_BASE_ADDR NULL
+#endif
+
+#if !defined(I2C4_BASE_ADDR)
+#define I2C4_BASE_ADDR NULL
+#endif
+
+static void * const i2c_bases[] = {
(void *)I2C1_BASE_ADDR,
(void *)I2C2_BASE_ADDR,
(void *)I2C3_BASE_ADDR,
(void *)I2C4_BASE_ADDR
-#else
-#error "architecture not supported"
-#endif
};
struct i2c_parms {