#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
/* Define the bits in register CBCMR */
+#if defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6DL)
#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET)
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET)
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
+#else
+#define MXC_CCM_CBCMR_LCDIF_PODF_MASK (0x7 << MXC_CCM_CBCMR_LCDIF_PODF_OFFSET)
+#define MXC_CCM_CBCMR_LCDIF_PODF_OFFSET 23
+#endif
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20)
#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
/* All IPU2_DI1 are LCDIF1 on MX6SX */
+#if defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6DL)
#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET)
#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
#define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET)
#define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET 12
#define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET)
#define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET 9
+#else
+#define MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_OFFSET 15
+#define MXC_CCM_CSCDR2_LCDIF_PRED_MASK (0x7 << MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET)
+#define MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET 12
+#define MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_LCDIF_CLK_SEL_OFFSET)
+#define MXC_CCM_CSCDR2_LCDIF_CLK_SEL_OFFSET 9
+#endif
/* All IPU2_DI0 are LCDIF2 on MX6SX */
#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET)
#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
#define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
#endif
-#ifndef CONFIG_SOC_MX6SX
-#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
-#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
-#else
+#if defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL)
#define MXC_CCM_CCGR2_CSI_OFFSET 2
#define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
+#else
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
#endif
-#ifndef CONFIG_SOC_MX6SX
+#if !defined(CONFIG_SOC_MX6SX) && !defined(CONFIG_SOC_MX6UL)
#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
#endif
#define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
-#ifdef CONFIG_SOC_MX6SX
+#if defined(CONFIG_SOC_MX6SX) || (CONFIG_SOC_MX6UL)
#define MXC_CCM_CCGR2_LCD_OFFSET 28
#define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
#define MXC_CCM_CCGR2_PXP_OFFSET 30
#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
+/* IPU2_DI1 on i.MX6Q, i.MX6DL */
#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
+/* LCDIF on i.MX6UL */
+#define MXC_CCM_CCGR3_LCDIF_OFFSET 10
+#define MXC_CCM_CCGR3_LCDIF_MASK (3 << MXC_CCM_CCGR3_LCDIF_OFFSET)
+
#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
#define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
--- /dev/null
+/*
+ * Freescale i.MX6SL,SX,UL LCDIF Register Definitions
+ *
+ * Copyright (C) 2015 Lothar Waßmann <LW@karo-electronics.de>
+ * based on: arch/arm/include/asm/arch-mxs/regs-lcdif.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MX6_REGS_LCDIF_H__
+#define __MX6_REGS_LCDIF_H__
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mxs_lcdif_regs {
+ mxs_reg_32(hw_lcdif_ctrl); /* 0x00 */
+ mxs_reg_32(hw_lcdif_ctrl1); /* 0x10 */
+ mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
+ mxs_reg_32(hw_lcdif_transfer_count); /* 0x30 */
+ mxs_reg_32(hw_lcdif_cur_buf); /* 0x40 */
+ mxs_reg_32(hw_lcdif_next_buf); /* 0x50 */
+ mxs_reg_32(hw_lcdif_timing); /* 0x60 */
+ mxs_reg_32(hw_lcdif_vdctrl0); /* 0x70 */
+ mxs_reg_32(hw_lcdif_vdctrl1); /* 0x80 */
+ mxs_reg_32(hw_lcdif_vdctrl2); /* 0x90 */
+ mxs_reg_32(hw_lcdif_vdctrl3); /* 0xa0 */
+ mxs_reg_32(hw_lcdif_vdctrl4); /* 0xb0 */
+ mxs_reg_32(hw_lcdif_dvictrl0); /* 0xc0 */
+ mxs_reg_32(hw_lcdif_dvictrl1); /* 0xd0 */
+ mxs_reg_32(hw_lcdif_dvictrl2); /* 0xe0 */
+ mxs_reg_32(hw_lcdif_dvictrl3); /* 0xf0 */
+ mxs_reg_32(hw_lcdif_dvictrl4); /* 0x100 */
+ mxs_reg_32(hw_lcdif_csc_coeffctrl0); /* 0x110 */
+ mxs_reg_32(hw_lcdif_csc_coeffctrl1); /* 0x120 */
+ mxs_reg_32(hw_lcdif_csc_coeffctrl2); /* 0x130 */
+ mxs_reg_32(hw_lcdif_csc_coeffctrl3); /* 0x140 */
+ mxs_reg_32(hw_lcdif_csc_coeffctrl4); /* 0x150 */
+ mxs_reg_32(hw_lcdif_csc_offset); /* 0x160 */
+ mxs_reg_32(hw_lcdif_csc_limit); /* 0x170 */
+ mxs_reg_32(hw_lcdif_data) /* 0x180 */
+ mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x190 */
+ mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
+ mxs_reg_32(hw_lcdif_lcdif_stat); /* 0x1b0 */
+ mxs_reg_32(hw_lcdif_version); /* 0x1c0 */
+ mxs_reg_32(hw_lcdif_debug0); /* 0x1d0 */
+ mxs_reg_32(hw_lcdif_debug1); /* 0x1e0 */
+ mxs_reg_32(hw_lcdif_debug2); /* 0x1f0 */
+ mxs_reg_32(hw_elcdif_thresh); /* 0x200 */
+ mxs_reg_32(hw_elcdif_as_ctrl); /* 0x210 */
+ mxs_reg_32(hw_elcdif_as_buf); /* 0x220 */
+ mxs_reg_32(hw_elcdif_as_next_buf); /* 0x230 */
+ mxs_reg_32(hw_elcdif_as_clrkeylow); /* 0x240 */
+ mxs_reg_32(hw_elcdif_as_clrkeyhigh); /* 0x250 */
+ mxs_reg_32(hw_elcdif_sync_delay); /* 0x260 */
+ mxs_reg_32(hw_elcdif_debug3); /* 0x270 */
+ mxs_reg_32(hw_lcdif_debug4); /* 0x280 */
+ mxs_reg_32(hw_lcdif_debug5); /* 0x290 */
+};
+#endif
+
+#define LCDIF_CTRL_SFTRST (1 << 31)
+#define LCDIF_CTRL_CLKGATE (1 << 30)
+#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29)
+#define LCDIF_CTRL_READ_WRITEB (1 << 28)
+#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27)
+#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26)
+#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21)
+#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21
+#define LCDIF_CTRL_DVI_MODE (1 << 20)
+#define LCDIF_CTRL_BYPASS_COUNT (1 << 19)
+#define LCDIF_CTRL_VSYNC_MODE (1 << 18)
+#define LCDIF_CTRL_DOTCLK_MODE (1 << 17)
+#define LCDIF_CTRL_DATA_SELECT (1 << 16)
+#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14)
+#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14
+#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12)
+#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10)
+#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8
+#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8)
+#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7)
+#define LCDIF_CTRL_LCDIF_MASTER (1 << 5)
+#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3)
+#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2)
+#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1)
+#define LCDIF_CTRL_RUN (1 << 0)
+
+#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27)
+#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26)
+#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25)
+#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24)
+#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23)
+#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22)
+#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21)
+#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20)
+#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16)
+#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16
+#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(n) (((n) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET) & \
+ LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
+#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15)
+#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14)
+#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
+#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12)
+#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11)
+#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10)
+#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
+#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8)
+#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2)
+#define LCDIF_CTRL1_MODE86 (1 << 1)
+#define LCDIF_CTRL1_RESET (1 << 0)
+
+#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21)
+#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12)
+#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10)
+#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9)
+#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8)
+#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4)
+#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4
+#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1)
+#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1
+
+#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16)
+#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16
+#define LCDIF_TRANSFER_COUNT_V_COUNT(n) (((n) << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) & \
+ LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
+#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0)
+#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0
+#define LCDIF_TRANSFER_COUNT_H_COUNT(n) (((n) << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET) & \
+ LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
+
+#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff
+#define LCDIF_CUR_BUF_ADDR_OFFSET 0
+
+#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff
+#define LCDIF_NEXT_BUF_ADDR_OFFSET 0
+
+#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24)
+#define LCDIF_TIMING_CMD_HOLD_OFFSET 24
+#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16)
+#define LCDIF_TIMING_CMD_SETUP_OFFSET 16
+#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8)
+#define LCDIF_TIMING_DATA_HOLD_OFFSET 8
+#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0)
+#define LCDIF_TIMING_DATA_SETUP_OFFSET 0
+
+#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29)
+#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28)
+#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27)
+#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26)
+#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25)
+#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24)
+#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)
+#define LCDIF_VDCTRL0_HALF_LINE (1 << 19)
+#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18)
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(n) (((n) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET) & \
+ LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
+
+#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
+#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
+#define LCDIF_VDCTRL1_VSYNC_PERIOD(n) (((n) << LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET) & \
+ LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
+
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(n) (((n) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) & \
+ LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
+#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
+#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
+#define LCDIF_VDCTRL2_HSYNC_PERIOD(n) (((n) << LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET) & \
+ LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
+
+#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
+#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28)
+#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16)
+#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16
+#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(n) (((n) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) & \
+ LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
+#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0)
+#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0
+#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(n) (((n) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET) & \
+ LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
+
+#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29)
+#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29
+#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(n) (((n) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) & \
+ LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
+#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
+#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
+#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
+#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(n) (((n) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET) & \
+ LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
+
+#endif /* __MX6_REGS_LCDIF_H__ */
{
if (lcd_enabled) {
printf("Disabling LCD\n");
-// ipuv3_fb_shutdown();
- }
-}
-
-void lcd_panel_disable(void)
-{
- if (lcd_enabled) {
- debug("Switching LCD off\n");
- gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
- !lcd_backlight_polarity());
- gpio_set_value(TX6UL_LCD_RST_GPIO, 0);
- gpio_set_value(TX6UL_LCD_PWR_GPIO, 0);
+ panel_info.vl_row = 0;
+ lcd_enabled = 0;
}
}
};
static const struct gpio stk5_lcd_gpios[] = {
-// { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
+ { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
{ TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
{ TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
};
struct fb_videomode *p = &tx6_fb_modes[0];
struct fb_videomode fb_mode;
int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
- int pix_fmt;
- int lcd_bus_width;
if (!lcd_enabled) {
debug("LCD disabled\n");
}
if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
- debug("Disabling LCD\n");
- lcd_enabled = 0;
+ lcd_disable();
setenv("splashimage", NULL);
return;
}
lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
if (video_mode == NULL) {
- debug("Disabling LCD\n");
- lcd_enabled = 0;
+ lcd_disable();
return;
}
vm = video_mode;
yres_set = 1;
} else if (!bpp_set) {
switch (val) {
- case 32:
- case 24:
- if (is_lvds())
- pix_fmt = IPU_PIX_FMT_LVDS888;
- /* fallthru */
- case 16:
case 8:
+ case 16:
+ case 18:
+ case 24:
+ case 32:
color_depth = val;
break;
- case 18:
- if (is_lvds()) {
- color_depth = val;
- break;
- }
- /* fallthru */
default:
printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
end - vm, vm, color_depth);
imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
ARRAY_SIZE(stk5_lcd_pads));
- lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
- switch (lcd_bus_width) {
- case 24:
- pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
- break;
-
- case 18:
- pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
- break;
-
- case 16:
- if (!is_lvds()) {
- pix_fmt = IPU_PIX_FMT_RGB565;
- break;
- }
- /* fallthru */
- default:
- lcd_enabled = 0;
- printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
- lcd_bus_width);
- return;
- }
- if (is_lvds()) {
- int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
- int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
- uint32_t gpr2;
- uint32_t gpr3;
-
- if (lvds_chan_mask == 0) {
- printf("No LVDS channel active\n");
- lcd_enabled = 0;
- return;
- }
+ debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
+ color_depth, refresh);
- gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
- if (lcd_bus_width == 24)
- gpr2 |= (1 << 5) | (1 << 7);
- gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
- gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
- debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
- writel(gpr2, IOMUXC_BASE_ADDR + 8);
-
- gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
- gpr3 &= ~((3 << 8) | (3 << 6));
- writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
- }
if (karo_load_splashimage(0) == 0) {
-#if 0
- int ret;
+ char vmode[128];
+
+ /* setup env variable for mxsfb display driver */
+ snprintf(vmode, sizeof(vmode),
+ "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
+ p->xres, p->yres, p->left_margin, p->right_margin,
+ p->upper_margin, p->lower_margin, p->hsync_len,
+ p->vsync_len, p->sync, p->pixclock, color_depth);
+ setenv("videomode", vmode);
debug("Initializing LCD controller\n");
- ret = ipuv3_fb_init(p, 0, pix_fmt,
- is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
- di_clk_rate, -1);
- if (ret) {
- printf("Failed to initialize FB driver: %d\n", ret);
- lcd_enabled = 0;
- }
-#else
- lcd_enabled = pix_fmt * 0;
-#endif
+ lcdif_clk_enable();
+ video_hw_init();
+ setenv("videomode", NULL);
} else {
debug("Skipping initialization of LCD controller\n");
}
projects / karo-tx-uboot.git / commitdiff