#
# Generated files
#
-
/LOG
-/errlog
-/reloc_off
-
/spl/
/tpl/
--- /dev/null
+#
+# This list is used by git-shortlog to fix a few botched name translations
+# in the git archive, either because the author's full name was messed up
+# and/or not always written the same way, making contributions from the
+# same person appearing not to be so or badly displayed.
+#
+# This file can be modified by hand or updated by the following command:
+# scripts/mailmapper > tmp; mv tmp .mailmap
+#
+
+Allen Martin <amartin@nvidia.com>
+Andreas Bießmann <andreas.devel@googlemail.com>
+Aneesh V <aneesh@ti.com>
+Dirk Behme <dirk.behme@googlemail.com>
+Fabio Estevam <fabio.estevam@freescale.com>
+Jagannadha Sutradharudu Teki <402jagan@gmail.com>
+Markus Klotzbuecher <mk@denx.de>
+Prabhakar Kushwaha <prabhakar@freescale.com>
+Rajeshwari Shinde <rajeshwari.s@samsung.com>
+Sandeep Paulraj <s-paulraj@ti.com>
+Shaohui Xie <Shaohui.Xie@freescale.com>
+Stefan Roese <stroese>
+Stefano Babic <sbabic@denx.de>
+TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Wolfgang Denk <wdenk>
+York Sun <yorksun@freescale.com>
+Łukasz Majewski <l.majewski@samsung.com>
VERSION = 2014
PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION =
NAME =
# *DOCUMENTATION*
binary_size_check: u-boot.bin System.map FORCE
@file_size=`stat -c %s u-boot.bin` ; \
map_size=$(shell cat System.map | \
- awk '/_image_copy_start/ {start = $$1} /_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print strtonum("0x" end) - strtonum("0x" start)}'); \
+ awk '/_image_copy_start/ {start = $$1} /_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print "ibase=16; " toupper(end) " - " toupper(start)}' \
+ | bc); \
if [ "" != "$$map_size" ]; then \
if test $$map_size -ne $$file_size; then \
echo "System.map shows a binary size of $$map_size" >&2 ; \
tpl/u-boot-tpl.bin: tools prepare
$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all CONFIG_TPL_BUILD=y
-TAG_SUBDIRS := $(u-boot-dirs) include
+TAG_SUBDIRS := $(patsubst %,$(srctree)/%,$(u-boot-dirs) include)
FIND := find
FINDFLAGS := -L
-name '*.[chS]' -print`
etags:
- etags -a -o $(obj)etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
+ etags -a -o etags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
-name '*.[chS]' -print`
cscope:
$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) -name '*.[chS]' -print > \
MRPROPER_DIRS += include/config include/generated \
.tmp_objdiff
MRPROPER_FILES += .config .config.old \
- tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
+ ctags etags cscope* GPATH GTAGS GRTAGS GSYMS \
include/config.h include/config.mk
# clean - Delete most, but leave enough to build external modules
mrproper: clobber $(mrproper-dirs)
$(call cmd,rmdirs)
$(call cmd,rmfiles)
- @rm -f arch/*/include/asm/arch arch/*/include/asm/proc
+ @rm -f arch/*/include/asm/arch
# distclean
#
@echo ' dir/file.[oisS] - Build specified target only'
@echo ' dir/file.lst - Build specified mixed source/assembly target only'
@echo ' (requires a recent binutils and recent build (System.map))'
- @echo ' tags/TAGS - Generate tags file for editors'
+ @echo ' tags/ctags - Generate ctags file for editors'
+ @echo ' etags - Generate etags file for editors'
@echo ' cscope - Generate cscope index'
@echo ' ubootrelease - Output the release version string'
@echo ' ubootversion - Output the version stored in Makefile'
9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
with a fix speed from 100000 and the slave addr 0!
+ - drivers/i2c/ihs_i2c.c
+ - activate this driver with CONFIG_SYS_I2C_IHS
+ - CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0
+ - CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0
+ - CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0
+ - CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1
+ - CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1
+ - CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1
+ - CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2
+ - CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2
+ - CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2
+ - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3
+ - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3
+ - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3
+
additional defines:
CONFIG_SYS_NUM_I2C_BUSES
disabled. If a board need legacy image format support
enable this through CONFIG_IMAGE_FORMAT_LEGACY
+ CONFIG_FIT_DISABLE_SHA256
+ Supporting SHA256 hashes has quite an impact on binary size.
+ For constrained systems sha256 hash support can be disabled
+ with this option.
+
- Standalone program support:
CONFIG_STANDALONE_LOAD_ADDR
- CONFIG_SYS_MALLOC_LEN:
Size of DRAM reserved for malloc() use.
+- CONFIG_SYS_MALLOC_F_LEN
+ Size of the malloc() pool for use before relocation. If
+ this is defined, then a very simple malloc() implementation
+ will become available before relocation. The address is just
+ below the global data, and the stack is moved down to make
+ space.
+
+ This feature allocates regions with increasing addresses
+ within the region. calloc() is supported, but realloc()
+ is not available. free() is supported but does nothing.
+ The memory will be freed (or in fact just forgotton) when
+ U-Boot relocates itself.
+
+ Pre-relocation malloc() is only supported on sandbox
+ at present but is fairly easy to enable for other archs.
+
- CONFIG_SYS_BOOTM_LEN:
Normally compressed uImages are limited to an
uncompressed size of 8 MBytes. If this is not enough,
environment area within the total memory of your DataFlash placed
at the specified address.
+- CONFIG_ENV_IS_IN_SPI_FLASH:
+
+ Define this if you have a SPI Flash memory device which you
+ want to use for the environment.
+
+ - CONFIG_ENV_OFFSET:
+ - CONFIG_ENV_SIZE:
+
+ These two #defines specify the offset and size of the
+ environment area within the SPI Flash. CONFIG_ENV_OFFSET must be
+ aligned to an erase sector boundary.
+
+ - CONFIG_ENV_SECT_SIZE:
+
+ Define the SPI flash's sector size.
+
+ - CONFIG_ENV_OFFSET_REDUND (optional):
+
+ This setting describes a second storage area of CONFIG_ENV_SIZE
+ size used to hold a redundant copy of the environment data, so
+ that there is a valid backup copy in case there is a power failure
+ during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be
+ aligned to an erase sector boundary.
+
+ - CONFIG_ENV_SPI_BUS (optional):
+ - CONFIG_ENV_SPI_CS (optional):
+
+ Define the SPI bus and chip select. If not defined they will be 0.
+
+ - CONFIG_ENV_SPI_MAX_HZ (optional):
+
+ Define the SPI max work clock. If not defined then use 1MHz.
+
+ - CONFIG_ENV_SPI_MODE (optional):
+
+ Define the SPI work mode. If not defined then use SPI_MODE_3.
+
- CONFIG_ENV_IS_IN_REMOTE:
Define this if you have a remote memory space which you
You will probably want to define these to avoid a really noisy system
when storing the env in UBI.
+- CONFIG_ENV_IS_IN_FAT:
+ Define this if you want to use the FAT file system for the environment.
+
+ - FAT_ENV_INTERFACE:
+
+ Define this to a string that is the name of the block device.
+
+ - FAT_ENV_DEV_AND_PART:
+
+ Define this to a string to specify the partition of the device. It can
+ be as following:
+
+ "D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1)
+ - "D:P": device D partition P. Error occurs if device D has no
+ partition table.
+ - "D:0": device D.
+ - "D" or "D:": device D partition 1 if device D has partition
+ table, or the whole device D if has no partition
+ table.
+ - "D:auto": first partition in device D with bootable flag set.
+ If none, first valid paratition in device D. If no
+ partition table then means device D.
+
+ - FAT_ENV_FILE:
+
+ It's a string of the FAT file name. This file use to store the
+ envrionment.
+
+ - CONFIG_FAT_WRITE:
+ This should be defined. Otherwise it cannot save the envrionment file.
+
- CONFIG_ENV_IS_IN_MMC:
Define this if you have an MMC device which you want to use for the
OBJCOPYFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
endif
+ifdef CONFIG_OF_EMBED
+OBJCOPYFLAGS += -j .dtb.init.rodata
+endif
+
ifneq ($(CONFIG_IMX_CONFIG),)
ifdef CONFIG_SPL
ifndef CONFIG_SPL_BUILD
writel(regs->emif_rd_wr_exec_thresh,
&emif_reg[nr]->emif_rd_wr_exec_thresh);
+ /*
+ * for most SOCs these registers won't need to be changed so only
+ * write to these registers if someone explicitly has set the
+ * register's value.
+ */
+ if(regs->emif_cos_config) {
+ writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
+ writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
+ writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
+ writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
+ }
+
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
#endif
#ifdef CONFIG_AM43XX
writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
- while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
+ while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
;
writel(0x80000000, &ddrctrl->ddrioctrl);
div = __raw_readl(&imx_ccm->analog_pll_sys);
div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
- return infreq * (div >> 1);
+ return (infreq * div) >> 1;
case PLL_BUS:
div = __raw_readl(&imx_ccm->analog_pll_528);
div &= BM_ANADIG_PLL_528_DIV_SELECT;
}
/*
- * Set the VDDSOC
+ * Set the PMU_REG_CORE register
*
- * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
- * them to the specified millivolt level.
+ * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
* Possible values are from 0.725V to 1.450V in steps of
* 0.025V (25mV).
*/
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
+obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
{ 0x40, "R8A7740" },
{ 0x45, "R8A7790" },
{ 0x47, "R8A7791" },
+ { 0x4C, "R8A7794" },
{ 0x0, "CPU" },
};
--- /dev/null
+/*
+ * arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
+ * This file is r8a7794 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+
+#define CPU_32_PORT(fn, pfx, sfx) \
+ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
+ PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
+ PORT_1(fn, pfx##31, sfx)
+
+#define CPU_26_PORT(fn, pfx, sfx) \
+ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
+ PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
+ PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
+ PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
+
+#define CPU_28_PORT(fn, pfx, sfx) \
+ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
+ PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
+ PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
+ PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
+ PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
+
+/*
+ * GP_0_0_DATA -> GP_6_25_DATA
+ * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30],GP1[31]
+ * GP5[28],GP5[29]),GP5[30],GP5[31],GP6[26],GP6[27],GP6[28],
+ * GP6[29]),GP6[30],GP6[31])
+ */
+#define CPU_ALL_PORT(fn, pfx, sfx) \
+ CPU_32_PORT(fn, pfx##_0_, sfx), \
+ CPU_26_PORT(fn, pfx##_1_, sfx), \
+ CPU_32_PORT(fn, pfx##_2_, sfx), \
+ CPU_32_PORT(fn, pfx##_3_, sfx), \
+ CPU_32_PORT(fn, pfx##_4_, sfx), \
+ CPU_28_PORT(fn, pfx##_5_, sfx), \
+ CPU_26_PORT(fn, pfx##_6_, sfx)
+
+#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
+#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
+ GP##pfx##_IN, GP##pfx##_OUT)
+
+#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
+#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
+
+#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
+#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
+#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
+
+
+#define PORT_10_REV(fn, pfx, sfx) \
+ PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
+ PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
+ PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
+ PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
+ PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
+
+#define CPU_32_PORT_REV(fn, pfx, sfx) \
+ PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
+ PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
+ PORT_10_REV(fn, pfx, sfx)
+
+#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
+#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
+
+#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
+#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
+ FN_##ipsr, FN_##fn)
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ GP_ALL(DATA),
+ PINMUX_DATA_END,
+
+ PINMUX_INPUT_BEGIN,
+ GP_ALL(IN),
+ PINMUX_INPUT_END,
+
+ PINMUX_OUTPUT_BEGIN,
+ GP_ALL(OUT),
+ PINMUX_OUTPUT_END,
+
+ PINMUX_FUNCTION_BEGIN,
+ GP_ALL(FN),
+
+ /* GPSR0 */
+ FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
+ FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
+ FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
+ FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
+ FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
+ FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
+ FN_IP2_17_16,
+
+ /* GPSR1 */
+ FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
+ FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
+ FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
+ FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
+ FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
+
+ /* GPSR2 */
+ FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
+ FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
+ FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
+ FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
+ FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
+ FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
+ FN_IP6_5_4, FN_IP6_7_6,
+
+ /* GPSR3 */
+ FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
+ FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
+ FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
+ FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
+ FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
+ FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
+ FN_IP8_22_20,
+
+ /* GPSR4 */
+ FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
+ FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
+ FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
+ FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
+ FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
+ FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
+ FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
+
+ /* GPSR5 */
+ FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
+ FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
+ FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
+ FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
+ FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
+ FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
+
+ /* GPSR6 */
+ FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
+ FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
+ FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
+ FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
+ FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
+
+ /*
+ * From IPSR0 to IPSR5 have been removed because they does not use.
+ */
+
+ /* IPSR6 */
+ FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28,
+ FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
+ FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB,
+ FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
+ FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2,
+ FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4,
+ FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6,
+ FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB,
+ FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD,
+ FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
+ FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
+ FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
+ FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK,
+ FN_ADIDATA, FN_AD_DI,
+
+ /* IPSR7 */
+ FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0,
+ FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
+ FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
+ FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
+ FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
+ FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
+ FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
+ FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
+ FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
+ FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
+ FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
+ FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
+ FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD,
+
+ /* IPSR8 */
+ FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
+ FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C,
+ FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX,
+ FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B,
+ FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
+ FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7,
+ FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
+ FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
+ FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
+ FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0,
+ FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD,
+ FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B,
+ FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B,
+ FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C,
+ FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
+
+ /*
+ * From IPSR9 to IPSR10 have been removed because they does not use.
+ */
+
+ /* IPSR11 */
+ FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
+ FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C,
+ FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
+ FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6,
+ FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
+ FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
+ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
+ FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
+ FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
+ FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
+ FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
+ FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
+ FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
+ FN_ADICLK_B, FN_AD_CLK_B,
+
+ /*
+ * From IPSR12 to IPSR13 have been removed because they does not use.
+ */
+
+ /* MOD_SEL */
+ FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
+ FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1,
+ FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1,
+ FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0,
+ FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1,
+ FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0,
+ FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
+ FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1,
+ FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0,
+ FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
+ FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
+ FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
+ FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1,
+ FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
+
+ /* MOD_SEL2 */
+ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0,
+ FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0,
+ FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
+ FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
+ FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
+ FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0,
+ FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+ FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1,
+ FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1,
+ FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1,
+ FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
+ FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1,
+ FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+ FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
+ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1,
+ FN_SEL_RDS_2, FN_SEL_RDS_3,
+
+ /* MOD_SEL3 */
+ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
+ FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
+ FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
+ FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
+ FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
+ FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
+ FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
+ FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
+ FN_SEL_SSI9_1,
+ PINMUX_FUNCTION_END,
+
+ PINMUX_MARK_BEGIN,
+ A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
+
+ USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
+
+ SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
+ SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
+
+ SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
+ SD1_DATA2_MARK, SD1_DATA3_MARK,
+
+ /*
+ * From IPSR0 to IPSR5 have been removed because they does not use.
+ */
+
+ /* IPSR6 */
+ DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK,
+ DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK,
+ DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK,
+ CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
+ AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
+ VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK,
+ AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
+ VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK,
+ AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK,
+ I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK,
+ VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
+ AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
+ IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
+ I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
+ VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK,
+ ADIDATA_MARK, AD_DI_MARK,
+
+ /* IPSR7 */
+ ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK,
+ AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
+ MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
+ AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
+ CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK,
+ ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
+ AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK,
+ MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
+ ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
+ SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
+ IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
+ VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK,
+ SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK,
+ AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK,
+ SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
+ DREQ0_N_MARK, SCIFB1_RXD_MARK,
+
+ /* IPSR8 */
+ ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
+ AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
+ I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
+ HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
+ AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
+ SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
+ HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
+ AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
+ HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
+ I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
+ AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
+ SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
+ CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK,
+ DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK,
+ I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK,
+ TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK,
+ I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK,
+ FMCLK_C_MARK, RDS_CLK_MARK,
+
+ /*
+ * From IPSR9 to IPSR10 have been removed because they does not use.
+ */
+
+ /* IPSR11 */
+ SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
+ CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK,
+ DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK,
+ SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
+ SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
+ DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
+ SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
+ CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK,
+ DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK,
+ DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
+ AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
+ MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
+ PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
+ ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK,
+ PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK,
+
+ /*
+ * From IPSR12 to IPSR13 have been removed because they does not use.
+ */
+
+ PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+ PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+ PINMUX_DATA(A2_MARK, FN_A2),
+ PINMUX_DATA(WE0_N_MARK, FN_WE0_N),
+ PINMUX_DATA(WE1_N_MARK, FN_WE1_N),
+ PINMUX_DATA(DACK0_MARK, FN_DACK0),
+ PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
+ PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
+ PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
+ PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
+ PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK),
+ PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD),
+ PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0),
+ PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1),
+ PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2),
+ PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3),
+ PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD),
+ PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP),
+ PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
+ PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD),
+ PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0),
+ PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1),
+ PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2),
+ PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3),
+
+ /*
+ * From IPSR0 to IPSR5 have been removed because they does not use.
+ */
+
+ /* IPSR6 */
+ PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
+ PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE),
+ PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28),
+ PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
+ PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE),
+ PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29),
+ PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP),
+ PINMUX_IPSR_DATA(IP6_5_4, QPOLA),
+ PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30),
+ PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE),
+ PINMUX_IPSR_DATA(IP6_7_6, QPOLB),
+ PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31),
+ PINMUX_IPSR_DATA(IP6_8, VI0_CLK),
+ PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK),
+ PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0),
+ PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV),
+ PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1),
+ PINMUX_IPSR_DATA(IP6_10, AVB_RXD0),
+ PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2),
+ PINMUX_IPSR_DATA(IP6_11, AVB_RXD1),
+ PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3),
+ PINMUX_IPSR_DATA(IP6_12, AVB_RXD2),
+ PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4),
+ PINMUX_IPSR_DATA(IP6_13, AVB_RXD3),
+ PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5),
+ PINMUX_IPSR_DATA(IP6_14, AVB_RXD4),
+ PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6),
+ PINMUX_IPSR_DATA(IP6_15, AVB_RXD5),
+ PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7),
+ PINMUX_IPSR_DATA(IP6_16, AVB_RXD6),
+ PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB),
+ PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
+ PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
+ PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2),
+ PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7),
+ PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD),
+ PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
+ PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
+ PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2),
+ PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER),
+ PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N),
+ PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
+ PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2),
+ PINMUX_IPSR_DATA(IP6_25_23, AVB_COL),
+ PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N),
+ PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
+ PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
+ PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN),
+ PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0),
+ PINMUX_IPSR_DATA(IP6_31_29, VI0_G0),
+ PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
+ PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0),
+ PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0),
+
+ /* IPSR7 */
+ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
+ PINMUX_IPSR_DATA(IP7_2_0, VI0_G1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
+ PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0),
+ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
+ PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0),
+ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
+ PINMUX_IPSR_DATA(IP7_5_3, VI0_G2),
+ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
+ PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0),
+ PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0),
+ PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0),
+ PINMUX_IPSR_DATA(IP7_8_6, VI0_G3),
+ PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
+ PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2),
+ PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0),
+ PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0),
+ PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0),
+ PINMUX_IPSR_DATA(IP7_11_9, VI0_G4),
+ PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
+ PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3),
+ PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0),
+ PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0),
+ PINMUX_IPSR_DATA(IP7_14_12, VI0_G5),
+ PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
+ PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4),
+ PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0),
+ PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
+ PINMUX_IPSR_DATA(IP7_17_15, VI0_G6),
+ PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
+ PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5),
+ PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0),
+ PINMUX_IPSR_DATA(IP7_20_18, VI0_G7),
+ PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
+ PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
+ PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6),
+ PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
+ PINMUX_IPSR_DATA(IP7_23_21, VI0_R0),
+ PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
+ PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
+ PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7),
+ PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
+ PINMUX_IPSR_DATA(IP7_26_24, VI0_R1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
+ PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER),
+ PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0),
+ PINMUX_IPSR_DATA(IP7_29_27, VI0_R2),
+ PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
+ PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
+ PINMUX_IPSR_DATA(IP7_31, DREQ0_N),
+ PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD),
+
+ /* IPSR8 */
+ PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0),
+ PINMUX_IPSR_DATA(IP8_2_0, VI0_R3),
+ PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
+ PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC),
+ PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
+ PINMUX_IPSR_DATA(IP8_5_3, VI0_R4),
+ PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
+ PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
+ PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO),
+ PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
+ PINMUX_IPSR_DATA(IP8_8_6, VI0_R5),
+ PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
+ PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
+ PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK),
+ PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
+ PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N),
+ PINMUX_IPSR_DATA(IP8_11_9, VI0_R6),
+ PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
+ PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
+ PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC),
+ PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
+ PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N),
+ PINMUX_IPSR_DATA(IP8_14_12, VI0_R7),
+ PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
+ PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
+ PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT),
+ PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
+ PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS),
+ PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
+ PINMUX_IPSR_DATA(IP8_19_17, PWM5),
+ PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1),
+ PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK),
+ PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
+ PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B),
+ PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
+ PINMUX_IPSR_DATA(IP8_22_20, TPUTO0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0),
+ PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE),
+ PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
+ PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
+ PINMUX_IPSR_DATA(IP8_25_23, PWM5_B),
+ PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
+ PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B),
+ PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
+ PINMUX_IPSR_DATA(IP8_28_26, IRQ5),
+ PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2),
+ PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD),
+ PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
+ PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2),
+ PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
+ PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2),
+ PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0),
+
+ /*
+ * From IPSR9 to IPSR10 have been removed because they does not use.
+ */
+
+ /* IPSR11 */
+ PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
+ PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0),
+ PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11),
+ PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
+ PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1),
+ PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12),
+ PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
+ PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13),
+ PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
+ PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
+ PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14),
+ PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
+ PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
+ PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15),
+ PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
+ PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP),
+ PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
+ PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE),
+ PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
+ PINMUX_IPSR_DATA(IP11_20_18, IRQ8),
+ PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
+ PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
+ PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N),
+ PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129),
+ PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
+ PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1),
+ PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N),
+ PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129),
+ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
+ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1),
+ PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
+ PINMUX_IPSR_DATA(IP11_29_27, PWM0_B),
+ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1),
+
+ /*
+ * From IPSR12 to IPSR13 have been removed because they does not use.
+ */
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+ PINMUX_GPIO_GP_ALL(),
+
+ GPIO_FN(A2), GPIO_FN(WE0_N), GPIO_FN(WE1_N), GPIO_FN(DACK0),
+ GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC), GPIO_FN(USB1_PWEN),
+ GPIO_FN(USB1_OVC), GPIO_FN(SD0_CLK), GPIO_FN(SD0_CMD),
+ GPIO_FN(SD0_DATA0), GPIO_FN(SD0_DATA1), GPIO_FN(SD0_DATA2),
+ GPIO_FN(SD0_DATA3), GPIO_FN(SD0_CD), GPIO_FN(SD0_WP),
+ GPIO_FN(SD1_CLK), GPIO_FN(SD1_CMD), GPIO_FN(SD1_DATA0),
+ GPIO_FN(SD1_DATA1), GPIO_FN(SD1_DATA2), GPIO_FN(SD1_DATA3),
+
+ /*
+ * From IPSR0 to IPSR5 have been removed because they does not use
+ */
+
+ /* IPSR6 */
+ GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
+ GPIO_FN(CC50_STATE28), GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE),
+ GPIO_FN(QCPV_QDE), GPIO_FN(CC50_STATE29), GPIO_FN(DU0_DISP),
+ GPIO_FN(QPOLA), GPIO_FN(CC50_STATE30), GPIO_FN(DU0_CDE), GPIO_FN(QPOLB),
+ GPIO_FN(CC50_STATE31), GPIO_FN(VI0_CLK), GPIO_FN(AVB_RX_CLK),
+ GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(AVB_RX_DV),
+ GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(AVB_RXD0), GPIO_FN(VI0_DATA2_VI0_B2),
+ GPIO_FN(AVB_RXD1), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(AVB_RXD2),
+ GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(AVB_RXD3), GPIO_FN(VI0_DATA5_VI0_B5),
+ GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RXD5),
+ GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RXD6), GPIO_FN(VI0_CLKENB),
+ GPIO_FN(I2C3_SCL), GPIO_FN(SCIFA5_RXD_C), GPIO_FN(IETX_C),
+ GPIO_FN(AVB_RXD7), GPIO_FN(VI0_FIELD), GPIO_FN(I2C3_SDA),
+ GPIO_FN(SCIFA5_TXD_C), GPIO_FN(IECLK_C), GPIO_FN(AVB_RX_ER),
+ GPIO_FN(VI0_HSYNC_N), GPIO_FN(SCIF0_RXD_B), GPIO_FN(I2C0_SCL_C),
+ GPIO_FN(IERX_C), GPIO_FN(AVB_COL), GPIO_FN(VI0_VSYNC_N),
+ GPIO_FN(SCIF0_TXD_B), GPIO_FN(I2C0_SDA_C), GPIO_FN(AUDIO_CLKOUT_B),
+ GPIO_FN(AVB_TX_EN), GPIO_FN(ETH_MDIO), GPIO_FN(VI0_G0),
+ GPIO_FN(MSIOF2_RXD_B), GPIO_FN(IIC0_SCL_D), GPIO_FN(AVB_TX_CLK),
+ GPIO_FN(ADIDATA), GPIO_FN(AD_DI),
+
+ /* IPSR7 */
+ GPIO_FN(ETH_CRS_DV), GPIO_FN(VI0_G1), GPIO_FN(MSIOF2_TXD_B),
+ GPIO_FN(IIC0_SDA_D), GPIO_FN(AVB_TXD0), GPIO_FN(ADICS_SAMP),
+ GPIO_FN(AD_DO), GPIO_FN(ETH_RX_ER), GPIO_FN(VI0_G2),
+ GPIO_FN(MSIOF2_SCK_B), GPIO_FN(CAN0_RX_B), GPIO_FN(AVB_TXD1),
+ GPIO_FN(ADICLK), GPIO_FN(AD_CLK), GPIO_FN(ETH_RXD0), GPIO_FN(VI0_G3),
+ GPIO_FN(MSIOF2_SYNC_B), GPIO_FN(CAN0_TX_B), GPIO_FN(AVB_TXD2),
+ GPIO_FN(ADICHS0), GPIO_FN(AD_NCS_N), GPIO_FN(ETH_RXD1),
+ GPIO_FN(VI0_G4), GPIO_FN(MSIOF2_SS1_B), GPIO_FN(SCIF4_RXD_D),
+ GPIO_FN(AVB_TXD3), GPIO_FN(ADICHS1), GPIO_FN(ETH_LINK), GPIO_FN(VI0_G5),
+ GPIO_FN(MSIOF2_SS2_B), GPIO_FN(SCIF4_TXD_D), GPIO_FN(AVB_TXD4),
+ GPIO_FN(ADICHS2), GPIO_FN(ETH_REFCLK), GPIO_FN(VI0_G6),
+ GPIO_FN(SCIF2_SCK_C), GPIO_FN(AVB_TXD5), GPIO_FN(SSI_SCK5_B),
+ GPIO_FN(ETH_TXD1), GPIO_FN(VI0_G7), GPIO_FN(SCIF2_RXD_C),
+ GPIO_FN(IIC1_SCL_D), GPIO_FN(AVB_TXD6), GPIO_FN(SSI_WS5_B),
+ GPIO_FN(ETH_TX_EN), GPIO_FN(VI0_R0), GPIO_FN(SCIF2_TXD_C),
+ GPIO_FN(IIC1_SDA_D), GPIO_FN(AVB_TXD7), GPIO_FN(SSI_SDATA5_B),
+ GPIO_FN(ETH_MAGIC), GPIO_FN(VI0_R1), GPIO_FN(SCIF3_SCK_B),
+ GPIO_FN(AVB_TX_ER), GPIO_FN(SSI_SCK6_B), GPIO_FN(ETH_TXD0),
+ GPIO_FN(VI0_R2), GPIO_FN(SCIF3_RXD_B), GPIO_FN(I2C4_SCL_E),
+ GPIO_FN(AVB_GTX_CLK), GPIO_FN(SSI_WS6_B), GPIO_FN(DREQ0_N),
+ GPIO_FN(SCIFB1_RXD),
+
+ /* IPSR8 */
+ GPIO_FN(ETH_MDC), GPIO_FN(VI0_R3), GPIO_FN(SCIF3_TXD_B),
+ GPIO_FN(I2C4_SDA_E), GPIO_FN(AVB_MDC), GPIO_FN(SSI_SDATA6_B),
+ GPIO_FN(HSCIF0_HRX), GPIO_FN(VI0_R4), GPIO_FN(I2C1_SCL_C),
+ GPIO_FN(AUDIO_CLKA_B), GPIO_FN(AVB_MDIO), GPIO_FN(SSI_SCK78_B),
+ GPIO_FN(HSCIF0_HTX), GPIO_FN(VI0_R5), GPIO_FN(I2C1_SDA_C),
+ GPIO_FN(AUDIO_CLKB_B), GPIO_FN(AVB_LINK), GPIO_FN(SSI_WS78_B),
+ GPIO_FN(HSCIF0_HCTS_N), GPIO_FN(VI0_R6), GPIO_FN(SCIF0_RXD_D),
+ GPIO_FN(I2C0_SCL_E), GPIO_FN(AVB_MAGIC), GPIO_FN(SSI_SDATA7_B),
+ GPIO_FN(HSCIF0_HRTS_N), GPIO_FN(VI0_R7), GPIO_FN(SCIF0_TXD_D),
+ GPIO_FN(I2C0_SDA_E), GPIO_FN(AVB_PHY_INT), GPIO_FN(SSI_SDATA8_B),
+ GPIO_FN(HSCIF0_HSCK), GPIO_FN(SCIF_CLK_B), GPIO_FN(AVB_CRS),
+ GPIO_FN(AUDIO_CLKC_B), GPIO_FN(I2C0_SCL), GPIO_FN(SCIF0_RXD_C),
+ GPIO_FN(PWM5), GPIO_FN(TCLK1_B), GPIO_FN(AVB_GTXREFCLK),
+ GPIO_FN(CAN1_RX_D), GPIO_FN(TPUTO0_B), GPIO_FN(I2C0_SDA),
+ GPIO_FN(SCIF0_TXD_C), GPIO_FN(TPUTO0), GPIO_FN(CAN_CLK),
+ GPIO_FN(DVC_MUTE), GPIO_FN(CAN1_TX_D), GPIO_FN(I2C1_SCL),
+ GPIO_FN(SCIF4_RXD), GPIO_FN(PWM5_B), GPIO_FN(DU1_DR0),
+ GPIO_FN(RIF1_SYNC_B), GPIO_FN(TS_SDATA_D), GPIO_FN(TPUTO1_B),
+ GPIO_FN(I2C1_SDA), GPIO_FN(SCIF4_TXD), GPIO_FN(IRQ5),
+ GPIO_FN(DU1_DR1), GPIO_FN(RIF1_CLK_B), GPIO_FN(TS_SCK_D),
+ GPIO_FN(BPFCLK_C), GPIO_FN(MSIOF0_RXD), GPIO_FN(SCIF5_RXD),
+ GPIO_FN(I2C2_SCL_C), GPIO_FN(DU1_DR2), GPIO_FN(RIF1_D0_B),
+ GPIO_FN(TS_SDEN_D), GPIO_FN(FMCLK_C), GPIO_FN(RDS_CLK),
+
+ /*
+ * From IPSR9 to IPSR10 have been removed because they does not use.
+ */
+
+ /* IPSR11 */
+ GPIO_FN(SSI_WS5), GPIO_FN(SCIFA3_RXD), GPIO_FN(I2C3_SCL_C),
+ GPIO_FN(DU1_DOTCLKOUT0), GPIO_FN(CAN_DEBUGOUT11), GPIO_FN(SSI_SDATA5),
+ GPIO_FN(SCIFA3_TXD), GPIO_FN(I2C3_SDA_C), GPIO_FN(DU1_DOTCLKOUT1),
+ GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6), GPIO_FN(SCIFA1_SCK_B),
+ GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(CAN_DEBUGOUT13),
+ GPIO_FN(SSI_WS6), GPIO_FN(SCIFA1_RXD_B), GPIO_FN(I2C4_SCL_C),
+ GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(CAN_DEBUGOUT14),
+ GPIO_FN(SSI_SDATA6), GPIO_FN(SCIFA1_TXD_B), GPIO_FN(I2C4_SDA_C),
+ GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), GPIO_FN(CAN_DEBUGOUT15),
+ GPIO_FN(SSI_SCK78), GPIO_FN(SCIFA2_SCK_B), GPIO_FN(IIC0_SDA_C),
+ GPIO_FN(DU1_DISP), GPIO_FN(SSI_WS78), GPIO_FN(SCIFA2_RXD_B),
+ GPIO_FN(IIC0_SCL_C), GPIO_FN(DU1_CDE), GPIO_FN(SSI_SDATA7),
+ GPIO_FN(SCIFA2_TXD_B), GPIO_FN(IRQ8), GPIO_FN(AUDIO_CLKA_D),
+ GPIO_FN(CAN_CLK_D), GPIO_FN(PCMOE_N), GPIO_FN(SSI_SCK0129),
+ GPIO_FN(MSIOF1_RXD_B), GPIO_FN(SCIF5_RXD_D), GPIO_FN(ADIDATA_B),
+ GPIO_FN(AD_DI_B), GPIO_FN(PCMWE_N), GPIO_FN(SSI_WS0129),
+ GPIO_FN(MSIOF1_TXD_B), GPIO_FN(SCIF5_TXD_D), GPIO_FN(ADICS_SAMP_B),
+ GPIO_FN(AD_DO_B), GPIO_FN(SSI_SDATA0), GPIO_FN(MSIOF1_SCK_B),
+ GPIO_FN(PWM0_B), GPIO_FN(ADICLK_B), GPIO_FN(AD_CLK_B),
+
+ /*
+ * From IPSR12 to IPSR13 have been removed because they does not use.
+ */
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+ { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+ GP_0_31_FN, FN_IP2_17_16,
+ GP_0_30_FN, FN_IP2_15_14,
+ GP_0_29_FN, FN_IP2_13_12,
+ GP_0_28_FN, FN_IP2_11_10,
+ GP_0_27_FN, FN_IP2_9_8,
+ GP_0_26_FN, FN_IP2_7_6,
+ GP_0_25_FN, FN_IP2_5_4,
+ GP_0_24_FN, FN_IP2_3_2,
+ GP_0_23_FN, FN_IP2_1_0,
+ GP_0_22_FN, FN_IP1_31_30,
+ GP_0_21_FN, FN_IP1_29_28,
+ GP_0_20_FN, FN_IP1_27,
+ GP_0_19_FN, FN_IP1_26,
+ GP_0_18_FN, FN_A2,
+ GP_0_17_FN, FN_IP1_24,
+ GP_0_16_FN, FN_IP1_23_22,
+ GP_0_15_FN, FN_IP1_21_20,
+ GP_0_14_FN, FN_IP1_19_18,
+ GP_0_13_FN, FN_IP1_17_15,
+ GP_0_12_FN, FN_IP1_14_13,
+ GP_0_11_FN, FN_IP1_12_11,
+ GP_0_10_FN, FN_IP1_10_8,
+ GP_0_9_FN, FN_IP1_7_6,
+ GP_0_8_FN, FN_IP1_5_4,
+ GP_0_7_FN, FN_IP1_3_2,
+ GP_0_6_FN, FN_IP1_1_0,
+ GP_0_5_FN, FN_IP0_31_30,
+ GP_0_4_FN, FN_IP0_29_28,
+ GP_0_3_FN, FN_IP0_27_26,
+ GP_0_2_FN, FN_IP0_25,
+ GP_0_1_FN, FN_IP0_24,
+ GP_0_0_FN, FN_IP0_23_22, }
+ },
+ { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_1_25_FN, FN_DACK0,
+ GP_1_24_FN, FN_IP7_31,
+ GP_1_23_FN, FN_IP4_1_0,
+ GP_1_22_FN, FN_WE1_N,
+ GP_1_21_FN, FN_WE0_N,
+ GP_1_20_FN, FN_IP3_31,
+ GP_1_19_FN, FN_IP3_30,
+ GP_1_18_FN, FN_IP3_29_27,
+ GP_1_17_FN, FN_IP3_26_24,
+ GP_1_16_FN, FN_IP3_23_21,
+ GP_1_15_FN, FN_IP3_20_18,
+ GP_1_14_FN, FN_IP3_17_15,
+ GP_1_13_FN, FN_IP3_14_13,
+ GP_1_12_FN, FN_IP3_12,
+ GP_1_11_FN, FN_IP3_11,
+ GP_1_10_FN, FN_IP3_10,
+ GP_1_9_FN, FN_IP3_9_8,
+ GP_1_8_FN, FN_IP3_7_6,
+ GP_1_7_FN, FN_IP3_5_4,
+ GP_1_6_FN, FN_IP3_3_2,
+ GP_1_5_FN, FN_IP3_1_0,
+ GP_1_4_FN, FN_IP2_31_30,
+ GP_1_3_FN, FN_IP2_29_27,
+ GP_1_2_FN, FN_IP2_26_24,
+ GP_1_1_FN, FN_IP2_23_21,
+ GP_1_0_FN, FN_IP2_20_18, }
+ },
+ { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+ GP_2_31_FN, FN_IP6_7_6,
+ GP_2_30_FN, FN_IP6_5_4,
+ GP_2_29_FN, FN_IP6_3_2,
+ GP_2_28_FN, FN_IP6_1_0,
+ GP_2_27_FN, FN_IP5_31_30,
+ GP_2_26_FN, FN_IP5_29_28,
+ GP_2_25_FN, FN_IP5_27_26,
+ GP_2_24_FN, FN_IP5_25_24,
+ GP_2_23_FN, FN_IP5_23_22,
+ GP_2_22_FN, FN_IP5_21_20,
+ GP_2_21_FN, FN_IP5_19_18,
+ GP_2_20_FN, FN_IP5_17_16,
+ GP_2_19_FN, FN_IP5_15_14,
+ GP_2_18_FN, FN_IP5_13_12,
+ GP_2_17_FN, FN_IP5_11_9,
+ GP_2_16_FN, FN_IP5_8_6,
+ GP_2_15_FN, FN_IP5_5_4,
+ GP_2_14_FN, FN_IP5_3_2,
+ GP_2_13_FN, FN_IP5_1_0,
+ GP_2_12_FN, FN_IP4_31_30,
+ GP_2_11_FN, FN_IP4_29_28,
+ GP_2_10_FN, FN_IP4_27_26,
+ GP_2_9_FN, FN_IP4_25_23,
+ GP_2_8_FN, FN_IP4_22_20,
+ GP_2_7_FN, FN_IP4_19_18,
+ GP_2_6_FN, FN_IP4_17_16,
+ GP_2_5_FN, FN_IP4_15_14,
+ GP_2_4_FN, FN_IP4_13_12,
+ GP_2_3_FN, FN_IP4_11_10,
+ GP_2_2_FN, FN_IP4_9_8,
+ GP_2_1_FN, FN_IP4_7_5,
+ GP_2_0_FN, FN_IP4_4_2 }
+ },
+ { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+ GP_3_31_FN, FN_IP8_22_20,
+ GP_3_30_FN, FN_IP8_19_17,
+ GP_3_29_FN, FN_IP8_16_15,
+ GP_3_28_FN, FN_IP8_14_12,
+ GP_3_27_FN, FN_IP8_11_9,
+ GP_3_26_FN, FN_IP8_8_6,
+ GP_3_25_FN, FN_IP8_5_3,
+ GP_3_24_FN, FN_IP8_2_0,
+ GP_3_23_FN, FN_IP7_29_27,
+ GP_3_22_FN, FN_IP7_26_24,
+ GP_3_21_FN, FN_IP7_23_21,
+ GP_3_20_FN, FN_IP7_20_18,
+ GP_3_19_FN, FN_IP7_17_15,
+ GP_3_18_FN, FN_IP7_14_12,
+ GP_3_17_FN, FN_IP7_11_9,
+ GP_3_16_FN, FN_IP7_8_6,
+ GP_3_15_FN, FN_IP7_5_3,
+ GP_3_14_FN, FN_IP7_2_0,
+ GP_3_13_FN, FN_IP6_31_29,
+ GP_3_12_FN, FN_IP6_28_26,
+ GP_3_11_FN, FN_IP6_25_23,
+ GP_3_10_FN, FN_IP6_22_20,
+ GP_3_9_FN, FN_IP6_19_17,
+ GP_3_8_FN, FN_IP6_16,
+ GP_3_7_FN, FN_IP6_15,
+ GP_3_6_FN, FN_IP6_14,
+ GP_3_5_FN, FN_IP6_13,
+ GP_3_4_FN, FN_IP6_12,
+ GP_3_3_FN, FN_IP6_11,
+ GP_3_2_FN, FN_IP6_10,
+ GP_3_1_FN, FN_IP6_9,
+ GP_3_0_FN, FN_IP6_8 }
+ },
+ { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+ GP_4_31_FN, FN_IP11_17_16,
+ GP_4_30_FN, FN_IP11_15_14,
+ GP_4_29_FN, FN_IP11_13_11,
+ GP_4_28_FN, FN_IP11_10_8,
+ GP_4_27_FN, FN_IP11_7_6,
+ GP_4_26_FN, FN_IP11_5_3,
+ GP_4_25_FN, FN_IP11_2_0,
+ GP_4_24_FN, FN_IP10_31_30,
+ GP_4_23_FN, FN_IP10_29_27,
+ GP_4_22_FN, FN_IP10_26_24,
+ GP_4_21_FN, FN_IP10_23_21,
+ GP_4_20_FN, FN_IP10_20_18,
+ GP_4_19_FN, FN_IP10_17_15,
+ GP_4_18_FN, FN_IP10_14_12,
+ GP_4_17_FN, FN_IP10_11_9,
+ GP_4_16_FN, FN_IP10_8_6,
+ GP_4_15_FN, FN_IP10_5_3,
+ GP_4_14_FN, FN_IP10_2_0,
+ GP_4_13_FN, FN_IP9_30_28,
+ GP_4_12_FN, FN_IP9_27_25,
+ GP_4_11_FN, FN_IP9_24_22,
+ GP_4_10_FN, FN_IP9_21_19,
+ GP_4_9_FN, FN_IP9_18_17,
+ GP_4_8_FN, FN_IP9_16_15,
+ GP_4_7_FN, FN_IP9_14_12,
+ GP_4_6_FN, FN_IP9_11_9,
+ GP_4_5_FN, FN_IP9_8_6,
+ GP_4_4_FN, FN_IP9_5_3,
+ GP_4_3_FN, FN_IP9_2_0,
+ GP_4_2_FN, FN_IP8_31_29,
+ GP_4_1_FN, FN_IP8_28_26,
+ GP_4_0_FN, FN_IP8_25_23 }
+ },
+ { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_5_27_FN, FN_USB1_OVC,
+ GP_5_26_FN, FN_USB1_PWEN,
+ GP_5_25_FN, FN_USB0_OVC,
+ GP_5_24_FN, FN_USB0_PWEN,
+ GP_5_23_FN, FN_IP13_26_24,
+ GP_5_22_FN, FN_IP13_23_21,
+ GP_5_21_FN, FN_IP13_20_18,
+ GP_5_20_FN, FN_IP13_17_15,
+ GP_5_19_FN, FN_IP13_14_12,
+ GP_5_18_FN, FN_IP13_11_9,
+ GP_5_17_FN, FN_IP13_8_6,
+ GP_5_16_FN, FN_IP13_5_3,
+ GP_5_15_FN, FN_IP13_2_0,
+ GP_5_14_FN, FN_IP12_29_27,
+ GP_5_13_FN, FN_IP12_26_24,
+ GP_5_12_FN, FN_IP12_23_21,
+ GP_5_11_FN, FN_IP12_20_18,
+ GP_5_10_FN, FN_IP12_17_15,
+ GP_5_9_FN, FN_IP12_14_13,
+ GP_5_8_FN, FN_IP12_12_11,
+ GP_5_7_FN, FN_IP12_10_9,
+ GP_5_6_FN, FN_IP12_8_6,
+ GP_5_5_FN, FN_IP12_5_3,
+ GP_5_4_FN, FN_IP12_2_0,
+ GP_5_3_FN, FN_IP11_29_27,
+ GP_5_2_FN, FN_IP11_26_24,
+ GP_5_1_FN, FN_IP11_23_21,
+ GP_5_0_FN, FN_IP11_20_18 }
+ },
+ { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_6_25_FN, FN_IP0_21_20,
+ GP_6_24_FN, FN_IP0_19_18,
+ GP_6_23_FN, FN_IP0_17,
+ GP_6_22_FN, FN_IP0_16,
+ GP_6_21_FN, FN_IP0_15,
+ GP_6_20_FN, FN_IP0_14,
+ GP_6_19_FN, FN_IP0_13,
+ GP_6_18_FN, FN_IP0_12,
+ GP_6_17_FN, FN_IP0_11,
+ GP_6_16_FN, FN_IP0_10,
+ GP_6_15_FN, FN_IP0_9_8,
+ GP_6_14_FN, FN_IP0_0,
+ GP_6_13_FN, FN_SD1_DATA3,
+ GP_6_12_FN, FN_SD1_DATA2,
+ GP_6_11_FN, FN_SD1_DATA1,
+ GP_6_10_FN, FN_SD1_DATA0,
+ GP_6_9_FN, FN_SD1_CMD,
+ GP_6_8_FN, FN_SD1_CLK,
+ GP_6_7_FN, FN_SD0_WP,
+ GP_6_6_FN, FN_SD0_CD,
+ GP_6_5_FN, FN_SD0_DATA3,
+ GP_6_4_FN, FN_SD0_DATA2,
+ GP_6_3_FN, FN_SD0_DATA1,
+ GP_6_2_FN, FN_SD0_DATA0,
+ GP_6_1_FN, FN_SD0_CMD,
+ GP_6_0_FN, FN_SD0_CLK }
+ },
+
+ /*
+ * From IPSR0 to IPSR5 have been removed because they does not use.
+ */
+
+ { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
+ 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
+ 2, 2) {
+ /* IP6_31_29 [3] */
+ FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D,
+ FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0,
+ /* IP6_28_26 [3] */
+ FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
+ FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
+ /* IP6_25_23 [3] */
+ FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
+ FN_AVB_COL, 0, 0, 0,
+ /* IP6_22_20 [3] */
+ FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
+ FN_AVB_RX_ER, 0, 0, 0,
+ /* IP6_19_17 [3] */
+ FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
+ FN_AVB_RXD7, 0, 0, 0,
+ /* IP6_16 [1] */
+ FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
+ /* IP6_15 [1] */
+ FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
+ /* IP6_14 [1] */
+ FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
+ /* IP6_13 [1] */
+ FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
+ /* IP6_12 [1] */
+ FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
+ /* IP6_11 [1] */
+ FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
+ /* IP6_10 [1] */
+ FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
+ /* IP6_9 [1] */
+ FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
+ /* IP6_8 [1] */
+ FN_VI0_CLK, FN_AVB_RX_CLK,
+ /* IP6_7_6 [2] */
+ FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0,
+ /* IP6_5_4 [2] */
+ FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,
+ /* IP6_3_2 [2] */
+ FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
+ /* IP6_1_0 [2] */
+ FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
+ 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+ /* IP7_31 [1] */
+ FN_DREQ0_N, FN_SCIFB1_RXD,
+ /* IP7_30 [1] */
+ 0, 0,
+ /* IP7_29_27 [3] */
+ FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
+ FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
+ /* IP7_26_24 [3] */
+ FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
+ FN_SSI_SCK6_B, 0, 0, 0,
+ /* IP7_23_21 [3] */
+ FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D,
+ FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
+ /* IP7_20_18 [3] */
+ FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D,
+ FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
+ /* IP7_17_15 [3] */
+ FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
+ FN_SSI_SCK5_B, 0, 0, 0,
+ /* IP7_14_12 [3] */
+ FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
+ FN_AVB_TXD4, FN_ADICHS2, 0, 0,
+ /* IP7_11_9 [3] */
+ FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
+ FN_AVB_TXD3, FN_ADICHS1, 0, 0,
+ /* IP7_8_6 [3] */
+ FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
+ FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0,
+ /* IP7_5_3 [3] */
+ FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
+ FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0,
+ /* IP7_2_0 [3] */
+ FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D,
+ FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, }
+ },
+ { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
+ 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
+ /* IP8_31_29 [3] */
+ FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
+ FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
+ /* IP8_28_26 [3] */
+ FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
+ FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0,
+ /* IP8_25_23 [3] */
+ FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
+ FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
+ /* IP8_22_20 [3] */
+ FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
+ FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
+ /* IP8_19_17 [3] */
+ FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
+ FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
+ /* IP8_16_15 [2] */
+ FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
+ /* IP8_14_12 [3] */
+ FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
+ FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
+ /* IP8_11_9 [3] */
+ FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
+ FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
+ /* IP8_8_6 [3] */
+ FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
+ FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
+ /* IP8_5_3 [3] */
+ FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
+ FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
+ /* IP8_2_0 [3] */
+ FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
+ FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
+ },
+
+ /*
+ * From IPSR9 to IPSR10 have been removed because they does not use.
+ */
+
+ { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
+ 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
+ /* IP11_31_30 [2] */
+ 0, 0, 0, 0,
+ /* IP11_29_27 [3] */
+ FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
+ FN_AD_CLK_B, 0, 0, 0,
+ /* IP11_26_24 [3] */
+ FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
+ FN_AD_DO_B, 0, 0, 0,
+ /* IP11_23_21 [3] */
+ FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
+ FN_AD_DI_B, FN_PCMWE_N, 0, 0,
+ /* IP11_20_18 [3] */
+ FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
+ FN_CAN_CLK_D, FN_PCMOE_N, 0, 0,
+ /* IP11_17_16 [2] */
+ FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE,
+ /* IP11_15_14 [2] */
+ FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP,
+ /* IP11_13_11 [3] */
+ FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
+ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0,
+ /* IP11_10_8 [3] */
+ FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
+ FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0,
+ /* IP11_7_6 [2] */
+ FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
+ FN_CAN_DEBUGOUT13,
+ /* IP11_5_3 [3] */
+ FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
+ FN_CAN_DEBUGOUT12, 0, 0, 0,
+ /* IP11_2_0 [3] */
+ FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
+ FN_CAN_DEBUGOUT11, 0, 0, 0, }
+ },
+
+ /*
+ * From IPSR12 to IPSR13 have been removed because they does not use.
+ */
+
+ { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
+ 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3,
+ 2, 1) {
+ /* SEL_ADG [2] */
+ FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
+ /* SEL_ADI [1] */
+ FN_SEL_ADI_0, FN_SEL_ADI_1,
+ /* SEL_CAN [2] */
+ FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
+ /* SEL_DARC [3] */
+ FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
+ FN_SEL_DARC_4, 0, 0, 0,
+ /* SEL_DR0 [1] */
+ FN_SEL_DR0_0, FN_SEL_DR0_1,
+ /* SEL_DR1 [1] */
+ FN_SEL_DR1_0, FN_SEL_DR1_1,
+ /* SEL_DR2 [1] */
+ FN_SEL_DR2_0, FN_SEL_DR2_1,
+ /* SEL_DR3 [1] */
+ FN_SEL_DR3_0, FN_SEL_DR3_1,
+ /* SEL_ETH [1] */
+ FN_SEL_ETH_0, FN_SEL_ETH_1,
+ /* SLE_FSN [1] */
+ FN_SEL_FSN_0, FN_SEL_FSN_1,
+ /* SEL_IC200 [3] */
+ FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
+ FN_SEL_I2C00_4, 0, 0, 0,
+ /* SEL_I2C01 [3] */
+ FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
+ FN_SEL_I2C01_4, 0, 0, 0,
+ /* SEL_I2C02 [3] */
+ FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
+ FN_SEL_I2C02_4, 0, 0, 0,
+ /* SEL_I2C03 [3] */
+ FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
+ FN_SEL_I2C03_4, 0, 0, 0,
+ /* SEL_I2C04 [3] */
+ FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
+ FN_SEL_I2C04_4, 0, 0, 0,
+ /* SEL_IIC00 [2] */
+ FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3,
+ /* SEL_AVB [1] */
+ FN_SEL_AVB_0, FN_SEL_AVB_1, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
+ 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
+ 2, 2, 2, 1, 1, 2) {
+ /* SEL_IEB [2] */
+ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
+ /* SEL_IIC0 [2] */
+ FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
+ /* SEL_LBS [1] */
+ FN_SEL_LBS_0, FN_SEL_LBS_1,
+ /* SEL_MSI1 [1] */
+ FN_SEL_MSI1_0, FN_SEL_MSI1_1,
+ /* SEL_MSI2 [1] */
+ FN_SEL_MSI2_0, FN_SEL_MSI2_1,
+ /* SEL_RAD [1] */
+ FN_SEL_RAD_0, FN_SEL_RAD_1,
+ /* SEL_RCN [1] */
+ FN_SEL_RCN_0, FN_SEL_RCN_1,
+ /* SEL_RSP [1] */
+ FN_SEL_RSP_0, FN_SEL_RSP_1,
+ /* SEL_SCIFA0 [2] */
+ FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
+ FN_SEL_SCIFA0_3,
+ /* SEL_SCIFA1 [2] */
+ FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
+ /* SEL_SCIFA2 [1] */
+ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+ /* SEL_SCIFA3 [1] */
+ FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
+ /* SEL_SCIFA4 [2] */
+ FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
+ FN_SEL_SCIFA4_3,
+ /* SEL_SCIFA5 [2] */
+ FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
+ FN_SEL_SCIFA5_3,
+ /* SEL_SPDM [1] */
+ FN_SEL_SPDM_0, FN_SEL_SPDM_1,
+ /* SEL_TMU [1] */
+ FN_SEL_TMU_0, FN_SEL_TMU_1,
+ /* SEL_TSIF0 [2] */
+ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+ /* SEL_CAN0 [2] */
+ FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+ /* SEL_CAN1 [2] */
+ FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+ /* SEL_HSCIF0 [1] */
+ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
+ /* SEL_HSCIF1 [1] */
+ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+ /* SEL_RDS [2] */
+ FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, }
+ },
+ { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
+ 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
+ /* SEL_SCIF0 [2] */
+ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+ /* SEL_SCIF1 [2] */
+ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
+ /* SEL_SCIF2 [2] */
+ FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
+ /* SEL_SCIF3 [1] */
+ FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
+ /* SEL_SCIF4 [3] */
+ FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
+ FN_SEL_SCIF4_4, 0, 0, 0,
+ /* SEL_SCIF5 [2] */
+ FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
+ /* SEL_SSI1 [1] */
+ FN_SEL_SSI1_0, FN_SEL_SSI1_1,
+ /* SEL_SSI2 [1] */
+ FN_SEL_SSI2_0, FN_SEL_SSI2_1,
+ /* SEL_SSI4 [1] */
+ FN_SEL_SSI4_0, FN_SEL_SSI4_1,
+ /* SEL_SSI5 [1] */
+ FN_SEL_SSI5_0, FN_SEL_SSI5_1,
+ /* SEL_SSI6 [1] */
+ FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+ /* SEL_SSI7 [1] */
+ FN_SEL_SSI7_0, FN_SEL_SSI7_1,
+ /* SEL_SSI8 [1] */
+ FN_SEL_SSI8_0, FN_SEL_SSI8_1,
+ /* SEL_SSI9 [1] */
+ FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+ /* RESEVED [1] */
+ 0, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* RESEVED [1] */
+ 0, 0,
+ /* RESEVED [1] */
+ 0, 0, }
+ },
+ { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
+ { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_1_25_IN, GP_1_25_OUT,
+ GP_1_24_IN, GP_1_24_OUT,
+ GP_1_23_IN, GP_1_23_OUT,
+ GP_1_22_IN, GP_1_22_OUT,
+ GP_1_21_IN, GP_1_21_OUT,
+ GP_1_20_IN, GP_1_20_OUT,
+ GP_1_19_IN, GP_1_19_OUT,
+ GP_1_18_IN, GP_1_18_OUT,
+ GP_1_17_IN, GP_1_17_OUT,
+ GP_1_16_IN, GP_1_16_OUT,
+ GP_1_15_IN, GP_1_15_OUT,
+ GP_1_14_IN, GP_1_14_OUT,
+ GP_1_13_IN, GP_1_13_OUT,
+ GP_1_12_IN, GP_1_12_OUT,
+ GP_1_11_IN, GP_1_11_OUT,
+ GP_1_10_IN, GP_1_10_OUT,
+ GP_1_9_IN, GP_1_9_OUT,
+ GP_1_8_IN, GP_1_8_OUT,
+ GP_1_7_IN, GP_1_7_OUT,
+ GP_1_6_IN, GP_1_6_OUT,
+ GP_1_5_IN, GP_1_5_OUT,
+ GP_1_4_IN, GP_1_4_OUT,
+ GP_1_3_IN, GP_1_3_OUT,
+ GP_1_2_IN, GP_1_2_OUT,
+ GP_1_1_IN, GP_1_1_OUT,
+ GP_1_0_IN, GP_1_0_OUT, }
+ },
+ { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
+ { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
+ { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
+ { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_5_27_IN, GP_5_27_OUT,
+ GP_5_26_IN, GP_5_26_OUT,
+ GP_5_25_IN, GP_5_25_OUT,
+ GP_5_24_IN, GP_5_24_OUT,
+ GP_5_23_IN, GP_5_23_OUT,
+ GP_5_22_IN, GP_5_22_OUT,
+ GP_5_21_IN, GP_5_21_OUT,
+ GP_5_20_IN, GP_5_20_OUT,
+ GP_5_19_IN, GP_5_19_OUT,
+ GP_5_18_IN, GP_5_18_OUT,
+ GP_5_17_IN, GP_5_17_OUT,
+ GP_5_16_IN, GP_5_16_OUT,
+ GP_5_15_IN, GP_5_15_OUT,
+ GP_5_14_IN, GP_5_14_OUT,
+ GP_5_13_IN, GP_5_13_OUT,
+ GP_5_12_IN, GP_5_12_OUT,
+ GP_5_11_IN, GP_5_11_OUT,
+ GP_5_10_IN, GP_5_10_OUT,
+ GP_5_9_IN, GP_5_9_OUT,
+ GP_5_8_IN, GP_5_8_OUT,
+ GP_5_7_IN, GP_5_7_OUT,
+ GP_5_6_IN, GP_5_6_OUT,
+ GP_5_5_IN, GP_5_5_OUT,
+ GP_5_4_IN, GP_5_4_OUT,
+ GP_5_3_IN, GP_5_3_OUT,
+ GP_5_2_IN, GP_5_2_OUT,
+ GP_5_1_IN, GP_5_1_OUT,
+ GP_5_0_IN, GP_5_0_OUT, }
+ },
+ { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ GP_6_25_IN, GP_6_25_OUT,
+ GP_6_24_IN, GP_6_24_OUT,
+ GP_6_23_IN, GP_6_23_OUT,
+ GP_6_22_IN, GP_6_22_OUT,
+ GP_6_21_IN, GP_6_21_OUT,
+ GP_6_20_IN, GP_6_20_OUT,
+ GP_6_19_IN, GP_6_19_OUT,
+ GP_6_18_IN, GP_6_18_OUT,
+ GP_6_17_IN, GP_6_17_OUT,
+ GP_6_16_IN, GP_6_16_OUT,
+ GP_6_15_IN, GP_6_15_OUT,
+ GP_6_14_IN, GP_6_14_OUT,
+ GP_6_13_IN, GP_6_13_OUT,
+ GP_6_12_IN, GP_6_12_OUT,
+ GP_6_11_IN, GP_6_11_OUT,
+ GP_6_10_IN, GP_6_10_OUT,
+ GP_6_9_IN, GP_6_9_OUT,
+ GP_6_8_IN, GP_6_8_OUT,
+ GP_6_7_IN, GP_6_7_OUT,
+ GP_6_6_IN, GP_6_6_OUT,
+ GP_6_5_IN, GP_6_5_OUT,
+ GP_6_4_IN, GP_6_4_OUT,
+ GP_6_3_IN, GP_6_3_OUT,
+ GP_6_2_IN, GP_6_2_OUT,
+ GP_6_1_IN, GP_6_1_OUT,
+ GP_6_0_IN, GP_6_0_OUT, }
+ },
+ { },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+ { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
+ { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
+ 0, 0, 0, 0,
+ 0, 0, GP_1_25_DATA, GP_1_24_DATA,
+ GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
+ GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
+ GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
+ GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
+ GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
+ GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
+ },
+ { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
+ { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
+ { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
+ { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) {
+ 0, 0, 0, 0,
+ GP_5_27_DATA, GP_5_26_DATA, GP_5_25_DATA, GP_5_24_DATA,
+ GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA,
+ GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA,
+ GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,
+ GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
+ GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
+ GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
+ },
+ { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) {
+ 0, 0, 0, 0,
+ 0, 0, GP_6_25_DATA, GP_6_24_DATA,
+ GP_6_23_DATA, GP_6_22_DATA, GP_6_21_DATA, GP_6_20_DATA,
+ GP_6_19_DATA, GP_6_18_DATA, GP_6_17_DATA, GP_6_16_DATA,
+ GP_6_15_DATA, GP_6_14_DATA, GP_6_13_DATA, GP_6_12_DATA,
+ GP_6_11_DATA, GP_6_10_DATA, GP_6_9_DATA, GP_6_8_DATA,
+ GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
+ GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
+ },
+ { },
+};
+
+static struct pinmux_info r8a7794_pinmux_info = {
+ .name = "r8a7794_pfc",
+
+ .unlock_reg = 0xe6060000, /* PMMR */
+
+ .reserved_id = PINMUX_RESERVED,
+ .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+ .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+ .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+ .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .first_gpio = GPIO_GP_0_0,
+ .last_gpio = GPIO_FN_AD_CLK_B,
+
+ .gpios = pinmux_gpios,
+ .cfg_regs = pinmux_config_regs,
+ .data_regs = pinmux_data_regs,
+
+ .gpio_data = pinmux_data,
+ .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void r8a7794_pinmux_init(void)
+{
+ register_pinmux(&r8a7794_pinmux_info);
+}
obj-y += board.o
obj-y += clock.o
obj-y += pinmux.o
+obj-$(CONFIG_SUN4I) += clock_sun4i.o
+obj-$(CONFIG_SUN5I) += clock_sun4i.o
obj-$(CONFIG_SUN7I) += clock_sun4i.o
ifndef CONFIG_SPL_BUILD
endif
ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SUN4I) += dram.o
+obj-$(CONFIG_SUN5I) += dram.o
obj-$(CONFIG_SUN7I) += dram.o
ifdef CONFIG_SPL_FEL
obj-y += start.o
*/
#include <common.h>
+#include <i2c.h>
#include <netdev.h>
#include <miiphy.h>
#include <serial.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
+#include <linux/compiler.h>
+
#ifdef CONFIG_SPL_BUILD
/* Pointer to the global data structure for SPL */
DECLARE_GLOBAL_DATA_PTR;
int gpio_init(void)
{
+#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
+ sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
+ sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
+#else
+#error Unsupported console port number. Please fix pin mux settings in board.c
+#endif
return 0;
}
void reset_cpu(ulong addr)
{
+ static const struct sunxi_wdog *wdog =
+ &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
+
+ /* Set the watchdog for its shortest interval (.5s) and wait */
+ writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
+ writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
+
+ while (1) {
+ /* sun5i sometimes gets stuck without this */
+ writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
+ }
}
/* do some early init */
clock_init();
timer_init();
gpio_init();
+ i2c_init_board();
#ifdef CONFIG_SPL_BUILD
gd = &gdata;
preloader_console_init();
+#ifdef CONFIG_SPL_I2C_SUPPORT
+ /* Needed early by sunxi_board_init if PMU is enabled */
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
sunxi_board_init();
#endif
}
*/
int cpu_eth_init(bd_t *bis)
{
- int rc;
+ __maybe_unused int rc;
+
+#ifdef CONFIG_SUNXI_EMAC
+ rc = sunxi_emac_initialize(bis);
+ if (rc < 0) {
+ printf("sunxi: failed to initialize emac\n");
+ return rc;
+ }
+#endif
#ifdef CONFIG_SUNXI_GMAC
rc = sunxi_gmac_initialize(bis);
CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
&ccm->cpu_ahb_apb0_cfg);
#ifdef CONFIG_SUN7I
- writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
- &ccm->ahb_gate0);
+ setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
#endif
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
}
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
+#ifdef CONFIG_SUN4I
+ puts("CPU: Allwinner A10 (SUN4I)\n");
+#elif defined CONFIG_SUN5I
+ u32 val = readl(SUNXI_SID_BASE + 0x08);
+ switch ((val >> 12) & 0xf) {
+ case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break;
+ case 3: puts("CPU: Allwinner A13 (SUN5I)\n"); break;
+ case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break;
+ default: puts("CPU: Allwinner A1X (SUN5I)\n");
+ }
+#elif defined CONFIG_SUN7I
puts("CPU: Allwinner A20 (SUN7I)\n");
+#else
+#warning Please update cpu_info.c with correct CPU information
+ puts("CPU: SUNXI Family\n");
+#endif
return 0;
}
#endif
struct sunxi_dram_reg *dram =
(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
- clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
- udelay(2);
- setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+#ifdef CONFIG_SUN4I
+ struct sunxi_timer_reg *timer =
+ (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
+ u32 reg_val;
+
+ writel(0, &timer->cpu_cfg);
+ reg_val = readl(&timer->cpu_cfg);
+
+ if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
+ CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
+ setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+ udelay(2);
+ clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
+ } else
+#endif
+ {
+ clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
+ udelay(2);
+ setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+ }
}
static void mctl_set_drive(void)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+#ifdef CONFIG_SUN7I
clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
+#else
+ clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
+#endif
DRAM_MCR_MODE_EN(0x3) |
0xffc);
}
}
static u32 hpcr_value[32] = {
+#ifdef CONFIG_SUN5I
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0x1031, 0x1031, 0x0735, 0x1035,
+ 0x1035, 0x0731, 0x1031, 0,
+ 0x0301, 0x0301, 0x0301, 0x0301,
+ 0x0301, 0x0301, 0x0301, 0
+#endif
+#ifdef CONFIG_SUN4I
+ 0x0301, 0x0301, 0x0301, 0x0301,
+ 0x0301, 0x0301, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0x1031, 0x1031, 0x0735, 0x5031,
+ 0x1035, 0x0731, 0x1031, 0x0735,
+ 0x1035, 0x1031, 0x0731, 0x1035,
+ 0x1031, 0x0301, 0x0301, 0x0731
+#endif
#ifdef CONFIG_SUN7I
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0x0301, 0x0301,
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
#endif
+#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
/* setup MBUS clock */
reg_val = CCM_MBUS_CTRL_GATE |
+#ifdef CONFIG_SUN7I
CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
+#else /* defined(CONFIG_SUN5I) */
+ CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
+ CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
+ CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
+#endif
writel(reg_val, &ccm->mbus_clk_cfg);
+#endif
/*
* open DRAMC AHB & DLL register clock
* close it first
*/
+#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
+#else
+ clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
+#endif
udelay(22);
/* then open it */
+#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
+#else
+ setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
+#endif
udelay(22);
}
else
clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
#endif
+#ifdef CONFIG_SUN4I
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ if (on)
+ setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
+ else
+ clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
+#endif
}
static const u16 tRFC_table[2][6] = {
/* setup DRAM relative clock */
mctl_setup_dram_clock(para->clock);
+#ifdef CONFIG_SUN5I
+ /* Disable any pad power save control */
+ writel(0, &dram->ppwrsctl);
+#endif
+
/* reset external DRAM */
+#ifndef CONFIG_SUN7I
+ mctl_ddr3_reset();
+#endif
mctl_set_drive();
/* dram clock off */
dramc_clock_output_en(0);
+#ifdef CONFIG_SUN4I
+ /* select dram controller 1 */
+ writel(DRAM_CSEL_MAGIC, &dram->csel);
+#endif
+
mctl_itm_disable();
mctl_enable_dll0(para->tpr3);
mctl_ddr3_reset();
else
setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+#else
+ /* dram clock on */
+ dramc_clock_output_en(1);
#endif
udelay(1);
mctl_enable_dllx(para->tpr3);
+#ifdef CONFIG_SUN4I
+ /* set odt impedance divide ratio */
+ reg_val = ((para->zq) >> 8) & 0xfffff;
+ reg_val |= ((para->zq) & 0xff) << 20;
+ reg_val |= (para->zq) & 0xf0000000;
+ writel(reg_val, &dram->zqcr0);
+#endif
+
+#ifdef CONFIG_SUN4I
+ /* set I/O configure register */
+ reg_val = 0x00cc0000;
+ reg_val |= (para->odt_en) & 0x3;
+ reg_val |= ((para->odt_en) & 0x3) << 30;
+ writel(reg_val, &dram->iocr);
+#endif
+
/* set refresh period */
dramc_set_autorefresh_cycle(para->clock, para->type - 2, density);
*(.data*)
}
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
. = ALIGN(4);
. = .;
.text :
{
__start = .;
+ *(.vectors)
arch/arm/cpu/armv7/start.o (.text)
*(.text*)
} > .sram
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ } > .sram
+
. = ALIGN(4);
__image_copy_end = .;
_end = .;
/* ECC is enabled when memory is in 16bit mode and it is enabled */
if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) &&
(width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) {
- puts("Memory: ECC enabled\n");
+ puts("ECC enabled ");
/*
* Clear the first 1MB because it is not initialized from
* first stage bootloader. To get ECC to work all memory has
*/
memset((void *)0, 0, 1 * 1024 * 1024);
} else {
- puts("Memory: ECC disabled\n");
+ puts("ECC disabled ");
}
}
#define OMAP_GPIO_SETDATAOUT 0x0194
/* Control Device Register */
+
+ /* Control Device Register */
+#define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F
+#define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8
+#define MREQPRIO_1_DSS_MASK 0xFFFFFF8F
+
struct ctrl_dev {
unsigned int deviceid; /* offset 0x00 */
unsigned int resv1[7];
unsigned int macid1h; /* offset 0x3c */
unsigned int resv4[4];
unsigned int miisel; /* offset 0x50 */
- unsigned int resv5[106];
+ unsigned int resv5[7];
+ unsigned int mreqprio_0; /* offset 0x70 */
+ unsigned int mreqprio_1; /* offset 0x74 */
+ unsigned int resv6[97];
unsigned int efuse_sma; /* offset 0x1FC */
};
+/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
+#define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0
+#define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0
+#define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800
+
+struct l3f_cfg_bwlimiter {
+ u32 padding0[2];
+ u32 modena_init0_bw_fractional;
+ u32 modena_init0_bw_integer;
+ u32 modena_init0_watermark_0;
+};
+
/* gmii_sel register defines */
#define GMII1_SEL_MII 0x0
#define GMII1_SEL_RMII 0x1
/* Module base addresses */
+/* L3 Fast Configuration Bandwidth Limiter Base Address */
+#define L3F_CFG_BWLIMITER 0x44005200
+
/* UART Base Address */
#define UART0_BASE 0x44E09000
#define VTP0_CTRL_ADDR 0x44E10E0C
#define VTP1_CTRL_ADDR 0x48140E10
+/* USB CTRL Base Address */
+#define USB1_CTRL 0x44e10628
+#define USB1_CTRL_CM_PWRDN BIT(0)
+#define USB1_CTRL_OTG_PWRDN BIT(1)
+
/* DDR Base address */
#define DDR_PHY_CMD_ADDR 0x44E12000
#define DDR_PHY_DATA_ADDR 0x44E120C8
#define SRAM_SCRATCH_SPACE_ADDR 0x40337C00
#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR
#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC
+#define AM4372_BOARD_VERSION_START SRAM_SCRATCH_SPACE_ADDR + 0xD
+#define AM4372_BOARD_VERSION_END SRAM_SCRATCH_SPACE_ADDR + 0x14
#define QSPI_BASE 0x47900000
#endif
#endif
*/
#ifdef CONFIG_CMD_I2C
#ifndef CONFIG_SYS_I2C_SOFT
-#define CONFIG_I2C_MVTWSI
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
#endif
#define CONFIG_SYS_I2C_SLAVE 0x0
#define CONFIG_SYS_I2C_SPEED 100000
MX6_PAD_DECL(DISP0_DAT1__LCD_DATA01, 0x03C8, 0x00B4, 1, 0x0000, 0, 0)
MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI, 0x03C8, 0x00B4, 2, 0x0000, 0, 0)
MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22, 0x03C8, 0x00B4, 5, 0x0000, 0, 0)
-MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10, 0x03CC, 0x00B8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10, 0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
MX6_PAD_DECL(DISP0_DAT10__LCD_DATA10, 0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm)
MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31, 0x03CC, 0x00B8, 5, 0x0000, 0, 0)
MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11, 0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC, 0x03F0, 0x00DC, 4, 0x07A0, 0, 0)
MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13, 0x03F0, 0x00DC, 5, 0x0000, 0, 0)
MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B, 0x03F0, 0x00DC, 7, 0x0000, 0, 0)
-MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02, 0x03F4, 0x00E0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02, 0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
MX6_PAD_DECL(DISP0_DAT2__LCD_DATA02, 0x03F4, 0x00E0, 1, 0x0000, 0, 0)
MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO, 0x03F4, 0x00E0, 2, 0x0000, 0, 0)
MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23, 0x03F4, 0x00E0, 5, 0x0000, 0, 0)
#elif defined(CONFIG_R8A7791)
#include "r8a7791-gpio.h"
void r8a7791_pinmux_init(void);
+#elif defined(CONFIG_R8A7794)
+#include "r8a7794-gpio.h"
+void r8a7794_pinmux_init(void);
#endif
#endif /* __ASM_ARCH_GPIO_H */
--- /dev/null
+#ifndef __ASM_R8A7794_H__
+#define __ASM_R8A7794_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+ GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
+ GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
+ GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
+ GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
+ GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
+ GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
+ GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
+ GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
+
+ GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
+ GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
+ GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
+ GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
+ GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
+ GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
+ GPIO_GP_1_24, GPIO_GP_1_25,
+
+ GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
+ GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
+ GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
+ GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
+ GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
+ GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
+ GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
+ GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
+
+ GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
+ GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
+ GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
+ GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
+ GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
+ GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
+ GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
+ GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
+
+ GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
+ GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
+ GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
+ GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
+ GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
+ GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
+ GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
+ GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
+
+ GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
+ GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
+ GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
+ GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
+ GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
+ GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
+ GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
+
+ GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
+ GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
+ GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
+ GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
+ GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
+ GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,
+ GPIO_GP_6_24, GPIO_GP_6_25,
+
+ GPIO_FN_A2, GPIO_FN_WE0_N, GPIO_FN_WE1_N, GPIO_FN_DACK0,
+ GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN,
+ GPIO_FN_USB1_OVC, GPIO_FN_SD0_CLK, GPIO_FN_SD0_CMD,
+ GPIO_FN_SD0_DATA0, GPIO_FN_SD0_DATA1, GPIO_FN_SD0_DATA2,
+ GPIO_FN_SD0_DATA3, GPIO_FN_SD0_CD, GPIO_FN_SD0_WP,
+ GPIO_FN_SD1_CLK, GPIO_FN_SD1_CMD, GPIO_FN_SD1_DATA0,
+ GPIO_FN_SD1_DATA1, GPIO_FN_SD1_DATA2, GPIO_FN_SD1_DATA3,
+
+ /*
+ * From IPSR0 to IPSR5 have been removed because they does not use.
+ */
+
+ /* IPSR6 */
+ GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE, GPIO_FN_CC50_STATE28,
+ GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
+ GPIO_FN_CC50_STATE29, GPIO_FN_DU0_DISP, GPIO_FN_QPOLA,
+ GPIO_FN_CC50_STATE30, GPIO_FN_DU0_CDE, GPIO_FN_QPOLB,
+ GPIO_FN_CC50_STATE31, GPIO_FN_VI0_CLK, GPIO_FN_AVB_RX_CLK,
+ GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_AVB_RX_DV, GPIO_FN_VI0_DATA1_VI0_B1,
+ GPIO_FN_AVB_RXD0, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_AVB_RXD1,
+ GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_AVB_RXD2, GPIO_FN_VI0_DATA4_VI0_B4,
+ GPIO_FN_AVB_RXD3, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_AVB_RXD4,
+ GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA7_VI0_B7,
+ GPIO_FN_AVB_RXD6, GPIO_FN_VI0_CLKENB, GPIO_FN_I2C3_SCL,
+ GPIO_FN_SCIFA5_RXD_C, GPIO_FN_IETX_C, GPIO_FN_AVB_RXD7,
+ GPIO_FN_VI0_FIELD, GPIO_FN_I2C3_SDA, GPIO_FN_SCIFA5_TXD_C,
+ GPIO_FN_IECLK_C, GPIO_FN_AVB_RX_ER, GPIO_FN_VI0_HSYNC_N,
+ GPIO_FN_SCIF0_RXD_B, GPIO_FN_I2C0_SCL_C, GPIO_FN_IERX_C,
+ GPIO_FN_AVB_COL, GPIO_FN_VI0_VSYNC_N, GPIO_FN_SCIF0_TXD_B,
+ GPIO_FN_I2C0_SDA_C, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_AVB_TX_EN,
+ GPIO_FN_ETH_MDIO, GPIO_FN_VI0_G0, GPIO_FN_MSIOF2_RXD_B,
+ GPIO_FN_IIC0_SCL_D, GPIO_FN_AVB_TX_CLK, GPIO_FN_ADIDATA, GPIO_FN_AD_DI,
+
+ /* IPSR7 */
+ GPIO_FN_ETH_CRS_DV, GPIO_FN_VI0_G1, GPIO_FN_MSIOF2_TXD_B,
+ GPIO_FN_IIC0_SDA_D, GPIO_FN_AVB_TXD0, GPIO_FN_ADICS_SAMP, GPIO_FN_AD_DO,
+ GPIO_FN_ETH_RX_ER, GPIO_FN_VI0_G2, GPIO_FN_MSIOF2_SCK_B,
+ GPIO_FN_CAN0_RX_B, GPIO_FN_AVB_TXD1, GPIO_FN_ADICLK, GPIO_FN_AD_CLK,
+ GPIO_FN_ETH_RXD0, GPIO_FN_VI0_G3, GPIO_FN_MSIOF2_SYNC_B,
+ GPIO_FN_CAN0_TX_B, GPIO_FN_AVB_TXD2, GPIO_FN_ADICHS0, GPIO_FN_AD_NCS_N,
+ GPIO_FN_ETH_RXD1, GPIO_FN_VI0_G4, GPIO_FN_MSIOF2_SS1_B,
+ GPIO_FN_SCIF4_RXD_D, GPIO_FN_AVB_TXD3, GPIO_FN_ADICHS1,
+ GPIO_FN_ETH_LINK, GPIO_FN_VI0_G5, GPIO_FN_MSIOF2_SS2_B,
+ GPIO_FN_SCIF4_TXD_D, GPIO_FN_AVB_TXD4, GPIO_FN_ADICHS2,
+ GPIO_FN_ETH_REFCLK, GPIO_FN_VI0_G6, GPIO_FN_SCIF2_SCK_C,
+ GPIO_FN_AVB_TXD5, GPIO_FN_SSI_SCK5_B, GPIO_FN_ETH_TXD1, GPIO_FN_VI0_G7,
+ GPIO_FN_SCIF2_RXD_C, GPIO_FN_IIC1_SCL_D, GPIO_FN_AVB_TXD6,
+ GPIO_FN_SSI_WS5_B, GPIO_FN_ETH_TX_EN, GPIO_FN_VI0_R0,
+ GPIO_FN_SCIF2_TXD_C, GPIO_FN_IIC1_SDA_D, GPIO_FN_AVB_TXD7,
+ GPIO_FN_SSI_SDATA5_B, GPIO_FN_ETH_MAGIC, GPIO_FN_VI0_R1,
+ GPIO_FN_SCIF3_SCK_B, GPIO_FN_AVB_TX_ER, GPIO_FN_SSI_SCK6_B,
+ GPIO_FN_ETH_TXD0, GPIO_FN_VI0_R2, GPIO_FN_SCIF3_RXD_B,
+ GPIO_FN_I2C4_SCL_E, GPIO_FN_AVB_GTX_CLK, GPIO_FN_SSI_WS6_B,
+ GPIO_FN_DREQ0_N, GPIO_FN_SCIFB1_RXD,
+
+ /* IPSR8 */
+ GPIO_FN_ETH_MDC, GPIO_FN_VI0_R3, GPIO_FN_SCIF3_TXD_B,
+ GPIO_FN_I2C4_SDA_E, GPIO_FN_AVB_MDC, GPIO_FN_SSI_SDATA6_B,
+ GPIO_FN_HSCIF0_HRX, GPIO_FN_VI0_R4, GPIO_FN_I2C1_SCL_C,
+ GPIO_FN_AUDIO_CLKA_B, GPIO_FN_AVB_MDIO, GPIO_FN_SSI_SCK78_B,
+ GPIO_FN_HSCIF0_HTX, GPIO_FN_VI0_R5, GPIO_FN_I2C1_SDA_C,
+ GPIO_FN_AUDIO_CLKB_B, GPIO_FN_AVB_LINK, GPIO_FN_SSI_WS78_B,
+ GPIO_FN_HSCIF0_HCTS_N, GPIO_FN_VI0_R6, GPIO_FN_SCIF0_RXD_D,
+ GPIO_FN_I2C0_SCL_E, GPIO_FN_AVB_MAGIC, GPIO_FN_SSI_SDATA7_B,
+ GPIO_FN_HSCIF0_HRTS_N, GPIO_FN_VI0_R7, GPIO_FN_SCIF0_TXD_D,
+ GPIO_FN_I2C0_SDA_E, GPIO_FN_AVB_PHY_INT, GPIO_FN_SSI_SDATA8_B,
+ GPIO_FN_HSCIF0_HSCK, GPIO_FN_SCIF_CLK_B, GPIO_FN_AVB_CRS,
+ GPIO_FN_AUDIO_CLKC_B, GPIO_FN_I2C0_SCL, GPIO_FN_SCIF0_RXD_C,
+ GPIO_FN_PWM5, GPIO_FN_TCLK1_B, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN1_RX_D,
+ GPIO_FN_TPUTO0_B, GPIO_FN_I2C0_SDA, GPIO_FN_SCIF0_TXD_C, GPIO_FN_TPUTO0,
+ GPIO_FN_CAN_CLK, GPIO_FN_DVC_MUTE, GPIO_FN_CAN1_TX_D, GPIO_FN_I2C1_SCL,
+ GPIO_FN_SCIF4_RXD, GPIO_FN_PWM5_B, GPIO_FN_DU1_DR0, GPIO_FN_RIF1_SYNC_B,
+ GPIO_FN_TS_SDATA_D, GPIO_FN_TPUTO1_B, GPIO_FN_I2C1_SDA,
+ GPIO_FN_SCIF4_TXD, GPIO_FN_IRQ5, GPIO_FN_DU1_DR1, GPIO_FN_RIF1_CLK_B,
+ GPIO_FN_TS_SCK_D, GPIO_FN_BPFCLK_C, GPIO_FN_MSIOF0_RXD,
+ GPIO_FN_SCIF5_RXD, GPIO_FN_I2C2_SCL_C, GPIO_FN_DU1_DR2,
+ GPIO_FN_RIF1_D0_B, GPIO_FN_TS_SDEN_D, GPIO_FN_FMCLK_C, GPIO_FN_RDS_CLK,
+
+ /*
+ * From IPSR9 to IPSR10 have been removed because they does not use.
+ */
+
+ /* IPSR11 */
+ GPIO_FN_SSI_WS5, GPIO_FN_SCIFA3_RXD, GPIO_FN_I2C3_SCL_C,
+ GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5,
+ GPIO_FN_SCIFA3_TXD, GPIO_FN_I2C3_SDA_C, GPIO_FN_DU1_DOTCLKOUT1,
+ GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SCK6, GPIO_FN_SCIFA1_SCK_B,
+ GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_SSI_WS6,
+ GPIO_FN_SCIFA1_RXD_B, GPIO_FN_I2C4_SCL_C, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC,
+ GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_SDATA6, GPIO_FN_SCIFA1_TXD_B,
+ GPIO_FN_I2C4_SDA_C, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
+ GPIO_FN_CAN_DEBUGOUT15, GPIO_FN_SSI_SCK78, GPIO_FN_SCIFA2_SCK_B,
+ GPIO_FN_IIC0_SDA_C, GPIO_FN_DU1_DISP, GPIO_FN_SSI_WS78,
+ GPIO_FN_SCIFA2_RXD_B, GPIO_FN_IIC0_SCL_C, GPIO_FN_DU1_CDE,
+ GPIO_FN_SSI_SDATA7, GPIO_FN_SCIFA2_TXD_B, GPIO_FN_IRQ8,
+ GPIO_FN_AUDIO_CLKA_D, GPIO_FN_CAN_CLK_D, GPIO_FN_PCMOE_N,
+ GPIO_FN_SSI_SCK0129, GPIO_FN_MSIOF1_RXD_B, GPIO_FN_SCIF5_RXD_D,
+ GPIO_FN_ADIDATA_B, GPIO_FN_AD_DI_B, GPIO_FN_PCMWE_N, GPIO_FN_SSI_WS0129,
+ GPIO_FN_MSIOF1_TXD_B, GPIO_FN_SCIF5_TXD_D, GPIO_FN_ADICS_SAMP_B,
+ GPIO_FN_AD_DO_B, GPIO_FN_SSI_SDATA0, GPIO_FN_MSIOF1_SCK_B,
+ GPIO_FN_PWM0_B, GPIO_FN_ADICLK_B, GPIO_FN_AD_CLK_B,
+
+ /*
+ * From IPSR12 to IPSR13 have been removed because they does not use.
+ */
+};
+
+#endif /* __ASM_R8A7794_H__ */
--- /dev/null
+/*
+ * arch/arm/include/asm/arch-rmobile/r8a7794.h
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+*/
+
+#ifndef __ASM_ARCH_R8A7794_H
+#define __ASM_ARCH_R8A7794_H
+
+#include "rcar-base.h"
+
+#endif /* __ASM_ARCH_R8A7794_H */
#define __ASM_ARCH_RCAR_BASE_H
/*
- * R-Car (R8A7790/R8A7791) I/O Addresses
+ * R-Car (R8A7790/R8A7791/R8A7794) I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
#define SYS_AXI_SAT1_BASE 0xFF8009C0
#define SYS_AXI_SDM0_BASE 0xFF800A00
#define SYS_AXI_SDM1_BASE 0xFF800A40
-#define SYS_AXI_TRAB_BASE 0xFF800B00
+#define SYS_AXI_TRAB_BASE 0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
#define SYS_AXI_UDM0_BASE 0xFF800B80
#define SYS_AXI_UDM1_BASE 0xFF800BC0
#include <asm/arch/r8a7790.h>
#elif defined(CONFIG_R8A7791)
#include <asm/arch/r8a7791.h>
+#elif defined(CONFIG_R8A7794)
+#include <asm/arch/r8a7794.h>
#else
#error "SOC Name not defined"
#endif
int sunxi_gpio_get_cfgpin(u32 pin);
int sunxi_gpio_set_drv(u32 pin, u32 val);
int sunxi_gpio_set_pull(u32 pin, u32 val);
+int sunxi_name_to_gpio(const char *name);
+#define name_to_gpio(name) sunxi_name_to_gpio(name)
#endif /* _SUNXI_GPIO_H */
--- /dev/null
+/*
+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _SUNXI_I2C_H_
+#define _SUNXI_I2C_H_
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_I2C_MVTWSI_BASE SUNXI_TWI0_BASE
+/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
+#define CONFIG_SYS_TCLK 24000000
+
+#endif
#ifndef _SUNXI_TIMER_H_
#define _SUNXI_TIMER_H_
+#define WDT_CTRL_RESTART (0x1 << 0)
+#define WDT_CTRL_KEY (0x0a57 << 1)
+#define WDT_MODE_EN (0x1 << 0)
+#define WDT_MODE_RESET_EN (0x1 << 1)
+
#ifndef __ASSEMBLY__
#include <linux/types.h>
/* bit fields definitions for IO Packet Header 3 format */
#define PKT_HDR3_READ_MODE_SHIFT 19
#define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT)
+#define PKT_HDR3_REPEAT_START_SHIFT 16
+#define PKT_HDR3_REPEAT_START_MASK (1 << PKT_HDR3_REPEAT_START_SHIFT)
#define PKT_HDR3_SLAVE_ADDR_SHIFT 0
#define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT)
u32 emif_ddr_phy_ctrl_1;
u32 emif_ddr_phy_ctrl_1_shdw;
u32 emif_ddr_phy_ctrl_2;
- u32 padding7[12];
+ u32 padding7[4];
+ u32 emif_prio_class_serv_map;
+ u32 emif_connect_id_serv_1_map;
+ u32 emif_connect_id_serv_2_map;
+ u32 padding8[5];
u32 emif_rd_wr_exec_thresh;
- u32 padding8[7];
+ u32 emif_cos_config;
+ u32 padding9[6];
u32 emif_ddr_phy_status[21];
- u32 padding9[27];
+ u32 padding10[27];
u32 emif_ddr_ext_phy_ctrl_1;
u32 emif_ddr_ext_phy_ctrl_1_shdw;
u32 emif_ddr_ext_phy_ctrl_2;
u32 emif_rd_wr_lvl_rmp_ctl;
u32 emif_rd_wr_lvl_ctl;
u32 emif_rd_wr_exec_thresh;
+ u32 emif_prio_class_serv_map;
+ u32 emif_connect_id_serv_1_map;
+ u32 emif_connect_id_serv_2_map;
+ u32 emif_cos_config;
};
struct lpddr2_mr_regs {
if (cooked_str != raw_str)
free((char *)cooked_str);
}
-static void jtag_putc(const char c)
+static void jtag_putc(struct stdio_dev *dev, const char c)
{
jtag_send(&c, 1);
}
-static void jtag_puts(const char *s)
+static void jtag_puts(struct stdio_dev *dev, const char *s)
{
jtag_send(s, strlen(s));
}
}
/* Higher layers want to know when any data is available */
-static int jtag_tstc(void)
+static int jtag_tstc(struct stdio_dev *dev)
{
return jtag_tstc_dbg() || leftovers_len;
}
* [32bit length][actual data]
*/
static uint32_t leftovers;
-static int jtag_getc(void)
+static int jtag_getc(struct stdio_dev *dev)
{
int ret;
uint32_t emudat;
leftovers = emudat;
}
- return jtag_getc();
+ return jtag_getc(dev);
}
int drv_jtag_console_init(void)
#ifndef __ASM_BLACKFIN_CONFIG_PRE_H__
#define __ASM_BLACKFIN_CONFIG_PRE_H__
-/* Misc helper functions */
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
* Depending on your cpu, some of these may not be valid, check your HRM.
* The actual values here are meaningless as long as they're unique.
{
return bfin_read_DMEM_CONTROL() & ACACHE_BCACHE;
}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ blackfin_dcache_flush_invalidate_range((const void *)start, (const void *)stop);
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ blackfin_dcache_flush_range((const void *)start, (const void *)stop);
+}
#include <asm/fec.h>
#endif
+/* The registers in fbcs_t struct can be 16-bit for CONFIG_M5235 or 32-bit wide otherwise. */
+#ifdef CONFIG_M5235
+#define out_be_fbcs_reg out_be16
+#else
+#define out_be_fbcs_reg out_be32
+#endif
+
/*
* Breath some life into the CPU...
*
out_8(&gpio->par_cs, 0);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+ out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+ out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+ out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+ out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+ out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+ out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+ out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+ out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
- out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
- out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+ out_be_fbcs_reg(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+ out_be_fbcs_reg(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
- out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
- out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+ out_be_fbcs_reg(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+ out_be_fbcs_reg(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
- out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
- out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
+ out_be_fbcs_reg(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
+ out_be_fbcs_reg(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
#endif
#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
- out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
- out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
+ out_be_fbcs_reg(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
+ out_be_fbcs_reg(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
#endif
gd->cpu_clk = vco / temp; /* cpu clock */
gd->arch.flb_clk = vco / temp; /* FlexBus clock */
gd->arch.flb_clk >>= 1;
- if (in_be16(ccm->misccr2) & 2) /* fsys/4 */
+ if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */
gd->arch.flb_clk >>= 1;
temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
typedef int __kernel_pid_t;
typedef unsigned int __kernel_uid_t;
typedef unsigned int __kernel_gid_t;
-typedef unsigned long __kernel_size_t;
+typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef long __kernel_ptrdiff_t;
typedef long __kernel_time_t;
sprintf(env_val, "%d", baudrate);
setenv(env_var, env_val);
- if (port->start())
+ if (port->start(port))
return NULL;
set_bit(num, &initialized);
if (!port)
return -1;
- ret = port->stop();
+ ret = port->stop(port);
clear_bit(num, &initialized);
return ret;
if (!port || !buf)
return -1;
- port->puts(buf);
+ port->puts(port, buf);
return 0;
}
if (!size)
return 0;
- while (port->tstc()) {
- buf[cnt++] = port->getc();
+ while (port->tstc(port)) {
+ buf[cnt++] = port->getc(port);
if (cnt > size)
break;
}
GOT_ENTRY(__init_end)
GOT_ENTRY(__bss_end)
GOT_ENTRY(__bss_start)
-#if defined(CONFIG_FADS)
- GOT_ENTRY(environment)
-#endif
END_GOT
/*
pre = 'M'; m = 1;
if (id_str == NULL)
id_str =
-# if defined(CONFIG_MPC852T)
- "PC852T";
-# elif defined(CONFIG_MPC859T)
+# if defined(CONFIG_MPC859T)
"PC859T";
-# elif defined(CONFIG_MPC859DSL)
- "PC859DSL";
-# elif defined(CONFIG_MPC866T)
- "PC866T";
# else
"PC866x"; /* Unknown chip from MPC866 family */
# endif
defined(CONFIG_MHPC) || \
defined(CONFIG_R360MPI) || \
defined(CONFIG_RMU) || \
- defined(CONFIG_RPXLITE) || \
- defined(CONFIG_SPC1920) || \
defined(CONFIG_SPD823TS)
memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
-#if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM)
- rpxlite_init ();
-#endif
-
#ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */
/* write config value */
immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;
*/
immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
-#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
- {
- volatile fec_t *fecp;
-
- /*
- * only two FECs please
- */
- if ((unsigned int)fecidx >= 2)
- hang();
-
- if (fecidx == 0)
- fecp = &immr->im_cpm.cp_fec1;
- else
- fecp = &immr->im_cpm.cp_fec2;
-
- /* our PHYs are the limit at 2.5 MHz */
- fecp->fec_mii_speed <<= 1;
- }
-#endif
-
#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
/* use MDC for MII */
immr->im_ioport.iop_pdpar |= 0x0080;
(volatile fec_t *) (CONFIG_SYS_IMMR + efis->fecp_offset);
int i;
- if (efis->ether_index == 0) {
-#if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */
-#if defined(CONFIG_MPC885ADS)
- *(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
-#else
- /* configure FADS for fast (FEC) ethernet, half-duplex */
- /* The LXT970 needs about 50ms to recover from reset, so
- * wait for it by discovering the PHY before leaving eth_init().
- */
- {
- volatile uint *bcsr4 = (volatile uint *) BCSR4;
-
- *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
- | (BCSR4_FETHCFG0 | BCSR4_FETHFDE |
- BCSR4_FETHRST);
-
- /* reset the LXT970 PHY */
- *bcsr4 &= ~BCSR4_FETHRST;
- udelay (10);
- *bcsr4 |= BCSR4_FETHRST;
- udelay (10);
- }
-#endif /* CONFIG_MPC885ADS */
-#endif /* CONFIG_FADS */
- }
-
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
/* the MII interface is connected to FEC1
* so for the miiphy_xxx function to work we must
reset_phy();
#endif
-#ifdef CONFIG_FADS
-#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T)
- /* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */
- *((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
- *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
- *((uint *) BCSR1) &= ~BCSR1_ETHEN;
-#else
- *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
- *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
- *((uint *) BCSR1) &= ~BCSR1_ETHEN;
-#endif
-#endif
-
pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]);
rxIdx = 0;
#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
#endif
-#ifdef CONFIG_RPXLITE
- *((uchar *) BCSR0) |= BCSR0_ETHEN;
-#endif
-
-#if defined(CONFIG_QS860T)
- /*
- * PB27=FDE-, set output low for full duplex
- * PB26=Link Test Enable, normally high output
- */
- immr->im_cpm.cp_pbdir |= 0x00000030;
- immr->im_cpm.cp_pbdat |= 0x00000020;
- immr->im_cpm.cp_pbdat &= ~0x00000010;
-#endif /* QS860T */
-
#if defined(CONFIG_NETVIA)
#if defined(PA_ENET_PDN)
immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
- /*
- * Work around transmit problem with first eth packet
- */
-#if defined (CONFIG_FADS)
- udelay (10000); /* wait 10 ms */
-#endif
-
return 1;
}
# endif
#endif
-#if defined(CONFIG_FADS)
- /* Enable RS232 */
-#if defined(CONFIG_8xx_CONS_SMC1)
- *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
-#else
- *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
-#endif
-#endif /* CONFIG_FADS */
-
-#if defined(CONFIG_RPXLITE)
- /* Enable Monitor Port Transceiver */
- *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
-#endif /* CONFIG_RPXLITE */
-
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
-#ifdef CONFIG_FADS
- /* Reset ADV7176 chip */
- debug ("[VIDEO ENCODER] Resetting encoder...\n");
- (*(int *) BCSR4) &= ~(1 << 21);
-
- /* Wait for 5 ms inside the reset */
- debug ("[VIDEO ENCODER] Waiting for encoder reset...\n");
- udelay (5000);
-
- /* Take ADV7176 out of reset */
- (*(int *) BCSR4) |= 1 << 21;
-
- /* Wait for 5 ms after the reset */
- udelay (5000);
-#endif /* CONFIG_FADS */
-
/* Send configuration */
#ifdef DEBUG
{
debug ("[VIDEO CTRL] Turning off video controller...\n");
SETBIT (immap->im_vid.vid_vccr, VIDEO_VCCR_VON, 0);
-#ifdef CONFIG_FADS
- /* Turn on Video Port LED */
- debug ("[VIDEO CTRL] Turning off video port led...\n");
- SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 1);
-
- /* Disable internal clock */
- debug ("[VIDEO CTRL] Disabling internal clock...\n");
- SETBIT (*(int *) BCSR4, VIDEO_BCSR4_EXTCLK_BIT, 0);
-#endif
-
/* Generate and make active a new video mode */
debug ("[VIDEO CTRL] Generating video mode...\n");
video_mode_generate ();
immap->im_ioport.iop_pdpar = 0x1fff;
immap->im_ioport.iop_pddir = 0x0000;
-#ifdef CONFIG_FADS
- /* Turn on Video Port Clock - ONLY AFTER SET VCCR TO ENABLE EXTERNAL CLOCK */
- debug ("[VIDEO CTRL] Turning on video clock...\n");
- SETBIT (*(int *) BCSR4, VIDEO_BCSR4_EXTCLK_BIT, 1);
-
- /* Turn on Video Port LED */
- debug ("[VIDEO CTRL] Turning on video port led...\n");
- SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 0);
-#endif
#ifdef CONFIG_RRVISION
debug ("PC5->Output(1): enable PAL clock");
immap->im_ioport.iop_pcpar &= ~(0x0400);
}
}
-void video_putc (const char c)
+void video_putc(struct stdio_dev *dev, const char c)
{
if (!video_enable) {
serial_putc (c);
}
}
-void video_puts (const char *s)
+void video_puts(struct stdio_dev *dev, const char *s)
{
int count = strlen (s);
serial_putc (*s++);
else
while (count--)
- video_putc (*s++);
+ video_putc(dev, *s++);
}
/************************************************************************/
{
u16 *screen = video_fb_address, width = VIDEO_COLS;
#ifdef VIDEO_INFO
-# ifndef CONFIG_FADS
char temp[32];
-# endif
char info[80];
#endif /* VIDEO_INFO */
sprintf (info, " Wolfgang DENK, wd@denx.de");
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2,
info);
-#ifndef CONFIG_FADS /* all normal boards */
+
/* leave one blank line */
sprintf(info, "MPC823 CPU at %s MHz, %ld MiB RAM, %ld MiB Flash",
gd->bd->bi_flashsize >> 20 );
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 4,
info);
-#else /* FADS :-( */
- sprintf (info, "MPC823 CPU at 50 MHz on FADS823 board");
- video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT,
- info);
-
- sprintf(info, "2MiB FLASH - 8MiB DRAM - 4MiB SRAM");
- video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y + VIDEO_FONT_HEIGHT * 2,
- info);
-#endif
#endif
return video_fb_address + VIDEO_LOGO_HEIGHT * VIDEO_LINE_LEN;
#define DEBUGF(fmt,args...)
#endif
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
#if defined(CONFIG_405GP)
void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
*/
#include <common.h>
+#include <dm/root.h>
#include <os.h>
#include <asm/state.h>
if (state_uninit())
os_exit(2);
+ if (dm_uninit())
+ os_exit(2);
+
/* This is considered normal termination for now */
os_exit(0);
}
#include <common.h>
#include <os.h>
#include <asm/getopt.h>
+#include <asm/io.h>
#include <asm/sections.h>
#include <asm/state.h>
int main(int argc, char *argv[])
{
struct sandbox_state *state;
+ gd_t data;
int ret;
ret = state_init();
if (state->ram_buf_rm && state->ram_buf_fname)
os_unlink(state->ram_buf_fname);
+ memset(&data, '\0', sizeof(data));
+ gd = &data;
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ gd->malloc_base = CONFIG_MALLOC_F_ADDR;
+#endif
+
/* Do pre- and post-relocation init */
board_init_f(0);
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#define CONFIG_SANDBOX_ARCH
/* Used by drivers/spi/sandbox_spi.c and arch/sandbox/include/asm/state.h */
+++ /dev/null
-/*
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Renesas Solutions Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- * entry and reloct_dst will be provided via ldflags
- */
- . = .;
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- KEEP(arch/sh/cpu/sh2/start.o (.text))
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- PROVIDE (reloc_dst_end = .);
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (__bss_end = .);
-}
+++ /dev/null
-/*
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2008-2009
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
- /*
- * entry and reloct_dst will be provided via ldflags
- */
- . = .;
-
- PROVIDE (_ftext = .);
- PROVIDE (_fcode = .);
- PROVIDE (_start = .);
-
- .text :
- {
- KEEP(arch/sh/cpu/sh4/start.o (.text))
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenv)
- . = ALIGN(8192);
- common/env_embedded.o (.ppcenvr)
- . = ALIGN(8192);
- *(.text)
- . = ALIGN(4);
- } =0xFF
- PROVIDE (_ecode = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- . = ALIGN(4);
- }
- PROVIDE (_etext = .);
-
-
- PROVIDE (_fdata = .);
- .data :
- {
- *(.data)
- . = ALIGN(4);
- }
- PROVIDE (_edata = .);
-
- PROVIDE (_fgot = .);
- .got :
- {
- *(.got)
- . = ALIGN(4);
- }
- PROVIDE (_egot = .);
-
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- PROVIDE (reloc_dst_end = .);
- /* _reloc_dst_end = .; */
-
- PROVIDE (bss_start = .);
- PROVIDE (__bss_start = .);
- .bss (NOLOAD) :
- {
- *(.bss)
- . = ALIGN(4);
- }
- PROVIDE (bss_end = .);
-
- PROVIDE (__bss_end = .);
-}
/*
- * Copyright (C) 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
* Copyright (C) 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
+ * Copyright (C) 2008-2009
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
* Copyright (C) 2008
* Mark Jonas <mark.jonas@de.bosch.com>
*
.text :
{
- KEEP(arch/sh/cpu/sh3/start.o (.text))
+ KEEP(*/start.o (.text))
. = ALIGN(8192);
common/env_embedded.o (.ppcenv)
. = ALIGN(8192);
/*
- * Linker script for Gaisler Research AB's GRSIM LEON3 simulator.
- *
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
*
* SPDX-License-Identifier: GPL-2.0+
_text = .;
*(.start)
- arch/sparc/cpu/leon3/start.o (.text)
+ */start.o (.text)
/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
. = ALIGN(8192);
/* PROM CODE, Will be relocated to the end of memory,
}
}
-static void video_putc(const char c)
+static void video_putc(struct stdio_dev *dev, const char c)
{
int x, y, pos;
outb_p(0xff & (pos >> 1), vidport+1);
}
-static void video_puts(const char *s)
+static void video_puts(struct stdio_dev *dev, const char *s)
{
int x, y, pos;
char c;
vga_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM;
vga_dev.putc = video_putc; /* 'putc' function */
vga_dev.puts = video_puts; /* 'puts' function */
- vga_dev.tstc = NULL; /* 'tstc' function */
- vga_dev.getc = NULL; /* 'getc' function */
if (stdio_register(&vga_dev) == 0)
return 1;
strcpy(kbd_dev.name, "kbd");
kbd_dev.ext = 0;
kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
- kbd_dev.putc = NULL; /* 'putc' function */
- kbd_dev.puts = NULL; /* 'puts' function */
kbd_dev.tstc = i8042_tstc; /* 'tstc' function */
kbd_dev.getc = i8042_getc; /* 'getc' function */
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = RPXlite_dw.o flash.o
+++ /dev/null
-
-After following the step of Yoo. Jonghoon and Wolfgang Denk,
-I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW.
-
-There are at least three differences between the Yoo-ported RPXlite and the RPXlite_DW.
-
-Board(in U-Boot) version(in EmbeddedPlanet) CPU SDRAM FLASH
-RPXlite RPXlite CW 850 16MB 4MB
-RPXlite_DW RPXlite DW(EP 823 H1 DW) 823e 64MB 16MB
-
-This fireware is specially coded for EmbeddedPlanet Co. Software Development
-Platform(RPXlite DW),which has a NEC NL6448BC20-08 LCD panel.
-
-It has the following three features:
-
-1. 64MHz/48MHz system frequence setting options.
-The default setting is 48MHz.To get a 64MHz u-boot,just add
-'64' in make command,like
-
-make distclean
-make RPXlite_DW_64_config
-make all
-
-2. CONFIG_ENV_IS_IN_FLASH/CONFIG_ENV_IS_IN_NVRAM
-
-The default environment parameter is stored in FLASH because it is a common choice for
-environment parameter.So I make NVRAM as backup parameter storeage.The reason why I
-didn't use EEPROM for ENV is that PlanetCore V2.0 use EEPROM as environment parameter
-home.Because of the possibility of using two firewares on this board,I didn't
-'disturb' EEPROM.To get NVRAM support,you may use the following build command:
-
-make distclean
-make RPXlite_DW_NVRAM_config
-make all
-
-3. LCD panel support
-
-To support the Platform better,I added LCD panel(NL6448BC20-08) function.
-For the convenience of debug, CONFIG_PERBOOT was supported. So you just
-perss ENTER if you want to get a serial console in boot downcounting.
-Then you can switch to LCD and serial console freely just typing
-'run lcd' or 'run ser'. They are only vaild when CONFIG_LCD was enabled.
-
-To get a LCD support u-boot,you can do the following:
-
-make distclean
-make RPXlite_DW_LCD_config
-make all
-
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-The basic make commands could be:
-
-make RPXlite_DW_config
-make RPXlite_DW_64_config
-make RPXlite_DW_LCD_config
-make RPXlite_DW_NVRAM_config
-
-BTW,you can combine the above features together and get a workable u-boot to meet your need.
-For example,to get a 64MHZ && ENV_IS_IN_FLASH && LCD panel support u-boot,you can type:
-
-make RPXlite_DW_NVRAM_64_LCD_config
-make all
-
-So other combining make commands could be:
-
-make RPXlite_DW_NVRAM_64_config
-make RPXlite_DW_NVRAM_LCD_config
-make RPXlite_DW_64_LCD_config
-
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The boot process by "make RPXlite_DW_config" could be:
-
-U-Boot 1.1.2 (Aug 29 2004 - 15:11:27)
-
-CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache
-Board: RPXlite_DW
-DRAM: 64 MB
-FLASH: 16 MB
-*** Warning - bad CRC, using default environment
-
-In: serial
-Out: serial
-Err: serial
-Net: SCC ETHERNET
-u-boot>
-
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-A word on the U-Boot environment variable setting and usage :
-
-In the beginning, you could just need very simple default environment variable setting,
-like[include/configs/RPXlite.h] :
-
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-This is enough for kernel NFS test. But as debug process goes on, you would expect
-to save some time on environment variable setting and u-boot/kernel updating.
-So the default environment variable setting would become more complicated. Just like
-the one I did in include/configs/RPXlite_DW.h.
-
-Two u-boot commands, ku and uu, should be careful to use. They were designed to update
-kernel and u-boot image file respectively. You must tftp your image to default address
-'100000' and then use them correctly. Yeah, you can create your own command to do this
-job. :-) The example u-boot image updating process could be :
-
-u-boot>t 100000 RPXlite_DW_LCD.bin
-Using SCC ETHERNET device
-TFTP from server 172.16.115.6; our IP address is 172.16.115.7
-Filename 'RPXlite_DW_LCD.bin'.
-Load address: 0x100000
-Loading: #############################
-done
-Bytes transferred = 144700 (2353c hex)
-u-boot>run uu
-Un-Protect Flash Sectors 0-4 in Bank # 1
-Erase Flash Sectors 0-4 in Bank # 1
-.... done
-Copy to Flash... done
-ff000000: 27051956 552d426f 6f742031 2e312e32 '..VU-Boot 1.1.2
-ff000010: 20284175 67203239 20323030 34202d20 (Aug 29 2004 -
-ff000020: 31353a32 303a3238 29000000 00000000 15:20:28).......
-ff000030: 00000000 00000000 00000000 00000000 ................
-ff000040: 00000000 00000000 00000000 00000000 ................
-ff000050: 00000000 00000000 00000000 00000000 ................
-ff000060: 00000000 00000000 00000000 00000000 ................
-ff000070: 00000000 00000000 00000000 00000000 ................
-ff000080: 00000000 00000000 00000000 00000000 ................
-ff000090: 00000000 00000000 00000000 00000000 ................
-ff0000a0: 00000000 00000000 00000000 00000000 ................
-ff0000b0: 00000000 00000000 00000000 00000000 ................
-ff0000c0: 00000000 00000000 00000000 00000000 ................
-ff0000d0: 00000000 00000000 00000000 00000000 ................
-ff0000e0: 00000000 00000000 00000000 00000000 ................
-ff0000f0: 00000000 00000000 00000000 00000000 ................
-u-boot updating finished
-u-boot>
-
-Also for environment updating, 'run eu' could let you erase OLD default environment variable
-and then use the working u-boot environment setting.
-
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-Finally, if you want to keep the serial port to possible debug on spot for deployment, you
-just need to enable 'DEPLOYMENT' in RPXlite_DW.h as 'DEBUG' does. Only the special string
-defined by CONFIG_AUTOBOOT_STOP_STR like 'st' can stop the autoboot.
-
-I'd like to extend my heartfelt gratitute to kind people for helping me work it out.
-I would particually thank Wolfgang Denk for his nice help.
-
-Enjoy,
-
-Sam Song, samsongshu@yahoo.com.cn
-Institute of Electrical Machinery and Controls
-Shanghai University
-
-Oct. 11, 2004
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Sam Song
- * U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW
- * Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz
- * with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75.
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-static long int dram_size (long int, long int *, long int);
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFCC25
-
-const uint sdram_table[] =
-{
- /*
- * Single Read. (Offset 00h in UPMA RAM)
- */
- 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_,
-
- /*
- * Burst Read. (Offset 08h in UPMA RAM)
- */
- 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
- 0x01FFCC20, 0x1FF74C20, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
- /*
- * Single Write. (Offset 18h in UPMA RAM)
- */
- 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */
- _NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35,
- _NOT_USED_,
-
- /*
- * Burst Write. (Offset 20h in UPMA RAM)
- */
- 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
- 0x01FFFC24, 0x1FF74C25, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
- /*
- * Refresh. (Offset 30h in UPMA RAM)
- */
- 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
- 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4,
- /* INIT sequence RAM WORDS
- * SDRAM Initialization (offset 0x36 in UPMA RAM)
- * The above definition uses the remaining space
- * to establish an initialization sequence,
- * which is executed by a RUN command.
- * The sequence is COMMAND INHIBIT(NOP),Precharge,
- * Load Mode Register,NOP,Auto Refresh.
- */
-
- /*
- * Exception. (Offset 3Ch in UPMA RAM)
- */
- 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
-};
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- puts ("Board: RPXlite_DW\n") ;
- return (0) ;
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size9;
-
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- /* Refresh clock prescalar */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR ;
-
- memctl->memc_mar = 0x00000088;
-
- /* Map controller banks 1 to the SDRAM bank */
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
- /*Disable Periodic timer A. */
-
- udelay(200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80002236; /* SDRAM bank 0 - refresh twice */
-
- udelay(1);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- /*Enable Periodic timer A */
-
- udelay (1000);
-
- /* Check Bank 0 Memory Size
- * try 9 column mode
- */
-
- size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
-
- /*
- * Final mapping:
- */
-
- memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-
- udelay (1000);
-
- return (size9);
-}
-
-void rpxlite_init (void)
-{
- /* Enable NVRAM */
- *((uchar *) BCSR0) |= BCSR0_ENNVRAM;
-}
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size (base, maxsize));
-}
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
- * U-Boot port on RPXlite board
- *
- * Some of flash control words are modified. (from 2x16bit device
- * to 4x8bit device)
- * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices
- * are not tested.
- *
- * (?) Does an RPXLite board which
- * does not use AM29LV800 flash memory exist ?
- * I don't know...
- */
-
-/* Yes,Yoo.They do use other FLASH for the board.
- *
- * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
- * U-Boot port on RPXlite DW version board
- *
- * By now,it uses 4 AM29DL323DB90VI devices(4x8bit).
- * The total FLASH has 16MB(4x4MB).
- * I just made some necessary changes on the basis of Wolfgang and Yoo's job.
- *
- * June 8, 2004 */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions vu_long : volatile unsigned long IN include/common.h
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0 ;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* If Monitor is in the cope of FLASH,then
- * protect this area by default in case for
- * other occupation. [SAM] */
-
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
- &flash_info[0]);
-#endif
- flash_info[0].size = size_b0;
- return (size_b0);
-}
-
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x00010000;
- info->start[3] = base + 0x00018000;
- info->start[4] = base + 0x00020000;
- info->start[5] = base + 0x00028000;
- info->start[6] = base + 0x00030000;
- info->start[7] = base + 0x00038000;
-
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] = base + ((i-7) * 0x00040000);
- }
- } else {
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00010000;
- info->start[i--] = base + info->size - 0x00018000;
- info->start[i--] = base + info->size - 0x00020000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00040000;
- }
- }
-
-}
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sector)\n");
- break;
- /* I just add the FLASH_AMDL323B for RPXlite_DW BOARD. [SAM] */
- default: printf ("Unknown Chip Type\n");
- break;
- }
- printf (" Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count);
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",info->start[i],info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0xAAA] = 0x00AA00AA ;
- addr[0x555] = 0x00550055 ;
- addr[0xAAA] = 0x00900090 ;
-
- value = addr[0] ;
- switch (value & 0x00FF00FF) {
- case AMD_MANUFACT: /* AMD_MANUFACT =0x00010001 in flash.h */
- info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h */
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[2] ; /* device ID */
- switch (value & 0x00FF00FF) {
- case (AMD_ID_LV400T & 0x00FF00FF):
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
- case (AMD_ID_LV400B & 0x00FF00FF):
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
- case (AMD_ID_LV800T & 0x00FF00FF):
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
- case (AMD_ID_LV800B & 0x00FF00FF):
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00400000; /* Size doubled by yooth */
- break; /* => 4 MB */
- case (AMD_ID_LV160T & 0x00FF00FF):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
- case (AMD_ID_LV160B & 0x00FF00FF):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
- case (AMD_ID_DL323B & 0x00FF00FF):
- info->flash_id += FLASH_AMDL323B;
- info->sector_count = 71;
- info->size = 0x01000000;
- break; /* => 16 MB(4x4MB) */
- /* AMD_ID_DL323B= 0x22532253 FLASH_AMDL323B= 0x0013
- * AMD_ID_DL323B could be found in <flash.h>.[SAM]
- * So we could get : flash_id = 0x00000013.
- * The first four-bit represents VEDOR ID,leaving others for FLASH ID. */
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* FLASH_BTYPE=0x0001 mask for bottom boot sector type.If the last bit equals 1,
- * it means bottom boot flash. GOOD IDEA! [SAM]
- */
-
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x00010000;
- info->start[3] = base + 0x00018000;
- info->start[4] = base + 0x00020000;
- info->start[5] = base + 0x00028000;
- info->start[6] = base + 0x00030000;
- info->start[7] = base + 0x00038000;
-
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] = base + ((i-7) * 0x00040000) ;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00010000;
- info->start[i--] = base + info->size - 0x00018000;
- info->start[i--] = base + info->size - 0x00020000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00040000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
- /* info->protect[i] = addr[4] & 1 ; */
- /* Mask it for disorder FLASH protection **[Sam]** */
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile unsigned long *)info->start[0];
-
- *addr = 0xF0F0F0F0; /* reset bank */
- }
- return (info->size);
-}
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0xAAA] = 0xAAAAAAAA;
- addr[0x555] = 0x55555555;
- addr[0xAAA] = 0x80808080;
- addr[0xAAA] = 0xAAAAAAAA;
- addr[0x555] = 0x55555555;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long *)(info->start[sect]) ;
- addr[0] = 0x30303030 ;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long *)(info->start[l_sect]);
- while ((addr[0] & 0x80808080) != 0x80808080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (vu_long *)info->start[0];
- addr[0] = 0xF0F0F0F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0xAAA] = 0xAAAAAAAA;
- addr[0x555] = 0x55555555;
- addr[0xAAA] = 0xA0A0A0A0;
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
#endif
}
-void video_putc(const char c)
-{
-}
-
-void video_puts(const char *s)
-{
-}
-
int drv_video_init(void)
{
int error, devices = 1;
strcpy(videodev.name, "video");
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
- videodev.putc = video_putc; /* 'putc' function */
- videodev.puts = video_puts; /* 'puts' function */
error = stdio_register(&videodev);
}
-void video_putc(const char c)
-{
-}
-
-void video_puts(const char *s)
-{
-}
-
int drv_video_init(void)
{
int error, devices = 1;
strcpy(videodev.name, "video");
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
- videodev.putc = video_putc; /* 'putc' function */
- videodev.puts = video_puts; /* 'puts' function */
error = stdio_register(&videodev);
}
-void video_putc(const char c)
-{
-}
-
-void video_puts(const char *s)
-{
-}
-
int drv_video_init(void)
{
int error, devices = 1;
strcpy(videodev.name, "video");
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
- videodev.putc = video_putc; /* 'putc' function */
- videodev.puts = video_puts; /* 'puts' function */
error = stdio_register(&videodev);
#endif
#if defined(CONFIG_CMD_BSP)
-
-extern int do_source (cmd_tbl_t *, int, int, char *[]);
-
#define ADDRMASK 0xfffff000
/*
int count2 = 0;
char addr[16];
char str[] = "\\|/-";
- char *local_args[2];
u32 la, ptm1la;
#if defined(CONFIG_440)
* Boot image via "source" command
*/
printf("executing script at addr 0x%s ...\n", addr);
- local_args[0] = addr;
- local_args[1] = NULL;
- do_source(cmdtp, 0, 1, local_args);
+ source(la, NULL);
break;
case 2:
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = fads.o flash.o lamp.o pcmcia.o
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Dave Ellis, SIXNET, dge@sixnetio.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-Using the Motorola MPC8XXFADS development board
-===============================================
-
-CONFIGURATIONS
---------------
-
-There are ready-to-use default configurations available for the
-FADS823, FADS850SAR and FADS860T. The FADS860T configuration also
-works for the 855T processor.
-
-LOADING U-Boot INTO FADS FLASH MEMORY
---------------------------------------
-
-MPC8BUG can load U-Boot into the FLASH memory using LOADF.
-
- loadf u-boot.srec 100000
-
-
-STARTING U-Boot FROM MPC8BUG
------------------------------
-
-To start U-Boot from MPC8BUG:
-
-1. Reset the board:
- reset :h
-
-2. Change BR0 and OR0 back to their values at reset:
- rms memc br0 00000001
- rms memc or0 00000d34
-
-3. Modify DER so MPC8BUG gets control only when it should:
- rms der 2002000f
-
-4. Start as if from reset:
- go 100
-
-This is NOT exactly the same as starting U-Boot without
-MPC8BUG. MPC8BUG turns off the watchdog as part of the hard reset.
-After it does the reset it writes SYPCR (to disable the watchdog)
-and sets BR0 and OR0 to map the FLASH at 0x02800000 (and does lots
-of other initialization). That is why it is necessary to set BR0
-and OR0 to map the FLASH everywhere. U-Boot can't turn on the
-watchdog after that, since MPC8BUG has used the only chance to write
-to SYPCR.
-
-Here is a bizarre sequence of MPC8BUG and U-Boot commands that lets
-U-Boot write to SYPCR. It works with MPC8BUG 1.5 and an 855T
-processor (your mileage may vary). It is probably better (and a lot
-easier) just to accept having the watchdog disabled when the debug
-cable is connected.
-
-in MPC8BUG:
- reset :h
- rms memc br0 00000001
- rms memc or0 00000d34
- rms der 2000f
- go 100
-
-Now U-Boot is running with the MPC8BUG value for SYPCR. Use the
-U-Boot 'reset' command to reset the board.
- =>reset
-Next, in MPC8BUG:
- rms der 2000f
- go
-
-Now U-Boot is running with the U-Boot value for SYPCR.
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <mpc8xx.h>
-#include <pcmcia.h>
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-/* ========================================================================= */
-
-#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
-
-#if defined(CONFIG_DRAM_50MHZ)
-/* 50MHz tables */
-static const uint dram_60ns[] =
-{ 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04,
- 0x00ffec00, 0x37ffec47, _NOT_USED_, _NOT_USED_,
- 0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c,
- 0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44,
- 0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00,
- 0x3fffc847, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
- 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
- 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
- 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
-
-static const uint dram_70ns[] =
-{ 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
- 0x00ffcc00, 0x37ffcc47, _NOT_USED_, _NOT_USED_,
- 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
- 0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00,
- 0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04,
- 0x00ffec00, 0x3fffec47, _NOT_USED_, _NOT_USED_,
- 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
- 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
- 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
- 0x7fffcc06, 0xffffcc85, 0xffffcc05, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
-
-static const uint edo_60ns[] =
-{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
- 0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_,
- 0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c,
- 0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c,
- 0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
- 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
- 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
- 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
-
-static const uint edo_70ns[] =
-{ 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04,
- 0x00f3cc00, 0x37f7cc47, _NOT_USED_, _NOT_USED_,
- 0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c,
- 0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00,
- 0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00,
- 0x33f7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
- 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
- 0x0cafcc00, 0x33bfcc47, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
- 0x7fffcc04, 0xffffcc86, 0xffffcc05, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
-
-#elif defined(CONFIG_DRAM_25MHZ)
-
-/* 25MHz tables */
-
-static const uint dram_60ns[] =
-{ 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
- 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
- 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
- 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
- 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
-
-static const uint dram_70ns[] =
-{ 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
- 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
- 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
- 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
- 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
-
-static const uint edo_60ns[] =
-{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c,
- 0x08f3cc00, 0x3ff7cc47, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48,
- 0x08afcc48, 0x39bfcc47, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
-
-static const uint edo_70ns[] =
-{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00,
- 0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00,
- 0x3ff7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
- 0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
- 0x37bfcc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
-#else
-#error dram not correctly defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
-#endif
-
-/* ------------------------------------------------------------------------- */
-static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- /* init upm */
-
- switch (delay) {
- case 70:
- if (edo) {
- upmconfig (UPMA, (uint *) edo_70ns,
- sizeof (edo_70ns) / sizeof (uint));
- } else {
- upmconfig (UPMA, (uint *) dram_70ns,
- sizeof (dram_70ns) / sizeof (uint));
- }
-
- break;
-
- case 60:
- if (edo) {
- upmconfig (UPMA, (uint *) edo_60ns,
- sizeof (edo_60ns) / sizeof (uint));
- } else {
- upmconfig (UPMA, (uint *) dram_60ns,
- sizeof (dram_60ns) / sizeof (uint));
- }
-
- break;
-
- default:
- return -1;
- }
-
- memctl->memc_mptpr = 0x0400; /* divide by 16 */
-
- switch (noMbytes) {
- case 4: /* 4 Mbyte uses only CS2 */
- memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */
- memctl->memc_or2 = 0xffc00800; /* 4M */
- break;
-
- case 8: /* 8 Mbyte uses both CS3 and CS2 */
- memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */
- memctl->memc_or3 = 0xffc00800; /* 4M */
- memctl->memc_br3 = 0x00400081 + base;
- memctl->memc_or2 = 0xffc00800; /* 4M */
- break;
-
- case 16: /* 16 Mbyte uses only CS2 */
- memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */
- memctl->memc_or2 = 0xff000800; /* 16M */
- break;
-
- case 32: /* 32 Mbyte uses both CS3 and CS2 */
- memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */
- memctl->memc_or3 = 0xff000800; /* 16M */
- memctl->memc_br3 = 0x01000081 + base;
- memctl->memc_or2 = 0xff000800; /* 16M */
- break;
-
- default:
- return -1;
- }
-
- memctl->memc_br2 = 0x81 + base; /* use upma */
-
- *((uint *) BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */
-
- /* if no dimm is inserted, noMbytes is still detected as 8m, so
- * sanity check top and bottom of memory */
-
- /* check bytes / 2 because get_ram_size tests at base+bytes, which
- * is not mapped */
- if (noMbytes == 8)
- if (get_ram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
- *((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */
- return -1;
- }
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-static void _dramdisable(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_br2 = 0x00000000;
- memctl->memc_br3 = 0x00000000;
-
- /* maybe we should turn off upma here or something */
-}
-#endif /* !CONFIG_MPC885ADS */
-
-/* ========================================================================= */
-
-#ifdef CONFIG_FADS /* SDRAM exists on FADS and newer boards */
-
-#if defined(CONFIG_SDRAM_100MHZ)
-
-/* ------------------------------------------------------------------------- */
-/* sdram table by Dan Malek */
-
-/* This has the stretched early timing so the 50 MHz
- * processor can make the 100 MHz timing. This will
- * work at all processor speeds.
- */
-
-#ifdef SDRAM_ALT_INIT_SEQENCE
-# define SDRAM_MBMRVALUE0 0xc3802114 /* PTx=195,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */
-#define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0
-# define SDRAM_MCRVALUE0 0x80808111 /* run upmb cs4 loop 1 addr 0x11 MRS */
-# define SDRAM_MCRVALUE1 SDRAM_MCRVALUE0 /* ??? why not 0x80808130? */
-#else
-# define SDRAM_MxMR_PTx 195
-# define UPM_MRS_ADDR 0x11
-# define UPM_REFRESH_ADDR 0x30 /* or 0x11 if we want to be like above? */
-#endif /* !SDRAM_ALT_INIT_SEQUENCE */
-
-static const uint sdram_table[] =
-{
- /* single read. (offset 0 in upm RAM) */
- 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04,
- 0xefbbbc00, 0x1ff77c45, _NOT_USED_, _NOT_USED_,
-
- /* burst read. (offset 8 in upm RAM) */
- 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04,
- 0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00,
- 0x1ff77c45,
-
- /* precharge + MRS. (offset 11 in upm RAM) */
- 0xeffbbc04, 0x1ff77c34, 0xefeabc34,
- 0x1fb57c35, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* single write. (offset 18 in upm RAM) */
- 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04,
- 0x1ff77c45, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* burst write. (offset 20 in upm RAM) */
- 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00,
- 0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* refresh. (offset 30 in upm RAM) */
- 0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* exception. (offset 3c in upm RAM) */
- 0xeffffc06, 0x1ffffc07, _NOT_USED_, _NOT_USED_ };
-
-#elif defined(CONFIG_SDRAM_50MHZ)
-
-/* ------------------------------------------------------------------------- */
-/* sdram table stolen from the fads manual */
-/* for chip MB811171622A-100 */
-
-/* this table is for 32-50MHz operation */
-#ifdef SDRAM_ALT_INIT_SEQENCE
-# define SDRAM_MBMRVALUE0 0x80802114 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */
-# define SDRAM_MBMRVALUE1 0x80802118 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=8 */
-# define SDRAM_MCRVALUE0 0x80808105 /* run upmb cs4 loop 1 addr 0x5 MRS */
-# define SDRAM_MCRVALUE1 0x80808130 /* run upmb cs4 loop 1 addr 0x30 REFRESH */
-# define SDRAM_MPTRVALUE 0x400
-#define SDRAM_MARVALUE 0x88
-#else
-# define SDRAM_MxMR_PTx 128
-# define UPM_MRS_ADDR 0x5
-# define UPM_REFRESH_ADDR 0x30
-#endif /* !SDRAM_ALT_INIT_SEQUENCE */
-
-static const uint sdram_table[] =
-{
- /* single read. (offset 0 in upm RAM) */
- 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
- 0x1ff77c47,
-
- /* precharge + MRS. (offset 5 in upm RAM) */
- 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
-
- /* burst read. (offset 8 in upm RAM) */
- 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
- 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* single write. (offset 18 in upm RAM) */
- 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* burst write. (offset 20 in upm RAM) */
- 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
- 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* refresh. (offset 30 in upm RAM) */
- 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* exception. (offset 3c in upm RAM) */
- 0x7ffffc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
-
-/* ------------------------------------------------------------------------- */
-#else
-#error SDRAM not correctly configured
-#endif
-/* ------------------------------------------------------------------------- */
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-#define SDRAM_OR4VALUE 0x00000a00 /* SAM,GL5A/S=01,addr mask or'ed on later */
-#define SDRAM_BR4VALUE 0x000000c1 /* UPMB,base addr or'ed on later */
-
-/* ------------------------------------------------------------------------- */
-#ifdef SDRAM_ALT_INIT_SEQENCE
-/* ------------------------------------------------------------------------- */
-
-static int _initsdram(uint base, uint noMbytes)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
-
- memctl->memc_mptpr = SDRAM_MPTPRVALUE;
-
- /* Configure the refresh (mostly). This needs to be
- * based upon processor clock speed and optimized to provide
- * the highest level of performance. For multiple banks,
- * this time has to be divided by the number of banks.
- * Although it is not clear anywhere, it appears the
- * refresh steps through the chip selects for this UPM
- * on each refresh cycle.
- * We have to be careful changing
- * UPM registers after we ask it to run these commands.
- */
-
- memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */
- memctl->memc_mar = SDRAM_MARVALUE; /* MRS code */
-
- udelay(200);
-
- /* Now run the precharge/nop/mrs commands.
- */
-
- memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50MHz) */
- /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100MHz) */
- udelay(200);
-
- /* Run 8 refresh cycles */
-
- memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 MHz)*/
- /* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */
-
- udelay(200);
-
- memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 MHz) or TLF 8 (50MHz) */
- memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 MHz) */
- /* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */
-
- udelay(200);
-
- memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */
-
- memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);
- memctl->memc_br4 = SDRAM_BR4VALUE | base;
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-#else /* !SDRAM_ALT_INIT_SEQUENCE */
-/* ------------------------------------------------------------------------- */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-# define MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-# define MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-# define MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-# define MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MxMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-# define SDRAM_MxMR_8COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTBE | \
- MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
-/* 9 column SDRAM */
-# define SDRAM_MxMR_9COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTAE | \
- MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
- MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
-
-static int _initsdram(uint base, uint noMbytes)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
-
- memctl->memc_mptpr = MPTPR_2BK_4K;
- memctl->memc_mbmr = SDRAM_MxMR_8COL & (~(MBMR_PTBE)); /* no refresh yet */
-
- /* map CS 4 */
- memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);
- memctl->memc_br4 = SDRAM_BR4VALUE | base;
-
- /* Perform SDRAM initilization */
-# ifdef UPM_NOP_ADDR /* not currently in UPM table */
- /* step 1: nop */
- memctl->memc_mar = 0x00000000;
- memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
- MCR_MLCF(0) | UPM_NOP_ADDR;
-# endif
-
- /* step 2: delay */
- udelay(200);
-
-# ifdef UPM_PRECHARGE_ADDR /* merged with MRS in UPM table */
- /* step 3: precharge */
- memctl->memc_mar = 0x00000000;
- memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
- MCR_MLCF(4) | UPM_PRECHARGE_ADDR;
-# endif
-
- /* step 4: refresh */
- memctl->memc_mar = 0x00000000;
- memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
- MCR_MLCF(2) | UPM_REFRESH_ADDR;
-
- /*
- * note: for some reason, the UPM values we are using include
- * precharge with MRS
- */
-
- /* step 5: mrs */
- memctl->memc_mar = 0x00000088;
- memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
- MCR_MLCF(1) | UPM_MRS_ADDR;
-
-# ifdef UPM_NOP_ADDR
- memctl->memc_mar = 0x00000000;
- memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
- MCR_MLCF(0) | UPM_NOP_ADDR;
-# endif
- /*
- * Enable refresh
- */
-
- memctl->memc_mbmr |= MBMR_PTBE;
- return 0;
-}
-#endif /* !SDRAM_ALT_INIT_SEQUENCE */
-
-/* ------------------------------------------------------------------------- */
-
-static void _sdramdisable(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_br4 = 0x00000000;
-
- /* maybe we should turn off upmb here or something */
-}
-
-/* ------------------------------------------------------------------------- */
-
-static int initsdram(uint base, uint *noMbytes)
-{
- uint m = CONFIG_SYS_SDRAM_SIZE>>20;
-
- /* _initsdram needs access to sdram */
- *((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */
-
- if(!_initsdram(base, m))
- {
- *noMbytes += m;
- return 0;
- }
- else
- {
- *((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */
-
- _sdramdisable();
-
- return -1;
- }
-}
-
-#endif /* CONFIG_FADS */
-
-/* ========================================================================= */
-
-phys_size_t initdram (int board_type)
-{
- uint sdramsz = 0; /* size of sdram in Mbytes */
- uint m = 0; /* size of dram in Mbytes */
-#ifndef CONFIG_MPC885ADS
- uint base = 0; /* base of dram in bytes */
- uint k, s;
-#endif
-
-#ifdef CONFIG_FADS
- if (!initsdram (0x00000000, &sdramsz)) {
-#ifndef CONFIG_MPC885ADS
- base = sdramsz << 20;
-#endif
- printf ("(%u MB SDRAM) ", sdramsz);
- }
-#endif
-#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
- k = (*((uint *) BCSR2) >> 23) & 0x0f;
-
- switch (k & 0x3) {
- /* "MCM36100 / MT8D132X" */
- case 0x00:
- m = 4;
- break;
-
- /* "MCM36800 / MT16D832X" */
- case 0x01:
- m = 32;
- break;
- /* "MCM36400 / MT8D432X" */
- case 0x02:
- m = 16;
- break;
- /* "MCM36200 / MT16D832X ?" */
- case 0x03:
- m = 8;
- break;
-
- }
-
- switch (k >> 2) {
- case 0x02:
- k = 70;
- break;
-
- case 0x03:
- k = 60;
- break;
-
- default:
- printf ("unknown dramdelay (0x%x) - defaulting to 70 ns", k);
- k = 70;
- }
-
-#ifdef CONFIG_FADS
- /* the FADS is missing this bit, all rams treated as non-edo */
- s = 0;
-#else
- s = (*((uint *) BCSR2) >> 27) & 0x01;
-#endif
-
- if (!_draminit (base, m, s, k)) {
- printf ("%dM %dns %sDRAM: ", m, k, s ? "EDO " : "");
- } else {
- _dramdisable ();
- m = 0;
- }
-#endif /* !CONFIG_MPC885ADS */
- m += sdramsz; /* add sdram size to total */
-
- return (m << 20);
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ========================================================================= */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
-#if defined(CONFIG_MPC86xADS)
- puts ("Board: MPC86xADS\n");
-#elif defined(CONFIG_MPC885ADS)
- puts ("Board: MPC885ADS\n");
-#else /* Only old ADS/FADS have got revision ID in BCSR3 */
- uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3)
- | (((*((uint *) BCSR3) >> 19) & 1) << 2)
- | (((*((uint *) BCSR3) >> 16) & 3));
-
- puts ("Board: ");
-#if defined(CONFIG_FADS)
- puts ("FADS");
- checkdboard ();
-#else
- puts ("ADS");
-#endif
-
- puts (" rev ");
-
- switch (r) {
- case 0x00:
- puts ("ENG\n");
- break;
- case 0x01:
- puts ("PILOT\n");
- break;
- default:
- printf ("unknown (0x%x)\n", r);
- return -1;
- }
-#endif /* CONFIG_MPC86xADS */
-
- return 0;
-}
-
-/* ========================================================================= */
-
-#if defined(CONFIG_CMD_PCMCIA)
-
-#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR
-volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR;
-#endif
-
-int pcmcia_init(void)
-{
- volatile pcmconf8xx_t *pcmp;
- uint v, slota = 0, slotb = 0;
-
- /*
- ** Enable the PCMCIA for a Flash card.
- */
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
-#if 0
- pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR;
- pcmp->pcmc_por0 = 0xc00ff05d;
-#endif
-
- /* Set all slots to zero by default. */
- pcmp->pcmc_pgcra = 0;
- pcmp->pcmc_pgcrb = 0;
-#ifdef CONFIG_PCMCIA_SLOT_A
- pcmp->pcmc_pgcra = 0x40;
-#endif
-#ifdef CONFIG_PCMCIA_SLOT_B
- pcmp->pcmc_pgcrb = 0x40;
-#endif
-
- /* enable PCMCIA buffers */
- *((uint *)BCSR1) &= ~BCSR1_PCCEN;
-
- /* Check if any PCMCIA card is plugged in. */
-
-#ifdef CONFIG_PCMCIA_SLOT_A
- slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
-#endif
-#ifdef CONFIG_PCMCIA_SLOT_B
- slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
-#endif
-
- if (!(slota || slotb)) {
- printf("No card present\n");
- pcmp->pcmc_pgcra = 0;
- pcmp->pcmc_pgcrb = 0;
- return -1;
- }
- else
- printf("Card present (");
-
- v = 0;
-
- /* both the ADS and the FADS have a 5V keyed pcmcia connector (?)
- **
- ** Paolo - Yes, but i have to insert some 3.3V card in that slot on
- ** my FADS... :-)
- */
-
-#if defined(CONFIG_MPC86x)
- switch ((pcmp->pcmc_pipr >> 30) & 3)
-#elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
- switch ((pcmp->pcmc_pipr >> 14) & 3)
-#endif
- {
- case 0x03 :
- printf("5V");
- v = 5;
- break;
- case 0x01 :
- printf("5V and 3V");
-#ifdef CONFIG_FADS
- v = 3; /* User lower voltage if supported! */
-#else
- v = 5;
-#endif
- break;
- case 0x00 :
- printf("5V, 3V and x.xV");
-#ifdef CONFIG_FADS
- v = 3; /* User lower voltage if supported! */
-#else
- v = 5;
-#endif
- break;
- }
-
- switch (v) {
-#ifdef CONFIG_FADS
- case 3:
- printf("; using 3V");
- /*
- ** Enable 3 volt Vcc.
- */
- *((uint *)BCSR1) &= ~BCSR1_PCCVCC1;
- *((uint *)BCSR1) |= BCSR1_PCCVCC0;
- break;
-#endif
- case 5:
- printf("; using 5V");
-#ifdef CONFIG_FADS
- /*
- ** Enable 5 volt Vcc.
- */
- *((uint *)BCSR1) &= ~BCSR1_PCCVCC0;
- *((uint *)BCSR1) |= BCSR1_PCCVCC1;
-#endif
- break;
-
- default:
- *((uint *)BCSR1) |= BCSR1_PCCEN; /* disable pcmcia */
-
- printf("; unknown voltage");
- return -1;
- }
- printf(")\n");
- /* disable pcmcia reset after a while */
-
- udelay(20);
-
-#ifdef CONFIG_PCMCIA_SLOT_A
- pcmp->pcmc_pgcra = 0;
-#endif
-#ifdef CONFIG_PCMCIA_SLOT_B
- pcmp->pcmc_pgcrb = 0;
-#endif
-
- /* If you using a real hd you should give a short
- * spin-up time. */
-#ifdef CONFIG_DISK_SPINUP_TIME
- udelay(CONFIG_DISK_SPINUP_TIME);
-#endif
-
- return 0;
-}
-
-#endif
-
-/* ========================================================================= */
-
-#ifdef CONFIG_SYS_PC_IDE_RESET
-
-void ide_set_reset(int on)
-{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
- /*
- * Configure PC for IDE Reset Pin
- */
- if (on) { /* assert RESET */
- immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
- } else { /* release RESET */
- immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
- }
-
- /* program port pin as GPIO output */
- immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
- immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
- immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
-}
-
-#endif /* CONFIG_SYS_PC_IDE_RESET */
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
- * and Dan Malek
- *
- * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
- *
- * This header file contains values common to all FADS family boards.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/****************************************************************************
- * Flash Memory Map as used by U-Boot:
- *
- * Start Address Length
- * +-----------------------+ 0xFE00_0000 Start of Flash -----------------
- * | | 0xFE00_0100 Reset Vector
- * + + 0xFE0?_????
- * | U-Boot code |
- * | |
- * +-----------------------+ 0xFE04_0000 (sector border)
- * | |
- * | |
- * | U-Boot environment |
- * | | ^
- * | | | U-Boot
- * +=======================+ 0xFE08_0000 (sector border) -----------------
- * | Available | | Applications
- * | ... | v
- *
- *****************************************************************************/
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_NFSBOOTCOMMAND \
- "dhcp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
- "bootm"
-
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
- "bootm fe080000"
-
-#undef CONFIG_BOOTARGS
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#if !defined(CONFIG_MPC885ADS)
-#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#endif
-
-/*
- * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
- * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
- * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
- * got FEC so FEC is the default.
- */
-#undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */
-#define CONFIG_FEC_ENET /* Use FEC ethernet */
-
-#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
-#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
-#endif
-
-#ifdef CONFIG_FEC_ENET
-#define CONFIG_SYS_DISCOVER_PHY
-#define CONFIG_MII_INIT 1
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-#if !defined(FADS_COMMANDS_ALREADY_DEFINED)
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PCMCIA
-#define CONFIG_CMD_PING
-
-#endif
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP /* #undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
-#define CONFIG_SYS_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
-/*
- * 2048 SDRAM rows
- * 1000 factor s -> ms
- * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- */
-#define CONFIG_SYS_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
-#elif defined(CONFIG_FADS) /* Old/new FADS */
-#define CONFIG_SYS_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
-#else /* Old ADS */
-#define CONFIG_SYS_SDRAM_SIZE 0x00000000 /* No SDRAM */
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
-#if (CONFIG_SYS_SDRAM_SIZE)
-#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
-#else
-#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
-#endif /* CONFIG_SYS_SDRAM_SIZE */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
-
-#ifdef CONFIG_BZIP2
-#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
-#else
-#define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
-#endif /* CONFIG_BZIP2 */
-
-/*-----------------------------------------------------------------------
- * Flash organization
- */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
-#define CONFIG_ENV_OFFSET CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */
-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-
-#if defined(CONFIG_CMD_JFFS2)
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
-#define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
-*/
-
-#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-
-/*-----------------------------------------------------------------------
- * I2C configuration
- */
-#if defined(CONFIG_CMD_I2C)
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address defaults */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR SCCR_TBS
-
-/*-----------------------------------------------------------------------
- * DER - Debug Enable Register
- *-----------------------------------------------------------------------
- * Set to zero to prevent the processor from entering debug mode
- */
-#define CONFIG_SYS_DER 0
-
-/* Because of the way the 860 starts up and assigns CS0 the entire
- * address space, we have to set the memory controller differently.
- * Normally, you write the option register first, and then enable the
- * chip select by writing the base register. For CS0, you must write
- * the base register first, followed by the option register.
- */
-
-/*
- * Init Memory Controller:
- *
- * BR0/OR0 (Flash)
- * BR1/OR1 (BCSR)
- */
-/* the other CS:s are determined by looking at parameters in BCSRx */
-
-#define BCSR_ADDR ((uint) 0xFF080000)
-
-#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
-
-/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 8 Mbyte until detected */
-#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_V )
-
-/* BCSRx - Board Control and Status Registers */
-#define CONFIG_SYS_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */
-#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V)
-
-/* values according to the manual */
-
-#define BCSR0 ((uint) (BCSR_ADDR + 0x00))
-#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
-#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
-#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
-#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
-
-/*
- * (F)ADS bitvalues by Helmut Buchsbaum
- *
- * See User's Manual for a proper
- * description of the following structures
- */
-
-#define BCSR0_ERB ((uint)0x80000000)
-#define BCSR0_IP ((uint)0x40000000)
-#define BCSR0_BDIS ((uint)0x10000000)
-#define BCSR0_BPS_MASK ((uint)0x0C000000)
-#define BCSR0_ISB_MASK ((uint)0x01800000)
-#define BCSR0_DBGC_MASK ((uint)0x00600000)
-#define BCSR0_DBPC_MASK ((uint)0x00180000)
-#define BCSR0_EBDF_MASK ((uint)0x00060000)
-
-#define BCSR1_FLASH_EN ((uint)0x80000000)
-#define BCSR1_DRAM_EN ((uint)0x40000000)
-#define BCSR1_ETHEN ((uint)0x20000000)
-#define BCSR1_IRDEN ((uint)0x10000000)
-#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
-#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
-#define BCSR1_BCSR_EN ((uint)0x02000000)
-#define BCSR1_RS232EN_1 ((uint)0x01000000)
-#define BCSR1_PCCEN ((uint)0x00800000)
-#define BCSR1_PCCVCC0 ((uint)0x00400000)
-#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
-#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
-#define BCSR1_RS232EN_2 ((uint)0x00040000)
-#define BCSR1_SDRAM_EN ((uint)0x00020000)
-#define BCSR1_PCCVCC1 ((uint)0x00010000)
-
-#define BCSR1_PCCVCCON BCSR1_PCCVCC0
-
-#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
-#define BCSR2_FLASH_PD_SHIFT 28
-#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
-#define BCSR2_DRAM_PD_SHIFT 23
-#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
-#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
-
-#define BCSR3_DBID_MASK ((ushort)0x3800)
-#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
-#define BCSR3_BREVNR0 ((ushort)0x0080)
-#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
-#define BCSR3_BREVN1 ((ushort)0x0008)
-#define BCSR3_BREVN2_MASK ((ushort)0x0003)
-
-#define BCSR4_ETHLOOP ((uint)0x80000000)
-#define BCSR4_TFPLDL ((uint)0x40000000)
-#define BCSR4_TPSQEL ((uint)0x20000000)
-#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
-#if defined(CONFIG_MPC823)
-#define BCSR4_USB_EN ((uint)0x08000000)
-#define BCSR4_USB_SPEED ((uint)0x04000000)
-#define BCSR4_VCCO ((uint)0x02000000)
-#define BCSR4_VIDEO_ON ((uint)0x00800000)
-#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
-#define BCSR4_VIDEO_RST ((uint)0x00200000)
-#define BCSR4_MODEM_EN ((uint)0x00100000)
-#define BCSR4_DATA_VOICE ((uint)0x00080000)
-#elif defined(CONFIG_MPC850)
-#define BCSR4_DATA_VOICE ((uint)0x00080000)
-#elif defined(CONFIG_MPC860SAR)
-#define BCSR4_UTOPIA_EN ((uint)0x08000000)
-#else /* MPC860T and other chips with FEC */
-#define BCSR4_FETH_EN ((uint)0x08000000)
-#define BCSR4_FETHCFG0 ((uint)0x04000000)
-#define BCSR4_FETHFDE ((uint)0x02000000)
-#define BCSR4_FETHCFG1 ((uint)0x00400000)
-#define BCSR4_FETHRST ((uint)0x00200000)
-#endif
-
-/* BSCR5 exists on MPC86xADS and MPC885ADS only */
-
-#define CONFIG_SYS_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
-
-#define BCSR5 (CONFIG_SYS_PHYDEV_ADDR + 0x300)
-
-#define BCSR5_MII2_EN 0x40
-#define BCSR5_MII2_RST 0x20
-#define BCSR5_T1_RST 0x10
-#define BCSR5_ATM155_RST 0x08
-#define BCSR5_ATM25_RST 0x04
-#define BCSR5_MII1_EN 0x02
-#define BCSR5_MII1_RST 0x01
-
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS 0
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_MAC_PARTITION 1
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_ISO_PARTITION 1
-
-#undef CONFIG_ATAPI
-#if 0 /* does not make sense when CONFIG_CMD_IDE is not enabled, too */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-#endif
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-/* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-#define QUAD_ID(id) ((((ulong)(id) & 0xFF) << 24) | \
- (((ulong)(id) & 0xFF) << 16) | \
- (((ulong)(id) & 0xFF) << 8) | \
- (((ulong)(id) & 0xFF) << 0) \
- )
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static int write_word (flash_info_t * info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- vu_long *bcsr = (vu_long *)BCSR_ADDR;
- unsigned long pd_size, total_size, bsize, or_am;
- int i;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].size = 0;
- flash_info[i].sector_count = 0;
- flash_info[i].start[0] = 0xFFFFFFFF; /* For TFTP */
- }
-
- switch ((bcsr[2] & BCSR2_FLASH_PD_MASK) >> BCSR2_FLASH_PD_SHIFT) {
- case 2:
- case 4:
- case 6:
- pd_size = 0x800000;
- or_am = 0xFF800000;
- break;
-
- case 5:
- case 7:
- pd_size = 0x400000;
- or_am = 0xFFC00000;
- break;
-
- case 8:
- pd_size = 0x200000;
- or_am = 0xFFE00000;
- break;
-
- default:
- pd_size = 0;
- or_am = 0xFFE00000;
- printf("## Unsupported flash detected by BCSR: 0x%08lX\n", bcsr[2]);
- }
-
- total_size = 0;
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS && total_size < pd_size; ++i) {
- bsize = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + total_size),
- &flash_info[i]);
-
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
- i, bsize, bsize >> 20);
- }
-
- total_size += bsize;
- }
-
- if (total_size != pd_size) {
- printf("## Detected flash size %lu conflicts with PD data %lu\n",
- total_size, pd_size);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = or_am | CONFIG_SYS_OR_TIMING_FLASH;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) {
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- if (CONFIG_SYS_MONITOR_BASE >= flash_info[i].start[0])
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[i]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- if (CONFIG_ENV_ADDR >= flash_info[i].start[0])
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[i]);
-#endif
- }
-
- return total_size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf ("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf ("FUJITSU ");
- break;
- case FLASH_MAN_BM:
- printf ("BRIGHT MICRO ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
- break;
- case FLASH_AM080:
- printf ("29F080 or 29LV080 (8 Mbit, uniform sectors)\n");
- break;
- case FLASH_AM400B:
- printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T:
- printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B:
- printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T:
- printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B:
- printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T:
- printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B:
- printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T:
- printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n", info->size >> 20,
- info->sector_count);
-
- printf (" Sector Start Addresses:");
-
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0) {
- printf ("\n ");
- }
-
- printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
-
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- * The following code can not run from flash!
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info)
-{
- short i;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
- addr[0x0555] = 0x90909090;
-
- switch (addr[0]) {
- case QUAD_ID(AMD_MANUFACT):
- info->flash_id = FLASH_MAN_AMD;
- break;
-
- case QUAD_ID(FUJ_MANUFACT):
- info->flash_id = FLASH_MAN_FUJ;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
- }
-
- switch (addr[1]) { /* device ID */
- case QUAD_ID(AMD_ID_F040B):
- case QUAD_ID(AMD_ID_LV040B):
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case QUAD_ID(AMD_ID_F080B):
- info->flash_id += FLASH_AM080;
- info->sector_count = 16;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#if 0
- case AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif /* 0 */
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
-#if 0
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-#else
- /* set sector offsets for uniform sector type */
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = (ulong)addr + (i * 0x00040000);
-#endif
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *) (info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile unsigned long *) info->start[0];
- *addr = 0xF0F0F0F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long *) (info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return ERR_INVAL;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type - aborted\n");
- return ERR_UNKNOWN_FLASH_TYPE;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
- addr[0x0555] = 0x80808080;
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long *) (info->start[sect]);
- addr[0] = 0x30303030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long *) (info->start[l_sect]);
- while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
- {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return ERR_TIMOUT;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- addr = (volatile unsigned long *) info->start[0];
- addr[0] = 0xF0F0F0F0; /* reset bank */
-
- printf (" done\n");
-
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_word (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *) (info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *) dest) & data) != data) {
- return ERR_NOT_ERASED;
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr[0x0555] = 0xAAAAAAAA;
- addr[0x02AA] = 0x55555555;
- addr[0x0555] = 0xA0A0A0A0;
-
- *((vu_long *) dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_long *) dest) & 0x80808080) != (data & 0x80808080))
- {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return ERR_TIMOUT;
- }
- }
- return (0);
-}
+++ /dev/null
-#include <config.h>
-
-#include <common.h>
-
-void
-signal_delay(unsigned int n)
-{
- while (n--);
-}
-
-void
-signal_on(void)
-{
- *((volatile uint *)BCSR4) &= ~(1<<(31-3)); /* led on */
-}
-
-void
-signal_off(void)
-{
- *((volatile uint *)BCSR4) |= (1<<(31-3)); /* led off */
-}
-
-void
-slow_blink(unsigned int n)
-{
- while (n--) {
- signal_on();
- signal_delay(0x00400000);
- signal_off();
- signal_delay(0x00400000);
- }
-}
-
-void
-fast_blink(unsigned int n)
-{
- while (n--) {
- signal_on();
- signal_delay(0x00100000);
- signal_off();
- signal_delay(0x00100000);
- }
-}
+++ /dev/null
-#include <common.h>
-#include <mpc8xx.h>
-#include <pcmcia.h>
-
-#undef CONFIG_PCMCIA
-
-#if defined(CONFIG_CMD_PCMCIA)
-#define CONFIG_PCMCIA
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
-#define CONFIG_PCMCIA
-#endif
-
-#ifdef CONFIG_PCMCIA
-
-#define PCMCIA_BOARD_MSG "FADS"
-
-int pcmcia_voltage_set(int slot, int vcc, int vpp)
-{
- u_long reg = 0;
-
- switch(vpp) {
- case 0: reg = 0; break;
- case 50: reg = 1; break;
- case 120: reg = 2; break;
- default: return 1;
- }
-
- switch(vcc) {
- case 0: reg = 0; break;
-#ifdef CONFIG_FADS
- case 33: reg = BCSR1_PCCVCC0 | BCSR1_PCCVCC1; break;
- case 50: reg = BCSR1_PCCVCC1; break;
-#endif
- default: return 1;
- }
-
- /* first, turn off all power */
-
-#ifdef CONFIG_FADS
- *((uint *)BCSR1) &= ~(BCSR1_PCCVCC0 | BCSR1_PCCVCC1);
-#endif
- *((uint *)BCSR1) &= ~BCSR1_PCCVPP_MASK;
-
- /* enable new powersettings */
-
-#ifdef CONFIG_FADS
- *((uint *)BCSR1) |= reg;
-#endif
-
- *((uint *)BCSR1) |= reg << 20;
-
- return 0;
-}
-
-int pcmcia_hardware_enable(int slot)
-{
- *((uint *)BCSR1) &= ~BCSR1_PCCEN;
- return 0;
-}
-
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_hardware_disable(int slot)
-{
- *((uint *)BCSR1) &= ~BCSR1_PCCEN;
- return 0;
-}
-#endif
-
-#endif /* CONFIG_PCMCIA */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- /*. = DEFINED(env_offset) ? env_offset : .;*/
- common/env_embedded.o (.ppcenv*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
-ENTRY(_start)
int flash_get_offsets(ulong base, flash_info_t * info)
{
- int j, k;
+ int i;
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
info->start[0] = base;
- for (k = 0, j = 0; j < CONFIG_SYS_SST_SECT; j++, k++) {
- info->start[k + 1] = info->start[k] + CONFIG_SYS_SST_SECTSZ;
- info->protect[k] = 0;
+ info->protect[0] = 0;
+ for (i = 1; i < CONFIG_SYS_SST_SECT; i++) {
+ info->start[i] = info->start[i - 1]
+ + CONFIG_SYS_SST_SECTSZ;
+ info->protect[i] = 0;
}
}
+++ /dev/null
-/*
- * Linker script for Gaisler Research AB's GR-CPCI-AX2000 board
- * with template design.
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
-OUTPUT_ARCH(sparc)
-ENTRY(_start)
-SECTIONS
-{
-
-/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
-
- .text : {
- _load_addr = .;
- _text = .;
-
- *(.start)
- arch/sparc/cpu/leon3/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
- . = ALIGN(8192);
-/* PROM CODE, Will be relocated to the end of memory,
- * no global data accesses please.
- */
- __prom_start = .;
- *(.prom.pgt)
- *(.prom.data)
- *(.prom.text)
- . = ALIGN(16);
- __prom_end = .;
- *(.text)
- *(.fixup)
- *(.gnu.warning)
-/* *(.got1)*/
- . = ALIGN(16);
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN(4);
- _etext = .;
-
- /* CMD Table */
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.data.rel)
- *(.data.rel.*)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = ALIGN(4);
- __got_start = .;
- .got : {
- *(.got)
-/* *(.data.rel)
- *(.data.rel.local)*/
- . = ALIGN(16);
- }
- __got_end = .;
-
-/* .data.rel : { } */
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(16); /* to speed clearing of bss up */
- }
- __bss_end = . ;
- __bss_end = . ;
- PROVIDE (end = .);
-
-/* Relocated into main memory */
-
- /* Start of main memory */
- /*. = 0x40000000;*/
-
- .stack (NOLOAD) : { *(.stack) }
-
- /* PROM CODE */
-
- /* global data in RAM passed to kernel after booting */
-
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
-
-}
+++ /dev/null
-/*
- * Linker script for Gaisler Research AB's Template design
- * for Altera NIOS Development board Stratix II Edition, EP2S60 FPGA.
- *
- * (C) Copyright 2008
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
-OUTPUT_ARCH(sparc)
-ENTRY(_start)
-SECTIONS
-{
-
-/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
-
- .text : {
- _load_addr = .;
- _text = .;
-
- *(.start)
- arch/sparc/cpu/leon3/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
- . = ALIGN(8192);
-/* PROM CODE, Will be relocated to the end of memory,
- * no global data accesses please.
- */
- __prom_start = .;
- *(.prom.pgt)
- *(.prom.data)
- *(.prom.text)
- . = ALIGN(16);
- __prom_end = .;
- *(.text)
- *(.fixup)
- *(.gnu.warning)
-/* *(.got1)*/
- . = ALIGN(16);
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN(4);
- _etext = .;
-
- /* CMD Table */
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.data.rel)
- *(.data.rel.*)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = ALIGN(4);
- __got_start = .;
- .got : {
- *(.got)
-/* *(.data.rel)
- *(.data.rel.local)*/
- . = ALIGN(16);
- }
- __got_end = .;
-
-/* .data.rel : { } */
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(16); /* to speed clearing of bss up */
- }
- __bss_end = . ;
- __bss_end = . ;
- PROVIDE (end = .);
-
-/* Relocated into main memory */
-
- /* Start of main memory */
- /*. = 0x40000000;*/
-
- .stack (NOLOAD) : { *(.stack) }
-
- /* PROM CODE */
-
- /* global data in RAM passed to kernel after booting */
-
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
-
-}
+++ /dev/null
-/*
- * Linker script for Gaisler Research AB's GR-XC3S-1500 board
- * with template design.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
-OUTPUT_ARCH(sparc)
-ENTRY(_start)
-SECTIONS
-{
-
-/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
-
- .text : {
- _load_addr = .;
- _text = .;
-
- *(.start)
- arch/sparc/cpu/leon3/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
- . = ALIGN(8192);
-/* PROM CODE, Will be relocated to the end of memory,
- * no global data accesses please.
- */
- __prom_start = .;
- *(.prom.pgt)
- *(.prom.data)
- *(.prom.text)
- . = ALIGN(16);
- __prom_end = .;
- *(.text)
- *(.fixup)
- *(.gnu.warning)
-/* *(.got1)*/
- . = ALIGN(16);
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN(4);
- _etext = .;
-
- /* CMD Table */
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.data.rel)
- *(.data.rel.*)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = ALIGN(4);
- __got_start = .;
- .got : {
- *(.got)
-/* *(.data.rel)
- *(.data.rel.local)*/
- . = ALIGN(16);
- }
- __got_end = .;
-
-/* .data.rel : { } */
-
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(16); /* to speed clearing of bss up */
- }
- __bss_end = . ;
- __bss_end = . ;
- PROVIDE (end = .);
-
-/* Relocated into main memory */
-
- /* Start of main memory */
- /*. = 0x40000000;*/
-
- .stack (NOLOAD) : { *(.stack) }
-
- /* PROM CODE */
-
- /* global data in RAM passed to kernel after booting */
-
-
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
-
-}
+++ /dev/null
-/*
- * Linker script for Gaisler Research AB's GRSIM LEON2 simulator.
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
-OUTPUT_ARCH(sparc)
-ENTRY(_start)
-SECTIONS
-{
-
-/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
-
- .text : {
- _load_addr = .;
- _text = .;
-
- *(.start)
- arch/sparc/cpu/leon2/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
- . = ALIGN(8192);
-/* PROM CODE, Will be relocated to the end of memory,
- * no global data accesses please.
- */
- __prom_start = .;
- *(.prom.pgt)
- *(.prom.data)
- *(.prom.text)
- . = ALIGN(16);
- __prom_end = .;
- *(.text)
- *(.fixup)
- *(.gnu.warning)
-/* *(.got1)*/
- . = ALIGN(16);
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN(4);
- _etext = .;
-
- /* CMD Table */
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.data.rel)
- *(.data.rel.*)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = ALIGN(4);
- __got_start = .;
- .got : {
- *(.got)
-/* *(.data.rel)
- *(.data.rel.local)*/
- . = ALIGN(16);
- }
- __got_end = .;
-
-/* .data.rel : { } */
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(16); /* to speed clearing of bss up */
- }
- __bss_end = . ;
- __bss_end = . ;
- PROVIDE (end = .);
-
-/* Relocated into main memory */
-
- /* Start of main memory */
- /*. = 0x40000000;*/
-
- .stack (NOLOAD) : { *(.stack) }
-
- /* PROM CODE */
-
- /* global data in RAM passed to kernel after booting */
-
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
-
-}
FPGA_GET_REG(0, fpga_features, &fpga_features);
- if (!legacy)
- ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
+ if (!legacy) {
+ /* Turn on Parade DP501 */
+ pca9698_direction_output(0x20, 9, 1);
- print_fpga_info(0, ch0_rgmii2_present);
- osd_probe(0);
+ ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
+ }
/* wait for FPGA done */
for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
}
}
- /* wait for slave-PLLs to be up and running */
+ /* give slave-PLLs and Parade DP501 some time to be up and running */
udelay(500000);
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
slaves = mclink_probe();
mclink_fpgacount = 0;
+ print_fpga_info(0, ch0_rgmii2_present);
+ osd_probe(0);
+
if (slaves <= 0)
return 0;
obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
obj-$(CONFIG_IO) += miiphybb.o
obj-$(CONFIG_IO64) += miiphybb.o
-obj-$(CONFIG_IOCON) += osd.o mclink.o
+obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o
obj-$(CONFIG_DLVISION_10G) += osd.o
obj-$(CONFIG_CONTROLCENTERD) += dp501.o
void dp501_powerup(u8 addr)
{
dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */
+ dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/
i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */
dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */
dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */
i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
+ dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */
+
+#ifdef CONFIG_SYS_DP501_VCAPCTRL0
+ i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0);
+#else
i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */
+#endif
+
+#ifdef CONFIG_SYS_DP501_DIFFERENTIAL
+ i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */
+ i2c_reg_write(addr + 2, 0x25, 0x04);
+ i2c_reg_write(addr + 2, 0x26, 0x10);
+#else
i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
+#endif
+
+ i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
+ i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
+ i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
+ i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
+ i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
+ i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
+ dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
+ i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
+ i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
+ i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
if (dp501_detect_cable_adapter(addr)) {
printf("DVI/HDMI cable adapter detected\n");
dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */
} else {
printf("no DVI/HDMI cable adapter detected\n");
- i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
- i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
- i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
- i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
- i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
- i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
- dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
- i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
- i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
- i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */
dp501_link_training(addr);
#include <i2c.h>
#include <malloc.h>
+#include "dp501.h"
#include <gdsys_fpga.h>
#define CH7301_I2C_ADDR 0x75
#define SIL1178_MASTER_I2C_ADDRESS 0x38
#define SIL1178_SLAVE_I2C_ADDRESS 0x39
+#define DP501_I2C_ADDR 0x08
+
#define PIXCLK_640_480_60 25180000
enum {
unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
-#ifdef CONFIG_SYS_CH7301
-int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
+int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
#endif
-#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
-static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
-{
- u16 val;
-
- do {
- FPGA_GET_REG(screen, extended_interrupt, &val);
- } while (val & (1 << 12));
-
- FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8));
- FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1));
-}
+#ifdef CONFIG_SYS_CH7301_I2C
+int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
+#endif
-static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
-{
- unsigned int ctr = 0;
- u16 val;
-
- do {
- FPGA_GET_REG(screen, extended_interrupt, &val);
- } while (val & (1 << 12));
-
- FPGA_SET_REG(screen, extended_interrupt, 1 << 14);
- FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg);
- FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1));
-
- FPGA_GET_REG(screen, extended_interrupt, &val);
- while (!(val & (1 << 14))) {
- udelay(100000);
- if (ctr++ > 5) {
- printf("iic receive timeout\n");
- break;
- }
- FPGA_GET_REG(screen, extended_interrupt, &val);
- }
+#ifdef CONFIG_SYS_SIL1178_I2C
+int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
+#endif
- FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val);
- return val >> 8;
-}
+#ifdef CONFIG_SYS_DP501_I2C
+int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
#endif
+
#ifdef CONFIG_SYS_MPC92469AC
static void mpc92469ac_calc_parameters(unsigned int fout,
unsigned int *post_div, unsigned int *feedback_div)
}
#endif
-#ifdef CONFIG_SYS_ICS8N3QV01
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
-static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index)
+static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
{
unsigned long long n;
unsigned long long mint;
if (index > 3)
return 0;
- reg_a = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0 + index);
- reg_b = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 4 + index);
- reg_c = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 8 + index);
- reg_d = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 12 + index);
- reg_f = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20 + index);
+ reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index);
+ reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index);
+ reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index);
+ reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index);
+ reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index);
mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
*_n = n;
}
-static void ics8n3qv01_set(unsigned screen, unsigned int fout)
+static void ics8n3qv01_set(unsigned int fout)
{
unsigned int n;
unsigned int mint;
long long off_ppm;
u8 reg0, reg4, reg8, reg12, reg18, reg20;
- fout_calc = ics8n3qv01_get_fout_calc(screen, 1);
+ fout_calc = ics8n3qv01_get_fout_calc(1);
off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
/ ICS8N3QV01_F_DEFAULT_1;
printf(" PLL is off by %lld ppm\n", off_ppm);
/ ICS8N3QV01_F_DEFAULT_1;
ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
- reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
+ reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
reg0 |= (mint & 0x1f) << 1;
reg0 |= (mfrac >> 17) & 0x01;
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0);
reg4 = mfrac >> 9;
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4);
reg8 = mfrac >> 1;
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8);
reg12 = mfrac << 7;
reg12 |= n & 0x7f;
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12);
- reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03;
+ reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03;
reg18 |= 0x20;
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18);
- reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
+ reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
reg20 |= mint & (1 << 5);
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20);
}
#endif
u16 version;
u16 features;
u8 value;
-#ifdef CONFIG_SYS_CH7301
int old_bus = i2c_get_bus_num();
-#endif
+ bool pixclock_present = false;
+ bool output_driver_present = false;
FPGA_GET_REG(0, osd.version, &version);
FPGA_GET_REG(0, osd.features, &features);
printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
screen, version/100, version%100, base_width, base_height);
-#ifdef CONFIG_SYS_CH7301
- i2c_set_bus_num(ch7301_i2c[screen]);
- value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
- if (value != 0x17) {
- printf(" Probing CH7301 failed, DID %02x\n", value);
- i2c_set_bus_num(old_bus);
- return -1;
- }
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
- i2c_set_bus_num(old_bus);
-#endif
+ /* setup pixclock */
#ifdef CONFIG_SYS_MPC92469AC
+ pixclock_present = true;
mpc92469ac_set(screen, PIXCLK_640_480_60);
#endif
-#ifdef CONFIG_SYS_ICS8N3QV01
- ics8n3qv01_set(screen, PIXCLK_640_480_60);
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
+ i2c_set_bus_num(ics8n3qv01_i2c[screen]);
+ if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) {
+ ics8n3qv01_set(PIXCLK_640_480_60);
+ pixclock_present = true;
+ }
#endif
-#ifdef CONFIG_SYS_SIL1178
- value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02);
- if (value != 0x06) {
- printf(" Probing CH7301 SIL1178, DEV_IDL %02x\n", value);
- return -1;
+ if (!pixclock_present)
+ printf(" no pixelclock found\n");
+
+ /* setup output driver */
+
+#ifdef CONFIG_SYS_CH7301_I2C
+ i2c_set_bus_num(ch7301_i2c[screen]);
+ if (!i2c_probe(CH7301_I2C_ADDR)) {
+ value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
+ if (value == 0x17) {
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
+ output_driver_present = true;
+ }
+ }
+#endif
+
+#ifdef CONFIG_SYS_SIL1178_I2C
+ i2c_set_bus_num(sil1178_i2c[screen]);
+ if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) {
+ value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02);
+ if (value == 0x06) {
+ /*
+ * magic initialization sequence,
+ * adapted from datasheet
+ */
+ i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
+ output_driver_present = true;
+ }
}
- /* magic initialization sequence adapted from datasheet */
- fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
#endif
- FPGA_SET_REG(screen, videocontrol, 0x0002);
+#ifdef CONFIG_SYS_DP501_I2C
+ i2c_set_bus_num(dp501_i2c[screen]);
+ if (!i2c_probe(DP501_I2C_ADDR)) {
+ dp501_powerup(DP501_I2C_ADDR);
+ output_driver_present = true;
+ }
+#endif
+
+ if (!output_driver_present)
+ printf(" no output driver found\n");
+
FPGA_SET_REG(screen, osd.control, 0x0049);
FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1));
if (screen > max_osd_screen)
max_osd_screen = screen;
+ i2c_set_bus_num(old_bus);
+
return 0;
}
ESDHC_BOOT_IMAGE_ENTRY_OFS = 0x60,
};
+enum {
+ I2C_SOC_0 = 0,
+ I2C_SOC_1 = 1,
+};
+
struct key_program {
uint32_t magic;
uint32_t code_crc;
int j;
#endif
- I2C_SET_BUS(0);
+ I2C_SET_BUS(I2C_SOC_0);
pca9698_direction_output(0x22, 0, 0); /* Finder */
pca9698_direction_output(0x22, 4, 0); /* Status */
int result = 0;
unsigned int orig_i2c_bus;
- orig_i2c_bus = I2C_GET_BUS();
- I2C_SET_BUS(1);
+ orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(I2C_SOC_1);
/* goto end; */
failure:
result = 1;
end:
- I2C_SET_BUS(orig_i2c_bus);
+ i2c_set_bus_num(orig_i2c_bus);
if (result)
ccdm_hang();
fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
PCI_REGION_MEM);
- versions = readl(fpga->versions);
- fpga_version = readl(fpga->fpga_version);
- fpga_features = readl(fpga->fpga_features);
+ versions = readl(&fpga->versions);
+ fpga_version = readl(&fpga->fpga_version);
+ fpga_features = readl(&fpga->fpga_features);
hardware_version = versions & 0xf;
feature_uart_channels = (fpga_features >> 6) & 0x1f;
#define ESDHC_BOOT_IMAGE_SIZE 0x48
#define ESDHC_BOOT_IMAGE_ADDR 0x50
-int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr)
+int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
{
u8 *tmp_buf;
u32 blklen, code_offset, code_len, n;
memset (&kbddev, 0, sizeof(kbddev));
strcpy(kbddev.name, DEVNAME);
kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
- kbddev.putc = NULL ;
- kbddev.puts = NULL ;
kbddev.getc = kbd_getc ;
kbddev.tstc = kbd_testc ;
}
/* test if a character is in the queue */
-int kbd_testc(void)
+int kbd_testc(struct stdio_dev *dev)
{
if(in_pointer==out_pointer)
return(0); /* no data */
return(1);
}
/* gets the character from the queue */
-int kbd_getc(void)
+int kbd_getc(struct stdio_dev *dev)
{
char c;
while(in_pointer==out_pointer);
#ifndef _KBD_H_
#define _KBD_H_
-extern int kbd_testc(void);
-extern int kbd_getc(void);
+struct stdio_dev;
+
+int kbd_testc(struct stdio_dev *sdev);
+int kbd_getc(struct stdio_dev *sdev);
extern void kbd_interrupt(void);
extern char *kbd_initialize(void);
PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA);
}
-void pci_con_putc(const char c)
+void pci_con_putc(struct stdio_dev *dev, const char c)
{
pci_con_put_it(c);
if(c == '\n')
}
-int pci_con_getc(void)
+int pci_con_getc(struct stdio_dev *dev)
{
int res;
int diff;
return res;
}
-int pci_con_tstc(void)
+int pci_con_tstc(struct stdio_dev *dev)
{
if(r_ptr==(volatile int)w_ptr)
return 0;
return 1;
}
-void pci_con_puts (const char *s)
+void pci_con_puts(struct stdio_dev *dev, const char *s)
{
while (*s) {
pci_con_putc(*s);
bne 0b
/* PLD access is now possible */
- /* r3 = SDRAMDATA
+ /* r3 = SDRAMDATA */
/* r13 = pointer to MEM controller regs */
ldr r1, =PLD_BASE
mov r4, #SDRAMENTRY_SIZE
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = netphone.o flash.o phone_console.o
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_byte(flash_info_t * info, ulong dest, uchar data);
-static void flash_get_offsets(ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size;
-#if CONFIG_NETPHONE_VERSION == 2
- unsigned long size1;
-#endif
- int i;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size << 20);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
-
- /* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-
-#ifdef CONFIG_ENV_ADDR_REDUND
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-#endif
-
- flash_info[0].size = size;
-
-#if CONFIG_NETPHONE_VERSION == 2
- size1 = flash_get_size((vu_long *) FLASH_BASE4_PRELIM, &flash_info[1]);
- if (size1 > 0) {
- if (flash_info[1].flash_id == FLASH_UNKNOWN)
- printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20);
-
- /* Remap FLASH according to real size */
- memctl->memc_or4 = CONFIG_SYS_OR_TIMING_FLASH | (-size1 & 0xFFFF8000);
- memctl->memc_br4 = (CONFIG_SYS_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK));
-
- /* Re-do sizing to get full correct info */
- size1 = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE4, &flash_info[1]);
-
- flash_get_offsets(CONFIG_SYS_FLASH_BASE4, &flash_info[1]);
-
- size += size1;
- } else
- memctl->memc_br4 &= ~BR_V;
-#endif
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets(ulong base, flash_info_t * info)
-{
- int i;
-
- /* set up sector start address table */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000);
- }
- } else if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf("FUJITSU ");
- break;
- case FLASH_MAN_MX:
- printf("MXIC ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400B:
- printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T:
- printf("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B:
- printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T:
- printf("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B:
- printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T:
- printf("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B:
- printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T:
- printf("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- break;
- }
-
- printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-{
- short i;
- uchar mid;
- uchar pid;
- vu_char *caddr = (vu_char *) addr;
- ulong base = (ulong) addr;
-
- /* Write auto select command: read Manufacturer ID */
- caddr[0x0555] = 0xAA;
- caddr[0x02AA] = 0x55;
- caddr[0x0555] = 0x90;
-
- mid = caddr[0];
- switch (mid) {
- case (AMD_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FUJ_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (MX_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_MX;
- break;
- case (STM_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- pid = caddr[1]; /* device ID */
- switch (pid) {
- case (AMD_ID_LV400T & 0xFF):
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case (AMD_ID_LV400B & 0xFF):
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case (AMD_ID_LV800T & 0xFF):
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV800B & 0xFF):
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV160T & 0xFF):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV160B & 0xFF):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV040B & 0xFF):
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break;
-
- case (STM_ID_M29W040B & 0xFF):
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break;
-
-#if 0 /* enable when device IDs are available */
- case (AMD_ID_LV320T & 0xFF):
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_LV320B & 0xFF):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- printf(" ");
- /* set up sector start address table */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000);
- }
- } else if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection: D0 = 1 if protected */
- caddr = (volatile unsigned char *)(info->start[i]);
- info->protect[i] = caddr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- caddr = (vu_char *) info->start[0];
-
- caddr[0x0555] = 0xAA;
- caddr[0x02AA] = 0x55;
- caddr[0x0555] = 0xF0;
-
- udelay(20000);
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
- vu_char *addr = (vu_char *) (info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("- missing\n");
- } else {
- printf("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0x80;
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_char *) (info->start[sect]);
- addr[0] = 0x30;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer(0);
- last = start;
- addr = (vu_char *) (info->start[l_sect]);
- while ((addr[0] & 0x80) != 0x80) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (vu_char *) info->start[0];
- addr[0] = 0xF0; /* reset bank */
-
- printf(" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- int rc;
-
- while (cnt > 0) {
- if ((rc = write_byte(info, addr++, *src++)) != 0) {
- return (rc);
- }
- --cnt;
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_byte(flash_info_t * info, ulong dest, uchar data)
-{
- vu_char *addr = (vu_char *) (info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_char *) dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0xA0;
-
- *((vu_char *) dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer(0);
- while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetTA4 board
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <sed156x.h>
-#include <status_led.h>
-
-#include "mpc8xx.h"
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-#endif
-
-int fec8xx_miiphy_read(char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value);
-int fec8xx_miiphy_write(char *devname, unsigned char addr,
- unsigned char reg, unsigned short value);
-
-/****************************************************************/
-
-/* some sane bit macros */
-#define _BD(_b) (1U << (31-(_b)))
-#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
-
-#define _BW(_b) (1U << (15-(_b)))
-#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
-
-#define _BB(_b) (1U << (7-(_b)))
-#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
-
-#define _B(_b) _BD(_b)
-#define _BR(_l, _h) _BDR(_l, _h)
-
-/****************************************************************/
-
-/*
- * Check Board Identity:
- *
- * Return 1 always.
- */
-
-int checkboard(void)
-{
- printf ("Intracom NetPhone V%d\n", CONFIG_NETPHONE_VERSION);
- return (0);
-}
-
-/****************************************************************/
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-/****************************************************************/
-
-#define CS_0000 0x00000000
-#define CS_0001 0x10000000
-#define CS_0010 0x20000000
-#define CS_0011 0x30000000
-#define CS_0100 0x40000000
-#define CS_0101 0x50000000
-#define CS_0110 0x60000000
-#define CS_0111 0x70000000
-#define CS_1000 0x80000000
-#define CS_1001 0x90000000
-#define CS_1010 0xA0000000
-#define CS_1011 0xB0000000
-#define CS_1100 0xC0000000
-#define CS_1101 0xD0000000
-#define CS_1110 0xE0000000
-#define CS_1111 0xF0000000
-
-#define BS_0000 0x00000000
-#define BS_0001 0x01000000
-#define BS_0010 0x02000000
-#define BS_0011 0x03000000
-#define BS_0100 0x04000000
-#define BS_0101 0x05000000
-#define BS_0110 0x06000000
-#define BS_0111 0x07000000
-#define BS_1000 0x08000000
-#define BS_1001 0x09000000
-#define BS_1010 0x0A000000
-#define BS_1011 0x0B000000
-#define BS_1100 0x0C000000
-#define BS_1101 0x0D000000
-#define BS_1110 0x0E000000
-#define BS_1111 0x0F000000
-
-#define GPL0_AAAA 0x00000000
-#define GPL0_AAA0 0x00200000
-#define GPL0_AAA1 0x00300000
-#define GPL0_000A 0x00800000
-#define GPL0_0000 0x00A00000
-#define GPL0_0001 0x00B00000
-#define GPL0_111A 0x00C00000
-#define GPL0_1110 0x00E00000
-#define GPL0_1111 0x00F00000
-
-#define GPL1_0000 0x00000000
-#define GPL1_0001 0x00040000
-#define GPL1_1110 0x00080000
-#define GPL1_1111 0x000C0000
-
-#define GPL2_0000 0x00000000
-#define GPL2_0001 0x00010000
-#define GPL2_1110 0x00020000
-#define GPL2_1111 0x00030000
-
-#define GPL3_0000 0x00000000
-#define GPL3_0001 0x00004000
-#define GPL3_1110 0x00008000
-#define GPL3_1111 0x0000C000
-
-#define GPL4_0000 0x00000000
-#define GPL4_0001 0x00001000
-#define GPL4_1110 0x00002000
-#define GPL4_1111 0x00003000
-
-#define GPL5_0000 0x00000000
-#define GPL5_0001 0x00000400
-#define GPL5_1110 0x00000800
-#define GPL5_1111 0x00000C00
-#define LOOP 0x00000080
-
-#define EXEN 0x00000040
-
-#define AMX_COL 0x00000000
-#define AMX_ROW 0x00000020
-#define AMX_MAR 0x00000030
-
-#define NA 0x00000008
-
-#define UTA 0x00000004
-
-#define TODT 0x00000002
-
-#define LAST 0x00000001
-
-#define A10_AAAA GPL0_AAAA
-#define A10_AAA0 GPL0_AAA0
-#define A10_AAA1 GPL0_AAA1
-#define A10_000A GPL0_000A
-#define A10_0000 GPL0_0000
-#define A10_0001 GPL0_0001
-#define A10_111A GPL0_111A
-#define A10_1110 GPL0_1110
-#define A10_1111 GPL0_1111
-
-#define RAS_0000 GPL1_0000
-#define RAS_0001 GPL1_0001
-#define RAS_1110 GPL1_1110
-#define RAS_1111 GPL1_1111
-
-#define CAS_0000 GPL2_0000
-#define CAS_0001 GPL2_0001
-#define CAS_1110 GPL2_1110
-#define CAS_1111 GPL2_1111
-
-#define WE_0000 GPL3_0000
-#define WE_0001 GPL3_0001
-#define WE_1110 GPL3_1110
-#define WE_1111 GPL3_1111
-
-/* #define CAS_LATENCY 3 */
-#define CAS_LATENCY 2
-
-const uint sdram_table[0x40] = {
-
-#if CAS_LATENCY == 3
- /* RSS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_,
-
- /* RBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WSS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-#endif
-
-#if CAS_LATENCY == 2
- /* RSS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
- /* RBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WSS */
- CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
- CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_,
-
- /* WBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
- CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
- CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
-#endif
-
- /* UPT */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
- /* EXC */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
- _NOT_USED_,
-
- /* REG */
- CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
- CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
-};
-
-#if CONFIG_NETPHONE_VERSION == 2
-static const uint nandcs_table[0x40] = {
- /* RSS */
- CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
- CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
- CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
- CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
- CS_0000 | GPL4_0000 | GPL5_1111,
- CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
- CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
- CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */
-
- /* RBS */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WSS */
- CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
- CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
- CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
- CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
- CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
- CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
- CS_0000 | GPL4_1111 | GPL5_1111,
- CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
-
- /* WBS */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* UPT */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* EXC */
- CS_0001 | LAST,
- _NOT_USED_,
-
- /* REG */
- CS_1110 ,
- CS_0001 | LAST,
-};
-#endif
-
-/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
-/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
-#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
-
-/* 8 */
-#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-void check_ram(unsigned int addr, unsigned int size)
-{
- unsigned int i, j, v, vv;
- volatile unsigned int *p;
- unsigned int pv;
-
- p = (unsigned int *)addr;
- pv = (unsigned int)p;
- for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
- *p++ = pv;
-
- p = (unsigned int *)addr;
- for (i = 0; i < size / sizeof(unsigned int); i++) {
- v = (unsigned int)p;
- vv = *p;
- if (vv != v) {
- printf("%p: read %08x instead of %08x\n", p, vv, v);
- hang();
- }
- p++;
- }
-
- for (j = 0; j < 5; j++) {
- switch (j) {
- case 0: v = 0x00000000; break;
- case 1: v = 0xffffffff; break;
- case 2: v = 0x55555555; break;
- case 3: v = 0xaaaaaaaa; break;
- default:v = 0xdeadbeef; break;
- }
- p = (unsigned int *)addr;
- for (i = 0; i < size / sizeof(unsigned int); i++) {
- *p = v;
- vv = *p;
- if (vv != v) {
- printf("%p: read %08x instead of %08x\n", p, vv, v);
- hang();
- }
- *p = ~v;
- p++;
- }
- }
-}
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size;
-
- upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
-
- /*
- * Preliminary prescaler for refresh
- */
- memctl->memc_mptpr = MPTPR_PTP_DIV8;
-
- memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
-
- /*
- * Map controller bank 3 to the SDRAM bank at preliminary address.
- */
- memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
- memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */
-
- udelay(200);
-
- /* perform SDRAM initialisation sequence */
- memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
- udelay(1);
-
- memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
- udelay(1);
-
- memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
- udelay(1);
-
- memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
-
- udelay(10000);
-
- {
- u32 d1, d2;
-
- d1 = 0xAA55AA55;
- *(volatile u32 *)0 = d1;
- d2 = *(volatile u32 *)0;
- if (d1 != d2) {
- printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
- hang();
- }
-
- d1 = 0x55AA55AA;
- *(volatile u32 *)0 = d1;
- d2 = *(volatile u32 *)0;
- if (d1 != d2) {
- printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
- hang();
- }
- }
-
- size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
-
- if (size == 0) {
- printf("SIZE is zero: LOOP on 0\n");
- for (;;) {
- *(volatile u32 *)0 = 0;
- (void)*(volatile u32 *)0;
- }
- }
-
- return size;
-}
-
-/* ------------------------------------------------------------------------- */
-
-void reset_phys(void)
-{
- int phyno;
- unsigned short v;
-
- udelay(10000);
- /* reset the damn phys */
- mii_init();
-
- for (phyno = 0; phyno < 32; ++phyno) {
- fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
- if (v == 0xFFFF)
- continue;
- fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
- udelay(10000);
- fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
- BMCR_RESET | BMCR_ANENABLE);
- udelay(10000);
- }
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* GP = general purpose, SP = special purpose (on chip peripheral) */
-
-/* bits that can have a special purpose or can be configured as inputs/outputs */
-#define PA_GP_INMASK 0
-#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
-#define PA_SP_MASK 0
-#define PA_ODR_VAL 0
-#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15))
-#define PA_SP_DIRVAL 0
-
-#define PB_GP_INMASK _B(28)
-#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
-#define PB_SP_MASK (_BR(22, 25))
-#define PB_ODR_VAL 0
-#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30))
-#define PB_SP_DIRVAL 0
-
-#if CONFIG_NETPHONE_VERSION == 1
-#define PC_GP_INMASK _BW(12)
-#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15))
-#elif CONFIG_NETPHONE_VERSION == 2
-#define PC_GP_INMASK (_BW(13) | _BW(15))
-#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12))
-#endif
-#define PC_SP_MASK 0
-#define PC_SOVAL 0
-#define PC_INTVAL 0
-#define PC_GP_OUTVAL (_BW(10) | _BW(11))
-#define PC_SP_DIRVAL 0
-
-#if CONFIG_NETPHONE_VERSION == 1
-#define PE_GP_INMASK _B(31)
-#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
-#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28))
-#elif CONFIG_NETPHONE_VERSION == 2
-#define PE_GP_INMASK _BR(28, 31)
-#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
-#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27))
-#endif
-#define PE_SP_MASK 0
-#define PE_ODR_VAL 0
-#define PE_SP_DIRVAL 0
-
-int board_early_init_f(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile iop8xx_t *ioport = &immap->im_ioport;
- volatile cpm8xx_t *cpm = &immap->im_cpm;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- /* NAND chip select */
-#if CONFIG_NETPHONE_VERSION == 1
- memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
- memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
-#elif CONFIG_NETPHONE_VERSION == 2
- upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
- memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
- memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
- memctl->memc_mamr = 0; /* all clear */
-#endif
-
- /* DSP chip select */
- memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
- memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
-
-#if CONFIG_NETPHONE_VERSION == 1
- memctl->memc_br4 &= ~BR_V;
-#endif
- memctl->memc_br5 &= ~BR_V;
- memctl->memc_br6 &= ~BR_V;
- memctl->memc_br7 &= ~BR_V;
-
- ioport->iop_padat = PA_GP_OUTVAL;
- ioport->iop_paodr = PA_ODR_VAL;
- ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
- ioport->iop_papar = PA_SP_MASK;
-
- cpm->cp_pbdat = PB_GP_OUTVAL;
- cpm->cp_pbodr = PB_ODR_VAL;
- cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
- cpm->cp_pbpar = PB_SP_MASK;
-
- ioport->iop_pcdat = PC_GP_OUTVAL;
- ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
- ioport->iop_pcso = PC_SOVAL;
- ioport->iop_pcint = PC_INTVAL;
- ioport->iop_pcpar = PC_SP_MASK;
-
- cpm->cp_pedat = PE_GP_OUTVAL;
- cpm->cp_peodr = PE_ODR_VAL;
- cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
- cpm->cp_pepar = PE_SP_MASK;
-
- return 0;
-}
-
-#ifdef CONFIG_HW_WATCHDOG
-
-void hw_watchdog_reset(void)
-{
- /* XXX add here the really funky stuff */
-}
-
-#endif
-
-#ifdef CONFIG_SHOW_ACTIVITY
-
-static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ; /* poll */
-
-/* called from timer interrupt every 1/CONFIG_SYS_HZ sec */
-void board_show_activity(ulong timestamp)
-{
- if (left_to_poll > -PHONE_CONSOLE_POLL_HZ)
- --left_to_poll;
-}
-
-extern void phone_console_do_poll(void);
-
-static void do_poll(void)
-{
- unsigned int base;
-
- while (left_to_poll <= 0) {
- phone_console_do_poll();
- base = left_to_poll + PHONE_CONSOLE_POLL_HZ;
- do {
- left_to_poll = base;
- } while (base != left_to_poll);
- }
-}
-
-/* called when looping */
-void show_activity(int arg)
-{
- do_poll();
-}
-
-#endif
-
-#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
-int overwrite_console(void)
-{
- /* printf("overwrite_console called\n"); */
- return 0;
-}
-#endif
-
-extern int drv_phone_init(void);
-extern int drv_phone_use_me(void);
-extern int drv_phone_is_idle(void);
-
-int misc_init_r(void)
-{
- return drv_phone_init();
-}
-
-int last_stage_init(void)
-{
- int i;
-
-#if CONFIG_NETPHONE_VERSION == 2
- /* assert peripheral reset */
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
- for (i = 0; i < 10; i++)
- udelay(1000);
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |= _BW(12);
-#endif
- reset_phys();
-
- /* check in order to enable the local console */
- left_to_poll = PHONE_CONSOLE_POLL_HZ;
- i = CONFIG_SYS_HZ * 2;
- while (i > 0) {
-
- if (tstc()) {
- getc();
- break;
- }
-
- do_poll();
-
- if (drv_phone_use_me()) {
- status_led_set(0, STATUS_LED_ON);
- while (!drv_phone_is_idle()) {
- do_poll();
- udelay(1000000 / CONFIG_SYS_HZ);
- }
-
- console_assign(stdin, "phone");
- console_assign(stdout, "phone");
- console_assign(stderr, "phone");
- setenv("bootdelay", "-1");
- break;
- }
-
- udelay(1000000 / CONFIG_SYS_HZ);
- i--;
- left_to_poll--;
- }
- left_to_poll = PHONE_CONSOLE_POLL_HZ;
-
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2004 Intracom S.A.
- * Pantelis Antoniou <panto@intracom.gr>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * phone_console.c
- *
- * A phone based console
- *
- * Virtual display of 80x24 characters.
- * The actual display is much smaller and panned to show the virtual one.
- * Input is made by a numeric keypad utilizing the input method of
- * mobile phones. Sorry no T9 lexicons...
- *
- */
-
-#include <common.h>
-
-#include <version.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-
-#include <sed156x.h>
-
-/*************************************************************************************************/
-
-#define ROWS 24
-#define COLS 80
-
-#define REFRESH_HZ (CONFIG_SYS_HZ/50) /* refresh every 20ms */
-#define BLINK_HZ (CONFIG_SYS_HZ/2) /* cursor blink every 500ms */
-
-/*************************************************************************************************/
-
-#define DISPLAY_BACKLIT_PORT ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat
-#define DISPLAY_BACKLIT_MASK 0x0010
-
-/*************************************************************************************************/
-
-#define KP_STABLE_HZ (CONFIG_SYS_HZ/100) /* stable for 10ms */
-#define KP_REPEAT_DELAY_HZ (CONFIG_SYS_HZ/4) /* delay before repeat 250ms */
-#define KP_REPEAT_HZ (CONFIG_SYS_HZ/20) /* repeat every 50ms */
-#define KP_FORCE_DELAY_HZ (CONFIG_SYS_HZ/2) /* key was force pressed */
-#define KP_IDLE_DELAY_HZ (CONFIG_SYS_HZ/2) /* key was released and idle */
-
-#if CONFIG_NETPHONE_VERSION == 1
-#define KP_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
-#define KP_SPI_RXD_MASK 0x0008
-
-#define KP_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
-#define KP_SPI_TXD_MASK 0x0004
-
-#define KP_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
-#define KP_SPI_CLK_MASK 0x0001
-#elif CONFIG_NETPHONE_VERSION == 2
-#define KP_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define KP_SPI_RXD_MASK 0x00000008
-
-#define KP_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define KP_SPI_TXD_MASK 0x00000004
-
-#define KP_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define KP_SPI_CLK_MASK 0x00000002
-#endif
-
-#define KP_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat)
-#define KP_CS_MASK 0x00000010
-
-#define KP_SPI_RXD() (KP_SPI_RXD_PORT & KP_SPI_RXD_MASK)
-
-#define KP_SPI_TXD(x) \
- do { \
- if (x) \
- KP_SPI_TXD_PORT |= KP_SPI_TXD_MASK; \
- else \
- KP_SPI_TXD_PORT &= ~KP_SPI_TXD_MASK; \
- } while(0)
-
-#define KP_SPI_CLK(x) \
- do { \
- if (x) \
- KP_SPI_CLK_PORT |= KP_SPI_CLK_MASK; \
- else \
- KP_SPI_CLK_PORT &= ~KP_SPI_CLK_MASK; \
- } while(0)
-
-#define KP_SPI_CLK_TOGGLE() (KP_SPI_CLK_PORT ^= KP_SPI_CLK_MASK)
-
-#define KP_SPI_BIT_DELAY() /* no delay */
-
-#define KP_CS(x) \
- do { \
- if (x) \
- KP_CS_PORT |= KP_CS_MASK; \
- else \
- KP_CS_PORT &= ~KP_CS_MASK; \
- } while(0)
-
-#define KP_ROWS 7
-#define KP_COLS 4
-
-#define KP_ROWS_MASK ((1 << KP_ROWS) - 1)
-#define KP_COLS_MASK ((1 << KP_COLS) - 1)
-
-#define SCAN 0
-#define SCAN_FILTER 1
-#define SCAN_COL 2
-#define SCAN_COL_FILTER 3
-#define PRESSED 4
-
-#define KP_F1 0 /* leftmost dot (tab) */
-#define KP_F2 1 /* middle left dot */
-#define KP_F3 2 /* up */
-#define KP_F4 3 /* middle right dot */
-#define KP_F5 4 /* rightmost dot */
-#define KP_F6 5 /* C */
-#define KP_F7 6 /* left */
-#define KP_F8 7 /* down */
-#define KP_F9 8 /* right */
-#define KP_F10 9 /* enter */
-#define KP_F11 10 /* R */
-#define KP_F12 11 /* save */
-#define KP_F13 12 /* redial */
-#define KP_F14 13 /* speaker */
-#define KP_F15 14 /* unused */
-#define KP_F16 15 /* unused */
-
-#define KP_RELEASE -1 /* key depressed */
-#define KP_FORCE -2 /* key was pressed for more than force hz */
-#define KP_IDLE -3 /* key was released and idle */
-
-#define KP_1 '1'
-#define KP_2 '2'
-#define KP_3 '3'
-#define KP_4 '4'
-#define KP_5 '5'
-#define KP_6 '6'
-#define KP_7 '7'
-#define KP_8 '8'
-#define KP_9 '9'
-#define KP_0 '0'
-#define KP_STAR '*'
-#define KP_HASH '#'
-
-/*************************************************************************************************/
-
-static int curs_disabled;
-static int curs_col, curs_row;
-static int disp_col, disp_row;
-
-static int width, height;
-
-/* the simulated vty buffer */
-static char vty_buf[ROWS * COLS];
-static char last_visible_buf[ROWS * COLS]; /* worst case */
-static char *last_visible_curs_ptr;
-static int last_visible_curs_rev;
-static int blinked_state;
-static int last_input_mode;
-static int refresh_time;
-static int blink_time;
-static char last_fast_punct;
-
-/*************************************************************************************************/
-
-#define IM_SMALL 0
-#define IM_CAPITAL 1
-#define IM_NUMBER 2
-
-static int input_mode;
-static char fast_punct;
-static int tab_indicator;
-static const char *fast_punct_list = ",.:;*";
-
-static const char *input_mode_txt[] = { "abc", "ABC", "123" };
-
-static const char *punct = ".,!;?'\"-()@/:_+&%*=<>$[]{}\\~^#|";
-static const char *whspace = " 0\n";
-/* per mode character select (for 2-9) */
-static const char *digits_sel[2][8] = {
- { /* small */
- "abc2", /* 2 */
- "def3", /* 3 */
- "ghi4", /* 4 */
- "jkl5", /* 5 */
- "mno6", /* 6 */
- "pqrs7", /* 7 */
- "tuv8", /* 8 */
- "wxyz9", /* 9 */
- }, { /* capital */
- "ABC2", /* 2 */
- "DEF3", /* 3 */
- "GHI4", /* 4 */
- "JKL5", /* 5 */
- "MNO6", /* 6 */
- "PQRS7", /* 7 */
- "TUV8", /* 8 */
- "WXYZ9", /* 9 */
- }
-};
-
-/*****************************************************************************/
-
-static void update(void);
-static void ensure_visible(int col, int row, int dx, int dy);
-
-static void console_init(void)
-{
- curs_disabled = 0;
- curs_col = 0;
- curs_row = 0;
-
- disp_col = 0;
- disp_row = 0;
-
- input_mode = IM_SMALL;
- fast_punct = ',';
- last_fast_punct = '\0';
- refresh_time = REFRESH_HZ;
- blink_time = BLINK_HZ;
-
- memset(vty_buf, ' ', sizeof(vty_buf));
-
- memset(last_visible_buf, ' ', sizeof(last_visible_buf));
- last_visible_curs_ptr = NULL;
- last_input_mode = -1;
- last_visible_curs_rev = 0;
-
- blinked_state = 0;
-
- sed156x_init();
- width = sed156x_text_width;
- height = sed156x_text_height - 1;
-
- tab_indicator = 0;
-}
-
-/*****************************************************************************/
-
-void phone_putc(const char c);
-
-/*****************************************************************************/
-
-static int queued_char = -1;
-static int enabled = 0;
-
-/*****************************************************************************/
-
-/* flush buffers */
-int phone_start(void)
-{
- console_init();
-
- update();
- sed156x_sync();
-
- enabled = 1;
- queued_char = 'U' - '@';
-
- /* backlit on */
- DISPLAY_BACKLIT_PORT &= ~DISPLAY_BACKLIT_MASK;
-
- return 0;
-}
-
-int phone_stop(void)
-{
- enabled = 0;
-
- sed156x_clear();
- sed156x_sync();
-
- /* backlit off */
- DISPLAY_BACKLIT_PORT |= DISPLAY_BACKLIT_MASK;
-
- return 0;
-}
-
-void phone_puts(const char *s)
-{
- int count = strlen(s);
-
- while (count--)
- phone_putc(*s++);
-}
-
-int phone_tstc(void)
-{
- return queued_char >= 0 ? 1 : 0;
-}
-
-int phone_getc(void)
-{
- int r;
-
- if (queued_char < 0)
- return -1;
-
- r = queued_char;
- queued_char = -1;
-
- return r;
-}
-
-/*****************************************************************************/
-
-int drv_phone_init(void)
-{
- struct stdio_dev console_dev;
-
- console_init();
-
- memset(&console_dev, 0, sizeof(console_dev));
- strcpy(console_dev.name, "phone");
- console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */
- console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
- console_dev.start = phone_start;
- console_dev.stop = phone_stop;
- console_dev.putc = phone_putc; /* 'putc' function */
- console_dev.puts = phone_puts; /* 'puts' function */
- console_dev.tstc = phone_tstc; /* 'tstc' function */
- console_dev.getc = phone_getc; /* 'getc' function */
-
- if (stdio_register(&console_dev) == 0)
- return 1;
-
- return 0;
-}
-
-static int use_me;
-
-int drv_phone_use_me(void)
-{
- return use_me;
-}
-
-static void kp_do_poll(void);
-
-void phone_console_do_poll(void)
-{
- int i, x, y;
-
- kp_do_poll();
-
- if (enabled) {
- /* do the blink */
- blink_time -= PHONE_CONSOLE_POLL_HZ;
- if (blink_time <= 0) {
- blink_time += BLINK_HZ;
- if (last_visible_curs_ptr) {
- i = last_visible_curs_ptr - last_visible_buf;
- x = i % width; y = i / width;
- sed156x_reverse_at(x, y, 1);
- last_visible_curs_rev ^= 1;
- }
- }
-
- /* do the refresh */
- refresh_time -= PHONE_CONSOLE_POLL_HZ;
- if (refresh_time <= 0) {
- refresh_time += REFRESH_HZ;
- sed156x_sync();
- }
- }
-
-}
-
-static int last_scancode = -1;
-static int forced_scancode = 0;
-static int input_state = -1;
-static int input_scancode = -1;
-static int input_selected_char = -1;
-static char input_covered_char;
-
-static void putchar_at_cursor(char c)
-{
- vty_buf[curs_row * COLS + curs_col] = c;
- ensure_visible(curs_col, curs_row, 1, 1);
-}
-
-static char getchar_at_cursor(void)
-{
- return vty_buf[curs_row * COLS + curs_col];
-}
-
-static void queue_input_char(char c)
-{
- if (c <= 0)
- return;
-
- queued_char = c;
-}
-
-static void terminate_input(void)
-{
- if (input_state < 0)
- return;
-
- if (input_selected_char >= 0)
- queue_input_char(input_selected_char);
-
- input_state = -1;
- input_selected_char = -1;
- putchar_at_cursor(input_covered_char);
-
- curs_disabled = 0;
- blink_time = BLINK_HZ;
- update();
-}
-
-static void handle_enabled_scancode(int scancode)
-{
- char c;
- int new_disp_col, new_disp_row;
- const char *sel;
-
-
- switch (scancode) {
-
- /* key was released */
- case KP_RELEASE:
- forced_scancode = 0;
- break;
-
- /* key was forced */
- case KP_FORCE:
-
- switch (last_scancode) {
- case '#':
- if (input_mode == IM_NUMBER) {
- input_mode = IM_CAPITAL;
- /* queue backspace to erase # */
- queue_input_char('\b');
- } else {
- input_mode = IM_NUMBER;
- fast_punct = '*';
- }
- update();
- break;
-
- case '0': case '1':
- case '2': case '3': case '4': case '5':
- case '6': case '7': case '8': case '9':
-
- if (input_state < 0)
- break;
-
- input_selected_char = last_scancode;
- putchar_at_cursor((char)input_selected_char);
- terminate_input();
-
- break;
-
- default:
- break;
- }
-
- break;
-
- /* release and idle */
- case KP_IDLE:
- input_scancode = -1;
- if (input_state < 0)
- break;
- terminate_input();
- break;
-
- /* change input mode */
- case '#':
- if (last_scancode == '#') /* no repeat */
- break;
-
- if (input_mode == IM_NUMBER) {
- input_scancode = scancode;
- input_state = 0;
- input_selected_char = scancode;
- input_covered_char = getchar_at_cursor();
- putchar_at_cursor((char)input_selected_char);
- terminate_input();
- break;
- }
-
- if (input_mode == IM_SMALL)
- input_mode = IM_CAPITAL;
- else
- input_mode = IM_SMALL;
-
- update();
- break;
-
- case '*':
- /* no repeat */
- if (last_scancode == scancode)
- break;
-
- if (input_state >= 0)
- terminate_input();
-
- input_scancode = fast_punct;
- input_state = 0;
- input_selected_char = input_scancode;
- input_covered_char = getchar_at_cursor();
- putchar_at_cursor((char)input_selected_char);
- terminate_input();
-
- break;
-
- case '0': case '1':
- case '2': case '3': case '4': case '5':
- case '6': case '7': case '8': case '9':
-
- /* no repeat */
- if (last_scancode == scancode)
- break;
-
- if (input_mode == IM_NUMBER) {
- input_scancode = scancode;
- input_state = 0;
- input_selected_char = scancode;
- input_covered_char = getchar_at_cursor();
- putchar_at_cursor((char)input_selected_char);
- terminate_input();
- break;
- }
-
- if (input_state >= 0 && input_scancode != scancode)
- terminate_input();
-
- if (input_state < 0) {
- curs_disabled = 1;
- input_scancode = scancode;
- input_state = 0;
- input_covered_char = getchar_at_cursor();
- } else
- input_state++;
-
- if (scancode == '0')
- sel = whspace;
- else if (scancode == '1')
- sel = punct;
- else
- sel = digits_sel[input_mode][scancode - '2'];
- c = *(sel + input_state);
- if (c == '\0') {
- input_state = 0;
- c = *sel;
- }
-
- input_selected_char = (int)c;
- putchar_at_cursor((char)input_selected_char);
- update();
-
- break;
-
- /* move visible display */
- case KP_F3: case KP_F8: case KP_F7: case KP_F9:
-
- new_disp_col = disp_col;
- new_disp_row = disp_row;
-
- switch (scancode) {
- /* up */
- case KP_F3:
- if (new_disp_row <= 0)
- break;
- new_disp_row--;
- break;
-
- /* down */
- case KP_F8:
- if (new_disp_row >= ROWS - height)
- break;
- new_disp_row++;
- break;
-
- /* left */
- case KP_F7:
- if (new_disp_col <= 0)
- break;
- new_disp_col--;
- break;
-
- /* right */
- case KP_F9:
- if (new_disp_col >= COLS - width)
- break;
- new_disp_col++;
- break;
- }
-
- /* no change? */
- if (disp_col == new_disp_col && disp_row == new_disp_row)
- break;
-
- disp_col = new_disp_col;
- disp_row = new_disp_row;
- update();
-
- break;
-
- case KP_F6: /* backspace */
- /* inputing something; no backspace sent, just cancel input */
- if (input_state >= 0) {
- input_selected_char = -1; /* cancel */
- terminate_input();
- break;
- }
- queue_input_char('\b');
- break;
-
- case KP_F10: /* enter */
- /* inputing something; first cancel input */
- if (input_state >= 0)
- terminate_input();
- queue_input_char('\r');
- break;
-
- case KP_F11: /* R -> Ctrl-C (abort) */
- if (input_state >= 0)
- terminate_input();
- queue_input_char('C' - 'Q'); /* ctrl-c */
- break;
-
- case KP_F5: /* F% -> Ctrl-U (clear line) */
- if (input_state >= 0)
- terminate_input();
- queue_input_char('U' - 'Q'); /* ctrl-c */
- break;
-
-
- case KP_F1: /* tab */
- /* inputing something; first cancel input */
- if (input_state >= 0)
- terminate_input();
- queue_input_char('\t');
- break;
-
- case KP_F2: /* change fast punct */
- sel = strchr(fast_punct_list, fast_punct);
- if (sel == NULL)
- sel = &fast_punct_list[0];
- sel++;
- if (*sel == '\0')
- sel = &fast_punct_list[0];
- fast_punct = *sel;
- update();
- break;
-
-
- }
-
- if (scancode != KP_FORCE && scancode != KP_IDLE) /* don't record forced or idle scancode */
- last_scancode = scancode;
-}
-
-static void scancode_action(int scancode)
-{
-#if 0
- if (scancode == KP_RELEASE)
- printf(" RELEASE\n");
- else if (scancode == KP_FORCE)
- printf(" FORCE\n");
- else if (scancode == KP_IDLE)
- printf(" IDLE\n");
- else if (scancode < 32)
- printf(" F%d", scancode + 1);
- else
- printf(" %c", (char)scancode);
- printf("\n");
-#endif
-
- if (enabled) {
- handle_enabled_scancode(scancode);
- return;
- }
-
- if (scancode == KP_FORCE && last_scancode == '*')
- use_me = 1;
-
- last_scancode = scancode;
-}
-
-/**************************************************************************************/
-
-/* update the display; make sure to update only the differences */
-static void update(void)
-{
- int i;
- char *s, *e, *t, *r, *b, *cp;
-
- if (input_mode != last_input_mode)
- sed156x_output_at(sed156x_text_width - 3, sed156x_text_height - 1, input_mode_txt[input_mode], 3);
-
- if (tab_indicator == 0) {
- sed156x_output_at(0, sed156x_text_height - 1, "\\t", 2);
- tab_indicator = 1;
- }
-
- if (fast_punct != last_fast_punct)
- sed156x_output_at(4, sed156x_text_height - 1, &fast_punct, 1);
-
- if (curs_disabled ||
- curs_col < disp_col || curs_col >= (disp_col + width) ||
- curs_row < disp_row || curs_row >= (disp_row + height)) {
- cp = NULL;
- } else
- cp = last_visible_buf + (curs_row - disp_row) * width + (curs_col - disp_col);
-
-
- /* printf("(%d,%d) (%d,%d) %s\n", curs_col, curs_row, disp_col, disp_row, cp ? "YES" : "no"); */
-
- /* clear previous cursor */
- if (last_visible_curs_ptr && last_visible_curs_rev == 0) {
- i = last_visible_curs_ptr - last_visible_buf;
- sed156x_reverse_at(i % width, i / width, 1);
- }
-
- b = vty_buf + disp_row * COLS + disp_col;
- t = last_visible_buf;
- for (i = 0; i < height; i++) {
- s = b;
- e = b + width;
- /* update only the differences */
- do {
- while (s < e && *s == *t) {
- s++;
- t++;
- }
- if (s == e) /* no more */
- break;
-
- /* find run */
- r = s;
- while (s < e && *s != *t)
- *t++ = *s++;
-
- /* and update */
- sed156x_output_at(r - b, i, r, s - r);
-
- } while (s < e);
-
- b += COLS;
- }
-
- /* set cursor */
- if (cp) {
- last_visible_curs_ptr = cp;
- i = last_visible_curs_ptr - last_visible_buf;
- sed156x_reverse_at(i % width, i / width, 1);
- last_visible_curs_rev = 0;
- } else {
- last_visible_curs_ptr = NULL;
- }
-
- last_input_mode = input_mode;
- last_fast_punct = fast_punct;
-}
-
-/* ensure visibility; the trick is to minimize the screen movement */
-static void ensure_visible(int col, int row, int dx, int dy)
-{
- int x1, y1, x2, y2, a1, b1, a2, b2;
-
- /* clamp visible region */
- if (col < 0) {
- dx -= col;
- col = 0;
- if (dx <= 0)
- dx = 1;
- }
-
- if (row < 0) {
- dy -= row;
- row = 0;
- if (dy <= 0)
- dy = 1;
- }
-
- if (col + dx > COLS)
- dx = COLS - col;
-
- if (row + dy > ROWS)
- dy = ROWS - row;
-
-
- /* move to easier to use vars */
- x1 = disp_col; y1 = disp_row;
- x2 = x1 + width; y2 = y1 + height;
- a1 = col; b1 = row;
- a2 = a1 + dx; b2 = b1 + dy;
-
- /* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */
-
- if (a2 > x2) {
- /* move to the right */
- x2 = a2;
- x1 = x2 - width;
- if (x1 < 0) {
- x1 = 0;
- x2 = width;
- }
- } else if (a1 < x1) {
- /* move to the left */
- x1 = a1;
- x2 = x1 + width;
- if (x2 > COLS) {
- x2 = COLS;
- x1 = x2 - width;
- }
- }
-
- if (b2 > y2) {
- /* move down */
- y2 = b2;
- y1 = y2 - height;
- if (y1 < 0) {
- y1 = 0;
- y2 = height;
- }
- } else if (b1 < y1) {
- /* move up */
- y1 = b1;
- y2 = y1 + width;
- if (y2 > ROWS) {
- y2 = ROWS;
- y1 = y2 - height;
- }
- }
-
- /* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */
-
- /* no movement? */
- if (disp_col == x1 && disp_row == y1)
- return;
-
- disp_col = x1;
- disp_row = y1;
-}
-
-/**************************************************************************************/
-
-static void newline(void)
-{
- curs_col = 0;
- if (curs_row + 1 < ROWS)
- curs_row++;
- else {
- memmove(vty_buf, vty_buf + COLS, COLS * (ROWS - 1));
- memset(vty_buf + (ROWS - 1) * COLS, ' ', COLS);
- }
-}
-
-void phone_putc(const char c)
-{
- int i;
-
- if (input_mode != -1) {
- input_selected_char = -1;
- terminate_input();
- }
-
- curs_disabled = 1;
- update();
-
- blink_time = BLINK_HZ;
-
- switch (c) {
- case '\a': /* ignore bell */
- case '\r': /* ignore carriage return */
- break;
-
- case '\n': /* next line */
- newline();
- ensure_visible(curs_col, curs_row, 1, 1);
- break;
-
- case 9: /* tab 8 */
- /* move to tab */
- i = curs_col;
- i |= 0x0008;
- i &= ~0x0007;
-
- if (i < COLS)
- curs_col = i;
- else
- newline();
-
- ensure_visible(curs_col, curs_row, 1, 1);
- break;
-
- case 8: /* backspace */
- if (curs_col <= 0)
- break;
- curs_col--;
-
- /* make sure that we see a couple of characters before */
- if (curs_col > 4)
- ensure_visible(curs_col - 4, curs_row, 4, 1);
- else
- ensure_visible(curs_col, curs_row, 1, 1);
-
- break;
-
- default: /* draw the char */
- putchar_at_cursor(c);
-
- /*
- * check for newline
- */
- if (curs_col + 1 < COLS)
- curs_col++;
- else
- newline();
-
- ensure_visible(curs_col, curs_row, 1, 1);
-
- break;
- }
-
- curs_disabled = 0;
- blink_time = BLINK_HZ;
- update();
-}
-
-/**************************************************************************************/
-
-static inline unsigned int kp_transfer(unsigned int val)
-{
- unsigned int rx;
- int b;
-
- rx = 0; b = 8;
- while (--b >= 0) {
- KP_SPI_TXD(val & 0x80);
- val <<= 1;
- KP_SPI_CLK_TOGGLE();
- KP_SPI_BIT_DELAY();
- rx <<= 1;
- if (KP_SPI_RXD())
- rx |= 1;
- KP_SPI_CLK_TOGGLE();
- KP_SPI_BIT_DELAY();
- }
-
- return rx;
-}
-
-unsigned int kp_data_transfer(unsigned int val)
-{
- KP_SPI_CLK(1);
- KP_CS(0);
- val = kp_transfer(val);
- KP_CS(1);
-
- return val;
-}
-
-unsigned int kp_get_col_mask(unsigned int row_mask)
-{
- unsigned int val, col_mask;
-
- val = 0x80 | (row_mask & 0x7F);
- (void)kp_data_transfer(val);
-#if CONFIG_NETPHONE_VERSION == 1
- col_mask = kp_data_transfer(val) & 0x0F;
-#elif CONFIG_NETPHONE_VERSION == 2
- col_mask = ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & 0x0f;
- /* XXX FUCK FUCK FUCK FUCK FUCK!!!! */
- col_mask = ((col_mask & 0x08) >> 3) | /* BKBR1 */
- ((col_mask & 0x04) << 1) | /* BKBR2 */
- (col_mask & 0x02) | /* BKBR3 */
- ((col_mask & 0x01) << 2); /* BKBR4 */
-
-#endif
- /* printf("col_mask(row_mask = 0x%x) -> col_mask = 0x%x\n", row_mask, col_mask); */
-
- return col_mask;
-}
-
-/**************************************************************************************/
-
-static const int kp_scancodes[KP_ROWS * KP_COLS] = {
- KP_F1, KP_F3, KP_F4, KP_F2,
- KP_F6, KP_F8, KP_F9, KP_F7,
- KP_1, KP_3, KP_F11, KP_2,
- KP_4, KP_6, KP_F12, KP_5,
- KP_7, KP_9, KP_F13, KP_8,
- KP_STAR, KP_HASH, KP_F14, KP_0,
- KP_F5, KP_F15, KP_F16, KP_F10,
-};
-
-static const int kp_repeats[KP_ROWS * KP_COLS] = {
- 0, 1, 0, 0,
- 0, 1, 1, 1,
- 1, 1, 0, 1,
- 1, 1, 0, 1,
- 1, 1, 0, 1,
- 1, 1, 0, 1,
- 0, 0, 0, 1,
-};
-
-static int kp_state = SCAN;
-static int kp_last_col_mask;
-static int kp_cur_row, kp_cur_col;
-static int kp_scancode;
-static int kp_stable;
-static int kp_repeat;
-static int kp_repeat_time;
-static int kp_force_time;
-static int kp_idle_time;
-
-static void kp_do_poll(void)
-{
- unsigned int col_mask;
- int col;
-
- switch (kp_state) {
- case SCAN:
- if (kp_idle_time > 0) {
- kp_idle_time -= PHONE_CONSOLE_POLL_HZ;
- if (kp_idle_time <= 0)
- scancode_action(KP_IDLE);
- }
-
- col_mask = kp_get_col_mask(KP_ROWS_MASK);
- if (col_mask == KP_COLS_MASK)
- break; /* nothing */
- kp_last_col_mask = col_mask;
- kp_stable = 0;
- kp_state = SCAN_FILTER;
- break;
-
- case SCAN_FILTER:
- col_mask = kp_get_col_mask(KP_ROWS_MASK);
- if (col_mask != kp_last_col_mask) {
- kp_state = SCAN;
- break;
- }
-
- kp_stable += PHONE_CONSOLE_POLL_HZ;
- if (kp_stable < KP_STABLE_HZ)
- break;
-
- kp_cur_row = 0;
- kp_stable = 0;
- kp_state = SCAN_COL;
-
- (void)kp_get_col_mask(1 << kp_cur_row);
- break;
-
- case SCAN_COL:
- col_mask = kp_get_col_mask(1 << kp_cur_row);
- if (col_mask == KP_COLS_MASK) {
- if (++kp_cur_row >= KP_ROWS) {
- kp_state = SCAN;
- break;
- }
- kp_get_col_mask(1 << kp_cur_row);
- break;
- }
- kp_last_col_mask = col_mask;
- kp_stable = 0;
- kp_state = SCAN_COL_FILTER;
- break;
-
- case SCAN_COL_FILTER:
- col_mask = kp_get_col_mask(1 << kp_cur_row);
- if (col_mask != kp_last_col_mask || col_mask == KP_COLS_MASK) {
- kp_state = SCAN;
- break;
- }
-
- kp_stable += PHONE_CONSOLE_POLL_HZ;
- if (kp_stable < KP_STABLE_HZ)
- break;
-
- for (col = 0; col < KP_COLS; col++)
- if ((col_mask & (1 << col)) == 0)
- break;
- kp_cur_col = col;
- kp_state = PRESSED;
- kp_scancode = kp_scancodes[kp_cur_row * KP_COLS + kp_cur_col];
- kp_repeat = kp_repeats[kp_cur_row * KP_COLS + kp_cur_col];
-
- if (kp_repeat)
- kp_repeat_time = KP_REPEAT_DELAY_HZ;
- kp_force_time = KP_FORCE_DELAY_HZ;
-
- scancode_action(kp_scancode);
-
- break;
-
- case PRESSED:
- col_mask = kp_get_col_mask(1 << kp_cur_row);
- if (col_mask != kp_last_col_mask) {
- kp_state = SCAN;
- scancode_action(KP_RELEASE);
- kp_idle_time = KP_IDLE_DELAY_HZ;
- break;
- }
-
- if (kp_repeat) {
- kp_repeat_time -= PHONE_CONSOLE_POLL_HZ;
- if (kp_repeat_time <= 0) {
- kp_repeat_time += KP_REPEAT_HZ;
- scancode_action(kp_scancode);
- }
- }
-
- if (kp_force_time > 0) {
- kp_force_time -= PHONE_CONSOLE_POLL_HZ;
- if (kp_force_time <= 0)
- scancode_action(KP_FORCE);
- }
-
- break;
- }
-}
-
-/**************************************************************************************/
-
-int drv_phone_is_idle(void)
-{
- return kp_state == SCAN;
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = netta.o flash.o dsp.o codec.o pcmcia.o
+++ /dev/null
-/*
- * CODEC
- */
-
-#include <common.h>
-#include <post.h>
-
-#include "mpc8xx.h"
-
-/***********************************************/
-
-#define MAX_DUSLIC 4
-
-#define NUM_CHANNELS 2
-#define MAX_SLICS (MAX_DUSLIC * NUM_CHANNELS)
-
-/***********************************************/
-
-#define SOP_READ_CH_0 0xC4 /* Read SOP Register for Channel A */
-#define SOP_READ_CH_1 0xCC /* Read SOP Register for Channel B */
-#define SOP_WRITE_CH_0 0x44 /* Write SOP Register for Channel A */
-#define SOP_WRITE_CH_1 0x4C /* Write SOP Register for Channel B */
-
-#define COP_READ_CH_0 0xC5
-#define COP_READ_CH_1 0xCD
-#define COP_WRITE_CH_0 0x45
-#define COP_WRITE_CH_1 0x4D
-
-#define POP_READ_CH_0 0xC6
-#define POP_READ_CH_1 0xCE
-#define POP_WRITE_CH_0 0x46
-#define POP_WRITE_CH_1 0x4E
-
-#define RST_CMD_DUSLIC_CHIP 0x40 /* OR 0x48 */
-#define RST_CMD_DUSLIC_CH_A 0x41
-#define RST_CMD_DUSLIC_CH_B 0x49
-
-#define PCM_RESYNC_CMD_CH_A 0x42
-#define PCM_RESYNC_CMD_CH_B 0x4A
-
-#define ACTIVE_HOOK_LEV_4 0
-#define ACTIVE_HOOK_LEV_12 1
-
-#define SLIC_P_NORMAL 0x01
-
-/************************************************/
-
-#define CODSP_WR 0x00
-#define CODSP_RD 0x80
-#define CODSP_OP 0x40
-#define CODSP_ADR(x) (((unsigned char)(x) & 7) << 3)
-#define CODSP_M(x) ((unsigned char)(x) & 7)
-#define CODSP_CMD(x) ((unsigned char)(x) & 7)
-
-/************************************************/
-
-/* command indication ops */
-#define CODSP_M_SLEEP_PWRDN 7
-#define CODSP_M_PWRDN_HIZ 0
-#define CODSP_M_ANY_ACT 2
-#define CODSP_M_RING 5
-#define CODSP_M_ACT_MET 6
-#define CODSP_M_GND_START 4
-#define CODSP_M_RING_PAUSE 1
-
-/* single byte commands */
-#define CODSP_CMD_SOFT_RESET CODSP_CMD(0)
-#define CODSP_CMD_RESET_CH CODSP_CMD(1)
-#define CODSP_CMD_RESYNC CODSP_CMD(2)
-
-/* two byte commands */
-#define CODSP_CMD_SOP CODSP_CMD(4)
-#define CODSP_CMD_COP CODSP_CMD(5)
-#define CODSP_CMD_POP CODSP_CMD(6)
-
-/************************************************/
-
-/* read as 4-bytes */
-#define CODSP_INTREG_INT_CH 0x80000000
-#define CODSP_INTREG_HOOK 0x40000000
-#define CODSP_INTREG_GNDK 0x20000000
-#define CODSP_INTREG_GNDP 0x10000000
-#define CODSP_INTREG_ICON 0x08000000
-#define CODSP_INTREG_VRTLIM 0x04000000
-#define CODSP_INTREG_OTEMP 0x02000000
-#define CODSP_INTREG_SYNC_FAIL 0x01000000
-#define CODSP_INTREG_LM_THRES 0x00800000
-#define CODSP_INTREG_READY 0x00400000
-#define CODSP_INTREG_RSTAT 0x00200000
-#define CODSP_INTREG_LM_OK 0x00100000
-#define CODSP_INTREG_IO4_DU 0x00080000
-#define CODSP_INTREG_IO3_DU 0x00040000
-#define CODSP_INTREG_IO2_DU 0x00020000
-#define CODSP_INTREG_IO1_DU 0x00010000
-#define CODSP_INTREG_DTMF_OK 0x00008000
-#define CODSP_INTREG_DTMF_KEY4 0x00004000
-#define CODSP_INTREG_DTMF_KEY3 0x00002000
-#define CODSP_INTREG_DTMF_KEY2 0x00001000
-#define CODSP_INTREG_DTMF_KEY1 0x00000800
-#define CODSP_INTREG_DTMF_KEY0 0x00000400
-#define CODSP_INTREG_UTDR_OK 0x00000200
-#define CODSP_INTREG_UTDX_OK 0x00000100
-#define CODSP_INTREG_EDSP_FAIL 0x00000080
-#define CODSP_INTREG_CIS_BOF 0x00000008
-#define CODSP_INTREG_CIS_BUF 0x00000004
-#define CODSP_INTREG_CIS_REQ 0x00000002
-#define CODSP_INTREG_CIS_ACT 0x00000001
-
-/************************************************/
-
-/* ======== SOP REG ADDRESSES =======*/
-
-#define REVISION_ADDR 0x00
-#define PCMC1_ADDR 0x05
-#define XCR_ADDR 0x06
-#define INTREG1_ADDR 0x07
-#define INTREG2_ADDR 0x08
-#define INTREG3_ADDR 0x09
-#define INTREG4_ADDR 0x0A
-#define LMRES1_ADDR 0x0D
-#define MASK_ADDR 0x11
-#define IOCTL3_ADDR 0x14
-#define BCR1_ADDR 0x15
-#define BCR2_ADDR 0x16
-#define BCR3_ADDR 0x17
-#define BCR4_ADDR 0x18
-#define BCR5_ADDR 0x19
-#define DSCR_ADDR 0x1A
-#define LMCR1_ADDR 0x1C
-#define LMCR2_ADDR 0x1D
-#define LMCR3_ADDR 0x1E
-#define OFR1_ADDR 0x1F
-#define PCMR1_ADDR 0x21
-#define PCMX1_ADDR 0x25
-#define TSTR3_ADDR 0x2B
-#define TSTR4_ADDR 0x2C
-#define TSTR5_ADDR 0x2D
-
-/* ========= POP REG ADDRESSES ========*/
-
-#define CIS_DAT_ADDR 0x00
-
-#define LEC_LEN_ADDR 0x3A
-#define LEC_POWR_ADDR 0x3B
-#define LEC_DELP_ADDR 0x3C
-#define LEC_DELQ_ADDR 0x3D
-#define LEC_GAIN_XI_ADDR 0x3E
-#define LEC_GAIN_RI_ADDR 0x3F
-#define LEC_GAIN_XO_ADDR 0x40
-#define LEC_RES_1_ADDR 0x41
-#define LEC_RES_2_ADDR 0x42
-
-#define NLP_POW_LPF_ADDR 0x30
-#define NLP_POW_LPS_ADDR 0x31
-#define NLP_BN_LEV_X_ADDR 0x32
-#define NLP_BN_LEV_R_ADDR 0x33
-#define NLP_BN_INC_ADDR 0x34
-#define NLP_BN_DEC_ADDR 0x35
-#define NLP_BN_MAX_ADDR 0x36
-#define NLP_BN_ADJ_ADDR 0x37
-#define NLP_RE_MIN_ERLL_ADDR 0x38
-#define NLP_RE_EST_ERLL_ADDR 0x39
-#define NLP_SD_LEV_X_ADDR 0x3A
-#define NLP_SD_LEV_R_ADDR 0x3B
-#define NLP_SD_LEV_BN_ADDR 0x3C
-#define NLP_SD_LEV_RE_ADDR 0x3D
-#define NLP_SD_OT_DT_ADDR 0x3E
-#define NLP_ERL_LIN_LP_ADDR 0x3F
-#define NLP_ERL_LEC_LP_ADDR 0x40
-#define NLP_CT_LEV_RE_ADDR 0x41
-#define NLP_CTRL_ADDR 0x42
-
-#define UTD_CF_H_ADDR 0x4B
-#define UTD_CF_L_ADDR 0x4C
-#define UTD_BW_H_ADDR 0x4D
-#define UTD_BW_L_ADDR 0x4E
-#define UTD_NLEV_ADDR 0x4F
-#define UTD_SLEV_H_ADDR 0x50
-#define UTD_SLEV_L_ADDR 0x51
-#define UTD_DELT_ADDR 0x52
-#define UTD_RBRK_ADDR 0x53
-#define UTD_RTIME_ADDR 0x54
-#define UTD_EBRK_ADDR 0x55
-#define UTD_ETIME_ADDR 0x56
-
-#define DTMF_LEV_ADDR 0x30
-#define DTMF_TWI_ADDR 0x31
-#define DTMF_NCF_H_ADDR 0x32
-#define DTMF_NCF_L_ADDR 0x33
-#define DTMF_NBW_H_ADDR 0x34
-#define DTMF_NBW_L_ADDR 0x35
-#define DTMF_GAIN_ADDR 0x36
-#define DTMF_RES1_ADDR 0x37
-#define DTMF_RES2_ADDR 0x38
-#define DTMF_RES3_ADDR 0x39
-
-#define CIS_LEV_H_ADDR 0x43
-#define CIS_LEV_L_ADDR 0x44
-#define CIS_BRS_ADDR 0x45
-#define CIS_SEIZ_H_ADDR 0x46
-#define CIS_SEIZ_L_ADDR 0x47
-#define CIS_MARK_H_ADDR 0x48
-#define CIS_MARK_L_ADDR 0x49
-#define CIS_LEC_MODE_ADDR 0x4A
-
-/*=====================================*/
-
-#define HOOK_LEV_ACT_START_ADDR 0x89
-#define RO1_START_ADDR 0x70
-#define RO2_START_ADDR 0x95
-#define RO3_START_ADDR 0x96
-
-#define TG1_FREQ_START_ADDR 0x38
-#define TG1_GAIN_START_ADDR 0x39
-#define TG1_BANDPASS_START_ADDR 0x3B
-#define TG1_BANDPASS_END_ADDR 0x3D
-
-#define TG2_FREQ_START_ADDR 0x40
-#define TG2_GAIN_START_ADDR 0x41
-#define TG2_BANDPASS_START_ADDR 0x43
-#define TG2_BANDPASS_END_ADDR 0x45
-
-/*====================================*/
-
-#define PCM_HW_B 0x80
-#define PCM_HW_A 0x00
-#define PCM_TIME_SLOT_0 0x00 /* Byte 0 of PCM Frame (by default is assigned to channel A ) */
-#define PCM_TIME_SLOT_1 0x01 /* Byte 1 of PCM Frame (by default is assigned to channel B ) */
-#define PCM_TIME_SLOT_4 0x04 /* Byte 4 of PCM Frame (Corresponds to B1 of the Second GCI ) */
-
-#define RX_LEV_ADDR 0x28
-#define TX_LEV_ADDR 0x30
-#define Ik1_ADDR 0x83
-
-#define AR_ROW 3 /* Is the row (AR Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */
-#define AX_ROW 6 /* Is the row (AX Params) of the ac_Coeff array in SMS_CODEC_Defaults struct */
-#define DCF_ROW 0 /* Is the row (DCF Params) of the dc_Coeff array in SMS_CODEC_Defaults struct */
-
-/* Mark the start byte of Duslic parameters that we use with configurator */
-#define Ik1_START_BYTE 3
-#define RX_LEV_START_BYTE 0
-#define TX_LEV_START_BYTE 0
-
-/************************************************/
-
-#define INTREG4_CIS_ACT (1 << 0)
-
-#define BCR1_SLEEP 0x20
-#define BCR1_REVPOL 0x10
-#define BCR1_ACTR 0x08
-#define BCR1_ACTL 0x04
-#define BCR1_SLIC_MASK 0x03
-
-#define BCR2_HARD_POL_REV 0x40
-#define BCR2_TTX 0x20
-#define BCR2_TTX_12K 0x10
-#define BCR2_HIMAN 0x08
-#define BCR2_PDOT 0x01
-
-#define BCR3_PCMX_EN (1 << 4)
-
-#define BCR5_DTMF_EN (1 << 0)
-#define BCR5_DTMF_SRC (1 << 1)
-#define BCR5_LEC_EN (1 << 2)
-#define BCR5_LEC_OUT (1 << 3)
-#define BCR5_CIS_EN (1 << 4)
-#define BCR5_CIS_AUTO (1 << 5)
-#define BCR5_UTDX_EN (1 << 6)
-#define BCR5_UTDR_EN (1 << 7)
-
-#define DSCR_TG1_EN (1 << 0)
-#define DSCR_TG2_EN (1 << 1)
-#define DSCR_PTG (1 << 2)
-#define DSCR_COR8 (1 << 3)
-#define DSCR_DG_KEY(x) (((x) & 0x0F) << 4)
-
-#define CIS_LEC_MODE_CIS_V23 (1 << 0)
-#define CIS_LEC_MODE_CIS_FRM (1 << 1)
-#define CIS_LEC_MODE_NLP_EN (1 << 2)
-#define CIS_LEC_MODE_UTDR_SUM (1 << 4)
-#define CIS_LEC_MODE_UTDX_SUM (1 << 5)
-#define CIS_LEC_MODE_LEC_FREEZE (1 << 6)
-#define CIS_LEC_MODE_LEC_ADAPT (1 << 7)
-
-#define TSTR4_COR_64 (1 << 5)
-
-#define TSTR3_AC_DLB_8K (1 << 2)
-#define TSTR3_AC_DLB_32K (1 << 3)
-#define TSTR3_AC_DLB_4M (1 << 5)
-
-
-#define LMCR1_TEST_EN (1 << 7)
-#define LMCR1_LM_EN (1 << 6)
-#define LMCR1_LM_THM (1 << 5)
-#define LMCR1_LM_ONCE (1 << 2)
-#define LMCR1_LM_MASK (1 << 1)
-
-#define LMCR2_LM_RECT (1 << 5)
-#define LMCR2_LM_SEL_VDD 0x0D
-#define LMCR2_LM_SEL_IO3 0x0A
-#define LMCR2_LM_SEL_IO4 0x0B
-#define LMCR2_LM_SEL_IO4_MINUS_IO3 0x0F
-
-#define LMCR3_RTR_SEL (1 << 6)
-
-#define LMCR3_RNG_OFFSET_NONE 0x00
-#define LMCR3_RNG_OFFSET_1 0x01
-#define LMCR3_RNG_OFFSET_2 0x02
-#define LMCR3_RNG_OFFSET_3 0x03
-
-#define TSTR5_DC_HOLD (1 << 3)
-
-/************************************************/
-
-#define TARGET_ONHOOK_BATH_x100 4600 /* 46.0 Volt */
-#define TARGET_ONHOOK_BATL_x100 2500 /* 25.0 Volt */
-#define TARGET_V_DIVIDER_RATIO_x100 21376L /* (R1+R2)/R2 = 213.76 */
-#define DIVIDER_RATIO_ACCURx100 (22 * 100)
-#define V_AD_x10000 10834L /* VAD = 1.0834 */
-#define TARGET_VDDx100 330 /* VDD = 3.3 * 10 */
-#define VDD_MAX_DIFFx100 20 /* VDD Accur = 0.2*100 */
-
-#define RMS_MULTIPLIERx100 111 /* pi/(2xsqrt(2)) = 1.11*/
-#define K_INTDC_RECT_ON 4 /* When Rectifier is ON this value is necessary(2^4) */
-#define K_INTDC_RECT_OFF 2 /* 2^2 */
-#define RNG_FREQ 25
-#define SAMPLING_FREQ (2000L)
-#define N_SAMPLES (SAMPLING_FREQ/RNG_FREQ) /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */
-#define HOOK_THRESH_RING_START_ADDR 0x8B
-#define RING_PARAMS_START_ADDR 0x70
-
-#define V_OUT_BATH_MAX_DIFFx100 300 /* 3.0 x100 */
-#define V_OUT_BATL_MAX_DIFFx100 400 /* 4.0 x100 */
-#define MAX_V_RING_MEANx100 50
-#define TARGET_V_RING_RMSx100 2720
-#define V_RMS_RING_MAX_DIFFx100 250
-
-#define LM_OK_SRC_IRG_2 (1 << 4)
-
-/************************************************/
-
-#define PORTB (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define PORTC (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
-#define PORTD (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
-
-#define _PORTD_SET(mask, state) \
- do { \
- if (state) \
- PORTD |= mask; \
- else \
- PORTD &= ~mask; \
- } while (0)
-
-#define _PORTB_SET(mask, state) \
- do { \
- if (state) \
- PORTB |= mask; \
- else \
- PORTB &= ~mask; \
- } while (0)
-
-#define _PORTB_TGL(mask) do { PORTB ^= mask; } while (0)
-#define _PORTB_GET(mask) (!!(PORTB & mask))
-
-#define _PORTC_GET(mask) (!!(PORTC & mask))
-
-/* port B */
-#define SPI_RXD (1 << (31 - 28))
-#define SPI_TXD (1 << (31 - 29))
-#define SPI_CLK (1 << (31 - 30))
-
-/* port C */
-#define COM_HOOK1 (1 << (15 - 9))
-#define COM_HOOK2 (1 << (15 - 10))
-
-#ifndef CONFIG_NETTA_SWAPHOOK
-
-#define COM_HOOK3 (1 << (15 - 11))
-#define COM_HOOK4 (1 << (15 - 12))
-
-#else
-
-#define COM_HOOK3 (1 << (15 - 12))
-#define COM_HOOK4 (1 << (15 - 11))
-
-#endif
-
-/* port D */
-#define SPIENC1 (1 << (15 - 9))
-#define SPIENC2 (1 << (15 - 10))
-#define SPIENC3 (1 << (15 - 11))
-#define SPIENC4 (1 << (15 - 14))
-
-#define SPI_DELAY() udelay(1)
-
-static inline unsigned int __SPI_Transfer(unsigned int tx)
-{
- unsigned int rx;
- int b;
-
- rx = 0; b = 8;
- while (--b >= 0) {
- _PORTB_SET(SPI_TXD, tx & 0x80);
- tx <<= 1;
- _PORTB_TGL(SPI_CLK);
- SPI_DELAY();
- rx <<= 1;
- rx |= _PORTB_GET(SPI_RXD);
- _PORTB_TGL(SPI_CLK);
- SPI_DELAY();
- }
-
- return rx;
-}
-
-static const char *codsp_dtmf_map = "D1234567890*#ABC";
-
-static const int spienc_mask_tab[4] = { SPIENC1, SPIENC2, SPIENC3, SPIENC4 };
-static const int com_hook_mask_tab[4] = { COM_HOOK1, COM_HOOK2, COM_HOOK3, COM_HOOK4 };
-
-static unsigned int codsp_send(int duslic_id, const unsigned char *cmd, int cmdlen, unsigned char *res, int reslen)
-{
- unsigned int rx;
- int i;
-
- /* just some sanity checks */
- if (cmd == 0 || cmdlen < 0)
- return -1;
-
- _PORTD_SET(spienc_mask_tab[duslic_id], 0);
-
- /* first 2 bytes are without response */
- i = 2;
- while (i-- > 0 && cmdlen-- > 0)
- __SPI_Transfer(*cmd++);
-
- while (cmdlen-- > 0) {
- rx = __SPI_Transfer(*cmd++);
- if (res != 0 && reslen-- > 0)
- *res++ = (unsigned char)rx;
- }
- if (res != 0) {
- while (reslen-- > 0)
- *res++ = __SPI_Transfer(0xFF);
- }
-
- _PORTD_SET(spienc_mask_tab[duslic_id], 1);
-
- return 0;
-}
-
-/****************************************************************************/
-
-void codsp_set_ciop_m(int duslic_id, int channel, unsigned char m)
-{
- unsigned char cmd = CODSP_WR | CODSP_ADR(channel) | CODSP_M(m);
- codsp_send(duslic_id, &cmd, 1, 0, 0);
-}
-
-void codsp_reset_chip(int duslic_id)
-{
- static const unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_CMD_SOFT_RESET;
- codsp_send(duslic_id, &cmd, 1, 0, 0);
-}
-
-void codsp_reset_channel(int duslic_id, int channel)
-{
- unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESET_CH;
- codsp_send(duslic_id, &cmd, 1, 0, 0);
-}
-
-void codsp_resync_channel(int duslic_id, int channel)
-{
- unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESYNC;
- codsp_send(duslic_id, &cmd, 1, 0, 0);
-}
-
-/****************************************************************************/
-
-void codsp_write_sop_char(int duslic_id, int channel, unsigned char regno, unsigned char val)
-{
- unsigned char cmd[3];
-
- cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
- cmd[1] = regno;
- cmd[2] = val;
-
- codsp_send(duslic_id, cmd, 3, 0, 0);
-}
-
-void codsp_write_sop_short(int duslic_id, int channel, unsigned char regno, unsigned short val)
-{
- unsigned char cmd[4];
-
- cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
- cmd[1] = regno;
- cmd[2] = (unsigned char)(val >> 8);
- cmd[3] = (unsigned char)val;
-
- codsp_send(duslic_id, cmd, 4, 0, 0);
-}
-
-void codsp_write_sop_int(int duslic_id, int channel, unsigned char regno, unsigned int val)
-{
- unsigned char cmd[6];
-
- cmd[0] = CODSP_WR | CODSP_ADR(channel) | CODSP_CMD_SOP;
- cmd[1] = regno;
- cmd[2] = (unsigned char)(val >> 24);
- cmd[3] = (unsigned char)(val >> 16);
- cmd[4] = (unsigned char)(val >> 8);
- cmd[5] = (unsigned char)val;
-
- codsp_send(duslic_id, cmd, 6, 0, 0);
-}
-
-unsigned char codsp_read_sop_char(int duslic_id, int channel, unsigned char regno)
-{
- unsigned char cmd[3];
- unsigned char res[2];
-
- cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
- cmd[1] = regno;
-
- codsp_send(duslic_id, cmd, 2, res, 2);
-
- return res[1];
-}
-
-unsigned short codsp_read_sop_short(int duslic_id, int channel, unsigned char regno)
-{
- unsigned char cmd[2];
- unsigned char res[3];
-
- cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
- cmd[1] = regno;
-
- codsp_send(duslic_id, cmd, 2, res, 3);
-
- return ((unsigned short)res[1] << 8) | res[2];
-}
-
-unsigned int codsp_read_sop_int(int duslic_id, int channel, unsigned char regno)
-{
- unsigned char cmd[2];
- unsigned char res[5];
-
- cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
- cmd[1] = regno;
-
- codsp_send(duslic_id, cmd, 2, res, 5);
-
- return ((unsigned int)res[1] << 24) | ((unsigned int)res[2] << 16) | ((unsigned int)res[3] << 8) | res[4];
-}
-
-/****************************************************************************/
-
-void codsp_write_cop_block(int duslic_id, int channel, unsigned char addr, const unsigned char *block)
-{
- unsigned char cmd[10];
-
- cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
- cmd[1] = addr;
- memcpy(cmd + 2, block, 8);
- codsp_send(duslic_id, cmd, 10, 0, 0);
-}
-
-void codsp_write_cop_char(int duslic_id, int channel, unsigned char addr, unsigned char val)
-{
- unsigned char cmd[3];
-
- cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
- cmd[1] = addr;
- cmd[2] = val;
- codsp_send(duslic_id, cmd, 3, 0, 0);
-}
-
-void codsp_write_cop_short(int duslic_id, int channel, unsigned char addr, unsigned short val)
-{
- unsigned char cmd[4];
-
- cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
- cmd[1] = addr;
- cmd[2] = (unsigned char)(val >> 8);
- cmd[3] = (unsigned char)val;
-
- codsp_send(duslic_id, cmd, 4, 0, 0);
-}
-
-void codsp_read_cop_block(int duslic_id, int channel, unsigned char addr, unsigned char *block)
-{
- unsigned char cmd[2];
- unsigned char res[9];
-
- cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
- cmd[1] = addr;
- codsp_send(duslic_id, cmd, 2, res, 9);
- memcpy(block, res + 1, 8);
-}
-
-unsigned char codsp_read_cop_char(int duslic_id, int channel, unsigned char addr)
-{
- unsigned char cmd[2];
- unsigned char res[2];
-
- cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
- cmd[1] = addr;
- codsp_send(duslic_id, cmd, 2, res, 2);
- return res[1];
-}
-
-unsigned short codsp_read_cop_short(int duslic_id, int channel, unsigned char addr)
-{
- unsigned char cmd[2];
- unsigned char res[3];
-
- cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
- cmd[1] = addr;
-
- codsp_send(duslic_id, cmd, 2, res, 3);
-
- return ((unsigned short)res[1] << 8) | res[2];
-}
-
-/****************************************************************************/
-
-#define MAX_POP_BLOCK 50
-
-void codsp_write_pop_block (int duslic_id, int channel, unsigned char addr,
- const unsigned char *block, int len)
-{
- unsigned char cmd[2 + MAX_POP_BLOCK];
-
- if (len > MAX_POP_BLOCK) /* truncate */
- len = MAX_POP_BLOCK;
-
- cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
- cmd[1] = addr;
- memcpy (cmd + 2, block, len);
- codsp_send (duslic_id, cmd, 2 + len, 0, 0);
-}
-
-void codsp_write_pop_char (int duslic_id, int channel, unsigned char regno,
- unsigned char val)
-{
- unsigned char cmd[3];
-
- cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
- cmd[1] = regno;
- cmd[2] = val;
-
- codsp_send (duslic_id, cmd, 3, 0, 0);
-}
-
-void codsp_write_pop_short (int duslic_id, int channel, unsigned char regno,
- unsigned short val)
-{
- unsigned char cmd[4];
-
- cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
- cmd[1] = regno;
- cmd[2] = (unsigned char) (val >> 8);
- cmd[3] = (unsigned char) val;
-
- codsp_send (duslic_id, cmd, 4, 0, 0);
-}
-
-void codsp_write_pop_int (int duslic_id, int channel, unsigned char regno,
- unsigned int val)
-{
- unsigned char cmd[6];
-
- cmd[0] = CODSP_WR | CODSP_ADR (channel) | CODSP_CMD_POP;
- cmd[1] = regno;
- cmd[2] = (unsigned char) (val >> 24);
- cmd[3] = (unsigned char) (val >> 16);
- cmd[4] = (unsigned char) (val >> 8);
- cmd[5] = (unsigned char) val;
-
- codsp_send (duslic_id, cmd, 6, 0, 0);
-}
-
-unsigned char codsp_read_pop_char (int duslic_id, int channel,
- unsigned char regno)
-{
- unsigned char cmd[3];
- unsigned char res[2];
-
- cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
- cmd[1] = regno;
-
- codsp_send (duslic_id, cmd, 2, res, 2);
-
- return res[1];
-}
-
-unsigned short codsp_read_pop_short (int duslic_id, int channel,
- unsigned char regno)
-{
- unsigned char cmd[2];
- unsigned char res[3];
-
- cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
- cmd[1] = regno;
-
- codsp_send (duslic_id, cmd, 2, res, 3);
-
- return ((unsigned short) res[1] << 8) | res[2];
-}
-
-unsigned int codsp_read_pop_int (int duslic_id, int channel,
- unsigned char regno)
-{
- unsigned char cmd[2];
- unsigned char res[5];
-
- cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
- cmd[1] = regno;
-
- codsp_send (duslic_id, cmd, 2, res, 5);
-
- return (((unsigned int) res[1] << 24) |
- ((unsigned int) res[2] << 16) |
- ((unsigned int) res[3] << 8) |
- res[4] );
-}
-/****************************************************************************/
-
-struct _coeffs {
- unsigned char addr;
- unsigned char values[8];
-};
-
-struct _coeffs ac_coeffs[11] = {
- { 0x60, {0xAD,0xDA,0xB5,0x9B,0xC7,0x2A,0x9D,0x00} }, /* 0x60 IM-Filter part 1 */
- { 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x77,0x0A,0x00} }, /* 0x68 IM-Filter part 2 */
- { 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter */
- { 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter */
- { 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter */
- { 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter */
- { 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter */
- { 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter */
- { 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, /* 0x00 TH-Filter part 1 */
- { 0x08, {0x81,0x00,0x80,0x00,0xD7,0x33,0xBA,0x01} }, /* 0x08 TH-Filter part 2 */
- { 0x10, {0xB3,0x6C,0xDC,0xA3,0xA4,0xE5,0x88,0x00} } /* 0x10 TH-Filter part 3 */
-};
-
-struct _coeffs ac_coeffs_0dB[11] = {
- { 0x60, {0xAC,0x2A,0xB5,0x9A,0xB7,0x2A,0x9D,0x00} },
- { 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x83,0x0A,0x00} },
- { 0x18, {0x08,0x20,0xD4,0xA4,0x65,0xEE,0x92,0x07} },
- { 0x28, {0x2B,0xAB,0x36,0xA5,0x88,0x00,0x00,0x00} },
- { 0x48, {0xAB,0xE9,0x4E,0x32,0xAB,0x25,0xA5,0x03} },
- { 0x20, {0x08,0x20,0xDB,0x9C,0xA7,0xFA,0xB4,0x07} },
- { 0x30, {0xF3,0x10,0x07,0x60,0x85,0x40,0xC0,0x1A} },
- { 0x50, {0x96,0x38,0x29,0x97,0x39,0x19,0x8B,0x00} },
- { 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} },
- { 0x08, {0x81,0x00,0x80,0x00,0x47,0x3C,0xD2,0x01} },
- { 0x10, {0x62,0xDB,0x4A,0x87,0x73,0x28,0x88,0x00} }
-};
-
-struct _coeffs dc_coeffs[9] = {
- { 0x80, {0x25,0x59,0x9C,0x23,0x24,0x23,0x32,0x1C} }, /* 0x80 DC-Parameter */
- { 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing */
- { 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters */
- { 0x88, {0xAF,0x80,0x27,0x7B,0x01,0x4C,0x7B,0x02} }, /* 0x88 Hook Levels */
- { 0x78, {0x00,0xC0,0x6D,0x7A,0xB3,0x78,0x89,0x00} }, /* 0x78 Ramp Generator */
- { 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX */
- { 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1 */
- { 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2 */
- { 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} } /* 0x98 Reserved */
-};
-
-void program_coeffs(int duslic_id, int channel, struct _coeffs *coeffs, int tab_size)
-{
- int i;
-
- for (i = 0; i < tab_size; i++)
- codsp_write_cop_block(duslic_id, channel, coeffs[i].addr, coeffs[i].values);
-}
-
-#define SS_OPEN_CIRCUIT 0
-#define SS_RING_PAUSE 1
-#define SS_ACTIVE 2
-#define SS_ACTIVE_HIGH 3
-#define SS_ACTIVE_RING 4
-#define SS_RINGING 5
-#define SS_ACTIVE_WITH_METERING 6
-#define SS_ONHOOKTRNSM 7
-#define SS_STANDBY 8
-#define SS_MAX 8
-
-static void codsp_set_slic(int duslic_id, int channel, int state)
-{
- unsigned char v;
-
- v = codsp_read_sop_char(duslic_id, channel, BCR1_ADDR);
-
- switch (state) {
-
- case SS_ACTIVE:
- codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTR) | BCR1_ACTL);
- codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
- break;
-
- case SS_ACTIVE_HIGH:
- codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTR | BCR1_ACTL));
- codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
- break;
-
- case SS_ACTIVE_RING:
- case SS_ONHOOKTRNSM:
- codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTL) | BCR1_ACTR);
- codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
- break;
-
- case SS_STANDBY:
- codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTL | BCR1_ACTR));
- codsp_set_ciop_m(duslic_id, channel, CODSP_M_SLEEP_PWRDN);
- break;
-
- case SS_OPEN_CIRCUIT:
- codsp_set_ciop_m(duslic_id, channel, CODSP_M_PWRDN_HIZ);
- break;
-
- case SS_RINGING:
- codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING);
- break;
-
- case SS_RING_PAUSE:
- codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING_PAUSE);
- break;
- }
-}
-
-const unsigned char Ring_Sin_28Vrms_25Hz[8] = { 0x90, 0x30, 0x1B, 0xC0, 0xC3, 0x9C, 0x88, 0x00 };
-const unsigned char Max_HookRingTh[3] = { 0x7B, 0x41, 0x62 };
-
-void retrieve_slic_state(int slic_id)
-{
- int duslic_id = slic_id >> 1;
- int channel = slic_id & 1;
-
- /* Retrieve the state of the SLICs */
- codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
-
- /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
- udelay(10000);
-
- codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
- codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);
- codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40);
-
- /* Program Default Hook Ring thresholds */
- codsp_write_cop_block(duslic_id, channel, dc_coeffs[1].addr, dc_coeffs[1].values);
-
- /* Now program Hook Threshold while Ring and ac RingTrip to max values */
- codsp_write_cop_block(duslic_id, channel, dc_coeffs[3].addr, dc_coeffs[3].values);
-
- codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
-
- udelay(40000);
-}
-
-int wait_level_metering_finish(int duslic_id, int channel)
-{
- int cnt;
-
- for (cnt = 0; cnt < 1000 &&
- (codsp_read_sop_char(duslic_id, channel, INTREG2_ADDR) & LM_OK_SRC_IRG_2) == 0; cnt++) { }
-
- return cnt != 1000;
-}
-
-int measure_on_hook_voltages(int slic_id, long *vdd,
- long *v_oh_H, long *v_oh_L, long *ring_mean_v, long *ring_rms_v)
-{
- short LM_Result, Offset_Compensation; /* Signed 16 bit */
- long int VDD, VDD_diff, V_in, V_out, Divider_Ratio, Vout_diff ;
- unsigned char err_mask = 0;
- int duslic_id = slic_id >> 1;
- int channel = slic_id & 1;
- int i;
-
- /* measure VDD */
- /* Now select the VDD level Measurement (but first of all Hold the DC characteristic) */
- codsp_write_sop_char(duslic_id, channel, TSTR5_ADDR, TSTR5_DC_HOLD);
-
- /* Activate Test Mode ==> To Enable DC Hold !!! */
- /* (else the LMRES is treated as Feeding Current and the Feeding voltage changes */
- /* imediatelly (after 500us when the LMRES Registers is updated for the first time after selection of (IO4-IO3) measurement !!!!))*/
- codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK);
-
- udelay(40000);
-
- /* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */
- codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_VDD);
-
- /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
- udelay(10000);
-
- /* Now Read the LM Result Registers */
- LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
- VDD = (-1)*((((long int)LM_Result) * 390L ) >> 15) ; /* VDDx100 */
-
- *vdd = VDD;
-
- VDD_diff = VDD - TARGET_VDDx100;
-
- if (VDD_diff < 0)
- VDD_diff = -VDD_diff;
-
- if (VDD_diff > VDD_MAX_DIFFx100)
- err_mask |= 1;
-
- Divider_Ratio = TARGET_V_DIVIDER_RATIO_x100;
-
- codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
- codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
-
- codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); /* Go back to ONHOOK Voltage */
-
- udelay(40000);
-
- codsp_write_sop_char(duslic_id, channel,
- LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK);
-
- udelay(40000);
-
- /* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */
- codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);
-
- /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
- udelay(10000);
-
- /* Now Read the LM Result Registers */
- LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
- V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/
-
- V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */
-
- *v_oh_H = V_out;
-
- Vout_diff = V_out - TARGET_ONHOOK_BATH_x100;
-
- if (Vout_diff < 0)
- Vout_diff = -Vout_diff;
-
- if (Vout_diff > V_OUT_BATH_MAX_DIFFx100)
- err_mask |= 2;
-
- codsp_set_slic(duslic_id, channel, SS_ACTIVE); /* Go back to ONHOOK Voltage */
-
- udelay(40000);
-
- /* Now Read the LM Result Registers */
- LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
-
- V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ; /* Vin x 10000*/
-
- V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */
-
- *v_oh_L = V_out;
-
- Vout_diff = V_out - TARGET_ONHOOK_BATL_x100;
-
- if (Vout_diff < 0)
- Vout_diff = -Vout_diff;
-
- if (Vout_diff > V_OUT_BATL_MAX_DIFFx100)
- err_mask |= 4;
-
- /* perform ring tests */
-
- codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
- codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
-
- udelay(40000);
-
- codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, LMCR3_RTR_SEL | LMCR3_RNG_OFFSET_NONE);
-
- /* Now program RO1 =0V , Ring Amplitude and frequency and shift factor K = 1 (LMDC=0x0088)*/
- codsp_write_cop_block(duslic_id, channel, RING_PARAMS_START_ADDR, Ring_Sin_28Vrms_25Hz);
-
- /* By Default RO1 is selected when ringing RNG-OFFSET = 00 */
-
- /* Now program Hook Threshold while Ring and ac RingTrip to max values */
- for(i = 0; i < sizeof(Max_HookRingTh); i++)
- codsp_write_cop_char(duslic_id, channel, HOOK_THRESH_RING_START_ADDR + i, Max_HookRingTh[i]);
-
- codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
-
- codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */
-
- /* select source for the levelmeter to be IO4-IO3 */
- codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);
-
- udelay(40000);
-
- /* Before Enabling Level Meter Programm the apropriate shift factor K_INTDC=(4 if Rectifier Enabled and 2 if Rectifier Disabled) */
- codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_OFF);
-
- udelay(10000);
-
- /* Enable LevelMeter to Integrate only once (Rectifier Disabled) */
- codsp_write_sop_char(duslic_id, channel,
- LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
-
- udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */
-
- if (wait_level_metering_finish(duslic_id, channel)) {
-
- udelay(10000); /* To be sure that Integration Results are Valid wait at least 500us !!! */
-
- /* Now Read the LM Result Registers (Will be valid until LM_EN becomes zero again( after that the Result is updated every 500us) ) */
- Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
- Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_OFF)) / N_SAMPLES);
-
- /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
- codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
-
- /* Now programm Integrator Offset Registers !!! */
- codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);
-
- codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing */
-
- udelay(40000);
-
- /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
- codsp_write_sop_char(duslic_id, channel,
- LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
-
- udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */
-
- /* Poll the LM_OK bit to see when Integration Result is Ready */
- if (wait_level_metering_finish(duslic_id, channel)) {
-
- udelay(10000); /* wait at least 500us to be sure that the Integration Result are valid !!! */
-
- /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
- /* ==>After that Result Regs will be updated every 500us !!!) */
- LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
- V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_OFF)) ; /* Vin x 10000*/
-
- V_out = (V_in * Divider_Ratio) / 10000L ; /* Vout x100 */
-
- if (V_out < 0)
- V_out= -V_out;
-
- if (V_out > MAX_V_RING_MEANx100)
- err_mask |= 8;
-
- *ring_mean_v = V_out;
- } else {
- err_mask |= 8;
- *ring_mean_v = 0;
- }
- } else {
- err_mask |= 8;
- *ring_mean_v = 0;
- }
-
- /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
- codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
- LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
- codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
-
- codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */
-
- /* Now Enable Rectifier */
- /* select source for the levelmeter to be IO4-IO3 */
- codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR,
- LMCR2_LM_SEL_IO4_MINUS_IO3 | LMCR2_LM_RECT);
-
- /* Program the apropriate shift factor K_INTDC (in order to avoid Overflow at Integtation Result !!!) */
- codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_ON);
-
- udelay(40000);
-
- /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
- codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
- LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
-
- udelay(40000);
-
- /* Poll the LM_OK bit to see when Integration Result is Ready */
- if (wait_level_metering_finish(duslic_id, channel)) {
-
- udelay(10000);
-
- /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
- /* ==>After that Result Regs will be updated every 500us !!!) */
- Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
- Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_ON)) / N_SAMPLES);
-
- /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
- codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
-
- /* Now programm Integrator Offset Registers !!! */
- codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);
-
- /* Be sure that a Ring is generated !!!! */
- codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing again */
-
- udelay(40000);
-
- /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
- codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
- LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
-
- udelay(40000);
-
- /* Poll the LM_OK bit to see when Integration Result is Ready */
- if (wait_level_metering_finish(duslic_id, channel)) {
-
- udelay(10000);
-
- /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
- /* ==>After that Result Regs will be updated every 500us !!!) */
- LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
- V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_ON) ) ; /* Vin x 10000*/
-
- V_out = (((V_in * Divider_Ratio) / 10000L) * RMS_MULTIPLIERx100) / 100 ; /* Vout_RMS x100 */
- if (V_out < 0)
- V_out = -V_out;
-
- Vout_diff = (V_out - TARGET_V_RING_RMSx100);
-
- if (Vout_diff < 0)
- Vout_diff = -Vout_diff;
-
- if (Vout_diff > V_RMS_RING_MAX_DIFFx100)
- err_mask |= 16;
-
- *ring_rms_v = V_out;
- } else {
- err_mask |= 16;
- *ring_rms_v = 0;
- }
- } else {
- err_mask |= 16;
- *ring_rms_v = 0;
- }
- /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
- codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
-
- retrieve_slic_state(slic_id);
-
- return(err_mask);
-}
-
-int test_dtmf(int slic_id)
-{
- unsigned char code;
- unsigned char b;
- unsigned int intreg;
- int duslic_id = slic_id >> 1;
- int channel = slic_id & 1;
-
- for (code = 0; code < 16; code++) {
- b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
- codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
- (b & ~(DSCR_PTG | DSCR_DG_KEY(15))) | DSCR_DG_KEY(code) | DSCR_TG1_EN | DSCR_TG2_EN);
- udelay(80000);
-
- intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR);
- if ((intreg & CODSP_INTREG_INT_CH) == 0)
- break;
-
- if ((intreg & CODSP_INTREG_DTMF_OK) == 0 ||
- codsp_dtmf_map[(intreg >> 10) & 15] != codsp_dtmf_map[code])
- break;
-
- b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
- codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
- b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
-
- udelay(80000);
-
- intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); /* for dtmf_pause irq */
- }
-
- if (code != 16) {
- b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */
- codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
- b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
- return(1);
- }
-
- return(0);
-}
-
-void data_up_persist_time(int duslic_id, int channel, int time_ms)
-{
- unsigned char b;
-
- b = codsp_read_sop_char(duslic_id, channel, IOCTL3_ADDR);
- b = (b & 0x0F) | ((time_ms & 0x0F) << 4);
- codsp_write_sop_char(duslic_id, channel, IOCTL3_ADDR, b);
-}
-
-static void program_dtmf_params(int duslic_id, int channel)
-{
- unsigned char b;
-
- codsp_write_pop_char(duslic_id, channel, DTMF_LEV_ADDR, 0x10);
- codsp_write_pop_char(duslic_id, channel, DTMF_TWI_ADDR, 0x0C);
- codsp_write_pop_char(duslic_id, channel, DTMF_NCF_H_ADDR, 0x79);
- codsp_write_pop_char(duslic_id, channel, DTMF_NCF_L_ADDR, 0x10);
- codsp_write_pop_char(duslic_id, channel, DTMF_NBW_H_ADDR, 0x02);
- codsp_write_pop_char(duslic_id, channel, DTMF_NBW_L_ADDR, 0xFB);
- codsp_write_pop_char(duslic_id, channel, DTMF_GAIN_ADDR, 0x91);
- codsp_write_pop_char(duslic_id, channel, DTMF_RES1_ADDR, 0x00);
- codsp_write_pop_char(duslic_id, channel, DTMF_RES2_ADDR, 0x00);
- codsp_write_pop_char(duslic_id, channel, DTMF_RES3_ADDR, 0x00);
-
- b = codsp_read_sop_char(duslic_id, channel, BCR5_ADDR);
- codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, b | BCR5_DTMF_EN);
-}
-
-static void codsp_channel_full_reset(int duslic_id, int channel)
-{
-
- program_coeffs(duslic_id, channel, ac_coeffs, sizeof(ac_coeffs) / sizeof(struct _coeffs));
- program_coeffs(duslic_id, channel, dc_coeffs, sizeof(dc_coeffs) / sizeof(struct _coeffs));
-
- /* program basic configuration registers */
- codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, 0x01);
- codsp_write_sop_char(duslic_id, channel, BCR2_ADDR, 0x41);
- codsp_write_sop_char(duslic_id, channel, BCR3_ADDR, 0x43);
- codsp_write_sop_char(duslic_id, channel, BCR4_ADDR, 0x00);
- codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, 0x00);
-
- codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, 0x04); /* PG */
-
- program_dtmf_params(duslic_id, channel);
-
- codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40); /* RingTRip_SEL */
-
- data_up_persist_time(duslic_id, channel, 4);
-
- codsp_write_sop_char(duslic_id, channel, MASK_ADDR, 0xFF); /* All interrupts masked */
-
- codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);
-}
-
-static int codsp_chip_full_reset(int duslic_id)
-{
- int i, cnt;
- int intreg[NUM_CHANNELS];
- unsigned char pcm_resync;
- unsigned char revision;
-
- codsp_reset_chip(duslic_id);
-
- udelay(2000);
-
- for (i = 0; i < NUM_CHANNELS; i++)
- intreg[i] = codsp_read_sop_int(duslic_id, i, INTREG1_ADDR);
-
- udelay(1500);
-
- if (_PORTC_GET(com_hook_mask_tab[duslic_id]) == 0) {
- printf("_HOOK(%d) stayed low\n", duslic_id);
- return -1;
- }
-
- for (pcm_resync = 0, i = 0; i < NUM_CHANNELS; i++) {
- if (intreg[i] & CODSP_INTREG_SYNC_FAIL)
- pcm_resync |= 1 << i;
- }
-
- for (cnt = 0; cnt < 5 && pcm_resync; cnt++) {
- for (i = 0; i < NUM_CHANNELS; i++)
- codsp_resync_channel(duslic_id, i);
-
- udelay(2000);
-
- pcm_resync = 0;
-
- for (i = 0; i < NUM_CHANNELS; i++) {
- if (codsp_read_sop_int(duslic_id, i, INTREG1_ADDR) & CODSP_INTREG_SYNC_FAIL)
- pcm_resync |= 1 << i;
- }
- }
-
- if (cnt == 5) {
- printf("PCM_Resync(%u) not completed\n", duslic_id);
- return -2;
- }
-
- revision = codsp_read_sop_char(duslic_id, 0, REVISION_ADDR);
- printf("DuSLIC#%d hardware version %d.%d\r\n", duslic_id, (revision & 0xF0) >> 4, revision & 0x0F);
-
- codsp_write_sop_char(duslic_id, 0, XCR_ADDR, 0x80); /* EDSP_EN */
-
- for (i = 0; i < NUM_CHANNELS; i++) {
- codsp_write_sop_char(duslic_id, i, PCMC1_ADDR, 0x01);
- codsp_channel_full_reset(duslic_id, i);
- }
-
- return 0;
-}
-
-int slic_self_test(int duslic_mask)
-{
- int slic;
- int i;
- int r;
- long vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v;
- const char *err_txt[] = { "VDD", "V_OH_H", "V_OH_L", "V_RING_MEAN", "V_RING_RMS" };
- int error = 0;
-
- for (slic = 0; slic < MAX_SLICS; slic++) { /* voltages self test */
- if (duslic_mask & (1 << (slic >> 1))) {
- r = measure_on_hook_voltages(slic, &vdd,
- &v_oh_H, &v_oh_L, &ring_mean_v, &ring_rms_v);
-
- printf("SLIC %u measured voltages (x100):\n\t"
- "VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n",
- slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v);
-
- if (r != 0)
- error |= 1 << slic;
-
- for (i = 0; i < 5; i++)
- if (r & (1 << i))
- printf("\t%s out of range\n", err_txt[i]);
- }
- }
-
- for (slic = 0; slic < MAX_SLICS; slic++) { /* voice path self test */
- if (duslic_mask & (1 << (slic >> 1))) {
- printf("SLIC %u VOICE PATH...CHECKING", slic);
- printf("\rSLIC %u VOICE PATH...%s\n", slic,
- (r = test_dtmf(slic)) != 0 ? "FAILED " : "PASSED ");
-
- if (r != 0)
- error |= 1 << slic;
- }
- }
-
- return(error);
-}
-
-#if defined(CONFIG_NETTA_ISDN)
-
-#define SPIENS1 (1 << (31 - 15))
-#define SPIENS2 (1 << (31 - 19))
-
-static const int spiens_mask_tab[2] = { SPIENS1, SPIENS2 };
-int s_initialized = 0;
-
-static inline unsigned int s_transfer_internal(int s_id, unsigned int address, unsigned int value)
-{
- unsigned int rx, v;
-
- _PORTB_SET(spiens_mask_tab[s_id], 0);
-
- rx = __SPI_Transfer(address);
-
- switch (address & 0xF0) {
- case 0x60: /* write byte register */
- case 0x70:
- rx = __SPI_Transfer(value);
- break;
-
- case 0xE0: /* read R6 register */
- v = __SPI_Transfer(0);
-
- rx = (rx << 8) | v;
-
- break;
-
- case 0xF0: /* read byte register */
- rx = __SPI_Transfer(0);
-
- break;
- }
-
- _PORTB_SET(spiens_mask_tab[s_id], 1);
-
- return rx;
-}
-
-static void s_write_BR(int s_id, unsigned int regno, unsigned int val)
-{
- unsigned int address;
-
- address = 0x70 | (regno & 15);
- val &= 0xff;
-
- (void)s_transfer_internal(s_id, address, val);
-}
-
-static void s_write_OR(int s_id, unsigned int regno, unsigned int val)
-{
- unsigned int address;
-
- address = 0x70 | (regno & 15);
- val &= 0xff;
-
- (void)s_transfer_internal(s_id, address, val);
-}
-
-static void s_write_NR(int s_id, unsigned int regno, unsigned int val)
-{
- unsigned int address;
-
- address = (regno & 7) << 4;
- val &= 0xf;
-
- (void)s_transfer_internal(s_id, address | val, 0x00);
-}
-
-#define BR7_IFR 0x08 /* IDL2 free run */
-#define BR7_ICSLSB 0x04 /* IDL2 clock speed LSB */
-
-#define BR15_OVRL_REG_EN 0x80
-#define OR7_D3VR 0x80 /* disable 3V regulator */
-
-#define OR8_TEME 0x10 /* TE mode enable */
-#define OR8_MME 0x08 /* master mode enable */
-
-void s_initialize(void)
-{
- int s_id;
-
- for (s_id = 0; s_id < 2; s_id++) {
- s_write_BR(s_id, 7, BR7_IFR | BR7_ICSLSB);
- s_write_BR(s_id, 15, BR15_OVRL_REG_EN);
- s_write_OR(s_id, 8, OR8_TEME | OR8_MME);
- s_write_OR(s_id, 7, OR7_D3VR);
- s_write_OR(s_id, 6, 0);
- s_write_BR(s_id, 15, 0);
- s_write_NR(s_id, 3, 0);
- }
-}
-
-#endif
-
-int board_post_codec(int flags)
-{
- int j;
- int r;
- int duslic_mask;
-
- printf("board_post_dsp\n");
-
-#if defined(CONFIG_NETTA_ISDN)
- if (s_initialized == 0) {
- s_initialize();
- s_initialized = 1;
-
- printf("s_initialized\n");
-
- udelay(20000);
- }
-#endif
- duslic_mask = 0;
-
- for (j = 0; j < MAX_DUSLIC; j++) {
- if (codsp_chip_full_reset(j) < 0)
- printf("Error initializing DuSLIC#%d\n", j);
- else
- duslic_mask |= 1 << j;
- }
-
- if (duslic_mask != 0) {
- printf("Testing SLICs...\n");
-
- r = slic_self_test(duslic_mask);
- for (j = 0; j < MAX_SLICS; j++) {
- if (duslic_mask & (1 << (j >> 1)))
- printf("SLIC %u...%s\n", j, r & (1 << j) ? "FAULTY" : "OK");
- }
- }
- printf("DuSLIC self test finished\n");
-
- return 0; /* return -1 on error */
-}
+++ /dev/null
-/*
- * Intracom TI6711/TI6412 DSP
- */
-
-#include <common.h>
-#include <post.h>
-
-#include "mpc8xx.h"
-
-struct ram_range {
- u32 start;
- u32 size;
-};
-
-#if defined(CONFIG_NETTA_6412)
-
-static const struct ram_range int_ram[] = {
- { 0x00000000U, 0x00040000U },
-};
-
-static const struct ram_range ext_ram[] = {
- { 0x80000000U, 0x00100000U },
-};
-
-static const struct ram_range ranges[] = {
- { 0x00000000U, 0x00040000U },
- { 0x80000000U, 0x00100000U },
-};
-
-static inline u16 bit_invert(u16 d)
-{
- register u8 i;
- register u16 r;
- register u16 bit;
-
- r = 0;
- for (i = 0; i < 16; i++) {
- bit = d & (1 << i);
- if (bit != 0)
- r |= 1 << (15 - i);
- }
- return r;
-}
-
-#else
-
-static const struct ram_range int_ram[] = {
- { 0x00000000U, 0x00010000U },
-};
-
-static const struct ram_range ext_ram[] = {
- { 0x80000000U, 0x00100000U },
-};
-
-static const struct ram_range ranges[] = {
- { 0x00000000U, 0x00010000U },
- { 0x80000000U, 0x00100000U },
-};
-
-#endif
-
-/*******************************************************************************************************/
-
-static inline int addr_in_int_ram(u32 addr)
-{
- int i;
-
- for (i = 0; i < sizeof(int_ram)/sizeof(int_ram[0]); i++)
- if (addr >= int_ram[i].start && addr < int_ram[i].start + int_ram[i].size)
- return 1;
-
- return 0;
-}
-
-static inline int addr_in_ext_ram(u32 addr)
-{
- int i;
-
- for (i = 0; i < sizeof(ext_ram)/sizeof(ext_ram[0]); i++)
- if (addr >= ext_ram[i].start && addr < ext_ram[i].start + ext_ram[i].size)
- return 1;
-
- return 0;
-}
-
-/*******************************************************************************************************/
-
-#define DSP_HPIC 0x0
-#define DSP_HPIA 0x4
-#define DSP_HPID1 0x8
-#define DSP_HPID2 0xC
-
-static u32 dummy_delay;
-static volatile u32 *ti6711_delay = &dummy_delay;
-
-static inline void dsp_go_slow(void)
-{
- volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl;
-#if defined(CONFIG_NETTA_6412)
- memctl->memc_or6 |= OR_SCY_15_CLK | OR_TRLX;
-#else
- memctl->memc_or2 |= OR_SCY_15_CLK | OR_TRLX;
-#endif
- memctl->memc_or5 |= OR_SCY_15_CLK | OR_TRLX;
-
- ti6711_delay = (u32 *)DUMMY_BASE;
-}
-
-static inline void dsp_go_fast(void)
-{
- volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl;
-#if defined(CONFIG_NETTA_6412)
- memctl->memc_or6 = (memctl->memc_or6 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
-#else
- memctl->memc_or2 = (memctl->memc_or2 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_3_CLK;
-#endif
- memctl->memc_or5 = (memctl->memc_or5 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
-
- ti6711_delay = &dummy_delay;
-}
-
-/*******************************************************************************************************/
-
-static inline void dsp_delay(void)
-{
- /* perform ti6711_delay chip select read to have a small delay */
- (void) *(volatile u32 *)ti6711_delay;
-}
-
-static inline u16 dsp_read_hpic(void)
-{
-#if defined(CONFIG_NETTA_6412)
- return bit_invert(*((volatile u16 *)DSP_BASE));
-#else
- return *((volatile u16 *)DSP_BASE);
-#endif
-}
-
-static inline void dsp_write_hpic(u16 val)
-{
-#if defined(CONFIG_NETTA_6412)
- *((volatile u16 *)DSP_BASE) = bit_invert(val);
-#else
- *((volatile u16 *)DSP_BASE) = val;
-#endif
-}
-
-static inline void dsp_reset(void)
-{
-#if defined(CONFIG_NETTA_6412)
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15));
- udelay(500);
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 15));
- udelay(500);
-#else
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7));
- udelay(250);
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 7));
- udelay(250);
-#endif
-}
-
-static inline u32 dsp_read_hpic_word(u32 addr)
-{
- u32 val;
- volatile u16 *p;
-#if defined(CONFIG_NETTA_6412)
- p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
-
- val = ((u32) bit_invert(p[0]) << 16);
- /* dsp_delay(); */
-
- val |= bit_invert(p[1]);
- /* dsp_delay(); */
-#else
- p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
-
- val = ((u32) p[0] << 16);
- dsp_delay();
-
- val |= p[1];
- dsp_delay();
-#endif
- return val;
-}
-
-static inline u16 dsp_read_hpic_hi_hword(u32 addr)
-{
-#if defined(CONFIG_NETTA_6412)
- return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr));
-#else
- return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr);
-#endif
-}
-
-static inline u16 dsp_read_hpic_lo_hword(u32 addr)
-{
-#if defined(CONFIG_NETTA_6412)
- return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2));
-#else
- return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2);
-#endif
-}
-
-static inline void dsp_wait_hrdy(void)
-{
- int i;
-
- i = 0;
-#if defined(CONFIG_NETTA_6412)
- while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) {
-#else
- while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
-#endif
- dsp_delay();
- i++;
- }
-}
-
-static inline void dsp_write_hpic_word(u32 addr, u32 val)
-{
- volatile u16 *p;
-#if defined(CONFIG_NETTA_6412)
- p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
- p[0] = bit_invert((u16)(val >> 16));
- /* dsp_delay(); */
-
- p[1] = bit_invert((u16)val);
- /* dsp_delay(); */
-#else
- p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
- p[0] = (u16)(val >> 16);
- dsp_delay();
-
- p[1] = (u16)val;
- dsp_delay();
-#endif
-}
-
-static inline void dsp_write_hpic_hi_hword(u32 addr, u16 val_h)
-{
-#if defined(CONFIG_NETTA_6412)
- *(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = bit_invert(val_h);
-#else
-
- *(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = val_h;
-#endif
-}
-
-static inline void dsp_write_hpic_lo_hword(u32 addr, u16 val_l)
-{
-#if defined(CONFIG_NETTA_6412)
- *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = bit_invert(val_l);
-#else
- *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = val_l;
-#endif
-}
-
-/********************************************************************/
-
-static inline void c62_write_word(u32 addr, u32 val)
-{
- dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
-#if !defined(CONFIG_NETTA_6412)
- dsp_delay();
-#endif
- dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
-#if !defined(CONFIG_NETTA_6412)
- dsp_delay();
-#endif
-
- dsp_wait_hrdy();
-#if !defined(CONFIG_NETTA_6412)
- dsp_delay();
-#endif
- dsp_write_hpic_hi_hword(DSP_HPID2, (u16)(val >> 16));
-#if !defined(CONFIG_NETTA_6412)
- dsp_delay();
-
- /* dsp_wait_hrdy();
- dsp_delay(); */
-#endif
- dsp_write_hpic_lo_hword(DSP_HPID2, (u16)val);
-#if !defined(CONFIG_NETTA_6412)
- dsp_delay();
-#endif
-}
-
-static u32 c62_read_word(u32 addr)
-{
- u32 val;
-
- dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
-#if !defined(CONFIG_NETTA_6412)
- dsp_delay();
-#endif
- dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
-#if !defined(CONFIG_NETTA_6412)
- dsp_delay();
-#endif
-
- /* FETCH */
-#if defined(CONFIG_NETTA_6412)
- dsp_write_hpic_word(DSP_HPIC, 0x00100010);
-#else
- dsp_write_hpic(0x10);
- dsp_delay();
-#endif
- dsp_wait_hrdy();
-#if !defined(CONFIG_NETTA_6412)
- dsp_delay();
-#endif
- val = (u32)dsp_read_hpic_hi_hword(DSP_HPID2) << 16;
-#if !defined(CONFIG_NETTA_6412)
- dsp_delay();
-
- /* dsp_wait_hrdy();
- dsp_delay(); */
-#endif
- val |= dsp_read_hpic_lo_hword(DSP_HPID2);
-#if !defined(CONFIG_NETTA_6412)
- dsp_delay();
-#endif
- return val;
-}
-
-static inline void c62_read(u32 addr, u32 *buffer, int numdata)
-{
- int i;
-
- if (numdata <= 0)
- return;
-
- for (i = 0; i < numdata; i++) {
- *buffer++ = c62_read_word(addr);
- addr += 4;
- }
-}
-
-static inline u32 c62_checksum(u32 addr, int numdata)
-{
- int i;
- u32 chksum;
-
- chksum = 0;
- for (i = 0; i < numdata; i++) {
- chksum += c62_read_word(addr);
- addr += 4;
- }
-
- return chksum;
-}
-
-static inline void c62_write(u32 addr, const u32 *buffer, int numdata)
-{
- int i;
-
- if (numdata <= 0)
- return;
-
- for (i = 0; i < numdata; i++) {
- c62_write_word(addr, *buffer++);
- addr += 4;
- }
-}
-
-static inline int c62_write_word_validated(u32 addr, u32 val)
-{
- c62_write_word(addr, val);
- return c62_read_word(addr) == val ? 0 : -1;
-}
-
-static inline int c62_write_validated(u32 addr, const u32 *buffer, int numdata)
-{
- int i, r;
-
- if (numdata <= 0)
- return 0;
-
- for (i = 0; i < numdata; i++) {
- r = c62_write_word_validated(addr, *buffer++);
- if (r < 0)
- return r;
- addr += 4;
- }
- return 0;
-}
-
-#if defined(CONFIG_NETTA_6412)
-
-#define DRAM_REGS_BASE 0x1800000
-
-#define GBLCTL DRAM_REGS_BASE
-#define CECTL1 (DRAM_REGS_BASE + 0x4)
-#define CECTL0 (DRAM_REGS_BASE + 0x8)
-#define CECTL2 (DRAM_REGS_BASE + 0x10)
-#define CECTL3 (DRAM_REGS_BASE + 0x14)
-#define SDCTL (DRAM_REGS_BASE + 0x18)
-#define SDTIM (DRAM_REGS_BASE + 0x1C)
-#define SDEXT (DRAM_REGS_BASE + 0x20)
-#define SESEC1 (DRAM_REGS_BASE + 0x44)
-#define SESEC0 (DRAM_REGS_BASE + 0x48)
-#define SESEC2 (DRAM_REGS_BASE + 0x50)
-#define SESEC3 (DRAM_REGS_BASE + 0x54)
-
-#define MAR128 0x1848200
-#define MAR129 0x1848204
-
-void dsp_dram_initialize(void)
-{
- c62_write_word(GBLCTL, 0x120E4);
- c62_write_word(CECTL1, 0x18);
- c62_write_word(CECTL0, 0xD0);
- c62_write_word(CECTL2, 0x18);
- c62_write_word(CECTL3, 0x18);
- c62_write_word(SDCTL, 0x47115000);
- c62_write_word(SDTIM, 1536);
- c62_write_word(SDEXT, 0x534A9);
-#if 0
- c62_write_word(SESEC1, 0);
- c62_write_word(SESEC0, 0);
- c62_write_word(SESEC2, 0);
- c62_write_word(SESEC3, 0);
-#endif
- c62_write_word(MAR128, 1);
- c62_write_word(MAR129, 0);
-}
-
-#endif
-
-static inline void dsp_init_hpic(void)
-{
- int i;
- volatile u16 *p;
-#if defined(CONFIG_NETTA_6412)
- dsp_go_fast();
-#else
- dsp_go_slow();
-#endif
- i = 0;
-#if defined(CONFIG_NETTA_6412)
- while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) {
-#else
- while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
-#endif
- dsp_delay();
- i++;
- }
-
- if (i == 1000)
- printf("HRDY stuck\n");
-
- dsp_delay();
-
- /* write control register */
- p = (volatile u16 *)DSP_BASE;
- p[0] = 0x0000;
- dsp_delay();
- p[1] = 0x0000;
- dsp_delay();
-
-#if !defined(CONFIG_NETTA_6412)
- dsp_go_fast();
-#endif
-}
-
-/***********************************************************************************************************/
-
-#if !defined(CONFIG_NETTA_6412)
-
-static const u8 bootstrap_rbin[5084] = {
- 0x52, 0x42, 0x49, 0x4e, 0xc5, 0xa9, 0x9f, 0x1a, 0x00, 0x00, 0x00, 0x02,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00,
- 0x00, 0x00, 0x11, 0xc0, 0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a,
- 0x00, 0x00, 0x03, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
- 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
- 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
- 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
- 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
- 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
- 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a, 0x00, 0x00, 0x03, 0x62,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x18, 0x00, 0xe2,
- 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
- 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
- 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
- 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
- 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x10, 0x5a,
- 0x00, 0x19, 0x2e, 0x28, 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64,
- 0x02, 0x00, 0x00, 0xaa, 0x02, 0x10, 0xac, 0xe2, 0x00, 0x00, 0x20, 0x00,
- 0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x9f, 0x7a,
- 0x30, 0x00, 0x08, 0x10, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x04, 0x28,
- 0x00, 0x00, 0xc6, 0x69, 0x02, 0x16, 0x4c, 0xa2, 0x02, 0x00, 0x90, 0x7a,
- 0x00, 0x10, 0x02, 0xe4, 0x00, 0x00, 0x60, 0x00, 0x00, 0x02, 0xd6, 0xc8,
- 0x00, 0x10, 0x02, 0xf4, 0x03, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00,
- 0x03, 0x1a, 0xf7, 0xca, 0x03, 0x10, 0x02, 0xf6, 0x00, 0x00, 0x04, 0x28,
- 0x00, 0x00, 0xc6, 0x69, 0x02, 0x16, 0x4c, 0xa2, 0x02, 0x00, 0x90, 0x7a,
- 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x02, 0x97, 0xcf, 0x5a,
- 0x02, 0x90, 0x02, 0xf6, 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00,
- 0x02, 0x96, 0x10, 0xca, 0x02, 0x90, 0x02, 0xf6, 0x00, 0x0c, 0x03, 0x62,
- 0x00, 0x00, 0x80, 0x00, 0x02, 0x90, 0x10, 0x5a, 0x00, 0x00, 0x04, 0x28,
- 0x00, 0x00, 0xc6, 0x69, 0x02, 0x16, 0x4c, 0xa2, 0x02, 0x00, 0x90, 0x7a,
- 0x03, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x03, 0x18, 0x2f, 0xda,
- 0x03, 0x10, 0x02, 0xf6, 0x03, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00,
- 0x03, 0x1a, 0x10, 0x8a, 0x03, 0x10, 0x02, 0xf6, 0x00, 0x19, 0x2e, 0x28,
- 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, 0x03, 0x00, 0x00, 0xaa,
- 0x02, 0x98, 0xac, 0xe2, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x02, 0x64,
- 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0xbf, 0x7a, 0x22, 0x90, 0x02, 0xe6,
- 0x00, 0x00, 0x60, 0x00, 0x22, 0x96, 0xd6, 0x8a, 0x22, 0x90, 0x02, 0xf6,
- 0x22, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x22, 0x96, 0xf7, 0x8a,
- 0x22, 0x90, 0x02, 0xf6, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00,
- 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62,
- 0x00, 0x00, 0x80, 0x00, 0x00, 0x19, 0x2e, 0x28, 0x00, 0x00, 0x00, 0x68,
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- 0x02, 0x00, 0xc6, 0x6a, 0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x08, 0x28,
- 0x00, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0xa7, 0xca,
- 0x02, 0x00, 0x02, 0x76, 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc6, 0x6a,
- 0x02, 0x90, 0x02, 0xe6, 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc6, 0x6a,
- 0x00, 0x00, 0x20, 0x00, 0x02, 0x96, 0x31, 0xca, 0x02, 0x96, 0x10, 0x8a,
- 0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc6, 0x6a,
- 0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x08, 0x28, 0x00, 0x00, 0xc6, 0x68,
- 0x00, 0x00, 0x20, 0x00, 0x02, 0x12, 0x74, 0xca, 0x02, 0x00, 0x02, 0x76,
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- 0x02, 0x00, 0x08, 0x2a, 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00,
- 0x02, 0x96, 0x52, 0x8a, 0x02, 0x90, 0x02, 0xf6, 0x90, 0x00, 0x19, 0x90,
- 0x90, 0x19, 0x2e, 0x28, 0x90, 0x00, 0x00, 0x68, 0x90, 0x00, 0x02, 0x64,
- 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x0a, 0x28, 0x00, 0x00, 0xc6, 0x68,
- 0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x0a, 0x28,
- 0x01, 0x8f, 0xbd, 0x88, 0x00, 0x00, 0xc6, 0x68, 0x01, 0x80, 0x02, 0x74,
- 0x00, 0x00, 0x0a, 0x28, 0x00, 0x00, 0xc6, 0x68, 0x00, 0x00, 0x02, 0x64,
- 0x02, 0x00, 0x0a, 0x2a, 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00,
- 0x00, 0x03, 0x9c, 0x88, 0x00, 0x10, 0x02, 0xf4, 0x02, 0x00, 0x0a, 0x2a,
- 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x10, 0x02, 0xe4, 0x02, 0x00, 0x0a, 0x2a,
- 0x02, 0x00, 0xc6, 0x6a, 0x00, 0x00, 0x20, 0x00, 0x00, 0x03, 0x1b, 0xc8,
- 0x00, 0x02, 0x17, 0x88, 0x00, 0x10, 0x02, 0xf4, 0x00, 0x19, 0x2e, 0x28,
- 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, 0x02, 0x00, 0x0a, 0x2a,
- 0x02, 0x00, 0xc6, 0x6a, 0x02, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x00, 0x00,
- 0x01, 0x82, 0x22, 0x64, 0x00, 0x00, 0x0a, 0x28, 0x00, 0x00, 0xc6, 0x68,
- 0x00, 0x00, 0x00, 0x00, 0x02, 0x10, 0x07, 0xca, 0x02, 0x0c, 0x9f, 0xfa,
- 0x02, 0x00, 0x02, 0x76, 0x00, 0x19, 0x2e, 0x28, 0x00, 0x00, 0x00, 0x68,
- 0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x03, 0x00, 0x80, 0x58,
- 0x03, 0x00, 0x10, 0x2a, 0x02, 0x04, 0x03, 0xe3, 0x00, 0x00, 0x00, 0x00,
- 0x02, 0x18, 0x56, 0x15, 0x02, 0x93, 0xcf, 0x5a, 0x00, 0x94, 0x03, 0xa2,
- 0x02, 0x18, 0x56, 0x14, 0x00, 0x00, 0x20, 0x00, 0x02, 0x98, 0x56, 0x15,
- 0x00, 0x90, 0x2a, 0x58, 0x81, 0x98, 0xa0, 0x14, 0x04, 0x04, 0x00, 0x59,
- 0x00, 0x00, 0x04, 0x12, 0x00, 0x90, 0x2a, 0x59, 0x02, 0x98, 0x56, 0x14,
- 0x00, 0x1b, 0x40, 0x5b, 0x03, 0x80, 0x00, 0xf9, 0x02, 0x00, 0x00, 0xa9,
- 0x81, 0x98, 0xa0, 0x14, 0x01, 0x20, 0x00, 0x59, 0x04, 0x04, 0x01, 0xa1,
- 0x20, 0x00, 0x00, 0x12, 0xa0, 0x10, 0x6c, 0xe1, 0x00, 0x94, 0x2a, 0x59,
- 0x02, 0x98, 0x56, 0x15, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
- 0xa3, 0x9c, 0x0f, 0xf9, 0x20, 0x03, 0xe0, 0x5b, 0x81, 0x98, 0xa0, 0x14,
- 0x04, 0x04, 0x00, 0x59, 0x01, 0x20, 0x01, 0xa0, 0x00, 0x94, 0x2a, 0x59,
- 0xa0, 0x10, 0x6c, 0xe1, 0x00, 0x00, 0x00, 0x00, 0xa3, 0x9c, 0x0f, 0xf9,
- 0x81, 0x98, 0x60, 0x14, 0x04, 0x04, 0x00, 0x59, 0x01, 0x20, 0x01, 0xa0,
- 0x00, 0x94, 0x2a, 0x59, 0xa0, 0x10, 0x6c, 0xe0, 0xa3, 0x9c, 0x0f, 0xf9,
- 0x81, 0x98, 0x20, 0x14, 0x02, 0x84, 0x00, 0x59, 0x01, 0x20, 0x01, 0xa0,
- 0xa0, 0x10, 0x6c, 0xe0, 0x01, 0x14, 0x01, 0xa1, 0xa3, 0x9c, 0x0f, 0xf8,
- 0x00, 0x90, 0x03, 0xa2, 0xa0, 0x10, 0x6c, 0xe0, 0xa3, 0x9c, 0x0f, 0xf8,
- 0x02, 0x00, 0x0c, 0x2b, 0x00, 0x00, 0x00, 0xa8, 0x02, 0x00, 0xc6, 0x6b,
- 0x00, 0x00, 0x01, 0xe8, 0x00, 0x10, 0x02, 0xf4, 0x02, 0x00, 0x0e, 0x2a,
- 0x02, 0x00, 0xc6, 0x6a, 0x03, 0x90, 0x02, 0xf4, 0x00, 0x00, 0x10, 0x28,
- 0x00, 0x00, 0xc6, 0x68, 0x03, 0x80, 0x02, 0x74, 0x00, 0x0c, 0x03, 0x62,
- 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x28, 0x00, 0x00, 0xc0, 0x69,
- 0x02, 0x00, 0x10, 0x2a, 0x02, 0x00, 0x02, 0x76, 0x00, 0x0c, 0x03, 0x62,
- 0x00, 0x00, 0x80, 0x00, 0x01, 0xbc, 0x54, 0xf6, 0x02, 0x04, 0x03, 0xe2,
- 0x02, 0x13, 0xcf, 0x5a, 0x00, 0x90, 0x03, 0xa2, 0x02, 0x18, 0x50, 0x2a,
- 0x02, 0x00, 0x00, 0x6a, 0x00, 0x10, 0x03, 0x62, 0x01, 0x97, 0x30, 0x2a,
- 0x01, 0x80, 0x00, 0x6a, 0x00, 0x00, 0x40, 0x00, 0x00, 0x17, 0xb4, 0x28,
- 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x13, 0x62, 0x01, 0x97, 0x3c, 0x2a,
- 0x01, 0x80, 0x00, 0x6a, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x04, 0x29,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x69, 0x02, 0x00, 0x10, 0x2a,
- 0x02, 0x00, 0x02, 0x76, 0x00, 0x14, 0x4e, 0x28, 0x00, 0x00, 0x00, 0x68,
- 0x00, 0x00, 0x13, 0x62, 0x01, 0x97, 0x52, 0x2a, 0x01, 0x80, 0x00, 0x6a,
- 0x00, 0x00, 0x40, 0x00, 0x00, 0x11, 0x94, 0x28, 0x00, 0x00, 0x00, 0x68,
- 0x00, 0x00, 0x13, 0x62, 0x01, 0x97, 0x5e, 0x2a, 0x01, 0x80, 0x00, 0x6a,
- 0x00, 0x00, 0x40, 0x00, 0x02, 0x11, 0x4c, 0x2a, 0x02, 0x00, 0x00, 0x6a,
- 0x00, 0x10, 0x03, 0x62, 0x01, 0x97, 0x6c, 0x2a, 0x01, 0x80, 0x00, 0x6a,
- 0x02, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x20, 0x00, 0x00, 0x11, 0x4c, 0x28,
- 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x13, 0x62, 0x01, 0x97, 0x7a, 0x2a,
- 0x01, 0x80, 0x00, 0x6a, 0x02, 0x00, 0x00, 0xa8, 0x00, 0x00, 0x20, 0x00,
- 0x02, 0x04, 0x03, 0xe2, 0x00, 0x12, 0x00, 0x28, 0x02, 0x00, 0x9f, 0xfa,
- 0x00, 0x90, 0x03, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
- 0x01, 0xbc, 0x52, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x00, 0x0c, 0x03, 0x62,
- 0x00, 0x00, 0x80, 0x00, 0x07, 0xae, 0xfe, 0x2a, 0x07, 0x80, 0x00, 0x6a,
- 0x00, 0x10, 0x00, 0x28, 0x02, 0x80, 0x13, 0xa2, 0x0f, 0xff, 0xe3, 0x12,
- 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00, 0x00, 0x19, 0x30, 0x28,
- 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00,
- 0x00, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x90, 0x00, 0x20, 0x90,
- 0x01, 0x04, 0x2a, 0x58, 0x00, 0x00, 0x60, 0x00, 0xa0, 0x00, 0x0a, 0x10,
- 0x00, 0x00, 0x80, 0x00, 0x02, 0x00, 0x00, 0xfa, 0x02, 0x00, 0xc0, 0x6a,
- 0x02, 0x90, 0x02, 0xe6, 0x03, 0x00, 0x08, 0x2a, 0x00, 0x00, 0x40, 0x00,
- 0x02, 0x94, 0xcd, 0xfa, 0x02, 0x90, 0x02, 0xf6, 0x00, 0x00, 0x00, 0xf8,
- 0x00, 0x00, 0xc0, 0x68, 0x01, 0x80, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00,
- 0x01, 0x8d, 0x0d, 0xd8, 0x01, 0x80, 0x02, 0x74, 0x0f, 0xff, 0xfa, 0x90,
- 0x00, 0x00, 0x80, 0x00, 0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xeb,
- 0x01, 0x80, 0x00, 0xf8, 0x01, 0x90, 0x02, 0xf4, 0x02, 0x60, 0x80, 0x2a,
- 0x02, 0x00, 0xdb, 0xeb, 0x02, 0x00, 0x04, 0x28, 0x02, 0x10, 0x02, 0xf4,
- 0x02, 0x00, 0x22, 0x66, 0x02, 0x60, 0x88, 0x28, 0x02, 0x00, 0xdb, 0xe8,
- 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x02, 0x76, 0x02, 0x80, 0x42, 0x66,
- 0x02, 0x60, 0x8a, 0x2a, 0x02, 0x00, 0xdb, 0xea, 0x00, 0x00, 0x20, 0x00,
- 0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0xc2, 0x66, 0x02, 0x60, 0x92, 0x28,
- 0x02, 0x00, 0xdb, 0xe8, 0x00, 0x00, 0x20, 0x00, 0x02, 0x10, 0x02, 0x76,
- 0x02, 0x80, 0x62, 0x66, 0x02, 0x60, 0x8c, 0x2a, 0x02, 0x00, 0xdb, 0xea,
- 0x00, 0x00, 0x20, 0x00, 0x02, 0x90, 0x02, 0xf6, 0x02, 0x00, 0x82, 0x66,
- 0x02, 0x60, 0x8e, 0x28, 0x02, 0x00, 0xdb, 0xe8, 0x00, 0x00, 0x20, 0x00,
- 0x02, 0x10, 0x02, 0x76, 0x00, 0x00, 0xa2, 0x64, 0x02, 0x60, 0x90, 0x2a,
- 0x02, 0x00, 0xdb, 0xea, 0x00, 0x00, 0x20, 0x00, 0x00, 0x10, 0x02, 0xf4,
- 0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xea, 0x01, 0x90, 0x02, 0xf4,
- 0x02, 0x60, 0x80, 0x2a, 0x02, 0x00, 0xdb, 0xeb, 0x00, 0x00, 0x00, 0xa8,
- 0x00, 0x10, 0x02, 0xf4, 0x00, 0x0c, 0x03, 0x62, 0x00, 0x00, 0x80, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x19, 0x2a, 0x2a,
- 0x02, 0x84, 0x20, 0xfb, 0x02, 0x00, 0x00, 0x6a, 0x02, 0x90, 0x02, 0xf6,
- 0x02, 0x98, 0xe0, 0x2a, 0x02, 0x19, 0x2c, 0x2a, 0x02, 0x00, 0x00, 0x6b,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4a, 0x29, 0x02, 0x80, 0x00, 0x6a,
- 0x03, 0x94, 0x10, 0x59, 0x00, 0x10, 0x02, 0xf4, 0x00, 0x00, 0x12, 0xaa,
- 0x00, 0x80, 0x00, 0xa8, 0x04, 0x08, 0x00, 0x28, 0x04, 0x00, 0x00, 0x68,
- 0x20, 0x03, 0xe0, 0x5b, 0x90, 0x14, 0x02, 0x64, 0x20, 0x00, 0x00, 0x12,
- 0x93, 0x1c, 0x36, 0x74, 0x00, 0x00, 0x00, 0x00, 0x03, 0x20, 0x02, 0x65,
- 0x02, 0x19, 0x2a, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x79,
- 0x01, 0xa0, 0x36, 0x65, 0x02, 0x00, 0x00, 0x68, 0x80, 0x87, 0xe0, 0x59,
- 0x90, 0x14, 0x02, 0x75, 0x02, 0x90, 0x01, 0xa0, 0x00, 0x14, 0x02, 0x64,
- 0x00, 0x00, 0x40, 0x00, 0x03, 0x1c, 0x36, 0x74, 0x00, 0x00, 0x60, 0x78,
- 0x00, 0x14, 0x02, 0x74, 0x00, 0x19, 0x2a, 0x28, 0x00, 0x00, 0x00, 0x68,
- 0x00, 0x18, 0xe0, 0x29, 0x00, 0x00, 0x02, 0x66, 0x00, 0x00, 0x00, 0x68,
- 0x00, 0x00, 0x40, 0x00, 0x31, 0x80, 0x80, 0x59, 0x32, 0x19, 0x2e, 0x2a,
- 0x32, 0x00, 0x00, 0x6a, 0x31, 0x90, 0x02, 0xf4, 0x30, 0x02, 0x9d, 0x41,
- 0x32, 0x19, 0x30, 0x2a, 0x32, 0x00, 0x00, 0x6a, 0x30, 0x10, 0x02, 0xf4,
- 0x30, 0x00, 0x09, 0x12, 0x00, 0x00, 0x80, 0x00, 0x02, 0x80, 0x00, 0xfa,
- 0x02, 0x80, 0xc0, 0x6a, 0x03, 0x14, 0x02, 0xe6, 0x02, 0x00, 0x08, 0x2a,
- 0x00, 0x00, 0x40, 0x00, 0x02, 0x18, 0x8d, 0xfa, 0x02, 0x14, 0x02, 0xf6,
- 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0xc0, 0x68, 0x01, 0x80, 0x02, 0x64,
- 0x00, 0x00, 0x60, 0x00, 0x01, 0x8d, 0x0d, 0xd8, 0x01, 0x80, 0x02, 0x74,
- 0x0f, 0xff, 0xf9, 0x90, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62,
- 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static int load_bootstrap(void)
-{
- const u8 *s = bootstrap_rbin;
- u32 l = sizeof(bootstrap_rbin);
- const u8 *data, *hdr, *h;
- u32 chksum, chksum2;
- int i, j, rangenr;
- u32 start, length;
-
- if (l < 12) {
- printf("bootstrap image corrupted. (too short header)\n");
- return -1;
- }
-
- chksum = ((u32)s[4] << 24) | ((u32)s[5] << 16) | ((u32)s[ 6] << 8) | (u32)s[ 7];
- rangenr = ((u32)s[8] << 24) | ((u32)s[9] << 16) | ((u32)s[10] << 8) | (u32)s[11];
- s += 12; l -= 12;
-
- hdr = s;
- s += 8 * rangenr; l -= 8 * rangenr;
- data = s;
-
- /* validate bootstrap image */
- h = hdr; s = data; chksum2 = 0;
- for (i = 0; i < rangenr; i++) {
- start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3];
- length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7];
- h += 8;
-
- /* too short */
- if (l < length) {
- printf("bootstrap image corrupted. (too short data)\n");
- return -1;
- }
- l -= length;
-
- j = (int)length / 4;
- while (j-- > 0) {
- chksum2 += ((u32)s[0] << 24) | ((u32)s[1] << 16) | ((u32)s[2] << 8) | (u32)s[3];
- s += 4;
- }
- }
-
- /* checksum must match */
- if (chksum != chksum2) {
- printf("bootstrap image corrupted. (checksum error)\n");
- return -1;
- }
-
- /* nothing must be left */
- if (l != 0) {
- printf("bootstrap image corrupted. (garbage at the end)\n");
- return -1;
- }
-
- /* write the image */
- h = hdr;
- s = data;
- for (i = 0; i < rangenr; i++) {
- start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3];
- length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7];
- h += 8;
- c62_write(start, (u32 *)s, length / 4);
- s += length;
- }
-
- /* and now validate checksum */
- h = hdr;
- s = data;
- chksum2 = 0;
- for (i = 0; i < rangenr; i++) {
- start = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] << 8) | (u32)h[3];
- length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] << 8) | (u32)h[7];
- h += 8;
- chksum2 += c62_checksum(start, length / 4);
- s += length;
- }
-
- /* checksum must match */
- if (chksum != chksum2) {
- printf("bootstrap in DSP memory is corrupted\n");
- return -1;
- }
-
- return 0;
-}
-
-struct host_init {
- u32 master_mode;
- struct {
- u8 port_id;
- u8 slot_id;
- } ch_serial_map[32];
- u32 clk_divider[2];
- /* pll */
- u32 initmode;
- u32 pllm;
- u32 div[4];
- u32 oscdiv1;
- u32 unused[10];
-};
-
-const struct host_init hi_default = {
- .master_mode =
-#if !defined(CONFIG_NETTA_ISDN)
- -1,
-#else
- 0,
-#endif
-
- .ch_serial_map = {
- [ 0] = { .port_id = 2, .slot_id = 16 },
- [ 1] = { .port_id = 2, .slot_id = 17 },
- [ 2] = { .port_id = 2, .slot_id = 18 },
- [ 3] = { .port_id = 2, .slot_id = 19 },
- [ 4] = { .port_id = 2, .slot_id = 20 },
- [ 5] = { .port_id = 2, .slot_id = 21 },
- [ 6] = { .port_id = 2, .slot_id = 22 },
- [ 7] = { .port_id = 2, .slot_id = 23 },
- [ 8] = { .port_id = 2, .slot_id = 24 },
- [ 9] = { .port_id = 2, .slot_id = 25 },
- [10] = { .port_id = 2, .slot_id = 26 },
- [11] = { .port_id = 2, .slot_id = 27 },
- [12] = { .port_id = 2, .slot_id = 28 },
- [13] = { .port_id = 2, .slot_id = 29 },
- [14] = { .port_id = 2, .slot_id = 30 },
- [15] = { .port_id = 2, .slot_id = 31 },
- },
-
- /*
- dsp_clk(xin, pllm) = xin * pllm
- serial_clk(xin, pllm, div) = (dsp_clk(xin, pllm) / 2) / (div + 1)
- */
-
- .clk_divider = {
- [0] = 47, /* must be 2048Hz */
- [1] = 47,
- },
-
- .initmode = 1,
- .pllm =
-#if !defined(CONFIG_NETTA_ISDN)
- 8, /* for =~ 25MHz 8 */
-#else
- 4,
-#endif
- .div = {
- [0] = 0x8000,
- [1] = 0x8000, /* for =~ 25MHz 0x8000 */
- [2] = 0x8001, /* for =~ 25MHz 0x8001 */
- [3] = 0x8001, /* for =~ 25MHz 0x8001 */
- },
-
- .oscdiv1 = 0,
-};
-
-static void hi_write(const struct host_init *hi)
-{
- u32 hi_buf[1 + sizeof(*hi) / sizeof(u32)];
- u32 *s;
- u32 chksum;
- int i;
-
- memset(hi_buf, 0, sizeof(hi_buf));
-
- s = hi_buf;
- s++;
- *s++ = hi->master_mode;
- for (i = 0; i < (sizeof(hi->ch_serial_map) / sizeof(hi->ch_serial_map[0])) / 2; i++)
- *s++ = ((u32)hi->ch_serial_map[i * 2 + 1].slot_id << 24) | ((u32)hi->ch_serial_map[i * 2 + 1].port_id << 16) |
- ((u32)hi->ch_serial_map[i * 2 + 0].slot_id << 8) | (u32)hi->ch_serial_map[i * 2 + 0].port_id;
-
- for (i = 0; i < sizeof(hi->clk_divider)/sizeof(hi->clk_divider[0]); i++)
- *s++ = hi->clk_divider[i];
-
- *s++ = hi->initmode;
- *s++ = hi->pllm;
- for (i = 0; i < sizeof(hi->div)/sizeof(hi->div[0]); i++)
- *s++ = hi->div[i];
- *s++ = hi->oscdiv1;
-
- chksum = 0;
- for (i = 1; i < sizeof(hi_buf)/sizeof(hi_buf[0]); i++)
- chksum += hi_buf[i];
- hi_buf[0] = -chksum;
-
- c62_write(0x1000, hi_buf, sizeof(hi_buf) / sizeof(hi_buf[0]));
-}
-
-static void run_bootstrap(void)
-{
- dsp_go_slow();
-
- hi_write(&hi_default);
-
- /* signal interrupt */
- dsp_write_hpic(0x0002);
- dsp_delay();
-
- dsp_go_fast();
-}
-
-#endif
-
-/***********************************************************************************************************/
-
-int board_post_dsp(int flags)
-{
- u32 ramS, ramE;
- u32 data, data2;
- int i, j, k;
-#if !defined(CONFIG_NETTA_6412)
- int r;
-#endif
- dsp_reset();
- dsp_init_hpic();
-#if !defined(CONFIG_NETTA_6412)
- dsp_go_slow();
-#endif
- data = 0x11223344;
- dsp_write_hpic_word(DSP_HPIA, data);
- data2 = dsp_read_hpic_word(DSP_HPIA);
- if (data2 != 0x11223344) {
- printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2);
- goto err;
- }
-
- data = 0xFFEEDDCC;
- dsp_write_hpic_word(DSP_HPIA, data);
- data2 = dsp_read_hpic_word(DSP_HPIA);
- if (data2 != 0xFFEEDDCC) {
- printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2);
- goto err;
- }
-#if defined(CONFIG_NETTA_6412)
- dsp_dram_initialize();
-#else
- r = load_bootstrap();
- if (r < 0) {
- printf("BOOTSTRAP: ** ERROR ** failed to load\n");
- goto err;
- }
-
- run_bootstrap();
-
- dsp_go_fast();
-#endif
- printf(" ");
-
- /* test RAMs */
- for (k = 0; k < sizeof(ranges)/sizeof(ranges[0]); k++) {
-
- ramS = ranges[k].start;
- ramE = ranges[k].start + ranges[k].size;
-
- for (j = 0; j < 3; j++) {
-
- printf("\b\b\b\bR%d.%d", k, j);
-
- for (i = ramS; i < ramE; i += 4) {
-
- data = 0;
- switch (j) {
- case 0: data = 0xAA55AA55; break;
- case 1: data = 0x55AA55AA; break;
- case 2: data = (u32)i; break;
- }
-
- c62_write_word(i, data);
- data2 = c62_read_word(i);
- if (data != data2) {
- printf(" ** ERROR at 0x%08X; wrote 0x%08X read 0x%08X **\n", i, data, data2);
- goto err;
- }
- }
- }
- }
-
- printf("\b\b\b\b \b\b\b\bOK\n");
-#if !defined(CONFIG_NETTA_6412)
- /* XXX assume that this works */
- load_bootstrap();
- run_bootstrap();
- dsp_go_fast();
-#endif
- return 0;
-
-err:
- return -1;
-}
-
-int board_dsp_reset(void)
-{
-#if !defined(CONFIG_NETTA_6412)
- int r;
-#endif
- dsp_reset();
- dsp_init_hpic();
-#if defined(CONFIG_NETTA_6412)
- dsp_dram_initialize();
-#else
- dsp_go_slow();
- r = load_bootstrap();
- if (r < 0)
- return r;
-
- run_bootstrap();
- dsp_go_fast();
-#endif
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_byte(flash_info_t * info, ulong dest, uchar data);
-static void flash_get_offsets(ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size;
- int i;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
-
- /* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-
-#ifdef CONFIG_ENV_ADDR_REDUND
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-#endif
-
-
- flash_info[0].size = size;
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets(ulong base, flash_info_t * info)
-{
- int i;
-
- /* set up sector start address table */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000);
- }
- } else if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf("FUJITSU ");
- break;
- case FLASH_MAN_MX:
- printf("MXIC ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400B:
- printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T:
- printf("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B:
- printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T:
- printf("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B:
- printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T:
- printf("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B:
- printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T:
- printf("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- break;
- }
-
- printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-{
- short i;
- uchar mid;
- uchar pid;
- vu_char *caddr = (vu_char *) addr;
- ulong base = (ulong) addr;
-
-
- /* Write auto select command: read Manufacturer ID */
- caddr[0x0555] = 0xAA;
- caddr[0x02AA] = 0x55;
- caddr[0x0555] = 0x90;
-
- mid = caddr[0];
- switch (mid) {
- case (AMD_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FUJ_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (MX_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_MX;
- break;
- case (STM_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- pid = caddr[1]; /* device ID */
- switch (pid) {
- case (AMD_ID_LV400T & 0xFF):
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case (AMD_ID_LV400B & 0xFF):
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case (AMD_ID_LV800T & 0xFF):
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV800B & 0xFF):
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV160T & 0xFF):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV160B & 0xFF):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV040B & 0xFF):
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break;
-
- case (STM_ID_M29W040B & 0xFF):
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break;
-
-#if 0 /* enable when device IDs are available */
- case (AMD_ID_LV320T & 0xFF):
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_LV320B & 0xFF):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- printf(" ");
- /* set up sector start address table */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000);
- }
- } else if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection: D0 = 1 if protected */
- caddr = (volatile unsigned char *)(info->start[i]);
- info->protect[i] = caddr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- caddr = (vu_char *) info->start[0];
-
- caddr[0x0555] = 0xAA;
- caddr[0x02AA] = 0x55;
- caddr[0x0555] = 0xF0;
-
- udelay(20000);
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
- vu_char *addr = (vu_char *) (info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("- missing\n");
- } else {
- printf("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0x80;
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_char *) (info->start[sect]);
- addr[0] = 0x30;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer(0);
- last = start;
- addr = (vu_char *) (info->start[l_sect]);
- while ((addr[0] & 0x80) != 0x80) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- addr = (vu_char *) info->start[0];
- addr[0] = 0xF0; /* reset bank */
-
- printf(" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- int rc;
-
- while (cnt > 0) {
- if ((rc = write_byte(info, addr++, *src++)) != 0) {
- return (rc);
- }
- --cnt;
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_byte(flash_info_t * info, ulong dest, uchar data)
-{
- vu_char *addr = (vu_char *) (info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_char *) dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0xA0;
-
- *((vu_char *) dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer(0);
- while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetTA4 board
- */
-
-#include <common.h>
-#include <miiphy.h>
-
-#include "mpc8xx.h"
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-#endif
-
-int fec8xx_miiphy_read(char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value);
-int fec8xx_miiphy_write(char *devname, unsigned char addr,
- unsigned char reg, unsigned short value);
-
-/****************************************************************/
-
-/* some sane bit macros */
-#define _BD(_b) (1U << (31-(_b)))
-#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
-
-#define _BW(_b) (1U << (15-(_b)))
-#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
-
-#define _BB(_b) (1U << (7-(_b)))
-#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
-
-#define _B(_b) _BD(_b)
-#define _BR(_l, _h) _BDR(_l, _h)
-
-/****************************************************************/
-
-/*
- * Check Board Identity:
- *
- * Return 1 always.
- */
-
-int checkboard(void)
-{
- printf ("Intracom NETTA"
-#if defined(CONFIG_NETTA_ISDN)
- " with ISDN support"
-#endif
-#if defined(CONFIG_NETTA_6412)
- " (DSP:TI6412)"
-#else
- " (DSP:TI6711)"
-#endif
- "\n"
- );
- return (0);
-}
-
-/****************************************************************/
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-/****************************************************************/
-
-#define CS_0000 0x00000000
-#define CS_0001 0x10000000
-#define CS_0010 0x20000000
-#define CS_0011 0x30000000
-#define CS_0100 0x40000000
-#define CS_0101 0x50000000
-#define CS_0110 0x60000000
-#define CS_0111 0x70000000
-#define CS_1000 0x80000000
-#define CS_1001 0x90000000
-#define CS_1010 0xA0000000
-#define CS_1011 0xB0000000
-#define CS_1100 0xC0000000
-#define CS_1101 0xD0000000
-#define CS_1110 0xE0000000
-#define CS_1111 0xF0000000
-
-#define BS_0000 0x00000000
-#define BS_0001 0x01000000
-#define BS_0010 0x02000000
-#define BS_0011 0x03000000
-#define BS_0100 0x04000000
-#define BS_0101 0x05000000
-#define BS_0110 0x06000000
-#define BS_0111 0x07000000
-#define BS_1000 0x08000000
-#define BS_1001 0x09000000
-#define BS_1010 0x0A000000
-#define BS_1011 0x0B000000
-#define BS_1100 0x0C000000
-#define BS_1101 0x0D000000
-#define BS_1110 0x0E000000
-#define BS_1111 0x0F000000
-
-#define A10_AAAA 0x00000000
-#define A10_AAA0 0x00200000
-#define A10_AAA1 0x00300000
-#define A10_000A 0x00800000
-#define A10_0000 0x00A00000
-#define A10_0001 0x00B00000
-#define A10_111A 0x00C00000
-#define A10_1110 0x00E00000
-#define A10_1111 0x00F00000
-
-#define RAS_0000 0x00000000
-#define RAS_0001 0x00040000
-#define RAS_1110 0x00080000
-#define RAS_1111 0x000C0000
-
-#define CAS_0000 0x00000000
-#define CAS_0001 0x00010000
-#define CAS_1110 0x00020000
-#define CAS_1111 0x00030000
-
-#define WE_0000 0x00000000
-#define WE_0001 0x00004000
-#define WE_1110 0x00008000
-#define WE_1111 0x0000C000
-
-#define GPL4_0000 0x00000000
-#define GPL4_0001 0x00001000
-#define GPL4_1110 0x00002000
-#define GPL4_1111 0x00003000
-
-#define GPL5_0000 0x00000000
-#define GPL5_0001 0x00000400
-#define GPL5_1110 0x00000800
-#define GPL5_1111 0x00000C00
-#define LOOP 0x00000080
-
-#define EXEN 0x00000040
-
-#define AMX_COL 0x00000000
-#define AMX_ROW 0x00000020
-#define AMX_MAR 0x00000030
-
-#define NA 0x00000008
-
-#define UTA 0x00000004
-
-#define TODT 0x00000002
-
-#define LAST 0x00000001
-
-/* #define CAS_LATENCY 3 */
-#define CAS_LATENCY 2
-
-const uint sdram_table[0x40] = {
-
-#if CAS_LATENCY == 3
- /* RSS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_,
-
- /* RBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WSS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-#endif
-
-#if CAS_LATENCY == 2
- /* RSS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
- /* RBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WSS */
- CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
- CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_,
-
- /* WBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
- CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
- CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
-#endif
-
- /* UPT */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
- /* EXC */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
- _NOT_USED_,
-
- /* REG */
- CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
- CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
-};
-
-/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
-/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
-#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
-
-/* 8 */
-#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-void check_ram(unsigned int addr, unsigned int size)
-{
- unsigned int i, j, v, vv;
- volatile unsigned int *p;
- unsigned int pv;
-
- p = (unsigned int *)addr;
- pv = (unsigned int)p;
- for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
- *p++ = pv;
-
- p = (unsigned int *)addr;
- for (i = 0; i < size / sizeof(unsigned int); i++) {
- v = (unsigned int)p;
- vv = *p;
- if (vv != v) {
- printf("%p: read %08x instead of %08x\n", p, vv, v);
- hang();
- }
- p++;
- }
-
- for (j = 0; j < 5; j++) {
- switch (j) {
- case 0: v = 0x00000000; break;
- case 1: v = 0xffffffff; break;
- case 2: v = 0x55555555; break;
- case 3: v = 0xaaaaaaaa; break;
- default:v = 0xdeadbeef; break;
- }
- p = (unsigned int *)addr;
- for (i = 0; i < size / sizeof(unsigned int); i++) {
- *p = v;
- vv = *p;
- if (vv != v) {
- printf("%p: read %08x instead of %08x\n", p, vv, v);
- hang();
- }
- *p = ~v;
- p++;
- }
- }
-}
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size;
-
- upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
-
- /*
- * Preliminary prescaler for refresh
- */
- memctl->memc_mptpr = MPTPR_PTP_DIV8;
-
- memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
-
- /*
- * Map controller bank 3 to the SDRAM bank at preliminary address.
- */
- memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
- memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */
-
- udelay(200);
-
- /* perform SDRAM initialisation sequence */
- memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
- udelay(1);
-
- memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
- udelay(1);
-
- memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
- udelay(1);
-
- memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
-
- udelay(10000);
-
- {
- u32 d1, d2;
-
- d1 = 0xAA55AA55;
- *(volatile u32 *)0 = d1;
- d2 = *(volatile u32 *)0;
- if (d1 != d2) {
- printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
- hang();
- }
-
- d1 = 0x55AA55AA;
- *(volatile u32 *)0 = d1;
- d2 = *(volatile u32 *)0;
- if (d1 != d2) {
- printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
- hang();
- }
- }
-
- size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
-
-#if 0
- printf("check 0\n");
- check_ram(( 0 << 20), (2 << 20));
- printf("check 16\n");
- check_ram((16 << 20), (2 << 20));
- printf("check 32\n");
- check_ram((32 << 20), (2 << 20));
- printf("check 48\n");
- check_ram((48 << 20), (2 << 20));
-#endif
-
- if (size == 0) {
- printf("SIZE is zero: LOOP on 0\n");
- for (;;) {
- *(volatile u32 *)0 = 0;
- (void)*(volatile u32 *)0;
- }
- }
-
- return size;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_r(void)
-{
- return(0);
-}
-
-void reset_phys(void)
-{
- int phyno;
- unsigned short v;
-
- /* reset the damn phys */
- mii_init();
-
- for (phyno = 0; phyno < 32; ++phyno) {
- fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
- if (v == 0xFFFF)
- continue;
- fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
- udelay(10000);
- fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
- BMCR_RESET | BMCR_ANENABLE);
- udelay(10000);
- }
-}
-
-extern int board_dsp_reset(void);
-
-int last_stage_init(void)
-{
- int r;
-
- reset_phys();
- r = board_dsp_reset();
- if (r < 0)
- printf("*** WARNING *** DSP reset failed (run diagnostics)\n");
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* GP = general purpose, SP = special purpose (on chip peripheral) */
-
-/* bits that can have a special purpose or can be configured as inputs/outputs */
-#define PA_GP_INMASK (_BWR(3) | _BWR(7, 9) | _BW(11))
-#define PA_GP_OUTMASK (_BW(6) | _BW(10) | _BWR(12, 15))
-#define PA_SP_MASK (_BWR(0, 2) | _BWR(4, 5))
-#define PA_ODR_VAL 0
-#define PA_GP_OUTVAL (_BW(13) | _BWR(14, 15))
-#define PA_SP_DIRVAL 0
-
-#define PB_GP_INMASK (_B(28) | _B(31))
-#define PB_GP_OUTMASK (_BR(15, 19) | _BR(26, 27) | _BR(29, 30))
-#define PB_SP_MASK (_BR(22, 25))
-#define PB_ODR_VAL 0
-#define PB_GP_OUTVAL (_BR(15, 19) | _BR(26, 27) | _BR(29, 31))
-#define PB_SP_DIRVAL 0
-
-#define PC_GP_INMASK (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15))
-#define PC_GP_OUTMASK (_BW(6) | _BW(12))
-#define PC_SP_MASK (_BW(4) | _BW(8))
-#define PC_SOVAL 0
-#define PC_INTVAL _BW(7)
-#define PC_GP_OUTVAL (_BW(6) | _BW(12))
-#define PC_SP_DIRVAL 0
-
-#define PD_GP_INMASK 0
-#define PD_GP_OUTMASK _BWR(3, 15)
-#define PD_SP_MASK 0
-
-#if defined(CONFIG_NETTA_6412)
-
-#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15))
-
-#else
-
-#define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11))
-
-#endif
-
-#define PD_SP_DIRVAL 0
-
-int board_early_init_f(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile iop8xx_t *ioport = &immap->im_ioport;
- volatile cpm8xx_t *cpm = &immap->im_cpm;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- /* CS1: NAND chip select */
- memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ;
- memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
-#if !defined(CONFIG_NETTA_6412)
- /* CS2: DSP */
- memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
- memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
-#else
- /* CS6: DSP */
- memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
- memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
-#endif
- /* CS4: External register chip select */
- memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
- memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
-
- /* CS5: dummy for accurate delay */
- memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2);
- memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
-
- ioport->iop_padat = PA_GP_OUTVAL;
- ioport->iop_paodr = PA_ODR_VAL;
- ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
- ioport->iop_papar = PA_SP_MASK;
-
- cpm->cp_pbdat = PB_GP_OUTVAL;
- cpm->cp_pbodr = PB_ODR_VAL;
- cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
- cpm->cp_pbpar = PB_SP_MASK;
-
- ioport->iop_pcdat = PC_GP_OUTVAL;
- ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
- ioport->iop_pcso = PC_SOVAL;
- ioport->iop_pcint = PC_INTVAL;
- ioport->iop_pcpar = PC_SP_MASK;
-
- ioport->iop_pddat = PD_GP_OUTVAL;
- ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL;
- ioport->iop_pdpar = PD_SP_MASK;
-
- /* ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7)); */
-
- return 0;
-}
-
-#if defined(CONFIG_CMD_PCMCIA)
-
-int pcmcia_init(void)
-{
- return 0;
-}
-
-#endif
-
-#ifdef CONFIG_HW_WATCHDOG
-
-void hw_watchdog_reset(void)
-{
- /* XXX add here the really funky stuff */
-}
-
-#endif
+++ /dev/null
-#include <common.h>
-#include <mpc8xx.h>
-#include <pcmcia.h>
-
-#undef CONFIG_PCMCIA
-
-#if defined(CONFIG_CMD_PCMCIA)
-#define CONFIG_PCMCIA
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
-#define CONFIG_PCMCIA
-#endif
-
-#ifdef CONFIG_PCMCIA
-
-/* some sane bit macros */
-#define _BD(_b) (1U << (31-(_b)))
-#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
-
-#define _BW(_b) (1U << (15-(_b)))
-#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
-
-#define _BB(_b) (1U << (7-(_b)))
-#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
-
-#define _B(_b) _BD(_b)
-#define _BR(_l, _h) _BDR(_l, _h)
-
-#define PCMCIA_BOARD_MSG "NETTA"
-
-static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) };
-
-static void cfg_vppd(int no)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- unsigned short mask;
-
- if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
- return;
-
- mask = vppd_masks[no];
-
- immap->im_ioport.iop_papar &= ~mask;
- immap->im_ioport.iop_paodr &= ~mask;
- immap->im_ioport.iop_padir |= mask;
-}
-
-static void set_vppd(int no, int what)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- unsigned short mask;
-
- if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
- return;
-
- mask = vppd_masks[no];
-
- if (what)
- immap->im_ioport.iop_padat |= mask;
- else
- immap->im_ioport.iop_padat &= ~mask;
-}
-
-static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) };
-
-static void cfg_vccd(int no)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- unsigned short mask;
-
- if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
- return;
-
- mask = vccd_masks[no];
-
- immap->im_ioport.iop_papar &= ~mask;
- immap->im_ioport.iop_paodr &= ~mask;
- immap->im_ioport.iop_padir |= mask;
-}
-
-static void set_vccd(int no, int what)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- unsigned short mask;
-
- if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
- return;
-
- mask = vccd_masks[no];
-
- if (what)
- immap->im_ioport.iop_padat |= mask;
- else
- immap->im_ioport.iop_padat &= ~mask;
-}
-
-static const unsigned short oc_mask = _BW(8);
-
-static void cfg_oc(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- unsigned short mask = oc_mask;
-
- immap->im_ioport.iop_pcdir &= ~mask;
- immap->im_ioport.iop_pcso &= ~mask;
- immap->im_ioport.iop_pcint &= ~mask;
- immap->im_ioport.iop_pcpar &= ~mask;
-}
-
-static int get_oc(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- unsigned short mask = oc_mask;
- int what;
-
- what = !!(immap->im_ioport.iop_pcdat & mask);;
- return what;
-}
-
-static const unsigned short shdn_mask = _BW(12);
-
-static void cfg_shdn(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- unsigned short mask;
-
- mask = shdn_mask;
-
- immap->im_ioport.iop_papar &= ~mask;
- immap->im_ioport.iop_paodr &= ~mask;
- immap->im_ioport.iop_padir |= mask;
-}
-
-static void set_shdn(int what)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- unsigned short mask;
-
- mask = shdn_mask;
-
- if (what)
- immap->im_ioport.iop_padat |= mask;
- else
- immap->im_ioport.iop_padat &= ~mask;
-}
-
-static void cfg_ports (void)
-{
- cfg_vppd(0); cfg_vppd(1); /* VPPD0,VPPD1 VAVPP => Hi-Z */
- cfg_vccd(0); cfg_vccd(1); /* 3V and 5V off */
- cfg_shdn();
- cfg_oc();
-
- /*
- * Configure Port A for TPS2211 PC-Card Power-Interface Switch
- *
- * Switch off all voltages, assert shutdown
- */
- set_vppd(0, 1); set_vppd(1, 1);
- set_vccd(0, 0); set_vccd(1, 0);
- set_shdn(1);
-
- udelay(100000);
-}
-
-int pcmcia_hardware_enable(int slot)
-{
- volatile pcmconf8xx_t *pcmp;
- uint reg, pipr, mask;
- int i;
-
- debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- udelay(10000);
-
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
- /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
- cfg_ports ();
-
- /* clear interrupt state, and disable interrupts */
- pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
- pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
- /*
- * Disable interrupts, DMA, and PCMCIA buffers
- * (isolate the interface) and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(500);
-
- /*
- * Make sure there is a card in the slot, then configure the interface.
- */
- udelay(10000);
- debug ("[%d] %s: PIPR(%p)=0x%x\n",
- __LINE__,__FUNCTION__,
- &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
- if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
- printf (" No Card found\n");
- return (1);
- }
-
- /*
- * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
- */
- mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
- pipr = pcmp->pcmc_pipr;
- debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
- pipr,
- (reg&PCMCIA_VS1(slot))?"n":"ff",
- (reg&PCMCIA_VS2(slot))?"n":"ff");
-
- if ((pipr & mask) == mask) {
- set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */
- set_vccd(0, 0); set_vccd(1, 1); /* 5V on, 3V off */
- puts (" 5.0V card found: ");
- } else {
- set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */
- set_vccd(0, 1); set_vccd(1, 0); /* 5V off, 3V on */
- puts (" 3.3V card found: ");
- }
-
- /* Wait 500 ms; use this to check for over-current */
- for (i=0; i<5000; ++i) {
- if (!get_oc()) {
- printf (" *** Overcurrent - Safety shutdown ***\n");
- set_vccd(0, 0); set_vccd(1, 0); /* VAVPP => Hi-Z */
- return (1);
- }
- udelay (100);
- }
-
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- udelay(250000); /* some cards need >150 ms to come up :-( */
-
- debug ("# hardware_enable done\n");
-
- return (0);
-}
-
-
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_hardware_disable(int slot)
-{
- u_long reg;
-
- debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
- /* Configure PCMCIA General Control Register */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = 0;
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
-
- /* All voltages off / Hi-Z */
- set_vppd(0, 1); set_vppd(1, 1);
- set_vccd(0, 1); set_vccd(1, 1);
-
- udelay(10000);
-
- return (0);
-}
-#endif
-
-
-int pcmcia_voltage_set(int slot, int vcc, int vpp)
-{
- volatile pcmconf8xx_t *pcmp;
- u_long reg;
-
- debug ("voltage_set: "
- PCMCIA_BOARD_MSG
- " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
- 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
- /*
- * Disable PCMCIA buffers (isolate the interface)
- * and assert RESET signal
- */
- debug ("Disable PCMCIA buffers and assert RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- /*
- * Configure Port C pins for
- * 5 Volts Enable and 3 Volts enable,
- * Turn all power pins to Hi-Z
- */
- debug ("PCMCIA power OFF\n");
- cfg_ports (); /* Enables switch, but all in Hi-Z */
-
- set_vppd(0, 1); set_vppd(1, 1);
-
- switch(vcc) {
- case 0:
- break; /* Switch off */
-
- case 33:
- set_vccd(0, 1); set_vccd(1, 0);
- break;
-
- case 50:
- set_vccd(0, 0); set_vccd(1, 1);
- break;
-
- default:
- goto done;
- }
-
- /* Checking supported voltages */
-
- debug ("PIPR: 0x%x --> %s\n",
- pcmp->pcmc_pipr,
- (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
-
-done:
- debug ("Enable PCMCIA buffers and stop RESET\n");
- reg = PCMCIA_PGCRX(_slot_);
- reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
- reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
- PCMCIA_PGCRX(_slot_) = reg;
- udelay(500);
-
- debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
- slot+'A');
- return (0);
-}
-
-#endif /* CONFIG_PCMCIA */
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = netta2.o flash.o
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_byte(flash_info_t * info, ulong dest, uchar data);
-static void flash_get_offsets(ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size;
- int i;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size << 20);
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
-
- /* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-
-#ifdef CONFIG_ENV_ADDR_REDUND
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-#endif
-
- flash_info[0].size = size;
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets(ulong base, flash_info_t * info)
-{
- int i;
-
- /* set up sector start address table */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000);
- }
- } else if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf("FUJITSU ");
- break;
- case FLASH_MAN_MX:
- printf("MXIC ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400B:
- printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T:
- printf("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B:
- printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T:
- printf("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B:
- printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T:
- printf("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B:
- printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T:
- printf("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- break;
- }
-
- printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-{
- short i;
- uchar mid;
- uchar pid;
- vu_char *caddr = (vu_char *) addr;
- ulong base = (ulong) addr;
-
- /* Write auto select command: read Manufacturer ID */
- caddr[0x0555] = 0xAA;
- caddr[0x02AA] = 0x55;
- caddr[0x0555] = 0x90;
-
- mid = caddr[0];
- switch (mid) {
- case (AMD_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FUJ_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (MX_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_MX;
- break;
- case (STM_MANUFACT & 0xFF):
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- pid = caddr[1]; /* device ID */
- switch (pid) {
- case (AMD_ID_LV400T & 0xFF):
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case (AMD_ID_LV400B & 0xFF):
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 512 kB */
-
- case (AMD_ID_LV800T & 0xFF):
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV800B & 0xFF):
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV160T & 0xFF):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV160B & 0xFF):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV040B & 0xFF):
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break;
-
- case (STM_ID_M29W040B & 0xFF):
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break;
-
-#if 0 /* enable when device IDs are available */
- case (AMD_ID_LV320T & 0xFF):
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_LV320B & 0xFF):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- printf(" ");
- /* set up sector start address table */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000);
- }
- } else if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection: D0 = 1 if protected */
- caddr = (volatile unsigned char *)(info->start[i]);
- info->protect[i] = caddr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- caddr = (vu_char *) info->start[0];
-
- caddr[0x0555] = 0xAA;
- caddr[0x02AA] = 0x55;
- caddr[0x0555] = 0xF0;
-
- udelay(20000);
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
- vu_char *addr = (vu_char *) (info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("- missing\n");
- } else {
- printf("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0x80;
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_char *) (info->start[sect]);
- addr[0] = 0x30;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer(0);
- last = start;
- addr = (vu_char *) (info->start[l_sect]);
- while ((addr[0] & 0x80) != 0x80) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (vu_char *) info->start[0];
- addr[0] = 0xF0; /* reset bank */
-
- printf(" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- int rc;
-
- while (cnt > 0) {
- if ((rc = write_byte(info, addr++, *src++)) != 0) {
- return (rc);
- }
- --cnt;
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_byte(flash_info_t * info, ulong dest, uchar data)
-{
- vu_char *addr = (vu_char *) (info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_char *) dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0xA0;
-
- *((vu_char *) dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer(0);
- while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetTA4 board
- */
-
-#include <common.h>
-#include <miiphy.h>
-
-#include "mpc8xx.h"
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-#endif
-
-int fec8xx_miiphy_read(char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value);
-int fec8xx_miiphy_write(char *devname, unsigned char addr,
- unsigned char reg, unsigned short value);
-
-/****************************************************************/
-
-/* some sane bit macros */
-#define _BD(_b) (1U << (31-(_b)))
-#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
-
-#define _BW(_b) (1U << (15-(_b)))
-#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
-
-#define _BB(_b) (1U << (7-(_b)))
-#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
-
-#define _B(_b) _BD(_b)
-#define _BR(_l, _h) _BDR(_l, _h)
-
-/****************************************************************/
-
-/*
- * Check Board Identity:
- *
- * Return 1 always.
- */
-
-int checkboard(void)
-{
- printf ("Intracom NetTA2 V%d\n", CONFIG_NETTA2_VERSION);
- return (0);
-}
-
-/****************************************************************/
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-/****************************************************************/
-
-#define CS_0000 0x00000000
-#define CS_0001 0x10000000
-#define CS_0010 0x20000000
-#define CS_0011 0x30000000
-#define CS_0100 0x40000000
-#define CS_0101 0x50000000
-#define CS_0110 0x60000000
-#define CS_0111 0x70000000
-#define CS_1000 0x80000000
-#define CS_1001 0x90000000
-#define CS_1010 0xA0000000
-#define CS_1011 0xB0000000
-#define CS_1100 0xC0000000
-#define CS_1101 0xD0000000
-#define CS_1110 0xE0000000
-#define CS_1111 0xF0000000
-
-#define BS_0000 0x00000000
-#define BS_0001 0x01000000
-#define BS_0010 0x02000000
-#define BS_0011 0x03000000
-#define BS_0100 0x04000000
-#define BS_0101 0x05000000
-#define BS_0110 0x06000000
-#define BS_0111 0x07000000
-#define BS_1000 0x08000000
-#define BS_1001 0x09000000
-#define BS_1010 0x0A000000
-#define BS_1011 0x0B000000
-#define BS_1100 0x0C000000
-#define BS_1101 0x0D000000
-#define BS_1110 0x0E000000
-#define BS_1111 0x0F000000
-
-#define GPL0_AAAA 0x00000000
-#define GPL0_AAA0 0x00200000
-#define GPL0_AAA1 0x00300000
-#define GPL0_000A 0x00800000
-#define GPL0_0000 0x00A00000
-#define GPL0_0001 0x00B00000
-#define GPL0_111A 0x00C00000
-#define GPL0_1110 0x00E00000
-#define GPL0_1111 0x00F00000
-
-#define GPL1_0000 0x00000000
-#define GPL1_0001 0x00040000
-#define GPL1_1110 0x00080000
-#define GPL1_1111 0x000C0000
-
-#define GPL2_0000 0x00000000
-#define GPL2_0001 0x00010000
-#define GPL2_1110 0x00020000
-#define GPL2_1111 0x00030000
-
-#define GPL3_0000 0x00000000
-#define GPL3_0001 0x00004000
-#define GPL3_1110 0x00008000
-#define GPL3_1111 0x0000C000
-
-#define GPL4_0000 0x00000000
-#define GPL4_0001 0x00001000
-#define GPL4_1110 0x00002000
-#define GPL4_1111 0x00003000
-
-#define GPL5_0000 0x00000000
-#define GPL5_0001 0x00000400
-#define GPL5_1110 0x00000800
-#define GPL5_1111 0x00000C00
-#define LOOP 0x00000080
-
-#define EXEN 0x00000040
-
-#define AMX_COL 0x00000000
-#define AMX_ROW 0x00000020
-#define AMX_MAR 0x00000030
-
-#define NA 0x00000008
-
-#define UTA 0x00000004
-
-#define TODT 0x00000002
-
-#define LAST 0x00000001
-
-#define A10_AAAA GPL0_AAAA
-#define A10_AAA0 GPL0_AAA0
-#define A10_AAA1 GPL0_AAA1
-#define A10_000A GPL0_000A
-#define A10_0000 GPL0_0000
-#define A10_0001 GPL0_0001
-#define A10_111A GPL0_111A
-#define A10_1110 GPL0_1110
-#define A10_1111 GPL0_1111
-
-#define RAS_0000 GPL1_0000
-#define RAS_0001 GPL1_0001
-#define RAS_1110 GPL1_1110
-#define RAS_1111 GPL1_1111
-
-#define CAS_0000 GPL2_0000
-#define CAS_0001 GPL2_0001
-#define CAS_1110 GPL2_1110
-#define CAS_1111 GPL2_1111
-
-#define WE_0000 GPL3_0000
-#define WE_0001 GPL3_0001
-#define WE_1110 GPL3_1110
-#define WE_1111 GPL3_1111
-
-/* #define CAS_LATENCY 3 */
-#define CAS_LATENCY 2
-
-const uint sdram_table[0x40] = {
-
-#if CAS_LATENCY == 3
- /* RSS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_,
-
- /* RBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WSS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-#endif
-
-#if CAS_LATENCY == 2
- /* RSS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
- /* RBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WSS */
- CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
- CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_,
-
- /* WBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
- CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
- CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
-#endif
-
- /* UPT */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
- /* EXC */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
- _NOT_USED_,
-
- /* REG */
- CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
- CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
-};
-
-#if CONFIG_NETTA2_VERSION == 2
-static const uint nandcs_table[0x40] = {
- /* RSS */
- CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
- CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
- CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
- CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
- CS_0000 | GPL4_0000 | GPL5_1111,
- CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
- CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
- CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */
-
- /* RBS */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WSS */
- CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
- CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
- CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
- CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
- CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
- CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
- CS_0000 | GPL4_1111 | GPL5_1111,
- CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
-
- /* WBS */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* UPT */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* EXC */
- CS_0001 | LAST,
- _NOT_USED_,
-
- /* REG */
- CS_1110 ,
- CS_0001 | LAST,
-};
-#endif
-
-/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
-/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
-#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
-
-/* 8 */
-#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-void check_ram(unsigned int addr, unsigned int size)
-{
- unsigned int i, j, v, vv;
- volatile unsigned int *p;
- unsigned int pv;
-
- p = (unsigned int *)addr;
- pv = (unsigned int)p;
- for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
- *p++ = pv;
-
- p = (unsigned int *)addr;
- for (i = 0; i < size / sizeof(unsigned int); i++) {
- v = (unsigned int)p;
- vv = *p;
- if (vv != v) {
- printf("%p: read %08x instead of %08x\n", p, vv, v);
- hang();
- }
- p++;
- }
-
- for (j = 0; j < 5; j++) {
- switch (j) {
- case 0: v = 0x00000000; break;
- case 1: v = 0xffffffff; break;
- case 2: v = 0x55555555; break;
- case 3: v = 0xaaaaaaaa; break;
- default:v = 0xdeadbeef; break;
- }
- p = (unsigned int *)addr;
- for (i = 0; i < size / sizeof(unsigned int); i++) {
- *p = v;
- vv = *p;
- if (vv != v) {
- printf("%p: read %08x instead of %08x\n", p, vv, v);
- hang();
- }
- *p = ~v;
- p++;
- }
- }
-}
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size;
-
- upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
-
- /*
- * Preliminary prescaler for refresh
- */
- memctl->memc_mptpr = MPTPR_PTP_DIV8;
-
- memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
-
- /*
- * Map controller bank 3 to the SDRAM bank at preliminary address.
- */
- memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
- memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */
-
- udelay(200);
-
- /* perform SDRAM initialisation sequence */
- memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
- udelay(1);
-
- memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
- udelay(1);
-
- memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
- udelay(1);
-
- memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
-
- udelay(10000);
-
- {
- u32 d1, d2;
-
- d1 = 0xAA55AA55;
- *(volatile u32 *)0 = d1;
- d2 = *(volatile u32 *)0;
- if (d1 != d2) {
- printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
- hang();
- }
-
- d1 = 0x55AA55AA;
- *(volatile u32 *)0 = d1;
- d2 = *(volatile u32 *)0;
- if (d1 != d2) {
- printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
- hang();
- }
- }
-
- size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
-
- if (size == 0) {
- printf("SIZE is zero: LOOP on 0\n");
- for (;;) {
- *(volatile u32 *)0 = 0;
- (void)*(volatile u32 *)0;
- }
- }
-
- return size;
-}
-
-/* ------------------------------------------------------------------------- */
-
-void reset_phys(void)
-{
- int phyno;
- unsigned short v;
-
- udelay(10000);
- /* reset the damn phys */
- mii_init();
-
- for (phyno = 0; phyno < 32; ++phyno) {
- fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
- if (v == 0xFFFF)
- continue;
- fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
- udelay(10000);
- fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
- BMCR_RESET | BMCR_ANENABLE);
- udelay(10000);
- }
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* GP = general purpose, SP = special purpose (on chip peripheral) */
-
-/* bits that can have a special purpose or can be configured as inputs/outputs */
-#define PA_GP_INMASK 0
-#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
-#define PA_SP_MASK 0
-#define PA_ODR_VAL 0
-#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15))
-#define PA_SP_DIRVAL 0
-
-#define PB_GP_INMASK _B(28)
-#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
-#define PB_SP_MASK (_BR(22, 25))
-#define PB_ODR_VAL 0
-#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30))
-#define PB_SP_DIRVAL 0
-
-#if CONFIG_NETTA2_VERSION == 1
-#define PC_GP_INMASK _BW(12)
-#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15))
-#elif CONFIG_NETTA2_VERSION == 2
-#define PC_GP_INMASK (_BW(13) | _BW(15))
-#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12))
-#endif
-#define PC_SP_MASK 0
-#define PC_SOVAL 0
-#define PC_INTVAL 0
-#define PC_GP_OUTVAL (_BW(10) | _BW(11))
-#define PC_SP_DIRVAL 0
-
-#if CONFIG_NETTA2_VERSION == 1
-#define PE_GP_INMASK _B(31)
-#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
-#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28))
-#elif CONFIG_NETTA2_VERSION == 2
-#define PE_GP_INMASK _BR(28, 31)
-#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
-#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27))
-#endif
-#define PE_SP_MASK 0
-#define PE_ODR_VAL 0
-#define PE_SP_DIRVAL 0
-
-int board_early_init_f(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile iop8xx_t *ioport = &immap->im_ioport;
- volatile cpm8xx_t *cpm = &immap->im_cpm;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- /* NAND chip select */
-#if CONFIG_NETTA2_VERSION == 1
- memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
- memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
-#elif CONFIG_NETTA2_VERSION == 2
- upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
- memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
- memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
- memctl->memc_mamr = 0; /* all clear */
-#endif
-
- /* DSP chip select */
- memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
- memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
-
-#if CONFIG_NETTA2_VERSION == 1
- memctl->memc_br4 &= ~BR_V;
-#endif
- memctl->memc_br5 &= ~BR_V;
- memctl->memc_br6 &= ~BR_V;
- memctl->memc_br7 &= ~BR_V;
-
- ioport->iop_padat = PA_GP_OUTVAL;
- ioport->iop_paodr = PA_ODR_VAL;
- ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
- ioport->iop_papar = PA_SP_MASK;
-
- cpm->cp_pbdat = PB_GP_OUTVAL;
- cpm->cp_pbodr = PB_ODR_VAL;
- cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
- cpm->cp_pbpar = PB_SP_MASK;
-
- ioport->iop_pcdat = PC_GP_OUTVAL;
- ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
- ioport->iop_pcso = PC_SOVAL;
- ioport->iop_pcint = PC_INTVAL;
- ioport->iop_pcpar = PC_SP_MASK;
-
- cpm->cp_pedat = PE_GP_OUTVAL;
- cpm->cp_peodr = PE_ODR_VAL;
- cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
- cpm->cp_pepar = PE_SP_MASK;
-
- return 0;
-}
-
-#ifdef CONFIG_HW_WATCHDOG
-
-void hw_watchdog_reset(void)
-{
- /* XXX add here the really funky stuff */
-}
-
-#endif
-
-#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
-int overwrite_console(void)
-{
- /* printf("overwrite_console called\n"); */
- return 0;
-}
-#endif
-
-extern int drv_phone_init(void);
-extern int drv_phone_use_me(void);
-extern int drv_phone_is_idle(void);
-
-int misc_init_r(void)
-{
- return 0;
-}
-
-int last_stage_init(void)
-{
-#if CONFIG_NETTA2_VERSION == 2
- int i;
-#endif
-
-#if CONFIG_NETTA2_VERSION == 2
- /* assert peripheral reset */
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
- for (i = 0; i < 10; i++)
- udelay(1000);
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |= _BW(12);
-#endif
- reset_phys();
-
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
* Routine: rx51_kp_tstc
* Description: Test if key was pressed (from buffer).
*/
-int rx51_kp_tstc(void)
+int rx51_kp_tstc(struct stdio_dev *sdev)
{
u8 c, r, dk, i;
u8 intr;
* Routine: rx51_kp_getc
* Description: Get last pressed key (from buffer).
*/
-int rx51_kp_getc(void)
+int rx51_kp_getc(struct stdio_dev *sdev)
{
keybuf_head %= KEYBUF_SIZE;
- while (!rx51_kp_tstc())
+ while (!rx51_kp_tstc(sdev))
WATCHDOG_RESET();
return keybuf[keybuf_head++];
}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = quantum.o fpga.o
+++ /dev/null
-/*
- * (C) Copyright 2001-2003
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/* The DEBUG define must be before common to enable debugging */
-#undef DEBUG
-#include <common.h>
-#include <asm/processor.h>
-#include <command.h>
-#include "fpga.h"
-/* ------------------------------------------------------------------------- */
-
-#define MAX_ONES 226
-
-/* MPC850 port D */
-#define PD(bit) (1 << (15 - (bit)))
-# define FPGA_INIT PD(11) /* FPGA init pin (ppc input) */
-# define FPGA_PRG PD(12) /* FPGA program pin (ppc output) */
-# define FPGA_CLK PD(13) /* FPGA clk pin (ppc output) */
-# define FPGA_DATA PD(14) /* FPGA data pin (ppc output) */
-# define FPGA_DONE PD(15) /* FPGA done pin (ppc input) */
-
-
-/* DDR 0 - input, 1 - output */
-#define FPGA_INIT_PDDIR FPGA_PRG | FPGA_CLK | FPGA_DATA /* just set outputs */
-
-
-#define SET_FPGA(data) immr->im_ioport.iop_pddat = (data)
-#define GET_FPGA immr->im_ioport.iop_pddat
-
-#define FPGA_WRITE_1 { \
- SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
- SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
-
-#define FPGA_WRITE_0 { \
- SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
- SET_FPGA(FPGA_PRG); /* set data to 0 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
-
-
-int fpga_boot (unsigned char *fpgadata, int size)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- int i, index, len;
- int count;
-
-#ifdef CONFIG_SYS_FPGA_SPARTAN2
- int j;
- unsigned char data;
-#else
- unsigned char b;
- int bit;
-#endif
-
- debug ("fpga_boot: fpgadata = %p, size = %d\n", fpgadata, size);
-
- /* display infos on fpgaimage */
- printf ("FPGA:");
- index = 15;
- for (i = 0; i < 4; i++) {
- len = fpgadata[index];
- printf (" %s", &(fpgadata[index + 1]));
- index += len + 3;
- }
- printf ("\n");
-
-
- index = 0;
-
-#ifdef CONFIG_SYS_FPGA_SPARTAN2
- /* search for preamble 0xFFFFFFFF */
- while (1) {
- if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
- && (fpgadata[index + 2] == 0xff)
- && (fpgadata[index + 3] == 0xff))
- break; /* preamble found */
- else
- index++;
- }
-#else
- /* search for preamble 0xFF2X */
- for (index = 0; index < size - 1; index++) {
- if ((fpgadata[index] == 0xff)
- && ((fpgadata[index + 1] & 0xf0) == 0x30))
- break;
- }
- index += 2;
-#endif
-
- debug ("FPGA: configdata starts at position 0x%x\n", index);
- debug ("FPGA: length of fpga-data %d\n", size - index);
-
- /*
- * Setup port pins for fpga programming
- */
- immr->im_ioport.iop_pddir = FPGA_INIT_PDDIR;
-
- debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
- debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
-
- /*
- * Init fpga by asserting and deasserting PROGRAM*
- */
- SET_FPGA (FPGA_CLK | FPGA_DATA);
-
- /* Wait for FPGA init line low */
- count = 0;
- while (GET_FPGA & FPGA_INIT) {
- udelay (1000); /* wait 1ms */
- /* Check for timeout - 100us max, so use 3ms */
- if (count++ > 3) {
- debug ("FPGA: Booting failed!\n");
- return ERROR_FPGA_PRG_INIT_LOW;
- }
- }
-
- debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
- debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
-
- /* deassert PROGRAM* */
- SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA);
-
- /* Wait for FPGA end of init period . */
- count = 0;
- while (!(GET_FPGA & FPGA_INIT)) {
- udelay (1000); /* wait 1ms */
- /* Check for timeout */
- if (count++ > 3) {
- debug ("FPGA: Booting failed!\n");
- return ERROR_FPGA_PRG_INIT_HIGH;
- }
- }
-
- debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
- debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
-
- debug ("write configuration data into fpga\n");
- /* write configuration-data into fpga... */
-
-#ifdef CONFIG_SYS_FPGA_SPARTAN2
- /*
- * Load uncompressed image into fpga
- */
- for (i = index; i < size; i++) {
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
- if ((i % 1024) == 0)
- printf ("%6d out of %6d\r", i, size); /* let them know we are alive */
-#endif
-
- data = fpgadata[i];
- for (j = 0; j < 8; j++) {
- if ((data & 0x80) == 0x80) {
- FPGA_WRITE_1;
- } else {
- FPGA_WRITE_0;
- }
- data <<= 1;
- }
- }
- /* add some 0xff to the end of the file */
- for (i = 0; i < 8; i++) {
- data = 0xff;
- for (j = 0; j < 8; j++) {
- if ((data & 0x80) == 0x80) {
- FPGA_WRITE_1;
- } else {
- FPGA_WRITE_0;
- }
- data <<= 1;
- }
- }
-#else
- /* send 0xff 0x20 */
- FPGA_WRITE_1;
- FPGA_WRITE_1;
- FPGA_WRITE_1;
- FPGA_WRITE_1;
- FPGA_WRITE_1;
- FPGA_WRITE_1;
- FPGA_WRITE_1;
- FPGA_WRITE_1;
- FPGA_WRITE_0;
- FPGA_WRITE_0;
- FPGA_WRITE_1;
- FPGA_WRITE_0;
- FPGA_WRITE_0;
- FPGA_WRITE_0;
- FPGA_WRITE_0;
- FPGA_WRITE_0;
-
- /*
- ** Bit_DeCompression
- ** Code 1 .. maxOnes : n '1's followed by '0'
- ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
- ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
- ** 255 : '1'
- */
-
- for (i = index; i < size; i++) {
- b = fpgadata[i];
- if ((b >= 1) && (b <= MAX_ONES)) {
- for (bit = 0; bit < b; bit++) {
- FPGA_WRITE_1;
- }
- FPGA_WRITE_0;
- } else if (b == (MAX_ONES + 1)) {
- for (bit = 1; bit < b; bit++) {
- FPGA_WRITE_1;
- }
- } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
- for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
- FPGA_WRITE_0;
- }
- FPGA_WRITE_1;
- } else if (b == 255) {
- FPGA_WRITE_1;
- }
- }
-#endif
- debug ("\n\n");
- debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
- debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
-
- /*
- * Check if fpga's DONE signal - correctly booted ?
- */
-
- /* Wait for FPGA end of programming period . */
- count = 0;
- while (!(GET_FPGA & FPGA_DONE)) {
- udelay (1000); /* wait 1ms */
- /* Check for timeout */
- if (count++ > 3) {
- debug ("FPGA: Booting failed!\n");
- return ERROR_FPGA_PRG_DONE;
- }
- }
-
- debug ("FPGA: Booting successful!\n");
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Virtex2 FPGA configuration support for the QUANTUM computer
- */
-int fpga_boot(unsigned char *fpgadata, int size);
-
-#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
-#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
-#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-#include <mpc8xx.h>
-#include "fpga.h"
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-unsigned long flash_init (void);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFCC25
-
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 00h in UPMA RAM)
- */
- 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Burst Read. (Offset 08h in UPMA RAM)
- */
- 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
- 0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Single Write. (Offset 18h in UPMA RAM)
- */
- 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Burst Write. (Offset 20h in UPMA RAM)
- */
- 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
- 0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Refresh. (Offset 30h in UPMA RAM)
- * (Initialization code at 0x36)
- */
- 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
- 0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4,
-
- /*
- * Exception. (Offset 3Ch in UPMA RAM)
- */
- 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- char buf[64];
- int i;
- int l = getenv_f("serial#", buf, sizeof(buf));
-
- puts ("Board QUANTUM, Serial No: ");
-
- for (i = 0; i < l; ++i) {
- if (buf[i] == ' ')
- break;
- putc (buf[i]);
- }
- putc ('\n');
- return (0); /* success */
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size9;
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /* Refresh clock prescalar */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- memctl->memc_mar = 0x00000088;
-
- /* Map controller banks 1 to the SDRAM bank */
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80002136; /* SDRAM bank 0 */
- udelay (1);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay (1000);
-
- /* Check Bank 0 Memory Size,
- * 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
- SDRAM_MAX_SIZE);
- /*
- * Final mapping:
- */
- memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
- udelay (1000);
-
- return (size9);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile ulong *addr;
- ulong cnt, val, size;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- memctl->memc_mamr = mamr_value;
-
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *)(base + cnt); /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = (volatile ulong *)base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- /* Restore the original data before leaving the function.
- */
- *addr = save[i];
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *)(base + cnt); /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- size = cnt * sizeof (long);
- /* Restore the original data before returning
- */
- for (cnt <<= 1; cnt <= maxsize / sizeof (long);
- cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- return (size);
- }
- }
- return (maxsize);
-}
-
-/*
- * Miscellaneous intialization
- */
-int misc_init_r (void)
-{
- char *fpga_data_str = getenv ("fpgadata");
- char *fpga_size_str = getenv ("fpgasize");
- void *fpga_data;
- int fpga_size;
- int status;
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- int flash_size;
-
- /* Remap FLASH according to real size */
- flash_size = flash_init ();
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
- if (fpga_data_str && fpga_size_str) {
- fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16);
- fpga_size = simple_strtoul (fpga_size_str, NULL, 10);
-
- status = fpga_boot (fpga_data, fpga_size);
- if (status != 0) {
- printf ("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf ("(Timeout: DONE not high after programming FPGA)\n ");
- break;
- }
- }
- }
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
#include <common.h>
#include <config.h>
+#include <fdt_support.h>
#include <lcd.h>
+#include <mmc.h>
#include <asm/arch/mbox.h>
#include <asm/arch/sdhci.h>
#include <asm/global_data.h>
return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
}
-int board_mmc_init(void)
+int board_mmc_init(bd_t *bis)
{
ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16);
int ret;
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = rbc823.o flash.o kbd.o
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*
- * Functions
- */
-static ulong flash_get_size(vu_long *addr, flash_info_t *info);
-static int write_word(flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets(ulong base, flash_info_t *info);
-
-unsigned long flash_init(void)
-{
- unsigned long size_b0;
- int i;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- /* Detect size */
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE,
- &flash_info[0]);
-
- /* Setup offsets */
- flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* Monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
- flash_info[0].size = size_b0;
-
- return size_b0;
-}
-
-/*-----------------------------------------------------------------------
- * Fix this to support variable sector sizes
-*/
-static void flash_get_offsets(ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
- /* set sector offsets for bottom boot block type */
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- puts("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf("FUJITSU ");
- break;
- case FLASH_MAN_BM:
- printf("BRIGHT MICRO ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- printf("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
- break;
- case FLASH_AM400B:
- printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T:
- printf("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B:
- printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T:
- printf("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B:
- printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T:
- printf("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B:
- printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T:
- printf("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- break;
- }
-
- if (info->size >> 20) {
- printf(" Size: %ld MB in %d Sectors\n",
- info->size >> 20,
- info->sector_count);
- } else {
- printf(" Size: %ld KB in %d Sectors\n",
- info->size >> 10,
- info->sector_count);
- }
-
- puts(" Sector Start Addresses:");
-
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- puts("\n ");
-
- printf(" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
-
- putc('\n');
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size(vu_long *addr, flash_info_t *info)
-{
- short i;
- volatile unsigned char *caddr;
- char value;
-
- caddr = (volatile unsigned char *)addr ;
-
- /* Write auto select command: read Manufacturer ID */
-
- debug("Base address is: %8p\n", caddr);
-
- caddr[0x0555] = 0xAA;
- caddr[0x02AA] = 0x55;
- caddr[0x0555] = 0x90;
-
- value = caddr[0];
-
- debug("Manufact ID: %02x\n", value);
-
- switch (value) {
- case 0x01: /*AMD_MANUFACT*/
- info->flash_id = FLASH_MAN_AMD;
- break;
-
- case 0x04: /*FUJ_MANUFACT*/
- info->flash_id = FLASH_MAN_FUJ;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
- }
-
- value = caddr[1]; /* device ID */
-
- debug("Device ID: %02x\n", value);
-
- switch (value) {
- case AMD_ID_LV040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break; /* => 512Kb */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return 0; /* => no or unknown flash */
- }
-
- flash_get_offsets((ulong)addr, &flash_info[0]);
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /*
- * read sector protection at sector address,
- * (A7 .. A0) = 0x02
- * D0 = 1 if protected
- */
- caddr = (volatile unsigned char *)(info->start[i]);
- info->protect[i] = caddr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- caddr = (volatile unsigned char *)info->start[0];
- *caddr = 0xF0; /* reset bank */
- }
-
- return info->size;
-}
-
-
-int flash_erase(flash_info_t *info, int s_first, int s_last)
-{
- volatile unsigned char *addr =
- (volatile unsigned char *)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN)
- printf("- missing\n");
- else
- printf("- no sectors to erase\n");
-
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect])
- prot++;
- }
-
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0x80;
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (volatile unsigned char *)(info->start[sect]);
- addr[0] = 0x30;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer(0);
- last = start;
- addr = (volatile unsigned char *)(info->start[l_sect]);
-
- while ((addr[0] & 0xFF) != 0xFF) {
- now = get_timer(start);
- if (now > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (volatile unsigned char *)info->start[0];
-
- addr[0] = 0xF0; /* reset bank */
-
- printf(" done\n");
- return 0;
-}
-
-/*
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- l = addr - wp;
-
- if (l != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp)
- data = (data << 8) | (*(uchar *)cp);
-
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
-
- for (; cnt == 0 && i < 4; ++i, ++cp)
- data = (data << 8) | (*(uchar *)cp);
-
- rc = write_word(info, wp, data);
-
- if (rc != 0)
- return rc;
-
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i)
- data = (data << 8) | *src++;
-
- rc = write_word(info, wp, data);
-
- if (rc != 0)
- return rc;
-
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0)
- return 0;
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp)
- data = (data << 8) | (*(uchar *)cp);
-
- return write_word(info, wp, data);
-}
-
-/*
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word(flash_info_t *info, ulong dest, ulong data)
-{
- volatile unsigned char *cdest, *cdata;
- volatile unsigned char *addr =
- (volatile unsigned char *)(info->start[0]);
- ulong start;
- int flag, count = 4 ;
-
- cdest = (volatile unsigned char *)dest ;
- cdata = (volatile unsigned char *)&data ;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest)&data) != data)
- return 2;
-
- while (count--) {
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0xAA;
- addr[0x02AA] = 0x55;
- addr[0x0555] = 0xA0;
-
- *cdest = *cdata;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer(0);
- while ((*cdest ^ *cdata) & 0x80) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
- return 1;
- }
-
- cdata++ ;
- cdest++ ;
- }
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* Modified by Udi Finkelstein
- *
- * This file includes communication routines for SMC1 that can run even if
- * SMC2 have already been initialized.
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <commproc.h>
-#include <stdio_dev.h>
-#include <lcd.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define SMC_INDEX 0
-#define PROFF_SMC PROFF_SMC1
-#define CPM_CR_CH_SMC CPM_CR_CH_SMC1
-
-#define RBC823_KBD_BAUDRATE 38400
-#define CPM_KEYBOARD_BASE 0x1000
-/*
- * Minimal serial functions needed to use one of the SMC ports
- * as serial console interface.
- */
-
-void smc1_setbrg (void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cp = &(im->im_cpm);
-
- /* Set up the baud rate generator.
- * See 8xx_io/commproc.c for details.
- *
- * Wire BRG2 to SMC1, BRG1 to SMC2
- */
-
- cp->cp_simode = 0x00001000;
-
- cp->cp_brgc2 =
- (((gd->cpu_clk / 16 / RBC823_KBD_BAUDRATE)-1) << 1) | CPM_BRG_EN;
-}
-
-int smc1_init (void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile smc_t *sp;
- volatile smc_uart_t *up;
- volatile cbd_t *tbdf, *rbdf;
- volatile cpm8xx_t *cp = &(im->im_cpm);
- uint dpaddr;
-
- /* initialize pointers to SMC */
-
- sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
- up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
-
- /* Disable transmitter/receiver.
- */
- sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
-
- /* Enable SDMA.
- */
- im->im_siu_conf.sc_sdcr = 1;
-
- /* clear error conditions */
-#ifdef CONFIG_SYS_SDSR
- im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
-#else
- im->im_sdma.sdma_sdsr = 0x83;
-#endif
-
- /* clear SDMA interrupt mask */
-#ifdef CONFIG_SYS_SDMR
- im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
-#else
- im->im_sdma.sdma_sdmr = 0x00;
-#endif
-
- /* Use Port B for SMC1 instead of other functions.
- */
- cp->cp_pbpar |= 0x000000c0;
- cp->cp_pbdir &= ~0x000000c0;
- cp->cp_pbodr &= ~0x000000c0;
-
- /* Set the physical address of the host memory buffers in
- * the buffer descriptors.
- */
-
-#ifdef CONFIG_SYS_ALLOC_DPRAM
- dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
-#else
- dpaddr = CPM_KEYBOARD_BASE ;
-#endif
-
- /* Allocate space for two buffer descriptors in the DP ram.
- * For now, this address seems OK, but it may have to
- * change with newer versions of the firmware.
- * damm: allocating space after the two buffers for rx/tx data
- */
-
- rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
- rbdf->cbd_bufaddr = (uint) (rbdf+2);
- rbdf->cbd_sc = 0;
- tbdf = rbdf + 1;
- tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
- tbdf->cbd_sc = 0;
-
- /* Set up the uart parameters in the parameter ram.
- */
- up->smc_rbase = dpaddr;
- up->smc_tbase = dpaddr+sizeof(cbd_t);
- up->smc_rfcr = SMC_EB;
- up->smc_tfcr = SMC_EB;
-
- /* Set UART mode, 8 bit, no parity, one stop.
- * Enable receive and transmit.
- */
- sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
-
- /* Mask all interrupts and remove anything pending.
- */
- sp->smc_smcm = 0;
- sp->smc_smce = 0xff;
-
- /* Set up the baud rate generator.
- */
- smc1_setbrg ();
-
- /* Make the first buffer the only buffer.
- */
- tbdf->cbd_sc |= BD_SC_WRAP;
- rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
-
- /* Single character receive.
- */
- up->smc_mrblr = 1;
- up->smc_maxidl = 0;
-
- /* Initialize Tx/Rx parameters.
- */
-
- while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
- ;
-
- cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
-
- while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
- ;
-
- /* Enable transmitter/receiver.
- */
- sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
-
- return (0);
-}
-
-void smc1_putc(const char c)
-{
- volatile cbd_t *tbdf;
- volatile char *buf;
- volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cpmp = &(im->im_cpm);
-
- up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
-
- tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
-
- /* Wait for last character to go.
- */
-
- buf = (char *)tbdf->cbd_bufaddr;
-
- *buf = c;
- tbdf->cbd_datlen = 1;
- tbdf->cbd_sc |= BD_SC_READY;
- __asm__("eieio");
-
- while (tbdf->cbd_sc & BD_SC_READY) {
- WATCHDOG_RESET ();
- __asm__("eieio");
- }
-}
-
-int smc1_getc(void)
-{
- volatile cbd_t *rbdf;
- volatile unsigned char *buf;
- volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cpmp = &(im->im_cpm);
- unsigned char c;
-
- up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
-
- rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
-
- /* Wait for character to show up.
- */
- buf = (unsigned char *)rbdf->cbd_bufaddr;
-
- while (rbdf->cbd_sc & BD_SC_EMPTY)
- WATCHDOG_RESET ();
-
- c = *buf;
- rbdf->cbd_sc |= BD_SC_EMPTY;
-
- return(c);
-}
-
-int smc1_tstc(void)
-{
- volatile cbd_t *rbdf;
- volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile cpm8xx_t *cpmp = &(im->im_cpm);
-
- up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
-
- rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
-
- return(!(rbdf->cbd_sc & BD_SC_EMPTY));
-}
-
-/* search for keyboard and register it if found */
-int drv_keyboard_init(void)
-{
- int error = 0;
- struct stdio_dev kbd_dev;
-
- if (0) {
- /* register the keyboard */
- memset (&kbd_dev, 0, sizeof(struct stdio_dev));
- strcpy(kbd_dev.name, "kbd");
- kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
- kbd_dev.putc = NULL;
- kbd_dev.puts = NULL;
- kbd_dev.getc = smc1_getc;
- kbd_dev.tstc = smc1_tstc;
- error = stdio_register (&kbd_dev);
- } else {
- lcd_is_enabled = 0;
- lcd_disable();
- }
- return error;
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include "mpc8xx.h"
-#include <linux/mtd/doc2000.h>
-
-extern int kbd_init(void);
-extern int drv_kbd_init(void);
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-const uint sdram_table[] =
-{
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
- 0x1FF77C47, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
- 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
- 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC84, 0xFFFFFC07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x1FF7FC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-const uint static_table[] =
-{
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04,
- 0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04,
- 0xFFFFFC04, 0xFFFFFC05, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04,
- 0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- *
- * Test TQ ID string (TQM8xx...)
- * If present, check for "L" type (no second DRAM bank),
- * otherwise "L" type is assumed as default.
- *
- * Return 1 for "L" type, 0 else.
- */
-
-int checkboard (void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- if (i < 0 || strncmp(buf, "TQM8", 4)) {
- printf ("### No HW ID - assuming RBC823\n");
- return (0);
- }
-
- puts(buf);
- putc('\n');
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size_b0, size8, size9;
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /*
- * 1 Bank of 64Mbit x 2 devices
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller SDRAM bank 0
- */
- memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
- memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
- udelay (200);
-
- /*
- * Perform SDRAM initializsation sequence
- */
- memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */
- udelay (1);
- memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
- udelay (200);
- memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */
- udelay (1);
- memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
- udelay (200);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
- udelay (1000);
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; /* 16: but should be: CONFIG_SYS_MPTPR_1BK_4K */
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM,
- SDRAM_MAX_SIZE);
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM,
- SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration at 9 columns */
- size_b0 = size9;
-/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
- } else { /* back to 8 columns */
- size_b0 = size8;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
- udelay (500);
-/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
- }
-
- udelay (1000);
-
- /*
- * Adjust refresh rate depending on SDRAM type, both banks
- * For types > 128 MBit leave it at the current (fast) rate
- */
- if ((size_b0 < 0x02000000)) {
- /* reduce to 15.6 us (62.4 us / quad) */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
- udelay (1000);
- }
-
- /* SDRAM Bank 0 is bigger - map first */
-
- memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
- memctl->memc_br4 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
- udelay (10000);
-
- return (size_b0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size (base, maxsize));
-}
-
-#ifdef CONFIG_CMD_DOC
-void doc_init (void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- upmconfig (UPMB, (uint *) static_table,
- sizeof (static_table) / sizeof (uint));
- memctl->memc_mbmr = MAMR_DSA_1_CYCL;
-
- doc_probe (FLASH_BASE1_PRELIM);
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- lib/built-in.o (.text*)
- net/built-in.o (.text*)
- arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
- arch/powerpc/lib/built-in.o (.text*)
-
- . = env_offset;
- common/env_embedded.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
--- /dev/null
+#
+# board/renesas/alt/Makefile
+#
+# Copyright (C) 2014 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y := alt.o qos.o
--- /dev/null
+/*
+ * board/renesas/alt/alt.c
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <div64.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
+
+ /* QoS */
+ qos_init();
+}
+
+#define MSTPSR1 0xE6150038
+#define SMSTPCR1 0xE6150134
+#define TMU0_MSTP125 (1 << 25)
+
+#define MSTPSR7 0xE61501C4
+#define SMSTPCR7 0xE615014C
+#define SCIF0_MSTP719 (1 << 19)
+
+#define MSTPSR8 0xE61509A0
+#define SMSTPCR8 0xE6150990
+#define ETHER_MSTP813 (1 << 13)
+
+#define mstp_setbits(type, addr, saddr, set) \
+ out_##type((saddr), in_##type(addr) | (set))
+#define mstp_clrbits(type, addr, saddr, clear) \
+ out_##type((saddr), in_##type(addr) & ~(clear))
+#define mstp_setbits_le32(addr, saddr, set) \
+ mstp_setbits(le32, addr, saddr, set)
+#define mstp_clrbits_le32(addr, saddr, clear) \
+ mstp_clrbits(le32, addr, saddr, clear)
+
+int board_early_init_f(void)
+{
+ /* TMU */
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+ /* SCIF0 */
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP719);
+
+ /* ETHER */
+ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
+ return 0;
+}
+
+void arch_preboot_os(void)
+{
+ /* Disable TMU0 */
+ mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = ALT_SDRAM_BASE + 0x100;
+
+ /* Init PFC controller */
+ r8a7794_pinmux_init();
+
+ /* Ether Enable */
+ gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+ gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+ gpio_request(GPIO_FN_ETH_RXD0, NULL);
+ gpio_request(GPIO_FN_ETH_RXD1, NULL);
+ gpio_request(GPIO_FN_ETH_LINK, NULL);
+ gpio_request(GPIO_FN_ETH_REFCLK, NULL);
+ gpio_request(GPIO_FN_ETH_MDIO, NULL);
+ gpio_request(GPIO_FN_ETH_TXD1, NULL);
+ gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+ gpio_request(GPIO_FN_ETH_MAGIC, NULL);
+ gpio_request(GPIO_FN_ETH_TXD0, NULL);
+ gpio_request(GPIO_FN_ETH_MDC, NULL);
+ gpio_request(GPIO_FN_IRQ8, NULL);
+
+ /* PHY reset */
+ gpio_request(GPIO_GP_1_24, NULL);
+ gpio_direction_output(GPIO_GP_1_24, 0);
+ mdelay(20);
+ gpio_set_value(GPIO_GP_1_24, 1);
+ udelay(1);
+
+ return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SH_ETHER
+ int ret = -ENODEV;
+ u32 val;
+ unsigned char enetaddr[6];
+
+ ret = sh_eth_initialize(bis);
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ return ret;
+
+ /* Set Mac address */
+ val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+ enetaddr[2] << 8 | enetaddr[3];
+ writel(val, CXR24);
+
+ val = enetaddr[4] << 8 | enetaddr[5];
+ writel(val, CXR25);
+
+ return ret;
+#else
+ return 0;
+#endif
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+ CONFIG_RMOBILE_BOARD_STRING
+};
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = ALT_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = ALT_SDRAM_SIZE;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ u8 val;
+
+ i2c_set_bus_num(1); /* PowerIC connected to ch3 */
+ i2c_init(400000, 0);
+ i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ val |= 0x02;
+ i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+}
--- /dev/null
+/*
+ * board/renesas/alt/qos.c
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.10 */
+
+enum {
+ DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+ DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+ DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+ DBSC3_15,
+ DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+ [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+ [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+ [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+ [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+ [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+ [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+ [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+ [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+ [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+ [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+ [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+ [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+ [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+ [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+ [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+ [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+ [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+ [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+ [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+ [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+ [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+ [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+ [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+ [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+ [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+ [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+ [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+ [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+ [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+ [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+ int i;
+ struct rcar_s3c *s3c;
+ struct rcar_s3c_qos *s3c_qos;
+ struct rcar_dbsc3_qos *qos_addr;
+ struct rcar_mxi *mxi;
+ struct rcar_mxi_qos *mxi_qos;
+ struct rcar_axi_qos *axi_qos;
+
+ /* DBSC DBADJ2 */
+ writel(0x20042004, DBSC3_0_DBADJ2);
+
+ /* S3C -QoS */
+ s3c = (struct rcar_s3c *)S3C_BASE;
+ writel(0x1F0D0B0A, &s3c->s3crorr);
+ writel(0x1F0D0B09, &s3c->s3cworr);
+
+ /* QoS Control Registers */
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+ writel(0x00890089, &s3c_qos->s3cqos0);
+ writel(0x20960010, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA2200, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960010, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA2200, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+ writel(0x00890089, &s3c_qos->s3cqos0);
+ writel(0x20960010, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA2200, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960010, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA2200, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+ writel(0x80928092, &s3c_qos->s3cqos0);
+ writel(0x20960020, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA20DC, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960020, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA20DC, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+ writel(0x00820082, &s3c_qos->s3cqos0);
+ writel(0x20960020, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA20FA, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960020, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA20FA, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ /* DBSC -QoS */
+ /* DBSC0 - Read */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x0000207D, &qos_addr->dbtmval0);
+ writel(0x00002053, &qos_addr->dbtmval1);
+ writel(0x0000202A, &qos_addr->dbtmval2);
+ writel(0x00001FBD, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002064, &qos_addr->dbthres0);
+ writel(0x0000203E, &qos_addr->dbthres1);
+ writel(0x00002019, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* DBSC0 - Write */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x0000207D, &qos_addr->dbtmval0);
+ writel(0x00002053, &qos_addr->dbtmval1);
+ writel(0x00002043, &qos_addr->dbtmval2);
+ writel(0x00002030, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002064, &qos_addr->dbthres0);
+ writel(0x0000203E, &qos_addr->dbthres1);
+ writel(0x00002031, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* CCI-400 -QoS */
+ writel(0x20001000, CCI_400_MAXOT_1);
+ writel(0x20001000, CCI_400_MAXOT_2);
+ writel(0x0000000C, CCI_400_QOSCNTL_1);
+ writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+ /* MXI -QoS */
+ /* Transaction Control (MXI) */
+ mxi = (struct rcar_mxi *)MXI_BASE;
+ writel(0x00000013, &mxi->mxrtcr);
+ writel(0x00000013, &mxi->mxwtcr);
+ writel(0x00780080, &mxi->mxsaar0);
+ writel(0x02000800, &mxi->mxsaar1);
+
+ /* QoS Control (MXI) */
+ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+ writel(0x0000000C, &mxi_qos->vspdu0);
+ writel(0x0000000E, &mxi_qos->du0);
+
+ /* AXI -QoS */
+ /* Transaction Control (MXI) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (RT-AXI) */
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (MP-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002037, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000206E, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (SYS-AXI256) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (CCI-AXI) */
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (Media-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020DC, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x000020AA, &axi_qos->qosthres0);
+ writel(0x00002032, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020DC, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x000020AA, &axi_qos->qosthres0);
+ writel(0x00002032, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+}
--- /dev/null
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = qs850.o flash.o
+++ /dev/null
-/*
- * (C) Copyright 2003
- * MuLogic B.V.
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/u-boot.h>
-#include <asm/processor.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-
-#define FLASH_WORD_SIZE unsigned long
-#define FLASH_ID_MASK 0xFFFFFFFF
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-/* stolen from esteem192e/flash.c */
-ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info);
-
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0, size_b1;
- int i;
- uint pbcr;
- unsigned long base_b0, base_b1;
- volatile FLASH_WORD_SIZE* flash_base;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here */
- /* Test for 8M Flash first */
- debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_8M_PRELIM);
- flash_base = (volatile FLASH_WORD_SIZE*)(FLASH_BASE0_8M_PRELIM);
- size_b0 = flash_get_size(flash_base, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- return 0;
- }
-
- if (size_b0 < 8*1024*1024) {
- /* Not quite 8M, try 4M Flash base address */
- debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_4M_PRELIM);
- flash_base = (volatile FLASH_WORD_SIZE*)(FLASH_BASE0_4M_PRELIM);
- size_b0 = flash_get_size(flash_base, &flash_info[0]);
- }
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- return 0;
- }
-
- /* Only one bank */
- if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
- /* Setup offsets */
- flash_get_offsets ((ulong)flash_base, &flash_info[0]);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]);
- size_b1 = 0 ;
- flash_info[0].size = size_b0;
- return(size_b0);
- }
-
- /* We have 2 banks */
- size_b1 = flash_get_size(flash_base, &flash_info[1]);
-
- /* Re-do sizing to get full correct info */
- if (size_b1) {
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b1 = -size_b1;
- pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
- mtdcr(EBC0_CFGDATA, pbcr);
- }
-
- if (size_b0) {
- mtdcr(EBC0_CFGADDR, PB1CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB1CR);
- base_b0 = base_b1 - size_b0;
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
- mtdcr(EBC0_CFGDATA, pbcr);
- }
-
- size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]);
- flash_get_offsets (base_b0, &flash_info[0]);
-
- /* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]);
-
- if (size_b1) {
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b1, &flash_info[1]);
- flash_get_offsets (base_b1, &flash_info[1]);
-
- /* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET, base_b1+size_b1-CONFIG_SYS_MONITOR_LEN,
- base_b1+size_b1-1, &flash_info[1]);
-
- /* monitor protection OFF by default (one is enough) */
- (void)flash_protect(FLAG_PROTECT_CLEAR, base_b0+size_b0-CONFIG_SYS_MONITOR_LEN,
- base_b0+size_b0-1, &flash_info[0]);
- } else {
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
- return (size_b0 + size_b1);
-}
-
-
-/*-----------------------------------------------------------------------
- This code is specific to the AM29DL163/AM29DL232 for the QS850/QS823.
- */
-
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
- long large_sect_size;
- long small_sect_size;
-
- /* set up sector start adress table */
- large_sect_size = info->size / (info->sector_count - 8 + 1);
- small_sect_size = large_sect_size / 8;
-
- if (info->flash_id & FLASH_BTYPE) {
-
- /* set sector offsets for bottom boot block type */
- for (i = 0; i < 7; i++) {
- info->start[i] = base;
- base += small_sect_size;
- }
-
- for (; i < info->sector_count; i++) {
- info->start[i] = base;
- base += large_sect_size;
- }
- }
- else
- {
- /* set sector offsets for top boot block type */
- for (i = 0; i < (info->sector_count - 8); i++) {
- info->start[i] = base;
- base += large_sect_size;
- }
-
- for (; i < info->sector_count; i++) {
- info->start[i] = base;
- base += small_sect_size;
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
- uchar *boottype;
- uchar botboot[]=", bottom boot sect)\n";
- uchar topboot[]=", top boot sector)\n";
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf ("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf ("FUJITSU ");
- break;
- case FLASH_MAN_SST:
- printf ("SST ");
- break;
- case FLASH_MAN_STM:
- printf ("STM ");
- break;
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- if (info->flash_id & 0x0001 ) {
- boottype = botboot;
- } else {
- boottype = topboot;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM160B:
- printf ("AM29LV160B (16 Mbit%s",boottype);
- break;
- case FLASH_AM160T:
- printf ("AM29LV160T (16 Mbit%s",boottype);
- break;
- case FLASH_AMDL163T:
- printf ("AM29DL163T (16 Mbit%s",boottype);
- break;
- case FLASH_AMDL163B:
- printf ("AM29DL163B (16 Mbit%s",boottype);
- break;
- case FLASH_AM320B:
- printf ("AM29LV320B (32 Mbit%s",boottype);
- break;
- case FLASH_AM320T:
- printf ("AM29LV320T (32 Mbit%s",boottype);
- break;
- case FLASH_AMDL323T:
- printf ("AM29DL323T (32 Mbit%s",boottype);
- break;
- case FLASH_AMDL323B:
- printf ("AM29DL323B (32 Mbit%s",boottype);
- break;
- case FLASH_AMDL322T:
- printf ("AM29DL322T (32 Mbit%s",boottype);
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-
-/*-----------------------------------------------------------------------
- * The following code cannot be run from FLASH!
- */
-ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
-{
- short i;
- ulong base = (ulong)addr;
- FLASH_WORD_SIZE value;
-
- /* Write auto select command: read Manufacturer ID */
-
- /*
- * Note: if it is an AMD flash and the word at addr[0000]
- * is 0x00890089 this routine will think it is an Intel
- * flash device and may(most likely) cause trouble.
- */
-
- addr[0x0000] = 0x00900090;
- if(addr[0x0000] != 0x00890089){
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00900090;
- }
- value = addr[0];
-
- switch (value) {
- case (AMD_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FUJ_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (STM_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_STM;
- break;
- case (SST_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_SST;
- break;
- case (INTEL_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[1]; /* device ID */
-
- switch (value) {
- case (AMD_ID_LV160T & FLASH_ID_MASK):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_LV160B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_DL163T & FLASH_ID_MASK):
- info->flash_id += FLASH_AMDL163T;
- info->sector_count = 39;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_DL163B & FLASH_ID_MASK):
- info->flash_id += FLASH_AMDL163B;
- info->sector_count = 39;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_DL323T & FLASH_ID_MASK):
- info->flash_id += FLASH_AMDL323T;
- info->sector_count = 71;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (AMD_ID_DL323B & FLASH_ID_MASK):
- info->flash_id += FLASH_AMDL323B;
- info->sector_count = 71;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (AMD_ID_DL322T & FLASH_ID_MASK):
- info->flash_id += FLASH_AMDL322T;
- info->sector_count = 71;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- default:
- /* FIXME*/
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
- flash_get_offsets(base, info);
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile FLASH_WORD_SIZE *)info->start[0];
- *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP) ) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00800080;
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
- addr[0] = (0x00300030 & FLASH_ID_MASK);
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]);
- while ((addr[0] & (0x00800080&FLASH_ID_MASK)) !=
- (0x00800080&FLASH_ID_MASK) )
- {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (volatile FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */
-
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int l;
- int i, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* AMD stuff */
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer(0);
-
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * MuLogic B.V.
- *
- * (C) Copyright 2002
- * Simple Network Magic Corporation, dnevil@snmc.com
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/u-boot.h>
-#include <commproc.h>
-#include "mpc8xx.h"
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-const uint sdram_table[] =
-{
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x0f07cc04, 0x00adcc04, 0x00a74c00, 0x00bfcc04,
- 0x1fffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0x0ff7fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
- 0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
- 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
- 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x0f07cc04, 0x0fafcc00, 0x01ad0c04, 0x1ff74c07,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x0ff7fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
- 0x00fffc00, 0x00fffc00, 0x0ffffc04, 0x0ff77c04,
- 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
- 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0xffffcc04, 0x1ff5cc84, 0xffffcc04, 0xffffcc04,
- 0xffffcc84, 0xffffcc05, 0xffffcc04, 0xffffcc04,
- 0xffffcc04, 0xffffcc04, 0xffffcc04, 0xffffcc04,
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x1ff74c04, 0xffffcc07, 0xffffaa34, 0x1fb54a37
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Test ID string (QS850, QS823, ...)
- *
- * Always return 1
- */
-#if defined(CONFIG_QS850)
-#define BOARD_IDENTITY "QS850"
-#elif defined(CONFIG_QS823)
-#define BOARD_IDENTITY "QS823"
-#else
-#define BOARD_IDENTITY "QS???"
-#endif
-
-int checkboard (void)
-{
- char *s, *e;
- char buf[64];
- int i;
-
- i = getenv_f("serial#", buf, sizeof(buf));
- s = (i>0) ? buf : NULL;
-
- if (!s || strncmp(s, BOARD_IDENTITY, 5)) {
- puts ("### No HW ID - assuming " BOARD_IDENTITY);
- } else {
- for (e=s; *e; ++e) {
- if (*e == ' ')
- break;
- }
-
- for ( ; s<e; ++s) {
- putc (*s);
- }
- }
- putc ('\n');
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-/* SDRAM Mode Register Definitions */
-
-/* Set SDRAM Burst Length to 4 (010) */
-/* See Motorola MPC850 User Manual, Page 13-14 */
-#define SDRAM_BURST_LENGTH (2)
-
-/* Set Wrap Type to Sequential (0) */
-/* See Motorola MPC850 User Manual, Page 13-14 */
-#define SDRAM_WRAP_TYPE (0 << 3)
-
-/* Set /CAS Latentcy to 2 clocks */
-#define SDRAM_CAS_LATENTCY (2 << 4)
-
-/* The Mode Register value must be shifted left by 2, since it is */
-/* placed on the address bus, and the 2 LSBs are ignored for 32-bit accesses */
-#define SDRAM_MODE_REG ((SDRAM_BURST_LENGTH|SDRAM_WRAP_TYPE|SDRAM_CAS_LATENTCY) << 2)
-
-#define UPMA_RUN(loops,index) (0x80002000 + (loops<<8) + index)
-
-/* Please note a value of zero = 16 loops */
-#define REFRESH_INIT_LOOPS (0)
-
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size;
-
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- /*
- * Prescaler for refresh
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- /*
- * Map controller bank 1 to the SDRAM address
- */
- memctl->memc_or1 = CONFIG_SYS_OR1;
- memctl->memc_br1 = CONFIG_SYS_BR1;
- udelay(1000);
-
- /* perform SDRAM initialization sequence */
- memctl->memc_mamr = CONFIG_SYS_16M_MAMR;
- udelay(100);
-
- /* Program the SDRAM's Mode Register */
- memctl->memc_mar = SDRAM_MODE_REG;
-
- /* Run the Prechard Pattern at 0x3C */
- memctl->memc_mcr = UPMA_RUN(1,0x3c);
- udelay(1);
-
- /* Run the Refresh program residing at MAD index 0x30 */
- /* This contains the CBR Refresh command with a loop */
- /* The SDRAM must be refreshed at least 2 times */
- /* Please note a value of zero = 16 loops */
- memctl->memc_mcr = UPMA_RUN(REFRESH_INIT_LOOPS,0x30);
- udelay(1);
-
- /* Run the Exception program residing at MAD index 0x3E */
- /* This contains the Write Mode Register command */
- /* The Write Mode Register command uses the value written to MAR */
- memctl->memc_mcr = UPMA_RUN(1,0x3e);
-
- udelay (1000);
-
- /*
- * Check for 32M SDRAM Memory Size
- */
- size = dram_size(CONFIG_SYS_32M_MAMR|MAMR_PTAE,
- (long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE);
- udelay (1000);
-
- /*
- * Check for 16M SDRAM Memory Size
- */
- if (size != SDRAM_32M_MAX_SIZE) {
- size = dram_size(CONFIG_SYS_16M_MAMR|MAMR_PTAE,
- (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
- udelay (1000);
- }
-
- udelay(10000);
- return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size(base, maxsize));
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = qs860t.o flash.o
+++ /dev/null
-/*
- * (C) Copyright 2003
- * MuLogic B.V.
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/u-boot.h>
-#include <asm/processor.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-
-#ifdef CONFIG_SYS_FLASH_16BIT
-#define FLASH_WORD_SIZE unsigned short
-#define FLASH_ID_MASK 0xFFFF
-#else
-#define FLASH_WORD_SIZE unsigned long
-#define FLASH_ID_MASK 0xFFFFFFFF
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-/* stolen from esteem192e/flash.c */
-ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info);
-
-#ifndef CONFIG_SYS_FLASH_16BIT
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-#else
-static int write_short (flash_info_t *info, ulong dest, ushort data);
-#endif
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0, size_b1;
- int i;
- uint pbcr;
- unsigned long base_b0, base_b1;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Only one bank */
- if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
- /* Setup offsets */
- flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[0]);
-
- /* Monitor protection ON by default */
-#if 0 /* sand: */
- (void)flash_protect(FLAG_PROTECT_SET,
- FLASH_BASE1_PRELIM-CONFIG_SYS_MONITOR_LEN+size_b0,
- FLASH_BASE1_PRELIM-1+size_b0,
- &flash_info[0]);
-#else
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
- &flash_info[0]);
-#endif
- size_b1 = 0 ;
- flash_info[0].size = size_b0;
- } else { /* 2 banks */
- size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
- /* Re-do sizing to get full correct info */
- if (size_b1) {
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b1 = -size_b1;
- pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
- mtdcr(EBC0_CFGDATA, pbcr);
- }
-
- if (size_b0) {
- mtdcr(EBC0_CFGADDR, PB1CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB1CR);
- base_b0 = base_b1 - size_b0;
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
- mtdcr(EBC0_CFGDATA, pbcr);
- }
-
- size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]);
-
- flash_get_offsets (base_b0, &flash_info[0]);
-
- /* monitor protection ON by default */
-#if 0 /* sand: */
- (void)flash_protect(FLAG_PROTECT_SET,
- FLASH_BASE1_PRELIM-CONFIG_SYS_MONITOR_LEN+size_b0,
- FLASH_BASE1_PRELIM-1+size_b0,
- &flash_info[0]);
-#else
- (void)flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
- &flash_info[0]);
-#endif
-
- if (size_b1) {
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b1, &flash_info[1]);
-
- flash_get_offsets (base_b1, &flash_info[1]);
-
- /* monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- base_b1+size_b1-CONFIG_SYS_MONITOR_LEN,
- base_b1+size_b1-1,
- &flash_info[1]);
- /* monitor protection OFF by default (one is enough) */
- (void)flash_protect(FLAG_PROTECT_CLEAR,
- base_b0+size_b0-CONFIG_SYS_MONITOR_LEN,
- base_b0+size_b0-1,
- &flash_info[0]);
- } else {
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
- }/* else 2 banks */
- return (size_b0 + size_b1);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start adress table */
- if ((info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F320J3A ||
- (info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F640J3A ||
- (info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F128J3A) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * info->size/info->sector_count);
- }
- }
- else if (info->flash_id & FLASH_BTYPE) {
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-
-#ifndef CONFIG_SYS_FLASH_16BIT
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00008000;
- info->start[3] = base + 0x0000C000;
- info->start[4] = base + 0x00010000;
- info->start[5] = base + 0x00014000;
- info->start[6] = base + 0x00018000;
- info->start[7] = base + 0x0001C000;
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x000E0000;
- }
- } else {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000) - 0x00060000;
- }
- }
-#else
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00002000;
- info->start[2] = base + 0x00004000;
- info->start[3] = base + 0x00006000;
- info->start[4] = base + 0x00008000;
- info->start[5] = base + 0x0000A000;
- info->start[6] = base + 0x0000C000;
- info->start[7] = base + 0x0000E000;
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00070000;
- }
- } else {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- }
-#endif
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-
-#ifndef CONFIG_SYS_FLASH_16BIT
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- info->start[i--] = base + info->size - 0x00014000;
- info->start[i--] = base + info->size - 0x00018000;
- info->start[i--] = base + info->size - 0x0001C000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- } else {
-
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x00010000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00020000;
- }
- }
-#else
- info->start[i--] = base + info->size - 0x00002000;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- info->start[i--] = base + info->size - 0x0000A000;
- info->start[i--] = base + info->size - 0x0000C000;
- info->start[i--] = base + info->size - 0x0000E000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- } else {
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-#endif
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
- uchar *boottype;
- uchar botboot[]=", bottom boot sect)\n";
- uchar topboot[]=", top boot sector)\n";
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- case FLASH_MAN_INTEL: printf ("INTEL "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- if (info->flash_id & 0x0001 ) {
- boottype = botboot;
- } else {
- boottype = topboot;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit%s",boottype);
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit%s",boottype);
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit%s",boottype);
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit%s",boottype);
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit%s",boottype);
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit%s",boottype);
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit%s",boottype);
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit%s",boottype);
- break;
- case FLASH_INTEL800B: printf ("INTEL28F800B (8 Mbit%s",boottype);
- break;
- case FLASH_INTEL800T: printf ("INTEL28F800T (8 Mbit%s",boottype);
- break;
- case FLASH_INTEL160B: printf ("INTEL28F160B (16 Mbit%s",boottype);
- break;
- case FLASH_INTEL160T: printf ("INTEL28F160T (16 Mbit%s",boottype);
- break;
- case FLASH_INTEL320B: printf ("INTEL28F320B (32 Mbit%s",boottype);
- break;
- case FLASH_INTEL320T: printf ("INTEL28F320T (32 Mbit%s",boottype);
- break;
- case FLASH_AMDL322T: printf ("AM29DL322T (32 Mbit%s",boottype);
- break;
-
-#if 0 /* enable when devices are available */
-
- case FLASH_INTEL640B: printf ("INTEL28F640B (64 Mbit%s",boottype);
- break;
- case FLASH_INTEL640T: printf ("INTEL28F640T (64 Mbit%s",boottype);
- break;
-#endif
- case INTEL_ID_28F320J3A: printf ("INTEL28F320JA3 (32 Mbit%s",boottype);
- break;
- case INTEL_ID_28F640J3A: printf ("INTEL28F640JA3 (64 Mbit%s",boottype);
- break;
- case INTEL_ID_28F128J3A: printf ("INTEL28F128JA3 (128 Mbit%s",boottype);
- break;
-
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
-{
- short i;
- ulong base = (ulong)addr;
- FLASH_WORD_SIZE value;
-
- /* Write auto select command: read Manufacturer ID */
-
-
-#ifndef CONFIG_SYS_FLASH_16BIT
-
- /*
- * Note: if it is an AMD flash and the word at addr[0000]
- * is 0x00890089 this routine will think it is an Intel
- * flash device and may(most likely) cause trouble.
- */
-
- addr[0x0000] = 0x00900090;
- if(addr[0x0000] != 0x00890089){
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00900090;
-#else
-
- /*
- * Note: if it is an AMD flash and the word at addr[0000]
- * is 0x0089 this routine will think it is an Intel
- * flash device and may(most likely) cause trouble.
- */
-
- addr[0x0000] = 0x0090;
-
- if(addr[0x0000] != 0x0089){
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
- addr[0x0555] = 0x0090;
-#endif
- }
- value = addr[0];
-
- switch (value) {
- case (AMD_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FUJ_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (STM_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_STM;
- break;
- case (SST_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_SST;
- break;
- case (INTEL_MANUFACT & FLASH_ID_MASK):
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
-
- }
-
- value = addr[1]; /* device ID */
-
- switch (value) {
-
- case (AMD_ID_LV400T & FLASH_ID_MASK):
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV400B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV800T & FLASH_ID_MASK):
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV800B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV160T & FLASH_ID_MASK):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_LV160B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case (AMD_ID_LV320T & FLASH_ID_MASK):
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (AMD_ID_LV320B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
-
- case (AMD_ID_DL322T & FLASH_ID_MASK):
- info->flash_id += FLASH_AMDL322T;
- info->sector_count = 71;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (INTEL_ID_28F800B3T & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL800T;
- info->sector_count = 23;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (INTEL_ID_28F800B3B & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL800B;
- info->sector_count = 23;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (INTEL_ID_28F160B3T & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL160T;
- info->sector_count = 39;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (INTEL_ID_28F160B3B & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL160B;
- info->sector_count = 39;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL320T;
- info->sector_count = 71;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 71;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
-#if 0 /* enable when devices are available */
- case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
- info->flash_id += FLASH_INTEL320T;
- info->sector_count = 135;
- info->size = 0x01000000;
- break; /* => 16 MB */
-
- case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
- info->flash_id += FLASH_AM320B;
- info->sector_count = 135;
- info->size = 0x01000000;
- break; /* => 16 MB */
-#endif
- case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
- info->flash_id += FLASH_28F320J3A;
- info->sector_count = 32;
- info->size = 0x00400000;
- break; /* => 32 MBit */
- case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000;
- break; /* => 64 MBit */
- case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000;
- break; /* => 128 MBit */
-
- default:
- /* FIXME*/
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
- }
-
- flash_get_offsets(base, info);
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- info->protect[i] = addr[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile FLASH_WORD_SIZE *)info->start[0];
- if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){
- *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */
- } else {
- *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */
- }
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-
- volatile FLASH_WORD_SIZE *addr =
- (volatile FLASH_WORD_SIZE *) (info->start[0]);
- int flag, prot, sect, l_sect, barf;
- ulong start, now, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- ((info->flash_id > FLASH_AMD_COMP) &&
- ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
- if (info->flash_id < FLASH_AMD_COMP) {
-#ifndef CONFIG_SYS_FLASH_16BIT
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00800080;
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
-#else
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
- addr[0x0555] = 0x0080;
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
-#endif
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (volatile FLASH_WORD_SIZE *) (info->start[sect]);
- addr[0] = (0x00300030 & FLASH_ID_MASK);
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
- while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
- (0x00800080 & FLASH_ID_MASK)) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- addr = (volatile FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */
- } else {
-
-
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- barf = 0;
-#ifndef CONFIG_SYS_FLASH_16BIT
- addr = (vu_long *) (info->start[sect]);
- addr[0] = 0x00200020;
- addr[0] = 0x00D000D0;
- while (!(addr[0] & 0x00800080)); /* wait for error or finish */
- if (addr[0] & 0x003A003A) { /* check for error */
- barf = addr[0] & 0x003A0000;
- if (barf) {
- barf >>= 16;
- } else {
- barf = addr[0] & 0x0000003A;
- }
- }
-#else
- addr = (vu_short *) (info->start[sect]);
- addr[0] = 0x0020;
- addr[0] = 0x00D0;
- while (!(addr[0] & 0x0080)); /* wait for error or finish */
- if (addr[0] & 0x003A) /* check for error */
- barf = addr[0] & 0x003A;
-#endif
- if (barf) {
- printf ("\nFlash error in sector at %lx\n",
- (unsigned long) addr);
- if (barf & 0x0002)
- printf ("Block locked, not erased.\n");
- if ((barf & 0x0030) == 0x0030)
- printf ("Command Sequence error.\n");
- if ((barf & 0x0030) == 0x0020)
- printf ("Block Erase error.\n");
- if (barf & 0x0008)
- printf ("Vpp Low error.\n");
- rcode = 1;
- } else
- printf (".");
- l_sect = sect;
- }
- addr = (volatile FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */
-
- }
-
- }
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*flash_info_t *addr2info (ulong addr)
-{
- flash_info_t *info;
- int i;
-
- for (i=0, info=&flash_info[0]; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i, ++info) {
- if ((addr >= info->start[0]) &&
- (addr < (info->start[0] + info->size)) ) {
- return (info);
- }
- }
-
- return (NULL);
-}
-*/
-/*-----------------------------------------------------------------------
- * Copy memory to flash.
- * Make sure all target addresses are within Flash bounds,
- * and no protected sectors are hit.
- * Returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - target range includes protected sectors
- * 8 - target address not in Flash memory
- */
-
-/*int flash_write (uchar *src, ulong addr, ulong cnt)
-{
- int i;
- ulong end = addr + cnt - 1;
- flash_info_t *info_first = addr2info (addr);
- flash_info_t *info_last = addr2info (end );
- flash_info_t *info;
-
- if (cnt == 0) {
- return (0);
- }
-
- if (!info_first || !info_last) {
- return (8);
- }
-
- for (info = info_first; info <= info_last; ++info) {
- ulong b_end = info->start[0] + info->size;*/ /* bank end addr */
-/* short s_end = info->sector_count - 1;
- for (i=0; i<info->sector_count; ++i) {
- ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
-
- if ((end >= info->start[i]) && (addr < e_addr) &&
- (info->protect[i] != 0) ) {
- return (4);
- }
- }
- }
-
-*/ /* finally write data to flash */
-/* for (info = info_first; info <= info_last && cnt>0; ++info) {
- ulong len;
-
- len = info->start[0] + info->size - addr;
- if (len > cnt)
- len = cnt;
- if ((i = write_buff(info, src, addr, len)) != 0) {
- return (i);
- }
- cnt -= len;
- addr += len;
- src += len;
- }
- return (0);
-}
-*/
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-#ifndef CONFIG_SYS_FLASH_16BIT
- ulong cp, wp, data;
- int l;
-#else
- ulong cp, wp;
- ushort data;
-#endif
- int i, rc;
-
-#ifndef CONFIG_SYS_FLASH_16BIT
-
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-
-#else
- wp = (addr & ~1); /* get lower word aligned address */
-
- /*
- * handle unaligned start byte
- */
- if (addr - wp) {
- data = 0;
- data = (data << 8) | *src++;
- --cnt;
- if ((rc = write_short(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 2;
- }
-
- /*
- * handle word aligned part
- */
-/* l = 0; used for debuging */
- while (cnt >= 2) {
- data = 0;
- for (i=0; i<2; ++i) {
- data = (data << 8) | *src++;
- }
-
-/* if(!l){
- printf("%x",data);
- l = 1;
- } used for debuging */
-
- if ((rc = write_short(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 2;
- cnt -= 2;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<2; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_short(info, wp, data));
-
-
-#endif
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-#ifndef CONFIG_SYS_FLASH_16BIT
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- ulong start,barf;
- int flag;
-
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- if(info->flash_id > FLASH_AMD_COMP) {
- /* AMD stuff */
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
- } else {
- /* intel stuff */
- *addr = 0x00400040;
- }
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
-
- if(info->flash_id > FLASH_AMD_COMP) {
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- } else {
- while(!(addr[0] & 0x00800080)) { /* wait for error or finish */
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
-
- if( addr[0] & 0x003A003A) { /* check for error */
- barf = addr[0] & 0x003A0000;
- if( barf ) {
- barf >>=16;
- } else {
- barf = addr[0] & 0x0000003A;
- }
- printf("\nFlash write error at address %lx\n",(unsigned long)dest);
- if(barf & 0x0002) printf("Block locked, not erased.\n");
- if(barf & 0x0010) printf("Programming error.\n");
- if(barf & 0x0008) printf("Vpp Low error.\n");
- return(2);
- }
- }
-
- return (0);
-}
-
-#else
-
-static int write_short (flash_info_t *info, ulong dest, ushort data)
-{
- vu_short *addr = (vu_short*)(info->start[0]);
- ulong start,barf;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_short *)dest) & data) != data) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- if(info->flash_id < FLASH_AMD_COMP) {
- /* AMD stuff */
- addr[0x0555] = 0x00AA;
- addr[0x02AA] = 0x0055;
- addr[0x0555] = 0x00A0;
- } else {
- /* intel stuff */
- *addr = 0x00D0;
- *addr = 0x0040;
- }
- *((vu_short *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
-
- if(info->flash_id < FLASH_AMD_COMP) {
- /* AMD stuff */
- while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
-
- } else {
- /* intel stuff */
- while(!(addr[0] & 0x0080)){ /* wait for error or finish */
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1);
- }
-
- if( addr[0] & 0x003A) { /* check for error */
- barf = addr[0] & 0x003A;
- printf("\nFlash write error at address %lx\n",(unsigned long)dest);
- if(barf & 0x0002) printf("Block locked, not erased.\n");
- if(barf & 0x0010) printf("Programming error.\n");
- if(barf & 0x0008) printf("Vpp Low error.\n");
- return(2);
- }
- *addr = 0x00B0;
- *addr = 0x0070;
- while(!(addr[0] & 0x0080)){ /* wait for error or finish */
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1);
- }
- *addr = 0x00FF;
- }
- return (0);
-}
-
-#endif
-
-/*-----------------------------------------------------------------------*/
+++ /dev/null
-/*
- * (C) Copyright 2003
- * MuLogic B.V.
- *
- * (C) Copyright 2002
- * Simple Network Magic Corporation, dnevil@snmc.com
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/u-boot.h>
-#include <commproc.h>
-#include "mpc8xx.h"
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-const uint sdram_table[] =
-{
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
- 0x1FF77C47, 0x1FF77C35, 0xEFEABC34, 0x1FB57C35,
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
- 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,
- 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
- 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,
- 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
- 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, 0xFFFFEC04,
- 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
- 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC84, 0xFFFFFC07, 0xFFFFEC04, 0xFFFFEC04,
- 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x7FFFFC07, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Test ID string (QS860T...)
- *
- * Always return 1
- */
-
-int checkboard (void)
-{
- char *s, *e;
- char buf[64];
- int i;
-
- i = getenv_f("serial#", buf, sizeof(buf));
- s = (i>0) ? buf : NULL;
-
- if (!s || strncmp(s, "QS860T", 6)) {
- puts ("### No HW ID - assuming QS860T");
- } else {
- for (e=s; *e; ++e) {
- if (*e == ' ')
- break;
- }
-
- for ( ; s<e; ++s) {
- putc (*s);
- }
- }
- putc ('\n');
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size;
-
- upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- /*
- * Prescaler for refresh
- */
- memctl->memc_mptpr = 0x0400;
-
- /*
- * Map controller bank 2 to the SDRAM address
- */
- memctl->memc_or2 = CONFIG_SYS_OR2;
- memctl->memc_br2 = CONFIG_SYS_BR2;
- udelay(200);
-
- /* perform SDRAM initialization sequence */
- memctl->memc_mbmr = CONFIG_SYS_16M_MBMR;
- udelay(100);
-
- memctl->memc_mar = 0x00000088;
- memctl->memc_mcr = 0x80804105; /* run precharge pattern */
- udelay(1);
-
- /* Run two refresh cycles on SDRAM */
- memctl->memc_mbmr = 0x18802118;
- memctl->memc_mcr = 0x80804130;
- memctl->memc_mbmr = 0x18802114;
- memctl->memc_mcr = 0x80804106;
-
- udelay (1000);
-
-#if 0
- /*
- * Check for 64M SDRAM Memory Size
- */
- size = dram_size (CONFIG_SYS_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE);
- udelay (1000);
-
- /*
- * Check for 16M SDRAM Memory Size
- */
- if (size != SDRAM_64M_MAX_SIZE) {
-#endif
- size = dram_size (CONFIG_SYS_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
- udelay (1000);
-#if 0
- }
-
- memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
-#endif
-
-
- udelay(10000);
-
-
-#if 0
-
- /*
- * Also, map other memory to correct position
- */
-
- /*
- * Map the 8M Intel Flash device to chip select 1
- */
- memctl->memc_or1 = CONFIG_SYS_OR1;
- memctl->memc_br1 = CONFIG_SYS_BR1;
-
-
- /*
- * Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg
- * to chip select 3
- */
- memctl->memc_or3 = CONFIG_SYS_OR3;
- memctl->memc_br3 = CONFIG_SYS_BR3;
-
- /*
- * Map chip selects 4, 5, 6, & 7 for external expansion connector
- */
- memctl->memc_or4 = CONFIG_SYS_OR4;
- memctl->memc_br4 = CONFIG_SYS_BR4;
-
- memctl->memc_or5 = CONFIG_SYS_OR5;
- memctl->memc_br5 = CONFIG_SYS_BR5;
-
- memctl->memc_or6 = CONFIG_SYS_OR6;
- memctl->memc_br6 = CONFIG_SYS_BR6;
-
- memctl->memc_or7 = CONFIG_SYS_OR7;
- memctl->memc_br7 = CONFIG_SYS_BR7;
-
-#endif
-
- return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mbmr_value, long int *base, long int maxsize)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mbmr = mbmr_value;
-
- return (get_ram_size(base, maxsize));
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = spc1920.o hpi.o
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Host Port Interface (HPI)
- */
-
-/* debug levels:
- * 0 : errors
- * 1 : usefull info
- * 2 : lots of info
- * 3 : noisy
- */
-
-#define DEBUG 0
-
-#include <config.h>
-#include <common.h>
-#include <mpc8xx.h>
-
-#include "pld.h"
-#include "hpi.h"
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-/* original table:
- * - inserted loops to achieve long CS low and high Periods (~217ns)
- * - move cs high 2/4 to the right
- */
-const uint dsp_table_slow[] =
-{
- /* single read (offset 0x00 in upm ram) */
- 0x8fffdc04, 0x0fffdc84, 0x0fffdc84, 0x0fffdc00,
- 0x3fffdc04, 0xffffdc84, 0xffffdc84, 0xffffdc05,
-
- /* burst read (offset 0x08 in upm ram) */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* single write (offset 0x18 in upm ram) */
- 0x8fffd004, 0x0fffd084, 0x0fffd084, 0x3fffd000,
- 0xffffd084, 0xffffd084, 0xffffd005, _NOT_USED_,
-
- /* burst write (offset 0x20 in upm ram) */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* refresh (offset 0x30 in upm ram) */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* exception (offset 0x3C in upm ram) */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* dsp hpi upm ram table
- * works fine for noninc access, failes on incremental.
- * - removed first word
- */
-const uint dsp_table_fast[] =
-{
- /* single read (offset 0x00 in upm ram) */
- 0x8fffdc04, 0x0fffdc04, 0x0fffdc00, 0x3fffdc04,
- 0xffffdc05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* burst read (offset 0x08 in upm ram) */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* single write (offset 0x18 in upm ram) */
- 0x8fffd004, 0x0fffd004, 0x3fffd000, 0xffffd005,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* burst write (offset 0x20 in upm ram) */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* refresh (offset 0x30 in upm ram) */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* exception (offset 0x3C in upm ram) */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-
-#ifdef CONFIG_SPC1920_HPI_TEST
-#undef HPI_TEST_OSZI
-
-#define HPI_TEST_CHUNKSIZE 0x1000
-#define HPI_TEST_PATTERN 0x00000000
-#define HPI_TEST_START 0x0
-#define HPI_TEST_END 0x30000
-
-#define TINY_AUTOINC_DATA_SIZE 16 /* 32bit words */
-#define TINY_AUTOINC_BASE_ADDR 0x0
-
-static int hpi_activate(void);
-#if 0
-static void hpi_inactivate(void);
-#endif
-static void dsp_reset(void);
-
-static int hpi_write_inc(u32 addr, u32 *data, u32 count);
-static int hpi_read_inc(u32 addr, u32 *buf, u32 count);
-static int hpi_write_noinc(u32 addr, u32 data);
-static u32 hpi_read_noinc(u32 addr);
-
-int hpi_test(void);
-static int hpi_write_addr_test(u32 addr);
-static int hpi_read_write_test(u32 addr, u32 data);
-#ifdef DO_TINY_TEST
-static int hpi_tiny_autoinc_test(void);
-#endif /* DO_TINY_TEST */
-#endif /* CONFIG_SPC1920_HPI_TEST */
-
-
-/* init the host port interface on UPMA */
-int hpi_init(void)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
- volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE;
-
- upmconfig(UPMA, (uint *)dsp_table_slow, sizeof(dsp_table_slow)/sizeof(uint));
- udelay(100);
-
- memctl->memc_mamr = CONFIG_SYS_MAMR;
- memctl->memc_or3 = CONFIG_SYS_OR3;
- memctl->memc_br3 = CONFIG_SYS_BR3;
-
- /* reset dsp */
- dsp_reset();
-
- /* activate hpi switch*/
- pld->dsp_hpi_on = 0x1;
-
- udelay(100);
-
- return 0;
-}
-
-#ifdef CONFIG_SPC1920_HPI_TEST
-/* activate the Host Port interface */
-static int hpi_activate(void)
-{
- volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE;
-
- /* turn on hpi */
- pld->dsp_hpi_on = 0x1;
-
- udelay(5);
-
- /* turn on the power EN_DSP_POWER high*/
- /* currently always on TBD */
-
- /* setup hpi control register */
- HPI_HPIC_1 = (u16) 0x0008;
- HPI_HPIC_2 = (u16) 0x0008;
-
- udelay(100);
-
- return 0;
-}
-
-#if 0
-/* turn off the host port interface */
-static void hpi_inactivate(void)
-{
- volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE;
-
- /* deactivate hpi */
- pld->dsp_hpi_on = 0x0;
-
- /* reset the dsp */
- /* pld->dsp_reset = 0x0; */
-
- /* turn off the power EN_DSP_POWER# high*/
- /* currently always on TBD */
-
-}
-#endif
-
-/* reset the DSP */
-static void dsp_reset(void)
-{
- volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE;
- pld->dsp_reset = 0x1;
- pld->dsp_hpi_on = 0x0;
-
- udelay(300000);
-
- pld->dsp_reset = 0x0;
- pld->dsp_hpi_on = 0x1;
-}
-
-
-/* write using autoinc (count is number of 32bit words) */
-static int hpi_write_inc(u32 addr, u32 *data, u32 count)
-{
- int i;
- u16 addr1, addr2;
-
- addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */
- addr2 = (u16) (addr & 0xffff);
-
- /* write address */
- HPI_HPIA_1 = addr1;
- HPI_HPIA_2 = addr2;
-
- debug("writing from data=0x%lx to 0x%lx\n",
- (ulong)data, (ulong)(data+count));
-
- for(i=0; i<count; i++) {
- HPI_HPID_INC_1 = (u16) ((data[i] >> 16) & 0xffff);
- HPI_HPID_INC_2 = (u16) (data[i] & 0xffff);
- debug("hpi_write_inc: data1=0x%x, data2=0x%x\n",
- (u16) ((data[i] >> 16) & 0xffff),
- (u16) (data[i] & 0xffff));
- }
-#if 0
- while(data_ptr < (u16*) (data + count)) {
- HPI_HPID_INC_1 = *(data_ptr++);
- HPI_HPID_INC_2 = *(data_ptr++);
- }
-#endif
-
- /* return number of bytes written */
- return count;
-}
-
-/*
- * read using autoinc (count is number of 32bit words)
- */
-static int hpi_read_inc(u32 addr, u32 *buf, u32 count)
-{
- int i;
- u16 addr1, addr2, data1, data2;
-
- addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */
- addr2 = (u16) (addr & 0xffff);
-
- /* write address */
- HPI_HPIA_1 = addr1;
- HPI_HPIA_2 = addr2;
-
- for(i=0; i<count; i++) {
- data1 = HPI_HPID_INC_1;
- data2 = HPI_HPID_INC_2;
- debug("hpi_read_inc: data1=0x%x, data2=0x%x\n", data1, data2);
- buf[i] = (((u32) data1) << 16) | (data2 & 0xffff);
- }
-
-#if 0
- while(buf_ptr < (u16*) (buf + count)) {
- *(buf_ptr++) = HPI_HPID_INC_1;
- *(buf_ptr++) = HPI_HPID_INC_2;
- }
-#endif
-
- /* return number of bytes read */
- return count;
-}
-
-
-/* write to non- auto inc regs */
-static int hpi_write_noinc(u32 addr, u32 data)
-{
-
- u16 addr1, addr2, data1, data2;
-
- addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */
- addr2 = (u16) (addr & 0xffff);
-
- /* printf("hpi_write_noinc: addr1=0x%x, addr2=0x%x\n", addr1, addr2); */
-
- HPI_HPIA_1 = addr1;
- HPI_HPIA_2 = addr2;
-
- data1 = (u16) ((data >> 16) & 0xffff);
- data2 = (u16) (data & 0xffff);
-
- /* printf("hpi_write_noinc: data1=0x%x, data2=0x%x\n", data1, data2); */
-
- HPI_HPID_NOINC_1 = data1;
- HPI_HPID_NOINC_2 = data2;
-
- return 0;
-}
-
-/* read from non- auto inc regs */
-static u32 hpi_read_noinc(u32 addr)
-{
- u16 addr1, addr2, data1, data2;
- u32 ret;
-
- addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */
- addr2 = (u16) (addr & 0xffff);
-
- HPI_HPIA_1 = addr1;
- HPI_HPIA_2 = addr2;
-
- /* printf("hpi_read_noinc: addr1=0x%x, addr2=0x%x\n", addr1, addr2); */
-
- data1 = HPI_HPID_NOINC_1;
- data2 = HPI_HPID_NOINC_2;
-
- /* printf("hpi_read_noinc: data1=0x%x, data2=0x%x\n", data1, data2); */
-
- ret = (((u32) data1) << 16) | (data2 & 0xffff);
- return ret;
-
-}
-
-/*
- * Host Port Interface Tests
- */
-
-#ifndef HPI_TEST_OSZI
-/* main test function */
-int hpi_test(void)
-{
- int err = 0;
- u32 i, ii, pattern, tmp;
-
- pattern = HPI_TEST_PATTERN;
-
- u32 test_data[HPI_TEST_CHUNKSIZE];
- u32 read_data[HPI_TEST_CHUNKSIZE];
-
- debug("hpi_test: activating hpi...");
- hpi_activate();
- debug("OK.\n");
-
-#if 0
- /* Dump the first 1024 bytes
- *
- */
- for(i=0; i<1024; i+=4) {
- if(i%16==0)
- printf("\n0x%08x: ", i);
- printf("0x%08x ", hpi_read_noinc(i));
- }
-#endif
-
- /* HPIA read-write test
- *
- */
- debug("hpi_test: starting HPIA read-write tests...\n");
- err |= hpi_write_addr_test(0xdeadc0de);
- err |= hpi_write_addr_test(0xbeefd00d);
- err |= hpi_write_addr_test(0xabcd1234);
- err |= hpi_write_addr_test(0xaaaaaaaa);
- if(err) {
- debug("hpi_test: HPIA read-write tests: *** FAILED ***\n");
- return -1;
- }
- debug("hpi_test: HPIA read-write tests: OK\n");
-
-
- /* read write test using nonincremental data regs
- *
- */
- debug("hpi_test: starting nonincremental tests...\n");
- for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) {
- err |= hpi_read_write_test(i, pattern);
-
- /* stolen from cmd_mem.c */
- if(pattern & 0x80000000) {
- pattern = -pattern; /* complement & increment */
- } else {
- pattern = ~pattern;
- }
- err |= hpi_read_write_test(i, pattern);
-
- if(err) {
- debug("hpi_test: nonincremental tests *** FAILED ***\n");
- return -1;
- }
- }
- debug("hpi_test: nonincremental test OK\n");
-
- /* read write a chunk of data using nonincremental data regs
- *
- */
- debug("hpi_test: starting nonincremental chunk tests...\n");
- pattern = HPI_TEST_PATTERN;
- for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) {
- hpi_write_noinc(i, pattern);
-
- /* stolen from cmd_mem.c */
- if(pattern & 0x80000000) {
- pattern = -pattern; /* complement & increment */
- } else {
- pattern = ~pattern;
- }
- }
- pattern = HPI_TEST_PATTERN;
- for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) {
- tmp = hpi_read_noinc(i);
-
- if(tmp != pattern) {
- debug("hpi_test: noninc chunk test *** FAILED *** @ 0x%x, written=0x%x, read=0x%x\n", i, pattern, tmp);
- err = -1;
- }
- /* stolen from cmd_mem.c */
- if(pattern & 0x80000000) {
- pattern = -pattern; /* complement & increment */
- } else {
- pattern = ~pattern;
- }
- }
- if(err)
- return -1;
- debug("hpi_test: nonincremental chunk test OK\n");
-
-
-#ifdef DO_TINY_TEST
- /* small verbose test using autoinc and nonautoinc to compare
- *
- */
- debug("hpi_test: tiny_autoinc_test...\n");
- hpi_tiny_autoinc_test();
- debug("hpi_test: tiny_autoinc_test done\n");
-#endif /* DO_TINY_TEST */
-
-
- /* $%& write a chunk of data using the autoincremental regs
- *
- */
- debug("hpi_test: starting autoinc test %d chunks with 0x%x bytes...\n",
- ((HPI_TEST_END - HPI_TEST_START) / HPI_TEST_CHUNKSIZE),
- HPI_TEST_CHUNKSIZE);
-
- for(i=HPI_TEST_START;
- i < ((HPI_TEST_END - HPI_TEST_START) / HPI_TEST_CHUNKSIZE);
- i++) {
- /* generate the pattern data */
- debug("generating pattern data: ");
- for(ii = 0; ii < HPI_TEST_CHUNKSIZE; ii++) {
- debug("0x%x ", pattern);
-
- test_data[ii] = pattern;
- read_data[ii] = 0x0; /* zero to be sure */
-
- /* stolen from cmd_mem.c */
- if(pattern & 0x80000000) {
- pattern = -pattern; /* complement & increment */
- } else {
- pattern = ~pattern;
- }
- }
- debug("done\n");
-
- debug("Writing autoinc data @ 0x%x\n", i);
- hpi_write_inc(i, test_data, HPI_TEST_CHUNKSIZE);
-
- debug("Reading autoinc data @ 0x%x\n", i);
- hpi_read_inc(i, read_data, HPI_TEST_CHUNKSIZE);
-
- /* compare */
- for(ii = 0; ii < HPI_TEST_CHUNKSIZE; ii++) {
- debug("hpi_test_autoinc: @ 0x%x, written=0x%x, read=0x%x", i+ii, test_data[ii], read_data[ii]);
- if(read_data[ii] != test_data[ii]) {
- debug("hpi_test: autoinc test @ 0x%x, written=0x%x, read=0x%x *** FAILED ***\n", i+ii, test_data[ii], read_data[ii]);
- return -1;
- }
- }
- }
- debug("hpi_test: autoinc test OK\n");
-
- return 0;
-}
-#else /* HPI_TEST_OSZI */
-int hpi_test(void)
-{
- int i;
- u32 read_data[TINY_AUTOINC_DATA_SIZE];
-
- unsigned int dummy_data[TINY_AUTOINC_DATA_SIZE] = {
- 0x11112222, 0x33334444, 0x55556666, 0x77778888,
- 0x9999aaaa, 0xbbbbcccc, 0xddddeeee, 0xffff1111,
- 0x00010002, 0x00030004, 0x00050006, 0x00070008,
- 0x0009000a, 0x000b000c, 0x000d000e, 0x000f0001
- };
-
- debug("hpi_test: activating hpi...");
- hpi_activate();
- debug("OK.\n");
-
- while(1) {
- led9(1);
- debug(" writing to autoinc...\n");
- hpi_write_inc(TINY_AUTOINC_BASE_ADDR,
- dummy_data, TINY_AUTOINC_DATA_SIZE);
-
- debug(" reading from autoinc...\n");
- hpi_read_inc(TINY_AUTOINC_BASE_ADDR,
- read_data, TINY_AUTOINC_DATA_SIZE);
-
- for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) {
- debug(" written=0x%x, read(inc)=0x%x\n",
- dummy_data[i], read_data[i]);
- }
- led9(0);
- udelay(2000000);
- }
- return 0;
-}
-#endif
-
-/* test if Host Port Address Register can be written correctly */
-static int hpi_write_addr_test(u32 addr)
-{
- u32 read_back;
- /* write address */
- HPI_HPIA_1 = ((u16) (addr >> 16)); /* First HW is most significant */
- HPI_HPIA_2 = ((u16) addr);
-
- read_back = (((u32) HPI_HPIA_1)<<16) | ((u32) HPI_HPIA_2);
-
- if(read_back == addr) {
- debug(" hpi_write_addr_test OK: written=0x%x, read=0x%x\n",
- addr, read_back);
- return 0;
- } else {
- debug(" hpi_write_addr_test *** FAILED ***: written=0x%x, read=0x%x\n",
- addr, read_back);
- return -1;
- }
-
- return 0;
-}
-
-/* test if a simple read/write sequence succeeds */
-static int hpi_read_write_test(u32 addr, u32 data)
-{
- u32 read_back;
-
- hpi_write_noinc(addr, data);
- read_back = hpi_read_noinc(addr);
-
- if(read_back == data) {
- debug(" hpi_read_write_test: OK, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back);
- return 0;
- } else {
- debug(" hpi_read_write_test: *** FAILED ***, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back);
- return -1;
- }
-
- return 0;
-}
-
-#ifdef DO_TINY_TEST
-static int hpi_tiny_autoinc_test(void)
-{
- int i;
- u32 read_data[TINY_AUTOINC_DATA_SIZE];
- u32 read_data_noinc[TINY_AUTOINC_DATA_SIZE];
-
- unsigned int dummy_data[TINY_AUTOINC_DATA_SIZE] = {
- 0x11112222, 0x33334444, 0x55556666, 0x77778888,
- 0x9999aaaa, 0xbbbbcccc, 0xddddeeee, 0xffff1111,
- 0x00010002, 0x00030004, 0x00050006, 0x00070008,
- 0x0009000a, 0x000b000c, 0x000d000e, 0x000f0001
- };
-
- printf(" writing to autoinc...\n");
- hpi_write_inc(TINY_AUTOINC_BASE_ADDR, dummy_data, TINY_AUTOINC_DATA_SIZE);
-
- printf(" reading from autoinc...\n");
- hpi_read_inc(TINY_AUTOINC_BASE_ADDR, read_data, TINY_AUTOINC_DATA_SIZE);
-
- printf(" reading from noinc for comparison...\n");
- for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++)
- read_data_noinc[i] = hpi_read_noinc(TINY_AUTOINC_BASE_ADDR+i*4);
-
- for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) {
- printf(" written=0x%x, read(inc)=0x%x, read(noinc)=0x%x\n",
- dummy_data[i], read_data[i], read_data_noinc[i]);
- }
- return 0;
-}
-#endif /* DO_TINY_TEST */
-
-#endif /* CONFIG_SPC1920_HPI_TEST */
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-int hpi_init(void);
-
-#ifdef CONFIG_SPC1920_HPI_TEST
-int hpi_test(void);
-#endif
+++ /dev/null
-#ifndef __PLD_H__
-#define __PLD_H__
-
-typedef struct spc1920_pld {
- uchar com1_en;
- uchar dsp_reset;
- uchar dsp_hpi_on;
- uchar superv_mode;
- uchar codec_dsp_power_en;
- uchar clk3_select;
- uchar clk4_select;
-} spc1920_pld_t;
-
-#endif /* __PLD_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <mpc8xx.h>
-#include "pld.h"
-#include "hpi.h"
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-static long int dram_size (long int, long int *, long int);
-
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 0 in UPMB RAM)
- */
- 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
- 0x1FF77C47, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPMB RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
- /*
- * Burst Read. (Offset 8 in UPMB RAM)
- */
- 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
- 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Single Write. (Offset 18 in UPMB RAM)
- */
- 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPMB RAM)
- */
- 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
- 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Refresh (Offset 30 in UPMB RAM)
- */
- 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC84, 0xFFFFFC07, /* last */
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /*
- * Exception. (Offset 3c in UPMB RAM)
- */
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
- /* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; */
-
- long int size_b0;
- long int size8, size9;
- int i;
-
- /*
- * Configure UPMB for SDRAM
- */
- upmconfig (UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- udelay(100);
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- /* burst length=4, burst type=sequential, CAS latency=2 */
- memctl->memc_mar = CONFIG_SYS_MAR;
-
- /*
- * Map controller bank 1 to the SDRAM bank at preliminary address.
- */
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
-
- /* initialize memory address register */
- memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */
-
- /* mode initialization (offset 5) */
- udelay (200); /* 0x80006105 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x05);
-
- /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
- udelay (1); /* 0x80006130 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);
- udelay (1); /* 0x80006130 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);
- udelay (1); /* 0x80006106 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x06);
-
- memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
-
- udelay (200);
-
- /* Need at least 10 DRAM accesses to stabilize */
- for (i = 0; i < 10; ++i) {
- volatile unsigned long *addr =
- (volatile unsigned long *) CONFIG_SYS_SDRAM_BASE;
- unsigned long val;
-
- val = *(addr + i);
- *(addr + i) = val;
- }
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MBMR_9COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration at 9 columns */
- size_b0 = size9;
- memctl->memc_mbmr = CONFIG_SYS_MBMR_9COL | MBMR_PTBE;
- udelay (500);
- } else { /* back to 8 columns */
- size_b0 = size8;
- memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
- udelay (500);
- }
-
- /*
- * Final mapping:
- */
-
- memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) |
- OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
- memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
- udelay (1000);
-
- /* initalize the DSP Host Port Interface */
- hpi_init();
-
- /* FRAM Setup */
- memctl->memc_or4 = CONFIG_SYS_OR4;
- memctl->memc_br4 = CONFIG_SYS_BR4;
- udelay(1000);
-
- return (size_b0);
-}
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-static long int dram_size (long int mbmr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mbmr = mbmr_value;
-
- return (get_ram_size (base, maxsize));
-}
-
-
-/************* other stuff ******************/
-
-
-int board_early_init_f(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- /* Set Go/NoGo led (PA15) to color red */
- immap->im_ioport.iop_papar &= ~0x1;
- immap->im_ioport.iop_paodr &= ~0x1;
- immap->im_ioport.iop_padir |= 0x1;
- immap->im_ioport.iop_padat |= 0x1;
-
-#if 0
- /* Turn on LED PD9 */
- immap->im_ioport.iop_pdpar &= ~(0x0040);
- immap->im_ioport.iop_pddir |= 0x0040;
- immap->im_ioport.iop_pddat |= 0x0040;
-#endif
-
- /*
- * Enable console on SMC1. This requires turning on
- * the com2_en signal and SMC1_DISABLE
- */
-
- /* SMC1_DISABLE: PB17 */
- immap->im_cpm.cp_pbodr &= ~0x4000;
- immap->im_cpm.cp_pbpar &= ~0x4000;
- immap->im_cpm.cp_pbdir |= 0x4000;
- immap->im_cpm.cp_pbdat &= ~0x4000;
-
- /* COM2_EN: PD10 */
- immap->im_ioport.iop_pdpar &= ~0x0020;
- immap->im_ioport.iop_pddir &= ~0x4000;
- immap->im_ioport.iop_pddir |= 0x0020;
- immap->im_ioport.iop_pddat |= 0x0020;
-
-
-#ifdef CONFIG_SYS_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */
- immap->im_cpm.cp_simode |= 0x7000;
- immap->im_cpm.cp_simode &= ~(0x8000);
-#endif
-
- return 0;
-}
-
-int last_stage_init(void)
-{
-#ifdef CONFIG_SPC1920_HPI_TEST
- printf("CMB1920 Host Port Interface Test: %s\n",
- hpi_test() ? "Failed!" : "OK");
-#endif
- return 0;
-}
-
-int checkboard (void)
-{
- puts("Board: SPC1920\n");
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
#
obj-y += board.o
obj-$(CONFIG_SUNXI_GMAC) += gmac.o
+obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o
+obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o
+obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o
obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o
+obj-$(CONFIG_R7DONGLE) += dram_r7dongle.o
*/
#include <common.h>
+#ifdef CONFIG_AXP152_POWER
+#include <axp152.h>
+#endif
+#ifdef CONFIG_AXP209_POWER
+#include <axp209.h>
+#endif
#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/dram.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
+#include <asm/io.h>
+#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
}
#endif
+void i2c_init_board(void)
+{
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
+ clock_twi_onoff(0, 1);
+}
+
#ifdef CONFIG_SPL_BUILD
void sunxi_board_init(void)
{
+ int power_failed = 0;
unsigned long ramsize;
+#ifdef CONFIG_AXP152_POWER
+ power_failed = axp152_init();
+ power_failed |= axp152_set_dcdc2(1400);
+ power_failed |= axp152_set_dcdc3(1500);
+ power_failed |= axp152_set_dcdc4(1250);
+ power_failed |= axp152_set_ldo2(3000);
+#endif
+#ifdef CONFIG_AXP209_POWER
+ power_failed |= axp209_init();
+ power_failed |= axp209_set_dcdc2(1400);
+ power_failed |= axp209_set_dcdc3(1250);
+ power_failed |= axp209_set_ldo2(3000);
+ power_failed |= axp209_set_ldo3(2800);
+ power_failed |= axp209_set_ldo4(2800);
+#endif
+
printf("DRAM:");
ramsize = sunxi_dram_init();
printf(" %lu MiB\n", ramsize >> 20);
if (!ramsize)
hang();
+
+ /*
+ * Only clock up the CPU to full speed if we are reasonably
+ * assured it's being powered with suitable core voltage
+ */
+ if (!power_failed)
+ clock_set_pll1(CONFIG_CLK_FULL_SPEED);
+ else
+ printf("Failed to set core voltage! Can't set CPU frequency\n");
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ if (!getenv("ethaddr")) {
+ uint32_t reg_val = readl(SUNXI_SID_BASE);
+
+ if (reg_val) {
+ uint8_t mac_addr[6];
+
+ mac_addr[0] = 0x02; /* Non OUI / registered MAC address */
+ mac_addr[1] = (reg_val >> 0) & 0xff;
+ reg_val = readl(SUNXI_SID_BASE + 0x0c);
+ mac_addr[2] = (reg_val >> 24) & 0xff;
+ mac_addr[3] = (reg_val >> 16) & 0xff;
+ mac_addr[4] = (reg_val >> 8) & 0xff;
+ mac_addr[5] = (reg_val >> 0) & 0xff;
+
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+ }
+
+ return 0;
}
#endif
--- /dev/null
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 408,
+ .type = 3,
+ .rank_num = 1,
+ .density = 2048,
+ .io_width = 16,
+ .bus_width = 16,
+ .cas = 9,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 256,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0,
+ .emr2 = 0x10,
+ .emr3 = 0,
+
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
--- /dev/null
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 480,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 32,
+ .cas = 6,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x30926692,
+ .tpr1 = 0x1090,
+ .tpr2 = 0x1a0c8,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0,
+ .emr2 = 0,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
--- /dev/null
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 480,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 32,
+ .cas = 9,
+ .zq = 0x7f,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0x0,
+ .tpr4 = 0x1,
+ .tpr5 = 0x0,
+ .emr1 = 0x4,
+ .emr2 = 0x10,
+ .emr3 = 0x0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
--- /dev/null
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 384,
+ .type = 3,
+ .rank_num = 1,
+ .density = 2048,
+ .io_width = 8,
+ .bus_width = 32,
+ .cas = 9,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0x04,
+ .emr2 = 0x10,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
/* Set MII clock */
+#ifdef CONFIG_RGMII
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
CCM_GMAC_CTRL_GPIT_RGMII);
+#else
+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
+ CCM_GMAC_CTRL_GPIT_MII);
+#endif
/* Configure pin mux settings for GMAC */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
+#ifdef CONFIG_RGMII
/* skip unused pins in RGMII mode */
if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
continue;
+#endif
sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
+#ifdef CONFIG_RGMII
return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
+#else
+ return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
+#endif
}
strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
am43xx_board_name[sizeof(header->name)] = 0;
+ strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version));
+ am43xx_board_rev[sizeof(header->version)] = 0;
+
return 0;
}
.emif_rd_wr_lvl_rmp_ctl = 0x0,
.emif_rd_wr_lvl_ctl = 0x0,
.emif_ddr_phy_ctlr_1 = 0x0E084006,
- .emif_rd_wr_exec_thresh = 0x00000405,
+ .emif_rd_wr_exec_thresh = 0x80000405,
.emif_ddr_ext_phy_ctrl_1 = 0x04010040,
.emif_ddr_ext_phy_ctrl_2 = 0x00500050,
.emif_ddr_ext_phy_ctrl_3 = 0x00500050,
.emif_ddr_ext_phy_ctrl_4 = 0x00500050,
- .emif_ddr_ext_phy_ctrl_5 = 0x00500050
+ .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
+ .emif_prio_class_serv_map = 0x80000001,
+ .emif_connect_id_serv_1_map = 0x80000094,
+ .emif_connect_id_serv_2_map = 0x00000000,
+ .emif_cos_config = 0x000FFFFF
};
const u32 ext_phy_ctrl_const_base_lpddr2[] = {
.emif_rd_wr_lvl_rmp_win = 0x0,
.emif_rd_wr_lvl_rmp_ctl = 0x0,
.emif_rd_wr_lvl_ctl = 0x0,
- .emif_rd_wr_exec_thresh = 0x00000405
+ .emif_rd_wr_exec_thresh = 0x80000405,
+ .emif_prio_class_serv_map = 0x80000001,
+ .emif_connect_id_serv_1_map = 0x80000094,
+ .emif_connect_id_serv_2_map = 0x00000000,
+ .emif_cos_config = 0x000FFFFF
+};
+
+/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
+const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
+ .sdram_config = 0x638413B2,
+ .ref_ctrl = 0x00000C30,
+ .sdram_tim1 = 0xEAAAD4DB,
+ .sdram_tim2 = 0x266B7FDA,
+ .sdram_tim3 = 0x107F8678,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x50074BE4,
+ .temp_alert_config = 0x0,
+ .emif_ddr_phy_ctlr_1 = 0x0E004008,
+ .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
+ .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
+ .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
+ .emif_rd_wr_exec_thresh = 0x80000405,
+ .emif_prio_class_serv_map = 0x80000001,
+ .emif_connect_id_serv_1_map = 0x80000094,
+ .emif_connect_id_serv_2_map = 0x00000000,
+ .emif_cos_config = 0x000FFFFF
+};
+
+/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
+const struct emif_regs ddr3_emif_regs_400Mhz_production = {
+ .sdram_config = 0x638413B2,
+ .ref_ctrl = 0x00000C30,
+ .sdram_tim1 = 0xEAAAD4DB,
+ .sdram_tim2 = 0x266B7FDA,
+ .sdram_tim3 = 0x107F8678,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x50074BE4,
+ .temp_alert_config = 0x0,
+ .emif_ddr_phy_ctlr_1 = 0x0E004008,
+ .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
+ .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
+ .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
+ .emif_rd_wr_exec_thresh = 0x80000405,
+ .emif_prio_class_serv_map = 0x80000001,
+ .emif_connect_id_serv_1_map = 0x80000094,
+ .emif_connect_id_serv_2_map = 0x00000000,
+ .emif_cos_config = 0x000FFFFF
};
static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
.emif_rd_wr_lvl_rmp_win = 0x0,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x80000000,
+ .emif_prio_class_serv_map = 0x80000001,
+ .emif_connect_id_serv_1_map = 0x80000094,
+ .emif_connect_id_serv_2_map = 0x00000000,
+ .emif_cos_config = 0x000FFFFF
};
const u32 ext_phy_ctrl_const_base_ddr3[] = {
0x08102040
};
+const u32 ext_phy_ctrl_const_base_ddr3_beta[] = {
+ 0x00000000,
+ 0x00000045,
+ 0x00000046,
+ 0x00000048,
+ 0x00000047,
+ 0x00000000,
+ 0x0000004C,
+ 0x00000070,
+ 0x00000085,
+ 0x000000A3,
+ 0x00000000,
+ 0x0000000C,
+ 0x00000030,
+ 0x00000045,
+ 0x00000063,
+ 0x00000000,
+ 0x0,
+ 0x0,
+ 0x40000000,
+ 0x08102040
+};
+
+const u32 ext_phy_ctrl_const_base_ddr3_production[] = {
+ 0x00000000,
+ 0x00000044,
+ 0x00000044,
+ 0x00000046,
+ 0x00000046,
+ 0x00000000,
+ 0x00000059,
+ 0x00000077,
+ 0x00000093,
+ 0x000000A8,
+ 0x00000000,
+ 0x00000019,
+ 0x00000037,
+ 0x00000053,
+ 0x00000068,
+ 0x00000000,
+ 0x0,
+ 0x0,
+ 0x40000000,
+ 0x08102040
+};
+
static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
/* first 5 are taken care by emif_regs */
0x00700070,
if (board_is_eposevm()) {
*regs = ext_phy_ctrl_const_base_lpddr2;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
+ } else if (board_is_evm_14_or_later()) {
+ *regs = ext_phy_ctrl_const_base_ddr3_production;
+ *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production);
+ } else if (board_is_evm_12_or_later()) {
+ *regs = ext_phy_ctrl_const_base_ddr3_beta;
+ *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta);
} else if (board_is_gpevm()) {
*regs = ext_phy_ctrl_const_base_ddr3;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
*/
if (board_is_eposevm()) {
config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
+ } else if (board_is_evm_14_or_later()) {
+ enable_vtt_regulator();
+ config_ddr(0, &ioregs_ddr3, NULL, NULL,
+ &ddr3_emif_regs_400Mhz_production, 0);
+ } else if (board_is_evm_12_or_later()) {
+ enable_vtt_regulator();
+ config_ddr(0, &ioregs_ddr3, NULL, NULL,
+ &ddr3_emif_regs_400Mhz_beta, 0);
} else if (board_is_gpevm()) {
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
int board_init(void)
{
+ struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
+ u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
+ modena_init0_bw_integer, modena_init0_watermark_0;
+
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ /* Clear all important bits for DSS errata that may need to be tweaked*/
+ mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
+ MREQPRIO_0_SAB_INIT0_MASK;
+
+ mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
+
+ modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
+ BW_LIMITER_BW_FRAC_MASK;
+
+ modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
+ BW_LIMITER_BW_INT_MASK;
+
+ modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
+ BW_LIMITER_BW_WATERMARK_MASK;
+
+ /* Setting MReq Priority of the DSS*/
+ mreqprio_0 |= 0x77;
+
+ /*
+ * Set L3 Fast Configuration Register
+ * Limiting bandwith for ARM core to 700 MBPS
+ */
+ modena_init0_bw_fractional |= 0x10;
+ modena_init0_bw_integer |= 0x3;
+
+ writel(mreqprio_0, &cdev->mreqprio_0);
+ writel(mreqprio_1, &cdev->mreqprio_1);
+
+ writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
+ writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
+ writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
+
return 0;
}
#include <asm/arch/omap.h>
static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START;
+static char *const am43xx_board_rev = (char *)AM4372_BOARD_VERSION_START;
/*
* TI AM437x EVMs define a system EEPROM that defines certain sub-fields.
return !strncmp(am43xx_board_name, "AM43__SK", HDR_NAME_LEN);
}
+static inline int board_is_evm_14_or_later(void)
+{
+ return (board_is_gpevm() && strncmp("1.4", am43xx_board_rev, 3) <= 0);
+}
+
+static inline int board_is_evm_12_or_later(void)
+{
+ return (board_is_gpevm() && strncmp("1.2", am43xx_board_rev, 3) <= 0);
+}
+
void enable_uart0_pin_mux(void);
void enable_board_pin_mux(void);
void enable_i2c0_pin_mux(void);
int board_late_init(void)
{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ if (omap_revision() == DRA722_ES1_0)
+ setenv("board_name", "dra72x");
+ else
+ setenv("board_name", "dra7xx");
+#endif
init_sata(0);
return 0;
}
{GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
{GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
{GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
+#if (CONFIG_CONS_INDEX == 1)
{UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
{UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
{UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */
{UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */
+#elif (CONFIG_CONS_INDEX == 3)
+ {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
+ {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
+#endif
{I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
{I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
{MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
+++ /dev/null
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = v37.o flash.o
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
- * U-Boot port on RPXlite board
- *
- * Some of flash control words are modified. (from 2x16bit device
- * to 4x8bit device)
- * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices
- * are not tested.
- *
- * (?) Does an RPXLite board which
- * does not use AM29LV800 flash memory exist ?
- * I don't know...
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips);
-static void flash_get_id_word( void *ptr, short *ptr_manuf, short *ptr_dev_id);
-static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0, size_b1;
- short manu, dev_id;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Do sizing to get full correct info */
-
- flash_get_id_word((void*)CONFIG_SYS_FLASH_BASE0,&manu,&dev_id);
-
- size_b0 = flash_get_size(manu, dev_id, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE0, &flash_info[0],0);
-
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (0 - size_b0);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE0
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
- flash_get_id_long((void*)CONFIG_SYS_FLASH_BASE1,&manu,&dev_id);
-
- size_b1 = 2 * flash_get_size(manu, dev_id, &flash_info[1]);
-
- flash_get_offsets(CONFIG_SYS_FLASH_BASE1, &flash_info[1],1);
-
- memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (0 - size_b1);
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
-
- return (size_b0+size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips)
-{
- int i, addr_shift;
- vu_short *addr = (vu_short*)base;
-
- addr[0x555] = 0x00AA ;
- addr[0xAAA] = 0x0055 ;
- addr[0x555] = 0x0090 ;
-
- addr_shift = (two_chips ? 2 : 1 );
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + (0x00000000<<addr_shift);
- info->start[1] = base + (0x00002000<<addr_shift);
- info->start[2] = base + (0x00003000<<addr_shift);
- info->start[3] = base + (0x00004000<<addr_shift);
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + ((i-3) * (0x00008000<<addr_shift)) ;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - (0x00002000<<addr_shift);
- info->start[i--] = base + info->size - (0x00003000<<addr_shift);
- info->start[i--] = base + info->size - (0x00004000<<addr_shift);
- for (; i >= 0; i--) {
- info->start[i] = base + i * (0x00008000<<addr_shift);
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (vu_short *)(info->start[i]);
- info->protect[i] = addr[1<<addr_shift] & 1 ;
- }
-
- addr = (vu_short *)info->start[0];
- *addr = 0xF0F0; /* reset bank */
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_TOSH: printf ("TOSHIBA "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static void flash_get_id_word( void *ptr, short *ptr_manuf, short *ptr_dev_id)
-{
- vu_short *addr = (vu_short*)ptr;
-
- addr[0x555] = 0x00AA ;
- addr[0xAAA] = 0x0055 ;
- addr[0x555] = 0x0090 ;
-
- *ptr_manuf = addr[0];
- *ptr_dev_id = addr[1];
-
- addr[0] = 0xf0f0; /* return to normal */
-}
-
-static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id)
-{
- vu_short *addr = (vu_short*)ptr;
- vu_short *addr1, *addr2, *addr3;
-
- addr1 = (vu_short*) ( ((int)ptr) + (0x5555<<2) );
- addr2 = (vu_short*) ( ((int)ptr) + (0x2AAA<<2) );
- addr3 = (vu_short*) ( ((int)ptr) + (0x5555<<2) );
-
- *addr1 = 0xAAAA;
- *addr2 = 0x5555;
- *addr3 = 0x9090;
-
- *ptr_manuf = addr[0];
- *ptr_dev_id = addr[2];
-
- addr[0] = 0xf0f0; /* return to normal */
-}
-
-static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info)
-{
- switch (manu) {
- case ((short)AMD_MANUFACT):
- info->flash_id = FLASH_MAN_AMD;
- break;
- case ((short)FUJ_MANUFACT):
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case ((short)TOSH_MANUFACT):
- info->flash_id = FLASH_MAN_TOSH;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
-
- switch (dev_id) {
- case ((short)TOSH_ID_FVT160):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 1 MB */
-
- case ((short)TOSH_ID_FVB160):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 1 MB */
-
- case ((short)AMD_ID_LV400T):
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case ((short)AMD_ID_LV400B):
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case ((short)AMD_ID_LV800T):
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case ((short)AMD_ID_LV800B):
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00400000; /*%%% Size doubled by yooth */
- break; /* => 4 MB */
-
- case ((short)AMD_ID_LV160T):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 4 MB */
-
- case ((short)AMD_ID_LV160B):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 4 MB */
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- return(info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_short *addr = (vu_short*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x555] = (vu_short)0xAAAAAAAA;
- addr[0xAAA] = (vu_short)0x55555555;
- addr[0x555] = (vu_short)0x80808080;
- addr[0x555] = (vu_short)0xAAAAAAAA;
- addr[0xAAA] = (vu_short)0x55555555;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_short *)(info->start[sect]) ;
- addr[0] = (vu_short)0x30303030 ;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_short *)(info->start[l_sect]);
- while ((addr[0] & 0x8080) != 0x8080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (vu_short *)info->start[0];
- addr[0] = (vu_short)0xF0F0F0F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_short *addr = (vu_short *)(info->start[0]);
- vu_short sdata;
-
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
-
- /* First write upper 16 bits */
- sdata = (short)(data>>16);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x555] = 0xAAAA;
- addr[0xAAA] = 0x5555;
- addr[0x555] = 0xA0A0;
-
- *((vu_short *)dest) = sdata;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_short *)dest) & 0x8080) != (sdata & 0x8080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
-
- /* Now write lower 16 bits */
- sdata = (short)(data&0xffff);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x555] = 0xAAAA;
- addr[0xAAA] = 0x5555;
- addr[0x555] = 0xA0A0;
-
- *((vu_short *)dest + 1) = sdata;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_short *)dest + 1) & 0x8080) != (sdata & 0x8080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * (C) Copyright 2003-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
- * U-Boot port on RPXlite board
- *
- * DRAM related UPMA register values are modified.
- * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
- */
-
-#include <common.h>
-#include "mpc8xx.h"
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (void);
-
-/* ------------------------------------------------------------------------- */
-
-#define MBYTE (1024*1024)
-#define DRAM_DELAY 0x00000379 /* DRAM delay count */
-#define _NOT_USED_ 0xFFFFCC25
-
-const uint sdram_table[] =
-{
- /* single read. (offset 0 in upm RAM) */
- 0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000,
- 0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35,
-
- /* burst read. (Offset 8 in upm RAM) */
- 0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000,
- 0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* single write. (Offset 0x18 in upm RAM) */
- 0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* burst write. (Offset 0x20 in upm RAM) */
- 0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000,
- 0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Refresh cycle, offset 0x30 */
- 0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* Exception, 0ffset 0x3C */
- 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-};
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Return 1 for now.
- *
- */
-
-int checkboard (void)
-{
- printf("Marel V37\n") ;
- return (0) ;
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long temp;
- volatile int delay_cnt;
- long int ramsize;
-
- ramsize = dram_size();
-
- /* Refresh clock prescalar */
- memctl->memc_mptpr = 0x400 ;
-
- if( ramsize == 32*MBYTE )
- temp = 0xd0904110;
- else /* 16MB */
- temp = 0xd0802110;
-
- memctl->memc_mbmr = temp;
-
- upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- /* Map controller banks 2 to the SDRAM bank */
- memctl->memc_or2 = 0xA00 | (0 - ramsize);
- memctl->memc_br2 = 0xC1;
-
- memctl->memc_mbmr = temp | 0x08;
- memctl->memc_mcr = 0x80804130;
-
- delay_cnt = 0;
- while( delay_cnt++ < DRAM_DELAY )
- ;
-
- /* Run MRS command in location 5-8 of UPMB */
-
- memctl->memc_mbmr = temp | 0x04;
- memctl->memc_mar = 0x88;
-
- memctl->memc_mcr = 0x80804105;
-
- delay_cnt = 0;
- while( delay_cnt++ < DRAM_DELAY )
- ;
-
-#ifdef CONFIG_CAN_DRIVER
- /* Initialize OR3 / BR3 */
- memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
- memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
-
- /* Initialize MBMR */
- memctl->memc_mamr = MAMR_GPL_A4DIS; /* GPL_A4 ouput line Disable */
-
- /* Initialize UPMB for CAN: single read */
- memctl->memc_mdr = 0xFFFFC004;
- memctl->memc_mcr = 0x0100 | UPMA;
-
- memctl->memc_mdr = 0x0FFFD004;
- memctl->memc_mcr = 0x0101 | UPMA;
-
- memctl->memc_mdr = 0x0FFFC000;
- memctl->memc_mcr = 0x0102 | UPMA;
-
- memctl->memc_mdr = 0x3FFFC004;
- memctl->memc_mcr = 0x0103 | UPMA;
-
- memctl->memc_mdr = 0xFFFFDC05;
- memctl->memc_mcr = 0x0104 | UPMA;
-
- /* Initialize UPMB for CAN: single write */
- memctl->memc_mdr = 0xFFFCC004;
- memctl->memc_mcr = 0x0118 | UPMA;
-
- memctl->memc_mdr = 0xCFFCD004;
- memctl->memc_mcr = 0x0119 | UPMA;
-
- memctl->memc_mdr = 0x0FFCC000;
- memctl->memc_mcr = 0x011A | UPMA;
-
- memctl->memc_mdr = 0x7FFCC004;
- memctl->memc_mcr = 0x011B | UPMA;
-
- memctl->memc_mdr = 0xFFFDCC05;
- memctl->memc_mcr = 0x011C | UPMA;
-#endif /* CONFIG_CAN_DRIVER */
-
- return (dram_size());
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Find size of RAM from configuration pins.
- * The input pins that contain the memory size are also the debug port
- * pins. Normally they are configured as debug port pins. To be able
- * to read the memory configuration, we must deactivate the debug port
- * and enable the pcmcia input pins. Then return the register to
- * previous state.
- */
-
-static long int dram_size ()
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile sysconf8xx_t *siu = &immap->im_siu_conf;
- volatile pcmconf8xx_t *pcm = &immap->im_pcmcia;
- long int i, memory=1;
- unsigned long siu_mcr;
-
- siu_mcr = siu->sc_siumcr;
- siu->sc_siumcr = siu_mcr & 0xFF9FFFFF;
- for(i=0; i<10; i++) i = i;
-
- memory = (pcm->pcmc_pipr>>12) & 0x3;
-
- siu->sc_siumcr = siu_mcr;
-
- switch( memory )
- {
- case 1:
- return( 32*MBYTE );
- case 2:
- return( 64*MBYTE );
- default:
- break;
- }
- return( 16*MBYTE );
-}
# Please copy ps7_init.c/h from hw project to this directory
obj-$(CONFIG_SPL_BUILD) += \
$(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o)
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_ps7_init.o := -Wstrict-prototypes
Active aarch64 armv8 fsl-lsch3 freescale ls2085a ls2085a_emu ls2085a_emu:ARM64,EMU York Sun <yorksun@freescale.com>
Active aarch64 armv8 fsl-lsch3 freescale ls2085a ls2085a_emu_D4 ls2085a_emu:ARM64,EMU,SYS_FSL_DDR4 York Sun <yorksun@freescale.com>
Active aarch64 armv8 fsl-lsch3 freescale ls2085a ls2085a_simu ls2085a_simu:ARM64,SIMU York Sun <yorksun@freescale.com>
-Active arc arc700 - abilis
- tb100 - Alexey Brodkin <abrodkin@synopsys.com>
-Active arc arc700 - synopsys - a
xs101 - Alexey Brodkin <abrodkin@synopsys.com>
-Active arc arc700 - synopsys
<none> arcangel4 - Alexey Brodkin <abrodkin@synopsys.com>
-Active arc arc700 - synopsys
<none> arcangel4-be - Alexey Brodkin <abrodkin@synopsys.com>
+Active arc arc700 - abilis
tb100 tb100 - Alexey Brodkin <abrodkin@synopsys.com>
+Active arc arc700 - synopsys - a
rcangel4 - Alexey Brodkin <abrodkin@synopsys.com>
+Active arc arc700 - synopsys
- arcangel4-be - Alexey Brodkin <abrodkin@synopsys.com>
+Active arc arc700 - synopsys
axs101 axs101 - Alexey Brodkin <abrodkin@synopsys.com>
Active arm arm1136 - armltd integrator integratorcp_cm1136 integratorcp:CM1136 Linus Walleij <linus.walleij@linaro.org>
-Active arm arm1136 mx31 - - imx31_phycore - -
-Active arm arm1136 mx31 davedenx - qong - Wolfgang Denk <wd@denx.de>
-Active arm arm1136 mx31 freescale - mx31pdk - Fabio Estevam <fabio.estevam@freescale.com>
-Active arm arm1136 mx31 hale - tt01 - Helmut Raiger <helmut.raiger@hale.at>
-Active arm arm1136 mx31 logicpd - imx31_litekit - -
-Active arm arm1136 mx35 - - woodburn - Stefano Babic <sbabic@denx.de>
+Active arm arm1136 mx31 - imx31_phycore imx31_phycore - -
+Active arm arm1136 mx31 davedenx qong qong - Wolfgang Denk <wd@denx.de>
+Active arm arm1136 mx31 freescale mx31pdk mx31pdk - Fabio Estevam <fabio.estevam@freescale.com>
+Active arm arm1136 mx31 hale tt01 tt01 - Helmut Raiger <helmut.raiger@hale.at>
+Active arm arm1136 mx31 logicpd imx31_litekit imx31_litekit - -
+Active arm arm1136 mx35 - woodburn woodburn - Stefano Babic <sbabic@denx.de>
Active arm arm1136 mx35 - woodburn woodburn_sd woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg -
-Active arm arm1136 mx35 CarMediaLab - flea3 - Stefano Babic <sbabic@denx.de>
-Active arm arm1136 mx35 freescale - mx35pdk - Stefano Babic <sbabic@denx.de>
+Active arm arm1136 mx35 CarMediaLab flea3 flea3 - Stefano Babic <sbabic@denx.de>
+Active arm arm1136 mx35 freescale mx35pdk mx35pdk - Stefano Babic <sbabic@denx.de>
Active arm arm1176 bcm2835 raspberrypi rpi_b rpi_b - Stephen Warren <swarren@wwwdotorg.org>
Active arm arm720t - armltd integrator integratorap_cm720t integratorap:CM720T Linus Walleij <linus.walleij@linaro.org>
Active arm arm920t - armltd integrator integratorap_cm920t integratorap:CM920T Linus Walleij <linus.walleij@linaro.org>
Active arm arm920t - armltd integrator integratorcp_cm920t integratorcp:CM920T Linus Walleij <linus.walleij@linaro.org>
-Active arm arm920t a320 faraday - a320evb - Po-Yu Chuang <ratbert@faraday-tech.com>
+Active arm arm920t a320 faraday a320evb a320evb - Po-Yu Chuang <ratbert@faraday-tech.com>
Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek - Andreas Bießmann <andreas.devel@gmail.com>
Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek_ram at91rm9200ek:RAMBOOT Andreas Bießmann <andreas.devel@gmail.com>
Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2 - Jens Scharsig <esw@bus-elektronik.de>
Active arm arm920t at91 eukrea cpuat91 cpuat91 - Eric Benard <eric@eukrea.com>
Active arm arm920t at91 eukrea cpuat91 cpuat91_ram cpuat91:RAMBOOT Eric Benard <eric@eukrea.com>
Active arm arm920t ep93xx cirrus edb93xx edb9315a edb93xx:MK_edb9315a Sergey Kostanbaev <sergey.kostanbaev@fairwaves.ru>
-Active arm arm920t imx - - scb9328 - Torsten Koschorrek <koschorrek@synertronixx.de>
-Active arm arm920t ks8695 - - cm4008 - Greg Ungerer <greg.ungerer@opengear.com>
-Active arm arm920t ks8695 - - cm41xx - -
+Active arm arm920t imx - scb9328 scb9328 - Torsten Koschorrek <koschorrek@synertronixx.de>
+Active arm arm920t ks8695 - cm4008 cm4008 - Greg Ungerer <greg.ungerer@opengear.com>
+Active arm arm920t ks8695 - cm41xx cm41xx - -
Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Müller <d.mueller@elsoft.ch>
-Active arm arm920t s3c24x0 samsung - smdk2410 - David Müller <d.mueller@elsoft.ch>
+Active arm arm920t s3c24x0 samsung smdk2410 smdk2410 - David Müller <d.mueller@elsoft.ch>
Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij <linus.walleij@linaro.org>
Active arm arm926ejs - armltd integrator integratorcp_cm926ejs integratorcp:CM924EJ_S Linus Walleij <linus.walleij@linaro.org>
-Active arm arm926ejs armada100 Marvell
- aspenite - Prafulla Wadaskar <prafulla@marvell.com>
-Active arm arm926ejs armada100 Marvell
- gplugd - Ajay Bhargav <ajay.bhargav@einfochips.com>
-Active arm arm926ejs at91 - - afeb9260 - Sergey Lapin <slapin@ossfans.org>
+Active arm arm926ejs armada100 Marvell
aspenite aspenite - Prafulla Wadaskar <prafulla@marvell.com>
+Active arm arm926ejs armada100 Marvell
gplugd gplugd - Ajay Bhargav <ajay.bhargav@einfochips.com>
+Active arm arm926ejs at91 - afeb9260 afeb9260 - Sergey Lapin <slapin@ossfans.org>
Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs0 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs1 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net>
Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_nandflash at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_mmc at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_nandflash at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_spiflash at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH Bo Shen <voice.shen@atmel.com>
-Active arm arm926ejs at91 bluewater - snapper9260 snapper9260:AT91SAM9260 Ryan Mallon <ryan@bluewatersys.com>
+Active arm arm926ejs at91 bluewater snapper9260 snapper9260 snapper9260:AT91SAM9260 Ryan Mallon <ryan@bluewatersys.com>
Active arm arm926ejs at91 bluewater snapper9260 snapper9g20 snapper9260:AT91SAM9G20 Ryan Mallon <ryan@bluewatersys.com>
Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc - Jens Scharsig <esw@bus-elektronik.de>
Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc_ram vl_ma2sc:RAMLOAD Jens Scharsig <esw@bus-elektronik.de>
Active arm arm926ejs davinci omicron calimain calimain - Manfred Rudigier <manfred.rudigier@omicron.at>:Christian Riesch <christian.riesch@omicron.at>
Active arm arm926ejs kirkwood buffalo lsxl lschlv2 lsxl:LSCHLV2 Michael Walle <michael@walle.cc>
Active arm arm926ejs kirkwood buffalo lsxl lsxhl lsxl:LSXHL Michael Walle <michael@walle.cc>
-Active arm arm926ejs kirkwood cloudengines - pogo_e02 - Dave Purdy <david.c.purdy@gmail.com>
-Active arm arm926ejs kirkwood d-link - dns325 - Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
-Active arm arm926ejs kirkwood iomega - iconnect - Luka Perkov <luka@openwrt.org>
+Active arm arm926ejs kirkwood cloudengines pogo_e02 pogo_e02 - Dave Purdy <david.c.purdy@gmail.com>
+Active arm arm926ejs kirkwood d-link dns325 dns325 - Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
+Active arm arm926ejs kirkwood iomega iconnect iconnect - Luka Perkov <luka@openwrt.org>
Active arm arm926ejs kirkwood karo tk71 tk71 - -
Active arm arm926ejs kirkwood keymile km_arm km_kirkwood km_kirkwood:KM_KIRKWOOD Valentin Longchamp <valentin.longchamp@keymile.com>
Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_128m16 km_kirkwood:KM_KIRKWOOD_128M16 Valentin Longchamp <valentin.longchamp@keymile.com>
Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_mini_v2 lacie_kw:NETSPACE_MINI_V2 -
Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_v2 lacie_kw:NETSPACE_V2 Simon Guinot <simon.guinot@sequanux.org>
Active arm arm926ejs kirkwood LaCie wireless_space wireless_space - -
-Active arm arm926ejs kirkwood Marvell - dreamplug - Jason Cooper <u-boot@lakedaemon.net>
-Active arm arm926ejs kirkwood Marvell - guruplug - Siddarth Gore <gores@marvell.com>
-Active arm arm926ejs kirkwood Marvell - mv88f6281gtw_ge - Prafulla Wadaskar <prafulla@marvell.com>
-Active arm arm926ejs kirkwood Marvell - rd6281a - Prafulla Wadaskar <prafulla@marvell.com>
-Active arm arm926ejs kirkwood Marvell - sheevaplug - Prafulla Wadaskar <prafulla@marvell.com>
+Active arm arm926ejs kirkwood Marvell dreamplug dreamplug - Jason Cooper <u-boot@lakedaemon.net>
+Active arm arm926ejs kirkwood Marvell guruplug guruplug - Siddarth Gore <gores@marvell.com>
+Active arm arm926ejs kirkwood Marvell mv88f6281gtw_ge mv88f6281gtw_ge - Prafulla Wadaskar <prafulla@marvell.com>
Active arm arm926ejs kirkwood Marvell openrd openrd_base openrd:BOARD_IS_OPENRD_BASE Prafulla Wadaskar <prafulla@marvell.com>
Active arm arm926ejs kirkwood Marvell openrd openrd_client openrd:BOARD_IS_OPENRD_CLIENT -
Active arm arm926ejs kirkwood Marvell openrd openrd_ultimate openrd:BOARD_IS_OPENRD_ULTIMATE -
+Active arm arm926ejs kirkwood Marvell rd6281a rd6281a - Prafulla Wadaskar <prafulla@marvell.com>
+Active arm arm926ejs kirkwood Marvell sheevaplug sheevaplug - Prafulla Wadaskar <prafulla@marvell.com>
Active arm arm926ejs kirkwood raidsonic ib62x0 ib62x0 - Luka Perkov <luka@openwrt.org>
-Active arm arm926ejs kirkwood Seagate - dockstar - Eric Cooper <ecc@cmu.edu>
-Active arm arm926ejs kirkwood Seagate - goflexhome - Suriyan Ramasami <suriyan.r@gmail.com>
+Active arm arm926ejs kirkwood Seagate dockstar dockstar - Eric Cooper <ecc@cmu.edu>
+Active arm arm926ejs kirkwood Seagate goflexhome goflexhome - Suriyan Ramasami <suriyan.r@gmail.com>
Active arm arm926ejs lpc32xx timll devkit3250 devkit3250 - Vladimir Zapolskiy <vz@mleia.com>
Active arm arm926ejs mb86r0x syteco jadecpu jadecpu - Matthias Weisser <weisserm@arcor.de>
Active arm arm926ejs mx25 freescale mx25pdk mx25pdk mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com>
Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut <marek.vasut@gmail.com>
Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
Active arm arm926ejs nomadik st nhk8815 nhk8815_onenand nhk8815:BOOT_ONENAND Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
-Active arm arm926ejs omap ti - omap5912osk - Rishi Bhattacharya <rishi@ti.com>
-Active arm arm926ejs orion5x LaCie - edminiv2 - Albert ARIBAUD <albert.u.boot@aribaud.net>
-Active arm arm926ejs pantheon Marvell - dkb - Lei Wen <leiwen@marvell.com>
-Active arm arm926ejs spear spear - x600 - Stefan Roese <sr@denx.de>
+Active arm arm926ejs omap ti omap5912osk omap5912osk - Rishi Bhattacharya <rishi@ti.com>
+Active arm arm926ejs orion5x LaCie edminiv2 edminiv2 - Albert ARIBAUD <albert.u.boot@aribaud.net>
+Active arm arm926ejs pantheon Marvell dkb dkb - Lei Wen <leiwen@marvell.com>
Active arm arm926ejs spear spear spear300 spear300 spear3xx_evb:spear300 Vipin Kumar <vipin.kumar@st.com>
Active arm arm926ejs spear spear spear300 spear300_nand spear3xx_evb:spear300,nand -
Active arm arm926ejs spear spear spear300 spear300_usbtty spear3xx_evb:spear300,usbtty -
Active arm arm926ejs spear spear spear600 spear600_nand spear6xx_evb:spear600,nand -
Active arm arm926ejs spear spear spear600 spear600_usbtty spear6xx_evb:spear600,usbtty -
Active arm arm926ejs spear spear spear600 spear600_usbtty_nand spear6xx_evb:spear600,usbtty,nand -
+Active arm arm926ejs spear spear x600 x600 - Stefan Roese <sr@denx.de>
Active arm arm926ejs versatile armltd versatile versatileab versatile:ARCH_VERSATILE_AB -
Active arm arm926ejs versatile armltd versatile versatilepb versatile:ARCH_VERSATILE_PB -
Active arm arm926ejs versatile armltd versatile versatileqemu versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB -
Active arm armv7 omap3 ti sdp3430 omap3_sdp3430 - Nishanth Menon <nm@ti.com>
Active arm armv7 omap3 timll devkit8000 devkit8000 - Thomas Weber <weber@corscience.de>
Active arm armv7 omap4 gumstix duovero duovero - Ash Charles <ash@gumstix.com>
-Active arm armv7 omap4 ti panda omap4_panda - Sricharan R <r.sricharan@ti.com>
-Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R <r.sricharan@ti.com>
+Active arm armv7 omap4 ti panda omap4_panda - Lokesh Vutla <lokeshvutla@ti.com>
+Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 omap5 compulab cm_t54 cm_t54 - Dmitry Lifshitz <lifshitz@compulab.co.il>
Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 omap5 ti dra7xx dra7xx_evm_qspiboot dra7xx_evm:CONS_INDEX=1,QSPI_BOOT Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 omap5 ti dra7xx dra7xx_evm_uart3 dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT Lokesh Vutla <lokeshvutla@ti.com>
-Active arm armv7 omap5 ti omap5_uevm omap5_uevm - -
+Active arm armv7 omap5 ti omap5_uevm omap5_uevm - Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
+Active arm armv7 rmobile renesas alt alt - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 s5pc1xx samsung goni s5p_goni - Robert Baldyga <r.baldyga@samsung.com>
Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
-Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII -
-Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII -
+Active arm armv7 sunxi - sunxi A13-OLinuXinoM sun5i:A13_OLINUXINOM,SPL,CONS_INDEX=2 Hans de Goede <hdegoede@redhat.com>
+Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC Hans de Goede <hdegoede@redhat.com>
+Active arm armv7 sunxi - sunxi Cubieboard2 sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
+Active arm armv7 sunxi - sunxi Cubieboard2_FEL sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
+Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
+Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII Ian Campbell <ijc@hellion.org.uk>:Hans de Goede <hdegoede@redhat.com>
+Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL,AXP152_POWER Hans de Goede <hdegoede@redhat.com>
Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>
Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel <alban.bedel@avionic-design.de>
Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren <twarren@nvidia.com>
-Active arm pxa - - - balloon3 - Marek Vasut <marek.vasut@gmail.com>
-Active arm pxa - - - h2200 - Lukasz Dalek <luk0104@gmail.com>
-Active arm pxa - - - palmld - Marek Vasut <marek.vasut@gmail.com>
-Active arm pxa - - - palmtc - Marek Vasut <marek.vasut@gmail.com>
-Active arm pxa - - - pxa255_idp - Cliff Brake <cliff.brake@gmail.com>
-Active arm pxa - - - trizepsiv - Stefano Babic <sbabic@denx.de>
-Active arm pxa - - - xaeniax - -
-Active arm pxa - - - zipitz2 - Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - balloon3 balloon3 - Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - h2200 h2200 - Lukasz Dalek <luk0104@gmail.com>
+Active arm pxa - - palmld palmld - Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - palmtc palmtc - Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - pxa255_idp pxa255_idp - Cliff Brake <cliff.brake@gmail.com>
Active arm pxa - - trizepsiv polaris trizepsiv:POLARIS Stefano Babic <sbabic@denx.de>
+Active arm pxa - - trizepsiv trizepsiv - Stefano Babic <sbabic@denx.de>
Active arm pxa - - vpac270 vpac270_nor_128 vpac270:NOR,RAM_128M Marek Vasut <marek.vasut@gmail.com>
Active arm pxa - - vpac270 vpac270_nor_256 vpac270:NOR,RAM_256M Marek Vasut <marek.vasut@gmail.com>
Active arm pxa - - vpac270 vpac270_ond_256 vpac270:ONENAND,RAM_256M Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - xaeniax xaeniax - -
+Active arm pxa - - zipitz2 zipitz2 - Marek Vasut <marek.vasut@gmail.com>
Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich <ynvich@gmail.com>
-Active arm pxa - toradex - colibri_pxa270 - Marek Vasut <marek.vasut@gmail.com>
-Active arm sa1100 - - - jornada - Kristoffer Ericson <kristoffer.ericson@gmail.com>
-Active avr32
at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann <andreas.devel@googlemail.com>
-Active avr32
at32ap at32ap700x in-circuit - grasshopper - Andreas Bießmann <andreas.devel@googlemail.com>
-Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson <mpfj@mimc.co.uk>
-Active avr32
at32ap at32ap700x miromico - hammerhead - Alex Raimondi <alex.raimondi@miromico.ch>
-Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald <devel@bct-electronic.com>
-Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf525-ucr2 - Haitao Zhang <hzhang@ucrobotics.com>:Chong Huang <chuang@ucrobotics.com>
-Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf527-sdp - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf533-stamp - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf537-minotaur - Martin Strubel <strubel@section5.ch>
-Active blackfin blackfin - - - bf537-pnav - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf537-srv1 - Martin Strubel <strubel@section5.ch>
-Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf561-acvilon - Valentin Yakovenkov <yakovenkov@niistt.ru>
-Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - blackstamp - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
-Active blackfin blackfin - - - blackvme - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
-Active blackfin blackfin - - - br4 - Dimitar Penev <dpn@switchfin.org>
-Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) <info@ssv-embedded.de>
-Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule <support@i-syst.com>
-Active blackfin blackfin - - - pr1 - Dimitar Penev <dpn@switchfin.org>
-Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi@gmail.com>
+Active arm pxa - toradex colibri_pxa270 colibri_pxa270 - Marek Vasut <marek.vasut@gmail.com>
+Active arm sa1100 - - jornada jornada - Kristoffer Ericson <kristoffer.ericson@gmail.com>
+Active avr32
- at32ap700x atmel atngw100mkii atngw100mkii - Andreas Bießmann <andreas.devel@googlemail.com>
+Active avr32
- at32ap700x in-circuit grasshopper grasshopper - Andreas Bießmann <andreas.devel@googlemail.com>
+Active avr32 - at32ap700x mimc mimc200 mimc200 - Mark Jackson <mpfj@mimc.co.uk>
+Active avr32
- at32ap700x miromico hammerhead hammerhead - Alex Raimondi <alex.raimondi@miromico.ch>
+Active blackfin - - - bct-brettl2 bct-brettl2 - Peter Meerwald <devel@bct-electronic.com>
+Active blackfin - - - bf506f-ezkit bf506f-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin - - - bf518f-ezbrd bf518f-ezbrd - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin - - - bf525-ucr2 bf525-ucr2 - Haitao Zhang <hzhang@ucrobotics.com>:Chong Huang <chuang@ucrobotics.com>
+Active blackfin - - - bf526-ezbrd bf526-ezbrd - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin - - - bf527-ad7160-eval bf527-ad7160-eval - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin - - - bf527-ezkit bf527-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin - - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin - - - bf527-sdp bf527-sdp - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin - - - bf533-ezkit bf533-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin - - - bf533-stamp bf533-stamp - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin - - - bf537-minotaur bf537-minotaur - Martin Strubel <strubel@section5.ch>
+Active blackfin - - - bf537-pnav bf537-pnav - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin - - - bf537-srv1 bf537-srv1 - Martin Strubel <strubel@section5.ch>
+Active blackfin - - - bf537-stamp bf537-stamp - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin - - - bf538f-ezkit bf538f-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin - - - bf548-ezkit bf548-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin - - - bf561-acvilon bf561-acvilon - Valentin Yakovenkov <yakovenkov@niistt.ru>
+Active blackfin - - - bf561-ezkit bf561-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin - - - bf609-ezkit bf609-ezkit - Sonic Zhang <sonic.adi@gmail.com>
+Active blackfin - - - blackstamp blackstamp - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
+Active blackfin - - - blackvme blackvme - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
+Active blackfin - - - br4 br4 - Dimitar Penev <dpn@switchfin.org>
+Active blackfin - - - dnp5370 dnp5370 - M.Hasewinkel (MHA) <info@ssv-embedded.de>
+Active blackfin - - - ibf-dsp561 ibf-dsp561 - I-SYST Micromodule <support@i-syst.com>
+Active blackfin - - - pr1 pr1 - Dimitar Penev <dpn@switchfin.org>
Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active m68k mcf547x_8x - freescale m548xevb M5485FFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active m68k mcf547x_8x - freescale m548xevb M5485GFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active m68k mcf547x_8x - freescale m548xevb M5485HFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek <monstr@monstr.eu>
+Active microblaze - - xilinx microblaze-generic microblaze-generic - Michal Simek <monstr@monstr.eu>
Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu <vlad.lungu@windriver.com>
Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN -
Active mips mips32 - imgtec malta malta malta:SYS_BIG_ENDIAN Paul Burton <paul.burton@imgtec.com>
Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
Active nds32 n1213 ag101 AndesTech adp-ag101p adp-ag101p - Andes <uboot@andestech.com>
Active nds32 n1213 ag102 AndesTech adp-ag102 adp-ag102 - Andes <uboot@andestech.com>
-Active nios2 nios2 - altera nios2-generic nios2-generic - Scott McNutt <smcnutt@psyent.com>
-Active nios2 nios2 - psyent pci5441 PCI5441 - Scott McNutt <smcnutt@psyent.com>
-Active nios2 nios2 - psyent pk1c20 PK1C20 - Scott McNutt <smcnutt@psyent.com>
-Active openrisc or1200 - openrisc openrisc-generic openrisc-generic - Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
-Active powerpc 74xx_7xx - - - ppmc7xx - -
+Active nios2 - - altera nios2-generic nios2-generic - Scott McNutt <smcnutt@psyent.com>
+Active nios2 - - psyent pci5441 PCI5441 - Scott McNutt <smcnutt@psyent.com>
+Active nios2 - - psyent pk1c20 PK1C20 - Scott McNutt <smcnutt@psyent.com>
+Active openrisc - - openrisc openrisc-generic openrisc-generic - Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Active powerpc 74xx_7xx - - evb64260 P3G4 - Wolfgang Denk <wd@denx.de>
+Active powerpc 74xx_7xx - - ppmc7xx ppmc7xx - -
Active powerpc 74xx_7xx - eltec elppc ELPPC - -
Active powerpc 74xx_7xx - esd cpci750 CPCI750 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Active powerpc 74xx_7xx - freescale mpc7448hpc2 mpc7448hpc2 - Roy Zang <tie-fei.zang@freescale.com>
Active powerpc 74xx_7xx - Marvell db64460 DB64460 - -
Active powerpc 74xx_7xx - prodrive p3mx p3m7448 p3mx:P3M7448 Stefan Roese <sr@denx.de>
Active powerpc 74xx_7xx - prodrive p3mx p3m750 p3mx:P3M750 Stefan Roese <sr@denx.de>
-Active powerpc mpc512x - - - pdm360ng - Michael Weiss <michael.weiss@ifm.com>
-Active powerpc mpc512x - davedenx - aria - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc512x - esd - mecp5123 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc512x - - pdm360ng pdm360ng - Michael Weiss <michael.weiss@ifm.com>
+Active powerpc mpc512x - davedenx aria aria - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc512x - esd mecp5123 mecp5123 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Active powerpc mpc512x - freescale mpc5121ads mpc5121ads - -
Active powerpc mpc512x - freescale mpc5121ads mpc5121ads_rev2 mpc5121ads:MPC5121ADS_REV2 -
Active powerpc mpc512x - ifm ac14xx ac14xx - Anatolij Gustschin <agust@denx.de>
Active powerpc mpc5xx - - cmi cmi_mpc5xx - -
Active powerpc mpc5xx - mpl pati PATI - -
-Active powerpc mpc5xxx - - - canmb - -
-Active powerpc mpc5xxx - - - cm5200 - -
-Active powerpc mpc5xxx - - - inka4x0 - Detlev Zundel <dzu@denx.de>
-Active powerpc mpc5xxx - - - ipek01 - Wolfgang Grandegger <wg@denx.de>
-Active powerpc mpc5xxx - - - jupiter - Heiko Schocher <hs@denx.de>
-Active powerpc mpc5xxx - - - motionpro - -
-Active powerpc mpc5xxx - - - munices - -
-Active powerpc mpc5xxx - - - v38b - -
Active powerpc mpc5xxx - - a3m071 a3m071 - Stefan Roese <sr@denx.de>
Active powerpc mpc5xxx - - a3m071 a4m2k a3m071:A4M2K Stefan Roese <sr@denx.de>
Active powerpc mpc5xxx - - a4m072 a4m072 - Sergei Poselenov <sposelenov@emcraft.com>
Active powerpc mpc5xxx - - bc3450 BC3450 - -
+Active powerpc mpc5xxx - - canmb canmb - -
+Active powerpc mpc5xxx - - cm5200 cm5200 - -
Active powerpc mpc5xxx - - icecube icecube_5200 IceCube Wolfgang Denk <wd@denx.de>
Active powerpc mpc5xxx - - icecube icecube_5200_DDR IceCube:MPC5200_DDR -
Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR -
Active powerpc mpc5xxx - - icecube lite5200b IceCube:MPC5200_DDR,LITE5200B -
Active powerpc mpc5xxx - - icecube lite5200b_LOWBOOT IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000 -
Active powerpc mpc5xxx - - icecube lite5200b_PM IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM -
+Active powerpc mpc5xxx - - inka4x0 inka4x0 - Detlev Zundel <dzu@denx.de>
+Active powerpc mpc5xxx - - ipek01 ipek01 - Wolfgang Grandegger <wg@denx.de>
+Active powerpc mpc5xxx - - jupiter jupiter - Heiko Schocher <hs@denx.de>
Active powerpc mpc5xxx - - mcc200 mcc200 - -
Active powerpc mpc5xxx - - mcc200 mcc200_COM12 mcc200:CONSOLE_COM12 -
Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000 -
Active powerpc mpc5xxx - - mcc200 prs200_DDR mcc200:PRS200 -
Active powerpc mpc5xxx - - mcc200 prs200_highboot mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
Active powerpc mpc5xxx - - mcc200 prs200_highboot_DDR mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000 -
+Active powerpc mpc5xxx - - motionpro motionpro - -
+Active powerpc mpc5xxx - - munices munices - -
Active powerpc mpc5xxx - - pm520 PM520 - Josef Wagner <Wagner@Microsys.de>
Active powerpc mpc5xxx - - pm520 PM520_DDR PM520:MPC5200_DDR Josef Wagner <Wagner@Microsys.de>
Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT PM520:BOOT_ROM Josef Wagner <Wagner@Microsys.de>
Active powerpc mpc5xxx - - total5200 Total5200_lowboot Total5200:TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000 -
Active powerpc mpc5xxx - - total5200 Total5200_Rev2 Total5200:TOTAL5200_REV=2 -
Active powerpc mpc5xxx - - total5200 Total5200_Rev2_lowboot Total5200:TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000 -
+Active powerpc mpc5xxx - - v38b v38b - -
Active powerpc mpc5xxx - emk top5200 EVAL5200 TOP5200:EVAL5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
Active powerpc mpc5xxx - emk top5200 MINI5200 TOP5200:MINI5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
Active powerpc mpc5xxx - emk top5200 TOP5200 TOP5200:TOP5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-Active powerpc mpc5xxx - esd - cpci5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-Active powerpc mpc5xxx - esd - mecp5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-Active powerpc mpc5xxx - esd - pf5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc5xxx - esd cpci5200 cpci5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc5xxx - esd mecp5200 mecp5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc5xxx - esd pf5200 pf5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Active powerpc mpc5xxx - ifm o2dnt2 O2D o2d Anatolij Gustschin <agust@denx.de>
Active powerpc mpc5xxx - ifm o2dnt2 O2D300 o2d300 Anatolij Gustschin <agust@denx.de>
Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2 o2dnt2 Anatolij Gustschin <agust@denx.de>
Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000 Werner Pfister <Pfister_Werner@intercontrol.de>
Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5 digsy_mtc:DIGSY_REV5 Werner Pfister <Pfister_Werner@intercontrol.de>
Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5 Werner Pfister <Pfister_Werner@intercontrol.de>
-Active powerpc mpc5xxx - manroland - hmi1001 - -
-Active powerpc mpc5xxx - manroland - mucmc52 - Heiko Schocher <hs@denx.de>
-Active powerpc mpc5xxx - manroland - uc101 - Heiko Schocher <hs@denx.de>
+Active powerpc mpc5xxx - manroland hmi1001 hmi1001 - -
+Active powerpc mpc5xxx - manroland mucmc52 mucmc52 - Heiko Schocher <hs@denx.de>
+Active powerpc mpc5xxx - manroland uc101 uc101 - Heiko Schocher <hs@denx.de>
Active powerpc mpc5xxx - phytec pcm030 pcm030 - Jon Smirl <jonsmirl@gmail.com>
Active powerpc mpc5xxx - phytec pcm030 pcm030_LOWBOOT pcm030:SYS_TEXT_BASE=0xFF000000 Jon Smirl <jonsmirl@gmail.com>
Active powerpc mpc5xxx - tqc tqm5200 aev - -
Active powerpc mpc5xxx - tqc tqm5200 TQM5200_STK100 TQM5200:STK52XX_REV100 -
Active powerpc mpc5xxx - tqc tqm5200 TQM5200S TQM5200:TQM5200_B,TQM5200S -
Active powerpc mpc5xxx - tqc tqm5200 TQM5200S_HIGHBOOT TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000 -
-Active powerpc mpc824x - - - utx8245 - Greg Allen <gallen@arlut.utexas.edu>
Active powerpc mpc824x - - a3000 A3000 - -
Active powerpc mpc824x - - cpc45 CPC45 - Josef Wagner <Wagner@Microsys.de>
Active powerpc mpc824x - - cpc45 CPC45_ROMBOOT CPC45:BOOT_ROM Josef Wagner <Wagner@Microsys.de>
Active powerpc mpc824x - - eXalion eXalion - Torsten Demke <torsten.demke@fci.com>
Active powerpc mpc824x - - mvblue MVBLUE - -
Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - - atc - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - - ep82xxm - -
-Active powerpc mpc8260 - - - gw8260 - Oliver Brown <obrown@adventnetworks.com>
-Active powerpc mpc8260 - - - hymod - Murray Jensen <Murray.Jensen@csiro.au>
+Active powerpc mpc824x - - utx8245 utx8245 - Greg Allen <gallen@arlut.utexas.edu>
+Active powerpc mpc8260 - - atc atc - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - cogent cogent_mpc8260 - Murray Jensen <Murray.Jensen@csiro.au>
Active powerpc mpc8260 - - cpu86 CPU86 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - cpu87 CPU87 - -
Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM -
+Active powerpc mpc8260 - - ep82xxm ep82xxm - -
+Active powerpc mpc8260 - - gw8260 gw8260 - Oliver Brown <obrown@adventnetworks.com>
+Active powerpc mpc8260 - - hymod hymod - Murray Jensen <Murray.Jensen@csiro.au>
Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg@denx.de>
Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs@denx.de>
Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs@denx.de>
Active powerpc mpc8260 - tqc tqm8260 TQM8260_AI TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - tqc tqm8260 TQM8265_AA TQM8260:MPC8265,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - tqc tqm8272 TQM8272 - -
-Active powerpc mpc83xx - - - mpc8308_p1m - Ilya Yanok <yanok@emcraft.com>
+Active powerpc mpc83xx - - mpc8308_p1m mpc8308_p1m - Ilya Yanok <yanok@emcraft.com>
Active powerpc mpc83xx - - sbc8349 sbc8349 - Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_33 sbc8349:PCI,PCI_33M Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_66 sbc8349:PCI,PCI_66M Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - keymile kmp204x kmcoge4 kmp204x:KMCOGE4 Valentin Longchamp <valentin.longchamp@keymile.com>
Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp <valentin.longchamp@keymile.com>
-Active powerpc mpc85xx - xes - xpedite520x - -
-Active powerpc mpc85xx - xes - xpedite537x - -
-Active powerpc mpc85xx - xes - xpedite550x - -
-Active powerpc mpc86xx - -
- sbc8641d - Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc85xx - xes xpedite520x xpedite520x - -
+Active powerpc mpc85xx - xes xpedite537x xpedite537x - -
+Active powerpc mpc85xx - xes xpedite550x xpedite550x - -
+Active powerpc mpc86xx - -
sbc8641d sbc8641d - Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc86xx - freescale mpc8610hpcd MPC8610HPCD - -
-Active powerpc mpc86xx - xes - xpedite517x - -
-Active powerpc mpc8xx - - - hermes - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - - lwmon - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - - quantum - -
-Active powerpc mpc8xx - - - RRvision - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - - spc1920 - -
-Active powerpc mpc8xx - - - v37 - -
+Active powerpc mpc86xx - xes xpedite517x xpedite517x - -
Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen@csiro.au>
Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark@esteem.com>
-Active powerpc mpc8xx - - fads MPC86xADS - -
-Active powerpc mpc8xx - - fads MPC885ADS - -
+Active powerpc mpc8xx - - hermes hermes - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - icu862 ICU862 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - icu862 ICU862_100MHz ICU862:100MHz Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - ip860 IP860 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - ivm IVMS8 IVMS8:IVMS8_16M Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - ivm IVMS8_128 IVMS8:IVMS8_32M Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - ivm IVMS8_256 IVMS8:IVMS8_64M Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - netphone NETPHONE NETPHONE:NETPHONE_VERSION=1 -
-Active powerpc mpc8xx - - netphone NETPHONE_V2 NETPHONE:NETPHONE_VERSION=2 -
-Active powerpc mpc8xx - - netta NETTA - -
-Active powerpc mpc8xx - - netta NETTA_6412 NETTA:NETTA_6412=1 -
-Active powerpc mpc8xx - - netta NETTA_6412_SWAPHOOK NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1 -
-Active powerpc mpc8xx - - netta NETTA_ISDN NETTA:NETTA_ISDN=1 -
-Active powerpc mpc8xx - - netta NETTA_ISDN_6412 NETTA:NETTA_ISDN=1,NETTA_6412=1 -
-Active powerpc mpc8xx - - netta NETTA_ISDN_6412_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_6412=1,NETTA_SWAPHOOK=1 -
-Active powerpc mpc8xx - - netta NETTA_ISDN_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_SWAPHOOK=1 -
-Active powerpc mpc8xx - - netta NETTA_SWAPHOOK NETTA:NETTA_SWAPHOOK=1 -
-Active powerpc mpc8xx - - netta2 NETTA2 NETTA2:NETTA2_VERSION=1 -
-Active powerpc mpc8xx - - netta2 NETTA2_V2 NETTA2:NETTA2_VERSION=2 -
+Active powerpc mpc8xx - - lwmon lwmon - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - netvia NETVIA NETVIA:NETVIA_VERSION=1 Pantelis Antoniou <panto@intracom.gr>
Active powerpc mpc8xx - - netvia NETVIA_V2 NETVIA:NETVIA_VERSION=2 Pantelis Antoniou <panto@intracom.gr>
Active powerpc mpc8xx - - r360mpi R360MPI - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - rbc823 RBC823 - -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW - -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64 RPXlite_DW:RPXlite_64MHz -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20 -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_LCD RPXlite_DW:LCD,NEC_NL6448BC20 -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM RPXlite_DW:ENV_IS_IN_NVRAM -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64 RPXlite_DW:RPXlite_64MHz,ENV_IS_IN_NVRAM -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -
-Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_LCD RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -
+Active powerpc mpc8xx - - RRvision RRvision - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - RRvision RRvision_LCD RRvision:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - spd8xx SPD823TS - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - eltec mhpc MHPC - Frank Gottschling <fgottschling@eltec.de>
Active powerpc mpc8xx - kup kup4k KUP4K - Klaus Heydeck <heydeck@kieback-peter.de>
Active powerpc mpc8xx - kup kup4x KUP4X - Klaus Heydeck <heydeck@kieback-peter.de>
Active powerpc mpc8xx - LEOX elpt860 ELPT860 - The LEOX team <team@leox.org>
-Active powerpc mpc8xx - manroland - uc100 - Stefan Roese <sr@denx.de>
-Active powerpc mpc8xx - snmc qs850 QS823 - -
-Active powerpc mpc8xx - snmc qs850 QS850 - -
-Active powerpc mpc8xx - snmc qs860t QS860T - -
+Active powerpc mpc8xx - manroland uc100 uc100 - Stefan Roese <sr@denx.de>
Active powerpc mpc8xx - tqc tqm8xx FPS850L - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - tqc tqm8xx FPS860L - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - tqc tqm8xx NSCU - -
Active powerpc mpc8xx - tqc tqm8xx TK885D - -
Active powerpc mpc8xx - tqc tqm8xx TQM823L - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - tqc tqm8xx TQM823L_LCD TQM823L:LCD,NEC_NL6448BC20 Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - tqc tqm8xx TQM823M - -
+Active powerpc mpc8xx - tqc tqm8xx TQM823M - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - tqc tqm8xx TQM850L - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - tqc tqm8xx TQM850M - -
+Active powerpc mpc8xx - tqc tqm8xx TQM850M - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - tqc tqm8xx TQM855L - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - tqc tqm8xx TQM855M - -
+Active powerpc mpc8xx - tqc tqm8xx TQM855M - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - tqc tqm8xx TQM860L - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - tqc tqm8xx TQM860M - -
-Active powerpc mpc8xx - tqc tqm8xx TQM862L - -
-Active powerpc mpc8xx - tqc tqm8xx TQM862M - -
-Active powerpc mpc8xx - tqc tqm8xx TQM866M - -
-Active powerpc mpc8xx - tqc tqm8xx TQM885D - -
+Active powerpc mpc8xx - tqc tqm8xx TQM860M - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx TQM862L - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx TQM862M - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx TQM866M - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx TQM885D - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - tqc tqm8xx TTTech TQM823L:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - tqc tqm8xx virtlab2 - -
+Active powerpc mpc8xx - tqc tqm8xx virtlab2 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - tqc tqm8xx wtk TQM823L:LCD,SHARP_LQ065T9DR51U Wolfgang Denk <wd@denx.de>
-Active powerpc ppc4xx - - - csb272 - Tolunay Orkun <torkun@nextio.com>
-Active powerpc ppc4xx - - - csb472 - Tolunay Orkun <torkun@nextio.com>
-Active powerpc ppc4xx - - - korat - Larry Johnson <lrj@acm.org>
-Active powerpc ppc4xx - - - lwmon5 - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - - - pcs440ep - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - - - sbc405 - -
-Active powerpc ppc4xx - - - sc3 - Heiko Schocher <hs@denx.de>
-Active powerpc ppc4xx - - - t3corp - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - - - zeus - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - - csb272 csb272 - Tolunay Orkun <torkun@nextio.com>
+Active powerpc ppc4xx - - csb472 csb472 - Tolunay Orkun <torkun@nextio.com>
Active powerpc ppc4xx - - g2000 G2000 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Active powerpc ppc4xx - - jse JSE - Stephen Williams <steve@icarus.com>
+Active powerpc ppc4xx - - korat korat - Larry Johnson <lrj@acm.org>
Active powerpc ppc4xx - - korat korat_perm korat:KORAT_PERMANENT Larry Johnson <lrj@acm.org>
Active powerpc ppc4xx - - lwmon5 lcd4_lwmon5 lwmon5:LCD4_LWMON5 Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - - lwmon5 lwmon5 - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - - pcs440ep pcs440ep - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - - sbc405 sbc405 - -
+Active powerpc ppc4xx - - sc3 sc3 - Heiko Schocher <hs@denx.de>
+Active powerpc ppc4xx - - t3corp t3corp - Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - - w7o W7OLMC - Erik Theisen <etheisen@mindspring.com>
Active powerpc ppc4xx - - w7o W7OLMG - Erik Theisen <etheisen@mindspring.com>
-Active powerpc ppc4xx - amcc - acadia - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc - bamboo - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc - bubinga - -
-Active powerpc ppc4xx - amcc - ebony - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc - katmai - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc - luan - John Otken <jotken@softadvances.com>
-Active powerpc ppc4xx - amcc - makalu - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc - ocotea - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc - redwood - Feng Kan <fkan@amcc.com>
-Active powerpc ppc4xx - amcc - taihu - John Otken <jotken@softadvances.com>
-Active powerpc ppc4xx - amcc - taishan - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - amcc - yucca - -
+Active powerpc ppc4xx - - zeus zeus - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc acadia acadia - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc bamboo bamboo - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc bubinga bubinga - -
Active powerpc ppc4xx - amcc canyonlands arches canyonlands:ARCHES Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands canyonlands canyonlands:CANYONLANDS Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc canyonlands glacier canyonlands:GLACIER Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc ebony ebony - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc katmai katmai - Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc kilauea haleakala kilauea:HALEAKALA Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc kilauea kilauea kilauea:KILAUEA Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc luan luan - John Otken <jotken@softadvances.com>
+Active powerpc ppc4xx - amcc makalu makalu - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc ocotea ocotea - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc redwood redwood - Feng Kan <fkan@amcc.com>
Active powerpc ppc4xx - amcc sequoia rainier sequoia:RAINIER Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia rainier_ramboot sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia sequoia sequoia:SEQUOIA Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc sequoia sequoia_ramboot sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc taihu taihu - John Otken <jotken@softadvances.com>
+Active powerpc ppc4xx - amcc taishan taishan - Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc walnut sycamore walnut Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc walnut walnut - Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc yosemite yellowstone yosemite:YELLOWSTONE Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - amcc yosemite yosemite yosemite:YOSEMITE Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc yucca yucca - -
Active powerpc ppc4xx - avnet fx12mm fx12mm fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de>
Active powerpc ppc4xx - avnet fx12mm fx12mm_flash fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de>
Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
Active powerpc ppc4xx - esd voh405 VOH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Active powerpc ppc4xx - esd vom405 VOM405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Active powerpc ppc4xx - esd wuh405 WUH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-Active powerpc ppc4xx - gdsys - dlvision - Dirk Eibach <eibach@gdsys.de>
-Active powerpc ppc4xx - gdsys - gdppc440etx - Dirk Eibach <eibach@gdsys.de>
Active powerpc ppc4xx - gdsys 405ep dlvision-10g - Dirk Eibach <eibach@gdsys.de>
Active powerpc ppc4xx - gdsys 405ep io - Dirk Eibach <eibach@gdsys.de>
Active powerpc ppc4xx - gdsys 405ep iocon - Dirk Eibach <eibach@gdsys.de>
Active powerpc ppc4xx - gdsys 405ep neo - Dirk Eibach <eibach@gdsys.de>
Active powerpc ppc4xx - gdsys 405ex io64 - Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys dlvision dlvision - Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys gdppc440etx gdppc440etx - Dirk Eibach <eibach@gdsys.de>
Active powerpc ppc4xx - gdsys intip devconcenter intip:DEVCONCENTER Dirk Eibach <eibach@gdsys.de>
Active powerpc ppc4xx - gdsys intip intip intip:INTIB Dirk Eibach <eibach@gdsys.de>
-Active powerpc ppc4xx - mosaixtech - icon - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - mosaixtech icon icon - Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - mpl mip405 MIP405 - Denis Peter <d.peter@mpl.ch>
Active powerpc ppc4xx - mpl mip405 MIP405T MIP405:MIP405T Denis Peter <d.peter@mpl.ch>
Active powerpc ppc4xx - mpl pip405 PIP405 - Denis Peter <d.peter@mpl.ch>
-Active powerpc ppc4xx - prodrive - alpr - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - prodrive - p3p440 - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - xes
- xpedite1000 - Peter Tyser <ptyser@xes-inc.com>
+Active powerpc ppc4xx - prodrive alpr alpr - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - prodrive p3p440 p3p440 - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - xes
xpedite1000 xpedite1000 - Peter Tyser <ptyser@xes-inc.com>
Active powerpc ppc4xx - xilinx ml507 ml507 ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
Active powerpc ppc4xx - xilinx ml507 ml507_flash ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000 Ricardo Ribalda <ricardo.ribalda@uam.es>
Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic_flash xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1 Ricardo Ribalda <ricardo.ribalda@uam.es>
Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic_flash xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
-Active sandbox sandbox - - sandbox sandbox - Simon Glass <sjg@chromium.org>
+Active sandbox - - - sandbox sandbox - Simon Glass <sjg@chromium.org>
Active sh sh2 - renesas rsk7203 rsk7203 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Active sh sh2 - renesas rsk7264 rsk7264 - Phil Edworthy <phil.edworthy@renesas.com>
Active sh sh2 - renesas rsk7269 rsk7269 - -
Active sh sh4 - renesas sh7763rdp sh7763rdp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Active sh sh4 - renesas sh7785lcr sh7785lcr - -
Active sh sh4 - renesas sh7785lcr sh7785lcr_32bit sh7785lcr:SH_32BIT=1 -
-Active sparc leon2 - gaisler - grsim_leon2 - -
-Active sparc leon3 - gaisler - gr_cpci_ax2000 - -
-Active sparc leon3 - gaisler - gr_ep2s60 - -
-Active sparc leon3 - gaisler - gr_xc3s_1500 - -
-Active sparc leon3 - gaisler - grsim - -
-Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 Simon Glass <sjg@chromium.org>
+Active sparc leon2 - gaisler grsim_leon2 grsim_leon2 - -
+Active sparc leon3 - gaisler gr_cpci_ax2000 gr_cpci_ax2000 - -
+Active sparc leon3 - gaisler gr_ep2s60 gr_ep2s60 - -
+Active sparc leon3 - gaisler gr_xc3s_1500 gr_xc3s_1500 - -
+Active sparc leon3 - gaisler grsim grsim - -
+Active x86 - coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 Simon Glass <sjg@chromium.org>
# The following were moved to "Orphan" in June, 2014
Orphan arm arm1176 tnetv107x ti tnetv107xevm tnetv107x_evm - Chan-Taek Park <c-park@ti.com>
Orphan arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_eeprom sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
Orphan arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
Orphan arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
Orphan arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre@adeneo-embedded.com>
-Orphan arm pxa - - - palmtreo680 - Mike Dunn <mikedunn@newsguy.com>
-Orphan avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Orphan avr32 at32ap at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
-Orphan blackfin blackfin - - - ip04 - Brent Kandetzki <brentk@teleco.com>
+Orphan arm pxa - - palmtreo680 palmtreo680 - Mike Dunn <mikedunn@newsguy.com>
+Orphan avr32 - at32ap700x atmel atngw100 atngw100 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Orphan avr32 - at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Orphan avr32 - at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Orphan avr32 - at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Orphan avr32 - at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Orphan avr32 - at32ap700x earthlcd favr-32-ezkit favr-32-ezkit - Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
+Orphan blackfin - - - ip04 ip04 - Brent Kandetzki <brentk@teleco.com>
Orphan m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser@freescale.com>
Orphan powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt <emillbrandt@dekaresearch.com>
Orphan powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt <emillbrandt@dekaresearch.com>
-Orphan powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno@delphintech.com>
-Orphan powerpc mpc8260 - - - sacsng - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
+Orphan powerpc mpc8260 - - ep8260 ep8260 - Frank Panno <fpanno@delphintech.com>
+Orphan powerpc mpc8260 - - sacsng sacsng - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
Orphan powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com>
Orphan powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com>
Orphan powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala <kumar.gala@freescale.com>
Orphan powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek <dan@embeddedalley.com>
Orphan powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN - Kumar Gala <kumar.gala@freescale.com>
Orphan powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala <kumar.gala@freescale.com>
-Orphan powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz@sinovee.com>
Orphan powerpc mpc8xx - - flagadm FLAGADM - Kári Davíðsson <kd@flaga.is>
Orphan powerpc mpc8xx - - gen860t GEN860T - Keith Outwater <Keith_Outwater@mvis.com>
Orphan powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater <Keith_Outwater@mvis.com>
Orphan powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis <DGE@sixnetio.com>
+Orphan powerpc mpc8xx - - svm_sc8xx svm_sc8xx - John Zhan <zhanz@sinovee.com>
Orphan powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek <dan@embeddedalley.com>
# The following were moved to "Orphan" in April, 2014
Orphan powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu <nyet@zumanetworks.com>
Orphan powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com>
Orphan powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim@musenki.com>
-Orphan powerpc mpc8260 - - - ppmc8260 - Brad Kemp <Brad.Kemp@seranoa.com>
+Orphan powerpc mpc8260 - - ppmc8260 ppmc8260 - Brad Kemp <Brad.Kemp@seranoa.com>
# The following were moved to "Orphan" in March, 2014
-Orphan blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Orphan blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Orphan blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Orphan blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Orphan blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Orphan blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Orphan blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-Orphan blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin - - - cm-bf527 cm-bf527 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin - - - cm-bf533 cm-bf533 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin - - - cm-bf537e cm-bf537e - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin - - - cm-bf537u cm-bf537u - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin - - - cm-bf548 cm-bf548 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin - - - cm-bf561 cm-bf561 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin - - - tcm-bf518 tcm-bf518 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Orphan blackfin - - - tcm-bf537 tcm-bf537 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
Orphan powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz <andre.schwarz@matrix-vision.de>
Orphan powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz <andre.schwarz@matrix-vision.de>
Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov <avorontsov@ru.mvista.com>
Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov@ru.mvista.com>
Orphan powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz <andre.schwarz@matrix-vision.de>
Orphan powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz <andre.schwarz@matrix-vision.de>
-Orphan powerpc ppc4xx - amcc - bluestone - Tirumala Marri <tmarri@apm.com>
+Orphan powerpc ppc4xx - amcc bluestone bluestone - Tirumala Marri <tmarri@apm.com>
Orphan powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff <dave@cray.com>
Orphan powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer <travis.sawyer@sandburst.com>
Orphan powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer <travis.sawyer@sandburst.com>
# The following were move to "Orphan" in September, 2013
Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
-Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+Orphan arm arm1136 mx31 freescale mx31ads mx31ads - (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
*/
#include <common.h>
+#include <autoboot.h>
#include <bootretry.h>
#include <cli.h>
#include <fdtdec.h>
#include <linux/compiler.h>
#include <version.h>
#include <environment.h>
+#include <dm.h>
#include <fdtdec.h>
#include <fs.h>
#if defined(CONFIG_CMD_IDE)
#include <os.h>
#include <post.h>
#include <spi.h>
+#include <status_led.h>
#include <trace.h>
#include <watchdog.h>
#include <asm/errno.h>
#ifdef CONFIG_SANDBOX
#include <asm/state.h>
#endif
+#include <dm/root.h>
#include <linux/compiler.h>
/*
************************************************************************
* May be supplied by boards if desired
*/
-inline void __coloured_LED_init(void) {}
-void coloured_LED_init(void)
- __attribute__((weak, alias("__coloured_LED_init")));
-inline void __red_led_on(void) {}
-void red_led_on(void) __attribute__((weak, alias("__red_led_on")));
-inline void __red_led_off(void) {}
-void red_led_off(void) __attribute__((weak, alias("__red_led_off")));
-inline void __green_led_on(void) {}
-void green_led_on(void) __attribute__((weak, alias("__green_led_on")));
-inline void __green_led_off(void) {}
-void green_led_off(void) __attribute__((weak, alias("__green_led_off")));
-inline void __yellow_led_on(void) {}
-void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on")));
-inline void __yellow_led_off(void) {}
-void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off")));
-inline void __blue_led_on(void) {}
-void blue_led_on(void) __attribute__((weak, alias("__blue_led_on")));
-inline void __blue_led_off(void) {}
-void blue_led_off(void) __attribute__((weak, alias("__blue_led_off")));
+__weak void coloured_LED_init(void) {}
+__weak void red_led_on(void) {}
+__weak void red_led_off(void) {}
+__weak void green_led_on(void) {}
+__weak void green_led_off(void) {}
+__weak void yellow_led_on(void) {}
+__weak void yellow_led_off(void) {}
+__weak void blue_led_on(void) {}
+__weak void blue_led_off(void) {}
/*
* Why is gd allocated a register? Prior to reloc it might be better to
return 0;
}
+static int initf_malloc(void)
+{
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ assert(gd->malloc_base); /* Set up by crt0.S */
+ gd->malloc_limit = gd->malloc_base + CONFIG_SYS_MALLOC_F_LEN;
+ gd->malloc_ptr = 0;
+#endif
+
+ return 0;
+}
+
+static int initf_dm(void)
+{
+#if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN)
+ int ret;
+
+ ret = dm_init_and_scan(true);
+ if (ret)
+ return ret;
+#endif
+
+ return 0;
+}
+
static init_fnc_t init_sequence_f[] = {
#ifdef CONFIG_SANDBOX
setup_ram_buf,
sdram_adjust_866,
init_timebase,
#endif
+ initf_malloc,
+ initf_dm,
init_baud_rate, /* initialze baudrate settings */
serial_init, /* serial communications setup */
console_init_f, /* stage 1 init of console */
{
ulong malloc_start;
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ debug("Pre-reloc malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
+ gd->malloc_ptr / 1024);
+#endif
/* The malloc area is immediately below the monitor copy in DRAM */
malloc_start = gd->relocaddr - TOTAL_MALLOC_LEN;
mem_malloc_init((ulong)map_sysmem(malloc_start, TOTAL_MALLOC_LEN),
#ifdef CONFIG_DM
static int initr_dm(void)
{
- int ret;
-
- ret = dm_init();
- if (ret) {
- debug("dm_init() failed: %d\n", ret);
- return ret;
- }
- ret = dm_scan_platdata();
- if (ret) {
- debug("dm_scan_platdata() failed: %d\n", ret);
- return ret;
- }
-#ifdef CONFIG_OF_CONTROL
- ret = dm_scan_fdt(gd->fdt_blob);
- if (ret) {
- debug("dm_scan_fdt() failed: %d\n", ret);
- return ret;
- }
-#endif
-
- return 0;
+ /* Save the pre-reloc driver model and start a new one */
+ gd->dm_root_f = gd->dm_root;
+ gd->dm_root = NULL;
+ return dm_init_and_scan(false);
}
#endif
#if defined(CONFIG_CMD_SCSI)
static int initr_scsi(void)
{
- /* Not supported properly on ARM yet */
-#ifndef CONFIG_ARM
puts("SCSI: ");
scsi_init();
-#endif
return 0;
}
-#endif /* CONFIG_CMD_NET */
+#endif
#if defined(CONFIG_CMD_DOC)
static int initr_doc(void)
};
/* Allow for arch specific config before we boot */
-static void __arch_preboot_os(void)
+__weak void arch_preboot_os(void)
{
/* please define platform specific arch_preboot_os() */
}
-void arch_preboot_os(void) __attribute__((weak, alias("__arch_preboot_os")));
int boot_selected_os(int argc, char * const argv[], int state,
bootm_headers_t *images, boot_os_fn *boot_fn)
#elif defined(CONFIG_ARM)
-int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
int i;
bd_t *bd = gd->bd;
puts("No arch specific invalidate_icache_all available!\n");
}
-int do_icache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_icache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
switch (argc) {
case 2: /* on / off */
/* please define arch specific flush_dcache_all */
}
-int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
switch (argc) {
case 2: /* on / off */
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_CMD_EEPROM)
-int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
const char *const fmt =
"\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
"read devaddr addr off cnt\n"
"eeprom write devaddr addr off cnt\n"
" - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
-);
+)
#else /* One EEPROM */
U_BOOT_CMD(
eeprom, 5, 1, do_eeprom,
"read addr off cnt\n"
"eeprom write addr off cnt\n"
" - read/write `cnt' bytes at EEPROM offset `off'"
-);
+)
#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
#endif
*/
#include <fs.h>
-int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_ext2ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return do_ls(cmdtp, flag, argc, argv, FS_TYPE_EXT);
}
/******************************************************************************
* Ext2fs boot command intepreter. Derived from diskboot
*/
-int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_ext2load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
return do_load(cmdtp, flag, argc, argv, FS_TYPE_EXT);
}
"list files in a directory (default /)",
"<interface> <dev[:part]> [directory]\n"
" - list files from 'dev' on 'interface' in a 'directory'"
-);
+)
U_BOOT_CMD(
ext2load, 6, 0, do_ext2load,
"load binary file from a Ext2 filesystem",
- "<interface> <dev[:part]> [addr] [filename] [bytes]\n"
+ "<interface> [<dev[:part]> [addr [filename [bytes [pos]]]]]\n"
" - load binary file 'filename' from 'dev' on 'interface'\n"
" to address 'addr' from ext2 filesystem."
-);
+)
U_BOOT_CMD(
fatload, 7, 0, do_fat_fsload,
"load binary file from a dos filesystem",
- "<interface> [<dev[:part]>] <addr> <filename> [bytes [pos]]\n"
+ "<interface> [<dev[:part]> [<addr> [<filename> [bytes [pos]]]]]\n"
" - Load binary file 'filename' from 'dev' on 'interface'\n"
" to address 'addr' from dos filesystem.\n"
" 'pos' gives the file position to start loading from.\n"
#include <command.h>
#include <fs.h>
-int do_load_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_load_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
return do_load(cmdtp, flag, argc, argv, FS_TYPE_ANY);
}
" If 'bytes' is 0 or omitted, the file is read until the end.\n"
" 'pos' gives the file byte position to start reading from.\n"
" If 'pos' is 0 or omitted, the file is read from the start."
-);
+)
-int do_ls_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_ls_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
return do_ls(cmdtp, flag, argc, argv, FS_TYPE_ANY);
}
"<interface> [<dev[:part]> [directory]]\n"
" - List files in directory 'directory' of partition 'part' on\n"
" device type 'interface' instance 'dev'."
-);
+)
* Returns zero always.
*/
#if defined(CONFIG_SYS_I2C)
-int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
int i;
#ifndef CONFIG_SYS_I2C_DIRECT_BUS
* on error.
*/
#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
-int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
int ret = 0;
unsigned int bus_no;
/* ------------------------------------------------------------------------- */
-void __ide_led(uchar led, uchar status)
+__weak void ide_led(uchar led, uchar status)
{
#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
static uchar led_buffer; /* Buffer for current LED status */
#endif
}
-void ide_led(uchar led, uchar status)
- __attribute__ ((weak, alias("__ide_led")));
-
#ifndef CONFIG_IDE_LED /* define LED macros, they are not used anyways */
# define DEVICE_LED(x) 0
# define LED_IDE1 1
/* ------------------------------------------------------------------------- */
-inline void __ide_outb(int dev, int port, unsigned char val)
+__weak void ide_outb(int dev, int port, unsigned char val)
{
debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
dev, port, val,
#endif
}
-void ide_outb(int dev, int port, unsigned char val)
- __attribute__ ((weak, alias("__ide_outb")));
-
-inline unsigned char __ide_inb(int dev, int port)
+__weak unsigned char ide_inb(int dev, int port)
{
uchar val;
return val;
}
-unsigned char ide_inb(int dev, int port)
- __attribute__ ((weak, alias("__ide_inb")));
-
-#ifdef CONFIG_TUNE_PIO
-inline int __ide_set_piomode(int pio_mode)
-{
- return 0;
-}
-
-inline int ide_set_piomode(int pio_mode)
- __attribute__ ((weak, alias("__ide_set_piomode")));
-#endif
-
void ide_init(void)
{
unsigned char c;
/* ------------------------------------------------------------------------- */
-void ide_input_swap_data(int dev, ulong *sect_buf, int words)
- __attribute__ ((weak, alias("__ide_input_swap_data")));
-
-void ide_input_data(int dev, ulong *sect_buf, int words)
- __attribute__ ((weak, alias("__ide_input_data")));
-
-void ide_output_data(int dev, const ulong *sect_buf, int words)
- __attribute__ ((weak, alias("__ide_output_data")));
-
/* We only need to swap data if we are running on a big endian cpu. */
#if defined(__LITTLE_ENDIAN)
-void __ide_input_swap_data(int dev, ulong *sect_buf, int words)
+__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
{
ide_input_data(dev, sect_buf, words);
}
#else
-void __ide_input_swap_data(int dev, ulong *sect_buf, int words)
+__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
{
volatile ushort *pbuf =
(ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
#if defined(CONFIG_IDE_SWAP_IO)
-void __ide_output_data(int dev, const ulong *sect_buf, int words)
+__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
{
ushort *dbuf;
volatile ushort *pbuf;
}
}
#else /* ! CONFIG_IDE_SWAP_IO */
-void __ide_output_data(int dev, const ulong *sect_buf, int words)
+__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
{
#if defined(CONFIG_IDE_AHB)
ide_write_data(dev, sect_buf, words);
#endif /* CONFIG_IDE_SWAP_IO */
#if defined(CONFIG_IDE_SWAP_IO)
-void __ide_input_data(int dev, ulong *sect_buf, int words)
+__weak void ide_input_data(int dev, ulong *sect_buf, int words)
{
ushort *dbuf;
volatile ushort *pbuf;
}
}
#else /* ! CONFIG_IDE_SWAP_IO */
-void __ide_input_data(int dev, ulong *sect_buf, int words)
+__weak void ide_input_data(int dev, ulong *sect_buf, int words)
{
#if defined(CONFIG_IDE_AHB)
ide_read_data(dev, sect_buf, words);
#ifdef CONFIG_ATAPI
int retries = 0;
#endif
-
-#ifdef CONFIG_TUNE_PIO
- int pio_mode;
-#endif
-
-#if 0
- int mode, cycle_time;
-#endif
int device;
device = dev_desc->dev;
else
dev_desc->removable = 0;
-#ifdef CONFIG_TUNE_PIO
- /* Mode 0 - 2 only, are directly determined by word 51. */
- pio_mode = iop.tPIO;
- if (pio_mode > 2) {
- printf("WARNING: Invalid PIO (word 51 = %d).\n", pio_mode);
- /* Force it to dead slow, and hope for the best... */
- pio_mode = 0;
- }
-
- /* Any CompactFlash Storage Card that supports PIO mode 3 or above
- * shall set bit 1 of word 53 to one and support the fields contained
- * in words 64 through 70.
- */
- if (iop.field_valid & 0x02) {
- /*
- * Mode 3 and above are possible. Check in order from slow
- * to fast, so we wind up with the highest mode allowed.
- */
- if (iop.eide_pio_modes & 0x01)
- pio_mode = 3;
- if (iop.eide_pio_modes & 0x02)
- pio_mode = 4;
- if (ata_id_is_cfa((u16 *)&iop)) {
- if ((iop.cf_advanced_caps & 0x07) == 0x01)
- pio_mode = 5;
- if ((iop.cf_advanced_caps & 0x07) == 0x02)
- pio_mode = 6;
- }
- }
-
- /* System-specific, depends on bus speeds, etc. */
- ide_set_piomode(pio_mode);
-#endif /* CONFIG_TUNE_PIO */
-
-#if 0
- /*
- * Drive PIO mode autoselection
- */
- mode = iop.tPIO;
-
- printf("tPIO = 0x%02x = %d\n", mode, mode);
- if (mode > 2) { /* 2 is maximum allowed tPIO value */
- mode = 2;
- debug("Override tPIO -> 2\n");
- }
- if (iop.field_valid & 2) { /* drive implements ATA2? */
- debug("Drive implements ATA2\n");
- if (iop.capability & 8) { /* drive supports use_iordy? */
- cycle_time = iop.eide_pio_iordy;
- } else {
- cycle_time = iop.eide_pio;
- }
- debug("cycle time = %d\n", cycle_time);
- mode = 4;
- if (cycle_time > 120)
- mode = 3; /* 120 ns for PIO mode 4 */
- if (cycle_time > 180)
- mode = 2; /* 180 ns for PIO mode 3 */
- if (cycle_time > 240)
- mode = 1; /* 240 ns for PIO mode 4 */
- if (cycle_time > 383)
- mode = 0; /* 383 ns for PIO mode 4 */
- }
- printf("PIO mode to use: PIO %d\n", mode);
-#endif /* 0 */
-
#ifdef CONFIG_ATAPI
if (dev_desc->if_type == IF_TYPE_ATAPI) {
atapi_inquiry(dev_desc);
* ATAPI Support
*/
-void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
- __attribute__ ((weak, alias("__ide_input_data_shorts")));
-
-void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
- __attribute__ ((weak, alias("__ide_output_data_shorts")));
-
-
#if defined(CONFIG_IDE_SWAP_IO)
/* since ATAPI may use commands with not 4 bytes alligned length
* we have our own transfer functions, 2 bytes alligned */
-void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
{
ushort *dbuf;
volatile ushort *pbuf;
}
}
-void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
{
ushort *dbuf;
volatile ushort *pbuf;
}
#else /* ! CONFIG_IDE_SWAP_IO */
-void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
{
outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
}
-void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
{
insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
}
DECLARE_GLOBAL_DATA_PTR;
/* Local prototypes */
-static void logbuff_putc(const char c);
-static void logbuff_puts(const char *s);
+static void logbuff_putc(struct stdio_dev *dev, const char c);
+static void logbuff_puts(struct stdio_dev *dev, const char *s);
static int logbuff_printk(const char *line);
static char buf[1024];
return (rc == 0) ? 1 : rc;
}
-static void logbuff_putc(const char c)
+static void logbuff_putc(struct stdio_dev *dev, const char c)
{
char buf[2];
buf[0] = c;
logbuff_printk(buf);
}
-static void logbuff_puts(const char *s)
+static void logbuff_puts(struct stdio_dev *dev, const char *s)
{
logbuff_printk (s);
}
*/
int do_log(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+ struct stdio_dev *sdev = NULL;
char *s;
unsigned long i, start, size;
/* Log concatenation of all arguments separated by spaces */
for (i = 2; i < argc; i++) {
logbuff_printk(argv[i]);
- logbuff_putc((i < argc - 1) ? ' ' : '\n');
+ logbuff_putc(sdev, (i < argc - 1) ? ' ' : '\n');
}
return 0;
}
mask_in_place = pdesc->mask << pdesc->lo;
- printf(" (%04hx:%04hx) %u.",
- mask_in_place,
- regval & mask_in_place,
- prd->regno);
+ printf(" (%04hx:%04x) %u.",
+ mask_in_place,
+ regval & mask_in_place,
+ prd->regno);
if (special_field(prd->regno, pdesc, regval)) {
}
#ifdef CONFIG_CMD_IMPORTENV
/*
- * env import [-d] [-t | -b | -c] addr [size]
+ * env import [-d] [-t [-r] | -b | -c] addr [size]
* -d: delete existing environment before importing;
* otherwise overwrite / append to existion definitions
* -t: assume text format; either "size" must be given or the
* text data must be '\0' terminated
+ * -r: handle CRLF like LF, that means exported variables with
+ * a content which ends with \r won't get imported. Used
+ * to import text files created with editors which are using CRLF
+ * for line endings. Only effective in addition to -t.
* -b: assume binary format ('\0' separated, "\0\0" terminated)
* -c: assume checksum protected environment format
* addr: memory address to read from
int chk = 0;
int fmt = 0;
int del = 0;
+ int crlf_is_lf = 0;
size_t size;
cmd = *argv;
goto sep_err;
sep = '\n';
break;
+ case 'r': /* handle CRLF like LF */
+ crlf_is_lf = 1;
+ break;
case 'd':
del = 1;
break;
if (!fmt)
printf("## Warning: defaulting to text format\n");
+ if (sep != '\n' && crlf_is_lf )
+ crlf_is_lf = 0;
+
addr = simple_strtoul(argv[0], NULL, 16);
ptr = map_sysmem(addr, 0);
ptr = (char *)ep->data;
}
- if (himport_r(&env_htab, ptr, size, sep, del ? 0 : H_NOCLEAR, 0,
- NULL) == 0) {
+ if (himport_r(&env_htab, ptr, size, sep, del ? 0 : H_NOCLEAR,
+ crlf_is_lf, 0, NULL) == 0) {
error("Environment import failed: errno = %d\n", errno);
return 1;
}
#endif
#endif
#if defined(CONFIG_CMD_IMPORTENV)
- "env import [-d] [-t | -b | -c] addr [size] - import environment\n"
+ "env import [-d] [-t [-r] | -b | -c] addr [size] - import environment\n"
#endif
"env print [-a | name ...] - print environment\n"
#if defined(CONFIG_CMD_RUN)
#error CONFIG_PARTITION_UUIDS must be enabled for CONFIG_CMD_PART to be enabled
#endif
-int do_part_uuid(int argc, char * const argv[])
+static int do_part_uuid(int argc, char * const argv[])
{
int part;
block_dev_desc_t *dev_desc;
return 0;
}
-int do_part_list(int argc, char * const argv[])
+static int do_part_list(int argc, char * const argv[])
{
int ret;
block_dev_desc_t *desc;
return 0;
}
-int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc < 2)
return CMD_RET_USAGE;
U_BOOT_CMD_MKENT(boot, 2, 1, do_pxe_boot, "", "")
};
-int do_pxe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_pxe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
cmd_tbl_t *cp;
*
* Returns 0 on success, 1 on error.
*/
-int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_sysboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned long pxefile_addr_r;
struct pxe_menu *cfg;
/**************************************************/
#if defined(CONFIG_CMD_SOURCE)
-int
-do_source (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_source(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr;
int rcode;
return err;
}
-int ubi_volume_continue_write(char *volume, void *buf, size_t size)
+static int ubi_volume_continue_write(char *volume, void *buf, size_t size)
{
int err = 1;
struct ubi_volume *vol;
static int ubifs_initialized;
static int ubifs_mounted;
-int do_ubifs_mount(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_ubifs_mount(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
char *vol_name;
int ret;
ubifs_initialized = 0;
}
-int do_ubifs_umount(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_ubifs_umount(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
if (argc != 1)
return CMD_RET_USAGE;
return 0;
}
-int do_ubifs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_ubifs_ls(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
char *filename = "/";
int ret;
return ret;
}
-int do_ubifs_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_ubifs_load(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
{
char *filename;
char *endp;
case stderr:
/* Start new device */
if (dev->start) {
- error = dev->start();
+ error = dev->start(dev);
/* If it's not started dont use it */
if (error < 0)
break;
unsigned char ret;
/* This is never called with testcdev == NULL */
- ret = tstcdev->getc();
+ ret = tstcdev->getc(tstcdev);
tstcdev = NULL;
return ret;
}
for (i = 0; i < cd_count[file]; i++) {
dev = console_devices[file][i];
if (dev->tstc != NULL) {
- ret = dev->tstc();
+ ret = dev->tstc(dev);
if (ret > 0) {
tstcdev = dev;
disable_ctrlc(0);
for (i = 0; i < cd_count[file]; i++) {
dev = console_devices[file][i];
if (dev->putc != NULL)
- dev->putc(c);
+ dev->putc(dev, c);
}
}
for (i = 0; i < cd_count[file]; i++) {
dev = console_devices[file][i];
if (dev->puts != NULL)
- dev->puts(s);
+ dev->puts(dev, s);
}
}
#else
static inline int console_getc(int file)
{
- return stdio_devices[file]->getc();
+ return stdio_devices[file]->getc(stdio_devices[file]);
}
static inline int console_tstc(int file)
{
- return stdio_devices[file]->tstc();
+ return stdio_devices[file]->tstc(stdio_devices[file]);
}
static inline void console_putc(int file, const char c)
{
- stdio_devices[file]->putc(c);
+ stdio_devices[file]->putc(stdio_devices[file], c);
}
static inline void console_puts(int file, const char *s)
{
- stdio_devices[file]->puts(s);
+ stdio_devices[file]->puts(stdio_devices[file], s);
}
static inline void console_printdevs(int file)
void putc(const char c)
{
#ifdef CONFIG_SANDBOX
- if (!gd) {
+ if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) {
os_putc(c);
return;
}
void puts(const char *s)
{
#ifdef CONFIG_SANDBOX
- if (!gd) {
+ if (!gd || !(gd->flags & GD_FLG_SERIAL_READY)) {
os_puts(s);
return;
}
uint i;
char printbuffer[CONFIG_SYS_PBSIZE];
-#ifndef CONFIG_PRE_CONSOLE_BUFFER
+#if defined(CONFIG_PRE_CONSOLE_BUFFER) && !defined(CONFIG_SANDBOX)
if (!gd->have_console)
return 0;
#endif
#include <common.h>
+#ifdef CONFIG_SANDBOX
+#define DEBUG
+#endif
+
#if 0 /* Moved to malloc.h */
/* ---------- To make a malloc.h, start cutting here ------------ */
*/
-\f
+
/* Preliminaries */
#endif /* 0 */ /* Moved to malloc.h */
#include <malloc.h>
+#include <asm/io.h>
+
#ifdef DEBUG
#if __STD_C
static void malloc_update_mallinfo (void);
#endif
-\f
+
/*
Type declarations
serviced via calls to mmap, and then later released via munmap.
*/
-\f
+
/* sizes, alignments */
#define SIZE_SZ (sizeof(INTERNAL_SIZE_T))
#define aligned_OK(m) (((unsigned long)((m)) & (MALLOC_ALIGN_MASK)) == 0)
-\f
+
/*
Physical chunk operations
#define chunk_at_offset(p, s) ((mchunkptr)(((char*)(p)) + (s)))
-\f
+
/*
Dealing with use bits
(((mchunkptr)(((char*)(p)) + (s)))->size &= ~(PREV_INUSE))
-\f
+
/*
Dealing with size fields
#define set_foot(p, s) (((mchunkptr)((char*)(p) + (s)))->prev_size = (s))
-\f
+
/*
#define is_small_request(nb) (nb < MAX_SMALLBIN_SIZE - SMALLBIN_WIDTH)
-\f
+
/*
To help compensate for the large number of bins, a one-level index
#define clear_binblock(ii) (binblocks_w = (mbinptr)(binblocks_r & ~(idx2binblock(ii))))
-\f
+
/* Other static bookkeeping data */
static unsigned long max_mmapped_mem = 0;
#endif
-\f
+
/*
Debugging support
#define check_malloced_chunk(P,N)
#endif
-\f
+
/*
Macro-based internal utilities
(last_remainder->fd = last_remainder->bk = last_remainder)
-\f
+
/* Routines dealing with mmap(). */
#endif /* HAVE_MMAP */
-\f
+
/*
Extend the top-most chunk by obtaining memory from system.
}
-\f
+
/* Main public routines */
INTERNAL_SIZE_T nb;
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ if (!(gd->flags & GD_FLG_RELOC)) {
+ ulong new_ptr;
+ void *ptr;
+
+ new_ptr = gd->malloc_ptr + bytes;
+ if (new_ptr > gd->malloc_limit)
+ panic("Out of pre-reloc memory");
+ ptr = map_sysmem(gd->malloc_base + gd->malloc_ptr, bytes);
+ gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr));
+ return ptr;
+ }
+#endif
+
/* check if mem_malloc_init() was run */
if ((mem_malloc_start == 0) && (mem_malloc_end == 0)) {
/* not initialized yet */
}
-\f
+
/*
mchunkptr fwd; /* misc temp for linking */
int islr; /* track whether merging with last_remainder */
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ /* free() is a no-op - all the memory will be freed on relocation */
+ if (!(gd->flags & GD_FLG_RELOC))
+ return;
+#endif
+
if (mem == NULL) /* free(0) has no effect */
return;
}
-\f
+
/*
/* realloc of null is supposed to be same as malloc */
if (oldmem == NULL) return mALLOc(bytes);
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ if (!(gd->flags & GD_FLG_RELOC)) {
+ /* This is harder to support and should not be needed */
+ panic("pre-reloc realloc() is not supported");
+ }
+#endif
+
newp = oldp = mem2chunk(oldmem);
newsize = oldsize = chunksize(oldp);
}
-\f
+
/*
}
-\f
+
/*
return NULL;
else
{
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ if (!(gd->flags & GD_FLG_RELOC)) {
+ MALLOC_ZERO(mem, sz);
+ return mem;
+ }
+#endif
p = mem2chunk(mem);
/* Two optional cases in which clearing not necessary */
}
#endif
-\f
+
/*
}
}
-\f
+
/*
malloc_usable_size:
}
-\f
+
/* Utility to update current_mallinfo for malloc_stats and mallinfo() */
}
#endif /* DEBUG */
-\f
+
/*
#endif /* DEBUG */
-\f
+
/*
mallopt:
.change_ok = env_flags_validate,
};
-static uchar __env_get_char_spec(int index)
+__weak uchar env_get_char_spec(int index)
{
return *((uchar *)(gd->env_addr + index));
}
-uchar env_get_char_spec(int)
- __attribute__((weak, alias("__env_get_char_spec")));
static uchar env_get_char_init(int index)
{
}
if (himport_r(&env_htab, (char *)default_environment,
- sizeof(default_environment), '\0', flags,
+ sizeof(default_environment), '\0', flags, 0,
0, NULL) == 0)
error("Environment import failed: errno = %d\n", errno);
*/
return himport_r(&env_htab, (const char *)default_environment,
sizeof(default_environment), '\0',
- H_NOCLEAR | H_INTERACTIVE, nvars, vars);
+ H_NOCLEAR | H_INTERACTIVE, 0, nvars, vars);
}
#ifdef CONFIG_ENV_AES
return ret;
}
- if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0,
+ if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0, 0,
0, NULL)) {
gd->flags |= GD_FLG_ENV_READY;
return 1;
{
env_t env_new;
block_dev_desc_t *dev_desc = NULL;
- int dev = FAT_ENV_DEVICE;
- int part = FAT_ENV_PART;
+ disk_partition_t info;
+ int dev, part;
int err;
err = env_export(&env_new);
if (err)
return err;
-#ifdef CONFIG_MMC
- if (strcmp(FAT_ENV_INTERFACE, "mmc") == 0) {
- struct mmc *mmc = find_mmc_device(dev);
-
- if (!mmc) {
- printf("no mmc device at slot %x\n", dev);
- return 1;
- }
-
- mmc->has_init = 0;
- mmc_init(mmc);
- }
-#endif /* CONFIG_MMC */
-
- dev_desc = get_dev(FAT_ENV_INTERFACE, dev);
- if (dev_desc == NULL) {
- printf("Failed to find %s%d\n",
- FAT_ENV_INTERFACE, dev);
+ part = get_device_and_partition(FAT_ENV_INTERFACE,
+ FAT_ENV_DEVICE_AND_PART,
+ &dev_desc, &info, 1);
+ if (part < 0)
return 1;
- }
- err = fat_register_device(dev_desc, part);
- if (err) {
- printf("Failed to register %s%d:%d\n",
- FAT_ENV_INTERFACE, dev, part);
+ dev = dev_desc->dev;
+ if (fat_set_blk_dev(dev_desc, &info) != 0) {
+ printf("\n** Unable to use %s %d:%d for saveenv **\n",
+ FAT_ENV_INTERFACE, dev, part);
return 1;
}
{
char buf[CONFIG_ENV_SIZE];
block_dev_desc_t *dev_desc = NULL;
- int dev = FAT_ENV_DEVICE;
- int part = FAT_ENV_PART;
+ disk_partition_t info;
+ int dev, part;
int err;
-#ifdef CONFIG_MMC
- if (strcmp(FAT_ENV_INTERFACE, "mmc") == 0) {
- struct mmc *mmc = find_mmc_device(dev);
-
- if (!mmc) {
- printf("no mmc device at slot %x\n", dev);
- set_default_env(NULL);
- return;
- }
-
- mmc->has_init = 0;
- mmc_init(mmc);
- }
-#endif /* CONFIG_MMC */
-
- dev_desc = get_dev(FAT_ENV_INTERFACE, dev);
- if (dev_desc == NULL) {
- printf("Failed to find %s%d\n",
- FAT_ENV_INTERFACE, dev);
- set_default_env(NULL);
- return;
- }
-
- err = fat_register_device(dev_desc, part);
- if (err) {
- printf("Failed to register %s%d:%d\n",
- FAT_ENV_INTERFACE, dev, part);
- set_default_env(NULL);
- return;
+ part = get_device_and_partition(FAT_ENV_INTERFACE,
+ FAT_ENV_DEVICE_AND_PART,
+ &dev_desc, &info, 1);
+ if (part < 0)
+ goto err_env_relocate;
+
+ dev = dev_desc->dev;
+ if (fat_set_blk_dev(dev_desc, &info) != 0) {
+ printf("\n** Unable to use %s %d:%d for loading the env **\n",
+ FAT_ENV_INTERFACE, dev, part);
+ goto err_env_relocate;
}
err = file_fat_read(FAT_ENV_FILE, (uchar *)&buf, CONFIG_ENV_SIZE);
if (err == -1) {
printf("\n** Unable to read \"%s\" from %s%d:%d **\n",
FAT_ENV_FILE, FAT_ENV_INTERFACE, dev, part);
- set_default_env(NULL);
- return;
+ goto err_env_relocate;
}
env_import(buf, 1);
+ return;
+
+err_env_relocate:
+ set_default_env(NULL);
}
/*----------------------------------------------------------------------*/
+static void lcd_stub_putc(struct stdio_dev *dev, const char c)
+{
+ lcd_putc(c);
+}
+
void lcd_putc(const char c)
{
if (!lcd_is_enabled) {
/*----------------------------------------------------------------------*/
+static void lcd_stub_puts(struct stdio_dev *dev, const char *s)
+{
+ lcd_puts(s);
+}
+
void lcd_puts(const char *s)
{
if (!lcd_is_enabled) {
strcpy(lcddev.name, "lcd");
lcddev.ext = 0; /* No extensions */
lcddev.flags = DEV_FLAGS_OUTPUT; /* Output only */
- lcddev.putc = lcd_putc; /* 'putc' function */
- lcddev.puts = lcd_puts; /* 'puts' function */
+ lcddev.putc = lcd_stub_putc; /* 'putc' function */
+ lcddev.puts = lcd_stub_puts; /* 'puts' function */
rc = stdio_register(&lcddev);
/*
* Board-specific Platform code can reimplement show_boot_progress () if needed
*/
-void inline __show_boot_progress (int val) {}
-void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress")));
+__weak void show_boot_progress(int val) {}
static void modem_init(void)
{
/* load linux */
nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
- CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
+ sizeof(*header), (void *)header);
spl_parse_image_header(header);
if (header->ih_os == IH_OS_LINUX) {
/* happy - was a linux */
#endif
#ifdef CONFIG_NAND_ENV_DST
nand_spl_load_image(CONFIG_ENV_OFFSET,
- CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
+ sizeof(*header), (void *)header);
spl_parse_image_header(header);
nand_spl_load_image(CONFIG_ENV_OFFSET, spl_image.size,
(void *)spl_image.load_addr);
#ifdef CONFIG_ENV_OFFSET_REDUND
nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND,
- CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
+ sizeof(*header), (void *)header);
spl_parse_image_header(header);
nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, spl_image.size,
(void *)spl_image.load_addr);
#include <common.h>
#include <splash.h>
-int __splash_screen_prepare(void)
+__weak int splash_screen_prepare(void)
{
return 0;
}
-int splash_screen_prepare(void)
- __attribute__ ((weak, alias("__splash_screen_prepare")));
-
-
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
void splash_get_pos(int *x, int *y)
{
#include <config.h>
#include <common.h>
+#include <errno.h>
#include <stdarg.h>
#include <malloc.h>
#include <stdio_dev.h>
#ifdef CONFIG_SYS_DEVICE_NULLDEV
-void nulldev_putc(const char c)
+void nulldev_putc(struct stdio_dev *dev, const char c)
{
/* nulldev is empty! */
}
-void nulldev_puts(const char *s)
+void nulldev_puts(struct stdio_dev *dev, const char *s)
{
/* nulldev is empty! */
}
-int nulldev_input(void)
+int nulldev_input(struct stdio_dev *dev)
{
/* nulldev is empty! */
return 0;
}
#endif
+void stdio_serial_putc(struct stdio_dev *dev, const char c)
+{
+ serial_putc(c);
+}
+
+void stdio_serial_puts(struct stdio_dev *dev, const char *s)
+{
+ serial_puts(s);
+}
+
+int stdio_serial_getc(struct stdio_dev *dev)
+{
+ return serial_getc();
+}
+
+int stdio_serial_tstc(struct stdio_dev *dev)
+{
+ return serial_tstc();
+}
+
/**************************************************************************
* SYSTEM DRIVERS
**************************************************************************
strcpy (dev.name, "serial");
dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
- dev.putc = serial_putc;
- dev.puts = serial_puts;
- dev.getc = serial_getc;
- dev.tstc = serial_tstc;
+ dev.putc = stdio_serial_putc;
+ dev.puts = stdio_serial_puts;
+ dev.getc = stdio_serial_getc;
+ dev.tstc = stdio_serial_tstc;
stdio_register (&dev);
#ifdef CONFIG_SYS_DEVICE_NULLDEV
return _dev;
}
-int stdio_register (struct stdio_dev * dev)
+int stdio_register_dev(struct stdio_dev *dev, struct stdio_dev **devp)
{
struct stdio_dev *_dev;
_dev = stdio_clone(dev);
if(!_dev)
- return -1;
+ return -ENODEV;
list_add_tail(&(_dev->list), &(devs.list));
+ if (devp)
+ *devp = _dev;
+
return 0;
}
+int stdio_register(struct stdio_dev *dev)
+{
+ return stdio_register_dev(dev, NULL);
+}
+
/* deregister the device "devname".
* returns 0 if success, -1 if device is assigned and 1 if devname not found
*/
#ifdef CONFIG_SYS_STDIO_DEREGISTER
-int stdio_deregister(const char *devname)
+int stdio_deregister_dev(struct stdio_dev *dev)
{
int l;
struct list_head *pos;
- struct stdio_dev *dev;
char temp_names[3][16];
- dev = stdio_get_by_name(devname);
-
- if(!dev) /* device not found */
- return -1;
/* get stdio devices (ListRemoveItem changes the dev list) */
for (l=0 ; l< MAX_FILES; l++) {
if (stdio_devices[l] == dev) {
}
return 0;
}
+
+int stdio_deregister(const char *devname)
+{
+ struct stdio_dev *dev;
+
+ dev = stdio_get_by_name(devname);
+
+ if (!dev) /* device not found */
+ return -ENODEV;
+
+ return stdio_deregister_dev(dev);
+}
#endif /* CONFIG_SYS_STDIO_DEREGISTER */
int stdio_init (void)
}
/* test if a character is in the queue */
-static int usb_kbd_testc(void)
+static int usb_kbd_testc(struct stdio_dev *sdev)
{
struct stdio_dev *dev;
struct usb_device *usb_kbd_dev;
}
/* gets the character from the queue */
-static int usb_kbd_getc(void)
+static int usb_kbd_getc(struct stdio_dev *sdev)
{
struct stdio_dev *dev;
struct usb_device *usb_kbd_dev;
memset(&usb_kbd_dev, 0, sizeof(struct stdio_dev));
strcpy(usb_kbd_dev.name, DEVNAME);
usb_kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
- usb_kbd_dev.putc = NULL;
- usb_kbd_dev.puts = NULL;
usb_kbd_dev.getc = usb_kbd_getc;
usb_kbd_dev.tstc = usb_kbd_testc;
usb_kbd_dev.priv = (void *)dev;
# so calculate CPUDIR before including ARCH/SOC/CPU config.mk files.
# Check if arch/$ARCH/cpu/$CPU exists, otherwise assume arch/$ARCH/cpu contains
# CPU-specific code.
-CPUDIR=arch/$(ARCH)/cpu/$(CPU)
-ifneq ($(srctree)/$(CPUDIR),$(wildcard $(srctree)/$(CPUDIR)))
-CPUDIR=arch/$(ARCH)/cpu
-endif
+CPUDIR=arch/$(ARCH)/cpu$(if $(CPU),/$(CPU),)
sinclude $(srctree)/arch/$(ARCH)/config.mk # include architecture dependend rules
sinclude $(srctree)/$(CPUDIR)/config.mk # include CPU specific rules
#endif /* any CONFIG_..._PARTITION */
-void print_part (block_dev_desc_t * dev_desc)
+void print_part(block_dev_desc_t * dev_desc)
{
switch (dev_desc->part_type) {
#endif /* HAVE_BLOCK_DEVICE */
-int get_partition_info(block_dev_desc_t *dev_desc, int part
- , disk_partition_t *info)
+int get_partition_info(block_dev_desc_t *dev_desc, int part,
+ disk_partition_t *info)
{
#ifdef HAVE_BLOCK_DEVICE
disk_partition_t tmpinfo;
/*
- * Special-case a psuedo block device "hostfs", to allow access to the
+ * Special-case a pseudo block device "hostfs", to allow access to the
* host's own filesystem.
*/
if (0 == strcmp(ifname, "hostfs")) {
To boot the kernel, these steps under a Falcon-aware U-Boot are required:
1. Boot the board into U-Boot.
-Use the "spl export" command to generate the kernel parameters area or the DT.
-U-Boot runs as when it boots the kernel, but stops before passing the control
-to the kernel.
+After loading the desired legacy-format kernel image into memory (and DT as
+well, if used), use the "spl export" command to generate the kernel parameters
+area or the DT. U-Boot runs as when it boots the kernel, but stops before
+passing the control to the kernel.
2. Save the prepared snapshot into persistent media.
The address where to save it must be configured into board configuration
------------------------
If you are unlucky then your architecture may not support generic board.
-The following architectures are supported at the time of writing:
+The following architectures are supported now:
arc
arm
+ mips
powerpc
sandbox
x86
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-simpc8313 powerpc mpc83xx - 2014-04-28 Ron Madrid <info@sheldoninst.com>
+spc1920 powerpc mpc8xx - -
+v37 powerpc mpc8xx - -
+fads powerpc mpc8xx - -
+netphone powerpc mpc8xx - -
+netta2 powerpc mpc8xx - -
+netta powerpc mpc8xx - -
+rbc823 powerpc mpc8xx - -
+quantum powerpc mpc8xx - -
+RPXlite_dw powerpc mpc8xx - -
+qs850 powerpc mpc8xx - -
+qs860t powerpc mpc8xx - -
+simpc8313 powerpc mpc83xx 7445207f 2014-06-05 Ron Madrid <info@sheldoninst.com>
hidden_dragon powerpc mpc824x 3fe1a854 2014-05-30 Yusdi Santoso <yusdi_santoso@adaptec.com>
debris powerpc mpc824x 7edb1f7b 2014-05-30 Sangmoon Kim <dogoil@etinsys.com>
kvme080 powerpc mpc824x 2868f862 2014-05-30 Sangmoon Kim <dogoil@etinsys.com>
You should see something like this:
<...U-Boot banner...>
- Running 12 driver model tests
+ Running 21 driver model tests
Test: dm_test_autobind
Test: dm_test_autoprobe
+ Test: dm_test_bus_children
+ Device 'd-test': seq 3 is in use by 'b-test'
+ Device 'c-test@0': seq 0 is in use by 'a-test'
+ Device 'c-test@1': seq 1 is in use by 'd-test'
+ Test: dm_test_bus_children_funcs
+ Test: dm_test_bus_parent_data
+ Test: dm_test_bus_parent_ops
Test: dm_test_children
Test: dm_test_fdt
+ Device 'd-test': seq 3 is in use by 'b-test'
+ Test: dm_test_fdt_offset
+ Test: dm_test_fdt_pre_reloc
+ Test: dm_test_fdt_uclass_seq
+ Device 'd-test': seq 3 is in use by 'b-test'
+ Device 'a-test': seq 0 is in use by 'd-test'
Test: dm_test_gpio
sandbox_gpio: sb_gpio_get_value: error: offset 4 not reserved
Test: dm_test_leak
- Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c
- Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c
Test: dm_test_lifecycle
Test: dm_test_operations
Test: dm_test_ordering
Test: dm_test_platdata
+ Test: dm_test_pre_reloc
Test: dm_test_remove
Test: dm_test_uclass
+ Test: dm_test_uclass_before_ready
Failures: 0
-(You can add '#define DEBUG' as suggested to check for memory leaks)
-
What is going on?
-----------------
end of the enum there, then declare your uclass as above.
+Device Sequence Numbers
+-----------------------
+
+U-Boot numbers devices from 0 in many situations, such as in the command
+line for I2C and SPI buses, and the device names for serial ports (serial0,
+serial1, ...). Driver model supports this numbering and permits devices
+to be locating by their 'sequence'.
+
+Sequence numbers start from 0 but gaps are permitted. For example, a board
+may have I2C buses 0, 1, 4, 5 but no 2 or 3. The choice of how devices are
+numbered is up to a particular board, and may be set by the SoC in some
+cases. While it might be tempting to automatically renumber the devices
+where there are gaps in the sequence, this can lead to confusion and is
+not the way that U-Boot works.
+
+Each device can request a sequence number. If none is required then the
+device will be automatically allocated the next available sequence number.
+
+To specify the sequence number in the device tree an alias is typically
+used.
+
+aliases {
+ serial2 = "/serial@22230000";
+};
+
+This indicates that in the uclass called "serial", the named node
+("/serial@22230000") will be given sequence number 2. Any command or driver
+which requests serial device 2 will obtain this device.
+
+Some devices represent buses where the devices on the bus are numbered or
+addressed. For example, SPI typically numbers its slaves from 0, and I2C
+uses a 7-bit address. In these cases the 'reg' property of the subnode is
+used, for example:
+
+{
+ aliases {
+ spi2 = "/spi@22300000";
+ };
+
+ spi@22300000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-flash@0 {
+ reg = <0>;
+ ...
+ }
+ eeprom@1 {
+ reg = <1>;
+ };
+ };
+
+In this case we have a SPI bus with two slaves at 0 and 1. The SPI bus
+itself is numbered 2. So we might access the SPI flash with:
+
+ sf probe 2:0
+
+and the eeprom with
+
+ sspi 2:1 32 ef
+
+These commands simply need to look up the 2nd device in the SPI uclass to
+find the right SPI bus. Then, they look at the children of that bus for the
+right sequence number (0 or 1 in this case).
+
+Typically the alias method is used for top-level nodes and the 'reg' method
+is used only for buses.
+
+Device sequence numbers are resolved when a device is probed. Before then
+the sequence number is only a request which may or may not be honoured,
+depending on what other devices have been probed. However the numbering is
+entirely under the control of the board author so a conflict is generally
+an error.
+
+
+Bus Drivers
+-----------
+
+A common use of driver model is to implement a bus, a device which provides
+access to other devices. Example of buses include SPI and I2C. Typically
+the bus provides some sort of transport or translation that makes it
+possible to talk to the devices on the bus.
+
+Driver model provides a few useful features to help with implementing
+buses. Firstly, a bus can request that its children store some 'parent
+data' which can be used to keep track of child state. Secondly, the bus can
+define methods which are called when a child is probed or removed. This is
+similar to the methods the uclass driver provides.
+
+Here an explanation of how a bus fits with a uclass may be useful. Consider
+a USB bus with several devices attached to it, each from a different (made
+up) uclass:
+
+ xhci_usb (UCLASS_USB)
+ eth (UCLASS_ETHERNET)
+ camera (UCLASS_CAMERA)
+ flash (UCLASS_FLASH_STORAGE)
+
+Each of the devices is connected to a different address on the USB bus.
+The bus device wants to store this address and some other information such
+as the bus speed for each device.
+
+To achieve this, the bus device can use dev->parent_priv in each of its
+three children. This can be auto-allocated if the bus driver has a non-zero
+value for per_child_auto_alloc_size. If not, then the bus device can
+allocate the space itself before the child device is probed.
+
+Also the bus driver can define the child_pre_probe() and child_post_remove()
+methods to allow it to do some processing before the child is activated or
+after it is deactivated.
+
+Note that the information that controls this behaviour is in the bus's
+driver, not the child's. In fact it is possible that child has no knowledge
+that it is connected to a bus. The same child device may even be used on two
+different bus types. As an example. the 'flash' device shown above may also
+be connected on a SATA bus or standalone with no bus:
+
+ xhci_usb (UCLASS_USB)
+ flash (UCLASS_FLASH_STORAGE) - parent data/methods defined by USB bus
+
+ sata (UCLASS_SATA)
+ flash (UCLASS_FLASH_STORAGE) - parent data/methods defined by SATA bus
+
+ flash (UCLASS_FLASH_STORAGE) - no parent data/methods (not on a bus)
+
+Above you can see that the driver for xhci_usb/sata controls the child's
+bus methods. In the third example the device is not on a bus, and therefore
+will not have these methods at all. Consider the case where the flash
+device defines child methods. These would be used for *its* children, and
+would be quite separate from the methods defined by the driver for the bus
+that the flash device is connetced to. The act of attaching a device to a
+parent device which is a bus, causes the device to start behaving like a
+bus device, regardless of its own views on the matter.
+
+The uclass for the device can also contain data private to that uclass.
+But note that each device on the bus may be a memeber of a different
+uclass, and this data has nothing to do with the child data for each child
+on the bus.
+
+
Driver Lifecycle
----------------
stored in the device, but it is uclass data. owned by the uclass driver.
It is possible for the device to access it.
- d. All parent devices are probed. It is not possible to activate a device
+ d. If the device's immediate parent specifies a per_child_auto_alloc_size
+ then this space is allocated. This is intended for use by the parent
+ device to keep track of things related to the child. For example a USB
+ flash stick attached to a USB host controller would likely use this
+ space. The controller can hold information about the USB state of each
+ of its children.
+
+ e. All parent devices are probed. It is not possible to activate a device
unless its predecessors (all the way up to the root device) are activated.
This means (for example) that an I2C driver will require that its bus
be activated.
- e. If the driver provides an ofdata_to_platdata() method, then this is
+ f. The device's sequence number is assigned, either the requested one
+ (assuming no conflicts) or the next available one if there is a conflict
+ or nothing particular is requested.
+
+ g. If the driver provides an ofdata_to_platdata() method, then this is
called to convert the device tree data into platform data. This should
do various calls like fdtdec_get_int(gd->fdt_blob, dev->of_offset, ...)
to access the node and store the resulting information into dev->platdata.
data, one day it is possible that U-Boot will cache platformat data for
devices which are regularly de/activated).
- f. The device's probe() method is called. This should do anything that
+ h. The device's probe() method is called. This should do anything that
is required by the device to get it going. This could include checking
that the hardware is actually present, setting up clocks for the
hardware and setting up hardware registers to initial values. The code
allocate the priv space here yourself. The same applies also to
platdata_auto_alloc_size. Remember to free them in the remove() method.
- g. The device is marked 'activated'
+ i. The device is marked 'activated'
- h. The uclass's post_probe() method is called, if one exists. This may
+ j. The uclass's post_probe() method is called, if one exists. This may
cause the uclass to do some housekeeping to record the device as
activated and 'known' by the uclass.
to be sure that no hardware is running, it should be enough to remove
all devices.
- d. The device memory is freed (platform data, private data, uclass data).
+ d. The device memory is freed (platform data, private data, uclass data,
+ parent data).
Note: Because the platform data for a U_BOOT_DEVICE() is defined with a
static pointer, it is not de-allocated during the remove() method. For
or preferably ofdata_to_platdata()) and the deallocation in remove()
are the responsibility of the driver author.
- e. The device is marked inactive. Note that it is still bound, so the
+ e. The device sequence number is set to -1, meaning that it no longer
+ has an allocated sequence. If the device is later reactivated and that
+ sequence number is still free, it may well receive the name sequence
+ number again. But from this point, the sequence number previously used
+ by this device will no longer exist (think of SPI bus 2 being removed
+ and bus 2 is no longer available for use).
+
+ f. The device is marked inactive. Note that it is still bound, so the
device structure itself is not freed at this point. Should the device be
activated again, then the cycle starts again at step 2 above.
- Implemented a GPIO system, trying to keep it simple
+Pre-Relocation Support
+----------------------
+
+For pre-relocation we simply call the driver model init function. Only
+drivers marked with DM_FLAG_PRE_RELOC or the device tree
+'u-boot,dm-pre-reloc' flag are initialised prior to relocation. This helps
+to reduce the driver model overhead.
+
+Then post relocation we throw that away and re-init driver model again.
+For drivers which require some sort of continuity between pre- and
+post-relocation devices, we can provide access to the pre-relocation
+device pointers, but this is not currently implemented (the root device
+pointer is saved but not made available through the driver model API).
+
+
Things to punt for later
------------------------
- SPL support - this will have to be present before many drivers can be
converted, but it seems like we can add it once we are happy with the
core implementation.
-- Pre-relocation support - similar story
-That is not to say that no thinking has gone into these - in fact there
+That is not to say that no thinking has gone into this - in fact there
is quite a lot there. However, getting these right is non-trivial and
there is a high cost associated with going down the wrong path.
For SPL, it may be possible to fit in a simplified driver model with only
bind and probe methods, to reduce size.
-For pre-relocation we can simply call the driver model init function. Then
-post relocation we throw that away and re-init driver model again. For drivers
-which require some sort of continuity between pre- and post-relocation
-devices, we can provide access to the pre-relocation device pointers.
-
Uclasses are statically numbered at compile time. It would be possible to
change this to dynamic numbering, but then we would require some sort of
lookup service, perhaps searching by name. This is slightly less efficient
alias galak Kumar Gala <galak@kernel.crashing.org>
alias gruss Graeme Russ <graeme.russ@gmail.com>
alias hs Heiko Schocher <hs@denx.de>
+alias ijc Ian Campbell <ijc+uboot@hellion.org.uk>
alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
alias jagan Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
alias jasonjin Jason Jin <jason.jin@freescale.com>
alias jhersh Joe Hershberger <joe.hershberger@gmail.com>
+alias jwrdegoede Hans de Goede <hdegoede@redhat.com>
alias kimphill Kim Phillips <kim.phillips@freescale.com>
alias lukma Lukasz Majewski <l.majewski@samsung.com>
alias macpaul Macpaul Lin <macpaul@andestech.com>
alias s3c samsung
alias s5pc samsung
alias samsung uboot, prom
+alias sunxi uboot, ijc, jwrdegoede
alias tegra uboot, sjg, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com>
alias tegra2 tegra
alias ti uboot, trini
+alias zynq uboot, monstr
alias avr32 uboot, abiessmann
#define WAIT_MS_SPINUP 20000
#define WAIT_MS_DATAIO 5000
#define WAIT_MS_FLUSH 5000
-#define WAIT_MS_LINKUP 40
+#define WAIT_MS_LINKUP 200
static inline u32 ahci_port_base(u32 base, u32 port)
{
*/
#include <common.h>
+#include <fdtdec.h>
#include <malloc.h>
#include <dm/device.h>
#include <dm/device-internal.h>
#include <linux/err.h>
#include <linux/list.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/**
* device_chld_unbind() - Unbind all device's children from the device
*
dev->parent = parent;
dev->driver = drv;
dev->uclass = uc;
+
+ /*
+ * For some devices, such as a SPI or I2C bus, the 'reg' property
+ * is a reasonable indicator of the sequence number. But if there is
+ * an alias, we use that in preference. In any case, this is just
+ * a 'requested' sequence, and will be resolved (and ->seq updated)
+ * when the device is probed.
+ */
+ dev->req_seq = fdtdec_get_int(gd->fdt_blob, of_offset, "reg", -1);
+ dev->seq = -1;
+ if (uc->uc_drv->name && of_offset != -1) {
+ fdtdec_get_alias_seq(gd->fdt_blob, uc->uc_drv->name, of_offset,
+ &dev->req_seq);
+ }
+
if (!dev->platdata && drv->platdata_auto_alloc_size)
dev->flags |= DM_FLAG_ALLOC_PDATA;
return ret;
}
-int device_bind_by_name(struct udevice *parent, const struct driver_info *info,
- struct udevice **devp)
+int device_bind_by_name(struct udevice *parent, bool pre_reloc_only,
+ const struct driver_info *info, struct udevice **devp)
{
struct driver *drv;
drv = lists_driver_lookup_name(info->name);
if (!drv)
return -ENOENT;
+ if (pre_reloc_only && !(drv->flags & DM_FLAG_PRE_RELOC))
+ return -EPERM;
return device_bind(parent, drv, info->name, (void *)info->platdata,
-1, devp);
free(dev->uclass_priv);
dev->uclass_priv = NULL;
}
+ if (dev->parent) {
+ size = dev->parent->driver->per_child_auto_alloc_size;
+ if (size) {
+ free(dev->parent_priv);
+ dev->parent_priv = NULL;
+ }
+ }
}
int device_probe(struct udevice *dev)
struct driver *drv;
int size = 0;
int ret;
+ int seq;
if (!dev)
return -EINVAL;
/* Ensure all parents are probed */
if (dev->parent) {
+ size = dev->parent->driver->per_child_auto_alloc_size;
+ if (size) {
+ dev->parent_priv = calloc(1, size);
+ if (!dev->parent_priv) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+ }
+
ret = device_probe(dev->parent);
if (ret)
goto fail;
}
+ seq = uclass_resolve_seq(dev);
+ if (seq < 0) {
+ ret = seq;
+ goto fail;
+ }
+ dev->seq = seq;
+
+ if (dev->parent && dev->parent->driver->child_pre_probe) {
+ ret = dev->parent->driver->child_pre_probe(dev);
+ if (ret)
+ goto fail;
+ }
+
if (drv->ofdata_to_platdata && dev->of_offset >= 0) {
ret = drv->ofdata_to_platdata(dev);
if (ret)
__func__, dev->name);
}
fail:
+ dev->seq = -1;
device_free(dev);
return ret;
goto err_remove;
}
+ if (dev->parent && dev->parent->driver->child_post_remove) {
+ ret = dev->parent->driver->child_post_remove(dev);
+ if (ret) {
+ dm_warn("%s: Device '%s' failed child_post_remove()",
+ __func__, dev->name);
+ }
+ }
+
device_free(dev);
+ dev->seq = -1;
dev->flags &= ~DM_FLAG_ACTIVATED;
- return 0;
+ return ret;
err_remove:
/* We can't put the children back */
return dev->priv;
}
+
+void *dev_get_parentdata(struct udevice *dev)
+{
+ if (!dev) {
+ dm_warn("%s: null device", __func__);
+ return NULL;
+ }
+
+ return dev->parent_priv;
+}
+
+static int device_get_device_tail(struct udevice *dev, int ret,
+ struct udevice **devp)
+{
+ if (ret)
+ return ret;
+
+ ret = device_probe(dev);
+ if (ret)
+ return ret;
+
+ *devp = dev;
+
+ return 0;
+}
+
+int device_get_child(struct udevice *parent, int index, struct udevice **devp)
+{
+ struct udevice *dev;
+
+ list_for_each_entry(dev, &parent->child_head, sibling_node) {
+ if (!index--)
+ return device_get_device_tail(dev, 0, devp);
+ }
+
+ return -ENODEV;
+}
+
+int device_find_child_by_seq(struct udevice *parent, int seq_or_req_seq,
+ bool find_req_seq, struct udevice **devp)
+{
+ struct udevice *dev;
+
+ *devp = NULL;
+ if (seq_or_req_seq == -1)
+ return -ENODEV;
+
+ list_for_each_entry(dev, &parent->child_head, sibling_node) {
+ if ((find_req_seq ? dev->req_seq : dev->seq) ==
+ seq_or_req_seq) {
+ *devp = dev;
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+
+int device_get_child_by_seq(struct udevice *parent, int seq,
+ struct udevice **devp)
+{
+ struct udevice *dev;
+ int ret;
+
+ *devp = NULL;
+ ret = device_find_child_by_seq(parent, seq, false, &dev);
+ if (ret == -ENODEV) {
+ /*
+ * We didn't find it in probed devices. See if there is one
+ * that will request this seq if probed.
+ */
+ ret = device_find_child_by_seq(parent, seq, true, &dev);
+ }
+ return device_get_device_tail(dev, ret, devp);
+}
+
+int device_find_child_by_of_offset(struct udevice *parent, int of_offset,
+ struct udevice **devp)
+{
+ struct udevice *dev;
+
+ *devp = NULL;
+
+ list_for_each_entry(dev, &parent->child_head, sibling_node) {
+ if (dev->of_offset == of_offset) {
+ *devp = dev;
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+
+int device_get_child_by_of_offset(struct udevice *parent, int seq,
+ struct udevice **devp)
+{
+ struct udevice *dev;
+ int ret;
+
+ *devp = NULL;
+ ret = device_find_child_by_of_offset(parent, seq, &dev);
+ return device_get_device_tail(dev, ret, devp);
+}
#include <errno.h>
#include <dm/device.h>
#include <dm/device-internal.h>
+#include <dm/lists.h>
#include <dm/platdata.h>
#include <dm/uclass.h>
#include <dm/util.h>
return NULL;
}
-int lists_bind_drivers(struct udevice *parent)
+int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only)
{
struct driver_info *info =
ll_entry_start(struct driver_info, driver_info);
int ret;
for (entry = info; entry != info + n_ents; entry++) {
- ret = device_bind_by_name(parent, entry, &dev);
- if (ret) {
+ ret = device_bind_by_name(parent, pre_reloc_only, entry, &dev);
+ if (ret && ret != -EPERM) {
dm_warn("No match for driver '%s'\n", entry->name);
if (!result || ret != -ENOENT)
result = ret;
const int n_ents = ll_entry_count(struct driver, driver);
struct driver *entry;
struct udevice *dev;
+ bool found = false;
const char *name;
int result = 0;
- int ret;
+ int ret = 0;
dm_dbg("bind node %s\n", fdt_get_name(blob, offset, NULL));
for (entry = driver; entry != driver + n_ents; entry++) {
ret = driver_check_compatible(blob, offset, entry->of_match);
+ name = fdt_get_name(blob, offset, NULL);
if (ret == -ENOENT) {
continue;
} else if (ret == -ENODEV) {
+ dm_dbg("Device '%s' has no compatible string\n", name);
break;
} else if (ret) {
dm_warn("Device tree error at offset %d\n", offset);
break;
}
- name = fdt_get_name(blob, offset, NULL);
dm_dbg(" - found match at '%s'\n", entry->name);
ret = device_bind(parent, entry, name, NULL, offset, &dev);
if (ret) {
- dm_warn("No match for driver '%s'\n", entry->name);
+ dm_warn("Error binding driver '%s'\n", entry->name);
if (!result || ret != -ENOENT)
result = ret;
+ } else {
+ found = true;
}
+ break;
+ }
+
+ if (!found && !result && ret != -ENODEV) {
+ dm_dbg("No match for node '%s'\n",
+ fdt_get_name(blob, offset, NULL));
}
return result;
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/platdata.h>
+#include <dm/root.h>
#include <dm/uclass.h>
#include <dm/util.h>
#include <linux/list.h>
}
INIT_LIST_HEAD(&DM_UCLASS_ROOT_NON_CONST);
- ret = device_bind_by_name(NULL, &root_info, &DM_ROOT_NON_CONST);
+ ret = device_bind_by_name(NULL, false, &root_info, &DM_ROOT_NON_CONST);
if (ret)
return ret;
+ ret = device_probe(DM_ROOT_NON_CONST);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int dm_uninit(void)
+{
+ device_remove(dm_root());
+ device_unbind(dm_root());
return 0;
}
-int dm_scan_platdata(void)
+int dm_scan_platdata(bool pre_reloc_only)
{
int ret;
- ret = lists_bind_drivers(DM_ROOT_NON_CONST);
+ ret = lists_bind_drivers(DM_ROOT_NON_CONST, pre_reloc_only);
if (ret == -ENOENT) {
dm_warn("Some drivers were not found\n");
ret = 0;
}
#ifdef CONFIG_OF_CONTROL
-int dm_scan_fdt(const void *blob)
+int dm_scan_fdt_node(struct udevice *parent, const void *blob, int offset,
+ bool pre_reloc_only)
{
- int offset = 0;
int ret = 0, err;
- int depth = 0;
- do {
- offset = fdt_next_node(blob, offset, &depth);
- if (offset > 0 && depth == 1) {
- err = lists_bind_fdt(gd->dm_root, blob, offset);
- if (err && !ret)
- ret = err;
- }
- } while (offset > 0);
+ for (offset = fdt_first_subnode(blob, offset);
+ offset > 0;
+ offset = fdt_next_subnode(blob, offset)) {
+ if (pre_reloc_only &&
+ !fdt_getprop(blob, offset, "u-boot,dm-pre-reloc", NULL))
+ continue;
+ err = lists_bind_fdt(parent, blob, offset);
+ if (err && !ret)
+ ret = err;
+ }
if (ret)
dm_warn("Some drivers failed to bind\n");
return ret;
}
+
+int dm_scan_fdt(const void *blob, bool pre_reloc_only)
+{
+ return dm_scan_fdt_node(gd->dm_root, blob, 0, pre_reloc_only);
+}
+#endif
+
+__weak int dm_scan_other(bool pre_reloc_only)
+{
+ return 0;
+}
+
+int dm_init_and_scan(bool pre_reloc_only)
+{
+ int ret;
+
+ ret = dm_init();
+ if (ret) {
+ debug("dm_init() failed: %d\n", ret);
+ return ret;
+ }
+ ret = dm_scan_platdata(pre_reloc_only);
+ if (ret) {
+ debug("dm_scan_platdata() failed: %d\n", ret);
+ return ret;
+ }
+#ifdef CONFIG_OF_CONTROL
+ ret = dm_scan_fdt(gd->fdt_blob, pre_reloc_only);
+ if (ret) {
+ debug("dm_scan_fdt() failed: %d\n", ret);
+ return ret;
+ }
#endif
+ ret = dm_scan_other(pre_reloc_only);
+ if (ret)
+ return ret;
+
+ return 0;
+}
/* This is the root driver - all drivers are children of this */
U_BOOT_DRIVER(root_driver) = {
{
struct uclass *uc;
+ if (!gd->dm_root)
+ return NULL;
/*
* TODO(sjg@chromium.org): Optimise this, perhaps moving the found
* node to the start of the list, or creating a linear array mapping
return -ENODEV;
}
-int uclass_get_device(enum uclass_id id, int index, struct udevice **devp)
+int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq,
+ bool find_req_seq, struct udevice **devp)
{
+ struct uclass *uc;
struct udevice *dev;
int ret;
*devp = NULL;
- ret = uclass_find_device(id, index, &dev);
+ debug("%s: %d %d\n", __func__, find_req_seq, seq_or_req_seq);
+ if (seq_or_req_seq == -1)
+ return -ENODEV;
+ ret = uclass_get(id, &uc);
+ if (ret)
+ return ret;
+
+ list_for_each_entry(dev, &uc->dev_head, uclass_node) {
+ debug(" - %d %d\n", dev->req_seq, dev->seq);
+ if ((find_req_seq ? dev->req_seq : dev->seq) ==
+ seq_or_req_seq) {
+ *devp = dev;
+ debug(" - found\n");
+ return 0;
+ }
+ }
+ debug(" - not found\n");
+
+ return -ENODEV;
+}
+
+static int uclass_find_device_by_of_offset(enum uclass_id id, int node,
+ struct udevice **devp)
+{
+ struct uclass *uc;
+ struct udevice *dev;
+ int ret;
+
+ *devp = NULL;
+ if (node < 0)
+ return -ENODEV;
+ ret = uclass_get(id, &uc);
+ if (ret)
+ return ret;
+
+ list_for_each_entry(dev, &uc->dev_head, uclass_node) {
+ if (dev->of_offset == node) {
+ *devp = dev;
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+
+/**
+ * uclass_get_device_tail() - handle the end of a get_device call
+ *
+ * This handles returning an error or probing a device as needed.
+ *
+ * @dev: Device that needs to be probed
+ * @ret: Error to return. If non-zero then the device is not probed
+ * @devp: Returns the value of 'dev' if there is no error
+ * @return ret, if non-zero, else the result of the device_probe() call
+ */
+static int uclass_get_device_tail(struct udevice *dev, int ret,
+ struct udevice **devp)
+{
if (ret)
return ret;
return 0;
}
+int uclass_get_device(enum uclass_id id, int index, struct udevice **devp)
+{
+ struct udevice *dev;
+ int ret;
+
+ *devp = NULL;
+ ret = uclass_find_device(id, index, &dev);
+ return uclass_get_device_tail(dev, ret, devp);
+}
+
+int uclass_get_device_by_seq(enum uclass_id id, int seq, struct udevice **devp)
+{
+ struct udevice *dev;
+ int ret;
+
+ *devp = NULL;
+ ret = uclass_find_device_by_seq(id, seq, false, &dev);
+ if (ret == -ENODEV) {
+ /*
+ * We didn't find it in probed devices. See if there is one
+ * that will request this seq if probed.
+ */
+ ret = uclass_find_device_by_seq(id, seq, true, &dev);
+ }
+ return uclass_get_device_tail(dev, ret, devp);
+}
+
+int uclass_get_device_by_of_offset(enum uclass_id id, int node,
+ struct udevice **devp)
+{
+ struct udevice *dev;
+ int ret;
+
+ *devp = NULL;
+ ret = uclass_find_device_by_of_offset(id, node, &dev);
+ return uclass_get_device_tail(dev, ret, devp);
+}
+
int uclass_first_device(enum uclass_id id, struct udevice **devp)
{
struct uclass *uc;
return 0;
}
+int uclass_resolve_seq(struct udevice *dev)
+{
+ struct udevice *dup;
+ int seq;
+ int ret;
+
+ assert(dev->seq == -1);
+ ret = uclass_find_device_by_seq(dev->uclass->uc_drv->id, dev->req_seq,
+ false, &dup);
+ if (!ret) {
+ dm_warn("Device '%s': seq %d is in use by '%s'\n",
+ dev->name, dev->req_seq, dup->name);
+ } else if (ret == -ENODEV) {
+ /* Our requested sequence number is available */
+ if (dev->req_seq != -1)
+ return dev->req_seq;
+ } else {
+ return ret;
+ }
+
+ for (seq = 0; seq < DM_MAX_SEQ; seq++) {
+ ret = uclass_find_device_by_seq(dev->uclass->uc_drv->id, seq,
+ false, &dup);
+ if (ret == -ENODEV)
+ break;
+ if (ret)
+ return ret;
+ }
+ return seq;
+}
+
int uclass_post_probe_device(struct udevice *dev)
{
struct uclass_driver *uc_drv = dev->uclass->uc_drv;
free(dev->uclass_priv);
dev->uclass_priv = NULL;
}
+ dev->seq = -1;
return 0;
}
DECLARE_GLOBAL_DATA_PTR;
UCLASS_DRIVER(demo) = {
+ .name = "demo",
.id = UCLASS_DEMO,
};
# SPDX-License-Identifier: GPL-2.0+
#
+ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
+endif
obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
obj-$(CONFIG_TCA642X) += tca642x.o
oby-$(CONFIG_SX151X) += sx151x.o
+obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
--- /dev/null
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * Based on earlier arch/arm/cpu/armv7/sunxi/gpio.c:
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+static int sunxi_gpio_output(u32 pin, u32 val)
+{
+ u32 dat;
+ u32 bank = GPIO_BANK(pin);
+ u32 num = GPIO_NUM(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ dat = readl(&pio->dat);
+ if (val)
+ dat |= 0x1 << num;
+ else
+ dat &= ~(0x1 << num);
+
+ writel(dat, &pio->dat);
+
+ return 0;
+}
+
+static int sunxi_gpio_input(u32 pin)
+{
+ u32 dat;
+ u32 bank = GPIO_BANK(pin);
+ u32 num = GPIO_NUM(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ dat = readl(&pio->dat);
+ dat >>= num;
+
+ return dat & 0x1;
+}
+
+int gpio_request(unsigned gpio, const char *label)
+{
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT);
+
+ return sunxi_gpio_input(gpio);
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT);
+
+ return sunxi_gpio_output(gpio, value);
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ return sunxi_gpio_input(gpio);
+}
+
+int gpio_set_value(unsigned gpio, int value)
+{
+ return sunxi_gpio_output(gpio, value);
+}
+
+int sunxi_name_to_gpio(const char *name)
+{
+ int group = 0;
+ int groupsize = 9 * 32;
+ long pin;
+ char *eptr;
+ if (*name == 'P' || *name == 'p')
+ name++;
+ if (*name >= 'A') {
+ group = *name - (*name > 'a' ? 'a' : 'A');
+ groupsize = 32;
+ name++;
+ }
+
+ pin = simple_strtol(name, &eptr, 10);
+ if (!*name || *eptr)
+ return -1;
+ if (pin < 0 || pin > groupsize || group >= 9)
+ return -1;
+ return group * 32 + pin;
+}
obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
obj-$(CONFIG_DW_I2C) += designware_i2c.o
-obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
+obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
+obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
DECLARE_GLOBAL_DATA_PTR;
-static const struct fsl_i2c *i2c_dev[2] = {
+static const struct fsl_i2c *i2c_dev[4] = {
(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
- (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET)
+ (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
+#endif
+#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
+ (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
+#endif
+#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
+ (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
#endif
};
CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
1)
#endif
+#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
+U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+ fsl_i2c_write, fsl_i2c_set_bus_speed,
+ CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
+ 2)
+#endif
+#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
+U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+ fsl_i2c_write, fsl_i2c_set_bus_speed,
+ CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
+ 3)
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <gdsys_fpga.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ I2CINT_ERROR_EV = 1 << 13,
+ I2CINT_TRANSMIT_EV = 1 << 14,
+ I2CINT_RECEIVE_EV = 1 << 15,
+};
+
+enum {
+ I2CMB_WRITE = 1 << 10,
+ I2CMB_2BYTE = 1 << 11,
+ I2CMB_HOLD_BUS = 1 << 13,
+ I2CMB_NATIVE = 2 << 14,
+};
+
+static int wait_for_int(bool read)
+{
+ u16 val;
+ unsigned int ctr = 0;
+
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
+ while (!(val & (I2CINT_ERROR_EV
+ | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
+ udelay(10);
+ if (ctr++ > 5000) {
+ return 1;
+ }
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
+ }
+
+ return (val & I2CINT_ERROR_EV) ? 1 : 0;
+}
+
+static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
+ bool is_last)
+{
+ u16 val;
+
+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, I2CINT_ERROR_EV
+ | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV);
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
+
+ if (!read && len) {
+ val = buffer[0];
+
+ if (len > 1)
+ val |= buffer[1] << 8;
+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox_ext, val);
+ }
+
+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox,
+ I2CMB_NATIVE
+ | (read ? 0 : I2CMB_WRITE)
+ | (chip << 1)
+ | ((len > 1) ? I2CMB_2BYTE : 0)
+ | (is_last ? 0 : I2CMB_HOLD_BUS));
+
+ if (wait_for_int(read))
+ return 1;
+
+ if (read) {
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.read_mailbox_ext, &val);
+ buffer[0] = val & 0xff;
+ if (len > 1)
+ buffer[1] = val >> 8;
+ }
+
+ return 0;
+}
+
+static int ihs_i2c_address(uchar chip, uint addr, int alen, bool hold_bus)
+{
+ int shift = (alen-1) * 8;
+
+ while (alen) {
+ int transfer = MIN(alen, 2);
+ uchar buf[2];
+ bool is_last = alen <= transfer;
+
+ buf[0] = addr >> shift;
+ if (alen > 1)
+ buf[1] = addr >> (shift - 8);
+
+ if (ihs_i2c_transfer(chip, buf, transfer, false,
+ hold_bus ? false : is_last))
+ return 1;
+
+ shift -= 16;
+ alen -= transfer;
+ }
+
+ return 0;
+}
+
+static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len, bool read)
+{
+ if (len <= 0)
+ return 1;
+
+ if (ihs_i2c_address(chip, addr, alen, !read))
+ return 1;
+
+ while (len) {
+ int transfer = MIN(len, 2);
+
+ if (ihs_i2c_transfer(chip, buffer, transfer, read,
+ len <= transfer))
+ return 1;
+
+ buffer += transfer;
+ addr += transfer;
+ len -= transfer;
+ }
+
+ return 0;
+}
+
+
+static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
+{
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+ /*
+ * Call board specific i2c bus reset routine before accessing the
+ * environment, which might be in a chip on that bus. For details
+ * about this problem see doc/I2C_Edge_Conditions.
+ */
+ i2c_init_board();
+#endif
+}
+
+static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
+{
+ uchar buffer[2];
+
+ if (ihs_i2c_transfer(chip, buffer, 0, true, true))
+ return 1;
+
+ return 0;
+}
+
+static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
+{
+ return ihs_i2c_access(adap, chip, addr, alen, buffer, len, true);
+}
+
+static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
+{
+ return ihs_i2c_access(adap, chip, addr, alen, buffer, len, false);
+}
+
+static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
+{
+ if (speed != adap->speed)
+ return 1;
+ return speed;
+}
+
+/*
+ * Register IHS i2c adapters
+ */
+#ifdef CONFIG_SYS_I2C_IHS_CH0
+U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
+ ihs_i2c_read, ihs_i2c_write,
+ ihs_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_IHS_SPEED_0,
+ CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
+#endif
+#ifdef CONFIG_SYS_I2C_IHS_CH1
+U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
+ ihs_i2c_read, ihs_i2c_write,
+ ihs_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_IHS_SPEED_1,
+ CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
+#endif
+#ifdef CONFIG_SYS_I2C_IHS_CH2
+U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
+ ihs_i2c_read, ihs_i2c_write,
+ ihs_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_IHS_SPEED_2,
+ CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
+#endif
+#ifdef CONFIG_SYS_I2C_IHS_CH3
+U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
+ ihs_i2c_read, ihs_i2c_write,
+ ihs_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_IHS_SPEED_3,
+ CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
+#endif
#include <asm/arch/orion5x.h>
#elif defined(CONFIG_KIRKWOOD)
#include <asm/arch/kirkwood.h>
+#elif defined(CONFIG_SUNXI)
+#include <asm/arch/i2c.h>
#else
#error Driver mvtwsi not supported by SoC or board
#endif
* TWSI register structure
*/
+#ifdef CONFIG_SUNXI
+
+struct mvtwsi_registers {
+ u32 slave_address;
+ u32 xtnd_slave_addr;
+ u32 data;
+ u32 control;
+ u32 status;
+ u32 baudrate;
+ u32 soft_reset;
+};
+
+#else
+
struct mvtwsi_registers {
u32 slave_address;
u32 data;
u32 soft_reset;
};
+#endif
+
/*
* Control register fields
*/
/*
* Reset controller.
- * Called at end of i2c_init unsuccessful i2c transactions.
* Controller reset also resets the baud rate and slave address, so
- * re-establish them.
+ * they must be re-established afterwards.
*/
-static void twsi_reset(u8 baud_rate, u8 slave_address)
+static void twsi_reset(struct i2c_adapter *adap)
{
/* ensure controller will be enabled by any twsi*() function */
twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
writel(0, &twsi->soft_reset);
/* wait 2 ms -- this is what the Marvell LSP does */
udelay(20000);
- /* set baud rate */
- writel(baud_rate, &twsi->baudrate);
- /* set slave address even though we don't use it */
- writel(slave_address, &twsi->slave_address);
- writel(0, &twsi->xtnd_slave_addr);
- /* assert STOP but don't care for the result */
- (void) twsi_stop(0);
}
/*
* I2C init called by cmd_i2c when doing 'i2c reset'.
* Sets baud to the highest possible value not exceeding requested one.
*/
-void i2c_init(int requested_speed, int slaveadd)
+static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int requested_speed)
{
- int tmp_speed, highest_speed, n, m;
- int baud = 0x44; /* baudrate at controller reset */
+ unsigned int tmp_speed, highest_speed, n, m;
+ unsigned int baud = 0x44; /* baudrate at controller reset */
/* use actual speed to collect progressively higher values */
highest_speed = 0;
}
}
}
+ writel(baud, &twsi->baudrate);
+ return 0;
+}
+
+static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+{
/* reset controller */
- twsi_reset(baud, slaveadd);
+ twsi_reset(adap);
+ /* set speed */
+ twsi_i2c_set_bus_speed(adap, speed);
+ /* set slave address even though we don't use it */
+ writel(slaveadd, &twsi->slave_address);
+ writel(0, &twsi->xtnd_slave_addr);
+ /* assert STOP but don't care for the result */
+ (void) twsi_stop(0);
}
/*
* I2C probe called by cmd_i2c when doing 'i2c probe'.
* Begin read, nak data byte, end.
*/
-int i2c_probe(uchar chip)
+static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
u8 dummy_byte;
int status;
* cmd_eeprom, so we have to choose here, and for the moment that'll be
* a repeated start without a preceding stop.
*/
-int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
+static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *data, int length)
{
int status;
/* begin i2c write to send the address bytes */
- status = i2c_begin(MVTWSI_STATUS_START, (dev << 1));
+ status = i2c_begin(MVTWSI_STATUS_START, (chip << 1));
/* send addr bytes */
while ((status == 0) && alen--)
status = twsi_send(addr >> (8*alen),
/* begin i2c read to receive eeprom data bytes */
if (status == 0)
status = i2c_begin(
- MVTWSI_STATUS_REPEATED_START, (dev << 1) | 1);
+ MVTWSI_STATUS_REPEATED_START, (chip << 1) | 1);
/* prepare ACK if at least one byte must be received */
if (length > 0)
twsi_control_flags |= MVTWSI_CONTROL_ACK;
* I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
* Begin write, send address byte(s), send data bytes, end.
*/
-int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
+static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *data, int length)
{
int status;
/* begin i2c write to send the eeprom adress bytes then data bytes */
- status = i2c_begin(MVTWSI_STATUS_START, (dev << 1));
+ status = i2c_begin(MVTWSI_STATUS_START, (chip << 1));
/* send addr bytes */
while ((status == 0) && alen--)
status = twsi_send(addr >> (8*alen),
return status;
}
-/*
- * Bus set routine: we only support bus 0.
- */
-int i2c_set_bus_num(unsigned int bus)
-{
- if (bus > 0) {
- return -1;
- }
- return 0;
-}
-
-/*
- * Bus get routine: hard-return bus 0.
- */
-unsigned int i2c_get_bus_num(void)
-{
- return 0;
-}
+U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
+ twsi_i2c_read, twsi_i2c_write,
+ twsi_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
return 0;
}
+
+static void omap24_i2c_deblock(struct i2c_adapter *adap)
+{
+ struct i2c *i2c_base = omap24_get_base(adap);
+ int i;
+ u16 systest;
+ u16 orgsystest;
+
+ /* set test mode ST_EN = 1 */
+ orgsystest = readw(&i2c_base->systest);
+ systest = orgsystest;
+ /* enable testmode */
+ systest |= I2C_SYSTEST_ST_EN;
+ writew(systest, &i2c_base->systest);
+ systest &= ~I2C_SYSTEST_TMODE_MASK;
+ systest |= 3 << I2C_SYSTEST_TMODE_SHIFT;
+ writew(systest, &i2c_base->systest);
+
+ /* set SCL, SDA = 1 */
+ systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
+ writew(systest, &i2c_base->systest);
+ udelay(10);
+
+ /* toggle scl 9 clocks */
+ for (i = 0; i < 9; i++) {
+ /* SCL = 0 */
+ systest &= ~I2C_SYSTEST_SCL_O;
+ writew(systest, &i2c_base->systest);
+ udelay(10);
+ /* SCL = 1 */
+ systest |= I2C_SYSTEST_SCL_O;
+ writew(systest, &i2c_base->systest);
+ udelay(10);
+ }
+
+ /* send stop */
+ systest &= ~I2C_SYSTEST_SDA_O;
+ writew(systest, &i2c_base->systest);
+ udelay(10);
+ systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
+ writew(systest, &i2c_base->systest);
+ udelay(10);
+
+ /* restore original mode */
+ writew(orgsystest, &i2c_base->systest);
+}
+
static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
struct i2c *i2c_base = omap24_get_base(adap);
int timeout = I2C_TIMEOUT;
+ int deblock = 1;
+retry:
if (readw(&i2c_base->con) & I2C_CON_EN) {
writew(0, &i2c_base->con);
udelay(50000);
udelay(1000);
flush_fifo(adap);
writew(0xFFFF, &i2c_base->stat);
+
+ /* Handle possible failed I2C state */
+ if (wait_for_bb(adap))
+ if (deblock == 1) {
+ omap24_i2c_deblock(adap);
+ deblock = 0;
+ goto retry;
+ }
}
static void flush_fifo(struct i2c_adapter *adap)
static void send_packet_headers(
struct i2c_bus *i2c_bus,
struct i2c_trans_info *trans,
- u32 packet_id)
+ u32 packet_id,
+ bool end_with_repeated_start)
{
u32 data;
/* Enable Read if it is not a write transaction */
if (!(trans->flags & I2C_IS_WRITE))
data |= PKT_HDR3_READ_MODE_MASK;
+ if (end_with_repeated_start)
+ data |= PKT_HDR3_REPEAT_START_MASK;
/* Write I2C specific header */
writel(data, &i2c_bus->control->tx_fifo);
int_status = readl(&control->int_status);
writel(int_status, &control->int_status);
- send_packet_headers(i2c_bus, trans, 1);
+ send_packet_headers(i2c_bus, trans, 1,
+ trans->flags & I2C_USE_REPEATED_START);
words = DIV_ROUND_UP(trans->num_bytes, 4);
last_bytes = trans->num_bytes & 3;
if (is_write) {
/* deal with word alignment */
- if ((unsigned)dptr & 3) {
+ if ((words == 1) && last_bytes) {
+ local = 0;
+ memcpy(&local, dptr, last_bytes);
+ } else if ((unsigned)dptr & 3) {
memcpy(&local, dptr, sizeof(u32));
- writel(local, &control->tx_fifo);
- debug("pkt data sent (0x%x)\n", local);
} else {
- writel(*wptr, &control->tx_fifo);
- debug("pkt data sent (0x%x)\n", *wptr);
+ local = *wptr;
}
+ writel(local, &control->tx_fifo);
+ debug("pkt data sent (0x%x)\n", local);
if (!wait_for_tx_fifo_empty(control)) {
error = -1;
goto exit;
}
static int tegra_i2c_write_data(struct i2c_bus *bus, u32 addr, u8 *data,
- u32 len)
+ u32 len, bool end_with_repeated_start)
{
int error;
struct i2c_trans_info trans_info;
trans_info.address = addr;
trans_info.buf = data;
trans_info.flags = I2C_IS_WRITE;
+ if (end_with_repeated_start)
+ trans_info.flags |= I2C_USE_REPEATED_START;
trans_info.num_bytes = len;
trans_info.is_10bit_address = 0;
}
/* i2c write version without the register address */
-int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len)
+int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len,
+ bool end_with_repeated_start)
{
int rc;
debug("\n");
/* Shift 7-bit address over for lower-level i2c functions */
- rc = tegra_i2c_write_data(bus, chip << 1, buffer, len);
+ rc = tegra_i2c_write_data(bus, chip << 1, buffer, len,
+ end_with_repeated_start);
if (rc)
debug("i2c_write_data(): rc=%d\n", rc);
if (!bus)
return 1;
reg = 0;
- rc = i2c_write_data(bus, chip, ®, 1);
+ rc = i2c_write_data(bus, chip, ®, 1, false);
if (rc) {
debug("Error probing 0x%x.\n", chip);
return 1;
uint offset;
int i;
- debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n",
- chip, addr, len);
+ debug("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x len=0x%x\n",
+ chip, addr, alen, len);
bus = tegra_i2c_get_bus(adap);
if (!bus)
return 1;
data[alen - i - 1] =
(addr + offset) >> (8 * i);
}
- if (i2c_write_data(bus, chip, data, alen)) {
+ if (i2c_write_data(bus, chip, data, alen, true)) {
debug("i2c_read: error sending (0x%x)\n",
addr);
return 1;
uint offset;
int i;
- debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n",
- chip, addr, len);
+ debug("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x len=0x%x\n",
+ chip, addr, alen, len);
bus = tegra_i2c_get_bus(adap);
if (!bus)
return 1;
for (i = 0; i < alen; i++)
data[alen - i - 1] = (addr + offset) >> (8 * i);
data[alen] = buffer[offset];
- if (i2c_write_data(bus, chip, data, alen + 1)) {
+ if (i2c_write_data(bus, chip, data, alen + 1, false)) {
debug("i2c_write: error sending (0x%x)\n", addr);
return 1;
}
*
* @return 0 if no keys available, 1 if keys are available
*/
-static int kbd_tstc(void)
+static int kbd_tstc(struct stdio_dev *dev)
{
/* Just get input to do this for us */
return config.inited ? input_tstc(&config.input) : 0;
*
* @return ASCII key code, or 0 if no key, or -1 if error
*/
-static int kbd_getc(void)
+static int kbd_getc(struct stdio_dev *dev)
{
/* Just get input to do this for us */
return config.inited ? input_getc(&config.input) : 0;
*
* @return 0 if ok, -1 on error
*/
-static int cros_ec_init_keyboard(void)
+static int cros_ec_init_keyboard(struct stdio_dev *dev)
{
const void *blob = gd->fdt_blob;
int node;
* i8042_tstc - test if keyboard input is available
* option: cursor blinking if called in a loop
*/
-int i8042_tstc(void)
+int i8042_tstc(struct stdio_dev *dev)
{
unsigned char scan_code = 0;
* i8042_getc - wait till keyboard input is available
* option: turn on/off cursor while waiting
*/
-int i8042_getc(void)
+int i8042_getc(struct stdio_dev *dev)
{
int ret_chr;
unsigned char scan_code;
}
/* test if a character is in the queue */
-static int kbd_testc(void)
+static int kbd_testc(struct stdio_dev *dev)
{
#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
/* no ISR is used, so received chars must be polled */
}
/* gets the character from the queue */
-static int kbd_getc(void)
+static int kbd_getc(struct stdio_dev *dev)
{
char c;
while(in_pointer==out_pointer) {
memset (&kbddev, 0, sizeof(kbddev));
strcpy(kbddev.name, DEVNAME);
kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
- kbddev.putc = NULL ;
- kbddev.puts = NULL ;
kbddev.getc = kbd_getc ;
kbddev.tstc = kbd_testc ;
*
* @return 0 if no keys available, 1 if keys are available
*/
-static int kbd_tstc(void)
+static int kbd_tstc(struct stdio_dev *dev)
{
/* Just get input to do this for us */
return input_tstc(&config.input);
*
* @return ASCII key code, or 0 if no key, or -1 if error
*/
-static int kbd_getc(void)
+static int kbd_getc(struct stdio_dev *dev)
{
/* Just get input to do this for us */
return input_getc(&config.input);
*
* @return 0 if ok, -ve on error
*/
-static int init_tegra_keyboard(void)
+static int init_tegra_keyboard(struct stdio_dev *dev)
{
/* check if already created */
if (config.created)
static struct cbmem_console *cbmem_console_p;
-void cbmemc_putc(char data)
+void cbmemc_putc(struct stdio_dev *dev, char data)
{
int cursor;
cbmem_console_p->buffer_body[cursor] = data;
}
-void cbmemc_puts(const char *str)
+void cbmemc_puts(struct stdio_dev *dev, const char *str)
{
char c;
while ((c = *str++) != 0)
- cbmemc_putc(c);
+ cbmemc_putc(dev, c);
}
int cbmemc_init(void)
static struct list_head mmc_devices;
static int cur_dev_num = -1;
-int __weak board_mmc_getwp(struct mmc *mmc)
+__weak int board_mmc_getwp(struct mmc *mmc)
{
return -1;
}
return wp;
}
-int __board_mmc_getcd(struct mmc *mmc) {
+__weak int board_mmc_getcd(struct mmc *mmc)
+{
return -1;
}
-int board_mmc_getcd(struct mmc *mmc)__attribute__((weak,
- alias("__board_mmc_getcd")));
-
int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
int ret;
return 0;
}
-int mmc_send_op_cond(struct mmc *mmc)
+static int mmc_send_op_cond(struct mmc *mmc)
{
struct mmc_cmd cmd;
int err, i;
return IN_PROGRESS;
}
-int mmc_complete_op_cond(struct mmc *mmc)
+static int mmc_complete_op_cond(struct mmc *mmc)
{
struct mmc_cmd cmd;
int timeout = 1000;
return 0;
}
-/*
- * CPU and board-specific MMC initializations. Aliased function
- * signals caller to move on
- */
-static int __def_mmc_init(bd_t *bis)
+/* CPU-specific MMC initializations */
+__weak int cpu_mmc_init(bd_t *bis)
{
return -1;
}
-int cpu_mmc_init(bd_t *bis) __attribute__((weak, alias("__def_mmc_init")));
-int board_mmc_init(bd_t *bis) __attribute__((weak, alias("__def_mmc_init")));
+/* board-specific MMC initializations. */
+__weak int board_mmc_init(bd_t *bis)
+{
+ return -1;
+}
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
}
#endif
-unsigned char mmc_board_init(struct mmc *mmc)
+static unsigned char mmc_board_init(struct mmc *mmc)
{
#if defined(CONFIG_OMAP34XX)
t2_t *t2_base = (t2_t *)T2_BASE;
#include <asm/arch/cpu.h>
#include <asm/arch/mmc.h>
-struct sunxi_mmc_des {
- u32 reserved1_1:1;
- u32 dic:1; /* disable interrupt on completion */
- u32 last_des:1; /* 1-this data buffer is the last buffer */
- u32 first_des:1; /* 1-data buffer is the first buffer,
- 0-data buffer contained in the next
- descriptor is 1st buffer */
- u32 des_chain:1; /* 1-the 2nd address in the descriptor is the
- next descriptor address */
- u32 end_of_ring:1; /* 1-last descriptor flag when using dual
- data buffer in descriptor */
- u32 reserved1_2:24;
- u32 card_err_sum:1; /* transfer error flag */
- u32 own:1; /* des owner:1-idma owns it, 0-host owns it */
-#define SDXC_DES_NUM_SHIFT 16
-#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT)
- u32 data_buf1_sz:16;
- u32 data_buf2_sz:16;
- u32 buf_addr_ptr1;
- u32 buf_addr_ptr2;
-};
-
struct sunxi_mmc_host {
unsigned mmc_no;
uint32_t *mclkreg;
/* Reset controller */
writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
+ udelay(1000);
return 0;
}
unsigned timeout_msecs = 2000;
unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
+ /* Always read / write data through the CPU */
+ setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
+
for (i = 0; i < (byte_cnt >> 2); i++) {
while (readl(&mmchost->reg->status) & status_bit) {
if (!timeout_msecs--)
return 0;
}
-static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data)
-{
- struct sunxi_mmc_host *mmchost = mmc->priv;
- unsigned byte_cnt = data->blocksize * data->blocks;
- unsigned char *buff;
- unsigned des_idx = 0;
- unsigned buff_frag_num =
- (byte_cnt + SDXC_DES_BUFFER_MAX_LEN - 1) >> SDXC_DES_NUM_SHIFT;
- unsigned remain;
- unsigned i, rval;
- ALLOC_CACHE_ALIGN_BUFFER(struct sunxi_mmc_des, pdes, buff_frag_num);
-
- buff = data->flags & MMC_DATA_READ ?
- (unsigned char *)data->dest : (unsigned char *)data->src;
- remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1);
-
- flush_cache((unsigned long)buff, (unsigned long)byte_cnt);
- for (i = 0; i < buff_frag_num; i++, des_idx++) {
- memset((void *)&pdes[des_idx], 0, sizeof(struct sunxi_mmc_des));
- pdes[des_idx].des_chain = 1;
- pdes[des_idx].own = 1;
- pdes[des_idx].dic = 1;
- if (buff_frag_num > 1 && i != buff_frag_num - 1)
- pdes[des_idx].data_buf1_sz = 0; /* 0 == max_len */
- else
- pdes[des_idx].data_buf1_sz = remain;
-
- pdes[des_idx].buf_addr_ptr1 =
- (u32) buff + i * SDXC_DES_BUFFER_MAX_LEN;
- if (i == 0)
- pdes[des_idx].first_des = 1;
-
- if (i == buff_frag_num - 1) {
- pdes[des_idx].dic = 0;
- pdes[des_idx].last_des = 1;
- pdes[des_idx].end_of_ring = 1;
- pdes[des_idx].buf_addr_ptr2 = 0;
- } else {
- pdes[des_idx].buf_addr_ptr2 = (u32)&pdes[des_idx + 1];
- }
- }
- flush_cache((unsigned long)pdes,
- sizeof(struct sunxi_mmc_des) * (des_idx + 1));
-
- rval = readl(&mmchost->reg->gctrl);
- /* Enable DMA */
- writel(rval | SUNXI_MMC_GCTRL_DMA_RESET | SUNXI_MMC_GCTRL_DMA_ENABLE,
- &mmchost->reg->gctrl);
- /* Reset iDMA */
- writel(SUNXI_MMC_IDMAC_RESET, &mmchost->reg->dmac);
- /* Enable iDMA */
- writel(SUNXI_MMC_IDMAC_FIXBURST | SUNXI_MMC_IDMAC_ENABLE,
- &mmchost->reg->dmac);
- rval = readl(&mmchost->reg->idie) &
- ~(SUNXI_MMC_IDIE_TXIRQ|SUNXI_MMC_IDIE_RXIRQ);
- if (data->flags & MMC_DATA_WRITE)
- rval |= SUNXI_MMC_IDIE_TXIRQ;
- else
- rval |= SUNXI_MMC_IDIE_RXIRQ;
- writel(rval, &mmchost->reg->idie);
- writel((u32) pdes, &mmchost->reg->dlba);
- writel((0x2 << 28) | (0x7 << 16) | (0x01 << 3),
- &mmchost->reg->ftrglevel);
-
- return 0;
-}
-
-static void mmc_enable_dma_accesses(struct mmc *mmc, int dma)
-{
- struct sunxi_mmc_host *mmchost = mmc->priv;
-
- unsigned int gctrl = readl(&mmchost->reg->gctrl);
- if (dma)
- gctrl &= ~SUNXI_MMC_GCTRL_ACCESS_BY_AHB;
- else
- gctrl |= SUNXI_MMC_GCTRL_ACCESS_BY_AHB;
- writel(gctrl, &mmchost->reg->gctrl);
-}
-
static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
unsigned int done_bit, const char *what)
{
unsigned int timeout_msecs;
int error = 0;
unsigned int status = 0;
- unsigned int usedma = 0;
unsigned int bytecnt = 0;
if (mmchost->fatal_err)
bytecnt = data->blocksize * data->blocks;
debug("trans data %d bytes\n", bytecnt);
-#if defined(CONFIG_MMC_SUNXI_USE_DMA) && !defined(CONFIG_SPL_BUILD)
- if (bytecnt > 64) {
-#else
- if (0) {
-#endif
- usedma = 1;
- mmc_enable_dma_accesses(mmc, 1);
- ret = mmc_trans_data_by_dma(mmc, data);
- writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
- } else {
- mmc_enable_dma_accesses(mmc, 0);
- writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
- ret = mmc_trans_data_by_cpu(mmc, data);
- }
+ writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
+ ret = mmc_trans_data_by_cpu(mmc, data);
if (ret) {
error = readl(&mmchost->reg->rint) & \
SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
goto out;
if (data) {
- timeout_msecs = usedma ? 120 * bytecnt : 120;
+ timeout_msecs = 120;
debug("cacl timeout %x msec\n", timeout_msecs);
error = mmc_rint_wait(mmc, timeout_msecs,
data->blocks > 1 ?
debug("mmc resp 0x%08x\n", cmd->response[0]);
}
out:
- if (data && usedma) {
- /* IDMASTAREG
- * IDST[0] : idma tx int
- * IDST[1] : idma rx int
- * IDST[2] : idma fatal bus error
- * IDST[4] : idma descriptor invalid
- * IDST[5] : idma error summary
- * IDST[8] : idma normal interrupt sumary
- * IDST[9] : idma abnormal interrupt sumary
- */
- status = readl(&mmchost->reg->idst);
- writel(status, &mmchost->reg->idst);
- writel(0, &mmchost->reg->idie);
- writel(0, &mmchost->reg->dmac);
- writel(readl(&mmchost->reg->gctrl) & ~SUNXI_MMC_GCTRL_DMA_ENABLE,
- &mmchost->reg->gctrl);
- }
if (error < 0) {
writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
mmc_update_clk(mmc);
#endif /* CONFIG_SYS_FLASH_QUIET_TEST */
}
#ifdef CONFIG_SYS_FLASH_PROTECTION
- else if ((s != NULL) && (strcmp(s, "yes") == 0)) {
+ else if (strcmp(s, "yes") == 0) {
/*
* Only the U-Boot image and it's environment
* is protected, all other sectors are
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
+obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o
obj-$(CONFIG_ENC28J60) += enc28j60.o
obj-$(CONFIG_EP93XX) += ep93xx_eth.o
obj-$(CONFIG_ETHOC) += ethoc.o
obj-$(CONFIG_SH_ETHER) += sh_eth.o
obj-$(CONFIG_SMC91111) += smc91111.o
obj-$(CONFIG_SMC911X) += smc911x.o
-obj-$(CONFIG_SUNXI_WEMAC) += sunxi_wemac.o
obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
}
}
-static int nc_start(void)
+static int nc_start(struct stdio_dev *dev)
{
int retval;
return 0;
}
-static void nc_putc(char c)
+static void nc_putc(struct stdio_dev *dev, char c)
{
if (output_recursion)
return;
output_recursion = 0;
}
-static void nc_puts(const char *s)
+static void nc_puts(struct stdio_dev *dev, const char *s)
{
int len;
output_recursion = 0;
}
-static int nc_getc(void)
+static int nc_getc(struct stdio_dev *dev)
{
uchar c;
return c;
}
-static int nc_tstc(void)
+static int nc_tstc(struct stdio_dev *dev)
{
struct eth_device *eth;
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+ defined(CONFIG_R8A7794)
sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
#endif
/* Configure phy */
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(eth, 1, RTRATE);
#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
- defined(CONFIG_R8A7791)
+ defined(CONFIG_R8A7791) || defined(CONFIG_R8A7794)
val = ECMR_RTM;
#endif
} else if (phy->speed == 10) {
#elif defined(CONFIG_R8A7740)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR 0xE9A00000
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+ defined(CONFIG_R8A7794)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xEE700200
#elif defined(CONFIG_R7S72100)
ECMR_PRM = 0x00000001,
#ifdef CONFIG_CPU_SH7724
ECMR_RTM = 0x00000010,
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+ defined(CONFIG_R8A7794)
ECMR_RTM = 0x00000004,
#endif
/*
- * sunxi_wemac.c -- Allwinner A10 ethernet driver
+ * sunxi_emac.c -- Allwinner A10 ethernet driver
*
* (C) Copyright 2012, Stefan Roese <sr@denx.de>
*
*/
#include <common.h>
+#include <linux/err.h>
#include <malloc.h>
-#include <net.h>
#include <miiphy.h>
-#include <linux/err.h>
+#include <net.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
/* EMAC register */
-struct wemac_regs {
+struct emac_regs {
u32 ctl; /* 0x00 */
u32 tx_mode; /* 0x04 */
u32 tx_flow; /* 0x08 */
u32 tx_pl1; /* 0x1c */
u32 tx_sta; /* 0x20 */
u32 tx_io_data; /* 0x24 */
- u32 tx_io_data1; /* 0x28 */
+ u32 tx_io_data1;/* 0x28 */
u32 tx_tsvl0; /* 0x2c */
u32 tx_tsvh0; /* 0x30 */
u32 tx_tsvl1; /* 0x34 */
#define EMAC_MAC_IPGT 0x15
-#define EMAC_MAC_NBTB_IPG1 0xC
+#define EMAC_MAC_NBTB_IPG1 0xc
#define EMAC_MAC_NBTB_IPG2 0x12
#define EMAC_MAC_CW 0x37
-#define EMAC_MAC_RM 0xF
+#define EMAC_MAC_RM 0xf
#define EMAC_MAC_MFL 0x0600
/* Receive status */
-#define EMAC_CRCERR (1 << 4)
-#define EMAC_LENERR (3 << 5)
+#define EMAC_CRCERR (0x1 << 4)
+#define EMAC_LENERR (0x3 << 5)
#define DMA_CPU_TRRESHOLD 2000
-struct wemac_eth_dev {
+struct emac_eth_dev {
u32 speed;
u32 duplex;
u32 phy_configured;
int link_printed;
};
-struct wemac_rxhdr {
+struct emac_rxhdr {
s16 rx_len;
u16 rx_status;
};
-static void wemac_inblk_32bit(void *reg, void *data, int count)
+static void emac_inblk_32bit(void *reg, void *data, int count)
{
int cnt = (count + 3) >> 2;
}
}
-static void wemac_outblk_32bit(void *reg, void *data, int count)
+static void emac_outblk_32bit(void *reg, void *data, int count)
{
int cnt = (count + 3) >> 2;
}
}
-/*
- * Read a word from phyxcer
- */
-static int wemac_phy_read(const char *devname, unsigned char addr,
+/* Read a word from phyxcer */
+static int emac_phy_read(const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
- struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
+ struct emac_regs *regs = (struct emac_regs *)dev->iobase;
/* issue the phy address and reg */
writel(addr << 8 | reg, ®s->mac_madr);
return 0;
}
-/*
- * Write a word to phyxcer
- */
-static int wemac_phy_write(const char *devname, unsigned char addr,
+/* Write a word to phyxcer */
+static int emac_phy_write(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
- struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
+ struct emac_regs *regs = (struct emac_regs *)dev->iobase;
/* issue the phy address and reg */
writel(addr << 8 | reg, ®s->mac_madr);
static void emac_setup(struct eth_device *dev)
{
- struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
+ struct emac_regs *regs = (struct emac_regs *)dev->iobase;
u32 reg_val;
u16 phy_val;
u32 duplex_flag;
writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0);
/* Set MAC CTL1 */
- wemac_phy_read(dev->name, 1, 0, &phy_val);
+ emac_phy_read(dev->name, 1, 0, &phy_val);
debug("PHY SETUP, reg 0 value: %x\n", phy_val);
duplex_flag = !!(phy_val & (1 << 8));
writel(EMAC_MAC_MFL, ®s->mac_maxf);
}
-static void wemac_reset(struct eth_device *dev)
+static void emac_reset(struct eth_device *dev)
{
- struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
+ struct emac_regs *regs = (struct emac_regs *)dev->iobase;
debug("resetting device\n");
udelay(200);
}
-static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
+static int sunxi_emac_eth_init(struct eth_device *dev, bd_t *bd)
{
- struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
- struct wemac_eth_dev *priv = dev->priv;
+ struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+ struct emac_eth_dev *priv = dev->priv;
u16 phy_reg;
/* Init EMAC */
/* Init MAC */
/* Soft reset MAC */
- clrbits_le32(®s->mac_ctl0, 1 << 15);
-
- /* Set MII clock */
- clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
+ clrbits_le32(®s->mac_ctl0, 0x1 << 15);
/* Clear RX counter */
writel(0x0, ®s->rx_fbc);
mdelay(1);
- wemac_reset(dev);
+ emac_reset(dev);
/* PHY POWER UP */
- wemac_phy_read(dev->name, 1, 0, &phy_reg);
- wemac_phy_write(dev->name, 1, 0, phy_reg & (~(1 << 11)));
+ emac_phy_read(dev->name, 1, 0, &phy_reg);
+ emac_phy_write(dev->name, 1, 0, phy_reg & (~(0x1 << 11)));
mdelay(1);
- wemac_phy_read(dev->name, 1, 0, &phy_reg);
+ emac_phy_read(dev->name, 1, 0, &phy_reg);
priv->speed = miiphy_speed(dev->name, 0);
priv->duplex = miiphy_duplex(dev->name, 0);
/* Set EMAC SPEED depend on PHY */
clrsetbits_le32(®s->mac_supp, 1 << 8,
- ((phy_reg & (1 << 13)) >> 13) << 8);
+ ((phy_reg & (0x1 << 13)) >> 13) << 8);
/* Set duplex depend on phy */
clrsetbits_le32(®s->mac_ctl1, 1 << 0,
- ((phy_reg & (1 << 8)) >> 8) << 0);
+ ((phy_reg & (0x1 << 8)) >> 8) << 0);
/* Enable RX/TX */
setbits_le32(®s->ctl, 0x7);
return 0;
}
-static void sunxi_wemac_eth_halt(struct eth_device *dev)
+static void sunxi_emac_eth_halt(struct eth_device *dev)
{
/* Nothing to do here */
}
-static int sunxi_wemac_eth_recv(struct eth_device *dev)
+static int sunxi_emac_eth_recv(struct eth_device *dev)
{
- struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
- struct wemac_rxhdr rxhdr;
+ struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+ struct emac_rxhdr rxhdr;
u32 rxcount;
u32 reg_val;
int rx_len;
/* Check packet ready or not */
- /*
- * Race warning: The first packet might arrive with
+ /* Race warning: The first packet might arrive with
* the interrupts disabled, but the second will fix
*/
rxcount = readl(®s->rx_fbc);
reg_val = readl(®s->rx_io_data);
if (reg_val != 0x0143414d) {
/* Disable RX */
- clrbits_le32(®s->ctl, 1 << 2);
+ clrbits_le32(®s->ctl, 0x1 << 2);
/* Flush RX FIFO */
- setbits_le32(®s->rx_ctl, 1 << 3);
- while (readl(®s->rx_ctl) & (1 << 3))
+ setbits_le32(®s->rx_ctl, 0x1 << 3);
+ while (readl(®s->rx_ctl) & (0x1 << 3))
;
/* Enable RX */
- setbits_le32(®s->ctl, 1 << 2);
+ setbits_le32(®s->ctl, 0x1 << 2);
return 0;
}
- /*
- * A packet ready now
+ /* A packet ready now
* Get status/length
*/
good_packet = 1;
- wemac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr));
+ emac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr));
rx_len = rxhdr.rx_len;
rx_status = rxhdr.rx_status;
printf("length error\n");
}
- /* Move data from WEMAC */
+ /* Move data from EMAC */
if (good_packet) {
if (rx_len > DMA_CPU_TRRESHOLD) {
printf("Received packet is too big (len=%d)\n", rx_len);
} else {
- wemac_inblk_32bit((void *)®s->rx_io_data,
- NetRxPackets[0], rx_len);
+ emac_inblk_32bit((void *)®s->rx_io_data,
+ NetRxPackets[0], rx_len);
/* Pass to upper layer */
NetReceive(NetRxPackets[0], rx_len);
return 0;
}
-static int sunxi_wemac_eth_send(struct eth_device *dev, void *packet, int len)
+static int sunxi_emac_eth_send(struct eth_device *dev, void *packet, int len)
{
- struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
+ struct emac_regs *regs = (struct emac_regs *)dev->iobase;
/* Select channel 0 */
writel(0, ®s->tx_ins);
/* Write packet */
- wemac_outblk_32bit((void *)®s->tx_io_data, packet, len);
+ emac_outblk_32bit((void *)®s->tx_io_data, packet, len);
/* Set TX len */
writel(len, ®s->tx_pl0);
return 0;
}
-int sunxi_wemac_initialize(void)
+int sunxi_emac_initialize(void)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_sramc_regs *sram =
(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
+ struct emac_regs *regs =
+ (struct emac_regs *)SUNXI_EMAC_BASE;
struct eth_device *dev;
- struct wemac_eth_dev *priv;
+ struct emac_eth_dev *priv;
int pin;
dev = malloc(sizeof(*dev));
if (dev == NULL)
return -ENOMEM;
- priv = (struct wemac_eth_dev *)malloc(sizeof(struct wemac_eth_dev));
+ priv = (struct emac_eth_dev *)malloc(sizeof(struct emac_eth_dev));
if (!priv) {
free(dev);
return -ENOMEM;
}
memset(dev, 0, sizeof(*dev));
- memset(priv, 0, sizeof(struct wemac_eth_dev));
+ memset(priv, 0, sizeof(struct emac_eth_dev));
/* Map SRAM to EMAC */
setbits_le32(&sram->ctrl1, 0x5 << 2);
/* Configure pin mux settings for MII Ethernet */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
- sunxi_gpio_set_cfgpin(pin, 2);
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPA0_EMAC);
/* Set up clock gating */
- setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_EMAC);
+ setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
+
+ /* Set MII clock */
+ clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
- dev->iobase = SUNXI_EMAC_BASE;
+ dev->iobase = (int)regs;
dev->priv = priv;
- dev->init = sunxi_wemac_eth_init;
- dev->halt = sunxi_wemac_eth_halt;
- dev->send = sunxi_wemac_eth_send;
- dev->recv = sunxi_wemac_eth_recv;
- strcpy(dev->name, "wemac");
+ dev->init = sunxi_emac_eth_init;
+ dev->halt = sunxi_emac_eth_halt;
+ dev->send = sunxi_emac_eth_send;
+ dev->recv = sunxi_emac_eth_recv;
+ strcpy(dev->name, "emac");
eth_register(dev);
- miiphy_register(dev->name, wemac_phy_read, wemac_phy_write);
+ miiphy_register(dev->name, emac_phy_read, emac_phy_write);
return 0;
}
obj-$(CONFIG_I82365) += i82365.o
obj-$(CONFIG_8xx) += mpc8xx_pcmcia.o
-obj-y += rpx_pcmcia.o
obj-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o
obj-y += tqm8xx_pcmcia.o
obj-$(CONFIG_MARUBUN_PCCARD) += marubun_pcmcia.o
#if 0
-#if defined(CONFIG_RPXLITE)
-
-/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
- * SYPCR is write once only, therefore must the slowest memory be faster
- * than the bus monitor or we will get a machine check due to the bus timeout.
- */
-#undef PCMCIA_BMT_LIMIT
-#define PCMCIA_BMT_LIMIT (6*8)
-#endif
-
static u_int m8xx_get_speed(u_int ns, u_int is_io)
{
u_int reg, clocks, psst, psl, psht;
+++ /dev/null
-/* -------------------------------------------------------------------- */
-/* RPX Boards from Embedded Planet */
-/* -------------------------------------------------------------------- */
-#include <common.h>
-#ifdef CONFIG_8xx
-#include <mpc8xx.h>
-#endif
-#include <pcmcia.h>
-
-#undef CONFIG_PCMCIA
-
-#if defined(CONFIG_CMD_PCMCIA)
-#define CONFIG_PCMCIA
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
-#define CONFIG_PCMCIA
-#endif
-
-#if defined(CONFIG_PCMCIA) \
- && defined(CONFIG_RPXLITE)
-
-#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
-
-int pcmcia_voltage_set(int slot, int vcc, int vpp)
-{
- u_long reg = 0;
-
- switch(vcc) {
- case 0: break;
- case 33: reg |= BCSR1_PCVCTL4; break;
- case 50: reg |= BCSR1_PCVCTL5; break;
- default: return 1;
- }
-
- switch(vpp) {
- case 0: break;
- case 33:
- case 50:
- if(vcc == vpp)
- reg |= BCSR1_PCVCTL6;
- else
- return 1;
- break;
- case 120:
- reg |= BCSR1_PCVCTL7;
- default: return 1;
- }
-
- /* first, turn off all power */
- *((uint *)RPX_CSR_ADDR) &= ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5
- | BCSR1_PCVCTL6 | BCSR1_PCVCTL7);
-
- /* enable new powersettings */
- *((uint *)RPX_CSR_ADDR) |= reg;
-
- return 0;
-}
-
-int pcmcia_hardware_enable (int slot)
-{
- return 0; /* No hardware to enable */
-}
-
-#if defined(CONFIG_CMD_PCMCIA)
-static int pcmcia_hardware_disable(int slot)
-{
- return 0; /* No hardware to disable */
-}
-#endif
-
-
-#endif /* CONFIG_PCMCIA && CONFIG_RPXLITE */
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_AXP152_POWER) += axp152.o
+obj-$(CONFIG_AXP209_POWER) += axp209.o
obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o
obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o
obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o
--- /dev/null
+/*
+ * (C) Copyright 2012
+ * Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <i2c.h>
+#include <axp152.h>
+
+enum axp152_reg {
+ AXP152_CHIP_VERSION = 0x3,
+ AXP152_DCDC2_VOLTAGE = 0x23,
+ AXP152_DCDC3_VOLTAGE = 0x27,
+ AXP152_DCDC4_VOLTAGE = 0x2B,
+ AXP152_LDO2_VOLTAGE = 0x2A,
+ AXP152_SHUTDOWN = 0x32,
+};
+
+#define AXP152_POWEROFF (1 << 7)
+
+static int axp152_write(enum axp152_reg reg, u8 val)
+{
+ return i2c_write(0x30, reg, 1, &val, 1);
+}
+
+static int axp152_read(enum axp152_reg reg, u8 *val)
+{
+ return i2c_read(0x30, reg, 1, val, 1);
+}
+
+static u8 axp152_mvolt_to_target(int mvolt, int min, int max, int div)
+{
+ if (mvolt < min)
+ mvolt = min;
+ else if (mvolt > max)
+ mvolt = max;
+
+ return (mvolt - min) / div;
+}
+
+int axp152_set_dcdc2(int mvolt)
+{
+ int rc;
+ u8 current, target;
+
+ target = axp152_mvolt_to_target(mvolt, 700, 2275, 25);
+
+ /* Do we really need to be this gentle? It has built-in voltage slope */
+ while ((rc = axp152_read(AXP152_DCDC2_VOLTAGE, ¤t)) == 0 &&
+ current != target) {
+ if (current < target)
+ current++;
+ else
+ current--;
+ rc = axp152_write(AXP152_DCDC2_VOLTAGE, current);
+ if (rc)
+ break;
+ }
+ return rc;
+}
+
+int axp152_set_dcdc3(int mvolt)
+{
+ u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 25);
+
+ return axp152_write(AXP152_DCDC3_VOLTAGE, target);
+}
+
+int axp152_set_dcdc4(int mvolt)
+{
+ u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 25);
+
+ return axp152_write(AXP152_DCDC4_VOLTAGE, target);
+}
+
+int axp152_set_ldo2(int mvolt)
+{
+ u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 100);
+
+ return axp152_write(AXP152_LDO2_VOLTAGE, target);
+}
+
+int axp152_init(void)
+{
+ u8 ver;
+ int rc;
+
+ rc = axp152_read(AXP152_CHIP_VERSION, &ver);
+ if (rc)
+ return rc;
+
+ if (ver != 0x05)
+ return -1;
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2012
+ * Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <axp209.h>
+
+enum axp209_reg {
+ AXP209_POWER_STATUS = 0x00,
+ AXP209_CHIP_VERSION = 0x03,
+ AXP209_DCDC2_VOLTAGE = 0x23,
+ AXP209_DCDC3_VOLTAGE = 0x27,
+ AXP209_LDO24_VOLTAGE = 0x28,
+ AXP209_LDO3_VOLTAGE = 0x29,
+ AXP209_IRQ_STATUS5 = 0x4c,
+ AXP209_SHUTDOWN = 0x32,
+};
+
+#define AXP209_POWER_STATUS_ON_BY_DC (1 << 0)
+
+#define AXP209_IRQ5_PEK_UP (1 << 6)
+#define AXP209_IRQ5_PEK_DOWN (1 << 5)
+
+#define AXP209_POWEROFF (1 << 7)
+
+static int axp209_write(enum axp209_reg reg, u8 val)
+{
+ return i2c_write(0x34, reg, 1, &val, 1);
+}
+
+static int axp209_read(enum axp209_reg reg, u8 *val)
+{
+ return i2c_read(0x34, reg, 1, val, 1);
+}
+
+static u8 axp209_mvolt_to_cfg(int mvolt, int min, int max, int div)
+{
+ if (mvolt < min)
+ mvolt = min;
+ else if (mvolt > max)
+ mvolt = max;
+
+ return (mvolt - min) / div;
+}
+
+int axp209_set_dcdc2(int mvolt)
+{
+ int rc;
+ u8 cfg, current;
+
+ cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
+
+ /* Do we really need to be this gentle? It has built-in voltage slope */
+ while ((rc = axp209_read(AXP209_DCDC2_VOLTAGE, ¤t)) == 0 &&
+ current != cfg) {
+ if (current < cfg)
+ current++;
+ else
+ current--;
+
+ rc = axp209_write(AXP209_DCDC2_VOLTAGE, current);
+ if (rc)
+ break;
+ }
+
+ return rc;
+}
+
+int axp209_set_dcdc3(int mvolt)
+{
+ u8 cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25);
+
+ return axp209_write(AXP209_DCDC3_VOLTAGE, cfg);
+}
+
+int axp209_set_ldo2(int mvolt)
+{
+ int rc;
+ u8 cfg, reg;
+
+ cfg = axp209_mvolt_to_cfg(mvolt, 1800, 3300, 100);
+
+ rc = axp209_read(AXP209_LDO24_VOLTAGE, ®);
+ if (rc)
+ return rc;
+
+ /* LDO2 configuration is in upper 4 bits */
+ reg = (reg & 0x0f) | (cfg << 4);
+ return axp209_write(AXP209_LDO24_VOLTAGE, reg);
+}
+
+int axp209_set_ldo3(int mvolt)
+{
+ u8 cfg;
+
+ if (mvolt == -1)
+ cfg = 0x80; /* determined by LDO3IN pin */
+ else
+ cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
+
+ return axp209_write(AXP209_LDO3_VOLTAGE, cfg);
+}
+
+int axp209_set_ldo4(int mvolt)
+{
+ int rc;
+ static const int vindex[] = {
+ 1250, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2500,
+ 2700, 2800, 3000, 3100, 3200, 3300
+ };
+ u8 cfg, reg;
+
+ /* Translate mvolt to register cfg value, requested <= selected */
+ for (cfg = 15; vindex[cfg] > mvolt && cfg > 0; cfg--);
+
+ rc = axp209_read(AXP209_LDO24_VOLTAGE, ®);
+ if (rc)
+ return rc;
+
+ /* LDO4 configuration is in lower 4 bits */
+ reg = (reg & 0xf0) | (cfg << 0);
+ return axp209_write(AXP209_LDO24_VOLTAGE, reg);
+}
+
+int axp209_init(void)
+{
+ u8 ver;
+ int rc;
+
+ rc = axp209_read(AXP209_CHIP_VERSION, &ver);
+ if (rc)
+ return rc;
+
+ /* Low 4 bits is chip version */
+ ver &= 0x0f;
+
+ if (ver != 0x1)
+ return -1;
+
+ return 0;
+}
+
+int axp209_poweron_by_dc(void)
+{
+ u8 v;
+
+ if (axp209_read(AXP209_POWER_STATUS, &v))
+ return 0;
+
+ return (v & AXP209_POWER_STATUS_ON_BY_DC);
+}
+
+int axp209_power_button(void)
+{
+ u8 v;
+
+ if (axp209_read(AXP209_IRQ_STATUS5, &v))
+ return 0;
+
+ axp209_write(AXP209_IRQ_STATUS5, AXP209_IRQ5_PEK_DOWN);
+
+ return v & AXP209_IRQ5_PEK_DOWN;
+}
serial_assign(default_serial_console()->name);
}
+int serial_stub_start(struct stdio_dev *sdev)
+{
+ struct serial_device *dev = sdev->priv;
+
+ return dev->start();
+}
+
+int serial_stub_stop(struct stdio_dev *sdev)
+{
+ struct serial_device *dev = sdev->priv;
+
+ return dev->stop();
+}
+
+void serial_stub_putc(struct stdio_dev *sdev, const char ch)
+{
+ struct serial_device *dev = sdev->priv;
+
+ dev->putc(ch);
+}
+
+void serial_stub_puts(struct stdio_dev *sdev, const char *str)
+{
+ struct serial_device *dev = sdev->priv;
+
+ dev->puts(str);
+}
+
+int serial_stub_getc(struct stdio_dev *sdev)
+{
+ struct serial_device *dev = sdev->priv;
+
+ return dev->getc();
+}
+
+int serial_stub_tstc(struct stdio_dev *sdev)
+{
+ struct serial_device *dev = sdev->priv;
+
+ return dev->tstc();
+}
+
/**
* serial_stdio_init() - Register serial ports with STDIO core
*
strcpy(dev.name, s->name);
dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
- dev.start = s->start;
- dev.stop = s->stop;
- dev.putc = s->putc;
- dev.puts = s->puts;
- dev.getc = s->getc;
- dev.tstc = s->tstc;
+ dev.start = serial_stub_start;
+ dev.stop = serial_stub_stop;
+ dev.putc = serial_stub_putc;
+ dev.puts = serial_stub_puts;
+ dev.getc = serial_stub_getc;
+ dev.tstc = serial_stub_tstc;
stdio_register(&dev);
*/
int serial_init(void)
{
+ gd->flags |= GD_FLG_SERIAL_READY;
return get_current()->start();
}
static int calc_divisor (NS16550_t port)
{
+ const unsigned int mode_x_div = 16;
+
#ifdef CONFIG_OMAP1510
/* If can't cleanly clock 115200 set div to 1 */
if ((CONFIG_SYS_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) {
}
port->osc_12m_sel = 0; /* clear if previsouly set */
#endif
-#ifdef CONFIG_OMAP1610
- /* If can't cleanly clock 115200 set div to 1 */
- if ((CONFIG_SYS_NS16550_CLK == 48000000) && (gd->baudrate == 115200)) {
- return (26); /* return 26 for base divisor */
- }
-#endif
-#define MODE_X_DIV 16
- /* Compute divisor value. Normally, we should simply return:
- * CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd->baudrate
- * but we need to round that value by adding 0.5.
- * Rounding is especially important at high baud rates.
- */
- return (CONFIG_SYS_NS16550_CLK + (gd->baudrate * (MODE_X_DIV / 2))) /
- (MODE_X_DIV * gd->baudrate);
+ return DIV_ROUND_CLOSEST(CONFIG_SYS_NS16550_CLK,
+ mode_x_div * gd->baudrate);
}
void
# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* Overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+ defined(CONFIG_R8A7794)
# define SCIF_ORER 0x0001
# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
#else
* Test whether a character is in the RX buffer
*/
-int usbtty_tstc (void)
+int usbtty_tstc(struct stdio_dev *dev)
{
struct usb_endpoint_instance *endpoint =
&endpoint_instance[rx_endpoint];
* written into its argument c.
*/
-int usbtty_getc (void)
+int usbtty_getc(struct stdio_dev *dev)
{
char c;
struct usb_endpoint_instance *endpoint =
/*
* Output a single byte to the usb client port.
*/
-void usbtty_putc (const char c)
+void usbtty_putc(struct stdio_dev *dev, const char c)
{
if (!usbtty_configured ())
return;
}
}
-void usbtty_puts (const char *str)
+void usbtty_puts(struct stdio_dev *dev, const char *str)
{
int n;
int len;
*/
#include <common.h>
-#include <asm/arch/sound.h>
+#include <asm/sound.h>
#include <asm/sdl.h>
int sound_play(uint32_t msec, uint32_t frequency)
goto out_recv;
}
- if ((status == chip->vendor.req_canceled)) {
+ if (status == chip->vendor.req_canceled) {
error("Operation Canceled\n");
rc = -ECANCELED;
goto out;
{
int ret = 0;
+ usb_phy_power(1);
omap_enable_phy(omap);
ret = dwc3_core_init(omap->dwc3_reg);
#include <asm/cache.h>
#include <asm/io.h>
#include <linux/list.h>
-
-#define upper_32_bits(n) (u32)((n) >> 32)
-#define lower_32_bits(n) (u32)(n)
+#include <linux/compat.h>
#define MAX_EP_CTX_NUM 31
#define XHCI_ALIGNMENT 64
__u32 *ptr = (__u32 *)regs;
u32 val_lo = lower_32_bits(val);
/* FIXME */
- u32 val_hi = 0;
+ u32 val_hi = upper_32_bits(val);
writel(val_lo, ptr);
writel(val_hi, ptr + 1);
}
void usb_phy_power(int on)
{
- return;
+ u32 val;
+
+ /* USB1_CTRL */
+ val = readl(USB1_CTRL);
+ if (on) {
+ /*
+ * these bits are re-used on AM437x to power up/down the USB
+ * CM and OTG PHYs, if we don't toggle them, USB will not be
+ * functional on newer silicon revisions
+ */
+ val &= ~(USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN);
+ } else {
+ val |= USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN;
+ }
+
+ writel(val, USB1_CTRL);
}
#endif /* CONFIG_AM437X_USB2PHY2_HOST */
CURSOR_SET;
}
-void video_putc(const char c)
+void video_putc(struct stdio_dev *dev, const char c)
{
#ifdef CONFIG_CFB_CONSOLE_ANSI
int i;
flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE);
}
-void video_puts(const char *s)
+void video_puts(struct stdio_dev *dev, const char *s)
{
int count = strlen(s);
while (count--)
- video_putc(*s++);
+ video_putc(dev, *s++);
}
/*
console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM;
console_dev.putc = video_putc; /* 'putc' function */
console_dev.puts = video_puts; /* 'puts' function */
- console_dev.tstc = NULL; /* 'tstc' function */
- console_dev.getc = NULL; /* 'getc' function */
#if !defined(CONFIG_VGA_AS_SINGLE_DEVICE)
/* Also init console device */
#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */
#endif
-#if defined(CONFIG_V37) || defined(CONFIG_EDT32F10)
+#if defined(CONFIG_EDT32F10)
#undef CONFIG_LCD_LOGO
#undef CONFIG_LCD_INFO
#endif
* the controller.
*/
-#ifdef CONFIG_RPXLITE
- /* This is special for RPXlite_DW Software Development Platform **[Sam]** */
- panel_info.vl_dp = CONFIG_SYS_LOW;
-#endif
-
lccrtmp = LCDBIT (LCCR_BNUM_BIT,
(((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));
/* Initialize LCD controller bus priorities.
*/
-#ifdef CONFIG_RBC823
- immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1; /* RAID = 01, LAID = 00 */
-#else
immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */
/* set SHFT/CLOCK division factor 4
immr->im_clkrst.car_sccr &= ~0x1F;
immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */
-#endif /* CONFIG_RBC823 */
-
-#if defined(CONFIG_RBC823)
- /* Enable LCD on port D.
- */
- immr->im_ioport.iop_pddat &= 0x0300;
- immr->im_ioport.iop_pdpar |= 0x1CFF;
- immr->im_ioport.iop_pddir |= 0x1CFF;
-
- /* Configure LCD_ON, VEE_ON, CCFL_ON on port B.
- */
- immr->im_cpm.cp_pbdat &= ~0x00005001;
- immr->im_cpm.cp_pbpar &= ~0x00005001;
- immr->im_cpm.cp_pbdir |= 0x00005001;
-#elif !defined(CONFIG_EDT32F10)
+#if !defined(CONFIG_EDT32F10)
/* Enable LCD on port D.
*/
immr->im_ioport.iop_pdpar |= 0x1FFF;
volatile lcd823_t *lcdp = &immr->im_lcd;
/* Enable the LCD panel */
-#ifndef CONFIG_RBC823
immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */
-#endif
lcdp->lcd_lccr |= LCCR_PON;
-#ifdef CONFIG_V37
- /* Turn on display backlight */
- immr->im_cpm.cp_pbpar |= 0x00008000;
- immr->im_cpm.cp_pbdir |= 0x00008000;
-#elif defined(CONFIG_RBC823)
- /* Turn on display backlight */
- immr->im_cpm.cp_pbdat |= 0x00004000;
-#endif
-
#if defined(CONFIG_LWMON)
{ uchar c = pic_read (0x60);
#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON)
r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF);
}
#endif /* CONFIG_R360MPI */
-#ifdef CONFIG_RBC823
- udelay(200000); /* wait 200ms */
- /* Turn VEE_ON first */
- immr->im_cpm.cp_pbdat |= 0x00000001;
- udelay(200000); /* wait 200ms */
- /* Now turn on LCD_ON */
- immr->im_cpm.cp_pbdat |= 0x00001000;
-#endif
#ifdef CONFIG_RRVISION
debug ("PC4->Output(1): enable LVDS\n");
debug ("PC5->Output(0): disable PAL clock\n");
#endif
}
-/*----------------------------------------------------------------------*/
-
-#if defined (CONFIG_RBC823)
-void lcd_disable (void)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile lcd823_t *lcdp = &immr->im_lcd;
-
-#if defined(CONFIG_LWMON)
- { uchar c = pic_read (0x60);
- c &= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */
- pic_write (0x60, c);
- }
-#elif defined(CONFIG_R360MPI)
- {
- extern void r360_i2c_lcd_write (uchar data0, uchar data1);
-
- r360_i2c_lcd_write(0x10, 0x00);
- r360_i2c_lcd_write(0x20, 0x00);
- r360_i2c_lcd_write(0x30, 0x00);
- r360_i2c_lcd_write(0x40, 0x00);
- }
-#endif /* CONFIG_LWMON */
- /* Disable the LCD panel */
- lcdp->lcd_lccr &= ~LCCR_PON;
-#ifdef CONFIG_RBC823
- /* Turn off display backlight, VEE and LCD_ON */
- immr->im_cpm.cp_pbdat &= ~0x00005001;
-#else
- immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25)); /* LAM = 0 */
-#endif /* CONFIG_RBC823 */
-}
-#endif /* NOT_USED_SO_FAR || CONFIG_RBC823 */
-
-
/************************************************************************/
#endif /* CONFIG_LCD */
#include <common.h>
#include <watchdog.h>
#include <asm/blackfin.h>
+#include <asm/clock.h>
#include <asm/mach-common/bits/watchdog.h>
void hw_watchdog_reset(void)
unsigned long pos;
int len_read;
unsigned long time;
+ char *ep;
if (argc < 2)
return CMD_RET_USAGE;
return 1;
if (argc >= 4) {
- addr = simple_strtoul(argv[3], NULL, 16);
+ addr = simple_strtoul(argv[3], &ep, 16);
+ if (ep == argv[3] || *ep != '\0')
+ return CMD_RET_USAGE;
} else {
addr_str = getenv("loadaddr");
if (addr_str != NULL)
const u8 *data,
const struct yaffs_ext_tags *tags)
{
- dev = dev;
- nand_chunk = nand_chunk;
- data = data;
- tags = tags;
}
static void yaffs_handle_chunk_update(struct yaffs_dev *dev, int nand_chunk,
const struct yaffs_ext_tags *tags)
{
- dev = dev;
- nand_chunk = nand_chunk;
- tags = tags;
}
void yaffs_handle_chunk_error(struct yaffs_dev *dev,
int required_depth;
int level = file_struct->top_level;
- dev = dev;
-
/* Check sane level and chunk Id */
if (level < 0 || level > YAFFS_TNODES_MAX_LEVEL)
return NULL;
} else {
yaffs_strncpy(name, oh_name + 1, buff_size - 1);
}
- } else {
-#else
- dev = dev;
- {
-#endif
- yaffs_strncpy(name, oh_name, buff_size - 1);
+
+ return;
}
+#endif
+
+ yaffs_strncpy(name, oh_name, buff_size - 1);
}
static void yaffs_load_oh_from_name(struct yaffs_dev *dev, YCHAR *oh_name,
const YCHAR *name)
{
#ifdef CONFIG_YAFFS_AUTO_UNICODE
-
int is_ascii;
YCHAR *w;
*oh_name = 0;
yaffs_strncpy(oh_name + 1, name, YAFFS_MAX_NAME_LENGTH - 2);
}
- } else {
-#else
- dev = dev;
- {
-#endif
- yaffs_strncpy(oh_name, name, YAFFS_MAX_NAME_LENGTH - 1);
+
+ return;
}
+#endif
+
+ yaffs_strncpy(oh_name, name, YAFFS_MAX_NAME_LENGTH - 1);
}
/* UpdateObjectHeader updates the header on NAND for an object.
int yaffs_skip_verification(struct yaffs_dev *dev)
{
- dev = dev;
return !(yaffs_trace_mask &
(YAFFS_TRACE_VERIFY | YAFFS_TRACE_VERIFY_FULL));
}
static int yaffs_skip_full_verification(struct yaffs_dev *dev)
{
- dev = dev;
return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY_FULL));
}
static int yaffs_skip_nand_verification(struct yaffs_dev *dev)
{
- dev = dev;
return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY_NAND));
}
int yaffs_verify_file_sane(struct yaffs_obj *in)
{
- in = in;
return YAFFS_OK;
}
int yaffs_mknod(const YCHAR *pathname, mode_t mode, dev_t dev)
{
- pathname = pathname;
- mode = mode;
- dev = dev;
-
yaffsfs_SetError(-EINVAL);
return -1;
}
int yaffs_dump_dev(const YCHAR *path)
{
-#if 1
- path = path;
-#else
+#if 0
YCHAR *rest;
struct yaffs_obj *obj = yaffsfs_FindRoot(path, &rest);
min_altera_type, /* insert all new types after this */
Altera_ACEX1K, /* ACEX1K Family */
Altera_CYC2, /* CYCLONII Family */
- Altera_StratixII, /* StratixII Familiy */
+ Altera_StratixII, /* StratixII Family */
/* Add new models here */
max_altera_type /* insert all new types before this */
} Altera_Family; /* end, typedef Altera_Family */
struct global_data *new_gd; /* relocated global data */
#ifdef CONFIG_DM
- struct udevice *dm_root;/* Root instance for Driver Model */
+ struct udevice *dm_root; /* Root instance for Driver Model */
+ struct udevice *dm_root_f; /* Pre-relocation root instance */
struct list_head uclass_root; /* Head of core tree */
#endif
#endif
unsigned long timebase_h;
unsigned long timebase_l;
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ unsigned long malloc_base; /* base address of early malloc() */
+ unsigned long malloc_limit; /* limit address */
+ unsigned long malloc_ptr; /* current address */
+#endif
struct arch_global_data arch; /* architecture-specific data */
} gd_t;
#endif
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define GD_FLG_ENV_READY 0x00080 /* Env. imported into hash table */
+#define GD_FLG_SERIAL_READY 0x00100 /* Pre-reloc serial console ready */
#endif /* __ASM_GENERIC_GBL_DATA_H */
--- /dev/null
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+int axp152_set_dcdc2(int mvolt);
+int axp152_set_dcdc3(int mvolt);
+int axp152_set_dcdc4(int mvolt);
+int axp152_set_ldo2(int mvolt);
+int axp152_init(void);
--- /dev/null
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+extern int axp209_set_dcdc2(int mvolt);
+extern int axp209_set_dcdc3(int mvolt);
+extern int axp209_set_ldo2(int mvolt);
+extern int axp209_set_ldo3(int mvolt);
+extern int axp209_set_ldo4(int mvolt);
+extern int axp209_init(void);
+extern int axp209_poweron_by_dc(void);
+extern int axp209_power_button(void);
#endif
#if defined(CONFIG_8xx)
#include <asm/8xx_immap.h>
-#if defined(CONFIG_MPC852) || defined(CONFIG_MPC852T) || \
- defined(CONFIG_MPC859) || defined(CONFIG_MPC859T) || \
- defined(CONFIG_MPC859DSL) || \
- defined(CONFIG_MPC866) || defined(CONFIG_MPC866T) || \
+#if defined(CONFIG_MPC859) || defined(CONFIG_MPC859T) || \
+ defined(CONFIG_MPC866) || \
defined(CONFIG_MPC866P)
# define CONFIG_MPC866_FAMILY 1
#elif defined(CONFIG_MPC870) \
extern ssize_t spi_write (uchar *, int, uchar *, int);
#endif
-void rpxlite_init (void);
-
#ifdef CONFIG_HERMES
/* $(BOARD)/hermes.c */
void hermes_start_lxt980 (int speed);
int serial_getc (void);
int serial_tstc (void);
+/* These versions take a stdio_dev pointer */
+struct stdio_dev;
+int serial_stub_getc(struct stdio_dev *sdev);
+int serial_stub_tstc(struct stdio_dev *sdev);
+
void _serial_setbrg (const int);
void _serial_putc (const char, const int);
void _serial_putc_raw(const char, const int);
#endif
-/*** FADS860T********************************************************/
-
-#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x)
-/*
- * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1.
- */
-#ifdef CONFIG_SCC1_ENET
-
-#define SCC_ENET 0
-
-#define PROFF_ENET PROFF_SCC1
-#define CPM_CR_ENET CPM_CR_CH_SCC1
-
-#define PA_ENET_RXD ((ushort)0x0001)
-#define PA_ENET_TXD ((ushort)0x0002)
-#define PA_ENET_TCLK ((ushort)0x0100)
-#define PA_ENET_RCLK ((ushort)0x0200)
-
-#define PB_ENET_TENA ((uint)0x00001000)
-
-#define PC_ENET_CLSN ((ushort)0x0010)
-#define PC_ENET_RENA ((ushort)0x0020)
-
-#define SICR_ENET_MASK ((uint)0x000000ff)
-#define SICR_ENET_CLKRT ((uint)0x0000002c)
-
-#endif /* CONFIG_SCC1_ETHERNET */
-
-/*
- * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS
- * with ethernet on FEC.
- */
-
-#ifdef CONFIG_FEC_ENET
-#define FEC_ENET /* Use FEC for Ethernet */
-#endif /* CONFIG_FEC_ENET */
-
-#endif /* CONFIG_FADS && CONFIG_MPC86x */
-
/*** FPS850L, FPS860L ************************************************/
#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
#endif /* CONFIG_NETVIA */
-/*** QS850/QS823 ***************************************************/
-
-#if defined(CONFIG_QS850) || defined(CONFIG_QS823)
-#undef FEC_ENET /* Don't use FEC for EThernet */
-
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-
-#define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */
-#define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */
-#define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */
-#define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */
-#define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */
-#define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */
-#define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */
-#define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */
-#define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */
-#define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */
-
-/* SCC2 TXCLK from CLK2
- * SCC2 RXCLK from CLK4
- * SCC2 Connected to NMSI */
-#define SICR_ENET_MASK ((uint)0x00007F00)
-#define SICR_ENET_CLKRT ((uint)0x00003D00)
-
-#endif /* CONFIG_QS850/QS823 */
-
-/*** QS860T ***************************************************/
-
-#ifdef CONFIG_QS860T
-#ifdef CONFIG_FEC_ENET
-#define FEC_ENET /* use FEC for EThernet */
-#endif /* CONFIG_FEC_ETHERNET */
-
-/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
-#define PROFF_ENET PROFF_SCC1
-#define CPM_CR_ENET CPM_CR_CH_SCC1
-#define SCC_ENET 0
-
-#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */
-#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */
-#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */
-#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */
-#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */
-#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */
-
-#define SICR_ENET_MASK ((uint)0x000000ff)
-/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */
-#define SICR_ENET_CLKRT ((uint)0x0000003D)
-
-#endif /* CONFIG_QS860T */
-
-/*** RPXLITE ********************************************************/
-
-#ifdef CONFIG_RPXLITE
-/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
- * this may be unique to the RPX-Lite configuration.
- * Note TENA is on Port B.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004)
-#define PA_ENET_TXD ((ushort)0x0008)
-#define PA_ENET_TCLK ((ushort)0x0200)
-#define PA_ENET_RCLK ((ushort)0x0800)
-#if defined(CONFIG_RMU)
-#define PC_ENET_TENA ((uint)0x00000002) /* PC14 */
-#else
-#define PB_ENET_TENA ((uint)0x00002000)
-#endif
-#define PC_ENET_CLSN ((ushort)0x0040)
-#define PC_ENET_RENA ((ushort)0x0080)
-
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00003d00)
-#endif /* CONFIG_RPXLITE */
-
/*** SM850 *********************************************************/
/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
- defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
+ defined(CONFIG_R360MPI) || \
defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \
defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \
defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \
# endif /* CONFIG_FEC_ENET */
#endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
-/*** V37 **********************************************************/
-
-#ifdef CONFIG_V37
-/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of
- * this may be unique to the Marel V37 configuration.
- * Note TENA is on Port B.
- */
-#define PROFF_ENET PROFF_SCC2
-#define CPM_CR_ENET CPM_CR_CH_SCC2
-#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004)
-#define PA_ENET_TXD ((ushort)0x0008)
-#define PA_ENET_TCLK ((ushort)0x0400)
-#define PA_ENET_RCLK ((ushort)0x0200)
-#define PB_ENET_TENA ((uint)0x00002000)
-#define PC_ENET_CLSN ((ushort)0x0040)
-#define PC_ENET_RENA ((ushort)0x0080)
-
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002e00)
-#endif /* CONFIG_V37 */
-
-
/*********************************************************************/
/* SCC Event register as used by Ethernet.
# include <machine/endian.h>
typedef unsigned long ulong;
#endif
+#include <time.h>
typedef uint8_t __u8;
typedef uint16_t __u16;
#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10))
-#define VIDEO_TSTC_FCT serial_tstc
-#define VIDEO_GETC_FCT serial_getc
+#define VIDEO_TSTC_FCT serial_stub_tstc
+#define VIDEO_GETC_FCT serial_stub_getc
#define CONFIG_VIDEO_SMI_LYNXEM
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_LOGO
#define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */
-#define VIDEO_TSTC_FCT serial_tstc
-#define VIDEO_GETC_FCT serial_getc
+#define VIDEO_TSTC_FCT serial_stub_tstc
+#define VIDEO_GETC_FCT serial_stub_getc
#define CONFIG_BR0_WORKAROUND 1
+++ /dev/null
-/*
- * A collection of structures, addresses, and values associated with
- * the Motorola MPC8xxADS board. Copied from the FADS config.
- *
- * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
- *
- * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
- *
- * Values common to all FADS family boards are in board/fads/fads.h
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/* board type */
-#define CONFIG_MPC86xADS 1 /* new ADS */
-#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */
-
-/* CPU type - pick one of these */
-#define CONFIG_MPC866T 1
-#undef CONFIG_MPC866P
-#undef CONFIG_MPC859T
-#undef CONFIG_MPC859DSL
-#undef CONFIG_MPC852T
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 38400
-
-#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */
-#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
-#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000
-#define CONFIG_SYS_8xx_CPUCLK_MAX 80000000
-
-#define CONFIG_DRAM_50MHZ 1
-#define CONFIG_SDRAM_50MHZ 1
-
-#include "../../board/fads/fads.h"
-
-#define CONFIG_SYS_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */
-#define CONFIG_SYS_BR5_PRELIM (CONFIG_SYS_PHYDEV_ADDR | BR_PS_8 | BR_V)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * A collection of structures, addresses, and values associated with
- * the Motorola MPC885ADS board. Values common to all FADS family boards
- * are in board/fads/fads.h
- *
- * Copyright (C) 2003-2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MPC885ADS 1 /* MPC885ADS board */
-#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */
-
-#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 38400
-
-#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
-#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
-#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000
-#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000
-
-#define CONFIG_SDRAM_50MHZ 1
-
-#include "../../board/fads/fads.h"
-
-#define CONFIG_SYS_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */
-#define CONFIG_SYS_BR5_PRELIM (CONFIG_SYS_PHYDEV_ADDR | BR_PS_8 | BR_V)
-
-#define CONFIG_HAS_ETH1
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetTA4 board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2
-#error Unsupported CONFIG_NETPHONE version
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC870 1 /* This is a MPC885 CPU */
-#define CONFIG_NETPHONE 1 /* ...on a NetPhone board */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
-
-/* #define CONFIG_XIN 10000000 */
-#define CONFIG_XIN 50000000
-/* #define MPC8XX_HZ 120000000 */
-#define MPC8XX_HZ 66666666
-
-#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT "echo;"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "tftpboot; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm"
-
-#define CONFIG_SOURCE
-#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_NISDOMAIN
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-#define FEC_ENET 1 /* eth.c needs it that way... */
-#undef CONFIG_SYS_DISCOVER_PHY
-#define CONFIG_MII 1
-#define CONFIG_MII_INIT 1
-#define CONFIG_RMII 1 /* use RMII interface */
-
-#define CONFIG_ETHER_ON_FEC1 1
-#define CONFIG_FEC1_PHY 8 /* phy address of FEC */
-#define CONFIG_FEC1_PHY_NORXERR 1
-
-#define CONFIG_ETHER_ON_FEC2 1
-#define CONFIG_FEC2_PHY 4
-#define CONFIG_FEC2_PHY_NORXERR 1
-
-#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_CDP
-
-
-#define CONFIG_BOARD_EARLY_INIT_F 1
-#define CONFIG_MISC_INIT_R
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#if defined(DEBUG)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#if CONFIG_NETPHONE_VERSION == 2
-#define CONFIG_SYS_FLASH_BASE4 0x40080000
-#endif
-
-#define CONFIG_SYS_RESET_ADDRESS 0x80000000
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#if CONFIG_NETPHONE_VERSION == 1
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#elif CONFIG_NETPHONE_VERSION == 2
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#endif
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x10000
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
-#define CONFIG_ENV_SIZE 0x4000
-
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#else /* we must activate GPL5 in the SIUMCR for CAN */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#endif /* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- */
-
-#if CONFIG_XIN == 10000000
-
-#if MPC8XX_HZ == 120000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 50000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 25000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 40000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 75000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 10MHz
-#endif
-
-#elif CONFIG_XIN == 50000000
-
-#if MPC8XX_HZ == 120000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 66666666
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 50MHz
-#endif
-
-#else
-
-#error unsupported XIN freq
-#endif
-
-
-/*
- *-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- *
- * Note: When TBS == 0 the timebase is independent of current cpu clock.
- */
-
-#define SCCR_MASK SCCR_EBDF11
-#if MPC8XX_HZ > 66666666
-#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00 | SCCR_EBDF01)
-#else
-#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define CONFIG_SYS_DER 0x2002000F*/
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-#if CONFIG_NETPHONE_VERSION == 2
-
-#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */
-
-#define CONFIG_SYS_OR4_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-#endif
-
-/*
- * BR3 and OR3 (SDRAM)
- *
- */
-#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
-
-#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock!)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- *
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider = 98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-
-#define CONFIG_SYS_MAMR_PTA 234
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
- */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
-
-/****************************************************************/
-
-#define DSP_SIZE 0x00010000 /* 64K */
-#define NAND_SIZE 0x00010000 /* 64K */
-
-#define DSP_BASE 0xF1000000
-#define NAND_BASE 0xF1010000
-
-/*****************************************************************************/
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-
-/*****************************************************************************/
-
-#if CONFIG_NETPHONE_VERSION == 1
-#define STATUS_LED_BIT 0x00000008 /* bit 28 */
-#elif CONFIG_NETPHONE_VERSION == 2
-#define STATUS_LED_BIT 0x00000080 /* bit 24 */
-#endif
-
-#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-#define STATUS_LED_STATE STATUS_LED_BLINKING
-
-#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
-#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-#ifndef __ASSEMBLY__
-
-/* LEDs */
-
-/* led_id_t is unsigned int mask */
-typedef unsigned int led_id_t;
-
-#define __led_toggle(_msk) \
- do { \
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \
- } while(0)
-
-#define __led_set(_msk, _st) \
- do { \
- if ((_st)) \
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \
- else \
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
- } while(0)
-
-#define __led_init(msk, st) __led_set(msk, st)
-
-#endif
-
-/***********************************************************************************************************
-
- ----------------------------------------------------------------------------------------------
-
- (V1) version 1 of the board
- (V2) version 2 of the board
-
- ----------------------------------------------------------------------------------------------
-
- Pin definitions:
-
- +------+----------------+--------+------------------------------------------------------------
- | # | Name | Type | Comment
- +------+----------------+--------+------------------------------------------------------------
- | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select
- | PA7 | DSP_INT | Output | DSP interrupt
- | PA10 | DSP_RESET | Output | DSP reset
- | PA14 | USBOE | Output | USB (1)
- | PA15 | USBRXD | Output | USB (1)
- | PB19 | BT_RTS | Output | Bluetooth (0)
- | PB23 | BT_CTS | Output | Bluetooth (0)
- | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select
- | PB27 | SPICS_DISP | Output | Display chip select
- | PB28 | SPI_RXD_3V | Input | SPI Data Rx
- | PB29 | SPI_TXD | Output | SPI Data Tx
- | PB30 | SPI_CLK | Output | SPI Clock
- | PC10 | DISPA0 | Output | Display A0
- | PC11 | BACKLIGHT | Output | Display backlit
- | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD
- | | IO_RESET | Output | (V2) General I/O reset
- | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1)
- | | HOOK | Input | (V2) Hook input interrupt
- | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK
- | | F_RY_BY | Input | (V2) NAND F_RY_BY
- | PE17 | F_ALE | Output | NAND F_ALE
- | PE18 | F_CLE | Output | NAND F_CLE
- | PE20 | F_CE | Output | NAND F_CE
- | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select
- | | LED | Output | (V2) LED
- | PE27 | SPICS_ER | Output | External serial register CS
- | PE28 | LEDIO1 | Output | (V1) LED
- | | BKBR1 | Input | (V2) Keyboard input scan
- | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2)
- | | BKBR2 | Input | (V2) Keyboard input scan
- | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2)
- | | BKBR3 | Input | (V2) Keyboard input scan
- | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY
- | | BKBR4 | Input | (V2) Keyboard input scan
- +------+----------------+--------+---------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Serial register input:
-
- +------+----------------+------------------------------------------------------------
- | # | Name | Comment
- +------+----------------+------------------------------------------------------------
- | 0 | BKBR1 | (V1) Keyboard input scan
- | 1 | BKBR3 | (V1) Keyboard input scan
- | 2 | BKBR4 | (V1) Keyboard input scan
- | 3 | BKBR2 | (V1) Keyboard input scan
- | 4 | HOOK | (V1) Hook switch
- | 5 | BT_LINK | (V1) Bluetooth link status
- | 6 | HOST_WAKE | (V1) Bluetooth host wake up
- | 7 | OK_ETH | (V1) Cisco inline power OK status
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Serial register output:
-
- +------+----------------+------------------------------------------------------------
- | # | Name | Comment
- +------+----------------+------------------------------------------------------------
- | 0 | KEY1 | Keyboard output scan
- | 1 | KEY2 | Keyboard output scan
- | 2 | KEY3 | Keyboard output scan
- | 3 | KEY4 | Keyboard output scan
- | 4 | KEY5 | Keyboard output scan
- | 5 | KEY6 | Keyboard output scan
- | 6 | KEY7 | Keyboard output scan
- | 7 | BT_WAKE | Bluetooth wake up
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Chip selects:
-
- +------+----------------+------------------------------------------------------------
- | # | Name | Comment
- +------+----------------+------------------------------------------------------------
- | CS0 | CS0 | Boot flash
- | CS1 | CS_FLASH | NAND flash
- | CS2 | CS_DSP | DSP
- | CS3 | DCS_DRAM | DRAM
- | CS4 | CS_FLASH2 | (V2) 2nd flash
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Interrupts:
-
- +------+----------------+------------------------------------------------------------
- | # | Name | Comment
- +------+----------------+------------------------------------------------------------
- | IRQ1 | IRQ_DSP | DSP interrupt
- | IRQ3 | S_INTER | DUSLIC ???
- | IRQ4 | F_RY_BY | NAND
- | IRQ7 | IRQ_MAX | MAX 3100 interrupt
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Interrupts on PCMCIA pins:
-
- +------+----------------+------------------------------------------------------------
- | # | Name | Comment
- +------+----------------+------------------------------------------------------------
- | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface
- | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface
- | IP_A2| RMII1_MDINT | PHY interrupt for #1
- | IP_A3| RMII2_MDINT | PHY interrupt for #2
- | IP_A5| HOST_WAKE | (V2) Bluetooth host wake
- | IP_A6| OK_ETH | (V2) Cisco inline power OK
- +------+----------------+------------------------------------------------------------
-
-*************************************************************************************************/
-
-#define CONFIG_SED156X 1 /* use SED156X */
-#define CONFIG_SED156X_PG12864Q 1 /* type of display used */
-
-/* serial interfacing macros */
-
-#define SED156X_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define SED156X_SPI_RXD_MASK 0x00000008
-
-#define SED156X_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define SED156X_SPI_TXD_MASK 0x00000004
-
-#define SED156X_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define SED156X_SPI_CLK_MASK 0x00000002
-
-#define SED156X_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define SED156X_CS_MASK 0x00000010
-
-#define SED156X_A0_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
-#define SED156X_A0_MASK 0x0020
-
-/*************************************************************************************************/
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
-
-/*************************************************************************************************/
-
-/* use board specific hardware */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_SHOW_ACTIVITY
-
-/*************************************************************************************************/
-
-/* phone console configuration */
-
-#define PHONE_CONSOLE_POLL_HZ (CONFIG_SYS_HZ/200) /* poll every 5ms */
-
-/*************************************************************************************************/
-
-#define CONFIG_CDP_DEVICE_ID 20
-#define CONFIG_CDP_DEVICE_ID_PREFIX "NP" /* netphone */
-#define CONFIG_CDP_PORT_ID "eth%d"
-#define CONFIG_CDP_CAPABILITIES 0x00000010
-#define CONFIG_CDP_VERSION "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME
-#define CONFIG_CDP_PLATFORM "Intracom NetPhone"
-#define CONFIG_CDP_TRIGGER 0x20020001
-#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
-#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone */
-
-/*************************************************************************************************/
-
-#define CONFIG_AUTO_COMPLETE 1
-
-/*************************************************************************************************/
-
-#define CONFIG_CRC32_VERIFY 1
-
-/*************************************************************************************************/
-
-#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
-
-/*************************************************************************************************/
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetTA4 board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
-#define CONFIG_NETTA 1 /* ...on a NetTA board */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
-
-/* #define CONFIG_XIN 10000000 */
-#define CONFIG_XIN 50000000
-#define MPC8XX_HZ 120000000
-/* #define MPC8XX_HZ 100000000 */
-/* #define MPC8XX_HZ 50000000 */
-/* #define MPC8XX_HZ 80000000 */
-
-#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "tftpboot; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_HW_WATCHDOG
-
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_NISDOMAIN
-
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-#define FEC_ENET 1 /* eth.c needs it that way... */
-#undef CONFIG_SYS_DISCOVER_PHY /* do not discover phys */
-#define CONFIG_MII 1
-#define CONFIG_MII_INIT 1
-#define CONFIG_RMII 1 /* use RMII interface */
-
-#if defined(CONFIG_NETTA_ISDN)
-#define CONFIG_ETHER_ON_FEC1 1
-#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */
-#define CONFIG_FEC1_PHY_NORXERR 1
-#undef CONFIG_ETHER_ON_FEC2
-#else
-#define CONFIG_ETHER_ON_FEC1 1
-#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */
-#define CONFIG_FEC1_PHY_NORXERR 1
-#define CONFIG_ETHER_ON_FEC2 1
-#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */
-#define CONFIG_FEC2_PHY_NORXERR 1
-#endif
-
-#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_CODEC | \
- CONFIG_SYS_POST_DSP )
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CDP
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCMCIA
-#define CONFIG_CMD_PING
-
-
-#define CONFIG_BOARD_EARLY_INIT_F 1
-#define CONFIG_MISC_INIT_R
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#if defined(DEBUG)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x10000
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
-#define CONFIG_ENV_SIZE 0x4000
-
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#else /* we must activate GPL5 in the SIUMCR for CAN */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#endif /* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- */
-
-#if CONFIG_XIN == 10000000
-
-#if MPC8XX_HZ == 120000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 50000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 25000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 40000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 75000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 10MHz
-#endif
-
-#elif CONFIG_XIN == 50000000
-
-#if MPC8XX_HZ == 120000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 80000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 50000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 50MHz
-#endif
-
-#else
-
-#error unsupported XIN freq
-#endif
-
-
-/*
- *-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- *
- * Note: When TBS == 0 the timebase is independent of current cpu clock.
- */
-
-#define SCCR_MASK SCCR_EBDF11
-#if MPC8XX_HZ > 66666666
-#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00 | SCCR_EBDF01)
-#else
-#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define CONFIG_SYS_DER 0x2002000F*/
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR3 and OR3 (SDRAM)
- *
- */
-#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
-
-#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock!)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- *
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider = 98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-
-#if MPC8XX_HZ == 120000000
-#define CONFIG_SYS_MAMR_PTA 234
-#elif MPC8XX_HZ == 100000000
-#define CONFIG_SYS_MAMR_PTA 195
-#elif MPC8XX_HZ == 80000000
-#define CONFIG_SYS_MAMR_PTA 156
-#elif MPC8XX_HZ == 50000000
-#define CONFIG_SYS_MAMR_PTA 98
-#else
-#error Unknown frequency
-#endif
-
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
- */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
-
-/***********************************************************************************************************
-
- Pin definitions:
-
- +------+----------------+--------+------------------------------------------------------------
- | # | Name | Type | Comment
- +------+----------------+--------+------------------------------------------------------------
- | PA3 | OK_ETH_3V | Input | CISCO Ethernet power OK
- | | | | (NetRoute: FEC1, TA: FEC2) (0=power OK)
- | PA6 | P_VCCD1 | Output | TPS2211A PCMCIA
- | PA7 | DCL1_3V | Periph | IDL1 PCM clock
- | PA8 | DSP_DR1 | Periph | IDL1 PCM Data Rx
- | PA9 | L1TXDA | Periph | IDL1 PCM Data Tx
- | PA10 | P_VCCD0 | Output | TPS2211A PCMCIA
- | PA12 | P_SHDN | Output | TPS2211A PCMCIA
- | PA13 | ETH_LOOP | Output | CISCO Loopback remote power
- | | | | (NetRoute: FEC1, TA: FEC2) (1=NORMAL)
- | PA14 | P_VPPD0 | Output | TPS2211A PCMCIA
- | PA15 | P_VPPD1 | Output | TPS2211A PCMCIA
- | PB14 | SPIEN_FXO | Output | SPI CS for FXO daughter-board
- | PB15 | SPIEN_S1 | Output | SPI CS for S-interface 1 (NetRoute only)
- | PB16 | DREQ1 | Output | D channel request for S-interface chip 1.
- | PB17 | L1ST3 | Periph | IDL1 timeslot enable signal for PPC
- | PB18 | L1ST2 | Periph | IDL1 timeslot enable signal for PPC
- | PB19 | SPIEN_S2 | Output | SPI CS for S-interface 2 (NetRoute only)
- | PB20 | SPIEN_SEEPROM | Output | SPI CS for serial eeprom
- | PB21 | LEDIO | Output | Led mode indication for PHY
- | PB22 | UART_CTS | Input | UART CTS
- | PB23 | UART_RTS | Output | UART RTS
- | PB24 | UART_RX | Periph | UART Data Rx
- | PB25 | UART_TX | Periph | UART Data Tx
- | PB26 | RMII-MDC | Periph | Free for future use (MII mgt clock)
- | PB27 | RMII-MDIO | Periph | Free for future use (MII mgt data)
- | PB28 | SPI_RXD_3V | Input | SPI Data Rx
- | PB29 | SPI_TXD | Output | SPI Data Tx
- | PB30 | SPI_CLK | Output | SPI Clock
- | PB31 | RMII1-REFCLK | Periph | RMII reference clock for FEC1
- | PC4 | PHY1_LINK | Input | PHY link state FEC1 (interrupt)
- | PC5 | PHY2_LINK | Input | PHY link state FEC2 (interrupt)
- | PC6 | RMII1-MDINT | Input | PHY prog interrupt FEC1 (interrupt)
- | PC7 | RMII2-MDINT | Input | PHY prog interrupt FEC1 (interrupt)
- | PC8 | P_OC | Input | TPS2211A PCMCIA overcurrent (interrupt) (1=OK)
- | PC9 | COM_HOOK1 | Input | Codec interrupt chip #1 (interrupt)
- | PC10 | COM_HOOK2 | Input | Codec interrupt chip #2 (interrupt)
- | PC11 | COM_HOOK4 | Input | Codec interrupt chip #4 (interrupt)
- | PC12 | COM_HOOK3 | Input | Codec interrupt chip #3 (interrupt)
- | PC13 | F_RY_BY | Input | NAND ready signal (interrupt)
- | PC14 | FAN_OK | Input | Fan status signal (interrupt) (1=OK)
- | PC15 | PC15_DIRECT0 | Periph | PCMCIA DMA request.
- | PD3 | F_ALE | Output | NAND
- | PD4 | F_CLE | Output | NAND
- | PD5 | F_CE | Output | NAND
- | PD6 | DSP_INT | Output | DSP debug interrupt
- | PD7 | DSP_RESET | Output | DSP reset
- | PD8 | RMII_MDC | Periph | MII mgt clock
- | PD9 | SPIEN_C1 | Output | SPI CS for codec #1
- | PD10 | SPIEN_C2 | Output | SPI CS for codec #2
- | PD11 | SPIEN_C3 | Output | SPI CS for codec #3
- | PD12 | FSC2 | Periph | IDL2 frame sync
- | PD13 | DGRANT2 | Input | D channel grant from S #2
- | PD14 | SPIEN_C4 | Output | SPI CS for codec #4
- | PD15 | TP700 | Output | Testpoint for software debugging
- | PE14 | RMII2-TXD0 | Periph | FEC2 transmit data
- | PE15 | RMII2-TXD1 | Periph | FEC2 transmit data
- | PE16 | RMII2-REFCLK | Periph | TA: RMII ref clock for
- | | DCL2 | Periph | NetRoute: PCM clock #2
- | PE17 | TP703 | Output | Testpoint for software debugging
- | PE18 | DGRANT1 | Input | D channel grant from S #1
- | PE19 | RMII2-TXEN | Periph | TA: FEC2 tx enable
- | | PCM2OUT | Periph | NetRoute: Tx data for IDL2
- | PE20 | FSC1 | Periph | IDL1 frame sync
- | PE21 | RMII2-RXD0 | Periph | FEC2 receive data
- | PE22 | RMII2-RXD1 | Periph | FEC2 receive data
- | PE23 | L1ST1 | Periph | IDL1 timeslot enable signal for PPC
- | PE24 | U-N1 | Output | Select user/network for S #1 (0=user)
- | PE25 | U-N2 | Output | Select user/network for S #2 (0=user)
- | PE26 | RMII2-RXDV | Periph | FEC2 valid
- | PE27 | DREQ2 | Output | D channel request for S #2.
- | PE28 | FPGA_DONE | Input | FPGA done signal
- | PE29 | FPGA_INIT | Output | FPGA init signal
- | PE30 | UDOUT2_3V | Input | IDL2 PCM input
- | PE31 | | | Free
- +------+----------------+--------+---------------------------------------------------
-
- Chip selects:
-
- +------+----------------+------------------------------------------------------------
- | # | Name | Comment
- +------+----------------+------------------------------------------------------------
- | CS0 | CS0 | Boot flash
- | CS1 | CS_FLASH | NAND flash
- | CS2 | CS_DSP | DSP
- | CS3 | DCS_DRAM | DRAM
- | CS4 | CS_ER1 | External output register
- +------+----------------+------------------------------------------------------------
-
- Interrupts:
-
- +------+----------------+------------------------------------------------------------
- | # | Name | Comment
- +------+----------------+------------------------------------------------------------
- | IRQ1 | UINTER_3V | S interrupt chips interrupt (common)
- | IRQ3 | IRQ_DSP | DSP interrupt
- | IRQ4 | IRQ_DSP1 | Extra DSP interrupt
- +------+----------------+------------------------------------------------------------
-
-*************************************************************************************************/
-
-#define DSP_SIZE 0x00010000 /* 64K */
-#define NAND_SIZE 0x00010000 /* 64K */
-#define ER_SIZE 0x00010000 /* 64K */
-#define DUMMY_SIZE 0x00010000 /* 64K */
-
-#define DSP_BASE 0xF1000000
-#define NAND_BASE 0xF1010000
-#define ER_BASE 0xF1020000
-#define DUMMY_BASE 0xF1FF0000
-
-/*****************************************************************************/
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-#define CONFIG_SYS_DIRECT_NAND_TFTP
-
-/*****************************************************************************/
-
-#if 1
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*************************************************************************************************/
-
-#define CONFIG_CDP_DEVICE_ID 20
-#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta */
-#define CONFIG_CDP_PORT_ID "eth%d"
-#define CONFIG_CDP_CAPABILITIES 0x00000010
-#define CONFIG_CDP_VERSION "u-boot 1.0" " " U_BOOT_DATE " " U_BOOT_TIME
-#define CONFIG_CDP_PLATFORM "Intracom NetTA"
-#define CONFIG_CDP_TRIGGER 0x20020001
-#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
-#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone? */
-
-/*************************************************************************************************/
-
-#define CONFIG_AUTO_COMPLETE 1
-
-/*************************************************************************************************/
-
-#define CONFIG_CRC32_VERIFY 1
-
-/*************************************************************************************************/
-
-#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
-
-/*************************************************************************************************/
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetTA4 board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#if !defined(CONFIG_NETTA2_VERSION) || CONFIG_NETTA2_VERSION > 2
-#error Unsupported CONFIG_NETTA2 version
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC870 1 /* This is a MPC885 CPU */
-#define CONFIG_NETTA2 1 /* ...on a NetTA2 board */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
-
-/* #define CONFIG_XIN 10000000 */
-#define CONFIG_XIN 50000000
-/* #define MPC8XX_HZ 120000000 */
-#define MPC8XX_HZ 66666666
-
-#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT "echo;"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "tftpboot; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-#define CONFIG_SOURCE
-#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_NISDOMAIN
-
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-#define FEC_ENET 1 /* eth.c needs it that way... */
-#undef CONFIG_SYS_DISCOVER_PHY
-#define CONFIG_MII 1
-#define CONFIG_MII_INIT 1
-#define CONFIG_RMII 1 /* use RMII interface */
-
-#define CONFIG_ETHER_ON_FEC1 1
-#define CONFIG_FEC1_PHY 8 /* phy address of FEC */
-#define CONFIG_FEC1_PHY_NORXERR 1
-
-#define CONFIG_ETHER_ON_FEC2 1
-#define CONFIG_FEC2_PHY 4
-#define CONFIG_FEC2_PHY_NORXERR 1
-
-#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_CDP
-
-
-#define CONFIG_BOARD_EARLY_INIT_F 1
-#define CONFIG_MISC_INIT_R
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-#if defined(DEBUG)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#if CONFIG_NETTA2_VERSION == 2
-#define CONFIG_SYS_FLASH_BASE4 0x40080000
-#endif
-
-#define CONFIG_SYS_RESET_ADDRESS 0x80000000
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#if CONFIG_NETTA2_VERSION == 1
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#elif CONFIG_NETTA2_VERSION == 2
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#endif
-#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x10000
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
-#define CONFIG_ENV_OFFSET 0
-#define CONFIG_ENV_SIZE 0x4000
-
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
-#define CONFIG_ENV_OFFSET_REDUND 0
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#else /* we must activate GPL5 in the SIUMCR for CAN */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#endif /* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- */
-
-#if CONFIG_XIN == 10000000
-
-#if MPC8XX_HZ == 120000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 50000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 25000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 40000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 75000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 10MHz
-#endif
-
-#elif CONFIG_XIN == 50000000
-
-#if MPC8XX_HZ == 120000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 66666666
-#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
- (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
- PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 50MHz
-#endif
-
-#else
-
-#error unsupported XIN freq
-#endif
-
-
-/*
- *-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- *
- * Note: When TBS == 0 the timebase is independent of current cpu clock.
- */
-
-#define SCCR_MASK SCCR_EBDF11
-#if MPC8XX_HZ > 66666666
-#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00 | SCCR_EBDF01)
-#else
-#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
- SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define CONFIG_SYS_DER 0x2002000F*/
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-#if CONFIG_NETTA2_VERSION == 2
-
-#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */
-
-#define CONFIG_SYS_OR4_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-#endif
-
-/*
- * BR3 and OR3 (SDRAM)
- *
- */
-#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
-
-#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock!)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- *
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider = 98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-
-#define CONFIG_SYS_MAMR_PTA 234
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
- */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
-
-/****************************************************************/
-
-#define DSP_SIZE 0x00010000 /* 64K */
-#define NAND_SIZE 0x00010000 /* 64K */
-
-#define DSP_BASE 0xF1000000
-#define NAND_BASE 0xF1010000
-
-/*****************************************************************************/
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-
-/*****************************************************************************/
-
-#if CONFIG_NETTA2_VERSION == 1
-#define STATUS_LED_BIT 0x00000008 /* bit 28 */
-#elif CONFIG_NETTA2_VERSION == 2
-#define STATUS_LED_BIT 0x00000080 /* bit 24 */
-#endif
-
-#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-#define STATUS_LED_STATE STATUS_LED_BLINKING
-
-#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
-#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-#ifndef __ASSEMBLY__
-
-/* LEDs */
-
-/* led_id_t is unsigned int mask */
-typedef unsigned int led_id_t;
-
-#define __led_toggle(_msk) \
- do { \
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \
- } while(0)
-
-#define __led_set(_msk, _st) \
- do { \
- if ((_st)) \
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \
- else \
- ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
- } while(0)
-
-#define __led_init(msk, st) __led_set(msk, st)
-
-#endif
-
-/***********************************************************************************************************
-
- ----------------------------------------------------------------------------------------------
-
- (V1) version 1 of the board
- (V2) version 2 of the board
-
- ----------------------------------------------------------------------------------------------
-
- Pin definitions:
-
- +------+----------------+--------+------------------------------------------------------------
- | # | Name | Type | Comment
- +------+----------------+--------+------------------------------------------------------------
- | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select
- | PA7 | DSP_INT | Output | DSP interrupt
- | PA10 | DSP_RESET | Output | DSP reset
- | PA14 | USBOE | Output | USB (1)
- | PA15 | USBRXD | Output | USB (1)
- | PB19 | BT_RTS | Output | Bluetooth (0)
- | PB23 | BT_CTS | Output | Bluetooth (0)
- | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select
- | PB27 | SPICS_DISP | Output | Display chip select
- | PB28 | SPI_RXD_3V | Input | SPI Data Rx
- | PB29 | SPI_TXD | Output | SPI Data Tx
- | PB30 | SPI_CLK | Output | SPI Clock
- | PC10 | DISPA0 | Output | Display A0
- | PC11 | BACKLIGHT | Output | Display backlit
- | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD
- | | IO_RESET | Output | (V2) General I/O reset
- | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1)
- | | HOOK | Input | (V2) Hook input interrupt
- | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK
- | | F_RY_BY | Input | (V2) NAND F_RY_BY
- | PE17 | F_ALE | Output | NAND F_ALE
- | PE18 | F_CLE | Output | NAND F_CLE
- | PE20 | F_CE | Output | NAND F_CE
- | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select
- | | LED | Output | (V2) LED
- | PE27 | SPICS_ER | Output | External serial register CS
- | PE28 | LEDIO1 | Output | (V1) LED
- | | BKBR1 | Input | (V2) Keyboard input scan
- | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2)
- | | BKBR2 | Input | (V2) Keyboard input scan
- | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2)
- | | BKBR3 | Input | (V2) Keyboard input scan
- | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY
- | | BKBR4 | Input | (V2) Keyboard input scan
- +------+----------------+--------+---------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Serial register input:
-
- +------+----------------+------------------------------------------------------------
- | # | Name | Comment
- +------+----------------+------------------------------------------------------------
- | 4 | HOOK | Hook switch
- | 5 | BT_LINK | Bluetooth link status
- | 6 | HOST_WAKE | Bluetooth host wake up
- | 7 | OK_ETH | Cisco inline power OK status
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Chip selects:
-
- +------+----------------+------------------------------------------------------------
- | # | Name | Comment
- +------+----------------+------------------------------------------------------------
- | CS0 | CS0 | Boot flash
- | CS1 | CS_FLASH | NAND flash
- | CS2 | CS_DSP | DSP
- | CS3 | DCS_DRAM | DRAM
- | CS4 | CS_FLASH2 | (V2) 2nd flash
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Interrupts:
-
- +------+----------------+------------------------------------------------------------
- | # | Name | Comment
- +------+----------------+------------------------------------------------------------
- | IRQ1 | IRQ_DSP | DSP interrupt
- | IRQ3 | S_INTER | DUSLIC ???
- | IRQ4 | F_RY_BY | NAND
- | IRQ7 | IRQ_MAX | MAX 3100 interrupt
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Interrupts on PCMCIA pins:
-
- +------+----------------+------------------------------------------------------------
- | # | Name | Comment
- +------+----------------+------------------------------------------------------------
- | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface
- | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface
- | IP_A2| RMII1_MDINT | PHY interrupt for #1
- | IP_A3| RMII2_MDINT | PHY interrupt for #2
- | IP_A5| HOST_WAKE | (V2) Bluetooth host wake
- | IP_A6| OK_ETH | (V2) Cisco inline power OK
- +------+----------------+------------------------------------------------------------
-
-**************************************************************************************************/
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
-
-/*************************************************************************************************/
-
-/* use board specific hardware */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_HW_WATCHDOG
-
-/*************************************************************************************************/
-
-#define CONFIG_CDP_DEVICE_ID 20
-#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta2 */
-#define CONFIG_CDP_PORT_ID "eth%d"
-#define CONFIG_CDP_CAPABILITIES 0x00000010
-#define CONFIG_CDP_VERSION "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME
-#define CONFIG_CDP_PLATFORM "Intracom NetTA2"
-#define CONFIG_CDP_TRIGGER 0x20020001
-#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
-#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone ? */
-
-/*************************************************************************************************/
-
-#define CONFIG_AUTO_COMPLETE 1
-
-/*************************************************************************************************/
-
-#define CONFIG_CRC32_VERIFY 1
-
-/*************************************************************************************************/
-
-#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
-
-/*************************************************************************************************/
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * MuLogic B.V.
- *
- * (C) Copyright 2002
- * Simple Network Magic Corporation
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* various debug settings */
-#undef CONFIG_SYS_DEVICE_NULLDEV /* null device */
-#undef CONFIG_SILENT_CONSOLE /* silent console */
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* silent console ? */
-#undef DEBUG_FLASH /* debug flash code */
-#undef FLASH_DEBUG /* debug fash code */
-#undef DEBUG_ENV /* debug environment code */
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */
-#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
-#define CONFIG_QS823 1 /* ...on a QS823 module */
-#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-/* Select the target clock speed */
-#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */
-#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */
-#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */
-#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */
-#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */
-
-#ifdef CONFIG_CLOCK_16MHZ
-#define CONFIG_CLOCK_MULT 512
-#endif
-
-#ifdef CONFIG_CLOCK_33MHZ
-#define CONFIG_CLOCK_MULT 1024
-#endif
-
-#ifdef CONFIG_CLOCK_50MHZ
-#define CONFIG_CLOCK_MULT 1525
-#endif
-
-#ifdef CONFIG_CLOCK_66MHZ
-#define CONFIG_CLOCK_MULT 2048
-#endif
-
-#ifdef CONFIG_CLOCK_80MHZ
-#define CONFIG_CLOCK_MULT 2441
-#endif
-
-/* choose flash size, 4Mb or 8Mb */
-#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */
-#undef CONFIG_FLASH_8MB /* board has 8Mb flash */
-
-#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */
-
-#undef CONFIG_8xx_CONS_SMC1
-#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
-#undef CONFIG_8xx_CONS_NONE
-
-#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
-
-#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
-
-/* Define default IP addresses */
-#define CONFIG_IPADDR 192.168.1.99 /* own ip address */
-#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */
-
-/* message to say directly after booting */
-#define CONFIG_PREBOOT "echo '';" \
- "echo 'type:';" \
- "echo 'run boot_nfs to boot to NFS';" \
- "echo 'run boot_flash to boot to flash';" \
- "echo '';" \
- "echo 'run flash_rootfs to install a new rootfs';" \
- "echo 'run flash_env to clear the env sector';" \
- "echo 'run flash_rw to clear the rw fs';" \
- "echo 'run flash_uboot to install a new u-boot';" \
- "echo 'run flash_kernel to install a new kernel';"
-
-/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTCOMMAND "run boot_nfs"
-
-#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */
-
-/* Our flash filesystem looks like this
- *
- * 4Mb board:
- * ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb)
- * ffec 0000 - ffed ffff read-write filesystem (ext2)
- * ffee 0000 - ffef ffff environment
- * fff0 0000 - fff1 ffff u-boot
- * fff2 0000 - ffff ffff linux kernel
- *
- * 8Mb board:
- * ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb)
- * ffec 0000 - ffed ffff read-write filesystem (ext2)
- * ffee 0000 - ffef ffff environment
- * fff0 0000 - fff1 ffff u-boot
- * fff2 0000 - ffff ffff linux kernel
- *
- */
-
-/* environment for 4Mb board */
-#ifdef CONFIG_FLASH_4MB
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "serial#=QS823\0" \
- "hostname=qs823\0" \
- "netdev=eth0\0" \
- "ethaddr=00:01:02:B4:36:56\0" \
- "rootpath=/exports/rootfs\0" \
- "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
- /* fill in variables */ \
- "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
- "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
- "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
- /* commands */ \
- "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
- "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
- /* reinstall flash parts */ \
- "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \
- "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
- "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
- "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \
- "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
-#endif /* CONFIG_FLASH_4MB */
-
-/* environment for 8Mb board */
-#ifdef CONFIG_FLASH_8MB
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "serial#=QS823\0" \
- "hostname=qs823\0" \
- "netdev=eth0\0" \
- "ethaddr=00:01:02:B4:36:56\0" \
- "rootpath=/exports/rootfs\0" \
- "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
- /* fill in variables */ \
- "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
- "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
- "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
- /* commands */ \
- "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
- "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
- /* reinstall flash parts */ \
- "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \
- "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
- "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
- "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \
- "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
-#endif /* CONFIG_FLASH_8MB */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#undef CONFIG_STATUS_LED /* Status LED disabled */
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_RUN
-
-
-/*-----------------------------------------------------------------------
- * Environment variable storage is in FLASH, one sector before U-boot
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */
-#define CONFIG_ENV_SIZE 0x2000 /* 8kb */
-#define CONFIG_ENV_ADDR 0xffee0000 /* address of env sector */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */
-
-#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */
-#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 /* U-boot location */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * TODO flash parameters
- * FLASH organization for Intel Strataflash
- */
-#undef CONFIG_SYS_FLASH_16BIT /* 32-bit wide flash memory */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-
-#ifdef CONFIG_WATCHDOG
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- */
-
-/* MF (Multiplication Factor of SPLL) */
-/* Sets the QS823 to specified clock from 32KHz clock at EXTAL. */
-#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20)
-#define CONFIG_SYS_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
-#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
-#define CONFIG_SYS_BRGCLK_PRESCALE 1
-#endif
-
-#if defined(CONFIG_CLOCK_66MHZ)
-#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
-#define CONFIG_SYS_BRGCLK_PRESCALE 4
-#endif
-
-#if defined(CONFIG_CLOCK_80MHZ)
-#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
-#define CONFIG_SYS_BRGCLK_PRESCALE 4
-#endif
-
-#define SCCR_MASK CONFIG_SYS_SCCR
-
-/*-----------------------------------------------------------------------
- * Debug Enable Register
- * 0x73E67C0F - All interrupts handled by BDM
- * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
- *-----------------------------------------------------------------------
-#define CONFIG_SYS_DER 0x73E67C0F
-#define CONFIG_SYS_DER 0x0082400F
-
- #-------------------------------------------------------------------------
- # Program the Debug Enable Register (DER). This register provides the user
- # with the reason for entering into the debug mode. We want all conditions
- # to end up as an exception. We don't want to enter into debug mode for
- # any condition. See the back of of the Development Support section of the
- # MPC860 User Manual for a description of this register.
- #-------------------------------------------------------------------------
-*/
-#define CONFIG_SYS_DER 0
-
-/*-----------------------------------------------------------------------
- * Memory Controller Initialization Constants
- *-----------------------------------------------------------------------
- */
-
-/*
- * BR0 and OR0 (AMD dual FLASH devices)
- * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
- */
-#define CONFIG_SYS_PRELIM_OR_AM
-#define CONFIG_SYS_OR_TIMING_FLASH
-
-/*
- *-----------------------------------------------------------------------
- * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
- * flash that resides on the QS823.
- *-----------------------------------------------------------------------
- */
-
-/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */
-/* represents a minumum 32K block size. */
-#define vBR0_BA ((0xFF80 << 16) + (0 << 15))
-#define CONFIG_SYS_BR0_PRELIM (vBR0_BA | BR_V)
-
-/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */
-/* which defines a 8 Mbyte memory block. */
-#define vOR0_AM ((0xFF80 << 16) + (0 << 15))
-
-#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
-/* 0101 = Add a 5 clock cycle wait state */
-#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
-#endif
-
-#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
-/* 0011 = Add a 3 clock cycle wait state */
-/* 29.8ns clock * (3 + 2) = 149ns cycle time */
-#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
-#endif
-
-#if defined(CONFIG_CLOCK_16MHZ)
-/* 0010 = Add a 2 clock cycle wait state */
-#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
-#endif
-
-/*
- * BR1 and OR1 (SDRAM)
- * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
- * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation)
- * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
- * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
- */
-
-#define SDRAM_BASE 0x00000000 /* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
-
-/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which
- * represents a 128 Mbyte block the DRAM in
- * this address base.
- */
-#define vOR1_AM ((0xF800 << 16) + (0 << 15))
-#define vBR1_BA ((0x0000 << 16) + (0 << 15))
-#define CONFIG_SYS_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI)
-#define CONFIG_SYS_BR1 (vBR1_BA | BR_MS_UPMA | BR_V)
-
-/* Machine A Mode Register */
-
-/* PTA Periodic Timer A */
-
-#if defined(CONFIG_CLOCK_80MHZ)
-#define vMAMR_PTA (19 << 24)
-#endif
-
-#if defined(CONFIG_CLOCK_66MHZ)
-#define vMAMR_PTA (16 << 24)
-#endif
-
-#if defined(CONFIG_CLOCK_50MHZ)
-#define vMAMR_PTA (195 << 24)
-#endif
-
-#if defined(CONFIG_CLOCK_33MHZ)
-#define vMAMR_PTA (131 << 24)
-#endif
-
-#if defined(CONFIG_CLOCK_16MHZ)
-#define vMAMR_PTA (65 << 24)
-#endif
-
-/* For boards with 16M of SDRAM */
-#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */
-#define CONFIG_SYS_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
-MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/* For boards with 32M of SDRAM */
-#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */
-#define CONFIG_SYS_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
-MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-
-/* Memory Periodic Timer Prescaler Register */
-
-#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
-/* Divide by 32 */
-#define CONFIG_SYS_MPTPR 0x02
-#endif
-
-#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
-/* Divide by 16 */
-#define CONFIG_SYS_MPTPR 0x04
-#endif
-
-/*
- * BR2 and OR2 (Unused)
- * Base address = 0xF020_0000 - 0xF020_0FFF
- *
- */
-#define CONFIG_SYS_OR2_PRELIM 0xFFF00000
-#define CONFIG_SYS_BR2_PRELIM 0xF0200000
-
-/*
- * BR3 and OR3 (External Bus CS3)
- * Base address = 0xF030_0000 - 0xF030_0FFF
- *
- */
-#define CONFIG_SYS_OR3_PRELIM 0xFFF00000
-#define CONFIG_SYS_BR3_PRELIM 0xF0300000
-
-/*
- * BR4 and OR4 (External Bus CS3)
- * Base address = 0xF040_0000 - 0xF040_0FFF
- *
- */
-#define CONFIG_SYS_OR4_PRELIM 0xFFF00000
-#define CONFIG_SYS_BR4_PRELIM 0xF0400000
-
-
-/*
- * BR4 and OR4 (External Bus CS3)
- * Base address = 0xF050_0000 - 0xF050_0FFF
- *
- */
-#define CONFIG_SYS_OR5_PRELIM 0xFFF00000
-#define CONFIG_SYS_BR5_PRELIM 0xF0500000
-
-/*
- * BR6 and OR6 (Unused)
- * Base address = 0xF060_0000 - 0xF060_0FFF
- *
- */
-#define CONFIG_SYS_OR6_PRELIM 0xFFF00000
-#define CONFIG_SYS_BR6_PRELIM 0xF0600000
-
-/*
- * BR7 and OR7 (Unused)
- * Base address = 0xF070_0000 - 0xF070_0FFF
- *
- */
-#define CONFIG_SYS_OR7_PRELIM 0xFFF00000
-#define CONFIG_SYS_BR7_PRELIM 0xF0700000
-
-/*
- * Sanity checks
- */
-#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
-#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
-#endif
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * MuLogic B.V.
- *
- * (C) Copyright 2002
- * Simple Network Magic Corporation
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* various debug settings */
-#undef CONFIG_SYS_DEVICE_NULLDEV /* null device */
-#undef CONFIG_SILENT_CONSOLE /* silent console */
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* silent console ? */
-#undef DEBUG_FLASH /* debug flash code */
-#undef FLASH_DEBUG /* debug fash code */
-#undef DEBUG_ENV /* debug environment code */
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */
-#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
-#define CONFIG_QS850 1 /* ...on a QS850 module */
-#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-/* Select the target clock speed */
-#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */
-#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */
-#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */
-#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */
-#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */
-
-#ifdef CONFIG_CLOCK_16MHZ
-#define CONFIG_CLOCK_MULT 512
-#endif
-
-#ifdef CONFIG_CLOCK_33MHZ
-#define CONFIG_CLOCK_MULT 1024
-#endif
-
-#ifdef CONFIG_CLOCK_50MHZ
-#define CONFIG_CLOCK_MULT 1525
-#endif
-
-#ifdef CONFIG_CLOCK_66MHZ
-#define CONFIG_CLOCK_MULT 2048
-#endif
-
-#ifdef CONFIG_CLOCK_80MHZ
-#define CONFIG_CLOCK_MULT 2441
-#endif
-
-/* choose flash size, 4Mb or 8Mb */
-#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */
-#undef CONFIG_FLASH_8MB /* board has 8Mb flash */
-
-#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
-#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
-
-#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
-
-/* Define default IP addresses */
-#define CONFIG_IPADDR 192.168.1.99 /* own ip address */
-#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */
-
-/* message to say directly after booting */
-#define CONFIG_PREBOOT "echo '';" \
- "echo 'type:';" \
- "echo 'run boot_nfs to boot to NFS';" \
- "echo 'run boot_flash to boot to flash';" \
- "echo '';" \
- "echo 'run flash_rootfs to install a new rootfs';" \
- "echo 'run flash_env to clear the env sector';" \
- "echo 'run flash_rw to clear the rw fs';" \
- "echo 'run flash_uboot to install a new u-boot';" \
- "echo 'run flash_kernel to install a new kernel';"
-
-/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_BOOTCOMMAND "run boot_nfs"
-
-#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */
-
-/* Our flash filesystem looks like this
- *
- * 4Mb board:
- * ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb)
- * ffec 0000 - ffed ffff read-write filesystem (ext2)
- * ffee 0000 - ffef ffff environment
- * fff0 0000 - fff1 ffff u-boot
- * fff2 0000 - ffff ffff linux kernel
- *
- * 8Mb board:
- * ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb)
- * ffec 0000 - ffed ffff read-write filesystem (ext2)
- * ffee 0000 - ffef ffff environment
- * fff0 0000 - fff1 ffff u-boot
- * fff2 0000 - ffff ffff linux kernel
- *
- */
-
-/* environment for 4Mb board */
-#ifdef CONFIG_FLASH_4MB
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "serial#=QS850\0" \
- "hostname=qs850\0" \
- "netdev=eth0\0" \
- "ethaddr=00:01:02:B4:36:56\0" \
- "rootpath=/exports/rootfs\0" \
- "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
- /* fill in variables */ \
- "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
- "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
- "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
- /* commands */ \
- "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
- "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
- /* reinstall flash parts */ \
- "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \
- "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
- "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
- "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \
- "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
-#endif /* CONFIG_FLASH_4MB */
-
-/* environment for 8Mb board */
-#ifdef CONFIG_FLASH_8MB
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "serial#=QS850\0" \
- "hostname=qs850\0" \
- "netdev=eth0\0" \
- "ethaddr=00:01:02:B4:36:56\0" \
- "rootpath=/exports/rootfs\0" \
- "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
- /* fill in variables */ \
- "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
- "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
- "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
- /* commands */ \
- "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
- "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
- /* reinstall flash parts */ \
- "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \
- "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
- "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
- "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \
- "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
-#endif /* CONFIG_FLASH_8MB */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#undef CONFIG_STATUS_LED /* Status LED disabled */
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-
-/*
- * Command line configuration.
- */
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_RUN
-
-
-/*-----------------------------------------------------------------------
- * Environment variable storage is in FLASH, one sector before U-boot
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */
-#define CONFIG_ENV_SIZE 0x2000 /* 8kb */
-#define CONFIG_ENV_ADDR 0xffee0000 /* address of env sector */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */
-
-#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */
-#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 /* U-boot location */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * TODO flash parameters
- * FLASH organization for Intel Strataflash
- */
-#undef CONFIG_SYS_FLASH_16BIT /* 32-bit wide flash memory */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-
-#ifdef CONFIG_WATCHDOG
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- */
-
-/* MF (Multiplication Factor of SPLL) */
-/* Sets the QS850 to specified clock from 32KHz clock at EXTAL. */
-#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20)
-#define CONFIG_SYS_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
-#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
-#define CONFIG_SYS_BRGCLK_PRESCALE 1
-#endif
-
-#if defined(CONFIG_CLOCK_66MHZ)
-#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
-#define CONFIG_SYS_BRGCLK_PRESCALE 4
-#endif
-
-#if defined(CONFIG_CLOCK_80MHZ)
-#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
-#define CONFIG_SYS_BRGCLK_PRESCALE 4
-#endif
-
-#define SCCR_MASK CONFIG_SYS_SCCR
-
-/*-----------------------------------------------------------------------
- * Debug Enable Register
- * 0x73E67C0F - All interrupts handled by BDM
- * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
- *-----------------------------------------------------------------------
-#define CONFIG_SYS_DER 0x73E67C0F
-#define CONFIG_SYS_DER 0x0082400F
-
- #-------------------------------------------------------------------------
- # Program the Debug Enable Register (DER). This register provides the user
- # with the reason for entering into the debug mode. We want all conditions
- # to end up as an exception. We don't want to enter into debug mode for
- # any condition. See the back of of the Development Support section of the
- # MPC860 User Manual for a description of this register.
- #-------------------------------------------------------------------------
-*/
-#define CONFIG_SYS_DER 0
-
-/*-----------------------------------------------------------------------
- * Memory Controller Initialization Constants
- *-----------------------------------------------------------------------
- */
-
-/*
- * BR0 and OR0 (AMD dual FLASH devices)
- * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
- */
-#define CONFIG_SYS_PRELIM_OR_AM
-#define CONFIG_SYS_OR_TIMING_FLASH
-
-/*
- *-----------------------------------------------------------------------
- * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
- * flash that resides on the QS850.
- *-----------------------------------------------------------------------
- */
-
-/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */
-/* represents a minumum 32K block size. */
-#define vBR0_BA ((0xFF80 << 16) + (0 << 15))
-#define CONFIG_SYS_BR0_PRELIM (vBR0_BA | BR_V)
-
-/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */
-/* which defines a 8 Mbyte memory block. */
-#define vOR0_AM ((0xFF80 << 16) + (0 << 15))
-
-#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
-/* 0101 = Add a 5 clock cycle wait state */
-#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
-#endif
-
-#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
-/* 0011 = Add a 3 clock cycle wait state */
-/* 29.8ns clock * (3 + 2) = 149ns cycle time */
-#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
-#endif
-
-#if defined(CONFIG_CLOCK_16MHZ)
-/* 0010 = Add a 2 clock cycle wait state */
-#define CONFIG_SYS_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
-#endif
-
-/*
- * BR1 and OR1 (SDRAM)
- * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
- * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation)
- * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
- * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
- */
-
-#define SDRAM_BASE 0x00000000 /* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
-
-/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which
- * represents a 128 Mbyte block the DRAM in
- * this address base.
- */
-#define vOR1_AM ((0xF800 << 16) + (0 << 15))
-#define vBR1_BA ((0x0000 << 16) + (0 << 15))
-#define CONFIG_SYS_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI)
-#define CONFIG_SYS_BR1 (vBR1_BA | BR_MS_UPMA | BR_V)
-
-/* Machine A Mode Register */
-
-/* PTA Periodic Timer A */
-
-#if defined(CONFIG_CLOCK_80MHZ)
-#define vMAMR_PTA (19 << 24)
-#endif
-
-#if defined(CONFIG_CLOCK_66MHZ)
-#define vMAMR_PTA (16 << 24)
-#endif
-
-#if defined(CONFIG_CLOCK_50MHZ)
-#define vMAMR_PTA (195 << 24)
-#endif
-
-#if defined(CONFIG_CLOCK_33MHZ)
-#define vMAMR_PTA (131 << 24)
-#endif
-
-#if defined(CONFIG_CLOCK_16MHZ)
-#define vMAMR_PTA (65 << 24)
-#endif
-
-/* For boards with 16M of SDRAM */
-#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */
-#define CONFIG_SYS_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
-MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/* For boards with 32M of SDRAM */
-#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */
-#define CONFIG_SYS_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
-MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-
-/* Memory Periodic Timer Prescaler Register */
-
-#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
-/* Divide by 32 */
-#define CONFIG_SYS_MPTPR 0x02
-#endif
-
-#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
-/* Divide by 16 */
-#define CONFIG_SYS_MPTPR 0x04
-#endif
-
-/*
- * BR2 and OR2 (Unused)
- * Base address = 0xF020_0000 - 0xF020_0FFF
- *
- */
-#define CONFIG_SYS_OR2_PRELIM 0xFFF00000
-#define CONFIG_SYS_BR2_PRELIM 0xF0200000
-
-/*
- * BR3 and OR3 (External Bus CS3)
- * Base address = 0xF030_0000 - 0xF030_0FFF
- *
- */
-#define CONFIG_SYS_OR3_PRELIM 0xFFF00000
-#define CONFIG_SYS_BR3_PRELIM 0xF0300000
-
-/*
- * BR4 and OR4 (External Bus CS3)
- * Base address = 0xF040_0000 - 0xF040_0FFF
- *
- */
-#define CONFIG_SYS_OR4_PRELIM 0xFFF00000
-#define CONFIG_SYS_BR4_PRELIM 0xF0400000
-
-
-/*
- * BR4 and OR4 (External Bus CS3)
- * Base address = 0xF050_0000 - 0xF050_0FFF
- *
- */
-#define CONFIG_SYS_OR5_PRELIM 0xFFF00000
-#define CONFIG_SYS_BR5_PRELIM 0xF0500000
-
-/*
- * BR6 and OR6 (Unused)
- * Base address = 0xF060_0000 - 0xF060_0FFF
- *
- */
-#define CONFIG_SYS_OR6_PRELIM 0xFFF00000
-#define CONFIG_SYS_BR6_PRELIM 0xF0600000
-
-/*
- * BR7 and OR7 (Unused)
- * Base address = 0xF070_0000 - 0xF070_0FFF
- *
- */
-#define CONFIG_SYS_OR7_PRELIM 0xFFF00000
-#define CONFIG_SYS_BR7_PRELIM 0xF0700000
-
-/*
- * Sanity checks
- */
-#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
-#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
-#endif
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2003
- * MuLogic B.V.
- *
- * (C) Copyright 2002
- * Simple Network Magic Corporation
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* various debug settings */
-#undef CONFIG_SYS_DEVICE_NULLDEV /* null device */
-#undef CONFIG_SILENT_CONSOLE /* silent console */
-#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* silent console ? */
-#undef DEBUG_FLASH /* debug flash code */
-#undef FLASH_DEBUG /* debug fash code */
-#undef DEBUG_ENV /* debug environment code */
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */
-#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */
-
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
-#define CONFIG_QS860T 1 /* ...on a QS860T module */
-
-/* Start address of 512K Socketed Flash */
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */
-#define CONFIG_MII
-#define FEC_INTERRUPT SIU_LEVEL1
-#undef CONFIG_SCC1_ENET /* SCC1 10BaseT ethernet */
-#define CONFIG_SYS_DISCOVER_PHY
-
-#undef CONFIG_8xx_CONS_SMC1
-#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC */
-#undef CONFIG_8xx_CONS_NONE
-
-#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-/* Pass clocks to Linux 2.4.18 in Hz */
-#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo 'Type \\\"run flash_nfs\\\" to mount root filesystem over NFS';" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-/* TODO compare against CADM860 */
-#define CONFIG_BOOTCOMMAND "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#undef CONFIG_STATUS_LED /* Status LED disabled */
-
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DATE
-
-
-/* TODO */
-#if 0
-/* Look at these */
-CONFIG_IPADDR
-CONFIG_SERVERIP
-CONFIG_I2C
-CONFIG_SPI
-#endif
-
-/*
- * Environment variable storage is in NVRAM
- */
-#define CONFIG_ENV_IS_IN_NVRAM 1
-#define CONFIG_ENV_SIZE 0x00001000 /* We use only the last 4K for PPCBoot */
-#define CONFIG_ENV_ADDR 0xD100E000
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-/* TODO - size? */
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFF00000
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/* TODO flash parameters */
-/*-----------------------------------------------------------------------
- * FLASH organization for Intel Strataflash
- */
-#define CONFIG_SYS_FLASH_16BIT 1 /* 16-bit wide flash memory */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#undef CONFIG_ENV_IS_IN_FLASH
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI)
-#else
-#define CONFIG_SYS_SYPCR 0xFFFFFF88
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR 0x00620000
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_TBSCR 0x00C3
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_PISCR 0x0082
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_PLPRCR 0x0090D000
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR 0x02000000
-
-
-/*-----------------------------------------------------------------------
- * Debug Enable Register
- * 0x73E67C0F - All interrupts handled by BDM
- * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
- *-----------------------------------------------------------------------
-#define CONFIG_SYS_DER 0x73E67C0F
-*/
-#define CONFIG_SYS_DER 0x0082400F
-
-
-/*-----------------------------------------------------------------------
- * Memory Controller Initialization Constants
- *-----------------------------------------------------------------------
- */
-
-/*
- * BR0 and OR0 (AMD 512K Socketed FLASH)
- * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
- */
-#define CONFIG_SYS_PRELIM_OR_AM
-#define CONFIG_SYS_OR_TIMING_FLASH
-
-#define FLASH_BASE0_PRELIM 0xFFF00001
-#define CONFIG_SYS_OR0_PRELIM 0xFFF80D42
-#define CONFIG_SYS_BR0_PRELIM 0xFFF00401
-
-
-/*
- * BR1 and OR1 (Intel 8M StrataFLASH)
- * Base address = 0xD000_0000 - 0xD07F_FFFF
- */
-
-#define FLASH_BASE1_PRELIM 0xD0000000
-#define CONFIG_SYS_OR1_PRELIM 0xFF800D42
-#define CONFIG_SYS_BR1_PRELIM 0xD0000801
-/* #define CONFIG_SYS_OR1 0xFF800D42 */
-/* #define CONFIG_SYS_BR1 0xD0000801 */
-
-
-/*
- * BR2 and OR2 (SDRAM)
- * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
- * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
- * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
- *
- */
-#define SDRAM_BASE 0x00000000 /* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
-
-/* SDRAM timing */
-#define SDRAM_TIMING 0x00000A00
-
-/* For boards with 16M of SDRAM */
-#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */
-#define CONFIG_SYS_16M_MBMR 0x18802114 /* Mem Periodic Timer Prescaler */
-
-/* For boards with 64M of SDRAM */
-#define SDRAM_64M_MAX_SIZE 0x04000000 /* max 64MB SDRAM */
-/* TODO - determine real value */
-#define CONFIG_SYS_64M_MBMR 0x18802114 /* Mem Period Timer Prescaler */
-
-#define CONFIG_SYS_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING)
-#define CONFIG_SYS_BR2 (SDRAM_BASE | 0x000000C1)
-
-
-/*
- * BR3 and OR3 (NVRAM, Sipex, NAND Flash)
- * Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM)
- * Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register)
- * Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register)
- * Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register)
- *
- */
-
-#define CONFIG_SYS_OR3_PRELIM 0xFFC00DF6
-#define CONFIG_SYS_BR3_PRELIM 0xD1000401
-/* #define CONFIG_SYS_OR3 0xFFC00DF6 */
-/* #define CONFIG_SYS_BR3 0xD1000401 */
-
-
-/*
- * BR4 and OR4 (Unused)
- * Base address = 0xE000_0000 - 0xE3FF_FFFF
- *
- */
-
-#define CONFIG_SYS_OR4_PRELIM 0xFF000000
-#define CONFIG_SYS_BR4_PRELIM 0xE0000000
-/* #define CONFIG_SYS_OR4 0xFF000000 */
-/* #define CONFIG_SYS_BR4 0xE0000000 */
-
-
-/*
- * BR5 and OR5 (Expansion bus)
- * Base address = 0xE400_0000 - 0xE7FF_FFFF
- *
- */
-
-#define CONFIG_SYS_OR5_PRELIM 0xFF000000
-#define CONFIG_SYS_BR5_PRELIM 0xE4000000
-/* #define CONFIG_SYS_OR5 0xFF000000 */
-/* #define CONFIG_SYS_BR5 0xE4000000 */
-
-
-/*
- * BR6 and OR6 (Expansion bus)
- * Base address = 0xE800_0000 - 0xEBFF_FFFF
- *
- */
-
-#define CONFIG_SYS_OR6_PRELIM 0xFF000000
-#define CONFIG_SYS_BR6_PRELIM 0xE8000000
-/* #define CONFIG_SYS_OR6 0xFF000000 */
-/* #define CONFIG_SYS_BR6 0xE8000000 */
-
-
-/*
- * BR7 and OR7 (Expansion bus)
- * Base address = 0xEC00_0000 - 0xEFFF_FFFF
- *
- */
-
-#define CONFIG_SYS_OR7_PRELIM 0xFF000000
-#define CONFIG_SYS_BR7_PRELIM 0xE8000000
-/* #define CONFIG_SYS_OR7 0xFF000000 */
-/* #define CONFIG_SYS_BR7 0xE8000000 */
-
-/*
- * Sanity checks
- */
-#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
-#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
-#endif
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified by Udi Finkelstein udif@udif.com
- * For the RBC823 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
-#define CONFIG_RBC823 1 /* ...on a RBC823 module */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#if 0
-#define DEBUG 1
-#define CONFIG_LAST_STAGE_INIT
-#endif
-#define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */
-#define CONFIG_LCD 1 /* use LCD controller ... */
-#define CONFIG_MPC8XX_LCD
-#define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */
-
-#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
-#undef CONFIG_8xx_CONS_SMC1
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
-#if 1
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-#define CONFIG_8xx_GCLK_FREQ 48000000L
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_STATUS_LED 1 /* Status LED enabled */
-
-#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#undef CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */
-
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED 40000
-#define CONFIG_SYS_I2C_SLAVE 0xfe
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_WRITE_DELAY_MS 10
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_BMP
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_CDP
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_KGDB
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PORTIO
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_SDRAM
-
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_XIMG
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x0100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFF00000
-#if defined(DEBUG)
-#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-/*
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-*/
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- */
-
-/*
- * for 48 MHz, we use a 4 MHz clock * 12
- */
-#define CONFIG_SYS_PLPRCR \
- ( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_RTDIV | SCCR_RTSEL | SCCR_CRQEN | \
- SCCR_PRQEN | SCCR_EBDF00 | \
- SCCR_COM01 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD001 | \
- SCCR_DFALCD00)
-
-#ifdef NOT_USED
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define CONFIG_SYS_DER 0x2002000F*/
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x04000000 /* D.O.C Millenium */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
-
-/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
-
-#define CONFIG_SYS_OR_TIMING_MSYS (OR_ACS_DIV1 | OR_BI)
-
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
-
-#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_MSYS)
-#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
- BR_PS_8 | BR_V)
-
-/*
- * BR4 and OR4 (SDRAM)
- *
- */
-#define SDRAM_BASE4_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
-/*
- * SDRAM timing:
- */
-#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM)
-
-#define CONFIG_SYS_OR4_PRELIM (~(SDRAM_MAX_SIZE-1) | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 187 /* start with divider for 48 MHz */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT ""
-#define MTDPARTS_DEFAULT ""
-*/
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
- * U-BOOT port on RPXlite board
- */
-
-/*
- * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
- * U-BOOT port on RPXlite DW version board--RPXlite_DW
- * June 8 ,2004
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-/* #define DEBUG 1 */
-/* #define DEPLOYMENT 1 */
-
-#undef CONFIG_MPC860
-#define CONFIG_MPC823 1 /* This is a MPC823e CPU. */
-#define CONFIG_RPXLITE 1 /* RPXlite DW version board */
-
-#define CONFIG_SYS_TEXT_BASE 0xff000000
-
-#ifdef CONFIG_LCD /* with LCD controller ? */
-#define CONFIG_MPC8XX_LCD
-#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
-#endif
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */
-
-#ifdef DEBUG
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */
-
-#ifdef DEPLOYMENT
-#define CONFIG_BOOT_RETRY_TIME -1
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT \
- "autoboot in %d seconds (stop with 'st')...\n", bootdelay
-#define CONFIG_AUTOBOOT_STOP_STR "st"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY 1
-#define CONFIG_BOOT_RETRY_MIN 1
-#endif /* DEPLOYMENT */
-#endif /* DEBUG */
-
-/* pre-boot commands */
-#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 " \
- "root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "gatewayip=172.16.115.254\0" \
- "netmask=255.255.255.0\0" \
- "kernel_addr=ff040000\0" \
- "ramdisk_addr=ff200000\0" \
- "ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} " \
- "${filesize};md ${kernel_addr};" \
- "echo kernel updating finished\0" \
- "uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 " \
- "${filesize};md ff000000;" \
- "echo u-boot updating finished\0" \
- "eu=protect off 1:6;era 1:6;reset\0" \
- "lcd=setenv stdout lcd;setenv stdin lcd\0" \
- "ser=setenv stdout serial;setenv stdin serial\0" \
- "verify=no"
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#if 1 /* Enable this stuff could make image enlarge about 25KB. Mask it if you
- don't want the advanced function */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_DHCP
-
-#ifdef CONFIG_SPLASH_SCREEN
-#define CONFIG_CMD_BMP
-#endif
-
-
-/* test-only */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-
-#define CONFIG_NETCONSOLE
-
-#endif /* 1 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "u-boot>" /* Monitor Command Prompt */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFA200000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-
-#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE 0xFF000000
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_ADDR 0xFA000100
-#define CONFIG_ENV_SIZE 0x1000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
-#endif /* CONFIG_ENV_IS_IN_NVRAM */
-
-#define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 32-bit 12-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif /* We can get SYPCR: 0xFFFF0689. */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 32-bit 12-30
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) /* SIUMCR:0x00000800 */
-
-/*---------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 16-bit 12-16
- *---------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
-/* TBSCR: 0x00C3 [SAM] */
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 16-bit 12-18
- *-----------------------------------------------------------------------
- * [RTC enabled but not stopped on FRZ]
- */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1 */
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 16-bit 12-23
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- * [Periodic timer enabled,Periodic timer interrupt disable. ]
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) /* PISCR:0x0083 */
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 32-bit 5-7
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- */
-/* up to 64 MHz we use a 1:2 clock */
-#if defined(RPXlite_64MHz)
-#define CONFIG_SYS_PLPRCR ( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) /*PLPRCR: 0x00700000. */
-#else
-#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
-#endif
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 5-3
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF00
-/* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */
-#if defined(RPXlite_64MHz)
-#define CONFIG_SYS_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */
-#else
-#define CONFIG_SYS_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */
-#endif
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-#define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFC000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
-
-/*
- * BR1 and OR1 (SDRAM)
- *
- */
-#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
-#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB in system */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
-#define CONFIG_SYS_OR_AM_SDRAM (-(SDRAM_MAX_SIZE & OR_AM_MSK))
-#define CONFIG_SYS_OR1_PRELIM ( CONFIG_SYS_OR_AM_SDRAM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/* RPXlite mem setting */
-#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */
-#define CONFIG_SYS_OR3_PRELIM 0xFF7F8900
-#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
-#define CONFIG_SYS_OR4_PRELIM 0xFFFE0040
-
-/*
- * Memory Periodic Timer Prescaler
- */
-/* periodic timer for refresh */
-#if defined(RPXlite_64MHz)
-#define CONFIG_SYS_MAMR_PTA 32
-#else
-#define CONFIG_SYS_MAMR_PTA 20
-#endif
-
-/*
- * Refresh clock Prescalar
- */
-#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10)
-/* CONFIG_SYS_MAMR_9COL:0x20904000 @ 64MHz */
-
-/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
-/* Configuration variable added by yooth. */
-/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
-/*
- * BCSRx
- *
- * Board Status and Control Registers
- *
- */
-#define BCSR0 0xFA400000
-#define BCSR1 0xFA400001
-#define BCSR2 0xFA400002
-#define BCSR3 0xFA400003
-
-#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
-#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
-#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
-#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
-#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
-#define BCSR0_COLTEST 0x20
-#define BCSR0_ETHLPBK 0x40
-#define BCSR0_ETHEN 0x80
-
-#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
-#define BCSR1_PCVCTL6 0x02
-#define BCSR1_PCVCTL5 0x04
-#define BCSR1_PCVCTL4 0x08
-#define BCSR1_IPB5SEL 0x10
-
-#define BCSR1_SMC1CTS 0x40 /* Added by SAM. */
-#define BCSR1_SMC1TRS 0x80 /* Added by SAM. */
-
-#define BCSR2_ENRTCIRQ 0x01 /* Added by SAM. */
-#define BCSR2_ENBRG1 0x04 /* Added by SAM. */
-
-#define BCSR2_ENPA5HDR 0x08 /* USB Control */
-#define BCSR2_ENUSBCLK 0x10
-#define BCSR2_USBPWREN 0x20
-#define BCSR2_USBSPD 0x40
-#define BCSR2_USBSUSP 0x80
-
-#define BCSR3_BWKAPWR 0x01 /* Changed by SAM. Backup battery situation */
-#define BCSR3_IRQRTC 0x02 /* Changed by SAM. NVRAM Battery */
-#define BCSR3_RDY_BSY 0x04 /* Changed by SAM. Flash Operation */
-#define BCSR3_MPLX_LIN 0x08 /* Changed by SAM. Linear or Multiplexed address Mode */
-
-#define BCSR3_D27 0x10 /* Dip Switch settings */
-#define BCSR3_D26 0x20
-#define BCSR3_D25 0x40
-#define BCSR3_D24 0x80
-
-/*
- * Environment setting
- */
-#define CONFIG_ETHADDR 00:10:EC:00:37:5B
-#define CONFIG_IPADDR 172.16.115.7
-#define CONFIG_SERVERIP 172.16.115.6
-#define CONFIG_ROOTPATH "/workspace/myfilesystem/target/"
-#define CONFIG_BOOTFILE "uImage.rpxusb"
-#define CONFIG_HOSTNAME LITE_H1_DW
-
-#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * include/configs/alt.h
+ * This file is alt board configuration.
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ALT_H
+#define __ALT_H
+
+#undef DEBUG
+#define CONFIG_ARMV7
+#define CONFIG_R8A7794
+#define CONFIG_RMOBILE
+#define CONFIG_RMOBILE_BOARD_STRING "Alt"
+#define CONFIG_SH_GPIO_PFC
+
+#include <asm/arch/rmobile.h>
+
+#define CONFIG_CMD_EDITENV
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+
+#define CONFIG_SYS_TEXT_BASE 0xE6304000
+#define CONFIG_SYS_THUMB_BUILD
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_OF_LIBFDT
+#define BOARD_LATE_INIT
+
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS ""
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_TMU_TIMER
+
+#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
+#define STACK_AREA_SIZE 0xC000
+#define LOW_LEVEL_MERAM_STACK \
+ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define ALT_SDRAM_BASE 0x40000000
+#define ALT_SDRAM_SIZE (1024u * 1024 * 1024)
+#define ALT_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE 512
+#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF2
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START (ALT_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
+ 504 * 1024 * 1024)
+#undef CONFIG_SYS_ALT_MEMTEST
+#undef CONFIG_SYS_MEMTEST_SCRATCH
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE (ALT_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE (ALT_UBOOT_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0)
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SH_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_QUAD
+#define CONFIG_SYS_NO_FLASH
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE (256 * 1024)
+#define CONFIG_ENV_ADDR 0xC0000
+#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootm_low=0x40e00000\0" \
+ "bootm_size=0x100000\0" \
+
+/* SH Ether */
+#define CONFIG_NET_MULTI
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT 0
+#define CONFIG_SH_ETHER_PHY_ADDR 0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK 20000000u
+#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
+#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
+#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_P_CLK_FREQ
+
+#define CONFIG_SYS_TMU_CLK_DIV 4
+
+/* i2c */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
+#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000
+#define CONFIG_SYS_I2C_SH_SPEED0 400000
+#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000
+#define CONFIG_SYS_I2C_SH_SPEED1 400000
+#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
+#define CONFIG_SYS_I2C_SH_SPEED2 400000
+#define CONFIG_SH_I2C_DATA_HIGH 4
+#define CONFIG_SH_I2C_DATA_LOW 5
+#define CONFIG_SH_I2C_CLOCK 10000000
+
+#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
+
+#endif /* __ALT_H */
"bootenv=uEnv.txt\0" \
"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
- "env import -t $loadaddr $filesize\0" \
+ "env import -t -r $loadaddr $filesize\0" \
"ramargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=${ramroot} " \
#elif CONFIG_SYS_USE_MMC
/* bootstrap + u-boot + env + linux in mmc */
#define FAT_ENV_INTERFACE "mmc"
-#define FAT_ENV_DEVICE 0
-#define FAT_ENV_PART 1
+/*
+ * We don't specify the part number, if device 0 has partition table, it means
+ * the first partition; it no partition table, then take whole device as a
+ * FAT file system.
+ */
+#define FAT_ENV_DEVICE_AND_PART "0"
#define FAT_ENV_FILE "uboot.env"
#define CONFIG_ENV_IS_IN_FAT
#define CONFIG_FAT_WRITE
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-/* Probing DP501 I2C-Bridge will hang */
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x30}, {0, 0x37}, {0, 0x3a}, \
- {0, 0x3b}, {0, 0x50} }
+
+#ifndef CONFIG_TRAILBLAZER
+#define CONFIG_CMD_I2C
+#endif
#define CONFIG_PCA9698 /* NXP PCA9698 */
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME dlvsion-10g
-#define CONFIG_IDENT_STRING " dlvision-10g 0.05"
+#define CONFIG_IDENT_STRING " dlvision-10g 0.06"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DTT
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DIAG
#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_NFS
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
/*
* I2C stuff
*/
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
+
+#define CONFIG_SYS_I2C_IHS
+#define CONFIG_SYS_I2C_IHS_CH0
+#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_IHS_CH1
+#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
+
+#define CONFIG_SYS_SPD_BUS_NUM 2
/* Temp sensor/hwmon/dtt */
+#define CONFIG_SYS_DTT_BUS_NUM 2
#define CONFIG_DTT_LM63 1 /* National LM63 */
#define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
#define CONFIG_DTT_PWM_LOOKUPTABLE \
{ 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
#define CONFIG_DTT_TACH_LIMIT 0xa10
+#define CONFIG_SYS_ICS8N3QV01_I2C {0, 1}
+#define CONFIG_SYS_SIL1178_I2C {0, 1}
+
/* EBC peripherals */
#define CONFIG_SYS_FLASH_BASE 0xFC000000
/*
* OSD Setup
*/
-#define CONFIG_SYS_ICS8N3QV01
#define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_SIL1178
#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
#endif /* __CONFIG_H */
* I2C related stuff
*/
#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MVTWSI
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE
#define CONFIG_SYS_I2C_SLAVE 0x0
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_IMI
#define CONFIG_FIT
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DTT
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DIAG
#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_NFS
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME iocon
-#define CONFIG_IDENT_STRING " iocon 0.05"
+#define CONFIG_IDENT_STRING " iocon 0.06"
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_FPGAD
#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_NFS
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_IHS
#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_SPD_BUS_NUM 4
#define CONFIG_PCA953X /* NXP PCA9554 */
#define CONFIG_PCA9698 /* NXP PCA9698 */
+#define CONFIG_SYS_I2C_IHS_CH0
+#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_IHS_CH1
+#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
+#define CONFIG_SYS_I2C_IHS_CH2
+#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
+#define CONFIG_SYS_I2C_IHS_CH3
+#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
+
/*
* Software (bit-bang) I2C driver configuration
*/
#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
-#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
+#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
+#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
+#define CONFIG_SYS_DP501_I2C {0, 1, 2, 3}
#ifndef __ASSEMBLY__
void fpga_gpio_set(unsigned int bus, int pin);
} while (0)
#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
-/*
- * OSD hardware
- */
-#define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_CH7301
-
/*
* FLASH organization
*/
* OSD Setup
*/
#define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_CH7301
#define CONFIG_SYS_OSD_SCREENS 1
+#define CONFIG_SYS_DP501_DIFFERENTIAL
+#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024)
#define VIDEO_FB_16BPP_WORD_SWAP
#define VIDEO_KBD_INIT_FCT 0
-#define VIDEO_TSTC_FCT serial_tstc
-#define VIDEO_GETC_FCT serial_getc
+#define VIDEO_TSTC_FCT serial_stub_tstc
+#define VIDEO_GETC_FCT serial_stub_getc
/*
* BOOTP options
#define MACH_TYPE_M28EVK 3613
#define CONFIG_MACH_TYPE MACH_TYPE_M28EVK
+#define CONFIG_FIT
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BMP
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_GREPENV
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_RANGE (512 * 1024)
-#define CONFIG_ENV_OFFSET 0x300000
+#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_OFFSET (24 * CONFIG_ENV_SECT_SIZE) /* 3 MiB */
#define CONFIG_ENV_OFFSET_REDUND \
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
#define MTDIDS_DEFAULT "nand0=gpmi-nand"
#define MTDPARTS_DEFAULT \
"mtdparts=gpmi-nand:" \
- "3m(bootloader)ro," \
- "512k(environment)," \
- "512k(redundant-environment)," \
- "4m(kernel)," \
- "128k(fdt)," \
- "8m(ramdisk)," \
- "-(filesystem)"
+ "3m(u-boot)," \
+ "512k(env1)," \
+ "512k(env2)," \
+ "14m(boot)," \
+ "238m(data)," \
+ "-@4096k(UBI)"
#else
#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_BMP_GZIP
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
#endif
/* Booting Linux */
#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTFILE "fitImage"
#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 "
-#define CONFIG_BOOTCOMMAND "run bootcmd_net"
+#define CONFIG_BOOTCOMMAND "run mmc_mmc"
#define CONFIG_LOADADDR 0x42000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Extra Environment */
+#define CONFIG_PREBOOT "run try_bootscript"
+#define CONFIG_HOSTNAME m28evk
+
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "consdev=ttyAMA0\0" \
+ "baudrate=115200\0" \
+ "bootdev=/dev/mmcblk0p2\0" \
+ "rootdev=/dev/mmcblk0p3\0" \
+ "netdev=eth0\0" \
+ "hostname=m28evk\0" \
+ "rootpath=/opt/eldk-5.5/armv5te/rootfs-qte-sdk\0" \
+ "kernel_addr_r=0x42000000\0" \
+ "videomode=video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066," \
+ "le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296," \
+ "vmode:0\0" \
"update_nand_full_filename=u-boot.nand\0" \
"update_nand_firmware_filename=u-boot.sb\0" \
"update_sd_firmware_filename=u-boot.sd\0" \
"if tftp ${update_nand_full_filename} ; then " \
"run update_nand_get_fcb_size ; " \
"nand scrub -y 0x0 ${filesize} ; " \
- "nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \
+ "nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \
"setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
"setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
"nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
"setexpr fw_sz ${fw_sz} + 1 ; " \
"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
"fi ; " \
+ "fi\0" \
+ "addcons=" \
+ "setenv bootargs ${bootargs} " \
+ "console=${consdev},${baudrate}\0" \
+ "addip=" \
+ "setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off\0" \
+ "addmisc=" \
+ "setenv bootargs ${bootargs} ${miscargs}\0" \
+ "adddfltmtd=" \
+ "if test \"x${mtdparts}\" == \"x\" ; then " \
+ "mtdparts default ; " \
+ "fi\0" \
+ "addmtd=" \
+ "run adddfltmtd ; " \
+ "setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addargs=run addcons addmtd addmisc\0" \
+ "mmcload=" \
+ "mmc rescan ; " \
+ "ext4load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \
+ "ubiload=" \
+ "ubi part UBI ; ubifsmount ubi0:rootfs ; " \
+ "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \
+ "netload=" \
+ "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
+ "miscargs=nohlt panic=1\0" \
+ "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
+ "ubiargs=" \
+ "setenv bootargs ubi.mtd=5 " \
+ "root=ubi0:rootfs rootfstype=ubifs\0" \
+ "nfsargs=" \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
+ "mmc_mmc=" \
+ "run mmcload mmcargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "mmc_ubi=" \
+ "run mmcload ubiargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "mmc_nfs=" \
+ "run mmcload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "ubi_mmc=" \
+ "run ubiload mmcargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "ubi_ubi=" \
+ "run ubiload ubiargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "ubi_nfs=" \
+ "run ubiload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_mmc=" \
+ "run netload mmcargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_ubi=" \
+ "run netload ubiargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_nfs=" \
+ "run netload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "try_bootscript=" \
+ "mmc rescan;" \
+ "if ext4load mmc 0:2 ${kernel_addr_r} ${bootscript};" \
+ "then;" \
+ "\techo Running bootscript...;" \
+ "\tsource ${kernel_addr_r};" \
"fi\0"
/* The rest of the configuration is shared */
#define CONFIG_REVISION_TAG
#define CONFIG_SYS_NO_FLASH
+#define CONFIG_FIT
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
/*
* U-Boot Commands
*/
#include <config_cmd_default.h>
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BMP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_SATA
+#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_USB
#define CONFIG_VIDEO
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_RANGE (512 * 1024)
-#define CONFIG_ENV_OFFSET 0x100000
+#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_OFFSET (8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */
#define CONFIG_ENV_OFFSET_REDUND \
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
#define MTDIDS_DEFAULT "nand0=mxc_nand"
#define MTDPARTS_DEFAULT \
"mtdparts=mxc_nand:" \
- "1m(bootloader)ro," \
- "512k(environment)," \
- "512k(redundant-environment)," \
- "4m(kernel)," \
- "128k(fdt)," \
- "8m(ramdisk)," \
- "-(filesystem)"
+ "1024k(u-boot)," \
+ "512k(env1)," \
+ "512k(env2)," \
+ "14m(boot)," \
+ "240m(data)," \
+ "-@2048k(UBI)"
#else
#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
+#define CONFIG_ETHPRIME "FEC0"
#endif
/*
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASHIMAGE_GUARD
+#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK 200000000
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
+#define CONFIG_IPUV3_CLK 200000000
#endif
/*
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTFILE "m53evk/uImage"
+#define CONFIG_BOOTFILE "fitImage"
#define CONFIG_BOOTARGS "console=ttymxc1,115200"
#define CONFIG_LOADADDR 0x70800000
+#define CONFIG_BOOTCOMMAND "run mmc_mmc"
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_OF_LIBFDT
#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+/*
+ * Extra Environments
+ */
+#define CONFIG_PREBOOT "run try_bootscript"
+#define CONFIG_HOSTNAME m53evk
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "consdev=ttymxc1\0" \
+ "baudrate=115200\0" \
+ "bootscript=boot.scr\0" \
+ "bootdev=/dev/mmcblk0p1\0" \
+ "rootdev=/dev/mmcblk0p2\0" \
+ "netdev=eth0\0" \
+ "rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-qte-sdk\0" \
+ "kernel_addr_r=0x72000000\0" \
+ "addcons=" \
+ "setenv bootargs ${bootargs} " \
+ "console=${consdev},${baudrate}\0" \
+ "addip=" \
+ "setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off\0" \
+ "addmisc=" \
+ "setenv bootargs ${bootargs} ${miscargs}\0" \
+ "adddfltmtd=" \
+ "if test \"x${mtdparts}\" == \"x\" ; then " \
+ "mtdparts default ; " \
+ "fi\0" \
+ "addmtd=" \
+ "run adddfltmtd ; " \
+ "setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addargs=run addcons addmtd addmisc\0" \
+ "mmcload=" \
+ "mmc rescan ; " \
+ "ext4load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \
+ "ubiload=" \
+ "ubi part UBI ; ubifsmount ubi0:rootfs ; " \
+ "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \
+ "netload=" \
+ "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
+ "miscargs=nohlt panic=1\0" \
+ "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
+ "ubiargs=" \
+ "setenv bootargs ubi.mtd=5 " \
+ "root=ubi0:rootfs rootfstype=ubifs\0" \
+ "nfsargs=" \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
+ "mmc_mmc=" \
+ "run mmcload mmcargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "mmc_ubi=" \
+ "run mmcload ubiargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "mmc_nfs=" \
+ "run mmcload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "ubi_mmc=" \
+ "run ubiload mmcargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "ubi_ubi=" \
+ "run ubiload ubiargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "ubi_nfs=" \
+ "run ubiload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_mmc=" \
+ "run netload mmcargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_ubi=" \
+ "run netload ubiargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_nfs=" \
+ "run netload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "try_bootscript=" \
+ "mmc rescan;" \
+ "if ext4load mmc 0:1 ${kernel_addr_r} ${bootscript};" \
+ "then;" \
+ "\techo Running bootscript...;" \
+ "\tsource ${kernel_addr_r};" \
+ "fi\0"
+
#endif /* __M53EVK_CONFIG_H__ */
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
#define CONFIG_CMD_DTT
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DIAG
#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_NFS
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
#define VIDEO_TSTC_FCT rx51_kp_tstc
#define VIDEO_GETC_FCT rx51_kp_getc
#ifndef __ASSEMBLY__
+struct stdio_dev;
int rx51_kp_init(void);
-int rx51_kp_tstc(void);
-int rx51_kp_getc(void);
+int rx51_kp_tstc(struct stdio_dev *sdev);
+int rx51_kp_getc(struct stdio_dev *sdev);
#endif
#ifndef MTDPARTS_DEFAULT
#define CONFIG_CMD_LED /* LED support */
#define CONFIG_CMD_SETEXPR /* Evaluate expressions */
#define CONFIG_CMD_GPIO /* Enable gpio command */
+#define CONFIG_CMD_DHCP
#define CONFIG_VIDEO_OMAP3 /* DSS Support */
"bootenv=uEnv.txt\0" \
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
- "env import -t $loadaddr $filesize\0" \
+ "env import -t -r $loadaddr $filesize\0" \
"ramargs=setenv bootargs console=${console} " \
"${optargs} " \
"mpurate=${mpurate} " \
+++ /dev/null
-/*
- * (C) Copyright 2003-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- * changes for 16M board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#undef CONFIG_MPC860
-#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
-#define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */
-#define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-/* default developmenmt environment */
-
-#define CONFIG_ETHADDR 00:0B:17:00:00:00
-
-#define CONFIG_IPADDR 10.10.69.10
-#define CONFIG_SERVERIP 10.10.69.49
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_HOSTNAME QUANTUM
-#define CONFIG_ROOTPATH "/opt/eldk/pcc_8xx"
-
-#define CONFIG_BOOTARGS "root=/dev/ram rw"
-
-#define CONFIG_BOOTCOMMAND "bootm ff000000"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "serial#=12345\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"
-
-/*
- * Select the more full-featured memory test (Barr embedded systems)
- */
-#define CONFIG_SYS_ALT_MEMTEST
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-
-/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/
-#define CONFIG_RTC_M48T35A 1
-
-#if 0
-#define CONFIG_WATCHDOG 1 /* watchdog enabled */
-#else
-#undef CONFIG_WATCHDOG
-#endif
-
-/* NVRAM and RTC */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA000000
-#define CONFIG_SYS_NVRAM_SIZE 2048
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SNTP
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
-#define CONFIG_AUTOBOOT_PROMPT \
- "\nEnter password - autoboot in %d sec...\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR "system"
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFA200000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-
-#if 1
- #define CONFIG_FLASH_CFI_DRIVER
-#else
- #undef CONFIG_FLASH_CFI_DRIVER
-#endif
-
-
-#ifdef CONFIG_FLASH_CFI_DRIVER
- #define CONFIG_SYS_FLASH_CFI 1
- #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
- #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
-#endif
-
-/*%%% #define CONFIG_SYS_FLASH_BASE 0xFFF00000 */
-#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE 0xFFF00000
-/*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector absolute address 0xfff40000*/
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/* FPGA */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_SYS_FPGA_SPARTAN2
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-
-
-/*-----------------------------------------------------------------------
- * Reset address
- */
-#define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-/* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF00
-/* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define CONFIG_SYS_DER 0x2002000F*/
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
-
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
-
-/*
- * BR1 and OR1 (SDRAM)
- *
- */
-#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
-#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
-
-#define CONFIG_SYS_OR1_PRELIM (0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */
-#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/* RPXLITE mem setting */
-#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* FPGA */
-#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910
-
-#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
-#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 20
-
-/*
- * Refresh clock Prescalar
- */
-#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
-
-/*
- * BCSRx
- *
- * Board Status and Control Registers
- *
- */
-
-#define BCSR0 0xFA400000
-#define BCSR1 0xFA400001
-#define BCSR2 0xFA400002
-#define BCSR3 0xFA400003
-
-#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
-#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
-#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
-#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
-#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
-#define BCSR0_COLTEST 0x20
-#define BCSR0_ETHLPBK 0x40
-#define BCSR0_ETHEN 0x80
-
-#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
-#define BCSR1_PCVCTL6 0x02
-#define BCSR1_PCVCTL5 0x04
-#define BCSR1_PCVCTL4 0x08
-#define BCSR1_IPB5SEL 0x10
-
-#define BCSR2_ENPA5HDR 0x08 /* USB Control */
-#define BCSR2_ENUSBCLK 0x10
-#define BCSR2_USBPWREN 0x20
-#define BCSR2_USBSPD 0x40
-#define BCSR2_USBSUSP 0x80
-
-#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
-#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
-#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
-#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
-#define BCSR3_D27 0x10 /* Dip Switch settings */
-#define BCSR3_D26 0x20
-#define BCSR3_D25 0x40
-#define BCSR3_D24 0x80
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_PREBOOT \
"if load mmc 0:1 ${loadaddr} /uEnv.txt; then " \
- "env import -t ${loadaddr} ${filesize}; " \
+ "env import -t -r ${loadaddr} ${filesize}; " \
"fi"
#define ENV_DEVICE_SETTINGS \
#define CONFIG_EFI_PARTITION
/*
- * Size of malloc() pool, although we don't actually use this yet.
+ * Size of malloc() pool, before and after relocation
*/
+#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
+#define CONFIG_MALLOC_F_ADDR 0x0010000
#define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */
#define CONFIG_SYS_HUSH_PARSER
#else
#define CONFIG_SYS_TIMER_RATE 25000000
#endif
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
#define CONFIG_ENV_IS_NOWHERE
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
- *
- * Configuation settings for the SPC1920 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __H
-#define __CONFIG_H
-
-#define CONFIG_SPC1920 1 /* SPC1920 board */
-#define CONFIG_MPC885 1 /* MPC885 CPU */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
-#define CONFIG_MII
-#define CONFIG_MII_INIT 1
-#undef CONFIG_ETHER_ON_FEC1
-#define CONFIG_ETHER_ON_FEC2
-#define FEC_ENET
-#define CONFIG_FEC2_PHY 1
-
-#define CONFIG_BAUDRATE 19200
-
-/* use PLD CLK4 instead of brg */
-#define CONFIG_SYS_SPC1920_SMC1_CLK4
-
-#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
-#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
-#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000
-#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000
-
-#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_LAST_STAGE_INIT
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_NFSBOOTCOMMAND \
- "dhcp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
- "bootm"
-
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
- "bootm fe080000"
-
-#undef CONFIG_BOOTARGS
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
-
-#ifdef CONFIG_BZIP2
-#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
-#else
-#define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
-#endif /* CONFIG_BZIP2 */
-
-#define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */
-
-/*
- * Flash
- */
-/*-----------------------------------------------------------------------
- * Flash organisation
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
-
-/* Environment is in flash */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-
-#define CONFIG_ENV_OVERWRITE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-
-#ifdef CONFIG_CMD_DATE
-# define CONFIG_RTC_DS3231
-# define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C configuration
- */
-#if defined(CONFIG_CMD_I2C)
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
-
-#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
-#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
-#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
- else immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
- else immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_FRC)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-/* #define CONFIG_SYS_SCCR SCCR_TBS */
-#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
- SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * DER - Debug Enable Register
- *-----------------------------------------------------------------------
- * Set to zero to prevent the processor from entering debug mode
- */
-#define CONFIG_SYS_DER 0
-
-
-/* Because of the way the 860 starts up and assigns CS0 the entire
- * address space, we have to set the memory controller differently.
- * Normally, you write the option register first, and then enable the
- * chip select by writing the base register. For CS0, you must write
- * the base register first, followed by the option register.
- */
-
-
-/*
- * Init Memory Controller:
- */
-
-/* BR0 and OR0 (FLASH) */
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/*
- * FLASH timing:
- */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
- OR_SCY_6_CLK | OR_EHTR | OR_BI)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-
-/*
- * SDRAM CS1 UPMB
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE_PRELIM CONFIG_SYS_SDRAM_BASE
-#define SDRAM_MAX_SIZE 0x4000000 /* max 64 MB */
-
-#define CONFIG_SYS_PRELIM_OR1_AM 0xF0000000
-/* #define CONFIG_SYS_OR1_TIMING OR_CSNT_SAM/\* | OR_G5LS /\\* *\\/ *\/ */
-#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
-
-#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
-#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
-
-/* #define CONFIG_SYS_OR1_FINAL ((CONFIG_SYS_OR1_AM & OR_AM_MSK) | CONFIG_SYS_OR1_TIMING) */
-/* #define CONFIG_SYS_BR1_FINAL ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
-
-#define CONFIG_SYS_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64))
-#define CONFIG_SYS_PTA_PER_CLK 195
-#define CONFIG_SYS_MBMR_PTB 195
-#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV16
-#define CONFIG_SYS_MAR 0x88
-
-#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_0 | \
- MBMR_G0CLB_A10 | \
- MBMR_DSB_1_CYCL | \
- MBMR_RLFB_1X | \
- MBMR_WLFB_1X | \
- MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
-
-#define CONFIG_SYS_MBMR_9COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
- MBMR_AMB_TYPE_1 | \
- MBMR_G0CLB_A10 | \
- MBMR_DSB_1_CYCL | \
- MBMR_RLFB_1X | \
- MBMR_WLFB_1X | \
- MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
-
-
-/*
- * DSP Host Port Interface CS3
- */
-#define CONFIG_SYS_SPC1920_HPI_BASE 0x90000000
-#define CONFIG_SYS_PRELIM_OR3_AM 0xF8000000
-
-#define CONFIG_SYS_OR3 (CONFIG_SYS_PRELIM_OR3_AM | \
- OR_G5LS | \
- OR_SCY_0_CLK | \
- OR_BI)
-
-#define CONFIG_SYS_BR3 ((CONFIG_SYS_SPC1920_HPI_BASE & BR_BA_MSK) | \
- BR_MS_UPMA | \
- BR_PS_16 | \
- BR_V)
-
-#define CONFIG_SYS_MAMR (MAMR_GPL_A4DIS | \
- MAMR_RLFA_5X | \
- MAMR_WLFA_5X)
-
-#define CONFIG_SPC1920_HPI_TEST
-
-#ifdef CONFIG_SPC1920_HPI_TEST
-#define HPI_REG(x) (*((volatile u16 *) (CONFIG_SYS_SPC1920_HPI_BASE + x)))
-#define HPI_HPIC_1 HPI_REG(0)
-#define HPI_HPIC_2 HPI_REG(2)
-#define HPI_HPIA_1 HPI_REG(0x2000008)
-#define HPI_HPIA_2 HPI_REG(0x2000008 + 2)
-#define HPI_HPID_INC_1 HPI_REG(0x1000004)
-#define HPI_HPID_INC_2 HPI_REG(0x1000004 + 2)
-#define HPI_HPID_NOINC_1 HPI_REG(0x300000c)
-#define HPI_HPID_NOINC_2 HPI_REG(0x300000c + 2)
-#endif /* CONFIG_SPC1920_HPI_TEST */
-
-/*
- * Ramtron FM18L08 FRAM 32KB on CS4
- */
-#define CONFIG_SYS_SPC1920_FRAM_BASE 0x80100000
-#define CONFIG_SYS_PRELIM_OR4_AM 0xffff8000
-#define CONFIG_SYS_OR4 (CONFIG_SYS_PRELIM_OR4_AM | \
- OR_ACS_DIV2 | \
- OR_BI | \
- OR_SCY_4_CLK | \
- OR_TRLX)
-
-#define CONFIG_SYS_BR4 ((CONFIG_SYS_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-
-/*
- * PLD CS5
- */
-#define CONFIG_SYS_SPC1920_PLD_BASE 0x80000000
-#define CONFIG_SYS_PRELIM_OR5_AM 0xffff8000
-
-#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PRELIM_OR5_AM | \
- OR_CSNT_SAM | \
- OR_ACS_DIV1 | \
- OR_BI | \
- OR_SCY_0_CLK | \
- OR_TRLX)
-
-#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-
-#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * Configuration settings for the Allwinner A10 (sun4i) CPU
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A10 specific configuration
+ */
+#define CONFIG_SUN4I /* sun4i SoC generation */
+#define CONFIG_CLK_FULL_SPEED 1008000000
+
+#define CONFIG_SYS_PROMPT "sun4i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * Configuration settings for the Allwinner A13 (sun5i) CPU
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SUN5I /* sun5i SoC generation */
+#define CONFIG_CLK_FULL_SPEED 1008000000
+
+#define CONFIG_SYS_PROMPT "sun5i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
* A20 specific configuration
*/
#define CONFIG_SUN7I /* sun7i SoC generation */
+#define CONFIG_CLK_FULL_SPEED 912000000
#define CONFIG_SYS_PROMPT "sun7i# "
#define CONFIG_CMD_MMC
#define CONFIG_MMC_SUNXI
#define CONFIG_MMC_SUNXI_SLOT 0
-#define CONFIG_MMC_SUNXI_USE_DMA
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
+/* I2C */
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_SLAVE 0x7f
+#define CONFIG_CMD_I2C
+
+/* PMU */
+#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER
+#define CONFIG_SPL_POWER_SUPPORT
+#endif
+
+#ifndef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX 1 /* UART0 */
+#endif
+
+/* GPIO */
+#define CONFIG_SUNXI_GPIO
+#define CONFIG_CMD_GPIO
+
+/* Ethernet support */
+#ifdef CONFIG_SUNXI_EMAC
+#define CONFIG_MII /* MII PHY management */
+#endif
#ifdef CONFIG_SUNXI_GMAC
#define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */
#define CONFIG_ENV_IS_NOWHERE
#endif
+#define CONFIG_MISC_INIT_R
+
#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>
#endif
#define PARTS_DEFAULT
#endif
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"console=" CONSOLEDEV ",115200n8\0" \
"setenv fdtfile omap5-uevm.dtb; fi; " \
"if test $board_name = dra7xx; then " \
"setenv fdtfile dra7-evm.dtb; fi;" \
+ "if test $board_name = dra72x; then " \
+ "setenv fdtfile dra72-evm.dtb; fi;" \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
-#define CONFIG_V37 1 /* ...on a Marel V37 board */
-
-#define CONFIG_SYS_TEXT_BASE 0x40000000
-
-#define CONFIG_LCD
-#define CONFIG_MPC8XX_LCD
-#define CONFIG_SHARP_LQ084V1DG21
-#undef CONFIG_LCD_LOGO
-
-/*-----------------------------------------------------------------------------
- * I2C Configuration
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_I2C 1
-#define CONFIG_SYS_I2C_SLAVE 0x2
-
-#define CONFIG_8xx_CONS_SMC1 1
-#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 9600 /* console baudrate = 115kbps */
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
-#endif
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_BOOTCOMMAND \
- "tftpboot; " \
- "setenv bootargs console=tty0 " \
- "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_DATE
-
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor1"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor1=v37-1"
-#define MTDPARTS_DEFAULT "mtdparts=v37-1:-(jffs2)"
-*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE0 0x40000000
-#define CONFIG_SYS_FLASH_BASE1 0x60000000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE1
-
-#if defined(DEBUG)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_ENV_IS_IN_NVRAM 1
-#define CONFIG_ENV_ADDR 0x80000000/* Address of Environment */
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-#define CONFIG_ENV_OFFSET 0
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR 0xFFFFFF88
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-/*
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-*/
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-/* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_PLPRCR ( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-/* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#undef CONFIG_IDE_PCCARD /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
-
-#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
-
-#define CONFIG_SYS_OR_TIMING_FLASH 0xF56
-
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V)
-
-#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR5_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V)
-
-/*
- * BR1 and OR1 (Battery backed SRAM)
- */
-#define CONFIG_SYS_BR1_PRELIM 0x80000401
-#define CONFIG_SYS_OR1_PRELIM 0xFFC00736
-
-/*
- * BR2 and OR2 (SDRAM)
- */
-#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB */
-
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/* Marel V37 mem setting */
-
-#define CONFIG_SYS_BR3_CAN 0xC0000401
-#define CONFIG_SYS_OR3_CAN 0xFFFF0724
-
-/*
-#define CONFIG_SYS_BR3_PRELIM 0xFA400001
-#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910
-#define CONFIG_SYS_BR4_PRELIM 0xFA000401
-#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970
-*/
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
-
-/*
- * Refresh clock Prescalar
- */
-#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV16
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 10 column SDRAM */
-#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
- MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_GENERIC_BOARD
+
#endif /* __CONFIG_ZYNQ_COMMON_H */
* tree.
*
* @parent: Pointer to device's parent
+ * @pre_reloc_only: If true, bind the driver only if its DM_INIT_F flag is set.
+ * If false bind the driver always.
* @info: Name and platdata for this device
* @devp: Returns a pointer to the bound device
* @return 0 if OK, -ve on error
*/
-int device_bind_by_name(struct udevice *parent, const struct driver_info *info,
- struct udevice **devp);
+int device_bind_by_name(struct udevice *parent, bool pre_reloc_only,
+ const struct driver_info *info, struct udevice **devp);
/**
* device_probe() - Probe a device, activating it
/* DM is responsible for allocating and freeing platdata */
#define DM_FLAG_ALLOC_PDATA (1 << 1)
+/* DM should init this device prior to relocation */
+#define DM_FLAG_PRE_RELOC (1 << 2)
+
/**
* struct udevice - An instance of a driver
*
* @priv: Private data for this device
* @uclass: Pointer to uclass for this device
* @uclass_priv: The uclass's private data for this device
+ * @parent_priv: The parent's private data for this device
* @uclass_node: Used by uclass to link its devices
* @child_head: List of children of this device
* @sibling_node: Next device in list of all devices
* @flags: Flags for this device DM_FLAG_...
+ * @req_seq: Requested sequence number for this device (-1 = any)
+ * @seq: Allocated sequence number for this device (-1 = none)
*/
struct udevice {
struct driver *driver;
void *priv;
struct uclass *uclass;
void *uclass_priv;
+ void *parent_priv;
struct list_head uclass_node;
struct list_head child_head;
struct list_head sibling_node;
uint32_t flags;
+ int req_seq;
+ int seq;
};
+/* Maximum sequence number supported */
+#define DM_MAX_SEQ 999
+
/* Returns the operations for a device */
#define device_get_ops(dev) (dev->driver->ops)
* @remove: Called to remove a device, i.e. de-activate it
* @unbind: Called to unbind a device from its driver
* @ofdata_to_platdata: Called before probe to decode device tree data
+ * @child_pre_probe: Called before a child device is probed. The device has
+ * memory allocated but it has not yet been probed.
+ * @child_post_remove: Called after a child device is removed. The device
+ * has memory allocated but its device_remove() method has been called.
* @priv_auto_alloc_size: If non-zero this is the size of the private data
* to be allocated in the device's ->priv pointer. If zero, then the driver
* is responsible for allocating any data required.
* This is typically only useful for device-tree-aware drivers (those with
* an of_match), since drivers which use platdata will have the data
* provided in the U_BOOT_DEVICE() instantiation.
- * ops: Driver-specific operations. This is typically a list of function
+ * @per_child_auto_alloc_size: Each device can hold private data owned by
+ * its parent. If required this will be automatically allocated if this
+ * value is non-zero.
+ * @ops: Driver-specific operations. This is typically a list of function
* pointers defined by the driver, to implement driver functions required by
* the uclass.
+ * @flags: driver flags - see DM_FLAGS_...
*/
struct driver {
char *name;
int (*remove)(struct udevice *dev);
int (*unbind)(struct udevice *dev);
int (*ofdata_to_platdata)(struct udevice *dev);
+ int (*child_pre_probe)(struct udevice *dev);
+ int (*child_post_remove)(struct udevice *dev);
int priv_auto_alloc_size;
int platdata_auto_alloc_size;
+ int per_child_auto_alloc_size;
const void *ops; /* driver-specific operations */
+ uint32_t flags;
};
/* Declare a new U-Boot driver */
*/
void *dev_get_platdata(struct udevice *dev);
+/**
+ * dev_get_parentdata() - Get the parent data for a device
+ *
+ * The parent data is data stored in the device but owned by the parent.
+ * For example, a USB device may have parent data which contains information
+ * about how to talk to the device over USB.
+ *
+ * This checks that dev is not NULL, but no other checks for now
+ *
+ * @dev Device to check
+ * @return parent data, or NULL if none
+ */
+void *dev_get_parentdata(struct udevice *dev);
+
/**
* dev_get_priv() - Get the private data for a device
*
*/
void *dev_get_priv(struct udevice *dev);
+/**
+ * device_get_child() - Get the child of a device by index
+ *
+ * Returns the numbered child, 0 being the first. This does not use
+ * sequence numbers, only the natural order.
+ *
+ * @dev: Parent device to check
+ * @index: Child index
+ * @devp: Returns pointer to device
+ */
+int device_get_child(struct udevice *parent, int index, struct udevice **devp);
+
+/**
+ * device_find_child_by_seq() - Find a child device based on a sequence
+ *
+ * This searches for a device with the given seq or req_seq.
+ *
+ * For seq, if an active device has this sequence it will be returned.
+ * If there is no such device then this will return -ENODEV.
+ *
+ * For req_seq, if a device (whether activated or not) has this req_seq
+ * value, that device will be returned. This is a strong indication that
+ * the device will receive that sequence when activated.
+ *
+ * @parent: Parent device
+ * @seq_or_req_seq: Sequence number to find (0=first)
+ * @find_req_seq: true to find req_seq, false to find seq
+ * @devp: Returns pointer to device (there is only one per for each seq).
+ * Set to NULL if none is found
+ * @return 0 if OK, -ve on error
+ */
+int device_find_child_by_seq(struct udevice *parent, int seq_or_req_seq,
+ bool find_req_seq, struct udevice **devp);
+
+/**
+ * device_get_child_by_seq() - Get a child device based on a sequence
+ *
+ * If an active device has this sequence it will be returned. If there is no
+ * such device then this will check for a device that is requesting this
+ * sequence.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @parent: Parent device
+ * @seq: Sequence number to find (0=first)
+ * @devp: Returns pointer to device (there is only one per for each seq)
+ * Set to NULL if none is found
+ * @return 0 if OK, -ve on error
+ */
+int device_get_child_by_seq(struct udevice *parent, int seq,
+ struct udevice **devp);
+
+/**
+ * device_find_child_by_of_offset() - Find a child device based on FDT offset
+ *
+ * Locates a child device by its device tree offset.
+ *
+ * @parent: Parent device
+ * @of_offset: Device tree offset to find
+ * @devp: Returns pointer to device if found, otherwise this is set to NULL
+ * @return 0 if OK, -ve on error
+ */
+int device_find_child_by_of_offset(struct udevice *parent, int of_offset,
+ struct udevice **devp);
+
+/**
+ * device_get_child_by_of_offset() - Get a child device based on FDT offset
+ *
+ * Locates a child device by its device tree offset.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @parent: Parent device
+ * @of_offset: Device tree offset to find
+ * @devp: Returns pointer to device if found, otherwise this is set to NULL
+ * @return 0 if OK, -ve on error
+ */
+int device_get_child_by_of_offset(struct udevice *parent, int seq,
+ struct udevice **devp);
+
#endif
* @early_only: If true, bind only drivers with the DM_INIT_F flag. If false
* bind all drivers.
*/
-int lists_bind_drivers(struct udevice *parent);
+int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only);
/**
* lists_bind_fdt() - bind a device tree node
#ifndef _DM_PLATDATA_H
#define _DM_PLATDATA_H
+/**
+ * struct driver_info - Information required to instantiate a device
+ *
+ * @name: Device name
+ * @platdata: Driver-specific platform data
+ */
struct driver_info {
- const char *name;
- const void *platdata;
+ const char *name;
+ const void *platdata;
};
#define U_BOOT_DEVICE(__name) \
*
* This scans all available platdata and creates drivers for each
*
+ * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
+ * flag. If false bind all drivers.
* @return 0 if OK, -ve on error
*/
-int dm_scan_platdata(void);
+int dm_scan_platdata(bool pre_reloc_only);
/**
* dm_scan_fdt() - Scan the device tree and bind drivers
*
- * This scans the device tree and creates a driver for each node
+ * This scans the device tree and creates a driver for each node. Only
+ * the top-level subnodes are examined.
*
* @blob: Pointer to device tree blob
+ * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
+ * flag. If false bind all drivers.
* @return 0 if OK, -ve on error
*/
-int dm_scan_fdt(const void *blob);
+int dm_scan_fdt(const void *blob, bool pre_reloc_only);
+
+/**
+ * dm_scan_fdt_node() - Scan the device tree and bind drivers for a node
+ *
+ * This scans the subnodes of a device tree node and and creates a driver
+ * for each one.
+ *
+ * @parent: Parent device for the devices that will be created
+ * @blob: Pointer to device tree blob
+ * @offset: Offset of node to scan
+ * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
+ * flag. If false bind all drivers.
+ * @return 0 if OK, -ve on error
+ */
+int dm_scan_fdt_node(struct udevice *parent, const void *blob, int offset,
+ bool pre_reloc_only);
+
+/**
+ * dm_scan_other() - Scan for other devices
+ *
+ * Some devices may not be visible to Driver Model. This weak function can
+ * be provided by boards which wish to create their own devices
+ * programmaticaly. They should do this by calling device_bind() on each
+ * device.
+ *
+ * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
+ * flag. If false bind all drivers.
+ */
+int dm_scan_other(bool pre_reloc_only);
+
+/**
+ * dm_init_and_scan() - Initialise Driver Model structures and scan for devices
+ *
+ * This function initialises the roots of the driver tree and uclass trees,
+ * then scans and binds available devices from platform data and the FDT.
+ * This calls dm_init() to set up Driver Model structures.
+ *
+ * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
+ * flag. If false bind all drivers.
+ * @return 0 if OK, -ve on error
+ */
+int dm_init_and_scan(bool pre_reloc_only);
/**
* dm_init() - Initialise Driver Model structures
*/
int dm_init(void);
+/**
+ * dm_uninit - Uninitialise Driver Model structures
+ *
+ * All devices will be removed and unbound
+ * @return 0 if OK, -ve on error
+ */
+int dm_uninit(void);
+
#endif
int total_add;
};
+/**
+ * struct dm_test_parent_data - parent's information on each child
+ *
+ * @sum: Test value used to check parent data works correctly
+ * @flag: Used to track calling of parent operations
+ */
+struct dm_test_parent_data {
+ int sum;
+ int flag;
+};
+
/*
* Operation counts for the test driver, used to check that each method is
* called correctly
* @fail_count: Number of tests that failed
* @force_fail_alloc: Force all memory allocs to fail
* @skip_post_probe: Skip uclass post-probe processing
+ * @removed: Used to keep track of a device that was removed
*/
struct dm_test_state {
struct udevice *root;
int fail_count;
int force_fail_alloc;
int skip_post_probe;
+ struct udevice *removed;
};
/* Test flags for each test */
int dm_check_operations(struct dm_test_state *dms, struct udevice *dev,
uint32_t base, struct dm_test_priv *priv);
+/**
+ * dm_check_devices() - check the devices respond to operations correctly
+ *
+ * @dms: Overall test state
+ * @num_devices: Number of test devices to check
+ * @return 0 if OK, -ve on error
+ */
+int dm_check_devices(struct dm_test_state *dms, int num_devices);
+
/**
* dm_test_main() - Run all the tests
*
UCLASS_DEMO,
UCLASS_TEST,
UCLASS_TEST_FDT,
+ UCLASS_TEST_BUS,
/* U-Boot uclasses start here */
- UCLASS_GPIO,
+ UCLASS_GPIO, /* Bank of general-purpose I/O pins */
UCLASS_COUNT,
UCLASS_INVALID = -1,
*/
int uclass_destroy(struct uclass *uc);
+/**
+ * uclass_find_device_by_seq() - Find uclass device based on ID and sequence
+ *
+ * This searches for a device with the given seq or req_seq.
+ *
+ * For seq, if an active device has this sequence it will be returned.
+ * If there is no such device then this will return -ENODEV.
+ *
+ * For req_seq, if a device (whether activated or not) has this req_seq
+ * value, that device will be returned. This is a strong indication that
+ * the device will receive that sequence when activated.
+ *
+ * The device is NOT probed, it is merely returned.
+ *
+ * @id: ID to look up
+ * @seq_or_req_seq: Sequence number to find (0=first)
+ * @find_req_seq: true to find req_seq, false to find seq
+ * @devp: Returns pointer to device (there is only one per for each seq)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq,
+ bool find_req_seq, struct udevice **devp);
+
#endif
*
* The device is probed to activate it ready for use.
*
- * id: ID to look up
+ * @id: ID to look up
* @index: Device number within that uclass (0=first)
* @devp: Returns pointer to device (there is only one per for each ID)
* @return 0 if OK, -ve on error
*/
int uclass_get_device(enum uclass_id id, int index, struct udevice **devp);
+/**
+ * uclass_get_device_by_seq() - Get a uclass device based on an ID and sequence
+ *
+ * If an active device has this sequence it will be returned. If there is no
+ * such device then this will check for a device that is requesting this
+ * sequence.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: ID to look up
+ * @seq: Sequence number to find (0=first)
+ * @devp: Returns pointer to device (there is only one for each seq)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get_device_by_seq(enum uclass_id id, int seq, struct udevice **devp);
+
+/**
+ * uclass_get_device_by_of_offset() - Get a uclass device by device tree node
+ *
+ * This searches the devices in the uclass for one attached to the given
+ * device tree node.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: ID to look up
+ * @node: Device tree offset to search for (if -ve then -ENODEV is returned)
+ * @devp: Returns pointer to device (there is only one for each node)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get_device_by_of_offset(enum uclass_id id, int node,
+ struct udevice **devp);
+
/**
* uclass_first_device() - Get the first device in a uclass
*
*/
int uclass_next_device(struct udevice **devp);
+/**
+ * uclass_resolve_seq() - Resolve a device's sequence number
+ *
+ * On entry dev->seq is -1, and dev->req_seq may be -1 (to allocate a
+ * sequence number automatically, or >= 0 to select a particular number.
+ * If the requested sequence number is in use, then this device will
+ * be allocated another one.
+ *
+ * Note that the device's seq value is not changed by this function.
+ *
+ * @dev: Device for which to allocate sequence number
+ * @return sequence number allocated, or -ve on error
+ */
+int uclass_resolve_seq(struct udevice *dev);
+
/**
* uclass_foreach_dev() - Helper function to iteration through devices
*
*/
#ifdef CONFIG_SPL_BUILD
#define U_BOOT_ENV_CALLBACK(name, callback) \
- static inline void _u_boot_env_noop_##name(void) \
+ static inline __maybe_unused void _u_boot_env_noop_##name(void) \
{ \
(void)callback; \
}
int fdtdec_add_aliases_for_id(const void *blob, const char *name,
enum fdt_compat_id id, int *node_list, int maxcount);
+/**
+ * Get the alias sequence number of a node
+ *
+ * This works out whether a node is pointed to by an alias, and if so, the
+ * sequence number of that alias. Aliases are of the form <base><num> where
+ * <num> is the sequence number. For example spi2 would be sequence number
+ * 2.
+ *
+ * @param blob Device tree blob (if NULL, then error is returned)
+ * @param base Base name for alias (before the underscore)
+ * @param node Node to look up
+ * @param seqp This is set to the sequence number if one is found,
+ * but otherwise the value is left alone
+ * @return 0 if a sequence was found, -ve if not
+ */
+int fdtdec_get_alias_seq(const void *blob, const char *base, int node,
+ int *seqp);
+
+/**
+ * Get the offset of the given alias node
+ *
+ * This looks up an alias in /aliases then finds the offset of that node.
+ *
+ * @param blob Device tree blob (if NULL, then error is returned)
+ * @param name Alias name, e.g. "console"
+ * @return Node offset referred to by that alias, or -ve FDT_ERR_...
+ */
+int fdtdec_get_alias_node(const void *blob, const char *name);
+
/*
* Get the name for a compatible ID
*
};
struct ihs_i2c {
- u16 write_mailbox;
+ u16 interrupt_status;
+ u16 interrupt_enable;
u16 write_mailbox_ext;
- u16 read_mailbox;
+ u16 write_mailbox;
u16 read_mailbox_ext;
+ u16 read_mailbox;
};
struct ihs_osd {
#endif
#ifdef CONFIG_IO64
-
struct ihs_fpga_channel {
u16 status_int;
u16 config_int;
u16 reserved_0[6]; /* 0x0008 */
struct ihs_gpio gpio; /* 0x0014 */
u16 mpc3w_control; /* 0x001a */
- u16 reserved_1[19]; /* 0x001c */
- u16 videocontrol; /* 0x0042 */
- u16 reserved_2[14]; /* 0x0044 */
+ u16 reserved_1[18]; /* 0x001c */
+ struct ihs_i2c i2c; /* 0x0040 */
+ u16 reserved_2[10]; /* 0x004c */
u16 mc_int; /* 0x0060 */
u16 mc_int_en; /* 0x0062 */
u16 mc_status; /* 0x0064 */
u16 fpga_features; /* 0x0006 */
u16 reserved_0[10]; /* 0x0008 */
u16 extended_interrupt; /* 0x001c */
- u16 reserved_1[9]; /* 0x001e */
- struct ihs_i2c i2c; /* 0x0030 */
- u16 reserved_2[16]; /* 0x0038 */
+ u16 reserved_1[29]; /* 0x001e */
u16 mpc3w_control; /* 0x0058 */
- u16 reserved_3[34]; /* 0x005a */
- u16 videocontrol; /* 0x009e */
- u16 reserved_4[176]; /* 0x00a0 */
+ u16 reserved_2[3]; /* 0x005a */
+ struct ihs_i2c i2c; /* 0x0060 */
+ u16 reserved_3[205]; /* 0x0066 */
struct ihs_osd osd; /* 0x0200 */
- u16 reserved_5[761]; /* 0x020e */
+ u16 reserved_4[761]; /* 0x020e */
u16 videomem[31736]; /* 0x0800 */
};
#endif
*/
int i8042_disable(void);
+struct stdio_dev;
+
int i8042_kbd_init(void);
-int i8042_tstc(void);
-int i8042_getc(void);
+int i8042_tstc(struct stdio_dev *dev);
+int i8042_getc(struct stdio_dev *dev);
#endif /* _I8042_H_ */
/*
* I/O function overrides
*/
+unsigned char ide_inb(int dev, int port);
+void ide_outb(int dev, int port, unsigned char val);
void ide_input_swap_data(int dev, ulong *sect_buf, int words);
void ide_input_data(int dev, ulong *sect_buf, int words);
void ide_output_data(int dev, const ulong *sect_buf, int words);
void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts);
void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts);
+void ide_led(uchar led, uchar status);
+
/**
* board_start_ide() - Start up the board IDE interfac
*
# define IMAGE_ENABLE_SHA256 1
# endif
+#ifdef CONFIG_FIT_DISABLE_SHA256
+#undef CONFIG_SHA256
+#undef IMAGE_ENABLE_SHA256
+#endif
+
#ifndef IMAGE_ENABLE_CRC32
#define IMAGE_ENABLE_CRC32 0
#endif
/* Video functions */
-#if defined(CONFIG_RBC823)
-void lcd_disable(void);
-#endif
-
void lcd_putc(const char c);
void lcd_puts(const char *s);
void lcd_printf(const char *fmt, ...);
, __FILE__, __LINE__); }
#define PAGE_SIZE 4096
+
+/**
+ * upper_32_bits - return MSB bits 32-63 of a number if little endian, or
+ * return MSB bits 0-31 of a number if big endian.
+ * @n: the number we're accessing
+ *
+ * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
+ * the "right shift count >= width of type" warning when that quantity is
+ * 32-bits.
+ */
+#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * lower_32_bits - return LSB bits 0-31 of a number if little endian, or
+ * return LSB bits 32-63 of a number if big endian.
+ * @n: the number we're accessing
+ */
+#define lower_32_bits(n) ((u32)(n))
+
#endif
int mmc_set_dev(int dev_num);
void print_mmc_devices(char separator);
int get_mmc_num(void);
-int board_mmc_getcd(struct mmc *mmc);
int mmc_switch_part(int dev_num, unsigned int part_num);
int mmc_getcd(struct mmc *mmc);
+int board_mmc_getcd(struct mmc *mmc);
int mmc_getwp(struct mmc *mmc);
+int board_mmc_getwp(struct mmc *mmc);
int mmc_set_dsr(struct mmc *mmc, u16 val);
/* Function to change the size of boot partition and rpmb partitions */
int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
#endif
int board_mmc_init(bd_t *bis);
+int cpu_mmc_init(bd_t *bis);
/* Set block count limit because of 16 bit register limit on some hardware*/
#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
int skge_initialize(bd_t *bis);
int smc91111_initialize(u8 dev_num, int base_addr);
int smc911x_initialize(u8 dev_num, int base_addr);
+int sunxi_emac_initialize(bd_t *bis);
int sunxi_gmac_initialize(bd_t *bis);
-int sunxi_wemac_initialize(bd_t *bis);
int tsi108_eth_initialize(bd_t *bis);
int uec_standard_init(bd_t *bis);
int uli526x_initialize(bd_t *bis);
#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
- /* The RPX series use SLOT_B */
-#if defined(CONFIG_RPXLITE)
-# define CONFIG_PCMCIA_SLOT_B
-#elif defined(CONFIG_FADS) /* The FADS series are a mess */
-# if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821)
-# define CONFIG_PCMCIA_SLOT_A
-# else
-# define CONFIG_PCMCIA_SLOT_B
-# endif
-#elif defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)
+#if defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)
# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
#elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */
# define CONFIG_PCMCIA_SLOT_B
# define CONFIG_PCMCIA_SLOT_B
#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
# define CONFIG_PCMCIA_SLOT_A
-#elif defined(CONFIG_NETTA)
-# define CONFIG_PCMCIA_SLOT_A
#elif defined(CONFIG_UC100) /* The UC100 use SLOT_B */
# define CONFIG_PCMCIA_SLOT_B
#else
*/
extern int himport_r(struct hsearch_data *__htab,
const char *__env, size_t __size, const char __sep,
- int __flag, int nvars, char * const vars[]);
+ int __flag, int __crlf_is_lf, int nvars,
+ char * const vars[]);
/* Walk the whole table calling the callback on each element */
extern int hwalk_r(struct hsearch_data *__htab, int (*callback)(ENTRY *));
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-/***** RBC823 ********************************************************/
-#elif defined(CONFIG_RBC823)
-
-# define STATUS_LED_PAR im_ioport.iop_pcpar
-# define STATUS_LED_DIR im_ioport.iop_pcdir
-# undef STATUS_LED_ODR
-# define STATUS_LED_DAT im_ioport.iop_pcdat
-
-# define STATUS_LED_BIT 0x0002 /* LED 0 is on PC.14 */
-# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
-# define STATUS_LED_STATE STATUS_LED_BLINKING
-# define STATUS_LED_BIT1 0x0004 /* LED 1 is on PC.13 */
-# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ)
-# define STATUS_LED_STATE1 STATUS_LED_OFF
-
-# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
-
-# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
-
-/***** NetPhone ********************************************************/
-#elif defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
-/* XXX empty just to avoid the error */
/***** STx XTc ********************************************************/
#elif defined(CONFIG_STXXTC)
/* XXX empty just to avoid the error */
# include <asm/status_led.h>
#endif
+#endif /* CONFIG_STATUS_LED */
+
/*
* Coloured LEDs API
*/
#ifndef __ASSEMBLY__
-extern void coloured_LED_init (void);
-extern void red_led_on(void);
-extern void red_led_off(void);
-extern void green_led_on(void);
-extern void green_led_off(void);
-extern void yellow_led_on(void);
-extern void yellow_led_off(void);
-extern void blue_led_on(void);
-extern void blue_led_off(void);
+void coloured_LED_init(void);
+void red_led_on(void);
+void red_led_off(void);
+void green_led_on(void);
+void green_led_off(void);
+void yellow_led_on(void);
+void yellow_led_off(void);
+void blue_led_on(void);
+void blue_led_off(void);
#else
.extern LED_init
.extern red_led_on
.extern blue_led_off
#endif
-#endif /* CONFIG_STATUS_LED */
-
#endif /* _STATUS_LED_H_ */
/* GENERAL functions */
- int (*start) (void); /* To start the device */
- int (*stop) (void); /* To stop the device */
+ int (*start)(struct stdio_dev *dev); /* To start the device */
+ int (*stop)(struct stdio_dev *dev); /* To stop the device */
/* OUTPUT functions */
- void (*putc) (const char c); /* To put a char */
- void (*puts) (const char *s); /* To put a string (accelerator) */
+ /* To put a char */
+ void (*putc)(struct stdio_dev *dev, const char c);
+ /* To put a string (accelerator) */
+ void (*puts)(struct stdio_dev *dev, const char *s);
/* INPUT functions */
- int (*tstc) (void); /* To test if a char is ready... */
- int (*getc) (void); /* To get that char */
+ /* To test if a char is ready... */
+ int (*tstc)(struct stdio_dev *dev);
+ int (*getc)(struct stdio_dev *dev); /* To get that char */
/* Other functions */
* PROTOTYPES
*/
int stdio_register (struct stdio_dev * dev);
+int stdio_register_dev(struct stdio_dev *dev, struct stdio_dev **devp);
int stdio_init (void);
void stdio_print_current_devices(void);
#ifdef CONFIG_SYS_STDIO_DEREGISTER
int stdio_deregister(const char *devname);
+int stdio_deregister_dev(struct stdio_dev *dev);
#endif
struct list_head* stdio_get_list(void);
struct stdio_dev* stdio_get_by_name(const char* name);
/* Video functions */
-int video_init (void *videobase);
-void video_putc (const char c);
-void video_puts (const char *s);
+struct stdio_dev;
+
+int video_init(void *videobase);
+void video_putc(struct stdio_dev *dev, const char c);
+void video_puts(struct stdio_dev *dev, const char *s);
/**
* Display a BMP format bitmap on the screen
DEFINE(GD_SIZE, sizeof(struct global_data));
DEFINE(GD_BD, offsetof(struct global_data, bd));
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base));
+#endif
#if defined(CONFIG_ARM)
* assembly versions such as arch/powerpc/lib/div64.S and arch/sh/lib/div64.S.
*/
+#include <div64.h>
#include <linux/types.h>
uint32_t __div64_32(uint64_t *n, uint32_t base)
#ifndef USE_HOSTCC
#include <common.h>
+#include <errno.h>
#include <serial.h>
#include <libfdt.h>
#include <fdtdec.h>
+#include <linux/ctype.h>
#include <asm/gpio.h>
return num_found;
}
+int fdtdec_get_alias_seq(const void *blob, const char *base, int offset,
+ int *seqp)
+{
+ int base_len = strlen(base);
+ const char *find_name;
+ int find_namelen;
+ int prop_offset;
+ int aliases;
+
+ find_name = fdt_get_name(blob, offset, &find_namelen);
+ debug("Looking for '%s' at %d, name %s\n", base, offset, find_name);
+
+ aliases = fdt_path_offset(blob, "/aliases");
+ for (prop_offset = fdt_first_property_offset(blob, aliases);
+ prop_offset > 0;
+ prop_offset = fdt_next_property_offset(blob, prop_offset)) {
+ const char *prop;
+ const char *name;
+ const char *slash;
+ const char *p;
+ int len;
+
+ prop = fdt_getprop_by_offset(blob, prop_offset, &name, &len);
+ debug(" - %s, %s\n", name, prop);
+ if (len < find_namelen || *prop != '/' || prop[len - 1] ||
+ strncmp(name, base, base_len))
+ continue;
+
+ slash = strrchr(prop, '/');
+ if (strcmp(slash + 1, find_name))
+ continue;
+ for (p = name; *p; p++) {
+ if (isdigit(*p)) {
+ *seqp = simple_strtoul(p, NULL, 10);
+ debug("Found seq %d\n", *seqp);
+ return 0;
+ }
+ }
+ }
+
+ debug("Not found\n");
+ return -ENOENT;
+}
+
+int fdtdec_get_alias_node(const void *blob, const char *name)
+{
+ const char *prop;
+ int alias_node;
+ int len;
+
+ if (!blob)
+ return -FDT_ERR_NOTFOUND;
+ alias_node = fdt_path_offset(blob, "/aliases");
+ prop = fdt_getprop(blob, alias_node, name, &len);
+ if (!prop)
+ return -FDT_ERR_NOTFOUND;
+ return fdt_path_offset(blob, prop);
+}
+
int fdtdec_check_fdt(void)
{
/*
int himport_r(struct hsearch_data *htab,
const char *env, size_t size, const char sep, int flag,
- int nvars, char * const vars[])
+ int crlf_is_lf, int nvars, char * const vars[])
{
char *data, *sp, *dp, *name, *value;
char *localvars[nvars];
}
}
+ if(!size)
+ return 1; /* everything OK */
+ if(crlf_is_lf) {
+ /* Remove Carriage Returns in front of Line Feeds */
+ unsigned ignored_crs = 0;
+ for(;dp < data + size && *dp; ++dp) {
+ if(*dp == '\r' &&
+ dp < data + size - 1 && *(dp+1) == '\n')
+ ++ignored_crs;
+ else
+ *(dp-ignored_crs) = *dp;
+ }
+ size -= ignored_crs;
+ dp = data;
+ }
/* Parse environment; allow for '\0' and 'sep' as separators */
do {
ENTRY e, *rv;
return 0;
}
-void __board_lmb_reserve(struct lmb *lmb)
+__weak void board_lmb_reserve(struct lmb *lmb)
{
/* please define platform specific board_lmb_reserve() */
}
-void board_lmb_reserve(struct lmb *lmb) __attribute__((weak, alias("__board_lmb_reserve")));
-void __arch_lmb_reserve(struct lmb *lmb)
+__weak void arch_lmb_reserve(struct lmb *lmb)
{
/* please define platform specific arch_lmb_reserve() */
}
-void arch_lmb_reserve(struct lmb *lmb) __attribute__((weak, alias("__arch_lmb_reserve")));
memset (&ctx, 0, sizeof (sha1_context));
}
-static const char _sha1_src[] = "_sha1_src";
-
#ifdef SELF_TEST
/*
* FIPS-180-1 test vectors
#endif
#ifndef CONFIG_WD_PERIOD
-# define CONFIG_WD_PERIOD (10 * 1000 * 1000) /* 10 seconds default*/
+# define CONFIG_WD_PERIOD (10 * 1000 * 1000) /* 10 seconds default */
#endif
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SYS_TIMER_RATE
+/* Returns tick rate in ticks per second */
ulong notrace get_tbclk(void)
{
return CONFIG_SYS_TIMER_RATE;
return ((unsigned long long)gd->timebase_h << 32) | gd->timebase_l;
}
-static unsigned long long notrace tick_to_time(uint64_t tick)
+/* Returns time in milliseconds */
+static unsigned long long notrace tick_to_time(unsigned long long tick)
{
- unsigned int div = get_tbclk();
+ ulong div = get_tbclk();
tick *= CONFIG_SYS_HZ;
do_div(tick, div);
return 0;
}
+/* Returns time in milliseconds */
ulong __weak get_timer(ulong base)
{
return tick_to_time(get_ticks()) - base;
{
return tick_to_time(get_ticks() * 1000);
}
+
static unsigned long long usec_to_tick(unsigned long usec)
{
- uint64_t tick = usec;
+ unsigned long long tick = usec;
tick *= get_tbclk();
do_div(tick, 1000000);
return tick;
void __weak __udelay(unsigned long usec)
{
unsigned long long tmp;
- ulong tmo;
- tmo = usec_to_tick(usec);
- tmp = get_ticks() + tmo; /* get current timestamp */
+ tmp = get_ticks() + usec_to_tick(usec); /* get current timestamp */
- while (get_ticks() < tmp) /* loop till event */
+ while (get_ticks() < tmp+1) /* loop till event */
/*NOP*/;
}
/* some reluctance to put this into a new limits.h, so it is here */
#define INT_MAX ((int)(~0U>>1))
-static const char hex_asc[] = "0123456789abcdef";
-#define hex_asc_lo(x) hex_asc[((x) & 0x0f)]
-#define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4]
-
-static inline char *pack_hex_byte(char *buf, u8 byte)
-{
- *buf++ = hex_asc_hi(byte);
- *buf++ = hex_asc_lo(byte);
- return buf;
-}
-
unsigned long simple_strtoul(const char *cp, char **endp,
unsigned int base)
{
}
#ifdef CONFIG_CMD_NET
+static const char hex_asc[] = "0123456789abcdef";
+#define hex_asc_lo(x) hex_asc[((x) & 0x0f)]
+#define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4]
+
+static inline char *pack_hex_byte(char *buf, u8 byte)
+{
+ *buf++ = hex_asc_hi(byte);
+ *buf++ = hex_asc_lo(byte);
+ return buf;
+}
+
static char *mac_address_string(char *buf, char *end, u8 *addr, int field_width,
int precision, int flags)
{
arch="$2"
cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $1}'`
spl_cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $2}'`
-if [ "$6" = "<none>" ] ; then
- board=
-elif [ "$6" = "-" ] ; then
- board=${BOARD_NAME}
-else
- board="$6"
+
+if [ "$cpu" = "-" ] ; then
+ cpu=
fi
+
+[ "$6" != "-" ] && board="$6"
[ "$5" != "-" ] && vendor="$5"
[ "$4" != "-" ] && soc="$4"
[ $# -gt 7 ] && [ "$8" != "-" ] && {
rm -f asm/arch
-if [ -z "${soc}" ] ; then
- ln -s ${LNPREFIX}arch-${cpu} asm/arch
-else
+if [ "${soc}" ] ; then
ln -s ${LNPREFIX}arch-${soc} asm/arch
+elif [ "${cpu}" ] ; then
+ ln -s ${LNPREFIX}arch-${cpu} asm/arch
fi
if [ -z "$KBUILD_SRC" ] ; then
int extlen, pktlen, iplen;
int eth_hdr_size;
#ifdef CONFIG_BOOTP_RANDOM_DELAY
- ulong i, rand_ms;
+ ulong rand_ms;
#endif
bootstage_mark_name(BOOTSTAGE_ID_BOOTP_START, "bootp_start");
rand_ms = rand() >> 19;
printf("Random delay: %ld ms...\n", rand_ms);
- for (i = 0; i < rand_ms; i++)
- udelay(1000); /*Wait 1ms*/
+ mdelay(rand_ms);
#endif /* CONFIG_BOOTP_RANDOM_DELAY */
#include <net.h>
#include <miiphy.h>
#include <phy.h>
+#include <asm/errno.h>
void eth_parse_enetaddr(const char *addr, uchar *enetaddr)
{
setenv("ethact", NULL);
}
+int eth_address_set(unsigned char *addr)
+{
+ return memcmp(addr, "\0\0\0\0\0\0", 6);
+}
+
int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
int eth_number)
{
eth_getenv_enetaddr_by_index(base_name, eth_number, env_enetaddr);
- if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) {
- if (memcmp(dev->enetaddr, "\0\0\0\0\0\0", 6) &&
+ if (eth_address_set(env_enetaddr)) {
+ if (eth_address_set(dev->enetaddr) &&
memcmp(dev->enetaddr, env_enetaddr, 6)) {
printf("\nWarning: %s MAC addresses don't match:\n",
dev->name);
dev->enetaddr);
printf("\nWarning: %s using MAC address from net device\n",
dev->name);
+ } else if (!(eth_address_set(dev->enetaddr))) {
+ printf("\nError: %s address not set.\n",
+ dev->name);
+ return -EINVAL;
}
- if (dev->write_hwaddr &&
- !eth_mac_skip(eth_number)) {
- if (!is_valid_ether_addr(dev->enetaddr))
- return -1;
+ if (dev->write_hwaddr && !eth_mac_skip(eth_number)) {
+ if (!is_valid_ether_addr(dev->enetaddr)) {
+ printf("\nError: %s address %pM illegal value\n",
+ dev->name, dev->enetaddr);
+ return -EINVAL;
+ }
ret = dev->write_hwaddr(dev);
+ if (ret)
+ printf("\nWarning: %s failed to set MAC address\n", dev->name);
}
return ret;
puts("\nWarning: eth device name has a space!"
"\n");
- if (eth_write_hwaddr(dev, "eth", dev->index))
- puts("\nWarning: failed to set MAC address\n");
+ eth_write_hwaddr(dev, "eth", dev->index);
dev = dev->next;
num_devices++;
immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-#if defined(CONFIG_FADS)
-#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC86xADS)
- /* The FADS860T and MPC86xADS don't use the MODEM_EN or DATA_VOICE signals. */
- *((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
- *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
- *((uint *) BCSR1) &= ~BCSR1_ETHEN;
-#else
- *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
- *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
- *((uint *) BCSR1) &= ~BCSR1_ETHEN;
-#endif
-#endif
-
pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]);
rxIdx = 0;
immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC |
SCC_PSMR_NIB22 | SCC_PSMR_LPB;
-#ifdef CONFIG_RPXLITE
- *((uchar *) BCSR0) |= BCSR0_ETHEN;
-#endif
-
/*
* Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
*/
immr->im_cpm.cp_scc[scc_index].scc_gsmrl |=
(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
-
- /*
- * Work around transmit problem with first eth packet
- */
-#if defined (CONFIG_FADS)
- udelay (10000); /* wait 10 ms */
-#endif
}
static void scc_halt (int scc_index)
im->im_sdma.sdma_sdmr = 0x00;
#endif
-#if defined(CONFIG_FADS)
- /* Enable RS232 */
- *((uint *) BCSR1) &=
- ~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2);
-#endif
-
-#if defined(CONFIG_RPXLITE)
- /* Enable Monitor Port Transceiver */
- *((uchar *) BCSR0) |= BCSR0_ENMONXCVR;
-#endif
-
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
--- /dev/null
+#!/usr/bin/env python
+#
+# Copyright (C) 2014, Masahiro Yamada <yamada.m@jp.panasonic.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+'''
+A tool to create/update the mailmap file
+
+The command 'git shortlog' summarizes git log output in a format suitable
+for inclusion in release announcements. Each commit will be grouped by
+author and title.
+
+One problem is that the authors' name and/or email address is sometimes
+spelled differently. The .mailmap feature can be used to coalesce together
+commits by the same persion.
+(See 'man git-shortlog' for furthur information of this feature.)
+
+This tool helps to create/update the mailmap file.
+
+It runs 'git shortlog' internally and searches differently spelled author
+names which share the same email address. The author name with the most
+commits is asuumed to be a canonical real name. If the number of commits
+from the cananonical name is equal to or greater than 'MIN_COMMITS',
+the entry for the cananical name will be output. ('MIN_COMMITS' is used
+here because we do not want to create a fat mailmap by adding every author
+with only a few commits.)
+
+If there exists a mailmap file specified by the mailmap.file configuration
+options or '.mailmap' at the toplevel of the repository, it is used as
+a base file. (The mailmap.file configuration takes precedence over the
+'.mailmap' file if both exist.)
+
+The base file and the newly added entries are merged together and sorted
+alphabetically (but the comment block is kept untouched), and then printed
+to standard output.
+
+Usage
+-----
+
+ scripts/mailmapper
+
+prints the mailmapping to standard output.
+
+ scripts/mailmapper > tmp; mv tmp .mailmap
+
+will be useful for updating '.mailmap' file.
+'''
+
+import sys
+import os
+import subprocess
+
+# The entries only for the canonical names with MIN_COMMITS or more commits.
+# This limitation is used so as not to create a too big mailmap file.
+MIN_COMMITS = 50
+
+try:
+ toplevel = subprocess.check_output(['git', 'rev-parse', '--show-toplevel'])
+except subprocess.CalledProcessError:
+ print >> sys.stderr, 'Please run in a git repository.'
+ sys.exit(1)
+
+# strip '\n'
+toplevel = toplevel.rstrip()
+
+# Change the current working directory to the toplevel of the respository
+# for our easier life.
+os.chdir(toplevel)
+
+# First, create 'auther name' vs 'number of commits' database.
+# We assume the name with the most commits as the canonical real name.
+shortlog = subprocess.check_output(['git', 'shortlog', '-s', '-n'])
+
+commits_per_name = {}
+
+for line in shortlog.splitlines():
+ try:
+ commits, name = line.split(None, 1)
+ except ValueError:
+ # ignore lines with an empty author name
+ pass
+ commits_per_name[name] = int(commits)
+
+# Next, coalesce the auther names with the same email address
+shortlog = subprocess.check_output(['git', 'shortlog', '-s', '-n', '-e'])
+
+mail_vs_name = {}
+output = {}
+
+for line in shortlog.splitlines():
+ # tmp, mail = line.rsplit(None, 1) is not safe
+ # because weird email addresses might include whitespaces
+ tmp, mail = line.split('<')
+ mail = '<' + mail.rstrip()
+ try:
+ _, name = tmp.rstrip().split(None, 1)
+ except ValueError:
+ # author name is empty
+ name = ''
+ if mail in mail_vs_name:
+ # another name for the same email address
+ prev_name = mail_vs_name[mail]
+ # Take the name with more commits
+ major_name = sorted([prev_name, name],
+ key=lambda x: commits_per_name[x] if x else 0)[1]
+ mail_vs_name[mail] = major_name
+ if commits_per_name[major_name] > MIN_COMMITS:
+ output[mail] = major_name
+ else:
+ mail_vs_name[mail] = name
+
+# [1] If there exists a mailmap file at the location pointed to
+# by the mailmap.file configuration option, update it.
+# [2] If the file .mailmap exists at the toplevel of the repository, update it.
+# [3] Otherwise, create a new mailmap file.
+mailmap_files = []
+
+try:
+ config_mailmap = subprocess.check_output(['git', 'config', 'mailmap.file'])
+except subprocess.CalledProcessError:
+ config_mailmap = ''
+
+config_mailmap = config_mailmap.rstrip()
+if config_mailmap:
+ mailmap_files.append(config_mailmap)
+
+mailmap_files.append('.mailmap')
+
+infile = None
+
+for map_file in mailmap_files:
+ try:
+ infile = open(map_file)
+ except:
+ # Failed to open. Try next.
+ continue
+ break
+
+comment_block = []
+output_lines = []
+
+if infile:
+ for line in infile:
+ if line[0] == '#' or line[0] == '\n':
+ comment_block.append(line)
+ else:
+ output_lines.append(line)
+ break
+ for line in infile:
+ output_lines.append(line)
+ infile.close()
+
+for mail, name in output.items():
+ output_lines.append(name + ' ' + mail + '\n')
+
+output_lines.sort()
+
+sys.stdout.write(''.join(comment_block + output_lines))
#
obj-$(CONFIG_CMD_DM) += cmd_dm.o
+obj-$(CONFIG_DM_TEST) += bus.o
obj-$(CONFIG_DM_TEST) += test-driver.o
obj-$(CONFIG_DM_TEST) += test-fdt.o
obj-$(CONFIG_DM_TEST) += test-main.o
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/root.h>
+#include <dm/test.h>
+#include <dm/ut.h>
+#include <dm/util.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ FLAG_CHILD_PROBED = 10,
+ FLAG_CHILD_REMOVED = -7,
+};
+
+static struct dm_test_state *test_state;
+
+static int testbus_drv_probe(struct udevice *dev)
+{
+ return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+}
+
+static int testbus_child_pre_probe(struct udevice *dev)
+{
+ struct dm_test_parent_data *parent_data = dev_get_parentdata(dev);
+
+ parent_data->flag += FLAG_CHILD_PROBED;
+
+ return 0;
+}
+
+static int testbus_child_post_remove(struct udevice *dev)
+{
+ struct dm_test_parent_data *parent_data = dev_get_parentdata(dev);
+ struct dm_test_state *dms = test_state;
+
+ parent_data->flag += FLAG_CHILD_REMOVED;
+ if (dms)
+ dms->removed = dev;
+
+ return 0;
+}
+
+static const struct udevice_id testbus_ids[] = {
+ {
+ .compatible = "denx,u-boot-test-bus",
+ .data = DM_TEST_TYPE_FIRST },
+ { }
+};
+
+U_BOOT_DRIVER(testbus_drv) = {
+ .name = "testbus_drv",
+ .of_match = testbus_ids,
+ .id = UCLASS_TEST_BUS,
+ .probe = testbus_drv_probe,
+ .priv_auto_alloc_size = sizeof(struct dm_test_priv),
+ .platdata_auto_alloc_size = sizeof(struct dm_test_pdata),
+ .per_child_auto_alloc_size = sizeof(struct dm_test_parent_data),
+ .child_pre_probe = testbus_child_pre_probe,
+ .child_post_remove = testbus_child_post_remove,
+};
+
+UCLASS_DRIVER(testbus) = {
+ .name = "testbus",
+ .id = UCLASS_TEST_BUS,
+};
+
+/* Test that we can probe for children */
+static int dm_test_bus_children(struct dm_test_state *dms)
+{
+ int num_devices = 4;
+ struct udevice *bus;
+ struct uclass *uc;
+
+ ut_assertok(uclass_get(UCLASS_TEST_FDT, &uc));
+ ut_asserteq(num_devices, list_count_items(&uc->dev_head));
+
+ /* Probe the bus, which should yield 3 more devices */
+ ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus));
+ num_devices += 3;
+
+ ut_assertok(uclass_get(UCLASS_TEST_FDT, &uc));
+ ut_asserteq(num_devices, list_count_items(&uc->dev_head));
+
+ ut_assert(!dm_check_devices(dms, num_devices));
+
+ return 0;
+}
+DM_TEST(dm_test_bus_children, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test our functions for accessing children */
+static int dm_test_bus_children_funcs(struct dm_test_state *dms)
+{
+ const void *blob = gd->fdt_blob;
+ struct udevice *bus, *dev;
+ int node;
+
+ ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus));
+
+ /* device_get_child() */
+ ut_assertok(device_get_child(bus, 0, &dev));
+ ut_asserteq(-ENODEV, device_get_child(bus, 4, &dev));
+ ut_assertok(device_get_child_by_seq(bus, 5, &dev));
+ ut_assert(dev->flags & DM_FLAG_ACTIVATED);
+ ut_asserteq_str("c-test@5", dev->name);
+
+ /* Device with sequence number 0 should be accessible */
+ ut_asserteq(-ENODEV, device_find_child_by_seq(bus, -1, true, &dev));
+ ut_assertok(device_find_child_by_seq(bus, 0, true, &dev));
+ ut_assert(!(dev->flags & DM_FLAG_ACTIVATED));
+ ut_asserteq(-ENODEV, device_find_child_by_seq(bus, 0, false, &dev));
+ ut_assertok(device_get_child_by_seq(bus, 0, &dev));
+ ut_assert(dev->flags & DM_FLAG_ACTIVATED);
+
+ /* There is no device with sequence number 2 */
+ ut_asserteq(-ENODEV, device_find_child_by_seq(bus, 2, false, &dev));
+ ut_asserteq(-ENODEV, device_find_child_by_seq(bus, 2, true, &dev));
+ ut_asserteq(-ENODEV, device_get_child_by_seq(bus, 2, &dev));
+
+ /* Looking for something that is not a child */
+ node = fdt_path_offset(blob, "/junk");
+ ut_asserteq(-ENODEV, device_find_child_by_of_offset(bus, node, &dev));
+ node = fdt_path_offset(blob, "/d-test");
+ ut_asserteq(-ENODEV, device_find_child_by_of_offset(bus, node, &dev));
+
+ /* Find a valid child */
+ node = fdt_path_offset(blob, "/some-bus/c-test@1");
+ ut_assertok(device_find_child_by_of_offset(bus, node, &dev));
+ ut_assert(!(dev->flags & DM_FLAG_ACTIVATED));
+ ut_assertok(device_get_child_by_of_offset(bus, node, &dev));
+ ut_assert(dev->flags & DM_FLAG_ACTIVATED);
+
+ return 0;
+}
+DM_TEST(dm_test_bus_children_funcs, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that the bus can store data about each child */
+static int dm_test_bus_parent_data(struct dm_test_state *dms)
+{
+ struct dm_test_parent_data *parent_data;
+ struct udevice *bus, *dev;
+ struct uclass *uc;
+ int value;
+
+ ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus));
+
+ /* Check that parent data is allocated */
+ ut_assertok(device_find_child_by_seq(bus, 0, true, &dev));
+ ut_asserteq_ptr(NULL, dev_get_parentdata(dev));
+ ut_assertok(device_get_child_by_seq(bus, 0, &dev));
+ parent_data = dev_get_parentdata(dev);
+ ut_assert(NULL != parent_data);
+
+ /* Check that it starts at 0 and goes away when device is removed */
+ parent_data->sum += 5;
+ ut_asserteq(5, parent_data->sum);
+ device_remove(dev);
+ ut_asserteq_ptr(NULL, dev_get_parentdata(dev));
+
+ /* Check that we can do this twice */
+ ut_assertok(device_get_child_by_seq(bus, 0, &dev));
+ parent_data = dev_get_parentdata(dev);
+ ut_assert(NULL != parent_data);
+ parent_data->sum += 5;
+ ut_asserteq(5, parent_data->sum);
+
+ /* Add parent data to all children */
+ ut_assertok(uclass_get(UCLASS_TEST_FDT, &uc));
+ value = 5;
+ uclass_foreach_dev(dev, uc) {
+ /* Ignore these if they are not on this bus */
+ if (dev->parent != bus) {
+ ut_asserteq_ptr(NULL, dev_get_parentdata(dev));
+ continue;
+ }
+ ut_assertok(device_probe(dev));
+ parent_data = dev_get_parentdata(dev);
+
+ parent_data->sum = value;
+ value += 5;
+ }
+
+ /* Check it is still there */
+ value = 5;
+ uclass_foreach_dev(dev, uc) {
+ /* Ignore these if they are not on this bus */
+ if (dev->parent != bus)
+ continue;
+ parent_data = dev_get_parentdata(dev);
+
+ ut_asserteq(value, parent_data->sum);
+ value += 5;
+ }
+
+ return 0;
+}
+
+DM_TEST(dm_test_bus_parent_data, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that the bus ops are called when a child is probed/removed */
+static int dm_test_bus_parent_ops(struct dm_test_state *dms)
+{
+ struct dm_test_parent_data *parent_data;
+ struct udevice *bus, *dev;
+ struct uclass *uc;
+
+ test_state = dms;
+ ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus));
+ ut_assertok(uclass_get(UCLASS_TEST_FDT, &uc));
+
+ uclass_foreach_dev(dev, uc) {
+ /* Ignore these if they are not on this bus */
+ if (dev->parent != bus)
+ continue;
+ ut_asserteq_ptr(NULL, dev_get_parentdata(dev));
+
+ ut_assertok(device_probe(dev));
+ parent_data = dev_get_parentdata(dev);
+ ut_asserteq(FLAG_CHILD_PROBED, parent_data->flag);
+ }
+
+ uclass_foreach_dev(dev, uc) {
+ /* Ignore these if they are not on this bus */
+ if (dev->parent != bus)
+ continue;
+ parent_data = dev_get_parentdata(dev);
+ ut_asserteq(FLAG_CHILD_PROBED, parent_data->flag);
+ ut_assertok(device_remove(dev));
+ ut_asserteq_ptr(NULL, dev_get_parentdata(dev));
+ ut_asserteq_ptr(dms->removed, dev);
+ }
+ test_state = NULL;
+
+ return 0;
+}
+DM_TEST(dm_test_bus_parent_ops, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
#include <dm/test.h>
#include <dm/uclass-internal.h>
+/**
+ * dm_display_line() - Display information about a single device
+ *
+ * Displays a single line of information with an option prefix
+ *
+ * @dev: Device to display
+ * @buf: Prefix to display at the start of the line
+ */
+static void dm_display_line(struct udevice *dev, char *buf)
+{
+ printf("%s- %c %s @ %08lx", buf,
+ dev->flags & DM_FLAG_ACTIVATED ? '*' : ' ',
+ dev->name, (ulong)map_to_sysmem(dev));
+ if (dev->req_seq != -1)
+ printf(", %d", dev->req_seq);
+ puts("\n");
+}
+
static int display_succ(struct udevice *in, char *buf)
{
int len;
char local[16];
struct udevice *pos, *n, *prev = NULL;
- printf("%s- %c %s @ %08lx", buf,
- in->flags & DM_FLAG_ACTIVATED ? '*' : ' ',
- in->name, (ulong)map_to_sysmem(in));
- puts("\n");
+ dm_display_line(in, buf);
if (list_empty(&in->child_head))
return 0;
continue;
printf("uclass %d: %s\n", id, uc->uc_drv->name);
- for (ret = uclass_first_device(id, &dev);
- dev;
- ret = uclass_next_device(&dev)) {
- printf(" %c %s @ %08lx:\n",
- dev->flags & DM_FLAG_ACTIVATED ? '*' : ' ',
- dev->name, (ulong)map_to_sysmem(dev));
+ if (list_empty(&uc->dev_head))
+ continue;
+ list_for_each_entry(dev, &uc->dev_head, uclass_node) {
+ dm_display_line(dev, "");
}
puts("\n");
}
U_BOOT_CMD(
dm, 2, 1, do_dm,
"Driver model low level access",
- "tree Dump driver model tree\n"
+ "tree Dump driver model tree ('*' = activated)\n"
"dm uclass Dump list of instances for each uclass"
TEST_HELP
);
TEST_INTVAL2 = 3,
TEST_INTVAL3 = 6,
TEST_INTVAL_MANUAL = 101112,
+ TEST_INTVAL_PRE_RELOC = 7,
};
static const struct dm_test_pdata test_pdata[] = {
.ping_add = TEST_INTVAL_MANUAL,
};
+static const struct dm_test_pdata test_pdata_pre_reloc = {
+ .ping_add = TEST_INTVAL_PRE_RELOC,
+};
+
U_BOOT_DEVICE(dm_test_info1) = {
.name = "test_drv",
.platdata = &test_pdata[0],
.platdata = &test_pdata_manual,
};
+static struct driver_info driver_info_pre_reloc = {
+ .name = "test_pre_reloc_drv",
+ .platdata = &test_pdata_manual,
+};
+
/* Test that binding with platdata occurs correctly */
static int dm_test_autobind(struct dm_test_state *dms)
{
ut_asserteq(0, list_count_items(&gd->dm_root->child_head));
ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_POST_BIND]);
- ut_assertok(dm_scan_platdata());
+ ut_assertok(dm_scan_platdata(false));
/* We should have our test class now at least, plus more children */
ut_assert(1 < list_count_items(&gd->uclass_root));
ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]);
/* The root device should not be activated until needed */
- ut_assert(!(dms->root->flags & DM_FLAG_ACTIVATED));
+ ut_assert(dms->root->flags & DM_FLAG_ACTIVATED);
/*
* We should be able to find the three test devices, and they should
memcpy(op_count, dm_testdrv_op_count, sizeof(op_count));
- ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
+ ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual,
&dev));
ut_assert(dev);
ut_assert(dm_testdrv_op_count[DM_TEST_OP_BIND]
struct udevice *dev, *dev_penultimate, *dev_last, *test_dev;
int pingret;
- ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
+ ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual,
&dev));
ut_assert(dev);
/* Bind two new devices (numbers 4 and 5) */
- ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
+ ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual,
&dev_penultimate));
ut_assert(dev_penultimate);
- ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
+ ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual,
&dev_last));
ut_assert(dev_last);
ut_assert(dev_last == test_dev);
/* Add back the original device 3, now in position 5 */
- ut_assertok(device_bind_by_name(dms->root, &driver_info_manual, &dev));
+ ut_assertok(device_bind_by_name(dms->root, false, &driver_info_manual,
+ &dev));
ut_assert(dev);
/* Try ping */
if (!start.uordblks)
puts("Warning: Please add '#define DEBUG' to the top of common/dlmalloc.c\n");
- ut_assertok(dm_scan_platdata());
- ut_assertok(dm_scan_fdt(gd->fdt_blob));
+ ut_assertok(dm_scan_platdata(false));
+ ut_assertok(dm_scan_fdt(gd->fdt_blob, false));
/* Scanning the uclass is enough to probe all the devices */
for (id = UCLASS_ROOT; id < UCLASS_COUNT; id++) {
for (i = 0; i < count; i++) {
struct dm_test_pdata *pdata;
- ut_assertok(device_bind_by_name(parent, &driver_info_manual,
- &dev));
+ ut_assertok(device_bind_by_name(parent, false,
+ &driver_info_manual, &dev));
pdata = calloc(1, sizeof(*pdata));
pdata->ping_add = key + i;
dev->platdata = pdata;
return 0;
}
DM_TEST(dm_test_children, 0);
+
+/* Test that pre-relocation devices work as expected */
+static int dm_test_pre_reloc(struct dm_test_state *dms)
+{
+ struct udevice *dev;
+
+ /* The normal driver should refuse to bind before relocation */
+ ut_asserteq(-EPERM, device_bind_by_name(dms->root, true,
+ &driver_info_manual, &dev));
+
+ /* But this one is marked pre-reloc */
+ ut_assertok(device_bind_by_name(dms->root, true,
+ &driver_info_pre_reloc, &dev));
+
+ return 0;
+}
+DM_TEST(dm_test_pre_reloc, 0);
+
+static int dm_test_uclass_before_ready(struct dm_test_state *dms)
+{
+ struct uclass *uc;
+
+ ut_assertok(uclass_get(UCLASS_TEST, &uc));
+
+ memset(gd, '\0', sizeof(*gd));
+ ut_asserteq_ptr(NULL, uclass_find(UCLASS_TEST));
+
+ return 0;
+}
+
+DM_TEST(dm_test_uclass_before_ready, 0);
.remove = test_manual_remove,
.unbind = test_manual_unbind,
};
+
+U_BOOT_DRIVER(test_pre_reloc_drv) = {
+ .name = "test_pre_reloc_drv",
+ .id = UCLASS_TEST,
+ .ops = &test_manual_ops,
+ .bind = test_manual_bind,
+ .probe = test_manual_probe,
+ .remove = test_manual_remove,
+ .unbind = test_manual_unbind,
+ .flags = DM_FLAG_PRE_RELOC,
+};
pdata->ping_add = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"ping-add", -1);
- pdata->base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ pdata->base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset,
+ "ping-expect");
return 0;
}
.id = UCLASS_TEST_FDT,
};
+int dm_check_devices(struct dm_test_state *dms, int num_devices)
+{
+ struct udevice *dev;
+ int ret;
+ int i;
+
+ /*
+ * Now check that the ping adds are what we expect. This is using the
+ * ping-add property in each node.
+ */
+ for (i = 0; i < num_devices; i++) {
+ uint32_t base;
+
+ ret = uclass_get_device(UCLASS_TEST_FDT, i, &dev);
+ ut_assert(!ret);
+
+ /*
+ * Get the 'ping-expect' property, which tells us what the
+ * ping add should be. We don't use the platdata because we
+ * want to test the code that sets that up
+ * (testfdt_drv_probe()).
+ */
+ base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset,
+ "ping-expect");
+ debug("dev=%d, base=%d: %s\n", i, base,
+ fdt_get_name(gd->fdt_blob, dev->of_offset, NULL));
+
+ ut_assert(!dm_check_operations(dms, dev, base,
+ dev_get_priv(dev)));
+ }
+
+ return 0;
+}
+
/* Test that FDT-based binding works correctly */
static int dm_test_fdt(struct dm_test_state *dms)
{
- const int num_drivers = 3;
+ const int num_devices = 4;
struct udevice *dev;
struct uclass *uc;
int ret;
int i;
- ret = dm_scan_fdt(gd->fdt_blob);
+ ret = dm_scan_fdt(gd->fdt_blob, false);
ut_assert(!ret);
ret = uclass_get(UCLASS_TEST_FDT, &uc);
ut_assert(!ret);
- /* These are num_drivers compatible root-level device tree nodes */
- ut_asserteq(num_drivers, list_count_items(&uc->dev_head));
+ /* These are num_devices compatible root-level device tree nodes */
+ ut_asserteq(num_devices, list_count_items(&uc->dev_head));
/* Each should have no platdata / priv */
- for (i = 0; i < num_drivers; i++) {
+ for (i = 0; i < num_devices; i++) {
ret = uclass_find_device(UCLASS_TEST_FDT, i, &dev);
ut_assert(!ret);
ut_assert(!dev_get_priv(dev));
ut_assert(!dev->platdata);
}
+ ut_assertok(dm_check_devices(dms, num_devices));
+
+ return 0;
+}
+DM_TEST(dm_test_fdt, 0);
+
+static int dm_test_fdt_pre_reloc(struct dm_test_state *dms)
+{
+ struct uclass *uc;
+ int ret;
+
+ ret = dm_scan_fdt(gd->fdt_blob, true);
+ ut_assert(!ret);
+
+ ret = uclass_get(UCLASS_TEST_FDT, &uc);
+ ut_assert(!ret);
+
+ /* These is only one pre-reloc device */
+ ut_asserteq(1, list_count_items(&uc->dev_head));
+
+ return 0;
+}
+DM_TEST(dm_test_fdt_pre_reloc, 0);
+
+/* Test that sequence numbers are allocated properly */
+static int dm_test_fdt_uclass_seq(struct dm_test_state *dms)
+{
+ struct udevice *dev;
+
+ /* A few basic santiy tests */
+ ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_FDT, 3, true, &dev));
+ ut_asserteq_str("b-test", dev->name);
+
+ ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_FDT, 0, true, &dev));
+ ut_asserteq_str("a-test", dev->name);
+
+ ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_TEST_FDT, 5,
+ true, &dev));
+ ut_asserteq_ptr(NULL, dev);
+
+ /* Test aliases */
+ ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 6, &dev));
+ ut_asserteq_str("e-test", dev->name);
+
+ ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_TEST_FDT, 7,
+ true, &dev));
+
/*
- * Now check that the ping adds are what we expect. This is using the
- * ping-add property in each node.
+ * Note that c-test nodes are not probed since it is not a top-level
+ * node
*/
- for (i = 0; i < num_drivers; i++) {
- uint32_t base;
+ ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 3, &dev));
+ ut_asserteq_str("b-test", dev->name);
- ret = uclass_get_device(UCLASS_TEST_FDT, i, &dev);
- ut_assert(!ret);
+ /*
+ * d-test wants sequence number 3 also, but it can't have it because
+ * b-test gets it first.
+ */
+ ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 2, &dev));
+ ut_asserteq_str("d-test", dev->name);
- /*
- * Get the 'reg' property, which tells us what the ping add
- * should be. We don't use the platdata because we want
- * to test the code that sets that up (testfdt_drv_probe()).
- */
- base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
- debug("dev=%d, base=%d: %s\n", i, base,
- fdt_get_name(gd->fdt_blob, dev->of_offset, NULL));
+ /* d-test actually gets 0 */
+ ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 0, &dev));
+ ut_asserteq_str("d-test", dev->name);
- ut_assert(!dm_check_operations(dms, dev, base,
- dev_get_priv(dev)));
- }
+ /* initially no one wants seq 1 */
+ ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_TEST_FDT, 1,
+ &dev));
+ ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 0, &dev));
+ ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 1, &dev));
+
+ /* But now that it is probed, we can find it */
+ ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 1, &dev));
+ ut_asserteq_str("a-test", dev->name);
return 0;
}
-DM_TEST(dm_test_fdt, 0);
+DM_TEST(dm_test_fdt_uclass_seq, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that we can find a device by device tree offset */
+static int dm_test_fdt_offset(struct dm_test_state *dms)
+{
+ const void *blob = gd->fdt_blob;
+ struct udevice *dev;
+ int node;
+
+ node = fdt_path_offset(blob, "/e-test");
+ ut_assert(node > 0);
+ ut_assertok(uclass_get_device_by_of_offset(UCLASS_TEST_FDT, node,
+ &dev));
+ ut_asserteq_str("e-test", dev->name);
+
+ /* This node should not be bound */
+ node = fdt_path_offset(blob, "/junk");
+ ut_assert(node > 0);
+ ut_asserteq(-ENODEV, uclass_get_device_by_of_offset(UCLASS_TEST_FDT,
+ node, &dev));
+
+ /* This is not a top level node so should not be probed */
+ node = fdt_path_offset(blob, "/some-bus/c-test@5");
+ ut_assert(node > 0);
+ ut_asserteq(-ENODEV, uclass_get_device_by_of_offset(UCLASS_TEST_FDT,
+ node, &dev));
+
+ return 0;
+}
+DM_TEST(dm_test_fdt_offset, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
ut_assertok(dm_test_init(dms));
if (test->flags & DM_TESTF_SCAN_PDATA)
- ut_assertok(dm_scan_platdata());
+ ut_assertok(dm_scan_platdata(false));
if (test->flags & DM_TESTF_PROBE_TEST)
ut_assertok(do_autoprobe(dms));
if (test->flags & DM_TESTF_SCAN_FDT)
- ut_assertok(dm_scan_fdt(gd->fdt_blob));
+ ut_assertok(dm_scan_fdt(gd->fdt_blob, false));
if (test->func(dms))
break;
#address-cells = <1>;
#size-cells = <0>;
+ aliases {
+ console = &uart0;
+ testfdt6 = "/e-test";
+ };
+
+ uart0: serial {
+ compatible = "sandbox,serial";
+ u-boot,dm-pre-reloc;
+ };
+
a-test {
reg = <0>;
compatible = "denx,u-boot-fdt-test";
+ ping-expect = <0>;
ping-add = <0>;
+ u-boot,dm-pre-reloc;
};
junk {
b-test {
reg = <3>;
compatible = "denx,u-boot-fdt-test";
+ ping-expect = <3>;
ping-add = <3>;
};
some-bus {
#address-cells = <1>;
#size-cells = <0>;
- reg = <4>;
+ compatible = "denx,u-boot-test-bus";
+ reg = <3>;
+ ping-expect = <4>;
ping-add = <4>;
- c-test {
+ c-test@5 {
compatible = "denx,u-boot-fdt-test";
reg = <5>;
+ ping-expect = <5>;
ping-add = <5>;
};
+ c-test@0 {
+ compatible = "denx,u-boot-fdt-test";
+ reg = <0>;
+ ping-expect = <6>;
+ ping-add = <6>;
+ };
+ c-test@1 {
+ compatible = "denx,u-boot-fdt-test";
+ reg = <1>;
+ ping-expect = <7>;
+ ping-add = <7>;
+ };
};
d-test {
- reg = <6>;
+ reg = <3>;
+ ping-expect = <6>;
+ ping-add = <6>;
+ compatible = "google,another-fdt-test";
+ };
+
+ e-test {
+ reg = <3>;
+ ping-expect = <6>;
ping-add = <6>;
compatible = "google,another-fdt-test";
};
return self.builder.do_make(commit, brd, stage, cwd, *args,
**kwargs)
- def RunCommit(self, commit_upto, brd, work_dir, do_config, force_build):
+ def RunCommit(self, commit_upto, brd, work_dir, do_config, force_build,
+ force_build_failures):
"""Build a particular commit.
If the build is already done, and we are not forcing a build, we skip
work_dir: Directory to which the source will be checked out
do_config: True to run a make <board>_config on the source
force_build: Force a build even if one was previously done
+ force_build_failures: Force a bulid if the previous result showed
+ failure
Returns:
tuple containing:
# Check if the job was already completed last time
done_file = self.builder.GetDoneFile(commit_upto, brd.target)
result.already_done = os.path.exists(done_file)
- if result.already_done and not force_build:
+ will_build = (force_build or force_build_failures or
+ not result.already_done)
+ if result.already_done and will_build:
# Get the return code from that build and use it
with open(done_file, 'r') as fd:
result.return_code = int(fd.readline())
err_file = self.builder.GetErrFile(commit_upto, brd.target)
if os.path.exists(err_file) and os.stat(err_file).st_size:
result.stderr = 'bad'
- else:
+ elif not force_build:
+ # The build passed, so no need to build it again
+ will_build = False
+
+ if will_build:
# We are going to have to build it. First, get a toolchain
if not self.toolchain:
try:
for commit_upto in range(0, len(job.commits), job.step):
result, request_config = self.RunCommit(commit_upto, brd,
work_dir, do_config,
- force_build or self.builder.force_build)
+ force_build or self.builder.force_build,
+ self.builder.force_build_failures)
failed = result.return_code or result.stderr
+ did_config = do_config
if failed and not do_config:
# If our incremental build failed, try building again
# with a reconfig.
if self.builder.force_config_on_failure:
result, request_config = self.RunCommit(commit_upto,
- brd, work_dir, True, True)
+ brd, work_dir, True, True, False)
+ did_config = True
do_config = request_config
# If we built that commit, then config is done. But if we got
# Of course this is substantially slower if there are build
# errors/warnings (e.g. 2-3x slower even if only 10% of builds
# have problems).
- if (failed and not result.already_done and not do_config and
+ if (failed and not result.already_done and not did_config and
self.builder.force_config_on_failure):
# If this build failed, try the next one with a
# reconfigure.
force_config_on_failure: If a commit fails for a board, disable
incremental building for the next commit we build for that
board, so that we will see all warnings/errors again.
+ force_build_failures: If a previously-built build (i.e. built on
+ a previous run of buildman) is marked as failed, rebuild it.
git_dir: Git directory containing source repository
last_line_len: Length of the last line we printed (used for erasing
it with new progress information)
self._complete_delay = None
self._next_delay_update = datetime.now()
self.force_config_on_failure = True
+ self.force_build_failures = False
self._step = step
self.col = terminal.Color()
parser.add_option('-f', '--force-build', dest='force_build',
action='store_true', default=False,
help='Force build of boards even if already built')
+parser.add_option('-F', '--force-build-failures', dest='force_build_failures',
+ action='store_true', default=False,
+ help='Force build of previously-failed build')
parser.add_option('-d', '--detail', dest='show_detail',
action='store_true', default=False,
help='Show detailed information for each board in summary')
ShowActions(series, why_selected, selected, builder, options)
else:
builder.force_build = options.force_build
+ builder.force_build_failures = options.force_build_failures
# Work out which boards to build
board_selected = boards.GetSelectedDict()
Returns:
Priority of toolchain, 0=highest, 20=lowest.
"""
- priority_list = ['-elf', '-unknown-linux-gnu', '-linux', '-elf',
+ priority_list = ['-elf', '-unknown-linux-gnu', '-linux',
'-none-linux-gnueabi', '-uclinux', '-none-eabi',
'-gentoo-linux-gnu', '-linux-gnueabi', '-le-linux', '-uclinux']
for prio in range(len(priority_list)):
if not toolchains:
print ("Warning: No tool chains - please add a [toolchain] section"
" to your buildman config file %s. See README for details" %
- config_fname)
+ bsettings.config_fname)
for name, value in toolchains:
if '*' in value:
{
int fd_in, fd_out;
struct boot_img img;
- unsigned file_size, load_size;
+ unsigned file_size;
int count;
if (argc < 2) {
if (file_size > SRAM_LOAD_MAX_SIZE) {
fprintf(stderr, "ERROR: File too large!\n");
return EXIT_FAILURE;
- } else {
- load_size = ALIGN(file_size, sizeof(int));
}
fd_out = open(argv[2], O_WRONLY | O_CREAT, 0666);
/* read file to buffer to calculate checksum */
lseek(fd_in, 0, SEEK_SET);
- count = read(fd_in, img.code, load_size);
- if (count != load_size) {
+ count = read(fd_in, img.code, file_size);
+ if (count != file_size) {
perror("Reading input image");
return EXIT_FAILURE;
}
& 0x00FFFFFF);
memcpy(img.header.magic, BOOT0_MAGIC, 8); /* no '0' termination */
img.header.length =
- ALIGN(load_size + sizeof(struct boot_file_head), BLOCK_SIZE);
+ ALIGN(file_size + sizeof(struct boot_file_head), BLOCK_SIZE);
gen_check_sum(&img.header);
count = write(fd_out, &img, img.header.length);
print stdout
return False
old_head = stdout.splitlines()[0]
+ if old_head == 'undefined':
+ str = "Invalid HEAD '%s'" % stdout.strip()
+ print col.Color(col.RED, str)
+ return False
# Checkout the required start point
cmd = ['git', 'checkout', 'HEAD~%d' % start_point]
projects / karo-tx-uboot.git / commitdiff