powerpc/85xx: update the work-around for P4080 erratum SERDES-9

The documented work-around for P4080 erratum SERDES-9 has been updated.
It is now compatible with the work-around for erratum A-4580.

This requires adding a few bitfield macros for the BnTTLCRy0 register.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 7f466ac6a94f2cb38796544d298eb947300aec5a..5495dc59eef868aaa3d90af882c6df23ae506646 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -714,9 +714,13 @@ void fsl_serdes_init(void)
 
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
                /*
-                * Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for
-                * each of the SerDes lanes selected as SGMII, XAUI, SRIO, or
-                * AURORA before the device is initialized.
+                * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1
+                * for each of the SerDes lanes selected as SGMII, XAUI, SRIO,
+                * or AURORA before the device is initialized.
+                *
+                * Note that this part of the SERDES-9 work-around is
+                * redundant if the work-around for A-4580 has already been
+                * applied via PBI.
                 */
                switch (lane_prtcl) {
                case SGMII_FM1_DTSEC1:
@@ -733,10 +737,12 @@ void fsl_serdes_init(void)
                case SRIO1:
                case SRIO2:
                case AURORA:
-                       clrsetbits_be32(&srds_regs->lane[idx].ttlcr0,
-                                       SRDS_TTLCR0_FLT_SEL_MASK,
-                                       SRDS_TTLCR0_FLT_SEL_750PPM |
-                                       SRDS_TTLCR0_PM_DIS);
+                       out_be32(&srds_regs->lane[idx].ttlcr0,
+                                SRDS_TTLCR0_FLT_SEL_KFR_26 |
+                                SRDS_TTLCR0_FLT_SEL_KPH_28 |
+                                SRDS_TTLCR0_FLT_SEL_750PPM |
+                                SRDS_TTLCR0_FREQOVD_EN);
+                       break;
                default:
                        break;
                }

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index b61f592d2b60fb189e7767effc1ff1ba4d559251..296b5497798ee08c86e1f9fec78c899e4a4ca93a 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2637,8 +2637,11 @@ typedef struct serdes_corenet {
                u32     res3;
                u32     ttlcr0; /* Transition Tracking Loop Ctrl 0 */
 #define SRDS_TTLCR0_FLT_SEL_MASK       0x3f000000
+#define SRDS_TTLCR0_FLT_SEL_KFR_26     0x10000000
+#define SRDS_TTLCR0_FLT_SEL_KPH_28     0x08000000
 #define SRDS_TTLCR0_FLT_SEL_750PPM     0x03000000
 #define SRDS_TTLCR0_PM_DIS             0x00004000
+#define SRDS_TTLCR0_FREQOVD_EN         0x00000001
                u32     res4[7];
        } lane[24];
        u32 res6[384];