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x86: Issue SMI to finalize Coreboot in final stage
authorDuncan Laurie <dlaurie@chromium.org>
Sat, 3 Nov 2012 11:41:35 +0000 (11:41 +0000)
committerSimon Glass <sjg@chromium.org>
Thu, 6 Dec 2012 22:30:43 +0000 (14:30 -0800)
This will write magic value to APMC command port which
will trigger an SMI and cause coreboot to lock down
the ME, chipset, and CPU.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>

No differences found
UBoot for KaRo TX COM modules