+
+#ifndef CONFIG_SPL_BUILD
+static int exynos_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ struct exynos_bank_info *state = dev_get_priv(dev);
+ int cfg;
+
+ if (!*state->label[offset])
+ return GPIOF_UNUSED;
+ cfg = s5p_gpio_get_cfg_pin(state->bank, offset);
+ if (cfg == S5P_GPIO_OUTPUT)
+ return GPIOF_OUTPUT;
+ else if (cfg == S5P_GPIO_INPUT)
+ return GPIOF_INPUT;
+ else
+ return GPIOF_FUNC;
+}
+
+static const struct dm_gpio_ops gpio_exynos_ops = {
+ .request = exynos_gpio_request,
+ .free = exynos_gpio_free,
+ .direction_input = exynos_gpio_direction_input,
+ .direction_output = exynos_gpio_direction_output,
+ .get_value = exynos_gpio_get_value,
+ .set_value = exynos_gpio_set_value,
+ .get_function = exynos_gpio_get_function,
+ .get_state = exynos_gpio_get_state,
+};
+
+static int gpio_exynos_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ struct exynos_bank_info *priv = dev->priv;
+ struct exynos_gpio_platdata *plat = dev->platdata;
+
+ /* Only child devices have ports */
+ if (!plat)
+ return 0;
+
+ priv->bank = plat->bank;
+
+ uc_priv->gpio_count = GPIO_PER_BANK;
+ uc_priv->bank_name = plat->bank_name;
+
+ return 0;
+}
+
+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child
+ * device for each Exynos GPIO bank.
+ */
+static int gpio_exynos_bind(struct udevice *parent)
+{
+ struct exynos_gpio_platdata *plat = parent->platdata;
+ struct s5p_gpio_bank *bank, *base;
+ const void *blob = gd->fdt_blob;
+ int node;
+
+ /* If this is a child device, there is nothing to do here */
+ if (plat)
+ return 0;
+
+ base = (struct s5p_gpio_bank *)fdtdec_get_addr(gd->fdt_blob,
+ parent->of_offset, "reg");
+ for (node = fdt_first_subnode(blob, parent->of_offset), bank = base;
+ node > 0;
+ node = fdt_next_subnode(blob, node), bank++) {
+ struct exynos_gpio_platdata *plat;
+ struct udevice *dev;
+ fdt_addr_t reg;
+ int ret;
+
+ if (!fdtdec_get_bool(blob, node, "gpio-controller"))
+ continue;
+ plat = calloc(1, sizeof(*plat));
+ if (!plat)
+ return -ENOMEM;
+ reg = fdtdec_get_addr(blob, node, "reg");
+ if (reg != FDT_ADDR_T_NONE)
+ bank = (struct s5p_gpio_bank *)((ulong)base + reg);
+ plat->bank = bank;
+ plat->bank_name = fdt_get_name(blob, node, NULL);
+ debug("dev at %p: %s\n", bank, plat->bank_name);
+
+ ret = device_bind(parent, parent->driver,
+ plat->bank_name, plat, -1, &dev);
+ if (ret)
+ return ret;
+ dev->of_offset = parent->of_offset;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id exynos_gpio_ids[] = {
+ { .compatible = "samsung,s5pc100-pinctrl" },
+ { .compatible = "samsung,s5pc110-pinctrl" },
+ { .compatible = "samsung,exynos4210-pinctrl" },
+ { .compatible = "samsung,exynos4x12-pinctrl" },
+ { .compatible = "samsung,exynos5250-pinctrl" },
+ { .compatible = "samsung,exynos5420-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(gpio_exynos) = {
+ .name = "gpio_exynos",
+ .id = UCLASS_GPIO,
+ .of_match = exynos_gpio_ids,
+ .bind = gpio_exynos_bind,
+ .probe = gpio_exynos_probe,
+ .priv_auto_alloc_size = sizeof(struct exynos_bank_info),
+ .ops = &gpio_exynos_ops,
+};
+#endif