+++ /dev/null
-#########################################################################
-# #
-# Regular Maintainers for U-Boot board support: #
-# #
-# For any board without permanent maintainer, please contact #
-# Wolfgang Denk <wd@denx.de> #
-# and Cc: the <u-boot@lists.denx.de> mailing list. #
-# #
-# Note: lists sorted by Maintainer Name #
-# Note: These are the maintainers for specific *boards*. The #
-# custodians for general architectures and subsystems can #
-# be found here -- http://www.denx.de/wiki/U-Boot/Custodians #
-# #
-#########################################################################
-
-
-#########################################################################
-# PowerPC Systems: #
-# #
-# Maintainer Name, Email Address #
-# Board CPU #
-#########################################################################
-
-Poonam Aggrwal <poonam.aggrwal@freescale.com>
-
- P2020RDB P2020
-
- BSC9131RDB BSC9131
-
-Naveen Burmi <NaveenBurmi@freescale.com>
-
- BSC9132QDS BSC9132
-
-Greg Allen <gallen@arlut.utexas.edu>
-
- UTX8245 MPC8245
-
-Pantelis Antoniou <panto@intracom.gr>
-
- NETVIA MPC8xx
-
-Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-
- cpci5200 MPC5200
- mecp5123 MPC5121
- mecp5200 MPC5200
- pf5200 MPC5200
-
- caddy2 MPC8349
- vme8349 MPC8349
-
- CPCI750 PPC750FX/GX
-
-Peter Barada <peter.barada@logicpd.com>
-
- omap3_logic ARM ARMV7 (Logic OMAP35xx/DM37xx)
-
-Yuli Barcohen <yuli@arabellasw.com>
-
- Adder MPC87x/MPC852T
- ep8248 MPC8248
- ISPAN MPC8260
- MPC8260ADS MPC826x/MPC827x/MPC8280
- Rattler MPC8248
- ZPC1900 MPC8265
-
-Michael Barkowski <michael.barkowski@freescale.com>
-
- MPC8323ERDB MPC8323
-
-Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
-
- sacsng MPC8260
-
-Oliver Brown <obrown@adventnetworks.com>
-
- gw8260 MPC8260
-
-Holger Brunck <holger.brunck@keymile.com>
-
- kmeter1 MPC8360
- kmcoge5ne MPC8360
- mgcoge MPC8247
- mgcoge3ne MPC8247
- suvd3 MPC8321
- tuge1 MPC8321
- tuxx1 MPC8321
-
-Conn Clark <clark@esteem.com>
-
- ESTEEM192E MPC8xx
-
-Jason Cooper <u-boot@lakedaemon.net>
-
- dreamplug ARM926EJS (Kirkwood SoC)
-
-Joe D'Abbraccio <ljd015@freescale.com>
-
- MPC837xERDB MPC837x
-
-Kári DavÃðsson <kd@flaga.is>
-
- FLAGADM MPC823
-
-Torsten Demke <torsten.demke@fci.com>
-
- eXalion MPC824x
-
-Wolfgang Denk <wd@denx.de>
-
- IceCube_5200 MPC5200
-
- ARIA MPC5121e
-
- FPS850L MPC850
- FPS860L MPC860
- ICU862 MPC862
- IP860 MPC860
- IVML24 MPC860
- IVML24_128 MPC860
- IVML24_256 MPC860
- IVMS8 MPC860
- IVMS8_128 MPC860
- IVMS8_256 MPC860
- LWMON MPC823
- R360MPI MPC823
- RRvision MPC823
- SM850 MPC850
- SPD823TS MPC823
- TQM823L MPC823
- TQM823L_LCD MPC823
- TQM850L MPC850
- TQM855L MPC855
- TQM860L MPC860
- TQM860L_FEC MPC860
- hermes MPC860
- lwmon MPC823
-
- CU824 MPC8240
- Sandpoint8240 MPC8240
-
- ATC MPC8250
- PM825 MPC8250
-
- TQM8255 MPC8255
-
- CPU86 MPC8260
- PM826 MPC8260
- TQM8260 MPC8260
-
- P3G4 MPC7410
-
-Phil Edworthy <phil.edworthy@renesas.com>
-
- rsk7264 SH7264
-
-egnite GmbH <info@egnite.de>
-
- ethernut5 ARM926EJS (AT91SAM9XE SoC)
-
-Dirk Eibach <eibach@gdsys.de>
-
- controlcenterd P1022
- devconcenter PPC460EX
- dlvision PPC405EP
- dlvision-10g PPC405EP
- gdppc440etx PPC440EP/GR
- intip PPC460EX
- io PPC405EP
- io64 PPC405EX
- iocon PPC405EP
- neo PPC405EP
-
-Dave Ellis <DGE@sixnetio.com>
-
- SXNI855T MPC8xx
-
-Thomas Frieden <ThomasF@hyperion-entertainment.com>
-
- AmigaOneG3SE MPC7xx
-
-Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-
- APC405 PPC405GP
- AR405 PPC405GP
- ASH405 PPC405EP
- CPCI2DP PPC405GP
- CPCI405 PPC405GP
- CPCI4052 PPC405GP
- CPCI405AB PPC405GP
- CPCI405DT PPC405GP
- CPCIISER4 PPC405GP
- DP405 PPC405EP
- DU405 PPC405GP
- DU440 PPC440EPx
- G2000 PPC405EP
- HH405 PPC405EP
- HUB405 PPC405EP
- OCRTC PPC405GP
- ORSG PPC405GP
- PCI405 PPC405GP
- PLU405 PPC405EP
- PMC405 PPC405GP
- PMC405DE PPC405EP
- PMC440 PPC440EPx
- VOH405 PPC405EP
- VOM405 PPC405EP
- WUH405 PPC405EP
- CMS700 PPC405EP
-
-Siddarth Gore <gores@marvell.com>
-
- guruplug ARM926EJS (Kirkwood SoC)
-
-Paul Gortmaker <paul.gortmaker@windriver.com>
-
- sbc8349 MPC8349
- sbc8548 MPC8548
- sbc8641d MPC8641D
-
-Frank Gottschling <fgottschling@eltec.de>
-
- MHPC MPC8xx
-
-Wolfgang Grandegger <wg@denx.de>
-
- ipek01 MPC5200
-
- PN62 MPC8240
- IPHASE4539 MPC8260
-
-Anatolij Gustschin <agust@denx.de>
-
- ac14xx MPC5121e
- O2D MPC5200
- O2D300 MPC5200
- O2DNT2 MPC5200
- O2I MPC5200
- O2MNT MPC5200
- O3DNT MPC5200
-
-Rob Herring <rob.herring@calxeda.com>
-
- highbank highbank
-
-Klaus Heydeck <heydeck@kieback-peter.de>
-
- KUP4K MPC855
- KUP4X MPC859
-
-Gabriel Huau <contact@huau-gabriel.fr>
-
- mini2440 s3c2440
-
-Gary Jennejohn <garyj@denx.de>
-
- quad100hd PPC405EP
-
-Murray Jensen <Murray.Jensen@csiro.au>
-
- cogent_mpc8xx MPC8xx
-
- cogent_mpc8260 MPC8260
- hymod MPC8260
-
-Larry Johnson <lrj@acm.org>
-
- korat PPC440EPx
-
-Feng Kan <fkan@amcc.com>
-
- redwood PPC4xx
-
-Brad Kemp <Brad.Kemp@seranoa.com>
-
- ppmc8260 MPC8260
-
-Sangmoon Kim <dogoil@etinsys.com>
-
- debris MPC8245
- KVME080 MPC8245
-
-The LEOX team <team@leox.org>
-
- ELPT860 MPC860T
-
-Guennadi Liakhovetski <g.liakhovetski@gmx.de>
-
- linkstation MPC8241
-
-Dave Liu <daveliu@freescale.com>
-
- MPC8315ERDB MPC8315
- MPC832XEMDS MPC832x
- MPC8360EMDS MPC8360
- MPC837XEMDS MPC837x
-
-Nye Liu <nyet@zumanetworks.com>
-
- ZUMA MPC7xx_74xx
-
-Kumar Gala <kumar.gala@freescale.com>
-
- MPC8540ADS MPC8540
- MPC8560ADS MPC8560
- MPC8541CDS MPC8541
- MPC8555CDS MPC8555
-
- MPC8641HPCN MPC8641D
-
-Ron Madrid <info@sheldoninst.com>
-
- SIMPC8313 MPC8313
-
-Dan Malek <dan@embeddedalley.com>
-
- stxgp3 MPC85xx
- stxssa MPC85xx
- stxxtc MPC8xx
-
-Ryan Mallon <ryan@bluewatersys.com>
-
- snapper9260 ARM926EJS (AT91SAM9260 SoC)
- snapper9g20 ARM926EJS (AT91SAM9G20 SoC)
-
-Andrea "llandre" Marson <andrea.marson@dave-tech.it>
-
- PPChameleonEVB PPC405EP
-
-Tirumala Marri <tmarri@apm.com>
-
- bluestone APM821XX
-
-Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-
- TOP860 MPC860T
- TOP5200 MPC5200
- TOP9000 ARM926EJS (AT91SAM9xxx SoC)
-
-Kyle Moffett <Kyle.D.Moffett@boeing.com>
-
- HWW1U1A P2020
-
-Tolunay Orkun <torkun@nextio.com>
-
- csb272 PPC405GP
- csb472 PPC405GP
-
-John Otken <jotken@softadvances.com>
-
- luan PPC440SP
- taihu PPC405EP
-
-Keith Outwater <Keith_Outwater@mvis.com>
-
- GEN860T MPC860T
- GEN860T_SC MPC860T
-
-Frank Panno <fpanno@delphintech.com>
-
- ep8260 MPC8260
-
-Chan-Taek Park <c-park@ti.com>
-
- tnetv107x_evm tnetv107x
-
-Denis Peter <d.peter@mpl.ch>
-
- MIP405 PPC4xx
- PIP405 PPC4xx
-
-Werner Pfister <Pfister_Werner@intercontrol.de>
- digsy_mtc mpc5200
- digsy_mtc_rev5 mpc5200
-
-Kim Phillips <kim.phillips@freescale.com>
-
- MPC8349EMDS MPC8349
-
-Sergei Poselenov <sposelenov@emcraft.com>
-
- a4m072 MPC5200
-
-Sudhakar Rajashekhara <sudhakar.raj@ti.com>
-
- da850evm ARM926EJS (DA850/OMAP-L138)
-
-Ricardo Ribalda <ricardo.ribalda@uam.es>
-
- ml507 PPC440x5
- v5fx30teval PPC440x5
- xilinx-ppc405-generic PPC405
- xilinx-ppc440-generic PPC440x5
-
-Stefan Roese <sr@denx.de>
-
- a3m071 MPC5200
- a4m2k MPC5200
-
- P3M7448 MPC7448
-
- uc100 MPC857
-
- acadia PPC405EZ
- alpr PPC440GX
- bamboo PPC440EP
- bunbinga PPC405EP
- canyonlands PPC460EX
- ebony PPC440GP
- glacier PPC460GT
- haleakala PPC405EXr
- icon PPC440SPe
- katmai PPC440SPe
- kilauea PPC405EX
- lwmon5 PPC440EPx
- makalu PPC405EX
- ocotea PPC440GX
- p3p440 PPC440GP
- pcs440ep PPC440EP
- rainier PPC440GRx
- sequoia PPC440EPx
- sycamore PPC405GPr
- t3corp PPC460GT
- taishan PPC440GX
- walnut PPC405GP
- yellowstone PPC440GR
- yosemite PPC440EP
- zeus PPC405EP
-
- P3M750 PPC750FX/GX/GL
-
-Yusdi Santoso <yusdi_santoso@adaptec.com>
-
- HIDDEN_DRAGON MPC8241/MPC8245
-
-Travis Sawyer (travis.sawyer@sandburst.com>
-
- KAREF PPC440GX
- METROBOX PPC440GX
-
-Georg Schardt <schardt@team-ctech.de>
-
- fx12mm PPC405
-
-Heiko Schocher <hs@denx.de>
-
- cam_enc_4xx davinci/ARM926EJS
- charon MPC5200
- ids8247 MPC8247
- ipam390 davinci/ARM926EJS
- jupiter MPC5200
- kmsupx5 MPC8321
- mucmc52 MPC5200
- muas3001 MPC8270
- municse MPC5200
- sc3 PPC405GP
- uc101 MPC5200
- ve8313 MPC8313
-
-Andre Schwarz <andre.schwarz@matrix-vision.de>
-
- mergerbox MPC8377
- mvbc_p MPC5200
- mvblm7 MPC8343
- mvsmr MPC5200
-
-Jon Smirl <jonsmirl@gmail.com>
-
- pcm030 MPC5200
-
-Ira W. Snyder <iws@ovro.caltech.edu>
-
- P2020COME P2020
-
-York Sun <yorksun@freescale.com>
-
- T4240EMU T4240
-
-Timur Tabi <timur@freescale.com>
-
- MPC8349E-mITX MPC8349
- MPC8349E-mITX-GP MPC8349
- P1022DS P1022
-
-Erik Theisen <etheisen@mindspring.com>
-
- W7OLMC PPC4xx
- W7OLMG PPC4xx
-
-Jim Thompson <jim@musenki.com>
-
- MUSENKI MPC8245/8241
- Sandpoint8245 MPC8245
-
-Rune Torgersen <runet@innovsys.com>
-
- MPC8266ADS MPC8266
-
-Peter Tyser <ptyser@xes-inc.com>
-
- xpedite1000 PPC440GX
- xpedite5170 MPC8640
- xpedite5200 MPC8548
- xpedite5370 MPC8572
- xpedite5500 P2020
-
-David Updegraff <dave@cray.com>
-
- CRAYL1 PPC4xx
-
-Anton Vorontsov <avorontsov@ru.mvista.com>
-
- MPC8360ERDK MPC8360
-
-Josef Wagner <Wagner@Microsys.de>
-
- CPC45 MPC8245
- PM520 MPC5200
-
-Michael Weiss <michael.weiss@ifm.com>
-
- PDM360NG MPC5121e
-
-Stephen Williams <steve@icarus.com>
-
- JSE PPC405GPr
-
-Ilya Yanok <yanok@emcraft.com>
-
- mpc8308_p1m MPC8308
- MPC8308RDB MPC8308
-
-Roy Zang <tie-fei.zang@freescale.com>
-
- mpc7448hpc2 MPC7448
- P1023RDS P1023
-
-John Zhan <zhanz@sinovee.com>
-
- svm_sc8xx MPC8xx
-
-Detlev Zundel <dzu@denx.de>
-
- inka4x0 MPC5200
-
-Po Liu <po.liu@freescale.com>
-
- C29XPCIE C29X
-
--------------------------------------------------------------------------
-
-Unknown / orphaned boards:
-
- ADS860 MPC8xx
- FADS823 MPC8xx
- FADS850SAR MPC8xx
- FADS860T MPC8xx
- GENIETV MPC8xx
- MBX MPC8xx
- MBX860T MPC8xx
- NX823 MPC8xx
- RPXClassic MPC8xx
- RPXlite MPC8xx
-
- MOUSSE MPC824x
-
- RPXsuper MPC8260
- rsdproto MPC8260
-
- EVB64260 MPC7xx_74xx
- EVB64260_750CX MPC750CX [Eran Man <eran@nbase.co.il>]
-
- versatile ARM926EJ-S
-
-#########################################################################
-# ARM Systems: #
-# #
-# Maintainer Name, Email Address #
-# Board CPU #
-#########################################################################
-
-Albert ARIBAUD <albert.u.boot@aribaud.net>
-
- edminiv2 ARM926EJS (Orion5x SoC)
-
-Raphael Assenat <raph@8d.com>
-
- eco5pk ARM ARMV7 (AM35x SoC)
-
-Stefano Babic <sbabic@denx.de>
-
- ea20 davinci
- flea3 i.MX35
- mt_ventoux omap3
- mx35pdk i.MX35
- mx51evk i.MX51
- polaris xscale/pxa
- trizepsiv xscale/pxa
- twister omap3
- vision2 i.MX51
- woodburn i.MX35
-
-Lukasz Dalek <luk0104@gmail.com>
-
- h2200 xscale/pxa
-
-Jason Liu <r64343@freescale.com>
-
- mx53evk i.MX53
- mx53loco i.MX53
- mx6qarm2 i.MX6Q
-
-Enric Balletbo i Serra <eballetbo@iseebcn.com>
-
- igep0020 ARM ARMV7 (OMAP3xx SoC)
- igep0030 ARM ARMV7 (OMAP3xx SoC)
- igep0032 ARM ARMV7 (OMAP3xx SoC)
- igep0033 ARM ARMV7 (AM33xx Soc)
-
-Eric Benard <eric@eukrea.com>
-
- cpuat91 ARM920T
- cpu9260 ARM926EJS (AT91SAM9260 SoC)
- cpu9G20 ARM926EJS (AT91SAM9G20 SoC)
-
-Ajay Bhargav <ajay.bhargav@einfochips.com>
-
- gplugd ARM926EJS (ARMADA100 88AP168 SoC)
-
-Rishi Bhattacharya <rishi@ti.com>
-
- omap5912osk ARM926EJS
-
-Andreas Bießmann <andreas.devel@gmail.com>
-
- at91rm9200ek at91rm9200
-
-Cliff Brake <cliff.brake@gmail.com>
-
- pxa255_idp xscale/pxa
-
-Rick Bronson <rick@efn.org>
-
- AT91RM9200DK at91rm9200
-
-Luca Ceresoli <luca.ceresoli@comelit.it>
-
- dig297 ARM ARMV7 (OMAP3530 SoC)
-
-Po-Yu Chuang <ratbert@faraday-tech.com>
-
- a320evb FA526 (ARM920T-like) (a320 SoC)
-
-Eric Cooper <ecc@cmu.edu>
-
- dockstar ARM926EJS (Kirkwood SoC)
-
-Wolfgang Denk <wd@denx.de>
- imx27lite i.MX27
- qong i.MX31
-
-Mike Dunn <mikedunn@newsguy.com>
- palmtreo680 pxa270
-
-Kristoffer Ericson <kristoffer.ericson@gmail.com>
-
- jornada SA1110
-
-Fabio Estevam <fabio.estevam@freescale.com>
-
- mx25pdk i.MX25
- mx28evk i.MX28
- mx31pdk i.MX31
- mx53ard i.MX53
- mx53smd i.MX53
- mx6sabresd i.MX6Q/DL
- mx6qsabreauto i.MX6Q
- wandboard i.MX6DL/S/Q
- mx6slevk i.MX6SL
-
-Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
-
- meesc ARM926EJS (AT91SAM9263 SoC)
- otc570 ARM926EJS (AT91SAM9263 SoC)
-
-Bo Shen<voice.shen@atmel.com>
- at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC)
- at91sam9m10g45ek ARM926EJS (AT91SAM9G45 SoC)
-
-Simon Guinot <simon.guinot@sequanux.org>
-
- inetspace_v2 ARM926EJS (Kirkwood SoC)
- netspace_v2 ARM926EJS (Kirkwood SoC)
- netspace_max_v2 ARM926EJS (Kirkwood SoC)
- net2big_v2 ARM926EJS (Kirkwood SoC)
-
-Igor Grinberg <grinberg@compulab.co.il>
-
- cm_t35 ARM ARMV7 (OMAP3xx Soc)
-
-Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
-
- dns325 ARM926EJS (Kirkwood SoC)
-
-Lauri Hintsala <lauri.hintsala@bluegiga.com>
-
- apx4devkit i.MX28
-
-Vaibhav Hiremath <hvaibhav@ti.com>
-
- am3517_evm ARM ARMV7 (AM35x SoC)
-
-Markus Hubig <mhubig@imko.de>
-
- STAMP9G20 ARM926EJS
-
-Grazvydas Ignotas <notasas@gmail.com>
-
- omap3_pandora ARM ARMV7 (OMAP3xx SoC)
-
-Ilko Iliev <iliev@ronetix.at>
-
- PM9261 AT91SAM9261
- PM9263 AT91SAM9263
- PM9G45 ARM926EJS (AT91SAM9G45 SoC)
-
-Michael Jones <michael.jones@matrix-vision.de>
-
- omap3_mvblx ARM ARMV7 (OMAP3xx SoC)
-
-Matthias Kaehlcke <matthias@kaehlcke.net>
- edb9301 ARM920T (EP9301)
- edb9302 ARM920T (EP9302)
- edb9302a ARM920T (EP9302)
- edb9307 ARM920T (EP9307)
- edb9307a ARM920T (EP9307)
- edb9312 ARM920T (EP9312)
- edb9315 ARM920T (EP9315)
- edb9315a ARM920T (EP9315)
-
-Nishant Kamat <nskamat@ti.com>
-
- omap1610h2 ARM926EJS
-
-Minkyu Kang <mk7.kang@samsung.com>
-
- SMDKC100 ARM ARMV7 (S5PC100 SoC)
- s5p_goni ARM ARMV7 (S5PC110 SoC)
- s5pc210_universal ARM ARMV7 (EXYNOS4210 SoC)
-
-Chander Kashyap <k.chander@samsung.com>
-
- origen ARM ARMV7 (EXYNOS4210 SoC)
- SMDKV310 ARM ARMV7 (EXYNOS4210 SoC)
- SMDK5250 ARM ARMV7 (EXYNOS5250 SoC)
-
-Lukasz Majewski <l.majewski@samsung.com>
-
- trats ARM ARMV7 (EXYNOS4210 SoC)
-
-Torsten Koschorrek <koschorrek@synertronixx.de>
- scb9328 ARM920T (i.MXL)
-
-Sergey Kubushyn <ksi@koi8.net>
-
- DV-EVM ARM926EJS
- SONATA ARM926EJS
- SCHMOOGIE ARM926EJS
-
-Vipin Kumar <vipin.kumar@st.com>
-
- spear300 ARM926EJS (spear300 Soc)
- spear310 ARM926EJS (spear310 Soc)
- spear320 ARM926EJS (spear320 Soc)
- spear600 ARM926EJS (spear600 Soc)
-
-Sergey Lapin <slapin@ossfans.org>
-
- afeb9260 ARM926EJS (AT91SAM9260 SoC)
-
-Valentin Longchamp <valentin.longchamp@keymile.com>
-
- km_kirkwood ARM926EJS (Kirkwood SoC)
- kmnusa ARM926EJS (Kirkwood SoC)
- mgcoge3un ARM926EJS (Kirkwood SoC)
- kmcoge5un ARM926EJS (Kirkwood SoC)
- portl2 ARM926EJS (Kirkwood SoC)
-
-Nishanth Menon <nm@ti.com>
-
- omap3_sdp3430 ARM ARMV7 (OMAP3xx SoC)
- omap3_zoom1 ARM ARMV7 (OMAP3xx SoC)
-
-David Müller <d.mueller@elsoft.ch>
-
- smdk2410 ARM920T
- VCMA9 ARM920T
-
-Eric Millbrandt <emillbrandt@dekaresearch.com>
-
- galaxy5200 mpc5200
-
-Nagendra T S <nagendra@mistralsolutions.com>
-
- am3517_crane ARM ARMV7 (AM35x SoC)
-
-Dinh Nguyen <dinguyen@altera.com>
-Chin Liang See <clsee@altera.com>
-
- socfpga socfpga_cyclone5
-
-Sandeep Paulraj <s-paulraj@ti.com>
-
- davinci_dm355evm ARM926EJS
- davinci_dm355leopard ARM926EJS
- davinci_dm365evm ARM926EJS
- davinci_dm6467evm ARM926EJS
-
-Helmut Raiger <helmut.raiger@hale.at>
-
- tt01 i.MX31
-
-Linus Walleij <linus.walleij@linaro.org>
- integratorap various
- integratorcp various
-
-Luka Perkov <luka@openwrt.org>
-
- ib62x0 ARM926EJS
- iconnect ARM926EJS
-
-Dave Peverley <dpeverley@mpc-data.co.uk>
-
- omap730p2 ARM926EJS
-
-Lars Poeschel <poeschel@lemonage.de>
- pcm051 ARM ARMV7 (AM33xx Soc)
-
-Mathieu Poirier <mathieu.poirier@linaro.org>
-
- snowball ARM ARMV7 (u8500 SoC)
-
-Stelian Pop <stelian@popies.net>
-
- at91sam9260ek ARM926EJS (AT91SAM9260 SoC)
- at91sam9261ek ARM926EJS (AT91SAM9261 SoC)
- at91sam9263ek ARM926EJS (AT91SAM9263 SoC)
- at91sam9rlek ARM926EJS (AT91SAM9RL SoC)
-
-Matt Porter <mporter@ti.com>
-
- ti814x_evm ARM ARMV7 (TI814x Soc)
-
-Dave Purdy <david.c.purdy@gmail.com>
-
- pogo_e02 ARM926EJS (Kirkwood SoC)
-
-Sricharan R <r.sricharan@ti.com>
-
- omap4_panda ARM ARMV7 (OMAP4xx SoC)
- omap4_sdp4430 ARM ARMV7 (OMAP4xx SoC)
- omap5_evm ARM ARMV7 (OMAP5xx Soc)
-
-Suriyan Ramasami <suriyan.r@gmail.com>
-
- goflexhome ARM926EJS (Kirkwood SoC)
-
-Thierry Reding <thierry.reding@avionic-design.de>
-
- plutux Tegra20 (ARM7 & A9 Dual Core)
- medcom-wide Tegra20 (ARM7 & A9 Dual Core)
- tec Tegra20 (ARM7 & A9 Dual Core)
-
-Christian Riesch <christian.riesch@omicron.at>
-Manfred Rudigier <manfred.rudigier@omicron.at>
-
- calimain ARM926EJS (AM1808 SoC)
-
-Tom Rini <trini@ti.com>
-
- am335x_evm ARM ARMV7 (AM33xx Soc)
- omap3_beagle ARM ARMV7 (OMAP3xx SoC)
- omap3_evm ARM ARMV7 (OMAP3xx SoC)
-
-Tom Rix <Tom.Rix@windriver.com>
-
- omap3_zoom2 ARM ARMV7 (OMAP3xx SoC)
-
-John Rigby <jcrigby@gmail.com>
-
- tx25 i.MX25
-
-Stefan Roese <sr@denx.de>
-
- x600 ARM926EJS (spear600 Soc)
-
- titanium i.MX6Q
-
- pdnb3 xscale/ixp
- scpu xscale/ixp
-
-Alessandro Rubini <rubini@unipv.it>
-Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>
-
- nhk8815 ARM926EJS (Nomadik 8815 Soc)
-
-Steve Sakoman <sakoman@gmail.com>
-
- omap3_overo ARM ARMV7 (OMAP3xx SoC)
-
-Leo Sartre <lsartre@adeneo-embedded.com>
-
- cgtqmx6qeval i.MX6Q
-
-Jens Scharsig <esw@bus-elektronik.de>
-
- eb_cpux9k2 ARM920T (AT91RM9200 SoC)
- vl_ma2sc ARM926EJS (AT91SAM9263 SoC)
-
-Heiko Schocher <hs@denx.de>
-
- enbw_cmc ARM926EJS (AM1808 SoC)
- magnesium i.MX27
-
-Michael Schwingen <michael@schwingen.org>
-
- actux1 xscale/ixp
- actux2 xscale/ixp
- actux3 xscale/ixp
- actux4 xscale/ixp
- dvlhost xscale/ixp
-
-Matt Sealey <matt@genesi-usa.com>
-
- efikamx i.MX51
- efikasb i.MX51
-
-Bo Shen <voice.shen@atmel.com>
- at91sam9x5ek ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
- sama5d3xek ARMV7 (SAMA5D31, D33, D34, D35 SoC)
-
-Rajeshwari Shinde <rajeshwari.s@samsung.com>
-
- snow ARM ARMV7 (EXYNOS5250 SoC)
-
-Michal Simek <monstr@monstr.eu>
-
- zynq ARM ARMV7 (Zynq SoC)
-
-Lucas Stach <dev@lynxeye.de>
-
- colibri_t20_iris Tegra20 (ARM7 & A9 Dual Core)
-
-Antoine Tenart <atenart@adeneo-embedded.com>
-
- TI816X ARM ARMV7 (TI816x Soc)
-
-Nick Thompson <nick.thompson@gefanuc.com>
-
- da830evm ARM926EJS (DA830/OMAP-L137)
-
-Albin Tonnerre <albin.tonnerre@free-electrons.com>
-
- sbc35_a9g20 ARM926EJS (AT91SAM9G20 SoC)
- tny_a9260 ARM926EJS (AT91SAM9260 SoC)
- tny_a9g20 ARM926EJS (AT91SAM9G20 SoC)
-
-Greg Ungerer <greg.ungerer@opengear.com>
-
- cm4008 ks8695p
- cm4116 ks8695p
- cm4148 ks8695p
-
-Marek Vasut <marek.vasut@gmail.com>
-
- balloon3 xscale/pxa
- colibri_pxa270 xscale/pxa
- palmld xscale/pxa
- palmtc xscale/pxa
- vpac270 xscale/pxa
- zipitz2 xscale/pxa
- mx23_olinuxino i.MX23
- m28evk i.MX28
- sc_sps_1 i.MX28
- m53evk i.MX53
-
-Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
-
- SFFSDR ARM926EJS
-
-Lokesh Vutla <lokeshvutla@ti.com>
-
- dra7xx_evm ARM ARMV7 (DRA7xx Soc)
-
-Matt Waddel <matt.waddel@linaro.org>
-
- vexpress_ca9x4 ARM ARMV7 (Quad Core)
- vexpress_ca5x2 ARM ARMV7 (Dual Core)
-
-Otavio Salvador <otavio@ossystems.com.br>
-
- mx23evk i.MX23
-
-Prafulla Wadaskar <prafulla@marvell.com>
-
- aspenite ARM926EJS (ARMADA100 88AP168 SoC)
- mv88f6281gtw_ge ARM926EJS (Kirkwood SoC)
- openrd_base ARM926EJS (Kirkwood SoC)
- rd6281a ARM926EJS (Kirkwood SoC)
- sheevaplug ARM926EJS (Kirkwood SoC)
-
-Michael Walle <michael@walle.cc>
-
- lschlv2 ARM926EJS (Kirkwood SoC)
- lsxhl ARM926EJS (Kirkwood SoC)
-
-Tom Warren <twarren@nvidia.com>
-
- harmony Tegra20 (ARM7 & A9 Dual Core)
- seaboard Tegra20 (ARM7 & A9 Dual Core)
- cardhu Tegra30 (ARM7 & A9 Quad Core)
- dalmore Tegra114 (ARM7 & A15 Quad Core)
-
-Tom Warren <twarren@nvidia.com>
-Stephen Warren <swarren@nvidia.com>
-
- ventana Tegra20 (ARM7 & A9 Dual Core)
- paz00 Tegra20 (ARM7 & A9 Dual Core)
- trimslice Tegra20 (ARM7 & A9 Dual Core)
- whistler Tegra20 (ARM7 & A9 Dual Core)
- beaver Tegra30 (ARM7 & A9 Quad Core)
-
-Stephen Warren <swarren@wwwdotorg.org>
-
- rpi_b BCM2835 (ARM1176)
-
-Thomas Weber <weber@corscience.de>
-
- devkit8000 ARM ARMV7 (OMAP3530 SoC)
- tricorder ARM ARMV7 (OMAP3503 SoC)
-
-Lei Wen <leiwen@marvell.com>
-
- dkb ARM926EJS (PANTHEON 88AP920 SOC)
-
-Matthias Weisser <weisserm@arcor.de>
-
- jadecpu ARM926EJS (MB86R01 SoC)
- zmx25 ARM926EJS (imx25 SoC)
-
-Josh Wu <josh.wu@atmel.com>
- at91sam9n12ek ARM926EJS (AT91SAM9N12 SoC)
-
-Ilya Yanok <yanok@emcraft.com>
-
- mcx ARM ARMV7 (AM35x SoC)
-
-Syed Mohammed Khasim <sm.khasim@gmail.com>
-Sughosh Ganu <urwithsughosh@gmail.com>
-
- hawkboard ARM926EJS (OMAP-L138)
-
-Vladimir Zapolskiy <vz@mleia.com>
-
- devkit3250 lpc32xx
-
-Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
-Tetsuyuki Kobayashi <koba@kmckk.co.jp>
-
- kzm9g SH73A0 (RMOBILE SoC)
-
-Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
-
- armadillo-800eva R8A7740 (RMOBILE SoC)
-
-Pali Rohár <pali.rohar@gmail.com>
-
- nokia_rx51 ARM ARMV7 (OMAP34xx SoC)
-
-Eric Nelson <eric.nelson@boundarydevices.com>
- mx6qsabrelite i.MX6Q 1GB
- nitrogen6dl i.MX6DL 1GB
- nitrogen6dl2g i.MX6DL 2GB
- nitrogen6q i.MX6Q/6D 1GB
- nitrogen6q2g i.MX6Q/6D 2GB
- nitrogen6s i.MX6S 512MB
- nitrogen6s1g i.MX6S 1GB
-
-Alison Wang <b18965@freescale.com>
-
- vf610twr VF610
-
-Sergey Yanovich <ynvich@gmail.com>
-
- lp8x4x xscale/pxa
-
--------------------------------------------------------------------------
-
-Unknown / orphaned boards:
- Board CPU Last known maintainer / Comment
-.........................................................................
-
- omap1510inn ARM925T Kshitij Gupta <kshitij@ti.com>
-
- lubbock xscale/pxa Kyle Harris <kharris@nexus-tech.net> / dead address
-
- imx31_phycore_eet i.MX31 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
- mx31ads i.MX31 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
-
-#########################################################################
-# x86 Systems: #
-# #
-# Maintainer Name, Email Address #
-# Board CPU #
-#########################################################################
-
-Simon Glass <sjg@chromium.org>
-
- chromebook-x86 Coreboot runs first, then U-Boot
- Supports Intel Sandy Bridge / Ivy Bridge so far
-
- Chromebooks for x86, including:
- Samsung Series 5 Chromebook
- Acer AC700 Chromebook
- Acer C7 Chromebook
- Samsung Chromebook 550
- HP Pavillion Chromebook
- Acer C710 Chromebook
- Chromebook Pixel
-
-#########################################################################
-# MIPS Systems: #
-# #
-# Maintainer Name, Email Address #
-# Board CPU #
-#########################################################################
-
-Wolfgang Denk <wd@denx.de>
-
- incaip MIPS32 4Kc
-
-Vlad Lungu <vlad.lungu@windriver.com>
- qemu_mips MIPS32
-
-Stefan Roese <sr@denx.de>
-
- vct_xxx MIPS32 4Kc
-
--------------------------------------------------------------------------
-
-Unknown / orphaned boards:
- Board CPU Last known maintainer / Comment
-.........................................................................
-
- dbau1x00 MIPS32 Au1000 Thomas Lange <thomas@corelatus.se>
-
-#########################################################################
-# Nios-II Systems: #
-# #
-# Maintainer Name, Email Address #
-# Board CPU #
-#########################################################################
-
-Scott McNutt <smcnutt@psyent.com>
-
- PCI5441 Nios-II
- PK1C20 Nios-II
- nios2-generic Nios-II
-
-#########################################################################
-# MicroBlaze Systems: #
-# #
-# Maintainer Name, Email Address #
-# Board CPU #
-#########################################################################
-
-Michal Simek <monstr@monstr.eu>
-
- microblaze-generic MicroBlaze
-
-#########################################################################
-# Coldfire Systems: #
-# #
-# Maintainer Name, Email Address #
-# Board CPU #
-#########################################################################
-
-Hayden Fraser <Hayden.Fraser@freescale.com>
-
- M5253EVBE mcf52x2
-
-Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-
- TASREG MCF5249
-
-Jens Scharsig <esw@bus-elektronik.de>
-
- eb_cpu5282 mfc5282
-
-TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-
- M52277EVB mcf5227x
- M5235EVB mcf52x2
- M5253DEMO mcf52x2
- M53017EVB mcf532x
- M5329EVB mcf532x
- M5373EVB mcf532x
- M54455EVB mcf5445x
- M5475EVB mcf547x_8x
- M5485EVB mcf547x_8x
-
-Wolfgang Wegner <w.wegner@astro-kom.de>
-
- astro_mcf5373l MCF5373L
-
-#########################################################################
-# AVR32 Systems: #
-# #
-# Maintainer Name, Email Address #
-# Board CPU #
-#########################################################################
-
-Andreas Bießmann <andreas.devel@googlemail.com>
- grasshopper AT32AP7000
- atngw100mkii AT32AP7000
-
-Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
-
- FAVR-32-EZKIT AT32AP7000
-
-Mark Jackson <mpfj@mimc.co.uk>
-
- MIMC200 AT32AP7000
-
-Alex Raimondi <alex.raimondi@miromico.ch>
-Julien May <julien.may@miromico.ch>
-
- HAMMERHEAD AT32AP7000
-
-Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-
- ATSTK1000 AT32AP7xxx
- ATSTK1002 AT32AP7000
- ATSTK1003 AT32AP7001
- ATSTK1004 AT32AP7002
- ATSTK1006 AT32AP7000
- ATNGW100 AT32AP7000
-
-#########################################################################
-# SuperH Systems: #
-# #
-# Maintainer Name, Email Address #
-# Board CPU #
-#########################################################################
-
-Yusuke Goda <goda.yusuke@renesas.com>
-
- MIGO-R SH7722
-
-Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- <iwamatsu.nobuhiro@renesas.com>
-
- MS7750SE SH7750
- MS7722SE SH7722
- R7780MP SH7780
- R2DPlus SH7751R
- SH7763RDP SH7763
- RSK7203 SH7203
- AP325RXA SH7723
- SHMIN SH7706
- ECOVEC SH7724
- R0P7734 SH7734
- AP_SH4A_4A SH7734
-
-Mark Jonas <mark.jonas@de.bosch.com>
-
- mpr2 SH7720
-
-Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
-
- MS7720SE SH7720
- R0P77520000RZ SH7752
- R0P77570030RL SH7757
- R0P77850011RL SH7785
-
-#########################################################################
-# Blackfin Systems: #
-# #
-# Maintainer Name, Email Address #
-# Board CPU #
-#########################################################################
-
-Sonic Zhang <sonic.adi@gmail.com>
-Blackfin Team <u-boot-devel@blackfin.uclinux.org>
-
- BF506F-EZKIT BF506
- BF518F-EZBRD BF518
- BF526-EZBRD BF526
- BF527-AD7160-EVAL BF527
- BF527-EZKIT BF527
- BF527-EZKIT-V2 BF527
- BF527-SDP BF527
- BF533-EZKIT BF533
- BF533-STAMP BF533
- BF537-PNAV BF537
- BF537-STAMP BF537
- BF538F-EZKIT BF538
- BF548-EZKIT BF548
- BF561-EZKIT BF561
- BF609-EZKIT BF609
-
-M.Hasewinkel (MHA) <info@ssv-embedded.de>
-
- dnp5370 BF537
-
-Brent Kandetzki <brentk@teleco.com>
-
- IP04 BF532
-
-Peter Meerwald <devel@bct-electronic.com>
-
- bct-brettl2 BF536
-
-I-SYST Micromodule <support@i-syst.com>
-
- IBF-DSP561 BF561
-
-Wojtek Skulski <skulski@pas.rochester.edu>
-Wojtek Skulski <info@skutek.com>
-Benjamin Matthews <mben12@gmail.com>
-
- BlackStamp BF533
- BlackVME BF561
-
-Martin Strubel <strubel@section5.ch>
-
- BF537-minotaur BF537
- BF537-srv1 BF537
-
-Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-
- CM-BF527 BF527
- CM-BF533 BF533
- CM-BF537E BF537
- CM-BF537U BF537
- CM-BF548 BF548
- CM-BF561 BF561
- TCM-BF518 BF518
- TCM-BF537 BF537
-
-Valentin Yakovenkov <yakovenkov@niistt.ru>
-Anton Shurpin <shurpin.aa@niistt.ru>
-
- BF561-ACVILON BF561
-
-Haitao Zhang <hzhang@ucrobotics.com>
-Chong Huang <chuang@ucrobotics.com>
-
- bf525-ucr2 BF525
-
-Dimitar Penev <dpn@switchfin.org>
-
- BR4 Appliance BF537
- PR1 Appliance BF537
-
-#########################################################################
-# NDS32 Systems: #
-# #
-# Maintainer Name, Email Address #
-# Board CPU #
-#########################################################################
-
-Andes <uboot@andestech.com>
-
- ADP-AG101 N1213 (AG101 SoC)
- ADP-AG101P N1213 (AG101P XC5 FPGA)
- ADP-AG102 N1213f (AG102 SoC with FPU)
-
-#########################################################################
-# OpenRISC Systems: #
-# #
-# Maintainer Name, Email Address #
-# Board CPU #
-#########################################################################
-
-Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
-
- openrisc-generic OpenRISC
-
-#########################################################################
-# Sandbox: #
-# #
-# Maintainer Name, Email Address #
-# Board CPU #
-#########################################################################
-
-Simon Glass <sjg@chromium.org>
-
- sandbox sandbox
-
-#########################################################################
-# End of MAINTAINERS list #
-#########################################################################
-s|--soc)
# echo "Option SoC: argument \`$2'"
if [ "$opt_s" ] ; then
- opt_s="${opt_s%)} || \$6 == \"$2\" || \$6 ~ /$2/)"
+ opt_s="${opt_s%)} || \$4 == \"$2\" || \$4 ~ /$2/)"
else
- opt_s="(\$6 == \"$2\" || \$6 ~ /$2/)"
+ opt_s="(\$4 == \"$2\" || \$4 ~ /$2/)"
fi
SELECTED='y'
shift 2 ;;
[ "$opt_v" ] && FILTER="${FILTER} && $opt_v"
if [ "$SELECTED" ] ; then
- SELECTED=$(awk '('"$FILTER"') { print $1 }' boards.cfg)
+ SELECTED=$(awk '('"$FILTER"') { print $7 }' boards.cfg)
# Make sure some boards from boards.cfg are actually found
if [ -z "$SELECTED" ] ; then
-v field="$1" \
-v select="$2" \
-F "$FS" \
- '($1 !~ /^#/ && $field == select) { print $1 }' \
+ '($1 !~ /^#/ && $field == select) { print $7 }' \
boards.cfg
}
boards_by_arch() { boards_by_field 2 "$@" ; }
boards_by_cpu() { boards_by_field 3 "$@" "[: \t]+" ; }
-boards_by_soc() { boards_by_field 6 "$@" ; }
+boards_by_soc() { boards_by_field 4 "$@" ; }
#########################################################################
## MPC5xx Systems
local vendor=""
# Automatic mode
- local line=`egrep -i "^[[:space:]]*${target}[[:space:]]" boards.cfg`
-
+ local line=`awk -F '\ +' '\$7 == "'"$target"'" { print \$0 }' boards.cfg`
if [ -z "${line}" ] ; then echo "" ; return ; fi
set ${line}
- # add default board name if needed
- [ $# = 3 ] && set ${line} ${1}
-
- CONFIG_NAME="${1%_config}"
+ CONFIG_NAME="${7%_config}"
- [ "${BOARD_NAME}" ] || BOARD_NAME="${1%_config}"
+ [ "${BOARD_NAME}" ] || BOARD_NAME="${7%_config}"
- if [ "$4" = "-" ] ; then
- board=${BOARD_NAME}
- else
- board="$4"
+ if [ $# -gt 5 ]; then
+ if [ "$6" = "-" ] ; then
+ board=${BOARD_NAME}
+ else
+ board="$6"
+ fi
fi
[ $# -gt 4 ] && [ "$5" != "-" ] && vendor="$5"
- [ $# -gt 6 ] && [ "$7" != "-" ] && {
- tmp="${7%:*}"
+ [ $# -gt 6 ] && [ "$8" != "-" ] && {
+ tmp="${8%:*}"
if [ "$tmp" ] ; then
CONFIG_NAME="$tmp"
fi
}
# Assign board directory to BOARDIR variable
- if [ -z "${vendor}" ] ; then
+ if [ "${vendor}" == "-" ] ; then
BOARDDIR=${board}
else
BOARDDIR=${vendor}/${board}
fi
- echo "${CONFIG_NAME}:${BOARDDIR}"
+ echo "${CONFIG_NAME}:${BOARDDIR}:${BOARD_NAME}"
}
get_target_maintainers() {
- local name=`echo $1 | cut -d : -f 1`
+ local name=`echo $1 | cut -d : -f 3`
- if ! grep -qsi "[[:blank:]]${name}[[:blank:]]" MAINTAINERS ; then
+ local line=`awk -F '\ +' '\$7 == "'"$target"'" { print \$0 }' boards.cfg`
+ if [ -z "${line}" ]; then
echo ""
return ;
fi
- local line=`tac MAINTAINERS | grep -ni "[[:blank:]]${name}[[:blank:]]" | cut -d : -f 1`
- local mail=`tac MAINTAINERS | tail -n +${line} | \
- sed -n ":start /.*@.*/ { b mail } ; n ; b start ; :mail /.*@.*/ { p ; n ; b mail } ; q" | \
- sed "s/^.*<//;s/>.*$//"`
- echo "$mail"
+ local mails=`echo ${line} | cut -d ' ' -f 9- | sed -e 's/[^<]*<//' -e 's/>.*</ /' -e 's/>[^>]*$//'`
+ [ "$mails" == "-" ] && mails=""
+ echo "$mails"
}
get_target_arch() {
VERSION = 2013
PATCHLEVEL = 10
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
+ALL-$(CONFIG_SPL_FRAMEWORK) += $(obj)u-boot.img
ALL-$(CONFIG_TPL) += $(obj)tpl/u-boot-tpl.bin
ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
ifneq ($(CONFIG_SPL_TARGET),)
sinclude $(obj).boards.depend
$(obj).boards.depend: boards.cfg
- @awk '(NF && $$1 !~ /^#/) { print $$1 ": " $$1 "_config; $$(MAKE)" }' $< > $@
+ @awk '(NF && $$1 !~ /^#/) { print $$7 ": " $$7 "_config; $$(MAKE) -d" }' $< > $@
#
# Functions to generate common board directory names
$(obj)tools/gdb/{astest,gdbcont,gdbsend} \
$(obj)tools/gen_eth_addr $(obj)tools/img2srec \
$(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \
- $(obj)tools/mk{smdk5250,}spl \
+ $(obj)tools/mk{$(BOARD),}spl \
$(obj)tools/mxsboot \
$(obj)tools/ncb $(obj)tools/ubsha1 \
$(obj)tools/kernel-doc/docproc \
"working". In fact, many of them are used in production systems.
In case of problems see the CHANGELOG and CREDITS files to find out
-who contributed the specific port. The MAINTAINERS file lists board
+who contributed the specific port. The boards.cfg file lists board
maintainers.
Note: There is no CHANGELOG file in the actual U-Boot source tree;
to compress the specified memory at its best effort.
- Compression support:
+ CONFIG_GZIP
+
+ Enabled by default to support gzip compressed images.
+
CONFIG_BZIP2
If this option is set, support for bzip2 compressed
then calculate the amount of needed dynamic memory (ensuring
the appropriate CONFIG_SYS_MALLOC_LEN value).
+ CONFIG_LZO
+
+ If this option is set, support for LZO compressed images
+ is included.
+
- MII/PHY support:
CONFIG_PHY_ADDR
* For major contributions, your entry to the CREDITS file
-* When you add support for a new board, don't forget to add this
- board to the MAINTAINERS file, too.
+* When you add support for a new board, don't forget to add a
+ maintainer e-mail address to the boards.cfg file, too.
* If your patch adds new configuration options, don't forget to
document these in the README file.
--- /dev/null
+SECTION 0x0 BOOTABLE
+ TAG LAST
+ LOAD 0x0 spl/u-boot-spl.bin
+ CALL 0x14 0x0
+ LOAD 0x40000100 u-boot.bin
+ CALL 0x40000100 0x0
--- /dev/null
+SECTION 0x0 BOOTABLE
+ TAG LAST
+ LOAD 0x0 spl/u-boot-spl.bin
+ LOAD IVT 0x8000 0x14
+ CALL HAB 0x8000 0x0
+ LOAD 0x40000100 u-boot.bin
+ LOAD IVT 0x8000 0x40000100
+ CALL HAB 0x8000 0x0
CLKCTRL_CLKSEQ_BYPASS_CPU);
}
-static void mxs_power_clear_auto_restart(void)
+static void mxs_power_set_auto_restart(void)
{
struct mxs_rtc_regs *rtc_regs =
(struct mxs_rtc_regs *)MXS_RTC_BASE;
while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
;
- /*
- * Due to the hardware design bug of mx28 EVK-A
- * we need to set the AUTO_RESTART bit.
- */
+ /* Do nothing if flag already set */
if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
return;
mxs_ungate_power();
mxs_power_clock2xtal();
- mxs_power_clear_auto_restart();
+ mxs_power_set_auto_restart();
mxs_power_set_linreg();
mxs_power_setup_5v_detect();
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_EMAC);
}
+
+void at91_gmac_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */
+ at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */
+ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */
+ at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */
+ at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */
+ at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */
+ at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */
+ at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */
+ at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */
+ at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */
+
+ at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */
+ at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */
+
+ at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */
+ at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */
+ at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_GMAC);
+}
#endif
#ifdef CONFIG_LCD
MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
}
-void enable_usboh3_clk(unsigned char enable)
+void enable_usboh3_clk(bool enable)
{
unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
}
#if defined(CONFIG_MX51)
-void enable_usb_phy1_clk(unsigned char enable)
+void enable_usb_phy1_clk(bool enable)
{
unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
MXC_CCM_CCGR2_USB_PHY(cg));
}
-void enable_usb_phy2_clk(unsigned char enable)
+void enable_usb_phy2_clk(bool enable)
{
/* i.MX51 has a single USB PHY clock, so do nothing here. */
}
#elif defined(CONFIG_MX53)
-void enable_usb_phy1_clk(unsigned char enable)
+void enable_usb_phy1_clk(bool enable)
{
unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
MXC_CCM_CCGR4_USB_PHY1(cg));
}
-void enable_usb_phy2_clk(unsigned char enable)
+void enable_usb_phy2_clk(bool enable)
{
unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
LIB = $(obj)lib$(SOC).o
-COBJS = soc.o clock.o
+COBJS-y = soc.o clock.o
+COBJS-$(CONFIG_SECURE_BOOT) += hab.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
all: $(obj).depend $(LIB)
--- /dev/null
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hab.h>
+
+/* -------- start of HAB API updates ------------*/
+#define hab_rvt_report_event ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)
+#define hab_rvt_report_status ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)
+#define hab_rvt_authenticate_image \
+ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)
+#define hab_rvt_entry ((hab_rvt_entry_t *)HAB_RVT_ENTRY)
+#define hab_rvt_exit ((hab_rvt_exit_t *)HAB_RVT_EXIT)
+#define hab_rvt_clock_init HAB_RVT_CLOCK_INIT
+
+bool is_hab_enabled(void)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[0];
+ struct fuse_bank0_regs *fuse =
+ (struct fuse_bank0_regs *)bank->fuse_regs;
+ uint32_t reg = readl(&fuse->cfg5);
+
+ return (reg & 0x2) == 0x2;
+}
+
+void display_event(uint8_t *event_data, size_t bytes)
+{
+ uint32_t i;
+
+ if (!(event_data && bytes > 0))
+ return;
+
+ for (i = 0; i < bytes; i++) {
+ if (i == 0)
+ printf("\t0x%02x", event_data[i]);
+ else if ((i % 8) == 0)
+ printf("\n\t0x%02x", event_data[i]);
+ else
+ printf(" 0x%02x", event_data[i]);
+ }
+}
+
+int get_hab_status(void)
+{
+ uint32_t index = 0; /* Loop index */
+ uint8_t event_data[128]; /* Event data buffer */
+ size_t bytes = sizeof(event_data); /* Event size in bytes */
+ enum hab_config config = 0;
+ enum hab_state state = 0;
+
+ if (is_hab_enabled())
+ puts("\nSecure boot enabled\n");
+ else
+ puts("\nSecure boot disabled\n");
+
+ /* Check HAB status */
+ if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) {
+ printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
+ config, state);
+
+ /* Display HAB Error events */
+ while (hab_rvt_report_event(HAB_FAILURE, index, event_data,
+ &bytes) == HAB_SUCCESS) {
+ puts("\n");
+ printf("--------- HAB Event %d -----------------\n",
+ index + 1);
+ puts("event data:\n");
+ display_event(event_data, bytes);
+ puts("\n");
+ bytes = sizeof(event_data);
+ index++;
+ }
+ }
+ /* Display message if no HAB events are found */
+ else {
+ printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
+ config, state);
+ puts("No HAB Events Found!\n\n");
+ }
+ return 0;
+}
+
+int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if ((argc != 1)) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ get_hab_status();
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
+ "display HAB status",
+ ""
+ );
void s_init(void)
{
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ int is_6q = is_cpu_type(MXC_CPU_MX6Q);
+ u32 mask480;
+ u32 mask528;
+
+ /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
+ * to make sure PFD is working right, otherwise, PFDs may
+ * not output clock after reset, MX6DL and MX6SL have added 396M pfd
+ * workaround in ROM code, as bus clock need it
+ */
+
+ mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
+ ANATOP_PFD_CLKGATE_MASK(1) |
+ ANATOP_PFD_CLKGATE_MASK(2) |
+ ANATOP_PFD_CLKGATE_MASK(3);
+ mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
+ ANATOP_PFD_CLKGATE_MASK(1) |
+ ANATOP_PFD_CLKGATE_MASK(3);
+
+ /*
+ * Don't reset PFD2 on DL/S
+ */
+ if (is_6q)
+ mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
+ writel(mask480, &anatop->pfd_480_set);
+ writel(mask528, &anatop->pfd_528_set);
+ writel(mask480, &anatop->pfd_480_clr);
+ writel(mask528, &anatop->pfd_528_clr);
}
#ifdef CONFIG_IMX_HDMI
* if running from flash, jump to small relocated code
* area in SRAM.
*/
- f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
- SRAM_VECT_CODE);
+ f_lock_pll = (void *) (SRAM_CLK_CODE);
p0 = readl(&prcm_base->clken_pll);
sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
* if running from flash, jump to small relocated code
* area in SRAM.
*/
- f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
- SRAM_VECT_CODE);
+ f_lock_pll = (void *) (SRAM_CLK_CODE);
p0 = readl(&prcm_base->clken_pll);
sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
*************************************************************************/
ENTRY(cpy_clk_code)
/* Copy DPLL code into SRAM */
- adr r0, go_to_speed /* get addr of clock setting code */
- mov r2, #384 /* r2 size to copy (div by 32 bytes) */
- mov r1, r1 /* r1 <- dest address (passed in) */
- add r2, r2, r0 /* r2 <- source end address */
+ adr r0, go_to_speed /* copy from start of go_to_speed... */
+ adr r2, lowlevel_init /* ... up to start of low_level_init */
next2:
ldmia r0!, {r3 - r10} /* copy from source address [r0] */
stmia r1!, {r3 - r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
- bne next2
+ blo next2
mov pc, lr /* back to caller */
ENDPROC(cpy_clk_code)
/*
* dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
* OMAP4430 OPP_TURBO frequency
+ * OMAP4470 OPP_NOM frequency
*/
static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
};
/* OMAP4460 OPP_NOM frequency */
+/* OMAP4470 OPP_NOM (Low Power) frequency */
static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
.ddr = NULL
};
+struct dplls omap4470_dplls = {
+ .mpu = mpu_dpll_params_1600mhz,
+ .core = core_dpll_params_1600mhz,
+ .per = per_dpll_params_1536mhz,
+ .iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
struct pmic_data twl6030_4430es1 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
.step = 12660, /* 12.66 mV represented in uV */
.pmic_write = omap_vc_bypass_send_value,
};
+/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
struct pmic_data twl6030 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
.step = 12660, /* 12.66 mV represented in uV */
.mm.pmic = &twl6030,
};
+struct vcores_data omap4470_volts = {
+ .mpu.value = 1200,
+ .mpu.addr = SMPS_REG_ADDR_SMPS1,
+ .mpu.pmic = &twl6030,
+
+ .core.value = 1126,
+ .core.addr = SMPS_REG_ADDR_SMPS1,
+ .core.pmic = &twl6030,
+
+ .mm.value = 1137,
+ .mm.addr = SMPS_REG_ADDR_SMPS1,
+ .mm.pmic = &twl6030,
+};
+
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
*omap_vcores = &omap4460_volts;
break;
+ case OMAP4470_ES1_0:
+ *dplls_data = &omap4470_dplls;
+ *omap_vcores = &omap4470_volts;
+ break;
+
default:
printf("\n INVALID OMAP REVISION ");
}
break;
case MIDR_CORTEX_A9_R2P10:
switch (readl(CONTROL_ID_CODE)) {
+ case OMAP4470_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = OMAP4470_ES1_0;
+ break;
case OMAP4460_CONTROL_ID_CODE_ES1_1:
*omap_si_rev = OMAP4460_ES1_1;
break;
.emif_ddr_phy_ctlr_1 = 0x049ff418
};
+const struct emif_regs emif_regs_elpida_400_mhz_1cs = {
+ .sdram_config_init = 0x80800eb2,
+ .sdram_config = 0x80801ab2,
+ .ref_ctrl = 0x00000618,
+ .sdram_tim1 = 0x10eb0662,
+ .sdram_tim2 = 0x20370dd2,
+ .sdram_tim3 = 0x00b1c33f,
+ .read_idle_ctrl = 0x000501ff,
+ .zq_config = 0x500b3215,
+ .temp_alert_config = 0x58016893,
+ .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
+ .emif_ddr_phy_ctlr_1 = 0x049ff418
+};
+
const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
.sdram_config_init = 0x80000eb9,
.sdram_config = 0x80001ab9,
*regs = &emif_regs_elpida_380_mhz_1cs;
else if (omap4_rev == OMAP4430_ES2_0)
*regs = &emif_regs_elpida_200_mhz_2cs;
- else
+ else if (omap4_rev < OMAP4470_ES1_0)
*regs = &emif_regs_elpida_400_mhz_2cs;
+ else
+ *regs = &emif_regs_elpida_400_mhz_1cs;
}
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
__attribute__((weak, alias("emif_get_reg_dump_sdp")));
.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
};
+static const struct lpddr2_device_details elpida_4G_S4_details = {
+ .type = LPDDR2_TYPE_S4,
+ .density = LPDDR2_DENSITY_4Gb,
+ .io_width = LPDDR2_IO_WIDTH_32,
+ .manufacturer = LPDDR2_MANUFACTURER_ELPIDA
+};
+
struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
struct lpddr2_device_details *lpddr2_dev_details)
{
u32 omap_rev = omap_revision();
/* EMIF1 & EMIF2 have identical configuration */
- if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) {
- /* Nothing connected on CS1 for ES1.0 */
+ if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
+ && (cs == CS1)) {
+ /* Nothing connected on CS1 for 4430/4470 ES1.0 */
return NULL;
- } else {
- /* In all other cases Elpida 2G device */
+ } else if (omap_rev < OMAP4470_ES1_0) {
+ /* In all other 4430/4460 cases Elpida 2G device */
*lpddr2_dev_details = elpida_2G_S4_details;
- return lpddr2_dev_details;
+ } else {
+ /* 4470: 4G device */
+ *lpddr2_dev_details = elpida_4G_S4_details;
}
+ return lpddr2_dev_details;
}
struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
/* Identical devices on EMIF1 & EMIF2 */
*cs0_device_timings = &elpida_2G_S4_timings;
- if (omap_rev == OMAP4430_ES1_0)
+ if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
*cs1_device_timings = NULL;
else
*cs1_device_timings = &elpida_2G_S4_timings;
LIB = $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
-COBJS-y := misc.o timer.o
+COBJS-y := misc.o timer.o reset_manager.o
COBJS-$(CONFIG_SPL_BUILD) += spl.o
COBJS := $(COBJS-y)
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/reset_manager.h>
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
-
-/*
- * Write the reset manager register to cause reset
- */
-void reset_cpu(ulong addr)
-{
- /* request a warm reset */
- writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl);
- /*
- * infinite loop here as watchdog will trigger and reset
- * the processor
- */
- while (1)
- ;
-}
-
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
- writel(0, &reset_manager_base->per_mod_reset);
-}
-
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
--- /dev/null
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+ (void *)SOCFPGA_RSTMGR_ADDRESS;
+
+/*
+ * Write the reset manager register to cause reset
+ */
+void reset_cpu(ulong addr)
+{
+ /* request a warm reset */
+ writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
+ &reset_manager_base->ctrl);
+ /*
+ * infinite loop here as watchdog will trigger and reset
+ * the processor
+ */
+ while (1)
+ ;
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+ writel(0, &reset_manager_base->per_mod_reset);
+}
COBJS-y := timer.o
COBJS-y += cpu.o
+COBJS-y += ddrc.o
COBJS-y += slcr.o
COBJS := $(COBJS-y)
--- /dev/null
+/*
+ * Copyright (C) 2012 - 2013 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2012 - 2013 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Control regsiter bitfield definitions */
+#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK 0xC
+#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT 2
+#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT 1
+
+/* ECC scrub regsiter definitions */
+#define ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK 0x7
+#define ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED 0x4
+
+void zynq_ddrc_init(void)
+{
+ u32 width, ecctype;
+
+ width = readl(&ddrc_base->ddrc_ctrl);
+ width = (width & ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK) >>
+ ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT;
+ ecctype = (readl(&ddrc_base->ecc_scrub) &
+ ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK);
+
+ /* ECC is enabled when memory is in 16bit mode and it is enabled */
+ if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) &&
+ (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) {
+ puts("Memory: ECC enabled\n");
+ /*
+ * Clear the first 1MB because it is not initialized from
+ * first stage bootloader. To get ECC to work all memory has
+ * been initialized by writing any value.
+ */
+ memset(0, 0, 1 * 1024 * 1024);
+ } else {
+ puts("Memory: ECC disabled\n");
+ }
+
+ if (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)
+ gd->ram_size /= 2;
+}
/* Configure GEM_RCLK_CTRL */
writel(rclk, &slcr_base->gem0_rclk_ctrl);
}
-
+ udelay(100000);
out:
zynq_slcr_lock();
}
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
+ /DISCARD/ : { *(.ARM.exidx*) }
+ /DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
}
#define PRM_RSTCTRL_RESET 0x01
#define PRM_RSTST_WARM_RESET_MASK 0x232
+/*
+ * Watchdog:
+ * Using the prescaler, the OMAP watchdog could go for many
+ * months before firing. These limits work without scaling,
+ * with the 60 second default assumed by most tools and docs.
+ */
+#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */
+#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */
+#define TIMER_MARGIN_MIN 1
+
+#define PTV 0 /* prescale */
+#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
+#define WDT_WWPS_PEND_WCLR BIT(0)
+#define WDT_WWPS_PEND_WLDR BIT(2)
+#define WDT_WWPS_PEND_WTGR BIT(3)
+#define WDT_WWPS_PEND_WSPR BIT(4)
+
+#define WDT_WCLR_PRE BIT(5)
+#define WDT_WCLR_PTV_OFF 2
+
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct gpmc_cs {
unsigned int dcan1clkctrl; /* offset 0xC4 */
unsigned int resv6[2];
unsigned int emiffwclkctrl; /* offset 0xD0 */
- unsigned int resv7[2];
+ unsigned int epwmss0clkctrl; /* offset 0xD4 */
+ unsigned int epwmss2clkctrl; /* offset 0xD8 */
unsigned int l3instrclkctrl; /* offset 0xDC */
unsigned int l3clkctrl; /* Offset 0xE0 */
unsigned int resv8[4];
unsigned int l4hsclkctrl; /* offset 0x120 */
unsigned int resv10[8];
unsigned int cpswclkstctrl; /* offset 0x144 */
+ unsigned int lcdcclkstctrl; /* offset 0x148 */
};
#else
/* Encapsulating core pll registers */
struct cm_dpll {
unsigned int resv1[2];
unsigned int clktimer2clk; /* offset 0x08 */
+ unsigned int resv2[10];
+ unsigned int clklcdcpixelclk; /* offset 0x34 */
};
/* Control Module RTC registers */
unsigned int resv4[4];
unsigned int miisel; /* offset 0x50 */
};
+
+/* gmii_sel register defines */
+#define GMII1_SEL_MII 0x0
+#define GMII1_SEL_RMII 0x1
+#define GMII1_SEL_RGMII 0x2
+#define GMII2_SEL_MII 0x0
+#define GMII2_SEL_RMII 0x4
+#define GMII2_SEL_RGMII 0x8
+#define RGMII1_IDMODE BIT(4)
+#define RGMII2_IDMODE BIT(5)
+#define RMII1_IO_CLK_EN BIT(6)
+#define RMII2_IO_CLK_EN BIT(7)
+
+#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
+#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
+#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
+#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
+#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
+
+/* PWMSS */
+struct pwmss_regs {
+ unsigned int idver;
+ unsigned int sysconfig;
+ unsigned int clkconfig;
+ unsigned int clkstatus;
+};
+#define ECAP_CLK_EN BIT(0)
+#define ECAP_CLK_STOP_REQ BIT(1)
+
+struct pwmss_ecap_regs {
+ unsigned int tsctr;
+ unsigned int ctrphs;
+ unsigned int cap1;
+ unsigned int cap2;
+ unsigned int cap3;
+ unsigned int cap4;
+ unsigned int resv1[4];
+ unsigned short ecctl1;
+ unsigned short ecctl2;
+};
+
+/* Capture Control register 2 */
+#define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
+#define ECTRL2_MDSL_ECAP BIT(9)
+#define ECTRL2_CTRSTP_FREERUN BIT(4)
+#define ECTRL2_PLSL_LOW BIT(10)
+#define ECTRL2_SYNC_EN BIT(5)
+
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
#define USB0_OTG_BASE 0x47401000
#define USB1_OTG_BASE 0x47401800
+/* LCD Controller */
+#define LCD_CNTL_BASE 0x4830E000
+
+/* PWMSS */
+#define PWMSS0_BASE 0x48300000
+#define AM33XX_ECAP0_BASE 0x48300100
+
#endif /* __AM33XX_HARDWARE_AM33XX_H */
#ifdef CONFIG_AM33XX
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END 0x40310000
-#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000
+#define SRAM_SCRATCH_SPACE_ADDR 0x4030B800
#elif defined(CONFIG_TI81XX)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000
#define AT91_COMMON_H
void at91_can_hw_init(void);
+void at91_gmac_hw_init(void);
void at91_macb_hw_init(void);
void at91_mci_hw_init(void);
void at91_serial0_hw_init(void);
#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
#define ATMEL_ID_UHP ATMEL_ID_UHPHS
+/*
+ * PMECC table in ROM
+ */
+#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000
+#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000
+
/*
* at91sam9x5 specific prototypes
*/
*/
#define ATMEL_PMECC_INDEX_OFFSET_512 0x10000
#define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000
-#define ATMEL_PMECC_ALPHA_OFFSET_512 0x10000
-#define ATMEL_PMECC_ALPHA_OFFSET_1024 0x18000
/*
* SAMA5D3 specific prototypes
#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x60C)
#else
struct at91_cs {
- u32 reserved[96];
u32 setup; /* 0x600 SMC Setup Register */
u32 pulse; /* 0x604 SMC Pulse Register */
u32 cycle; /* 0x608 SMC Cycle Register */
};
struct at91_smc {
+ u32 reserved[384];
struct at91_cs cs[4];
};
#endif /* __ASSEMBLY__ */
return EXYNOS5_GPIO_PART2_MAX;
} else if (cpu_is_exynos4()) {
- if (nr < EXYNOS4_GPIO_PART1_MAX)
- return 0;
- else
- return EXYNOS4_GPIO_PART1_MAX;
+ if (proid_is_exynos4412()) {
+ if (nr < EXYNOS4X12_GPIO_PART1_MAX)
+ return 0;
+ else if (nr < EXYNOS4X12_GPIO_PART2_MAX)
+ return EXYNOS4X12_GPIO_PART1_MAX;
+ else
+ return EXYNOS4X12_GPIO_PART2_MAX;
+ } else {
+ if (nr < EXYNOS4_GPIO_PART1_MAX)
+ return 0;
+ else
+ return EXYNOS4_GPIO_PART1_MAX;
+ }
}
return 0;
#ifndef __ASM_ARCH_MMC_H_
#define __ASM_ARCH_MMC_H_
+#define S5P_MMC_DEV_OFFSET 0x10000
+
#define SDHCI_CONTROL2 0x80
#define SDHCI_CONTROL3 0x84
#define SDHCI_CONTROL4 0x8C
static inline unsigned int s5p_mmc_init(int index, int bus_width)
{
- unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
+ unsigned int base = samsung_get_base_mmc() +
+ (S5P_MMC_DEV_OFFSET * index);
+
return s5p_sdhci_init(base, index, bus_width);
}
#endif
unsigned int mxc_get_clock(enum mxc_clock clk);
int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
void set_usb_phy_clk(void);
-void enable_usb_phy1_clk(unsigned char enable);
-void enable_usb_phy2_clk(unsigned char enable);
+void enable_usb_phy1_clk(bool enable);
+void enable_usb_phy2_clk(bool enable);
void set_usboh3_clk(void);
-void enable_usboh3_clk(unsigned char enable);
+void enable_usboh3_clk(bool enable);
void mxc_set_sata_internal_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
void enable_nfc_clk(unsigned char enable);
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+*/
+
+#ifndef __SECURE_MX6Q_H__
+#define __SECURE_MX6Q_H__
+
+#include <linux/types.h>
+
+/* -------- start of HAB API updates ------------*/
+/* The following are taken from HAB4 SIS */
+
+/* Status definitions */
+enum hab_status {
+ HAB_STS_ANY = 0x00,
+ HAB_FAILURE = 0x33,
+ HAB_WARNING = 0x69,
+ HAB_SUCCESS = 0xf0
+};
+
+/* Security Configuration definitions */
+enum hab_config {
+ HAB_CFG_RETURN = 0x33, /**< Field Return IC */
+ HAB_CFG_OPEN = 0xf0, /**< Non-secure IC */
+ HAB_CFG_CLOSED = 0xcc /**< Secure IC */
+};
+
+/* State definitions */
+enum hab_state {
+ HAB_STATE_INITIAL = 0x33, /**< Initialising state (transitory) */
+ HAB_STATE_CHECK = 0x55, /**< Check state (non-secure) */
+ HAB_STATE_NONSECURE = 0x66, /**< Non-secure state */
+ HAB_STATE_TRUSTED = 0x99, /**< Trusted state */
+ HAB_STATE_SECURE = 0xaa, /**< Secure state */
+ HAB_STATE_FAIL_SOFT = 0xcc, /**< Soft fail state */
+ HAB_STATE_FAIL_HARD = 0xff, /**< Hard fail state (terminal) */
+ HAB_STATE_NONE = 0xf0, /**< No security state machine */
+ HAB_STATE_MAX
+};
+
+/*Function prototype description*/
+typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
+ uint8_t* , size_t*);
+typedef enum hab_status hab_rvt_report_status_t(enum hab_config *,
+ enum hab_state *);
+typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*);
+typedef enum hab_status hab_rvt_entry_t(void);
+typedef enum hab_status hab_rvt_exit_t(void);
+typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
+ void **, size_t *, hab_loader_callback_f_t);
+typedef void hapi_clock_init_t(void);
+
+#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4)
+#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8)
+#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4)
+#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098)
+#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C)
+#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D)
+
+#define HAB_CID_ROM 0 /**< ROM Caller ID */
+#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
+/* ----------- end of HAB API updates ------------*/
+
+#endif
u32 uid_low;
u32 rsvd1[3];
u32 uid_high;
- u32 rsvd2[0x17];
+ u32 rsvd2[3];
+ u32 rsvd3[4];
+ u32 rsvd4[4];
+ u32 rsvd5[4];
+ u32 cfg5;
+ u32 rsvd6[3];
+ u32 rsvd7[4];
};
struct fuse_bank4_regs {
u32 digprog_sololite; /* 0x280 */
};
-#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
-#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
-#define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
-#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
-#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
-#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
-#define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
-#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
-#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
-#define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
-#define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
-#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
-#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
-#define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT)
-#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
-#define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT)
-#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
+#define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
+#define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
+#define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
+#define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
+#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
+#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
struct iomuxc_base_regs {
u32 gpr[14]; /* 0x000 */
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
u32 get_cpu_rev(void);
+
+/* returns MXC_CPU_ value */
+#define cpu_type(rev) (((rev) >> 12)&0xff)
+
+/* use with MXC_CPU_ constants */
+#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu)
+
const char *get_imx_type(u32 imxtype);
unsigned imx_ddr_size(void);
--- /dev/null
+/*
+ * Freescale MXS UARTAPP Register Definitions
+ *
+ * Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com>
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM___MXS_UARTAPP_H
+#define __ARCH_ARM___MXS_UARTAPP_H
+
+#include <asm/imx-common/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mxs_uartapp_regs {
+ mxs_reg_32(hw_uartapp_ctrl0)
+ mxs_reg_32(hw_uartapp_ctrl1)
+ mxs_reg_32(hw_uartapp_ctrl2)
+ mxs_reg_32(hw_uartapp_linectrl)
+ mxs_reg_32(hw_uartapp_linectrl2)
+ mxs_reg_32(hw_uartapp_intr)
+ mxs_reg_32(hw_uartapp_data)
+ mxs_reg_32(hw_uartapp_stat)
+ mxs_reg_32(hw_uartapp_debug)
+ mxs_reg_32(hw_uartapp_version)
+ mxs_reg_32(hw_uartapp_autobaud)
+};
+#endif
+
+#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31)
+#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30)
+#define UARTAPP_CTRL0_RUN_MASK (1 << 29)
+#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28)
+#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27)
+#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16
+#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16)
+#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0
+#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF
+
+#define UARTAPP_CTRL1_RUN_MASK (1 << 28)
+
+#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0
+#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF
+
+#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31)
+#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30)
+#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29)
+#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28)
+#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27)
+#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26)
+#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25)
+#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24)
+#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20
+#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20)
+
+#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20)
+#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16
+#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16)
+#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15)
+#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14)
+#define UARTAPP_CTRL2_OUT2_MASK (1 << 13)
+#define UARTAPP_CTRL2_OUT1_MASK (1 << 12)
+#define UARTAPP_CTRL2_RTS_MASK (1 << 11)
+#define UARTAPP_CTRL2_DTR_MASK (1 << 10)
+#define UARTAPP_CTRL2_RXE_MASK (1 << 9)
+#define UARTAPP_CTRL2_TXE_MASK (1 << 8)
+#define UARTAPP_CTRL2_LBE_MASK (1 << 7)
+#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6)
+
+#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2)
+#define UARTAPP_CTRL2_SIREN_MASK (1 << 1)
+#define UARTAPP_CTRL2_UARTEN_MASK 0x01
+
+#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16
+#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16)
+#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6
+
+#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8
+#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8)
+#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
+
+#define UARTAPP_LINECTRL_SPS_MASK (1 << 7)
+#define UARTAPP_LINECTRL_WLEN_OFFSET 5
+#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5)
+#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5)
+#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5)
+#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5)
+#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5)
+
+#define UARTAPP_LINECTRL_FEN_MASK (1 << 4)
+#define UARTAPP_LINECTRL_STP2_MASK (1 << 3)
+#define UARTAPP_LINECTRL_EPS_MASK (1 << 2)
+#define UARTAPP_LINECTRL_PEN_MASK (1 << 1)
+#define UARTAPP_LINECTRL_BRK_MASK 1
+
+#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16
+#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16)
+#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6
+
+#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8
+#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8)
+#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
+
+#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7)
+#define UARTAPP_LINECTRL2_WLEN_OFFSET 5
+#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5)
+#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5)
+#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5)
+#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5)
+#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5)
+
+#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4)
+#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3)
+#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2)
+#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1)
+
+#define UARTAPP_INTR_ABDIEN_MASK (1 << 27)
+#define UARTAPP_INTR_OEIEN_MASK (1 << 26)
+#define UARTAPP_INTR_BEIEN_MASK (1 << 25)
+#define UARTAPP_INTR_PEIEN_MASK (1 << 24)
+#define UARTAPP_INTR_FEIEN_MASK (1 << 23)
+#define UARTAPP_INTR_RTIEN_MASK (1 << 22)
+#define UARTAPP_INTR_TXIEN_MASK (1 << 21)
+#define UARTAPP_INTR_RXIEN_MASK (1 << 20)
+#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19)
+#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18)
+#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17)
+#define UARTAPP_INTR_RIMIEN_MASK (1 << 16)
+
+#define UARTAPP_INTR_ABDIS_MASK (1 << 11)
+#define UARTAPP_INTR_OEIS_MASK (1 << 10)
+#define UARTAPP_INTR_BEIS_MASK (1 << 9)
+#define UARTAPP_INTR_PEIS_MASK (1 << 8)
+#define UARTAPP_INTR_FEIS_MASK (1 << 7)
+#define UARTAPP_INTR_RTIS_MASK (1 << 6)
+#define UARTAPP_INTR_TXIS_MASK (1 << 5)
+#define UARTAPP_INTR_RXIS_MASK (1 << 4)
+#define UARTAPP_INTR_DSRMIS_MASK (1 << 3)
+#define UARTAPP_INTR_DCDMIS_MASK (1 << 2)
+#define UARTAPP_INTR_CTSMIS_MASK (1 << 1)
+#define UARTAPP_INTR_RIMIS_MASK 0x1
+
+#define UARTAPP_DATA_DATA_OFFSET 0
+#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF
+#define UARTAPP_STAT_PRESENT_MASK (1 << 31)
+#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31)
+#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31)
+
+#define UARTAPP_STAT_HISPEED_MASK (1 << 30)
+#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30)
+#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30)
+
+#define UARTAPP_STAT_BUSY_MASK (1 << 29)
+#define UARTAPP_STAT_CTS_MASK (1 << 28)
+#define UARTAPP_STAT_TXFE_MASK (1 << 27)
+#define UARTAPP_STAT_RXFF_MASK (1 << 26)
+#define UARTAPP_STAT_TXFF_MASK (1 << 25)
+#define UARTAPP_STAT_RXFE_MASK (1 << 24)
+#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20
+#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20)
+
+#define UARTAPP_STAT_OERR_MASK (1 << 19)
+#define UARTAPP_STAT_BERR_MASK (1 << 18)
+#define UARTAPP_STAT_PERR_MASK (1 << 17)
+#define UARTAPP_STAT_FERR_MASK (1 << 16)
+#define UARTAPP_STAT_RXCOUNT_OFFSET 0
+#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF
+
+#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16
+#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16)
+
+#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10
+#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10)
+
+#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5)
+#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4)
+#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3)
+#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2)
+#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1)
+#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01
+
+#define UARTAPP_VERSION_MAJOR_OFFSET 24
+#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24)
+
+#define UARTAPP_VERSION_MINOR_OFFSET 16
+#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16)
+
+#define UARTAPP_VERSION_STEP_OFFSET 0
+#define UARTAPP_VERSION_STEP_MASK 0xFFFF
+
+#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24
+#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24)
+
+#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16
+#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16)
+
+#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4)
+#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3)
+#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2)
+#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1)
+#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01
+#endif /* __ARCH_ARM___UARTAPP_H */
extern dpll_param *get_36x_per_dpll_param(void);
extern dpll_param *get_36x_per2_dpll_param(void);
-extern void *_end_vect, *_start;
-
#endif
/* PRM_VC_VAL_BYPASS */
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
-/* SMPS */
+/* PMIC */
#define SMPS_I2C_SLAVE_ADDR 0x12
+/* TWL6030 SMPS */
#define SMPS_REG_ADDR_VCORE1 0x55
#define SMPS_REG_ADDR_VCORE2 0x5B
#define SMPS_REG_ADDR_VCORE3 0x61
+/* TWL6032 SMPS */
+#define SMPS_REG_ADDR_SMPS1 0x55
+#define SMPS_REG_ADDR_SMPS2 0x5B
+#define SMPS_REG_ADDR_SMPS5 0x49
#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F
#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
+#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F
/* UART */
#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
/* CM_L3INIT_USBPHY_CLKCTRL */
#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
+/* CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OPTFCLKEN_FUNC48M_CLK (1 << 15)
+#define OPTFCLKEN_HSIC480M_P2_CLK (1 << 14)
+#define OPTFCLKEN_HSIC480M_P1_CLK (1 << 13)
+#define OPTFCLKEN_HSIC60M_P2_CLK (1 << 12)
+#define OPTFCLKEN_HSIC60M_P1_CLK (1 << 11)
+#define OPTFCLKEN_UTMI_P3_CLK (1 << 10)
+#define OPTFCLKEN_UTMI_P2_CLK (1 << 9)
+#define OPTFCLKEN_UTMI_P1_CLK (1 << 8)
+#define OPTFCLKEN_HSIC480M_P3_CLK (1 << 7)
+#define OPTFCLKEN_HSIC60M_P3_CLK (1 << 6)
+
+/* CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OPTFCLKEN_USB_CH0_CLK_ENABLE (1 << 8)
+#define OPTFCLKEN_USB_CH1_CLK_ENABLE (1 << 9)
+#define OPTFCLKEN_USB_CH2_CLK_ENABLE (1 << 10)
+
/* CM_MPU_MPU_CLKCTRL */
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
--- /dev/null
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com*
+ * Author: Govindraj R <govindraj.raja@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _EHCI_H
+#define _EHCI_H
+
+#define OMAP_EHCI_BASE (OMAP54XX_L4_CORE_BASE + 0x64C00)
+#define OMAP_UHH_BASE (OMAP54XX_L4_CORE_BASE + 0x64000)
+#define OMAP_USBTLL_BASE (OMAP54XX_L4_CORE_BASE + 0x62000)
+
+/* TLL Register Set */
+#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
+#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
+#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
+#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
+#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1
+
+#define OMAP_UHH_SYSCONFIG_SOFTRESET 1
+#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2)
+#define OMAP_UHH_SYSCONFIG_NOIDLE (1 << 2)
+#define OMAP_UHH_SYSCONFIG_NOSTDBY (1 << 4)
+
+#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \
+ OMAP_UHH_SYSCONFIG_NOSTDBY)
+
+#endif /* _EHCI_H */
#define EFUSE_4 0x45145100
#endif /* __ASSEMBLY__ */
+/*
+ * In all cases, the TRM defines the RAM Memory Map for the processor
+ * and indicates the area for the downloaded image. We use all of that
+ * space for download and once up and running may use other parts of the
+ * map for our needs. We set a scratch space that is at the end of the
+ * OMAP5 download area, but within the DRA7xx download area (as it is
+ * much larger) and do not, at this time, make use of the additional
+ * space.
+ */
#ifdef CONFIG_DRA7XX
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
#endif
-#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
+#define SRAM_SCRATCH_SPACE_ADDR 0x4031E000
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000
#ifndef __ASM_ARCH_MMC_H_
#define __ASM_ARCH_MMC_H_
+#define S5P_MMC_DEV_OFFSET 0x100000
+
#define SDHCI_CONTROL2 0x80
#define SDHCI_CONTROL3 0x84
#define SDHCI_CONTROL4 0x8C
static inline unsigned int s5p_mmc_init(int index, int bus_width)
{
- unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
+ unsigned int base = samsung_get_base_mmc() +
+ (S5P_MMC_DEV_OFFSET * index);
+
return s5p_sdhci_init(base, index, bus_width);
}
#endif
void reset_deassert_peripherals_handoff(void);
struct socfpga_reset_manager {
- u32 padding1;
+ u32 status;
u32 ctrl;
- u32 padding2;
- u32 padding3;
+ u32 counts;
+ u32 padding1;
u32 mpu_mod_reset;
u32 per_mod_reset;
u32 per2_mod_reset;
u32 brg_mod_reset;
};
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
+#else
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+#endif
#endif /* _RESET_MANAGER_H_ */
#define ZYNQ_I2C_BASEADDR1 0xE0005000
#define ZYNQ_SPI_BASEADDR0 0xE0006000
#define ZYNQ_SPI_BASEADDR1 0xE0007000
+#define ZYNQ_DDRC_BASEADDR 0xF8006000
/* Reflect slcr offsets */
struct slcr_regs {
#define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
+struct ddrc_regs {
+ u32 ddrc_ctrl; /* 0x0 */
+ u32 reserved[60];
+ u32 ecc_scrub; /* 0xF4 */
+};
+#define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
+
#endif /* _ASM_ARCH_HARDWARE_H */
extern void zynq_slcr_devcfg_disable(void);
extern void zynq_slcr_devcfg_enable(void);
extern u32 zynq_slcr_get_idcode(void);
+extern void zynq_ddrc_init(void);
/* Driver extern functions */
extern int zynq_sdhci_init(u32 regbase);
/* Values of UHH_REVISION - Note: these are not given in the TRM */
#define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
#define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
+#define OMAP_USBHS_REV2_1 0x50700101 /* OMAP5 */
/* UHH Register Set */
#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
#define OMAP_P2_MODE_CLEAR (3 << 18)
#define OMAP_P2_MODE_TLL (1 << 18)
#define OMAP_P2_MODE_HSIC (3 << 18)
+#define OMAP_P3_MODE_CLEAR (3 << 20)
#define OMAP_P3_MODE_HSIC (3 << 20)
/* EHCI Register Set */
#define OMAP4430_ES2_3 0x44300230
#define OMAP4460_ES1_0 0x44600100
#define OMAP4460_ES1_1 0x44600110
+#define OMAP4470_ES1_0 0x44700100
/* omap5 */
#define OMAP5430_SILICON_ID_INVALID 0
2005 Free Software Foundation, Inc.
* SPDX-License-Identifier: GPL-2.0+
+ */
/* You have to define the following before including this file:
#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
puts("Work-around for Erratum A-005812 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
+ puts("Work-around for Erratum A005125 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
* AN2919.
*/
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
- defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
+ defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
+ defined(CONFIG_P1022)
gd->arch.i2c1_clk = sys_info.freq_systembus;
#elif defined(CONFIG_MPC8544)
/*
isync
2:
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
+ msync
+ isync
+ mfspr r3, SPRN_HDBCR0
+ oris r3, r3, 0x0080
+ mtspr SPRN_HDBCR0, r3
+#endif
+
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
/* ISBC uses L2 as stack.
}
_edata = .;
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_MPC8540)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_MPC8548)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_MPC8572)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_DDR_115
#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1010)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1012 is single core version of P1021 */
#elif defined(CONFIG_P1012)
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1013 is single core version of P1022 */
#elif defined(CONFIG_P1013)
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_FSL_SATA_ERRATUM_A001
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1014)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1020)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1021)
#define CONFIG_MAX_CPUS 2
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1022)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_FSL_SATA_ERRATUM_A001
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1023)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1025 is lower end variant of P1021 */
#elif defined(CONFIG_P1025)
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P2010 is single core version of P2020 */
#elif defined(CONFIG_P2010)
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P2020)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_BSC9132)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_FSL_ERRATUM_A005125
#else
#error Processor type not defined for this platform
# (mem base + reserved)
#
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SPL_PAD_TO := 12320
UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg
ifndef CONFIG_SPL_BUILD
ALL-y += $(obj)u-boot.ubl
+++ /dev/null
-CONFIG_SYS_TEXT_BASE = 0x73f00000
+++ /dev/null
-CONFIG_SYS_TEXT_BASE = 0x26f00000
#include <lcd.h>
#include <atmel_lcdc.h>
#include <atmel_mci.h>
+#include <micrel.h>
#include <net.h>
#include <netdev.h>
#ifdef CONFIG_MACB
if (has_emac())
at91_macb_hw_init();
+ if (has_gmac())
+ at91_gmac_hw_init();
#endif
#ifdef CONFIG_LCD
if (has_lcdc())
return 0;
}
+int board_phy_config(struct phy_device *phydev)
+{
+ /* rx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222);
+ /* tx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222);
+ /* rx/tx clock delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4);
+
+ return 0;
+}
+
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
if (has_emac())
rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+ if (has_gmac())
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
#endif
return rc;
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
int reg;
reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
writel(reg, &mxc_ccm->CCGR3);
- /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
- writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
- writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
-
/* set LDB0, LDB1 clk select to 011/011 */
reg = readl(&mxc_ccm->cs2cdr);
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
writel(reg, &iomux->gpr[2]);
reg = readl(&iomux->gpr[3]);
- reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
+ reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
+ |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
writel(reg, &iomux->gpr[3]);
1. Boot source, boot from SD card
---------------------------------
-This version of u-boot works only on the SD card. By default, the
-Congatec board can boot only from the SPI-NOR.
+By default, the Congatec board can boot only from the SPI-NOR.
But, with the u-boot version provided with the board you can write boot
registers to force the board to reboot and boot from the SD slot. If
"bmode" command is not available from your pre-installed u-boot, these
env_relocate();
#endif
- i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#ifdef CONFIG_SYS_I2C
+ i2c_init_all();
+#else
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
gd->ram_size = initdram(0);
#ifdef CONFIG_SPL_NAND_BOOT
DECLARE_GLOBAL_DATA_PTR;
-/* MII mode defines */
-#define RMII_MODE_ENABLE 0x4D
-
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
#ifdef CONFIG_SPL_BUILD
eth_setenv_enetaddr("ethaddr", mac_addr);
}
- writel(RMII_MODE_ENABLE, &cdev->miisel);
+ writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
+ &cdev->miisel);
rv = cpsw_register(&cpsw_data);
if (rv < 0)
*/
board_early_init_f();
+ /* enable the LSB transmitter */
+ gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
+
/*
* Clear resets
*/
DECLARE_GLOBAL_DATA_PTR;
/* MII mode defines */
-#define MII_MODE_ENABLE 0x0
-#define RGMII_MODE_ENABLE 0xA
#define RMII_RGMII2_MODE_ENABLE 0x49
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
--- /dev/null
+#
+# Copyright (C) 2013 Samsung Electronics
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS += arndale_spl.o
+
+ifndef CONFIG_SPL_BUILD
+COBJS += arndale.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+ALL := $(obj).depend $(LIB)
+
+all: $(ALL)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/power.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+ return 0;
+}
+
+int dram_init(void)
+{
+ int i;
+ u32 addr;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+ }
+ return 0;
+}
+
+int power_init_board(void)
+{
+ set_ps_hold_ctrl();
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ int i;
+ u32 addr, size;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+
+ gd->bd->bi_dram[i].start = addr;
+ gd->bd->bi_dram[i].size = size;
+ }
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+ /* dwmmc initializattion for available channels */
+ ret = exynos_dwmmc_init(gd->fdt_blob);
+ if (ret)
+ debug("dwmmc init failed\n");
+
+ return ret;
+}
+#endif
+
+static int board_uart_init(void)
+{
+ int err = 0, uart_id;
+
+ for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+ err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("UART%d not configured\n",
+ (uart_id - PERIPH_ID_UART0));
+ return err;
+ }
+ }
+ return err;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ int err;
+
+ err = board_uart_init();
+ if (err) {
+ debug("UART init failed\n");
+ return err;
+ }
+ return err;
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf("\nBoard: Arndale\n");
+
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/spl.h>
+
+#define SIGNATURE 0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+ __attribute__((section(".machine_param"))) = {
+ .signature = SIGNATURE,
+ .version = 1,
+ .params = "vmubfasirM",
+ .size = sizeof(machine_param),
+
+ .mem_iv_size = 0x1f,
+ .mem_type = DDR_MODE_DDR3,
+
+ /*
+ * Set uboot_size to 0x100000 bytes.
+ *
+ * This is an overly conservative value chosen to accommodate all
+ * possible U-Boot image. You are advised to set this value to a
+ * smaller realistic size via scripts that modifies the .machine_param
+ * section of output U-Boot image.
+ */
+ .uboot_size = 0x100000,
+
+ .boot_source = BOOT_MODE_OM,
+ .frequency_mhz = 800,
+ .arm_freq_mhz = 1000,
+ .serial_base = 0x12c30000,
+ .i2c_base = 0x12c60000,
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+ if (machine_param.signature != SIGNATURE) {
+ /* Will hang if SIGNATURE dont match */
+ while (1)
+ ;
+ }
+
+ return &machine_param;
+}
--- /dev/null
+/*
+ * SAMSUNG Arndale board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+/dts-v1/;
+#include "exynos5250.dtsi"
+
+/ {
+ model = "SAMSUNG Arndale board based on EXYNOS5250";
+ compatible = "samsung,arndale", "samsung,exynos5250";
+
+ aliases {
+ serial0 = "/serial@12C20000";
+ console = "/serial@12C20000";
+ };
+
+ mmc@12200000 {
+ samsung,bus-width = <8>;
+ samsung,timing = <1 3 3>;
+ };
+
+ mmc@12210000 {
+ status = "disabled";
+ };
+
+ mmc@12220000 {
+ samsung,bus-width = <4>;
+ samsung,timing = <1 2 3>;
+ };
+
+ mmc@12230000 {
+ status = "disabled";
+ };
+};
+++ /dev/null
-#
-# Copyright (C) 2010 Samsung Electronics
-# Kyungmin Park <kyungmin.park@samsung.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# On S5PC100 we use the 128 MiB OneDRAM bank at
-#
-# 0x30000000 to 0x35000000 (80MiB)
-# 0x38000000 to 0x40000000 (128MiB)
-#
-# On S5PC110 we use the 128 MiB OneDRAM bank at
-#
-# 0x30000000 to 0x35000000 (80MiB)
-# 0x40000000 to 0x50000000 (256MiB)
-#
-CONFIG_SYS_TEXT_BASE = 0x34800000
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
- int i;
+ int i, ret, ret_sd = 0;
/* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */
s5p_gpio_direction_output(&s5pc110_gpio->j2, 7, 1);
s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
}
- return s5p_mmc_init(0, 4);
+ ret = s5p_mmc_init(0, 4);
+ if (ret)
+ error("MMC: Failed to init MMC:0.\n");
+
+ /*
+ * SD card (T_FLASH) detect and init
+ * T_FLASH_DETECT: EINT28: GPH3[4] input mode
+ */
+ s5p_gpio_cfg_pin(&s5pc110_gpio->h3, 4, GPIO_INPUT);
+ s5p_gpio_set_pull(&s5pc110_gpio->h3, 4, GPIO_PULL_UP);
+
+ if (!s5p_gpio_get_value(&s5pc110_gpio->h3, 4)) {
+ for (i = 0; i < 7; i++) {
+ if (i == 2)
+ continue;
+
+ /* GPG2[0:6] special function 2 */
+ s5p_gpio_cfg_pin(&s5pc110_gpio->g2, i, 0x2);
+ /* GPG2[0:6] pull disable */
+ s5p_gpio_set_pull(&s5pc110_gpio->g2, i, GPIO_PULL_NONE);
+ /* GPG2[0:6] drv 4x */
+ s5p_gpio_set_drv(&s5pc110_gpio->g2, i, GPIO_DRV_4X);
+ }
+
+ ret_sd = s5p_mmc_init(2, 4);
+ if (ret_sd)
+ error("MMC: Failed to init SD card (MMC:2).\n");
+ }
+
+ return ret & ret_sd;
}
#endif
+++ /dev/null
-#
-# Copyright (C) 2008 # Samsung Elecgtronics
-# Kyungmin Park <kyungmin.park@samsung.com>
-#
-
-# On S5PC100 we use the 128 MiB OneDRAM bank at
-#
-# 0x30000000 to 0x35000000 (80MiB)
-# 0x38000000 to 0x40000000 (128MiB)
-#
-# On S5PC110 we use the 128 MiB OneDRAM bank at
-#
-# 0x30000000 to 0x35000000 (80MiB)
-# 0x40000000 to 0x48000000 (128MiB)
-#
-CONFIG_SYS_TEXT_BASE = 0x34800000
--- /dev/null
+/*
+ * Common board functions for siemens AM335X based boards
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/board/ti/am335x/board.c
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <watchdog.h>
+#include "../common/factoryset.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ /* Initalize the board header */
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ if (read_eeprom() < 0)
+ puts("Could not get board ID.\n");
+
+ enable_board_pin_mux();
+}
+
+void sdram_init(void)
+{
+ spl_siemens_board_init();
+ board_init_ddr();
+
+ return;
+}
+#endif /* #ifdef CONFIG_SPL_BUILD */
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif /* defined(CONFIG_HW_WATCHDOG) */
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ if (read_eeprom() < 0)
+ puts("Could not get board ID.\n");
+
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_FACTORYSET
+ factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR);
+#endif
+ gpmc_init();
+
+#ifdef CONFIG_VIDEO
+ board_video_init();
+#endif
+
+ return 0;
+}
+#endif /* #ifndef CONFIG_SPL_BUILD */
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+ DDR_PLL_FREQ, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ omap_nand_switch_ecc(1, 8);
+
+ return 0;
+}
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#if defined(BOARD_DFU_BUTTON_GPIO)
+/*
+ * This command returns the status of the user button on
+ * Input - none
+ * Returns - 1 if button is held down
+ * 0 if button is not held down
+ */
+static int
+do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int button = 0;
+ int gpio;
+
+ gpio = BOARD_DFU_BUTTON_GPIO;
+ gpio_request(gpio, "DFU");
+ gpio_direction_input(gpio);
+ if (gpio_get_value(gpio))
+ button = 1;
+ else
+ button = 0;
+
+ gpio_free(gpio);
+ if (!button) {
+ /* LED0 - RED=1: GPIO2_0 2*32 = 64 */
+ gpio_request(BOARD_DFU_BUTTON_LED, "");
+ gpio_direction_output(BOARD_DFU_BUTTON_LED, 1);
+ gpio_set_value(BOARD_DFU_BUTTON_LED, 1);
+ }
+
+ return button;
+}
+
+U_BOOT_CMD(
+ dfubutton, CONFIG_SYS_MAXARGS, 1, do_userbutton,
+ "Return the status of the DFU button",
+ ""
+);
+#endif
+
+static int
+do_usertestwdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ printf("\n\n\n Go into infinite loop\n\n\n");
+ while (1)
+ ;
+ return 0;
+};
+
+U_BOOT_CMD(
+ testwdt, CONFIG_SYS_MAXARGS, 1, do_usertestwdt,
+ "Sends U-Boot into infinite loop",
+ ""
+);
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ printf("Enable d-cache\n");
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_SPL_BUILD */
--- /dev/null
+/*
+ *
+ * Read FactorySet information from EEPROM into global structure.
+ * (C) Copyright 2013 Siemens Schweiz AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#if !defined(CONFIG_SPL_BUILD)
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/unaligned.h>
+#include <net.h>
+#include <usbdescriptors.h>
+#include "factoryset.h"
+
+#define EEPR_PG_SZ 0x80
+#define EEPROM_FATORYSET_OFFSET 0x400
+#define OFF_PG EEPROM_FATORYSET_OFFSET/EEPR_PG_SZ
+
+/* Global variable that contains necessary information from FactorySet */
+struct factorysetcontainer factory_dat;
+
+#define fact_get_char(i) *((char *)&eeprom_buf[i])
+
+static int fact_match(unsigned char *eeprom_buf, uchar *s1, int i2)
+{
+ if (s1 == NULL)
+ return -1;
+
+ while (*s1 == fact_get_char(i2++))
+ if (*s1++ == '=')
+ return i2;
+
+ if (*s1 == '\0' && fact_get_char(i2-1) == '=')
+ return i2;
+
+ return -1;
+}
+
+static int get_factory_val(unsigned char *eeprom_buf, int size, uchar *name,
+ uchar *buf, int len)
+{
+ int i, nxt = 0;
+
+ for (i = 0; fact_get_char(i) != '\0'; i = nxt + 1) {
+ int val, n;
+
+ for (nxt = i; fact_get_char(nxt) != '\0'; ++nxt) {
+ if (nxt >= size)
+ return -1;
+ }
+
+ val = fact_match(eeprom_buf, (uchar *)name, i);
+ if (val < 0)
+ continue;
+
+ /* found; copy out */
+ for (n = 0; n < len; ++n, ++buf) {
+ *buf = fact_get_char(val++);
+ if (*buf == '\0')
+ return n;
+ }
+
+ if (n)
+ *--buf = '\0';
+
+ printf("env_buf [%d bytes] too small for value of \"%s\"\n",
+ len, name);
+
+ return n;
+ }
+ return -1;
+}
+
+static
+int get_factory_record_val(unsigned char *eeprom_buf, int size, uchar *record,
+ uchar *name, uchar *buf, int len)
+{
+ int ret = -1;
+ int i, nxt = 0;
+ int c;
+ unsigned char end = 0xff;
+
+ for (i = 0; fact_get_char(i) != end; i = nxt) {
+ nxt = i + 1;
+ if (fact_get_char(i) == '>') {
+ int pos;
+ int endpos;
+ int z;
+
+ c = strncmp((char *)&eeprom_buf[i + 1], (char *)record,
+ strlen((char *)record));
+ if (c == 0) {
+ /* record found */
+ pos = i + strlen((char *)record) + 2;
+ nxt = pos;
+ /* search for "<" */
+ c = -1;
+ for (z = pos; fact_get_char(z) != end; z++) {
+ if ((fact_get_char(z) == '<') ||
+ (fact_get_char(z) == '>')) {
+ endpos = z;
+ nxt = endpos;
+ c = 0;
+ break;
+ }
+ }
+ }
+ if (c == 0) {
+ /* end found -> call get_factory_val */
+ eeprom_buf[endpos] = end;
+ ret = get_factory_val(&eeprom_buf[pos],
+ size - pos, name, buf, len);
+ /* fix buffer */
+ eeprom_buf[endpos] = '<';
+ debug("%s: %s.%s = %s\n",
+ __func__, record, name, buf);
+ return ret;
+ }
+ }
+ }
+ return ret;
+}
+
+int factoryset_read_eeprom(int i2c_addr)
+{
+ int i, pages = 0, size = 0;
+ unsigned char eeprom_buf[0x3c00], hdr[4], buf[MAX_STRING_LENGTH];
+ unsigned char *cp, *cp1;
+
+#if defined(CONFIG_DFU_FUNCTION)
+ factory_dat.usb_vendor_id = CONFIG_G_DNL_VENDOR_NUM;
+ factory_dat.usb_product_id = CONFIG_G_DNL_PRODUCT_NUM;
+#endif
+ if (i2c_probe(i2c_addr))
+ goto err;
+
+ if (i2c_read(i2c_addr, EEPROM_FATORYSET_OFFSET, 2, hdr, sizeof(hdr)))
+ goto err;
+
+ if ((hdr[0] != 0x99) || (hdr[1] != 0x80)) {
+ printf("FactorySet is not right in eeprom.\n");
+ return 1;
+ }
+
+ /* get FactorySet size */
+ size = (hdr[2] << 8) + hdr[3] + sizeof(hdr);
+ if (size > 0x3bfa)
+ size = 0x3bfa;
+
+ pages = size / EEPR_PG_SZ;
+
+ /*
+ * read the eeprom using i2c
+ * I can not read entire eeprom in once, so separate into several
+ * times. Furthermore, fetch eeprom take longer time, so we fetch
+ * data after every time we got a record from eeprom
+ */
+ debug("Read eeprom page :\n");
+ for (i = 0; i < pages; i++)
+ if (i2c_read(i2c_addr, (OFF_PG + i) * EEPR_PG_SZ, 2,
+ eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ))
+ goto err;
+
+ if (size % EEPR_PG_SZ)
+ if (i2c_read(i2c_addr, (OFF_PG + pages) * EEPR_PG_SZ, 2,
+ eeprom_buf + (pages * EEPR_PG_SZ),
+ (size % EEPR_PG_SZ)))
+ goto err;
+
+ /* we do below just for eeprom align */
+ for (i = 0; i < size; i++)
+ if (eeprom_buf[i] == '\n')
+ eeprom_buf[i] = 0;
+
+ /* skip header */
+ size -= sizeof(hdr);
+ cp = (uchar *)eeprom_buf + sizeof(hdr);
+
+ /* get mac address */
+ get_factory_record_val(cp, size, (uchar *)"ETH1", (uchar *)"mac",
+ buf, MAX_STRING_LENGTH);
+ cp1 = buf;
+ for (i = 0; i < 6; i++) {
+ factory_dat.mac[i] = simple_strtoul((char *)cp1, NULL, 16);
+ cp1 += 3;
+ }
+
+#if defined(CONFIG_DFU_FUNCTION)
+ /* read vid and pid for dfu mode */
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1",
+ (uchar *)"vid", buf,
+ MAX_STRING_LENGTH)) {
+ factory_dat.usb_vendor_id = simple_strtoul((char *)buf,
+ NULL, 16);
+ }
+
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1",
+ (uchar *)"pid", buf,
+ MAX_STRING_LENGTH)) {
+ factory_dat.usb_product_id = simple_strtoul((char *)buf,
+ NULL, 16);
+ }
+ printf("DFU USB: VID = 0x%4x, PID = 0x%4x\n", factory_dat.usb_vendor_id,
+ factory_dat.usb_product_id);
+#endif
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
+ (uchar *)"id", buf,
+ MAX_STRING_LENGTH)) {
+ if (strncmp((const char *)buf, "PXM50", 5) == 0)
+ factory_dat.pxm50 = 1;
+ else
+ factory_dat.pxm50 = 0;
+ }
+ debug("PXM50: %d\n", factory_dat.pxm50);
+#if defined(CONFIG_VIDEO)
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"DISP1",
+ (uchar *)"name", factory_dat.disp_name,
+ MAX_STRING_LENGTH)) {
+ debug("display name: %s\n", factory_dat.disp_name);
+ }
+
+#endif
+ return 0;
+
+err:
+ printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
+ return 1;
+}
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+static int factoryset_mac_setenv(void)
+{
+ uint8_t mac_addr[6];
+
+ debug("FactorySet: Set mac address\n");
+ if (is_valid_ether_addr(factory_dat.mac)) {
+ memcpy(mac_addr, factory_dat.mac, 6);
+ } else {
+ uint32_t mac_hi, mac_lo;
+
+ debug("Warning: FactorySet: <ethaddr> not set. Fallback to E-fuse\n");
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+ if (!is_valid_ether_addr(mac_addr)) {
+ printf("Warning: ethaddr not set by FactorySet or E-fuse. Set <ethaddr> variable to overcome this.\n");
+ return -1;
+ }
+ }
+
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ return 0;
+}
+
+int factoryset_setenv(void)
+{
+ int ret = 0;
+
+ if (factoryset_mac_setenv() < 0)
+ ret = -1;
+
+ return ret;
+}
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev)
+{
+ put_unaligned(factory_dat.usb_vendor_id, &dev->idVendor);
+ put_unaligned(factory_dat.usb_product_id, &dev->idProduct);
+ return 0;
+}
+#endif /* defined(CONFIG_SPL_BUILD) */
--- /dev/null
+/*
+ * Common board functions for siemens AM335X based boards
+ * (C) Copyright 2013 Siemens Schweiz AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FACTORYSET_H
+#define __FACTORYSET_H
+
+#define MAX_STRING_LENGTH 32
+
+struct factorysetcontainer {
+ uchar mac[6];
+ int usb_vendor_id;
+ int usb_product_id;
+ int pxm50;
+#if defined(CONFIG_VIDEO)
+ unsigned char disp_name[MAX_STRING_LENGTH];
+#endif
+};
+
+int factoryset_read_eeprom(int i2c_addr);
+int factoryset_setenv(void);
+extern struct factorysetcontainer factory_dat;
+
+#endif /* __FACTORYSET_H */
--- /dev/null
+#
+# Makefile
+#
+# (C) Copyright 2013 Siemens Schweiz AG
+# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# Based on:
+# u-boot:/board/ti/am335x/Makefile
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS := mux.o
+endif
+
+COBJS += board.o
+ifndef CONFIG_SPL_BUILD
+COBJS += ../common/factoryset.o
+endif
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Board functions for TI AM335X based dxr2 board
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ *
+ * Board functions for TI AM335X based boards
+ * u-boot:/board/ti/am335x/board.c
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <watchdog.h>
+#include "board.h"
+#include "../common/factoryset.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+static struct dxr2_baseboard_id __attribute__((section(".data"))) settings;
+
+const struct ddr3_data ddr3_default = {
+ 0x33524444, 0x56312e33, 0x0100, 0x0001, 0x003A, 0x008A, 0x010B,
+ 0x00C4, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x0006, 0x61C04AB2,
+ 0x00000618,
+};
+
+static void set_default_ddr3_timings(void)
+{
+ printf("Set default DDR3 settings\n");
+ settings.ddr3 = ddr3_default;
+}
+
+static void print_ddr3_timings(void)
+{
+ printf("\n\nDDR3 Timing parameters:\n");
+ printf("Diff Eeprom Default\n");
+ PRINTARGS(magic);
+ PRINTARGS(version);
+ PRINTARGS(ddr3_sratio);
+ PRINTARGS(iclkout);
+
+ PRINTARGS(dt0rdsratio0);
+ PRINTARGS(dt0wdsratio0);
+ PRINTARGS(dt0fwsratio0);
+ PRINTARGS(dt0wrsratio0);
+
+ PRINTARGS(sdram_tim1);
+ PRINTARGS(sdram_tim2);
+ PRINTARGS(sdram_tim3);
+
+ PRINTARGS(emif_ddr_phy_ctlr_1);
+
+ PRINTARGS(sdram_config);
+ PRINTARGS(ref_ctrl);
+}
+
+static void print_chip_data(void)
+{
+ printf("\n");
+ printf("Device: '%s'\n", settings.chip.sdevname);
+ printf("HW version: '%s'\n", settings.chip.shwver);
+}
+#endif /* CONFIG_SPL_BUILD */
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+ /* Check if baseboard eeprom is available */
+ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+ printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
+ return 1;
+ }
+
+#ifdef CONFIG_SPL_BUILD
+ /* Read Siemens eeprom data (DDR3) */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
+ (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
+ printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
+ set_default_ddr3_timings();
+ }
+ /* Read Siemens eeprom data (CHIP) */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
+ (uchar *)&settings.chip, sizeof(settings.chip)))
+ printf("Could not read chip settings\n");
+
+ if (ddr3_default.magic == settings.ddr3.magic &&
+ ddr3_default.version == settings.ddr3.version) {
+ printf("Using DDR3 settings from EEPROM\n");
+ } else {
+ if (ddr3_default.magic != settings.ddr3.magic)
+ printf("Error: No valid DDR3 data in eeprom.\n");
+ if (ddr3_default.version != settings.ddr3.version)
+ printf("Error: DDR3 data version does not match.\n");
+
+ printf("Using default settings\n");
+ set_default_ddr3_timings();
+ }
+
+ if (MAGIC_CHIP == settings.chip.magic) {
+ printf("Valid chip data in eeprom\n");
+ print_chip_data();
+ } else {
+ printf("Error: No chip data in eeprom\n");
+ }
+
+ print_ddr3_timings();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+static void board_init_ddr(void)
+{
+struct emif_regs dxr2_ddr3_emif_reg_data = {
+ .zq_config = 0x50074BE4,
+};
+
+struct ddr_data dxr2_ddr3_data = {
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
+ .cmd0dldiff = 0,
+ .cmd1dldiff = 0,
+ .cmd2dldiff = 0,
+};
+ /* pass values from eeprom */
+ dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
+ dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
+ dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
+ dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
+ settings.ddr3.emif_ddr_phy_ctlr_1;
+ dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
+ dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
+
+ dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
+ dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
+ dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
+ dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
+
+ dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
+ dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
+ dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
+ dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
+ dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
+ dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
+
+ config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &dxr2_ddr3_data,
+ &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
+}
+
+static void spl_siemens_board_init(void)
+{
+ return;
+}
+#endif /* if def CONFIG_SPL_BUILD */
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_id = 0,
+ .phy_if = PHY_INTERFACE_MODE_MII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 4,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+#if defined(CONFIG_DRIVER_TI_CPSW) || \
+ (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
+int board_eth_init(bd_t *bis)
+{
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+ int n = 0;
+ int rv;
+
+ factoryset_setenv();
+
+ /* Set rgmii mode and enable rmii clock to be sourced from chip */
+ writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+ return n;
+}
+#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
+#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+
+#include "../common/board.c"
--- /dev/null
+/*
+ * board.h
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * TI AM335x boards information header
+ * u-boot:/board/ti/am335x/board.h
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#define PARGS3(x) settings.ddr3.x-ddr3_default.x, \
+ settings.ddr3.x, ddr3_default.x
+#define PRINTARGS(y) printf("%x, %8x, %8x : "#y"\n", PARGS3(y))
+#define MAGIC_CHIP 0x50494843
+
+/* Automatic generated definition */
+/* Wed, 19 Jun 2013 10:57:48 +0200 */
+/* From file: draco/ddr3-data-micron.txt */
+struct ddr3_data {
+ unsigned int magic; /* 0x33524444 */
+ unsigned int version; /* 0x56312e33 */
+ unsigned short int ddr3_sratio; /* 0x0100 */
+ unsigned short int iclkout; /* 0x0001 */
+ unsigned short int dt0rdsratio0; /* 0x003A */
+ unsigned short int dt0wdsratio0; /* 0x008A */
+ unsigned short int dt0fwsratio0; /* 0x010B */
+ unsigned short int dt0wrsratio0; /* 0x00C4 */
+ unsigned int sdram_tim1; /* 0x0888A39B */
+ unsigned int sdram_tim2; /* 0x26247FDA */
+ unsigned int sdram_tim3; /* 0x501F821F */
+ unsigned short int emif_ddr_phy_ctlr_1; /* 0x0006 */
+ unsigned int sdram_config; /* 0x61C04AB2 */
+ unsigned int ref_ctrl; /* 0x00000618 */
+};
+
+struct chip_data {
+ unsigned int magic;
+ char sdevname[16];
+ char shwver[7];
+};
+
+struct dxr2_baseboard_id {
+ struct ddr3_data ddr3;
+ struct chip_data chip;
+};
+
+/*
+ * We have three pin mux functions that must exist. We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
--- /dev/null
+/*
+ * pinmux setup for siemens dxr2 board
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/mux.c
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+ {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+
+static struct module_pin_mux gpios_pin_mux[] = {
+ /* DFU button GPIO0_27*/
+ {OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)},
+ {OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */
+ {OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */
+ {-1},
+};
+
+static struct module_pin_mux ethernet_pin_mux[] = {
+ {OFFSET(mii1_col), (MODE(3) | RXACTIVE)},
+ {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_txen), (MODE(1))},
+ {OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)},
+ {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_txd1), (MODE(1))},
+ {OFFSET(mii1_txd0), (MODE(1))},
+ {OFFSET(mii1_txclk), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxclk), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxd3), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxd2), (MODE(1))},
+ {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)},
+ {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)},
+ {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)},
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+ configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ enable_uart3_pin_mux();
+ configure_module_pin_mux(nand_pin_mux);
+ configure_module_pin_mux(ethernet_pin_mux);
+ configure_module_pin_mux(gpios_pin_mux);
+}
--- /dev/null
+#
+# Makefile
+#
+# (C) Copyright 2013 Siemens Schweiz AG
+# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# Based on:
+# u-boot:/board/ti/am335x/Makefile
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS := mux.o
+endif
+
+COBJS += board.o
+ifndef CONFIG_SPL_BUILD
+COBJS += ../common/factoryset.o
+endif
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Board functions for TI AM335X based pxm2 board
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/board.c
+ *
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include "../../../drivers/video/da8xx-fb.h"
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <watchdog.h>
+#include "board.h"
+#include "../common/factoryset.h"
+#include "pmic.h"
+#include <nand.h>
+#include <bmp_layout.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+static void board_init_ddr(void)
+{
+struct emif_regs pxm2_ddr3_emif_reg_data = {
+ .sdram_config = 0x41805332,
+ .sdram_tim1 = 0x666b3c9,
+ .sdram_tim2 = 0x243631ca,
+ .sdram_tim3 = 0x33f,
+ .emif_ddr_phy_ctlr_1 = 0x100005,
+ .zq_config = 0,
+ .ref_ctrl = 0x81a,
+};
+
+struct ddr_data pxm2_ddr3_data = {
+ .datardsratio0 = 0x81204812,
+ .datawdsratio0 = 0,
+ .datafwsratio0 = 0x8020080,
+ .datawrsratio0 = 0x4010040,
+ .datauserank0delay = 1,
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
+ .cmd0csratio = 0x80,
+ .cmd0dldiff = 0,
+ .cmd0iclkout = 0,
+ .cmd1csratio = 0x80,
+ .cmd1dldiff = 0,
+ .cmd1iclkout = 0,
+ .cmd2csratio = 0x80,
+ .cmd2dldiff = 0,
+ .cmd2iclkout = 0,
+};
+
+ config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data,
+ &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
+}
+
+/*
+ * voltage switching for MPU frequency switching.
+ * @module = mpu - 0, core - 1
+ * @vddx_op_vol_sel = vdd voltage to set
+ */
+
+#define MPU 0
+#define CORE 1
+
+int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
+{
+ uchar buf[4];
+ unsigned int reg_offset;
+
+ if (module == MPU)
+ reg_offset = PMIC_VDD1_OP_REG;
+ else
+ reg_offset = PMIC_VDD2_OP_REG;
+
+ /* Select VDDx OP */
+ if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
+ return 1;
+
+ buf[0] &= ~PMIC_OP_REG_CMD_MASK;
+
+ if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
+ return 1;
+
+ /* Configure VDDx OP Voltage */
+ if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
+ return 1;
+
+ buf[0] &= ~PMIC_OP_REG_SEL_MASK;
+ buf[0] |= vddx_op_vol_sel;
+
+ if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
+ return 1;
+
+ if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
+ return 1;
+
+ if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
+ return 1;
+
+ return 0;
+}
+
+#define OSC (V_OSCK/1000000)
+
+const struct dpll_params dpll_mpu_pxm2 = {
+ 720, OSC-1, 1, -1, -1, -1, -1};
+
+void spl_siemens_board_init(void)
+{
+ uchar buf[4];
+ /*
+ * pxm2 PMIC code. All boards currently want an MPU voltage
+ * of 1.2625V and CORE voltage of 1.1375V to operate at
+ * 720MHz.
+ */
+ if (i2c_probe(PMIC_CTRL_I2C_ADDR))
+ return;
+
+ /* VDD1/2 voltage selection register access by control i/f */
+ if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
+ return;
+
+ buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
+
+ if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
+ return;
+
+ /* Frequency switching for OPP 120 */
+ if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
+ voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
+ printf("voltage update failed\n");
+ }
+}
+#endif /* if def CONFIG_SPL_BUILD */
+
+int read_eeprom(void)
+{
+ /* nothing ToDo here for this board */
+
+ return 0;
+}
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_id = 0,
+ .phy_if = PHY_INTERFACE_MODE_RMII,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_id = 1,
+ .phy_if = PHY_INTERFACE_MODE_RMII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 4,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+
+#if defined(CONFIG_DRIVER_TI_CPSW) || \
+ (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
+int board_eth_init(bd_t *bis)
+{
+ int n = 0;
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+#ifdef CONFIG_FACTORYSET
+ int rv;
+ if (!is_valid_ether_addr(factory_dat.mac))
+ printf("Error: no valid mac address\n");
+ else
+ eth_setenv_enetaddr("ethaddr", factory_dat.mac);
+#endif /* #ifdef CONFIG_FACTORYSET */
+
+ /* Set rgmii mode and enable rmii clock to be sourced from chip */
+ writel(RGMII_MODE_ENABLE , &cdev->miisel);
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+#endif
+ return n;
+}
+#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
+
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+static struct da8xx_panel lcd_panels[] = {
+ /* AUO G156XW01 V1 */
+ [0] = {
+ .name = "AUO_G156XW01_V1",
+ .width = 1376,
+ .height = 768,
+ .hfp = 14,
+ .hbp = 64,
+ .hsw = 56,
+ .vfp = 1,
+ .vbp = 28,
+ .vsw = 3,
+ .pxl_clk = 60000000,
+ .invert_pxl_clk = 0,
+ },
+ /* AUO B101EVN06 V0 */
+ [1] = {
+ .name = "AUO_B101EVN06_V0",
+ .width = 1280,
+ .height = 800,
+ .hfp = 52,
+ .hbp = 84,
+ .hsw = 36,
+ .vfp = 3,
+ .vbp = 14,
+ .vsw = 6,
+ .pxl_clk = 60000000,
+ .invert_pxl_clk = 0,
+ },
+ /*
+ * Settings from factoryset
+ * stored in EEPROM
+ */
+ [2] = {
+ .name = "factoryset",
+ .width = 0,
+ .height = 0,
+ .hfp = 0,
+ .hbp = 0,
+ .hsw = 0,
+ .vfp = 0,
+ .vbp = 0,
+ .vsw = 0,
+ .pxl_clk = 60000000,
+ .invert_pxl_clk = 0,
+ },
+};
+
+static const struct display_panel disp_panel = {
+ WVGA,
+ 32,
+ 16,
+ COLOR_ACTIVE,
+};
+
+static const struct lcd_ctrl_config lcd_cfg = {
+ &disp_panel,
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 32,
+ .fdd = 0x80,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+};
+
+static int set_gpio(int gpio, int state)
+{
+ gpio_request(gpio, "temp");
+ gpio_direction_output(gpio, state);
+ gpio_set_value(gpio, state);
+ gpio_free(gpio);
+ return 0;
+}
+
+static int enable_backlight(void)
+{
+ set_gpio(BOARD_LCD_POWER, 1);
+ set_gpio(BOARD_BACK_LIGHT, 1);
+ set_gpio(BOARD_TOUCH_POWER, 1);
+ return 0;
+}
+
+static int enable_pwm(void)
+{
+ struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
+ struct pwmss_ecap_regs *ecap;
+ int ticks = PWM_TICKS;
+ int duty = PWM_DUTY;
+
+ ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
+ /* enable clock */
+ setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
+ /* TimeStam Counter register */
+ writel(0xdb9, &ecap->tsctr);
+ /* config period */
+ writel(ticks - 1, &ecap->cap3);
+ writel(ticks - 1, &ecap->cap1);
+ setbits_le16(&ecap->ecctl2,
+ (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
+ /* config duty */
+ writel(duty, &ecap->cap2);
+ writel(duty, &ecap->cap4);
+ /* start */
+ setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
+ return 0;
+}
+
+static struct dpll_regs dpll_lcd_regs = {
+ .cm_clkmode_dpll = CM_WKUP + 0x98,
+ .cm_idlest_dpll = CM_WKUP + 0x48,
+ .cm_clksel_dpll = CM_WKUP + 0x54,
+};
+
+/* no console on this board */
+int board_cfb_skip(void)
+{
+ return 1;
+}
+
+#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
+#define PLL_GET_N(v) (v & 0x7f)
+
+static int get_clk(struct dpll_regs *dpll_regs)
+{
+ unsigned int val;
+ unsigned int m, n;
+ int f = 0;
+
+ val = readl(dpll_regs->cm_clksel_dpll);
+ m = PLL_GET_M(val);
+ n = PLL_GET_N(val);
+ f = (m * V_OSCK) / n;
+
+ return f;
+};
+
+int clk_get(int clk)
+{
+ return get_clk(&dpll_lcd_regs);
+};
+
+static int conf_disp_pll(int m, int n)
+{
+ struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
+ struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
+ struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
+
+ u32 *const clk_domains[] = {
+ &cmper->lcdclkctrl,
+ 0
+ };
+ u32 *const clk_modules_explicit_en[] = {
+ &cmper->lcdclkctrl,
+ &cmper->lcdcclkstctrl,
+ &cmper->epwmss0clkctrl,
+ 0
+ };
+ do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+ writel(0x0, &cmdpll->clklcdcpixelclk);
+
+ do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
+
+ return 0;
+}
+
+static int board_video_init(void)
+{
+ /* set 300 MHz */
+ conf_disp_pll(25, 2);
+ if (factory_dat.pxm50)
+ da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
+ else
+ da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
+
+ enable_pwm();
+ enable_backlight();
+
+ return 0;
+}
+#endif
+#include "../common/board.c"
--- /dev/null
+/*
+ * board.h
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * TI AM335x boards information header
+ * u-boot:/board/ti/am335x/board.h
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
--- /dev/null
+/*
+ * pinmux setup for siemens pxm2 board
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */
+ {-1},
+};
+
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUP_EN}, /* RGMII2_RD0 */
+ {OFFSET(mcasp0_ahclkx), MODE(7) | PULLUDEN}, /* MCASP0_AHCLKX */
+ {-1},
+};
+#endif
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+ {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {-1},
+};
+
+#ifndef CONFIG_NO_ETH
+static struct module_pin_mux rgmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
+ {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
+ {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
+ {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
+ {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
+ {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
+ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
+ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
+ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
+ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
+ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux rgmii2_pin_mux[] = {
+ {OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */
+ {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */
+ {OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */
+ {OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */
+ {OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */
+ {OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */
+ {OFFSET(gpmc_a6), MODE(7)}, /* RGMII2_TCLK */
+ {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */
+ {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */
+ {OFFSET(gpmc_a9), MODE(7)}, /* RGMII2_RD2 */
+ {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+#endif
+
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDEN)}, /* MMC0_CD */
+ {-1},
+};
+#endif
+
+static struct module_pin_mux lcdc_pin_mux[] = {
+ {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD_DAT0 */
+ {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD_DAT1 */
+ {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD_DAT2 */
+ {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD_DAT3 */
+ {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD_DAT4 */
+ {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD_DAT5 */
+ {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD_DAT6 */
+ {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD_DAT7 */
+ {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD_DAT8 */
+ {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD_DAT9 */
+ {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD_DAT10 */
+ {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD_DAT11 */
+ {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD_DAT12 */
+ {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD_DAT13 */
+ {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD_DAT14 */
+ {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD_DAT15 */
+ {OFFSET(gpmc_ad8), (MODE(1))}, /* LCD_DAT16 */
+ {OFFSET(gpmc_ad9), (MODE(1))}, /* LCD_DAT17 */
+ {OFFSET(gpmc_ad10), (MODE(1))}, /* LCD_DAT18 */
+ {OFFSET(gpmc_ad11), (MODE(1))}, /* LCD_DAT19 */
+ {OFFSET(gpmc_ad12), (MODE(1))}, /* LCD_DAT20 */
+ {OFFSET(gpmc_ad13), (MODE(1))}, /* LCD_DAT21 */
+ {OFFSET(gpmc_ad14), (MODE(1))}, /* LCD_DAT22 */
+ {OFFSET(gpmc_ad15), (MODE(1))}, /* LCD_DAT23 */
+ {OFFSET(lcd_vsync), (MODE(0))}, /* LCD_VSYNC */
+ {OFFSET(lcd_hsync), (MODE(0))}, /* LCD_HSYNC */
+ {OFFSET(lcd_pclk), (MODE(0))}, /* LCD_PCLK */
+ {OFFSET(lcd_ac_bias_en), (MODE(0))}, /* LCD_AC_BIAS_EN */
+ {-1},
+};
+
+static struct module_pin_mux ecap0_pin_mux[] = {
+ {OFFSET(ecap0_in_pwm0_out), (MODE(0))},
+ {-1},
+};
+
+static struct module_pin_mux gpio_pin_mux[] = {
+ {OFFSET(mcasp0_fsx), MODE(7)}, /* GPIO3_15 LCD power*/
+ {OFFSET(mcasp0_axr0), MODE(7)}, /* GPIO3_16 Backlight */
+ {OFFSET(gpmc_a9), MODE(7)}, /* GPIO1_25 Touch power */
+ {-1},
+};
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+ configure_module_pin_mux(i2c1_pin_mux);
+#ifdef CONFIG_NAND
+ configure_module_pin_mux(nand_pin_mux);
+#endif
+#ifndef CONFIG_NO_ETH
+ configure_module_pin_mux(rgmii1_pin_mux);
+ configure_module_pin_mux(rgmii2_pin_mux);
+#endif
+#ifdef CONFIG_MMC
+ configure_module_pin_mux(mmc0_pin_mux);
+#endif
+ configure_module_pin_mux(lcdc_pin_mux);
+ configure_module_pin_mux(gpio_pin_mux);
+ configure_module_pin_mux(ecap0_pin_mux);
+}
--- /dev/null
+/*
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef PMIC_H
+#define PMIC_H
+
+/*
+ * The PMIC on this board is a TPS65910.
+ */
+
+#define PMIC_SR_I2C_ADDR 0x12
+#define PMIC_CTRL_I2C_ADDR 0x2D
+/* PMIC Register offsets */
+#define PMIC_VDD1_REG 0x21
+#define PMIC_VDD1_OP_REG 0x22
+#define PMIC_VDD2_REG 0x24
+#define PMIC_VDD2_OP_REG 0x25
+#define PMIC_DEVCTRL_REG 0x3f
+
+/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
+#define PMIC_VGAIN_SEL_MASK (0x3 << 6)
+#define PMIC_ILMAX_MASK (0x1 << 5)
+#define PMIC_TSTEP_MASK (0x7 << 2)
+#define PMIC_ST_MASK (0x3)
+
+#define PMIC_REG_VGAIN_SEL_X1 (0x0 << 6)
+#define PMIC_REG_VGAIN_SEL_X1_0 (0x1 << 6)
+#define PMIC_REG_VGAIN_SEL_X3 (0x2 << 6)
+#define PMIC_REG_VGAIN_SEL_X4 (0x3 << 6)
+
+#define PMIC_REG_ILMAX_1_0_A (0x0 << 5)
+#define PMIC_REG_ILMAX_1_5_A (0x1 << 5)
+
+#define PMIC_REG_TSTEP_ (0x0 << 2)
+#define PMIC_REG_TSTEP_12_5 (0x1 << 2)
+#define PMIC_REG_TSTEP_9_4 (0x2 << 2)
+#define PMIC_REG_TSTEP_7_5 (0x3 << 2)
+#define PMIC_REG_TSTEP_6_25 (0x4 << 2)
+#define PMIC_REG_TSTEP_4_7 (0x5 << 2)
+#define PMIC_REG_TSTEP_3_12 (0x6 << 2)
+#define PMIC_REG_TSTEP_2_5 (0x7 << 2)
+
+#define PMIC_REG_ST_OFF (0x0)
+#define PMIC_REG_ST_ON_HI_POW (0x1)
+#define PMIC_REG_ST_OFF_1 (0x2)
+#define PMIC_REG_ST_ON_LOW_POW (0x3)
+
+
+/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
+#define PMIC_OP_REG_SEL (0x7F)
+
+#define PMIC_OP_REG_CMD_MASK (0x1 << 7)
+#define PMIC_OP_REG_CMD_OP (0x0 << 7)
+#define PMIC_OP_REG_CMD_SR (0x1 << 7)
+
+#define PMIC_OP_REG_SEL_MASK (0x7F)
+#define PMIC_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */
+#define PMIC_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */
+
+/* Device control register . (DEVCTRL_REG) */
+#define PMIC_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4)
+#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4)
+#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4)
+
+#endif
--- /dev/null
+#
+# Makefile
+#
+# (C) Copyright 2013 Siemens Schweiz AG
+# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# Based on:
+# u-boot:/board/ti/am335x/Makefile
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS := mux.o
+endif
+
+COBJS += board.o
+ifndef CONFIG_SPL_BUILD
+COBJS += ../common/factoryset.o
+endif
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Board functions for TI AM335X based rut board
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/board.c
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spi.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <video.h>
+#include <watchdog.h>
+#include "board.h"
+#include "../common/factoryset.h"
+#include "../../../drivers/video/da8xx-fb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+static void board_init_ddr(void)
+{
+struct emif_regs rut_ddr3_emif_reg_data = {
+ .sdram_config = 0x61C04AB2,
+ .sdram_tim1 = 0x0888A39B,
+ .sdram_tim2 = 0x26337FDA,
+ .sdram_tim3 = 0x501F830F,
+ .emif_ddr_phy_ctlr_1 = 0x6,
+ .zq_config = 0x50074BE4,
+ .ref_ctrl = 0x93B,
+};
+
+struct ddr_data rut_ddr3_data = {
+ .datardsratio0 = 0x3b,
+ .datawdsratio0 = 0x85,
+ .datafwsratio0 = 0x100,
+ .datawrsratio0 = 0xc1,
+ .datauserank0delay = 1,
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+struct cmd_control rut_ddr3_cmd_ctrl_data = {
+ .cmd0csratio = 0x40,
+ .cmd0dldiff = 0,
+ .cmd0iclkout = 1,
+ .cmd1csratio = 0x40,
+ .cmd1dldiff = 0,
+ .cmd1iclkout = 1,
+ .cmd2csratio = 0x40,
+ .cmd2dldiff = 0,
+ .cmd2iclkout = 1,
+};
+
+ config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data,
+ &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
+}
+
+static void spl_siemens_board_init(void)
+{
+ return;
+}
+#endif /* if def CONFIG_SPL_BUILD */
+
+#if defined(CONFIG_DRIVER_TI_CPSW)
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_id = 1,
+ .phy_if = PHY_INTERFACE_MODE_RMII,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_id = 0,
+ .phy_if = PHY_INTERFACE_MODE_RMII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+#if defined(CONFIG_DRIVER_TI_CPSW) || \
+ (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
+int board_eth_init(bd_t *bis)
+{
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+ int n = 0;
+ int rv;
+
+#ifndef CONFIG_SPL_BUILD
+ factoryset_setenv();
+#endif
+
+ /* Set rgmii mode and enable rmii clock to be sourced from chip */
+ writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+ return n;
+}
+#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
+#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+
+#if defined(CONFIG_HW_WATCHDOG)
+static bool hw_watchdog_init_done;
+static int hw_watchdog_trigger_level;
+
+void hw_watchdog_reset(void)
+{
+ if (!hw_watchdog_init_done)
+ return;
+
+ hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
+ gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
+}
+
+void hw_watchdog_init(void)
+{
+ gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
+ gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
+
+ hw_watchdog_reset();
+
+ hw_watchdog_init_done = 1;
+}
+#endif /* defined(CONFIG_HW_WATCHDOG) */
+
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+static struct da8xx_panel lcd_panels[] = {
+ /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
+ [0] = {
+ .name = "KWH043MC17-F01",
+ .width = 480,
+ .height = 800,
+ .hfp = 50, /* no spec, "don't care" values */
+ .hbp = 50,
+ .hsw = 50,
+ .vfp = 50,
+ .vbp = 50,
+ .vsw = 50,
+ .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
+ .invert_pxl_clk = 1,
+ },
+ /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
+ [1] = {
+ .name = "KWH043ST20-F01",
+ .width = 480,
+ .height = 800,
+ .hfp = 50, /* no spec, "don't care" values */
+ .hbp = 50,
+ .hsw = 50,
+ .vfp = 50,
+ .vbp = 50,
+ .vsw = 50,
+ .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
+ .invert_pxl_clk = 1,
+ },
+ /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
+ [2] = {
+ .name = "MI0430VT-1",
+ .width = 480,
+ .height = 800,
+ .hfp = 50, /* no spec, "don't care" values */
+ .hbp = 50,
+ .hsw = 50,
+ .vfp = 50,
+ .vbp = 50,
+ .vsw = 50,
+ .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
+ .invert_pxl_clk = 1,
+ },
+};
+
+static const struct display_panel disp_panels[] = {
+ [0] = {
+ WVGA,
+ 16, /* RGB 888 */
+ 16,
+ COLOR_ACTIVE,
+ },
+ [1] = {
+ WVGA,
+ 16, /* RGB 888 */
+ 16,
+ COLOR_ACTIVE,
+ },
+ [2] = {
+ WVGA,
+ 24, /* RGB 888 */
+ 16,
+ COLOR_ACTIVE,
+ },
+};
+
+static const struct lcd_ctrl_config lcd_cfgs[] = {
+ [0] = {
+ &disp_panels[0],
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 16,
+ .fdd = 0x80,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+ },
+ [1] = {
+ &disp_panels[1],
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 16,
+ .fdd = 0x80,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+ },
+ [2] = {
+ &disp_panels[2],
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 24,
+ .fdd = 0x80,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+ },
+
+};
+
+/* no console on this board */
+int board_cfb_skip(void)
+{
+ return 1;
+}
+
+#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
+#define PLL_GET_N(v) (v & 0x7f)
+
+static struct dpll_regs dpll_lcd_regs = {
+ .cm_clkmode_dpll = CM_WKUP + 0x98,
+ .cm_idlest_dpll = CM_WKUP + 0x48,
+ .cm_clksel_dpll = CM_WKUP + 0x54,
+};
+
+static int get_clk(struct dpll_regs *dpll_regs)
+{
+ unsigned int val;
+ unsigned int m, n;
+ int f = 0;
+
+ val = readl(dpll_regs->cm_clksel_dpll);
+ m = PLL_GET_M(val);
+ n = PLL_GET_N(val);
+ f = (m * V_OSCK) / n;
+
+ return f;
+};
+
+
+
+int clk_get(int clk)
+{
+ return get_clk(&dpll_lcd_regs);
+};
+
+static int conf_disp_pll(int m, int n)
+{
+ struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
+ struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
+ struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
+#if defined(DISPL_PLL_SPREAD_SPECTRUM)
+ struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
+#endif
+
+ u32 *const clk_domains[] = {
+ &cmper->lcdclkctrl,
+ 0
+ };
+ u32 *const clk_modules_explicit_en[] = {
+ &cmper->lcdclkctrl,
+ &cmper->lcdcclkstctrl,
+ &cmper->spi1clkctrl,
+ 0
+ };
+ do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+ /* 0x44e0_0500 write lcdc pixel clock mux Linux hat hier 0 */
+ writel(0x0, &cmdpll->clklcdcpixelclk);
+
+ do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
+
+#if defined(DISPL_PLL_SPREAD_SPECTRUM)
+ writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
+ writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
+ writel(readl(&cmwkup->clkmoddplldisp) | (1 << 12),
+ &cmwkup->clkmoddplldisp); /* 0x98 */
+#endif
+ return 0;
+}
+
+static int set_gpio(int gpio, int state)
+{
+ gpio_request(gpio, "temp");
+ gpio_direction_output(gpio, state);
+ gpio_set_value(gpio, state);
+ gpio_free(gpio);
+ return 0;
+}
+
+static int enable_lcd(void)
+{
+ unsigned char buf[1];
+
+ set_gpio(BOARD_LCD_RESET, 1);
+
+ /* spi lcd init */
+ kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_3);
+
+ /* backlight on */
+ buf[0] = 0xf;
+ i2c_write(0x24, 0x7, 1, buf, 1);
+ buf[0] = 0x3f;
+ i2c_write(0x24, 0x8, 1, buf, 1);
+ return 0;
+}
+
+int arch_early_init_r(void)
+{
+ enable_lcd();
+ return 0;
+}
+
+static int board_video_init(void)
+{
+ int i;
+ int anzdisp = ARRAY_SIZE(lcd_panels);
+ int display = 1;
+
+ for (i = 0; i < anzdisp; i++) {
+ if (strncmp((const char *)factory_dat.disp_name,
+ lcd_panels[i].name,
+ strlen((const char *)factory_dat.disp_name)) == 0) {
+ printf("DISPLAY: %s\n", factory_dat.disp_name);
+ break;
+ }
+ }
+ if (i == anzdisp) {
+ i = 1;
+ printf("%s: %s not found, using default %s\n", __func__,
+ factory_dat.disp_name, lcd_panels[i].name);
+ }
+ conf_disp_pll(25, 2);
+ da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
+ lcd_cfgs[display].bpp);
+
+ return 0;
+}
+
+
+#endif /* ifdef CONFIG_VIDEO */
+#include "../common/board.c"
--- /dev/null
+/*
+ * board.h
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * TI AM335x boards information header
+ * u-boot:/board/ti/am335x/board.h
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
--- /dev/null
+/*
+ * pinmux setup for siemens rut board
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux ddr_pin_mux[] = {
+ {OFFSET(ddr_resetn), (MODE(0))},
+ {OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_ck), (MODE(0))},
+ {OFFSET(ddr_nck), (MODE(0))},
+ {OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_ba0), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_ba1), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_ba2), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a0), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a1), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a2), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a3), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a4), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a5), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a6), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a7), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a8), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a9), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a10), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a11), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a12), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a13), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a14), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a15), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_odt), (MODE(0))},
+ {OFFSET(ddr_d0), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d1), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d2), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d3), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d4), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d5), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d6), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d7), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d8), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d9), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d10), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d11), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d12), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d13), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d14), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d15), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_dqm0), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_dqm1), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_dqs0), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_dqsn0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(ddr_dqs1), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_dqsn1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(ddr_vref), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ddr_vtp), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+ {OFFSET(gpmc_ad8), (MODE(1))},
+ {OFFSET(gpmc_ad9), (MODE(1))},
+ {OFFSET(gpmc_ad10), (MODE(1))},
+ {OFFSET(gpmc_ad11), (MODE(1))},
+ {OFFSET(gpmc_ad12), (MODE(1))},
+ {OFFSET(gpmc_ad13), (MODE(1))},
+ {OFFSET(gpmc_ad14), (MODE(1))},
+ {OFFSET(gpmc_ad15), (MODE(1))},
+ {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_vsync), (MODE(0))},
+ {OFFSET(lcd_hsync), (MODE(0))},
+ {OFFSET(lcd_pclk), (MODE(0))},
+ {OFFSET(lcd_ac_bias_en), (MODE(0))},
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux mii_pin_mux[] = {
+ {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_txen), (MODE(1))},
+ {OFFSET(mii1_txd1), (MODE(1))},
+ {OFFSET(mii1_txd0), (MODE(1))},
+ {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)},
+ {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)},
+ {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux gpio_pin_mux[] = {
+ {OFFSET(mii1_col), (MODE(7) | RXACTIVE)},
+ {OFFSET(uart1_ctsn), (MODE(7) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(uart1_rtsn), (MODE(7) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(uart1_txd), (MODE(7) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(mii1_rxdv), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_txclk), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_rxclk), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_rxd3), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_rxd2), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a0), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a1), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a4), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a5), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a6), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a7), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a8), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a9), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a10), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a11), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_wpn), (MODE(7) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(gpmc_be1n), (MODE(7) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(gpmc_csn1), (MODE(7) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(gpmc_csn2), (MODE(7) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(gpmc_csn3), (MODE(7) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mcasp0_aclkr), (MODE(7) | RXACTIVE)},
+ {OFFSET(mcasp0_fsr), (MODE(7))},
+ {OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)},
+ {OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE)},
+ {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(xdma_event_intr1), (MODE(7) | RXACTIVE | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+ {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux usb0_pin_mux[] = {
+ {OFFSET(usb0_dm), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb0_dp), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb0_ce), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb0_id), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb0_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb0_drvvbus), (MODE(0))},
+ {-1},
+};
+
+static struct module_pin_mux usb1_pin_mux[] = {
+ {OFFSET(usb1_dm), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb1_dp), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb1_ce), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb1_id), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb1_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb1_drvvbus), (MODE(0))},
+ {-1},
+};
+
+static struct module_pin_mux spi0_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(spi0_cs1), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux spi1_pin_mux[] = {
+ {OFFSET(mcasp0_aclkx), (MODE(3) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux jtag_pin_mux[] = {
+ {OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(tdo), (MODE(0) | PULLUP_EN)},
+ {OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(ntrst), (MODE(0) | RXACTIVE)},
+ {-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | RXACTIVE)},
+ {OFFSET(gpmc_ad1), (MODE(0) | RXACTIVE)},
+ {OFFSET(gpmc_ad2), (MODE(0) | RXACTIVE)},
+ {OFFSET(gpmc_ad3), (MODE(0) | RXACTIVE)},
+ {OFFSET(gpmc_ad4), (MODE(0) | RXACTIVE)},
+ {OFFSET(gpmc_ad5), (MODE(0) | RXACTIVE)},
+ {OFFSET(gpmc_ad6), (MODE(0) | RXACTIVE)},
+ {OFFSET(gpmc_ad7), (MODE(0) | RXACTIVE)},
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUP_EN)},
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUP_EN)},
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)},
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUP_EN)},
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux ainx_pin_mux[] = {
+ {OFFSET(ain7), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ain6), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ain5), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ain4), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ain3), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ain2), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ain1), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ain0), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux rtc_pin_mux[] = {
+ {OFFSET(osc1_in), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(osc1_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux gpmc_pin_mux[] = {
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(gpmc_clk), (MODE(0) | RXACTIVE)},
+ {-1},
+};
+
+static struct module_pin_mux pmic_pin_mux[] = {
+ {OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux osc_pin_mux[] = {
+ {OFFSET(osc0_in), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(osc0_out), (MODE(0) | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux pwm_pin_mux[] = {
+ {OFFSET(ecap0_in_pwm0_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(gpmc_a2), (MODE(6))},
+ {OFFSET(gpmc_a3), (MODE(6))},
+ {-1},
+};
+
+static struct module_pin_mux emu_pin_mux[] = {
+ {OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux vref_pin_mux[] = {
+ {OFFSET(vrefp), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(vrefn), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux misc_pin_mux[] = {
+ {OFFSET(porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)},
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ configure_module_pin_mux(ddr_pin_mux);
+ configure_module_pin_mux(lcd_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(mii_pin_mux);
+ configure_module_pin_mux(gpio_pin_mux);
+ configure_module_pin_mux(i2c1_pin_mux);
+ configure_module_pin_mux(usb0_pin_mux);
+ configure_module_pin_mux(usb1_pin_mux);
+ configure_module_pin_mux(spi0_pin_mux);
+ configure_module_pin_mux(spi1_pin_mux);
+ configure_module_pin_mux(jtag_pin_mux);
+ configure_module_pin_mux(nand_pin_mux);
+ configure_module_pin_mux(ainx_pin_mux);
+ configure_module_pin_mux(rtc_pin_mux);
+ configure_module_pin_mux(gpmc_pin_mux);
+ configure_module_pin_mux(pmic_pin_mux);
+ configure_module_pin_mux(osc_pin_mux);
+ configure_module_pin_mux(pwm_pin_mux);
+ configure_module_pin_mux(emu_pin_mux);
+ configure_module_pin_mux(vref_pin_mux);
+ configure_module_pin_mux(misc_pin_mux);
+}
- AM335x EVM SK
- Beaglebone White
- Beaglebone Black
-'
+
+Customization
+=============
+
+Given that all of the above boards are reference platforms (and the
+Beaglebone platforms are OSHA), it is likely that this platform code and
+configuration will be used as the basis of a custom platform. It is
+worth noting that aside from things such as NAND or MMC only being
+required if a custom platform makes use of these blocks, the following
+are required, depending on design:
+
+- GPIO is only required if DDR3 power is controlled in a way similar to
+ EVM SK
+- SPI is only required for SPI flash, or exposing the SPI bus.
+
+The following blocks are required:
+- I2C, to talk with the PMIC and ensure that we do not run afoul of
+ errata 1.0.24.
+
+When removing options as part of customization,
+CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your
+needs and to remove no longer relevant options as in some cases we
+define additional text blocks (such as for NAND or DFU strings). Also
+note that all of the SPL options are grouped together, rather than with
+the IP blocks, so both areas will need their choices updated to reflect
+the custom design.
+
NAND
====
DECLARE_GLOBAL_DATA_PTR;
-/* MII mode defines */
-#define MII_MODE_ENABLE 0x0
-#define RGMII_MODE_ENABLE 0x3A
-
/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN 7
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
} else {
- writel(RGMII_MODE_ENABLE, &cdev->miisel);
+ writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_RGMII;
}
#include "mux_data.h"
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ehci.h>
+#include <asm/ehci-omap.h>
+
+#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
+#define DIE_ID_REG_OFFSET 0x200
+
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
const struct omap_sysinfo sysinfo = {
- "Board: OMAP5430 EVM\n"
+ "Board: OMAP5432 uEVM\n"
};
/**
return 0;
}
#endif
+
+#ifdef CONFIG_USB_EHCI
+static struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
+ .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
+};
+
+static void enable_host_clocks(void)
+{
+ int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
+ OPTFCLKEN_HSIC480M_P3_CLK |
+ OPTFCLKEN_HSIC60M_P2_CLK |
+ OPTFCLKEN_HSIC480M_P2_CLK |
+ OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
+
+ /* Enable port 2 and 3 clocks*/
+ setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
+
+ /* Enable port 2 and 3 usb host ports tll clocks*/
+ setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
+ (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
+}
+
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ int ret;
+ int auxclk;
+ int reg;
+ uint8_t device_mac[6];
+
+ enable_host_clocks();
+
+ if (!getenv("usbethaddr")) {
+ reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
+
+ /*
+ * create a fake MAC address from the processor ID code.
+ * first byte is 0x02 to signify locally administered.
+ */
+ device_mac[0] = 0x02;
+ device_mac[1] = readl(reg + 0x10) & 0xff;
+ device_mac[2] = readl(reg + 0xC) & 0xff;
+ device_mac[3] = readl(reg + 0x8) & 0xff;
+ device_mac[4] = readl(reg) & 0xff;
+ device_mac[5] = (readl(reg) >> 8) & 0xff;
+
+ eth_setenv_enetaddr("usbethaddr", device_mac);
+ }
+
+ auxclk = readl((*prcm)->scrm_auxclk1);
+ /* Request auxilary clock */
+ auxclk |= AUXCLK_ENABLE_MASK;
+ writel(auxclk, (*prcm)->scrm_auxclk1);
+
+ ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+ if (ret < 0) {
+ puts("Failed to initialize ehci\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+ int ret;
+
+ ret = omap_ehci_hcd_stop();
+ return ret;
+}
+
+void usb_hub_reset_devices(int port)
+{
+ /* The LAN9730 needs to be reset after the port power has been set. */
+ if (port == 3) {
+ gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
+ udelay(10);
+ gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
+ }
+}
+#endif
{USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */
{I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */
{I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */
-
+ {HSI2_ACWAKE, (PTU | M6)}, /* HSI2_ACWAKE */
+ {HSI2_CAFLAG, (PTU | M6)}, /* HSI2_CAFLAG */
};
const struct pad_conf_entry wkup_padconf_array_essential[] = {
{SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
{SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
{SYS_32K, (IEN | M0)}, /* SYS_32K */
+ {FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */
};
{
gpmc_init();
- gd->bd->bi_arch_number = MACH_TYPE_OMAP_4430SDP;
gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
return 0;
sizeof(wkup_padconf_array_essential) /
sizeof(struct pad_conf_entry));
- if (omap_revision() >= OMAP4460_ES1_0)
+ if ((omap_revision() >= OMAP4460_ES1_0) &&
+ (omap_revision() < OMAP4470_ES1_0))
do_set_mux((*ctrl)->control_padconf_wkup_base,
wkup_padconf_array_essential_4460,
sizeof(wkup_padconf_array_essential_4460) /
{
u32 ret = 0;
+#ifdef CONFIG_XILINX_AXIEMAC
+ ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
+ XILINX_AXIDMA_BASEADDR);
+#endif
+#ifdef CONFIG_XILINX_EMACLITE
+ u32 txpp = 0;
+ u32 rxpp = 0;
+# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
+ txpp = 1;
+# endif
+# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
+ rxpp = 1;
+# endif
+ ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
+ txpp, rxpp);
+#endif
+
#if defined(CONFIG_ZYNQ_GEM)
# if defined(CONFIG_ZYNQ_GEM0)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ zynq_ddrc_init();
+
return 0;
}
# #define CONFIG_HAS_BAR 1
# #define CONFIG_BAZ 64
#
-# The list should be ordered according to the following fields,
-# from most to least significant:
-#
-# ARCH, CPU, SoC, Vendor, Target
-#
-# To keep the list sorted, use something like
-# :.,$! sort -bdf -k2,2 -k3,3 -k6,6 -k5,5 -k1,1
+# The maintainers field lists the e-mail addresses of the board's
+# maintainers, separated by colons. NOTE: there are spaces in this field!
+# For any board without permanent maintainer, please contact
+# Wolfgang Denk <wd@denx.de>
+# And Cc: the <u-boot@lists.denx.de> mailing list.
+
+# The list should be ordered according to the C locale.
#
-# To reformat the list, use something like
-# :.,$! column -t
+# To keep the list formatted and sorted, script tools/reformat.py is available.
+# It can be used from a shell:
+# tools/reformat.py -i -d '-' -s 8 <boards.cfg >boards0.cfg && mv boards0.cfg boards.cfg
+# It can directly be invoked from vim:
+# :%tools/reformat.py -i -d '-' -s 8
#
-# Target ARCH CPU Board name Vendor SoC Options
+# Status, Arch, CPU:SPLCPU, SoC, Vendor, Board name, Target, Options, Maintainers
###########################################################################################################
-integratorcp_cm1136 arm arm1136 integrator armltd - integratorcp:CM1136
-imx31_phycore arm arm1136 - - mx31
-imx31_phycore_eet arm arm1136 imx31_phycore - mx31 imx31_phycore:IMX31_PHYCORE_EET
-qong arm arm1136 - davedenx mx31
-mx31ads arm arm1136 - freescale mx31
-mx31pdk arm arm1136 - freescale mx31
-tt01 arm arm1136 - hale mx31
-imx31_litekit arm arm1136 - logicpd mx31
-flea3 arm arm1136 - CarMediaLab mx35
-mx35pdk arm arm1136 - freescale mx35
-woodburn arm arm1136 - - mx35
-woodburn_sd arm arm1136 woodburn - mx35 woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg
-tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
-rpi_b arm arm1176 rpi_b raspberrypi bcm2835
-integratorap_cm720t arm arm720t integrator armltd - integratorap:CM720T
-integratorap_cm920t arm arm920t integrator armltd - integratorap:CM920T
-integratorcp_cm920t arm arm920t integrator armltd - integratorcp:CM920T
-a320evb arm arm920t - faraday a320
-at91rm9200ek arm arm920t at91rm9200ek atmel at91 at91rm9200ek
-at91rm9200ek_ram arm arm920t at91rm9200ek atmel at91 at91rm9200ek:RAMBOOT
-eb_cpux9k2 arm arm920t eb_cpux9k2 BuS at91 eb_cpux9k2
-eb_cpux9k2_ram arm arm920t eb_cpux9k2 BuS at91 eb_cpux9k2:RAMBOOT
-cpuat91 arm arm920t cpuat91 eukrea at91 cpuat91
-cpuat91_ram arm arm920t cpuat91 eukrea at91 cpuat91:RAMBOOT
-mx1ads arm arm920t - - imx
-scb9328 arm arm920t - - imx
-cm4008 arm arm920t - - ks8695
-cm41xx arm arm920t - - ks8695
-mini2440 arm arm920t mini2440 friendlyarm s3c24x0
-VCMA9 arm arm920t vcma9 mpl s3c24x0
-smdk2410 arm arm920t - samsung s3c24x0
-omap1510inn arm arm925t - ti
-integratorap_cm926ejs arm arm926ejs integrator armltd - integratorap:CM926EJ_S
-integratorcp_cm926ejs arm arm926ejs integrator armltd - integratorcp:CM924EJ_S
-aspenite arm arm926ejs - Marvell armada100
-gplugd arm arm926ejs - Marvell armada100
-afeb9260 arm arm926ejs - - at91
-at91sam9260ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0
-at91sam9260ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1
-at91sam9260ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH
-at91sam9261ek_dataflash_cs0 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS0
-at91sam9261ek_dataflash_cs3 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS3
-at91sam9261ek_nandflash arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9261,SYS_USE_NANDFLASH
-at91sam9263ek_dataflash arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH
-at91sam9263ek_dataflash_cs0 arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH
-at91sam9263ek_nandflash arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_NANDFLASH
-at91sam9263ek_norflash arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH
-at91sam9263ek_norflash_boot arm arm926ejs at91sam9263ek atmel at91 at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH
-at91sam9g10ek_dataflash_cs0 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS0
-at91sam9g10ek_dataflash_cs3 arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS3
-at91sam9g10ek_nandflash arm arm926ejs at91sam9261ek atmel at91 at91sam9261ek:AT91SAM9G10,SYS_USE_NANDFLASH
-at91sam9g20ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0
-at91sam9g20ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1
-at91sam9g20ek_mmc arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_MMC
-at91sam9g20ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH
-at91sam9g20ek_2mmc_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH
-at91sam9m10g45ek_nandflash arm arm926ejs at91sam9m10g45ek atmel at91 at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH
-at91sam9rlek_dataflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH
-at91sam9rlek_nandflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH
-at91sam9x5ek_nandflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH
-at91sam9x5ek_dataflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_DATAFLASH
-at91sam9x5ek_spiflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH
-at91sam9x5ek_mmc arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC
-at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0
-at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1
-at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH
-at91sam9n12ek_nandflash arm arm926ejs at91sam9n12ek atmel at91 at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH
-at91sam9n12ek_spiflash arm arm926ejs at91sam9n12ek atmel at91 at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH
-at91sam9n12ek_mmc arm arm926ejs at91sam9n12ek atmel at91 at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC
-snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260
-snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20
-vl_ma2sc arm arm926ejs vl_ma2sc BuS at91
-vl_ma2sc_ram arm arm926ejs vl_ma2sc BuS at91 vl_ma2sc:RAMLOAD
-sbc35_a9g20_eeprom arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM
-sbc35_a9g20_nandflash arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH
-tny_a9260_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_EEPROM
-tny_a9260_nandflash arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH
-tny_a9g20_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9G20,SYS_USE_EEPROM
-tny_a9g20_nandflash arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH
-ethernut5 arm arm926ejs ethernut5 egnite at91 ethernut5:AT91SAM9XE
-top9000eval_xe arm arm926ejs top9000 emk at91 top9000:EVAL9000
-top9000su_xe arm arm926ejs top9000 emk at91 top9000:SU9000
-meesc arm arm926ejs meesc esd at91 meesc:AT91SAM9263,SYS_USE_NANDFLASH
-meesc_dataflash arm arm926ejs meesc esd at91 meesc:AT91SAM9263,SYS_USE_DATAFLASH
-otc570 arm arm926ejs otc570 esd at91 otc570:AT91SAM9263,SYS_USE_NANDFLASH
-otc570_dataflash arm arm926ejs otc570 esd at91 otc570:AT91SAM9263,SYS_USE_DATAFLASH
-cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260
-cpu9260_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,CPU9260_128M
-cpu9260_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,NANDBOOT
-cpu9260_nand_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,CPU9260_128M,NANDBOOT
-cpu9G20 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20
-cpu9G20_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,CPU9G20_128M
-cpu9G20_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,NANDBOOT
-cpu9G20_nand_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT
-pm9261 arm arm926ejs pm9261 ronetix at91 pm9261:AT91SAM9261
-pm9263 arm arm926ejs pm9263 ronetix at91 pm9263:AT91SAM9263
-pm9g45 arm arm926ejs pm9g45 ronetix at91 pm9g45:AT91SAM9G45
-portuxg20 arm arm926ejs stamp9g20 taskit at91 stamp9g20:AT91SAM9G20,PORTUXG20
-stamp9g20 arm arm926ejs stamp9g20 taskit at91 stamp9g20:AT91SAM9G20
-cam_enc_4xx arm arm926ejs cam_enc_4xx ait davinci cam_enc_4xx
-ipam390 arm arm926ejs ipam390 Barix davinci
-da830evm arm arm926ejs da8xxevm davinci davinci
-da850_am18xxevm arm arm926ejs da8xxevm davinci davinci da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50
-da850evm arm arm926ejs da8xxevm davinci davinci da850evm:MAC_ADDR_IN_SPIFLASH
-da850evm_direct_nor arm arm926ejs da8xxevm davinci davinci da850evm:MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT
-davinci_dm355evm arm arm926ejs dm355evm davinci davinci
-davinci_dm355leopard arm arm926ejs dm355leopard davinci davinci
-davinci_dm365evm arm arm926ejs dm365evm davinci davinci
-davinci_dm6467evm arm arm926ejs dm6467evm davinci davinci davinci_dm6467evm:REFCLK_FREQ=27000000
-davinci_dm6467Tevm arm arm926ejs dm6467evm davinci davinci davinci_dm6467evm:DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000
-davinci_dvevm arm arm926ejs dvevm davinci davinci
-davinci_schmoogie arm arm926ejs schmoogie davinci davinci
-davinci_sffsdr arm arm926ejs sffsdr davinci davinci
-davinci_sonata arm arm926ejs sonata davinci davinci
-ea20 arm arm926ejs ea20 davinci davinci
-hawkboard arm arm926ejs da8xxevm davinci davinci
-hawkboard_uart arm arm926ejs da8xxevm davinci davinci hawkboard:UART_U_BOOT
-enbw_cmc arm arm926ejs enbw_cmc enbw davinci
-calimain arm arm926ejs calimain omicron davinci
-pogo_e02 arm arm926ejs - cloudengines kirkwood
-dns325 arm arm926ejs - d-link kirkwood
-iconnect arm arm926ejs - iomega kirkwood
-lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2
-lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL
-km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD
-km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI
-kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA
-kmsuv31 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_SUV31
-mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN
-kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN
-portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2
-d2net_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:D2NET_V2
-inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2
-net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2
-netspace_lite_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_LITE_V2
-netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2
-netspace_mini_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MINI_V2
-netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_V2
-wireless_space arm arm926ejs wireless_space LaCie kirkwood
-dreamplug arm arm926ejs - Marvell kirkwood
-guruplug arm arm926ejs - Marvell kirkwood
-mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood
-openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE
-openrd_client arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_CLIENT
-openrd_ultimate arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_ULTIMATE
-rd6281a arm arm926ejs - Marvell kirkwood
-sheevaplug arm arm926ejs - Marvell kirkwood
-ib62x0 arm arm926ejs ib62x0 raidsonic kirkwood
-dockstar arm arm926ejs - Seagate kirkwood
-goflexhome arm arm926ejs - Seagate kirkwood
-tk71 arm arm926ejs tk71 karo kirkwood
-devkit3250 arm arm926ejs devkit3250 timll lpc32xx
-jadecpu arm arm926ejs jadecpu syteco mb86r0x
-mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg
-tx25 arm arm926ejs tx25 karo mx25
-zmx25 arm arm926ejs zmx25 syteco mx25
-imx27lite arm arm926ejs imx27lite logicpd mx27
-magnesium arm arm926ejs imx27lite logicpd mx27
-mx23_olinuxino arm arm926ejs mx23_olinuxino olimex mxs mx23_olinuxino
-apx4devkit arm arm926ejs apx4devkit bluegiga mxs apx4devkit
-mx23evk arm arm926ejs mx23evk freescale mxs mx23evk
-m28evk arm arm926ejs m28evk denx mxs m28evk
-mx28evk arm arm926ejs mx28evk freescale mxs mx28evk:ENV_IS_IN_MMC
-mx28evk_nand arm arm926ejs mx28evk freescale mxs mx28evk:ENV_IS_IN_NAND
-sc_sps_1 arm arm926ejs sc_sps_1 schulercontrol mxs
-nhk8815 arm arm926ejs nhk8815 st nomadik
-nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND
-omap5912osk arm arm926ejs - ti omap
-omap730p2 arm arm926ejs omap730p2 ti omap omap730p2:CS3_BOOT
-omap730p2_cs0boot arm arm926ejs omap730p2 ti omap omap730p2:CS0_BOOT
-omap730p2_cs3boot arm arm926ejs omap730p2 ti omap omap730p2:CS3_BOOT
-edminiv2 arm arm926ejs - LaCie orion5x
-dkb arm arm926ejs - Marvell pantheon
-spear300 arm arm926ejs spear300 spear spear spear3xx_evb:spear300
-spear300_nand arm arm926ejs spear300 spear spear spear3xx_evb:spear300,nand
-spear300_usbtty arm arm926ejs spear300 spear spear spear3xx_evb:spear300,usbtty
-spear300_usbtty_nand arm arm926ejs spear300 spear spear spear3xx_evb:spear300,usbtty,nand
-spear310 arm arm926ejs spear310 spear spear spear3xx_evb:spear310
-spear310_pnor arm arm926ejs spear310 spear spear spear3xx_evb:spear310,FLASH_PNOR
-spear310_nand arm arm926ejs spear310 spear spear spear3xx_evb:spear310,nand
-spear310_usbtty arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty
-spear310_usbtty_pnor arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty,FLASH_PNOR
-spear310_usbtty_nand arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty,nand
-spear320 arm arm926ejs spear320 spear spear spear3xx_evb:spear320
-spear320_pnor arm arm926ejs spear320 spear spear spear3xx_evb:spear320,FLASH_PNOR
-spear320_nand arm arm926ejs spear320 spear spear spear3xx_evb:spear320,nand
-spear320_usbtty arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty
-spear320_usbtty_pnor arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty,FLASH_PNOR
-spear320_usbtty_nand arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty,nand
-spear600 arm arm926ejs spear600 spear spear spear6xx_evb:spear600
-spear600_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,nand
-spear600_usbtty arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty
-spear600_usbtty_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty,nand
-x600 arm arm926ejs - spear spear x600
-versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB
-versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB
-versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB
-integratorap_cm946es arm arm946es integrator armltd - integratorap:CM946ES
-integratorcp_cm946es arm arm946es integrator armltd - integratorcp:CM946ES
-vexpress_ca15_tc2 arm armv7 vexpress armltd
-vexpress_ca5x2 arm armv7 vexpress armltd
-vexpress_ca9x4 arm armv7 vexpress armltd
-am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NAND
-am335x_evm_nor arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR
-am335x_evm_norboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT
-am335x_evm_spiboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT
-am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=1,NAND
-am335x_evm_uart2 arm armv7 am335x ti am33xx am335x_evm:SERIAL3,CONS_INDEX=1,NAND
-am335x_evm_uart3 arm armv7 am335x ti am33xx am335x_evm:SERIAL4,CONS_INDEX=1,NAND
-am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=1,NAND
-am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=1,NAND
-am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT
-am335x_boneblack arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT
-am43xx_evm arm armv7 am43xx ti am33xx am43xx_evm:SERIAL1,CONS_INDEX=1
-ti814x_evm arm armv7 ti814x ti am33xx
-ti816x_evm arm armv7 ti816x ti am33xx
-pcm051 arm armv7 pcm051 phytec am33xx pcm051
-sama5d3xek_mmc arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_MMC
-sama5d3xek_nandflash arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH
-sama5d3xek_spiflash arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH
-highbank arm armv7 highbank - highbank
-m53evk arm armv7 m53evk denx mx5 m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg
-mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
-mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
-mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
-mx53ard arm armv7 mx53ard freescale mx5 mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg
-mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg
-mx53loco arm armv7 mx53loco freescale mx5 mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg
-mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg
-ima3-mx53 arm armv7 ima3-mx53 esg mx5 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg
-vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
-cgtqmx6qeval arm armv7 cgtqmx6eval congatec mx6 cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
-mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
-mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q
-mx6qsabrelite arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE
-mx6dlsabresd arm armv7 mx6sabresd freescale mx6 mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL
-mx6qsabresd arm armv7 mx6sabresd freescale mx6 mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
-mx6slevk arm armv7 mx6slevk freescale mx6 mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL
-titanium arm armv7 titanium freescale mx6 titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg
-vf610twr arm armv7 vf610twr freescale vf610 vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg
-eco5pk arm armv7 eco5pk 8dtech omap3
-nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
-nitrogen6dl2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048
-nitrogen6q arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024
-nitrogen6q2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048
-nitrogen6s arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512
-nitrogen6s1g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024
-wandboard_dl arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
-wandboard_quad arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048
-wandboard_solo arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512
-omap3_overo arm armv7 overo - omap3
-omap3_pandora arm armv7 pandora - omap3
-dig297 arm armv7 dig297 comelit omap3
-cm_t35 arm armv7 cm_t35 compulab omap3
-igep0020 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND
-igep0020_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND
-igep0030 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND
-igep0030_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND
-igep0032 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND
-igep0033 arm armv7 igep0033 isee am33xx
-am3517_evm arm armv7 am3517evm logicpd omap3
-mt_ventoux arm armv7 mt_ventoux teejet omap3
-omap3_zoom1 arm armv7 zoom1 logicpd omap3
-omap3_zoom2 arm armv7 zoom2 logicpd omap3
-omap3_logic arm armv7 omap3som logicpd omap3
-omap3_mvblx arm armv7 mvblx matrix_vision omap3
-am3517_crane arm armv7 am3517crane ti omap3
-omap3_beagle arm armv7 beagle ti omap3
-omap3_evm arm armv7 evm ti omap3
-omap3_evm_quick_mmc arm armv7 evm ti omap3
-omap3_evm_quick_nand arm armv7 evm ti omap3
-omap3_sdp3430 arm armv7 sdp3430 ti omap3
-devkit8000 arm armv7 devkit8000 timll omap3
-mcx arm armv7 mcx htkw omap3
-tricorder arm armv7 tricorder corscience omap3
-twister arm armv7 twister technexion omap3
-nokia_rx51 arm armv7 rx51 nokia omap3
-omap4_panda arm armv7 panda ti omap4
-omap4_sdp4430 arm armv7 sdp4430 ti omap4
-omap5_uevm arm armv7 omap5_uevm ti omap5
-dra7xx_evm arm armv7 dra7xx ti omap5
-s5p_goni arm armv7 goni samsung s5pc1xx
-smdkc100 arm armv7 smdkc100 samsung s5pc1xx
-origen arm armv7 origen samsung exynos
-s5pc210_universal arm armv7 universal_c210 samsung exynos
-snow arm armv7 smdk5250 samsung exynos
-smdk5250 arm armv7 smdk5250 samsung exynos
-smdkv310 arm armv7 smdkv310 samsung exynos
-trats arm armv7 trats samsung exynos
-harmony arm armv7:arm720t harmony nvidia tegra20
-seaboard arm armv7:arm720t seaboard nvidia tegra20
-ventana arm armv7:arm720t ventana nvidia tegra20
-whistler arm armv7:arm720t whistler nvidia tegra20
-cardhu arm armv7:arm720t cardhu nvidia tegra30
-beaver arm armv7:arm720t beaver nvidia tegra30
-dalmore arm armv7:arm720t dalmore nvidia tegra114
-colibri_t20_iris arm armv7:arm720t colibri_t20_iris toradex tegra20
-u8500_href arm armv7 u8500 st-ericsson u8500
-snowball arm armv7 snowball st-ericsson u8500
-kzm9g arm armv7 kzm9g kmc rmobile
-armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile
-zynq arm armv7 zynq xilinx zynq
-zynq_dcc arm armv7 zynq xilinx zynq zynq:ZYNQ_DCC
-socfpga_cyclone5 arm armv7 socfpga altera socfpga
-actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2
-actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB
-actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8
-actux1_8_32 arm ixp actux1 - - actux1:FLASH1X8,RAM_32MB
-actux2 arm ixp
-actux3 arm ixp
-actux4 arm ixp
-dvlhost arm ixp
-pdnb3 arm ixp pdnb3 prodrive
-scpu arm ixp pdnb3 prodrive - pdnb3:SCPU
-balloon3 arm pxa
-h2200 arm pxa
-lp8x4x arm pxa lp8x4x icpdas
-lubbock arm pxa
-palmld arm pxa
-palmtc arm pxa
-palmtreo680 arm pxa
-polaris arm pxa trizepsiv - - trizepsiv:POLARIS
-pxa255_idp arm pxa
-trizepsiv arm pxa
-vpac270_nor_128 arm pxa vpac270 - - vpac270:NOR,RAM_128M
-vpac270_nor_256 arm pxa vpac270 - - vpac270:NOR,RAM_256M
-vpac270_ond_256 arm pxa vpac270 - - vpac270:ONENAND,RAM_256M
-xaeniax arm pxa
-zipitz2 arm pxa
-colibri_pxa270 arm pxa - toradex
-jornada arm sa1100
-plutux arm armv7:arm720t plutux avionic-design tegra20
-medcom-wide arm armv7:arm720t medcom-wide avionic-design tegra20
-tec arm armv7:arm720t tec avionic-design tegra20
-paz00 arm armv7:arm720t paz00 compal tegra20
-trimslice arm armv7:arm720t trimslice compulab tegra20
-atngw100 avr32 at32ap - atmel at32ap700x
-atngw100mkii avr32 at32ap - atmel at32ap700x
-atstk1002 avr32 at32ap atstk1000 atmel at32ap700x
-atstk1003 avr32 at32ap atstk1000 atmel at32ap700x
-atstk1004 avr32 at32ap atstk1000 atmel at32ap700x
-atstk1006 avr32 at32ap atstk1000 atmel at32ap700x
-favr-32-ezkit avr32 at32ap - earthlcd at32ap700x
-grasshopper avr32 at32ap - in-circuit at32ap700x
-mimc200 avr32 at32ap - mimc at32ap700x
-hammerhead avr32 at32ap - miromico at32ap700x
-bct-brettl2 blackfin blackfin
-bf506f-ezkit blackfin blackfin
-bf518f-ezbrd blackfin blackfin
-bf525-ucr2 blackfin blackfin
-bf526-ezbrd blackfin blackfin
-bf527-ad7160-eval blackfin blackfin
-bf527-ezkit blackfin blackfin
-bf527-ezkit-v2 blackfin blackfin bf527-ezkit - - bf527-ezkit:BF527_EZKIT_REV_2_1
-bf527-sdp blackfin blackfin
-bf533-ezkit blackfin blackfin
-bf533-stamp blackfin blackfin
-bf537-minotaur blackfin blackfin
-bf537-pnav blackfin blackfin
-bf537-srv1 blackfin blackfin
-bf537-stamp blackfin blackfin
-bf538f-ezkit blackfin blackfin
-bf548-ezkit blackfin blackfin
-bf561-acvilon blackfin blackfin
-bf561-ezkit blackfin blackfin
-bf609-ezkit blackfin blackfin
-blackstamp blackfin blackfin
-blackvme blackfin blackfin
-br4 blackfin blackfin
-cm-bf527 blackfin blackfin
-cm-bf533 blackfin blackfin
-cm-bf537e blackfin blackfin
-cm-bf537u blackfin blackfin
-cm-bf548 blackfin blackfin
-cm-bf561 blackfin blackfin
-dnp5370 blackfin blackfin
-ibf-dsp561 blackfin blackfin
-ip04 blackfin blackfin
-pr1 blackfin blackfin
-tcm-bf518 blackfin blackfin
-tcm-bf537 blackfin blackfin
-M52277EVB m68k mcf5227x m52277evb freescale - M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000
-M52277EVB_stmicro m68k mcf5227x m52277evb freescale - M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000
-M5235EVB m68k mcf523x m5235evb freescale - M5235EVB:SYS_TEXT_BASE=0xFFE00000
-M5235EVB_Flash32 m68k mcf523x m5235evb freescale - M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000
-cobra5272 m68k mcf52x2 cobra5272 -
-idmr m68k mcf52x2
-eb_cpu5282 m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400
-eb_cpu5282_internal m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418
-TASREG m68k mcf52x2 tasreg esd
-M5208EVBE m68k mcf52x2 m5208evbe freescale
-M5249EVB m68k mcf52x2 m5249evb freescale
-M5253DEMO m68k mcf52x2 m5253demo freescale
-M5253EVBE m68k mcf52x2 m5253evbe freescale
-M5271EVB m68k mcf52x2 m5271evb freescale
-M5272C3 m68k mcf52x2 m5272c3 freescale
-M5275EVB m68k mcf52x2 m5275evb freescale
-M5282EVB m68k mcf52x2 m5282evb freescale
-astro_mcf5373l m68k mcf532x mcf5373l astro
-M53017EVB m68k mcf532x m53017evb freescale
-M5329AFEE m68k mcf532x m5329evb freescale - M5329EVB:NANDFLASH_SIZE=0
-M5329BFEE m68k mcf532x m5329evb freescale - M5329EVB:NANDFLASH_SIZE=16
-M5373EVB m68k mcf532x m5373evb freescale - M5373EVB:NANDFLASH_SIZE=16
-M54418TWR m68k mcf5445x m54418twr freescale - M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000
-M54418TWR_nand_mii m68k mcf5445x m54418twr freescale - M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000
-M54418TWR_nand_rmii m68k mcf5445x m54418twr freescale - M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000
-M54418TWR_nand_rmii_lowfreq m68k mcf5445x m54418twr freescale - M54418TWR:SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000
-M54418TWR_serial_mii m68k mcf5445x m54418twr freescale - M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000
-M54418TWR_serial_rmii m68k mcf5445x m54418twr freescale - M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000
-M54451EVB m68k mcf5445x m54451evb freescale - M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000
-M54451EVB_stmicro m68k mcf5445x m54451evb freescale - M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000
-M54455EVB m68k mcf5445x m54455evb freescale - M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333
-M54455EVB_a66 m68k mcf5445x m54455evb freescale - M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666
-M54455EVB_i66 m68k mcf5445x m54455evb freescale - M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666
-M54455EVB_intel m68k mcf5445x m54455evb freescale - M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333
-M54455EVB_stm33 m68k mcf5445x m54455evb freescale - M54455EVB:SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333
-M5475AFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64
-M5475BFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16
-M5475CFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL
-M5475DFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL
-M5475EFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL
-M5475FFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64
-M5475GFE m68k mcf547x_8x m547xevb freescale - M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64
-M5485AFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64
-M5485BFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16
-M5485CFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL
-M5485DFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL
-M5485EFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL
-M5485FFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64
-M5485GFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64
-M5485HFE m68k mcf547x_8x m548xevb freescale - M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO
-microblaze-generic microblaze microblaze microblaze-generic xilinx
-qemu_mips mips mips32 qemu-mips - - qemu-mips:SYS_BIG_ENDIAN
-qemu_mipsel mips mips32 qemu-mips - - qemu-mips:SYS_LITTLE_ENDIAN
-qemu_mips64 mips mips64 qemu-mips - - qemu-mips64:SYS_BIG_ENDIAN
-qemu_mips64el mips mips64 qemu-mips - - qemu-mips64:SYS_LITTLE_ENDIAN
-qemu_malta mips mips32 qemu-malta - - qemu-malta:MIPS32,SYS_BIG_ENDIAN
-qemu_maltael mips mips32 qemu-malta - - qemu-malta:MIPS32,SYS_LITTLE_ENDIAN
-vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM
-vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC
-vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
-vct_platinumavc_onenand_small mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
-vct_platinumavc_small mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE
-vct_platinum_onenand mips mips32 vct micronas - vct:VCT_PLATINUM,VCT_ONENAND
-vct_platinum_onenand_small mips mips32 vct micronas - vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE
-vct_platinum_small mips mips32 vct micronas - vct:VCT_PLATINUM,VCT_SMALL_IMAGE
-vct_premium mips mips32 vct micronas - vct:VCT_PREMIUM
-vct_premium_onenand mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_ONENAND
-vct_premium_onenand_small mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE
-vct_premium_small mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_SMALL_IMAGE
-dbau1000 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1000
-dbau1100 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1100
-dbau1500 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1500
-dbau1550 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550
-dbau1550_el mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN
-pb1000 mips mips32 pb1x00 - au1x00 pb1x00:PB1000
-incaip mips mips32 incaip - incaip
-incaip_100MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=100000000
-incaip_133MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=133000000
-incaip_150MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=150000000
-adp-ag101 nds32 n1213 adp-ag101 AndesTech ag101
-adp-ag101p nds32 n1213 adp-ag101p AndesTech ag101
-adp-ag102 nds32 n1213 adp-ag102 AndesTech ag102
-nios2-generic nios2 nios2 nios2-generic altera
-PCI5441 nios2 nios2 pci5441 psyent
-PK1C20 nios2 nios2 pk1c20 psyent
-openrisc-generic openrisc or1200 openrisc-generic openrisc -
-EVB64260 powerpc 74xx_7xx evb64260 - - EVB64260
-EVB64260_750CX powerpc 74xx_7xx evb64260 - - EVB64260
-P3G4 powerpc 74xx_7xx evb64260
-ppmc7xx powerpc 74xx_7xx
-ZUMA powerpc 74xx_7xx evb64260
-ELPPC powerpc 74xx_7xx elppc eltec
-CPCI750 powerpc 74xx_7xx cpci750 esd
-mpc7448hpc2 powerpc 74xx_7xx mpc7448hpc2 freescale
-DB64360 powerpc 74xx_7xx db64360 Marvell
-DB64460 powerpc 74xx_7xx db64460 Marvell
-p3m7448 powerpc 74xx_7xx p3mx prodrive - p3mx:P3M7448
-p3m750 powerpc 74xx_7xx p3mx prodrive - p3mx:P3M750
-pdm360ng powerpc mpc512x
-aria powerpc mpc512x - davedenx
-mecp5123 powerpc mpc512x - esd
-mpc5121ads powerpc mpc512x mpc5121ads freescale
-mpc5121ads_rev2 powerpc mpc512x mpc5121ads freescale - mpc5121ads:MPC5121ADS_REV2
-ac14xx powerpc mpc512x ac14xx ifm
-cmi_mpc5xx powerpc mpc5xx cmi
-PATI powerpc mpc5xx pati mpl
-a3m071 powerpc mpc5xxx a3m071
-a4m072 powerpc mpc5xxx a4m072
-a4m2k powerpc mpc5xxx a3m071 - - a3m071:A4M2K
-BC3450 powerpc mpc5xxx bc3450
-canmb powerpc mpc5xxx
-cm5200 powerpc mpc5xxx
-galaxy5200 powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200
-galaxy5200_LOWBOOT powerpc mpc5xxx galaxy5200 - - galaxy5200:galaxy5200_LOWBOOT
-icecube_5200 powerpc mpc5xxx icecube - - IceCube
-icecube_5200_DDR powerpc mpc5xxx icecube - - IceCube:MPC5200_DDR
-icecube_5200_DDR_LOWBOOT powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR
-icecube_5200_DDR_LOWBOOT08 powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR
-icecube_5200_LOWBOOT powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF000000
-icecube_5200_LOWBOOT08 powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF800000
-inka4x0 powerpc mpc5xxx
-ipek01 powerpc mpc5xxx
-jupiter powerpc mpc5xxx
-Lite5200 powerpc mpc5xxx icecube - - IceCube
-lite5200b powerpc mpc5xxx icecube - - IceCube:MPC5200_DDR,LITE5200B
-lite5200b_LOWBOOT powerpc mpc5xxx icecube - - IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000
-lite5200b_PM powerpc mpc5xxx icecube - - IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM
-Lite5200_LOWBOOT powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF000000
-Lite5200_LOWBOOT08 powerpc mpc5xxx icecube - - IceCube:SYS_TEXT_BASE=0xFF800000
-mcc200 powerpc mpc5xxx mcc200 - - mcc200
-mcc200_COM12 powerpc mpc5xxx mcc200 - - mcc200:CONSOLE_COM12
-mcc200_COM12_highboot powerpc mpc5xxx mcc200 - - mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000
-mcc200_COM12_highboot_SDRAM powerpc mpc5xxx mcc200 - - mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM
-mcc200_COM12_SDRAM powerpc mpc5xxx mcc200 - - mcc200:CONSOLE_COM12,MCC200_SDRAM
-mcc200_highboot powerpc mpc5xxx mcc200 - - mcc200:SYS_TEXT_BASE=0xFFF00000
-mcc200_highboot_SDRAM powerpc mpc5xxx mcc200 - - mcc200:SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM
-mcc200_SDRAM powerpc mpc5xxx mcc200 - - mcc200:MCC200_SDRAM
-motionpro powerpc mpc5xxx
-munices powerpc mpc5xxx
-PM520 powerpc mpc5xxx pm520
-PM520_DDR powerpc mpc5xxx pm520 - - PM520:MPC5200_DDR
-PM520_ROMBOOT powerpc mpc5xxx pm520 - - PM520:BOOT_ROM
-PM520_ROMBOOT_DDR powerpc mpc5xxx pm520 - - PM520:MPC5200_DDR,BOOT_ROM
-prs200 powerpc mpc5xxx mcc200 - - mcc200:PRS200,MCC200_SDRAM
-prs200_DDR powerpc mpc5xxx mcc200 - - mcc200:PRS200
-prs200_highboot powerpc mpc5xxx mcc200 - - mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM
-prs200_highboot_DDR powerpc mpc5xxx mcc200 - - mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000
-Total5200 powerpc mpc5xxx total5200 - - Total5200:TOTAL5200_REV=1
-Total5200_lowboot powerpc mpc5xxx total5200 - - Total5200:TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000
-Total5200_Rev2 powerpc mpc5xxx total5200 - - Total5200:TOTAL5200_REV=2
-Total5200_Rev2_lowboot powerpc mpc5xxx total5200 - - Total5200:TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000
-v38b powerpc mpc5xxx
-EVAL5200 powerpc mpc5xxx top5200 emk - TOP5200:EVAL5200
-MINI5200 powerpc mpc5xxx top5200 emk - TOP5200:MINI5200
-TOP5200 powerpc mpc5xxx top5200 emk - TOP5200:TOP5200
-cpci5200 powerpc mpc5xxx - esd
-mecp5200 powerpc mpc5xxx - esd
-pf5200 powerpc mpc5xxx - esd
-O2D powerpc mpc5xxx o2dnt2 ifm - o2d
-O2D300 powerpc mpc5xxx o2dnt2 ifm - o2d300
-O2DNT2 powerpc mpc5xxx o2dnt2 ifm - o2dnt2
-O2DNT2_RAMBOOT powerpc mpc5xxx o2dnt2 ifm - o2dnt2:SYS_TEXT_BASE=0x00100000
-O2I powerpc mpc5xxx o2dnt2 ifm - o2i
-O2MNT powerpc mpc5xxx o2dnt2 ifm - o2mnt
-O2MNT_O2M110 powerpc mpc5xxx o2dnt2 ifm - o2mnt:IFM_SENSOR_TYPE="O2M110"
-O2MNT_O2M112 powerpc mpc5xxx o2dnt2 ifm - o2mnt:IFM_SENSOR_TYPE="O2M112"
-O2MNT_O2M113 powerpc mpc5xxx o2dnt2 ifm - o2mnt:IFM_SENSOR_TYPE="O2M113"
-O3DNT powerpc mpc5xxx o2dnt2 ifm - o3dnt
-digsy_mtc powerpc mpc5xxx digsy_mtc intercontrol
-digsy_mtc_RAMBOOT powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:SYS_TEXT_BASE=0x00100000
-digsy_mtc_rev5 powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:DIGSY_REV5
-digsy_mtc_rev5_RAMBOOT powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5
-hmi1001 powerpc mpc5xxx - manroland
-mucmc52 powerpc mpc5xxx - manroland
-uc101 powerpc mpc5xxx - manroland
-MVBC_P powerpc mpc5xxx mvbc_p matrix_vision - MVBC_P:MVBC_P
-MVSMR powerpc mpc5xxx mvsmr matrix_vision
-pcm030 powerpc mpc5xxx pcm030 phytec - pcm030
-pcm030_LOWBOOT powerpc mpc5xxx pcm030 phytec - pcm030:SYS_TEXT_BASE=0xFF000000
-aev powerpc mpc5xxx tqm5200 tqc
-cam5200 powerpc mpc5xxx tqm5200 tqc - TQM5200:CAM5200,TQM5200S,TQM5200_B
-cam5200_niosflash powerpc mpc5xxx tqm5200 tqc - TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH
-charon powerpc mpc5xxx tqm5200 tqc - charon
-fo300 powerpc mpc5xxx tqm5200 tqc - TQM5200:FO300
-MiniFAP powerpc mpc5xxx tqm5200 tqc - TQM5200:MINIFAP
-TB5200 powerpc mpc5xxx tqm5200 tqc
-TB5200_B powerpc mpc5xxx tqm5200 tqc - TB5200:TQM5200_B
-TQM5200 powerpc mpc5xxx tqm5200 tqc - TQM5200:
-TQM5200_B powerpc mpc5xxx tqm5200 tqc - TQM5200:TQM5200_B
-TQM5200_B_HIGHBOOT powerpc mpc5xxx tqm5200 tqc - TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000
-TQM5200S powerpc mpc5xxx tqm5200 tqc - TQM5200:TQM5200_B,TQM5200S
-TQM5200S_HIGHBOOT powerpc mpc5xxx tqm5200 tqc - TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000
-TQM5200_STK100 powerpc mpc5xxx tqm5200 tqc - TQM5200:STK52XX_REV100
-A3000 powerpc mpc824x a3000
-CPC45 powerpc mpc824x cpc45 - - CPC45
-CPC45_ROMBOOT powerpc mpc824x cpc45 - - CPC45:BOOT_ROM
-CU824 powerpc mpc824x cu824
-eXalion powerpc mpc824x eXalion
-HIDDEN_DRAGON powerpc mpc824x hidden_dragon
-linkstation_HGLAN powerpc mpc824x linkstation - - linkstation:HGLAN=1
-MOUSSE powerpc mpc824x mousse
-MUSENKI powerpc mpc824x musenki
-MVBLUE powerpc mpc824x mvblue
-PN62 powerpc mpc824x pn62
-Sandpoint8240 powerpc mpc824x sandpoint
-Sandpoint8245 powerpc mpc824x sandpoint
-utx8245 powerpc mpc824x
-debris powerpc mpc824x - etin
-kvme080 powerpc mpc824x - etin
-atc powerpc mpc8260
-cogent_mpc8260 powerpc mpc8260 cogent
-CPU86 powerpc mpc8260 cpu86 - - CPU86
-CPU86_ROMBOOT powerpc mpc8260 cpu86 - - CPU86:BOOT_ROM
-CPU87 powerpc mpc8260 cpu87 - - CPU87
-CPU87_ROMBOOT powerpc mpc8260 cpu87 - - CPU87:BOOT_ROM
-ep8248 powerpc mpc8260 ep8248
-ep8248E powerpc mpc8260 ep8248 - - ep8248
-ep8260 powerpc mpc8260
-ep82xxm powerpc mpc8260
-gw8260 powerpc mpc8260
-hymod powerpc mpc8260
-IDS8247 powerpc mpc8260 ids8247
-IPHASE4539 powerpc mpc8260 iphase4539
-ISPAN powerpc mpc8260 ispan
-ISPAN_REVB powerpc mpc8260 ispan - - ISPAN:SYS_REV_B
-muas3001 powerpc mpc8260 muas3001
-muas3001_dev powerpc mpc8260 muas3001 - - muas3001:MUAS_DEV_BOARD
-PM825 powerpc mpc8260 pm826 - - PM826:PCI,SYS_TEXT_BASE=0xFF000000
-PM825_BIGFLASH powerpc mpc8260 pm826 - - PM826:PCI,FLASH_32MB,SYS_TEXT_BASE=0x40000000
-PM825_ROMBOOT powerpc mpc8260 pm826 - - PM826:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000
-PM825_ROMBOOT_BIGFLASH powerpc mpc8260 pm826 - - PM826:PCI,BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000
-PM826 powerpc mpc8260 pm826 - - PM826:SYS_TEXT_BASE=0xFF000000
-PM826_BIGFLASH powerpc mpc8260 pm826 - - PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000
-PM826_ROMBOOT powerpc mpc8260 pm826 - - PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000
-PM826_ROMBOOT_BIGFLASH powerpc mpc8260 pm826 - - PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000
-PM828 powerpc mpc8260 pm828 - - PM828
-PM828_PCI powerpc mpc8260 pm828 - - PM828:PCI
-PM828_ROMBOOT powerpc mpc8260 pm828 - - PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000
-PM828_ROMBOOT_PCI powerpc mpc8260 pm828 - - PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000
-ppmc8260 powerpc mpc8260
-Rattler powerpc mpc8260 rattler - - Rattler
-Rattler8248 powerpc mpc8260 rattler - - Rattler:MPC8248
-RPXsuper powerpc mpc8260 rpxsuper
-rsdproto powerpc mpc8260
-sacsng powerpc mpc8260
-ZPC1900 powerpc mpc8260 zpc1900
-MPC8260ADS powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS
-MPC8260ADS_33MHz powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000
-MPC8260ADS_33MHz_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000
-MPC8260ADS_40MHz powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000
-MPC8260ADS_40MHz_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000
-MPC8260ADS_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000
-MPC8266ADS powerpc mpc8260 mpc8266ads freescale
-MPC8272ADS powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS
-MPC8272ADS_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000
-PQ2FADS powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS
-PQ2FADS_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000
-PQ2FADS-VR powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000
-PQ2FADS-VR_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000
-PQ2FADS-ZU powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS
-PQ2FADS-ZU_66MHz powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000
-PQ2FADS-ZU_66MHz_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000
-PQ2FADS-ZU_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000
-VoVPN-GW_66MHz powerpc mpc8260 vovpn-gw funkwerk - VoVPN-GW:CLKIN_66MHz
-mgcoge powerpc mpc8260 km82xx keymile - km82xx:MGCOGE
-mgcoge3ne powerpc mpc8260 km82xx keymile - km82xx:MGCOGE3NE
-TQM8255_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8255,300MHz
-TQM8260_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz
-TQM8260_AB powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x
-TQM8260_AC powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x
-TQM8260_AD powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz,BUSMODE_60x
-TQM8260_AE powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,266MHz
-TQM8260_AF powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz,BUSMODE_60x
-TQM8260_AG powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz
-TQM8260_AH powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz,L2_CACHE,BUSMODE_60x
-TQM8260_AI powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,300MHz,BUSMODE_60x
-TQM8265_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8265,300MHz,BUSMODE_60x
-TQM8272 powerpc mpc8260 tqm8272 tqc
-mpc8308_p1m powerpc mpc83xx
-sbc8349 powerpc mpc83xx sbc8349 - - sbc8349
-sbc8349_PCI_33 powerpc mpc83xx sbc8349 - - sbc8349:PCI,PCI_33M
-sbc8349_PCI_66 powerpc mpc83xx sbc8349 - - sbc8349:PCI,PCI_66M
-ve8313 powerpc mpc83xx ve8313
-caddy2 powerpc mpc83xx vme8349 esd - vme8349:CADDY2
-vme8349 powerpc mpc83xx vme8349 esd - vme8349
-MPC8308RDB powerpc mpc83xx mpc8308rdb freescale
-MPC8313ERDB_33 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_33MHZ
-MPC8313ERDB_66 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_66MHZ
-MPC8313ERDB_NAND_33 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_33MHZ,NAND
-MPC8313ERDB_NAND_66 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_66MHZ,NAND
-MPC8315ERDB powerpc mpc83xx mpc8315erdb freescale - MPC8315ERDB
-MPC8315ERDB_NAND powerpc mpc83xx mpc8315erdb freescale - MPC8315ERDB:NAND_U_BOOT
-MPC8323ERDB powerpc mpc83xx mpc8323erdb freescale
-MPC832XEMDS powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:
-MPC832XEMDS_ATM powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1
-MPC832XEMDS_HOST_33 powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1
-MPC832XEMDS_HOST_66 powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1
-MPC832XEMDS_SLAVE powerpc mpc83xx mpc832xemds freescale - MPC832XEMDS:PCI,PCISLAVE
-MPC8349EMDS powerpc mpc83xx mpc8349emds freescale
-MPC8349ITX powerpc mpc83xx mpc8349itx freescale - MPC8349ITX:MPC8349ITX
-MPC8349ITXGP powerpc mpc83xx mpc8349itx freescale - MPC8349ITX:MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000
-MPC8349ITX_LOWBOOT powerpc mpc83xx mpc8349itx freescale - MPC8349ITX:MPC8349ITX,SYS_TEXT_BASE=0xFE000000
-MPC8360EMDS_33 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ
-MPC8360EMDS_33_ATM powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1
-MPC8360EMDS_33_HOST_33 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_33M,PQ_MDS_PIB=1
-MPC8360EMDS_33_HOST_66 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_66M,PQ_MDS_PIB=1
-MPC8360EMDS_33_SLAVE powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_33MHZ,PCI,PCISLAVE
-MPC8360EMDS_66 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ
-MPC8360EMDS_66_ATM powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1
-MPC8360EMDS_66_HOST_33 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1
-MPC8360EMDS_66_HOST_66 powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1
-MPC8360EMDS_66_SLAVE powerpc mpc83xx mpc8360emds freescale - MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE
-MPC8360ERDK powerpc mpc83xx mpc8360erdk freescale - MPC8360ERDK
-MPC8360ERDK_33 powerpc mpc83xx mpc8360erdk freescale - MPC8360ERDK:CLKIN_33MHZ
-MPC8360ERDK_66 powerpc mpc83xx mpc8360erdk freescale - MPC8360ERDK
-MPC837XEMDS powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS
-MPC837XEMDS_HOST powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS:PCI
-MPC837XERDB powerpc mpc83xx mpc837xerdb freescale
-kmcoge5ne powerpc mpc83xx km83xx keymile - km8360:KMCOGE5NE
-kmeter1 powerpc mpc83xx km83xx keymile - km8360:KMETER1
-MERGERBOX powerpc mpc83xx mergerbox matrix_vision
-MVBLM7 powerpc mpc83xx mvblm7 matrix_vision
-SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP
-SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP
-TQM834x powerpc mpc83xx tqm834x tqc
-suvd3 powerpc mpc83xx km83xx keymile - suvd3:SUVD3
-kmvect1 powerpc mpc83xx km83xx keymile - suvd3:KMVECT1
-tuge1 powerpc mpc83xx km83xx keymile - tuxx1:TUGE1
-tuxx1 powerpc mpc83xx km83xx keymile - tuxx1:TUXX1
-kmopti2 powerpc mpc83xx km83xx keymile - tuxx1:KMOPTI2
-kmsupx5 powerpc mpc83xx km83xx keymile - tuxx1:KMSUPX5
-sbc8548 powerpc mpc85xx sbc8548 - - sbc8548
-sbc8548_PCI_33 powerpc mpc85xx sbc8548 - - sbc8548:PCI,33
-sbc8548_PCI_33_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,33,PCIE
-sbc8548_PCI_66 powerpc mpc85xx sbc8548 - - sbc8548:PCI,66
-sbc8548_PCI_66_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,66,PCIE
-socrates powerpc mpc85xx socrates
-HWW1U1A powerpc mpc85xx hww1u1a exmeritus
-MPC8536DS powerpc mpc85xx mpc8536ds freescale - MPC8536DS
-MPC8536DS_36BIT powerpc mpc85xx mpc8536ds freescale - MPC8536DS:36BIT
-MPC8536DS_NAND powerpc mpc85xx mpc8536ds freescale - MPC8536DS:NAND
-MPC8536DS_SDCARD powerpc mpc85xx mpc8536ds freescale - MPC8536DS:SDCARD
-MPC8536DS_SPIFLASH powerpc mpc85xx mpc8536ds freescale - MPC8536DS:SPIFLASH
-MPC8540ADS powerpc mpc85xx mpc8540ads freescale
-MPC8541CDS powerpc mpc85xx mpc8541cds freescale - MPC8541CDS
-MPC8541CDS_legacy powerpc mpc85xx mpc8541cds freescale - MPC8541CDS:LEGACY
-MPC8544DS powerpc mpc85xx mpc8544ds freescale
-MPC8548CDS powerpc mpc85xx mpc8548cds freescale - MPC8548CDS
-MPC8548CDS_36BIT powerpc mpc85xx mpc8548cds freescale - MPC8548CDS:36BIT
-MPC8548CDS_legacy powerpc mpc85xx mpc8548cds freescale - MPC8548CDS:LEGACY
-MPC8555CDS powerpc mpc85xx mpc8555cds freescale - MPC8555CDS
-MPC8555CDS_legacy powerpc mpc85xx mpc8555cds freescale - MPC8555CDS:LEGACY
-MPC8560ADS powerpc mpc85xx mpc8560ads freescale
-MPC8568MDS powerpc mpc85xx mpc8568mds freescale
-MPC8569MDS powerpc mpc85xx mpc8569mds freescale - MPC8569MDS
-MPC8569MDS_ATM powerpc mpc85xx mpc8569mds freescale - MPC8569MDS:ATM
-MPC8569MDS_NAND powerpc mpc85xx mpc8569mds freescale - MPC8569MDS:NAND
-MPC8572DS powerpc mpc85xx mpc8572ds freescale - MPC8572DS
-MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT
-MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND
-C29XPCIE powerpc mpc85xx c29xpcie freescale - C29XPCIE:C29XPCIE,36BIT
-C29XPCIE_SPIFLASH powerpc mpc85xx c29xpcie freescale - C29XPCIE:C29XPCIE,36BIT,SPIFLASH
-P1010RDB_36BIT_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND
-P1010RDB_36BIT_NAND_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND_SECBOOT,SECURE_BOOT
-P1010RDB_36BIT_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT
-P1010RDB_36BIT_NOR_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SECURE_BOOT
-P1010RDB_36BIT_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SDCARD
-P1010RDB_36BIT_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SPIFLASH
-P1010RDB_36BIT_SPIFLASH_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SPIFLASH,SECURE_BOOT
-P1010RDB_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,NAND
-P1010RDB_NAND_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,NAND_SECBOOT,SECURE_BOOT
-P1010RDB_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB
-P1010RDB_NOR_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SECURE_BOOT
-P1010RDB_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SDCARD
-P1010RDB_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SPIFLASH
-P1010RDB_SPIFLASH_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SPIFLASH,SECURE_BOOT
-P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB
-P1011RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT
-P1011RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SDCARD
-P1011RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SPIFLASH
-P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,NAND
-P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SDCARD
-P1011RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SPIFLASH
-P1020MBG-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020MBG
-P1020MBG-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020MBG,36BIT
-P1020MBG-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020MBG,SDCARD,36BIT
-P1020MBG-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020MBG,SDCARD
-P1020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB
-P1020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT
-P1020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SDCARD
-P1020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SPIFLASH
-P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,NAND
-P1020RDB-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC
-P1020RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,36BIT
-P1020RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,36BIT,NAND
-P1020RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,36BIT,SDCARD
-P1020RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,36BIT,SPIFLASH
-P1020RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,NAND
-P1020RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,SDCARD
-P1020RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PC,SPIFLASH
-P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD
-P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH
-P1020RDB-PD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PD
-P1020RDB-PD_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PD,NAND
-P1020RDB-PD_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PD,SDCARD
-P1020RDB-PD_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020RDB_PD,SPIFLASH
-P1020UTM-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM
-P1020UTM-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM,36BIT
-P1020UTM-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD
-P1020UTM-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1020UTM,SDCARD
-P1021RDB-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB
-P1021RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,36BIT
-P1021RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,36BIT,NAND
-P1021RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,36BIT,SDCARD
-P1021RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,36BIT,SPIFLASH
-P1021RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,NAND
-P1021RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SDCARD
-P1021RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SPIFLASH
-P1022DS powerpc mpc85xx p1022ds freescale
-P1022DS_NAND powerpc mpc85xx p1022ds freescale - P1022DS:NAND
-P1022DS_36BIT_NAND powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,NAND
-P1022DS_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:SPIFLASH
-P1022DS_36BIT_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SPIFLASH
-P1022DS_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:SDCARD
-P1022DS_36BIT_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SDCARD
-P1022DS_36BIT powerpc mpc85xx p1022ds freescale - P1022DS:36BIT
-P1023RDB powerpc mpc85xx p1023rdb freescale - P1023RDB
-P1023RDS powerpc mpc85xx p1023rds freescale - P1023RDS
-P1023RDS_NAND powerpc mpc85xx p1023rds freescale - P1023RDS:NAND
-P1024RDB powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB
-P1024RDB_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB,36BIT
-P1024RDB_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB,NAND
-P1024RDB_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB,SDCARD
-P1024RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1024RDB,SPIFLASH
-P1025RDB powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB
-P1025RDB_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,36BIT
-P1025RDB_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,NAND
-P1025RDB_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,SDCARD
-P1025RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1025RDB,SPIFLASH
-TWR-P1025 powerpc mpc85xx p1_twr freescale - p1_twr:TWR_P1025
-P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB
-P2010RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT
-P2010RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SDCARD
-P2010RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SPIFLASH
-P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,NAND
-P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SDCARD
-P2010RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SPIFLASH
-P2020COME_SDCARD powerpc mpc85xx p2020come freescale - P2020COME:SDCARD
-P2020COME_SPIFLASH powerpc mpc85xx p2020come freescale - P2020COME:SPIFLASH
-P2020DS powerpc mpc85xx p2020ds freescale
-P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT
-P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2
-P2020DS_SDCARD powerpc mpc85xx p2020ds freescale - P2020DS:SDCARD
-P2020DS_SPIFLASH powerpc mpc85xx p2020ds freescale - P2020DS:SPIFLASH
-P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB
-P2020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT
-P2020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SDCARD
-P2020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SPIFLASH
-P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND
-P2020RDB-PC powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB
-P2020RDB-PC_36BIT powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT
-P2020RDB-PC_36BIT_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,NAND
-P2020RDB-PC_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD
-P2020RDB-PC_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH
-P2020RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,NAND
-P2020RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,SDCARD
-P2020RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P2020RDB,SPIFLASH
-P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD
-P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH
-P2041RDB powerpc mpc85xx p2041rdb freescale
-P2041RDB_NAND powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
-P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
-P2041RDB_SECURE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SECURE_BOOT
-P2041RDB_SPIFLASH powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
-P2041RDB_SRIO_PCIE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
-P3041DS powerpc mpc85xx corenet_ds freescale
-P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
-P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
-P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT
-P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
-P3041DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
-P4080DS powerpc mpc85xx corenet_ds freescale
-P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
-P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT
-P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
-P4080DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
-P5020DS powerpc mpc85xx corenet_ds freescale
-P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
-P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
-P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT
-P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
-P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
-P5040DS powerpc mpc85xx corenet_ds freescale
-P5040DS_NAND powerpc mpc85xx corenet_ds freescale - P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
-P5040DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
-P5040DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
-BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH
-BSC9131RDB_SPIFLASH_SYSCLK100 powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH,SYS_CLK_100
-BSC9131RDB_NAND powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,NAND
-BSC9131RDB_NAND_SYSCLK100 powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100
-BSC9132QDS_NOR_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100
-BSC9132QDS_NOR_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133
-BSC9132QDS_NAND_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_100
-BSC9132QDS_NAND_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_133
-BSC9132QDS_SDCARD_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100
-BSC9132QDS_SDCARD_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133
-BSC9132QDS_SPIFLASH_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100
-BSC9132QDS_SPIFLASH_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133
-controlcenterd_36BIT_SDCARD powerpc mpc85xx p1022 gdsys - controlcenterd:36BIT,SDCARD
-controlcenterd_36BIT_SDCARD_DEVELOP powerpc mpc85xx p1022 gdsys - controlcenterd:36BIT,SDCARD,DEVELOP
-controlcenterd_TRAILBLAZER powerpc mpc85xx p1022 gdsys - controlcenterd:TRAILBLAZER,SPIFLASH
-controlcenterd_TRAILBLAZER_DEVELOP powerpc mpc85xx p1022 gdsys - controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP
-stxgp3 powerpc mpc85xx stxgp3 stx
-stxssa powerpc mpc85xx stxssa stx - stxssa
-stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M
-T4240QDS powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240
-T4240EMU powerpc mpc85xx t4qds freescale - T4240EMU:PPC_T4240
-T4240QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
-T4240QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
-T4240QDS_SRIO_PCIE_BOOT powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
-T4160QDS powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160
-T4160QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
-T4160QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
-B4860QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860
-B4860QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
-B4860QDS_SPIFLASH powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
-B4860QDS_SRIO_PCIE_BOOT powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
-B4420QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420
-B4420QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
-B4420QDS_SPIFLASH powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
-xpedite520x powerpc mpc85xx - xes
-xpedite537x powerpc mpc85xx - xes
-xpedite550x powerpc mpc85xx - xes
-sbc8641d powerpc mpc86xx
-MPC8610HPCD powerpc mpc86xx mpc8610hpcd freescale
-MPC8641HPCN powerpc mpc86xx mpc8641hpcn freescale - MPC8641HPCN
-MPC8641HPCN_36BIT powerpc mpc86xx mpc8641hpcn freescale - MPC8641HPCN:PHYS_64BIT
-xpedite517x powerpc mpc86xx - xes
-Adder powerpc mpc8xx adder
-Adder87x powerpc mpc8xx adder - - Adder
-AdderII powerpc mpc8xx adder - - Adder:MPC852T
-AdderUSB powerpc mpc8xx adder - - Adder
-ADS860 powerpc mpc8xx fads
-cogent_mpc8xx powerpc mpc8xx cogent
-ESTEEM192E powerpc mpc8xx esteem192e
-FADS823 powerpc mpc8xx fads
-FADS850SAR powerpc mpc8xx fads
-FADS860T powerpc mpc8xx fads
-FLAGADM powerpc mpc8xx flagadm
-GEN860T powerpc mpc8xx gen860t
-GEN860T_SC powerpc mpc8xx gen860t - - GEN860T:SC
-GENIETV powerpc mpc8xx genietv
-hermes powerpc mpc8xx
-ICU862 powerpc mpc8xx icu862
-ICU862_100MHz powerpc mpc8xx icu862 - - ICU862:100MHz
-IP860 powerpc mpc8xx ip860
-IVML24 powerpc mpc8xx ivm - - IVML24:IVML24_16M
-IVML24_128 powerpc mpc8xx ivm - - IVML24:IVML24_32M
-IVML24_256 powerpc mpc8xx ivm - - IVML24:IVML24_64M
-IVMS8 powerpc mpc8xx ivm - - IVMS8:IVMS8_16M
-IVMS8_128 powerpc mpc8xx ivm - - IVMS8:IVMS8_32M
-IVMS8_256 powerpc mpc8xx ivm - - IVMS8:IVMS8_64M
-lwmon powerpc mpc8xx
-MBX powerpc mpc8xx mbx8xx
-MBX860T powerpc mpc8xx mbx8xx
-MPC86xADS powerpc mpc8xx fads
-MPC885ADS powerpc mpc8xx fads
-NETPHONE powerpc mpc8xx netphone - - NETPHONE:NETPHONE_VERSION=1
-NETPHONE_V2 powerpc mpc8xx netphone - - NETPHONE:NETPHONE_VERSION=2
-NETTA powerpc mpc8xx netta - - NETTA
-NETTA2 powerpc mpc8xx netta2 - - NETTA2:NETTA2_VERSION=1
-NETTA2_V2 powerpc mpc8xx netta2 - - NETTA2:NETTA2_VERSION=2
-NETTA_6412 powerpc mpc8xx netta - - NETTA:NETTA_6412=1
-NETTA_6412_SWAPHOOK powerpc mpc8xx netta - - NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1
-NETTA_ISDN powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1
-NETTA_ISDN_6412 powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1,NETTA_6412=1
-NETTA_ISDN_6412_SWAPHOOK powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1,NETTA_6412=1,NETTA_SWAPHOOK=1
-NETTA_ISDN_SWAPHOOK powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1,NETTA_SWAPHOOK=1
-NETTA_SWAPHOOK powerpc mpc8xx netta - - NETTA:NETTA_SWAPHOOK=1
-NETVIA powerpc mpc8xx netvia - - NETVIA:NETVIA_VERSION=1
-NETVIA_V2 powerpc mpc8xx netvia - - NETVIA:NETVIA_VERSION=2
-NX823 powerpc mpc8xx nx823
-quantum powerpc mpc8xx
-R360MPI powerpc mpc8xx r360mpi
-RBC823 powerpc mpc8xx rbc823
-RPXClassic powerpc mpc8xx
-RPXlite powerpc mpc8xx
-RPXlite_DW powerpc mpc8xx RPXlite_dw - - RPXlite_DW
-RPXlite_DW_64 powerpc mpc8xx RPXlite_dw - - RPXlite_DW:RPXlite_64MHz
-RPXlite_DW_64_LCD powerpc mpc8xx RPXlite_dw - - RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20
-RPXlite_DW_LCD powerpc mpc8xx RPXlite_dw - - RPXlite_DW:LCD,NEC_NL6448BC20
-RPXlite_DW_NVRAM powerpc mpc8xx RPXlite_dw - - RPXlite_DW:ENV_IS_IN_NVRAM
-RPXlite_DW_NVRAM_64 powerpc mpc8xx RPXlite_dw - - RPXlite_DW:RPXlite_64MHz,ENV_IS_IN_NVRAM
-RPXlite_DW_NVRAM_64_LCD powerpc mpc8xx RPXlite_dw - - RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM
-RPXlite_DW_NVRAM_LCD powerpc mpc8xx RPXlite_dw - - RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM
-RRvision powerpc mpc8xx
-RRvision_LCD powerpc mpc8xx RRvision - - RRvision:LCD,SHARP_LQ104V7DS01
-spc1920 powerpc mpc8xx
-SPD823TS powerpc mpc8xx spd8xx
-svm_sc8xx powerpc mpc8xx
-SXNI855T powerpc mpc8xx sixnet
-v37 powerpc mpc8xx
-MHPC powerpc mpc8xx mhpc eltec
-TOP860 powerpc mpc8xx top860 emk
-KUP4K powerpc mpc8xx kup4k kup
-KUP4X powerpc mpc8xx kup4x kup
-ELPT860 powerpc mpc8xx elpt860 LEOX
-uc100 powerpc mpc8xx - manroland
-QS823 powerpc mpc8xx qs850 snmc
-QS850 powerpc mpc8xx qs850 snmc
-QS860T powerpc mpc8xx qs860t snmc
-stxxtc powerpc mpc8xx stxxtc stx
-FPS850L powerpc mpc8xx tqm8xx tqc
-FPS860L powerpc mpc8xx tqm8xx tqc
-NSCU powerpc mpc8xx tqm8xx tqc
-SM850 powerpc mpc8xx tqm8xx tqc
-TK885D powerpc mpc8xx tqm8xx tqc
-TQM823L powerpc mpc8xx tqm8xx tqc
-TQM823L_LCD powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,NEC_NL6448BC20
-TQM823M powerpc mpc8xx tqm8xx tqc
-TQM850L powerpc mpc8xx tqm8xx tqc
-TQM850M powerpc mpc8xx tqm8xx tqc
-TQM855L powerpc mpc8xx tqm8xx tqc
-TQM855M powerpc mpc8xx tqm8xx tqc
-TQM860L powerpc mpc8xx tqm8xx tqc
-TQM860M powerpc mpc8xx tqm8xx tqc
-TQM862L powerpc mpc8xx tqm8xx tqc
-TQM862M powerpc mpc8xx tqm8xx tqc
-TQM866M powerpc mpc8xx tqm8xx tqc
-TQM885D powerpc mpc8xx tqm8xx tqc
-TTTech powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,SHARP_LQ104V7DS01
-virtlab2 powerpc mpc8xx tqm8xx tqc
-wtk powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,SHARP_LQ065T9DR51U
-csb272 powerpc ppc4xx
-csb472 powerpc ppc4xx
-G2000 powerpc ppc4xx g2000
-JSE powerpc ppc4xx jse
-korat powerpc ppc4xx
-korat_perm powerpc ppc4xx korat - - korat:KORAT_PERMANENT
-lwmon5 powerpc ppc4xx
-lcd4_lwmon5 powerpc ppc4xx lwmon5 - - lwmon5:LCD4_LWMON5
-pcs440ep powerpc ppc4xx
-quad100hd powerpc ppc4xx
-sbc405 powerpc ppc4xx
-sc3 powerpc ppc4xx
-t3corp powerpc ppc4xx
-W7OLMC powerpc ppc4xx w7o
-W7OLMG powerpc ppc4xx w7o
-zeus powerpc ppc4xx
-acadia powerpc ppc4xx - amcc
-acadia_nand powerpc ppc4xx acadia amcc - acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
-arches powerpc ppc4xx canyonlands amcc - canyonlands:ARCHES
-bamboo powerpc ppc4xx - amcc
-bamboo_nand powerpc ppc4xx bamboo amcc - bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
-bluestone powerpc ppc4xx - amcc
-bubinga powerpc ppc4xx - amcc
-canyonlands powerpc ppc4xx canyonlands amcc - canyonlands:CANYONLANDS
-canyonlands_nand powerpc ppc4xx canyonlands amcc - canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
-ebony powerpc ppc4xx - amcc
-glacier powerpc ppc4xx canyonlands amcc - canyonlands:GLACIER
-glacier_nand powerpc ppc4xx canyonlands amcc - canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
-haleakala powerpc ppc4xx kilauea amcc - kilauea:HALEAKALA
-haleakala_nand powerpc ppc4xx kilauea amcc - kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
-katmai powerpc ppc4xx - amcc
-kilauea powerpc ppc4xx kilauea amcc - kilauea:KILAUEA
-kilauea_nand powerpc ppc4xx kilauea amcc - kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
-luan powerpc ppc4xx - amcc
-makalu powerpc ppc4xx - amcc
-ocotea powerpc ppc4xx - amcc
-rainier powerpc ppc4xx sequoia amcc - sequoia:RAINIER
-rainier_nand powerpc ppc4xx sequoia amcc - sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
-rainier_ramboot powerpc ppc4xx sequoia amcc - sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds
-redwood powerpc ppc4xx - amcc
-sequoia powerpc ppc4xx sequoia amcc - sequoia:SEQUOIA
-sequoia_nand powerpc ppc4xx sequoia amcc - sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000
-sequoia_ramboot powerpc ppc4xx sequoia amcc - sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds
-sycamore powerpc ppc4xx walnut amcc - walnut
-taihu powerpc ppc4xx - amcc
-taishan powerpc ppc4xx - amcc
-walnut powerpc ppc4xx walnut amcc
-yellowstone powerpc ppc4xx yosemite amcc - yosemite:YELLOWSTONE
-yosemite powerpc ppc4xx yosemite amcc - yosemite:YOSEMITE
-yucca powerpc ppc4xx - amcc
-fx12mm powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o
-fx12mm_flash powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o
-v5fx30teval powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o
-v5fx30teval_flash powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o
-CRAYL1 powerpc ppc4xx L1 cray
-CATcenter powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1
-CATcenter_25 powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25
-CATcenter_33 powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33
-PPChameleonEVB powerpc ppc4xx PPChameleonEVB dave
-PPChameleonEVB_BA_25 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_25
-PPChameleonEVB_BA_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_33
-PPChameleonEVB_HI_25 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_25
-PPChameleonEVB_HI_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33
-PPChameleonEVB_ME_25 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25
-PPChameleonEVB_ME_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33
-APC405 powerpc ppc4xx apc405 esd
-AR405 powerpc ppc4xx ar405 esd
-ASH405 powerpc ppc4xx ash405 esd
-CMS700 powerpc ppc4xx cms700 esd
-CPCI2DP powerpc ppc4xx cpci2dp esd
-CPCI405 powerpc ppc4xx cpci405 esd
-CPCI4052 powerpc ppc4xx cpci405 esd
-CPCI405AB powerpc ppc4xx cpci405 esd
-CPCI405DT powerpc ppc4xx cpci405 esd
-CPCIISER4 powerpc ppc4xx cpciiser4 esd
-DP405 powerpc ppc4xx dp405 esd
-DU405 powerpc ppc4xx du405 esd
-DU440 powerpc ppc4xx du440 esd
-HH405 powerpc ppc4xx hh405 esd
-HUB405 powerpc ppc4xx hub405 esd
-OCRTC powerpc ppc4xx ocrtc esd
-PCI405 powerpc ppc4xx pci405 esd
-PLU405 powerpc ppc4xx plu405 esd
-PMC405 powerpc ppc4xx pmc405 esd
-PMC405DE powerpc ppc4xx pmc405de esd
-PMC440 powerpc ppc4xx pmc440 esd
-VOH405 powerpc ppc4xx voh405 esd
-VOM405 powerpc ppc4xx vom405 esd
-WUH405 powerpc ppc4xx wuh405 esd
-devconcenter powerpc ppc4xx intip gdsys - intip:DEVCONCENTER
-dlvision powerpc ppc4xx - gdsys
-dlvision-10g powerpc ppc4xx 405ep gdsys
-gdppc440etx powerpc ppc4xx - gdsys
-intip powerpc ppc4xx intip gdsys - intip:INTIB
-io powerpc ppc4xx 405ep gdsys
-io64 powerpc ppc4xx 405ex gdsys
-iocon powerpc ppc4xx 405ep gdsys
-neo powerpc ppc4xx 405ep gdsys
-icon powerpc ppc4xx - mosaixtech
-MIP405 powerpc ppc4xx mip405 mpl
-MIP405T powerpc ppc4xx mip405 mpl - MIP405:MIP405T
-PIP405 powerpc ppc4xx pip405 mpl
-alpr powerpc ppc4xx - prodrive
-p3p440 powerpc ppc4xx - prodrive
-KAREF powerpc ppc4xx karef sandburst
-METROBOX powerpc ppc4xx metrobox sandburst
-xpedite1000 powerpc ppc4xx - xes
-ml507 powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o
-ml507_flash powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o
-xilinx-ppc405-generic powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000
-xilinx-ppc405-generic_flash powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC
-xilinx-ppc440-generic powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1
-xilinx-ppc440-generic_flash powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC
-sandbox sandbox sandbox sandbox sandbox -
-rsk7203 sh sh2 rsk7203 renesas -
-rsk7264 sh sh2 rsk7264 renesas -
-rsk7269 sh sh2 rsk7269 renesas -
-mpr2 sh sh3 mpr2 - -
-ms7720se sh sh3 ms7720se - -
-shmin sh sh3 shmin - -
-espt sh sh4 espt - -
-ms7722se sh sh4 ms7722se - -
-ms7750se sh sh4 ms7750se - -
-ap325rxa sh sh4 ap325rxa renesas -
-ecovec sh sh4 ecovec renesas -
-MigoR sh sh4 MigoR renesas -
-r2dplus sh sh4 r2dplus renesas -
-r7780mp sh sh4 r7780mp renesas -
-sh7752evb sh sh4 sh7752evb renesas -
-sh7757lcr sh sh4 sh7757lcr renesas -
-sh7763rdp sh sh4 sh7763rdp renesas -
-sh7785lcr sh sh4 sh7785lcr renesas -
-sh7785lcr_32bit sh sh4 sh7785lcr renesas - sh7785lcr:SH_32BIT=1
-r0p7734 sh sh4 r0p7734 renesas -
-ap_sh4a_4a sh sh4 ap_sh4a_4a alphaproject -
-grsim_leon2 sparc leon2 - gaisler
-gr_cpci_ax2000 sparc leon3 - gaisler
-gr_ep2s60 sparc leon3 - gaisler
-grsim sparc leon3 - gaisler
-gr_xc3s_1500 sparc leon3 - gaisler
-coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0x01110000
-# Target ARCH CPU Board name Vendor SoC Options
-########################################################################################################################
+Active arm arm1136 - armltd integrator integratorcp_cm1136 integratorcp:CM1136 Linus Walleij <linus.walleij@linaro.org>
+Active arm arm1136 mx31 - - imx31_phycore - -
+Active arm arm1136 mx31 davedenx - qong - Wolfgang Denk <wd@denx.de>
+Active arm arm1136 mx31 freescale - mx31pdk - Fabio Estevam <fabio.estevam@freescale.com>
+Active arm arm1136 mx31 hale - tt01 - Helmut Raiger <helmut.raiger@hale.at>
+Active arm arm1136 mx31 logicpd - imx31_litekit - -
+Active arm arm1136 mx35 - - woodburn - Stefano Babic <sbabic@denx.de>
+Active arm arm1136 mx35 - woodburn woodburn_sd woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg -
+Active arm arm1136 mx35 CarMediaLab - flea3 - Stefano Babic <sbabic@denx.de>
+Active arm arm1136 mx35 freescale - mx35pdk - Stefano Babic <sbabic@denx.de>
+Active arm arm1176 bcm2835 raspberrypi rpi_b rpi_b - Stephen Warren <swarren@wwwdotorg.org>
+Active arm arm1176 tnetv107x ti tnetv107xevm tnetv107x_evm - Chan-Taek Park <c-park@ti.com>
+Active arm arm720t - armltd integrator integratorap_cm720t integratorap:CM720T Linus Walleij <linus.walleij@linaro.org>
+Active arm arm920t - armltd integrator integratorap_cm920t integratorap:CM920T Linus Walleij <linus.walleij@linaro.org>
+Active arm arm920t - armltd integrator integratorcp_cm920t integratorcp:CM920T Linus Walleij <linus.walleij@linaro.org>
+Active arm arm920t a320 faraday - a320evb - Po-Yu Chuang <ratbert@faraday-tech.com>
+Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek at91rm9200ek Andreas Bießmann <andreas.devel@gmail.com>
+Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek_ram at91rm9200ek:RAMBOOT Andreas Bießmann <andreas.devel@gmail.com>
+Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2 eb_cpux9k2 Jens Scharsig <esw@bus-elektronik.de>
+Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2_ram eb_cpux9k2:RAMBOOT Jens Scharsig <esw@bus-elektronik.de>
+Active arm arm920t at91 eukrea cpuat91 cpuat91 cpuat91 Eric Benard <eric@eukrea.com>
+Active arm arm920t at91 eukrea cpuat91 cpuat91_ram cpuat91:RAMBOOT Eric Benard <eric@eukrea.com>
+Active arm arm920t imx - - mx1ads - -
+Active arm arm920t imx - - scb9328 - Torsten Koschorrek <koschorrek@synertronixx.de>
+Active arm arm920t ks8695 - - cm4008 - Greg Ungerer <greg.ungerer@opengear.com>
+Active arm arm920t ks8695 - - cm41xx - -
+Active arm arm920t s3c24x0 friendlyarm mini2440 mini2440 - Gabriel Huau <contact@huau-gabriel.fr>
+Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Müller <d.mueller@elsoft.ch>
+Active arm arm920t s3c24x0 samsung - smdk2410 - David Müller <d.mueller@elsoft.ch>
+Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij <linus.walleij@linaro.org>
+Active arm arm926ejs - armltd integrator integratorcp_cm926ejs integratorcp:CM924EJ_S Linus Walleij <linus.walleij@linaro.org>
+Active arm arm926ejs armada100 Marvell - aspenite - Prafulla Wadaskar <prafulla@marvell.com>
+Active arm arm926ejs armada100 Marvell - gplugd - Ajay Bhargav <ajay.bhargav@einfochips.com>
+Active arm arm926ejs at91 - - afeb9260 - Sergey Lapin <slapin@ossfans.org>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs0 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs1 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_nandflash at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_2mmc_nandflash at91sam9260ek:AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_dataflash_cs0 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_dataflash_cs1 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_mmc at91sam9260ek:AT91SAM9G20,SYS_USE_MMC Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_nandflash at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_dataflash_cs0 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_dataflash_cs1 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_nandflash at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_dataflash_cs0 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_dataflash_cs3 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS3 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_nandflash at91sam9261ek:AT91SAM9261,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_dataflash_cs0 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_dataflash_cs3 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS3 Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_nandflash at91sam9261ek:AT91SAM9G10,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_dataflash at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_dataflash_cs0 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_nandflash at91sam9263ek:AT91SAM9263,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash_boot at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9m10g45ek at91sam9m10g45ek_nandflash at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH Bo Shen<voice.shen@atmel.com>
+Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_mmc at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC Josh Wu <josh.wu@atmel.com>
+Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_nandflash at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH Josh Wu <josh.wu@atmel.com>
+Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_spiflash at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH Josh Wu <josh.wu@atmel.com>
+Active arm arm926ejs at91 atmel at91sam9rlek at91sam9rlek_dataflash at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9rlek at91sam9rlek_nandflash at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
+Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_dataflash at91sam9x5ek:AT91SAM9X5,SYS_USE_DATAFLASH Bo Shen <voice.shen@atmel.com>
+Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_mmc at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
+Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_nandflash at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
+Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_spiflash at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH Bo Shen <voice.shen@atmel.com>
+Active arm arm926ejs at91 bluewater - snapper9260 snapper9260:AT91SAM9260 Ryan Mallon <ryan@bluewatersys.com>
+Active arm arm926ejs at91 bluewater snapper9260 snapper9g20 snapper9260:AT91SAM9G20 Ryan Mallon <ryan@bluewatersys.com>
+Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc - Jens Scharsig <esw@bus-elektronik.de>
+Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc_ram vl_ma2sc:RAMLOAD Jens Scharsig <esw@bus-elektronik.de>
+Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_eeprom sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_nandflash sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Active arm arm926ejs at91 calao tny_a9260 tny_a9260_eeprom tny_a9260:AT91SAM9260,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Active arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Active arm arm926ejs at91 egnite ethernut5 ethernut5 ethernut5:AT91SAM9XE egnite GmbH <info@egnite.de>
+Active arm arm926ejs at91 emk top9000 top9000eval_xe top9000:EVAL9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+Active arm arm926ejs at91 emk top9000 top9000su_xe top9000:SU9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+Active arm arm926ejs at91 esd meesc meesc meesc:AT91SAM9263,SYS_USE_NANDFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+Active arm arm926ejs at91 esd meesc meesc_dataflash meesc:AT91SAM9263,SYS_USE_DATAFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+Active arm arm926ejs at91 esd otc570 otc570 otc570:AT91SAM9263,SYS_USE_NANDFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+Active arm arm926ejs at91 esd otc570 otc570_dataflash otc570:AT91SAM9263,SYS_USE_DATAFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+Active arm arm926ejs at91 eukrea cpu9260 cpu9260 cpu9260:CPU9260 Eric Benard <eric@eukrea.com>
+Active arm arm926ejs at91 eukrea cpu9260 cpu9260_128M cpu9260:CPU9260,CPU9260_128M Eric Benard <eric@eukrea.com>
+Active arm arm926ejs at91 eukrea cpu9260 cpu9260_nand cpu9260:CPU9260,NANDBOOT Eric Benard <eric@eukrea.com>
+Active arm arm926ejs at91 eukrea cpu9260 cpu9260_nand_128M cpu9260:CPU9260,CPU9260_128M,NANDBOOT Eric Benard <eric@eukrea.com>
+Active arm arm926ejs at91 eukrea cpu9260 cpu9G20 cpu9260:CPU9G20 Eric Benard <eric@eukrea.com>
+Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_128M cpu9260:CPU9G20,CPU9G20_128M Eric Benard <eric@eukrea.com>
+Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_nand cpu9260:CPU9G20,NANDBOOT Eric Benard <eric@eukrea.com>
+Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_nand_128M cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT Eric Benard <eric@eukrea.com>
+Active arm arm926ejs at91 ronetix pm9261 pm9261 pm9261:AT91SAM9261 Ilko Iliev <iliev@ronetix.at>
+Active arm arm926ejs at91 ronetix pm9263 pm9263 pm9263:AT91SAM9263 Ilko Iliev <iliev@ronetix.at>
+Active arm arm926ejs at91 ronetix pm9g45 pm9g45 pm9g45:AT91SAM9G45 Ilko Iliev <iliev@ronetix.at>
+Active arm arm926ejs at91 taskit stamp9g20 portuxg20 stamp9g20:AT91SAM9G20,PORTUXG20 Markus Hubig <mhubig@imko.de>
+Active arm arm926ejs at91 taskit stamp9g20 stamp9g20 stamp9g20:AT91SAM9G20 Markus Hubig <mhubig@imko.de>
+Active arm arm926ejs davinci ait cam_enc_4xx cam_enc_4xx cam_enc_4xx Heiko Schocher <hs@denx.de>
+Active arm arm926ejs davinci Barix ipam390 ipam390 - Heiko Schocher <hs@denx.de>
+Active arm arm926ejs davinci davinci da8xxevm da830evm - Nick Thompson <nick.thompson@gefanuc.com>
+Active arm arm926ejs davinci davinci da8xxevm da850_am18xxevm da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50 Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+Active arm arm926ejs davinci davinci da8xxevm da850evm da850evm:MAC_ADDR_IN_SPIFLASH Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+Active arm arm926ejs davinci davinci da8xxevm da850evm_direct_nor da850evm:MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+Active arm arm926ejs davinci davinci da8xxevm hawkboard - Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
+Active arm arm926ejs davinci davinci da8xxevm hawkboard_uart hawkboard:UART_U_BOOT Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
+Active arm arm926ejs davinci davinci dm355evm davinci_dm355evm - Sandeep Paulraj <s-paulraj@ti.com>
+Active arm arm926ejs davinci davinci dm355leopard davinci_dm355leopard - Sandeep Paulraj <s-paulraj@ti.com>
+Active arm arm926ejs davinci davinci dm365evm davinci_dm365evm - Sandeep Paulraj <s-paulraj@ti.com>
+Active arm arm926ejs davinci davinci dm6467evm davinci_dm6467evm davinci_dm6467evm:REFCLK_FREQ=27000000 Sandeep Paulraj <s-paulraj@ti.com>
+Active arm arm926ejs davinci davinci dm6467evm davinci_dm6467Tevm davinci_dm6467evm:DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000 Sandeep Paulraj <s-paulraj@ti.com>
+Active arm arm926ejs davinci davinci dvevm davinci_dvevm - -
+Active arm arm926ejs davinci davinci ea20 ea20 - Stefano Babic <sbabic@denx.de>
+Active arm arm926ejs davinci davinci schmoogie davinci_schmoogie - -
+Active arm arm926ejs davinci davinci sffsdr davinci_sffsdr - -
+Active arm arm926ejs davinci davinci sonata davinci_sonata - -
+Active arm arm926ejs davinci enbw enbw_cmc enbw_cmc - Heiko Schocher <hs@denx.de>
+Active arm arm926ejs davinci omicron calimain calimain - Manfred Rudigier <manfred.rudigier@omicron.at>:Christian Riesch <christian.riesch@omicron.at>
+Active arm arm926ejs kirkwood buffalo lsxl lschlv2 lsxl:LSCHLV2 Michael Walle <michael@walle.cc>
+Active arm arm926ejs kirkwood buffalo lsxl lsxhl lsxl:LSXHL Michael Walle <michael@walle.cc>
+Active arm arm926ejs kirkwood cloudengines - pogo_e02 - Dave Purdy <david.c.purdy@gmail.com>
+Active arm arm926ejs kirkwood d-link - dns325 - Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
+Active arm arm926ejs kirkwood iomega - iconnect - Luka Perkov <luka@openwrt.org>
+Active arm arm926ejs kirkwood karo tk71 tk71 - -
+Active arm arm926ejs kirkwood keymile km_arm km_kirkwood km_kirkwood:KM_KIRKWOOD Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood keymile km_arm kmcoge5un km_kirkwood:KM_COGE5UN Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood keymile km_arm kmnusa km_kirkwood:KM_NUSA Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood keymile km_arm kmsuv31 km_kirkwood:KM_SUV31 Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood keymile km_arm mgcoge3un km_kirkwood:KM_MGCOGE3UN Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood keymile km_arm portl2 km_kirkwood:KM_PORTL2 Valentin Longchamp <valentin.longchamp@keymile.com>
+Active arm arm926ejs kirkwood LaCie net2big_v2 d2net_v2 lacie_kw:D2NET_V2 -
+Active arm arm926ejs kirkwood LaCie net2big_v2 net2big_v2 lacie_kw:NET2BIG_V2 Simon Guinot <simon.guinot@sequanux.org>
+Active arm arm926ejs kirkwood LaCie netspace_v2 inetspace_v2 lacie_kw:INETSPACE_V2 Simon Guinot <simon.guinot@sequanux.org>
+Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_lite_v2 lacie_kw:NETSPACE_LITE_V2 -
+Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_max_v2 lacie_kw:NETSPACE_MAX_V2 Simon Guinot <simon.guinot@sequanux.org>
+Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_mini_v2 lacie_kw:NETSPACE_MINI_V2 -
+Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_v2 lacie_kw:NETSPACE_V2 Simon Guinot <simon.guinot@sequanux.org>
+Active arm arm926ejs kirkwood LaCie wireless_space wireless_space - -
+Active arm arm926ejs kirkwood Marvell - dreamplug - Jason Cooper <u-boot@lakedaemon.net>
+Active arm arm926ejs kirkwood Marvell - guruplug - Siddarth Gore <gores@marvell.com>
+Active arm arm926ejs kirkwood Marvell - mv88f6281gtw_ge - Prafulla Wadaskar <prafulla@marvell.com>
+Active arm arm926ejs kirkwood Marvell - rd6281a - Prafulla Wadaskar <prafulla@marvell.com>
+Active arm arm926ejs kirkwood Marvell - sheevaplug - Prafulla Wadaskar <prafulla@marvell.com>
+Active arm arm926ejs kirkwood Marvell openrd openrd_base openrd:BOARD_IS_OPENRD_BASE Prafulla Wadaskar <prafulla@marvell.com>
+Active arm arm926ejs kirkwood Marvell openrd openrd_client openrd:BOARD_IS_OPENRD_CLIENT -
+Active arm arm926ejs kirkwood Marvell openrd openrd_ultimate openrd:BOARD_IS_OPENRD_ULTIMATE -
+Active arm arm926ejs kirkwood raidsonic ib62x0 ib62x0 - Luka Perkov <luka@openwrt.org>
+Active arm arm926ejs kirkwood Seagate - dockstar - Eric Cooper <ecc@cmu.edu>
+Active arm arm926ejs kirkwood Seagate - goflexhome - Suriyan Ramasami <suriyan.r@gmail.com>
+Active arm arm926ejs lpc32xx timll devkit3250 devkit3250 - Vladimir Zapolskiy <vz@mleia.com>
+Active arm arm926ejs mb86r0x syteco jadecpu jadecpu - Matthias Weisser <weisserm@arcor.de>
+Active arm arm926ejs mx25 freescale mx25pdk mx25pdk mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com>
+Active arm arm926ejs mx25 karo tx25 tx25 - John Rigby <jcrigby@gmail.com>
+Active arm arm926ejs mx25 syteco zmx25 zmx25 - Matthias Weisser <weisserm@arcor.de>
+Active arm arm926ejs mx27 logicpd imx27lite imx27lite - Wolfgang Denk <wd@denx.de>
+Active arm arm926ejs mx27 logicpd imx27lite magnesium - Heiko Schocher <hs@denx.de>
+Active arm arm926ejs mxs bluegiga apx4devkit apx4devkit apx4devkit Lauri Hintsala <lauri.hintsala@bluegiga.com>
+Active arm arm926ejs mxs denx m28evk m28evk m28evk Marek Vasut <marek.vasut@gmail.com>
+Active arm arm926ejs mxs freescale mx23evk mx23evk mx23evk Otavio Salvador <otavio@ossystems.com.br>
+Active arm arm926ejs mxs freescale mx28evk mx28evk mx28evk:ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
+Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
+Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam <fabio.estevam@freescale.com>
+Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino mx23_olinuxino Marek Vasut <marek.vasut@gmail.com>
+Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut <marek.vasut@gmail.com>
+Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
+Active arm arm926ejs nomadik st nhk8815 nhk8815_onenand nhk8815:BOOT_ONENAND Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
+Active arm arm926ejs omap ti - omap5912osk - Rishi Bhattacharya <rishi@ti.com>
+Active arm arm926ejs omap ti omap730p2 omap730p2 omap730p2:CS3_BOOT Dave Peverley <dpeverley@mpc-data.co.uk>
+Active arm arm926ejs omap ti omap730p2 omap730p2_cs0boot omap730p2:CS0_BOOT Dave Peverley <dpeverley@mpc-data.co.uk>
+Active arm arm926ejs omap ti omap730p2 omap730p2_cs3boot omap730p2:CS3_BOOT Dave Peverley <dpeverley@mpc-data.co.uk>
+Active arm arm926ejs orion5x LaCie - edminiv2 - Albert ARIBAUD <albert.u.boot@aribaud.net>
+Active arm arm926ejs pantheon Marvell - dkb - Lei Wen <leiwen@marvell.com>
+Active arm arm926ejs spear spear - x600 x600 Stefan Roese <sr@denx.de>
+Active arm arm926ejs spear spear spear300 spear300 spear3xx_evb:spear300 Vipin Kumar <vipin.kumar@st.com>
+Active arm arm926ejs spear spear spear300 spear300_nand spear3xx_evb:spear300,nand -
+Active arm arm926ejs spear spear spear300 spear300_usbtty spear3xx_evb:spear300,usbtty -
+Active arm arm926ejs spear spear spear300 spear300_usbtty_nand spear3xx_evb:spear300,usbtty,nand -
+Active arm arm926ejs spear spear spear310 spear310 spear3xx_evb:spear310 Vipin Kumar <vipin.kumar@st.com>
+Active arm arm926ejs spear spear spear310 spear310_nand spear3xx_evb:spear310,nand -
+Active arm arm926ejs spear spear spear310 spear310_pnor spear3xx_evb:spear310,FLASH_PNOR -
+Active arm arm926ejs spear spear spear310 spear310_usbtty spear3xx_evb:spear310,usbtty -
+Active arm arm926ejs spear spear spear310 spear310_usbtty_nand spear3xx_evb:spear310,usbtty,nand -
+Active arm arm926ejs spear spear spear310 spear310_usbtty_pnor spear3xx_evb:spear310,usbtty,FLASH_PNOR -
+Active arm arm926ejs spear spear spear320 spear320 spear3xx_evb:spear320 Vipin Kumar <vipin.kumar@st.com>
+Active arm arm926ejs spear spear spear320 spear320_nand spear3xx_evb:spear320,nand -
+Active arm arm926ejs spear spear spear320 spear320_pnor spear3xx_evb:spear320,FLASH_PNOR -
+Active arm arm926ejs spear spear spear320 spear320_usbtty spear3xx_evb:spear320,usbtty -
+Active arm arm926ejs spear spear spear320 spear320_usbtty_nand spear3xx_evb:spear320,usbtty,nand -
+Active arm arm926ejs spear spear spear320 spear320_usbtty_pnor spear3xx_evb:spear320,usbtty,FLASH_PNOR -
+Active arm arm926ejs spear spear spear600 spear600 spear6xx_evb:spear600 Vipin Kumar <vipin.kumar@st.com>
+Active arm arm926ejs spear spear spear600 spear600_nand spear6xx_evb:spear600,nand -
+Active arm arm926ejs spear spear spear600 spear600_usbtty spear6xx_evb:spear600,usbtty -
+Active arm arm926ejs spear spear spear600 spear600_usbtty_nand spear6xx_evb:spear600,usbtty,nand -
+Active arm arm926ejs versatile armltd versatile versatileab versatile:ARCH_VERSATILE_AB -
+Active arm arm926ejs versatile armltd versatile versatilepb versatile:ARCH_VERSATILE_PB -
+Active arm arm926ejs versatile armltd versatile versatileqemu versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB -
+Active arm arm946es - armltd integrator integratorap_cm946es integratorap:CM946ES Linus Walleij <linus.walleij@linaro.org>
+Active arm arm946es - armltd integrator integratorcp_cm946es integratorcp:CM946ES Linus Walleij <linus.walleij@linaro.org>
+Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - -
+Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel <matt.waddel@linaro.org>
+Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel <matt.waddel@linaro.org>
+Active arm armv7 am33xx isee igep0033 igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com>
+Active arm armv7 am33xx phytec pcm051 pcm051 pcm051 Lars Poeschel <poeschel@lemonage.de>
+Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com>
+Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com>
+Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com>
+Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_norboot am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_spiboot am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_uart1 am335x_evm:SERIAL2,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_uart2 am335x_evm:SERIAL3,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_uart3 am335x_evm:SERIAL4,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 -
+Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter <mporter@ti.com>
+Active arm armv7 am33xx ti ti816x ti816x_evm - -
+Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
+Active arm armv7 at91 atmel sama5d3xek sama5d3xek_nandflash sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
+Active arm armv7 at91 atmel sama5d3xek sama5d3xek_spiflash sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH Bo Shen <voice.shen@atmel.com>
+Active arm armv7 exynos samsung arndale arndale - Inderpal Singh <inderpal.singh@linaro.org>
+Active arm armv7 exynos samsung origen origen - Chander Kashyap <k.chander@samsung.com>
+Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap <k.chander@samsung.com>
+Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde <rajeshwari.s@samsung.com>
+Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap <k.chander@samsung.com>
+Active arm armv7 exynos samsung trats trats - Lukasz Majewski <l.majewski@samsung.com>
+Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Minkyu Kang <mk7.kang@samsung.com>
+Active arm armv7 highbank - highbank highbank - Rob Herring <rob.herring@calxeda.com>
+Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <marek.vasut@gmail.com>
+Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg -
+Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <sbabic@denx.de>
+Active arm armv7 mx5 freescale mx53ard mx53ard mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx5 freescale mx53evk mx53evk mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg Jason Liu <r64343@freescale.com>
+Active arm armv7 mx5 freescale mx53loco mx53loco mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg Jason Liu <r64343@freescale.com>
+Active arm armv7 mx5 freescale mx53smd mx53smd mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg -
+Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg -
+Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic <sbabic@denx.de>
+Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 boundary nitrogen6x mx6qsabrelite nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE Eric Nelson <eric.nelson@boundarydevices.com>
+Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
+Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com>
+Active arm armv7 mx6 boundary nitrogen6x nitrogen6q nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
+Active arm armv7 mx6 boundary nitrogen6x nitrogen6q2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com>
+Active arm armv7 mx6 boundary nitrogen6x nitrogen6s nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Eric Nelson <eric.nelson@boundarydevices.com>
+Active arm armv7 mx6 boundary nitrogen6x nitrogen6s1g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
+Active arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre@adeneo-embedded.com>
+Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg Jason Liu <r64343@freescale.com>
+Active arm armv7 mx6 freescale mx6qsabreauto mx6qsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 freescale titanium titanium titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg Stefan Roese <sr@denx.de>
+Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com>
+Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com>
+Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat <raph@8d.com>
+Active arm armv7 omap3 comelit dig297 dig297 - Luca Ceresoli <luca.ceresoli@comelit.it>
+Active arm armv7 omap3 compulab cm_t35 cm_t35 - Igor Grinberg <grinberg@compulab.co.il>
+Active arm armv7 omap3 corscience tricorder tricorder - Thomas Weber <weber@corscience.de>
+Active arm armv7 omap3 htkw mcx mcx - Ilya Yanok <yanok@emcraft.com>
+Active arm armv7 omap3 isee igep00x0 igep0020 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com>
+Active arm armv7 omap3 isee igep00x0 igep0020_nand igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND -
+Active arm armv7 omap3 isee igep00x0 igep0030 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com>
+Active arm armv7 omap3 isee igep00x0 igep0030_nand igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND -
+Active arm armv7 omap3 isee igep00x0 igep0032 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com>
+Active arm armv7 omap3 logicpd am3517evm am3517_evm - Vaibhav Hiremath <hvaibhav@ti.com>
+Active arm armv7 omap3 logicpd omap3som omap3_logic - Peter Barada <peter.barada@logicpd.com>
+Active arm armv7 omap3 logicpd zoom1 omap3_zoom1 - Nishanth Menon <nm@ti.com>
+Active arm armv7 omap3 logicpd zoom2 omap3_zoom2 - Tom Rix <Tom.Rix@windriver.com>
+Active arm armv7 omap3 matrix_vision mvblx omap3_mvblx - Michael Jones <michael.jones@matrix-vision.de>
+Active arm armv7 omap3 nokia rx51 nokia_rx51 - Pali Rohár <pali.rohar@gmail.com>
+Active arm armv7 omap3 technexion twister twister - Stefano Babic <sbabic@denx.de>
+Active arm armv7 omap3 teejet mt_ventoux mt_ventoux - Stefano Babic <sbabic@denx.de>
+Active arm armv7 omap3 ti am3517crane am3517_crane - Nagendra T S <nagendra@mistralsolutions.com>
+Active arm armv7 omap3 ti beagle omap3_beagle - Tom Rini <trini@ti.com>
+Active arm armv7 omap3 ti evm omap3_evm - Tom Rini <trini@ti.com>
+Active arm armv7 omap3 ti evm omap3_evm_quick_mmc - -
+Active arm armv7 omap3 ti evm omap3_evm_quick_nand - -
+Active arm armv7 omap3 ti sdp3430 omap3_sdp3430 - Nishanth Menon <nm@ti.com>
+Active arm armv7 omap3 timll devkit8000 devkit8000 - Thomas Weber <weber@corscience.de>
+Active arm armv7 omap4 ti panda omap4_panda - Sricharan R <r.sricharan@ti.com>
+Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R <r.sricharan@ti.com>
+Active arm armv7 omap5 ti dra7xx dra7xx_evm - Lokesh Vutla <lokeshvutla@ti.com>
+Active arm armv7 omap5 ti omap5_uevm omap5_uevm - -
+Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
+Active arm armv7 s5pc1xx samsung goni s5p_goni - Minkyu Kang <mk7.kang@samsung.com>
+Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
+Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
+Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
+Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
+Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>
+Active arm armv7 zynq xilinx zynq zynq - Michal Simek <monstr@monstr.eu>
+Active arm armv7 zynq xilinx zynq zynq_dcc zynq:ZYNQ_DCC Michal Simek <monstr@monstr.eu>
+Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
+Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding <thierry.reding@avionic-design.de>
+Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding <thierry.reding@avionic-design.de>
+Active arm armv7:arm720t tegra20 avionic-design tec tec - Thierry Reding <thierry.reding@avionic-design.de>
+Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
+Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
+Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren <twarren@nvidia.com>
+Active arm armv7:arm720t tegra20 nvidia seaboard seaboard - Tom Warren <twarren@nvidia.com>
+Active arm armv7:arm720t tegra20 nvidia ventana ventana - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
+Active arm armv7:arm720t tegra20 nvidia whistler whistler - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
+Active arm armv7:arm720t tegra20 toradex colibri_t20_iris colibri_t20_iris - Lucas Stach <dev@lynxeye.de>
+Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
+Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren <twarren@nvidia.com>
+Active arm ixp - - - actux2 - Michael Schwingen <michael@schwingen.org>
+Active arm ixp - - - actux3 - Michael Schwingen <michael@schwingen.org>
+Active arm ixp - - - actux4 - Michael Schwingen <michael@schwingen.org>
+Active arm ixp - - - dvlhost - Michael Schwingen <michael@schwingen.org>
+Active arm ixp - - actux1 actux1_4_16 actux1:FLASH2X2 Michael Schwingen <michael@schwingen.org>
+Active arm ixp - - actux1 actux1_4_32 actux1:FLASH2X2,RAM_32MB Michael Schwingen <michael@schwingen.org>
+Active arm ixp - - actux1 actux1_8_16 actux1:FLASH1X8 Michael Schwingen <michael@schwingen.org>
+Active arm ixp - - actux1 actux1_8_32 actux1:FLASH1X8,RAM_32MB Michael Schwingen <michael@schwingen.org>
+Active arm ixp - prodrive pdnb3 pdnb3 - Stefan Roese <sr@denx.de>
+Active arm ixp - prodrive pdnb3 scpu pdnb3:SCPU Stefan Roese <sr@denx.de>
+Active arm pxa - - - balloon3 - Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - - h2200 - Lukasz Dalek <luk0104@gmail.com>
+Active arm pxa - - - palmld - Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - - palmtc - Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - - palmtreo680 - Mike Dunn <mikedunn@newsguy.com>
+Active arm pxa - - - pxa255_idp - Cliff Brake <cliff.brake@gmail.com>
+Active arm pxa - - - trizepsiv - Stefano Babic <sbabic@denx.de>
+Active arm pxa - - - xaeniax - -
+Active arm pxa - - - zipitz2 - Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - trizepsiv polaris trizepsiv:POLARIS Stefano Babic <sbabic@denx.de>
+Active arm pxa - - vpac270 vpac270_nor_128 vpac270:NOR,RAM_128M Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - vpac270 vpac270_nor_256 vpac270:NOR,RAM_256M Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - - vpac270 vpac270_ond_256 vpac270:ONENAND,RAM_256M Marek Vasut <marek.vasut@gmail.com>
+Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich <ynvich@gmail.com>
+Active arm pxa - toradex - colibri_pxa270 - Marek Vasut <marek.vasut@gmail.com>
+Active arm sa1100 - - - jornada - Kristoffer Ericson <kristoffer.ericson@gmail.com>
+Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann <andreas.devel@googlemail.com>
+Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Active avr32 at32ap at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Active avr32 at32ap at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Active avr32 at32ap at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Active avr32 at32ap at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
+Active avr32 at32ap at32ap700x in-circuit - grasshopper - Andreas Bießmann <andreas.devel@googlemail.com>
+Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson <mpfj@mimc.co.uk>
+Active avr32 at32ap at32ap700x miromico - hammerhead - Julien May <julien.may@miromico.ch>:Alex Raimondi <alex.raimondi@miromico.ch>
+Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald <devel@bct-electronic.com>
+Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf525-ucr2 - Haitao Zhang <hzhang@ucrobotics.com>:Chong Huang <chuang@ucrobotics.com>
+Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf527-sdp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf533-stamp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf537-minotaur - Martin Strubel <strubel@section5.ch>
+Active blackfin blackfin - - - bf537-pnav - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf537-srv1 - Martin Strubel <strubel@section5.ch>
+Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf561-acvilon - Anton Shurpin <shurpin.aa@niistt.ru>:Valentin Yakovenkov <yakovenkov@niistt.ru>
+Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active blackfin blackfin - - - blackstamp - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
+Active blackfin blackfin - - - blackvme - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
+Active blackfin blackfin - - - br4 - Dimitar Penev <dpn@switchfin.org>
+Active blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Active blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Active blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Active blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Active blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Active blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) <info@ssv-embedded.de>
+Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule <support@i-syst.com>
+Active blackfin blackfin - - - ip04 - Brent Kandetzki <brentk@teleco.com>
+Active blackfin blackfin - - - pr1 - Dimitar Penev <dpn@switchfin.org>
+Active blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Active blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
+Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf523x - freescale m5235evb M5235EVB_Flash32 M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf52x2 - - - idmr - -
+Active m68k mcf52x2 - - cobra5272 cobra5272 - -
+Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282 eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 Jens Scharsig <esw@bus-elektronik.de>
+Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282_internal eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 Jens Scharsig <esw@bus-elektronik.de>
+Active m68k mcf52x2 - esd tasreg TASREG - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active m68k mcf52x2 - freescale m5208evbe M5208EVBE - -
+Active m68k mcf52x2 - freescale m5249evb M5249EVB - -
+Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser@freescale.com>
+Active m68k mcf52x2 - freescale m5271evb M5271EVB - -
+Active m68k mcf52x2 - freescale m5272c3 M5272C3 - -
+Active m68k mcf52x2 - freescale m5275evb M5275EVB - -
+Active m68k mcf52x2 - freescale m5282evb M5282EVB - -
+Active m68k mcf532x - astro mcf5373l astro_mcf5373l - Wolfgang Wegner <w.wegner@astro-kom.de>
+Active m68k mcf532x - freescale m53017evb M53017EVB - TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf532x - freescale m5329evb M5329AFEE M5329EVB:NANDFLASH_SIZE=0 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf532x - freescale m5329evb M5329BFEE M5329EVB:NANDFLASH_SIZE=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf532x - freescale m5373evb M5373EVB M5373EVB:NANDFLASH_SIZE=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf5445x - freescale m54418twr M54418TWR M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
+Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_mii M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 -
+Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_rmii M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
+Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_rmii_lowfreq M54418TWR:SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
+Active m68k mcf5445x - freescale m54418twr M54418TWR_serial_mii M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 -
+Active m68k mcf5445x - freescale m54418twr M54418TWR_serial_rmii M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
+Active m68k mcf5445x - freescale m54451evb M54451EVB M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000 -
+Active m68k mcf5445x - freescale m54451evb M54451EVB_stmicro M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000 -
+Active m68k mcf5445x - freescale m54455evb M54455EVB M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf5445x - freescale m54455evb M54455EVB_a66 M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf5445x - freescale m54455evb M54455EVB_i66 M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf5445x - freescale m54455evb M54455EVB_intel M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf5445x - freescale m54455evb M54455EVB_stm33 M54455EVB:SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m547xevb M5475AFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m547xevb M5475BFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m547xevb M5475CFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m547xevb M5475DFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m547xevb M5475EFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m547xevb M5475FFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m547xevb M5475GFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m548xevb M5485AFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m548xevb M5485BFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m548xevb M5485CFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m548xevb M5485DFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m548xevb M5485EFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m548xevb M5485FFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m548xevb M5485GFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active m68k mcf547x_8x - freescale m548xevb M5485HFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek <monstr@monstr.eu>
+Active mips mips32 - - qemu-malta qemu_malta qemu-malta:MIPS32,SYS_BIG_ENDIAN -
+Active mips mips32 - - qemu-malta qemu_maltael qemu-malta:MIPS32,SYS_LITTLE_ENDIAN -
+Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu <vlad.lungu@windriver.com>
+Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN -
+Active mips mips32 - micronas vct vct_platinum vct:VCT_PLATINUM -
+Active mips mips32 - micronas vct vct_platinum_onenand vct:VCT_PLATINUM,VCT_ONENAND -
+Active mips mips32 - micronas vct vct_platinum_onenand_small vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE -
+Active mips mips32 - micronas vct vct_platinum_small vct:VCT_PLATINUM,VCT_SMALL_IMAGE -
+Active mips mips32 - micronas vct vct_platinumavc vct:VCT_PLATINUMAVC -
+Active mips mips32 - micronas vct vct_platinumavc_onenand vct:VCT_PLATINUMAVC,VCT_ONENAND -
+Active mips mips32 - micronas vct vct_platinumavc_onenand_small vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE -
+Active mips mips32 - micronas vct vct_platinumavc_small vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE -
+Active mips mips32 - micronas vct vct_premium vct:VCT_PREMIUM -
+Active mips mips32 - micronas vct vct_premium_onenand vct:VCT_PREMIUM,VCT_ONENAND -
+Active mips mips32 - micronas vct vct_premium_onenand_small vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE -
+Active mips mips32 - micronas vct vct_premium_small vct:VCT_PREMIUM,VCT_SMALL_IMAGE -
+Active mips mips32 au1x00 - dbau1x00 dbau1000 dbau1x00:DBAU1000 Thomas Lange <thomas@corelatus.se>
+Active mips mips32 au1x00 - dbau1x00 dbau1100 dbau1x00:DBAU1100 Thomas Lange <thomas@corelatus.se>
+Active mips mips32 au1x00 - dbau1x00 dbau1500 dbau1x00:DBAU1500 Thomas Lange <thomas@corelatus.se>
+Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se>
+Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se>
+Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 -
+Active mips mips32 incaip - incaip incaip - Wolfgang Denk <wd@denx.de>
+Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
+Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
+Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
+Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
+Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
+Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
+Active nds32 n1213 ag101 AndesTech adp-ag101p adp-ag101p - Andes <uboot@andestech.com>
+Active nds32 n1213 ag102 AndesTech adp-ag102 adp-ag102 - Andes <uboot@andestech.com>
+Active nios2 nios2 - altera nios2-generic nios2-generic - Scott McNutt <smcnutt@psyent.com>
+Active nios2 nios2 - psyent pci5441 PCI5441 - Scott McNutt <smcnutt@psyent.com>
+Active nios2 nios2 - psyent pk1c20 PK1C20 - Scott McNutt <smcnutt@psyent.com>
+Active openrisc or1200 - openrisc openrisc-generic openrisc-generic - Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+Active powerpc 74xx_7xx - - - ppmc7xx - -
+Active powerpc 74xx_7xx - - evb64260 P3G4 - Wolfgang Denk <wd@denx.de>
+Active powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu <nyet@zumanetworks.com>
+Active powerpc 74xx_7xx - eltec elppc ELPPC - -
+Active powerpc 74xx_7xx - esd cpci750 CPCI750 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc 74xx_7xx - freescale mpc7448hpc2 mpc7448hpc2 - Roy Zang <tie-fei.zang@freescale.com>
+Active powerpc 74xx_7xx - Marvell db64360 DB64360 - -
+Active powerpc 74xx_7xx - Marvell db64460 DB64460 - -
+Active powerpc 74xx_7xx - prodrive p3mx p3m7448 p3mx:P3M7448 Stefan Roese <sr@denx.de>
+Active powerpc 74xx_7xx - prodrive p3mx p3m750 p3mx:P3M750 Stefan Roese <sr@denx.de>
+Active powerpc mpc512x - - - pdm360ng - Michael Weiss <michael.weiss@ifm.com>
+Active powerpc mpc512x - davedenx - aria - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc512x - esd - mecp5123 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc512x - freescale mpc5121ads mpc5121ads - -
+Active powerpc mpc512x - freescale mpc5121ads mpc5121ads_rev2 mpc5121ads:MPC5121ADS_REV2 -
+Active powerpc mpc512x - ifm ac14xx ac14xx - Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xx - - cmi cmi_mpc5xx - -
+Active powerpc mpc5xx - mpl pati PATI - -
+Active powerpc mpc5xxx - - - canmb - -
+Active powerpc mpc5xxx - - - cm5200 - -
+Active powerpc mpc5xxx - - - inka4x0 - Detlev Zundel <dzu@denx.de>
+Active powerpc mpc5xxx - - - ipek01 - Wolfgang Grandegger <wg@denx.de>
+Active powerpc mpc5xxx - - - jupiter - Heiko Schocher <hs@denx.de>
+Active powerpc mpc5xxx - - - motionpro - -
+Active powerpc mpc5xxx - - - munices - -
+Active powerpc mpc5xxx - - - v38b - -
+Active powerpc mpc5xxx - - a3m071 a3m071 - Stefan Roese <sr@denx.de>
+Active powerpc mpc5xxx - - a3m071 a4m2k a3m071:A4M2K Stefan Roese <sr@denx.de>
+Active powerpc mpc5xxx - - a4m072 a4m072 - Sergei Poselenov <sposelenov@emcraft.com>
+Active powerpc mpc5xxx - - bc3450 BC3450 - -
+Active powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt <emillbrandt@dekaresearch.com>
+Active powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt <emillbrandt@dekaresearch.com>
+Active powerpc mpc5xxx - - icecube icecube_5200 IceCube Wolfgang Denk <wd@denx.de>
+Active powerpc mpc5xxx - - icecube icecube_5200_DDR IceCube:MPC5200_DDR -
+Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR -
+Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR -
+Active powerpc mpc5xxx - - icecube icecube_5200_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF000000 -
+Active powerpc mpc5xxx - - icecube icecube_5200_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000 -
+Active powerpc mpc5xxx - - icecube Lite5200 IceCube -
+Active powerpc mpc5xxx - - icecube Lite5200_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF000000 -
+Active powerpc mpc5xxx - - icecube Lite5200_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000 -
+Active powerpc mpc5xxx - - icecube lite5200b IceCube:MPC5200_DDR,LITE5200B -
+Active powerpc mpc5xxx - - icecube lite5200b_LOWBOOT IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000 -
+Active powerpc mpc5xxx - - icecube lite5200b_PM IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM -
+Active powerpc mpc5xxx - - mcc200 mcc200 mcc200 -
+Active powerpc mpc5xxx - - mcc200 mcc200_COM12 mcc200:CONSOLE_COM12 -
+Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000 -
+Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot_SDRAM mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
+Active powerpc mpc5xxx - - mcc200 mcc200_COM12_SDRAM mcc200:CONSOLE_COM12,MCC200_SDRAM -
+Active powerpc mpc5xxx - - mcc200 mcc200_highboot mcc200:SYS_TEXT_BASE=0xFFF00000 -
+Active powerpc mpc5xxx - - mcc200 mcc200_highboot_SDRAM mcc200:SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
+Active powerpc mpc5xxx - - mcc200 mcc200_SDRAM mcc200:MCC200_SDRAM -
+Active powerpc mpc5xxx - - mcc200 prs200 mcc200:PRS200,MCC200_SDRAM -
+Active powerpc mpc5xxx - - mcc200 prs200_DDR mcc200:PRS200 -
+Active powerpc mpc5xxx - - mcc200 prs200_highboot mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
+Active powerpc mpc5xxx - - mcc200 prs200_highboot_DDR mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000 -
+Active powerpc mpc5xxx - - pm520 PM520 - Josef Wagner <Wagner@Microsys.de>
+Active powerpc mpc5xxx - - pm520 PM520_DDR PM520:MPC5200_DDR Josef Wagner <Wagner@Microsys.de>
+Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT PM520:BOOT_ROM Josef Wagner <Wagner@Microsys.de>
+Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT_DDR PM520:MPC5200_DDR,BOOT_ROM Josef Wagner <Wagner@Microsys.de>
+Active powerpc mpc5xxx - - total5200 Total5200 Total5200:TOTAL5200_REV=1 -
+Active powerpc mpc5xxx - - total5200 Total5200_lowboot Total5200:TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000 -
+Active powerpc mpc5xxx - - total5200 Total5200_Rev2 Total5200:TOTAL5200_REV=2 -
+Active powerpc mpc5xxx - - total5200 Total5200_Rev2_lowboot Total5200:TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000 -
+Active powerpc mpc5xxx - emk top5200 EVAL5200 TOP5200:EVAL5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+Active powerpc mpc5xxx - emk top5200 MINI5200 TOP5200:MINI5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+Active powerpc mpc5xxx - emk top5200 TOP5200 TOP5200:TOP5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+Active powerpc mpc5xxx - esd - cpci5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc5xxx - esd - mecp5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc5xxx - esd - pf5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc5xxx - ifm o2dnt2 O2D o2d Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O2D300 o2d300 Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2 o2dnt2 Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2_RAMBOOT o2dnt2:SYS_TEXT_BASE=0x00100000 Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O2I o2i Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O2MNT o2mnt Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M110 o2mnt:IFM_SENSOR_TYPE="O2M110" Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M112 o2mnt:IFM_SENSOR_TYPE="O2M112" Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M113 o2mnt:IFM_SENSOR_TYPE="O2M113" Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - ifm o2dnt2 O3DNT o3dnt Anatolij Gustschin <agust@denx.de>
+Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc - Werner Pfister <Pfister_Werner@intercontrol.de>
+Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000 Werner Pfister <Pfister_Werner@intercontrol.de>
+Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5 digsy_mtc:DIGSY_REV5 Werner Pfister <Pfister_Werner@intercontrol.de>
+Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5 Werner Pfister <Pfister_Werner@intercontrol.de>
+Active powerpc mpc5xxx - manroland - hmi1001 - -
+Active powerpc mpc5xxx - manroland - mucmc52 - Heiko Schocher <hs@denx.de>
+Active powerpc mpc5xxx - manroland - uc101 - Heiko Schocher <hs@denx.de>
+Active powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz <andre.schwarz@matrix-vision.de>
+Active powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz <andre.schwarz@matrix-vision.de>
+Active powerpc mpc5xxx - phytec pcm030 pcm030 pcm030 Jon Smirl <jonsmirl@gmail.com>
+Active powerpc mpc5xxx - phytec pcm030 pcm030_LOWBOOT pcm030:SYS_TEXT_BASE=0xFF000000 Jon Smirl <jonsmirl@gmail.com>
+Active powerpc mpc5xxx - tqc tqm5200 aev - -
+Active powerpc mpc5xxx - tqc tqm5200 cam5200 TQM5200:CAM5200,TQM5200S,TQM5200_B -
+Active powerpc mpc5xxx - tqc tqm5200 cam5200_niosflash TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH -
+Active powerpc mpc5xxx - tqc tqm5200 charon charon Heiko Schocher <hs@denx.de>
+Active powerpc mpc5xxx - tqc tqm5200 fo300 TQM5200:FO300 -
+Active powerpc mpc5xxx - tqc tqm5200 MiniFAP TQM5200:MINIFAP -
+Active powerpc mpc5xxx - tqc tqm5200 TB5200 - -
+Active powerpc mpc5xxx - tqc tqm5200 TB5200_B TB5200:TQM5200_B -
+Active powerpc mpc5xxx - tqc tqm5200 TQM5200 TQM5200: -
+Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B TQM5200:TQM5200_B -
+Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B_HIGHBOOT TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000 -
+Active powerpc mpc5xxx - tqc tqm5200 TQM5200_STK100 TQM5200:STK52XX_REV100 -
+Active powerpc mpc5xxx - tqc tqm5200 TQM5200S TQM5200:TQM5200_B,TQM5200S -
+Active powerpc mpc5xxx - tqc tqm5200 TQM5200S_HIGHBOOT TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000 -
+Active powerpc mpc824x - - - utx8245 - Greg Allen <gallen@arlut.utexas.edu>
+Active powerpc mpc824x - - a3000 A3000 - -
+Active powerpc mpc824x - - cpc45 CPC45 CPC45 Josef Wagner <Wagner@Microsys.de>
+Active powerpc mpc824x - - cpc45 CPC45_ROMBOOT CPC45:BOOT_ROM Josef Wagner <Wagner@Microsys.de>
+Active powerpc mpc824x - - cu824 CU824 - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc824x - - eXalion eXalion - Torsten Demke <torsten.demke@fci.com>
+Active powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso@adaptec.com>
+Active powerpc mpc824x - - linkstation linkstation_HGLAN linkstation:HGLAN=1 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com>
+Active powerpc mpc824x - - mvblue MVBLUE - -
+Active powerpc mpc824x - - pn62 PN62 - Wolfgang Grandegger <wg@denx.de>
+Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim@musenki.com>
+Active powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com>
+Active powerpc mpc824x - etin - kvme080 - Sangmoon Kim <dogoil@etinsys.com>
+Active powerpc mpc8260 - - - atc - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno@delphintech.com>
+Active powerpc mpc8260 - - - ep82xxm - -
+Active powerpc mpc8260 - - - gw8260 - Oliver Brown <obrown@adventnetworks.com>
+Active powerpc mpc8260 - - - hymod - Murray Jensen <Murray.Jensen@csiro.au>
+Active powerpc mpc8260 - - - ppmc8260 - Brad Kemp <Brad.Kemp@seranoa.com>
+Active powerpc mpc8260 - - - sacsng - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
+Active powerpc mpc8260 - - cogent cogent_mpc8260 - Murray Jensen <Murray.Jensen@csiro.au>
+Active powerpc mpc8260 - - cpu86 CPU86 CPU86 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - cpu87 CPU87 CPU87 -
+Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM -
+Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - - ep8248 ep8248E ep8248 Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - - ids8247 IDS8247 - Heiko Schocher <hs@denx.de>
+Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg@denx.de>
+Active powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs@denx.de>
+Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs@denx.de>
+Active powerpc mpc8260 - - pm826 PM825 PM826:PCI,SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - pm826 PM825_BIGFLASH PM826:PCI,FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - pm826 PM825_ROMBOOT PM826:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - pm826 PM825_ROMBOOT_BIGFLASH PM826:PCI,BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - pm826 PM826 PM826:SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - pm826 PM826_BIGFLASH PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - pm826 PM826_ROMBOOT PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - pm826 PM826_ROMBOOT_BIGFLASH PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - - pm828 PM828 PM828 -
+Active powerpc mpc8260 - - pm828 PM828_PCI PM828:PCI -
+Active powerpc mpc8260 - - pm828 PM828_ROMBOOT PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -
+Active powerpc mpc8260 - - pm828 PM828_ROMBOOT_PCI PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -
+Active powerpc mpc8260 - - rattler Rattler Rattler Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8260 - freescale mpc8266ads MPC8266ADS - Rune Torgersen <runet@innovsys.com>
+Active powerpc mpc8260 - funkwerk vovpn-gw VoVPN-GW_66MHz VoVPN-GW:CLKIN_66MHz -
+Active powerpc mpc8260 - keymile km82xx mgcoge km82xx:MGCOGE Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc8260 - keymile km82xx mgcoge3ne km82xx:MGCOGE3NE Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc8260 - tqc tqm8260 TQM8255_AA TQM8260:MPC8255,300MHz Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AA TQM8260:MPC8260,200MHz Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AB TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AC TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AD TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AE TQM8260:MPC8260,266MHz Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AF TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AG TQM8260:MPC8260,300MHz Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AH TQM8260:MPC8260,300MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8260_AI TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8260 TQM8265_AA TQM8260:MPC8265,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8260 - tqc tqm8272 TQM8272 - -
+Active powerpc mpc83xx - - - mpc8308_p1m - Ilya Yanok <yanok@emcraft.com>
+Active powerpc mpc83xx - - sbc8349 sbc8349 sbc8349 Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_33 sbc8349:PCI,PCI_33M Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_66 sbc8349:PCI,PCI_66M Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc83xx - - ve8313 ve8313 - Heiko Schocher <hs@denx.de>
+Active powerpc mpc83xx - esd vme8349 caddy2 vme8349:CADDY2 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc83xx - esd vme8349 vme8349 vme8349 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+Active powerpc mpc83xx - freescale mpc8308rdb MPC8308RDB - Ilya Yanok <yanok@emcraft.com>
+Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_33 MPC8313ERDB:SYS_33MHZ -
+Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_66 MPC8313ERDB:SYS_66MHZ -
+Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_33 MPC8313ERDB:SYS_33MHZ,NAND -
+Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_66 MPC8313ERDB:SYS_66MHZ,NAND -
+Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB MPC8315ERDB Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB_NAND MPC8315ERDB:NAND_U_BOOT Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8323erdb MPC8323ERDB - Michael Barkowski <michael.barkowski@freescale.com>
+Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS MPC832XEMDS: Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_ATM MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_33 MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_66 MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_SLAVE MPC832XEMDS:PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8349emds MPC8349EMDS - Kim Phillips <kim.phillips@freescale.com>
+Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITX MPC8349ITX:MPC8349ITX -
+Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITX_LOWBOOT MPC8349ITX:MPC8349ITX,SYS_TEXT_BASE=0xFE000000 -
+Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITXGP MPC8349ITX:MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000 -
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33 MPC8360EMDS:CLKIN_33MHZ Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_ATM MPC8360EMDS:CLKIN_33MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_HOST_33 MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_HOST_66 MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_SLAVE MPC8360EMDS:CLKIN_33MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66 MPC8360EMDS:CLKIN_66MHZ Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_ATM MPC8360EMDS:CLKIN_66MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_33 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_66 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK MPC8360ERDK Anton Vorontsov <avorontsov@ru.mvista.com>
+Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov@ru.mvista.com>
+Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_66 MPC8360ERDK Anton Vorontsov <avorontsov@ru.mvista.com>
+Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS MPC837XEMDS Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu@freescale.com>
+Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com>
+Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc83xx - keymile km83xx kmeter1 km8360:KMETER1 Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc83xx - keymile km83xx kmopti2 tuxx1:KMOPTI2 Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc83xx - keymile km83xx kmsupx5 tuxx1:KMSUPX5 Heiko Schocher <hs@denx.de>
+Active powerpc mpc83xx - keymile km83xx kmvect1 suvd3:KMVECT1 Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc83xx - keymile km83xx suvd3 suvd3:SUVD3 Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc83xx - keymile km83xx tuge1 tuxx1:TUGE1 Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc83xx - keymile km83xx tuxx1 tuxx1:TUXX1 Holger Brunck <holger.brunck@keymile.com>
+Active powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz <andre.schwarz@matrix-vision.de>
+Active powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz <andre.schwarz@matrix-vision.de>
+Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_LP SIMPC8313:NAND_LP Ron Madrid <info@sheldoninst.com>
+Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_SP SIMPC8313:NAND_SP Ron Madrid <info@sheldoninst.com>
+Active powerpc mpc83xx - tqc tqm834x TQM834x - -
+Active powerpc mpc85xx - - sbc8548 sbc8548 sbc8548 Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33 sbc8548:PCI,33 Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33_PCIE sbc8548:PCI,33,PCIE Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66 sbc8548:PCI,66 Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66_PCIE sbc8548:PCI,66,PCIE Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc85xx - - socrates socrates - -
+Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com>
+Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 -
+Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 -
+Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND_SYSCLK100 BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH BSC9131RDB:BSC9131RDB,SPIFLASH Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH_SYSCLK100 BSC9131RDB:BSC9131RDB,SPIFLASH,SYS_CLK_100 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK100 BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK133 BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK100 BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK133 BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK100 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
+Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com>
+Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com>
+Active powerpc mpc85xx - freescale corenet_ds P3041DS - -
+Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P3041DS_SECURE_BOOT P3041DS:SECURE_BOOT -
+Active powerpc mpc85xx - freescale corenet_ds P3041DS_SPIFLASH P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P3041DS_SRIO_PCIE_BOOT P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P4080DS - -
+Active powerpc mpc85xx - freescale corenet_ds P4080DS_SDCARD P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P4080DS_SECURE_BOOT P4080DS:SECURE_BOOT -
+Active powerpc mpc85xx - freescale corenet_ds P4080DS_SPIFLASH P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P4080DS_SRIO_PCIE_BOOT P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P5020DS - -
+Active powerpc mpc85xx - freescale corenet_ds P5020DS_NAND P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P5020DS_SDCARD P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P5020DS_SECURE_BOOT P5020DS:SECURE_BOOT -
+Active powerpc mpc85xx - freescale corenet_ds P5020DS_SPIFLASH P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P5020DS_SRIO_PCIE_BOOT P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P5040DS - -
+Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS MPC8536DS -
+Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_36BIT MPC8536DS:36BIT -
+Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_NAND MPC8536DS:NAND -
+Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SDCARD MPC8536DS:SDCARD -
+Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SPIFLASH MPC8536DS:SPIFLASH -
+Active powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS MPC8541CDS Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc85xx - freescale mpc8544ds MPC8544DS - -
+Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS MPC8548CDS -
+Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_36BIT MPC8548CDS:36BIT -
+Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_legacy MPC8548CDS:LEGACY -
+Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS MPC8555CDS Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc85xx - freescale mpc8568mds MPC8568MDS - -
+Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS MPC8569MDS -
+Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM -
+Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND -
+Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS MPC8572DS -
+Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT -
+Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_NAND P1010RDB:P1010RDB,36BIT,NAND -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_NAND_SECBOOT P1010RDB:P1010RDB,36BIT,NAND_SECBOOT,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_NOR P1010RDB:P1010RDB,36BIT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_NOR_SECBOOT P1010RDB:P1010RDB,36BIT,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_SDCARD P1010RDB:P1010RDB,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_SPIFLASH P1010RDB:P1010RDB,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB,36BIT,SPIFLASH,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB_NAND P1010RDB:P1010RDB,NAND -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB_NAND_SECBOOT P1010RDB:P1010RDB,NAND_SECBOOT,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB_NOR P1010RDB:P1010RDB -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB_NOR_SECBOOT P1010RDB:P1010RDB,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB_SDCARD P1010RDB:P1010RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB_SPIFLASH P1010RDB:P1010RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1010rdb P1010RDB_SPIFLASH_SECBOOT P1010RDB:P1010RDB,SPIFLASH,SECURE_BOOT -
+Active powerpc mpc85xx - freescale p1022ds P1022DS - Timur Tabi <timur@freescale.com>
+Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT P1022DS:36BIT Timur Tabi <timur@freescale.com>
+Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_NAND P1022DS:36BIT,NAND Timur Tabi <timur@freescale.com>
+Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_SDCARD P1022DS:36BIT,SDCARD Timur Tabi <timur@freescale.com>
+Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_SPIFLASH P1022DS:36BIT,SPIFLASH Timur Tabi <timur@freescale.com>
+Active powerpc mpc85xx - freescale p1022ds P1022DS_NAND P1022DS:NAND Timur Tabi <timur@freescale.com>
+Active powerpc mpc85xx - freescale p1022ds P1022DS_SDCARD P1022DS:SDCARD Timur Tabi <timur@freescale.com>
+Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi <timur@freescale.com>
+Active powerpc mpc85xx - freescale p1023rdb P1023RDB P1023RDB -
+Active powerpc mpc85xx - freescale p1023rds P1023RDS P1023RDS Roy Zang <tie-fei.zang@freescale.com>
+Active powerpc mpc85xx - freescale p1023rds P1023RDS_NAND P1023RDS:NAND Roy Zang <tie-fei.zang@freescale.com>
+Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SDCARD P1_P2_RDB:P1011RDB,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SPIFLASH P1_P2_RDB:P1011RDB,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_NAND P1_P2_RDB:P1011RDB,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_SDCARD P1_P2_RDB:P1011RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_SPIFLASH P1_P2_RDB:P1011RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB P1_P2_RDB:P1020RDB -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT P1_P2_RDB:P1020RDB,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT_SDCARD P1_P2_RDB:P1020RDB,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT_SPIFLASH P1_P2_RDB:P1020RDB,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_NAND P1_P2_RDB:P1020RDB,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_SDCARD P1_P2_RDB:P1020RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_SPIFLASH P1_P2_RDB:P1020RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB P1_P2_RDB:P2010RDB -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT P1_P2_RDB:P2010RDB,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT_SDCARD P1_P2_RDB:P2010RDB,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT_SPIFLASH P1_P2_RDB:P2010RDB,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_NAND P1_P2_RDB:P2010RDB,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_SDCARD P1_P2_RDB:P2010RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_SPIFLASH P1_P2_RDB:P2010RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB P1_P2_RDB:P2020RDB Poonam Aggrwal <poonam.aggrwal@freescale.com>
+Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT P1_P2_RDB:P2020RDB,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT_SDCARD P1_P2_RDB:P2020RDB,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT_SPIFLASH P1_P2_RDB:P2020RDB,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_NAND P1_P2_RDB:P2020RDB,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_SDCARD P1_P2_RDB:P2020RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_SPIFLASH P1_P2_RDB:P2020RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC p1_p2_rdb_pc:P1020MBG -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_36BIT p1_p2_rdb_pc:P1020MBG,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020MBG,SDCARD,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_SDCARD p1_p2_rdb_pc:P1020MBG,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC p1_p2_rdb_pc:P1020RDB_PC -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT p1_p2_rdb_pc:P1020RDB_PC,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_NAND p1_p2_rdb_pc:P1020RDB_PC,36BIT,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020RDB_PC,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P1020RDB_PC,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_NAND p1_p2_rdb_pc:P1020RDB_PC,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_SDCARD p1_p2_rdb_pc:P1020RDB_PC,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_SPIFLASH p1_p2_rdb_pc:P1020RDB_PC,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD p1_p2_rdb_pc:P1020RDB_PD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_NAND p1_p2_rdb_pc:P1020RDB_PD,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_SDCARD p1_p2_rdb_pc:P1020RDB_PD,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_SPIFLASH p1_p2_rdb_pc:P1020RDB_PD,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC p1_p2_rdb_pc:P1020UTM -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_36BIT p1_p2_rdb_pc:P1020UTM,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_SDCARD p1_p2_rdb_pc:P1020UTM,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC p1_p2_rdb_pc:P1021RDB -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT p1_p2_rdb_pc:P1021RDB,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_NAND p1_p2_rdb_pc:P1021RDB,36BIT,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P1021RDB,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P1021RDB,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_NAND p1_p2_rdb_pc:P1021RDB,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_SDCARD p1_p2_rdb_pc:P1021RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_SPIFLASH p1_p2_rdb_pc:P1021RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB p1_p2_rdb_pc:P1024RDB -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_36BIT p1_p2_rdb_pc:P1024RDB,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_NAND p1_p2_rdb_pc:P1024RDB,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_SDCARD p1_p2_rdb_pc:P1024RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_SPIFLASH p1_p2_rdb_pc:P1024RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB p1_p2_rdb_pc:P1025RDB -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_36BIT p1_p2_rdb_pc:P1025RDB,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_NAND p1_p2_rdb_pc:P1025RDB,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_SDCARD p1_p2_rdb_pc:P1025RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_SPIFLASH p1_p2_rdb_pc:P1025RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC p1_p2_rdb_pc:P2020RDB -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT p1_p2_rdb_pc:P2020RDB,36BIT -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_NAND p1_p2_rdb_pc:P2020RDB,36BIT,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_NAND p1_p2_rdb_pc:P2020RDB,NAND -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_SDCARD p1_p2_rdb_pc:P2020RDB,SDCARD -
+Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_SPIFLASH p1_p2_rdb_pc:P2020RDB,SPIFLASH -
+Active powerpc mpc85xx - freescale p1_twr TWR-P1025 p1_twr:TWR_P1025 -
+Active powerpc mpc85xx - freescale p2020come P2020COME_SDCARD P2020COME:SDCARD Ira W. Snyder <iws@ovro.caltech.edu>
+Active powerpc mpc85xx - freescale p2020come P2020COME_SPIFLASH P2020COME:SPIFLASH Ira W. Snyder <iws@ovro.caltech.edu>
+Active powerpc mpc85xx - freescale p2020ds P2020DS - -
+Active powerpc mpc85xx - freescale p2020ds P2020DS_36BIT P2020DS:36BIT -
+Active powerpc mpc85xx - freescale p2020ds P2020DS_DDR2 P2020DS:DDR2 -
+Active powerpc mpc85xx - freescale p2020ds P2020DS_SDCARD P2020DS:SDCARD -
+Active powerpc mpc85xx - freescale p2020ds P2020DS_SPIFLASH P2020DS:SPIFLASH -
+Active powerpc mpc85xx - freescale p2041rdb P2041RDB - -
+Active powerpc mpc85xx - freescale p2041rdb P2041RDB_NAND P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SDCARD P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SECURE_BOOT P2041RDB:SECURE_BOOT -
+Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
+Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun@freescale.com>
+Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 -
+Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -
+Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de>
+Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de>
+Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de>
+Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach <eibach@gdsys.de>
+Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek <dan@embeddedalley.com>
+Active powerpc mpc85xx - stx stxssa stxssa stxssa Dan Malek <dan@embeddedalley.com>
+Active powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek <dan@embeddedalley.com>
+Active powerpc mpc85xx - xes - xpedite520x - -
+Active powerpc mpc85xx - xes - xpedite537x - -
+Active powerpc mpc85xx - xes - xpedite550x - -
+Active powerpc mpc86xx - - - sbc8641d - Paul Gortmaker <paul.gortmaker@windriver.com>
+Active powerpc mpc86xx - freescale mpc8610hpcd MPC8610HPCD - -
+Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN MPC8641HPCN Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala <kumar.gala@freescale.com>
+Active powerpc mpc86xx - xes - xpedite517x - -
+Active powerpc mpc8xx - - - hermes - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - - lwmon - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - - quantum - -
+Active powerpc mpc8xx - - - RRvision - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - - spc1920 - -
+Active powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz@sinovee.com>
+Active powerpc mpc8xx - - - v37 - -
+Active powerpc mpc8xx - - adder Adder - Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8xx - - adder Adder87x Adder Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8xx - - adder AdderUSB Adder Yuli Barcohen <yuli@arabellasw.com>
+Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen@csiro.au>
+Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark@esteem.com>
+Active powerpc mpc8xx - - fads MPC86xADS - -
+Active powerpc mpc8xx - - fads MPC885ADS - -
+Active powerpc mpc8xx - - flagadm FLAGADM - Kári DavÃðsson <kd@flaga.is>
+Active powerpc mpc8xx - - gen860t GEN860T - Keith Outwater <Keith_Outwater@mvis.com>
+Active powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater <Keith_Outwater@mvis.com>
+Active powerpc mpc8xx - - icu862 ICU862 - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - icu862 ICU862_100MHz ICU862:100MHz Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - ip860 IP860 - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - ivm IVML24 IVML24:IVML24_16M Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - ivm IVML24_128 IVML24:IVML24_32M Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - ivm IVML24_256 IVML24:IVML24_64M Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - ivm IVMS8 IVMS8:IVMS8_16M Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - ivm IVMS8_128 IVMS8:IVMS8_32M Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - ivm IVMS8_256 IVMS8:IVMS8_64M Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - netphone NETPHONE NETPHONE:NETPHONE_VERSION=1 -
+Active powerpc mpc8xx - - netphone NETPHONE_V2 NETPHONE:NETPHONE_VERSION=2 -
+Active powerpc mpc8xx - - netta NETTA NETTA -
+Active powerpc mpc8xx - - netta NETTA_6412 NETTA:NETTA_6412=1 -
+Active powerpc mpc8xx - - netta NETTA_6412_SWAPHOOK NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1 -
+Active powerpc mpc8xx - - netta NETTA_ISDN NETTA:NETTA_ISDN=1 -
+Active powerpc mpc8xx - - netta NETTA_ISDN_6412 NETTA:NETTA_ISDN=1,NETTA_6412=1 -
+Active powerpc mpc8xx - - netta NETTA_ISDN_6412_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_6412=1,NETTA_SWAPHOOK=1 -
+Active powerpc mpc8xx - - netta NETTA_ISDN_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_SWAPHOOK=1 -
+Active powerpc mpc8xx - - netta NETTA_SWAPHOOK NETTA:NETTA_SWAPHOOK=1 -
+Active powerpc mpc8xx - - netta2 NETTA2 NETTA2:NETTA2_VERSION=1 -
+Active powerpc mpc8xx - - netta2 NETTA2_V2 NETTA2:NETTA2_VERSION=2 -
+Active powerpc mpc8xx - - netvia NETVIA NETVIA:NETVIA_VERSION=1 Pantelis Antoniou <panto@intracom.gr>
+Active powerpc mpc8xx - - netvia NETVIA_V2 NETVIA:NETVIA_VERSION=2 Pantelis Antoniou <panto@intracom.gr>
+Active powerpc mpc8xx - - r360mpi R360MPI - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - rbc823 RBC823 - -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW RPXlite_DW -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64 RPXlite_DW:RPXlite_64MHz -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20 -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_LCD RPXlite_DW:LCD,NEC_NL6448BC20 -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM RPXlite_DW:ENV_IS_IN_NVRAM -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64 RPXlite_DW:RPXlite_64MHz,ENV_IS_IN_NVRAM -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -
+Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_LCD RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -
+Active powerpc mpc8xx - - RRvision RRvision_LCD RRvision:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis <DGE@sixnetio.com>
+Active powerpc mpc8xx - - spd8xx SPD823TS - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - eltec mhpc MHPC - Frank Gottschling <fgottschling@eltec.de>
+Active powerpc mpc8xx - emk top860 TOP860 - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+Active powerpc mpc8xx - kup kup4k KUP4K - Klaus Heydeck <heydeck@kieback-peter.de>
+Active powerpc mpc8xx - kup kup4x KUP4X - Klaus Heydeck <heydeck@kieback-peter.de>
+Active powerpc mpc8xx - LEOX elpt860 ELPT860 - The LEOX team <team@leox.org>
+Active powerpc mpc8xx - manroland - uc100 - Stefan Roese <sr@denx.de>
+Active powerpc mpc8xx - snmc qs850 QS823 - -
+Active powerpc mpc8xx - snmc qs850 QS850 - -
+Active powerpc mpc8xx - snmc qs860t QS860T - -
+Active powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek <dan@embeddedalley.com>
+Active powerpc mpc8xx - tqc tqm8xx FPS850L - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx FPS860L - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx NSCU - -
+Active powerpc mpc8xx - tqc tqm8xx SM850 - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx TK885D - -
+Active powerpc mpc8xx - tqc tqm8xx TQM823L - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx TQM823L_LCD TQM823L:LCD,NEC_NL6448BC20 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx TQM823M - -
+Active powerpc mpc8xx - tqc tqm8xx TQM850L - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx TQM850M - -
+Active powerpc mpc8xx - tqc tqm8xx TQM855L - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx TQM855M - -
+Active powerpc mpc8xx - tqc tqm8xx TQM860L - Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx TQM860M - -
+Active powerpc mpc8xx - tqc tqm8xx TQM862L - -
+Active powerpc mpc8xx - tqc tqm8xx TQM862M - -
+Active powerpc mpc8xx - tqc tqm8xx TQM866M - -
+Active powerpc mpc8xx - tqc tqm8xx TQM885D - -
+Active powerpc mpc8xx - tqc tqm8xx TTTech TQM823L:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de>
+Active powerpc mpc8xx - tqc tqm8xx virtlab2 - -
+Active powerpc mpc8xx - tqc tqm8xx wtk TQM823L:LCD,SHARP_LQ065T9DR51U Wolfgang Denk <wd@denx.de>
+Active powerpc ppc4xx - - - csb272 - Tolunay Orkun <torkun@nextio.com>
+Active powerpc ppc4xx - - - csb472 - Tolunay Orkun <torkun@nextio.com>
+Active powerpc ppc4xx - - - korat - Larry Johnson <lrj@acm.org>
+Active powerpc ppc4xx - - - lwmon5 - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - - - pcs440ep - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - - - quad100hd - Gary Jennejohn <garyj@denx.de>
+Active powerpc ppc4xx - - - sbc405 - -
+Active powerpc ppc4xx - - - sc3 - Heiko Schocher <hs@denx.de>
+Active powerpc ppc4xx - - - t3corp - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - - - zeus - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - - g2000 G2000 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - - jse JSE - Stephen Williams <steve@icarus.com>
+Active powerpc ppc4xx - - korat korat_perm korat:KORAT_PERMANENT Larry Johnson <lrj@acm.org>
+Active powerpc ppc4xx - - lwmon5 lcd4_lwmon5 lwmon5:LCD4_LWMON5 Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - - w7o W7OLMC - Erik Theisen <etheisen@mindspring.com>
+Active powerpc ppc4xx - - w7o W7OLMG - Erik Theisen <etheisen@mindspring.com>
+Active powerpc ppc4xx - amcc - acadia - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc - bamboo - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc - bluestone - Tirumala Marri <tmarri@apm.com>
+Active powerpc ppc4xx - amcc - bubinga - -
+Active powerpc ppc4xx - amcc - ebony - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc - katmai - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc - luan - John Otken <jotken@softadvances.com>
+Active powerpc ppc4xx - amcc - makalu - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc - ocotea - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc - redwood - Feng Kan <fkan@amcc.com>
+Active powerpc ppc4xx - amcc - taihu - John Otken <jotken@softadvances.com>
+Active powerpc ppc4xx - amcc - taishan - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc - yucca - -
+Active powerpc ppc4xx - amcc acadia acadia_nand acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc bamboo bamboo_nand bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc canyonlands arches canyonlands:ARCHES Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc canyonlands canyonlands canyonlands:CANYONLANDS Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc canyonlands canyonlands_nand canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc canyonlands glacier canyonlands:GLACIER Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc canyonlands glacier_nand canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc kilauea haleakala kilauea:HALEAKALA Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc kilauea haleakala_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc kilauea kilauea kilauea:KILAUEA Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc kilauea kilauea_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc sequoia rainier sequoia:RAINIER Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc sequoia rainier_nand sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc sequoia rainier_ramboot sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc sequoia sequoia sequoia:SEQUOIA Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc sequoia sequoia_nand sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc sequoia sequoia_ramboot sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc walnut sycamore walnut Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc walnut walnut - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc yosemite yellowstone yosemite:YELLOWSTONE Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - amcc yosemite yosemite yosemite:YOSEMITE Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - avnet fx12mm fx12mm fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de>
+Active powerpc ppc4xx - avnet fx12mm fx12mm_flash fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de>
+Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
+Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval_flash v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
+Active powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff <dave@cray.com>
+Active powerpc ppc4xx - dave PPChameleonEVB CATcenter CATcenter:PPCHAMELEON_MODULE_MODEL=1 -
+Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_25 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 -
+Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_33 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 -
+Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB - Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_BA_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_BA_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_HI_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_HI_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_ME_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_ME_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+Active powerpc ppc4xx - esd apc405 APC405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd ar405 AR405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd ash405 ASH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd cms700 CMS700 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd cpci2dp CPCI2DP - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd cpci405 CPCI405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd cpci405 CPCI4052 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd cpci405 CPCI405AB - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd cpci405 CPCI405DT - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd cpciiser4 CPCIISER4 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd dp405 DP405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd du405 DU405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd du440 DU440 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd hh405 HH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd hub405 HUB405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd ocrtc OCRTC - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd pci405 PCI405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd plu405 PLU405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd pmc405 PMC405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd pmc405de PMC405DE - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd pmc440 PMC440 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd voh405 VOH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd vom405 VOM405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - esd wuh405 WUH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Active powerpc ppc4xx - gdsys - dlvision - Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys - gdppc440etx - Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys 405ep dlvision-10g - Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys 405ep io - Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys 405ep iocon - Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys 405ep neo - Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys 405ex io64 - Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys intip devconcenter intip:DEVCONCENTER Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - gdsys intip intip intip:INTIB Dirk Eibach <eibach@gdsys.de>
+Active powerpc ppc4xx - mosaixtech - icon - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - mpl mip405 MIP405 - Denis Peter <d.peter@mpl.ch>
+Active powerpc ppc4xx - mpl mip405 MIP405T MIP405:MIP405T Denis Peter <d.peter@mpl.ch>
+Active powerpc ppc4xx - mpl pip405 PIP405 - Denis Peter <d.peter@mpl.ch>
+Active powerpc ppc4xx - prodrive - alpr - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - prodrive - p3p440 - Stefan Roese <sr@denx.de>
+Active powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer (travis.sawyer@sandburst.com>
+Active powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer (travis.sawyer@sandburst.com>
+Active powerpc ppc4xx - xes - xpedite1000 - Peter Tyser <ptyser@xes-inc.com>
+Active powerpc ppc4xx - xilinx ml507 ml507 ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
+Active powerpc ppc4xx - xilinx ml507 ml507_flash ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
+Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000 Ricardo Ribalda <ricardo.ribalda@uam.es>
+Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic_flash xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
+Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1 Ricardo Ribalda <ricardo.ribalda@uam.es>
+Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic_flash xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
+Active sandbox sandbox - sandbox sandbox sandbox - Simon Glass <sjg@chromium.org>
+Active sh sh2 - renesas rsk7203 rsk7203 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh2 - renesas rsk7264 rsk7264 - Phil Edworthy <phil.edworthy@renesas.com>
+Active sh sh2 - renesas rsk7269 rsk7269 - -
+Active sh sh3 - - mpr2 mpr2 - Mark Jonas <mark.jonas@de.bosch.com>
+Active sh sh3 - - ms7720se ms7720se - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Active sh sh3 - - shmin shmin - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - - espt espt - -
+Active sh sh4 - - ms7722se ms7722se - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - - ms7750se ms7750se - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - alphaproject ap_sh4a_4a ap_sh4a_4a - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - renesas ap325rxa ap325rxa - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - renesas ecovec ecovec - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - renesas MigoR MigoR - -
+Active sh sh4 - renesas r0p7734 r0p7734 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - renesas r2dplus r2dplus - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - renesas r7780mp r7780mp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - renesas sh7752evb sh7752evb - -
+Active sh sh4 - renesas sh7757lcr sh7757lcr - -
+Active sh sh4 - renesas sh7763rdp sh7763rdp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Active sh sh4 - renesas sh7785lcr sh7785lcr - -
+Active sh sh4 - renesas sh7785lcr sh7785lcr_32bit sh7785lcr:SH_32BIT=1 -
+Active sparc leon2 - gaisler - grsim_leon2 - -
+Active sparc leon3 - gaisler - gr_cpci_ax2000 - -
+Active sparc leon3 - gaisler - gr_ep2s60 - -
+Active sparc leon3 - gaisler - gr_xc3s_1500 - -
+Active sparc leon3 - gaisler - grsim - -
+Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 -
+Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+Orphan arm arm925t - ti - omap1510inn - Kshitij Gupta <kshitij@ti.com>
+Orphan arm pxa - - - lubbock - (dead address) Kyle Harris <kharris@nexus-tech.net>
+Orphan powerpc 74xx_7xx - - evb64260 EVB64260 EVB64260 -
+Orphan powerpc 74xx_7xx - - evb64260 EVB64260_750CX EVB64260 Eran Man <eran@nbase.co.il>
+Orphan powerpc mpc824x - - mousse MOUSSE - -
+Orphan powerpc mpc8260 - - - rsdproto - -
+Orphan powerpc mpc8260 - - rpxsuper RPXsuper - -
+Orphan powerpc mpc8xx - - - RPXClassic - -
+Orphan powerpc mpc8xx - - - RPXlite - -
+Orphan powerpc mpc8xx - - fads ADS860 - -
+Orphan powerpc mpc8xx - - fads FADS823 - -
+Orphan powerpc mpc8xx - - fads FADS850SAR - -
+Orphan powerpc mpc8xx - - fads FADS860T - -
+Orphan powerpc mpc8xx - - genietv GENIETV - -
+Orphan powerpc mpc8xx - - mbx8xx MBX - -
+Orphan powerpc mpc8xx - - mbx8xx MBX860T - -
+Orphan powerpc mpc8xx - - nx823 NX823 - -
const char *type_name = genimg_get_type_name(os.type);
- load_buf = map_sysmem(load, image_len);
+ load_buf = map_sysmem(load, unc_len);
image_buf = map_sysmem(image_start, image_len);
switch (comp) {
case IH_COMP_NONE:
}
#endif /* CONFIG_LZMA */
#ifdef CONFIG_LZO
- case IH_COMP_LZO:
+ case IH_COMP_LZO: {
+ size_t size;
+
printf(" Uncompressing %s ... ", type_name);
- ret = lzop_decompress(image_buf, image_len, load_buf,
- &unc_len);
+ ret = lzop_decompress(image_buf, image_len, load_buf, &size);
if (ret != LZO_E_OK) {
printf("LZO: uncompress or overwrite error %d "
"- must RESET board to recover\n", ret);
return BOOTM_ERR_RESET;
}
- *load_end = load + unc_len;
+ *load_end = load + size;
break;
+ }
#endif /* CONFIG_LZO */
default:
printf("Unimplemented compression type %d\n", comp);
printf("Current bus is %d\n", i2c_get_bus_num());
else {
bus_no = simple_strtoul(argv[1], NULL, 10);
+#if defined(CONFIG_SYS_I2C)
if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) {
printf("Invalid bus %d\n", bus_no);
return -1;
}
+#endif
printf("Setting bus to %d\n", bus_no);
ret = i2c_set_bus_num(bus_no);
if (ret)
#include <bzlib.h>
#endif
#include <asm/byteorder.h>
+#include <asm/io.h>
#ifndef CONFIG_SYS_XIMG_LEN
/* use 8MByte as default max gunzip size */
ulong data, len, count;
int verify;
int part = 0;
- image_header_t *hdr;
+ image_header_t *hdr = NULL;
#if defined(CONFIG_FIT)
const char *uname = NULL;
const void* fit_hdr;
* which requires at most 2300 KB of memory.
*/
i = BZ2_bzBuffToBuffDecompress(
- (char *)ntohl(hdr->ih_load),
+ map_sysmem(ntohl(hdr->ih_load), 0),
&unc_len, (char *)data, len,
CONFIG_SYS_MALLOC_LEN < (4096 * 1024),
0);
{ IH_TYPE_SCRIPT, "script", "Script", },
{ IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
{ IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",},
+ { IH_TYPE_MXSIMAGE, "mxsimage", "Freescale MXS Boot Image",},
{ -1, "", "", },
};
/*******************************************************************************
* Parse the config, located in buffer, and fills the dev->config structure.
* Note that all little/big endian swapping are done automatically.
+ * (wTotalLength has already been swapped and sanitized when it was read.)
*/
static int usb_parse_config(struct usb_device *dev,
unsigned char *buffer, int cfgno)
head->bDescriptorType);
return -1;
}
- memcpy(&dev->config, buffer, buffer[0]);
- le16_to_cpus(&(dev->config.desc.wTotalLength));
+ if (head->bLength != USB_DT_CONFIG_SIZE) {
+ printf("ERROR: Invalid USB CFG length (%d)\n", head->bLength);
+ return -1;
+ }
+ memcpy(&dev->config, head, USB_DT_CONFIG_SIZE);
dev->config.no_of_if = 0;
index = dev->config.desc.bLength;
/* Ok the first entry must be a configuration entry,
* now process the others */
head = (struct usb_descriptor_header *) &buffer[index];
- while (index + 1 < dev->config.desc.wTotalLength) {
+ while (index + 1 < dev->config.desc.wTotalLength && head->bLength) {
switch (head->bDescriptorType) {
case USB_DT_INTERFACE:
+ if (head->bLength != USB_DT_INTERFACE_SIZE) {
+ printf("ERROR: Invalid USB IF length (%d)\n",
+ head->bLength);
+ break;
+ }
+ if (index + USB_DT_INTERFACE_SIZE >
+ dev->config.desc.wTotalLength) {
+ puts("USB IF descriptor overflowed buffer!\n");
+ break;
+ }
if (((struct usb_interface_descriptor *) \
- &buffer[index])->bInterfaceNumber != curr_if_num) {
+ head)->bInterfaceNumber != curr_if_num) {
/* this is a new interface, copy new desc */
ifno = dev->config.no_of_if;
+ if (ifno >= USB_MAXINTERFACES) {
+ puts("Too many USB interfaces!\n");
+ /* try to go on with what we have */
+ return 1;
+ }
if_desc = &dev->config.if_desc[ifno];
dev->config.no_of_if++;
- memcpy(if_desc, &buffer[index], buffer[index]);
+ memcpy(if_desc, head,
+ USB_DT_INTERFACE_SIZE);
if_desc->no_of_ep = 0;
if_desc->num_altsetting = 1;
curr_if_num =
}
break;
case USB_DT_ENDPOINT:
+ if (head->bLength != USB_DT_ENDPOINT_SIZE) {
+ printf("ERROR: Invalid USB EP length (%d)\n",
+ head->bLength);
+ break;
+ }
+ if (index + USB_DT_ENDPOINT_SIZE >
+ dev->config.desc.wTotalLength) {
+ puts("USB EP descriptor overflowed buffer!\n");
+ break;
+ }
+ if (ifno < 0) {
+ puts("Endpoint descriptor out of order!\n");
+ break;
+ }
epno = dev->config.if_desc[ifno].no_of_ep;
if_desc = &dev->config.if_desc[ifno];
+ if (epno > USB_MAXENDPOINTS) {
+ printf("Interface %d has too many endpoints!\n",
+ if_desc->desc.bInterfaceNumber);
+ return 1;
+ }
/* found an endpoint */
if_desc->no_of_ep++;
- memcpy(&if_desc->ep_desc[epno],
- &buffer[index], buffer[index]);
+ memcpy(&if_desc->ep_desc[epno], head,
+ USB_DT_ENDPOINT_SIZE);
ep_wMaxPacketSize = get_unaligned(&dev->config.\
if_desc[ifno].\
ep_desc[epno].\
debug("if %d, ep %d\n", ifno, epno);
break;
case USB_DT_SS_ENDPOINT_COMP:
+ if (head->bLength != USB_DT_SS_EP_COMP_SIZE) {
+ printf("ERROR: Invalid USB EPC length (%d)\n",
+ head->bLength);
+ break;
+ }
+ if (index + USB_DT_SS_EP_COMP_SIZE >
+ dev->config.desc.wTotalLength) {
+ puts("USB EPC descriptor overflowed buffer!\n");
+ break;
+ }
+ if (ifno < 0 || epno < 0) {
+ puts("EPC descriptor out of order!\n");
+ break;
+ }
if_desc = &dev->config.if_desc[ifno];
- memcpy(&if_desc->ss_ep_comp_desc[epno],
- &buffer[index], buffer[index]);
+ memcpy(&if_desc->ss_ep_comp_desc[epno], head,
+ USB_DT_SS_EP_COMP_SIZE);
break;
default:
if (head->bLength == 0)
unsigned char *buffer, int cfgno)
{
int result;
- unsigned int tmp;
+ unsigned int length;
struct usb_config_descriptor *config;
config = (struct usb_config_descriptor *)&buffer[0];
"(expected %i, got %i)\n", 9, result);
return -1;
}
- tmp = le16_to_cpu(config->wTotalLength);
+ length = le16_to_cpu(config->wTotalLength);
- if (tmp > USB_BUFSIZ) {
- printf("usb_get_configuration_no: failed to get " \
- "descriptor - too long: %d\n", tmp);
+ if (length > USB_BUFSIZ) {
+ printf("%s: failed to get descriptor - too long: %d\n",
+ __func__, length);
return -1;
}
- result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, tmp);
- debug("get_conf_no %d Result %d, wLength %d\n", cfgno, result, tmp);
+ result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, length);
+ debug("get_conf_no %d Result %d, wLength %d\n", cfgno, result, length);
+ config->wTotalLength = length; /* validated, with CPU byte order */
+
return result;
}
static struct usb_hub_device hub_dev[USB_MAX_HUB];
static int usb_hub_index;
+__weak void usb_hub_reset_devices(int port)
+{
+ return;
+}
static int usb_get_hub_descriptor(struct usb_device *dev, void *data, int size)
{
static int usb_hub_configure(struct usb_device *dev)
{
- int i;
+ int i, length;
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, USB_BUFSIZ);
unsigned char *bitmap;
short hubCharacteristics;
}
descriptor = (struct usb_hub_descriptor *)buffer;
- /* silence compiler warning if USB_BUFSIZ is > 256 [= sizeof(char)] */
- i = descriptor->bLength;
- if (i > USB_BUFSIZ) {
- debug("usb_hub_configure: failed to get hub " \
- "descriptor - too long: %d\n", descriptor->bLength);
- return -1;
- }
+ length = min(descriptor->bLength, sizeof(struct usb_hub_descriptor));
- if (usb_get_hub_descriptor(dev, buffer, descriptor->bLength) < 0) {
+ if (usb_get_hub_descriptor(dev, buffer, length) < 0) {
debug("usb_hub_configure: failed to get hub " \
"descriptor 2nd giving up %lX\n", dev->status);
return -1;
}
- memcpy((unsigned char *)&hub->desc, buffer, descriptor->bLength);
+ memcpy((unsigned char *)&hub->desc, buffer, length);
/* adjust 16bit values */
put_unaligned(le16_to_cpu(get_unaligned(
&descriptor->wHubCharacteristics)),
"" : "no ");
usb_hub_power_on(hub);
+ /*
+ * Reset any devices that may be in a bad state when applying
+ * the power. This is a __weak function. Resetting of the devices
+ * should occur in the board file of the device.
+ */
+ for (i = 0; i < dev->maxchild; i++)
+ usb_hub_reset_devices(i + 1);
+
for (i = 0; i < dev->maxchild; i++) {
ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
unsigned short portstatus, portchange;
uint8_t flags;
};
+extern int __maybe_unused net_busy_flag;
+
+/* The period of time between two calls of usb_kbd_testc(). */
+static unsigned long __maybe_unused kbd_testc_tms;
+
/* Generic keyboard event polling. */
void usb_kbd_generic_poll(void)
{
struct usb_device *usb_kbd_dev;
struct usb_kbd_pdata *data;
+#ifdef CONFIG_CMD_NET
+ /*
+ * If net_busy_flag is 1, NET transfer is running,
+ * then we check key-pressed every second (first check may be
+ * less than 1 second) to improve TFTP booting performance.
+ */
+ if (net_busy_flag && (get_timer(kbd_testc_tms) < CONFIG_SYS_HZ))
+ return 0;
+ kbd_testc_tms = get_timer(0);
+#endif
dev = stdio_get_by_name(DEVNAME);
usb_kbd_dev = (struct usb_device *)dev->priv;
data = usb_kbd_dev->privptr;
endif
# TODO(sjg@chromium.org): Is this correct on Mac OS?
+
+# MXSImage needs LibSSL
+ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
+HOSTLIBS += -lssl -lcrypto
+# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
+# the mxsimage support within tools/mxsimage.c .
+HOSTCFLAGS += -DCONFIG_MXS
+endif
+
ifdef CONFIG_FIT_SIGNATURE
HOSTLIBS += -lssl -lcrypto
CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
endif
-ifneq ($(CONFIG_SPL_TEXT_BASE),)
-CPPFLAGS += -DCONFIG_SPL_TEXT_BASE=$(CONFIG_SPL_TEXT_BASE)
-endif
-
-ifneq ($(CONFIG_SPL_PAD_TO),)
-CPPFLAGS += -DCONFIG_SPL_PAD_TO=$(CONFIG_SPL_PAD_TO)
-endif
-
-ifneq ($(CONFIG_TPL_PAD_TO),)
-CPPFLAGS += -DCONFIG_TPL_PAD_TO=$(CONFIG_TPL_PAD_TO)
-endif
-
-ifneq ($(CONFIG_UBOOT_PAD_TO),)
-CPPFLAGS += -DCONFIG_UBOOT_PAD_TO=$(CONFIG_UBOOT_PAD_TO)
-endif
-
ifeq ($(CONFIG_SPL_BUILD),y)
CPPFLAGS += -DCONFIG_SPL_BUILD
ifeq ($(CONFIG_TPL_BUILD),y)
endif
endif
-ifneq ($(RESET_VECTOR_ADDRESS),)
-CPPFLAGS += -DRESET_VECTOR_ADDRESS=$(RESET_VECTOR_ADDRESS)
-endif
-
ifneq ($(OBJTREE),$(SRCTREE))
CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include
endif
CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o)
CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o)
CONFIG_SPL_RAM_DEVICE (common/spl/spl.c)
-
+CONFIG_SPL_WATCHDOG_SUPPORT (drivers/watchdog/libwatchdog.o)
Normally CPU is assumed to be the same between the SPL and normal
u-boot build. However it is possible to specify a different CPU for
It can be 2, 4, 8, 12 or 24.
2. The PMECC sector size: CONFIG_PMECC_SECTOR_SIZE.
It only can be 512 or 1024.
- 3. The PMECC index lookup table's offsets in ROM code: CONFIG_PMECC_INDEX_TABLE_OFFSET.
- In the chip datasheet section "Boot Stragegies", you can find
- two Galois Field Table in the ROM code. One table is for 512-bytes
- sector. Another is for 1024-byte sector. Each Galois Field includes
- two sub-table: indext table & alpha table.
- In the beginning of each Galois Field Table is the index table,
- Alpha table is in the following.
- So the index table's offset is same as the Galois Field Table.
-
- Please set CONFIG_PMECC_INDEX_TABLE_OFFSET correctly according the
- Galois Field Table's offset base on the sector size you used.
Take AT91SAM9X5EK as an example, the board definition file likes:
#define CONFIG_ATMEL_NAND_HW_PMECC 1
#define CONFIG_PMECC_CAP 2
#define CONFIG_PMECC_SECTOR_SIZE 512
-#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000
-NOTE: If you use 1024 as the sector size, then need set 0x10000 as the
- CONFIG_PMECC_INDEX_TABLE_OFFSET
For more details refer Chapter 2 - System Boot and section 2.14
(flash header description) of the processor's manual.
-This implementation does not use at the moment the secure boot feature
-of the processor. The image is generated disabling all security fields.
-
Command syntax:
--------------
./tools/mkimage -l <mx u-boot_file>
Example:
BOOT_FROM spi
+ CSF value
+
+ Total size of CSF (Command Sequence File)
+ used for Secure Boot/ High Assurance Boot
+ (HAB).
+
+ Using this command will populate the IVT
+ (Initial Vector Table) CSF pointer and adjust
+ the length fields only. The CSF itself needs
+ to be generated with Freescale tools and
+ 'manually' appended to the u-boot.imx file.
+
+ The CSF is then simply concatenated
+ to the u-boot image, making a signed bootloader,
+ that the processor can verify
+ if the fuses for the keys are burned.
+
+ Further infos how to configure the SOC to verify
+ the bootloader can be found in the "High
+ Assurance Boot Version Application Programming
+ Interface Reference Manual" as part of the
+ Freescale Code Signing Tool, available on the
+ manufacturer's website.
+
+ Example:
+ CSF 0x2000
+
DATA type address value
type: word=4, halfword=2, byte=1
--- /dev/null
+High Assurance Boot (HAB) for i.MX6 CPUs
+
+To authenticate U-Boot only by the CPU there is no code required in
+U-Boot itself. However, the U-Boot image to be programmed into the
+boot media needs to be properly constructed, i.e. it must contain a
+proper Command Sequence File (CSF).
+
+The Initial Vector Table contains a pointer to the CSF. Please see
+doc/README.imximage for how to prepare u-boot.imx.
+
+The CSF itself is being generated by Freescale HAB tools.
+
+mkimage will output additional information about "HAB Blocks"
+which can be used in the Freescale tooling to authenticate U-Boot
+(entries in the CSF file).
+
+Image Type: Freescale IMX Boot Image
+Image Ver: 2 (i.MX53/6 compatible)
+Data Size: 327680 Bytes = 320.00 kB = 0.31 MB
+Load Address: 177ff420
+Entry Point: 17800000
+HAB Blocks: 177ff400 00000000 0004dc00
+ ^^^^^^^^ ^^^^^^^^ ^^^^^^^^
+ | | |
+ | | -------- (1)
+ | |
+ | ------------------- (2)
+ |
+ --------------------------- (3)
+
+(1) Size of area in file u-boot.imx to sign
+ This area should include the IVT, the Boot Data the DCD
+ and U-Boot itself.
+(2) Start of area in u-boot.imx to sign
+(3) Start of area in RAM to authenticate
+
+CONFIG_SECURE_BOOT currently enables only an additional command
+'hab_status' in U-Boot to retrieve the HAB status and events. This
+can be useful while developing and testing HAB.
+
+Commands to generate a signed U-Boot using Freescale HAB tools:
+cst --o U-Boot_CSF.bin < U-Boot.CSF
+objcopy -I binary -O binary --pad-to 0x2000 --gap-fill=0x00 \
+ U-Boot_CSF.bin U-Boot_CSF_pad.bin
+cat u-boot.imx U-Boot_CSF_pad.bin > u-boot-signed.imx
+
+NOTE: U-Boot_CSF.bin needs to be padded to the value specified in
+the imximage.cfg file.
--- /dev/null
+Freescale i.MX233/i.MX28 SB image generator via mkimage
+=======================================================
+
+This tool allows user to produce SB BootStream encrypted with a zero key.
+Such a BootStream is then bootable on i.MX23/i.MX28.
+
+Usage -- producing image:
+=========================
+The mxsimage tool is targeted to be a simple replacement for the elftosb2 .
+To generate an image, write an image configuration file and run:
+
+ mkimage -A arm -O u-boot -T mxsimage -n <path to configuration file> \
+ <output bootstream file>
+
+The output bootstream file is usually using the .sb file extension. Note
+that the example configuration files for producing bootable BootStream with
+the U-Boot bootloader can be found under arch/arm/boot/cpu/arm926ejs/mxs/
+directory. See the following files:
+
+ mxsimage.mx23.cfg -- This is an example configuration for i.MX23
+ mxsimage.mx28.cfg -- This is an example configuration for i.MX28
+
+Each configuration file uses very simple instruction semantics and a few
+additional rules have to be followed so that a useful image can be produced.
+These semantics and rules will be outlined now.
+
+- Each line of the configuration file contains exactly one instruction.
+- Every numeric value must be encoded in hexadecimal and in format 0xabcdef12 .
+- The configuration file is a concatenation of blocks called "sections" and
+ optionally "DCD blocks" (see below).
+ - Each "section" is started by the "SECTION" instruction.
+ - The "SECTION" instruction has the following semantics:
+
+ SECTION u32_section_number [BOOTABLE]
+ - u32_section_number :: User-selected ID of the section
+ - BOOTABLE :: Sets the section as bootable
+
+ - A bootable section is one from which the BootROM starts executing
+ subsequent instructions or code. Exactly one section must be selected
+ as bootable, usually the one containing the instructions and data to
+ load the bootloader.
+
+ - A "SECTION" must be immediatelly followed by a "TAG" instruction.
+ - The "TAG" instruction has the following semantics:
+
+ TAG [LAST]
+ - LAST :: Flag denoting the last section in the file
+
+ - After a "TAG" unstruction, any of the following instructions may follow
+ in any order and any quantity:
+
+ NOOP
+ - This instruction does nothing
+
+ LOAD u32_address string_filename
+ - Instructs the BootROM to load file pointed by "string_filename" onto
+ address "u32_address".
+
+ LOAD IVT u32_address u32_IVT_entry_point
+ - Crafts and loads IVT onto address "u32_address" with the entry point
+ of u32_IVT_entry_point.
+ - i.MX28-specific instruction!
+
+ LOAD DCD u32_address u32_DCD_block_ID
+ - Loads the DCD block with ID "u32_DCD_block_ID" onto address
+ "u32_address" and executes the contents of this DCD block
+ - i.MX28-specific instruction!
+
+ FILL u32_address u32_pattern u32_length
+ - Starts to write memory from addres "u32_address" with a pattern
+ specified by "u32_pattern". Writes exactly "u32_length" bytes of the
+ pattern.
+
+ JUMP [HAB] u32_address [u32_r0_arg]
+ - Jumps onto memory address specified by "u32_address" by setting this
+ address in PT. The BootROM will pass the "u32_r0_arg" value in ARM
+ register "r0" to the executed code if this option is specified.
+ Otherwise, ARM register "r0" will default to value 0x00000000. The
+ optional "HAB" flag is i.MX28-specific flag turning on the HAB boot.
+
+ CALL [HAB] u32_address [u32_r0_arg]
+ - See JUMP instruction above, as the operation is exactly the same with
+ one difference. The CALL instruction does allow returning into the
+ BootROM from the executed code. U-Boot makes use of this in it's SPL
+ code.
+
+ MODE string_mode
+ - Restart the CPU and start booting from device specified by the
+ "string_mode" argument. The "string_mode" differs for each CPU
+ and can be:
+ i.MX23, string_mode = USB/I2C/SPI1_FLASH/SPI2_FLASH/NAND_BCH
+ JTAG/SPI3_EEPROM/SD_SSP0/SD_SSP1
+ i.MX28, string_mode = USB/I2C/SPI2_FLASH/SPI3_FLASH/NAND_BCH
+ JTAG/SPI2_EEPROM/SD_SSP0/SD_SSP1
+
+ - An optional "DCD" blocks can be added at the begining of the configuration
+ file. Note that the DCD is only supported on i.MX28.
+ - The DCD blocks must be inserted before the first "section" in the
+ configuration file.
+ - The DCD block has the following semantics:
+
+ DCD u32_DCD_block_ID
+ - u32_DCD_block_ID :: The ID number of the DCD block, must match
+ the ID number used by "LOAD DCD" instruction.
+
+ - The DCD block must be followed by one of the following instructions. All
+ of the instructions operate either on 1, 2 or 4 bytes. This is selected by
+ the 'n' suffix of the instruction:
+
+ WRITE.n u32_address u32_value
+ - Write the "u32_value" to the "u32_address" address.
+
+ ORR.n u32_address u32_value
+ - Read the "u32_address", perform a bitwise-OR with the "u32_value" and
+ write the result back to "u32_address".
+
+ ANDC.n u32_address u32_value
+ - Read the "u32_address", perform a bitwise-AND with the complement of
+ "u32_value" and write the result back to "u32_address".
+
+ EQZ.n u32_address u32_count
+ - Read the "u32_address" at most "u32_count" times and test if the value
+ read is zero. If it is, break the loop earlier.
+
+ NEZ.n u32_address u32_count
+ - Read the "u32_address" at most "u32_count" times and test if the value
+ read is non-zero. If it is, break the loop earlier.
+
+ EQ.n u32_address u32_mask
+ - Read the "u32_address" in a loop and test if the result masked with
+ "u32_mask" equals the "u32_mask". If the values are equal, break the
+ reading loop.
+
+ NEQ.n u32_address u32_mask
+ - Read the "u32_address" in a loop and test if the result masked with
+ "u32_mask" does not equal the "u32_mask". If the values are not equal,
+ break the reading loop.
+
+ NOOP
+ - This instruction does nothing.
+
+- If the verbose output from the BootROM is enabled, the BootROM will produce a
+ letter on the Debug UART for each instruction it started processing. Here is a
+ mapping between the above instructions and the BootROM verbose output:
+
+ H -- SB Image header loaded
+ T -- TAG instruction
+ N -- NOOP instruction
+ L -- LOAD instruction
+ F -- FILL instruction
+ J -- JUMP instruction
+ C -- CALL instruction
+ M -- MODE instruction
+
+Usage -- verifying image:
+=========================
+
+The mxsimage can also verify and dump contents of an image. Use the following
+syntax to verify and dump contents of an image:
+
+ mkimage -l <input bootstream file>
+
+This will output all the information from the SB image header and all the
+instructions contained in the SB image. It will also check if the various
+checksums in the SB image are correct.
alias jhersh Joe Hershberger <joe.hershberger@gmail.com>
alias kimphill Kim Phillips <kim.phillips@freescale.com>
alias macpaul Macpaul Lin <macpaul@andestech.com>
-alias marex Marek Vasut <marek.vasut@gmail.com>
+alias marex Marek Vasut <marex@denx.de>
alias monstr Michal Simek <monstr@monstr.eu>
+alias panto Pantelis Antoniou <panto@antoniou-consulting.com>
alias prafulla Prafulla Wadaskar <prafulla@marvell.com>
alias prom Minkyu Kang <mk7.kang@samsung.com>
alias rbohmer Remy Bohmer <linux@bohmer.net>
alias kerneldoc uboot, marex
alias fdt uboot, Jerry Van Baren <vanbaren@cideas.com>
alias i2c uboot, hs
-alias mmc uboot, afleming
+alias mmc uboot, panto
alias nand uboot, scottwood
alias net uboot, jhersh
alias usb uboot, marex
#include <asm/io.h>
#include <malloc.h>
#include <scsi.h>
-#include <ata.h>
+#include <libata.h>
#include <linux/ctype.h>
#include <ahci.h>
static int ata_io_flush(u8 port);
struct ahci_probe_ent *probe_ent = NULL;
-hd_driveid_t *ataid[AHCI_MAX_PORTS];
+u16 *ataid[AHCI_MAX_PORTS];
#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
#endif
/* Maximum timeouts for each event */
-#define WAIT_MS_SPINUP 10000
+#define WAIT_MS_SPINUP 20000
#define WAIT_MS_DATAIO 5000
#define WAIT_MS_FLUSH 5000
#define WAIT_MS_LINKUP 4
return (i < timeout_msec) ? 0 : -1;
}
+int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)
+{
+ u32 tmp;
+ int j = 0;
+ u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
+
+ /*
+ * Bring up SATA link.
+ * SATA link bringup time is usually less than 1 ms; only very
+ * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
+ */
+ while (j < WAIT_MS_LINKUP) {
+ tmp = readl(port_mmio + PORT_SCR_STAT);
+ tmp &= PORT_SCR_STAT_DET_MASK;
+ if (tmp == PORT_SCR_STAT_DET_PHYRDY)
+ return 0;
+ udelay(1000);
+ j++;
+ }
+ return 1;
+}
static int ahci_host_init(struct ahci_probe_ent *probe_ent)
{
#endif
volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
u32 tmp, cap_save, cmd;
- int i, j;
+ int i, j, ret;
volatile u8 *port_mmio;
+ u32 port_map;
debug("ahci_host_init: start\n");
#endif
probe_ent->cap = readl(mmio + HOST_CAP);
probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
+ port_map = probe_ent->port_map;
probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
debug("cap 0x%x port_map 0x%x n_ports %d\n",
probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
for (i = 0; i < probe_ent->n_ports; i++) {
+ if (!(port_map & (1 << i)))
+ continue;
probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
port_mmio = (u8 *) probe_ent->port[i].port_mmio;
ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
cmd |= PORT_CMD_SPIN_UP;
writel_with_flush(cmd, port_mmio + PORT_CMD);
- /* Bring up SATA link.
- * SATA link bringup time is usually less than 1 ms; only very
- * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
- */
- j = 0;
- while (j < WAIT_MS_LINKUP) {
- tmp = readl(port_mmio + PORT_SCR_STAT);
- if ((tmp & 0xf) == 0x3)
- break;
- udelay(1000);
- j++;
- }
- if (j == WAIT_MS_LINKUP) {
+ /* Bring up SATA link. */
+ ret = ahci_link_up(probe_ent, i);
+ if (ret) {
printf("SATA link %d timeout.\n", i);
continue;
} else {
j = 0;
while (j < WAIT_MS_SPINUP) {
tmp = readl(port_mmio + PORT_TFDATA);
- if (!(tmp & (ATA_STAT_BUSY | ATA_STAT_DRQ)))
+ if (!(tmp & (ATA_BUSY | ATA_DRQ)))
break;
udelay(1000);
+ tmp = readl(port_mmio + PORT_SCR_STAT);
+ tmp &= PORT_SCR_STAT_DET_MASK;
+ if (tmp == PORT_SCR_STAT_DET_PHYRDY)
+ break;
j++;
}
+
+ tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
+ if (tmp == PORT_SCR_STAT_DET_COMINIT) {
+ debug("SATA link %d down (COMINIT received), retrying...\n", i);
+ i--;
+ continue;
+ }
+
printf("Target spinup took %d ms.\n", j);
if (j == WAIT_MS_SPINUP)
debug("timeout.\n");
/* register linkup ports */
tmp = readl(port_mmio + PORT_SCR_STAT);
debug("SATA port %d status: 0x%x\n", i, tmp);
- if ((tmp & 0xf) == 0x03)
+ if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
probe_ent->link_port_map |= (0x01 << i);
}
u16 vendor;
int rc;
- memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
-
probe_ent = malloc(sizeof(struct ahci_probe_ent));
memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
probe_ent->dev = pdev;
memset(fis, 0, sizeof(fis));
fis[0] = 0x27;
fis[1] = 1 << 7;
- fis[2] = ATA_CMD_SETF;
+ fis[2] = ATA_CMD_SET_FEATURES;
fis[3] = SETFEATURES_XFER;
fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
return (char *)target;
}
-
-static void dump_ataid(hd_driveid_t *ataid)
-{
- debug("(49)ataid->capability = 0x%x\n", ataid->capability);
- debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
- debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
- debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
- debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
- debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
- debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
- debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
- debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
- debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
- debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
- debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
- debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
- debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
- debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
-}
-
-
/*
* SCSI INQUIRY command operation.
*/
static int ata_scsiop_inquiry(ccb *pccb)
{
- u8 hdr[] = {
+ static const u8 hdr[] = {
0,
0,
0x5, /* claim SPC-3 version compatibility */
95 - 4,
};
u8 fis[20];
- u8 *tmpid;
+ u16 *tmpid;
u8 port;
/* Clean ccb data buffer */
/* Construct the FIS */
fis[0] = 0x27; /* Host to device FIS. */
fis[1] = 1 << 7; /* Command FIS. */
- fis[2] = ATA_CMD_IDENT; /* Command byte. */
+ fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
/* Read id from sata */
port = pccb->target;
- if (!(tmpid = malloc(sizeof(hd_driveid_t))))
+ tmpid = malloc(ATA_ID_WORDS * 2);
+ if (!tmpid)
return -ENOMEM;
- if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid,
- sizeof(hd_driveid_t), 0)) {
+ if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
+ ATA_ID_WORDS * 2, 0)) {
debug("scsi_ahci: SCSI inquiry command failure.\n");
+ free(tmpid);
return -EIO;
}
if (ataid[port])
free(ataid[port]);
- ataid[port] = (hd_driveid_t *) tmpid;
+ ataid[port] = tmpid;
+ ata_swap_buf_le16(tmpid, ATA_ID_WORDS);
memcpy(&pccb->pdata[8], "ATA ", 8);
- ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
- ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
+ ata_id_strcpy((u16 *) &pccb->pdata[16], &tmpid[ATA_ID_PROD], 16);
+ ata_id_strcpy((u16 *) &pccb->pdata[32], &tmpid[ATA_ID_FW_REV], 4);
- dump_ataid(ataid[port]);
+#ifdef DEBUG
+ ata_dump_id(tmpid);
+#endif
return 0;
}
now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
- transfer_size = ATA_BLOCKSIZE * now_blocks;
+ transfer_size = ATA_SECT_SIZE * now_blocks;
if (transfer_size > user_buffer_size) {
printf("scsi_ahci: Error: buffer too small.\n");
return -EIO;
static int ata_scsiop_read_capacity10(ccb *pccb)
{
u32 cap;
+ u64 cap64;
u32 block_size;
if (!ataid[pccb->target]) {
return -EPERM;
}
- cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
- if (cap == 0xfffffff) {
- unsigned short *cap48 = ataid[pccb->target]->lba48_capacity;
- if (cap48[2] || cap48[3]) {
- cap = 0xffffffff;
- } else {
- cap = (le16_to_cpu(cap48[1]) << 16) |
- (le16_to_cpu(cap48[0]));
- }
- }
+ cap64 = ata_id_n_sectors(ataid[pccb->target]);
+ if (cap64 > 0x100000000ULL)
+ cap64 = 0xffffffff;
- cap = cpu_to_be32(cap);
+ cap = cpu_to_be32(cap64);
memcpy(pccb->pdata, &cap, sizeof(cap));
block_size = cpu_to_be32((u32)512);
return -EPERM;
}
- cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
- if (cap == 0xfffffff) {
- memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap));
- cap = le64_to_cpu(cap);
- }
-
+ cap = ata_id_n_sectors(ataid[pccb->target]);
cap = cpu_to_be64(cap);
memcpy(pccb->pdata, &cap, sizeof(cap));
int i, rc = 0;
u32 linkmap;
- memset(ataid, 0, sizeof(ataid));
-
probe_ent = malloc(sizeof(struct ahci_probe_ent));
memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
return ret;
}
+static int dfu_flush_medium_nand(struct dfu_entity *dfu)
+{
+ int ret = 0;
+
+ /* in case of ubi partition, erase rest of the partition */
+ if (dfu->data.nand.ubi) {
+ nand_info_t *nand;
+ nand_erase_options_t opts;
+
+ if (nand_curr_device < 0 ||
+ nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
+ !nand_info[nand_curr_device].name) {
+ printf("%s: invalid nand device\n", __func__);
+ return -1;
+ }
+
+ nand = &nand_info[nand_curr_device];
+
+ memset(&opts, 0, sizeof(opts));
+ opts.offset = dfu->data.nand.start + dfu->offset +
+ dfu->bad_skip;
+ opts.length = dfu->data.nand.start +
+ dfu->data.nand.size - opts.offset;
+ ret = nand_erase_opts(nand, &opts);
+ if (ret != 0)
+ printf("Failure erase: %d\n", ret);
+ }
+
+ return ret;
+}
+
int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s)
{
char *st;
int ret, dev, part;
+ dfu->data.nand.ubi = 0;
dfu->dev_type = DFU_DEV_NAND;
st = strsep(&s, " ");
if (!strcmp(st, "raw")) {
dfu->data.nand.start = simple_strtoul(s, &s, 16);
s++;
dfu->data.nand.size = simple_strtoul(s, &s, 16);
- } else if (!strcmp(st, "part")) {
+ } else if ((!strcmp(st, "part")) || (!strcmp(st, "partubi"))) {
char mtd_id[32];
struct mtd_device *mtd_dev;
u8 part_num;
dfu->data.nand.start = pi->offset;
dfu->data.nand.size = pi->size;
-
+ if (!strcmp(st, "partubi"))
+ dfu->data.nand.ubi = 1;
} else {
printf("%s: Memory layout (%s) not supported!\n", __func__, st);
return -1;
dfu->read_medium = dfu_read_medium_nand;
dfu->write_medium = dfu_write_medium_nand;
+ dfu->flush_medium = dfu_flush_medium_nand;
/* initial state */
dfu->inited = 0;
/*
- * Memory Setup stuff - taken from blob memsetup.S
+ * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
*
* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
*
* SPDX-License-Identifier: GPL-2.0+
*/
-/*
- * WARNING:
- *
- * As the code is right now, it expects all PIO ports A,B,C,...
- * to be evenly spaced in the memory map:
- * ATMEL_BASE_PIOA + port * sizeof at91pio_t
- * This might not necessaryly be true in future Atmel SoCs.
- * This code should be fixed to use a pointer array to the ports.
- */
-
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pio.h>
+static struct at91_port *at91_pio_get_port(unsigned port)
+{
+ switch (port) {
+ case AT91_PIO_PORTA:
+ return (struct at91_port *)ATMEL_BASE_PIOA;
+ case AT91_PIO_PORTB:
+ return (struct at91_port *)ATMEL_BASE_PIOB;
+ case AT91_PIO_PORTC:
+ return (struct at91_port *)ATMEL_BASE_PIOC;
+#if (ATMEL_PIO_PORTS > 3)
+ case AT91_PIO_PORTD:
+ return (struct at91_port *)ATMEL_BASE_PIOD;
+#if (ATMEL_PIO_PORTS > 4)
+ case AT91_PIO_PORTE:
+ return (struct at91_port *)ATMEL_BASE_PIOE;
+#endif
+#endif
+ default:
+ return NULL;
+ }
+}
+
int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
- u32 mask;
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
- if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ if (at91_port && (pin < 32)) {
mask = 1 << pin;
if (use_pullup)
- writel(1 << pin, &pio->port[port].puer);
+ writel(1 << pin, &at91_port->puer);
else
- writel(1 << pin, &pio->port[port].pudr);
- writel(mask, &pio->port[port].per);
+ writel(1 << pin, &at91_port->pudr);
+ writel(mask, &at91_port->per);
}
+
return 0;
}
*/
int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
- u32 mask;
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
- if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ if (at91_port && (pin < 32)) {
mask = 1 << pin;
- writel(mask, &pio->port[port].idr);
+ writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
- writel(mask, &pio->port[port].per);
+ writel(mask, &at91_port->per);
}
+
return 0;
}
*/
int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
- u32 mask;
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
- if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ if (at91_port && (pin < 32)) {
mask = 1 << pin;
- writel(mask, &pio->port[port].idr);
+ writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
#if defined(CPU_HAS_PIO3)
- writel(readl(&pio->port[port].abcdsr1) & ~mask,
- &pio->port[port].abcdsr1);
- writel(readl(&pio->port[port].abcdsr2) & ~mask,
- &pio->port[port].abcdsr2);
+ writel(readl(&at91_port->abcdsr1) & ~mask,
+ &at91_port->abcdsr1);
+ writel(readl(&at91_port->abcdsr2) & ~mask,
+ &at91_port->abcdsr2);
#else
- writel(mask, &pio->port[port].asr);
+ writel(mask, &at91_port->asr);
#endif
- writel(mask, &pio->port[port].pdr);
+ writel(mask, &at91_port->pdr);
}
+
return 0;
}
*/
int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
- u32 mask;
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
- if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ if (at91_port && (pin < 32)) {
mask = 1 << pin;
- writel(mask, &pio->port[port].idr);
+ writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
#if defined(CPU_HAS_PIO3)
- writel(readl(&pio->port[port].abcdsr1) | mask,
- &pio->port[port].abcdsr1);
- writel(readl(&pio->port[port].abcdsr2) & ~mask,
- &pio->port[port].abcdsr2);
+ writel(readl(&at91_port->abcdsr1) | mask,
+ &at91_port->abcdsr1);
+ writel(readl(&at91_port->abcdsr2) & ~mask,
+ &at91_port->abcdsr2);
#else
- writel(mask, &pio->port[port].bsr);
+ writel(mask, &at91_port->bsr);
#endif
- writel(mask, &pio->port[port].pdr);
+ writel(mask, &at91_port->pdr);
}
+
return 0;
}
*/
int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
- u32 mask;
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
- if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ if (at91_port && (pin < 32)) {
mask = 1 << pin;
- writel(mask, &pio->port[port].idr);
+ writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
- writel(readl(&pio->port[port].abcdsr1) & ~mask,
- &pio->port[port].abcdsr1);
- writel(readl(&pio->port[port].abcdsr2) | mask,
- &pio->port[port].abcdsr2);
- writel(mask, &pio->port[port].pdr);
+ writel(readl(&at91_port->abcdsr1) & ~mask,
+ &at91_port->abcdsr1);
+ writel(readl(&at91_port->abcdsr2) | mask,
+ &at91_port->abcdsr2);
+ writel(mask, &at91_port->pdr);
}
+
return 0;
}
*/
int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup)
{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
- u32 mask;
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
- if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ if (at91_port && (pin < 32)) {
mask = 1 << pin;
- writel(mask, &pio->port[port].idr);
+ writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
- writel(readl(&pio->port[port].abcdsr1) | mask,
- &pio->port[port].abcdsr1);
- writel(readl(&pio->port[port].abcdsr2) | mask,
- &pio->port[port].abcdsr2);
- writel(mask, &pio->port[port].pdr);
+ writel(readl(&at91_port->abcdsr1) | mask,
+ &at91_port->abcdsr1);
+ writel(readl(&at91_port->abcdsr2) | mask,
+ &at91_port->abcdsr2);
+ writel(mask, &at91_port->pdr);
}
+
return 0;
}
#endif
*/
int at91_set_pio_input(unsigned port, u32 pin, int use_pullup)
{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
- u32 mask;
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
- if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ if (at91_port && (pin < 32)) {
mask = 1 << pin;
- writel(mask, &pio->port[port].idr);
+ writel(mask, &at91_port->idr);
at91_set_pio_pullup(port, pin, use_pullup);
- writel(mask, &pio->port[port].odr);
- writel(mask, &pio->port[port].per);
+ writel(mask, &at91_port->odr);
+ writel(mask, &at91_port->per);
}
+
return 0;
}
*/
int at91_set_pio_output(unsigned port, u32 pin, int value)
{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
- u32 mask;
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
mask = 1 << pin;
- writel(mask, &pio->port[port].idr);
- writel(mask, &pio->port[port].pudr);
+ writel(mask, &at91_port->idr);
+ writel(mask, &at91_port->pudr);
if (value)
- writel(mask, &pio->port[port].sodr);
+ writel(mask, &at91_port->sodr);
else
- writel(mask, &pio->port[port].codr);
- writel(mask, &pio->port[port].oer);
- writel(mask, &pio->port[port].per);
+ writel(mask, &at91_port->codr);
+ writel(mask, &at91_port->oer);
+ writel(mask, &at91_port->per);
}
+
return 0;
}
*/
int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
- u32 mask;
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
- if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ if (at91_port && (pin < 32)) {
mask = 1 << pin;
if (is_on) {
#if defined(CPU_HAS_PIO3)
- writel(mask, &pio->port[port].ifscdr);
+ writel(mask, &at91_port->ifscdr);
#endif
- writel(mask, &pio->port[port].ifer);
+ writel(mask, &at91_port->ifer);
} else {
- writel(mask, &pio->port[port].ifdr);
+ writel(mask, &at91_port->ifdr);
}
}
+
return 0;
}
*/
int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
- u32 mask;
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
- if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ if (at91_port && (pin < 32)) {
mask = 1 << pin;
if (is_on) {
- writel(mask, &pio->port[port].ifscer);
- writel(div & PIO_SCDR_DIV, &pio->port[port].scdr);
- writel(mask, &pio->port[port].ifer);
+ writel(mask, &at91_port->ifscer);
+ writel(div & PIO_SCDR_DIV, &at91_port->scdr);
+ writel(mask, &at91_port->ifer);
} else {
- writel(mask, &pio->port[port].ifdr);
+ writel(mask, &at91_port->ifdr);
}
}
+
return 0;
}
*/
int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
- u32 mask;
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
- if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ if (at91_port && (pin < 32)) {
mask = 1 << pin;
- writel(mask, &pio->port[port].pudr);
+ writel(mask, &at91_port->pudr);
if (is_on)
- writel(mask, &pio->port[port].ppder);
+ writel(mask, &at91_port->ppder);
else
- writel(mask, &pio->port[port].ppddr);
+ writel(mask, &at91_port->ppddr);
}
+
return 0;
}
*/
int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
- u32 mask;
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
- if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ if (at91_port && (pin < 32)) {
mask = 1 << pin;
- writel(readl(&pio->port[port].schmitt) | mask,
- &pio->port[port].schmitt);
+ writel(readl(&at91_port->schmitt) | mask,
+ &at91_port->schmitt);
}
+
return 0;
}
#endif
*/
int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on)
{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
- u32 mask;
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
- if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ if (at91_port && (pin < 32)) {
mask = 1 << pin;
if (is_on)
- writel(mask, &pio->port[port].mder);
+ writel(mask, &at91_port->mder);
else
- writel(mask, &pio->port[port].mddr);
+ writel(mask, &at91_port->mddr);
}
+
return 0;
}
*/
int at91_set_pio_value(unsigned port, unsigned pin, int value)
{
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
- u32 mask;
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 mask;
- if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ if (at91_port && (pin < 32)) {
mask = 1 << pin;
if (value)
- writel(mask, &pio->port[port].sodr);
+ writel(mask, &at91_port->sodr);
else
- writel(mask, &pio->port[port].codr);
+ writel(mask, &at91_port->codr);
}
+
return 0;
}
*/
int at91_get_pio_value(unsigned port, unsigned pin)
{
- u32 pdsr = 0;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
- u32 mask;
+ struct at91_port *at91_port = at91_pio_get_port(port);
+ u32 pdsr = 0, mask;
- if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
+ if (at91_port && (pin < 32)) {
mask = 1 << pin;
- pdsr = readl(&pio->port[port].pdsr) & mask;
+ pdsr = readl(&at91_port->pdsr) & mask;
}
+
return pdsr != 0;
}
+
+/* Common GPIO API */
+
+#define at91_gpio_to_port(gpio) (gpio / 32)
+#define at91_gpio_to_pin(gpio) (gpio % 32)
+
+int gpio_request(unsigned gpio, const char *label)
+{
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ at91_set_pio_input(at91_gpio_to_port(gpio),
+ at91_gpio_to_pin(gpio), 0);
+ return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ at91_set_pio_output(at91_gpio_to_port(gpio),
+ at91_gpio_to_pin(gpio), value);
+ return 0;
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ return at91_get_pio_value(at91_gpio_to_port(gpio),
+ at91_gpio_to_pin(gpio));
+}
+
+int gpio_set_value(unsigned gpio, int value)
+{
+ at91_set_pio_value(at91_gpio_to_port(gpio),
+ at91_gpio_to_pin(gpio), value);
+
+ return 0;
+}
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
- MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ MMC_MODE_HS_52MHz | MMC_MODE_HS |
+ MMC_MODE_HC;
/*
* SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
+#include <malloc.h>
#include <nand.h>
#include <watchdog.h>
void __iomem *pmecc_index_of;
/* data for pmecc computation */
- int16_t pmecc_smu[(CONFIG_PMECC_CAP + 2) * (2 * CONFIG_PMECC_CAP + 1)];
- int16_t pmecc_partial_syn[2 * CONFIG_PMECC_CAP + 1];
- int16_t pmecc_si[2 * CONFIG_PMECC_CAP + 1];
- int16_t pmecc_lmu[CONFIG_PMECC_CAP + 1]; /* polynomal order */
- int pmecc_mu[CONFIG_PMECC_CAP + 1];
- int pmecc_dmu[CONFIG_PMECC_CAP + 1];
- int pmecc_delta[CONFIG_PMECC_CAP + 1];
+ int16_t *pmecc_smu;
+ int16_t *pmecc_partial_syn;
+ int16_t *pmecc_si;
+ int16_t *pmecc_lmu; /* polynomal order */
+ int *pmecc_mu;
+ int *pmecc_dmu;
+ int *pmecc_delta;
};
static struct atmel_nand_host pmecc_host;
table_size * sizeof(int16_t);
}
+static void pmecc_data_free(struct atmel_nand_host *host)
+{
+ free(host->pmecc_partial_syn);
+ free(host->pmecc_si);
+ free(host->pmecc_lmu);
+ free(host->pmecc_smu);
+ free(host->pmecc_mu);
+ free(host->pmecc_dmu);
+ free(host->pmecc_delta);
+}
+
+static int pmecc_data_alloc(struct atmel_nand_host *host)
+{
+ const int cap = host->pmecc_corr_cap;
+ int size;
+
+ size = (2 * cap + 1) * sizeof(int16_t);
+ host->pmecc_partial_syn = malloc(size);
+ host->pmecc_si = malloc(size);
+ host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
+ host->pmecc_smu = malloc((cap + 2) * size);
+
+ size = (cap + 1) * sizeof(int);
+ host->pmecc_mu = malloc(size);
+ host->pmecc_dmu = malloc(size);
+ host->pmecc_delta = malloc(size);
+
+ if (host->pmecc_partial_syn &&
+ host->pmecc_si &&
+ host->pmecc_lmu &&
+ host->pmecc_smu &&
+ host->pmecc_mu &&
+ host->pmecc_dmu &&
+ host->pmecc_delta)
+ return 0;
+
+ /* error happened */
+ pmecc_data_free(host);
+ return -ENOMEM;
+
+}
+
static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
{
struct nand_chip *nand_chip = mtd->priv;
pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
}
+#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
+/*
+ * get_onfi_ecc_param - Get ECC requirement from ONFI parameters
+ * @ecc_bits: store the ONFI ECC correct bits capbility
+ * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
+ *
+ * Returns -1 if ONFI parameters is not supported. In this case @ecc_bits,
+ * @sector_size are initialize to 0.
+ * Return 0 if success to get the ECC requirement.
+ */
+static int get_onfi_ecc_param(struct nand_chip *chip,
+ int *ecc_bits, int *sector_size)
+{
+ *ecc_bits = *sector_size = 0;
+
+ if (chip->onfi_params.ecc_bits == 0xff)
+ /* TODO: the sector_size and ecc_bits need to be find in
+ * extended ecc parameter, currently we don't support it.
+ */
+ return -1;
+
+ *ecc_bits = chip->onfi_params.ecc_bits;
+
+ /* The default sector size (ecc codeword size) is 512 */
+ *sector_size = 512;
+
+ return 0;
+}
+
+/*
+ * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
+ * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
+ * ONFI ECC parameters.
+ * @host: point to an atmel_nand_host structure.
+ * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
+ * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
+ * @chip: point to an nand_chip structure.
+ * @cap: store the ONFI ECC correct bits capbility
+ * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
+ *
+ * Return 0 if success. otherwise return the error code.
+ */
+static int pmecc_choose_ecc(struct atmel_nand_host *host,
+ struct nand_chip *chip,
+ int *cap, int *sector_size)
+{
+ /* Get ECC requirement from ONFI parameters */
+ *cap = *sector_size = 0;
+ if (chip->onfi_version) {
+ if (!get_onfi_ecc_param(chip, cap, sector_size)) {
+ MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
+ *cap, *sector_size);
+ } else {
+ dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
+ }
+ } else {
+ dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
+ }
+ if (*cap == 0 && *sector_size == 0) {
+ /* Non-ONFI compliant or use extended ONFI parameters */
+ *cap = 2;
+ *sector_size = 512;
+ }
+
+ /* If head file doesn't specify then use the one in ONFI parameters */
+ if (host->pmecc_corr_cap == 0) {
+ /* use the most fitable ecc bits (the near bigger one ) */
+ if (*cap <= 2)
+ host->pmecc_corr_cap = 2;
+ else if (*cap <= 4)
+ host->pmecc_corr_cap = 4;
+ else if (*cap <= 8)
+ host->pmecc_corr_cap = 8;
+ else if (*cap <= 12)
+ host->pmecc_corr_cap = 12;
+ else if (*cap <= 24)
+ host->pmecc_corr_cap = 24;
+ else
+ return -EINVAL;
+ }
+ if (host->pmecc_sector_size == 0) {
+ /* use the most fitable sector size (the near smaller one ) */
+ if (*sector_size >= 1024)
+ host->pmecc_sector_size = 1024;
+ else if (*sector_size >= 512)
+ host->pmecc_sector_size = 512;
+ else
+ return -EINVAL;
+ }
+ return 0;
+}
+#endif
+
static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
struct mtd_info *mtd)
{
nand->ecc.correct = NULL;
nand->ecc.hwctl = NULL;
- cap = host->pmecc_corr_cap = CONFIG_PMECC_CAP;
- sector_size = host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
- host->pmecc_index_table_offset = CONFIG_PMECC_INDEX_TABLE_OFFSET;
+#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
+ host->pmecc_corr_cap = host->pmecc_sector_size = 0;
+
+#ifdef CONFIG_PMECC_CAP
+ host->pmecc_corr_cap = CONFIG_PMECC_CAP;
+#endif
+#ifdef CONFIG_PMECC_SECTOR_SIZE
+ host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
+#endif
+ /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
+ * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
+ * from ONFI.
+ */
+ if (pmecc_choose_ecc(host, nand, &cap, §or_size)) {
+ dev_err(host->dev, "The NAND flash's ECC requirement(ecc_bits: %d, sector_size: %d) are not support!",
+ cap, sector_size);
+ return -EINVAL;
+ }
+
+ if (cap > host->pmecc_corr_cap)
+ dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
+ host->pmecc_corr_cap, cap);
+ if (sector_size < host->pmecc_sector_size)
+ dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
+ host->pmecc_sector_size, sector_size);
+#else /* CONFIG_SYS_NAND_ONFI_DETECTION */
+ host->pmecc_corr_cap = CONFIG_PMECC_CAP;
+ host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
+#endif
+
+ cap = host->pmecc_corr_cap;
+ sector_size = host->pmecc_sector_size;
+
+ /* TODO: need check whether cap & sector_size is validate */
+
+ if (host->pmecc_sector_size == 512)
+ host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
+ else
+ host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
MTDDEBUG(MTD_DEBUG_LEVEL1,
"Initialize PMECC params, cap: %d, sector: %d\n",
switch (mtd->writesize) {
case 2048:
case 4096:
- host->pmecc_degree = PMECC_GF_DIMENSION_13;
+ host->pmecc_degree = (sector_size == 512) ?
+ PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
host->pmecc_sector_number = mtd->writesize / sector_size;
host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
return 0;
}
+ /* Allocate data for PMECC computation */
+ if (pmecc_data_alloc(host)) {
+ dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
+ return -ENOMEM;
+ }
+
nand->ecc.read_page = atmel_nand_pmecc_read_page;
nand->ecc.write_page = atmel_nand_pmecc_write_page;
nand->ecc.strength = cap;
if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
memcpy(edev->enetaddr, ethaddr, 6);
+ if (!getenv("ethaddr"))
+ eth_setenv_enetaddr("ethaddr", ethaddr);
}
return ret;
err3:
#include <asm/io.h>
#include <asm/dma-mapping.h>
#include <asm/arch/clk.h>
+#include <asm-generic/errno.h>
#include "macb.h"
}
#ifdef CONFIG_PHYLIB
- phydev->bus = macb->bus;
- phydev->dev = netdev;
- phydev->addr = macb->phy_addr;
+ /* need to consider other phy interface mode */
+ phydev = phy_connect(macb->bus, macb->phy_addr, netdev,
+ PHY_INTERFACE_MODE_RGMII);
+ if (!phydev) {
+ printf("phy_connect failed\n");
+ return -ENODEV;
+ }
+
phy_config(phydev);
#endif
DECLARE_GLOBAL_DATA_PTR;
+static const char max77686_buck_addr[] = {
+ 0xff, 0x10, 0x12, 0x1c, 0x26, 0x30, 0x32, 0x34, 0x36, 0x38
+};
+
+static unsigned int max77686_ldo_volt2hex(int ldo, ulong uV)
+{
+ unsigned int hex = 0;
+
+ switch (ldo) {
+ case 1:
+ case 2:
+ case 6:
+ case 7:
+ case 8:
+ case 15:
+ hex = (uV - 800000) / 25000;
+ break;
+ default:
+ hex = (uV - 800000) / 50000;
+ }
+
+ if (hex >= 0 && hex <= MAX77686_LDO_VOLT_MAX_HEX)
+ return hex;
+
+ debug("%s: %ld is wrong voltage value for LDO%d\n", __func__, uV, ldo);
+ return 0;
+}
+
+int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
+{
+ unsigned int val, ret, hex, adr;
+
+ if (ldo < 1 && ldo > 26) {
+ printf("%s: %d is wrong ldo number\n", __func__, ldo);
+ return -1;
+ }
+
+ adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1;
+ hex = max77686_ldo_volt2hex(ldo, uV);
+
+ if (!hex)
+ return -1;
+
+ ret = pmic_reg_read(p, adr, &val);
+ if (ret)
+ return ret;
+
+ val &= ~MAX77686_LDO_VOLT_MASK;
+ val |= hex;
+ ret |= pmic_reg_write(p, adr, val);
+
+ return ret;
+}
+
+int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode)
+{
+ unsigned int val, ret, adr, mode;
+
+ if (ldo < 1 && 26 < ldo) {
+ printf("%s: %d is wrong ldo number\n", __func__, ldo);
+ return -1;
+ }
+
+ adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1;
+
+ /* mode */
+ switch (opmode) {
+ case OPMODE_OFF:
+ mode = MAX77686_LDO_MODE_OFF;
+ break;
+ case OPMODE_STANDBY:
+ switch (ldo) {
+ case 2:
+ case 6:
+ case 7:
+ case 8:
+ case 10:
+ case 11:
+ case 12:
+ case 14:
+ case 15:
+ case 16:
+ mode = MAX77686_LDO_MODE_STANDBY;
+ break;
+ default:
+ mode = 0xff;
+ }
+ break;
+ case OPMODE_LPM:
+ mode = MAX77686_LDO_MODE_LPM;
+ break;
+ case OPMODE_ON:
+ mode = MAX77686_LDO_MODE_ON;
+ break;
+ default:
+ mode = 0xff;
+ }
+
+ if (mode == 0xff) {
+ printf("%s: %d is not supported on LDO%d\n",
+ __func__, opmode, ldo);
+ return -1;
+ }
+
+ ret = pmic_reg_read(p, adr, &val);
+ if (ret)
+ return ret;
+
+ val &= ~MAX77686_LDO_MODE_MASK;
+ val |= mode;
+ ret |= pmic_reg_write(p, adr, val);
+
+ return ret;
+}
+
+int max77686_set_buck_mode(struct pmic *p, int buck, char opmode)
+{
+ unsigned int val, ret, mask, adr, size, mode, mode_shift;
+
+ size = ARRAY_SIZE(max77686_buck_addr);
+ if (buck >= size) {
+ printf("%s: %d is wrong buck number\n", __func__, buck);
+ return -1;
+ }
+
+ adr = max77686_buck_addr[buck];
+
+ /* mask */
+ switch (buck) {
+ case 2:
+ case 3:
+ case 4:
+ mode_shift = MAX77686_BUCK_MODE_SHIFT_2;
+ break;
+ default:
+ mode_shift = MAX77686_BUCK_MODE_SHIFT_1;
+ }
+
+ mask = MAX77686_BUCK_MODE_MASK << mode_shift;
+
+ /* mode */
+ switch (opmode) {
+ case OPMODE_OFF:
+ mode = MAX77686_BUCK_MODE_OFF;
+ break;
+ case OPMODE_STANDBY:
+ switch (buck) {
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ mode = MAX77686_BUCK_MODE_STANDBY << mode_shift;
+ break;
+ default:
+ mode = 0xff;
+ }
+ break;
+ case OPMODE_LPM:
+ switch (buck) {
+ case 2:
+ case 3:
+ case 4:
+ mode = MAX77686_BUCK_MODE_LPM << mode_shift;
+ break;
+ default:
+ mode = 0xff;
+ }
+ break;
+ case OPMODE_ON:
+ mode = MAX77686_BUCK_MODE_ON << mode_shift;
+ break;
+ default:
+ mode = 0xff;
+ }
+
+ if (mode == 0xff) {
+ printf("%s: %d is not supported on BUCK%d\n",
+ __func__, opmode, buck);
+ return -1;
+ }
+
+ ret = pmic_reg_read(p, adr, &val);
+ if (ret)
+ return ret;
+
+ val &= ~mask;
+ val |= mode;
+ ret |= pmic_reg_write(p, adr, val);
+
+ return ret;
+}
+
int pmic_init(unsigned char bus)
{
static const char name[] = "MAX77686_PMIC";
COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
COBJS-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
COBJS-$(CONFIG_FSL_LPUART) += serial_lpuart.o
+COBJS-$(CONFIG_MXS_AUART) += mxs_auart.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
--- /dev/null
+/*
+ * Freescale i.MX23/i.MX28 AUART driver
+ *
+ * Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com>
+ *
+ * Based on the MXC serial driver:
+ *
+ * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * Further based on the Linux mxs-auart.c driver:
+ *
+ * Freescale STMP37XX/STMP38X Application UART drkiver
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <serial.h>
+#include <linux/compiler.h>
+#include <asm/arch/regs-base.h>
+#include <asm/arch/regs-uartapp.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_MXS_AUART_BASE
+#error "CONFIG_MXS_AUART_BASE must be set to the base UART to use"
+#endif
+
+/* AUART clock always supplied by XTAL and always 24MHz */
+#define MXS_AUART_CLK 24000000
+
+static struct mxs_uartapp_regs *get_uartapp_registers(void)
+{
+ return (struct mxs_uartapp_regs *)CONFIG_MXS_AUART_BASE;
+}
+
+/**
+ * Sets the baud rate and settings.
+ * The settings are: 8 data bits, no parit and 1 stop bit.
+ */
+void mxs_auart_setbrg(void)
+{
+ u32 div;
+ u32 linectrl = 0;
+ struct mxs_uartapp_regs *regs = get_uartapp_registers();
+
+ if (!gd->baudrate)
+ gd->baudrate = CONFIG_BAUDRATE;
+
+ /*
+ * From i.MX28 datasheet:
+ * div is calculated by calculating UARTCLK*32/baudrate, rounded to int
+ * div must be between 0xEC and 0x003FFFC0 inclusive
+ * Lowest 6 bits of div goes in BAUD_DIVFRAC part of LINECTRL register
+ * Next 16 bits goes in BAUD_DIVINT part of LINECTRL register
+ */
+ div = (MXS_AUART_CLK * 32) / gd->baudrate;
+ if (div < 0xEC || div > 0x003FFFC0)
+ return;
+
+ linectrl |= ((div & UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK) <<
+ UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET) &
+ UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK;
+ linectrl |= ((div >> UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET) <<
+ UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET) &
+ UARTAPP_LINECTRL_BAUD_DIVINT_MASK;
+
+ /* Word length: 8 bits */
+ linectrl |= UARTAPP_LINECTRL_WLEN_8BITS;
+
+ /* Enable FIFOs. */
+ linectrl |= UARTAPP_LINECTRL_FEN_MASK;
+
+ /* Write above settings, no parity, 1 stop bit */
+ writel(linectrl, ®s->hw_uartapp_linectrl);
+}
+
+int mxs_auart_init(void)
+{
+ struct mxs_uartapp_regs *regs = get_uartapp_registers();
+ /* Reset everything */
+ mxs_reset_block(®s->hw_uartapp_ctrl0_reg);
+ /* Disable interrupts */
+ writel(0, ®s->hw_uartapp_intr);
+ /* Set baud rate and settings */
+ serial_setbrg();
+ /* Disable RTS and CTS, ignore LINECTRL2 register */
+ writel(UARTAPP_CTRL2_RTSEN_MASK |
+ UARTAPP_CTRL2_CTSEN_MASK |
+ UARTAPP_CTRL2_USE_LCR2_MASK,
+ ®s->hw_uartapp_ctrl2_clr);
+ /* Enable receiver, transmitter and UART */
+ writel(UARTAPP_CTRL2_RXE_MASK |
+ UARTAPP_CTRL2_TXE_MASK |
+ UARTAPP_CTRL2_UARTEN_MASK,
+ ®s->hw_uartapp_ctrl2_set);
+ return 0;
+}
+
+void mxs_auart_putc(const char c)
+{
+ struct mxs_uartapp_regs *regs = get_uartapp_registers();
+ /* Wait in loop while the transmit FIFO is full */
+ while (readl(®s->hw_uartapp_stat) & UARTAPP_STAT_TXFF_MASK)
+ ;
+
+ writel(c, ®s->hw_uartapp_data);
+
+ if (c == '\n')
+ mxs_auart_putc('\r');
+}
+
+int mxs_auart_tstc(void)
+{
+ struct mxs_uartapp_regs *regs = get_uartapp_registers();
+ /* Checks if receive FIFO is empty */
+ return !(readl(®s->hw_uartapp_stat) & UARTAPP_STAT_RXFE_MASK);
+}
+
+int mxs_auart_getc(void)
+{
+ struct mxs_uartapp_regs *regs = get_uartapp_registers();
+ /* Wait until a character is available to read */
+ while (!mxs_auart_tstc())
+ ;
+ /* Read the character from the data register */
+ return readl(®s->hw_uartapp_data) & 0xFF;
+}
+
+static struct serial_device mxs_auart_drv = {
+ .name = "mxs_auart_serial",
+ .start = mxs_auart_init,
+ .stop = NULL,
+ .setbrg = mxs_auart_setbrg,
+ .putc = mxs_auart_putc,
+ .puts = default_serial_puts,
+ .getc = mxs_auart_getc,
+ .tstc = mxs_auart_tstc,
+};
+
+void mxs_auart_initialize(void)
+{
+ serial_register(&mxs_auart_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &mxs_auart_drv;
+}
serial_initfunc(sa1100_serial_initialize);
serial_initfunc(sh_serial_initialize);
serial_initfunc(arm_dcc_initialize);
+serial_initfunc(mxs_auart_initialize);
/**
* serial_register() - Register serial driver with serial driver core
sa1100_serial_initialize();
sh_serial_initialize();
arm_dcc_initialize();
+ mxs_auart_initialize();
serial_assign(default_serial_console()->name);
}
#define STRING_MANUFACTURER 25
#define STRING_PRODUCT 2
+/* Index of String Descriptor describing this configuration */
#define STRING_USBDOWN 2
-#define CONFIG_USBDOWNLOADER 2
+/* Number of supported configurations */
+#define CONFIGURATION_NUMBER 1
#define DRIVER_VERSION "usb_dnl 2.0"
.bNumConfigurations = 1,
};
-/* static strings, in UTF-8 */
+/*
+ * static strings, in UTF-8
+ * IDs for those strings are assigned dynamically at g_dnl_bind()
+ */
static struct usb_string g_dnl_string_defs[] = {
- { 0, manufacturer, },
- { 1, product, },
- { } /* end of list */
+ {.s = manufacturer},
+ {.s = product},
+ { } /* end of list */
};
static struct usb_gadget_strings g_dnl_string_tab = {
static struct usb_configuration config = {
.label = "usb_dnload",
.bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,
- .bConfigurationValue = CONFIG_USBDOWNLOADER,
+ .bConfigurationValue = CONFIGURATION_NUMBER,
.iConfiguration = STRING_USBDOWN,
.bind = g_dnl_do_config,
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
-#ifdef CONFIG_MX53
- struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR;
- u32 reg;
-
- reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26);
- /* derive USB PHY clock multiplexer from PLL3 */
- reg |= 1 << 26;
- __raw_writel(reg, &sc_regs->cscmr1);
-#endif
set_usboh3_clk();
- enable_usboh3_clk(1);
+ enable_usboh3_clk(true);
set_usb_phy_clk();
- enable_usb_phy1_clk(1);
- enable_usb_phy2_clk(1);
+ enable_usb_phy1_clk(true);
+ enable_usb_phy2_clk(true);
mdelay(1);
/* Do board specific initialization */
writel(reg, &usbtll->channel_conf + port);
}
+#ifdef CONFIG_USB_ULPI
static void omap_ehci_soft_phy_reset(int port)
{
struct ulpi_viewport ulpi_vp;
ulpi_reset(&ulpi_vp);
}
+#else
+static void omap_ehci_soft_phy_reset(int port)
+{
+ return;
+}
+#endif
inline int __board_usb_init(void)
{
int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
- defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO)
+ defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
+ defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
/* controls PHY(s) reset signal(s) */
static inline void omap_ehci_phy_reset(int on, int delay)
{
gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
#endif
+#ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
+ gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
+ gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
+#endif
/* Hold the PHY in RESET for enough time till DIR is high */
/* Refer: ISSUE1 */
else
setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
} else if (rev == OMAP_USBHS_REV2) {
+
clrsetbits_le32(®, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
- /* Clear port mode fields for PHY mode*/
+ /* Clear port mode fields for PHY mode */
+
+ if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
+ setbits_le32(®, OMAP_P1_MODE_HSIC);
+
+ if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
+ setbits_le32(®, OMAP_P2_MODE_HSIC);
+
+ } else if (rev == OMAP_USBHS_REV2_1) {
+
+ clrsetbits_le32(®,
+ (OMAP_P1_MODE_CLEAR |
+ OMAP_P2_MODE_CLEAR |
+ OMAP_P3_MODE_CLEAR),
+ OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
+
+ /* Clear port mode fields for PHY mode */
if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
setbits_le32(®, OMAP_P1_MODE_HSIC);
#define cpu_relax() do {} while (0)
#define pr_debug(fmt, args...) debug(fmt, ##args)
-#define dev_dbg(dev, fmt, args...) \
- debug(fmt, ##args)
-#define dev_vdbg(dev, fmt, args...) \
- debug(fmt, ##args)
-#define dev_info(dev, fmt, args...) \
- printf(fmt, ##args)
-#define dev_err(dev, fmt, args...) \
- printf(fmt, ##args)
-#define printk printf
#define WARN(condition, fmt, args...) ({ \
int ret_warn = !!condition; \
printf(fmt, ##args); \
ret_warn; })
-#define KERN_DEBUG
-#define KERN_NOTICE
-#define KERN_WARNING
-#define KERN_ERR
-
-#define kfree(ptr) free(ptr)
-
#define pm_runtime_get_sync(dev) do {} while (0)
#define pm_runtime_put(dev) do {} while (0)
#define pm_runtime_put_sync(dev) do {} while (0)
COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
COBJS-$(CONFIG_VIDEO_TEGRA) += tegra.o
COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
+COBJS-$(CONFIG_FORMIKE) += formike.o
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * LCD: Formike, TFT 4.3", 480x800, RGB24, KWH043ST20-F01, DriverIC NT35510-16
+ * LCD initialization via SPI
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * Based on:
+ *
+ */
+#include <common.h>
+#include <errno.h>
+#include <spi.h>
+
+#define TAG_READ 0x80
+#define TAG_WRITE 0x00
+
+#define TAG_DATA 0x40
+#define TAG_COMMAND 0x00
+
+#define TAG_ADDR_H 0x20
+#define TAG_ADDR_L 0x00
+
+static int spi_write_tag_val(struct spi_slave *spi, unsigned char tag,
+ unsigned char val)
+{
+ unsigned long flags = SPI_XFER_BEGIN;
+ u8 buf[2];
+ int ret;
+
+ buf[0] = tag;
+ buf[1] = val;
+ flags |= SPI_XFER_END;
+
+ ret = spi_xfer(spi, 16, buf, NULL, flags);
+#ifdef KWH043ST20_F01_SPI_DEBUG
+ printf("spi_write_tag_val: tag=%02X, val=%02X ret: %d\n",
+ tag, val, ret);
+#endif /* KWH043ST20_F01_SPI_DEBUG */
+ if (ret)
+ debug("%s: Failed to send: %d\n", __func__, ret);
+
+ return ret;
+}
+
+static void spi_write_dat(struct spi_slave *spi, unsigned int val)
+{
+ spi_write_tag_val(spi, TAG_WRITE|TAG_DATA, val);
+}
+
+static void spi_write_com(struct spi_slave *spi, unsigned int addr)
+{
+ spi_write_tag_val(spi, TAG_WRITE|TAG_COMMAND|TAG_ADDR_H,
+ (addr & 0xff00) >> 8);
+ spi_write_tag_val(spi, TAG_WRITE|TAG_COMMAND|TAG_ADDR_L,
+ (addr & 0x00ff) >> 0);
+}
+
+int kwh043st20_f01_spi_startup(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
+{
+ struct spi_slave *spi;
+ int ret;
+
+ spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
+ if (!spi) {
+ debug("%s: Failed to set up slave\n", __func__);
+ return -1;
+ }
+
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ debug("%s: Failed to claim SPI bus: %d\n", __func__, ret);
+ goto err_claim_bus;
+ }
+
+
+ /* LV2 Page 1 enable */
+ spi_write_com(spi, 0xF000); spi_write_dat(spi, 0x55);
+ spi_write_com(spi, 0xF001); spi_write_dat(spi, 0xAA);
+ spi_write_com(spi, 0xF002); spi_write_dat(spi, 0x52);
+ spi_write_com(spi, 0xF003); spi_write_dat(spi, 0x08);
+ spi_write_com(spi, 0xF004); spi_write_dat(spi, 0x01);
+
+ /* AVDD Set AVDD 5.2V */
+ spi_write_com(spi, 0xB000); spi_write_dat(spi, 0x0D);
+ spi_write_com(spi, 0xB001); spi_write_dat(spi, 0x0D);
+ spi_write_com(spi, 0xB002); spi_write_dat(spi, 0x0D);
+
+ /* AVDD ratio */
+ spi_write_com(spi, 0xB600); spi_write_dat(spi, 0x34);
+ spi_write_com(spi, 0xB601); spi_write_dat(spi, 0x34);
+ spi_write_com(spi, 0xB602); spi_write_dat(spi, 0x34);
+
+ /* AVEE -5.2V */
+ spi_write_com(spi, 0xB100); spi_write_dat(spi, 0x0D);
+ spi_write_com(spi, 0xB101); spi_write_dat(spi, 0x0D);
+ spi_write_com(spi, 0xB102); spi_write_dat(spi, 0x0D);
+
+ /* AVEE ratio */
+ spi_write_com(spi, 0xB700); spi_write_dat(spi, 0x35);
+ spi_write_com(spi, 0xB701); spi_write_dat(spi, 0x35);
+ spi_write_com(spi, 0xB702); spi_write_dat(spi, 0x35);
+
+ /* VCL -2.5V */
+ spi_write_com(spi, 0xB200); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xB201); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xB202); spi_write_dat(spi, 0x00);
+
+ /* VCL ratio */
+ spi_write_com(spi, 0xB800); spi_write_dat(spi, 0x24);
+ spi_write_com(spi, 0xB801); spi_write_dat(spi, 0x24);
+ spi_write_com(spi, 0xB802); spi_write_dat(spi, 0x24);
+
+ /* VGH 15V */
+ spi_write_com(spi, 0xBF00); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xB300); spi_write_dat(spi, 0x08);
+ spi_write_com(spi, 0xB301); spi_write_dat(spi, 0x08);
+ spi_write_com(spi, 0xB302); spi_write_dat(spi, 0x08);
+
+ /* VGH ratio */
+ spi_write_com(spi, 0xB900); spi_write_dat(spi, 0x34);
+ spi_write_com(spi, 0xB901); spi_write_dat(spi, 0x34);
+ spi_write_com(spi, 0xB902); spi_write_dat(spi, 0x34);
+
+ /* VGLX ratio */
+ spi_write_com(spi, 0xBA00); spi_write_dat(spi, 0x24);
+ spi_write_com(spi, 0xBA01); spi_write_dat(spi, 0x24);
+ spi_write_com(spi, 0xBA02); spi_write_dat(spi, 0x24);
+
+ /* VGMP/VGSP 4.7V/0V */
+ spi_write_com(spi, 0xBC00); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xBC01); spi_write_dat(spi, 0x88);
+ spi_write_com(spi, 0xBC02); spi_write_dat(spi, 0x00);
+
+ /* VGMN/VGSN -4.7V/0V */
+ spi_write_com(spi, 0xBD00); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xBD01); spi_write_dat(spi, 0x88);
+ spi_write_com(spi, 0xBD02); spi_write_dat(spi, 0x00);
+
+ /* VCOM 1.525V */
+ spi_write_com(spi, 0xBE00); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xBE01); spi_write_dat(spi, 0x7A);
+
+ /* Gamma Setting */
+ spi_write_com(spi, 0xD100); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD101); spi_write_dat(spi, 0x05);
+ spi_write_com(spi, 0xD102); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD103); spi_write_dat(spi, 0x15);
+ spi_write_com(spi, 0xD104); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD105); spi_write_dat(spi, 0x30);
+ spi_write_com(spi, 0xD106); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD107); spi_write_dat(spi, 0x47);
+ spi_write_com(spi, 0xD108); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD109); spi_write_dat(spi, 0x5B);
+ spi_write_com(spi, 0xD10A); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD10B); spi_write_dat(spi, 0x7D);
+ spi_write_com(spi, 0xD10C); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD10D); spi_write_dat(spi, 0x9D);
+ spi_write_com(spi, 0xD10E); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD10F); spi_write_dat(spi, 0xCC);
+ spi_write_com(spi, 0xD110); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD111); spi_write_dat(spi, 0xF3);
+ spi_write_com(spi, 0xD112); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD113); spi_write_dat(spi, 0x32);
+ spi_write_com(spi, 0xD114); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD115); spi_write_dat(spi, 0x63);
+ spi_write_com(spi, 0xD116); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD117); spi_write_dat(spi, 0xB1);
+ spi_write_com(spi, 0xD118); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD119); spi_write_dat(spi, 0xF0);
+ spi_write_com(spi, 0xD11A); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD11B); spi_write_dat(spi, 0xF2);
+ spi_write_com(spi, 0xD11C); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD11D); spi_write_dat(spi, 0x2A);
+ spi_write_com(spi, 0xD11E); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD11F); spi_write_dat(spi, 0x67);
+ spi_write_com(spi, 0xD120); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD121); spi_write_dat(spi, 0x90);
+ spi_write_com(spi, 0xD122); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD123); spi_write_dat(spi, 0xCB);
+ spi_write_com(spi, 0xD124); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD125); spi_write_dat(spi, 0xF2);
+ spi_write_com(spi, 0xD126); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD127); spi_write_dat(spi, 0x2A);
+ spi_write_com(spi, 0xD128); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD129); spi_write_dat(spi, 0x51);
+ spi_write_com(spi, 0xD12A); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD12B); spi_write_dat(spi, 0x80);
+ spi_write_com(spi, 0xD12C); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD12D); spi_write_dat(spi, 0x9F);
+ spi_write_com(spi, 0xD12E); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD12F); spi_write_dat(spi, 0xBE);
+ spi_write_com(spi, 0xD130); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD131); spi_write_dat(spi, 0xF9);
+ spi_write_com(spi, 0xD132); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD133); spi_write_dat(spi, 0xFF);
+
+ spi_write_com(spi, 0xD200); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD201); spi_write_dat(spi, 0x05);
+ spi_write_com(spi, 0xD202); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD203); spi_write_dat(spi, 0x15);
+ spi_write_com(spi, 0xD204); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD205); spi_write_dat(spi, 0x30);
+ spi_write_com(spi, 0xD206); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD207); spi_write_dat(spi, 0x47);
+ spi_write_com(spi, 0xD208); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD209); spi_write_dat(spi, 0x5B);
+ spi_write_com(spi, 0xD20A); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD20B); spi_write_dat(spi, 0x7D);
+ spi_write_com(spi, 0xD20C); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD20D); spi_write_dat(spi, 0x9D);
+ spi_write_com(spi, 0xD20E); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD20F); spi_write_dat(spi, 0xCC);
+ spi_write_com(spi, 0xD210); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD211); spi_write_dat(spi, 0xF3);
+ spi_write_com(spi, 0xD212); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD213); spi_write_dat(spi, 0x32);
+ spi_write_com(spi, 0xD214); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD215); spi_write_dat(spi, 0x63);
+ spi_write_com(spi, 0xD216); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD217); spi_write_dat(spi, 0xB1);
+ spi_write_com(spi, 0xD218); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD219); spi_write_dat(spi, 0xF0);
+ spi_write_com(spi, 0xD21A); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD21B); spi_write_dat(spi, 0xF2);
+ spi_write_com(spi, 0xD21C); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD21D); spi_write_dat(spi, 0x2A);
+ spi_write_com(spi, 0xD21E); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD21F); spi_write_dat(spi, 0x67);
+ spi_write_com(spi, 0xD220); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD221); spi_write_dat(spi, 0x90);
+ spi_write_com(spi, 0xD222); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD223); spi_write_dat(spi, 0xCB);
+ spi_write_com(spi, 0xD224); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD225); spi_write_dat(spi, 0xF2);
+ spi_write_com(spi, 0xD226); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD227); spi_write_dat(spi, 0x2A);
+ spi_write_com(spi, 0xD228); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD229); spi_write_dat(spi, 0x51);
+ spi_write_com(spi, 0xD22A); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD22B); spi_write_dat(spi, 0x80);
+ spi_write_com(spi, 0xD22C); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD22D); spi_write_dat(spi, 0x9F);
+ spi_write_com(spi, 0xD22E); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD22F); spi_write_dat(spi, 0xBE);
+ spi_write_com(spi, 0xD230); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD231); spi_write_dat(spi, 0xF9);
+ spi_write_com(spi, 0xD232); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD233); spi_write_dat(spi, 0xFF);
+
+ spi_write_com(spi, 0xD300); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD301); spi_write_dat(spi, 0x05);
+ spi_write_com(spi, 0xD302); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD303); spi_write_dat(spi, 0x15);
+ spi_write_com(spi, 0xD304); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD305); spi_write_dat(spi, 0x30);
+ spi_write_com(spi, 0xD306); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD307); spi_write_dat(spi, 0x47);
+ spi_write_com(spi, 0xD308); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD309); spi_write_dat(spi, 0x5B);
+ spi_write_com(spi, 0xD30A); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD30B); spi_write_dat(spi, 0x7D);
+ spi_write_com(spi, 0xD30C); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD30D); spi_write_dat(spi, 0x9D);
+ spi_write_com(spi, 0xD30E); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD30F); spi_write_dat(spi, 0xCC);
+ spi_write_com(spi, 0xD310); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD311); spi_write_dat(spi, 0xF3);
+ spi_write_com(spi, 0xD312); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD313); spi_write_dat(spi, 0x32);
+ spi_write_com(spi, 0xD314); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD315); spi_write_dat(spi, 0x63);
+ spi_write_com(spi, 0xD316); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD317); spi_write_dat(spi, 0xB1);
+ spi_write_com(spi, 0xD318); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD319); spi_write_dat(spi, 0xF0);
+ spi_write_com(spi, 0xD31A); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD31B); spi_write_dat(spi, 0xF2);
+ spi_write_com(spi, 0xD31C); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD31D); spi_write_dat(spi, 0x2A);
+ spi_write_com(spi, 0xD31E); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD31F); spi_write_dat(spi, 0x67);
+ spi_write_com(spi, 0xD320); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD321); spi_write_dat(spi, 0x90);
+ spi_write_com(spi, 0xD322); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD323); spi_write_dat(spi, 0xCB);
+ spi_write_com(spi, 0xD324); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD325); spi_write_dat(spi, 0xF2);
+ spi_write_com(spi, 0xD326); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD327); spi_write_dat(spi, 0x2A);
+ spi_write_com(spi, 0xD328); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD329); spi_write_dat(spi, 0x51);
+ spi_write_com(spi, 0xD32A); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD32B); spi_write_dat(spi, 0x80);
+ spi_write_com(spi, 0xD32C); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD32D); spi_write_dat(spi, 0x9F);
+ spi_write_com(spi, 0xD32E); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD32F); spi_write_dat(spi, 0xBE);
+ spi_write_com(spi, 0xD330); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD331); spi_write_dat(spi, 0xF9);
+ spi_write_com(spi, 0xD332); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD333); spi_write_dat(spi, 0xFF);
+
+ spi_write_com(spi, 0xD400); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD401); spi_write_dat(spi, 0x05);
+ spi_write_com(spi, 0xD402); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD403); spi_write_dat(spi, 0x15);
+ spi_write_com(spi, 0xD404); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD405); spi_write_dat(spi, 0x30);
+ spi_write_com(spi, 0xD406); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD407); spi_write_dat(spi, 0x47);
+ spi_write_com(spi, 0xD408); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD409); spi_write_dat(spi, 0x5B);
+ spi_write_com(spi, 0xD40A); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD40B); spi_write_dat(spi, 0x7D);
+ spi_write_com(spi, 0xD40C); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD40D); spi_write_dat(spi, 0x9D);
+ spi_write_com(spi, 0xD40E); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD40F); spi_write_dat(spi, 0xCC);
+ spi_write_com(spi, 0xD410); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD411); spi_write_dat(spi, 0xF3);
+ spi_write_com(spi, 0xD412); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD413); spi_write_dat(spi, 0x32);
+ spi_write_com(spi, 0xD414); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD415); spi_write_dat(spi, 0x63);
+ spi_write_com(spi, 0xD416); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD417); spi_write_dat(spi, 0xB1);
+ spi_write_com(spi, 0xD418); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD419); spi_write_dat(spi, 0xF0);
+ spi_write_com(spi, 0xD41A); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD41B); spi_write_dat(spi, 0xF2);
+ spi_write_com(spi, 0xD41C); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD41D); spi_write_dat(spi, 0x2A);
+ spi_write_com(spi, 0xD41E); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD41F); spi_write_dat(spi, 0x67);
+ spi_write_com(spi, 0xD420); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD421); spi_write_dat(spi, 0x90);
+ spi_write_com(spi, 0xD422); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD423); spi_write_dat(spi, 0xCB);
+ spi_write_com(spi, 0xD424); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD425); spi_write_dat(spi, 0xF2);
+ spi_write_com(spi, 0xD426); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD427); spi_write_dat(spi, 0x2A);
+ spi_write_com(spi, 0xD428); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD429); spi_write_dat(spi, 0x51);
+ spi_write_com(spi, 0xD42A); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD42B); spi_write_dat(spi, 0x80);
+ spi_write_com(spi, 0xD42C); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD42D); spi_write_dat(spi, 0x9F);
+ spi_write_com(spi, 0xD42E); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD42F); spi_write_dat(spi, 0xBE);
+ spi_write_com(spi, 0xD430); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD431); spi_write_dat(spi, 0xF9);
+ spi_write_com(spi, 0xD432); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD433); spi_write_dat(spi, 0xFF);
+
+ spi_write_com(spi, 0xD500); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD501); spi_write_dat(spi, 0x05);
+ spi_write_com(spi, 0xD502); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD503); spi_write_dat(spi, 0x15);
+ spi_write_com(spi, 0xD504); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD505); spi_write_dat(spi, 0x30);
+ spi_write_com(spi, 0xD506); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD507); spi_write_dat(spi, 0x47);
+ spi_write_com(spi, 0xD508); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD509); spi_write_dat(spi, 0x5B);
+ spi_write_com(spi, 0xD50A); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD50B); spi_write_dat(spi, 0x7D);
+ spi_write_com(spi, 0xD50C); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD50D); spi_write_dat(spi, 0x9D);
+ spi_write_com(spi, 0xD50E); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD50F); spi_write_dat(spi, 0xCC);
+ spi_write_com(spi, 0xD510); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD511); spi_write_dat(spi, 0xF3);
+ spi_write_com(spi, 0xD512); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD513); spi_write_dat(spi, 0x32);
+ spi_write_com(spi, 0xD514); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD515); spi_write_dat(spi, 0x63);
+ spi_write_com(spi, 0xD516); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD517); spi_write_dat(spi, 0xB1);
+ spi_write_com(spi, 0xD518); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD519); spi_write_dat(spi, 0xF0);
+ spi_write_com(spi, 0xD51A); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD51B); spi_write_dat(spi, 0xF2);
+ spi_write_com(spi, 0xD51C); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD51D); spi_write_dat(spi, 0x2A);
+ spi_write_com(spi, 0xD51E); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD51F); spi_write_dat(spi, 0x67);
+ spi_write_com(spi, 0xD520); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD521); spi_write_dat(spi, 0x90);
+ spi_write_com(spi, 0xD522); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD523); spi_write_dat(spi, 0xCB);
+ spi_write_com(spi, 0xD524); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD525); spi_write_dat(spi, 0xF2);
+ spi_write_com(spi, 0xD526); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD527); spi_write_dat(spi, 0x2A);
+ spi_write_com(spi, 0xD528); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD529); spi_write_dat(spi, 0x51);
+ spi_write_com(spi, 0xD52A); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD52B); spi_write_dat(spi, 0x80);
+ spi_write_com(spi, 0xD52C); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD52D); spi_write_dat(spi, 0x9F);
+ spi_write_com(spi, 0xD52E); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD52F); spi_write_dat(spi, 0xBE);
+ spi_write_com(spi, 0xD530); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD531); spi_write_dat(spi, 0xF9);
+ spi_write_com(spi, 0xD532); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD533); spi_write_dat(spi, 0xFF);
+
+ spi_write_com(spi, 0xD600); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD601); spi_write_dat(spi, 0x05);
+ spi_write_com(spi, 0xD602); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD603); spi_write_dat(spi, 0x15);
+ spi_write_com(spi, 0xD604); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD605); spi_write_dat(spi, 0x30);
+ spi_write_com(spi, 0xD606); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD607); spi_write_dat(spi, 0x47);
+ spi_write_com(spi, 0xD608); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD609); spi_write_dat(spi, 0x5B);
+ spi_write_com(spi, 0xD60A); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD60B); spi_write_dat(spi, 0x7D);
+ spi_write_com(spi, 0xD60C); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD60D); spi_write_dat(spi, 0x9D);
+ spi_write_com(spi, 0xD60E); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD60F); spi_write_dat(spi, 0xCC);
+ spi_write_com(spi, 0xD610); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xD611); spi_write_dat(spi, 0xF3);
+ spi_write_com(spi, 0xD612); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD613); spi_write_dat(spi, 0x32);
+ spi_write_com(spi, 0xD614); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD615); spi_write_dat(spi, 0x63);
+ spi_write_com(spi, 0xD616); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD617); spi_write_dat(spi, 0xB1);
+ spi_write_com(spi, 0xD618); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD619); spi_write_dat(spi, 0xF0);
+ spi_write_com(spi, 0xD61A); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xD61B); spi_write_dat(spi, 0xF2);
+ spi_write_com(spi, 0xD61C); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD61D); spi_write_dat(spi, 0x2A);
+ spi_write_com(spi, 0xD61E); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD61F); spi_write_dat(spi, 0x67);
+ spi_write_com(spi, 0xD620); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD621); spi_write_dat(spi, 0x90);
+ spi_write_com(spi, 0xD622); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD623); spi_write_dat(spi, 0xCB);
+ spi_write_com(spi, 0xD624); spi_write_dat(spi, 0x02);
+ spi_write_com(spi, 0xD625); spi_write_dat(spi, 0xF2);
+ spi_write_com(spi, 0xD626); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD627); spi_write_dat(spi, 0x2A);
+ spi_write_com(spi, 0xD628); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD629); spi_write_dat(spi, 0x51);
+ spi_write_com(spi, 0xD62A); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD62B); spi_write_dat(spi, 0x80);
+ spi_write_com(spi, 0xD62C); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD62D); spi_write_dat(spi, 0x9F);
+ spi_write_com(spi, 0xD62E); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD62F); spi_write_dat(spi, 0xBE);
+ spi_write_com(spi, 0xD630); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD631); spi_write_dat(spi, 0xF9);
+ spi_write_com(spi, 0xD632); spi_write_dat(spi, 0x03);
+ spi_write_com(spi, 0xD633); spi_write_dat(spi, 0xFF);
+
+ /* LV2 Page 0 enable */
+ spi_write_com(spi, 0xF000); spi_write_dat(spi, 0x55);
+ spi_write_com(spi, 0xF001); spi_write_dat(spi, 0xAA);
+ spi_write_com(spi, 0xF002); spi_write_dat(spi, 0x52);
+ spi_write_com(spi, 0xF003); spi_write_dat(spi, 0x08);
+ spi_write_com(spi, 0xF004); spi_write_dat(spi, 0x00);
+
+ /* Display control */
+ spi_write_com(spi, 0xB100); spi_write_dat(spi, 0xFC);
+ spi_write_com(spi, 0xB101); spi_write_dat(spi, 0x00);
+
+ /* Source hold time */
+ spi_write_com(spi, 0xB600); spi_write_dat(spi, 0x05);
+
+ /* Gate EQ control */
+ spi_write_com(spi, 0xB700); spi_write_dat(spi, 0x70);
+ spi_write_com(spi, 0xB701); spi_write_dat(spi, 0x70);
+
+ /* Source EQ control (Mode 2) */
+ spi_write_com(spi, 0xB800); spi_write_dat(spi, 0x01);
+ spi_write_com(spi, 0xB801); spi_write_dat(spi, 0x05);
+ spi_write_com(spi, 0xB802); spi_write_dat(spi, 0x05);
+ spi_write_com(spi, 0xB803); spi_write_dat(spi, 0x05);
+
+ /* Inversion mode (Column) */
+ spi_write_com(spi, 0xBC00); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xBC01); spi_write_dat(spi, 0x00);
+ spi_write_com(spi, 0xBC02); spi_write_dat(spi, 0x00);
+
+ /* Timing control 8phase dual side/4H/4delay/RST_EN */
+ spi_write_com(spi, 0xC900); spi_write_dat(spi, 0xD0);
+ spi_write_com(spi, 0xC901); spi_write_dat(spi, 0x82);
+ spi_write_com(spi, 0xC902); spi_write_dat(spi, 0x50);
+ spi_write_com(spi, 0xC903); spi_write_dat(spi, 0x50);
+ spi_write_com(spi, 0xC904); spi_write_dat(spi, 0x50);
+
+ spi_write_com(spi, 0x3A00); spi_write_dat(spi, 0x55);
+ mdelay(120);
+ spi_write_com(spi, 0x1100);
+ mdelay(120);
+ spi_write_com(spi, 0x2900);
+ mdelay(120);
+ /* spi_write_com(spi, 0x2100); spi_write_dat(spi, 0x00); */
+ spi_write_com(spi, 0x2C00);
+
+ return 0;
+err_claim_bus:
+ spi_free_slave(spi);
+ return -1;
+}
COBJS-$(CONFIG_S5P) += s5p_wdt.o
COBJS-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
COBJS-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
+COBJS-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * omap_wdt.c
+ *
+ * (C) Copyright 2013
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * Based on:
+ *
+ * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
+ *
+ * commit 2d991a164a61858012651e13c59521975504e260
+ * Author: Bill Pemberton <wfp5p@virginia.edu>
+ * Date: Mon Nov 19 13:21:41 2012 -0500
+ *
+ * watchdog: remove use of __devinit
+ *
+ * CONFIG_HOTPLUG is going away as an option so __devinit is no longer
+ * needed.
+ *
+ * Author: MontaVista Software, Inc.
+ * <gdavis@mvista.com> or <source@mvista.com>
+ *
+ * History:
+ *
+ * 20030527: George G. Davis <gdavis@mvista.com>
+ * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
+ * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
+ * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
+ *
+ * Copyright (c) 2004 Texas Instruments.
+ * 1. Modified to support OMAP1610 32-KHz watchdog timer
+ * 2. Ported to 2.6 kernel
+ *
+ * Copyright (c) 2005 David Brownell
+ * Use the driver model and standard identifiers; handle bigger timeouts.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/cpu.h>
+
+/* Hardware timeout in seconds */
+#define WDT_HW_TIMEOUT 60
+
+static unsigned int wdt_trgr_pattern = 0x1234;
+
+void hw_watchdog_reset(void)
+{
+ struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
+
+ /* wait for posted write to complete */
+ while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR)
+ ;
+
+ wdt_trgr_pattern = ~wdt_trgr_pattern;
+ writel(wdt_trgr_pattern, &wdt->wdtwtgr);
+
+ /* wait for posted write to complete */
+ while ((readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WTGR))
+ ;
+}
+
+static int omap_wdt_set_timeout(unsigned int timeout)
+{
+ struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
+ u32 pre_margin = GET_WLDR_VAL(timeout);
+
+ /* just count up at 32 KHz */
+ while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
+ ;
+
+ writel(pre_margin, &wdt->wdtwldr);
+ while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
+ ;
+
+ return 0;
+}
+
+void hw_watchdog_init(void)
+{
+ struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
+
+ /* initialize prescaler */
+ while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
+ ;
+
+ writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &wdt->wdtwclr);
+ while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
+ ;
+
+ omap_wdt_set_timeout(WDT_HW_TIMEOUT);
+
+ /* Sequence to enable the watchdog */
+ writel(0xBBBB, &wdt->wdtwspr);
+ while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
+ ;
+
+ writel(0x4444, &wdt->wdtwspr);
+ while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
+ ;
+}
+
+void hw_watchdog_disable(void)
+{
+ struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
+
+ /*
+ * Disable watchdog
+ */
+ writel(0xAAAA, &wdt->wdtwspr);
+ while (readl(&wdt->wdtwwps) != 0x0)
+ ;
+ writel(0x5555, &wdt->wdtwspr);
+ while (readl(&wdt->wdtwwps) != 0x0)
+ ;
+}
debug("clustnum: %d, startsect: %d\n", clustnum, startsect);
- if (disk_write(startsect, size / mydata->sect_size, buffer) < 0) {
- debug("Error writing data\n");
- return -1;
+ if ((size / mydata->sect_size) > 0) {
+ if (disk_write(startsect, size / mydata->sect_size, buffer) < 0) {
+ debug("Error writing data\n");
+ return -1;
+ }
}
if (size % mydata->sect_size) {
| PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \
| PORT_IRQ_D2H_REG_FIS
+/* PORT_SCR_STAT bits */
+#define PORT_SCR_STAT_DET_MASK 0x3
+#define PORT_SCR_STAT_DET_COMINIT 0x1
+#define PORT_SCR_STAT_DET_PHYRDY 0x3
+
/* PORT_CMD bits */
#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
#define AHCI_MAX_PORTS 32
-/* SETFEATURES stuff */
-#define SETFEATURES_XFER 0x03
-#define XFER_UDMA_7 0x47
-#define XFER_UDMA_6 0x46
-#define XFER_UDMA_5 0x45
-#define XFER_UDMA_4 0x44
-#define XFER_UDMA_3 0x43
-#define XFER_UDMA_2 0x42
-#define XFER_UDMA_1 0x41
-#define XFER_UDMA_0 0x40
-#define XFER_MW_DMA_2 0x22
-#define XFER_MW_DMA_1 0x21
-#define XFER_MW_DMA_0 0x20
-#define XFER_SW_DMA_2 0x12
-#define XFER_SW_DMA_1 0x11
-#define XFER_SW_DMA_0 0x10
-#define XFER_PIO_4 0x0C
-#define XFER_PIO_3 0x0B
-#define XFER_PIO_2 0x0A
-#define XFER_PIO_1 0x09
-#define XFER_PIO_0 0x08
-#define XFER_PIO_SLOW 0x00
-
#define ATA_FLAG_SATA (1 << 3)
#define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */
#define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */
#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LIBATA
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LIBATA
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LIBATA
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LIBATA
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LIBATA
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
/*
* RapidIO
"echo Running uenvcmd ...;" \
"run uenvcmd;" \
"fi;" \
- "run mmcloados;" \
+ "if run loaduimage; then " \
+ "run mmcloados;" \
+ "fi;" \
"fi;\0" \
"spiboot=echo Booting from spi ...; " \
"run spiargs; " \
"run mmcboot;" \
"run nandboot;"
-/* USB Composite download gadget - g_dnl */
-#define CONFIG_USB_GADGET
-#define CONFIG_USBDOWNLOAD_GADGET
-
-/* USB TI's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0403
-#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
-
-/* USB Device Firmware Update support */
-#define CONFIG_DFU_FUNCTION
-#define CONFIG_DFU_MMC
-#define CONFIG_CMD_DFU
-#define DFU_ALT_INFO_MMC \
- "boot part 0 1;" \
- "rootfs part 0 2;" \
- "MLO fat 0 1;" \
- "MLO.raw mmc 100 100;" \
- "u-boot.img.raw mmc 300 400;" \
- "spl-os-args.raw mmc 80 80;" \
- "spl-os-image.raw mmc 900 2000;" \
- "spl-os-args fat 0 1;" \
- "spl-os-image fat 0 1;" \
- "u-boot.img fat 0 1;" \
- "uEnv.txt fat 0 1"
-#ifdef CONFIG_NAND
-#define CONFIG_DFU_NAND
-#define DFU_ALT_INFO_NAND \
- "SPL part 0 1;" \
- "SPL.backup1 part 0 2;" \
- "SPL.backup2 part 0 3;" \
- "SPL.backup3 part 0 4;" \
- "u-boot part 0 5;" \
- "u-boot-spl-os part 0 6;" \
- "kernel part 0 8;" \
- "rootfs part 0 9"
-#endif
-
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
/* SPL */
#ifndef CONFIG_NOR_BOOT
#define CONFIG_SPL_YMODEM_SUPPORT
+
+/* CPSW support */
+#define CONFIG_SPL_ETH_SUPPORT
+
+/* USB gadget RNDIS */
+#define CONFIG_SPL_MUSB_NEW_SUPPORT
+
+/* General network SPL, both CPSW and USB gadget RNDIS */
#define CONFIG_SPL_NET_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
-#define CONFIG_SPL_ETH_SUPPORT
+
+/* SPI flash. */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_BUS 0
#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-#define CONFIG_SPL_MUSB_NEW_SUPPORT
+
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#ifdef CONFIG_NAND
#endif
/*
- * USB configuration
+ * USB configuration. We enable MUSB support, both for host and for
+ * gadget. We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each. Then for host we
+ * add mass storage support and for gadget we add both RNDIS ethernet
+ * and DFU.
*/
#define CONFIG_USB_MUSB_DSPS
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_MUSB_GADGET
#define CONFIG_MUSB_PIO_ONLY
#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_USB_GADGET
+#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_MUSB_HOST
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
+
+/* USB TI's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x0403
+#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
+#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
#endif /* CONFIG_MUSB_GADGET */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
#undef CONFIG_SPL_ETH_SUPPORT
#endif
+/* USB Device Firmware Update support */
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+#define CONFIG_CMD_DFU
+#define DFU_ALT_INFO_MMC \
+ "boot part 0 1;" \
+ "rootfs part 0 2;" \
+ "MLO fat 0 1;" \
+ "MLO.raw mmc 100 100;" \
+ "u-boot.img.raw mmc 300 400;" \
+ "spl-os-args.raw mmc 80 80;" \
+ "spl-os-image.raw mmc 900 2000;" \
+ "spl-os-args fat 0 1;" \
+ "spl-os-image fat 0 1;" \
+ "u-boot.img fat 0 1;" \
+ "uEnv.txt fat 0 1"
+#ifdef CONFIG_NAND
+#define CONFIG_DFU_NAND
+#define DFU_ALT_INFO_NAND \
+ "SPL part 0 1;" \
+ "SPL.backup1 part 0 2;" \
+ "SPL.backup2 part 0 3;" \
+ "SPL.backup3 part 0 4;" \
+ "u-boot part 0 5;" \
+ "u-boot-spl-os part 0 6;" \
+ "kernel part 0 8;" \
+ "rootfs part 0 9"
+#endif
+
/*
* Default to using SPI for environment, etc.
* 0x000000 - 0x020000 : SPL (128KiB)
--- /dev/null
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Configuration settings for the SAMSUNG Arndale board.
+ */
+
+#ifndef __CONFIG_ARNDALE_H
+#define __CONFIG_ARNDALE_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG /* in a SAMSUNG core */
+#define CONFIG_S5P /* S5P Family */
+#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
+#define CONFIG_EXYNOS5250
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Enable fdt support for Exynos5250 */
+#define CONFIG_ARCH_DEVICE_TREE exynos5250
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* Allow tracing to be enabled */
+#define CONFIG_TRACE
+#define CONFIG_CMD_TRACE
+#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
+#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
+#define CONFIG_TRACE_EARLY
+#define CONFIG_TRACE_EARLY_ADDR 0x50000000
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_TEXT_BASE 0x43E00000
+
+/* input clock of PLL: SMDK5250 has 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP 0x00000BAD
+#define S5P_CHECK_DIDLE 0xBAD00000
+#define S5P_CHECK_LPA 0xABAD0000
+
+/* Offset for inform registers */
+#define INFORM0_OFFSET 0x800
+#define INFORM1_OFFSET 0x804
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE 115200
+#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
+#define CONFIG_SILENT_CONSOLE
+
+/* Console configuration */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define EXYNOS_DEVICE_SETTINGS \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXYNOS_DEVICE_SETTINGS
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
+#define CONFIG_DWMMC
+#define CONFIG_EXYNOS_DWMMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* PWM */
+#define CONFIG_PWM
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_HASH
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_EXYNOS
+#define CONFIG_USB_STORAGE
+
+/* MMC SPL */
+#define CONFIG_SPL
+#define COPY_BL2_FNPTR_ADDR 0x02020030
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+
+/* specific .lds file */
+#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
+#define CONFIG_SPL_TEXT_BASE 0x02023400
+#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
+
+#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT "ARNDALE # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_RD_LVL
+
+#define CONFIG_NR_DRAM_BANKS 8
+#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_IDENT_STRING " for ARNDALE"
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SECURE_BL1_ONLY
+
+/* Secure FW size configuration */
+#ifdef CONFIG_SECURE_BL1_ONLY
+#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
+#else
+#define CONFIG_SEC_FW_SIZE 0
+#endif
+
+/* Configuration of BL1, BL2, ENV Blocks on mmc */
+#define CONFIG_RES_BLOCK_SIZE (512)
+#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
+
+#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
+#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
+#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
+#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
+
+#define CONFIG_SPI_BOOTING
+#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
+#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
+
+#define CONFIG_IRAM_STACK 0x02050000
+
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
+
+/* I2C */
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_HARD_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
+#define CONFIG_DRIVER_S3C24X0_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_MAX_I2C_NUM 8
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_I2C_EDID
+
+/* PMIC */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_I2C
+#define CONFIG_PMIC_MAX77686
+
+#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-arndale
+
+/* Ethernet Controllor Driver */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE 0x5000000
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_ENV_SROM_BANK 1
+#endif /*CONFIG_CMD_NET*/
+
+/* Enable PXE Support */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
+#endif
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+/* Enable Time Command */
+#define CONFIG_CMD_TIME
+
+#endif /* __CONFIG_H */
#include <asm/hardware.h>
+#define CONFIG_SYS_TEXT_BASE 0x73f00000
+
#define CONFIG_AT91_LEGACY
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_PMECC_CAP 2
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000
+
+#define CONFIG_CMD_NAND_TRIMFFS
+
#endif
#define CONFIG_MTD_PARTITIONS
#include <asm/hardware.h>
+#define CONFIG_SYS_TEXT_BASE 0x26f00000
+
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
#define CONFIG_ATMEL_NAND_HW_PMECC 1
#define CONFIG_PMECC_CAP 2
#define CONFIG_PMECC_SECTOR_SIZE 512
-#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000
+
+#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_MTDPARTS
#define CONFIG_SPL_STACK (0x00010000 + 0x7f00)
#define CONFIG_SPL_TEXT_BASE 0x00000020 /*CONFIG_SYS_SRAM_START*/
+/* Provide at least 16MB spacing between us and the Linux Kernel image */
+#define CONFIG_SPL_PAD_TO 12320
#define CONFIG_SPL_MAX_FOOTPRINT 12288
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LIBATA
#define CONFIG_SYS_64BIT_LBA
#define CONFIG_SATA_INTEL 1
#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
#include "tegra114-common.h"
-/* Must be off for Dalmore to boot !?!? FIXME */
-#define CONFIG_SYS_DCACHE_OFF
-
/* Enable fdt support for Dalmore. Flash the image in u-boot-dtb.bin */
#define CONFIG_DEFAULT_DEVICE_TREE tegra114-dalmore
#define CONFIG_OF_CONTROL
#include <configs/omap5_common.h>
/* CPSW Ethernet */
-#define CONFIG_CMD_NET
+#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_MII
-#define CONFIG_DRIVER_TI_CPSW
-#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_NET_MULTI
-#define CONFIG_PHY_GIGE
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
+#define CONFIG_MII /* Required in net/eth.c */
+#define CONFIG_PHY_GIGE /* per-board part of CPSW */
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR 2
--- /dev/null
+/*
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_DXR2_H
+#define __CONFIG_DXR2_H
+
+#define CONFIG_SIEMENS_DXR2
+#define MACH_TYPE_DXR2 4315
+#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DXR2
+
+#include "siemens-am33x-common.h"
+
+#define CONFIG_SYS_MPUCLK 275
+#define DXR2_IOCTRL_VAL 0x18b
+#define DDR_PLL_FREQ 266
+#define CONFIG_SPL_AM33XX_DO_NOT_ENABLE_RTC32K
+
+#define BOARD_DFU_BUTTON_GPIO 27
+#define BOARD_DFU_BUTTON_LED 64
+
+#undef CONFIG_DOS_PARTITION
+#undef CONFIG_CMD_FAT
+
+
+ /* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define EEPROM_ADDR_DDR3 0x90
+#define EEPROM_ADDR_CHIP 0x120
+
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300
+
+#undef CONFIG_SPL_NET_SUPPORT
+#undef CONFIG_SPL_NET_VCI_STRING
+#undef CONFIG_SPL_ETH_SUPPORT
+
+#undef CONFIG_MII
+#undef CONFIG_PHY_GIGE
+#define CONFIG_PHY_ADDR 0
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_FACTORYSET
+
+/* Watchdog */
+#define CONFIG_OMAP_WATCHDOG
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hostname=dxr2\0" \
+ "nand_img_size=0x300000\0" \
+ "optargs=\0" \
+ CONFIG_COMMON_ENV_SETTINGS
+
+#ifndef CONFIG_RESTORE_FLASH
+/* set to negative value for no autoboot */
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_BOOTCOMMAND \
+"if dfubutton; then " \
+ "run dfu_start; " \
+ "reset; " \
+"fi;" \
+"if ping ${serverip}; then " \
+ "run net_nfs; " \
+"fi;" \
+"run nand_boot;"
+
+#else
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv autoload no; " \
+ "dhcp; " \
+ "if tftp 80000000 debrick.scr; then " \
+ "source 80000000; " \
+ "fi"
+#endif
+#endif /* CONFIG_SPL_BUILD */
+#endif /* ! __CONFIG_DXR2_H */
#define CONFIG_SYS_TEXT_BASE 0x21f00000
#endif
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
+#define CONFIG_STANDALONE_LOAD_ADDR 0x21000000
#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
-#define CONFIG_I2C_CMD_NO_FLAT
#define CONFIG_I2C_CMD_TREE
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT
-
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_UBIFS
#define CONFIG_SYS_LONGHELP
/*
- * Filesystems
+ * MTD defines
*/
-#define CONFIG_JFFS2_NAND 1
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
-#ifndef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV "nand0"
-#define CONFIG_JFFS2_PART_OFFSET 0
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#else
-#define MTDIDS_DEFAULT "nor0=0,nand0=1"
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
#define MTDPARTS_DEFAULT "mtdparts=" \
- "0:" \
- "384k(U-Boot)," \
- "128k(Env)," \
- "128k(Splash)," \
- "4M(Kernel)," \
- "-(FS)" \
+ "physmap-flash.0:" \
+ "512k(U-Boot)," \
+ "128k(Env)," \
+ "128k(Splash)," \
+ "4M(Kernel)," \
+ "384k(MiniFS)," \
+ "-(FS)" \
";" \
- "1:" \
- "-(jffs2)"
-#endif /* CONFIG_JFFS2_CMDLINE */
-
+ "atmel_nand:" \
+ "1M(emergency)," \
+ "-(data)"
/*
* Hardware drivers
*/
#define CONFIG_BOOTDELAY 5
#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
+#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x80000)
#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */
#define CONFIG_BAUDRATE 115200
"displayheight=512\0" \
"displaybsteps=1023\0" \
"ubootaddr=10000000\0" \
- "splashimage=10080000\0" \
- "kerneladdr=100A0000\0" \
+ "splashimage=100A0000\0" \
+ "kerneladdr=100C0000\0" \
"kernelsize=00400000\0" \
- "rootfsaddr=104A0000\0" \
+ "rootfsaddr=10520000\0" \
"copy_addr=21200000\0" \
- "rootfssize=00B60000\0" \
+ "rootfssize=00AE0000\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
"bootargsdefaults=set bootargs " \
"console=ttyS0,115200 " \
"video=vcxk_fb:xres:${displaywidth}," \
"erase $(rootfsaddr) +$(rootfssize);" \
"cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
"\0" \
- "update_uboot=protect off 10000000 1005FFFF;" \
+ "update_uboot=protect off 10000000 1007FFFF;" \
"dhcp $(copy_addr) u-boot_eb_cpux9k2;" \
- "erase 10000000 1005FFFF;" \
+ "erase 10000000 1007FFFF;" \
"cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
- "protect on 10000000 1005FFFF;reset\0" \
+ "protect on 10000000 1007FFFF;reset\0" \
"update_splash=protect off $(splashimage) +20000;" \
"dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \
"erase $(splashimage) +20000;" \
- "cp.b $(fileaddr) 10080000 $(filesize);" \
+ "cp.b $(fileaddr) $(splashimage) $(filesize);" \
"protect on $(splashimage) +20000;reset\0" \
"emergency=run bootargsdefaults;" \
"set bootargs $(bootargs) root=initramfs boot=emergency " \
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
#define CONFIG_S5P /* S5P Family */
#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
-#define CONFIG_SMDK5250 /* which is in a SMDK5250 */
+#define CONFIG_EXYNOS5250
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfff3cf0c
#define CONFIG_MISC_INIT_R
+#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 5
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
/*
* NS16550 Configuration
#define CONFIG_SYS_GPIO_PHY1_RST 12
#define CONFIG_SYS_GPIO_FLASH_WP 14
#define CONFIG_SYS_GPIO_PHY0_RST 22
+#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49
#define CONFIG_SYS_GPIO_DSPIC_READY 51
#define CONFIG_SYS_GPIO_CAN_ENABLE 53
#define CONFIG_SYS_GPIO_LSB_ENABLE 54
#define CONFIG_SYS_GPIO_SYSMON_STATUS 62
#define CONFIG_SYS_GPIO_WATCHDOG 63
+/* On LCD4, GPIO49 has to be configured to 0 instead of 1 */
+#ifdef CONFIG_LCD4_LWMON5
+#define GPIO49_VAL 0
+#else
+#define GPIO49_VAL 1
+#endif
+
/*
* PPC440 GPIO Configuration
*/
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
/* GPIO */
#define CONFIG_MXS_GPIO
-/* DUART Serial Driver */
+/*
+ * DUART Serial Driver.
+ * Conflicts with AUART driver which can be set by board.
+ */
+#ifndef CONFIG_MXS_AUART
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
#define CONFIG_CONS_INDEX 0
+#endif
/* Default baudrate can be overriden by board! */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
* High Level Configuration Options
*/
#define CONFIG_4430SDP 1 /* working with SDP */
+#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_4430SDP
#include <configs/omap4_common.h>
/* Use General purpose timer 1 */
#define CONFIG_SYS_TIMERBASE GPT2_BASE
+/*
+ * For the DDR timing information we can either dynamically determine
+ * the timings to use or use pre-determined timings (based on using the
+ * dynamic method. Default to the static timing infomation.
+ */
#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-
-/* Defines for SDRAM init */
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
"fi"
-/* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE 0x40300350
-#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */
+/*
+ * SPL related defines. The Public RAM memory map the ROM defines the
+ * area between 0x40300000 and 0x4031E000 as a download area for OMAP5
+ * (dra7xx is larger, but we do not need to be larger at this time). We
+ * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
+ * print some information.
+ */
+#define CONFIG_SPL_TEXT_BASE 0x40300000
+#define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_DISPLAY_PRINT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
"uuid_disk=${uuid_gpt_disk};" \
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
+#include <configs/omap5_common.h>
+
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 UART3_BASE
#define CONFIG_BAUDRATE 115200
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
+/* Required support for the TCA642X GPIO we have on the uEVM */
#define CONFIG_TCA642X
#define CONFIG_CMD_TCA642X
#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4
#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
+/* USB UHH support options */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80
+#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79
+
+/* Enabled commands */
+#define CONFIG_CMD_DHCP /* DHCP Support */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_NFS /* NFS support */
+
+/* USB Networking options */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
#define CONSOLEDEV "ttyO2"
-#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296
-#include <configs/omap5_common.h>
+/* Max time to hold reset on this board, see doc/README.omap-reset-time */
+#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296
#endif /* __CONFIG_OMAP5_EVM_H */
--- /dev/null
+/*
+ * siemens pxm2
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_PXM2_H
+#define __CONFIG_PXM2_H
+
+#define CONFIG_SIEMENS_PXM2
+#define MACH_TYPE_PXM2 4309
+#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_PXM2
+
+#include "siemens-am33x-common.h"
+
+#define CONFIG_SYS_MPUCLK 720
+#define DXR2_IOCTRL_VAL 0x18b
+#define DDR_PLL_FREQ 266
+
+#define BOARD_DFU_BUTTON_GPIO 59
+#define BOARD_DFU_BUTTON_LED 117
+#define BOARD_LCD_POWER 111
+#define BOARD_BACK_LIGHT 112
+#define BOARD_TOUCH_POWER 57
+
+ /* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+
+
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300
+
+#undef CONFIG_SPL_NET_SUPPORT
+#undef CONFIG_SPL_NET_VCI_STRING
+#undef CONFIG_SPL_ETH_SUPPORT
+
+#define CONFIG_PHY_ADDR 0
+#define CONFIG_PHY_ATHEROS
+
+#define CONFIG_FACTORYSET
+
+/* UBI Support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+/* Watchdog */
+#define CONFIG_OMAP_WATCHDOG
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hostname=pxm2\0" \
+ "nand_img_size=0x500000\0" \
+ "optargs=\0" \
+ CONFIG_COMMON_ENV_SETTINGS \
+ "mmc_dev=0\0" \
+ "mmc_root=/dev/mmcblk0p2 rw\0" \
+ "mmc_root_fs_type=ext4 rootwait\0" \
+ "mmc_load_uimage=" \
+ "mmc rescan; " \
+ "setenv bootfile uImage;" \
+ "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \
+ "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "mmc_args=run bootargs_defaults;" \
+ "mtdparts default;" \
+ "setenv bootargs ${bootargs} " \
+ "root=${mmc_root} ${mtdparts}" \
+ "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \
+ "eth=${ethaddr} " \
+ "\0" \
+ "mmc_boot=run mmc_args; " \
+ "run mmc_load_uimage; " \
+ "bootm ${kloadaddr}\0" \
+ ""
+
+#ifndef CONFIG_RESTORE_FLASH
+/* set to negative value for no autoboot */
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_BOOTCOMMAND \
+ "if dfubutton; then " \
+ "run dfu_start; " \
+ "reset; " \
+ "fi; " \
+ "if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmc_dev};" \
+ "if run loadbootenv; then " \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run mmc_load_uimage; then " \
+ "run mmc_args;" \
+ "bootm ${kloadaddr};" \
+ "fi;" \
+ "fi;" \
+ "run nand_boot;" \
+ "if ping ${serverip}; then " \
+ "run net_nfs; " \
+ "fi; "
+
+#else
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv autoload no; " \
+ "dhcp; " \
+ "if tftp 80000000 debrick.scr; then " \
+ "source 80000000; " \
+ "fi"
+#endif
+#endif /* CONFIG_SPL_BUILD */
+
+#define CONFIG_VIDEO
+#if defined(CONFIG_VIDEO)
+#define CONFIG_VIDEO_DA8XX
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CMD_BMP
+#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE
+#define PWM_TICKS 0x1388
+#define PWM_DUTY 0x200
+#endif
+
+#endif /* ! __CONFIG_PXM2_H */
--- /dev/null
+/*
+ * siemens rut
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_RUT_H
+#define __CONFIG_RUT_H
+
+#define CONFIG_SIEMENS_RUT
+#define MACH_TYPE_RUT 4316
+#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT
+
+#include "siemens-am33x-common.h"
+
+#define CONFIG_SYS_MPUCLK 600
+#define RUT_IOCTRL_VAL 0x18b
+#define DDR_PLL_FREQ 303
+
+ /* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
+
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200
+
+#undef CONFIG_SPL_NET_SUPPORT
+#undef CONFIG_SPL_NET_VCI_STRING
+#undef CONFIG_SPL_ETH_SUPPORT
+
+#define CONFIG_PHY_ADDR 1
+#define CONFIG_PHY_NATSEMI
+
+#define CONFIG_FACTORYSET
+
+/* UBI Support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+/* Watchdog */
+#define WATCHDOG_TRIGGER_GPIO 14
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hostname=rut\0" \
+ "splashpos=488,352\0" \
+ "optargs=fixrtc --no-log consoleblank=0 \0" \
+ CONFIG_COMMON_ENV_SETTINGS \
+ "mmc_dev=0\0" \
+ "mmc_root=/dev/mmcblk0p2 rw\0" \
+ "mmc_root_fs_type=ext4 rootwait\0" \
+ "mmc_load_uimage=" \
+ "mmc rescan; " \
+ "setenv bootfile uImage;" \
+ "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \
+ "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "mmc_args=run bootargs_defaults;" \
+ "mtdparts default;" \
+ "setenv bootargs ${bootargs} " \
+ "root=${mmc_root} ${mtdparts}" \
+ "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \
+ "eth=${ethaddr} " \
+ "\0" \
+ "mmc_boot=run mmc_args; " \
+ "run mmc_load_uimage; " \
+ "bootm ${kloadaddr}\0" \
+ ""
+
+#ifndef CONFIG_RESTORE_FLASH
+/* set to negative value for no autoboot */
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmc_dev};" \
+ "if run loadbootenv; then " \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run mmc_load_uimage; then " \
+ "run mmc_args;" \
+ "bootm ${kloadaddr};" \
+ "fi;" \
+ "fi;" \
+ "run nand_boot;" \
+ "if ping ${serverip}; then " \
+ "run net_nfs; " \
+ "fi; "
+
+#else
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv autoload no; " \
+ "dhcp; " \
+ "if tftp 80000000 debrick.scr; then " \
+ "source 80000000; " \
+ "fi"
+#endif
+
+#endif /* CONFIG_SPL_BUILD */
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_HW_WATCHDOG
+#endif
+
+#define CONFIG_VIDEO
+#if defined(CONFIG_VIDEO)
+#define CONFIG_VIDEO_DA8XX
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CMD_BMP
+#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE
+
+#define CONFIG_SPI
+#define CONFIG_OMAP3_SPI
+
+#define BOARD_LCD_RESET 115 /* Bank 3 pin 19 */
+#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_FORMIKE
+#endif
+
+#endif /* ! __CONFIG_RUT_H */
/* DRAM Base */
#define CONFIG_SYS_SDRAM_BASE 0x30000000
+/* Text Base */
+#define CONFIG_SYS_TEXT_BASE 0x34800000
+
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define LCD_BPP LCD_COLOR16
#define LCD_OUTPUT_BPP 24
#define CONFIG_LCD_LOGO
-#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO
#define CONFIG_LCD_INFO_BELOW_LOGO
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_CMD_NAND
#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_MAX_CHIPS 1
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_ATMEL_NAND_HW_PMECC
#define CONFIG_PMECC_CAP 4
#define CONFIG_PMECC_SECTOR_SIZE 512
-#define CONFIG_PMECC_INDEX_TABLE_OFFSET ATMEL_PMECC_INDEX_OFFSET_512
#define CONFIG_CMD_NAND_TRIMFFS
#endif
/* Ethernet Hardware */
#define CONFIG_MACB
#define CONFIG_RMII
-#define CONFIG_NET_MULTI
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_RGMII
+#define CONFIG_CMD_MII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
/* MMC */
#define CONFIG_CMD_MMC
"bootm 0x22000000 - 0x21000000"
#define CONFIG_SYS_MMC_ENV_DEV 0
#else
-#define CONIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_NOWHERE
#endif
#ifdef CONFIG_SYS_USE_MMC
"stdout=serial\0" \
"stderr=serial\0"
+#define CONFIG_GZIP_COMPRESSED
+#define CONFIG_BZIP2
+#define CONFIG_LZO
+#define CONFIG_LZMA
+
#endif
--- /dev/null
+/*
+ * siemens am33x common board options
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_SIEMENS_AM33X_COMMON_H
+#define __CONFIG_SIEMENS_AM33X_COMMON_H
+
+#define CONFIG_AM33XX
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+
+#include <asm/arch/omap.h>
+
+#define CONFIG_DMA_COHERENT
+#define CONFIG_DMA_COHERENT_SIZE (1 << 20)
+
+#define CONFIG_ENV_SIZE (0x2000)
+#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT "U-Boot# "
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_MACH_TYPE CONFIG_SIEMENS_MACH_TYPE
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_ROOTPATH "/opt/eldk"
+#endif
+
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_AUTOLOAD "yes"
+
+/* Clock Defines */
+#define V_OSCK 24000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+/* We set the max number of command args high to avoid HUSH bugs. */
+#define CONFIG_SYS_MAXARGS 32
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * memtest works on 8 MB in DRAM after skipping 32MB from
+ * start addr of ram disk
+ */
+#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024))
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
+ + (8 * 1024 * 1024))
+
+#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
+#define CONFIG_SYS_HZ 1000 /* 1ms clock */
+
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_SPI
+#define CONFIG_OMAP3_SPI
+#define CONFIG_MTD_DEVICE
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED (75000000)
+
+ /* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
+ GENERATED_GBL_DATA_SIZE)
+ /* Platform/Board specific defs */
+#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK (48000000)
+#define CONFIG_SYS_NS16550_COM1 0x44e09000
+#define CONFIG_SYS_NS16550_COM4 0x481a6000
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SERIAL1 1
+#define CONFIG_CONS_INDEX 1
+
+/* I2C Configuration */
+#define CONFIG_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_DRIVER_OMAP24XX_I2C
+
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x402F0400
+#define CONFIG_SPL_MAX_SIZE (101 * 1024)
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_FS_FAT
+#define CONFIG_SPL_I2C_SUPPORT
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+
+#define CONFIG_SYS_NAND_ECCSTEPS 4
+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
+ CONFIG_SYS_NAND_ECCSTEPS)
+
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x80100000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * USB configuration
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_GADGET
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_MUSB_HOST
+
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
+#ifdef CONFIG_MUSB_GADGET
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
+#endif /* CONFIG_MUSB_GADGET */
+
+#define CONFIG_USB_GADGET
+#define CONFIG_USBDOWNLOAD_GADGET
+
+/* USB TI's IDs */
+#define CONFIG_USBD_HS
+#define CONFIG_G_DNL_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM 0x4a47
+#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
+
+/* USB Device Firmware Update support */
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_NAND
+#define CONFIG_CMD_DFU
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20)
+
+#endif /* CONFIG_SPL_BUILD */
+
+/*
+ * Default to using SPI for environment, etc. We have multiple copies
+ * of SPL as the ROM will check these locations.
+ * 0x0 - 0x20000 : First copy of SPL
+ * 0x20000 - 0x40000 : Second copy of SPL
+ * 0x40000 - 0x60000 : Third copy of SPL
+ * 0x60000 - 0x80000 : Fourth copy of SPL
+ * 0x80000 - 0xDF000 : U-Boot
+ * 0xDF000 - 0xE0000 : U-Boot Environment
+ * 0xE0000 - 0x442000 : Linux Kernel
+ * 0x442000 - 0x800000 : Userland
+ */
+#if defined(CONFIG_SPI_BOOT)
+# undef CONFIG_ENV_IS_NOWHERE
+# define CONFIG_ENV_IS_IN_SPI_FLASH
+# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+# define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */
+# define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
+#endif /* SPI support */
+
+/* Unsupported features */
+#undef CONFIG_USE_IRQ
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_CMD_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+
+#define CONFIG_NAND
+/* NAND support */
+#ifdef CONFIG_NAND
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+
+#define MTDIDS_NAME_STR "omap2-nand.0"
+#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "128k(spl)," \
+ "128k(spl.backup1)," \
+ "128k(spl.backup2)," \
+ "128k(spl.backup3)," \
+ "1920k(u-boot)," \
+ "128k(uboot.env)," \
+ "5120k(kernel_a)," \
+ "5120k(kernel_b)," \
+ "8192k(mtdoops)," \
+ "-(rootfs)"
+/*
+ * chip-size = 256MiB
+ *| name | size | address area |
+ *-------------------------------------------------------
+ *| spl | 128.000 KiB | 0x 0..0x 1ffff |
+ *| spl.backup1 | 128.000 KiB | 0x 20000..0x 3ffff |
+ *| spl.backup2 | 128.000 KiB | 0x 40000..0x 5ffff |
+ *| spl.backup3 | 128.000 KiB | 0x 60000..0x 7ffff |
+ *| u-boot | 1.875 MiB | 0x 80000..0x 25ffff |
+ *| uboot.env | 128.000 KiB | 0x 260000..0x 27ffff |
+ *| kernel_a | 5.000 MiB | 0x 280000..0x 77ffff |
+ *| kernel_b | 5.000 MiB | 0x 780000..0x c7ffff |
+ *| mtdoops | 8.000 MiB | 0x c80000..0x 147ffff |
+ *| rootfs | 235.500 MiB | 0x 1480000..0x fffffff |
+ *-------------------------------------------------------
+ */
+
+#define DFU_ALT_INFO_NAND \
+ "spl part 0 1;" \
+ "spl.backup1 part 0 2;" \
+ "spl.backup2 part 0 3;" \
+ "spl.backup3 part 0 4;" \
+ "u-boot part 0 5;" \
+ "u-boot.env part 0 6;" \
+ "kernel_a part 0 7;" \
+ "kernel_b part 0 8;" \
+ "rootfs partubi 0 10"
+
+#define CONFIG_COMMON_ENV_SETTINGS \
+ "verify=no \0" \
+ "project_dir=systemone\0" \
+ "loadaddr=0x82000000\0" \
+ "kloadaddr=0x81000000\0" \
+ "script_addr=0x81900000\0" \
+ "console=console=ttyMTD,mtdoops console=ttyO0,115200n8\0" \
+ "active_set=a\0" \
+ "nand_active_ubi_vol=rootfs_a\0" \
+ "nand_root_fs_type=ubifs rootwait=1\0" \
+ "nand_src_addr=0x280000\0" \
+ "nand_src_addr_a=0x280000\0" \
+ "nand_src_addr_b=0x780000\0" \
+ "nfsopts=nolock rw mem=128M\0" \
+ "ip_method=none\0" \
+ "bootenv=uEnv.txt\0" \
+ "bootargs_defaults=setenv bootargs " \
+ "console=${console} " \
+ "${optargs}\0" \
+ "nand_args=run bootargs_defaults;" \
+ "mtdparts default;" \
+ "setenv nand_active_ubi_vol rootfs_${active_set};" \
+ "setenv ${active_set} true;" \
+ "if test -n ${a}; then " \
+ "setenv nand_src_addr ${nand_src_addr_a};" \
+ "fi;" \
+ "if test -n ${b}; then " \
+ "setenv nand_src_addr ${nand_src_addr_b};" \
+ "fi;" \
+ "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
+ "ubi.mtd=9,2048;" \
+ "setenv bootargs ${bootargs} " \
+ "root=${nand_root} noinitrd ${mtdparts} " \
+ "rootfstype=${nand_root_fs_type} ip=${ip_method} " \
+ "console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \
+ "=mtdoops\0" \
+ "dfu_args=run bootargs_defaults;" \
+ "setenv bootargs ${bootargs} ;" \
+ "mtdparts default; " \
+ "dfu nand 0; \0" \
+ "dfu_alt_info=" DFU_ALT_INFO_NAND "\0" \
+ "net_args=run bootargs_defaults;" \
+ "mtdparts default;" \
+ "setenv bootfile ${project_dir}/kernel/uImage;" \
+ "setenv rootpath /home/projects/${project_dir}/rootfs;" \
+ "setenv bootargs ${bootargs} " \
+ "root=/dev/nfs ${mtdparts} " \
+ "nfsroot=${serverip}:${rootpath},${nfsopts} " \
+ "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \
+ "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
+ "nand_boot=echo Booting from nand, active set ${active_set} ...; " \
+ "run nand_args; " \
+ "nand read.i ${kloadaddr} ${nand_src_addr} " \
+ "${nand_img_size}; bootm ${kloadaddr}\0" \
+ "net_nfs=echo Booting from network ...; " \
+ "run net_args; " \
+ "tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \
+ "bootm ${kloadaddr}\0" \
+ "flash_self=run nand_boot\0" \
+ "flash_self_test=setenv bootargs_defaults ${bootargs_defaults} test; " \
+ "run nand_boot\0" \
+ "dfu_start=echo Preparing for dfu mode ...; " \
+ "run dfu_args; \0" \
+ "preboot=echo; "\
+ "echo Type 'run flash_self' to use kernel and root " \
+ "filesystem on memory; echo Type 'run flash_self_test' to " \
+ "use kernel and root filesystem on memory, boot in test " \
+ "mode; echo Not ready yet: 'run flash_nfs' to use kernel " \
+ "from memory and root filesystem over NFS; echo Type " \
+ "'run net_nfs' to get Kernel over TFTP and mount root " \
+ "filesystem over NFS; echo Set active_set variable to 'a' " \
+ "or 'b' to select kernel and rootfs partition; " \
+ "echo" \
+ "\0"
+
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
+#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */
+ /* to access nand at */
+ /* CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND
+ devices */
+#if !defined(CONFIG_SPI_BOOT)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#endif
+#endif
+
+#define CONFIG_OMAP_GPIO
+
+/* Watchdog */
+#define CONFIG_HW_WATCHDOG
+
+/* Stop autoboot with ESC ESC key detected */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR "\x1b\x1b"
+#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
+ "press \"<Esc><Esc>\" to stop\n", bootdelay
+
+#endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */
/* DRAM Base */
#define CONFIG_SYS_SDRAM_BASE 0x30000000
+/* Text Base */
+#define CONFIG_SYS_TEXT_BASE 0x34800000
+
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
/*
* High level configuration
*/
+/* Virtual target or real hardware */
+#define CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_ARMV7
#define CONFIG_L2_OFF
#define CONFIG_SINGLE_BOOTLOADER
#define CONFIG_SOCFPGA
+/* base address for .text section */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_TEXT_BASE 0x08000040
-#define V_NS16550_CLK 1000000
-#define CONFIG_BAUDRATE 57600
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_TIMER_CLOCK_KHZ 2400
+#else
+#define CONFIG_SYS_TEXT_BASE 0x01000040
+#endif
#define CONFIG_SYS_LOAD_ADDR 0x7fc0
/* Console I/O Buffer Size */
/* SDRAM Bank #1 */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* SDRAM memory size */
-#define PHYS_SDRAM_1_SIZE 0x80000000
+#define PHYS_SDRAM_1_SIZE 0x40000000
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_START 0x00000000
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 UART0_BASE
-
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define V_NS16550_CLK 1000000
+#else
+#define V_NS16550_CLK 100000000
+#endif
+#define CONFIG_BAUDRATE 115200
/*
* FLASH
/* This timer use eosc1 where the clock frequency is fixed
* throughout any condition */
#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
-
/* reload value when timer count to zero */
#define TIMER_LOAD_VAL 0xFFFFFFFF
+/* Timer info */
+#define CONFIG_SYS_HZ 1000
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_TIMER_CLOCK_KHZ 2400
+#else
+#define CONFIG_TIMER_CLOCK_KHZ 25000
+#endif
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_TEGRA /* which is a Tegra generic machine */
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#include <asm/arch/tegra.h> /* get chip and board defs */
/*
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_ENTERRCM
#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
/* Defines for SPL */
#define CONFIG_SPL
#define _TEGRA114_COMMON_H_
#include "tegra-common.h"
+/* Cortex-A15 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
/*
* NS16550 Configuration
*/
#define _TEGRA20_COMMON_H_
#include "tegra-common.h"
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
/*
* Errata configuration
*/
#define _TEGRA30_COMMON_H_
#include "tegra-common.h"
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
/*
* Errata configuration
*/
#define CONFIG_SYS_NS16550_CLK 48000000
/* Network defines. */
-#define CONFIG_CMD_NET
+#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_DRIVER_TI_CPSW
-#define CONFIG_MII
-#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_CMD_PING
+#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
+#define CONFIG_MII /* Required in net/eth.c */
-/* SPL defines. */
+/*
+ * SPL related defines. The Public RAM memory map the ROM defines the
+ * area between 0x402F0400 and 0x4030B800 as a download area and
+ * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also
+ * supports X-MODEM loading via UART, and we leverage this and then use
+ * Y-MODEM to load u-boot.img, when booted over UART.
+ */
#define CONFIG_SPL_TEXT_BASE 0x402F0400
-#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE)
-#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE)
/*
* Since SPL did pll and ddr initialization for us,
/* I2C IP block */
#define CONFIG_I2C
-#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_DRIVER_OMAP24XX_I2C
+#define CONFIG_CMD_I2C
/* MMC/SD IP block */
#define CONFIG_MMC
* access CS0 at is 0x8000000.
*/
#ifdef CONFIG_NAND
-#define CONFIG_CMD_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_BASE 0x8000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_CMD_NAND
#endif
/*
* console baudrate of 115200 and use the default baud rate table.
*/
#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
-#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "U-Boot# "
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_ENV_VARS_UBOOT_CONFIG /* Strongly encouraged */
+#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */
+
+/* As stated above, the following choices are optional. */
+#define CONFIG_SYS_LONGHELP
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_PROMPT "U-Boot# "
#define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_BAUDRATE 115200
/* We set the max number of command args high to avoid HUSH bugs. */
#define CONFIG_SYS_MAXARGS 64
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
/*
* When we have SPI, NOR or NAND flash we expect to be making use of
* mtdparts, both for ease of use in U-Boot and for passing information
* useful commands. Note that we must have set CONFIG_SYS_NO_FLASH
* prior to this include, in order to skip a few commands. When we do
* have flash, if we expect these commands they must be enabled in that
- * config.
+ * config. If desired, a specific list of desired commands can be used
+ * instead.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#endif
#ifdef CONFIG_MMC
+#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#endif
-/* General parts of the framework. */
+/* General parts of the framework, required. */
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
unsigned int dev;
unsigned int part;
+ /* for nand/ubi use */
+ unsigned int ubi;
};
static inline unsigned int get_mmc_blk_size(int dev)
#define IH_TYPE_AISIMAGE 13 /* TI Davinci AIS Image */
#define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image, can run from any load address */
#define IH_TYPE_PBLIMAGE 15 /* Freescale PBL Boot Image */
+#define IH_TYPE_MXSIMAGE 16 /* Freescale MXSBoot Image */
/*
* Compression Types
#define ndelay(x) udelay(1)
+#define dev_dbg(dev, fmt, args...) \
+ debug(fmt, ##args)
+#define dev_vdbg(dev, fmt, args...) \
+ debug(fmt, ##args)
+#define dev_info(dev, fmt, args...) \
+ printf(fmt, ##args)
+#define dev_err(dev, fmt, args...) \
+ printf(fmt, ##args)
#define printk printf
#define KERN_EMERG
#endif
#define __deprecated __attribute__((deprecated))
-#define __packed __attribute__((packed))
+#ifndef __packed
+# define __packed __attribute__((packed))
+#endif
#define __weak __attribute__((weak))
/*
* would be.
* [...]
*/
-#define __pure __attribute__((pure))
-#define __aligned(x) __attribute__((aligned(x)))
+#ifndef __pure
+# define __pure __attribute__((pure))
+#endif
+#ifndef __aligned
+# define __aligned(x) __attribute__((aligned(x)))
+#endif
#define __printf(a,b) __attribute__((format(printf,a,b)))
#define noinline __attribute__((noinline))
#define __attribute_const__ __attribute__((__const__))
#define __used __attribute__((__used__))
#define __must_check __attribute__((warn_unused_result))
#define __compiler_offsetof(a,b) __builtin_offsetof(a,b)
-#define __always_inline inline __attribute__((always_inline))
+#ifndef __always_inline
+# define __always_inline inline __attribute__((always_inline))
+#endif
/*
* A trick to suppress uninitialized variable warning without generating any
EN_LDO = (0x3 << 6),
};
+enum {
+ OPMODE_OFF = 0,
+ OPMODE_STANDBY,
+ OPMODE_LPM,
+ OPMODE_ON,
+};
+
+int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
+int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
+int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
+
+#define MAX77686_LDO_VOLT_MAX_HEX 0x3f
+#define MAX77686_LDO_VOLT_MASK 0x3f
+#define MAX77686_LDO_MODE_MASK 0xc0
+#define MAX77686_LDO_MODE_OFF (0x00 << 0x06)
+#define MAX77686_LDO_MODE_STANDBY (0x01 << 0x06)
+#define MAX77686_LDO_MODE_LPM (0x02 << 0x06)
+#define MAX77686_LDO_MODE_ON (0x03 << 0x06)
+#define MAX77686_BUCK_MODE_MASK 0x03
+#define MAX77686_BUCK_MODE_SHIFT_1 0x00
+#define MAX77686_BUCK_MODE_SHIFT_2 0x04
+#define MAX77686_BUCK_MODE_OFF 0x00
+#define MAX77686_BUCK_MODE_STANDBY 0x01
+#define MAX77686_BUCK_MODE_LPM 0x02
+#define MAX77686_BUCK_MODE_ON 0x03
+
/* Buck1 1 volt value */
#define MAX77686_BUCK1OUT_1V 0x5
/* Buck1 1.05 volt value */
/* Clear the display */
void video_clear(void);
+#if defined(CONFIG_FORMIKE)
+int kwh043st20_f01_spi_startup(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode);
+#endif
#endif
s.avail_out = dstlen;
do {
r = inflate(&s, Z_FINISH);
- if (r != Z_STREAM_END && r != Z_BUF_ERROR && stoponerr == 1) {
+ if (stoponerr == 1 && r != Z_STREAM_END &&
+ (s.avail_out == 0 || r != Z_BUF_ERROR)) {
printf("Error: inflate() returned %d\n", r);
inflateEnd(&s);
return -1;
}
s.avail_in = *lenp - offset - (int)(s.next_out - (unsigned char*)dst);
- s.avail_out = dstlen;
} while (r == Z_BUF_ERROR);
*lenp = s.next_out - (unsigned char *) dst;
inflateEnd(&s);
g_Alloc.Alloc = SzAlloc;
g_Alloc.Free = SzFree;
+ /* Short-circuit early if we know the buffer can't hold the results. */
+ if (outSizeFull != (SizeT)-1 && *uncompressedSize < outSizeFull)
+ return SZ_ERROR_OUTPUT_EOF;
+
/* Decompress */
- outProcessed = outSizeFull;
+ outProcessed = *uncompressedSize;
WATCHDOG_RESET();
res = LzmaDecode(
outStream, &outProcessed,
inStream + LZMA_DATA_OFFSET, &compressedSize,
- inStream, LZMA_PROPS_SIZE, LZMA_FINISH_ANY, &state, &g_Alloc);
+ inStream, LZMA_PROPS_SIZE, LZMA_FINISH_END, &state, &g_Alloc);
*uncompressedSize = outProcessed;
if (res != SZ_OK) {
return res;
unsigned char *start = dst;
const unsigned char *send = src + src_len;
u32 slen, dlen;
- size_t tmp;
+ size_t tmp, remaining;
int r;
src = parse_header(src);
if (!src)
return LZO_E_ERROR;
+ remaining = *dst_len;
while (src < send) {
/* read uncompressed block size */
dlen = get_unaligned_be32(src);
if (slen <= 0 || slen > dlen)
return LZO_E_ERROR;
+ /* abort if buffer ran out of room */
+ if (dlen > remaining)
+ return LZO_E_OUTPUT_OVERRUN;
+
/* decompress */
tmp = dlen;
r = lzo1x_decompress_safe((u8 *) src, slen, dst, &tmp);
src += slen;
dst += dlen;
+ remaining -= dlen;
}
return LZO_E_INPUT_OVERRUN;
if [ \( $# -eq 2 \) -a \( "$1" = "-A" \) ] ; then
# Automatic mode
- line=`egrep -i "^[[:space:]]*${2}[[:space:]]" boards.cfg` || {
+ line=`awk '($0 !~ /^#/ && $7 ~ /^'"$2"'$/) { print $1, $2, $3, $4, $5, $6, $7, $8 }' boards.cfg`
+ if [ -z "$line" ] ; then
echo "make: *** No rule to make target \`$2_config'. Stop." >&2
exit 1
- }
+ fi
set ${line}
# add default board name if needed
case "$1" in
--) shift ; break ;;
-a) shift ; APPEND=yes ;;
- -n) shift ; BOARD_NAME="${1%_config}" ; shift ;;
+ -n) shift ; BOARD_NAME="${7%_config}" ; shift ;;
-t) shift ; TARGETS="`echo $1 | sed 's:_: :g'` ${TARGETS}" ; shift ;;
*) break ;;
esac
done
-[ $# -lt 4 ] && exit 1
-[ $# -gt 7 ] && exit 1
+[ $# -lt 7 ] && exit 1
+[ $# -gt 8 ] && exit 1
# Strip all options and/or _config suffixes
-CONFIG_NAME="${1%_config}"
+CONFIG_NAME="${7%_config}"
-[ "${BOARD_NAME}" ] || BOARD_NAME="${1%_config}"
+[ "${BOARD_NAME}" ] || BOARD_NAME="${7%_config}"
arch="$2"
cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $1}'`
spl_cpu=`echo $3 | awk 'BEGIN {FS = ":"} ; {print $2}'`
-if [ "$4" = "-" ] ; then
+if [ "$6" = "-" ] ; then
board=${BOARD_NAME}
else
- board="$4"
+ board="$6"
fi
-[ $# -gt 4 ] && [ "$5" != "-" ] && vendor="$5"
-[ $# -gt 5 ] && [ "$6" != "-" ] && soc="$6"
-[ $# -gt 6 ] && [ "$7" != "-" ] && {
+[ "$5" != "-" ] && vendor="$5"
+[ "$4" != "-" ] && soc="$4"
+[ $# -gt 7 ] && [ "$8" != "-" ] && {
# check if we have a board config name in the options field
# the options field mave have a board config name and a list
# of options, both separated by a colon (':'); the options are
# separated by commas (',').
#
# Check for board name
- tmp="${7%:*}"
+ tmp="${8%:*}"
if [ "$tmp" ] ; then
CONFIG_NAME="$tmp"
fi
# Check if we only have a colon...
- if [ "${tmp}" != "$7" ] ; then
- options=${7#*:}
+ if [ "${tmp}" != "$8" ] ; then
+ options=${8#*:}
TARGETS="`echo ${options} | sed 's:,: :g'` ${TARGETS}"
fi
}
static int NetTryCount;
+int __maybe_unused net_busy_flag;
+
/**********************************************************************/
static int on_bootfile(const char *name, const char *value, enum env_op op,
eth_init_state_only(bd);
restart:
+#ifdef CONFIG_USB_KEYBOARD
+ net_busy_flag = 0;
+#endif
net_set_state(NETLOOP_CONTINUE);
/*
status_led_set(STATUS_LED_RED, STATUS_LED_ON);
#endif /* CONFIG_SYS_FAULT_ECHO_LINK_DOWN, ... */
#endif /* CONFIG_MII, ... */
+#ifdef CONFIG_USB_KEYBOARD
+ net_busy_flag = 1;
+#endif
/*
* Main packet reception loop. Loop receiving packets until
}
done:
+#ifdef CONFIG_USB_KEYBOARD
+ net_busy_flag = 0;
+#endif
#ifdef CONFIG_CMD_TFTPPUT
/* Clear out the handlers */
net_set_udp_handler(NULL);
LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/net/phy/libphy.o
LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o
LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o
+LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/libwatchdog.o
ifneq ($(CONFIG_OMAP_COMMON),)
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
LIB = $(obj)libtest.o
COBJS-$(CONFIG_SANDBOX) += command_ut.o
+COBJS-$(CONFIG_SANDBOX) += compression.o
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * Copyright (c) 2013, The Chromium Authors
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define DEBUG
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+
+#include <u-boot/zlib.h>
+#include <bzlib.h>
+
+#include <lzma/LzmaTypes.h>
+#include <lzma/LzmaDec.h>
+#include <lzma/LzmaTools.h>
+
+#include <linux/lzo.h>
+
+static const char plain[] =
+ "I am a highly compressable bit of text.\n"
+ "I am a highly compressable bit of text.\n"
+ "I am a highly compressable bit of text.\n"
+ "There are many like me, but this one is mine.\n"
+ "If I were any shorter, there wouldn't be much sense in\n"
+ "compressing me in the first place. At least with lzo, anyway,\n"
+ "which appears to behave poorly in the face of short text\n"
+ "messages.\n";
+
+/* bzip2 -c /tmp/plain.txt > /tmp/plain.bz2 */
+static const char bzip2_compressed[] =
+ "\x42\x5a\x68\x39\x31\x41\x59\x26\x53\x59\xe5\x63\xdd\x09\x00\x00"
+ "\x28\x57\x80\x00\x10\x40\x85\x20\x20\x04\x00\x3f\xef\xdf\xf0\x30"
+ "\x00\xd6\xd0\x34\x91\x89\xa6\xf5\x4d\x19\x1a\x19\x0d\x02\x34\xd4"
+ "\xc9\x00\x34\x34\x00\x02\x48\x41\x35\x4f\xd4\xc6\x88\xd3\x50\x3d"
+ "\x4f\x51\x82\x4f\x88\xc3\x0d\x05\x62\x4f\x91\xa3\x52\x1b\xd0\x52"
+ "\x41\x4a\xa3\x98\xc2\x6b\xca\xa3\x82\xa5\xac\x8b\x15\x99\x68\xad"
+ "\xdf\x29\xd6\xf1\xf7\x5a\x10\xcd\x8c\x26\x61\x94\x95\xfe\x9e\x16"
+ "\x18\x28\x69\xd4\x23\x64\xcc\x2b\xe5\xe8\x5f\x00\xa4\x70\x26\x2c"
+ "\xee\xbd\x59\x6d\x6a\xec\xfc\x31\xda\x59\x0a\x14\x2a\x60\x1c\xf0"
+ "\x04\x86\x73\x9a\xc5\x5b\x87\x3f\x5b\x4c\x93\xe6\xb5\x35\x0d\xa6"
+ "\xb1\x2e\x62\x7b\xab\x67\xe7\x99\x2a\x14\x5e\x9f\x64\xcb\x96\xf4"
+ "\x0d\x65\xd4\x39\xe6\x8b\x7e\xea\x1c\x03\x69\x97\x83\x58\x91\x96"
+ "\xe1\xf0\x9d\xa4\x15\x8b\xb8\xc6\x93\xdc\x3d\xd9\x3c\x22\x55\xef"
+ "\xfb\xbb\x2a\xd3\x87\xa2\x8b\x04\xd9\x19\xf8\xe2\xfd\x4f\xdb\x1a"
+ "\x07\xc8\x60\xa3\x3f\xf8\xbb\x92\x29\xc2\x84\x87\x2b\x1e\xe8\x48";
+static const unsigned long bzip2_compressed_size = 240;
+
+/* lzma -z -c /tmp/plain.txt > /tmp/plain.lzma */
+static const char lzma_compressed[] =
+ "\x5d\x00\x00\x80\x00\xff\xff\xff\xff\xff\xff\xff\xff\x00\x24\x88"
+ "\x08\x26\xd8\x41\xff\x99\xc8\xcf\x66\x3d\x80\xac\xba\x17\xf1\xc8"
+ "\xb9\xdf\x49\x37\xb1\x68\xa0\x2a\xdd\x63\xd1\xa7\xa3\x66\xf8\x15"
+ "\xef\xa6\x67\x8a\x14\x18\x80\xcb\xc7\xb1\xcb\x84\x6a\xb2\x51\x16"
+ "\xa1\x45\xa0\xd6\x3e\x55\x44\x8a\x5c\xa0\x7c\xe5\xa8\xbd\x04\x57"
+ "\x8f\x24\xfd\xb9\x34\x50\x83\x2f\xf3\x46\x3e\xb9\xb0\x00\x1a\xf5"
+ "\xd3\x86\x7e\x8f\x77\xd1\x5d\x0e\x7c\xe1\xac\xde\xf8\x65\x1f\x4d"
+ "\xce\x7f\xa7\x3d\xaa\xcf\x26\xa7\x58\x69\x1e\x4c\xea\x68\x8a\xe5"
+ "\x89\xd1\xdc\x4d\xc7\xe0\x07\x42\xbf\x0c\x9d\x06\xd7\x51\xa2\x0b"
+ "\x7c\x83\x35\xe1\x85\xdf\xee\xfb\xa3\xee\x2f\x47\x5f\x8b\x70\x2b"
+ "\xe1\x37\xf3\x16\xf6\x27\x54\x8a\x33\x72\x49\xea\x53\x7d\x60\x0b"
+ "\x21\x90\x66\xe7\x9e\x56\x61\x5d\xd8\xdc\x59\xf0\xac\x2f\xd6\x49"
+ "\x6b\x85\x40\x08\x1f\xdf\x26\x25\x3b\x72\x44\xb0\xb8\x21\x2f\xb3"
+ "\xd7\x9b\x24\x30\x78\x26\x44\x07\xc3\x33\xd1\x4d\x03\x1b\xe1\xff"
+ "\xfd\xf5\x50\x8d\xca";
+static const unsigned long lzma_compressed_size = 229;
+
+/* lzop -c /tmp/plain.txt > /tmp/plain.lzo */
+static const char lzo_compressed[] =
+ "\x89\x4c\x5a\x4f\x00\x0d\x0a\x1a\x0a\x10\x30\x20\x60\x09\x40\x01"
+ "\x05\x03\x00\x00\x09\x00\x00\x81\xb4\x52\x09\x54\xf1\x00\x00\x00"
+ "\x00\x09\x70\x6c\x61\x69\x6e\x2e\x74\x78\x74\x65\xb1\x07\x9c\x00"
+ "\x00\x01\x5e\x00\x00\x01\x0f\xc3\xc7\x7a\xe0\x00\x16\x49\x20\x61"
+ "\x6d\x20\x61\x20\x68\x69\x67\x68\x6c\x79\x20\x63\x6f\x6d\x70\x72"
+ "\x65\x73\x73\x61\x62\x6c\x65\x20\x62\x69\x74\x20\x6f\x66\x20\x74"
+ "\x65\x78\x74\x2e\x0a\x20\x2f\x9c\x00\x00\x22\x54\x68\x65\x72\x65"
+ "\x20\x61\x72\x65\x20\x6d\x61\x6e\x79\x20\x6c\x69\x6b\x65\x20\x6d"
+ "\x65\x2c\x20\x62\x75\x74\x20\x74\x68\x69\x73\x20\x6f\x6e\x65\x20"
+ "\x69\x73\x20\x6d\x69\x6e\x65\x2e\x0a\x49\x66\x20\x49\x20\x77\x84"
+ "\x06\x0a\x6e\x79\x20\x73\x68\x6f\x72\x74\x65\x72\x2c\x20\x74\x90"
+ "\x08\x00\x08\x77\x6f\x75\x6c\x64\x6e\x27\x74\x20\x62\x65\x20\x6d"
+ "\x75\x63\x68\x20\x73\x65\x6e\x73\x65\x20\x69\x6e\x0a\xf8\x19\x02"
+ "\x69\x6e\x67\x20\x6d\x64\x02\x64\x06\x00\x5a\x20\x66\x69\x72\x73"
+ "\x74\x20\x70\x6c\x61\x63\x65\x2e\x20\x41\x74\x20\x6c\x65\x61\x73"
+ "\x74\x20\x77\x69\x74\x68\x20\x6c\x7a\x6f\x2c\x20\x61\x6e\x79\x77"
+ "\x61\x79\x2c\x0a\x77\x68\x69\x63\x68\x20\x61\x70\x70\x65\x61\x72"
+ "\x73\x20\x74\x6f\x20\x62\x65\x68\x61\x76\x65\x20\x70\x6f\x6f\x72"
+ "\x6c\x79\x20\x69\x6e\x20\x74\x68\x65\x20\x66\x61\x63\x65\x20\x6f"
+ "\x66\x20\x73\x68\x6f\x72\x74\x20\x74\x65\x78\x74\x0a\x6d\x65\x73"
+ "\x73\x61\x67\x65\x73\x2e\x0a\x11\x00\x00\x00\x00\x00\x00";
+static const unsigned long lzo_compressed_size = 334;
+
+
+#define TEST_BUFFER_SIZE 512
+
+typedef int (*mutate_func)(void *, unsigned long, void *, unsigned long,
+ unsigned long *);
+
+static int compress_using_gzip(void *in, unsigned long in_size,
+ void *out, unsigned long out_max,
+ unsigned long *out_size)
+{
+ int ret;
+ unsigned long inout_size = out_max;
+
+ ret = gzip(out, &inout_size, in, in_size);
+ if (out_size)
+ *out_size = inout_size;
+
+ return ret;
+}
+
+static int uncompress_using_gzip(void *in, unsigned long in_size,
+ void *out, unsigned long out_max,
+ unsigned long *out_size)
+{
+ int ret;
+ unsigned long inout_size = in_size;
+
+ ret = gunzip(out, out_max, in, &inout_size);
+ if (out_size)
+ *out_size = inout_size;
+
+ return ret;
+}
+
+static int compress_using_bzip2(void *in, unsigned long in_size,
+ void *out, unsigned long out_max,
+ unsigned long *out_size)
+{
+ /* There is no bzip2 compression in u-boot, so fake it. */
+ assert(in_size == strlen(plain));
+ assert(memcmp(plain, in, in_size) == 0);
+
+ if (bzip2_compressed_size > out_max)
+ return -1;
+
+ memcpy(out, bzip2_compressed, bzip2_compressed_size);
+ if (out_size)
+ *out_size = bzip2_compressed_size;
+
+ return 0;
+}
+
+static int uncompress_using_bzip2(void *in, unsigned long in_size,
+ void *out, unsigned long out_max,
+ unsigned long *out_size)
+{
+ int ret;
+ unsigned int inout_size = out_max;
+
+ ret = BZ2_bzBuffToBuffDecompress(out, &inout_size, in, in_size,
+ CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0);
+ if (out_size)
+ *out_size = inout_size;
+
+ return (ret != BZ_OK);
+}
+
+static int compress_using_lzma(void *in, unsigned long in_size,
+ void *out, unsigned long out_max,
+ unsigned long *out_size)
+{
+ /* There is no lzma compression in u-boot, so fake it. */
+ assert(in_size == strlen(plain));
+ assert(memcmp(plain, in, in_size) == 0);
+
+ if (lzma_compressed_size > out_max)
+ return -1;
+
+ memcpy(out, lzma_compressed, lzma_compressed_size);
+ if (out_size)
+ *out_size = lzma_compressed_size;
+
+ return 0;
+}
+
+static int uncompress_using_lzma(void *in, unsigned long in_size,
+ void *out, unsigned long out_max,
+ unsigned long *out_size)
+{
+ int ret;
+ SizeT inout_size = out_max;
+
+ ret = lzmaBuffToBuffDecompress(out, &inout_size, in, in_size);
+ if (out_size)
+ *out_size = inout_size;
+
+ return (ret != SZ_OK);
+}
+
+static int compress_using_lzo(void *in, unsigned long in_size,
+ void *out, unsigned long out_max,
+ unsigned long *out_size)
+{
+ /* There is no lzo compression in u-boot, so fake it. */
+ assert(in_size == strlen(plain));
+ assert(memcmp(plain, in, in_size) == 0);
+
+ if (lzo_compressed_size > out_max)
+ return -1;
+
+ memcpy(out, lzo_compressed, lzo_compressed_size);
+ if (out_size)
+ *out_size = lzo_compressed_size;
+
+ return 0;
+}
+
+static int uncompress_using_lzo(void *in, unsigned long in_size,
+ void *out, unsigned long out_max,
+ unsigned long *out_size)
+{
+ int ret;
+ size_t input_size = in_size;
+ size_t output_size = out_max;
+
+ ret = lzop_decompress(in, input_size, out, &output_size);
+ if (out_size)
+ *out_size = output_size;
+
+ return (ret != LZO_E_OK);
+}
+
+#define errcheck(statement) if (!(statement)) { \
+ fprintf(stderr, "\tFailed: %s\n", #statement); \
+ ret = 1; \
+ goto out; \
+}
+
+static int run_test(char *name, mutate_func compress, mutate_func uncompress)
+{
+ ulong orig_size, compressed_size, uncompressed_size;
+ void *orig_buf;
+ void *compressed_buf = NULL;
+ void *uncompressed_buf = NULL;
+ void *compare_buf = NULL;
+ int ret;
+
+ printf(" testing %s ...\n", name);
+
+ orig_buf = (void *)plain;
+ orig_size = strlen(orig_buf); /* Trailing NULL not included. */
+ errcheck(orig_size > 0);
+
+ compressed_size = uncompressed_size = TEST_BUFFER_SIZE;
+ compressed_buf = malloc(compressed_size);
+ errcheck(compressed_buf != NULL);
+ uncompressed_buf = malloc(uncompressed_size);
+ errcheck(uncompressed_buf != NULL);
+ compare_buf = malloc(uncompressed_size);
+ errcheck(compare_buf != NULL);
+
+ /* Compress works as expected. */
+ printf("\torig_size:%lu\n", orig_size);
+ memset(compressed_buf, 'A', TEST_BUFFER_SIZE);
+ errcheck(compress(orig_buf, orig_size,
+ compressed_buf, compressed_size,
+ &compressed_size) == 0);
+ printf("\tcompressed_size:%lu\n", compressed_size);
+ errcheck(compressed_size > 0);
+ errcheck(compressed_size < orig_size);
+ errcheck(((char *)compressed_buf)[compressed_size-1] != 'A');
+ errcheck(((char *)compressed_buf)[compressed_size] == 'A');
+
+ /* Uncompresses with space remaining. */
+ errcheck(uncompress(compressed_buf, compressed_size,
+ uncompressed_buf, uncompressed_size,
+ &uncompressed_size) == 0);
+ printf("\tuncompressed_size:%lu\n", uncompressed_size);
+ errcheck(uncompressed_size == orig_size);
+ errcheck(memcmp(orig_buf, uncompressed_buf, orig_size) == 0);
+
+ /* Uncompresses with exactly the right size output buffer. */
+ memset(uncompressed_buf, 'A', TEST_BUFFER_SIZE);
+ errcheck(uncompress(compressed_buf, compressed_size,
+ uncompressed_buf, orig_size,
+ &uncompressed_size) == 0);
+ errcheck(uncompressed_size == orig_size);
+ errcheck(memcmp(orig_buf, uncompressed_buf, orig_size) == 0);
+ errcheck(((char *)uncompressed_buf)[orig_size] == 'A');
+
+ /* Make sure compression does not over-run. */
+ memset(compare_buf, 'A', TEST_BUFFER_SIZE);
+ ret = compress(orig_buf, orig_size,
+ compare_buf, compressed_size - 1,
+ NULL);
+ errcheck(((char *)compare_buf)[compressed_size] == 'A');
+ errcheck(ret != 0);
+ printf("\tcompress does not overrun\n");
+
+ /* Make sure decompression does not over-run. */
+ memset(compare_buf, 'A', TEST_BUFFER_SIZE);
+ ret = uncompress(compressed_buf, compressed_size,
+ compare_buf, uncompressed_size - 1,
+ NULL);
+ errcheck(((char *)compare_buf)[uncompressed_size - 1] == 'A');
+ errcheck(ret != 0);
+ printf("\tuncompress does not overrun\n");
+
+ /* Got here, everything is fine. */
+ ret = 0;
+
+out:
+ printf(" %s: %s\n", name, ret == 0 ? "ok" : "FAILED");
+
+ free(compare_buf);
+ free(uncompressed_buf);
+ free(compressed_buf);
+
+ return ret;
+}
+
+
+static int do_test_compression(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int err = 0;
+
+ err += run_test("gzip", compress_using_gzip, uncompress_using_gzip);
+ err += run_test("bzip2", compress_using_bzip2, uncompress_using_bzip2);
+ err += run_test("lzma", compress_using_lzma, uncompress_using_lzma);
+ err += run_test("lzo", compress_using_lzo, uncompress_using_lzo);
+
+ printf("test_compression %s\n", err == 0 ? "ok" : "FAILED");
+
+ return err;
+}
+
+U_BOOT_CMD(
+ test_compression, 5, 1, do_test_compression,
+ "Basic test of compressors: gzip bzip2 lzma lzo", ""
+);
BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
BIN_FILES-y += mkenvimage$(SFX)
BIN_FILES-y += mkimage$(SFX)
-BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX)
+BIN_FILES-$(CONFIG_EXYNOS5250) += mk$(BOARD)spl$(SFX)
BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX)
BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
EXT_OBJ_FILES-y += lib/sha1.o
# Source files located in the tools directory
-OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
-OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o
+NOPED_OBJ_FILES-y += aisimage.o
NOPED_OBJ_FILES-y += default_image.o
-NOPED_OBJ_FILES-y += proftool.o
-OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o
NOPED_OBJ_FILES-y += fit_image.o
-OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
-OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
-OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o
-NOPED_OBJ_FILES-y += aisimage.o
-NOPED_OBJ_FILES-y += kwbimage.o
-NOPED_OBJ_FILES-y += pblimage.o
-NOPED_OBJ_FILES-y += imximage.o
NOPED_OBJ_FILES-y += image-host.o
-NOPED_OBJ_FILES-y += omapimage.o
+NOPED_OBJ_FILES-y += imximage.o
+NOPED_OBJ_FILES-y += kwbimage.o
NOPED_OBJ_FILES-y += mkenvimage.o
NOPED_OBJ_FILES-y += mkimage.o
-OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o
+NOPED_OBJ_FILES-y += mxsimage.o
+NOPED_OBJ_FILES-y += omapimage.o
+NOPED_OBJ_FILES-y += os_support.o
+NOPED_OBJ_FILES-y += pblimage.o
+NOPED_OBJ_FILES-y += proftool.o
+NOPED_OBJ_FILES-y += ublimage.o
+OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o
+OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
+OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
+OBJ_FILES-$(CONFIG_EXYNOS5250) += mkexynosspl.o
+OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
+OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
OBJ_FILES-$(CONFIG_MX23) += mxsboot.o
OBJ_FILES-$(CONFIG_MX28) += mxsboot.o
OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
-NOPED_OBJ_FILES-y += os_support.o
OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
-NOPED_OBJ_FILES-y += ublimage.o
-OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
+OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o
+OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o
+OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o
# Don't build by default
#ifeq ($(ARCH),ppc)
$(HOSTSTRIP) $@
$(obj)mkimage$(SFX): $(obj)aisimage.o \
+ $(FIT_SIG_OBJS) \
$(obj)crc32.o \
$(obj)default_image.o \
$(obj)fit_image.o \
$(obj)image-fit.o \
- $(obj)image.o \
$(obj)image-host.o \
- $(FIT_SIG_OBJS) \
+ $(obj)image.o \
$(obj)imximage.o \
$(obj)kwbimage.o \
- $(obj)pblimage.o \
$(obj)md5.o \
$(obj)mkimage.o \
- $(obj)os_support.o \
+ $(obj)mxsimage.o \
$(obj)omapimage.o \
+ $(obj)os_support.o \
+ $(obj)pblimage.o \
$(obj)sha1.o \
$(obj)ublimage.o \
$(LIBFDT_OBJS) \
for upto in range(len(fields)):
if fields[upto] == '-':
fields[upto] = ''
- while len(fields) < 7:
+ while len(fields) < 9:
fields.append('')
board = Board(*fields)
MEMGETBADBLOCK needs 64 bits */
int rc;
- blocklen = DEVESIZE (dev);
+ /*
+ * For mtd devices only offset and size of the environment do matter
+ */
+ if (mtd_type == MTD_ABSENT) {
+ blocklen = count;
+ top_of_range = offset + count;
+ erase_len = blocklen;
+ blockstart = offset;
+ block_seek = 0;
+ write_total = blocklen;
+ } else {
+ blocklen = DEVESIZE(dev);
- top_of_range = ((DEVOFFSET(dev) / blocklen) +
- ENVSECTORS (dev)) * blocklen;
+ top_of_range = ((DEVOFFSET(dev) / blocklen) +
+ ENVSECTORS(dev)) * blocklen;
- erase_offset = (offset / blocklen) * blocklen;
+ erase_offset = (offset / blocklen) * blocklen;
- /* Maximum area we may use */
- erase_len = top_of_range - erase_offset;
+ /* Maximum area we may use */
+ erase_len = top_of_range - erase_offset;
- blockstart = erase_offset;
- /* Offset inside a block */
- block_seek = offset - erase_offset;
+ blockstart = erase_offset;
+ /* Offset inside a block */
+ block_seek = offset - erase_offset;
- /*
- * Data size we actually have to write: from the start of the block
- * to the start of the data, then count bytes of data, and to the
- * end of the block
- */
- write_total = ((block_seek + count + blocklen - 1) /
- blocklen) * blocklen;
+ /*
+ * Data size we actually write: from the start of the block
+ * to the start of the data, then count bytes of data, and
+ * to the end of the block
+ */
+ write_total = ((block_seek + count + blocklen - 1) /
+ blocklen) * blocklen;
+ }
/*
* Support data anywhere within erase sectors: read out the complete
continue;
}
- erase.start = blockstart;
- ioctl (fd, MEMUNLOCK, &erase);
- /* These do not need an explicit erase cycle */
- if (mtd_type != MTD_ABSENT &&
- mtd_type != MTD_DATAFLASH)
- if (ioctl (fd, MEMERASE, &erase) != 0) {
- fprintf (stderr, "MTD erase error on %s: %s\n",
- DEVNAME (dev),
- strerror (errno));
- return -1;
- }
+ if (mtd_type != MTD_ABSENT) {
+ erase.start = blockstart;
+ ioctl(fd, MEMUNLOCK, &erase);
+ /* These do not need an explicit erase cycle */
+ if (mtd_type != MTD_DATAFLASH)
+ if (ioctl(fd, MEMERASE, &erase) != 0) {
+ fprintf(stderr,
+ "MTD erase error on %s: %s\n",
+ DEVNAME(dev), strerror(errno));
+ return -1;
+ }
+ }
if (lseek (fd, blockstart, SEEK_SET) == -1) {
fprintf (stderr,
return -1;
}
- ioctl (fd, MEMLOCK, &erase);
+ if (mtd_type != MTD_ABSENT)
+ ioctl(fd, MEMLOCK, &erase);
processed += blocklen;
block_seek = 0;
} else if (DEVTYPE(dev_current) == MTD_UBIVOLUME &&
DEVTYPE(!dev_current) == MTD_UBIVOLUME) {
environment.flag_scheme = FLAG_INCREMENTAL;
+ } else if (DEVTYPE(dev_current) == MTD_ABSENT &&
+ DEVTYPE(!dev_current) == MTD_ABSENT) {
+ environment.flag_scheme = FLAG_INCREMENTAL;
} else {
fprintf (stderr, "Incompatible flash types!\n");
return -1;
#include <image.h>
#include "imximage.h"
+#define UNDEFINED 0xFFFFFFFF
+
/*
* Supported commands for configuration file
*/
{CMD_BOOT_FROM, "BOOT_FROM", "boot command", },
{CMD_BOOT_OFFSET, "BOOT_OFFSET", "Boot offset", },
{CMD_DATA, "DATA", "Reg Write Data", },
+ {CMD_CSF, "CSF", "Command Sequence File", },
{CMD_IMAGE_VERSION, "IMAGE_VERSION", "image version", },
{-1, "", "", },
};
* Supported Boot options for configuration file
* this is needed to set the correct flash offset
*/
-static table_entry_t imximage_bootops[] = {
+static table_entry_t imximage_boot_offset[] = {
{FLASH_OFFSET_ONENAND, "onenand", "OneNAND Flash",},
{FLASH_OFFSET_NAND, "nand", "NAND Flash", },
{FLASH_OFFSET_NOR, "nor", "NOR Flash", },
{-1, "", "Invalid", },
};
+/*
+ * Supported Boot options for configuration file
+ * this is needed to determine the initial load size
+ */
+static table_entry_t imximage_boot_loadsize[] = {
+ {FLASH_LOADSIZE_ONENAND, "onenand", "OneNAND Flash",},
+ {FLASH_LOADSIZE_NAND, "nand", "NAND Flash", },
+ {FLASH_LOADSIZE_NOR, "nor", "NOR Flash", },
+ {FLASH_LOADSIZE_SATA, "sata", "SATA Disk", },
+ {FLASH_LOADSIZE_SD, "sd", "SD Card", },
+ {FLASH_LOADSIZE_SPI, "spi", "SPI Flash", },
+ {-1, "", "Invalid", },
+};
+
/*
* IMXIMAGE version definition for i.MX chips
*/
static struct imx_header imximage_header;
static uint32_t imximage_version;
+/*
+ * Image Vector Table Offset
+ * Initialized to a wrong not 4-bytes aligned address to
+ * check if it is was set by the cfg file.
+ */
+static uint32_t imximage_ivt_offset = UNDEFINED;
+static uint32_t imximage_csf_size = UNDEFINED;
+/* Initial Load Region Size */
+static uint32_t imximage_init_loadsize;
static set_dcd_val_t set_dcd_val;
static set_dcd_rst_t set_dcd_rst;
static set_imx_hdr_t set_imx_hdr;
static uint32_t max_dcd_entries;
static uint32_t *header_size_ptr;
+static uint32_t *csf_ptr;
static uint32_t get_cfg_value(char *token, char *name, int linenr)
{
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
- hdr_base = entry_point - sizeof(struct imx_header);
+ /* TODO: check i.MX image V1 handling, for now use 'old' style */
+ hdr_base = entry_point - 4096;
fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
fhdr_v1->app_code_jump_vector = entry_point;
fhdr_v2->entry = entry_point;
fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
- fhdr_v2->self = hdr_base = entry_point - sizeof(struct imx_header);
-
+ hdr_base = entry_point - imximage_init_loadsize +
+ flash_offset;
+ fhdr_v2->self = hdr_base;
fhdr_v2->dcd_ptr = hdr_base + offsetof(imx_header_v2_t, dcd_table);
fhdr_v2->boot_data_ptr = hdr_base
+ offsetof(imx_header_v2_t, boot_data);
- hdr_v2->boot_data.start = hdr_base - flash_offset;
+ hdr_v2->boot_data.start = entry_point - imximage_init_loadsize;
- /* Security feature are not supported */
fhdr_v2->csf = 0;
+
header_size_ptr = &hdr_v2->boot_data.size;
+ csf_ptr = &fhdr_v2->csf;
}
static void set_hdr_func(struct imx_header *imxhdr)
genimg_print_size(hdr_v2->boot_data.size);
printf("Load Address: %08x\n", (uint32_t)fhdr_v2->boot_data_ptr);
printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
+ if (fhdr_v2->csf && (imximage_ivt_offset != UNDEFINED) &&
+ (imximage_csf_size != UNDEFINED)) {
+ printf("HAB Blocks: %08x %08x %08x\n",
+ (uint32_t)fhdr_v2->self, 0,
+ hdr_v2->boot_data.size - imximage_ivt_offset -
+ imximage_csf_size);
+ }
}
static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
set_hdr_func(imxhdr);
break;
case CMD_BOOT_FROM:
- imxhdr->flash_offset = get_table_entry_id(imximage_bootops,
+ imximage_ivt_offset = get_table_entry_id(imximage_boot_offset,
"imximage boot option", token);
- if (imxhdr->flash_offset == -1) {
+ if (imximage_ivt_offset == -1) {
fprintf(stderr, "Error: %s[%d] -Invalid boot device"
"(%s)\n", name, lineno, token);
exit(EXIT_FAILURE);
}
+
+ imximage_init_loadsize =
+ get_table_entry_id(imximage_boot_loadsize,
+ "imximage boot option", token);
+
+ if (imximage_init_loadsize == -1) {
+ fprintf(stderr,
+ "Error: %s[%d] -Invalid boot device(%s)\n",
+ name, lineno, token);
+ exit(EXIT_FAILURE);
+ }
+
+ /*
+ * The SOC loads from the storage starting at address 0
+ * then ensures that the load size contains the offset
+ */
+ if (imximage_init_loadsize < imximage_ivt_offset)
+ imximage_init_loadsize = imximage_ivt_offset;
if (unlikely(cmd_ver_first != 1))
cmd_ver_first = 0;
break;
case CMD_BOOT_OFFSET:
- imxhdr->flash_offset = get_cfg_value(token, name, lineno);
+ imximage_ivt_offset = get_cfg_value(token, name, lineno);
if (unlikely(cmd_ver_first != 1))
cmd_ver_first = 0;
break;
if (unlikely(cmd_ver_first != 1))
cmd_ver_first = 0;
break;
+ case CMD_CSF:
+ if (imximage_version != 2) {
+ fprintf(stderr,
+ "Error: %s[%d] - CSF only supported for VERSION 2(%s)\n",
+ name, lineno, token);
+ exit(EXIT_FAILURE);
+ }
+ imximage_csf_size = get_cfg_value(token, name, lineno);
+ if (unlikely(cmd_ver_first != 1))
+ cmd_ver_first = 0;
+ break;
}
}
exit(EXIT_FAILURE);
}
- /* Very simple parsing, line starting with # are comments
+ /*
+ * Very simple parsing, line starting with # are comments
* and are dropped
*/
while ((getline(&line, &len, fd)) > 0) {
fclose(fd);
/* Exit if there is no BOOT_FROM field specifying the flash_offset */
- if (imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
+ if (imximage_ivt_offset == FLASH_OFFSET_UNDEFINED) {
fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);
exit(EXIT_FAILURE);
}
*/
imximage_version = IMXIMAGE_V1;
/* Be able to detect if the cfg file has no BOOT_FROM tag */
- imxhdr->flash_offset = FLASH_OFFSET_UNDEFINED;
+ imximage_ivt_offset = FLASH_OFFSET_UNDEFINED;
+ imximage_csf_size = 0;
set_hdr_func(imxhdr);
/* Parse dcd configuration file */
dcd_len = parse_cfg_file(imxhdr, params->imagename);
/* Set the imx header */
- (*set_imx_hdr)(imxhdr, dcd_len, params->ep, imxhdr->flash_offset);
+ (*set_imx_hdr)(imxhdr, dcd_len, params->ep, imximage_ivt_offset);
/*
* ROM bug alert
*
* The remaining fraction of a block bytes would not be loaded!
*/
- *header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 4096);
+ *header_size_ptr = ROUND(sbuf->st_size, 4096);
+
+ if (csf_ptr && imximage_csf_size) {
+ *csf_ptr = params->ep - imximage_init_loadsize +
+ *header_size_ptr;
+ *header_size_ptr += imximage_csf_size;
+ }
}
int imximage_check_params(struct mkimage_params *params)
(params->xflag) || !(strlen(params->imagename));
}
+static int imximage_generate(struct mkimage_params *params,
+ struct image_type_params *tparams)
+{
+ struct imx_header *imxhdr;
+ size_t alloc_len;
+ struct stat sbuf;
+ char *datafile = params->datafile;
+ uint32_t pad_len;
+
+ memset(&imximage_header, 0, sizeof(imximage_header));
+
+ /*
+ * In order to not change the old imx cfg file
+ * by adding VERSION command into it, here need
+ * set up function ptr group to V1 by default.
+ */
+ imximage_version = IMXIMAGE_V1;
+ /* Be able to detect if the cfg file has no BOOT_FROM tag */
+ imximage_ivt_offset = FLASH_OFFSET_UNDEFINED;
+ imximage_csf_size = 0;
+ set_hdr_func(imxhdr);
+
+ /* Parse dcd configuration file */
+ parse_cfg_file(&imximage_header, params->imagename);
+
+ /* TODO: check i.MX image V1 handling, for now use 'old' style */
+ if (imximage_version == IMXIMAGE_V1) {
+ alloc_len = 4096;
+ } else {
+ if (imximage_init_loadsize < imximage_ivt_offset +
+ sizeof(imx_header_v2_t))
+ imximage_init_loadsize = imximage_ivt_offset +
+ sizeof(imx_header_v2_t);
+ alloc_len = imximage_init_loadsize - imximage_ivt_offset;
+ }
+
+ if (alloc_len < sizeof(struct imx_header)) {
+ fprintf(stderr, "%s: header error\n",
+ params->cmdname);
+ exit(EXIT_FAILURE);
+ }
+
+ imxhdr = malloc(alloc_len);
+
+ if (!imxhdr) {
+ fprintf(stderr, "%s: malloc return failure: %s\n",
+ params->cmdname, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ memset(imxhdr, 0, alloc_len);
+
+ tparams->header_size = alloc_len;
+ tparams->hdr = imxhdr;
+
+ /* determine data image file length */
+
+ if (stat(datafile, &sbuf) < 0) {
+ fprintf(stderr, "%s: Can't stat %s: %s\n",
+ params->cmdname, datafile, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ pad_len = ROUND(sbuf.st_size, 4096) - sbuf.st_size;
+
+ /* TODO: check i.MX image V1 handling, for now use 'old' style */
+ if (imximage_version == IMXIMAGE_V1)
+ return 0;
+ else
+ return pad_len;
+}
+
+
/*
* imximage parameters
*/
static struct image_type_params imximage_params = {
.name = "Freescale i.MX Boot Image support",
- .header_size = sizeof(struct imx_header),
- .hdr = (void *)&imximage_header,
+ .header_size = 0,
+ .hdr = NULL,
.check_image_type = imximage_check_image_types,
.verify_header = imximage_verify_header,
.print_header = imximage_print_header,
.set_header = imximage_set_header,
.check_params = imximage_check_params,
+ .vrec_header = imximage_generate,
};
void init_imx_image_type(void)
#define APP_CODE_BARKER 0xB1
#define DCD_BARKER 0xB17219E9
-#define HEADER_OFFSET 0x400
-
/*
* NOTE: This file must be kept in sync with arch/arm/include/asm/\
* imx-common/imximage.cfg because tools/imximage.c can not
* cross-include headers from arch/arm/ and vice-versa.
*/
#define CMD_DATA_STR "DATA"
+
+/* Initial Vector Table Offset */
#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
#define FLASH_OFFSET_STANDARD 0x400
#define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
#define FLASH_OFFSET_NOR 0x1000
#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
+/* Initial Load Region Size */
+#define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
+#define FLASH_LOADSIZE_STANDARD 0x1000
+#define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD
+#define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD
+#define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD
+#define FLASH_LOADSIZE_ONENAND 0x400
+#define FLASH_LOADSIZE_NOR 0x0 /* entire image */
+#define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD
+
#define IVT_HEADER_TAG 0xD1
#define IVT_VERSION 0x40
#define DCD_HEADER_TAG 0xD2
CMD_IMAGE_VERSION,
CMD_BOOT_FROM,
CMD_BOOT_OFFSET,
- CMD_DATA
+ CMD_DATA,
+ CMD_CSF,
};
enum imximage_fld_types {
imx_header_v1_t hdr_v1;
imx_header_v2_t hdr_v2;
} header;
- uint32_t flash_offset;
-} __attribute__((aligned(4096)));
+};
typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
char *name, int lineno,
char *ptr;
int retval = 0;
struct image_type_params *tparams = NULL;
+ int pad_len = 0;
/* Init Freescale PBL Boot image generation/list support */
init_pbl_image_type();
init_kwb_image_type ();
/* Init Freescale imx Boot image generation/list support */
init_imx_image_type ();
+ /* Init Freescale mxs Boot image generation/list support */
+ init_mxs_image_type();
/* Init FIT image generation/list support */
init_fit_image_type ();
/* Init TI OMAP Boot image generation/list support */
* allocate memory for the header itself.
*/
if (tparams->vrec_header)
- tparams->vrec_header(¶ms, tparams);
+ pad_len = tparams->vrec_header(¶ms, tparams);
else
memset(tparams->hdr, 0, tparams->header_size);
/* PBL has special Image format, implements its' own */
pbl_load_uboot(ifd, ¶ms);
} else {
- copy_file (ifd, params.datafile, 0);
+ copy_file(ifd, params.datafile, pad_len);
}
}
unsigned char *ptr;
int tail;
int zero = 0;
+ uint8_t zeros[4096];
int offset = 0;
int size;
struct image_type_params *tparams = mkimage_get_type (params.type);
+ if (pad >= sizeof(zeros)) {
+ fprintf(stderr, "%s: Can't pad to %d\n",
+ params.cmdname, pad);
+ exit(EXIT_FAILURE);
+ }
+
+ memset(zeros, 0, sizeof(zeros));
+
if (params.vflag) {
fprintf (stderr, "Adding Image %s\n", datafile);
}
exit (EXIT_FAILURE);
}
- if (pad && ((tail = size % 4) != 0)) {
+ tail = size % 4;
+ if ((pad == 1) && (tail != 0)) {
if (write(ifd, (char *)&zero, 4-tail) != 4-tail) {
fprintf (stderr, "%s: Write error on %s: %s\n",
strerror(errno));
exit (EXIT_FAILURE);
}
+ } else if (pad > 1) {
+ if (write(ifd, (char *)&zeros, pad) != pad) {
+ fprintf(stderr, "%s: Write error on %s: %s\n",
+ params.cmdname, params.imagefile,
+ strerror(errno));
+ exit(EXIT_FAILURE);
+ }
}
(void) munmap((void *)ptr, sbuf.st_size);
/*
* This callback function will be executed for variable size record
* It is expected to build this header in memory and return its length
- * and a pointer to it
+ * and a pointer to it by using image_type_params.header_size and
+ * image_type_params.hdr. The return value shall indicate if an
+ * additional padding should be used when copying the data image
+ * by returning the padding length.
*/
int (*vrec_header) (struct mkimage_params *,
struct image_type_params *);
void init_ais_image_type(void);
void init_kwb_image_type (void);
void init_imx_image_type (void);
+void init_mxs_image_type(void);
void init_default_image_type (void);
void init_fit_image_type (void);
void init_ubl_image_type(void);
*
* TWEAK this if you have different kind of NAND chip.
*/
-uint32_t nand_writesize = 2048;
-uint32_t nand_oobsize = 64;
-uint32_t nand_erasesize = 128 * 1024;
+static uint32_t nand_writesize = 2048;
+static uint32_t nand_oobsize = 64;
+static uint32_t nand_erasesize = 128 * 1024;
/*
* Sector on which the SigmaTel boot partition (0x53) starts.
*/
-uint32_t sd_sector = 2048;
+static uint32_t sd_sector = 2048;
/*
* Each of the U-Boot bootstreams is at maximum 1MB big.
return 0;
}
-void usage(void)
+static void usage(void)
{
printf(
"Usage: mxsboot [ops] <type> <infile> <outfile>\n"
return ret;
}
-int parse_ops(int argc, char **argv)
+static int parse_ops(int argc, char **argv)
{
int i;
int tmp;
--- /dev/null
+/*
+ * Freescale i.MX23/i.MX28 SB image generator
+ *
+ * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifdef CONFIG_MXS
+
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <limits.h>
+
+#include <openssl/evp.h>
+
+#include "mkimage.h"
+#include "mxsimage.h"
+#include <image.h>
+
+
+/*
+ * DCD block
+ * |-Write to address command block
+ * | 0xf00 == 0xf33d
+ * | 0xba2 == 0xb33f
+ * |-ORR address with mask command block
+ * | 0xf00 |= 0x1337
+ * |-Write to address command block
+ * | 0xba2 == 0xd00d
+ * :
+ */
+#define SB_HAB_DCD_WRITE 0xccUL
+#define SB_HAB_DCD_CHECK 0xcfUL
+#define SB_HAB_DCD_NOOP 0xc0UL
+#define SB_HAB_DCD_MASK_BIT (1 << 3)
+#define SB_HAB_DCD_SET_BIT (1 << 4)
+
+/* Addr.n = Value.n */
+#define SB_DCD_WRITE \
+ (SB_HAB_DCD_WRITE << 24)
+/* Addr.n &= ~Value.n */
+#define SB_DCD_ANDC \
+ ((SB_HAB_DCD_WRITE << 24) | SB_HAB_DCD_SET_BIT)
+/* Addr.n |= Value.n */
+#define SB_DCD_ORR \
+ ((SB_HAB_DCD_WRITE << 24) | SB_HAB_DCD_SET_BIT | SB_HAB_DCD_MASK_BIT)
+/* (Addr.n & Value.n) == 0 */
+#define SB_DCD_CHK_EQZ \
+ (SB_HAB_DCD_CHECK << 24)
+/* (Addr.n & Value.n) == Value.n */
+#define SB_DCD_CHK_EQ \
+ ((SB_HAB_DCD_CHECK << 24) | SB_HAB_DCD_SET_BIT)
+/* (Addr.n & Value.n) != Value.n */
+#define SB_DCD_CHK_NEQ \
+ ((SB_HAB_DCD_CHECK << 24) | SB_HAB_DCD_MASK_BIT)
+/* (Addr.n & Value.n) != 0 */
+#define SB_DCD_CHK_NEZ \
+ ((SB_HAB_DCD_CHECK << 24) | SB_HAB_DCD_SET_BIT | SB_HAB_DCD_MASK_BIT)
+/* NOP */
+#define SB_DCD_NOOP \
+ (SB_HAB_DCD_NOOP << 24)
+
+struct sb_dcd_ctx {
+ struct sb_dcd_ctx *dcd;
+
+ uint32_t id;
+
+ /* The DCD block. */
+ uint32_t *payload;
+ /* Size of the whole DCD block. */
+ uint32_t size;
+
+ /* Pointer to previous DCD command block. */
+ uint32_t *prev_dcd_head;
+};
+
+/*
+ * IMAGE
+ * |-SECTION
+ * | |-CMD
+ * | |-CMD
+ * | `-CMD
+ * |-SECTION
+ * | |-CMD
+ * : :
+ */
+struct sb_cmd_list {
+ char *cmd;
+ size_t len;
+ unsigned int lineno;
+};
+
+struct sb_cmd_ctx {
+ uint32_t size;
+
+ struct sb_cmd_ctx *cmd;
+
+ uint8_t *data;
+ uint32_t length;
+
+ struct sb_command payload;
+ struct sb_command c_payload;
+};
+
+struct sb_section_ctx {
+ uint32_t size;
+
+ /* Section flags */
+ unsigned int boot:1;
+
+ struct sb_section_ctx *sect;
+
+ struct sb_cmd_ctx *cmd_head;
+ struct sb_cmd_ctx *cmd_tail;
+
+ struct sb_sections_header payload;
+};
+
+struct sb_image_ctx {
+ unsigned int in_section:1;
+ unsigned int in_dcd:1;
+ /* Image configuration */
+ unsigned int verbose_boot:1;
+ unsigned int silent_dump:1;
+ char *input_filename;
+ char *output_filename;
+ char *cfg_filename;
+ uint8_t image_key[16];
+
+ /* Number of section in the image */
+ unsigned int sect_count;
+ /* Bootable section */
+ unsigned int sect_boot;
+ unsigned int sect_boot_found:1;
+
+ struct sb_section_ctx *sect_head;
+ struct sb_section_ctx *sect_tail;
+
+ struct sb_dcd_ctx *dcd_head;
+ struct sb_dcd_ctx *dcd_tail;
+
+ EVP_CIPHER_CTX cipher_ctx;
+ EVP_MD_CTX md_ctx;
+ uint8_t digest[32];
+ struct sb_key_dictionary_key sb_dict_key;
+
+ struct sb_boot_image_header payload;
+};
+
+/*
+ * Instruction semantics:
+ * NOOP
+ * TAG [LAST]
+ * LOAD address file
+ * LOAD IVT address IVT_entry_point
+ * FILL address pattern length
+ * JUMP [HAB] address [r0_arg]
+ * CALL [HAB] address [r0_arg]
+ * MODE mode
+ * For i.MX23, mode = USB/I2C/SPI1_FLASH/SPI2_FLASH/NAND_BCH
+ * JTAG/SPI3_EEPROM/SD_SSP0/SD_SSP1
+ * For i.MX28, mode = USB/I2C/SPI2_FLASH/SPI3_FLASH/NAND_BCH
+ * JTAG/SPI2_EEPROM/SD_SSP0/SD_SSP1
+ */
+
+/*
+ * AES libcrypto
+ */
+static int sb_aes_init(struct sb_image_ctx *ictx, uint8_t *iv, int enc)
+{
+ EVP_CIPHER_CTX *ctx = &ictx->cipher_ctx;
+ int ret;
+
+ /* If there is no init vector, init vector is all zeroes. */
+ if (!iv)
+ iv = ictx->image_key;
+
+ EVP_CIPHER_CTX_init(ctx);
+ ret = EVP_CipherInit(ctx, EVP_aes_128_cbc(), ictx->image_key, iv, enc);
+ if (ret == 1)
+ EVP_CIPHER_CTX_set_padding(ctx, 0);
+ return ret;
+}
+
+static int sb_aes_crypt(struct sb_image_ctx *ictx, uint8_t *in_data,
+ uint8_t *out_data, int in_len)
+{
+ EVP_CIPHER_CTX *ctx = &ictx->cipher_ctx;
+ int ret, outlen;
+ uint8_t *outbuf;
+
+ outbuf = malloc(in_len);
+ if (!outbuf)
+ return -ENOMEM;
+ memset(outbuf, 0, sizeof(in_len));
+
+ ret = EVP_CipherUpdate(ctx, outbuf, &outlen, in_data, in_len);
+ if (!ret) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ if (out_data)
+ memcpy(out_data, outbuf, outlen);
+
+err:
+ free(outbuf);
+ return ret;
+}
+
+static int sb_aes_deinit(EVP_CIPHER_CTX *ctx)
+{
+ return EVP_CIPHER_CTX_cleanup(ctx);
+}
+
+static int sb_aes_reinit(struct sb_image_ctx *ictx, int enc)
+{
+ int ret;
+ EVP_CIPHER_CTX *ctx = &ictx->cipher_ctx;
+ struct sb_boot_image_header *sb_header = &ictx->payload;
+ uint8_t *iv = sb_header->iv;
+
+ ret = sb_aes_deinit(ctx);
+ if (!ret)
+ return ret;
+ return sb_aes_init(ictx, iv, enc);
+}
+
+/*
+ * CRC32
+ */
+static uint32_t crc32(uint8_t *data, uint32_t len)
+{
+ const uint32_t poly = 0x04c11db7;
+ uint32_t crc32 = 0xffffffff;
+ unsigned int byte, bit;
+
+ for (byte = 0; byte < len; byte++) {
+ crc32 ^= data[byte] << 24;
+
+ for (bit = 8; bit > 0; bit--) {
+ if (crc32 & (1UL << 31))
+ crc32 = (crc32 << 1) ^ poly;
+ else
+ crc32 = (crc32 << 1);
+ }
+ }
+
+ return crc32;
+}
+
+/*
+ * Debug
+ */
+static void soprintf(struct sb_image_ctx *ictx, const char *fmt, ...)
+{
+ va_list ap;
+
+ if (ictx->silent_dump)
+ return;
+
+ va_start(ap, fmt);
+ vfprintf(stdout, fmt, ap);
+ va_end(ap);
+}
+
+/*
+ * Code
+ */
+static time_t sb_get_timestamp(void)
+{
+ struct tm time_2000 = {
+ .tm_yday = 1, /* Jan. 1st */
+ .tm_year = 100, /* 2000 */
+ };
+ time_t seconds_to_2000 = mktime(&time_2000);
+ time_t seconds_to_now = time(NULL);
+
+ return seconds_to_now - seconds_to_2000;
+}
+
+static int sb_get_time(time_t time, struct tm *tm)
+{
+ struct tm time_2000 = {
+ .tm_yday = 1, /* Jan. 1st */
+ .tm_year = 0, /* 1900 */
+ };
+ const time_t seconds_to_2000 = mktime(&time_2000);
+ const time_t seconds_to_now = seconds_to_2000 + time;
+ struct tm *ret;
+ ret = gmtime_r(&seconds_to_now, tm);
+ return ret ? 0 : -EINVAL;
+}
+
+static void sb_encrypt_sb_header(struct sb_image_ctx *ictx)
+{
+ EVP_MD_CTX *md_ctx = &ictx->md_ctx;
+ struct sb_boot_image_header *sb_header = &ictx->payload;
+ uint8_t *sb_header_ptr = (uint8_t *)sb_header;
+
+ /* Encrypt the header, compute the digest. */
+ sb_aes_crypt(ictx, sb_header_ptr, NULL, sizeof(*sb_header));
+ EVP_DigestUpdate(md_ctx, sb_header_ptr, sizeof(*sb_header));
+}
+
+static void sb_encrypt_sb_sections_header(struct sb_image_ctx *ictx)
+{
+ EVP_MD_CTX *md_ctx = &ictx->md_ctx;
+ struct sb_section_ctx *sctx = ictx->sect_head;
+ struct sb_sections_header *shdr;
+ uint8_t *sb_sections_header_ptr;
+ const int size = sizeof(*shdr);
+
+ while (sctx) {
+ shdr = &sctx->payload;
+ sb_sections_header_ptr = (uint8_t *)shdr;
+
+ sb_aes_crypt(ictx, sb_sections_header_ptr,
+ ictx->sb_dict_key.cbc_mac, size);
+ EVP_DigestUpdate(md_ctx, sb_sections_header_ptr, size);
+
+ sctx = sctx->sect;
+ };
+}
+
+static void sb_encrypt_key_dictionary_key(struct sb_image_ctx *ictx)
+{
+ EVP_MD_CTX *md_ctx = &ictx->md_ctx;
+
+ sb_aes_crypt(ictx, ictx->image_key, ictx->sb_dict_key.key,
+ sizeof(ictx->sb_dict_key.key));
+ EVP_DigestUpdate(md_ctx, &ictx->sb_dict_key, sizeof(ictx->sb_dict_key));
+}
+
+static void sb_decrypt_key_dictionary_key(struct sb_image_ctx *ictx)
+{
+ EVP_MD_CTX *md_ctx = &ictx->md_ctx;
+
+ EVP_DigestUpdate(md_ctx, &ictx->sb_dict_key, sizeof(ictx->sb_dict_key));
+ sb_aes_crypt(ictx, ictx->sb_dict_key.key, ictx->image_key,
+ sizeof(ictx->sb_dict_key.key));
+}
+
+static void sb_encrypt_tag(struct sb_image_ctx *ictx,
+ struct sb_cmd_ctx *cctx)
+{
+ EVP_MD_CTX *md_ctx = &ictx->md_ctx;
+ struct sb_command *cmd = &cctx->payload;
+
+ sb_aes_crypt(ictx, (uint8_t *)cmd,
+ (uint8_t *)&cctx->c_payload, sizeof(*cmd));
+ EVP_DigestUpdate(md_ctx, &cctx->c_payload, sizeof(*cmd));
+}
+
+static int sb_encrypt_image(struct sb_image_ctx *ictx)
+{
+ /* Start image-wide crypto. */
+ EVP_MD_CTX_init(&ictx->md_ctx);
+ EVP_DigestInit(&ictx->md_ctx, EVP_sha1());
+
+ /*
+ * SB image header.
+ */
+ sb_aes_init(ictx, NULL, 1);
+ sb_encrypt_sb_header(ictx);
+
+ /*
+ * SB sections header.
+ */
+ sb_encrypt_sb_sections_header(ictx);
+
+ /*
+ * Key dictionary.
+ */
+ sb_aes_reinit(ictx, 1);
+ sb_encrypt_key_dictionary_key(ictx);
+
+ /*
+ * Section tags.
+ */
+ struct sb_cmd_ctx *cctx;
+ struct sb_command *ccmd;
+ struct sb_section_ctx *sctx = ictx->sect_head;
+
+ while (sctx) {
+ cctx = sctx->cmd_head;
+
+ sb_aes_reinit(ictx, 1);
+
+ while (cctx) {
+ ccmd = &cctx->payload;
+
+ sb_encrypt_tag(ictx, cctx);
+
+ if (ccmd->header.tag == ROM_TAG_CMD) {
+ sb_aes_reinit(ictx, 1);
+ } else if (ccmd->header.tag == ROM_LOAD_CMD) {
+ sb_aes_crypt(ictx, cctx->data, cctx->data,
+ cctx->length);
+ EVP_DigestUpdate(&ictx->md_ctx, cctx->data,
+ cctx->length);
+ }
+
+ cctx = cctx->cmd;
+ }
+
+ sctx = sctx->sect;
+ };
+
+ /*
+ * Dump the SHA1 of the whole image.
+ */
+ sb_aes_reinit(ictx, 1);
+
+ EVP_DigestFinal(&ictx->md_ctx, ictx->digest, NULL);
+ sb_aes_crypt(ictx, ictx->digest, ictx->digest, sizeof(ictx->digest));
+
+ /* Stop the encryption session. */
+ sb_aes_deinit(&ictx->cipher_ctx);
+
+ return 0;
+}
+
+static int sb_load_file(struct sb_cmd_ctx *cctx, char *filename)
+{
+ long real_size, roundup_size;
+ uint8_t *data;
+ long ret;
+ unsigned long size;
+ FILE *fp;
+
+ if (!filename) {
+ fprintf(stderr, "ERR: Missing filename!\n");
+ return -EINVAL;
+ }
+
+ fp = fopen(filename, "r");
+ if (!fp)
+ goto err_open;
+
+ ret = fseek(fp, 0, SEEK_END);
+ if (ret < 0)
+ goto err_file;
+
+ real_size = ftell(fp);
+ if (real_size < 0)
+ goto err_file;
+
+ ret = fseek(fp, 0, SEEK_SET);
+ if (ret < 0)
+ goto err_file;
+
+ roundup_size = roundup(real_size, SB_BLOCK_SIZE);
+ data = calloc(1, roundup_size);
+ if (!data)
+ goto err_file;
+
+ size = fread(data, 1, real_size, fp);
+ if (size != (unsigned long)real_size)
+ goto err_alloc;
+
+ cctx->data = data;
+ cctx->length = roundup_size;
+
+ fclose(fp);
+ return 0;
+
+err_alloc:
+ free(data);
+err_file:
+ fclose(fp);
+err_open:
+ fprintf(stderr, "ERR: Failed to load file \"%s\"\n", filename);
+ return -EINVAL;
+}
+
+static uint8_t sb_command_checksum(struct sb_command *inst)
+{
+ uint8_t *inst_ptr = (uint8_t *)inst;
+ uint8_t csum = 0;
+ unsigned int i;
+
+ for (i = 0; i < sizeof(struct sb_command); i++)
+ csum += inst_ptr[i];
+
+ return csum;
+}
+
+static int sb_token_to_long(char *tok, uint32_t *rid)
+{
+ char *endptr;
+ unsigned long id;
+
+ if (tok[0] != '0' || tok[1] != 'x') {
+ fprintf(stderr, "ERR: Invalid hexadecimal number!\n");
+ return -EINVAL;
+ }
+
+ tok += 2;
+
+ id = strtoul(tok, &endptr, 16);
+ if ((errno == ERANGE && id == ULONG_MAX) || (errno != 0 && id == 0)) {
+ fprintf(stderr, "ERR: Value can't be decoded!\n");
+ return -EINVAL;
+ }
+
+ /* Check for 32-bit overflow. */
+ if (id > 0xffffffff) {
+ fprintf(stderr, "ERR: Value too big!\n");
+ return -EINVAL;
+ }
+
+ if (endptr == tok) {
+ fprintf(stderr, "ERR: Deformed value!\n");
+ return -EINVAL;
+ }
+
+ *rid = (uint32_t)id;
+ return 0;
+}
+
+static int sb_grow_dcd(struct sb_dcd_ctx *dctx, unsigned int inc_size)
+{
+ uint32_t *tmp;
+
+ if (!inc_size)
+ return 0;
+
+ dctx->size += inc_size;
+ tmp = realloc(dctx->payload, dctx->size);
+ if (!tmp)
+ return -ENOMEM;
+
+ dctx->payload = tmp;
+
+ /* Assemble and update the HAB DCD header. */
+ dctx->payload[0] = htonl((SB_HAB_DCD_TAG << 24) |
+ (dctx->size << 8) |
+ SB_HAB_VERSION);
+
+ return 0;
+}
+
+static int sb_build_dcd(struct sb_image_ctx *ictx, struct sb_cmd_list *cmd)
+{
+ struct sb_dcd_ctx *dctx;
+
+ char *tok;
+ uint32_t id;
+ int ret;
+
+ dctx = calloc(1, sizeof(*dctx));
+ if (!dctx)
+ return -ENOMEM;
+
+ ret = sb_grow_dcd(dctx, 4);
+ if (ret)
+ goto err_dcd;
+
+ /* Read DCD block number. */
+ tok = strtok(cmd->cmd, " ");
+ if (!tok) {
+ fprintf(stderr, "#%i ERR: DCD block without number!\n",
+ cmd->lineno);
+ ret = -EINVAL;
+ goto err_dcd;
+ }
+
+ /* Parse the DCD block number. */
+ ret = sb_token_to_long(tok, &id);
+ if (ret) {
+ fprintf(stderr, "#%i ERR: Malformed DCD block number!\n",
+ cmd->lineno);
+ goto err_dcd;
+ }
+
+ dctx->id = id;
+
+ /*
+ * The DCD block is now constructed. Append it to the list.
+ * WARNING: The DCD size is still not computed and will be
+ * updated while parsing it's commands.
+ */
+ if (!ictx->dcd_head) {
+ ictx->dcd_head = dctx;
+ ictx->dcd_tail = dctx;
+ } else {
+ ictx->dcd_tail->dcd = dctx;
+ ictx->dcd_tail = dctx;
+ }
+
+ return 0;
+
+err_dcd:
+ free(dctx->payload);
+ free(dctx);
+ return ret;
+}
+
+static int sb_build_dcd_block(struct sb_image_ctx *ictx,
+ struct sb_cmd_list *cmd,
+ uint32_t type)
+{
+ char *tok;
+ uint32_t address, value, length;
+ int ret;
+
+ struct sb_dcd_ctx *dctx = ictx->dcd_tail;
+ uint32_t *dcd;
+
+ if (dctx->prev_dcd_head && (type != SB_DCD_NOOP) &&
+ ((dctx->prev_dcd_head[0] & 0xff0000ff) == type)) {
+ /* Same instruction as before, just append it. */
+ ret = sb_grow_dcd(dctx, 8);
+ if (ret)
+ return ret;
+ } else if (type == SB_DCD_NOOP) {
+ ret = sb_grow_dcd(dctx, 4);
+ if (ret)
+ return ret;
+
+ /* Update DCD command block pointer. */
+ dctx->prev_dcd_head = dctx->payload +
+ dctx->size / sizeof(*dctx->payload) - 1;
+
+ /* NOOP has only 4 bytes and no payload. */
+ goto noop;
+ } else {
+ /*
+ * Either a different instruction block started now
+ * or this is the first instruction block.
+ */
+ ret = sb_grow_dcd(dctx, 12);
+ if (ret)
+ return ret;
+
+ /* Update DCD command block pointer. */
+ dctx->prev_dcd_head = dctx->payload +
+ dctx->size / sizeof(*dctx->payload) - 3;
+ }
+
+ dcd = dctx->payload + dctx->size / sizeof(*dctx->payload) - 2;
+
+ /*
+ * Prepare the command.
+ */
+ tok = strtok(cmd->cmd, " ");
+ if (!tok) {
+ fprintf(stderr, "#%i ERR: Missing DCD address!\n",
+ cmd->lineno);
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* Read DCD destination address. */
+ ret = sb_token_to_long(tok, &address);
+ if (ret) {
+ fprintf(stderr, "#%i ERR: Incorrect DCD address!\n",
+ cmd->lineno);
+ goto err;
+ }
+
+ tok = strtok(NULL, " ");
+ if (!tok) {
+ fprintf(stderr, "#%i ERR: Missing DCD value!\n",
+ cmd->lineno);
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* Read DCD operation value. */
+ ret = sb_token_to_long(tok, &value);
+ if (ret) {
+ fprintf(stderr, "#%i ERR: Incorrect DCD value!\n",
+ cmd->lineno);
+ goto err;
+ }
+
+ /* Fill in the new DCD entry. */
+ dcd[0] = htonl(address);
+ dcd[1] = htonl(value);
+
+noop:
+ /* Update the DCD command block. */
+ length = dctx->size -
+ ((dctx->prev_dcd_head - dctx->payload) *
+ sizeof(*dctx->payload));
+ dctx->prev_dcd_head[0] = htonl(type | (length << 8));
+
+err:
+ return ret;
+}
+
+static int sb_build_section(struct sb_image_ctx *ictx, struct sb_cmd_list *cmd)
+{
+ struct sb_section_ctx *sctx;
+ struct sb_sections_header *shdr;
+ char *tok;
+ uint32_t bootable = 0;
+ uint32_t id;
+ int ret;
+
+ sctx = calloc(1, sizeof(*sctx));
+ if (!sctx)
+ return -ENOMEM;
+
+ /* Read section number. */
+ tok = strtok(cmd->cmd, " ");
+ if (!tok) {
+ fprintf(stderr, "#%i ERR: Section without number!\n",
+ cmd->lineno);
+ ret = -EINVAL;
+ goto err_sect;
+ }
+
+ /* Parse the section number. */
+ ret = sb_token_to_long(tok, &id);
+ if (ret) {
+ fprintf(stderr, "#%i ERR: Malformed section number!\n",
+ cmd->lineno);
+ goto err_sect;
+ }
+
+ /* Read section's BOOTABLE flag. */
+ tok = strtok(NULL, " ");
+ if (tok && (strlen(tok) == 8) && !strncmp(tok, "BOOTABLE", 8))
+ bootable = SB_SECTION_FLAG_BOOTABLE;
+
+ sctx->boot = bootable;
+
+ shdr = &sctx->payload;
+ shdr->section_number = id;
+ shdr->section_flags = bootable;
+
+ /*
+ * The section is now constructed. Append it to the list.
+ * WARNING: The section size is still not computed and will
+ * be updated while parsing it's commands.
+ */
+ ictx->sect_count++;
+
+ /* Mark that this section is bootable one. */
+ if (bootable) {
+ if (ictx->sect_boot_found) {
+ fprintf(stderr,
+ "#%i WARN: Multiple bootable section!\n",
+ cmd->lineno);
+ } else {
+ ictx->sect_boot = id;
+ ictx->sect_boot_found = 1;
+ }
+ }
+
+ if (!ictx->sect_head) {
+ ictx->sect_head = sctx;
+ ictx->sect_tail = sctx;
+ } else {
+ ictx->sect_tail->sect = sctx;
+ ictx->sect_tail = sctx;
+ }
+
+ return 0;
+
+err_sect:
+ free(sctx);
+ return ret;
+}
+
+static int sb_build_command_nop(struct sb_image_ctx *ictx)
+{
+ struct sb_section_ctx *sctx = ictx->sect_tail;
+ struct sb_cmd_ctx *cctx;
+ struct sb_command *ccmd;
+
+ cctx = calloc(1, sizeof(*cctx));
+ if (!cctx)
+ return -ENOMEM;
+
+ ccmd = &cctx->payload;
+
+ /*
+ * Construct the command.
+ */
+ ccmd->header.checksum = 0x5a;
+ ccmd->header.tag = ROM_NOP_CMD;
+
+ cctx->size = sizeof(*ccmd);
+
+ /*
+ * Append the command to the last section.
+ */
+ if (!sctx->cmd_head) {
+ sctx->cmd_head = cctx;
+ sctx->cmd_tail = cctx;
+ } else {
+ sctx->cmd_tail->cmd = cctx;
+ sctx->cmd_tail = cctx;
+ }
+
+ return 0;
+}
+
+static int sb_build_command_tag(struct sb_image_ctx *ictx,
+ struct sb_cmd_list *cmd)
+{
+ struct sb_section_ctx *sctx = ictx->sect_tail;
+ struct sb_cmd_ctx *cctx;
+ struct sb_command *ccmd;
+ char *tok;
+
+ cctx = calloc(1, sizeof(*cctx));
+ if (!cctx)
+ return -ENOMEM;
+
+ ccmd = &cctx->payload;
+
+ /*
+ * Prepare the command.
+ */
+ /* Check for the LAST keyword. */
+ tok = strtok(cmd->cmd, " ");
+ if (tok && !strcmp(tok, "LAST"))
+ ccmd->header.flags = ROM_TAG_CMD_FLAG_ROM_LAST_TAG;
+
+ /*
+ * Construct the command.
+ */
+ ccmd->header.checksum = 0x5a;
+ ccmd->header.tag = ROM_TAG_CMD;
+
+ cctx->size = sizeof(*ccmd);
+
+ /*
+ * Append the command to the last section.
+ */
+ if (!sctx->cmd_head) {
+ sctx->cmd_head = cctx;
+ sctx->cmd_tail = cctx;
+ } else {
+ sctx->cmd_tail->cmd = cctx;
+ sctx->cmd_tail = cctx;
+ }
+
+ return 0;
+}
+
+static int sb_build_command_load(struct sb_image_ctx *ictx,
+ struct sb_cmd_list *cmd)
+{
+ struct sb_section_ctx *sctx = ictx->sect_tail;
+ struct sb_cmd_ctx *cctx;
+ struct sb_command *ccmd;
+ char *tok;
+ int ret, is_ivt = 0, is_dcd = 0;
+ uint32_t dest, dcd = 0;
+
+ cctx = calloc(1, sizeof(*cctx));
+ if (!cctx)
+ return -ENOMEM;
+
+ ccmd = &cctx->payload;
+
+ /*
+ * Prepare the command.
+ */
+ tok = strtok(cmd->cmd, " ");
+ if (!tok) {
+ fprintf(stderr, "#%i ERR: Missing LOAD address or 'IVT'!\n",
+ cmd->lineno);
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* Check for "IVT" flag. */
+ if (!strcmp(tok, "IVT"))
+ is_ivt = 1;
+ if (!strcmp(tok, "DCD"))
+ is_dcd = 1;
+ if (is_ivt || is_dcd) {
+ tok = strtok(NULL, " ");
+ if (!tok) {
+ fprintf(stderr, "#%i ERR: Missing LOAD address!\n",
+ cmd->lineno);
+ ret = -EINVAL;
+ goto err;
+ }
+ }
+
+ /* Read load destination address. */
+ ret = sb_token_to_long(tok, &dest);
+ if (ret) {
+ fprintf(stderr, "#%i ERR: Incorrect LOAD address!\n",
+ cmd->lineno);
+ goto err;
+ }
+
+ /* Read filename or IVT entrypoint or DCD block ID. */
+ tok = strtok(NULL, " ");
+ if (!tok) {
+ fprintf(stderr,
+ "#%i ERR: Missing LOAD filename or IVT ep or DCD block ID!\n",
+ cmd->lineno);
+ ret = -EINVAL;
+ goto err;
+ }
+
+ if (is_ivt) {
+ /* Handle IVT. */
+ struct sb_ivt_header *ivt;
+ uint32_t ivtep;
+ ret = sb_token_to_long(tok, &ivtep);
+
+ if (ret) {
+ fprintf(stderr,
+ "#%i ERR: Incorrect IVT entry point!\n",
+ cmd->lineno);
+ goto err;
+ }
+
+ ivt = calloc(1, sizeof(*ivt));
+ if (!ivt) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ ivt->header = sb_hab_ivt_header();
+ ivt->entry = ivtep;
+ ivt->self = dest;
+
+ cctx->data = (uint8_t *)ivt;
+ cctx->length = sizeof(*ivt);
+ } else if (is_dcd) {
+ struct sb_dcd_ctx *dctx = ictx->dcd_head;
+ uint32_t dcdid;
+ uint8_t *payload;
+ uint32_t asize;
+ ret = sb_token_to_long(tok, &dcdid);
+
+ if (ret) {
+ fprintf(stderr,
+ "#%i ERR: Incorrect DCD block ID!\n",
+ cmd->lineno);
+ goto err;
+ }
+
+ while (dctx) {
+ if (dctx->id == dcdid)
+ break;
+ dctx = dctx->dcd;
+ }
+
+ if (!dctx) {
+ fprintf(stderr, "#%i ERR: DCD block %08x not found!\n",
+ cmd->lineno, dcdid);
+ goto err;
+ }
+
+ asize = roundup(dctx->size, SB_BLOCK_SIZE);
+ payload = calloc(1, asize);
+ if (!payload) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ memcpy(payload, dctx->payload, dctx->size);
+
+ cctx->data = payload;
+ cctx->length = asize;
+
+ /* Set the Load DCD flag. */
+ dcd = ROM_LOAD_CMD_FLAG_DCD_LOAD;
+ } else {
+ /* Regular LOAD of a file. */
+ ret = sb_load_file(cctx, tok);
+ if (ret) {
+ fprintf(stderr, "#%i ERR: Cannot load '%s'!\n",
+ cmd->lineno, tok);
+ goto err;
+ }
+ }
+
+ if (cctx->length & (SB_BLOCK_SIZE - 1)) {
+ fprintf(stderr, "#%i ERR: Unaligned payload!\n",
+ cmd->lineno);
+ }
+
+ /*
+ * Construct the command.
+ */
+ ccmd->header.checksum = 0x5a;
+ ccmd->header.tag = ROM_LOAD_CMD;
+ ccmd->header.flags = dcd;
+
+ ccmd->load.address = dest;
+ ccmd->load.count = cctx->length;
+ ccmd->load.crc32 = crc32(cctx->data, cctx->length);
+
+ cctx->size = sizeof(*ccmd) + cctx->length;
+
+ /*
+ * Append the command to the last section.
+ */
+ if (!sctx->cmd_head) {
+ sctx->cmd_head = cctx;
+ sctx->cmd_tail = cctx;
+ } else {
+ sctx->cmd_tail->cmd = cctx;
+ sctx->cmd_tail = cctx;
+ }
+
+ return 0;
+
+err:
+ free(cctx);
+ return ret;
+}
+
+static int sb_build_command_fill(struct sb_image_ctx *ictx,
+ struct sb_cmd_list *cmd)
+{
+ struct sb_section_ctx *sctx = ictx->sect_tail;
+ struct sb_cmd_ctx *cctx;
+ struct sb_command *ccmd;
+ char *tok;
+ uint32_t address, pattern, length;
+ int ret;
+
+ cctx = calloc(1, sizeof(*cctx));
+ if (!cctx)
+ return -ENOMEM;
+
+ ccmd = &cctx->payload;
+
+ /*
+ * Prepare the command.
+ */
+ tok = strtok(cmd->cmd, " ");
+ if (!tok) {
+ fprintf(stderr, "#%i ERR: Missing FILL address!\n",
+ cmd->lineno);
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* Read fill destination address. */
+ ret = sb_token_to_long(tok, &address);
+ if (ret) {
+ fprintf(stderr, "#%i ERR: Incorrect FILL address!\n",
+ cmd->lineno);
+ goto err;
+ }
+
+ tok = strtok(NULL, " ");
+ if (!tok) {
+ fprintf(stderr, "#%i ERR: Missing FILL pattern!\n",
+ cmd->lineno);
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* Read fill pattern address. */
+ ret = sb_token_to_long(tok, &pattern);
+ if (ret) {
+ fprintf(stderr, "#%i ERR: Incorrect FILL pattern!\n",
+ cmd->lineno);
+ goto err;
+ }
+
+ tok = strtok(NULL, " ");
+ if (!tok) {
+ fprintf(stderr, "#%i ERR: Missing FILL length!\n",
+ cmd->lineno);
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* Read fill pattern address. */
+ ret = sb_token_to_long(tok, &length);
+ if (ret) {
+ fprintf(stderr, "#%i ERR: Incorrect FILL length!\n",
+ cmd->lineno);
+ goto err;
+ }
+
+ /*
+ * Construct the command.
+ */
+ ccmd->header.checksum = 0x5a;
+ ccmd->header.tag = ROM_FILL_CMD;
+
+ ccmd->fill.address = address;
+ ccmd->fill.count = length;
+ ccmd->fill.pattern = pattern;
+
+ cctx->size = sizeof(*ccmd);
+
+ /*
+ * Append the command to the last section.
+ */
+ if (!sctx->cmd_head) {
+ sctx->cmd_head = cctx;
+ sctx->cmd_tail = cctx;
+ } else {
+ sctx->cmd_tail->cmd = cctx;
+ sctx->cmd_tail = cctx;
+ }
+
+ return 0;
+
+err:
+ free(cctx);
+ return ret;
+}
+
+static int sb_build_command_jump_call(struct sb_image_ctx *ictx,
+ struct sb_cmd_list *cmd,
+ unsigned int is_call)
+{
+ struct sb_section_ctx *sctx = ictx->sect_tail;
+ struct sb_cmd_ctx *cctx;
+ struct sb_command *ccmd;
+ char *tok;
+ uint32_t dest, arg = 0x0;
+ uint32_t hab = 0;
+ int ret;
+ const char *cmdname = is_call ? "CALL" : "JUMP";
+
+ cctx = calloc(1, sizeof(*cctx));
+ if (!cctx)
+ return -ENOMEM;
+
+ ccmd = &cctx->payload;
+
+ /*
+ * Prepare the command.
+ */
+ tok = strtok(cmd->cmd, " ");
+ if (!tok) {
+ fprintf(stderr,
+ "#%i ERR: Missing %s address or 'HAB'!\n",
+ cmd->lineno, cmdname);
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* Check for "HAB" flag. */
+ if (!strcmp(tok, "HAB")) {
+ hab = is_call ? ROM_CALL_CMD_FLAG_HAB : ROM_JUMP_CMD_FLAG_HAB;
+ tok = strtok(NULL, " ");
+ if (!tok) {
+ fprintf(stderr, "#%i ERR: Missing %s address!\n",
+ cmd->lineno, cmdname);
+ ret = -EINVAL;
+ goto err;
+ }
+ }
+ /* Read load destination address. */
+ ret = sb_token_to_long(tok, &dest);
+ if (ret) {
+ fprintf(stderr, "#%i ERR: Incorrect %s address!\n",
+ cmd->lineno, cmdname);
+ goto err;
+ }
+
+ tok = strtok(NULL, " ");
+ if (tok) {
+ ret = sb_token_to_long(tok, &arg);
+ if (ret) {
+ fprintf(stderr,
+ "#%i ERR: Incorrect %s argument!\n",
+ cmd->lineno, cmdname);
+ goto err;
+ }
+ }
+
+ /*
+ * Construct the command.
+ */
+ ccmd->header.checksum = 0x5a;
+ ccmd->header.tag = is_call ? ROM_CALL_CMD : ROM_JUMP_CMD;
+ ccmd->header.flags = hab;
+
+ ccmd->call.address = dest;
+ ccmd->call.argument = arg;
+
+ cctx->size = sizeof(*ccmd);
+
+ /*
+ * Append the command to the last section.
+ */
+ if (!sctx->cmd_head) {
+ sctx->cmd_head = cctx;
+ sctx->cmd_tail = cctx;
+ } else {
+ sctx->cmd_tail->cmd = cctx;
+ sctx->cmd_tail = cctx;
+ }
+
+ return 0;
+
+err:
+ free(cctx);
+ return ret;
+}
+
+static int sb_build_command_jump(struct sb_image_ctx *ictx,
+ struct sb_cmd_list *cmd)
+{
+ return sb_build_command_jump_call(ictx, cmd, 0);
+}
+
+static int sb_build_command_call(struct sb_image_ctx *ictx,
+ struct sb_cmd_list *cmd)
+{
+ return sb_build_command_jump_call(ictx, cmd, 1);
+}
+
+static int sb_build_command_mode(struct sb_image_ctx *ictx,
+ struct sb_cmd_list *cmd)
+{
+ struct sb_section_ctx *sctx = ictx->sect_tail;
+ struct sb_cmd_ctx *cctx;
+ struct sb_command *ccmd;
+ char *tok;
+ int ret;
+ unsigned int i;
+ uint32_t mode = 0xffffffff;
+
+ cctx = calloc(1, sizeof(*cctx));
+ if (!cctx)
+ return -ENOMEM;
+
+ ccmd = &cctx->payload;
+
+ /*
+ * Prepare the command.
+ */
+ tok = strtok(cmd->cmd, " ");
+ if (!tok) {
+ fprintf(stderr, "#%i ERR: Missing MODE boot mode argument!\n",
+ cmd->lineno);
+ ret = -EINVAL;
+ goto err;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(modetable); i++) {
+ if (!strcmp(tok, modetable[i].name)) {
+ mode = modetable[i].mode;
+ break;
+ }
+
+ if (!modetable[i].altname)
+ continue;
+
+ if (!strcmp(tok, modetable[i].altname)) {
+ mode = modetable[i].mode;
+ break;
+ }
+ }
+
+ if (mode == 0xffffffff) {
+ fprintf(stderr, "#%i ERR: Invalid MODE boot mode argument!\n",
+ cmd->lineno);
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /*
+ * Construct the command.
+ */
+ ccmd->header.checksum = 0x5a;
+ ccmd->header.tag = ROM_MODE_CMD;
+
+ ccmd->mode.mode = mode;
+
+ cctx->size = sizeof(*ccmd);
+
+ /*
+ * Append the command to the last section.
+ */
+ if (!sctx->cmd_head) {
+ sctx->cmd_head = cctx;
+ sctx->cmd_tail = cctx;
+ } else {
+ sctx->cmd_tail->cmd = cctx;
+ sctx->cmd_tail = cctx;
+ }
+
+ return 0;
+
+err:
+ free(cctx);
+ return ret;
+}
+
+static int sb_prefill_image_header(struct sb_image_ctx *ictx)
+{
+ struct sb_boot_image_header *hdr = &ictx->payload;
+
+ /* Fill signatures */
+ memcpy(hdr->signature1, "STMP", 4);
+ memcpy(hdr->signature2, "sgtl", 4);
+
+ /* SB Image version 1.1 */
+ hdr->major_version = SB_VERSION_MAJOR;
+ hdr->minor_version = SB_VERSION_MINOR;
+
+ /* Boot image major version */
+ hdr->product_version.major = htons(0x999);
+ hdr->product_version.minor = htons(0x999);
+ hdr->product_version.revision = htons(0x999);
+ /* Boot image major version */
+ hdr->component_version.major = htons(0x999);
+ hdr->component_version.minor = htons(0x999);
+ hdr->component_version.revision = htons(0x999);
+
+ /* Drive tag must be 0x0 for i.MX23 */
+ hdr->drive_tag = 0;
+
+ hdr->header_blocks =
+ sizeof(struct sb_boot_image_header) / SB_BLOCK_SIZE;
+ hdr->section_header_size =
+ sizeof(struct sb_sections_header) / SB_BLOCK_SIZE;
+ hdr->timestamp_us = sb_get_timestamp() * 1000000;
+
+ /* FIXME -- add proper config option */
+ hdr->flags = ictx->verbose_boot ? SB_IMAGE_FLAG_VERBOSE : 0,
+
+ /* FIXME -- We support only default key */
+ hdr->key_count = 1;
+
+ return 0;
+}
+
+static int sb_postfill_image_header(struct sb_image_ctx *ictx)
+{
+ struct sb_boot_image_header *hdr = &ictx->payload;
+ struct sb_section_ctx *sctx = ictx->sect_head;
+ uint32_t kd_size, sections_blocks;
+ EVP_MD_CTX md_ctx;
+
+ /* The main SB header size in blocks. */
+ hdr->image_blocks = hdr->header_blocks;
+
+ /* Size of the key dictionary, which has single zero entry. */
+ kd_size = hdr->key_count * sizeof(struct sb_key_dictionary_key);
+ hdr->image_blocks += kd_size / SB_BLOCK_SIZE;
+
+ /* Now count the payloads. */
+ hdr->section_count = ictx->sect_count;
+ while (sctx) {
+ hdr->image_blocks += sctx->size / SB_BLOCK_SIZE;
+ sctx = sctx->sect;
+ }
+
+ if (!ictx->sect_boot_found) {
+ fprintf(stderr, "ERR: No bootable section selected!\n");
+ return -EINVAL;
+ }
+ hdr->first_boot_section_id = ictx->sect_boot;
+
+ /* The n * SB section size in blocks. */
+ sections_blocks = hdr->section_count * hdr->section_header_size;
+ hdr->image_blocks += sections_blocks;
+
+ /* Key dictionary offset. */
+ hdr->key_dictionary_block = hdr->header_blocks + sections_blocks;
+
+ /* Digest of the whole image. */
+ hdr->image_blocks += 2;
+
+ /* Pointer past the dictionary. */
+ hdr->first_boot_tag_block =
+ hdr->key_dictionary_block + kd_size / SB_BLOCK_SIZE;
+
+ /* Compute header digest. */
+ EVP_MD_CTX_init(&md_ctx);
+
+ EVP_DigestInit(&md_ctx, EVP_sha1());
+ EVP_DigestUpdate(&md_ctx, hdr->signature1,
+ sizeof(struct sb_boot_image_header) -
+ sizeof(hdr->digest));
+ EVP_DigestFinal(&md_ctx, hdr->digest, NULL);
+
+ return 0;
+}
+
+static int sb_fixup_sections_and_tags(struct sb_image_ctx *ictx)
+{
+ /* Fixup the placement of sections. */
+ struct sb_boot_image_header *ihdr = &ictx->payload;
+ struct sb_section_ctx *sctx = ictx->sect_head;
+ struct sb_sections_header *shdr;
+ struct sb_cmd_ctx *cctx;
+ struct sb_command *ccmd;
+ uint32_t offset = ihdr->first_boot_tag_block;
+
+ while (sctx) {
+ shdr = &sctx->payload;
+
+ /* Fill in the section TAG offset. */
+ shdr->section_offset = offset + 1;
+ offset += shdr->section_size;
+
+ /* Section length is measured from the TAG block. */
+ shdr->section_size--;
+
+ /* Fixup the TAG command. */
+ cctx = sctx->cmd_head;
+ while (cctx) {
+ ccmd = &cctx->payload;
+ if (ccmd->header.tag == ROM_TAG_CMD) {
+ ccmd->tag.section_number = shdr->section_number;
+ ccmd->tag.section_length = shdr->section_size;
+ ccmd->tag.section_flags = shdr->section_flags;
+ }
+
+ /* Update the command checksum. */
+ ccmd->header.checksum = sb_command_checksum(ccmd);
+
+ cctx = cctx->cmd;
+ }
+
+ sctx = sctx->sect;
+ }
+
+ return 0;
+}
+
+static int sb_parse_line(struct sb_image_ctx *ictx, struct sb_cmd_list *cmd)
+{
+ char *tok;
+ char *line = cmd->cmd;
+ char *rptr;
+ int ret;
+
+ /* Analyze the identifier on this line first. */
+ tok = strtok_r(line, " ", &rptr);
+ if (!tok || (strlen(tok) == 0)) {
+ fprintf(stderr, "#%i ERR: Invalid line!\n", cmd->lineno);
+ return -EINVAL;
+ }
+
+ cmd->cmd = rptr;
+
+ /* DCD */
+ if (!strcmp(tok, "DCD")) {
+ ictx->in_section = 0;
+ ictx->in_dcd = 1;
+ sb_build_dcd(ictx, cmd);
+ return 0;
+ }
+
+ /* Section */
+ if (!strcmp(tok, "SECTION")) {
+ ictx->in_section = 1;
+ ictx->in_dcd = 0;
+ sb_build_section(ictx, cmd);
+ return 0;
+ }
+
+ if (!ictx->in_section && !ictx->in_dcd) {
+ fprintf(stderr, "#%i ERR: Data outside of a section!\n",
+ cmd->lineno);
+ return -EINVAL;
+ }
+
+ if (ictx->in_section) {
+ /* Section commands */
+ if (!strcmp(tok, "NOP")) {
+ ret = sb_build_command_nop(ictx);
+ } else if (!strcmp(tok, "TAG")) {
+ ret = sb_build_command_tag(ictx, cmd);
+ } else if (!strcmp(tok, "LOAD")) {
+ ret = sb_build_command_load(ictx, cmd);
+ } else if (!strcmp(tok, "FILL")) {
+ ret = sb_build_command_fill(ictx, cmd);
+ } else if (!strcmp(tok, "JUMP")) {
+ ret = sb_build_command_jump(ictx, cmd);
+ } else if (!strcmp(tok, "CALL")) {
+ ret = sb_build_command_call(ictx, cmd);
+ } else if (!strcmp(tok, "MODE")) {
+ ret = sb_build_command_mode(ictx, cmd);
+ } else {
+ fprintf(stderr,
+ "#%i ERR: Unsupported instruction '%s'!\n",
+ cmd->lineno, tok);
+ return -ENOTSUP;
+ }
+ } else if (ictx->in_dcd) {
+ char *lptr;
+ uint32_t ilen = '1';
+
+ tok = strtok_r(tok, ".", &lptr);
+ if (!tok || (strlen(tok) == 0) || (lptr && strlen(lptr) != 1)) {
+ fprintf(stderr, "#%i ERR: Invalid line!\n",
+ cmd->lineno);
+ return -EINVAL;
+ }
+
+ if (lptr &&
+ (lptr[0] != '1' && lptr[0] != '2' && lptr[0] != '4')) {
+ fprintf(stderr, "#%i ERR: Invalid instruction width!\n",
+ cmd->lineno);
+ return -EINVAL;
+ }
+
+ if (lptr)
+ ilen = lptr[0] - '1';
+
+ /* DCD commands */
+ if (!strcmp(tok, "WRITE")) {
+ ret = sb_build_dcd_block(ictx, cmd,
+ SB_DCD_WRITE | ilen);
+ } else if (!strcmp(tok, "ANDC")) {
+ ret = sb_build_dcd_block(ictx, cmd,
+ SB_DCD_ANDC | ilen);
+ } else if (!strcmp(tok, "ORR")) {
+ ret = sb_build_dcd_block(ictx, cmd,
+ SB_DCD_ORR | ilen);
+ } else if (!strcmp(tok, "EQZ")) {
+ ret = sb_build_dcd_block(ictx, cmd,
+ SB_DCD_CHK_EQZ | ilen);
+ } else if (!strcmp(tok, "EQ")) {
+ ret = sb_build_dcd_block(ictx, cmd,
+ SB_DCD_CHK_EQ | ilen);
+ } else if (!strcmp(tok, "NEQ")) {
+ ret = sb_build_dcd_block(ictx, cmd,
+ SB_DCD_CHK_NEQ | ilen);
+ } else if (!strcmp(tok, "NEZ")) {
+ ret = sb_build_dcd_block(ictx, cmd,
+ SB_DCD_CHK_NEZ | ilen);
+ } else if (!strcmp(tok, "NOOP")) {
+ ret = sb_build_dcd_block(ictx, cmd, SB_DCD_NOOP);
+ } else {
+ fprintf(stderr,
+ "#%i ERR: Unsupported instruction '%s'!\n",
+ cmd->lineno, tok);
+ return -ENOTSUP;
+ }
+ } else {
+ fprintf(stderr, "#%i ERR: Unsupported instruction '%s'!\n",
+ cmd->lineno, tok);
+ return -ENOTSUP;
+ }
+
+ /*
+ * Here we have at least one section with one command, otherwise we
+ * would have failed already higher above.
+ *
+ * FIXME -- should the updating happen here ?
+ */
+ if (ictx->in_section && !ret) {
+ ictx->sect_tail->size += ictx->sect_tail->cmd_tail->size;
+ ictx->sect_tail->payload.section_size =
+ ictx->sect_tail->size / SB_BLOCK_SIZE;
+ }
+
+ return ret;
+}
+
+static int sb_load_cmdfile(struct sb_image_ctx *ictx)
+{
+ struct sb_cmd_list cmd;
+ int lineno = 1;
+ FILE *fp;
+ char *line = NULL;
+ ssize_t rlen;
+ size_t len;
+
+ fp = fopen(ictx->cfg_filename, "r");
+ if (!fp)
+ goto err_file;
+
+ while ((rlen = getline(&line, &len, fp)) > 0) {
+ memset(&cmd, 0, sizeof(cmd));
+
+ /* Strip the trailing newline. */
+ line[rlen - 1] = '\0';
+
+ cmd.cmd = line;
+ cmd.len = rlen;
+ cmd.lineno = lineno++;
+
+ sb_parse_line(ictx, &cmd);
+ }
+
+ free(line);
+
+ fclose(fp);
+
+ return 0;
+
+err_file:
+ fclose(fp);
+ fprintf(stderr, "ERR: Failed to load file \"%s\"\n",
+ ictx->cfg_filename);
+ return -EINVAL;
+}
+
+static int sb_build_tree_from_cfg(struct sb_image_ctx *ictx)
+{
+ int ret;
+
+ ret = sb_load_cmdfile(ictx);
+ if (ret)
+ return ret;
+
+ ret = sb_prefill_image_header(ictx);
+ if (ret)
+ return ret;
+
+ ret = sb_postfill_image_header(ictx);
+ if (ret)
+ return ret;
+
+ ret = sb_fixup_sections_and_tags(ictx);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int sb_verify_image_header(struct sb_image_ctx *ictx,
+ FILE *fp, long fsize)
+{
+ /* Verify static fields in the image header. */
+ struct sb_boot_image_header *hdr = &ictx->payload;
+ const char *stat[2] = { "[PASS]", "[FAIL]" };
+ struct tm tm;
+ int sz, ret = 0;
+ unsigned char digest[20];
+ EVP_MD_CTX md_ctx;
+ unsigned long size;
+
+ /* Start image-wide crypto. */
+ EVP_MD_CTX_init(&ictx->md_ctx);
+ EVP_DigestInit(&ictx->md_ctx, EVP_sha1());
+
+ soprintf(ictx, "---------- Verifying SB Image Header ----------\n");
+
+ size = fread(&ictx->payload, 1, sizeof(ictx->payload), fp);
+ if (size != sizeof(ictx->payload)) {
+ fprintf(stderr, "ERR: SB image header too short!\n");
+ return -EINVAL;
+ }
+
+ /* Compute header digest. */
+ EVP_MD_CTX_init(&md_ctx);
+ EVP_DigestInit(&md_ctx, EVP_sha1());
+ EVP_DigestUpdate(&md_ctx, hdr->signature1,
+ sizeof(struct sb_boot_image_header) -
+ sizeof(hdr->digest));
+ EVP_DigestFinal(&md_ctx, digest, NULL);
+
+ sb_aes_init(ictx, NULL, 1);
+ sb_encrypt_sb_header(ictx);
+
+ if (memcmp(digest, hdr->digest, 20))
+ ret = -EINVAL;
+ soprintf(ictx, "%s Image header checksum: %s\n", stat[!!ret],
+ ret ? "BAD" : "OK");
+ if (ret)
+ return ret;
+
+ if (memcmp(hdr->signature1, "STMP", 4) ||
+ memcmp(hdr->signature2, "sgtl", 4))
+ ret = -EINVAL;
+ soprintf(ictx, "%s Signatures: '%.4s' '%.4s'\n",
+ stat[!!ret], hdr->signature1, hdr->signature2);
+ if (ret)
+ return ret;
+
+ if ((hdr->major_version != SB_VERSION_MAJOR) ||
+ ((hdr->minor_version != 1) && (hdr->minor_version != 2)))
+ ret = -EINVAL;
+ soprintf(ictx, "%s Image version: v%i.%i\n", stat[!!ret],
+ hdr->major_version, hdr->minor_version);
+ if (ret)
+ return ret;
+
+ ret = sb_get_time(hdr->timestamp_us / 1000000, &tm);
+ soprintf(ictx,
+ "%s Creation time: %02i:%02i:%02i %02i/%02i/%04i\n",
+ stat[!!ret], tm.tm_hour, tm.tm_min, tm.tm_sec,
+ tm.tm_mday, tm.tm_mon, tm.tm_year + 2000);
+ if (ret)
+ return ret;
+
+ soprintf(ictx, "%s Product version: %x.%x.%x\n", stat[0],
+ ntohs(hdr->product_version.major),
+ ntohs(hdr->product_version.minor),
+ ntohs(hdr->product_version.revision));
+ soprintf(ictx, "%s Component version: %x.%x.%x\n", stat[0],
+ ntohs(hdr->component_version.major),
+ ntohs(hdr->component_version.minor),
+ ntohs(hdr->component_version.revision));
+
+ if (hdr->flags & ~SB_IMAGE_FLAG_VERBOSE)
+ ret = -EINVAL;
+ soprintf(ictx, "%s Image flags: %s\n", stat[!!ret],
+ hdr->flags & SB_IMAGE_FLAG_VERBOSE ? "Verbose_boot" : "");
+ if (ret)
+ return ret;
+
+ if (hdr->drive_tag != 0)
+ ret = -EINVAL;
+ soprintf(ictx, "%s Drive tag: %i\n", stat[!!ret],
+ hdr->drive_tag);
+ if (ret)
+ return ret;
+
+ sz = sizeof(struct sb_boot_image_header) / SB_BLOCK_SIZE;
+ if (hdr->header_blocks != sz)
+ ret = -EINVAL;
+ soprintf(ictx, "%s Image header size (blocks): %i\n", stat[!!ret],
+ hdr->header_blocks);
+ if (ret)
+ return ret;
+
+ sz = sizeof(struct sb_sections_header) / SB_BLOCK_SIZE;
+ if (hdr->section_header_size != sz)
+ ret = -EINVAL;
+ soprintf(ictx, "%s Section header size (blocks): %i\n", stat[!!ret],
+ hdr->section_header_size);
+ if (ret)
+ return ret;
+
+ soprintf(ictx, "%s Sections count: %i\n", stat[!!ret],
+ hdr->section_count);
+ soprintf(ictx, "%s First bootable section %i\n", stat[!!ret],
+ hdr->first_boot_section_id);
+
+ if (hdr->image_blocks != fsize / SB_BLOCK_SIZE)
+ ret = -EINVAL;
+ soprintf(ictx, "%s Image size (blocks): %i\n", stat[!!ret],
+ hdr->image_blocks);
+ if (ret)
+ return ret;
+
+ sz = hdr->header_blocks + hdr->section_header_size * hdr->section_count;
+ if (hdr->key_dictionary_block != sz)
+ ret = -EINVAL;
+ soprintf(ictx, "%s Key dict offset (blocks): %i\n", stat[!!ret],
+ hdr->key_dictionary_block);
+ if (ret)
+ return ret;
+
+ if (hdr->key_count != 1)
+ ret = -EINVAL;
+ soprintf(ictx, "%s Number of encryption keys: %i\n", stat[!!ret],
+ hdr->key_count);
+ if (ret)
+ return ret;
+
+ sz = hdr->header_blocks + hdr->section_header_size * hdr->section_count;
+ sz += hdr->key_count *
+ sizeof(struct sb_key_dictionary_key) / SB_BLOCK_SIZE;
+ if (hdr->first_boot_tag_block != (unsigned)sz)
+ ret = -EINVAL;
+ soprintf(ictx, "%s First TAG block (blocks): %i\n", stat[!!ret],
+ hdr->first_boot_tag_block);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void sb_decrypt_tag(struct sb_image_ctx *ictx,
+ struct sb_cmd_ctx *cctx)
+{
+ EVP_MD_CTX *md_ctx = &ictx->md_ctx;
+ struct sb_command *cmd = &cctx->payload;
+
+ sb_aes_crypt(ictx, (uint8_t *)&cctx->c_payload,
+ (uint8_t *)&cctx->payload, sizeof(*cmd));
+ EVP_DigestUpdate(md_ctx, &cctx->c_payload, sizeof(*cmd));
+}
+
+static int sb_verify_command(struct sb_image_ctx *ictx,
+ struct sb_cmd_ctx *cctx, FILE *fp,
+ unsigned long *tsize)
+{
+ struct sb_command *ccmd = &cctx->payload;
+ unsigned long size, asize;
+ char *csum, *flag = "";
+ int ret;
+ unsigned int i;
+ uint8_t csn, csc = ccmd->header.checksum;
+ ccmd->header.checksum = 0x5a;
+ csn = sb_command_checksum(ccmd);
+ ccmd->header.checksum = csc;
+
+ if (csc == csn)
+ ret = 0;
+ else
+ ret = -EINVAL;
+ csum = ret ? "checksum BAD" : "checksum OK";
+
+ switch (ccmd->header.tag) {
+ case ROM_NOP_CMD:
+ soprintf(ictx, " NOOP # %s\n", csum);
+ return ret;
+ case ROM_TAG_CMD:
+ if (ccmd->header.flags & ROM_TAG_CMD_FLAG_ROM_LAST_TAG)
+ flag = "LAST";
+ soprintf(ictx, " TAG %s # %s\n", flag, csum);
+ sb_aes_reinit(ictx, 0);
+ return ret;
+ case ROM_LOAD_CMD:
+ soprintf(ictx, " LOAD addr=0x%08x length=0x%08x # %s\n",
+ ccmd->load.address, ccmd->load.count, csum);
+
+ cctx->length = ccmd->load.count;
+ asize = roundup(cctx->length, SB_BLOCK_SIZE);
+ cctx->data = malloc(asize);
+ if (!cctx->data)
+ return -ENOMEM;
+
+ size = fread(cctx->data, 1, asize, fp);
+ if (size != asize) {
+ fprintf(stderr,
+ "ERR: SB LOAD command payload too short!\n");
+ return -EINVAL;
+ }
+
+ *tsize += size;
+
+ EVP_DigestUpdate(&ictx->md_ctx, cctx->data, asize);
+ sb_aes_crypt(ictx, cctx->data, cctx->data, asize);
+
+ if (ccmd->load.crc32 != crc32(cctx->data, asize)) {
+ fprintf(stderr,
+ "ERR: SB LOAD command payload CRC32 invalid!\n");
+ return -EINVAL;
+ }
+ return 0;
+ case ROM_FILL_CMD:
+ soprintf(ictx,
+ " FILL addr=0x%08x length=0x%08x pattern=0x%08x # %s\n",
+ ccmd->fill.address, ccmd->fill.count,
+ ccmd->fill.pattern, csum);
+ return 0;
+ case ROM_JUMP_CMD:
+ if (ccmd->header.flags & ROM_JUMP_CMD_FLAG_HAB)
+ flag = " HAB";
+ soprintf(ictx,
+ " JUMP%s addr=0x%08x r0_arg=0x%08x # %s\n",
+ flag, ccmd->fill.address, ccmd->jump.argument, csum);
+ return 0;
+ case ROM_CALL_CMD:
+ if (ccmd->header.flags & ROM_CALL_CMD_FLAG_HAB)
+ flag = " HAB";
+ soprintf(ictx,
+ " CALL%s addr=0x%08x r0_arg=0x%08x # %s\n",
+ flag, ccmd->fill.address, ccmd->jump.argument, csum);
+ return 0;
+ case ROM_MODE_CMD:
+ for (i = 0; i < ARRAY_SIZE(modetable); i++) {
+ if (ccmd->mode.mode == modetable[i].mode) {
+ soprintf(ictx, " MODE %s # %s\n",
+ modetable[i].name, csum);
+ break;
+ }
+ }
+ fprintf(stderr, " MODE !INVALID! # %s\n", csum);
+ return 0;
+ }
+
+ return ret;
+}
+
+static int sb_verify_commands(struct sb_image_ctx *ictx,
+ struct sb_section_ctx *sctx, FILE *fp)
+{
+ unsigned long size, tsize = 0;
+ struct sb_cmd_ctx *cctx;
+ int ret;
+
+ sb_aes_reinit(ictx, 0);
+
+ while (tsize < sctx->size) {
+ cctx = calloc(1, sizeof(*cctx));
+ if (!cctx)
+ return -ENOMEM;
+ if (!sctx->cmd_head) {
+ sctx->cmd_head = cctx;
+ sctx->cmd_tail = cctx;
+ } else {
+ sctx->cmd_tail->cmd = cctx;
+ sctx->cmd_tail = cctx;
+ }
+
+ size = fread(&cctx->c_payload, 1, sizeof(cctx->c_payload), fp);
+ if (size != sizeof(cctx->c_payload)) {
+ fprintf(stderr, "ERR: SB command header too short!\n");
+ return -EINVAL;
+ }
+
+ tsize += size;
+
+ sb_decrypt_tag(ictx, cctx);
+
+ ret = sb_verify_command(ictx, cctx, fp, &tsize);
+ if (ret)
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int sb_verify_sections_cmds(struct sb_image_ctx *ictx, FILE *fp)
+{
+ struct sb_boot_image_header *hdr = &ictx->payload;
+ struct sb_sections_header *shdr;
+ unsigned int i;
+ int ret;
+ struct sb_section_ctx *sctx;
+ unsigned long size;
+ char *bootable = "";
+
+ soprintf(ictx, "----- Verifying SB Sections and Commands -----\n");
+
+ for (i = 0; i < hdr->section_count; i++) {
+ sctx = calloc(1, sizeof(*sctx));
+ if (!sctx)
+ return -ENOMEM;
+ if (!ictx->sect_head) {
+ ictx->sect_head = sctx;
+ ictx->sect_tail = sctx;
+ } else {
+ ictx->sect_tail->sect = sctx;
+ ictx->sect_tail = sctx;
+ }
+
+ size = fread(&sctx->payload, 1, sizeof(sctx->payload), fp);
+ if (size != sizeof(sctx->payload)) {
+ fprintf(stderr, "ERR: SB section header too short!\n");
+ return -EINVAL;
+ }
+ }
+
+ size = fread(&ictx->sb_dict_key, 1, sizeof(ictx->sb_dict_key), fp);
+ if (size != sizeof(ictx->sb_dict_key)) {
+ fprintf(stderr, "ERR: SB key dictionary too short!\n");
+ return -EINVAL;
+ }
+
+ sb_encrypt_sb_sections_header(ictx);
+ sb_aes_reinit(ictx, 0);
+ sb_decrypt_key_dictionary_key(ictx);
+
+ sb_aes_reinit(ictx, 0);
+
+ sctx = ictx->sect_head;
+ while (sctx) {
+ shdr = &sctx->payload;
+
+ if (shdr->section_flags & SB_SECTION_FLAG_BOOTABLE) {
+ sctx->boot = 1;
+ bootable = " BOOTABLE";
+ }
+
+ sctx->size = (shdr->section_size * SB_BLOCK_SIZE) +
+ sizeof(struct sb_command);
+ soprintf(ictx, "SECTION 0x%x%s # size = %i bytes\n",
+ shdr->section_number, bootable, sctx->size);
+
+ if (shdr->section_flags & ~SB_SECTION_FLAG_BOOTABLE)
+ fprintf(stderr, " WARN: Unknown section flag(s) %08x\n",
+ shdr->section_flags);
+
+ if ((shdr->section_flags & SB_SECTION_FLAG_BOOTABLE) &&
+ (hdr->first_boot_section_id != shdr->section_number)) {
+ fprintf(stderr,
+ " WARN: Bootable section does ID not match image header ID!\n");
+ }
+
+ ret = sb_verify_commands(ictx, sctx, fp);
+ if (ret)
+ return ret;
+
+ sctx = sctx->sect;
+ }
+
+ /*
+ * FIXME IDEA:
+ * check if the first TAG command is at sctx->section_offset
+ */
+ return 0;
+}
+
+static int sb_verify_image_end(struct sb_image_ctx *ictx,
+ FILE *fp, off_t filesz)
+{
+ uint8_t digest[32];
+ unsigned long size;
+ off_t pos;
+ int ret;
+
+ soprintf(ictx, "------------- Verifying image end -------------\n");
+
+ size = fread(digest, 1, sizeof(digest), fp);
+ if (size != sizeof(digest)) {
+ fprintf(stderr, "ERR: SB key dictionary too short!\n");
+ return -EINVAL;
+ }
+
+ pos = ftell(fp);
+ if (pos != filesz) {
+ fprintf(stderr, "ERR: Trailing data past the image!\n");
+ return -EINVAL;
+ }
+
+ /* Check the image digest. */
+ EVP_DigestFinal(&ictx->md_ctx, ictx->digest, NULL);
+
+ /* Decrypt the image digest from the input image. */
+ sb_aes_reinit(ictx, 0);
+ sb_aes_crypt(ictx, digest, digest, sizeof(digest));
+
+ /* Check all of 20 bytes of the SHA1 hash. */
+ ret = memcmp(digest, ictx->digest, 20) ? -EINVAL : 0;
+
+ if (ret)
+ soprintf(ictx, "[FAIL] Full-image checksum: BAD\n");
+ else
+ soprintf(ictx, "[PASS] Full-image checksum: OK\n");
+
+ return ret;
+}
+
+
+static int sb_build_tree_from_img(struct sb_image_ctx *ictx)
+{
+ long filesize;
+ int ret;
+ FILE *fp;
+
+ if (!ictx->input_filename) {
+ fprintf(stderr, "ERR: Missing filename!\n");
+ return -EINVAL;
+ }
+
+ fp = fopen(ictx->input_filename, "r");
+ if (!fp)
+ goto err_open;
+
+ ret = fseek(fp, 0, SEEK_END);
+ if (ret < 0)
+ goto err_file;
+
+ filesize = ftell(fp);
+ if (filesize < 0)
+ goto err_file;
+
+ ret = fseek(fp, 0, SEEK_SET);
+ if (ret < 0)
+ goto err_file;
+
+ if (filesize < (signed)sizeof(ictx->payload)) {
+ fprintf(stderr, "ERR: File too short!\n");
+ goto err_file;
+ }
+
+ if (filesize & (SB_BLOCK_SIZE - 1)) {
+ fprintf(stderr, "ERR: The file is not aligned!\n");
+ goto err_file;
+ }
+
+ /* Load and verify image header */
+ ret = sb_verify_image_header(ictx, fp, filesize);
+ if (ret)
+ goto err_verify;
+
+ /* Load and verify sections and commands */
+ ret = sb_verify_sections_cmds(ictx, fp);
+ if (ret)
+ goto err_verify;
+
+ ret = sb_verify_image_end(ictx, fp, filesize);
+ if (ret)
+ goto err_verify;
+
+ ret = 0;
+
+err_verify:
+ soprintf(ictx, "-------------------- Result -------------------\n");
+ soprintf(ictx, "Verification %s\n", ret ? "FAILED" : "PASSED");
+
+ /* Stop the encryption session. */
+ sb_aes_deinit(&ictx->cipher_ctx);
+
+ fclose(fp);
+ return ret;
+
+err_file:
+ fclose(fp);
+err_open:
+ fprintf(stderr, "ERR: Failed to load file \"%s\"\n",
+ ictx->input_filename);
+ return -EINVAL;
+}
+
+static void sb_free_image(struct sb_image_ctx *ictx)
+{
+ struct sb_section_ctx *sctx = ictx->sect_head, *s_head;
+ struct sb_dcd_ctx *dctx = ictx->dcd_head, *d_head;
+ struct sb_cmd_ctx *cctx, *c_head;
+
+ while (sctx) {
+ s_head = sctx;
+ c_head = sctx->cmd_head;
+
+ while (c_head) {
+ cctx = c_head;
+ c_head = c_head->cmd;
+ if (cctx->data)
+ free(cctx->data);
+ free(cctx);
+ }
+
+ sctx = sctx->sect;
+ free(s_head);
+ }
+
+ while (dctx) {
+ d_head = dctx;
+ dctx = dctx->dcd;
+ free(d_head->payload);
+ free(d_head);
+ }
+}
+
+/*
+ * MXSSB-MKIMAGE glue code.
+ */
+static int mxsimage_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_MXSIMAGE)
+ return EXIT_SUCCESS;
+ else
+ return EXIT_FAILURE;
+}
+
+static void mxsimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+ struct mkimage_params *params)
+{
+}
+
+int mxsimage_check_params(struct mkimage_params *params)
+{
+ if (!params)
+ return -1;
+ if (!strlen(params->imagename)) {
+ fprintf(stderr,
+ "Error: %s - Configuration file not specified, it is needed for mxsimage generation\n",
+ params->cmdname);
+ return -1;
+ }
+
+ /*
+ * Check parameters:
+ * XIP is not allowed and verify that incompatible
+ * parameters are not sent at the same time
+ * For example, if list is required a data image must not be provided
+ */
+ return (params->dflag && (params->fflag || params->lflag)) ||
+ (params->fflag && (params->dflag || params->lflag)) ||
+ (params->lflag && (params->dflag || params->fflag)) ||
+ (params->xflag) || !(strlen(params->imagename));
+}
+
+static int mxsimage_verify_print_header(char *file, int silent)
+{
+ int ret;
+ struct sb_image_ctx ctx;
+
+ memset(&ctx, 0, sizeof(ctx));
+
+ ctx.input_filename = file;
+ ctx.silent_dump = silent;
+
+ ret = sb_build_tree_from_img(&ctx);
+ sb_free_image(&ctx);
+
+ return ret;
+}
+
+char *imagefile;
+static int mxsimage_verify_header(unsigned char *ptr, int image_size,
+ struct mkimage_params *params)
+{
+ struct sb_boot_image_header *hdr;
+
+ if (!ptr)
+ return -EINVAL;
+
+ hdr = (struct sb_boot_image_header *)ptr;
+
+ /*
+ * Check if the header contains the MXS image signatures,
+ * if so, do a full-image verification.
+ */
+ if (memcmp(hdr->signature1, "STMP", 4) ||
+ memcmp(hdr->signature2, "sgtl", 4))
+ return -EINVAL;
+
+ imagefile = params->imagefile;
+
+ return mxsimage_verify_print_header(params->imagefile, 1);
+}
+
+static void mxsimage_print_header(const void *hdr)
+{
+ if (imagefile)
+ mxsimage_verify_print_header(imagefile, 0);
+}
+
+static int sb_build_image(struct sb_image_ctx *ictx,
+ struct image_type_params *tparams)
+{
+ struct sb_boot_image_header *sb_header = &ictx->payload;
+ struct sb_section_ctx *sctx;
+ struct sb_cmd_ctx *cctx;
+ struct sb_command *ccmd;
+ struct sb_key_dictionary_key *sb_dict_key = &ictx->sb_dict_key;
+
+ uint8_t *image, *iptr;
+
+ /* Calculate image size. */
+ uint32_t size = sizeof(*sb_header) +
+ ictx->sect_count * sizeof(struct sb_sections_header) +
+ sizeof(*sb_dict_key) + sizeof(ictx->digest);
+
+ sctx = ictx->sect_head;
+ while (sctx) {
+ size += sctx->size;
+ sctx = sctx->sect;
+ };
+
+ image = malloc(size);
+ if (!image)
+ return -ENOMEM;
+ iptr = image;
+
+ memcpy(iptr, sb_header, sizeof(*sb_header));
+ iptr += sizeof(*sb_header);
+
+ sctx = ictx->sect_head;
+ while (sctx) {
+ memcpy(iptr, &sctx->payload, sizeof(struct sb_sections_header));
+ iptr += sizeof(struct sb_sections_header);
+ sctx = sctx->sect;
+ };
+
+ memcpy(iptr, sb_dict_key, sizeof(*sb_dict_key));
+ iptr += sizeof(*sb_dict_key);
+
+ sctx = ictx->sect_head;
+ while (sctx) {
+ cctx = sctx->cmd_head;
+ while (cctx) {
+ ccmd = &cctx->payload;
+
+ memcpy(iptr, &cctx->c_payload, sizeof(cctx->payload));
+ iptr += sizeof(cctx->payload);
+
+ if (ccmd->header.tag == ROM_LOAD_CMD) {
+ memcpy(iptr, cctx->data, cctx->length);
+ iptr += cctx->length;
+ }
+
+ cctx = cctx->cmd;
+ }
+
+ sctx = sctx->sect;
+ };
+
+ memcpy(iptr, ictx->digest, sizeof(ictx->digest));
+ iptr += sizeof(ictx->digest);
+
+ /* Configure the mkimage */
+ tparams->hdr = image;
+ tparams->header_size = size;
+
+ return 0;
+}
+
+static int mxsimage_generate(struct mkimage_params *params,
+ struct image_type_params *tparams)
+{
+ int ret;
+ struct sb_image_ctx ctx;
+
+ /* Do not copy the U-Boot image! */
+ params->skipcpy = 1;
+
+ memset(&ctx, 0, sizeof(ctx));
+
+ ctx.cfg_filename = params->imagename;
+ ctx.output_filename = params->imagefile;
+ ctx.verbose_boot = 1;
+
+ ret = sb_build_tree_from_cfg(&ctx);
+ if (ret)
+ goto fail;
+
+ ret = sb_encrypt_image(&ctx);
+ if (!ret)
+ ret = sb_build_image(&ctx, tparams);
+
+fail:
+ sb_free_image(&ctx);
+
+ return ret;
+}
+
+/*
+ * mxsimage parameters
+ */
+static struct image_type_params mxsimage_params = {
+ .name = "Freescale MXS Boot Image support",
+ .header_size = 0,
+ .hdr = NULL,
+ .check_image_type = mxsimage_check_image_types,
+ .verify_header = mxsimage_verify_header,
+ .print_header = mxsimage_print_header,
+ .set_header = mxsimage_set_header,
+ .check_params = mxsimage_check_params,
+ .vrec_header = mxsimage_generate,
+};
+
+void init_mxs_image_type(void)
+{
+ mkimage_register(&mxsimage_params);
+}
+
+#else
+void init_mxs_image_type(void)
+{
+}
+#endif
--- /dev/null
+/*
+ * Freescale i.MX28 SB image generator
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MXSSB_H__
+#define __MXSSB_H__
+
+#include <stdint.h>
+#include <arpa/inet.h>
+
+#define SB_BLOCK_SIZE 16
+
+#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+struct sb_boot_image_version {
+ uint16_t major;
+ uint16_t pad0;
+ uint16_t minor;
+ uint16_t pad1;
+ uint16_t revision;
+ uint16_t pad2;
+};
+
+struct sb_boot_image_header {
+ union {
+ /* SHA1 of the header. */
+ uint8_t digest[20];
+ struct {
+ /* CBC-MAC initialization vector. */
+ uint8_t iv[16];
+ uint8_t extra[4];
+ };
+ };
+ /* 'STMP' */
+ uint8_t signature1[4];
+ /* Major version of the image format. */
+ uint8_t major_version;
+ /* Minor version of the image format. */
+ uint8_t minor_version;
+ /* Flags associated with the image. */
+ uint16_t flags;
+ /* Size of the image in 16b blocks. */
+ uint32_t image_blocks;
+ /* Offset of the first tag in 16b blocks. */
+ uint32_t first_boot_tag_block;
+ /* ID of the section to boot from. */
+ uint32_t first_boot_section_id;
+ /* Amount of crypto keys. */
+ uint16_t key_count;
+ /* Offset to the key dictionary in 16b blocks. */
+ uint16_t key_dictionary_block;
+ /* Size of this header in 16b blocks. */
+ uint16_t header_blocks;
+ /* Amount of section headers. */
+ uint16_t section_count;
+ /* Section header size in 16b blocks. */
+ uint16_t section_header_size;
+ /* Padding to align timestamp to uint64_t. */
+ uint8_t padding0[2];
+ /* 'sgtl' (since v1.1) */
+ uint8_t signature2[4];
+ /* Image generation date, in microseconds since 1.1.2000 . */
+ uint64_t timestamp_us;
+ /* Product version. */
+ struct sb_boot_image_version
+ product_version;
+ /* Component version. */
+ struct sb_boot_image_version
+ component_version;
+ /* Drive tag for the system drive. (since v1.1) */
+ uint16_t drive_tag;
+ /* Padding. */
+ uint8_t padding1[6];
+};
+
+#define SB_VERSION_MAJOR 1
+#define SB_VERSION_MINOR 1
+
+/* Enable to HTLLC verbose boot report. */
+#define SB_IMAGE_FLAG_VERBOSE (1 << 0)
+
+struct sb_key_dictionary_key {
+ /* The CBC-MAC of image and sections header. */
+ uint8_t cbc_mac[SB_BLOCK_SIZE];
+ /* The AES key encrypted by image key (zero). */
+ uint8_t key[SB_BLOCK_SIZE];
+};
+
+struct sb_ivt_header {
+ uint32_t header;
+ uint32_t entry;
+ uint32_t reserved1;
+ uint32_t dcd;
+ uint32_t boot_data;
+ uint32_t self;
+ uint32_t csf;
+ uint32_t reserved2;
+};
+
+#define SB_HAB_IVT_TAG 0xd1UL
+#define SB_HAB_DCD_TAG 0xd2UL
+
+#define SB_HAB_VERSION 0x40UL
+
+/*
+ * The "size" field in the IVT header is not naturally aligned,
+ * use this macro to fill first 4 bytes of the IVT header without
+ * causing issues on some systems (esp. M68k, PPC, MIPS-BE, ARM-BE).
+ */
+static inline uint32_t sb_hab_ivt_header(void)
+{
+ uint32_t ret = 0;
+ ret |= SB_HAB_IVT_TAG << 24;
+ ret |= sizeof(struct sb_ivt_header) << 16;
+ ret |= SB_HAB_VERSION;
+ return htonl(ret);
+}
+
+struct sb_sections_header {
+ /* Section number. */
+ uint32_t section_number;
+ /* Offset of this sections first instruction after "TAG". */
+ uint32_t section_offset;
+ /* Size of the section in 16b blocks. */
+ uint32_t section_size;
+ /* Section flags. */
+ uint32_t section_flags;
+};
+
+#define SB_SECTION_FLAG_BOOTABLE (1 << 0)
+
+struct sb_command {
+ struct {
+ uint8_t checksum;
+ uint8_t tag;
+ uint16_t flags;
+#define ROM_TAG_CMD_FLAG_ROM_LAST_TAG 0x1
+#define ROM_LOAD_CMD_FLAG_DCD_LOAD 0x1 /* MX28 only */
+#define ROM_JUMP_CMD_FLAG_HAB 0x1 /* MX28 only */
+#define ROM_CALL_CMD_FLAG_HAB 0x1 /* MX28 only */
+ } header;
+
+ union {
+ struct {
+ uint32_t reserved[3];
+ } nop;
+ struct {
+ uint32_t section_number;
+ uint32_t section_length;
+ uint32_t section_flags;
+ } tag;
+ struct {
+ uint32_t address;
+ uint32_t count;
+ uint32_t crc32;
+ } load;
+ struct {
+ uint32_t address;
+ uint32_t count;
+ uint32_t pattern;
+ } fill;
+ struct {
+ uint32_t address;
+ uint32_t reserved;
+ /* Passed in register r0 before JUMP */
+ uint32_t argument;
+ } jump;
+ struct {
+ uint32_t address;
+ uint32_t reserved;
+ /* Passed in register r0 before CALL */
+ uint32_t argument;
+ } call;
+ struct {
+ uint32_t reserved1;
+ uint32_t reserved2;
+ uint32_t mode;
+ } mode;
+
+ };
+};
+
+/*
+ * Most of the mode names are same or at least similar
+ * on i.MX23 and i.MX28, but some of the mode names
+ * differ. The "name" field represents the mode name
+ * on i.MX28 as seen in Table 12-2 of the datasheet.
+ * The "altname" field represents the differently named
+ * fields on i.MX23 as seen in Table 35-3 of the
+ * datasheet.
+ */
+static const struct {
+ const char *name;
+ const char *altname;
+ const uint8_t mode;
+} modetable[] = {
+ { "USB", NULL, 0x00 },
+ { "I2C", NULL, 0x01 },
+ { "SPI2_FLASH", "SPI1_FLASH", 0x02 },
+ { "SPI3_FLASH", "SPI2_FLASH", 0x03 },
+ { "NAND_BCH", NULL, 0x04 },
+ { "JTAG", NULL, 0x06 },
+ { "SPI3_EEPROM", "SPI2_EEPROM", 0x08 },
+ { "SD_SSP0", NULL, 0x09 },
+ { "SD_SSP1", NULL, 0x0A }
+};
+
+enum sb_tag {
+ ROM_NOP_CMD = 0x00,
+ ROM_TAG_CMD = 0x01,
+ ROM_LOAD_CMD = 0x02,
+ ROM_FILL_CMD = 0x03,
+ ROM_JUMP_CMD = 0x04,
+ ROM_CALL_CMD = 0x05,
+ ROM_MODE_CMD = 0x06
+};
+
+struct sb_source_entry {
+ uint8_t tag;
+ uint32_t address;
+ uint32_t flags;
+ char *filename;
+};
+
+#endif /* __MXSSB_H__ */
--- /dev/null
+#! /usr/bin/python
+########################################################################
+#
+# reorder and reformat a file in columns
+#
+# this utility takes lines from its standard input and reproduces them,
+# partially reordered and reformatted, on its standard output.
+#
+# It has the same effect as a 'sort | column -t', with the exception
+# that empty lines, as well as lines which start with a '#' sign, are
+# not affected, i.e. they keep their position and formatting, and act
+# as separators, i.e. the parts before and after them are each sorted
+# separately (but overall field widths are computed across the whole
+# input).
+#
+# Options:
+# -i:
+# --ignore-case:
+# Do not consider case when sorting.
+# -d:
+# --default:
+# What to chage empty fields to.
+# -s <N>:
+# --split=<N>:
+# Treat only the first N whitespace sequences as separators.
+# line content after the Nth separator will count as only one
+# field even if it contains whitespace.
+# Example : '-s 2' causes input 'a b c d e' to be split into
+# three fields, 'a', 'b', and 'c d e'.
+#
+# boards.cfg requires -ids 6.
+#
+########################################################################
+
+import sys, getopt, locale
+
+# ensure we sort using the C locale.
+
+locale.setlocale(locale.LC_ALL, 'C')
+
+# check options
+
+maxsplit = 0
+ignore_case = 0
+default_field =''
+
+try:
+ opts, args = getopt.getopt(sys.argv[1:], "id:s:",
+ ["ignore-case","default","split="])
+except getopt.GetoptError as err:
+ print str(err) # will print something like "option -a not recognized"
+ sys.exit(2)
+
+for o, a in opts:
+ if o in ("-s", "--split"):
+ maxsplit = eval(a)
+ elif o in ("-i", "--ignore-case"):
+ ignore_case = 1
+ elif o in ("-d", "--default"):
+ default_field = a
+ else:
+ assert False, "unhandled option"
+
+# collect all lines from standard input and, for the ones which must be
+# reformatted and sorted, count their fields and compute each field's
+# maximum size
+
+input_lines = []
+field_width = []
+
+for line in sys.stdin:
+ # remove final end of line
+ input_line = line.strip('\n')
+ if (len(input_line)>0) and (input_line[0] != '#'):
+ # sortable line: split into fields
+ fields = input_line.split(None,maxsplit)
+ # if there are new fields, top up field_widths
+ for f in range(len(field_width), len(fields)):
+ field_width.append(0)
+ # compute the maximum witdh of each field
+ for f in range(len(fields)):
+ field_width[f] = max(field_width[f],len(fields[f]))
+ # collect the line for next stage
+ input_lines.append(input_line)
+
+# run through collected input lines, collect the ones which must be
+# reformatted and sorted, and whenever a non-reformattable, non-sortable
+# line is met, sort the collected lines before it and append them to the
+# output lines, then add the non-sortable line too.
+
+output_lines = []
+sortable_lines = []
+for input_line in input_lines:
+ if (len(input_line)>0) and (input_line[0] != '#'):
+ # this line should be reformatted and sorted
+ input_fields = input_line.split(None,maxsplit)
+ output_fields = [];
+ # reformat each field to this field's column width
+ for f in range(len(input_fields)):
+ output_field = input_fields[f];
+ output_fields.append(output_field.ljust(field_width[f]))
+ # any missing field is set to default if it exists
+ if default_field != '':
+ for f in range(len(input_fields),len(field_width)):
+ output_fields.append(default_field.ljust(field_width[f]))
+ # join fields using two spaces, like column -t would
+ output_line = ' '.join(output_fields);
+ # collect line for later
+ sortable_lines.append(output_line)
+ else:
+ # this line is non-sortable
+ # sort collected sortable lines
+ if ignore_case!=0:
+ sortable_lines.sort(key=lambda x: str.lower(locale.strxfrm(x)))
+ else:
+ sortable_lines.sort(key=lambda x: locale.strxfrm(x))
+ # append sortable lines to the final output
+ output_lines.extend(sortable_lines)
+ sortable_lines = []
+ # append non-sortable line to the final output
+ output_lines.append(input_line)
+# maybe we had sortable lines pending, so append them to the final output
+if ignore_case!=0:
+ sortable_lines.sort(key=lambda x: str.lower(locale.strxfrm(x)))
+else:
+ sortable_lines.sort(key=lambda x: locale.strxfrm(x))
+output_lines.extend(sortable_lines)
+
+# run through output lines and print them, except rightmost whitespace
+
+for output_line in output_lines:
+ print output_line.rstrip()
projects / karo-tx-uboot.git / commitdiff
