board-specific files to invoke that common implementation.
+======================================================================
+Changes since U-Boot 1.0.1:
+======================================================================
+
+* Add a common get_ram_size() function and modify the the
+ board-specific files to invoke that common implementation.
+
======================================================================
Changes for U-Boot 1.0.1:
======================================================================
#define _NOT_USED_ 0xFFFFFFFF
-const uint init_sdram_table[] =
-{
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
- 0xFFFFFC04, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, /* last */
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
- 0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
- 0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
+const uint init_sdram_table[] = {
+ /*
+ * Single Read. (Offset 0 in UPMA RAM)
+ */
+ 0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
+ 0xFFFFFC04, /* last */
+ /*
+ * SDRAM Initialization (offset 5 in UPMA RAM)
+ *
+ * This is no UPM entry point. The following definition uses
+ * the remaining space to establish an initialization
+ * sequence, which is executed by a RUN command.
+ *
+ */
+ 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, /* last */
+ /*
+ * Burst Read. (Offset 8 in UPMA RAM)
+ */
+ 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+ 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+ 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
+ 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
+ /*
+ * Single Write. (Offset 18 in UPMA RAM)
+ */
+ 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
+ 0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
+ /*
+ * Burst Write. (Offset 20 in UPMA RAM)
+ */
+ 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+ 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
+ 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
+ 0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
};
-const uint sdram_table[] =
-{
- /*
- * Single Read. (Offset 0 in UPMA RAM)
- */
- 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
- 0xFF0FFC00, /* last */
- /*
- * SDRAM Initialization (offset 5 in UPMA RAM)
- *
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
- *
- */
- 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */
- /*
- * Burst Read. (Offset 8 in UPMA RAM)
- */
- 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
- 0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
- 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
- 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
- /*
- * Single Write. (Offset 18 in UPMA RAM)
- */
- 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
- 0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */
- _NOT_USED_,
- /*
- * Burst Write. (Offset 20 in UPMA RAM)
- */
- 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
- 0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
- 0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
- 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
- /*
- * Refresh (Offset 30 in UPMA RAM)
- */
- 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
- 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
- /*
- * Exception. (Offset 3c in UPMA RAM)
- */
- 0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
+const uint sdram_table[] = {
+ /*
+ * Single Read. (Offset 0 in UPMA RAM)
+ */
+ 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
+ 0xFF0FFC00, /* last */
+ /*
+ * SDRAM Initialization (offset 5 in UPMA RAM)
+ *
+ * This is no UPM entry point. The following definition uses
+ * the remaining space to establish an initialization
+ * sequence, which is executed by a RUN command.
+ *
+ */
+ 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */
+ /*
+ * Burst Read. (Offset 8 in UPMA RAM)
+ */
+ 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
+ 0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
+ 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
+ 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
+ /*
+ * Single Write. (Offset 18 in UPMA RAM)
+ */
+ 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
+ 0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */
+ _NOT_USED_,
+ /*
+ * Burst Write. (Offset 20 in UPMA RAM)
+ */
+ 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
+ 0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
+ 0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
+ 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
+ /*
+ * Refresh (Offset 30 in UPMA RAM)
+ */
+ 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+ 0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
+ 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
+ /*
+ * Exception. (Offset 3c in UPMA RAM)
+ */
+ 0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
};
/* ------------------------------------------------------------------------- */
/*
* Very early board init code (fpga boot, etc.)
*/
-int
-board_pre_init (void)
+int board_pre_init (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
- /*
- * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
- */
- immr->im_ioport.iop_pcdat &= ~CFG_DS1; /* PCDAT (DS1 = 0) */
- immr->im_ioport.iop_pcpar &= ~CFG_DS1; /* PCPAR (0=general purpose I/O) */
- immr->im_ioport.iop_pcdir |= CFG_DS1; /* PCDIR (I/O: 0=input, 1=output) */
+ /*
+ * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
+ */
+ immr->im_ioport.iop_pcdat &= ~CFG_DS1; /* PCDAT (DS1 = 0) */
+ immr->im_ioport.iop_pcpar &= ~CFG_DS1; /* PCPAR (0=general purpose I/O) */
+ immr->im_ioport.iop_pcdir |= CFG_DS1; /* PCDIR (I/O: 0=input, 1=output) */
- return ( 0 ); /* success */
+ return (0); /* success */
}
/*
* Return 1 if no second DRAM bank, otherwise returns 0
*/
-int
-checkboard (void)
+int checkboard (void)
{
- unsigned char *s = getenv("serial#");
+ unsigned char *s = getenv ("serial#");
- if ( !s || strncmp(s, "ELPT860", 7) )
- printf ("### No HW ID - assuming ELPT860\n");
+ if (!s || strncmp (s, "ELPT860", 7))
+ printf ("### No HW ID - assuming ELPT860\n");
- return ( 0 ); /* success */
+ return (0); /* success */
}
/* ------------------------------------------------------------------------- */
-long int
-initdram (int board_type)
+long int initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size8, size9;
- long int size_b0 = 0;
-
- /*
- * This sequence initializes SDRAM chips on ELPT860 board
- */
- upmconfig(UPMA, (uint *)init_sdram_table,
- sizeof(init_sdram_table)/sizeof(uint));
-
- memctl->memc_mptpr = 0x0200;
- memctl->memc_mamr = 0x18002111;
-
- memctl->memc_mar = 0x00000088;
- memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */
-
- upmconfig(UPMA, (uint *)sdram_table,
- sizeof(sdram_table)/sizeof(uint));
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
-
- /*
- * The following value is used as an address (i.e. opcode) for
- * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
- * the port size is 32bit the SDRAM does NOT "see" the lower two
- * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
- * MICRON SDRAMs:
- * -> 0 00 010 0 010
- * | | | | +- Burst Length = 4
- * | | | +----- Burst Type = Sequential
- * | | +------- CAS Latency = 2
- * | +----------- Operating Mode = Standard
- * +-------------- Write Burst Mode = Programmed Burst Length
- */
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
- * preliminary addresses - these have to be modified after the
- * SDRAM size has been determined.
- */
- memctl->memc_or1 = CFG_OR1_PRELIM;
- memctl->memc_br1 = CFG_BR1_PRELIM;
-
- memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */
- udelay (1);
- memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */
- udelay (1);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay (1000);
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CFG_MAMR_8COL,
- (ulong *) SDRAM_BASE1_PRELIM,
- SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CFG_MAMR_9COL,
- (ulong *) SDRAM_BASE1_PRELIM,
- SDRAM_MAX_SIZE);
-
- if ( size8 < size9 ) /* leave configuration at 9 columns */
- {
- size_b0 = size9;
- /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
- }
- else /* back to 8 columns */
- {
- size_b0 = size8;
- memctl->memc_mamr = CFG_MAMR_8COL;
- udelay (500);
- /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
- }
-
- udelay (1000);
-
- /*
- * Adjust refresh rate depending on SDRAM type, both banks
- * For types > 128 MBit leave it at the current (fast) rate
- */
- if ( size_b0 < 0x02000000 )
- {
- /* reduce to 15.6 us (62.4 us / quad) */
- memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size8, size9;
+ long int size_b0 = 0;
+
+ /*
+ * This sequence initializes SDRAM chips on ELPT860 board
+ */
+ upmconfig (UPMA, (uint *) init_sdram_table,
+ sizeof (init_sdram_table) / sizeof (uint));
+
+ memctl->memc_mptpr = 0x0200;
+ memctl->memc_mamr = 0x18002111;
+
+ memctl->memc_mar = 0x00000088;
+ memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */
+
+ upmconfig (UPMA, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
+
+ /*
+ * Preliminary prescaler for refresh (depends on number of
+ * banks): This value is selected for four cycles every 62.4 us
+ * with two SDRAM banks or four cycles every 31.2 us with one
+ * bank. It will be adjusted after memory sizing.
+ */
+ memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+ /*
+ * The following value is used as an address (i.e. opcode) for
+ * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
+ * the port size is 32bit the SDRAM does NOT "see" the lower two
+ * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
+ * MICRON SDRAMs:
+ * -> 0 00 010 0 010
+ * | | | | +- Burst Length = 4
+ * | | | +----- Burst Type = Sequential
+ * | | +------- CAS Latency = 2
+ * | +----------- Operating Mode = Standard
+ * +-------------- Write Burst Mode = Programmed Burst Length
+ */
+ memctl->memc_mar = 0x00000088;
+
+ /*
+ * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+ * preliminary addresses - these have to be modified after the
+ * SDRAM size has been determined.
+ */
+ memctl->memc_or1 = CFG_OR1_PRELIM;
+ memctl->memc_br1 = CFG_BR1_PRELIM;
+
+ memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+
+ udelay (200);
+
+ /* perform SDRAM initializsation sequence */
+
+ memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */
+ udelay (1);
+ memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */
+ udelay (1);
+
+ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+
+ udelay (1000);
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ *
+ * try 8 column mode
+ */
+ size8 = dram_size (CFG_MAMR_8COL,
+ (ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+
udelay (1000);
- }
- /*
- * Final mapping: map bigger bank first
- */
- memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
- memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+ /*
+ * try 9 column mode
+ */
+ size9 = dram_size (CFG_MAMR_9COL,
+ (ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+
+ if (size8 < size9) { /* leave configuration at 9 columns */
+ size_b0 = size9;
+ /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
+ } else { /* back to 8 columns */
+
+ size_b0 = size8;
+ memctl->memc_mamr = CFG_MAMR_8COL;
+ udelay (500);
+ /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
+ }
+
+ udelay (1000);
+
+ /*
+ * Adjust refresh rate depending on SDRAM type, both banks
+ * For types > 128 MBit leave it at the current (fast) rate
+ */
+ if (size_b0 < 0x02000000) {
+ /* reduce to 15.6 us (62.4 us / quad) */
+ memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+ udelay (1000);
+ }
+
+ /*
+ * Final mapping: map bigger bank first
+ */
+ memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+ memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
- {
- unsigned long reg;
+ {
+ unsigned long reg;
- /* adjust refresh rate depending on SDRAM type, one bank */
- reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
- memctl->memc_mptpr = reg;
- }
+ /* adjust refresh rate depending on SDRAM type, one bank */
+ reg = memctl->memc_mptpr;
+ reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
+ memctl->memc_mptpr = reg;
+ }
- udelay(10000);
+ udelay (10000);
- return (size_b0);
+ return (size_b0);
}
/* ------------------------------------------------------------------------- */
*/
static long int
-dram_size (long int mamr_value,
- long int *base,
- long int maxsize)
+dram_size (long int mamr_value, long int *base, long int maxsize)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- memctl->memc_mamr = mamr_value;
-
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1)
- {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
- /* check at base address */
- if ( (val = *addr) != 0 )
- {
- *addr = save[i];
-
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1)
- {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if ( val != (~cnt) )
- {
- return (cnt * sizeof(long));
- }
- }
+ memctl->memc_mamr = mamr_value;
- return (maxsize);
+ return (get_ram_size (base, maxsize));
}
/* ------------------------------------------------------------------------- */
#define CFG_LBKs (CFG_PA2 | CFG_PA1)
-void
-reset_phy (void)
+void reset_phy (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
-
- /*
- * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
- * and no AUI loopback
- */
- immr->im_ioport.iop_padat &= ~CFG_LBKs; /* PADAT (LBK eth 1&2 = 0) */
- immr->im_ioport.iop_papar &= ~CFG_LBKs; /* PAPAR (0=general purpose I/O) */
- immr->im_ioport.iop_padir |= CFG_LBKs; /* PADIR (I/O: 0=input, 1=output) */
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+ /*
+ * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
+ * and no AUI loopback
+ */
+ immr->im_ioport.iop_padat &= ~CFG_LBKs; /* PADAT (LBK eth 1&2 = 0) */
+ immr->im_ioport.iop_papar &= ~CFG_LBKs; /* PAPAR (0=general purpose I/O) */
+ immr->im_ioport.iop_padir |= CFG_LBKs; /* PADIR (I/O: 0=input, 1=output) */
}
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
+ return (get_ram_size(base, maxsize));
}
/*-----------------------------------------------------------------------------
* aschex_to_byte --
#define _NOT_USED_ 0xFFFFCC25
-const uint sdram_table[] =
-{
+const uint sdram_table[] = {
/*
* Single Read. (Offset 00h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
- 0x3FBFCC27, /* last */
+ 0x3FBFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Read. (Offset 08h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
- 0x3FBFCC27, /* last */
+ 0x3FBFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
* Single Write. (Offset 18h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
- 0x3FFFCC27, /* last */
+ 0x3FFFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20h in UPMA RAM)
*/
0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
- 0x0CFFCC00, 0x33FFCC27, /* last */
+ 0x0CFFCC00, 0x33FFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_,
* Refresh. (Offset 30h in UPMA RAM)
*/
0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
- 0x3FFFCC27, /* last */
+ 0x3FFFCC27, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
int checkboard (void)
{
- puts ("Board: RPXlite\n") ;
- return (0) ;
+ puts ("Board: RPXlite\n");
+ return (0);
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size10 ;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size10;
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+ upmconfig (UPMA, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
/* Refresh clock prescalar */
- memctl->memc_mptpr = CFG_MPTPR ;
+ memctl->memc_mptpr = CFG_MPTPR;
- memctl->memc_mar = 0x00000000;
+ memctl->memc_mar = 0x00000000;
/* Map controller banks 1 to the SDRAM bank */
- memctl->memc_or1 = CFG_OR1_PRELIM;
- memctl->memc_br1 = CFG_BR1_PRELIM;
+ memctl->memc_or1 = CFG_OR1_PRELIM;
+ memctl->memc_br1 = CFG_BR1_PRELIM;
- memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
+ memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
- udelay(200);
+ udelay (200);
- /* perform SDRAM initializsation sequence */
+ /* perform SDRAM initializsation sequence */
- memctl->memc_mcr = 0x80002230 ; /* SDRAM bank 0 - refresh twice */
- udelay(1);
+ memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */
+ udelay (1);
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
- udelay (1000);
+ udelay (1000);
/* Check Bank 0 Memory Size
* try 10 column mode
*/
- size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
+ size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE_PRELIM,
+ SDRAM_MAX_SIZE);
- return (size10);
+ return (size10);
}
/* ------------------------------------------------------------------------- */
* - short between data lines
*/
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+static long int dram_size (long int mamr_value, long int *base,
+ long int maxsize)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- memctl->memc_mamr = mamr_value;
-
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
- val = *addr;
- *addr = save[--i];
+ memctl->memc_mamr = mamr_value;
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
- }
- }
- return (maxsize);
+ return (get_ram_size (base, maxsize));
}
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val, size;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- /* Restore the original data before leaving the function.
- */
- *addr = save[i];
- for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- size = cnt * sizeof (long);
- /* Restore the original data before returning
- */
- for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- return (size);
- }
- }
- return (maxsize);
+ return (get_ram_size(base, maxsize));
}
long int initdram (int board_type)
{
- int i, cnt;
- volatile uchar * base= CFG_SDRAM_BASE;
- volatile ulong * addr;
- ulong save[32];
- ulong val, ret = 0;
+ long size;
+ long new_bank0_end;
+ long mear1;
+ long emear1;
- for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *)base + cnt;
- save[i++] = *addr;
- *addr = ~cnt;
- }
+ size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
- addr = (volatile ulong *)base;
- save[i] = *addr;
- *addr = 0;
+ new_bank0_end = size - 1;
+ mear1 = mpc824x_mpc107_getreg(MEAR1);
+ emear1 = mpc824x_mpc107_getreg(EMEAR1);
+ mear1 = (mear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+ emear1 = (emear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+ mpc824x_mpc107_setreg(MEAR1, mear1);
+ mpc824x_mpc107_setreg(EMEAR1, emear1);
- if (*addr != 0) {
- *addr = save[i];
- goto Done;
- }
-
- for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *)base + cnt;
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- ulong new_bank0_end = cnt * sizeof(long) - 1;
- ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
- ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- ret = cnt * sizeof(long);
- goto Done;
- }
- }
-
- ret = CFG_MAX_RAM_SIZE;
-Done:
- return ret;
+ return (size);
}
/*
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
- ulong cnt, val, size;
- volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
+ ulong maxsize, size;
int i;
- ulong save[32]; /* to make test non-destructive */
- ulong maxsize;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
- /*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
- i = 0;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- save[i++] = *addr;
- *addr = ~cnt;
- }
+ size = get_ram_size((long *)base, maxsize);
- addr = (volatile ulong *) base;
- save[i] = *addr;
- *addr = 0;
-
- if ((val = *addr) != 0) {
- /* Restore the original data before leaving the function.
- */
- *addr = save[i];
- for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- return (0);
- }
+ *orx_ptr = orx | ~(size - 1);
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- size = cnt * sizeof (long);
- /* Restore the original data before returning
- */
- for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- /* Write the actual size to ORx
- */
- *orx_ptr = orx | ~(size - 1);
- return (size);
- }
- }
- return (maxsize);
+ return (size);
}
int misc_init_r(void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val, size;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- /* Restore the original data before leaving the function.
- */
- *addr = save[i];
- for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- size = cnt * sizeof (long);
- /* Restore the original data before returning
- */
- for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- return (size);
- }
- }
- return (maxsize);
+ return (get_ram_size(base, maxsize));
}
long int initdram(int board_type)
{
- int i, cnt;
- volatile uchar * base = CFG_SDRAM_BASE;
- volatile ulong * addr;
- ulong save[32];
- ulong val, ret = 0;
-
- for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
-
- addr = (volatile ulong *)base + cnt;
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- addr = (volatile ulong *)base;
- save[i] = *addr;
- *addr = 0;
-
- if (*addr != 0) {
- *addr = save[i];
- goto Done;
- }
-
- for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *)base + cnt;
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- ulong new_bank0_end = cnt * sizeof(long) - 1;
- ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
- ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- ret = cnt * sizeof(long);
- goto Done;
- }
- }
-
- ret = CFG_MAX_RAM_SIZE;
-Done:
- return ret;
+ long size;
+ long new_bank0_end;
+ long mear1;
+ long emear1;
+
+ size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+ new_bank0_end = size - 1;
+ mear1 = mpc824x_mpc107_getreg(MEAR1);
+ emear1 = mpc824x_mpc107_getreg(EMEAR1);
+ mear1 = (mear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+ emear1 = (emear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+ mpc824x_mpc107_setreg(MEAR1, mear1);
+ mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+ return (size);
}
/*
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
- ulong cnt, val;
- volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
+ ulong maxsize, size;
int i;
- ulong save[32]; /* to make test non-destructive */
- ulong maxsize;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
- /*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
- i = 0;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- save[i++] = *addr;
- *addr = ~cnt;
- }
+ size = get_ram_size((long *)base, maxsize);
- addr = (volatile ulong *) base;
- save[i] = *addr;
- *addr = 0;
+ *orx_ptr = orx | ~(size - 1);
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- /* Write the actual size to ORx
- */
- *orx_ptr = orx | ~(cnt * sizeof (long) - 1);
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
+ return (size);
}
long int initdram (int board_type)
long int initdram(int board_type)
{
- int i, cnt;
- volatile uchar * base = CFG_SDRAM_BASE;
- volatile ulong * addr;
- ulong save[32];
- ulong val, ret = 0;
-
- for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *)base + cnt;
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- addr = (volatile ulong *)base;
- save[i] = *addr;
- *addr = 0;
-
- if (*addr != 0) {
- *addr = save[i];
- goto Done;
- }
-
- for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *)base + cnt;
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- ulong new_bank0_end = cnt * sizeof(long) - 1;
- ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
- ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- ret = cnt * sizeof(long);
- goto Done;
- }
- }
-
- ret = CFG_MAX_RAM_SIZE;
-Done:
- return ret;
+ long size;
+ long new_bank0_end;
+ long mear1;
+ long emear1;
+
+ size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+ new_bank0_end = size - 1;
+ mear1 = mpc824x_mpc107_getreg(MEAR1);
+ emear1 = mpc824x_mpc107_getreg(EMEAR1);
+ mear1 = (mear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+ emear1 = (emear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+ mpc824x_mpc107_setreg(MEAR1, mear1);
+ mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+ return (size);
}
/*
/* ------------------------------------------------------------------------- */
-static long int dram_size ( long int *base, long int maxsize);
-
-/* ------------------------------------------------------------------------- */
-
#define _NOT_USED_ 0xFFFFFFFF
-const uint sdram_table[] =
-{
+const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPMA RAM)
*
* active, NOP, read, precharge, NOP */
0x0F27CC04, 0x0EAECC04, 0x00B98C04, 0x00F74C00,
- 0x11FFCC05, /* last */
+ 0x11FFCC05, /* last */
/*
* SDRAM Initialization (offset 5 in UPMA RAM)
*
* sequence, which is executed by a RUN command.
* NOP, Program
*/
- 0x0F0A8C34, 0x1F354C37, /* last */
+ 0x0F0A8C34, 0x1F354C37, /* last */
- _NOT_USED_, /* Not used */
+ _NOT_USED_, /* Not used */
/*
* Burst Read. (Offset 8 in UPMA RAM)
* active, NOP, read, NOP, NOP, NOP, NOP, NOP */
0x0F37CC04, 0x0EFECC04, 0x00FDCC04, 0x00FFCC00,
- 0x00FFCC00, 0x01FFCC00, 0x0FFFCC00, 0x1FFFCC05, /* last */
+ 0x00FFCC00, 0x01FFCC00, 0x0FFFCC00, 0x1FFFCC05, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMA RAM)
* active, NOP, write, NOP, precharge, NOP */
0x0F27CC04, 0x0EAE8C00, 0x01BD4C04, 0x0FFB8C04,
- 0x0FF74C04, 0x1FFFCC05, /* last */
+ 0x0FF74C04, 0x1FFFCC05, /* last */
_NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMA RAM)
* active, NOP, write, NOP, NOP, NOP, NOP, NOP */
0x0F37CC04, 0x0EFE8C00, 0x00FD4C00, 0x00FFCC00,
- 0x00FFCC00, 0x01FFCC04, 0x0FFFCC04, 0x1FFFCC05, /* last */
+ 0x00FFCC00, 0x01FFCC04, 0x0FFFCC04, 0x1FFFCC05, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPMA RAM)
* precharge, NOP, auto_ref, NOP, NOP, NOP */
0x0FF74C34, 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34,
- 0x0FFFCCB4, 0x1FFFCC35, /* last */
- _NOT_USED_, _NOT_USED_,
+ 0x0FFFCCB4, 0x1FFFCC35, /* last */
+ _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPMA RAM)
*/
- 0x0FFB8C00, 0x1FF74C03, /* last */
- _NOT_USED_, _NOT_USED_
+ 0x0FFB8C00, 0x1FF74C03, /* last */
+ _NOT_USED_, _NOT_USED_
};
/* ------------------------------------------------------------------------- */
int checkboard (void)
{
- puts ("Board: Esteem 192E\n");
- return(0);
+ puts ("Board: Esteem 192E\n");
+ return (0);
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size_b0, size_b1;
-
- /*
- * Explain frequency of refresh here
- */
-
- memctl->memc_mptpr = 0x0200; /* divide by 32 */
-
- memctl->memc_mamr = 0x18003112; /*CFG_MAMR_8COL;*/ /* 0x18005112 TODO: explain here */
-
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size_b0, size_b1;
- /*
- * Map cs 2 and 3 to the SDRAM banks 0 and 1 at
- * preliminary addresses - these have to be modified after the
- * SDRAM size has been determined.
- */
-
- memctl->memc_or2 = CFG_OR2_PRELIM; /* not defined yet */
- memctl->memc_br2 = CFG_BR2_PRELIM;
+ /*
+ * Explain frequency of refresh here
+ */
- memctl->memc_or3 = CFG_OR3_PRELIM;
- memctl->memc_br3 = CFG_BR3_PRELIM;
+ memctl->memc_mptpr = 0x0200; /* divide by 32 */
+ memctl->memc_mamr = 0x18003112; /*CFG_MAMR_8COL; *//* 0x18005112 TODO: explain here */
- /* perform SDRAM initializsation sequence */
- memctl->memc_mar = 0x00000088;
+ upmconfig (UPMA, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
- memctl->memc_mcr = 0x80004830; /* SDRAM bank 0 execute 8 refresh */
+ /*
+ * Map cs 2 and 3 to the SDRAM banks 0 and 1 at
+ * preliminary addresses - these have to be modified after the
+ * SDRAM size has been determined.
+ */
- memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
+ memctl->memc_or2 = CFG_OR2_PRELIM; /* not defined yet */
+ memctl->memc_br2 = CFG_BR2_PRELIM;
+ memctl->memc_or3 = CFG_OR3_PRELIM;
+ memctl->memc_br3 = CFG_BR3_PRELIM;
- memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */
- memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
+ /* perform SDRAM initializsation sequence */
+ memctl->memc_mar = 0x00000088;
+ memctl->memc_mcr = 0x80004830; /* SDRAM bank 0 execute 8 refresh */
+ memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
+ memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */
+ memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
- memctl->memc_mamr = CFG_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */
+ memctl->memc_mamr = CFG_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */
/* printf ("banks 0 and 1 are programed\n"); */
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- */
-
- size_b0 = dram_size ((ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
-
- size_b1 = dram_size ((ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-
-
- printf ("\nbank 0 size %lu\nbank 1 size %lu\n",size_b0,size_b1);
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ *
+ */
+ size_b0 = get_ram_size ((ulong *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+ size_b1 = get_ram_size ((ulong *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+ printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1);
/* printf ("bank 1 size %u\n",size_b1); */
- if(size_b1 == 0) {
-
- /*
- * Adjust refresh rate if bank 0 isn't stuffed
- */
-
- memctl->memc_mptpr = 0x0400; /* divide by 64 */
- memctl->memc_br3 &= 0x0FFFFFFFE;
-
- /*
- * Adjust OR2 for size of bank 0
- */
- memctl->memc_or2 |= 7 * size_b0;
-
- }
-
- else {
-
- if(size_b0 < size_b1) {
- memctl->memc_br2 &= 0x00007FFE;
- memctl->memc_br3 &= 0x00007FFF;
-
- /*
- * Adjust OR3 for size of bank 1
- */
- memctl->memc_or3 |= 15 * size_b1;
-
- /*
- * Adjust OR2 for size of bank 0
- */
- memctl->memc_or2 |= 15 * size_b0;
-
- memctl->memc_br2 += (size_b1 + 1);
-
- }
- else {
-
- memctl->memc_br3 &= 0x00007FFE;
-
-
- /*
- * Adjust OR2 for size of bank 0
- */
- memctl->memc_or2 |= 15 * size_b0;
-
- /*
- * Adjust OR3 for size of bank 1
- */
- memctl->memc_or3 |= 15 * size_b1;
-
- memctl->memc_br3 += (size_b0 + 1);
-
-
- }
- }
-
-
-/* before leaving set all unused i/o pins to outputs */
-
-/*
- * --*Unused Pin List*--
- *
- * group/port bit number
- * IP_B 0,1,3,4,5 Taken care of in pcmcia-cs-x.x.xx
- * PA 5,7,8,9,14,15
- * PB 22,23,31
- * PC 4,5,6,7,10,11,12,13,14,15
- * PD 5,6,7
- *
- */
-
-/*
- * --*Pin Used for I/O List*--
- *
- * port input bit number output bit number either
- * PB 18,26,27
- * PD 3,4 8,9,10,11,12,13,14,15
- *
- */
-
-
- immap->im_ioport.iop_papar &= ~0x05C3; /* set pins as io */
- immap->im_ioport.iop_padir |= 0x05C3; /* set pins as output */
- immap->im_ioport.iop_paodr &= 0x0008; /* config pins 9 & 14 as normal outputs */
- immap->im_ioport.iop_padat |= 0x05C3; /* set unused pins as high */
-
- immap->im_cpm.cp_pbpar &= ~0x00001331; /* set unused port b pins as io */
- immap->im_cpm.cp_pbdir |= 0x00001331; /* set unused port b pins as output */
- immap->im_cpm.cp_pbodr &= ~0x00001331; /* config bits 18,22,23,26,27 & 31 as normal outputs */
- immap->im_cpm.cp_pbdat |= 0x00001331; /* set T/E LED, /NV_CS, & /POWER_ADJ_CS and the rest to a high */
-
- immap->im_ioport.iop_pcpar &= ~0x0F3F; /* set unused port c pins as io */
- immap->im_ioport.iop_pcdir |= 0x0F3F; /* set unused port c pins as output */
- immap->im_ioport.iop_pcso &= ~0x0F3F; /* clear special purpose bit for unused port c pins for clarity */
- immap->im_ioport.iop_pcdat |= 0x0F3F; /* set unused port c pins high*/
-
- immap->im_ioport.iop_pdpar &= 0xE000; /* set pins as io */
- immap->im_ioport.iop_pddir &= 0xE000; /* set bit 3 & 4 as inputs */
- immap->im_ioport.iop_pddir |= 0x07FF; /* set bits 5 - 15 as outputs */
- immap->im_ioport.iop_pddat = 0x0055; /* set alternating pattern on test port */
-
-
- return (size_b0 + size_b1);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size ( long int *base, long int maxsize)
-{
+ if (size_b1 == 0) {
+ /*
+ * Adjust refresh rate if bank 0 isn't stuffed
+ */
+ memctl->memc_mptpr = 0x0400; /* divide by 64 */
+ memctl->memc_br3 &= 0x0FFFFFFFE;
+
+ /*
+ * Adjust OR2 for size of bank 0
+ */
+ memctl->memc_or2 |= 7 * size_b0;
+ } else {
+ if (size_b0 < size_b1) {
+ memctl->memc_br2 &= 0x00007FFE;
+ memctl->memc_br3 &= 0x00007FFF;
+
+ /*
+ * Adjust OR3 for size of bank 1
+ */
+ memctl->memc_or3 |= 15 * size_b1;
+
+ /*
+ * Adjust OR2 for size of bank 0
+ */
+ memctl->memc_or2 |= 15 * size_b0;
+ memctl->memc_br2 += (size_b1 + 1);
+ } else {
+ memctl->memc_br3 &= 0x00007FFE;
+
+ /*
+ * Adjust OR2 for size of bank 0
+ */
+ memctl->memc_or2 |= 15 * size_b0;
+
+ /*
+ * Adjust OR3 for size of bank 1
+ */
+ memctl->memc_or3 |= 15 * size_b1;
+ memctl->memc_br3 += (size_b0 + 1);
+ }
+ }
- volatile long int *addr;
- long int cnt, val;
+ /* before leaving set all unused i/o pins to outputs */
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
+ /*
+ * --*Unused Pin List*--
+ *
+ * group/port bit number
+ * IP_B 0,1,3,4,5 Taken care of in pcmcia-cs-x.x.xx
+ * PA 5,7,8,9,14,15
+ * PB 22,23,31
+ * PC 4,5,6,7,10,11,12,13,14,15
+ * PD 5,6,7
+ *
+ */
- *addr = ~cnt;
- }
+ /*
+ * --*Pin Used for I/O List*--
+ *
+ * port input bit number output bit number either
+ * PB 18,26,27
+ * PD 3,4 8,9,10,11,12,13,14,15
+ *
+ */
- /* write 0 to base address */
- addr = base;
- *addr = 0;
+ immap->im_ioport.iop_papar &= ~0x05C3; /* set pins as io */
+ immap->im_ioport.iop_padir |= 0x05C3; /* set pins as output */
+ immap->im_ioport.iop_paodr &= 0x0008; /* config pins 9 & 14 as normal outputs */
+ immap->im_ioport.iop_padat |= 0x05C3; /* set unused pins as high */
- /* check at base address */
- if ((val = *addr) != 0) {
- return (0);
- }
+ immap->im_cpm.cp_pbpar &= ~0x00001331; /* set unused port b pins as io */
+ immap->im_cpm.cp_pbdir |= 0x00001331; /* set unused port b pins as output */
+ immap->im_cpm.cp_pbodr &= ~0x00001331; /* config bits 18,22,23,26,27 & 31 as normal outputs */
+ immap->im_cpm.cp_pbdat |= 0x00001331; /* set T/E LED, /NV_CS, & /POWER_ADJ_CS and the rest to a high */
- for (cnt = 1; ; cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
+ immap->im_ioport.iop_pcpar &= ~0x0F3F; /* set unused port c pins as io */
+ immap->im_ioport.iop_pcdir |= 0x0F3F; /* set unused port c pins as output */
+ immap->im_ioport.iop_pcso &= ~0x0F3F; /* clear special purpose bit for unused port c pins for clarity */
+ immap->im_ioport.iop_pcdat |= 0x0F3F; /* set unused port c pins high */
- val = *addr;
+ immap->im_ioport.iop_pdpar &= 0xE000; /* set pins as io */
+ immap->im_ioport.iop_pddir &= 0xE000; /* set bit 3 & 4 as inputs */
+ immap->im_ioport.iop_pddir |= 0x07FF; /* set bits 5 - 15 as outputs */
+ immap->im_ioport.iop_pddat = 0x0055; /* set alternating pattern on test port */
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
- }
- }
- /* NOTREACHED */
+ return (size_b0 + size_b1);
}
long int initdram (int board_type)
{
- int i, cnt;
- volatile uchar * base= CFG_SDRAM_BASE;
- volatile ulong * addr;
- ulong save[32];
- ulong val, ret = 0;
-
- for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *)base + cnt;
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- addr = (volatile ulong *)base;
- save[i] = *addr;
- *addr = 0;
-
- if (*addr != 0) {
- *addr = save[i];
- goto Done;
- }
+ long size;
+#if 0
+ long new_bank0_end;
+ long mear1;
+ long emear1;
+#endif
- for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *)base + cnt;
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
-/* ulong new_bank0_end = cnt * sizeof(long) - 1;
- ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
- ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);*/
-
- ret = cnt * sizeof(long);
- goto Done;
- }
- }
+ size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+#if 0
+ new_bank0_end = size - 1;
+ mear1 = mpc824x_mpc107_getreg(MEAR1);
+ emear1 = mpc824x_mpc107_getreg(EMEAR1);
+ mear1 = (mear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+ emear1 = (emear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+ mpc824x_mpc107_setreg(MEAR1, mear1);
+ mpc824x_mpc107_setreg(EMEAR1, emear1);
+#endif
- ret = CFG_MAX_RAM_SIZE;
-Done:
- return ret;
+ return (size);
}
/*
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val, size;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- /* Restore the original data before leaving the function.
- */
- *addr = save[i];
- for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- size = cnt * sizeof (long);
- /* Restore the original data before returning
- */
- for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- return (size);
- }
- }
- return (maxsize);
+ return (get_ram_size(base, maxsize));
}
/* ------------------------------------------------------------------------- */
#error dram not correctly defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
#endif
-/* ------------------------------------------------------------------------- */
-static long int dram_size (long int *base, long int maxsize)
-{
- volatile long int *addr=base;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
-}
-
/* ------------------------------------------------------------------------- */
static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
{
/* if no dimm is inserted, noMbytes is still detected as 8m, so
* sanity check top and bottom of memory */
- /* check bytes / 2 because dram_size tests at base+bytes, which
+ /* check bytes / 2 because get_ram_size tests at base+bytes, which
* is not mapped */
if (noMbytes == 8)
- if (dram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
+ if (get_ram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
*((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */
return -1;
}
#define _NOT_USED_ 0xFFFFFFFF
-const uint sdram_table[] =
-{
+const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPMB RAM)
*/
0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBEEC00,
- 0x1FFDDC47, /* last */
+ 0x1FFDDC47, /* last */
/*
* SDRAM Initialization (offset 5 in UPMB RAM)
*
* sequence, which is executed by a RUN command.
*
*/
- 0x1FFDDC34, 0xEFEEAC34, 0x1FBD5C35, /* last */
+ 0x1FFDDC34, 0xEFEEAC34, 0x1FBD5C35, /* last */
/*
* Burst Read. (Offset 8 in UPMB RAM)
*/
0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
- 0xF0AFFC00, 0xF1AFFC00, 0xEFBEEC00, 0x1FFDDC47, /* last */
+ 0xF0AFFC00, 0xF1AFFC00, 0xEFBEEC00, 0x1FFDDC47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMB RAM)
*/
- 0x1F2DFC04, 0xEEAFAC00, 0x01BE4C04, 0x1FFDDC47, /* last */
+ 0x1F2DFC04, 0xEEAFAC00, 0x01BE4C04, 0x1FFDDC47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMB RAM)
*/
0x1F0DFC04, 0xEEAFAC00, 0x10AF5C00, 0xF0AFFC00,
- 0xF0AFFC00, 0xE1BEEC04, 0x1FFDDC47, /* last */
- _NOT_USED_,
+ 0xF0AFFC00, 0xE1BEEC04, 0x1FFDDC47, /* last */
+ _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPMB RAM)
*/
0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC84, 0xFFFFFC07, /* last */
- _NOT_USED_, _NOT_USED_,
+ 0xFFFFFC84, 0xFFFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPMB RAM)
*/
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0x7FFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
int checkboard (void)
{
- puts ("Board: GenieTV\n");
- return 0;
+ puts ("Board: GenieTV\n");
+ return 0;
}
#if 0
-static void PrintState(void)
+static void PrintState (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &im->im_memctl;
-
- printf("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0, memctl->memc_or0);
- printf("\n1 - SDRAM: B=%08x O=%08x", memctl->memc_br1, memctl->memc_or1);
- printf("\n2 - SDRAM: B=%08x O=%08x", memctl->memc_br2, memctl->memc_or2);
+ volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &im->im_memctl;
+
+ printf ("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0,
+ memctl->memc_or0);
+ printf ("\n1 - SDRAM: B=%08x O=%08x", memctl->memc_br1,
+ memctl->memc_or1);
+ printf ("\n2 - SDRAM: B=%08x O=%08x", memctl->memc_br2,
+ memctl->memc_or2);
}
#endif
long int initdram (int board_type)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &im->im_memctl;
- long int size_b0, size_b1, size8;
+ volatile immap_t *im = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &im->im_memctl;
+ long int size_b0, size_b1, size8;
- /* Enable SDRAM */
+ /* Enable SDRAM */
- /* Configuring PA7 for general purpouse output pin */
- im->im_ioport.iop_papar &= ~CFG_PA7 ; /* 0 = general purpouse */
- im->im_ioport.iop_padir |= CFG_PA7 ; /* 1 = output */
+ /* Configuring PA7 for general purpouse output pin */
+ im->im_ioport.iop_papar &= ~CFG_PA7; /* 0 = general purpouse */
+ im->im_ioport.iop_padir |= CFG_PA7; /* 1 = output */
- /* Enable SDRAM - PA7 = 1 */
- im->im_ioport.iop_padat |= CFG_PA7 ; /* value of PA7 */
+ /* Enable SDRAM - PA7 = 1 */
+ im->im_ioport.iop_padat |= CFG_PA7; /* value of PA7 */
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CFG_MPTPR_2BK_4K ;
+ /*
+ * Preliminary prescaler for refresh (depends on number of
+ * banks): This value is selected for four cycles every 62.4 us
+ * with two SDRAM banks or four cycles every 31.2 us with one
+ * bank. It will be adjusted after memory sizing.
+ */
+ memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
- memctl->memc_mbmr = CFG_MBMR_8COL;
+ memctl->memc_mbmr = CFG_MBMR_8COL;
- upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+ upmconfig (UPMB, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
- /*
- * Map controller banks 1 and 2 to the SDRAM banks 1 and 2 at
- * preliminary addresses - these have to be modified after the
- * SDRAM size has been determined.
- */
+ /*
+ * Map controller banks 1 and 2 to the SDRAM banks 1 and 2 at
+ * preliminary addresses - these have to be modified after the
+ * SDRAM size has been determined.
+ */
- memctl->memc_or1 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
- memctl->memc_br1 = ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
+ memctl->memc_or1 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
+ memctl->memc_br1 =
+ ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
- memctl->memc_or2 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
- memctl->memc_br2 = ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
+ memctl->memc_or2 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
+ memctl->memc_br2 =
+ ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
- /* perform SDRAM initialization sequence */
- memctl->memc_mar = 0x00000088;
+ /* perform SDRAM initialization sequence */
+ memctl->memc_mar = 0x00000088;
- memctl->memc_mcr = 0x80802105; /* SDRAM bank 0 */
+ memctl->memc_mcr = 0x80802105; /* SDRAM bank 0 */
- memctl->memc_mcr = 0x80804105; /* SDRAM bank 1 */
+ memctl->memc_mcr = 0x80804105; /* SDRAM bank 1 */
- /* Execute refresh 8 times */
- memctl->memc_mbmr = (CFG_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X ;
+ /* Execute refresh 8 times */
+ memctl->memc_mbmr = (CFG_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X;
- memctl->memc_mcr = 0x80802130; /* SDRAM bank 0 - execute twice */
+ memctl->memc_mcr = 0x80802130; /* SDRAM bank 0 - execute twice */
- memctl->memc_mcr = 0x80804130; /* SDRAM bank 1 - execute twice */
+ memctl->memc_mcr = 0x80804130; /* SDRAM bank 1 - execute twice */
- /* Execute refresh 4 times */
- memctl->memc_mbmr = CFG_MBMR_8COL;
+ /* Execute refresh 4 times */
+ memctl->memc_mbmr = CFG_MBMR_8COL;
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ *
+ * try 8 column mode
+ */
#if 0
- PrintState();
+ PrintState ();
#endif
/* printf ("\nChecking bank1..."); */
- size8 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+ size8 = dram_size (CFG_MBMR_8COL, (ulong *) SDRAM_BASE1_PRELIM,
+ SDRAM_MAX_SIZE);
- size_b0 = size8 ;
+ size_b0 = size8;
/* printf ("\nChecking bank2..."); */
- size_b1 = dram_size (memctl->memc_mbmr, (ulong *)SDRAM_BASE2_PRELIM,SDRAM_MAX_SIZE);
+ size_b1 =
+ dram_size (memctl->memc_mbmr, (ulong *) SDRAM_BASE2_PRELIM,
+ SDRAM_MAX_SIZE);
- /*
- * Final mapping: map bigger bank first
- */
-
- memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
- memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
-
- if (size_b1 > 0)
- {
- /*
- * Position Bank 1 immediately above Bank 0
- */
- memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
- memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) +
- (size_b0 & BR_BA_MSK);
- }
- else
- {
/*
- * No bank 1
- *
- * invalidate bank
+ * Final mapping: map bigger bank first
*/
- memctl->memc_br2 = 0;
- /* adjust refresh rate depending on SDRAM type, one bank */
- memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
- }
-
- /* If no memory detected, disable SDRAM */
- if ((size_b0 + size_b1) == 0)
- {
- printf("disabling SDRAM!\n");
- /* Disable SDRAM - PA7 = 1 */
- im->im_ioport.iop_padat &= ~CFG_PA7 ; /* value of PA7 */
- }
+
+ memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+ memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
+
+ if (size_b1 > 0) {
+ /*
+ * Position Bank 1 immediately above Bank 0
+ */
+ memctl->memc_or2 =
+ ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+ memctl->memc_br2 =
+ ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) +
+ (size_b0 & BR_BA_MSK);
+ } else {
+ /*
+ * No bank 1
+ *
+ * invalidate bank
+ */
+ memctl->memc_br2 = 0;
+ /* adjust refresh rate depending on SDRAM type, one bank */
+ memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
+ }
+
+ /* If no memory detected, disable SDRAM */
+ if ((size_b0 + size_b1) == 0) {
+ printf ("disabling SDRAM!\n");
+ /* Disable SDRAM - PA7 = 1 */
+ im->im_ioport.iop_padat &= ~CFG_PA7; /* value of PA7 */
+ }
/* else */
/* printf("done! (%08lx)\n", size_b0 + size_b1); */
#if 0
- PrintState();
+ PrintState ();
#endif
- return (size_b0 + size_b1);
+ return (size_b0 + size_b1);
}
/* ------------------------------------------------------------------------- */
* - short between data lines
*/
-static long int dram_size (long int mbmr_value, long int *base, long int maxsize)
+static long int dram_size (long int mbmr_value, long int *base,
+ long int maxsize)
{
- volatile long int *addr;
- long int cnt, val;
-
- /*memctl->memc_mbmr = mbmr_value; */
+ long size;
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
+ /*memctl->memc_mbmr = mbmr_value; */
- *addr = ~cnt;
- }
+ size = get_ram_size (base, maxsize);
- /* write 0 to base address */
- addr = base;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- printf("(0)");
- return (0);
- }
-
- for (cnt = 1; ; cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- if (val != (~cnt)) {
-/* printf("(%08lx)", cnt*sizeof(long)); */
- return (cnt * sizeof(long));
+ if (size) {
+/* printf("(%08lx)", size); */
+ } else {
+ printf ("(0)");
}
- }
- /* NOTREACHED */
- return (0);
+
+ return (size);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#ifdef CFG_PCMCIA_MEM_ADDR
-volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
+volatile unsigned char *pcmcia_mem = (unsigned char *) CFG_PCMCIA_MEM_ADDR;
#endif
-int pcmcia_init(void)
+int pcmcia_init (void)
{
- volatile pcmconf8xx_t *pcmp;
+ volatile pcmconf8xx_t *pcmp;
uint v, slota, slotb;
/*
- ** Enable the PCMCIA for a Flash card.
- */
- pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ ** Enable the PCMCIA for a Flash card.
+ */
+ pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia));
#if 0
pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR;
#endif
/* Check if any PCMCIA card is luged in. */
- slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
- slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
+ slota = (pcmp->pcmc_pipr & 0x18000000) == 0;
+ slotb = (pcmp->pcmc_pipr & 0x00001800) == 0;
- if (!(slota || slotb))
- {
- printf("No card present\n");
+ if (!(slota || slotb)) {
+ printf ("No card present\n");
#ifdef PCMCIA_SLOT_A
pcmp->pcmc_pgcra = 0;
#endif
pcmp->pcmc_pgcrb = 0;
#endif
return -1;
- }
- else
- printf("Unknown card (");
+ } else
+ printf ("Unknown card (");
v = 0;
- switch( (pcmp->pcmc_pipr >> 14) & 3 )
- {
- case 0x00 :
- printf("5V");
- v = 5;
- break;
- case 0x01 :
- printf("5V and 3V");
- v = 3;
- break;
- case 0x03 :
- printf("5V, 3V and x.xV");
- v = 3;
- break;
+ switch ((pcmp->pcmc_pipr >> 14) & 3) {
+ case 0x00:
+ printf ("5V");
+ v = 5;
+ break;
+ case 0x01:
+ printf ("5V and 3V");
+ v = 3;
+ break;
+ case 0x03:
+ printf ("5V, 3V and x.xV");
+ v = 3;
+ break;
}
- switch(v){
+ switch (v) {
case 3:
- printf("; using 3V");
- /* Enable 3 volt Vcc. */
+ printf ("; using 3V");
+ /* Enable 3 volt Vcc. */
- break;
+ break;
default:
- printf("; unknown voltage");
+ printf ("; unknown voltage");
return -1;
}
- printf(")\n");
+ printf (")\n");
/* disable pcmcia reset after a while */
- udelay(20);
+ udelay (20);
pcmp->pcmc_pgcrb = 0;
/* If you using a real hd you should give a short
- * spin-up time. */
+ * spin-up time. */
#ifdef CONFIG_DISK_SPINUP_TIME
- udelay(CONFIG_DISK_SPINUP_TIME);
+ udelay (CONFIG_DISK_SPINUP_TIME);
#endif
return 0;
}
-#endif /* CFG_CMD_PCMCIA */
+#endif /* CFG_CMD_PCMCIA */
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
+ return (get_ram_size(base, maxsize));
}
/* ------------------------------------------------------------------------- */
#include <pci.h>
#ifndef CFG_RAMBOOT
-static long int dram_size(long int *base, long int maxsize)
-{
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
-}
-
static void sdram_start (int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
*(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
#endif
sdram_start(0);
- test1 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
#ifdef CONFIG_MPC5200_DDR
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
sdram_start(0);
- test1 = dram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(1);
- test2 = dram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+ test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
+ return (get_ram_size(base, maxsize));
}
return size;
}
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size(long int *base, long int maxsize)
-{
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
-}
-
long int initdram(int board_type)
{
int rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0;
{
*INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) |
(rows << 4) | cols;
- size = dram_size((ulong *)CFG_SDRAM_BASE,
+ size = get_ram_size((ulong *)CFG_SDRAM_BASE,
max_sdram_size());
if (size > max_size)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
+ return (get_ram_size(base, maxsize));
}
/* ------------------------------------------------------------------------- */
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar *base;
- volatile ulong *addr, cnt, val;
- ulong save[32]; /* to make test non-destructive */
- int i, maxsize;
+ ulong maxsize;
+ int i;
memctl->memc_psrt = CFG_PSRT;
memctl->memc_mptpr = CFG_MPTPR;
*/
maxsize = (1 + (~memctl->memc_or1 | 0x7fff)) / 2;
- /*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
- i = 0;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- save[i++] = *addr;
- *addr = ~cnt;
- }
+ maxsize = get_ram_size((long *)base, maxsize);
- addr = (volatile ulong *) base;
- save[i] = *addr;
- *addr = 0;
-
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- /* Write the actual size to ORx
- */
- memctl->memc_or1 |= ~(cnt * sizeof (long) - 1);
- maxsize = cnt * sizeof (long) / 2;
- break;
- }
- }
+ memctl->memc_or1 |= ~(maxsize - 1);
- maxsize *= 2;
if (maxsize != hwc_main_sdram_size ())
printf ("Oops: memory test has not found all memory!\n");
#endif
/*
* 50 MHz SHARC access using UPM A
*/
-const uint sharc_table[] =
-{
+const uint sharc_table[] = {
/*
* Single Read. (Offset 0 in UPM RAM)
*/
0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
- 0xFFFFEC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0xFFFFEC05, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Read. (Offset 8 in UPM RAM)
*/
* Single Write. (Offset 18 in UPM RAM)
*/
0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
- 0xFFFFEC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0xFFFFEC05, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPM RAM)
*/
/*
* Exception. (Offset 3c in UPM RAM)
*/
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0x7FFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/*
* 50 MHz SDRAM access using UPM B
*/
-const uint sdram_table[] =
-{
+const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPM RAM)
*/
* sequence, which is executed by a RUN command.
*
*/
- 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
+ 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
/*
* Burst Read. (Offset 8 in UPM RAM)
*/
0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00,
- 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45, /* last */
- _NOT_USED_,
+ 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45, /* last */
+ _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPM RAM)
*/
- 0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45, /* last */
+ 0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPM RAM)
*/
0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00,
- 0xE1BBBC04, 0x1FF77C45, /* last */
- _NOT_USED_, _NOT_USED_,
+ 0xE1BBBC04, 0x1FF77C45, /* last */
+ _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPM RAM)
*/
0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84,
- 0xFFFFFC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0xFFFFFC05, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPM RAM)
*/
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0x7FFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
-long int
-initdram (int board_type)
+long int initdram (int board_type)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
- long int size_b0;
-
- /* enable SDRAM clock ("switch on" SDRAM) */
- immr->im_cpm.cp_pbpar &= ~(CFG_PB_SDRAM_CLKE); /* GPIO */
- immr->im_cpm.cp_pbodr &= ~(CFG_PB_SDRAM_CLKE); /* active output */
- immr->im_cpm.cp_pbdir |= CFG_PB_SDRAM_CLKE ; /* output */
- immr->im_cpm.cp_pbdat |= CFG_PB_SDRAM_CLKE ; /* assert SDRAM CLKE */
- udelay(1);
-
- /*
- * Map controller bank 1 for ELIC SACCO
- */
- memctl->memc_or1 = CFG_OR1;
- memctl->memc_br1 = CFG_BR1;
-
- /*
- * Map controller bank 2 for ELIC EPIC
- */
- memctl->memc_or2 = CFG_OR2;
- memctl->memc_br2 = CFG_BR2;
-
- /*
- * Configure UPMA for SHARC
- */
- upmconfig(UPMA, (uint *)sharc_table, sizeof(sharc_table)/sizeof(uint));
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immr->im_memctl;
+ long int size_b0;
+
+ /* enable SDRAM clock ("switch on" SDRAM) */
+ immr->im_cpm.cp_pbpar &= ~(CFG_PB_SDRAM_CLKE); /* GPIO */
+ immr->im_cpm.cp_pbodr &= ~(CFG_PB_SDRAM_CLKE); /* active output */
+ immr->im_cpm.cp_pbdir |= CFG_PB_SDRAM_CLKE; /* output */
+ immr->im_cpm.cp_pbdat |= CFG_PB_SDRAM_CLKE; /* assert SDRAM CLKE */
+ udelay (1);
+
+ /*
+ * Map controller bank 1 for ELIC SACCO
+ */
+ memctl->memc_or1 = CFG_OR1;
+ memctl->memc_br1 = CFG_BR1;
+
+ /*
+ * Map controller bank 2 for ELIC EPIC
+ */
+ memctl->memc_or2 = CFG_OR2;
+ memctl->memc_br2 = CFG_BR2;
+
+ /*
+ * Configure UPMA for SHARC
+ */
+ upmconfig (UPMA, (uint *) sharc_table,
+ sizeof (sharc_table) / sizeof (uint));
#if defined(CONFIG_IVML24)
- /*
- * Map controller bank 4 for HDLC Address space
- */
- memctl->memc_or4 = CFG_OR4;
- memctl->memc_br4 = CFG_BR4;
+ /*
+ * Map controller bank 4 for HDLC Address space
+ */
+ memctl->memc_or4 = CFG_OR4;
+ memctl->memc_br4 = CFG_BR4;
#endif
- /*
- * Map controller bank 5 for SHARC
- */
- memctl->memc_or5 = CFG_OR5;
- memctl->memc_br5 = CFG_BR5;
-
- memctl->memc_mamr = 0x00001000;
-
- /*
- * Configure UPMB for SDRAM
- */
- upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller bank 3 to the SDRAM bank at preliminary address.
- */
- memctl->memc_or3 = CFG_OR3_PRELIM;
- memctl->memc_br3 = CFG_BR3_PRELIM;
-
- memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
-
- udelay(200);
- memctl->memc_mcr = 0x80806105; /* precharge */
- udelay(1);
- memctl->memc_mcr = 0x80806106; /* load mode register */
- udelay(1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay(1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay(1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay(1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay(1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay(1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay(1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
- udelay(1);
- memctl->memc_mcr = 0x80806130; /* autorefresh */
-
- memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- */
- size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-
- memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
-
- return (size_b0);
+ /*
+ * Map controller bank 5 for SHARC
+ */
+ memctl->memc_or5 = CFG_OR5;
+ memctl->memc_br5 = CFG_BR5;
+
+ memctl->memc_mamr = 0x00001000;
+
+ /*
+ * Configure UPMB for SDRAM
+ */
+ upmconfig (UPMB, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
+
+ memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+
+ memctl->memc_mar = 0x00000088;
+
+ /*
+ * Map controller bank 3 to the SDRAM bank at preliminary address.
+ */
+ memctl->memc_or3 = CFG_OR3_PRELIM;
+ memctl->memc_br3 = CFG_BR3_PRELIM;
+
+ memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
+
+ udelay (200);
+ memctl->memc_mcr = 0x80806105; /* precharge */
+ udelay (1);
+ memctl->memc_mcr = 0x80806106; /* load mode register */
+ udelay (1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay (1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay (1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay (1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay (1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay (1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay (1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay (1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+
+ memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ */
+ size_b0 =
+ dram_size (CFG_MBMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
+ SDRAM_MAX_SIZE);
+
+ memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
+
+ return (size_b0);
}
/* ------------------------------------------------------------------------- */
* - short between data lines
*/
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+static long int dram_size (long int mamr_value, long int *base,
+ long int maxsize)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- memctl->memc_mbmr = mamr_value;
-
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immr->im_memctl;
- for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
+ memctl->memc_mbmr = mamr_value;
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
- }
- }
- return (maxsize);
+ return (get_ram_size (base, maxsize));
}
/* ------------------------------------------------------------------------- */
-void reset_phy(void)
+void reset_phy (void)
{
- immap_t *immr = (immap_t *)CFG_IMMR;
+ immap_t *immr = (immap_t *) CFG_IMMR;
/* De-assert Ethernet Powerdown */
- immr->im_cpm.cp_pbpar &= ~(CFG_PB_ETH_POWERDOWN); /* GPIO */
- immr->im_cpm.cp_pbodr &= ~(CFG_PB_ETH_POWERDOWN); /* active output */
- immr->im_cpm.cp_pbdir |= CFG_PB_ETH_POWERDOWN ; /* output */
- immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
- udelay(1000);
+ immr->im_cpm.cp_pbpar &= ~(CFG_PB_ETH_POWERDOWN); /* GPIO */
+ immr->im_cpm.cp_pbodr &= ~(CFG_PB_ETH_POWERDOWN); /* active output */
+ immr->im_cpm.cp_pbdir |= CFG_PB_ETH_POWERDOWN; /* output */
+ immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
+ udelay (1000);
/*
* RESET is implemented by a positive pulse of at least 1 us
* Configure RESET pins for NS DP83843 PHY, and RESET chip.
*
* Note: The RESET pin is high active, but there is an
- * inverter on the SPD823TS board...
+ * inverter on the SPD823TS board...
*/
immr->im_ioport.iop_pcpar &= ~(CFG_PC_ETH_RESET);
- immr->im_ioport.iop_pcdir |= CFG_PC_ETH_RESET;
+ immr->im_ioport.iop_pcdir |= CFG_PC_ETH_RESET;
/* assert RESET signal of PHY */
immr->im_ioport.iop_pcdat &= ~(CFG_PC_ETH_RESET);
udelay (10);
/* de-assert RESET signal of PHY */
- immr->im_ioport.iop_pcdat |= CFG_PC_ETH_RESET;
+ immr->im_ioport.iop_pcdat |= CFG_PC_ETH_RESET;
udelay (10);
}
# if defined(STATUS_LED_YELLOW)
status_led_set (STATUS_LED_YELLOW,
(status < 0) ? STATUS_LED_ON : STATUS_LED_OFF);
-# endif /* STATUS_LED_YELLOW */
+# endif /* STATUS_LED_YELLOW */
# if defined(STATUS_LED_BOOT)
if (status == 6)
- status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
-# endif /* STATUS_LED_BOOT */
+ status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF);
+# endif /* STATUS_LED_BOOT */
#endif /* CONFIG_STATUS_LED */
}
/* ------------------------------------------------------------------------- */
-void ide_set_reset(int on)
+void ide_set_reset (int on)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
/*
* Configure PC for IDE Reset Pin
if (on) { /* assert RESET */
immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
} else { /* release RESET */
- immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
+ immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
}
/* program port pin as GPIO output */
immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
- immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
- immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
+ immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
+ immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
}
/* ------------------------------------------------------------------------- */
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
+ return(get_ram_size(base, maxsize));
}
#endif
#define _NOT_USED_ 0xFFFFFFFF
-const uint sdram_table[] =
-{
+const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
- 0x1ff77c47, /* last */
+ 0x1ff77c47, /* last */
/*
* SDRAM Initialization (offset 5 in UPMA RAM)
*
* sequence, which is executed by a RUN command.
*
*/
- 0x1ff77c35, 0xefeabc34, 0x1fb57c35, /* last */
+ 0x1ff77c35, 0xefeabc34, 0x1fb57c35, /* last */
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
- 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
+ 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
- 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
+ 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
- 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */
- _NOT_USED_,
+ 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */
+ _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, 0xfffffc07, /* last */
- _NOT_USED_,
+ 0xfffffc84, 0xfffffc07, 0xfffffc07, /* last */
+ _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPMA RAM)
*/
- 0x7ffffc07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0x7ffffc07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
int checkboard (void)
{
- printf("Board: Lantec special edition rev.%d\n", CONFIG_LANTEC);
+ printf ("Board: Lantec special edition rev.%d\n", CONFIG_LANTEC);
return 0;
}
long int initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size_b0;
int i;
/*
* Configure UPMA for SDRAM
*/
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+ upmconfig (UPMA, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
- memctl->memc_mptpr = CFG_MPTPR_1BK_8K /* XXX CFG_MPTPR XXX */;
+ memctl->memc_mptpr = CFG_MPTPR_1BK_8K /* XXX CFG_MPTPR XXX */ ;
/* burst length=4, burst type=sequential, CAS latency=2 */
memctl->memc_mar = 0x00000088;
/*
- * Map controller bank 3 to the SDRAM bank at preliminary address.
- */
+ * Map controller bank 3 to the SDRAM bank at preliminary address.
+ */
memctl->memc_or3 = CFG_OR3_PRELIM;
memctl->memc_br3 = CFG_BR3_PRELIM;
memctl->memc_mamr = CFG_MAMR_8COL; /* refresh not enabled yet */
/* mode initialization (offset 5) */
- udelay(200); /* 0x80006105 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x05);
+ udelay (200); /* 0x80006105 */
+ memctl->memc_mcr =
+ MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);
/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
- udelay(1); /* 0x80006130 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
- udelay(1); /* 0x80006130 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
+ udelay (1); /* 0x80006130 */
+ memctl->memc_mcr =
+ MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
+ udelay (1); /* 0x80006130 */
+ memctl->memc_mcr =
+ MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
- udelay(1); /* 0x80006106 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x06);
+ udelay (1); /* 0x80006106 */
+ memctl->memc_mcr =
+ MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */
- udelay(200);
+ udelay (200);
/* Need at least 10 DRAM accesses to stabilize */
- for (i=0; i<10; ++i) {
- volatile unsigned long *addr = \
- (volatile unsigned long *)SDRAM_BASE3_PRELIM;
+ for (i = 0; i < 10; ++i) {
+ volatile unsigned long *addr =
+ (volatile unsigned long *) SDRAM_BASE3_PRELIM;
unsigned long val;
val = *(addr + i);
}
/*
- * Check Bank 0 Memory Size for re-configuration
- */
+ * Check Bank 0 Memory Size for re-configuration
+ */
size_b0 = dram_size (CFG_MAMR_8COL,
- (ulong *)SDRAM_BASE3_PRELIM,
- SDRAM_MAX_SIZE);
+ (ulong *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
- udelay(1000);
+ udelay (1000);
return (size_b0);
}
* - short between data lines
*/
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+static long int dram_size (long int mamr_value, long int *base,
+ long int maxsize)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- memctl->memc_mamr = mamr_value;
-
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
- val = *addr;
- *addr = save[--i];
+ memctl->memc_mamr = mamr_value;
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
- }
- }
- return (maxsize);
+ return (get_ram_size (base, maxsize));
}
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
+ return (get_ram_size(base, maxsize));
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
- int i, cnt;
- volatile uchar * base= CFG_SDRAM_BASE;
- volatile ulong * addr;
- ulong save[32];
- ulong val, ret = 0;
-
- for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *)base + cnt;
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- addr = (volatile ulong *)base;
- save[i] = *addr;
- *addr = 0;
-
- if (*addr != 0) {
- *addr = save[i];
- goto Done;
- }
-
- for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *)base + cnt;
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- ulong new_bank0_end = cnt * sizeof(long) - 1;
- ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
- ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- ret = cnt * sizeof(long);
- goto Done;
- }
- }
-
- ret = CFG_MAX_RAM_SIZE;
-Done:
- return ret;
+ long size;
+ long new_bank0_end;
+ long mear1;
+ long emear1;
+
+ size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+ new_bank0_end = size - 1;
+ mear1 = mpc824x_mpc107_getreg(MEAR1);
+ emear1 = mpc824x_mpc107_getreg(EMEAR1);
+ mear1 = (mear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+ emear1 = (emear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+ mpc824x_mpc107_setreg(MEAR1, mear1);
+ mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+ return (size);
}
/*
long int initdram (int board_type)
{
- int i, cnt;
- volatile uchar *base = CFG_SDRAM_BASE;
- volatile ulong *addr;
- ulong save[32];
- ulong val, ret = 0;
-
- for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
- cnt >>= 1) {
- addr = (volatile ulong *) base + cnt;
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- addr = (volatile ulong *) base;
- save[i] = *addr;
- *addr = 0;
-
- if (*addr != 0) {
- *addr = save[i];
- goto Done;
- }
-
- for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- ulong new_bank0_end = cnt * sizeof (long) - 1;
- ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
- ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
-
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >>
- MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >>
- MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg (MEAR1, mear1);
- mpc824x_mpc107_setreg (EMEAR1, emear1);
- ret = cnt * sizeof (long);
- goto Done;
- }
- }
-
- ret = CFG_MAX_RAM_SIZE;
- Done:
- return ret;
+ long size;
+ long new_bank0_end;
+ long mear1;
+ long emear1;
+
+ size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+ new_bank0_end = size - 1;
+ mear1 = mpc824x_mpc107_getreg(MEAR1);
+ emear1 = mpc824x_mpc107_getreg(EMEAR1);
+ mear1 = (mear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+ emear1 = (emear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+ mpc824x_mpc107_setreg(MEAR1, mear1);
+ mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+ return (size);
}
/* ------------------------------------------------------------------------- */
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- long int cnt, val;
-
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- return (0);
- }
-
- for (cnt = 1;; cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
-
- if (val != (~cnt)) {
- return (cnt * sizeof (long));
- }
- }
- /* NOTREACHED */
+ return (get_ram_size(base, maxsize));
}
#define _NOT_USED_ 0xFFFFFFFF
-const uint sdram_table[] =
-{
+const uint sdram_table[] = {
#if (MPC8XX_SPEED <= 50000000L)
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
- 0x0F07EC04,
- 0x01BBD804,
- 0x1FF7F440,
- 0xFFFFFC07,
+ 0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07,
0xFFFFFFFF,
/*
* sequence, which is executed by a RUN command.
*
*/
- 0x1FE7F434,
- 0xEFABE834,
- 0x1FA7D435,
+ 0x1FE7F434, 0xEFABE834, 0x1FA7D435,
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
- 0x0F07EC04,
- 0x10EFDC04,
- 0xF0AFFC00,
- 0xF0AFFC00,
- 0xF1AFFC00,
- 0xFFAFFC40,
- 0xFFAFFC07,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
+ 0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00,
+ 0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
- 0x0E07E804,
- 0x01BBD000,
- 0x1FF7F447,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
+ 0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
- 0x0E07E800,
- 0x10EFD400,
- 0xF0AFFC00,
- 0xF0AFFC00,
- 0xF1AFFC47,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
+ 0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00,
+ 0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
- 0x1FF7DC84,
- 0xFFFFFC04,
- 0xFFFFFC84,
- 0xFFFFFC07,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
+ 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
/*
* Exception. (Offset 3c in UPMA RAM)
*/
- 0x7FFFFC07,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF
-
+ 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
#else
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
- 0x1F07FC04,
- 0xEEAFEC04,
- 0x11AFDC04,
- 0xEFBBF800,
+ 0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800,
0x1FF7F447,
/*
* sequence, which is executed by a RUN command.
*
*/
- 0x1FF7F434,
- 0xEFEBE834,
- 0x1FB7D435,
+ 0x1FF7F434, 0xEFEBE834, 0x1FB7D435,
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
- 0x1F07FC04,
- 0xEEAFEC04,
- 0x10AFDC04,
- 0xF0AFFC00,
- 0xF0AFFC00,
- 0xF1AFFC00,
- 0xEFBBF800,
- 0x1FF7F447,
+ 0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00,
+ 0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
- 0x1F07FC04,
- 0xEEAFE800,
- 0x01BBD004,
- 0x1FF7F447,
+ 0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
- 0x1F07FC04,
- 0xEEAFE800,
- 0x10AFD400,
- 0xF0AFFC00,
- 0xF0AFFC00,
- 0xE1BBF804,
- 0x1FF7F447,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00,
+ 0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
- 0x1FF7DC84,
- 0xFFFFFC04,
- 0xFFFFFC04,
- 0xFFFFFC04,
- 0xFFFFFC84,
- 0xFFFFFC07,
+ 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+ 0xFFFFFC84, 0xFFFFFC07,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
* Exception. (Offset 3c in UPMA RAM)
*/
0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
#endif
};
int checkboard (void)
{
- printf ("Board: Nexus NX823");
- return (0);
+ printf ("Board: Nexus NX823");
+ return (0);
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size_b0, size_b1, size8, size9;
-
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- /*
- * Up to 2 Banks of 64Mbit x 2 devices
- * Initial builds only have 1
- */
- memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller SDRAM bank 0
- */
- memctl->memc_or1 = CFG_OR1_PRELIM;
- memctl->memc_br1 = CFG_BR1_PRELIM;
- memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
- udelay(200);
-
- /*
- * Map controller SDRAM bank 1
- */
- memctl->memc_or2 = CFG_OR2_PRELIM;
- memctl->memc_br2 = CFG_BR2_PRELIM;
-
- /*
- * Perform SDRAM initializsation sequence
- */
- memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
- udelay(1);
- memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */
- udelay(1);
-
- memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
- udelay(1);
- memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */
- udelay(1);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
- udelay (1000);
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
-
- memctl->memc_mar = 0x00000088;
-
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration at 9 columns */
- size_b0 = size9;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size_b0, size_b1, size8, size9;
+
+ upmconfig (UPMA, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
+
+ /*
+ * Up to 2 Banks of 64Mbit x 2 devices
+ * Initial builds only have 1
+ */
+ memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
+ memctl->memc_mar = 0x00000088;
+
+ /*
+ * Map controller SDRAM bank 0
+ */
+ memctl->memc_or1 = CFG_OR1_PRELIM;
+ memctl->memc_br1 = CFG_BR1_PRELIM;
+ memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+ udelay (200);
+
+ /*
+ * Map controller SDRAM bank 1
+ */
+ memctl->memc_or2 = CFG_OR2_PRELIM;
+ memctl->memc_br2 = CFG_BR2_PRELIM;
+
+ /*
+ * Perform SDRAM initializsation sequence
+ */
+ memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
+ udelay (1);
+ memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */
+ udelay (1);
+
+ memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
+ udelay (1);
+ memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */
+ udelay (1);
+
+ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+ udelay (1000);
+
+ /*
+ * Preliminary prescaler for refresh (depends on number of
+ * banks): This value is selected for four cycles every 62.4 us
+ * with two SDRAM banks or four cycles every 31.2 us with one
+ * bank. It will be adjusted after memory sizing.
+ */
+ memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+ memctl->memc_mar = 0x00000088;
+
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ *
+ * try 8 column mode
+ */
+ size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE1_PRELIM,
+ SDRAM_MAX_SIZE);
+
+ udelay (1000);
+
+ /*
+ * try 9 column mode
+ */
+ size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE1_PRELIM,
+ SDRAM_MAX_SIZE);
+
+ if (size8 < size9) { /* leave configuration at 9 columns */
+ size_b0 = size9;
/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
- } else { /* back to 8 columns */
- size_b0 = size8;
- memctl->memc_mamr = CFG_MAMR_8COL;
- udelay(500);
+ } else { /* back to 8 columns */
+ size_b0 = size8;
+ memctl->memc_mamr = CFG_MAMR_8COL;
+ udelay (500);
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
- }
+ }
/*
* Check Bank 1 Memory Size
* [9 column SDRAM may also be used in 8 column mode,
* but then only half the real size will be used.]
*/
- size_b1 = dram_size (memctl->memc_mamr, (ulong *)SDRAM_BASE2_PRELIM,
- SDRAM_MAX_SIZE);
+ size_b1 = dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE2_PRELIM,
+ SDRAM_MAX_SIZE);
/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
- udelay (1000);
-
- /*
- * Adjust refresh rate depending on SDRAM type, both banks
- * For types > 128 MBit leave it at the current (fast) rate
- */
- if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
- /* reduce to 15.6 us (62.4 us / quad) */
- memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
- udelay(1000);
- }
-
- /*
- * Final mapping: map bigger bank first
- */
- if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
-
- memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
- memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
- if (size_b0 > 0) {
- /*
- * Position Bank 0 immediately above Bank 1
- */
- memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
- memctl->memc_br1 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
- + size_b1;
- } else {
- unsigned long reg;
- /*
- * No bank 0
- *
- * invalidate bank
- */
- memctl->memc_br1 = 0;
-
- /* adjust refresh rate depending on SDRAM type, one bank */
- reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
- memctl->memc_mptpr = reg;
+ udelay (1000);
+
+ /*
+ * Adjust refresh rate depending on SDRAM type, both banks
+ * For types > 128 MBit leave it at the current (fast) rate
+ */
+ if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
+ /* reduce to 15.6 us (62.4 us / quad) */
+ memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+ udelay (1000);
}
- } else { /* SDRAM Bank 0 is bigger - map first */
-
- memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
- memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
- if (size_b1 > 0) {
- /*
- * Position Bank 1 immediately above Bank 0
- */
- memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
- memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
- + size_b0;
- } else {
- unsigned long reg;
- /*
- * No bank 1
- *
- * invalidate bank
- */
- memctl->memc_br2 = 0;
-
- /* adjust refresh rate depending on SDRAM type, one bank */
- reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
- memctl->memc_mptpr = reg;
+ /*
+ * Final mapping: map bigger bank first
+ */
+ if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
+
+ memctl->memc_or2 =
+ ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+ memctl->memc_br2 =
+ (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+ if (size_b0 > 0) {
+ /*
+ * Position Bank 0 immediately above Bank 1
+ */
+ memctl->memc_or1 =
+ ((-size_b0) & 0xFFFF0000) |
+ CFG_OR_TIMING_SDRAM;
+ memctl->memc_br1 =
+ ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
+ BR_V)
+ + size_b1;
+ } else {
+ unsigned long reg;
+
+ /*
+ * No bank 0
+ *
+ * invalidate bank
+ */
+ memctl->memc_br1 = 0;
+
+ /* adjust refresh rate depending on SDRAM type, one bank */
+ reg = memctl->memc_mptpr;
+ reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
+ memctl->memc_mptpr = reg;
+ }
+
+ } else { /* SDRAM Bank 0 is bigger - map first */
+
+ memctl->memc_or1 =
+ ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+ memctl->memc_br1 =
+ (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+ if (size_b1 > 0) {
+ /*
+ * Position Bank 1 immediately above Bank 0
+ */
+ memctl->memc_or2 =
+ ((-size_b1) & 0xFFFF0000) |
+ CFG_OR_TIMING_SDRAM;
+ memctl->memc_br2 =
+ ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
+ BR_V)
+ + size_b0;
+ } else {
+ unsigned long reg;
+
+ /*
+ * No bank 1
+ *
+ * invalidate bank
+ */
+ memctl->memc_br2 = 0;
+
+ /* adjust refresh rate depending on SDRAM type, one bank */
+ reg = memctl->memc_mptpr;
+ reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
+ memctl->memc_mptpr = reg;
+ }
}
- }
- udelay(10000);
+ udelay (10000);
- return (size_b0 + size_b1);
+ return (size_b0 + size_b1);
}
/* ------------------------------------------------------------------------- */
* - short between data lines
*/
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+static long int dram_size (long int mamr_value, long int *base,
+ long int maxsize)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- long int cnt, val;
-
- memctl->memc_mamr = mamr_value;
-
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- *addr = ~cnt;
- }
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
- /* write 0 to base address */
- addr = base;
- *addr = 0;
+ memctl->memc_mamr = mamr_value;
- /* check at base address */
- if ((val = *addr) != 0) {
- return (0);
- }
-
- for (cnt = 1; ; cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
-
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
- }
- }
- /* NOTREACHED */
+ return (get_ram_size (base, maxsize));
}
u_long *my_sernum;
u_char *e = gd->bd->bi_enetaddr;
/* save serial numbre from flash (uniquely programmed) */
- my_sernum = malloc(8);
- memcpy(my_sernum,gd->bd->bi_sernum,8);
+ my_sernum = malloc (8);
+ memcpy (my_sernum, gd->bd->bi_sernum, 8);
/* save env variables according to sernum */
- sprintf(tmp,"%08lx%08lx",my_sernum[0],my_sernum[1]);
- setenv("serial#",tmp);
+ sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]);
+ setenv ("serial#", tmp);
- sprintf(tmp,"%02x:%02x:%02x:%02x:%02x:%02x"
- ,e[0],e[1],e[2],e[3],e[4],e[5]);
- setenv("ethaddr",tmp);
+ sprintf (tmp, "%02x:%02x:%02x:%02x:%02x:%02x", e[0], e[1], e[2], e[3],
+ e[4], e[5]);
+ setenv ("ethaddr", tmp);
return (0);
}
DECLARE_GLOBAL_DATA_PTR;
int i;
- bd_t * bd = gd->bd;
+ bd_t *bd = gd->bd;
for (i = 0; i < 8; i++) {
bd->bi_sernum[i] = *(u_char *) (CFG_FLASH_SN_BASE + i);
long int initdram (int board_type)
{
#ifndef CFG_RAMBOOT
- int i, cnt;
- volatile uchar * base= CFG_SDRAM_BASE;
- volatile ulong * addr;
- ulong save[32];
- ulong val, ret = 0;
-
- for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *)base + cnt;
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- addr = (volatile ulong *)base;
- save[i] = *addr;
- *addr = 0;
-
- if (*addr != 0) {
- *addr = save[i];
- goto Done;
- }
-
- for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *)base + cnt;
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- ulong new_bank0_end = cnt * sizeof(long) - 1;
- ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
- ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- ret = cnt * sizeof(long);
- goto Done;
- }
- }
-
- ret = CFG_MAX_RAM_SIZE;
-Done:
- return ret;
+ long size;
+ long new_bank0_end;
+ long mear1;
+ long emear1;
+
+ size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+ new_bank0_end = size - 1;
+ mear1 = mpc824x_mpc107_getreg(MEAR1);
+ emear1 = mpc824x_mpc107_getreg(EMEAR1);
+ mear1 = (mear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+ emear1 = (emear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+ mpc824x_mpc107_setreg(MEAR1, mear1);
+ mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+ return (size);
#else
/* if U-Boot starts from RAM, then suppose we have 16Mb of RAM */
return (16 << 20);
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
- volatile ulong cnt, val;
- volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
+ ulong maxsize, size;
int i;
- ulong save[32]; /* to make test non-destructive */
- ulong maxsize;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
- /*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
- i = 0;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- save[i++] = *addr;
- *addr = ~cnt;
- }
+ size = get_ram_size((long *)base, maxsize);
- addr = (volatile ulong *) base;
- save[i] = *addr;
- *addr = 0;
+ *orx_ptr = orx | ~(size - 1);
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- /* Write the actual size to ORx
- */
- *orx_ptr = orx | ~(cnt * sizeof (long) - 1);
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
+ return (size);
}
long int initdram (int board_type)
{
- int i, cnt;
- volatile uchar *base = CFG_SDRAM_BASE;
- volatile ulong *addr;
- ulong save[32];
- ulong val, ret = 0;
+ long size;
+ long new_bank0_end;
+ long mear1;
+ long emear1;
show_startup_phase (2);
- for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
- cnt >>= 1) {
- addr = (volatile ulong *) base + cnt;
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- addr = (volatile ulong *) base;
- save[i] = *addr;
- *addr = 0;
+ size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
- if (*addr != 0) {
- *addr = save[i];
- goto Done;
- }
-
- for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- ulong new_bank0_end = cnt * sizeof (long) - 1;
- ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
- ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
-
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg (MEAR1, mear1);
- mpc824x_mpc107_setreg (EMEAR1, emear1);
-
- ret = cnt * sizeof (long);
- goto Done;
- }
- }
+ new_bank0_end = size - 1;
+ mear1 = mpc824x_mpc107_getreg (MEAR1);
+ emear1 = mpc824x_mpc107_getreg (EMEAR1);
+ mear1 = (mear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+ emear1 = (emear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+ mpc824x_mpc107_setreg (MEAR1, mear1);
+ mpc824x_mpc107_setreg (EMEAR1, emear1);
- ret = CFG_MAX_RAM_SIZE;
- Done:
- show_startup_phase (3);
- return ret;
+ return (size);
}
/*
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
+ return (get_ram_size(base, maxsize));
}
/* ------------------------------------------------------------------------- */
int checkboard (void)
{
- unsigned char *s = getenv("serial#");
+ unsigned char *s = getenv ("serial#");
- if (!s || strncmp(s, "TQM8", 4)) {
- printf ("### No HW ID - assuming RBC823\n");
- return (0);
- }
+ if (!s || strncmp (s, "TQM8", 4)) {
+ printf ("### No HW ID - assuming RBC823\n");
+ return (0);
+ }
- puts(s);
- putc ('\n');
+ puts (s);
+ putc ('\n');
- return (0);
+ return (0);
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size_b0, size8, size9;
-
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- /*
- * 1 Bank of 64Mbit x 2 devices
- */
- memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller SDRAM bank 0
- */
- memctl->memc_or4 = CFG_OR4_PRELIM;
- memctl->memc_br4 = CFG_BR4_PRELIM;
- memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
- udelay(200);
-
- /*
- * Perform SDRAM initializsation sequence
- */
- memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */
- udelay(1);
- memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
- udelay(200);
- memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */
- udelay(1);
- memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
- udelay(200);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
- udelay (1000);
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CFG_MPTPR_2BK_4K; /* 16: but should be: CFG_MPTPR_1BK_4K */
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE);
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE);
-
- if (size8 < size9) { /* leave configuration at 9 columns */
- size_b0 = size9;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size_b0, size8, size9;
+
+ upmconfig (UPMA, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
+
+ /*
+ * 1 Bank of 64Mbit x 2 devices
+ */
+ memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
+ memctl->memc_mar = 0x00000088;
+
+ /*
+ * Map controller SDRAM bank 0
+ */
+ memctl->memc_or4 = CFG_OR4_PRELIM;
+ memctl->memc_br4 = CFG_BR4_PRELIM;
+ memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+ udelay (200);
+
+ /*
+ * Perform SDRAM initializsation sequence
+ */
+ memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */
+ udelay (1);
+ memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
+ udelay (200);
+ memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */
+ udelay (1);
+ memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
+ udelay (200);
+
+ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+ udelay (1000);
+
+ /*
+ * Preliminary prescaler for refresh (depends on number of
+ * banks): This value is selected for four cycles every 62.4 us
+ * with two SDRAM banks or four cycles every 31.2 us with one
+ * bank. It will be adjusted after memory sizing.
+ */
+ memctl->memc_mptpr = CFG_MPTPR_2BK_4K; /* 16: but should be: CFG_MPTPR_1BK_4K */
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ *
+ * try 8 column mode
+ */
+ size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE4_PRELIM,
+ SDRAM_MAX_SIZE);
+ udelay (1000);
+
+ /*
+ * try 9 column mode
+ */
+ size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE4_PRELIM,
+ SDRAM_MAX_SIZE);
+
+ if (size8 < size9) { /* leave configuration at 9 columns */
+ size_b0 = size9;
/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
- } else { /* back to 8 columns */
- size_b0 = size8;
- memctl->memc_mamr = CFG_MAMR_8COL;
- udelay(500);
+ } else { /* back to 8 columns */
+ size_b0 = size8;
+ memctl->memc_mamr = CFG_MAMR_8COL;
+ udelay (500);
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
- }
+ }
- udelay (1000);
+ udelay (1000);
- /*
- * Adjust refresh rate depending on SDRAM type, both banks
- * For types > 128 MBit leave it at the current (fast) rate
- */
- if ((size_b0 < 0x02000000) ) {
- /* reduce to 15.6 us (62.4 us / quad) */
- memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
- udelay(1000);
- }
+ /*
+ * Adjust refresh rate depending on SDRAM type, both banks
+ * For types > 128 MBit leave it at the current (fast) rate
+ */
+ if ((size_b0 < 0x02000000)) {
+ /* reduce to 15.6 us (62.4 us / quad) */
+ memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+ udelay (1000);
+ }
- /* SDRAM Bank 0 is bigger - map first */
+ /* SDRAM Bank 0 is bigger - map first */
- memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
- memctl->memc_br4 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+ memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+ memctl->memc_br4 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
- udelay(10000);
+ udelay (10000);
- return (size_b0);
+ return (size_b0);
}
/* ------------------------------------------------------------------------- */
* - short between data lines
*/
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+static long int dram_size (long int mamr_value, long int *base,
+ long int maxsize)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- long int cnt, val;
-
- memctl->memc_mamr = mamr_value;
-
- for (cnt = maxsize/sizeof(long)/2; cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
- *addr = ~cnt;
- }
+ memctl->memc_mamr = mamr_value;
- /* write 0 to base address */
- addr = base;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- return (0);
- }
-
- for (cnt = 1; cnt < maxsize/sizeof(long) ; cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
-
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
- }
- }
- return cnt * sizeof(long);
- /* NOTREACHED */
+ return (get_ram_size (base, maxsize));
}
-void doc_init(void)
+void doc_init (void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
- upmconfig(UPMB, (uint *)static_table, sizeof(static_table)/sizeof(uint));
- memctl->memc_mbmr = MAMR_DSA_1_CYCL;
+ upmconfig (UPMB, (uint *) static_table,
+ sizeof (static_table) / sizeof (uint));
+ memctl->memc_mbmr = MAMR_DSA_1_CYCL;
- doc_probe(FLASH_BASE1_PRELIM);
+ doc_probe (FLASH_BASE1_PRELIM);
}
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val, size;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- /* Restore the original data before leaving the function.
- */
- *addr = save[i];
- for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- size = cnt * sizeof (long);
- /* Restore the original data before returning
- */
- for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- return (size);
- }
- }
- return (maxsize);
+ return (get_ram_size(base, maxsize));
}
long int initdram (int board_type)
{
- int i, cnt;
- volatile uchar * base= CFG_SDRAM_BASE;
- volatile ulong * addr;
- ulong save[32];
- ulong val, ret = 0;
+ long size;
+ long new_bank0_end;
+ long mear1;
+ long emear1;
- for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *)base + cnt;
- save[i++] = *addr;
- *addr = ~cnt;
- }
+ size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
- addr = (volatile ulong *)base;
- save[i] = *addr;
- *addr = 0;
+ new_bank0_end = size - 1;
+ mear1 = mpc824x_mpc107_getreg(MEAR1);
+ emear1 = mpc824x_mpc107_getreg(EMEAR1);
+ mear1 = (mear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+ emear1 = (emear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+ mpc824x_mpc107_setreg(MEAR1, mear1);
+ mpc824x_mpc107_setreg(EMEAR1, emear1);
- if (*addr != 0) {
- *addr = save[i];
- goto Done;
- }
-
- for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *)base + cnt;
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- ulong new_bank0_end = cnt * sizeof(long) - 1;
- ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
- ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- ret = cnt * sizeof(long);
- goto Done;
- }
- }
-
- ret = CFG_MAX_RAM_SIZE;
-Done:
- return ret;
+ return (size);
}
/*
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
- }
- }
- return (maxsize);
+ return (get_ram_size(base, maxsize));
}
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFFFFF
-const uint sdram_table[] =
-{
+const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
- 0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47, /* last */
+ 0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47, /* last */
_NOT_USED_,
/*
* SDRAM Initialization (offset 5 in UPMA RAM)
* sequence, which is executed by a RUN command.
*
*/
- 0xFFFAF834, 0xFFE5B435, /* last */
- _NOT_USED_,
+ 0xFFFAF834, 0xFFE5B435, /* last */
+ _NOT_USED_,
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00,
- 0xF0AFFC00, 0xF0AAF800, 0xF1A5E447, /* last */
- _NOT_USED_,
+ 0xF0AFFC00, 0xF0AAF800, 0xF1A5E447, /* last */
+ _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
- 0xFE29B300, 0xF1A27304, 0xFFA5F747, /* last */
- _NOT_USED_,
+ 0xFE29B300, 0xF1A27304, 0xFFA5F747, /* last */
+ _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
- 0xF1AAF804, 0xFFA5F447, /* last */
- _NOT_USED_, _NOT_USED_,
+ 0xF1AAF804, 0xFFA5F447, /* last */
+ _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84,
- 0xFFAFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0xFFAFFC07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* MRS sequence (Offset 38 in UPMA RAM)
*/
- 0xFFAAB834, 0xFFA57434, 0xFFAFFC05, /* last */
- _NOT_USED_,
+ 0xFFAAB834, 0xFFA57434, 0xFFAFFC05, /* last */
+ _NOT_USED_,
/*
* Exception. (Offset 3c in UPMA RAM)
*/
- 0xFFAFFC04, 0xFFAFFC05, /* last */
- _NOT_USED_, _NOT_USED_,
+ 0xFFAFFC04, 0xFFAFFC05, /* last */
+ _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile iop8xx_t *iop = &immap->im_ioport;
- volatile fec_t *fecp = &immap->im_cpm.cp_fec;
- long int size;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile iop8xx_t *iop = &immap->im_ioport;
+ volatile fec_t *fecp = &immap->im_cpm.cp_fec;
+ long int size;
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+ upmconfig (UPMA, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CFG_MPTPR;
+ /*
+ * Preliminary prescaler for refresh (depends on number of
+ * banks): This value is selected for four cycles every 62.4 us
+ * with two SDRAM banks or four cycles every 31.2 us with one
+ * bank. It will be adjusted after memory sizing.
+ */
+ memctl->memc_mptpr = CFG_MPTPR;
- memctl->memc_mar = 0x00000088;
+ memctl->memc_mar = 0x00000088;
- /*
- * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
- * preliminary addresses - these have to be modified after the
- * SDRAM size has been determined.
- */
- memctl->memc_or2 = CFG_OR2_PRELIM;
- memctl->memc_br2 = CFG_BR2_PRELIM;
+ /*
+ * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+ * preliminary addresses - these have to be modified after the
+ * SDRAM size has been determined.
+ */
+ memctl->memc_or2 = CFG_OR2_PRELIM;
+ memctl->memc_br2 = CFG_BR2_PRELIM;
- memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
+ memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
- udelay(200);
+ udelay (200);
- /* perform SDRAM initializsation sequence */
+ /* perform SDRAM initializsation sequence */
- memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
- udelay(1);
- memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
- udelay(1);
+ memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
+ udelay (1);
+ memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
+ udelay (1);
- memctl->memc_mcr = 0x80004105; /* SDRAM precharge */
- udelay(1);
- memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */
- udelay(1);
- memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */
- udelay(1);
+ memctl->memc_mcr = 0x80004105; /* SDRAM precharge */
+ udelay (1);
+ memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */
+ udelay (1);
+ memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */
+ udelay (1);
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
- udelay (1000);
+ udelay (1000);
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- */
- size = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ *
+ */
+ size = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE_PRELIM,
+ SDRAM_MAX_SIZE);
- udelay (1000);
+ udelay (1000);
- memctl->memc_mamr = CFG_MAMR;
- udelay (1000);
+ memctl->memc_mamr = CFG_MAMR;
+ udelay (1000);
- /*
- * Final mapping
- */
- memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM;
- memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
+ /*
+ * Final mapping
+ */
+ memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM;
+ memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
- udelay(10000);
+ udelay (10000);
- /* prepare pin multiplexing for fast ethernet */
+ /* prepare pin multiplexing for fast ethernet */
- atmLoad();
- fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
- iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
+ atmLoad ();
+ fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
+ iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
- return (size);
+ return (size);
}
/* ------------------------------------------------------------------------- */
* - short between data lines
*/
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+static long int dram_size (long int mamr_value, long int *base,
+ long int maxsize)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- memctl->memc_mamr = mamr_value;
-
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
- for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
+ memctl->memc_mamr = mamr_value;
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
- }
- }
- return (maxsize);
+ return (get_ram_size (base, maxsize));
}
/*
int checkboard (void)
{
- return (0);
+ return (0);
}
-void board_serial_init(void)
+void board_serial_init (void)
{
- ;/* nothing to do here */
+ ; /* nothing to do here */
}
-void board_ether_init(void)
+void board_ether_init (void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile iop8xx_t *iop = &immap->im_ioport;
- volatile fec_t *fecp = &immap->im_cpm.cp_fec;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile iop8xx_t *iop = &immap->im_ioport;
+ volatile fec_t *fecp = &immap->im_cpm.cp_fec;
- atmLoad();
- fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
- iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
+ atmLoad ();
+ fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
+ iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
}
int board_pre_init (void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile iop8xx_t *iop = &immap->im_ioport;
-
- /* configure the LED timing output pins - port A pin 4 */
- iop->iop_papar = 0x0800;
- iop->iop_padir = 0x0800;
-
- /* start timer 2 for the 4hz LED blink rate */
- timers->cpmt_tmr2 = 0xff2c; /* 4hz for 64mhz */
- timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */
- timers->cpmt_tgcr = 0x00000810; /* run timer 2 */
-
- /* chip select for PLD access */
- memctl->memc_br6 = 0x10000401;
- memctl->memc_or6 = 0xFC000908;
-
- /* PLD initial values ( set LEDs, remove reset on LXT) */
-
- *PLD_GCR1_REG = 0x06;
- *PLD_EXT_RES = 0xC0;
- *PLD_EXT_FETH = 0x40;
- *PLD_EXT_LED = 0xFF;
- *PLD_EXT_X21 = 0x04;
- return 0;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile iop8xx_t *iop = &immap->im_ioport;
+
+ /* configure the LED timing output pins - port A pin 4 */
+ iop->iop_papar = 0x0800;
+ iop->iop_padir = 0x0800;
+
+ /* start timer 2 for the 4hz LED blink rate */
+ timers->cpmt_tmr2 = 0xff2c; /* 4hz for 64mhz */
+ timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */
+ timers->cpmt_tgcr = 0x00000810; /* run timer 2 */
+
+ /* chip select for PLD access */
+ memctl->memc_br6 = 0x10000401;
+ memctl->memc_or6 = 0xFC000908;
+
+ /* PLD initial values ( set LEDs, remove reset on LXT) */
+
+ *PLD_GCR1_REG = 0x06;
+ *PLD_EXT_RES = 0xC0;
+ *PLD_EXT_FETH = 0x40;
+ *PLD_EXT_LED = 0xFF;
+ *PLD_EXT_X21 = 0x04;
+ return 0;
}
-void board_get_enetaddr (uchar *addr)
+void board_get_enetaddr (uchar * addr)
{
- int i;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile cpm8xx_t *cpm = &immap->im_cpm;
- unsigned int rccrtmp;
-
- char default_mac_addr[] = {0x00, 0x08, 0x01, 0x02, 0x03, 0x04};
-
- for (i=0; i<6; i++)
- addr[i] = default_mac_addr[i];
+ int i;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile cpm8xx_t *cpm = &immap->im_cpm;
+ unsigned int rccrtmp;
- printf("There is an error in the i2c driver .. /n");
- printf("You need to fix it first....../n");
+ char default_mac_addr[] = { 0x00, 0x08, 0x01, 0x02, 0x03, 0x04 };
- rccrtmp = cpm->cp_rccr;
- cpm->cp_rccr |= 0x0020;
+ for (i = 0; i < 6; i++)
+ addr[i] = default_mac_addr[i];
- i2c_reg_read(0xa0, 0);
- printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
- i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0),
- i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0) );
+ printf ("There is an error in the i2c driver .. /n");
+ printf ("You need to fix it first....../n");
- cpm->cp_rccr = rccrtmp;
+ rccrtmp = cpm->cp_rccr;
+ cpm->cp_rccr |= 0x0020;
+ i2c_reg_read (0xa0, 0);
+ printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
+ i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
+ i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
+ i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0));
+ cpm->cp_rccr = rccrtmp;
}
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
- ulong cnt, val;
- volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
+ ulong maxsize, size;
int i;
- ulong save[32]; /* to make test non-destructive */
- ulong maxsize;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
- /*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
- i = 0;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- save[i++] = *addr;
- *addr = ~cnt;
- }
+ size = get_ram_size((long *)base, maxsize);
- addr = (volatile ulong *) base;
- save[i] = *addr;
- *addr = 0;
+ *orx_ptr = orx | ~(size - 1);
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- /* Write the actual size to ORx
- */
- *orx_ptr = orx | ~(cnt * sizeof (long) - 1);
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
+ return (size);
}
/*
static long int dram_size (long int, long int *, long int);
static void puma_status (void);
static void puma_set_mode (int mode);
-static int puma_init_done (void);
+static int puma_init_done (void);
static void puma_load (ulong addr, ulong len);
/* ------------------------------------------------------------------------- */
/*
* 50 MHz SDRAM access using UPM A
*/
-const uint sdram_table[] =
-{
+const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPM RAM)
*/
0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00,
- 0x1ffddc47, /* last */
+ 0x1ffddc47, /* last */
/*
* SDRAM Initialization (offset 5 in UPM RAM)
*
* sequence, which is executed by a RUN command.
*
*/
- 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */
+ 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */
/*
* Burst Read. (Offset 8 in UPM RAM)
*/
0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00,
- 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
+ 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPM RAM)
*/
- 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */
+ 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPM RAM)
*/
0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00,
- 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */
- _NOT_USED_,
+ 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */
+ _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPM RAM)
*/
0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, /* last */
- _NOT_USED_, _NOT_USED_,
+ 0xfffffc84, 0xfffffc07, /* last */
+ _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPM RAM)
*/
- 0x7ffffc07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0x7ffffc07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
/*
* PUMA access using UPM B
*/
-const uint puma_table[] =
-{
+const uint puma_table[] = {
/*
* Single Read. (Offset 0 in UPM RAM)
*/
/*
* Precharge and MRS
*/
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Read. (Offset 8 in UPM RAM)
*/
/*
* Single Write. (Offset 18 in UPM RAM)
*/
- 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
- _NOT_USED_,
+ 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
+ _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPM RAM)
/*
* Exception. (Offset 3c in UPM RAM)
*/
- 0x7ffffc07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0x7ffffc07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
-long int
-initdram (int board_type)
+long int initdram (int board_type)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
- long int size_b0, reg;
- int i;
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immr->im_memctl;
+ long int size_b0, reg;
+ int i;
- /*
- * Configure UPMA for SDRAM
- */
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+ /*
+ * Configure UPMA for SDRAM
+ */
+ upmconfig (UPMA, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
- memctl->memc_mptpr = CFG_MPTPR;
+ memctl->memc_mptpr = CFG_MPTPR;
- /* burst length=4, burst type=sequential, CAS latency=2 */
- memctl->memc_mar = 0x00000088;
+ /* burst length=4, burst type=sequential, CAS latency=2 */
+ memctl->memc_mar = 0x00000088;
- /*
- * Map controller bank 2 to the SDRAM bank at preliminary address.
- */
+ /*
+ * Map controller bank 2 to the SDRAM bank at preliminary address.
+ */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- memctl->memc_or5 = CFG_OR5_PRELIM;
- memctl->memc_br5 = CFG_BR5_PRELIM;
-#else /* XXX */
- memctl->memc_or2 = CFG_OR2_PRELIM;
- memctl->memc_br2 = CFG_BR2_PRELIM;
-#endif /* XXX */
+ memctl->memc_or5 = CFG_OR5_PRELIM;
+ memctl->memc_br5 = CFG_BR5_PRELIM;
+#else /* XXX */
+ memctl->memc_or2 = CFG_OR2_PRELIM;
+ memctl->memc_br2 = CFG_BR2_PRELIM;
+#endif /* XXX */
- /* initialize memory address register */
- memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */
+ /* initialize memory address register */
+ memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */
- /* mode initialization (offset 5) */
+ /* mode initialization (offset 5) */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- udelay(200); /* 0x8000A105 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x05);
-#else /* XXX */
- udelay(200); /* 0x80004105 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x05);
-#endif /* XXX */
-
- /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
+ udelay (200); /* 0x8000A105 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05);
+#else /* XXX */
+ udelay (200); /* 0x80004105 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05);
+#endif /* XXX */
+
+ /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- udelay(1); /* 0x8000A830 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(8) | MCR_MAD(0x30);
-#else /* XXX */
- udelay(1); /* 0x80004830 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(8) | MCR_MAD(0x30);
-#endif /* XXX */
+ udelay (1); /* 0x8000A830 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30);
+#else /* XXX */
+ udelay (1); /* 0x80004830 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30);
+#endif /* XXX */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- udelay(1); /* 0x8000A106 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x06);
-#else /* XXX */
- udelay(1); /* 0x80004106 */
- memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x06);
-#endif /* XXX */
-
- reg = memctl->memc_mamr;
- reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */
- reg |= MAMR_TLFA_4X; /* ... to 4x */
- reg |= MAMR_PTAE; /* enable refresh */
- memctl->memc_mamr = reg;
-
- udelay(200);
-
- /* Need at least 10 DRAM accesses to stabilize */
- for (i=0; i<10; ++i) {
+ udelay (1); /* 0x8000A106 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06);
+#else /* XXX */
+ udelay (1); /* 0x80004106 */
+ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06);
+#endif /* XXX */
+
+ reg = memctl->memc_mamr;
+ reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */
+ reg |= MAMR_TLFA_4X; /* ... to 4x */
+ reg |= MAMR_PTAE; /* enable refresh */
+ memctl->memc_mamr = reg;
+
+ udelay (200);
+
+ /* Need at least 10 DRAM accesses to stabilize */
+ for (i = 0; i < 10; ++i) {
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE5_PRELIM;
-#else /* XXX */
- volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE2_PRELIM;
-#endif /* XXX */
- unsigned long val;
-
- val = *(addr + i);
- *(addr + i) = val;
- }
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- */
+ volatile unsigned long *addr =
+ (volatile unsigned long *) SDRAM_BASE5_PRELIM;
+#else /* XXX */
+ volatile unsigned long *addr =
+ (volatile unsigned long *) SDRAM_BASE2_PRELIM;
+#endif /* XXX */
+ unsigned long val;
+
+ val = *(addr + i);
+ *(addr + i) = val;
+ }
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
-#else /* XXX */
- size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
-#endif /* XXX */
+ size_b0 = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
+#else /* XXX */
+ size_b0 = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+#endif /* XXX */
- memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
+ memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
- /*
- * Final mapping:
- */
+ /*
+ * Final mapping:
+ */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
- memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-#else /* XXX */
- memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
- memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-#endif /* XXX */
- udelay(1000);
-
- /*
- * Configure UPMB for PUMA
- */
- upmconfig(UPMB, (uint *)puma_table, sizeof(puma_table)/sizeof(uint));
-
- return (size_b0);
+ memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
+ memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+#else /* XXX */
+ memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
+ memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+#endif /* XXX */
+ udelay (1000);
+
+ /*
+ * Configure UPMB for PUMA
+ */
+ upmconfig (UPMB, (uint *) puma_table,
+ sizeof (puma_table) / sizeof (uint));
+
+ return (size_b0);
}
/* ------------------------------------------------------------------------- */
* - short between data lines
*/
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+static long int dram_size (long int mamr_value, long int *base,
+ long int maxsize)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- memctl->memc_mamr = mamr_value;
-
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immr->im_memctl;
- val = *addr;
- *addr = save[--i];
+ memctl->memc_mamr = mamr_value;
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
- }
- }
- return (maxsize);
+ return (get_ram_size (base, maxsize));
}
/* ------------------------------------------------------------------------- */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
-#else /* XXX */
+#else /* XXX */
#define ETH_CFG_BITS (CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \
CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
#endif /* XXX */
#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET)
-void reset_phy(void)
+void reset_phy (void)
{
- immap_t *immr = (immap_t *)CFG_IMMR;
+ immap_t *immr = (immap_t *) CFG_IMMR;
ulong value;
/* Configure all needed port pins for GPIO */
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
# if CFG_ETH_MDDIS_VALUE
- immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
+ immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
# else
immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS); /* Set low */
# endif
immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS); /* GPIO */
immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS); /* active output */
- immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS; /* output */
+ immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS; /* output */
#endif /* XXX */
immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
- value = immr->im_cpm.cp_pbdat;
+ value = immr->im_cpm.cp_pbdat;
/* Assert Powerdown and Reset signals */
- value |= CFG_PB_ETH_POWERDOWN;
+ value |= CFG_PB_ETH_POWERDOWN;
value &= ~(CFG_PB_ETH_RESET);
/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
#if !PCU_E_WITH_SWAPPED_CS
# if CFG_ETH_MDDIS_VALUE
- value |= CFG_PB_ETH_MDDIS;
+ value |= CFG_PB_ETH_MDDIS;
# else
value &= ~(CFG_PB_ETH_MDDIS);
# endif
#endif
#if CFG_ETH_CFG1_VALUE
- value |= CFG_PB_ETH_CFG1;
+ value |= CFG_PB_ETH_CFG1;
#else
value &= ~(CFG_PB_ETH_CFG1);
#endif
#if CFG_ETH_CFG2_VALUE
- value |= CFG_PB_ETH_CFG2;
+ value |= CFG_PB_ETH_CFG2;
#else
value &= ~(CFG_PB_ETH_CFG2);
#endif
#if CFG_ETH_CFG3_VALUE
- value |= CFG_PB_ETH_CFG3;
+ value |= CFG_PB_ETH_CFG3;
#else
value &= ~(CFG_PB_ETH_CFG3);
#endif
/* Drive output signals to initial state */
- immr->im_cpm.cp_pbdat = value;
+ immr->im_cpm.cp_pbdat = value;
immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
udelay (10000);
/* De-assert Ethernet Powerdown */
- immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
+ immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
udelay (10000);
/* de-assert RESET signal of PHY */
- immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET;
+ immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET;
udelay (1000);
}
#define PUMA_READ_MODE 0
#define PUMA_LOAD_MODE 1
-int do_puma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
ulong addr, len;
switch (argc) {
- case 2: /* PUMA reset */
- if (strncmp(argv[1], "stat", 4) == 0) { /* Reset */
+ case 2: /* PUMA reset */
+ if (strncmp (argv[1], "stat", 4) == 0) { /* Reset */
puma_status ();
return 0;
}
break;
- case 4: /* PUMA load addr len */
- if (strcmp(argv[1],"load") != 0)
+ case 4: /* PUMA load addr len */
+ if (strcmp (argv[1], "load") != 0)
break;
- addr = simple_strtoul(argv[2], NULL, 16);
- len = simple_strtoul(argv[3], NULL, 16);
+ addr = simple_strtoul (argv[2], NULL, 16);
+ len = simple_strtoul (argv[3], NULL, 16);
printf ("PUMA load: addr %08lX len %ld (0x%lX): ",
addr, len, len);
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
-U_BOOT_CMD(
- puma, 4, 1, do_puma,
- "puma - access PUMA FPGA\n",
- "status - print PUMA status\n"
- "puma load addr len - load PUMA configuration data\n"
-);
-#endif /* CFG_CMD_BSP */
+U_BOOT_CMD (puma, 4, 1, do_puma,
+ "puma - access PUMA FPGA\n",
+ "status - print PUMA status\n"
+ "puma load addr len - load PUMA configuration data\n");
+
+#endif /* CFG_CMD_BSP */
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
static void puma_set_mode (int mode)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
/* disable PUMA in memory controller */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- memctl->memc_br3 = 0;
-#else /* XXX */
- memctl->memc_br4 = 0;
-#endif /* XXX */
+ memctl->memc_br3 = 0;
+#else /* XXX */
+ memctl->memc_br4 = 0;
+#endif /* XXX */
switch (mode) {
case PUMA_READ_MODE:
#if PCU_E_WITH_SWAPPED_CS /* XXX */
memctl->memc_or3 = PUMA_CONF_OR_READ;
memctl->memc_br3 = PUMA_CONF_BR_READ;
-#else /* XXX */
+#else /* XXX */
memctl->memc_or4 = PUMA_CONF_OR_READ;
memctl->memc_br4 = PUMA_CONF_BR_READ;
-#endif /* XXX */
+#endif /* XXX */
break;
case PUMA_LOAD_MODE:
#if PCU_E_WITH_SWAPPED_CS /* XXX */
memctl->memc_or3 = PUMA_CONF_OR_LOAD;
memctl->memc_br3 = PUMA_CONF_BR_LOAD;
-#else /* XXX */
+#else /* XXX */
memctl->memc_or4 = PUMA_CONF_OR_READ;
memctl->memc_br4 = PUMA_CONF_BR_READ;
-#endif /* XXX */
+#endif /* XXX */
break;
}
}
static void puma_load (ulong addr, ulong len)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile uchar *fpga_addr = (volatile uchar *)PUMA_CONF_BASE; /* XXX ??? */
- uchar *data = (uchar *)addr;
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */
+ uchar *data = (uchar *) addr;
int i;
/* align length */
immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_INIT);
immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT);
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG); /* GPIO */
immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG); /* active output */
immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG); /* Set low */
#endif /* XXX */
udelay (100);
-#if PCU_E_WITH_SWAPPED_CS /* XXX */
- immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG; /* release reset */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+ immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG; /* release reset */
#else
- immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG; /* release reset */
+ immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG; /* release reset */
#endif /* XXX */
/* wait until INIT indicates completion of reset */
- for (i=0; i<PUMA_INIT_TIMEOUT; ++i) {
+ for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) {
udelay (1000);
if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT)
break;
{
/* Check state */
printf ("PUMA initialization is %scomplete\n",
- puma_init_done() ? "" : "NOT ");
+ puma_init_done ()? "" : "NOT ");
}
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
static int puma_init_done (void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
/* make sure pin is GPIO input */
immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE);
- immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE);
+ immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE);
immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE);
return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0;
int misc_init_r (void)
{
ulong addr = 0;
- ulong len = 0;
+ ulong len = 0;
char *s;
printf ("PUMA: ");
- if (puma_init_done()) {
+ if (puma_init_done ()) {
printf ("initialized\n");
return 0;
}
- if ((s = getenv("puma_addr")) != NULL)
- addr = simple_strtoul(s, NULL, 16);
+ if ((s = getenv ("puma_addr")) != NULL)
+ addr = simple_strtoul (s, NULL, 16);
- if ((s = getenv("puma_len")) != NULL)
- len = simple_strtoul(s, NULL, 16);
+ if ((s = getenv ("puma_len")) != NULL)
+ len = simple_strtoul (s, NULL, 16);
if ((!addr) || (!len)) {
printf ("net list undefined\n");
long int initdram (int board_type)
{
#ifndef CFG_RAMBOOT
- int i, cnt;
- volatile uchar * base= CFG_SDRAM_BASE;
- volatile ulong * addr;
- ulong save[32];
- ulong val, ret = 0;
+ long size;
+ long new_bank0_end;
+ long mear1;
+ long emear1;
- for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *)base + cnt;
- save[i++] = *addr;
- *addr = ~cnt;
- }
+ size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
- addr = (volatile ulong *)base;
- save[i] = *addr;
- *addr = 0;
+ new_bank0_end = size - 1;
+ mear1 = mpc824x_mpc107_getreg(MEAR1);
+ emear1 = mpc824x_mpc107_getreg(EMEAR1);
+ mear1 = (mear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+ emear1 = (emear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+ mpc824x_mpc107_setreg(MEAR1, mear1);
+ mpc824x_mpc107_setreg(EMEAR1, emear1);
- if (*addr != 0) {
- *addr = save[i];
- goto Done;
- }
-
- for (cnt = 1; cnt < CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *)base + cnt;
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- ulong new_bank0_end = cnt * sizeof(long) - 1;
- ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
- ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- ret = cnt * sizeof(long);
- goto Done;
- }
- }
-
- ret = CFG_MAX_RAM_SIZE;
-Done:
- return ret;
+ return (size);
#else
return CFG_MAX_RAM_SIZE;
#endif
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- long int cnt, val;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- return (0);
- }
-
- for (cnt = 1; ; cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
- val = *addr;
-
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
- }
- }
- /* NOTREACHED */
+ return (get_ram_size(base, maxsize));
}
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- long int cnt, val;
memctl->memc_mbmr = mbmr_value;
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- return (0);
- }
-
- for (cnt = 1; ; cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
- val = *addr;
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
- }
- }
- /* NOTREACHED */
+ return (get_ram_size(base, maxsize));
}
#define _NOT_USED_ 0xFFFFFFFF
-const uint sharc_table[] =
-{
+const uint sharc_table[] = {
/*
* Single Read. (Offset 0 in UPM RAM)
*/
0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
- 0xFFFFEC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0xFFFFEC05, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Read. (Offset 8 in UPM RAM)
*/
* Single Write. (Offset 18 in UPM RAM)
*/
0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
- 0xFFFFEC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0xFFFFEC05, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPM RAM)
*/
/*
* Exception. (Offset 3c in UPM RAM)
*/
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0x7FFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
};
-const uint sdram_table[] =
-{
+const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPM RAM)
*/
0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
- 0x1FF77C47, /* last */
+ 0x1FF77C47, /* last */
/*
* SDRAM Initialization (offset 5 in UPM RAM)
*
* sequence, which is executed by a RUN command.
*
*/
- 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
+ 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
/*
* Burst Read. (Offset 8 in UPM RAM)
*/
0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
- 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
+ 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPM RAM)
*/
- 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
+ 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPM RAM)
*/
0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
- 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
- _NOT_USED_,
+ 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
+ _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPM RAM)
*/
0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
- 0xFFFFFC84, 0xFFFFFC07, /* last */
- _NOT_USED_, _NOT_USED_,
+ 0xFFFFFC84, 0xFFFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPM RAM)
*/
- 0x7FFFFC07, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0x7FFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
-long int
-initdram (int board_type)
+long int initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size_b0;
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size_b0;
#if 0
- /*
- * Map controller bank 2 to the SRAM bank at preliminary address.
- */
- memctl->memc_or2 = CFG_OR2;
- memctl->memc_br2 = CFG_BR2;
+ /*
+ * Map controller bank 2 to the SRAM bank at preliminary address.
+ */
+ memctl->memc_or2 = CFG_OR2;
+ memctl->memc_br2 = CFG_BR2;
#endif
- /*
- * Map controller bank 4 to the PER8 bank.
- */
- memctl->memc_or4 = CFG_OR4;
- memctl->memc_br4 = CFG_BR4;
+ /*
+ * Map controller bank 4 to the PER8 bank.
+ */
+ memctl->memc_or4 = CFG_OR4;
+ memctl->memc_br4 = CFG_BR4;
#if 0
- /* Configure SHARC at UMA */
- upmconfig(UPMA, (uint *)sharc_table, sizeof(sharc_table)/sizeof(uint));
- /* Map controller bank 5 to the SHARC */
- memctl->memc_or5 = CFG_OR5;
- memctl->memc_br5 = CFG_BR5;
+ /* Configure SHARC at UMA */
+ upmconfig (UPMA, (uint *) sharc_table,
+ sizeof (sharc_table) / sizeof (uint));
+ /* Map controller bank 5 to the SHARC */
+ memctl->memc_or5 = CFG_OR5;
+ memctl->memc_br5 = CFG_BR5;
#endif
- memctl->memc_mamr = 0x00001000;
+ memctl->memc_mamr = 0x00001000;
- /* Configure SDRAM at UMB */
- upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+ /* Configure SDRAM at UMB */
+ upmconfig (UPMB, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
- memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+ memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
- memctl->memc_mar = 0x00000088;
+ memctl->memc_mar = 0x00000088;
- /*
- * Map controller bank 3 to the SDRAM bank at preliminary address.
- */
- memctl->memc_or3 = CFG_OR3_PRELIM;
- memctl->memc_br3 = CFG_BR3_PRELIM;
+ /*
+ * Map controller bank 3 to the SDRAM bank at preliminary address.
+ */
+ memctl->memc_or3 = CFG_OR3_PRELIM;
+ memctl->memc_br3 = CFG_BR3_PRELIM;
- memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
+ memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
- udelay(200);
- memctl->memc_mcr = 0x80806105;
- udelay(1);
- memctl->memc_mcr = 0x80806130;
- udelay(1);
- memctl->memc_mcr = 0x80806130;
- udelay(1);
- memctl->memc_mcr = 0x80806106;
+ udelay (200);
+ memctl->memc_mcr = 0x80806105;
+ udelay (1);
+ memctl->memc_mcr = 0x80806130;
+ udelay (1);
+ memctl->memc_mcr = 0x80806130;
+ udelay (1);
+ memctl->memc_mcr = 0x80806106;
- memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
+ memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
- /*
- * Check Bank 0 Memory Size for re-configuration
- */
- size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ */
+ size_b0 =
+ dram_size (CFG_MBMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
+ SDRAM_MAX_SIZE);
- memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
+ memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
- return (size_b0);
+ return (size_b0);
}
/* ------------------------------------------------------------------------- */
* - short between data lines
*/
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+static long int dram_size (long int mamr_value, long int *base,
+ long int maxsize)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
-
- memctl->memc_mbmr = mamr_value;
-
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
- val = *addr;
- *addr = save[--i];
+ memctl->memc_mbmr = mamr_value;
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
- }
- }
- return (maxsize);
+ return (get_ram_size (base, maxsize));
}
/* ------------------------------------------------------------------------- */
-void reset_phy(void)
+void reset_phy (void)
{
- immap_t *immr = (immap_t *)CFG_IMMR;
+ immap_t *immr = (immap_t *) CFG_IMMR;
ushort sreg;
/* Configure extra port pins for NS DP83843 PHY */
immr->im_ioport.iop_papar &= ~(PA_ENET_MDC | PA_ENET_MDIO);
- sreg = immr->im_ioport.iop_padir;
- sreg |= PA_ENET_MDC; /* Mgmt. Data Clock is Output */
+ sreg = immr->im_ioport.iop_padir;
+ sreg |= PA_ENET_MDC; /* Mgmt. Data Clock is Output */
sreg &= ~(PA_ENET_MDIO); /* Mgmt. Data I/O is bidirect. => Input */
immr->im_ioport.iop_padir = sreg;
* Configure RESET pins for NS DP83843 PHY, and RESET chip.
*
* Note: The RESET pin is high active, but there is an
- * inverter on the SPD823TS board...
+ * inverter on the SPD823TS board...
*/
immr->im_ioport.iop_pcpar &= ~(PC_ENET_RESET);
- immr->im_ioport.iop_pcdir |= PC_ENET_RESET;
+ immr->im_ioport.iop_pcdir |= PC_ENET_RESET;
/* assert RESET signal of PHY */
immr->im_ioport.iop_pcdat &= ~(PC_ENET_RESET);
udelay (10);
/* de-assert RESET signal of PHY */
- immr->im_ioport.iop_pcdat |= PC_ENET_RESET;
+ immr->im_ioport.iop_pcdat |= PC_ENET_RESET;
udelay (10);
}
/* ------------------------------------------------------------------------- */
-void ide_set_reset(int on)
+void ide_set_reset (int on)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
/*
* Configure PC for IDE Reset Pin
if (on) { /* assert RESET */
immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
} else { /* release RESET */
- immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
+ immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
}
/* program port pin as GPIO output */
immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
- immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
- immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
+ immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
+ immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
}
/* ------------------------------------------------------------------------- */
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
- ulong cnt, val;
- volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
- int i;
- ulong save[32]; /* to make test non-destructive */
ulong maxsize, size;
+ int i;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
- /*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
- i = 0;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- save[i++] = *addr;
- *addr = ~cnt;
- }
+ size = get_ram_size((long *)base, maxsize);
+ *orx_ptr = orx | ~(size - 1);
- addr = (volatile ulong *) base;
- save[i] = *addr;
- *addr = 0;
-
- if ((val = *addr) != 0) {
- /* Restore the original data before leaving the function. */
- *addr = save[i];
- for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- size = cnt * sizeof (long);
- /* Restore the original data before leaving the function. */
- for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- /* Write the actual size to ORx
- */
- *orx_ptr = orx | ~(size - 1);
- return (size);
- }
- }
- return (maxsize);
+ return (size);
}
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val, size;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- /* Restore the original data before leaving the function.
- */
- *addr = save[i];
- for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- size = cnt * sizeof (long);
- /* Restore the original data before returning
- */
- for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- return (size);
- }
- }
- return (maxsize);
+ return (get_ram_size(base, maxsize));
}
/* ------------------------------------------------------------------------- */
long int initdram(int board_type)
{
#if 1
- int i, cnt;
- volatile uchar *base = CFG_SDRAM_BASE;
- volatile ulong *addr;
- ulong save[SAVE_SZ];
- ulong val, ret = 0;
+ long size;
+ long new_bank0_end;
+ long mear1;
+ long emear1;
/*
write_bat(IBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP),
( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE));
write_bat(DBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP),
( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE));
*/
- for (i=0; i<SAVE_SZ; i++) {
- save[i] = 0; /* clear table */
- }
-
- for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *)base + cnt;
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- addr = (volatile ulong *)base;
- save[i] = *addr;
- *addr = 0;
-
- if (*addr != 0) {
- *addr = save[i];
- goto Done;
- }
-
- for (cnt = 1; cnt < CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *)base + cnt;
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- ulong new_bank0_end = cnt * sizeof(long) - 1;
- ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
- ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- ret = cnt * sizeof(long);
- goto Done;
- }
- }
-
- ret = CFG_MAX_RAM_SIZE;
-Done:
- return ret;
+ size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+ new_bank0_end = size - 1;
+ mear1 = mpc824x_mpc107_getreg(MEAR1);
+ emear1 = mpc824x_mpc107_getreg(EMEAR1);
+ mear1 = (mear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+ emear1 = (emear1 & 0xFFFFFF00) |
+ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+ mpc824x_mpc107_setreg(MEAR1, mear1);
+ mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+ return (size);
#else
return (CFG_MAX_RAM_SIZE);
#endif
#include "errors.h"
#include <watchdog.h>
-unsigned long get_dram_size(void);
+unsigned long get_dram_size (void);
/*
* Macros to transform values
int board_pre_init (void)
{
#if defined(CONFIG_W7OLMG)
- /*
- * Setup GPIO pins - reset devices.
- */
- out32(IBM405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
- out32(IBM405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
- out32(IBM405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
- */
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
-
- mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
- mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
- mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,
- INT0 highest priority*/
-
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ /*
+ * Setup GPIO pins - reset devices.
+ */
+ out32 (IBM405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
+ out32 (IBM405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
+ out32 (IBM405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
+ */
+ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (uicer, 0x00000000); /* disable all ints */
+
+ mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
+ mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
+ mtdcr (uictr, 0x10000000); /* set int trigger levels */
+ mtdcr (uicvcr, 0x00000001); /* set vect base=0,
+ INT0 highest priority */
+
+ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
#elif defined(CONFIG_W7OLMC)
- /*
- * Setup GPIO pins
- */
- out32(IBM405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
- out32(IBM405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
- out32(IBM405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
- */
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
-
- mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
- mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
- mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,
- INT0 highest priority*/
-
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
-
-#else /* Unknown */
+ /*
+ * Setup GPIO pins
+ */
+ out32 (IBM405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
+ out32 (IBM405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
+ out32 (IBM405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
+ */
+ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (uicer, 0x00000000); /* disable all ints */
+
+ mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
+ mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
+ mtdcr (uictr, 0x10000000); /* set int trigger levels */
+ mtdcr (uicvcr, 0x00000001); /* set vect base=0,
+ INT0 highest priority */
+
+ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
+
+#else /* Unknown */
# error "Unknown W7O board configuration"
#endif
- WATCHDOG_RESET(); /* Reset the watchdog */
- temp_uart_init(); /* init the uart for debug */
- WATCHDOG_RESET(); /* Reset the watchdog */
- test_led(); /* test the LEDs */
- test_sdram(get_dram_size()); /* test the dram */
- log_stat(ERR_POST1); /* log status,post1 complete */
- return 0;
+ WATCHDOG_RESET (); /* Reset the watchdog */
+ temp_uart_init (); /* init the uart for debug */
+ WATCHDOG_RESET (); /* Reset the watchdog */
+ test_led (); /* test the LEDs */
+ test_sdram (get_dram_size ()); /* test the dram */
+ log_stat (ERR_POST1); /* log status,post1 complete */
+ return 0;
}
*/
int checkboard (void)
{
- VPD vpd;
-
- puts ("Board: ");
-
- /* VPD data present in I2C EEPROM */
- if (vpd_get_data(CFG_DEF_EEPROM_ADDR, &vpd) == 0) {
- /*
- * Known board type.
- */
- if (vpd.productId[0] &&
- ((strncmp(vpd.productId, "GMM", 3) == 0) ||
- (strncmp(vpd.productId, "CMM", 3) == 0))) {
-
- /* Output board information on startup */
- printf("\"%s\", revision '%c', serial# %ld, manufacturer %u\n",
- vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
- return (0);
+ VPD vpd;
+
+ puts ("Board: ");
+
+ /* VPD data present in I2C EEPROM */
+ if (vpd_get_data (CFG_DEF_EEPROM_ADDR, &vpd) == 0) {
+ /*
+ * Known board type.
+ */
+ if (vpd.productId[0] &&
+ ((strncmp (vpd.productId, "GMM", 3) == 0) ||
+ (strncmp (vpd.productId, "CMM", 3) == 0))) {
+
+ /* Output board information on startup */
+ printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
+ return (0);
+ }
}
- }
- puts ("### Unknown HW ID - assuming NOTHING\n");
- return (0);
+ puts ("### Unknown HW ID - assuming NOTHING\n");
+ return (0);
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
- return get_dram_size();
+ return get_dram_size ();
}
unsigned long get_dram_size (void)
{
- int tmp, i, regs[4];
- int size = 0;
+ int tmp, i, regs[4];
+ int size = 0;
- /* Get bank Size registers */
- mtdcr(memcfga, mem_mb0cf); /* get bank 0 config reg */
- regs[0] = mfdcr(memcfgd);
+ /* Get bank Size registers */
+ mtdcr (memcfga, mem_mb0cf); /* get bank 0 config reg */
+ regs[0] = mfdcr (memcfgd);
- mtdcr(memcfga, mem_mb1cf); /* get bank 1 config reg */
- regs[1] = mfdcr(memcfgd);
+ mtdcr (memcfga, mem_mb1cf); /* get bank 1 config reg */
+ regs[1] = mfdcr (memcfgd);
- mtdcr(memcfga, mem_mb2cf); /* get bank 2 config reg */
- regs[2] = mfdcr(memcfgd);
+ mtdcr (memcfga, mem_mb2cf); /* get bank 2 config reg */
+ regs[2] = mfdcr (memcfgd);
- mtdcr(memcfga, mem_mb3cf); /* get bank 3 config reg */
- regs[3] = mfdcr(memcfgd);
+ mtdcr (memcfga, mem_mb3cf); /* get bank 3 config reg */
+ regs[3] = mfdcr (memcfgd);
- /* compute the size, add each bank if enabled */
- for(i = 0; i < 4; i++) {
- if (regs[i] & 0x0001) { /* if enabled, */
- tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */
- tmp = 0x400000 << tmp; /* Size bits X 4MB = size */
- size += tmp;
+ /* compute the size, add each bank if enabled */
+ for (i = 0; i < 4; i++) {
+ if (regs[i] & 0x0001) { /* if enabled, */
+ tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */
+ tmp = 0x400000 << tmp; /* Size bits X 4MB = size */
+ size += tmp;
+ }
}
- }
- return size;
+ return size;
}
int misc_init_f (void)
{
- return 0;
+ return 0;
}
-static void
-w7o_env_init(VPD *vpd)
+static void w7o_env_init (VPD * vpd)
{
- /*
- * Read VPD
- */
- if (vpd_get_data(CFG_DEF_EEPROM_ADDR, vpd) != 0)
- return;
-
- /*
- * Known board type.
- */
- if (vpd->productId[0] &&
- ((strncmp(vpd->productId, "GMM", 3) == 0) ||
- (strncmp(vpd->productId, "CMM", 3) == 0))) {
- char buf[30];
- char *eth;
- unsigned char *serial = getenv("serial#");
- unsigned char *ethaddr = getenv("ethaddr");
-
- /* Set 'serial#' envvar if serial# isn't set */
- if (!serial) {
- sprintf(buf, "%s-%ld", vpd->productId, vpd->serialNum);
- setenv("serial#", buf);
- }
+ /*
+ * Read VPD
+ */
+ if (vpd_get_data (CFG_DEF_EEPROM_ADDR, vpd) != 0)
+ return;
- /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
- eth = vpd->ethAddrs[0];
- if (ethaddr && (strcmp(ethaddr, MK_STR(CONFIG_ETHADDR)) == 0)) {
- /* Now setup ethaddr */
- sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
- eth[0], eth[1], eth[2], eth[3], eth[4], eth[5]);
- setenv("ethaddr", buf);
+ /*
+ * Known board type.
+ */
+ if (vpd->productId[0] &&
+ ((strncmp (vpd->productId, "GMM", 3) == 0) ||
+ (strncmp (vpd->productId, "CMM", 3) == 0))) {
+ char buf[30];
+ char *eth;
+ unsigned char *serial = getenv ("serial#");
+ unsigned char *ethaddr = getenv ("ethaddr");
+
+ /* Set 'serial#' envvar if serial# isn't set */
+ if (!serial) {
+ sprintf (buf, "%s-%ld", vpd->productId,
+ vpd->serialNum);
+ setenv ("serial#", buf);
+ }
+
+ /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
+ eth = vpd->ethAddrs[0];
+ if (ethaddr
+ && (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) {
+ /* Now setup ethaddr */
+ sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
+ eth[0], eth[1], eth[2], eth[3], eth[4],
+ eth[5]);
+ setenv ("ethaddr", buf);
+ }
}
- }
-} /* w7o_env_init() */
+} /* w7o_env_init() */
int misc_init_r (void)
{
- VPD vpd; /* VPD information */
+ VPD vpd; /* VPD information */
#if defined(CONFIG_W7OLMG)
- unsigned long greg; /* GPIO Register */
+ unsigned long greg; /* GPIO Register */
- greg = in32(IBM405GP_GPIO0_OR);
+ greg = in32 (IBM405GP_GPIO0_OR);
- /*
- * XXX - Unreset devices - this should be moved into VxWorks driver code
- */
- greg |= 0x41800000L; /* SAM, PHY, Galileo */
+ /*
+ * XXX - Unreset devices - this should be moved into VxWorks driver code
+ */
+ greg |= 0x41800000L; /* SAM, PHY, Galileo */
- out32(IBM405GP_GPIO0_OR, greg); /* set output pins to default */
+ out32 (IBM405GP_GPIO0_OR, greg); /* set output pins to default */
#endif /* CONFIG_W7OLMG */
- /*
- * Initialize W7O environment variables
- */
- w7o_env_init(&vpd);
+ /*
+ * Initialize W7O environment variables
+ */
+ w7o_env_init (&vpd);
- /*
- * Initialize the FPGA(s).
- */
- if (init_fpga() == 0)
- test_fpga((unsigned short *)CONFIG_FPGAS_BASE);
+ /*
+ * Initialize the FPGA(s).
+ */
+ if (init_fpga () == 0)
+ test_fpga ((unsigned short *) CONFIG_FPGAS_BASE);
- /* More POST testing. */
- post2();
+ /* More POST testing. */
+ post2 ();
- /* Done with hardware initialization and POST. */
- log_stat(ERR_POSTOK);
+ /* Done with hardware initialization and POST. */
+ log_stat (ERR_POSTOK);
- /* Call silly, fail safe boot init routine */
- init_fsboot();
+ /* Call silly, fail safe boot init routine */
+ init_fsboot ();
return (0);
}
hush.o kgdb.o lists.o lynxkdi.o miiphybb.o miiphyutil.o \
s_record.o soft_i2c.o soft_spi.o spartan2.o \
usb.o usb_kbd.o usb_storage.o \
- virtex2.o xilinx.o
+ virtex2.o xilinx.o memsize.o
OBJS = $(AOBJS) $(COBJS)
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'.
+ */
+long get_ram_size(volatile long *base, long maxsize)
+{
+ volatile long *addr;
+ long save[32];
+ long cnt;
+ long val;
+ long size;
+ int i = 0;
+
+ for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
+ addr = base + cnt; /* pointer arith! */
+ save[i++] = *addr;
+ *addr = ~cnt;
+ }
+
+ addr = base;
+ save[i] = *addr;
+ *addr = 0;
+
+ if ((val = *addr) != 0) {
+ /* Restore the original data before leaving the function.
+ */
+ *addr = save[i];
+ for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
+ addr = base + cnt;
+ *addr = save[--i];
+ }
+ return (0);
+ }
+
+ for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
+ addr = base + cnt; /* pointer arith! */
+ val = *addr;
+ *addr = save[--i];
+ if (val != ~cnt) {
+ size = cnt * sizeof (long);
+ /* Restore the original data before leaving the function.
+ */
+ for (cnt <<= 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
+ addr = base + cnt;
+ *addr = save[--i];
+ }
+ return (size);
+ }
+ }
+
+ return (maxsize);
+}
#define debugX(level,fmt,args...)
#endif /* DEBUG */
-typedef void (interrupt_handler_t)(void *);
+typedef void (interrupt_handler_t)(void *);
-#include <asm/u-boot.h> /* boot information for Linux kernel */
+#include <asm/u-boot.h> /* boot information for Linux kernel */
#include <asm/global_data.h> /* global data used for startup functions */
/*
int serial_buffered_tstc (void);
#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
-void hang (void) __attribute__ ((noreturn));
+void hang (void) __attribute__ ((noreturn));
/* */
long int initdram (int);
-int display_options (void);
+int display_options (void);
void print_size (ulong, const char *);
/* common/main.c */
/* common/cmd_bootm.c */
void print_image_hdr (image_header_t *hdr);
-extern ulong load_addr; /* Default Load Address */
+extern ulong load_addr; /* Default Load Address */
/* common/cmd_nvedit.c */
int env_init (void);
void env_relocate (void);
-char *getenv (uchar *);
+char *getenv (uchar *);
int getenv_r (uchar *name, uchar *buf, unsigned len);
-int saveenv (void);
+int saveenv (void);
#ifdef CONFIG_PPC /* ARM version to be fixed! */
void inline setenv (char *, char *);
#else
-void setenv (char *, char *);
+void setenv (char *, char *);
#endif /* CONFIG_PPC */
#ifdef CONFIG_ARM
# include <asm/setup.h>
# include <asm/u-boot-i386.h>
#endif /* CONFIG_I386 */
-void pci_init (void);
-void pci_init_board(void);
-void pciinfo (int, int);
+void pci_init (void);
+void pci_init_board(void);
+void pciinfo (int, int);
#if defined(CONFIG_PCI) && defined(CONFIG_440)
# if defined(CFG_PCI_PRE_INIT)
- int pci_pre_init (struct pci_controller * );
+ int pci_pre_init (struct pci_controller * );
# endif
# if defined(CFG_PCI_TARGET_INIT)
- void pci_target_init (struct pci_controller *);
+ void pci_target_init (struct pci_controller *);
# endif
# if defined(CFG_PCI_MASTER_INIT)
- void pci_master_init (struct pci_controller *);
+ void pci_master_init (struct pci_controller *);
# endif
- int is_pci_host (struct pci_controller *);
+ int is_pci_host (struct pci_controller *);
#endif
int misc_init_f (void);
/* common/exports.c */
void jumptable_init(void);
+/* common/memsize.c */
+int get_ram_size (volatile long *, long);
+
/* $(BOARD)/$(BOARD).c */
void reset_phy (void);
-void fdc_hw_init (void);
+void fdc_hw_init (void);
/* $(BOARD)/eeprom.c */
void eeprom_init (void);
#if defined(CONFIG_SPI)
extern void spi_init_f (void);
extern void spi_init_r (void);
-extern ssize_t spi_read (uchar *, int, uchar *, int);
+extern ssize_t spi_read (uchar *, int, uchar *, int);
extern ssize_t spi_write (uchar *, int, uchar *, int);
#endif
#endif /* CFG_DRAM_TEST */
/* $(CPU)/start.S */
-#if defined(CONFIG_5xx) || \
+#if defined(CONFIG_5xx) || \
defined(CONFIG_8xx)
uint get_immr (uint);
#endif
-uint get_pir (void);
+uint get_pir (void);
uint get_pvr (void);
uint rd_ic_cst (void);
void wr_ic_cst (uint);
defined (CONFIG_74x) || \
defined (CONFIG_75x) || \
defined (CONFIG_74xx)
-unsigned char in8(unsigned int);
-void out8(unsigned int, unsigned char);
-unsigned short in16(unsigned int);
-unsigned short in16r(unsigned int);
-void out16(unsigned int, unsigned short value);
-void out16r(unsigned int, unsigned short value);
-unsigned long in32(unsigned int);
-unsigned long in32r(unsigned int);
-void out32(unsigned int, unsigned long value);
-void out32r(unsigned int, unsigned long value);
-void ppcDcbf(unsigned long value);
-void ppcDcbi(unsigned long value);
-void ppcSync(void);
+unsigned char in8(unsigned int);
+void out8(unsigned int, unsigned char);
+unsigned short in16(unsigned int);
+unsigned short in16r(unsigned int);
+void out16(unsigned int, unsigned short value);
+void out16r(unsigned int, unsigned short value);
+unsigned long in32(unsigned int);
+unsigned long in32r(unsigned int);
+void out32(unsigned int, unsigned long value);
+void out32r(unsigned int, unsigned long value);
+void ppcDcbf(unsigned long value);
+void ppcDcbi(unsigned long value);
+void ppcSync(void);
#endif
/* $(CPU)/cpu.c */
ulong get_UCLK (void);
#endif
#if defined CONFIG_INCA_IP
-uint incaip_get_cpuclk (void);
+uint incaip_get_cpuclk (void);
#endif
ulong get_bus_freq (ulong);
#if defined(CONFIG_MPC85xx)
typedef MPC85xx_SYS_INFO sys_info_t;
-void get_sys_info ( sys_info_t * );
+void get_sys_info ( sys_info_t * );
#endif
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
# else
typedef PPC405_SYS_INFO sys_info_t;
# endif
-void get_sys_info ( sys_info_t * );
+void get_sys_info ( sys_info_t * );
#endif
/* $(CPU)/cpu_init.c */
#endif
/* $(CPU)/interrupts.c */
-int interrupt_init (void);
-void timer_interrupt (struct pt_regs *);
+int interrupt_init (void);
+void timer_interrupt (struct pt_regs *);
void external_interrupt (struct pt_regs *);
void irq_install_handler(int, interrupt_handler_t *, void *);
void irq_free_handler (int);
long simple_strtol(const char *cp,char **endp,unsigned int base);
void panic(const char *fmt, ...);
int sprintf(char * buf, const char *fmt, ...);
-int vsprintf(char *buf, const char *fmt, va_list args);
+int vsprintf(char *buf, const char *fmt, va_list args);
/* lib_generic/crc32.c */
ulong crc32 (ulong, const unsigned char *, uint);
-#ifndef __MON_SYS_CALL_H__
-#define __MON_SYS_CALL_H__
+#ifndef __EXPORTS_H__
+#define __EXPORTS_H__
#ifndef __ASSEMBLY__
extern gd_t *global_data;
#endif
-#endif
+#endif /* __EXPORTS_H__ */
#ifndef __VERSION_H__
#define __VERSION_H__
-#define U_BOOT_VERSION "U-Boot 1.0.1"
+#define U_BOOT_VERSION "U-Boot 1.0.2"
#endif /* __VERSION_H__ */
projects / karo-tx-uboot.git / commitdiff