endif
export obj src
-TIMESTAMP_FILE = $(obj)include/timestamp_autogenerated.h
-VERSION_FILE = $(obj)include/version_autogenerated.h
+TIMESTAMP_FILE = $(obj)include/generated/timestamp_autogenerated.h
+VERSION_FILE = $(obj)include/generated/version_autogenerated.h
# Make sure CDPATH settings don't interfere
unexport CDPATH
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := mx23_evk.o
-SOBJS := lowlevel_init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
-
+++ /dev/null
-#
-# image should be loaded at 0x41008000
-#
-LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
-
-TEXT_BASE = 0x41008000
+++ /dev/null
-/*
- * Board specific setup info
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2003, ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-/* Set up the platform, once the cpu has been initialized */
-.globl lowlevel_init
-lowlevel_init:
-
- /* All SDRAM settings are done by sdram_prep */
- mov pc, lr
+++ /dev/null
-/*
- *
- * (c) 2008 Embedded Alley Solutions, Inc.
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <asm/arch/mx23.h>
-#include <asm/arch/clkctrl.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/spi.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define KHz 1000
-#define MHz (1000 * KHz)
-
-static void set_pinmux(void)
-{
-
-#if defined(CONFIG_SPI_SSP1)
-
- /* Configure SSP1 pins for ENC28j60: 8maA */
- REG_CLR(PINCTRL_BASE + PINCTRL_MUXSEL(4), 0x00003fff);
-
- REG_CLR(PINCTRL_BASE + PINCTRL_DRIVE(8), 0X03333333);
- REG_SET(PINCTRL_BASE + PINCTRL_DRIVE(8), 0x01111111);
-
- REG_CLR(PINCTRL_BASE + PINCTRL_PULL(2), 0x0000003f);
-#endif
-
-#if defined(CONFIG_SPI_SSP2)
-
- /* Configure SSP2 pins for ENC28j60: 8maA */
- REG_CLR(PINCTRL_BASE + PINCTRL_MUXSEL(0), 0x00000fc3);
- REG_SET(PINCTRL_BASE + PINCTRL_MUXSEL(0), 0x00000a82);
-
- REG_CLR(PINCTRL_BASE + PINCTRL_MUXSEL(1), 0x00030300);
- REG_SET(PINCTRL_BASE + PINCTRL_MUXSEL(1), 0x00020200);
-
- REG_CLR(PINCTRL_BASE + PINCTRL_DRIVE(0), 0X00333003);
- REG_SET(PINCTRL_BASE + PINCTRL_DRIVE(0), 0x00111001);
-
- REG_CLR(PINCTRL_BASE + PINCTRL_DRIVE(2), 0x00030000);
- REG_SET(PINCTRL_BASE + PINCTRL_DRIVE(2), 0x00010000);
-
- REG_CLR(PINCTRL_BASE + PINCTRL_DRIVE(3), 0x00000003);
- REG_SET(PINCTRL_BASE + PINCTRL_DRIVE(3), 0x00000001);
-
- REG_CLR(PINCTRL_BASE + PINCTRL_PULL(0), 0x00100039);
-#endif
-
-}
-
-#define IO_DIVIDER 18
-static void set_clocks(void)
-{
- u32 ssp_source_clk, ssp_clk;
- u32 ssp_div = 1;
- u32 val = 0;
-
- /*
- * Configure 480Mhz IO clock
- */
-
- /* Ungate IO_CLK and set divider */
- REG_CLR(CLKCTRL_BASE + CLKCTRL_FRAC, FRAC_CLKGATEIO);
- REG_CLR(CLKCTRL_BASE + CLKCTRL_FRAC, 0x3f << FRAC_IOFRAC);
- REG_SET(CLKCTRL_BASE + CLKCTRL_FRAC, IO_DIVIDER << FRAC_IOFRAC);
-
- /*
- * Set SSP CLK to desired value
- */
-
- /* Calculate SSP_CLK divider relatively to 480Mhz IO_CLK*/
- ssp_source_clk = 480 * MHz;
- ssp_clk = CONFIG_SSP_CLK;
- ssp_div = (ssp_source_clk + ssp_clk - 1) / ssp_clk;
-
- /* Enable SSP clock */
- val = REG_RD(CLKCTRL_BASE + CLKCTRL_SSP);
- val &= ~SSP_CLKGATE;
- REG_WR(CLKCTRL_BASE + CLKCTRL_SSP, val);
-
- /* Wait while clock is gated */
- while (REG_RD(CLKCTRL_BASE + CLKCTRL_SSP) & SSP_CLKGATE)
- ;
-
- /* Set SSP clock divider */
- val &= ~(0x1ff << SSP_DIV);
- val |= ssp_div << SSP_DIV;
- REG_WR(CLKCTRL_BASE + CLKCTRL_SSP, val);
-
- /* Wait until new divider value is set */
- while (REG_RD(CLKCTRL_BASE + CLKCTRL_SSP) & SSP_BUSY)
- ;
-
- /* Set SSP clock source to IO_CLK */
- REG_SET(CLKCTRL_BASE + CLKCTRL_CLKSEQ, CLKSEQ_BYPASS_SSP);
- REG_CLR(CLKCTRL_BASE + CLKCTRL_CLKSEQ, CLKSEQ_BYPASS_SSP);
-}
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-int board_init(void)
-{
- /* arch number of Freescale STMP 378x development board */
- gd->bd->bi_arch_number = MACH_TYPE_MX23EVK;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- set_clocks();
-
- set_pinmux();
-
- /* Configure SPI on SSP1 or SSP2 */
- spi_init();
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- return 0;
-}
-
-int checkboard(void)
-{
- printf("Board: MX23 EVK. \n");
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
- . = ALIGN(4);
- .text :
- {
- cpu/arm926ejs/start.o (.text)
- *(.text)
- }
- .rodata : { *(.rodata) }
- . = ALIGN(4);
- .data : { *(.data) }
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) }
- _end = .;
-}
+++ /dev/null
-#
-# (c) Copyright 2009 Freescale Semiconductor
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := mx25_3stack.o
-SOBJS := lowlevel_init.o dcdheader.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
-
-TEXT_BASE = 0x83F00000
+++ /dev/null
-/*
- * Copyright (c) 2009 Freescale Semiconductor
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-
-.extern reset
-
-#define DCDGEN(i,type, addr, data) \
-dcd_##i: ;\
- .long type ;\
- .long addr ;\
- .long data
-
-.globl _initheader
-_initheader:
- b reset
- .org 0x400
-app_code_jump_v: .long reset
-app_code_barker: .long 0xB1
-app_code_csf: .long 0
-hwcfg_ptr_ptr: .long hwcfg_ptr
-super_root_key: .long 0
-hwcfg_ptr: .long dcd_data
-app_dest_ptr: .long TEXT_BASE
-dcd_data: .long 0xB17219E9
-
-#ifdef MXC_MEMORY_MDDR
-dcd_len: .long 12*15
-#else
-dcd_len: .long 12*24
-#endif
-
-/* WEIM config-CS5 init -- CPLD */
-DCDGEN( 1, 4, 0xB8002050, 0x0000D843) /* CS5_CSCRU */
-DCDGEN( 2, 4, 0xB8002054, 0x22252521) /* CS5_CSCRL */
-DCDGEN( 3, 4, 0xB8002058, 0x22220A00) /* CS5_CSCRA */
-#ifdef MXC_MEMORY_MDDR
-/* MDDR init */
-DCDGEN( 4, 4, 0xB8001010, 0x00000004) /* enable mDDR */
-DCDGEN( 5, 4, 0xB8001000, 0x92100000) /* precharge command */
-DCDGEN( 6, 1, 0x80000400, 0x12344321) /* precharge all dummy write */
-DCDGEN( 7, 4, 0xB8001000, 0xA2100000) /* auto-refresh command */
-DCDGEN( 8, 4, 0x80000000, 0x12344321) /* dummy write for refresh */
-DCDGEN( 9, 4, 0x80000000, 0x12344321) /* dummy write for refresh */
-DCDGEN(10, 4, 0xB8001000, 0xB2100000) /* Load Mode Reg command - cas=3 bl=8 */
-DCDGEN(11, 1, 0x80000033, 0xda) /* dummy write -- address has the mode bits */
-DCDGEN(12, 1, 0x81000000, 0xff) /* dummy write -- address has the mode bits */
-DCDGEN(13, 4, 0xB8001000, 0x82216880)
-DCDGEN(14, 4, 0xB8001004, 0x00295729)
-#else
-/* DDR2 init */
-DCDGEN( 4, 4, 0xB8001004, 0x0076E83A) /* initial value for ESDCFG0 */
-DCDGEN( 5, 4, 0xB8001010, 0x00000204) /* ESD_MISC */
-DCDGEN( 6, 4, 0xB8001000, 0x92210000) /* CS0 precharge command */
-DCDGEN( 7, 4, 0x80000f00, 0x12344321) /* precharge all dummy write */
-DCDGEN( 8, 4, 0xB8001000, 0xB2210000) /* Load Mode Register command */
-DCDGEN( 9, 1, 0x82000000, 0xda) /* dummy write Load EMR2 */
-DCDGEN(10, 1, 0x83000000, 0xda) /* dummy write Load EMR3 */
-DCDGEN(11, 1, 0x81000400, 0xda) /* dummy write Load EMR1; enable DLL */
-DCDGEN(12, 1, 0x80000333, 0xda) /* dummy write Load MR; reset DLL */
-
-DCDGEN(13, 4, 0xB8001000, 0x92210000) /* CS0 precharge command */
-DCDGEN(14, 1, 0x80000400, 0x12345678) /* precharge all dummy write */
-
-DCDGEN(15, 4, 0xB8001000, 0xA2210000) /* select manual refresh mode */
-DCDGEN(16, 4, 0x80000000, 0x87654321) /* manual refresh */
-DCDGEN(17, 4, 0x80000000, 0x87654321) /* manual refresh twice */
-
-DCDGEN(18, 4, 0xB8001000, 0xB2210000) /* Load Mode Register command */
-DCDGEN(19, 1, 0x80000233, 0xda) /* Load MR; CL=3, BL=8, end DLL reset */
-DCDGEN(20, 1, 0x81000780, 0xda) /* Load EMR1; OCD default */
-DCDGEN(21, 1, 0x81000400, 0xda) /* Load EMR1; OCD exit */
-DCDGEN(22, 4, 0xB8001000, 0x82216080) /* normal mode */
-DCDGEN(23, 4, 0x43FAC454, 0x00001000) /* IOMUXC_SW_PAD_CTL_GRP_DDRTYPE(1-5) */
-#endif
-
-DCDGEN(99, 4, 0x53F80008, 0x20034000) /* CLKCTL ARM=400 AHB=133 */
-card_cfg: .long UBOOT_IMAGE_SIZE
+++ /dev/null
-/*
- * Copyright (c) 2009 Freescale Semiconductor
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/mx25-regs.h>
-
-.macro REG reg, val
- ldr r2, =\reg
- ldr r3, =\val
- str r3, [r2]
-.endm
-
-.macro REG8 reg, val
- ldr r2, =\reg
- ldr r3, =\val
- strb r3, [r2]
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
-
- REG 0x53F80008, 0x20034000 // ARM clk = 399, AHB clk = 133
-
- /* Init Debug Board CS5 */
- REG 0xB8002050, 0x0000D843
- REG 0xB8002054, 0x22252521
- REG 0xB8002058, 0x22220A00
-
- /* MAX (Multi-Layer AHB Crossbar Switch) setup */
- /* MAX - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB */
- ldr r0, =MAX_BASE
- ldr r1, =0x00002143
- str r1, [r0, #0x000] /* for S0 */
- str r1, [r0, #0x100] /* for S1 */
- str r1, [r0, #0x200] /* for S2 */
- str r1, [r0, #0x300] /* for S3 */
- str r1, [r0, #0x400] /* for S4 */
- /* SGPCR - always park on last master */
- ldr r1, =0x10
- str r1, [r0, #0x010] /* for S0 */
- str r1, [r0, #0x110] /* for S1 */
- str r1, [r0, #0x210] /* for S2 */
- str r1, [r0, #0x310] /* for S3 */
- str r1, [r0, #0x410] /* for S4 */
- /* MGPCR - restore default values */
- ldr r1, =0x0
- str r1, [r0, #0x800] /* for M0 */
- str r1, [r0, #0x900] /* for M1 */
- str r1, [r0, #0xA00] /* for M2 */
- str r1, [r0, #0xB00] /* for M3 */
- str r1, [r0, #0xC00] /* for M4 */
-
- /* M3IF setup */
- ldr r1, =M3IF_BASE
- ldr r0, =0x00000001
- str r0, [r1] /* M3IF control reg */
-
- /* default CLKO to 1/32 of the ARM core */
- ldr r0, =CCM_MCR
- ldr r1, =CCM_MCR
- bic r1, r1, #0x00F00000
- bic r1, r1, #0x7F000000
- mov r2, #0x5F000000
- add r2, r2, #0x00200000
- orr r1, r1, r2
- str r1, [r0]
-
- /* enable all the clocks */
- ldr r2, =0x1FFFFFFF
- ldr r0, =CCM_CGR0
- str r2, [r0]
- ldr r2, =0xFFFFFFFF
- ldr r0, =CCM_CGR1
- str r2, [r0]
- ldr r2, =0x000FDFFF
- ldr r0, =CCM_CGR2
- str r2, [r0]
- mov pc, lr
-
+++ /dev/null
-/*
- * (c) Copyright 2009-2010 Freescale Semiconductor
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/mx25.h>
-#include <asm/arch/mx25-regs.h>
-#include <asm/arch/mx25_pins.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/gpio.h>
-#include <imx_spi.h>
-
-#ifdef CONFIG_LCD
-#include <mx2fb.h>
-#include <lcd.h>
-#endif
-
-#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-#include <asm/imx_iim.h>
-#endif
-
-#ifdef CONFIG_CMD_MMC
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static u32 system_rev;
-#ifdef CONFIG_LCD
-char lcd_cmap[256];
-#endif
-
-u32 get_board_rev(void)
-{
- return system_rev;
-}
-
-static inline void setup_soc_rev(void)
-{
- int reg;
- reg = __REG(IIM_BASE + IIM_SREV);
- if (!reg) {
- reg = __REG(ROMPATCH_REV);
- reg <<= 4;
- } else
- reg += CHIP_REV_1_0;
- system_rev = 0x25000 + (reg & 0xFF);
-}
-
-inline int is_soc_rev(int rev)
-{
- return (system_rev & 0xFF) - rev;
-}
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_MMC
-
-struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE, 1, 1},
- {MMC_SDHC2_BASE, 1, 1},
-};
-
-int esdhc_gpio_init(bd_t *bis)
-{
- s32 status = 0;
- u32 index = 0;
- u32 val = 0;
-
- for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
- ++index) {
- switch (index) {
- case 0:
- /* Pins */
- writel(0x10, IOMUXC_BASE + 0x190); /* SD1_CMD */
- writel(0x10, IOMUXC_BASE + 0x194); /* SD1_CLK */
- writel(0x00, IOMUXC_BASE + 0x198); /* SD1_DATA0 */
- writel(0x00, IOMUXC_BASE + 0x19c); /* SD1_DATA1 */
- writel(0x00, IOMUXC_BASE + 0x1a0); /* SD1_DATA2 */
- writel(0x00, IOMUXC_BASE + 0x1a4); /* SD1_DATA3 */
- writel(0x06, IOMUXC_BASE + 0x094); /* D12 (SD1_DATA4) */
- writel(0x06, IOMUXC_BASE + 0x090); /* D13 (SD1_DATA5) */
- writel(0x06, IOMUXC_BASE + 0x08c); /* D14 (SD1_DATA6) */
- writel(0x06, IOMUXC_BASE + 0x088); /* D15 (SD1_DATA7) */
- writel(0x05, IOMUXC_BASE + 0x010); /* A14 (SD1_WP) */
- writel(0x05, IOMUXC_BASE + 0x014); /* A15 (SD1_DET) */
-
- /* Pads */
- writel(0xD1, IOMUXC_BASE + 0x388); /* SD1_CMD */
- writel(0xD1, IOMUXC_BASE + 0x38c); /* SD1_CLK */
- writel(0xD1, IOMUXC_BASE + 0x390); /* SD1_DATA0 */
- writel(0xD1, IOMUXC_BASE + 0x394); /* SD1_DATA1 */
- writel(0xD1, IOMUXC_BASE + 0x398); /* SD1_DATA2 */
- writel(0xD1, IOMUXC_BASE + 0x39c); /* SD1_DATA3 */
- writel(0xD1, IOMUXC_BASE + 0x28c); /* D12 (SD1_DATA4) */
- writel(0xD1, IOMUXC_BASE + 0x288); /* D13 (SD1_DATA5) */
- writel(0xD1, IOMUXC_BASE + 0x284); /* D14 (SD1_DATA6) */
- writel(0xD1, IOMUXC_BASE + 0x280); /* D15 (SD1_DATA7) */
- writel(0xD1, IOMUXC_BASE + 0x230); /* A14 (SD1_WP) */
- writel(0xD1, IOMUXC_BASE + 0x234); /* A15 (SD1_DET) */
-
- /*
- * Set write protect and card detect gpio as inputs
- * A14 (SD1_WP) and A15 (SD1_DET)
- */
- val = ~(3 << 0) & readl(GPIO1_BASE + GPIO_GDIR);
- writel(val, GPIO1_BASE + GPIO_GDIR);
- break;
- case 1:
- /* Pins */
- writel(0x16, IOMUXC_BASE + 0x0e8); /* LD8 (SD1_CMD) */
- writel(0x16, IOMUXC_BASE + 0x0ec); /* LD9 (SD1_CLK) */
- writel(0x06, IOMUXC_BASE + 0x0f0); /* LD10 (SD1_DATA0)*/
- writel(0x06, IOMUXC_BASE + 0x0f4); /* LD11 (SD1_DATA1)*/
- writel(0x06, IOMUXC_BASE + 0x0f8); /* LD12 (SD1_DATA2)*/
- writel(0x06, IOMUXC_BASE + 0x0fc); /* LD13 (SD1_DATA3)*/
- /* CSI_D2 (SD1_DATA4) */
- writel(0x02, IOMUXC_BASE + 0x120);
- /* CSI_D3 (SD1_DATA5) */
- writel(0x02, IOMUXC_BASE + 0x124);
- /* CSI_D4 (SD1_DATA6) */
- writel(0x02, IOMUXC_BASE + 0x128);
- /* CSI_D5 (SD1_DATA7) */
- writel(0x02, IOMUXC_BASE + 0x12c);
-
- /* Pads */
- writel(0xD1, IOMUXC_BASE + 0x2e0); /* LD8 (SD1_CMD) */
- writel(0xD1, IOMUXC_BASE + 0x2e4); /* LD9 (SD1_CLK) */
- writel(0xD1, IOMUXC_BASE + 0x2e8); /* LD10 (SD1_DATA0)*/
- writel(0xD1, IOMUXC_BASE + 0x2ec); /* LD11 (SD1_DATA1)*/
- writel(0xD1, IOMUXC_BASE + 0x2f0); /* LD12 (SD1_DATA2)*/
- writel(0xD1, IOMUXC_BASE + 0x2f4); /* LD13 (SD1_DATA3)*/
- /* CSI_D2 (SD1_DATA4) */
- writel(0xD1, IOMUXC_BASE + 0x318);
- /* CSI_D3 (SD1_DATA5) */
- writel(0xD1, IOMUXC_BASE + 0x31c);
- /* CSI_D4 (SD1_DATA6) */
- writel(0xD1, IOMUXC_BASE + 0x320);
- /* CSI_D5 (SD1_DATA7) */
- writel(0xD1, IOMUXC_BASE + 0x324);
- break;
- default:
- printf("Warning: you configured more ESDHC controller"
- "(%d) as supported by the board(2)\n",
- CONFIG_SYS_FSL_ESDHC_NUM);
- return status;
- break;
- }
- status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
- }
- return 0;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- if (!esdhc_gpio_init(bis))
- return 0;
- else
- return -1;
-}
-#endif
-
-s32 spi_get_cfg(struct imx_spi_dev_t *dev)
-{
- switch (dev->slave.cs) {
- case 0:
- /* cpld */
- dev->base = CSPI1_BASE;
- dev->freq = 25000000;
- dev->ss_pol = IMX_SPI_ACTIVE_LOW;
- dev->ss = 0;
- dev->fifo_sz = 32;
- dev->us_delay = 0;
- break;
- default:
- printf("Invalid Bus ID! \n");
- break;
- }
-
- return 0;
-}
-
-void spi_io_init(struct imx_spi_dev_t *dev)
-{
- switch (dev->base) {
- case CSPI1_BASE:
- writel(0, IOMUXC_BASE + 0x180); /* CSPI1 SCLK */
- writel(0x1C0, IOMUXC_BASE + 0x5c4);
- writel(0, IOMUXC_BASE + 0x184); /* SPI_RDY */
- writel(0x1E0, IOMUXC_BASE + 0x5c8);
- writel(0, IOMUXC_BASE + 0x170); /* MOSI */
- writel(0x1C0, IOMUXC_BASE + 0x5b4);
- writel(0, IOMUXC_BASE + 0x174); /* MISO */
- writel(0x1C0, IOMUXC_BASE + 0x5b8);
- writel(0, IOMUXC_BASE + 0x17C); /* SS1 */
- writel(0x1E0, IOMUXC_BASE + 0x5C0);
- break;
- default:
- break;
- }
-}
-
-#ifdef CONFIG_LCD
-
-vidinfo_t panel_info = {
- vl_refresh:60,
- vl_col:640,
- vl_row:480,
- vl_pixclock:39683,
- vl_left_margin:45,
- vl_right_margin:114,
- vl_upper_margin:33,
- vl_lower_margin:11,
- vl_hsync:1,
- vl_vsync:1,
- vl_sync : FB_SYNC_CLK_LAT_FALL,
- vl_mode:0,
- vl_flag:0,
- vl_bpix:4,
- cmap : (void *)lcd_cmap,
-};
-
-void lcdc_hw_init(void)
-{
- /* Set VSTBY_REQ as GPIO3[17] on ALT5 */
- mxc_request_iomux(MX25_PIN_VSTBY_REQ, MUX_CONFIG_ALT5);
-
- /* Set GPIO3[17] as output */
- writel(0x20000, GPIO3_BASE + 0x04);
-
- /* Set GPIOE as LCDC_LD[16] on ALT2 */
- mxc_request_iomux(MX25_PIN_GPIO_E, MUX_CONFIG_ALT2);
-
- /* Set GPIOF as LCDC_LD[17] on ALT2 */
- mxc_request_iomux(MX25_PIN_GPIO_F, MUX_CONFIG_ALT2);
-
- /* Enable pull up on LCDC_LD[16] */
- mxc_iomux_set_pad(MX25_PIN_GPIO_E,
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU);
-
- /* Enable pull up on LCDC_LD[17] */
- mxc_iomux_set_pad(MX25_PIN_GPIO_F,
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU);
-
- /* Enable Pull/Keeper for pad LSCKL */
- mxc_iomux_set_pad(MX25_PIN_LSCLK,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD |
- PAD_CTL_100K_PU | PAD_CTL_SRE_FAST);
-
- gd->fb_base = CONFIG_FB_BASE;
-}
-
-#ifdef CONFIG_SPLASH_SCREEN
-int setup_splash_img()
-{
-#ifdef CONFIG_SPLASH_IS_IN_MMC
- int mmc_dev = CONFIG_SPLASH_IMG_MMC_DEV;
- ulong offset = CONFIG_SPLASH_IMG_OFFSET;
- ulong size = CONFIG_SPLASH_IMG_SIZE;
- ulong addr = 0;
- char *s = NULL;
- struct mmc *mmc = find_mmc_device(mmc_dev);
- uint blk_start, blk_cnt, n;
-
- s = getenv("splashimage");
-
- if (NULL == s) {
- puts("env splashimage not found!\n");
- return -1;
- }
- addr = simple_strtoul(s, NULL, 16);
-
- if (!mmc) {
- printf("MMC Device %d not found\n",
- mmc_dev);
- return -1;
- }
-
- if (mmc_init(mmc)) {
- puts("MMC init failed\n");
- return -1;
- }
-
- blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
- blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
- n = mmc->block_dev.block_read(mmc_dev, blk_start,
- blk_cnt, (u_char *)addr);
- flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
-
- return (n == blk_cnt) ? 0 : -1;
-#endif
-}
-#endif
-#endif
-
-#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-
-int fec_get_mac_addr(unsigned char *mac)
-{
- u32 *iim0_mac_base =
- (u32 *)(IIM_BASE + IIM_BANK_AREA_0_OFFSET +
- CONFIG_IIM_MAC_ADDR_OFFSET);
- int i;
-
- for (i = 0; i < 6; ++i, ++iim0_mac_base)
- mac[i] = readl(iim0_mac_base);
-
- return 0;
-}
-#endif
-
-int board_init(void)
-{
-
-#ifdef CONFIG_MFG
- /* MFG firmware need reset usb to avoid host crash firstly */
-#define USBCMD 0x140
- int val = readl(USB_BASE + USBCMD);
- val &= ~0x1; /*RS bit*/
- writel(val, USB_BASE + USBCMD);
-#endif
-
- setup_soc_rev();
-
- /* setup pins for UART1 */
- /* UART 1 IOMUX Configs */
- mxc_request_iomux(MX25_PIN_UART1_RXD, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX25_PIN_UART1_TXD, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX25_PIN_UART1_RTS, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX25_PIN_UART1_CTS, MUX_CONFIG_FUNC);
- mxc_iomux_set_pad(MX25_PIN_UART1_RXD,
- PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
- PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX25_PIN_UART1_TXD,
- PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX25_PIN_UART1_RTS,
- PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
- PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX25_PIN_UART1_CTS,
- PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
-
- /* setup pins for FEC */
- mxc_request_iomux(MX25_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX25_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX25_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX25_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX25_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX25_PIN_FEC_MDC, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX25_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX25_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX25_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX25_PIN_POWER_FAIL, MUX_CONFIG_FUNC); /* PHY INT */
-
-#define FEC_PAD_CTL1 (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PUE_PUD | \
- PAD_CTL_PKE_ENABLE)
-#define FEC_PAD_CTL2 (PAD_CTL_PUE_PUD)
-
- mxc_iomux_set_pad(MX25_PIN_FEC_TX_CLK, FEC_PAD_CTL1);
- mxc_iomux_set_pad(MX25_PIN_FEC_RX_DV, FEC_PAD_CTL1);
- mxc_iomux_set_pad(MX25_PIN_FEC_RDATA0, FEC_PAD_CTL1);
- mxc_iomux_set_pad(MX25_PIN_FEC_TDATA0, FEC_PAD_CTL2);
- mxc_iomux_set_pad(MX25_PIN_FEC_TX_EN, FEC_PAD_CTL2);
- mxc_iomux_set_pad(MX25_PIN_FEC_MDC, FEC_PAD_CTL2);
- mxc_iomux_set_pad(MX25_PIN_FEC_MDIO, FEC_PAD_CTL1 | PAD_CTL_22K_PU);
- mxc_iomux_set_pad(MX25_PIN_FEC_RDATA1, FEC_PAD_CTL1);
- mxc_iomux_set_pad(MX25_PIN_FEC_TDATA1, FEC_PAD_CTL2);
- mxc_iomux_set_pad(MX25_PIN_POWER_FAIL, FEC_PAD_CTL1);
-
- /*
- * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
- * Assert FEC_RESET_B, then power up the PHY by asserting
- * FEC_ENABLE, at the same time lifting FEC_RESET_B.
- *
- * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin D12
- * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin A17
- */
- mxc_request_iomux(MX25_PIN_A17, MUX_CONFIG_ALT5); /* FEC_EN */
- mxc_request_iomux(MX25_PIN_D12, MUX_CONFIG_ALT5); /* FEC_RESET_B */
-
- mxc_iomux_set_pad(MX25_PIN_A17, PAD_CTL_ODE_OpenDrain);
- mxc_iomux_set_pad(MX25_PIN_D12, 0);
-
- mxc_set_gpio_direction(MX25_PIN_A17, 0); /* FEC_EN */
- mxc_set_gpio_direction(MX25_PIN_D12, 0); /* FEC_RESET_B */
-
- /* drop PHY power */
- mxc_set_gpio_dataout(MX25_PIN_A17, 0); /* FEC_EN */
-
- /* assert reset */
- mxc_set_gpio_dataout(MX25_PIN_D12, 0); /* FEC_RESET_B */
- udelay(2); /* spec says 1us min */
-
- /* turn on PHY power and lift reset */
- mxc_set_gpio_dataout(MX25_PIN_A17, 1); /* FEC_EN */
- mxc_set_gpio_dataout(MX25_PIN_D12, 1); /* FEC_RESET_B */
-
-#define I2C_PAD_CTL (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | \
- PAD_CTL_PUE_PUD | PAD_CTL_100K_PU | PAD_CTL_ODE_OpenDrain)
-
- mxc_request_iomux(MX25_PIN_I2C1_CLK, MUX_CONFIG_SION);
- mxc_request_iomux(MX25_PIN_I2C1_DAT, MUX_CONFIG_SION);
- mxc_iomux_set_pad(MX25_PIN_I2C1_CLK, 0x1E8);
- mxc_iomux_set_pad(MX25_PIN_I2C1_DAT, 0x1E8);
-
-#ifdef CONFIG_LCD
- lcdc_hw_init();
-#endif
-
- gd->bd->bi_arch_number = MACH_TYPE_MX25_3DS; /* board id for linux */
- gd->bd->bi_boot_params = 0x80000100; /* address of boot parameters */
-
- return 0;
-
-#undef FEC_PAD_CTL1
-#undef FEC_PAD_CTL2
-#undef I2C_PAD_CTL
-}
-
-#ifdef BOARD_LATE_INIT
-int board_late_init(void)
-{
- u8 reg[4];
-
- /* Turn PMIC On*/
- reg[0] = 0x09;
- i2c_write(0x54, 0x02, 1, reg, 1);
-
-#ifdef CONFIG_IMX_SPI_CPLD
- mxc_cpld_spi_init();
-#endif
-
-#ifdef CONFIG_SPLASH_SCREEN
- if (!setup_splash_img())
- printf("Read splash screen failed!\n");
-#endif
-
- return 0;
-}
-#endif
-
-
-int checkboard(void)
-{
- printf("Board: i.MX25 MAX PDK (3DS)\n");
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = -ENODEV;
-#if defined(CONFIG_SMC911X)
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
-
- cpu_eth_init(bis);
-
- return rc;
-}
-
+++ /dev/null
-/*
- * (c) Copyright 2009 Freescale Semiconductor
- *
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- board/freescale/mx25_3stack/dcdheader.o (.text)
- cpu/arm926ejs/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := mx28_evk.o
-SOBJS := lowlevel_init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
-
+++ /dev/null
-#
-# image should be loaded at 0x41008000
-#
-LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
-
-TEXT_BASE = 0x41008000
+++ /dev/null
-/*
- * Board specific setup info
- *
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2003, ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-/* Set up the platform, once the cpu has been initialized */
-.globl lowlevel_init
-lowlevel_init:
-
- /* All SDRAM settings are done by sdram_prep */
- mov pc, lr
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/regs-pinctrl.h>
-#include <asm/arch/pinctrl.h>
-#include <asm/arch/regs-clkctrl.h>
-#include <asm/arch/regs-ocotp.h>
-
-#include <mmc.h>
-#include <imx_ssp_mmc.h>
-
-/* This should be removed after it's added into mach-types.h */
-#ifndef MACH_TYPE_MX28EVK
-#define MACH_TYPE_MX28EVK 2531
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_IMX_SSP_MMC
-
-/* MMC pins */
-static struct pin_desc mmc0_pins_desc[] = {
- { PINID_SSP0_DATA0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_DATA1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_DATA2, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_DATA3, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_DATA4, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_DATA5, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_DATA6, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_DATA7, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_CMD, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_DETECT, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_SCK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
-};
-
-static struct pin_desc mmc1_pins_desc[] = {
- { PINID_GPMI_D00, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
- { PINID_GPMI_D01, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
- { PINID_GPMI_D02, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
- { PINID_GPMI_D03, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
- { PINID_GPMI_D04, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
- { PINID_GPMI_D05, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
- { PINID_GPMI_D06, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
- { PINID_GPMI_D07, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
- { PINID_GPMI_RDY1, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
- { PINID_GPMI_RDY0, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
- { PINID_GPMI_WRN, PIN_FUN2, PAD_8MA, PAD_3V3, 1 }
-};
-
-static struct pin_group mmc0_pins = {
- .pins = mmc0_pins_desc,
- .nr_pins = ARRAY_SIZE(mmc0_pins_desc)
-};
-
-static struct pin_group mmc1_pins = {
- .pins = mmc1_pins_desc,
- .nr_pins = ARRAY_SIZE(mmc1_pins_desc)
-};
-
-struct imx_ssp_mmc_cfg ssp_mmc_cfg[2] = {
- {REGS_SSP0_BASE, HW_CLKCTRL_SSP0, BM_CLKCTRL_CLKSEQ_BYPASS_SSP0},
- {REGS_SSP1_BASE, HW_CLKCTRL_SSP1, BM_CLKCTRL_CLKSEQ_BYPASS_SSP1},
-};
-#endif
-
-/* ENET pins */
-static struct pin_desc enet_pins_desc[] = {
- { PINID_ENET0_MDC, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_ENET0_MDIO, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_ENET0_RX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_ENET0_RXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_ENET0_RXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_ENET0_TX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_ENET0_TXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_ENET0_TXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_ENET_CLK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }
-};
-
-static struct pin_group enet_pins = {
- .pins = enet_pins_desc,
- .nr_pins = ARRAY_SIZE(enet_pins_desc)
-};
-
-/*
- * Functions
- */
-int board_init(void)
-{
- /* Will change it for MX28 EVK later */
- gd->bd->bi_arch_number = MACH_TYPE_MX28EVK;
- /* Adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-#ifdef CONFIG_IMX_SSP_MMC
-
-#ifdef CONFIG_DYNAMIC_MMC_DEVNO
-int get_mmc_env_devno()
-{
- unsigned long global_boot_mode;
-
- global_boot_mode = REG_RD_ADDR(GLOBAL_BOOT_MODE_ADDR);
- return ((global_boot_mode & 0xf) == BOOT_MODE_SD1) ? 1 : 0;
-}
-#endif
-
-#define PINID_SSP0_GPIO_WP PINID_SSP1_SCK
-#define PINID_SSP1_GPIO_WP PINID_GPMI_RESETN
-
-u32 ssp_mmc_is_wp(struct mmc *mmc)
-{
- return (mmc->block_dev.dev == 0) ?
- pin_gpio_get(PINID_SSP0_GPIO_WP) :
- pin_gpio_get(PINID_SSP1_GPIO_WP);
-}
-
-int ssp_mmc_gpio_init(bd_t *bis)
-{
- s32 status = 0;
- u32 index = 0;
-
- for (index = 0; index < CONFIG_SYS_SSP_MMC_NUM;
- ++index) {
- switch (index) {
- case 0:
- /* Set up MMC pins */
- pin_set_group(&mmc0_pins);
-
- /* Power on the card slot 0 */
- pin_set_type(PINID_PWM3, PIN_GPIO);
- pin_gpio_direction(PINID_PWM3, 1);
- pin_gpio_set(PINID_PWM3, 0);
-
- /* Wait 10 ms for card ramping up */
- udelay(10000);
-
- /* Set up SD0 WP pin */
- pin_set_type(PINID_SSP0_GPIO_WP, PIN_GPIO);
- pin_gpio_direction(PINID_SSP0_GPIO_WP, 0);
-
- break;
- case 1:
- /* Set up MMC pins */
- pin_set_group(&mmc1_pins);
-
- /* Power on the card slot 1 */
- pin_set_type(PINID_PWM4, PIN_GPIO);
- pin_gpio_direction(PINID_PWM4, 1);
- pin_gpio_set(PINID_PWM4, 0);
-
- /* Wait 10 ms for card ramping up */
- udelay(10000);
-
- /* Set up SD1 WP pin */
- pin_set_type(PINID_SSP1_GPIO_WP, PIN_GPIO);
- pin_gpio_direction(PINID_SSP1_GPIO_WP, 0);
-
- break;
- default:
- printf("Warning: you configured more ssp mmc controller"
- "(%d) as supported by the board(2)\n",
- CONFIG_SYS_SSP_MMC_NUM);
- return status;
- }
- status |= imx_ssp_mmc_initialize(bis, &ssp_mmc_cfg[index]);
- }
-
- return status;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- if (!ssp_mmc_gpio_init(bis))
- return 0;
- else
- return -1;
-}
-
-#endif
-
-#ifdef CONFIG_MXC_FEC
-#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-int fec_get_mac_addr(unsigned char *mac)
-{
- u32 val;
-
- /*set this bit to open the OTP banks for reading*/
- REG_WR(REGS_OCOTP_BASE, HW_OCOTP_CTRL_SET,
- BM_OCOTP_CTRL_RD_BANK_OPEN);
-
- /*wait until OTP contents are readable*/
- while (BM_OCOTP_CTRL_BUSY & REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CTRL))
- udelay(100);
-
- mac[0] = 0x00;
- mac[1] = 0x04;
- val = REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CUSTn(0));
- mac[2] = (val >> 24) & 0xFF;
- mac[3] = (val >> 16) & 0xFF;
- mac[4] = (val >> 8) & 0xFF;
- mac[5] = (val >> 0) & 0xFF;
- return 0;
-}
-#endif
-#endif
-
-void enet_board_init(void)
-{
- /* Set up ENET pins */
- pin_set_group(&enet_pins);
-
- /* Power on the external phy */
- pin_set_type(PINID_SSP1_DATA3, PIN_GPIO);
- pin_gpio_direction(PINID_SSP1_DATA3, 1);
- pin_gpio_set(PINID_SSP1_DATA3, 0);
-
- /* Reset the external phy */
- pin_set_type(PINID_ENET0_RX_CLK, PIN_GPIO);
- pin_gpio_direction(PINID_ENET0_RX_CLK, 1);
- pin_gpio_set(PINID_ENET0_RX_CLK, 0);
- udelay(200);
- pin_gpio_set(PINID_ENET0_RX_CLK, 1);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
- . = ALIGN(4);
- .text :
- {
- cpu/arm926ejs/start.o (.text)
- *(.text)
- }
- .rodata : { *(.rodata) }
- . = ALIGN(4);
- .data : { *(.data) }
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- __bss_start = .;
- .bss (NOLOAD) : { *(.bss) }
- _end = .;
-}
+++ /dev/null
-#
-# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := mx31_3stack.o
-SOBJS := lowlevel_init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
-
-TEXT_BASE = 0x87f00000
+++ /dev/null
-/*
- * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
- * Copyright (C) 2008, Freescale Semiconductor
- * Modifications for MX31 3Stack board
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/mx31-regs.h>
-
-.macro REG reg, val
- ldr r2, =\reg
- ldr r3, =\val
- str r3, [r2]
-.endm
-
-.macro REG8 reg, val
- ldr r2, =\reg
- ldr r3, =\val
- strb r3, [r2]
-.endm
-
-.macro DELAY loops
- ldr r2, =\loops
-1:
- subs r2, r2, #1
- nop
- bcs 1b
-.endm
-
-.macro init_aips
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- ldr r0, =0x43F00000
- ldr r1, =0x77777777
- str r1, [r0, #0x00]
- str r1, [r0, #0x04]
- ldr r0, =0x53F00000
- str r1, [r0, #0x00]
- str r1, [r0, #0x04]
-
- /*
- * Clear the on and off peripheral modules Supervisor Protect bit
- * for SDMA to access them. Did not change the AIPS control registers
- * (offset 0x20) access type
- */
- ldr r0, =0x43F00000
- ldr r1, =0x0
- str r1, [r0, #0x40]
- str r1, [r0, #0x44]
- str r1, [r0, #0x48]
- str r1, [r0, #0x4C]
- ldr r1, [r0, #0x50]
- and r1, r1, #0x00FFFFFF
- str r1, [r0, #0x50]
-
- ldr r0, =0x53F00000
- ldr r1, =0x0
- str r1, [r0, #0x40]
- str r1, [r0, #0x44]
- str r1, [r0, #0x48]
- str r1, [r0, #0x4C]
- ldr r1, [r0, #0x50]
- and r1, r1, #0x00FFFFFF
- str r1, [r0, #0x50]
-.endm /* init_aips */
-
-.macro init_max
- ldr r0, =0x43F04000
- /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
- ldr r1, =0x00302154
- str r1, [r0, #0x000] /* for S0 */
- str r1, [r0, #0x100] /* for S1 */
- str r1, [r0, #0x200] /* for S2 */
- str r1, [r0, #0x300] /* for S3 */
- str r1, [r0, #0x400] /* for S4 */
- /* SGPCR - always park on last master */
- ldr r1, =0x10
- str r1, [r0, #0x010] /* for S0 */
- str r1, [r0, #0x110] /* for S1 */
- str r1, [r0, #0x210] /* for S2 */
- str r1, [r0, #0x310] /* for S3 */
- str r1, [r0, #0x410] /* for S4 */
- /* MGPCR - restore default values */
- ldr r1, =0x0
- str r1, [r0, #0x800] /* for M0 */
- str r1, [r0, #0x900] /* for M1 */
- str r1, [r0, #0xA00] /* for M2 */
- str r1, [r0, #0xB00] /* for M3 */
- str r1, [r0, #0xC00] /* for M4 */
- str r1, [r0, #0xD00] /* for M5 */
-.endm /* init_max */
-
-.macro init_m3if
- /* Configure M3IF registers */
- ldr r1, =0xB8003000
- /*
- * M3IF Control Register (M3IFCTL)
- * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
- * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
- * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
- * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
- * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
- * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
- * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
- * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
- * ------------
- * 0x00000040
- */
- ldr r0, =0x00000040
- str r0, [r1] /* M3IF control reg */
-.endm /* init_m3if */
-
-.macro init_drive_strength
- /*
- * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
- * in SW_PAD_CTL registers
- */
-
- /* SDCLK */
- ldr r1, =0x43FAC200
- ldr r0, [r1, #0x6C]
- bic r0, r0, #(1 << 12)
- str r0, [r1, #0x6C]
-
- /* CAS */
- ldr r0, [r1, #0x70]
- bic r0, r0, #(1 << 22)
- str r0, [r1, #0x70]
-
- /* RAS */
- ldr r0, [r1, #0x74]
- bic r0, r0, #(1 << 2)
- str r0, [r1, #0x74]
-
- /* CS2 (CSD0) */
- ldr r0, [r1, #0x7C]
- bic r0, r0, #(1 << 22)
- str r0, [r1, #0x7C]
-
- /* DQM3 */
- ldr r0, [r1, #0x84]
- bic r0, r0, #(1 << 22)
- str r0, [r1, #0x84]
-
- /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
- ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
-pad_loop:
- ldr r0, [r1, #0x88]
- bic r0, r0, #(1 << 22)
- bic r0, r0, #(1 << 12)
- bic r0, r0, #(1 << 2)
- str r0, [r1, #0x88]
- add r1, r1, #4
- subs r2, r2, #0x1
- bne pad_loop
-.endm /* init_drive_strength */
-
-.section ".text.init", "x"
-
-.globl lowlevel_init
-lowlevel_init:
-
- ldr r0, =0x40000015 /* start from AIPS 2GB region */
- mcr p15, 0, r0, c15, c2, 4
-
- init_aips
-
- init_max
-
- init_m3if
-
- init_drive_strength
-
- /* Image Processing Unit: */
- /* Too early to switch display on? */
- REG IPU_CONF, IPU_CONF_DI_EN
- /* Clock Control Module: */
- REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
-
- DELAY 0x40000
-
- REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
- /* Switch to MCU PLL */
- REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
-
- /* 532-133-66.5 */
- ldr r0, =CCM_BASE
- ldr r1, =0xFF871D58
- /* PDR0 */
- str r1, [r0, #0x4]
- ldr r1, MPCTL_PARAM_532
- /* MPCTL */
- str r1, [r0, #0x10]
-
- /* Set UPLL=240MHz, USB=60MHz */
- ldr r1, =0x49FCFE7F
- /* PDR1 */
- str r1, [r0, #0x8]
- ldr r1, UPCTL_PARAM_240
- /* UPCTL */
- str r1, [r0, #0x14]
- /* default CLKO to 1/8 of the ARM core */
- mov r1, #0x000002C0
- add r1, r1, #0x00000006
- /* COSR */
- str r1, [r0, #0x1c]
-
- /* initial CSD0 MDDR */
- REG 0xB8001004, 0x0075E73A
- REG 0xB8001010, 0x00000002 /* reset */
- REG 0xB8001010, 0x00000004
- DELAY 0x10000
-
- REG 0xB8001000, 0x92100000
- REG 0x80000F00, 0x0
- REG 0xB8001000, 0xA2100000
- REG 0x80000000, 0x0
- REG 0xB8001000, 0xB2100000
- REG8 0x80000033, 0x0
- REG8 0x81000000, 0xff
- REG 0xB8001000, 0x82226080
- REG 0x80000000, 0x0
- REG 0xB8001010, 0x0000000c
-
- mov r13, ip
- /* copy blocks of total uboot to DDR */
- b mxc_nand_load
-
-MPCTL_PARAM_532:
- .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
-UPCTL_PARAM_240:
- .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
+++ /dev/null
-/*
- * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- * Modifications for MX31 3Stack board
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mx31.h>
-#include <asm/arch/mx31-regs.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-int board_init(void)
-{
- /* CS5: Debug board for ethernet */
- __REG(CSCR_U(5)) = 0x0000D843;
- __REG(CSCR_L(5)) = 0x22252521;
- __REG(CSCR_A(5)) = 0x22220A00;
-
- /* setup pins for UART1 */
- mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
- mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
- mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
- mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
-
- /* SPI2 */
- mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2);
- mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK);
- mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SPI_RDY);
- mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI);
- mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO);
- mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0);
- mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS1);
-
- /* start SPI2 clock */
- __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
-
- gd->bd->bi_arch_number = MACH_TYPE_MX31_3DS; /* board id for linux */
- gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */
-
- return 0;
-}
-
-int checkboard(void)
-{
- printf("Board: MX31 3Stack\n");
- return 0;
-}
+++ /dev/null
-/*
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(reset)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- * (.text.head) /* arm reset handler */
- * (.text.init) /* lowlevel initial */
- * (.text.load) /* nand copy and load */
- * (.text.setup)
- board/freescale/mx31_3stack/libmx31_3stack.a (.text)
- lib_arm/libarm.a (.text)
- net/libnet.a (.text)
- drivers/mtd/libmtd.a (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o(.text)
-
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
+++ /dev/null
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := mx35_3stack.o
-SOBJS := lowlevel_init.o
-SOBJS += flash_header.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __BOARD_MX35_3STACK_H
-#define __BOARD_MX35_3STACK_H
-
-#define UNALIGNED_ACCESS_ENABLE
-#define LOW_INT_LATENCY_ENABLE
-#define BRANCH_PREDICTION_ENABLE
-
-#define L2CC_AUX_CTL_CONFIG 0x00030024
-
-#define AIPS_MPR_CONFIG 0x77777777
-#define AIPS_OPACR_CONFIG 0x00000000
-
-/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
-#define MAX_MPR_CONFIG 0x00302154
-/* SGPCR - always park on last master */
-#define MAX_SGPCR_CONFIG 0x00000010
-/* MGPCR - restore default values */
-#define MAX_MGPCR_CONFIG 0x00000000
-
-/*
- * M3IF Control Register (M3IFCTL)
- * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
- * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
- * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
- * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
- * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
- * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
- * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
- * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
- * ------------
- * 0x00000040
- */
-#define M3IF_CONFIG 0x00000040
-
-#define DBG_BASE_ADDR WEIM_CTRL_CS5
-#define DBG_CSCR_U_CONFIG 0x0000D843
-#define DBG_CSCR_L_CONFIG 0x22252521
-#define DBG_CSCR_A_CONFIG 0x22220A00
-
-#define CCM_CCMR_CONFIG 0x003F4208
-#define CCM_PDR0_CONFIG 0x00801000
-
-#define PLL_BRM_OFFSET 31
-#define PLL_PD_OFFSET 26
-#define PLL_MFD_OFFSET 16
-#define PLL_MFI_OFFSET 10
-
-#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET)
-#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET)
-#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET)
-#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET)
-#define _PLL_MFN(x) (x)
-#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
- (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
- _PLL_MFN(mfn))
-
-#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1)
-#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
-#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
-
-/*MEMORY SETING*/
-#define ESDCTL_0x92220000 0x92220000
-#define ESDCTL_0xA2220000 0xA2220000
-#define ESDCTL_0xB2220000 0xB2220000
-#define ESDCTL_0x82228080 0x82228080
-
-#define ESDCTL_PRECHARGE 0x00000400
-
-#define ESDCTL_MDDR_CONFIG 0x007FFC3F
-#define ESDCTL_MDDR_MR 0x00000033
-#define ESDCTL_MDDR_EMR 0x02000000
-
-#define ESDCTL_DDR2_CONFIG 0x007FFC3F
-#define ESDCTL_DDR2_EMR2 0x04000000
-#define ESDCTL_DDR2_EMR3 0x06000000
-#define ESDCTL_DDR2_EN_DLL 0x02000400
-#define ESDCTL_DDR2_RESET_DLL 0x00000333
-#define ESDCTL_DDR2_MR 0x00000233
-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
-
-#define ESDCTL_DELAY_LINE5 0x00F49F00
-#endif /* __BOARD_MX35_3STACK_H */
+++ /dev/null
-LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
-
-TEXT_BASE = 0x87800000
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx35.h>
-#include "board-mx35_3stack.h"
-
-#ifdef CONFIG_FLASH_HEADER
-#ifndef CONFIG_FLASH_HEADER_OFFSET
-# error "Must define the offset of flash header"
-#endif
-
-/* Flash header setup */
-#define DCDGEN(i,type, addr, data) \
-dcd_##i: ;\
- .long type ;\
- .long addr ;\
- .long data
-
-#define GEN_FHEADERADDR(x) (x)
-
-.section ".text.flasheader", "x"
- b _start
- .org CONFIG_FLASH_HEADER_OFFSET
-app_code_jump_v: .long GEN_FHEADERADDR(_start)
-app_code_barker: .long CONFIG_FLASH_HEADER_BARKER
-app_code_csf: .long 0
-hwcfg_ptr_ptr: .long GEN_FHEADERADDR(hwcfg_ptr)
-super_root_key: .long 0
-hwcfg_ptr: .long GEN_FHEADERADDR(dcd_data)
-app_dest_ptr: .long TEXT_BASE
-dcd_data: .long 0xB17219E9
-#ifdef MEMORY_MDDR_ENABLE
- .long (dcd_data_end - dcd_data - 8)
-
-//WEIM config-CS5 init
-DCDGEN(1, 4, 0xB8002054, 0x444a4541)
-DCDGEN(1_1, 4, 0xB8002050, 0x0000dcf6)
-DCDGEN(1_2, 4, 0xB8002058, 0x44443302)
-//MDDR init
-//enable mDDR
-DCDGEN(2, 4, 0xB8001010, 0x00000004)
-//reset delay time
-DCDGEN(3, 4, 0xB8001010, 0x0000000C)
-DCDGEN(4, 4, 0xB800100C, 0x007ffc3f)
-DCDGEN(5, 4, 0xB800100C, 0x007ffc3f)
-DCDGEN(6, 4, 0xB8001004, 0x007ffc3f)
-DCDGEN(7, 4, 0xB8001000, 0x92220000)
-DCDGEN(8, 1, 0x80000400, 0xda)
-DCDGEN(9, 4, 0xB8001000, 0xA2220000)
-DCDGEN(10, 4, 0x80000000, 0x87654321)
-DCDGEN(11, 4, 0x80000000, 0x87654321)
-DCDGEN(12, 4, 0xB8001000, 0xB2220000)
-DCDGEN(13, 1, 0x80000033, 0xda)
-DCDGEN(14, 1, 0x82000000, 0xda)
-DCDGEN(15, 4, 0xB8001000, 0x82226080)
-DCDGEN(16, 4, 0xB8001010, 0x00000004)
-DCDGEN(17, 4, 0xB8001008, 0x00002000)
-
-#else
- .long 240
-
-//WEIM config-CS5 init
-DCDGEN(1, 4, 0xB8002050, 0x0000d843)
-DCDGEN(1_1, 4, 0xB8002054, 0x22252521)
-DCDGEN(1_2, 4, 0xB8002058, 0x22220a00)
-
-//DDR2 init
-DCDGEN(2, 4, 0xB8001010, 0x00000304)
-DCDGEN(3, 4, 0xB8001010, 0x0000030C)
-DCDGEN(4, 4, 0xB8001004, 0x007ffc3f)
-DCDGEN(5, 4, 0xB8001000, 0x92220000)
-DCDGEN(6, 4, 0x80000400, 0x12345678)
-DCDGEN(7, 4, 0xB8001000, 0xA2220000)
-DCDGEN(8, 4, 0x80000000, 0x87654321)
-DCDGEN(9, 4, 0x80000000, 0x87654321)
-DCDGEN(10, 4, 0xB8001000, 0xB2220000)
-DCDGEN(11, 1, 0x80000233, 0xda)
-DCDGEN(12, 1, 0x82000780, 0xda)
-DCDGEN(13, 1, 0x82000400, 0xda)
-DCDGEN(14, 4, 0xB8001000, 0x82226080)
-DCDGEN(15, 4, 0xB8001004, 0x007ffc3f)
-DCDGEN(16, 4, 0xB800100C, 0x007ffc3f)
-DCDGEN(17, 4, 0xB8001010, 0x00000304)
-DCDGEN(18, 4, 0xB8001008, 0x00002000)
-
-#endif
-dcd_data_end:
-
-//CARD_FLASH_CFG_PARMS_T---length
-card_cfg: .long 0x100000
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx35.h>
-#include "board-mx35_3stack.h"
-
-/*
- * return soc version
- * 0x10: TO1
- * 0x20: TO2
- * 0x30: TO3
- */
-.macro check_soc_version ret, tmp
- ldr \tmp, =IIM_BASE_ADDR
- ldr \ret, [\tmp, #IIM_SREV]
- cmp \ret, #0x00
- moveq \tmp, #ROMPATCH_REV
- ldreq \ret, [\tmp]
- moveq \ret, \ret, lsl #4
- addne \ret, \ret, #0x10
-.endm
-
-/*
- * L2CC Cache setup/invalidation/disable
- */
-.macro init_l2cc
- /* Disable L2 cache first */
- mov r0, #L2CC_BASE_ADDR
- ldr r1, [r0, #L2_CACHE_CTL_REG]
- bic r1, r1, #0x1
- str r1, [r0, #L2_CACHE_CTL_REG]
-
- /*
- * Configure L2 Cache:
- * - 128k size(16k way)
- * - 8-way associativity
- * - 0 ws TAG/VALID/DIRTY
- * - 4 ws DATA R/W
- */
- ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
- and r1, r1, #0xFE000000
- ldr r2, =L2CC_AUX_CTL_CONFIG
- orr r1, r1, r2
- str r1, [r0, #L2_CACHE_AUX_CTL_REG]
-
- /* Workaournd for TO1 DDR issue:WT*/
- check_soc_version r1, r2
- cmp r1, #CHIP_REV_2_0
- ldrlo r1, [r0, #L2_CACHE_DBG_CTL_REG]
- orrlo r1, r1, #2
- strlo r1, [r0, #L2_CACHE_DBG_CTL_REG]
-
- /* Invalidate L2 */
- mov r1, #0x000000FF
- str r1, [r0, #L2_CACHE_INV_WAY_REG]
-1:
- /* Poll Invalidate By Way register */
- ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
- cmp r2, #0
- bne 1b
-.endm /* init_l2cc */
-
-/* AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.*/
-.macro init_aips
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- ldr r0, =AIPS1_BASE_ADDR
- ldr r1, =AIPS_MPR_CONFIG
- str r1, [r0, #0x00]
- str r1, [r0, #0x04]
- ldr r0, =AIPS2_BASE_ADDR
- str r1, [r0, #0x00]
- str r1, [r0, #0x04]
-
- /*
- * Clear the on and off peripheral modules Supervisor Protect bit
- * for SDMA to access them. Did not change the AIPS control registers
- * (offset 0x20) access type
- */
- ldr r0, =AIPS1_BASE_ADDR
- ldr r1, =AIPS_OPACR_CONFIG
- str r1, [r0, #0x40]
- str r1, [r0, #0x44]
- str r1, [r0, #0x48]
- str r1, [r0, #0x4C]
- str r1, [r0, #0x50]
- ldr r0, =AIPS2_BASE_ADDR
- str r1, [r0, #0x40]
- str r1, [r0, #0x44]
- str r1, [r0, #0x48]
- str r1, [r0, #0x4C]
- str r1, [r0, #0x50]
-.endm /* init_aips */
-
-/* MAX (Multi-Layer AHB Crossbar Switch) setup */
-.macro init_max
- ldr r0, =MAX_BASE_ADDR
- /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
- ldr r1, =MAX_MPR_CONFIG
- str r1, [r0, #0x000] /* for S0 */
- str r1, [r0, #0x100] /* for S1 */
- str r1, [r0, #0x200] /* for S2 */
- str r1, [r0, #0x300] /* for S3 */
- str r1, [r0, #0x400] /* for S4 */
- /* SGPCR - always park on last master */
- ldr r1, =MAX_SGPCR_CONFIG
- str r1, [r0, #0x010] /* for S0 */
- str r1, [r0, #0x110] /* for S1 */
- str r1, [r0, #0x210] /* for S2 */
- str r1, [r0, #0x310] /* for S3 */
- str r1, [r0, #0x410] /* for S4 */
- /* MGPCR - restore default values */
- ldr r1, =MAX_MGPCR_CONFIG
- str r1, [r0, #0x800] /* for M0 */
- str r1, [r0, #0x900] /* for M1 */
- str r1, [r0, #0xA00] /* for M2 */
- str r1, [r0, #0xB00] /* for M3 */
- str r1, [r0, #0xC00] /* for M4 */
- str r1, [r0, #0xD00] /* for M5 */
-.endm /* init_max */
-
-/* M3IF setup */
-.macro init_m3if
- /* Configure M3IF registers */
- ldr r1, =M3IF_BASE_ADDR
- /*
- * M3IF Control Register (M3IFCTL)
- * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
- * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
- * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
- * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
- * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
- * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
- * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
- * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
- * ------------
- * 0x00000040
- */
- ldr r0, =M3IF_CONFIG
- str r0, [r1] /* M3IF control reg */
-.endm /* init_m3if */
-
-/* To support 133MHz DDR */
-.macro init_drive_strength
-/*
- mov r0, #0x2
- ldr r1, =IOMUXC_BASE_ADDR
- add r1, r1, #0x368
- add r2, r1, #0x4C8 - 0x368
-1: str r0, [r1], #4
- cmp r1, r2
- ble 1b
-*/
-.endm /* init_drive_strength */
-
-/* CPLD on CS5 setup */
-.macro init_debug_board
- ldr r0, =DBG_BASE_ADDR
- ldr r1, =DBG_CSCR_U_CONFIG
- str r1, [r0, #0x00]
- ldr r1, =DBG_CSCR_L_CONFIG
- str r1, [r0, #0x04]
- ldr r1, =DBG_CSCR_A_CONFIG
- str r1, [r0, #0x08]
-.endm /* init_debug_board */
-
-/* clock setup */
-.macro init_clock
- ldr r0, =CCM_BASE_ADDR
-
- /* default CLKO to 1/32 of the ARM core*/
- ldr r1, [r0, #CLKCTL_COSR]
- bic r1, r1, #0x00000FF00
- bic r1, r1, #0x0000000FF
- mov r2, #0x00006C00
- add r2, r2, #0x67
- orr r1, r1, r2
- str r1, [r0, #CLKCTL_COSR]
-
- ldr r2, =CCM_CCMR_CONFIG
- str r2, [r0, #CLKCTL_CCMR]
-
- check_soc_version r1, r2
- cmp r1, #CHIP_REV_2_0
- ldrhs r3, =CCM_MPLL_532_HZ
- bhs 1f
- ldr r2, [r0, #CLKCTL_PDR0]
- tst r2, #CLKMODE_CONSUMER
- ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
- ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
-1:
- str r3, [r0, #CLKCTL_MPCTL]
-
- ldr r1, =CCM_PPLL_300_HZ
- str r1, [r0, #CLKCTL_PPCTL]
-
- ldr r1, =CCM_PDR0_CONFIG
- bic r1, r1, #0x800000
- str r1, [r0, #CLKCTL_PDR0]
-
- ldr r1, [r0, #CLKCTL_CGR0]
- orr r1, r1, #0x0C300000
- str r1, [r0, #CLKCTL_CGR0]
-
- ldr r1, [r0, #CLKCTL_CGR1]
- orr r1, r1, #0x00000C00
- orr r1, r1, #0x00000003
- str r1, [r0, #CLKCTL_CGR1]
-.endm /* init_clock */
-
-.macro setup_sdram
- ldr r0, =ESDCTL_BASE_ADDR
- mov r3, #0x2000
- str r3, [r0, #0x0]
- str r3, [r0, #0x8]
-
- /*ip(r12) has used to save lr register in upper calling*/
- mov fp, lr
-
- mov r5, #0x00
- mov r2, #0x00
- mov r1, #CSD0_BASE_ADDR
- bl setup_sdram_bank
- cmp r3, #0x0
- orreq r5, r5, #1
- eorne r2, r2, #0x1
- blne setup_sdram_bank
-
- mov lr, fp
-
- check_soc_version r3, r4
- cmp r1, #CHIP_REV_2_0
- bhs 1f
- cmp r5, #0
- movne r3, #L2CC_BASE_ADDR
- ldrne r4, [r3, #L2_CACHE_AUX_CTL_REG]
- orrne r4, r4, #0x1000
- strne r4, [r3, #L2_CACHE_AUX_CTL_REG]
-1:
- ldr r3, =ESDCTL_DELAY_LINE5
- str r3, [r0, #0x30]
-.endm /* setup_sdram */
-
-.section ".text.init", "x"
-
-.globl lowlevel_init
-lowlevel_init:
- /* Platform CHIP level init*/
-#ifdef TURN_OFF_IMPRECISE_ABORT
- mrs r0, cpsr
- bic r0, r0, #0x100
- msr cpsr, r0
-#endif
-
- mrc 15, 0, r1, c1, c0, 0
-
-#ifndef BRANCH_PREDICTION_ENABLE
- mrc 15, 0, r0, c1, c0, 1
- bic r0, r0, #7
- mcr 15, 0, r0, c1, c0, 1
-#else
- mrc 15, 0, r0, c1, c0, 1
- orr r0, r0, #7
- mcr 15, 0, r0, c1, c0, 1
- orr r1, r1, #(1<<11)
-#endif
-
-#ifdef UNALIGNED_ACCESS_ENABLE
- orr r1, r1, #(1<<22)
-#endif
-
-#ifdef LOW_INT_LATENCY_ENABLE
- orr r1, r1, #(1<<21)
-#endif
- mcr 15, 0, r1, c1, c0, 0
-
- mov r0, #0
-#ifdef BRANCH_PREDICTION_ENABLE
- mcr 15, 0, r0, c15, c2, 4
-#endif
- mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
- mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
- mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
-
- /* initializes very early AIPS, what for?
- * Then it also initializes Multi-Layer AHB Crossbar Switch,
- * M3IF */
- /* Also setup the Peripheral Port Remap register inside the core */
- ldr r0, =0x40000015 /* start from AIPS 2GB region */
- mcr p15, 0, r0, c15, c2, 4
-
- init_l2cc
-
- init_aips
-
- init_max
-
- init_m3if
-
- init_drive_strength
-
- init_clock
- init_debug_board
-
- cmp pc, #PHYS_SDRAM_1
- blo init_sdram_start
- cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
- blo skip_sdram_setup
-
-init_sdram_start:
- /*init_sdram*/
- setup_sdram
-skip_sdram_setup:
- mov r0, #NFC_BASE_ADDR
- add r1, r0, #NFC_BUF_SIZE
- cmp pc, r0
- movlo pc, lr
- cmp pc, r1
- movhi pc, lr
- /* return from mxc_nand_load */
- /* r12 saved upper lr*/
- b mxc_nand_load
-
-/*
- * r0: ESDCTL control base, r1: sdram slot base
- * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
- */
-setup_sdram_bank:
- mov r3, #0xE /*0xA + 0x4*/
- tst r2, #0x1
- orreq r3, r3, #0x300 /*DDR2*/
- str r3, [r0, #0x10]
- bic r3, r3, #0x00A
- str r3, [r0, #0x10]
- beq 2f
-
- mov r3, #0x20000
-1: subs r3, r3, #1
- bne 1b
-
-2: tst r2, #0x1
- ldreq r3, =ESDCTL_DDR2_CONFIG
- ldrne r3, =ESDCTL_MDDR_CONFIG
- cmp r1, #CSD1_BASE_ADDR
- strlo r3, [r0, #0x4]
- strhs r3, [r0, #0xC]
-
- ldr r3, =ESDCTL_0x92220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- ldr r4, =ESDCTL_PRECHARGE
- strb r3, [r1, r4]
-
- tst r2, #0x1
- bne skip_set_mode
-
- cmp r1, #CSD1_BASE_ADDR
- ldr r3, =ESDCTL_0xB2220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- ldr r4, =ESDCTL_DDR2_EMR2
- strb r3, [r1, r4]
- ldr r4, =ESDCTL_DDR2_EMR3
- strb r3, [r1, r4]
- ldr r4, =ESDCTL_DDR2_EN_DLL
- strb r3, [r1, r4]
- ldr r4, =ESDCTL_DDR2_RESET_DLL
- strb r3, [r1, r4]
-
- ldr r3, =ESDCTL_0x92220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- ldr r4, =ESDCTL_PRECHARGE
- strb r3, [r1, r4]
-
-skip_set_mode:
- cmp r1, #CSD1_BASE_ADDR
- ldr r3, =ESDCTL_0xA2220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- strb r3, [r1]
- strb r3, [r1]
-
- ldr r3, =ESDCTL_0xB2220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- tst r2, #0x1
- ldreq r4, =ESDCTL_DDR2_MR
- ldrne r4, =ESDCTL_MDDR_MR
- mov r3, #0xDA
- strb r3, [r1, r4]
- ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
- streqb r3, [r1, r4]
- ldreq r4, =ESDCTL_DDR2_EN_DLL
- ldrne r4, =ESDCTL_MDDR_EMR
- strb r3, [r1, r4]
-
- cmp r1, #CSD1_BASE_ADDR
- ldr r3, =ESDCTL_0x82228080
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
-
- tst r2, #0x1
- moveq r4, #0x20000
- movne r4, #0x200
-1: subs r4, r4, #1
- bne 1b
-
- str r3, [r1, #0x100]
- ldr r4, [r1, #0x100]
- cmp r3, r4
- movne r3, #1
- moveq r3, #0
-
- mov pc, lr
+++ /dev/null
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/mx35.h>
-#include <asm/arch/mx35_pins.h>
-#include <asm/arch/iomux.h>
-#include <i2c.h>
-#include <linux/types.h>
-
-#ifdef CONFIG_CMD_MMC
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#endif
-
-#ifdef CONFIG_ARCH_MMU
-#include <asm/mmu.h>
-#include <asm/arch/mmu.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static u32 system_rev;
-
-u32 get_board_rev(void)
-{
- return system_rev;
-}
-
-static inline void setup_soc_rev(void)
-{
- int reg;
- reg = __REG(IIM_BASE_ADDR + IIM_SREV);
- if (!reg) {
- reg = __REG(ROMPATCH_REV);
- reg <<= 4;
- } else
- reg += CHIP_REV_1_0;
- system_rev = 0x35000 + (reg & 0xFF);
-}
-
-static inline void set_board_rev(int rev)
-{
- system_rev = (system_rev & ~(0xF << 8)) | (rev & 0xF) << 8;
-}
-
-int is_soc_rev(int rev)
-{
- return (system_rev & 0xFF) - rev;
-}
-
-#ifdef CONFIG_ARCH_MMU
-void board_mmu_init(void)
-{
- unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
- unsigned long i;
-
- /*
- * Set the TTB register
- */
- asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
-
- /*
- * Set the Domain Access Control Register
- */
- i = ARM_ACCESS_DACR_DEFAULT;
- asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
-
- /*
- * First clear all TT entries - ie Set them to Faulting
- */
- memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
- /* Actual Virtual Size Attributes Function */
- /* Base Base MB cached? buffered? access permissions */
- /* xxx00000 xxx00000 */
- X_ARM_MMU_SECTION(0x000, 0xF00, 0x1,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* ROM */
- X_ARM_MMU_SECTION(0x100, 0x100, 0x1,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* iRAM */
- X_ARM_MMU_SECTION(0x300, 0x300, 0x1,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* L2CC */
- /* Internal Regsisters upto SDRAM*/
- X_ARM_MMU_SECTION(0x400, 0x400, 0x400,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW);
- X_ARM_MMU_SECTION(0x800, 0x000, 0x80,
- ARM_CACHEABLE, ARM_BUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
- X_ARM_MMU_SECTION(0x800, 0x800, 0x80,
- ARM_CACHEABLE, ARM_BUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
- X_ARM_MMU_SECTION(0x800, 0x880, 0x80,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
- X_ARM_MMU_SECTION(0x900, 0x900, 0x80,
- ARM_CACHEABLE, ARM_BUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* SDRAM 1:128M*/
- X_ARM_MMU_SECTION(0xA00, 0xA00, 0x40,
- ARM_CACHEABLE, ARM_BUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* Flash */
- X_ARM_MMU_SECTION(0xB00, 0xB00, 0x20,
- ARM_CACHEABLE, ARM_BUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* PSRAM */
- /* ESDCTL, WEIM, M3IF, EMI, NFC, External I/O */
- X_ARM_MMU_SECTION(0xB20, 0xB20, 0x1E0,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW);
-
- /* Enable MMU */
- MMU_ON();
-}
-#endif
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-int board_init(void)
-{
- int pad;
-
-#ifdef CONFIG_MFG
-/* MFG firmware need reset usb to avoid host crash firstly */
-#define USBCMD 0x53FF4140
- int val = readl(USBCMD);
- val &= ~0x1; /*RS bit*/
- writel(val, USBCMD);
-#endif
-
- setup_soc_rev();
-
- /* enable clocks */
- __REG(CCM_BASE_ADDR + CLKCTL_CGR0) |= 0x003F0000;
- __REG(CCM_BASE_ADDR + CLKCTL_CGR1) |= 0x00030FFF;
-
- /* setup pins for I2C1 */
- mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
-
- pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
- | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
-
- mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
- mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
-
- /* setup pins for FEC */
- mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
-
- pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \
- PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW);
-
- mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \
- PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \
- PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \
- PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU);
- mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \
- PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \
- PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \
- PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \
- PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
-
- gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */
- gd->bd->bi_boot_params = 0x80000100; /* address of boot parameters */
-
- return 0;
-}
-
-#ifdef BOARD_LATE_INIT
-static inline int board_detect(void)
-{
- u8 buf[4];
- int id;
-
- if (i2c_read(0x08, 0x7, 1, buf, 3) < 0) {
- printf("board_late_init: read PMIC@0x08:0x7 fail\n");
- return 0;
- }
- id = (buf[0] << 16) + (buf[1] << 8) + buf[2];
- printf("PMIC@0x08:0x7 is %x\n", id);
- id = (id >> 6) & 0x7;
- if (id == 0x7) {
- set_board_rev(1);
- return 1;
- }
- set_board_rev(0);
- return 0;
-}
-
-int board_late_init(void)
-{
- u8 reg[3];
- int i;
-
- if (board_detect()) {
- mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
- MUX_CONFIG_ALT1);
- printf("i.MX35 CPU board version 2.0\n");
- if (i2c_read(0x08, 0x1E, 1, reg, 3)) {
- printf("board_late_init: read PMIC@0x08:0x1E fail\n");
- return 0;
- }
- reg[2] |= 0x3;
- if (i2c_write(0x08, 0x1E, 1, reg, 3)) {
- printf("board_late_init: write PMIC@0x08:0x1E fail\n");
- return 0;
- }
- if (i2c_read(0x08, 0x20, 1, reg, 3)) {
- printf("board_late_init: read PMIC@0x08:0x20 fail\n");
- return 0;
- }
- reg[2] |= 0x1;
- if (i2c_write(0x08, 0x20, 1, reg, 3)) {
- printf("board_late_init: write PMIC@0x08:0x20 fail\n");
- return 0;
- }
- mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
- mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
- __REG(GPIO1_BASE_ADDR + 0x04) |= 1 << 5;
- __REG(GPIO1_BASE_ADDR) |= 1 << 5;
- } else
- printf("i.MX35 CPU board version 1.0\n");
-
- if (i2c_read(0x69, 0x20, 1, reg, 1) < 0) {
- printf("board_late_init: read PMIC@0x69:0x20 fail\n");
- return 0;
- }
-
- reg[0] |= 0x4;
- if (i2c_write(0x69, 0x20, 1, reg, 1) < 0) {
- printf("board_late_init: write back PMIC@0x69:0x20 fail\n");
- return 0;
- }
-
- for (i = 0; i < 1000; i++)
- udelay(200);
-
- if (i2c_read(0x69, 0x1A, 1, reg, 1) < 0) {
- printf("board_late_init: read PMIC@0x69:0x1A fail\n");
- return 0;
- }
-
- reg[0] &= 0x7F;
- if (i2c_write(0x69, 0x1A, 1, reg, 1) < 0) {
- printf("board_late_init: write back PMIC@0x69:0x1A fail\n");
- return 0;
- }
- for (i = 0; i < 1000; i++)
- udelay(200);
-
- reg[0] |= 0x80;
- if (i2c_write(0x69, 0x1A, 1, reg, 1) < 0) {
- printf("board_late_init: 2st write back PMIC@0x69:0x1A fail\n");
- return 0;
- }
-
- return 0;
-}
-#endif
-
-int checkboard(void)
-{
- printf("Board: MX35 3STACK ");
-
- if (system_rev & CHIP_REV_2_0)
- printf("2.0 [");
- else
- printf("1.0 [");
-
- switch (__REG(CCM_BASE_ADDR + CLKCTL_RCSR) & 0x0F) {
- case 0x0000:
- printf("POR");
- break;
- case 0x0002:
- printf("JTAG");
- break;
- case 0x0004:
- printf("RST");
- break;
- case 0x0008:
- printf("WDT");
- break;
- default:
- printf("unknown");
- }
- printf("]\n");
- return 0;
-}
-
-#if defined(CONFIG_SMC911X)
-extern int smc911x_initialize(u8 dev_num, int base_addr);
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- int rc = -ENODEV;
-#if defined(CONFIG_SMC911X)
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
-
- cpu_eth_init(bis);
-
- return rc;
-}
-
-#ifdef CONFIG_CMD_MMC
-
-struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR, 1, 1},
- {MMC_SDHC2_BASE_ADDR, 1, 1},
-};
-
-int esdhc_gpio_init(bd_t *bis)
-{
- u32 pad_val = 0, index = 0;
- s32 status = 0;
-
- /* IOMUX PROGRAMMING */
- for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
- ++index) {
- switch (index) {
- case 0:
- pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH |
- PAD_CTL_100K_PD | PAD_CTL_SRE_FAST;
- mxc_request_iomux(MX35_PIN_SD1_CMD,
- MUX_CONFIG_FUNC | MUX_CONFIG_SION);
- mxc_iomux_set_pad(MX35_PIN_SD1_CMD, pad_val);
-
- pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH |
- PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
- mxc_request_iomux(MX35_PIN_SD1_CLK,
- MUX_CONFIG_FUNC | MUX_CONFIG_SION);
- mxc_iomux_set_pad(MX35_PIN_SD1_CLK, pad_val);
- mxc_request_iomux(MX35_PIN_SD1_DATA0,
- MUX_CONFIG_FUNC);
- mxc_iomux_set_pad(MX35_PIN_SD1_DATA0, pad_val);
- mxc_request_iomux(MX35_PIN_SD1_DATA3,
- MUX_CONFIG_FUNC);
- mxc_iomux_set_pad(MX35_PIN_SD1_DATA3, pad_val);
-
- break;
- case 1:
- mxc_request_iomux(MX35_PIN_SD2_CLK,
- MUX_CONFIG_FUNC | MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_SD2_CMD,
- MUX_CONFIG_FUNC | MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_SD2_DATA0,
- MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_SD2_DATA3,
- MUX_CONFIG_FUNC);
-
- pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
- PAD_CTL_100K_PD | PAD_CTL_SRE_FAST;
- mxc_iomux_set_pad(MX35_PIN_SD2_CMD, pad_val);
-
- pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH |
- PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
- mxc_iomux_set_pad(MX35_PIN_SD2_CLK, pad_val);
- mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, pad_val);
- mxc_iomux_set_pad(MX35_PIN_SD2_DATA3, pad_val);
-
- break;
- default:
- printf("Warning: you configured more ESDHC controller"
- "(%d) as supported by the board(2)\n",
- CONFIG_SYS_FSL_ESDHC_NUM);
- return status;
- break;
- }
- status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
- }
-
- return status;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- if (!esdhc_gpio_init(bis))
- return 0;
- else
- return -1;
-}
-#endif
+++ /dev/null
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
- board/freescale/mx35_3stack/flash_header.o (.text.flasheader)
- *(.text.head) /*arm startup code*/
- *(.text.init) /*platform lowlevel initial code*/
- *(.text.load) /*load bootloader*/
- *(.text.setup) /*platform post lowlevel initial code*/
- *(.text.vect) /*platform post lowlevel initial code*/
- board/freescale/mx35_3stack/libmx35_3stack.a (.text)
- lib_arm/libarm.a (.text)
- net/libnet.a (.text)
- drivers/mtd/libmtd.a (.text)
- drivers/mmc/libmmc.a (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o(.text)
-
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
+++ /dev/null
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2010 Freescale Semiconductor, Inc.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := mx50_arm2.o
-SOBJS := lowlevel_init.o flash_header.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
-
-sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp
-
-ifndef TEXT_BASE
- TEXT_BASE = 0x77800000
-endif
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx50.h>
-
-#ifdef CONFIG_FLASH_HEADER
-#ifndef CONFIG_FLASH_HEADER_OFFSET
-# error "Must define the offset of flash header"
-#endif
-
-.section ".text.flasheader", "x"
- b _start
- .org CONFIG_FLASH_HEADER_OFFSET
-
-/* First IVT to copy the plugin that initializes the system into OCRAM */
-ivt_header: .long 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
-app_code_jump_v: .long 0xF8006458 /* Plugin entry point */
-reserv1: .long 0x0
-dcd_ptr: .long 0x0
-boot_data_ptr: .long 0xF8006420
-self_ptr: .long 0xF8006400
-app_code_csf: .long 0x0 /* reserve 4K for csf */
-reserv2: .long 0x0
-boot_data: .long 0xF8006000
-image_len: .long 8*1024 /* Can copy upto 72K, OCRAM free space */
-plugin: .long 0x1 /* Enable plugin flag */
-
-/* Second IVT to give entry point into the bootloader copied to DDR */
-ivt2_header: .long 0x402000D1 //Tag=0xD1, Len=0x0020, Ver=0x40
-app2_code_jump_v: .long _start // Entry point for the bootloader
-reserv3: .long 0x0
-dcd2_ptr: .long 0x0
-boot_data2_ptr: .long boot_data2
-self_ptr2: .long ivt2_header
-app_code_csf2: .long 0x0 // reserve 4K for csf
-reserv4: .long 0x0
-boot_data2: .long TEXT_BASE
-image_len2: .long _end - TEXT_BASE
-plugin2: .long 0x0
-
-/*=============================================================================
- * Here starts the plugin code
- *===========================================================================*/
-
-plugin_start:
-/* Save the return address and the function arguments */
- push {r0-r2, lr}
-
-/*=============================================================================
- *init script for codex LPDDR1-200MHz CPU board
- *===========================================================================*/
-
-/* Setup PLL1 to be 800 MHz */
- ldr r0, =CCM_BASE_ADDR
-
-/* Switch ARM domain to be clocked from LP-APM */
- mov r1, #0x4
- str r1, [r0, #CLKCTL_CCSR]
-
- ldr r0, =PLL1_BASE_ADDR
- ldr r1, =0x1232
- str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
- ldr r1, =0x2
- str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-
- ldr r1, =DP_OP_800
- str r1, [r0, #PLL_DP_OP]
- str r1, [r0, #PLL_DP_HFS_OP]
-
- ldr r1, =DP_MFD_800
- str r1, [r0, #PLL_DP_MFD]
- str r1, [r0, #PLL_DP_HFS_MFD]
-
- ldr r1, =DP_MFN_800
- str r1, [r0, #PLL_DP_MFN]
- str r1, [r0, #PLL_DP_HFS_MFN]
-
- /* Now restart PLL */
- ldr r1, =0x1232
- str r1, [r0, #PLL_DP_CTL]
-wait_pll1_lock:
- ldr r1, [r0, #PLL_DP_CTL]
- ands r1, r1, #0x1
- beq wait_pll1_lock
-
-/* Switch ARM back to PLL1 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x0
- str r1, [r0,#CLKCTL_CCSR]
-
-/*=============================================================================
- * Enable all clocks (they are disabled by ROM code)
- *===========================================================================*/
-
- mov r1, #0xffffffff
- str r1, [r0, #0x68]
- str r1, [r0, #0x6c]
- str r1, [r0, #0x70]
- str r1, [r0, #0x74]
- str r1, [r0, #0x78]
- str r1, [r0, #0x7c]
- str r1, [r0, #0x80]
- str r1, [r0, #0x84]
-
-#if defined(CONFIG_LPDDR2)
-
-/* DDR clock setting -- Set DDR to be div 3 to get 266MHz */
-/* setmem /32 0x53FD4098 = 0x80000003 */
- ldr r1, =0x80000003
- str r1, [r0, #0x98]
-
-/* poll to make sure DDR dividers take effect */
-1:
- ldr r1, [r0, #0x8c]
- ands r1, r1, #0x4
- bne 1b
-
-/*=============================================================================
- * IOMUX
- *===========================================================================*/
- ldr r0, =0x53fa8000
- mov r1, #0x04000000
- str r1, [r0, #0x6ac]
- mov r2, #0x00380000
- str r2, [r0, #0x6a4]
- str r2, [r0, #0x668]
- str r2, [r0, #0x698]
- str r2, [r0, #0x6a0]
- str r2, [r0, #0x6a8]
- str r2, [r0, #0x6b4]
- str r2, [r0, #0x498]
- str r2, [r0, #0x49c]
- str r2, [r0, #0x4f0]
- str r2, [r0, #0x500]
- str r2, [r0, #0x4c8]
- str r2, [r0, #0x528]
- str r2, [r0, #0x4f4]
- str r2, [r0, #0x4fc]
- str r2, [r0, #0x4cc]
- str r2, [r0, #0x524]
-
-/*=============================================================================
- * DDR setting
- *===========================================================================*/
-
- ldr r0, =DATABAHN_BASE_ADDR
-/* setmem /32 0x14000000 = 0x00000500 */
- ldr r1, =0x00000500
- str r1, [r0, #0x0]
-/* setmem /32 0x14000004 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x4]
-/* setmem /32 0x14000008 = 0x0000001b */
- ldr r1, =0x0000001b
- str r1, [r0, #0x8]
-/* setmem /32 0x1400000c = 0x0000d056 */
- ldr r1, =0x0000d056
- str r1, [r0, #0xc]
-/* setmem /32 0x14000010 = 0x0000010b */
- ldr r1, =0x0000010b
- str r1, [r0, #0xc]
-/* setmem /32 0x14000014 = 0x00000a6b */
- ldr r1, =0x00000a6b
- str r1, [r0, #0x14]
-/* setmem /32 0x14000018 = 0x02020d0c */
- ldr r1, =0x02020d0c
- str r1, [r0, #0x18]
-/* setmem /32 0x1400001c = 0x0c110302 */
- ldr r1, =0x0c110302
- str r1, [r0, #0x1c]
-/* setmem /32 0x14000020 = 0x05020503 */
- ldr r1, =0x05020503
- str r1, [r0, #0x20]
-/* setmem /32 0x14000024 = 0x00000105 */
- ldr r1, =0x00000105
- str r1, [r0, #0x24]
-/* setmem /32 0x14000028 = 0x01000403 */
- ldr r1, =0x01000403
- str r1, [r0, #0x28]
-/* setmem /32 0x1400002c = 0x09040501 */
- ldr r1, =0x09040501
- str r1, [r0, #0x2c]
-/* setmem /32 0x14000030 = 0x02000000 */
- ldr r1, =0x02000000
- str r1, [r0, #0x30]
-/* setmem /32 0x14000034 = 0x00000e02 */
- ldr r1, =0x00000e02
- str r1, [r0, #0x34]
-/* setmem /32 0x14000038 = 0x00000006 */
- ldr r1, =0x00000006
- str r1, [r0, #0x38]
-/* setmem /32 0x1400003c = 0x00002301 */
- ldr r1, =0x00002301
- str r1, [r0, #0x3c]
-/* setmem /32 0x14000040 = 0x00050408 */
- ldr r1, =0x00050408
- str r1, [r0, #0x40]
-/* setmem /32 0x14000044 = 0x00000300 */
- ldr r1, =0x00000300
- str r1, [r0, #0x44]
-/* setmem /32 0x14000048 = 0x00260026 */
- ldr r1, =0x00260026
- str r1, [r0, #0x48]
-/* setmem /32 0x1400004c = 0x00010000 */
- ldr r1, =0x00010000
- str r1, [r0, #0x4c]
-/* setmem /32 0x1400005c = 0x02000000 */
- ldr r1, =0x02000000
- str r1, [r0, #0x5c]
-/* setmem /32 0x14000060 = 0x00000002 */
- ldr r1, =0x00000002
- str r1, [r0, #0x60]
-/* setmem /32 0x14000064 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x64]
-/* setmem /32 0x14000068 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x68]
-/* setmem /32 0x1400006c = 0x00040042 */
- ldr r1, =0x00040042
- str r1, [r0, #0x6c]
-/* setmem /32 0x14000070 = 0x00000001 */
- ldr r1, =0x00000001
- str r1, [r0, #0x70]
-/* setmem /32 0x14000074 = 0x00000000 */
- ldr r1, =0x00000001
- str r1, [r0, #0x74]
-/* setmem /32 0x14000078 = 0x00040042 */
- ldr r1, =0x00040042
- str r1, [r0, #0x78]
-/* setmem /32 0x1400007c = 0x00000001 */
- ldr r1, =0x00000001
- str r1, [r0, #0x7c]
-/* setmem /32 0x14000080 = 0x010b0000 */
- ldr r1, =0x010b0000
- str r1, [r0, #0x80]
-/* setmem /32 0x14000084 = 0x00000060 */
- ldr r1, =0x00000060
- str r1, [r0, #0x84]
-/* setmem /32 0x14000088 = 0x02400018 */
- ldr r1, =0x02400018
- str r1, [r0, #0x88]
-/* setmem /32 0x1400008c = 0x01000e00 */
- ldr r1, =0x01000e00
- str r1, [r0, #0x8c]
-/* setmem /32 0x14000090 = 0x0a010101 */
- ldr r1, =0x0a010101
- str r1, [r0, #0x90]
-/* setmem /32 0x14000094 = 0x01011f1f */
- ldr r1, =0x01011f1f
- str r1, [r0, #0x94]
-/* setmem /32 0x14000098 = 0x01010101 */
- ldr r1, =0x01010101
- str r1, [r0, #0x98]
-/* setmem /32 0x1400009c = 0x00030101 */
- ldr r1, =0x00030101
- str r1, [r0, #0x9c]
-/* setmem /32 0x140000a0 = 0x00010000 */
- ldr r1, =0x00010000
- str r1, [r0, #0xa0]
-/* setmem /32 0x140000a4 = 0x00010000 */
- ldr r1, =0x00010000
- str r1, [r0, #0xa4]
-/* setmem /32 0x140000a8 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0xa8]
-/* setmem /32 0x140000ac = 0x0000ffff */
- ldr r1, =0x0000ffff
- str r1, [r0, #0xac]
-/* setmem /32 0x140000c8 = 0x02020101 */
- ldr r1, =0x02020101
- str r1, [r0, #0xc8]
-/* setmem /32 0x140000cc = 0x01000000 */
- ldr r1, =0x01000000
- str r1, [r0, #0xcc]
-/* setmem /32 0x140000d0 = 0x01000201 */
- ldr r1, =0x01000201
- str r1, [r0, #0xd0]
-/* setmem /32 0x140000d4 = 0x00000200 */
- ldr r1, =0x00000200
- str r1, [r0, #0xd4]
-/* setmem /32 0x140000d8 = 0x00000102 */
- ldr r1, =0x00000102
- str r1, [r0, #0xd8]
-/* setmem /32 0x140000dc = 0x0000ffff */
- ldr r1, =0x0000ffff
- str r1, [r0, #0xdc]
-/* setmem /32 0x140000e0 = 0x0000ffff */
- ldr r1, =0x0000ffff
- str r1, [r0, #0xdc]
-/* setmem /32 0x140000e4 = 0x02020000 */
- ldr r1, =0x02020000
- str r1, [r0, #0xe4]
-/* setmem /32 0x140000e8 = 0x02020202 */
- ldr r1, =0x02020202
- str r1, [r0, #0xe8]
-/* setmem /32 0x140000ec = 0x00000202 */
- ldr r1, =0x00000202
- str r1, [r0, #0xec]
-/* setmem /32 0x140000f0 = 0x01010064 */
- ldr r1, =0x01010064
- str r1, [r0, #0xf0]
-/* setmem /32 0x140000f4 = 0x01010101 */
- ldr r1, =0x01010101
- str r1, [r0, #0xf4]
-/* setmem /32 0x140000f8 = 0x00010101 */
- ldr r1, =0x00010101
- str r1, [r0, #0xf8]
-/* setmem /32 0x140000fc = 0x00000064 */
- ldr r1, =0x00000064
- str r1, [r0, #0xfc]
-/* setmem /32 0x14000100 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x100]
-/* setmem /32 0x14000104 = 0x02000802 */
- ldr r1, =0x02000802
- str r1, [r0, #0x104]
-/* setmem /32 0x14000108 = 0x04080000 */
- ldr r1, =0x04080000
- str r1, [r0, #0x108]
-/* setmem /32 0x1400010c = 0x04080408 */
- ldr r1, =0x04080408
- str r1, [r0, #0x10c]
-/* setmem /32 0x14000110 = 0x04080408 */
- ldr r1, =0x04080408
- str r1, [r0, #0x110]
-/* setmem /32 0x14000114 = 0x03060408 */
- ldr r1, =0x03060408
- str r1, [r0, #0x114]
-/* setmem /32 0x14000118 = 0x01010002 */
- ldr r1, =0x01010002
- str r1, [r0, #0x118]
-/* setmem /32 0x1400011c = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x11c]
-/* setmem /32 0x14000200 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x200]
-/* setmem /32 0x14000204 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x204]
-/* setmem /32 0x14000208 = 0xf5003a27 */
- ldr r1, =0xf5003a27
- str r1, [r0, #0x208]
-/* setmem /32 0x1400020c = 0x074002e1 */
- ldr r1, =0x074002e1
- str r1, [r0, #0x20c]
-/* setmem /32 0x14000210 = 0xf5003a27 */
- ldr r1, =0xf5003a27
- str r1, [r0, #0x210]
-/* setmem /32 0x14000214 = 0x074002e1 */
- ldr r1, =0x074002e1
- str r1, [r0, #0x214]
-/* setmem /32 0x14000218 = 0xf5003a27 */
- ldr r1, =0xf5003a27
- str r1, [r0, #0x218]
-/* setmem /32 0x1400021c = 0x074002e1 */
- ldr r1, =0x074002e1
- str r1, [r0, #0x21c]
-/* setmem /32 0x14000220 = 0xf5003a27 */
- ldr r1, =0xf5003a27
- str r1, [r0, #0x220]
-/* setmem /32 0x14000224 = 0x074002e1 */
- ldr r1, =0x074002e1
- str r1, [r0, #0x224]
-/* setmem /32 0x14000228 = 0xf5003a27 */
- ldr r1, =0xf5003a27
- str r1, [r0, #0x228]
-/* setmem /32 0x1400022c = 0x074002e1 */
- ldr r1, =0x074002e1
- str r1, [r0, #0x22c]
-/* setmem /32 0x14000230 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x230]
-/* setmem /32 0x14000234 = 0x00810006 */
- ldr r1, =0x00810006
- str r1, [r0, #0x234]
-/* setmem /32 0x14000238 = 0x20099414 */
- ldr r1, =0x20099414
- str r1, [r0, #0x238]
-/* setmem /32 0x1400023c = 0x000a1401 */
- ldr r1, =0x000a1401
- str r1, [r0, #0x23c]
-/* setmem /32 0x14000240 = 0x20099414 */
- ldr r1, =0x20099414
- str r1, [r0, #0x240]
-/* setmem /32 0x14000244 = 0x000a1401 */
- ldr r1, =0x000a1401
- str r1, [r0, #0x244]
-/* setmem /32 0x14000248 = 0x20099414 */
- ldr r1, =0x20099414
- str r1, [r0, #0x248]
-/* setmem /32 0x1400024c = 0x000a1401 */
- ldr r1, =0x000a1401
- str r1, [r0, #0x24c]
-/* setmem /32 0x14000250 = 0x20099414 */
- ldr r1, =0x20099414
- str r1, [r0, #0x250]
-/* setmem /32 0x14000254 = 0x000a1401 */
- ldr r1, =0x000a1401
- str r1, [r0, #0x254]
-/* setmem /32 0x14000258 = 0x20099414 */
- ldr r1, =0x000a1401
- str r1, [r0, #0x258]
-/* setmem /32 0x1400025c = 0x000a1401 */
- ldr r1, =0x000a1401
- str r1, [r0, #0x25c]
-
-/* Start ddr */
-/* setmem /32 0x14000000 = 0x00000501 // bit[0]: start */
- ldr r1, =0x00000501
- str r1, [r0, #0x0]
-/* poll to make sure it is done */
-1:
- ldr r1, [r0, #0xa8]
- ands r1, r1, #0x10
- beq 1b
-#else
-
-/*==================================================================
- * lpddr1-mddr
- *=================================================================*/
-
-/* DDR clock setting -- Set DDR to be div 4 to get 200MHz */
-/* setmem /32 0x53FD4098 = 0x80000004 */
- ldr r1, =0x80000004
- str r1, [r0, #0x98]
-
-/* poll to make sure DDR dividers take effect */
-1:
- ldr r1, [r0, #0x8c]
- ands r1, r1, #0x4
- bne 1b
-
-/*==================================================================
- * IOMUX
- *=================================================================*/
- ldr r0, =0x53fa8600
- mov r1, #0x02000000
- mov r3, #0x00200000
- mov r2, #0x0
- str r1, [r0, #0xac]
- str r2, [r0, #0x6c]
- str r2, [r0, #0x8c]
- str r3, [r0, #0xa4]
- str r3, [r0, #0x68]
- str r3, [r0, #0x98]
- str r3, [r0, #0xa0]
- str r3, [r0, #0xa8]
- str r3, [r0, #0xb4]
-
- ldr r0, =0x53fa8400
- str r3, [r0, #0x98]
- str r3, [r0, #0x9c]
- str r3, [r0, #0xf0]
- str r3, [r0, #0x100]
- str r3, [r0, #0xc8]
- str r3, [r0, #0x128]
- str r3, [r0, #0xf4]
- str r3, [r0, #0xfc]
- str r3, [r0, #0xcc]
- str r3, [r0, #0x124]
- str r2, [r0, #0x270]
-
-/*==============================================================
- * DDR setting
- *=============================================================*/
- ldr r0, =DATABAHN_BASE_ADDR
-/* setmem /32 0x14000000 = 0x00000100 */
- ldr r1, =0x00000100
- str r1, [r0, #0x0]
-/* setmem /32 0x14000008 = 0x00009c40 */
- ldr r1, =0x00009c40
- str r1, [r0, #0x8]
-/* setmem /32 0x14000014 = 0x02000000 */
- ldr r1, =0x02000000
- str r1, [r0, #0x14]
-/* setmem /32 0x14000018 = 0x01010706 */
- ldr r1, =0x01010706
- str r1, [r0, #0x018]
-/* setmem /32 0x1400001c = 0x080b0201 */
- ldr r1, =0x080b0201
- str r1, [r0, #0x01c]
-/* setmem /32 0x14000020 = 0x02000303 */
- ldr r1, =0x02000303
- str r1, [r0, #0x020]
-/* setmem /32 0x14000024 = 0x0136b002 */
- ldr r1, =0x0136b002
- str r1, [r0, #0x024]
-/* setmem /32 0x14000028 = 0x01000101 */
- ldr r1, =0x01000101
- str r1, [r0, #0x028]
-/* setmem /32 0x1400002c = 0x06030301 */
- ldr r1, =0x06030301
- str r1, [r0, #0x02c]
-/* setmem /32 0x14000030 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x030]
-/* setmem /32 0x14000034 = 0x00000a02 */
- ldr r1, =0x00000a02
- str r1, [r0, #0x034]
-/* setmem /32 0x14000038 = 0x00000003 */
- ldr r1, =0x00000003
- str r1, [r0, #0x038]
-/* setmem /32 0x1400003c = 0x00001401 */
- ldr r1, =0x00001401
- str r1, [r0, #0x03c]
-/* setmem /32 0x14000040 = 0x0005030f */
- ldr r1, =0x0005030f
- str r1, [r0, #0x040]
-/* setmem /32 0x14000044 = 0x00000200 */
- ldr r1, =0x00000200
- str r1, [r0, #0x044]
-/* setmem /32 0x14000048 = 0x00180018 */
- ldr r1, =0x00180018
- str r1, [r0, #0x048]
-/* setmem /32 0x1400004c = 0x00010000 */
- ldr r1, =0x00010000
- str r1, [r0, #0x04c]
-/* setmem /32 0x1400005c = 0x01000000 */
- ldr r1, =0x01000000
- str r1, [r0, #0x05c]
-/* setmem /32 0x14000060 = 0x00000001 */
- ldr r1, =0x00000001
- str r1, [r0, #0x060]
-/* setmem /32 0x14000064 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x064]
-/* setmem /32 0x14000068 = 0x00320000 */
- ldr r1, =0x00320000
- str r1, [r0, #0x068]
-/* setmem /32 0x1400006c = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x06c]
-/* setmem /32 0x14000070 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x070]
-/* setmem /32 0x14000074 = 0x00320000 */
- ldr r1, =0x00320000
- str r1, [r0, #0x074]
-/* setmem /32 0x14000080 = 0x02000000 */
- ldr r1, =0x02000000
- str r1, [r0, #0x080]
-/* setmem /32 0x14000084 = 0x00000100 */
- ldr r1, =0x00000100
- str r1, [r0, #0x084]
-/* setmem /32 0x14000088 = 0x02400040 */
- ldr r1, =0x02400040
- str r1, [r0, #0x088]
-/* setmem /32 0x1400008c = 0x01000000 */
- ldr r1, =0x01000000
- str r1, [r0, #0x08c]
-/* setmem /32 0x14000090 = 0x0a000100 */
- ldr r1, =0x0a000100
- str r1, [r0, #0x090]
-/* setmem /32 0x14000094 = 0x01011f1f */
- ldr r1, =0x01011f1f
- str r1, [r0, #0x094]
-/* setmem /32 0x14000098 = 0x01010101 */
- ldr r1, =0x01010101
- str r1, [r0, #0x098]
-/* setmem /32 0x1400009c = 0x00030101 */
- ldr r1, =0x00030101
- str r1, [r0, #0x09c]
-/* setmem /32 0x140000a4 = 0x00010000 */
- ldr r1, =0x00010000
- str r1, [r0, #0x0a4]
-/* setmem /32 0x140000ac = 0x0000ffff */
- ldr r1, =0x0000ffff
- str r1, [r0, #0x0ac]
-/* setmem /32 0x140000c8 = 0x02020101 */
- ldr r1, =0x02020101
- str r1, [r0, #0x0c8]
-/* setmem /32 0x140000cc = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x0cc]
-/* setmem /32 0x140000d0 = 0x01000202 */
- ldr r1, =0x01000202
- str r1, [r0, #0x0d0]
-/* setmem /32 0x140000d4 = 0x02030302 */
- ldr r1, =0x02030302
- str r1, [r0, #0x0d4]
-/* setmem /32 0x140000d8 = 0x00000001 */
- ldr r1, =0x00000001
- str r1, [r0, #0x0d8]
-/* setmem /32 0x140000dc = 0x0000ffff */
- ldr r1, =0x0000ffff
- str r1, [r0, #0x0dc]
-/* setmem /32 0x140000e0 = 0x0000ffff */
- ldr r1, =0x0000ffff
- str r1, [r0, #0x0e0]
-/* setmem /32 0x140000e4 = 0x02020000 */
- ldr r1, =0x02020000
- str r1, [r0, #0x0e4]
-/* setmem /32 0x140000e8 = 0x02020202 */
- ldr r1, =0x02020202
- str r1, [r0, #0x0e8]
-/* setmem /32 0x140000ec = 0x00000202 */
- ldr r1, =0x00000202
- str r1, [r0, #0x0ec]
-/* setmem /32 0x140000f0 = 0x01010064 */
- ldr r1, =0x01010064
- str r1, [r0, #0x0f0]
-/* setmem /32 0x140000f4 = 0x01010101 */
- ldr r1, =0x01010101
- str r1, [r0, #0x0f4]
-/* setmem /32 0x140000f8 = 0x00010101 */
- ldr r1, =0x00010101
- str r1, [r0, #0x0f8]
-/* setmem /32 0x140000fc = 0x00000064 */
- ldr r1, =0x00000064
- str r1, [r0, #0x0fc]
-/* setmem /32 0x14000104 = 0x02000602 */
- ldr r1, =0x02000602
- str r1, [r0, #0x0104]
-/* setmem /32 0x14000108 = 0x06120000 */
- ldr r1, =0x06120000
- str r1, [r0, #0x0108]
-/* setmem /32 0x1400010c = 0x06120612 */
- ldr r1, =0x06120612
- str r1, [r0, #0x010c]
-/* setmem /32 0x14000110 = 0x06120612 */
- ldr r1, =0x06120612
- str r1, [r0, #0x0110]
-/* setmem /32 0x14000114 = 0x01030612 */
- ldr r1, =0x01030612
- str r1, [r0, #0x0114]
-/* setmem /32 0x14000118 = 0x01010002 */
- ldr r1, =0x01010002
- str r1, [r0, #0x0118]
-
-/*=============================================================
- * DDR PHY setting
- *===========================================================*/
-
-/* setmem /32 0x14000200 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x200]
-/* setmem /32 0x14000204 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x0204]
-
-/* setmem /32 0x14000208 = 0xf5002725 */
- ldr r1, =0xf5002725
- str r1, [r0, #0x0208]
-/* setmem /32 0x14000210 = 0xf5002725 */
- ldr r1, =0xf5002725
- str r1, [r0, #0x210]
-/* setmem /32 0x14000218 = 0xf5002725 */
- ldr r1, =0xf5002725
- str r1, [r0, #0x218]
-/* setmem /32 0x14000220 = 0xf5002725 */
- ldr r1, =0xf5002725
- str r1, [r0, #0x0220]
-/* setmem /32 0x14000228 = 0xf5002725 */
- ldr r1, =0xf5002725
- str r1, [r0, #0x0228]
-
-/* setmem /32 0x1400020c = 0x070002d0 */
- ldr r1, =0x070002d0
- str r1, [r0, #0x020c]
-
-/* setmem /32 0x14000214 = 0x074002d0 */
- ldr r1, =0x074002d0
- str r1, [r0, #0x0214]
-
-/* setmem /32 0x1400021c = 0x074002d0 */
- ldr r1, =0x074002d0
- str r1, [r0, #0x021c]
-
-/* setmem /32 0x14000224 = 0x074002d0 */
- ldr r1, =0x074002d0
- str r1, [r0, #0x0224]
-
-/* setmem /32 0x1400022c = 0x074002d0 */
- ldr r1, =0x074002d0
- str r1, [r0, #0x022c]
-/* setmem /32 0x14000230 = 0x00000000 */
- ldr r1, =0x00000000
- str r1, [r0, #0x0230]
-/* setmem /32 0x14000234 = 0x00800006 */
- ldr r1, =0x00800006
- str r1, [r0, #0x0234]
-
-/* setmem /32 0x14000238 = 0x200e1014 */
- ldr r1, =0x200e1014
- str r1, [r0, #0x0238]
-/* setmem /32 0x14000240 = 0x200e1014 */
- ldr r1, =0x200e1014
- str r1, [r0, #0x0240]
-/* setmem /32 0x14000248 = 0x200e1014 */
- ldr r1, =0x200e1014
- str r1, [r0, #0x0248]
-/* setmem /32 0x14000250 = 0x200e1014 */
- ldr r1, =0x200e1014
- str r1, [r0, #0x0250]
-/* setmem /32 0x14000258 = 0x200e1014 */
- ldr r1, =0x200e1014
- str r1, [r0, #0x0258]
-
-/* setmem /32 0x1400023c = 0x000d9f01 */
- ldr r1, =0x000d9f01
- str r1, [r0, #0x023c]
-/* setmem /32 0x14000244 = 0x000d9f01 */
- ldr r1, =0x000d9f01
- str r1, [r0, #0x0244]
-/* setmem /32 0x1400024c = 0x000d9f01 */
- ldr r1, =0x000d9f01
- str r1, [r0, #0x024c]
-/* setmem /32 0x14000254 = 0x000d9f01 */
- ldr r1, =0x000d9f01
- str r1, [r0, #0x0254]
-/* setmem /32 0x1400025c = 0x000d9f01 */
- ldr r1, =0x000d9f01
- str r1, [r0, #0x025c]
-
-/* Start ddr */
-/* setmem /32 0x14000000 = 0x00000101 // bit[0]: start */
- ldr r1, =0x00000101
- str r1, [r0, #0x0]
-/* poll to make sure it is done */
-1:
- ldr r1, [r0, #0xa8]
- ands r1, r1, #0x10
- beq 1b
-
-#endif
-
-/*
- * The following is to fill in those arguments for this ROM function
- * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
- *
- * This function is used to copy data from the storage media into DDR.
-
- * start - Initial (possibly partial) image load address on entry.
- * Final image load address on exit.
- * bytes - Initial (possibly partial) image size on entry.
- * Final image size on exit.
- * boot_data - Initial @ref ivt Boot Data load address.
- */
- adr r0, DDR_DEST_ADDR
- adr r1, COPY_SIZE
- adr r2, BOOT_DATA
-
-before_calling_rom___pu_irom_hwcnfg_setup:
- mov r4, #0x2a00
- add r4, r4, #0x19
- blx r4 // This address might change in future ROM versions
-after_calling_rom___pu_irom_hwcnfg_setup:
-
-
-/* To return to ROM from plugin, we need to fill in these argument.
- * Here is what need to do:
- * Need to construct the paramters for this function before return to ROM:
- * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
- */
- pop {r0-r2, lr}
- ldr r3, DDR_DEST_ADDR
- str r3, [r0]
- ldr r3, COPY_SIZE
- str r3, [r1]
- mov r3, #0x400 /* Point to the second IVT table at offset 0x42C */
- add r3, r3, #0x2C
- str r3, [r2]
- mov r0, #1
- bx lr /* return back to ROM code */
-
-DDR_DEST_ADDR: .word 0x77800000
-COPY_SIZE: .word 0x40000
-BOOT_DATA: .word 0x77800000
- .word 0x40000 /*data be copied by pu_irom_hwcnfg_setup()*/
- .word 0
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx50.h>
-
-/*
- * L2CC Cache setup/invalidation/disable
- */
-.macro init_l2cc
- /* explicitly disable L2 cache */
- mrc 15, 0, r0, c1, c0, 1
- bic r0, r0, #0x2
- mcr 15, 0, r0, c1, c0, 1
-
- /* reconfigure L2 cache aux control reg */
- mov r0, #0xC0 /* tag RAM */
- add r0, r0, #0x4 /* data RAM */
- orr r0, r0, #(1 << 24) /* disable write allocate delay */
- orr r0, r0, #(1 << 23) /* disable write allocate combine */
- orr r0, r0, #(1 << 22) /* disable write allocate */
-
- mcr 15, 1, r0, c9, c0, 2
-.endm /* init_l2cc */
-
-/* AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.*/
-.macro init_aips
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- ldr r0, =AIPS1_BASE_ADDR
- ldr r1, =0x77777777
- str r1, [r0, #0x0]
- str r1, [r0, #0x4]
- ldr r0, =AIPS2_BASE_ADDR
- str r1, [r0, #0x0]
- str r1, [r0, #0x4]
-.endm /* init_aips */
-
-.macro setup_pll pll, freq
- ldr r0, =\pll
- ldr r1, =0x00001232
- str r1, [r0, #PLL_DP_CTL]
- mov r1, #0x2
- str r1, [r0, #PLL_DP_CONFIG]
-
- ldr r1, W_DP_OP_\freq
- str r1, [r0, #PLL_DP_OP]
- str r1, [r0, #PLL_DP_HFS_OP]
-
- ldr r1, W_DP_MFD_\freq
- str r1, [r0, #PLL_DP_MFD]
- str r1, [r0, #PLL_DP_HFS_MFD]
-
- ldr r1, W_DP_MFN_\freq
- str r1, [r0, #PLL_DP_MFN]
- str r1, [r0, #PLL_DP_HFS_MFN]
-
- ldr r1, =0x00001232
- str r1, [r0, #PLL_DP_CTL]
-1: ldr r1, [r0, #PLL_DP_CTL]
- ands r1, r1, #0x1
- beq 1b
-.endm
-
-.macro init_clock
-
- setup_pll PLL3_BASE_ADDR, 400
-
- /* Switch peripheral to PLL3 */
- /* Set periph_clk_sel[1:0]=0b10 to PLL3 */
-
- ldr r0, CCM_BASE_ADDR_W
- ldr r1, [r0, #CLKCTL_CBCDR]
- orr r1, r1, #(3 << 25)
- eor r1, r1, #(3 << 25)
- orr r1, r1, #(2 << 25)
- str r1, [r0, #CLKCTL_CBCDR]
-
- /* make sure change is effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ
-
- /* Switch peripheral to PLL2 */
- /* Set periph_clk_sel[1:0]=0b01 to PLL2 */
-
- ldr r0, CCM_BASE_ADDR_W
- ldr r1, [r0, #CLKCTL_CBCDR]
- orr r1, r1, #(3 << 25)
- eor r1, r1, #(3 << 25)
- orr r1, r1, #(1 << 25)
-
- orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10)
- orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16)
- orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19)
- str r1, [r0, #CLKCTL_CBCDR]
-
- /* make sure change is effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- setup_pll PLL3_BASE_ADDR, 216
-
- /* Set the platform clock dividers */
- ldr r0, PLATFORM_BASE_ADDR_W
- ldr r1, PLATFORM_CLOCK_DIV_W
- str r1, [r0, #PLATFORM_ICGC]
-
- /* ARM2 run at full speed */
- ldr r0, CCM_BASE_ADDR_W
- mov r1, #0
- str r1, [r0, #CLKCTL_CACRR]
-
- /* make sure change is effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- /* Restore the default values in the Gate registers */
- ldr r1, =0xFFFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
- str r1, [r0, #CLKCTL_CCGR4]
- str r1, [r0, #CLKCTL_CCGR5]
- str r1, [r0, #CLKCTL_CCGR6]
- str r1, [r0, #CLKCTL_CCGR7]
-
- /* for cko - for ARM div by 8 */
- mov r1, #0x000A0000
- add r1, r1, #0x00000F0
- str r1, [r0, #CLKCTL_CCOSR]
-.endm
-
-.section ".text.init", "x"
-
-.globl lowlevel_init
-lowlevel_init:
-
-#ifdef ENABLE_IMPRECISE_ABORT
- mrs r1, spsr /* save old spsr */
- mrs r0, cpsr /* read out the cpsr */
- bic r0, r0, #0x100 /* clear the A bit */
- msr spsr, r0 /* update spsr */
- add lr, pc, #0x8 /* update lr */
- movs pc, lr /* update cpsr */
- nop
- nop
- nop
- nop
- msr spsr, r1 /* restore old spsr */
-#endif
-
- /* ARM errata ID #468414 */
- mrc 15, 0, r1, c1, c0, 1
- orr r1, r1, #(1 << 5) /* enable L1NEON bit */
- mcr 15, 0, r1, c1, c0, 1
-
- init_l2cc
-
- init_aips
-
- init_clock /* not finished */
-
- mov pc, lr
-
-/* Board level setting value */
-CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
-W_DP_OP_800: .word DP_OP_800
-W_DP_MFD_800: .word DP_MFD_800
-W_DP_MFN_800: .word DP_MFN_800
-W_DP_OP_600: .word DP_OP_600
-W_DP_MFD_600: .word DP_MFD_600
-W_DP_MFN_600: .word DP_MFN_600
-W_DP_OP_400: .word DP_OP_400
-W_DP_MFD_400: .word DP_MFD_400
-W_DP_MFN_400: .word DP_MFN_400
-W_DP_OP_216: .word DP_OP_216
-W_DP_MFD_216: .word DP_MFD_216
-W_DP_MFN_216: .word DP_MFN_216
-PLATFORM_BASE_ADDR_W: .word ARM_BASE_ADDR
-PLATFORM_CLOCK_DIV_W: .word 0x00000124
+++ /dev/null
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mx50.h>
-#include <asm/arch/mx50_pins.h>
-#include <asm/arch/iomux.h>
-#include <asm/errno.h>
-
-#ifdef CONFIG_IMX_CSPI
-#include <imx_spi.h>
-#include <asm/arch/imx_spi_pmic.h>
-#endif
-
-#if CONFIG_I2C_MXC
-#include <i2c.h>
-#endif
-
-#ifdef CONFIG_CMD_MMC
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#endif
-
-#ifdef CONFIG_ARCH_MMU
-#include <asm/mmu.h>
-#include <asm/arch/mmu.h>
-#endif
-
-#ifdef CONFIG_CMD_CLOCK
-#include <asm/clock.h>
-#endif
-
-#ifdef CONFIG_MXC_EPDC
-#include <lcd.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static u32 system_rev;
-static enum boot_device boot_dev;
-u32 mx51_io_base_addr;
-
-static inline void setup_boot_device(void)
-{
- uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
- uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
- uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
-
- switch (bt_mem_ctl) {
- case 0x0:
- if (bt_mem_type)
- boot_dev = ONE_NAND_BOOT;
- else
- boot_dev = WEIM_NOR_BOOT;
- break;
- case 0x2:
- if (bt_mem_type)
- boot_dev = SATA_BOOT;
- else
- boot_dev = PATA_BOOT;
- break;
- case 0x3:
- if (bt_mem_type)
- boot_dev = SPI_NOR_BOOT;
- else
- boot_dev = I2C_BOOT;
- break;
- case 0x4:
- case 0x5:
- boot_dev = SD_BOOT;
- break;
- case 0x6:
- case 0x7:
- boot_dev = MMC_BOOT;
- break;
- case 0x8 ... 0xf:
- boot_dev = NAND_BOOT;
- break;
- default:
- boot_dev = UNKNOWN_BOOT;
- break;
- }
-}
-
-enum boot_device get_boot_device(void)
-{
- return boot_dev;
-}
-
-u32 get_board_rev(void)
-{
- return system_rev;
-}
-
-static inline void setup_soc_rev(void)
-{
- system_rev = 0x50000 | CHIP_REV_1_0;
-}
-
-static inline void setup_board_rev(int rev)
-{
- system_rev |= (rev & 0xF) << 8;
-}
-
-inline int is_soc_rev(int rev)
-{
- return (system_rev & 0xFF) - rev;
-}
-
-#ifdef CONFIG_ARCH_MMU
-void board_mmu_init(void)
-{
- unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
- unsigned long i;
-
- /*
- * Set the TTB register
- */
- asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
-
- /*
- * Set the Domain Access Control Register
- */
- i = ARM_ACCESS_DACR_DEFAULT;
- asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
-
- /*
- * First clear all TT entries - ie Set them to Faulting
- */
- memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
- /* Actual Virtual Size Attributes Function */
- /* Base Base MB cached? buffered? access permissions */
- /* xxx00000 xxx00000 */
- X_ARM_MMU_SECTION(0x000, 0x000, 0x10,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* ROM, 16M */
- X_ARM_MMU_SECTION(0x070, 0x070, 0x010,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* IRAM */
- X_ARM_MMU_SECTION(0x100, 0x100, 0x040,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* SATA */
- X_ARM_MMU_SECTION(0x180, 0x180, 0x100,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* IPUv3M */
- X_ARM_MMU_SECTION(0x200, 0x200, 0x200,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* GPU */
- X_ARM_MMU_SECTION(0x400, 0x400, 0x300,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* periperals */
- X_ARM_MMU_SECTION(0x700, 0x700, 0x400,
- ARM_CACHEABLE, ARM_BUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */
- X_ARM_MMU_SECTION(0x700, 0xB00, 0x400,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */
- X_ARM_MMU_SECTION(0xF00, 0xF00, 0x100,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
- X_ARM_MMU_SECTION(0xF80, 0xF80, 0x001,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* iRam */
-
- /* Workaround for arm errata #709718 */
- /* Setup PRRR so device is always mapped to non-shared */
- asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
- i &= (~(3 << 0x10));
- asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
-
- /* Enable MMU */
- MMU_ON();
-}
-#endif
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-static void setup_uart(void)
-{
-
- /* UART1 RXD */
- mxc_request_iomux(MX50_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX50_PIN_UART1_RXD, 0x1E4);
- mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
-
- /* UART1 TXD */
- mxc_request_iomux(MX50_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX50_PIN_UART1_TXD, 0x1E4);
-}
-
-#ifdef CONFIG_I2C_MXC
-static void setup_i2c(unsigned int module_base)
-{
- switch (module_base) {
- case I2C1_BASE_ADDR:
- /* i2c1 SDA */
- mxc_request_iomux(MX50_PIN_I2C1_SDA,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX50_PIN_I2C1_SDA, PAD_CTL_SRE_FAST |
- PAD_CTL_ODE_OPENDRAIN_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_HYS_ENABLE);
- /* i2c1 SCL */
- mxc_request_iomux(MX50_PIN_I2C1_SCL,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX50_PIN_I2C1_SCL, PAD_CTL_SRE_FAST |
- PAD_CTL_ODE_OPENDRAIN_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_HYS_ENABLE);
- break;
- case I2C2_BASE_ADDR:
- /* i2c2 SDA */
- mxc_request_iomux(MX50_PIN_I2C2_SDA,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX50_PIN_I2C2_SDA,
- PAD_CTL_SRE_FAST |
- PAD_CTL_ODE_OPENDRAIN_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_HYS_ENABLE);
-
- /* i2c2 SCL */
- mxc_request_iomux(MX50_PIN_I2C2_SCL,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX50_PIN_I2C2_SCL,
- PAD_CTL_SRE_FAST |
- PAD_CTL_ODE_OPENDRAIN_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_HYS_ENABLE);
- break;
- case I2C3_BASE_ADDR:
- /* i2c3 SDA */
- mxc_request_iomux(MX50_PIN_I2C3_SDA,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX50_PIN_I2C3_SDA,
- PAD_CTL_SRE_FAST |
- PAD_CTL_ODE_OPENDRAIN_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_HYS_ENABLE);
-
- /* i2c3 SCL */
- mxc_request_iomux(MX50_PIN_I2C3_SCL,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX50_PIN_I2C3_SCL,
- PAD_CTL_SRE_FAST |
- PAD_CTL_ODE_OPENDRAIN_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_HYS_ENABLE);
- break;
- default:
- printf("Invalid I2C base: 0x%x\n", module_base);
- break;
- }
-}
-
-#endif
-
-#ifdef CONFIG_IMX_CSPI
-s32 spi_get_cfg(struct imx_spi_dev_t *dev)
-{
- switch (dev->slave.cs) {
- case 0:
- /* PMIC */
- dev->base = CSPI3_BASE_ADDR;
- dev->freq = 25000000;
- dev->ss_pol = IMX_SPI_ACTIVE_HIGH;
- dev->ss = 0;
- dev->fifo_sz = 32;
- dev->us_delay = 0;
- break;
- case 1:
- /* SPI-NOR */
- dev->base = CSPI3_BASE_ADDR;
- dev->freq = 25000000;
- dev->ss_pol = IMX_SPI_ACTIVE_LOW;
- dev->ss = 1;
- dev->fifo_sz = 32;
- dev->us_delay = 0;
- break;
- default:
- printf("Invalid Bus ID! \n");
- }
-
- return 0;
-}
-
-void spi_io_init(struct imx_spi_dev_t *dev)
-{
- switch (dev->base) {
- case CSPI3_BASE_ADDR:
- mxc_request_iomux(MX50_PIN_CSPI_MOSI, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX50_PIN_CSPI_MOSI, 0x4);
-
- mxc_request_iomux(MX50_PIN_CSPI_MISO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX50_PIN_CSPI_MISO, 0x4);
-
- if (dev->ss == 0) {
- /* de-select SS1 of instance: cspi */
- mxc_request_iomux(MX50_PIN_ECSPI1_MOSI,
- IOMUX_CONFIG_ALT1);
-
- mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX50_PIN_CSPI_SS0, 0xE4);
- } else if (dev->ss == 1) {
- /* de-select SS0 of instance: cspi */
- mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT1);
-
- mxc_request_iomux(MX50_PIN_ECSPI1_MOSI,
- IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_ECSPI1_MOSI, 0xE4);
- mxc_iomux_set_input(
- MUX_IN_CSPI_IPP_IND_SS1_B_SELECT_INPUT, 0x1);
- }
-
- mxc_request_iomux(MX50_PIN_CSPI_SCLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX50_PIN_CSPI_SCLK, 0x4);
- break;
- case CSPI2_BASE_ADDR:
- case CSPI1_BASE_ADDR:
- /* ecspi1-2 fall through */
- break;
- default:
- break;
- }
-}
-#endif
-
-#ifdef CONFIG_MXC_FEC
-
-#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-
-#define HW_OCOTP_MACn(n) (0x00000250 + (n) * 0x10)
-
-int fec_get_mac_addr(unsigned char *mac)
-{
- u32 *ocotp_mac_base =
- (u32 *)(OCOTP_CTRL_BASE_ADDR + HW_OCOTP_MACn(0));
- int i;
-
- for (i = 0; i < 6; ++i, ++ocotp_mac_base)
- mac[6 - 1 - i] = readl(++ocotp_mac_base);
-
- return 0;
-}
-#endif
-
-static void setup_fec(void)
-{
- volatile unsigned int reg;
-
- /*FEC_MDIO*/
- mxc_request_iomux(MX50_PIN_SSI_RXC, IOMUX_CONFIG_ALT6);
- mxc_iomux_set_pad(MX50_PIN_SSI_RXC, 0xC);
- mxc_iomux_set_input(MUX_IN_FEC_FEC_MDI_SELECT_INPUT, 0x1);
-
- /*FEC_MDC*/
- mxc_request_iomux(MX50_PIN_SSI_RXFS, IOMUX_CONFIG_ALT6);
- mxc_iomux_set_pad(MX50_PIN_SSI_RXFS, 0x004);
-
- /* FEC RXD1 */
- mxc_request_iomux(MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D3, 0x0);
- mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, 0x0);
-
- /* FEC RXD0 */
- mxc_request_iomux(MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D4, 0x0);
- mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, 0x0);
-
- /* FEC TXD1 */
- mxc_request_iomux(MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D6, 0x004);
-
- /* FEC TXD0 */
- mxc_request_iomux(MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D7, 0x004);
-
- /* FEC TX_EN */
- mxc_request_iomux(MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D5, 0x004);
-
- /* FEC TX_CLK */
- mxc_request_iomux(MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D0, 0x0);
- mxc_iomux_set_input(MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, 0x0);
-
- /* FEC RX_ER */
- mxc_request_iomux(MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D1, 0x0);
- mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, 0);
-
- /* FEC CRS */
- mxc_request_iomux(MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX50_PIN_DISP_D2, 0x0);
- mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, 0);
-
- /* phy reset: gpio4-6 */
- mxc_request_iomux(MX50_PIN_KEY_COL3, IOMUX_CONFIG_ALT1);
-
- reg = readl(GPIO4_BASE_ADDR + 0x0);
- reg &= ~0x40;
- writel(reg, GPIO4_BASE_ADDR + 0x0);
-
- reg = readl(GPIO4_BASE_ADDR + 0x4);
- reg |= 0x40;
- writel(reg, GPIO4_BASE_ADDR + 0x4);
-
- udelay(500);
-
- reg = readl(GPIO4_BASE_ADDR + 0x0);
- reg |= 0x40;
- writel(reg, GPIO4_BASE_ADDR + 0x0);
-}
-#endif
-
-#ifdef CONFIG_CMD_MMC
-
-struct fsl_esdhc_cfg esdhc_cfg[3] = {
- {MMC_SDHC1_BASE_ADDR, 1, 1},
- {MMC_SDHC2_BASE_ADDR, 1, 1},
- {MMC_SDHC3_BASE_ADDR, 1, 1},
-};
-
-
-#ifdef CONFIG_DYNAMIC_MMC_DEVNO
-int get_mmc_env_devno()
-{
- uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
- int mmc_devno = 0;
-
- switch (soc_sbmr & 0x00300000) {
- default:
- case 0x0:
- mmc_devno = 0;
- break;
- case 0x00100000:
- mmc_devno = 1;
- break;
- case 0x00200000:
- mmc_devno = 2;
- break;
- }
-
- return mmc_devno;
-}
-#endif
-
-
-int esdhc_gpio_init(bd_t *bis)
-{
- s32 status = 0;
- u32 index = 0;
-
- for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
- ++index) {
- switch (index) {
- case 0:
- mxc_request_iomux(MX50_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD1_D0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD1_D1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD1_D2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD1_D3, IOMUX_CONFIG_ALT0);
-
- mxc_iomux_set_pad(MX50_PIN_SD1_CMD, 0x1E4);
- mxc_iomux_set_pad(MX50_PIN_SD1_CLK, 0xD4);
- mxc_iomux_set_pad(MX50_PIN_SD1_D0, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD1_D1, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD1_D2, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD1_D3, 0x1D4);
-
- break;
- case 1:
- mxc_request_iomux(MX50_PIN_SD2_CMD, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_CLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_D0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_D1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_D2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_D3, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_D4, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_D5, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_D6, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD2_D7, IOMUX_CONFIG_ALT0);
-
- mxc_iomux_set_pad(MX50_PIN_SD2_CMD, 0x14);
- mxc_iomux_set_pad(MX50_PIN_SD2_CLK, 0xD4);
- mxc_iomux_set_pad(MX50_PIN_SD2_D0, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD2_D1, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD2_D2, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD2_D3, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD2_D4, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD2_D5, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD2_D6, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD2_D7, 0x1D4);
-
- break;
- case 2:
- mxc_request_iomux(MX50_PIN_SD3_CMD, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_CLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_D0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_D1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_D2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_D3, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_D4, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_D5, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_D6, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_SD3_D7, IOMUX_CONFIG_ALT0);
-
- mxc_iomux_set_pad(MX50_PIN_SD3_CMD, 0x1E4);
- mxc_iomux_set_pad(MX50_PIN_SD3_CLK, 0xD4);
- mxc_iomux_set_pad(MX50_PIN_SD3_D0, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD3_D1, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD3_D2, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD3_D3, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD3_D4, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD3_D5, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD3_D6, 0x1D4);
- mxc_iomux_set_pad(MX50_PIN_SD3_D7, 0x1D4);
-
- break;
- default:
- printf("Warning: you configured more ESDHC controller"
- "(%d) as supported by the board(2)\n",
- CONFIG_SYS_FSL_ESDHC_NUM);
- return status;
- break;
- }
- status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
- }
-
- return status;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- if (!esdhc_gpio_init(bis))
- return 0;
- else
- return -1;
-}
-
-#endif
-
-#ifdef CONFIG_MXC_EPDC
-#ifdef CONFIG_SPLASH_SCREEN
-int setup_splash_img()
-{
-#ifdef CONFIG_SPLASH_IS_IN_MMC
- int mmc_dev = get_mmc_env_devno();
- ulong offset = CONFIG_SPLASH_IMG_OFFSET;
- ulong size = CONFIG_SPLASH_IMG_SIZE;
- ulong addr = 0;
- char *s = NULL;
- struct mmc *mmc = find_mmc_device(mmc_dev);
- uint blk_start, blk_cnt, n;
-
- s = getenv("splashimage");
-
- if (NULL == s) {
- puts("env splashimage not found!\n");
- return -1;
- }
- addr = simple_strtoul(s, NULL, 16);
-
- if (!mmc) {
- printf("MMC Device %d not found\n",
- mmc_dev);
- return -1;
- }
-
- if (mmc_init(mmc)) {
- puts("MMC init failed\n");
- return -1;
- }
-
- blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
- blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
- n = mmc->block_dev.block_read(mmc_dev, blk_start,
- blk_cnt, (u_char *)addr);
- flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
-
- return (n == blk_cnt) ? 0 : -1;
-#endif
-}
-#endif
-
-vidinfo_t panel_info = {
- .vl_refresh = 60,
- .vl_col = 800,
- .vl_row = 600,
- .vl_pixclock = 17700000,
- .vl_left_margin = 8,
- .vl_right_margin = 142,
- .vl_upper_margin = 4,
- .vl_lower_margin = 10,
- .vl_hsync = 20,
- .vl_vsync = 4,
- .vl_sync = 0,
- .vl_mode = 0,
- .vl_flag = 0,
- .vl_bpix = 3,
- cmap:0,
-};
-
-static void setup_epdc_power()
-{
- unsigned int reg;
-
- /* Setup epdc voltage */
-
- /* EPDC PWRSTAT - GPIO3[28] for PWR_GOOD status */
- mxc_request_iomux(MX50_PIN_EPDC_PWRSTAT, IOMUX_CONFIG_ALT1);
-
- /* EPDC VCOM0 - GPIO4[21] for VCOM control */
- mxc_request_iomux(MX50_PIN_EPDC_VCOM0, IOMUX_CONFIG_ALT1);
- /* Set as output */
- reg = readl(GPIO4_BASE_ADDR + 0x4);
- reg |= (1 << 21);
- writel(reg, GPIO4_BASE_ADDR + 0x4);
-
- /* UART4 TXD - GPIO6[16] for EPD PMIC WAKEUP */
- mxc_request_iomux(MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1);
- /* Set as output */
- reg = readl(GPIO6_BASE_ADDR + 0x4);
- reg |= (1 << 16);
- writel(reg, GPIO6_BASE_ADDR + 0x4);
-}
-
-void epdc_power_on()
-{
- unsigned int reg;
-
- /* Set PMIC Wakeup to high - enable Display power */
- reg = readl(GPIO6_BASE_ADDR + 0x0);
- reg |= (1 << 16);
- writel(reg, GPIO6_BASE_ADDR + 0x0);
-
- /* Wait for PWRGOOD == 1 */
- while (1) {
- reg = readl(GPIO3_BASE_ADDR + 0x0);
- if (!(reg & (1 << 28)))
- break;
-
- udelay(100);
- }
-
- /* Enable VCOM */
- reg = readl(GPIO4_BASE_ADDR + 0x0);
- reg |= (1 << 21);
- writel(reg, GPIO4_BASE_ADDR + 0x0);
-
- reg = readl(GPIO4_BASE_ADDR + 0x0);
-
- udelay(500);
-}
-
-void epdc_power_off()
-{
- unsigned int reg;
- /* Set PMIC Wakeup to low - disable Display power */
- reg = readl(GPIO6_BASE_ADDR + 0x0);
- reg |= 0 << 16;
- writel(reg, GPIO6_BASE_ADDR + 0x0);
-
- /* Disable VCOM */
- reg = readl(GPIO4_BASE_ADDR + 0x0);
- reg |= 0 << 21;
- writel(reg, GPIO4_BASE_ADDR + 0x0);
-}
-
-int setup_waveform_file()
-{
-#ifdef CONFIG_WAVEFORM_FILE_IN_MMC
- int mmc_dev = get_mmc_env_devno();
- ulong offset = CONFIG_WAVEFORM_FILE_OFFSET;
- ulong size = CONFIG_WAVEFORM_FILE_SIZE;
- ulong addr = CONFIG_WAVEFORM_BUF_ADDR;
- char *s = NULL;
- struct mmc *mmc = find_mmc_device(mmc_dev);
- uint blk_start, blk_cnt, n;
-
- if (!mmc) {
- printf("MMC Device %d not found\n",
- mmc_dev);
- return -1;
- }
-
- if (mmc_init(mmc)) {
- puts("MMC init failed\n");
- return -1;
- }
-
- blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
- blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
- n = mmc->block_dev.block_read(mmc_dev, blk_start,
- blk_cnt, (u_char *)addr);
- flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
-
- return (n == blk_cnt) ? 0 : -1;
-#else
- return -1;
-#endif
-}
-
-static void setup_epdc()
-{
- unsigned int reg;
-
- /* epdc iomux settings */
- mxc_request_iomux(MX50_PIN_EPDC_D0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_D1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_D2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_D3, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_D4, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_D5, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_D6, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_D7, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_GDCLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_GDSP, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_GDOE, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_GDRL, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_SDCLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_SDOE, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_SDLE, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_SDSHR, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_BDR0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_SDCE0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_SDCE1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX50_PIN_EPDC_SDCE2, IOMUX_CONFIG_ALT0);
-
-
- /*** epdc Maxim PMIC settings ***/
-
- /* EPDC PWRSTAT - GPIO3[28] for PWR_GOOD status */
- mxc_request_iomux(MX50_PIN_EPDC_PWRSTAT, IOMUX_CONFIG_ALT1);
-
- /* EPDC VCOM0 - GPIO4[21] for VCOM control */
- mxc_request_iomux(MX50_PIN_EPDC_VCOM0, IOMUX_CONFIG_ALT1);
-
- /* UART4 TXD - GPIO6[16] for EPD PMIC WAKEUP */
- mxc_request_iomux(MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1);
-
-
- /*** Set pixel clock rates for EPDC ***/
-
- /* EPDC AXI clk and EPDC PIX clk from PLL1 */
- reg = readl(CCM_BASE_ADDR + CLKCTL_CLKSEQ_BYPASS);
- reg &= ~(0x3 << 4);
- reg |= (0x2 << 4) | (0x2 << 12);
- writel(reg, CCM_BASE_ADDR + CLKCTL_CLKSEQ_BYPASS);
-
- /* EPDC AXI clk enable and set to 200MHz (800/4) */
- reg = readl(CCM_BASE_ADDR + 0xA8);
- reg &= ~((0x3 << 30) | 0x3F);
- reg |= (0x2 << 30) | 0x4;
- writel(reg, CCM_BASE_ADDR + 0xA8);
-
- /* EPDC PIX clk enable and set to 20MHz (800/40) */
- reg = readl(CCM_BASE_ADDR + 0xA0);
- reg &= ~((0x3 << 30) | (0x3 << 12) | 0x3F);
- reg |= (0x2 << 30) | (0x1 << 12) | 0x2D;
- writel(reg, CCM_BASE_ADDR + 0xA0);
-
- panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR;
- panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR;
-
- panel_info.epdc_data.wv_modes.mode_init = 0;
- panel_info.epdc_data.wv_modes.mode_du = 1;
- panel_info.epdc_data.wv_modes.mode_gc4 = 3;
- panel_info.epdc_data.wv_modes.mode_gc8 = 2;
- panel_info.epdc_data.wv_modes.mode_gc16 = 2;
- panel_info.epdc_data.wv_modes.mode_gc32 = 2;
-
- setup_epdc_power();
-
- /* Assign fb_base */
- gd->fb_base = CONFIG_FB_BASE;
-}
-#endif
-
-#ifdef CONFIG_IMX_CSPI
-static void setup_power(void)
-{
- struct spi_slave *slave;
- unsigned int val;
- unsigned int reg;
-
- puts("PMIC Mode: SPI\n");
-
- /* Enable VGEN1 to enable ethernet */
- slave = spi_pmic_probe();
-
- val = pmic_reg(slave, 30, 0, 0);
- val |= 0x3;
- pmic_reg(slave, 30, val, 1);
-
- val = pmic_reg(slave, 32, 0, 0);
- val |= 0x1;
- pmic_reg(slave, 32, val, 1);
-
- /* Enable VCAM */
- val = pmic_reg(slave, 33, 0, 0);
- val |= 0x40;
- pmic_reg(slave, 33, val, 1);
-
- spi_pmic_free(slave);
-}
-
-void setup_voltage_cpu(void)
-{
- /* Currently VDDGP 1.05v
- * no one tell me we need increase the core
- * voltage to let CPU run at 800Mhz, not do it
- */
-
- /* Raise the core frequency to 800MHz */
- writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
-
-}
-#endif
-
-int board_init(void)
-{
-#ifdef CONFIG_MFG
-/* MFG firmware need reset usb to avoid host crash firstly */
-#define USBCMD 0x140
- int val = readl(OTG_BASE_ADDR + USBCMD);
- val &= ~0x1; /*RS bit*/
- writel(val, OTG_BASE_ADDR + USBCMD);
-#endif
- /* boot device */
- setup_boot_device();
-
- /* soc rev */
- setup_soc_rev();
-
- /* arch id for linux */
- gd->bd->bi_arch_number = MACH_TYPE_MX50_ARM2;
-
- /* boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- /* iomux for uart */
- setup_uart();
-
-#ifdef CONFIG_MXC_FEC
- /* iomux for fec */
- setup_fec();
-#endif
-
-#ifdef CONFIG_MXC_EPDC
- setup_epdc();
-#endif
-
- return 0;
-}
-
-int board_late_init(void)
-{
-#ifdef CONFIG_IMX_CSPI
- setup_power();
-#endif
- return 0;
-}
-
-int checkboard(void)
-{
- printf("Board: MX50 ARM2 board\n");
-
- printf("Boot Reason: [");
-
- switch (__REG(SRC_BASE_ADDR + 0x8)) {
- case 0x0001:
- printf("POR");
- break;
- case 0x0009:
- printf("RST");
- break;
- case 0x0010:
- case 0x0011:
- printf("WDOG");
- break;
- default:
- printf("unknown");
- }
- printf("]\n");
-
- printf("Boot Device: ");
- switch (get_boot_device()) {
- case WEIM_NOR_BOOT:
- printf("NOR\n");
- break;
- case ONE_NAND_BOOT:
- printf("ONE NAND\n");
- break;
- case PATA_BOOT:
- printf("PATA\n");
- break;
- case SATA_BOOT:
- printf("SATA\n");
- break;
- case I2C_BOOT:
- printf("I2C\n");
- break;
- case SPI_NOR_BOOT:
- printf("SPI NOR\n");
- break;
- case SD_BOOT:
- printf("SD\n");
- break;
- case MMC_BOOT:
- printf("MMC\n");
- break;
- case NAND_BOOT:
- printf("NAND\n");
- break;
- case UNKNOWN_BOOT:
- default:
- printf("UNKNOWN\n");
- break;
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
- board/freescale/mx50_arm2/flash_header.o (.text.flasheader)
- cpu/arm_cortexa8/start.o
- board/freescale/mx50_arm2/libmx50_arm2.a (.text)
- lib_arm/libarm.a (.text)
- net/libnet.a (.text)
- drivers/mtd/libmtd.a (.text)
- drivers/mmc/libmmc.a (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o(.text)
-
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
+++ /dev/null
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2009 Freescale Semiconductor, Inc.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := mx51_3stack.o
-SOBJS := lowlevel_init.o flash_header.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __BOARD_FREESCALE_BOARD_MX51_3STACK_H__
-#define __BOARD_FREESCALE_BOARD_MX51_3STACK_H__
-
-/*!
- * @defgroup BRDCFG_MX51 Board Configuration Options
- * @ingroup MSL_MX51
- */
-
-/*!
- * @file mx51_3stack/board-mx51_3stack.h
- *
- * @brief This file contains all the board level configuration options.
- *
- * It currently hold the options defined for MX51 3Stack Platform.
- *
- * @ingroup BRDCFG_MX51
- */
-
-/* CPLD offsets */
-#define PBC_LED_CTRL (0x20000)
-#define PBC_SB_STAT (0x20008)
-#define PBC_ID_AAAA (0x20040)
-#define PBC_ID_5555 (0x20048)
-#define PBC_VERSION (0x20050)
-#define PBC_ID_CAFE (0x20058)
-#define PBC_INT_STAT (0x20010)
-#define PBC_INT_MASK (0x20038)
-#define PBC_INT_REST (0x20020)
-#define PBC_SW_RESET (0x20060)
-
-/* LED switchs */
-#define LED_SWITCH_REG 0x00
-/* buttons */
-#define SWITCH_BUTTONS_REG 0x08
-/* status, interrupt */
-#define INTR_STATUS_REG 0x10
-#define INTR_MASK_REG 0x38
-#define INTR_RESET_REG 0x20
-/* magic word for debug CPLD */
-#define MAGIC_NUMBER1_REG 0x40
-#define MAGIC_NUMBER2_REG 0x48
-/* CPLD code version */
-#define CPLD_CODE_VER_REG 0x50
-/* magic word for debug CPLD */
-#define MAGIC_NUMBER3_REG 0x58
-/* module reset register*/
-#define MODULE_RESET_REG 0x60
-/* CPU ID and Personality ID */
-#define MCU_BOARD_ID_REG 0x68
-
-#endif /* __BOARD_FREESCALE_BOARD_MX51_3STACK_H__ */
+++ /dev/null
-LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
-
-TEXT_BASE = 0x97800000
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx51.h>
-#include "board-mx51_3stack.h"
-
-#ifdef CONFIG_FLASH_HEADER
-#ifndef CONFIG_FLASH_HEADER_OFFSET
-# error "Must define the offset of flash header"
-#endif
-#define MXC_DCD_ITEM(i, type, addr, val) \
-dcd_node_##i: \
- .word type ; \
- .word addr ; \
- .word val ; \
-
-.section ".text.flasheader", "x"
- b _start
- .org CONFIG_FLASH_HEADER_OFFSET
-app_code_jump_v: .word _start
-app_code_code_barker: .word CONFIG_FLASH_HEADER_BARKER
-app_code_csf: .word 0
-dcd_ptr_ptr: .word dcd_ptr
-super_root_key: .word 0
-dcd_ptr: .word dcd_array_start
-app_dest_ptr: .word TEXT_BASE
-dcd_array_start:
-magic: .word 0xB17219E9
-dcd_array_size: .word dcd_data_end - dcd_array_start - 8
-/* DCD */
-/* DDR2 IOMUX configuration */
-MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200)
-MXC_DCD_ITEM(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5)
-MXC_DCD_ITEM(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5)
-MXC_DCD_ITEM(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2)
-MXC_DCD_ITEM(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2)
-MXC_DCD_ITEM(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7)
-MXC_DCD_ITEM(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45)
-MXC_DCD_ITEM(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45)
-MXC_DCD_ITEM(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45)
-MXC_DCD_ITEM(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45)
-MXC_DCD_ITEM(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0)
-MXC_DCD_ITEM(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3)
-MXC_DCD_ITEM(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3)
-MXC_DCD_ITEM(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3)
-MXC_DCD_ITEM(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3)
-MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3)
-MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3)
-MXC_DCD_ITEM(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2)
-/* Set drive strength to MAX */
-MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x6)
-MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x6)
-MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x6)
-MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x6)
-/* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
-/* CAS=3, BL=4 */
-MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
-MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
-MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
-MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa)
-MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa)
-/* Init DRAM on CS0 */
-MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
-MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
-MXC_DCD_ITEM(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
-MXC_DCD_ITEM(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019)
-MXC_DCD_ITEM(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
-MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
-MXC_DCD_ITEM(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
-MXC_DCD_ITEM(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
-MXC_DCD_ITEM(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
-MXC_DCD_ITEM(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
-MXC_DCD_ITEM(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019)
-MXC_DCD_ITEM(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
-/* Init DRAM on CS1 */
-MXC_DCD_ITEM(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
-MXC_DCD_ITEM(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
-MXC_DCD_ITEM(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
-MXC_DCD_ITEM(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
-MXC_DCD_ITEM(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
-MXC_DCD_ITEM(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
-MXC_DCD_ITEM(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
-MXC_DCD_ITEM(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
-MXC_DCD_ITEM(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
-MXC_DCD_ITEM(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
-MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d)
-MXC_DCD_ITEM(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
-MXC_DCD_ITEM(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
-MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
-MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
-MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
-MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
-dcd_data_end:
-//image_len: .word 0x80000
-image_len: .word __u_boot_cmd_end - TEXT_BASE
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx51.h>
-#include "board-mx51_3stack.h"
-
-/*
- * return soc version
- * 0x10: TO1
- * 0x20: TO2
- * 0x30: TO3
- */
-.macro check_soc_version ret, tmp
-.endm
-
-/*
- * L2CC Cache setup/invalidation/disable
- */
-.macro init_l2cc
- /* explicitly disable L2 cache */
- mrc 15, 0, r0, c1, c0, 1
- bic r0, r0, #0x2
- mcr 15, 0, r0, c1, c0, 1
-
- /* reconfigure L2 cache aux control reg */
- mov r0, #0xC0 /* tag RAM */
- add r0, r0, #0x4 /* data RAM */
- orr r0, r0, #(1 << 24) /* disable write allocate delay */
- orr r0, r0, #(1 << 23) /* disable write allocate combine */
- orr r0, r0, #(1 << 22) /* disable write allocate */
-
- ldr r1, =0x00000000
- ldr r3, [r1, #ROM_SI_REV]
- cmp r3, #0x10 /* r3 contains the silicon rev */
- /* disable write combine for TO 2 and lower */
- orrls r0, r0, #(1 << 25)
-
- mcr 15, 1, r0, c9, c0, 2
-.endm /* init_l2cc */
-
-/* AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.*/
-.macro init_aips
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- ldr r0, =AIPS1_BASE_ADDR
- ldr r1, =0x77777777
- str r1, [r0, #0x0]
- str r1, [r0, #0x4]
- ldr r0, =AIPS2_BASE_ADDR
- str r1, [r0, #0x0]
- str r1, [r0, #0x4]
- /*
- * Clear the on and off peripheral modules Supervisor Protect bit
- * for SDMA to access them. Did not change the AIPS control registers
- * (offset 0x20) access type
- */
-.endm /* init_aips */
-
-/* MAX (Multi-Layer AHB Crossbar Switch) setup */
-.macro init_max
-.endm /* init_max */
-
-/* M4IF setup */
-.macro init_m4if
- /* VPU and IPU given higher priority (0x4)
- * IPU accesses with ID=0x1 given highest priority (=0xA)
- */
- ldr r0, =M4IF_BASE_ADDR
-
- ldr r1, =0x00000203
- str r1, [r0, #0x40]
-
- ldr r1, =0x0
- str r1, [r0, #0x44]
-
- ldr r1, =0x00120125
- str r1, [r0, #0x9C]
-
- ldr r1, =0x001901A3
- str r1, [r0, #0x48]
-.endm /* init_m4if */
-
-/* To support 133MHz DDR */
-.macro init_drive_strength
-.endm /* init_drive_strength */
-
-/* CPLD on CS5 setup */
-.macro init_debug_board
-.endm /* init_debug_board */
-
-.macro setup_pll pll, freq
- ldr r2, =\pll
- ldr r1, =0x00001232
- str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
- mov r1, #0x2
- str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-
- str r3, [r2, #PLL_DP_OP]
- str r3, [r2, #PLL_DP_HFS_OP]
-
- str r4, [r2, #PLL_DP_MFD]
- str r4, [r2, #PLL_DP_HFS_MFD]
-
- str r5, [r2, #PLL_DP_MFN]
- str r5, [r2, #PLL_DP_HFS_MFN]
-
- ldr r1, =0x00001232
- str r1, [r2, #PLL_DP_CTL]
-1: ldr r1, [r2, #PLL_DP_CTL]
- ands r1, r1, #0x1
- beq 1b
-.endm
-
-.macro init_clock
- ldr r0, =CCM_BASE_ADDR
-
- /* Gate of clocks to the peripherals first */
- ldr r1, =0x3FFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- ldr r1, =0x0
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
-
- ldr r1, =0x00030000
- str r1, [r0, #CLKCTL_CCGR4]
- ldr r1, =0x00FFF030
- str r1, [r0, #CLKCTL_CCGR5]
- ldr r1, =0x00000300
- str r1, [r0, #CLKCTL_CCGR6]
-
- /* Disable IPU and HSC dividers */
- mov r1, #0x60000
- str r1, [r0, #CLKCTL_CCDR]
-
- /* Make sure to switch the DDR away from PLL 1 */
- ldr r1, =0x19239145
- str r1, [r0, #CLKCTL_CBCDR]
- /* make sure divider effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- /* Switch ARM to step clock */
- mov r1, #0x4
- str r1, [r0, #CLKCTL_CCSR]
-
- mov r3, #DP_OP_800
- mov r4, #DP_MFD_800
- mov r5, #DP_MFN_800
- setup_pll PLL1_BASE_ADDR
- mov r3, #DP_OP_665
- mov r4, #DP_MFD_665
- mov r5, #DP_MFN_665
- setup_pll PLL3_BASE_ADDR
-
- /* Switch peripheral to PLL 3 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x000010C0
- str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, =0x13239145
- str r1, [r0, #CLKCTL_CBCDR]
-
- mov r3, #DP_OP_665
- mov r4, #DP_MFD_665
- mov r5, #DP_MFN_665
- setup_pll PLL2_BASE_ADDR
-
- /* Switch peripheral to PLL2 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x19239145
- str r1, [r0, #CLKCTL_CBCDR]
- ldr r1, =0x000020C0
- str r1, [r0, #CLKCTL_CBCMR]
-
- mov r3, #DP_OP_216
- mov r4, #DP_MFD_216
- mov r5, #DP_MFN_216
- setup_pll PLL3_BASE_ADDR
-
- /* Set the platform clock dividers */
- ldr r0, =ARM_BASE_ADDR
- ldr r1, =0x00000725
- str r1, [r0, #0x14]
-
- ldr r0, =CCM_BASE_ADDR
- /* Run TO 3.0 at Full speed, for other TO's wait
- till we increase VDDGP */
- ldr r1, =0x0
- ldr r3, [r1, #ROM_SI_REV]
- cmp r3, #0x10
- movls r1, #0x1
- movhi r1, #0
- str r1, [r0, #CLKCTL_CACRR]
-
- /* Switch ARM back to PLL 1 */
- mov r1, #0
- str r1, [r0, #CLKCTL_CCSR]
-
- /* setup the rest */
- /* Use lp_apm (24MHz) source for perclk */
- ldr r1, =0x000020C2
- str r1, [r0, #CLKCTL_CBCMR]
- /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
-#ifdef CONFIG_IMX51_MDDR
- ldr r1, =0x61E35100
-#else
- ldr r1, =0x59E35100
-#endif
- str r1, [r0, #CLKCTL_CBCDR]
-
- /* Restore the default values in the Gate registers */
- ldr r1, =0xFFFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
- str r1, [r0, #CLKCTL_CCGR4]
- str r1, [r0, #CLKCTL_CCGR5]
- str r1, [r0, #CLKCTL_CCGR6]
-
- /* Use PLL 2 for UART's, get 66.5MHz from it */
- ldr r1, =0xA5A2A020
- str r1, [r0, #CLKCTL_CSCMR1]
- ldr r1, =0x00C30321
- str r1, [r0, #CLKCTL_CSCDR1]
-
- /* make sure divider effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- mov r1, #0x0
- str r1, [r0, #CLKCTL_CCDR]
-
- /* for cko - for ARM div by 8 */
- mov r1, #0x000A0000
- add r1, r1, #0x00000F0
- str r1, [r0, #CLKCTL_CCOSR]
-.endm
-
-.macro setup_wdog
- ldr r0, =WDOG1_BASE_ADDR
- mov r1, #0x30
- strh r1, [r0]
-.endm
-
-.macro setup_sdram
- ldr r0, =ESDCTL_BASE_ADDR
- /* Set CSD0 */
- mov r1, #0x80000000
- str r1, [r0, #ESDCTL_ESDCTL0]
- /* Precharge command */
- ldr r1, DDR_PERCHARGE_CMD
- str r1, [r0, #ESDCTL_ESDSCR]
- /* 2 refresh commands */
- ldr r1, DDR_REFRESH_CMD
- str r1, [r0, #ESDCTL_ESDSCR]
- str r1, [r0, #ESDCTL_ESDSCR]
- /* LMR with CAS=3 and BL=3 */
- ldr r1, DDR_LMR1_W
- str r1, [r0, #ESDCTL_ESDSCR]
- /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
- ldr r1, DDR_LMR_CMD
- str r1, [r0, #ESDCTL_ESDCTL0]
- /* Timing parameters */
- ldr r1, DDR_TIMING_W
- str r1, [r0, #ESDCTL_ESDCFG0]
- /* MDDR enable, RLAT=2 */
- ldr r1, DDR_MISC_W
- str r1, [r0, #ESDCTL_ESDMISC]
- /* Normal mode */
- mov r1, #0x00000000
- str r1, [r0, #ESDCTL_ESDSCR]
-1:
-.endm /* setup_sdram */
-
-.section ".text.init", "x"
-
-.globl lowlevel_init
-lowlevel_init:
- ldr r1, =0x00000000
- ldr r3, [r1, #ROM_SI_REV]
- ldr r0, =GPC_BASE_ADDR
- cmp r3, #0x10 // r3 contains the silicon rev
- ldrls r1, =0x1FC00000
- ldrhi r1, =0x1A800000
- str r1, [r0, #4]
-
-#ifdef ENABLE_IMPRECISE_ABORT
- mrs r1, spsr /* save old spsr */
- mrs r0, cpsr /* read out the cpsr */
- bic r0, r0, #0x100 /* clear the A bit */
- msr spsr, r0 /* update spsr */
- add lr, pc, #0x8 /* update lr */
- movs pc, lr /* update cpsr */
- nop
- nop
- nop
- nop
- msr spsr, r1 /* restore old spsr */
-#endif
-
- /* ARM errata ID #468414 */
- mrc 15, 0, r1, c1, c0, 1
- orr r1, r1, #(1 << 5) /* enable L1NEON bit */
- mcr 15, 0, r1, c1, c0, 1
-
- init_l2cc
-
- init_aips
-
-
- init_max
-
- init_m4if
-
- init_drive_strength
-
- cmp pc, #PHYS_SDRAM_1
- blo do_sdram_setup
- cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
- blo init_clock_start
-
-do_sdram_setup:
- setup_sdram
-
-init_clock_start:
- init_clock
- init_debug_board
- /*init_sdram*/
-
- /* return from mxc_nand_load */
- /* r12 saved upper lr*/
- b mxc_nand_load
-
-/* Board level setting value */
-DDR_PERCHARGE_CMD: .word 0x04008008
-DDR_REFRESH_CMD: .word 0x00008010
-DDR_LMR1_W: .word 0x00338018
-DDR_LMR_CMD: .word 0xB2220000
-DDR_TIMING_W: .word 0xB02567A9
-DDR_MISC_W: .word 0x000A0104
+++ /dev/null
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/mx51.h>
-#include <asm/arch/mx51_pins.h>
-#include <asm/arch/iomux.h>
-#include <i2c.h>
-#include <asm/arch/keypad.h>
-#include "board-mx51_3stack.h"
-#include <netdev.h>
-
-#ifdef CONFIG_CMD_MMC
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#endif
-
-#ifdef CONFIG_ARCH_MMU
-#include <asm/mmu.h>
-#include <asm/arch/mmu.h>
-#endif
-
-#ifdef CONFIG_FSL_ANDROID
-#include <mxc_keyb.h>
-#include <part.h>
-#include <ext2fs.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <ubi_uboot.h>
-#include <jffs2/load_kernel.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static u32 system_rev;
-static enum boot_device boot_dev;
-u32 mx51_io_base_addr;
-
-static inline void setup_boot_device(void)
-{
- uint *fis_addr = (uint *)IRAM_BASE_ADDR;
-
- switch (*fis_addr) {
- case NAND_FLASH_BOOT:
- boot_dev = NAND_BOOT;
- break;
- case SPI_NOR_FLASH_BOOT:
- boot_dev = SPI_NOR_BOOT;
- break;
- case MMC_FLASH_BOOT:
- boot_dev = MMC_BOOT;
- break;
- default:
- {
- uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
- uint bt_mem_ctl = soc_sbmr & 0x00000003;
- uint bt_mem_type = (soc_sbmr & 0x00000180) >> 7;
-
- switch (bt_mem_ctl) {
- case 0x3:
- if (bt_mem_type == 0)
- boot_dev = MMC_BOOT;
- else if (bt_mem_type == 3)
- boot_dev = SPI_NOR_BOOT;
- else
- boot_dev = UNKNOWN_BOOT;
- break;
- case 0x1:
- boot_dev = NAND_BOOT;
- break;
- default:
- boot_dev = UNKNOWN_BOOT;
- }
- }
- break;
- }
-}
-
-enum boot_device get_boot_device(void)
-{
- return boot_dev;
-}
-
-u32 get_board_rev(void)
-{
- return system_rev;
-}
-
-static inline void setup_soc_rev(void)
-{
- int reg;
-#ifdef CONFIG_ARCH_MMU
- reg = __REG(0x20000000 + ROM_SI_REV); /* Virtual address */
-#else
- reg = __REG(ROM_SI_REV); /* Virtual address */
-#endif
-
- switch (reg) {
- case 0x02:
- system_rev = 0x51000 | CHIP_REV_1_1;
- break;
- case 0x10:
- system_rev = 0x51000 | CHIP_REV_2_0;
- break;
- default:
- system_rev = 0x51000 | CHIP_REV_1_0;
- }
-}
-
-static inline void set_board_rev(int rev)
-{
- system_rev |= (rev & 0xF) << 8;
-}
-
-inline int is_soc_rev(int rev)
-{
- return (system_rev & 0xFF) - rev;
-}
-
-#ifdef CONFIG_ARCH_MMU
-void board_mmu_init(void)
-{
- unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
- unsigned long i;
-
- /*
- * Set the TTB register
- */
- asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_base) /*:*/);
-
- /*
- * Set the Domain Access Control Register
- */
- i = ARM_ACCESS_DACR_DEFAULT;
- asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i) /*:*/);
-
- /*
- * First clear all TT entries - ie Set them to Faulting
- */
- memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
- /* Actual Virtual Size Attributes Function */
- /* Base Base MB cached? buffered? access permissions */
- /* xxx00000 xxx00000 */
- X_ARM_MMU_SECTION(0x000, 0x200, 0x1,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* ROM */
- X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* IRAM */
- X_ARM_MMU_SECTION(0x300, 0x300, 0x100,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* GPU */
- X_ARM_MMU_SECTION(0x400, 0x400, 0x200,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
- X_ARM_MMU_SECTION(0x600, 0x600, 0x300,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* periperals */
- X_ARM_MMU_SECTION(0x900, 0x000, 0x080,
- ARM_CACHEABLE, ARM_BUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* SDRAM */
- X_ARM_MMU_SECTION(0x900, 0x900, 0x080,
- ARM_CACHEABLE, ARM_BUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* SDRAM */
- X_ARM_MMU_SECTION(0x900, 0x980, 0x080,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
- X_ARM_MMU_SECTION(0xA00, 0xA00, 0x100,
- ARM_CACHEABLE, ARM_BUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* SDRAM */
- X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
- X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
-
- /* Workaround for arm errata #709718 */
- /* Setup PRRR so device is always mapped to non-shared */
- asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
- i &= (~(3 << 0x10));
- asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
-
- /* Enable MMU */
- MMU_ON();
-}
-#endif
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-static void setup_uart(void)
-{
- unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
- PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
- mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
- mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
-}
-
-void setup_nfc(void)
-{
- /* Enable NFC IOMUX */
- mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0);
-}
-
-static void setup_expio(void)
-{
- u32 reg;
- /* CS5 setup */
- mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
- writel(0x00410089, WEIM_BASE_ADDR + 0x78 + CSGCR1);
- writel(0x00000002, WEIM_BASE_ADDR + 0x78 + CSGCR2);
- /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
- writel(0x32260000, WEIM_BASE_ADDR + 0x78 + CSRCR1);
- /* APR = 0 */
- writel(0x00000000, WEIM_BASE_ADDR + 0x78 + CSRCR2);
- /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
- * WCSA=0, WCSN=0
- */
- writel(0x72080F00, WEIM_BASE_ADDR + 0x78 + CSWCR1);
- if ((readw(CS5_BASE_ADDR + PBC_ID_AAAA) == 0xAAAA) &&
- (readw(CS5_BASE_ADDR + PBC_ID_5555) == 0x5555)) {
- if (is_soc_rev(CHIP_REV_2_0) < 0) {
- reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
- reg = (reg & (~0x70000)) | 0x30000;
- writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
- /* make sure divider effective */
- while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
- ;
- writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
- }
- mx51_io_base_addr = CS5_BASE_ADDR;
- } else {
- /* CS1 */
- writel(0x00410089, WEIM_BASE_ADDR + 0x18 + CSGCR1);
- writel(0x00000002, WEIM_BASE_ADDR + 0x18 + CSGCR2);
- /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
- writel(0x32260000, WEIM_BASE_ADDR + 0x18 + CSRCR1);
- /* APR=0 */
- writel(0x00000000, WEIM_BASE_ADDR + 0x18 + CSRCR2);
- /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
- * WEN=0, WCSA=0, WCSN=0
- */
- writel(0x72080F00, WEIM_BASE_ADDR + 0x18 + CSWCR1);
- mx51_io_base_addr = CS1_BASE_ADDR;
- }
-
- /* Reset interrupt status reg */
- writew(0x1F, mx51_io_base_addr + PBC_INT_REST);
- writew(0x00, mx51_io_base_addr + PBC_INT_REST);
- writew(0xFFFF, mx51_io_base_addr + PBC_INT_MASK);
-
- /* Reset the XUART and Ethernet controllers */
- reg = readw(mx51_io_base_addr + PBC_SW_RESET);
- reg |= 0x9;
- writew(reg, mx51_io_base_addr + PBC_SW_RESET);
- reg &= ~0x9;
- writew(reg, mx51_io_base_addr + PBC_SW_RESET);
-}
-
-#if defined(CONFIG_MXC_ATA)
-int setup_ata(void)
-{
- u32 pad;
-
- pad = (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH);
-
- /* Need to disable nand iomux first */
- mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, pad);
-
- /* TO 2.0 */
- mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, pad);
-
- /* TO 1.0 */
- mxc_request_iomux(MX51_PIN_NANDF_RB5, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB5, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D0, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D1, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D2, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D3, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D4, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D5, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D6, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D7, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D8, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D9, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D10, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D11, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D12, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D13, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D14, pad);
-
- mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D15, pad);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_I2C_MXC
-static setup_i2c(unsigned int module_base)
-{
- unsigned int reg;
-
- switch (module_base) {
- case I2C1_BASE_ADDR:
- reg = IOMUXC_BASE_ADDR + 0x210; /* i2c SDA */
- writel(0x11, reg);
- reg = IOMUXC_BASE_ADDR + 0x600;
- writel(0x1ad, reg);
- reg = IOMUXC_BASE_ADDR + 0x9B4;
- writel(0x1, reg);
-
- reg = IOMUXC_BASE_ADDR + 0x224; /* i2c SCL */
- writel(0x11, reg);
- reg = IOMUXC_BASE_ADDR + 0x614;
- writel(0x1ad, reg);
- reg = IOMUXC_BASE_ADDR + 0x9B0;
- writel(0x1, reg);
- break;
- case I2C2_BASE_ADDR:
- /* Workaround for Atlas Lite */
- writel(0x0, IOMUXC_BASE_ADDR + 0x3CC); /* i2c SCL */
- writel(0x0, IOMUXC_BASE_ADDR + 0x3D0); /* i2c SDA */
- reg = readl(GPIO1_BASE_ADDR + 0x0);
- reg |= 0xC; /* write a 1 on the SCL and SDA lines */
- writel(reg, GPIO1_BASE_ADDR + 0x0);
- reg = readl(GPIO1_BASE_ADDR + 0x4);
- reg |= 0xC; /* configure GPIO lines as output */
- writel(reg, GPIO1_BASE_ADDR + 0x4);
- reg = readl(GPIO1_BASE_ADDR + 0x0);
- reg &= ~0x4 ; /* set SCL low for a few milliseconds */
- writel(reg, GPIO1_BASE_ADDR + 0x0);
- udelay(20000);
- reg |= 0x4;
- writel(reg, GPIO1_BASE_ADDR + 0x0);
- udelay(10);
- reg = readl(GPIO1_BASE_ADDR + 0x4);
- reg &= ~0xC; /* configure GPIO lines back as input */
- writel(reg, GPIO1_BASE_ADDR + 0x4);
-
- writel(0x12, IOMUXC_BASE_ADDR + 0x3CC); /* i2c SCL */
- writel(0x3, IOMUXC_BASE_ADDR + 0x9B8);
- writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D4);
-
- writel(0x12, IOMUXC_BASE_ADDR + 0x3D0); /* i2c SDA */
- writel(0x3, IOMUXC_BASE_ADDR + 0x9BC);
- writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D8);
- break;
- default:
- printf("Invalid I2C base: 0x%x\n", module_base);
- break;
- }
-}
-
-#define REV_ATLAS_LITE_1_0 0x8
-#define REV_ATLAS_LITE_1_1 0x9
-#define REV_ATLAS_LITE_2_0 0x10
-#define REV_ATLAS_LITE_2_1 0x11
-
-void setup_core_voltages(void)
-{
- unsigned char buf[4] = { 0 };
-
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- if (is_soc_rev(CHIP_REV_2_0) <= 0) {
- /* Set core voltage to 1.1V */
- if (i2c_read(0x8, 24, 1, buf, 3)) {
- puts("setup_core_voltages: read PMIC@0x08:0x18 fail\n");
- return;
- }
- buf[2] = (buf[2] & (~0x1F)) | 0x14;
- if (i2c_write(0x8, 24, 1, buf, 3)) {
- puts("setup_core_voltages: write PMIC@0x08:0x18 fail\n");
- return;
- }
-
- /* Setup VCC (SW2) to 1.25 */
- if (i2c_read(0x8, 25, 1, buf, 3)) {
- puts("setup_core_voltages: read PMIC@0x08:0x19 fail\n");
- return;
- }
- buf[2] = (buf[2] & (~0x1F)) | 0x1A;
- if (i2c_write(0x8, 25, 1, buf, 3)) {
- puts("setup_core_voltages: write PMIC@0x08:0x19 fail\n");
- return;
- }
-
- /* Setup 1V2_DIG1 (SW3) to 1.25 */
- if (i2c_read(0x8, 26, 1, buf, 3)) {
- puts("setup_core_voltages: read PMIC@0x08:0x1A fail\n");
- return;
- }
- buf[2] = (buf[2] & (~0x1F)) | 0x1A;
- if (i2c_write(0x8, 26, 1, buf, 3)) {
- puts("setup_core_voltages: write PMIC@0x08:0x1A fail\n");
- return;
- }
-
- udelay(50);
-
- /* Raise the core frequency to 800MHz */
- writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
- } else {
- /* TO 3.0 */
- /* Setup VCC (SW2) to 1.225 */
- if (i2c_read(0x8, 25, 1, buf, 3)) {
- puts("setup_core_voltages: read PMIC@0x08:0x19 fail\n");
- return;
- }
- buf[2] = (buf[2] & (~0x1F)) | 0x19;
- if (i2c_write(0x8, 25, 1, buf, 3)) {
- puts("setup_core_voltages: write PMIC@0x08:0x19 fail\n");
- return;
- }
-
- /* Setup 1V2_DIG1 (SW3) to 1.2 */
- if (i2c_read(0x8, 26, 1, buf, 3)) {
- puts("setup_core_voltages: read PMIC@0x08:0x1A fail\n");
- return;
- }
- buf[2] = (buf[2] & (~0x1F)) | 0x18;
- if (i2c_write(0x8, 26, 1, buf, 3)) {
- puts("setup_core_voltages: write PMIC@0x08:0x1A fail\n");
- return;
- }
- }
-
- if (i2c_read(0x8, 7, 1, buf, 3)) {
- puts("setup_core_voltages: read PMIC@0x08:0x07 fail\n");
- return;
- }
-
- if (((buf[2] & 0x1F) < REV_ATLAS_LITE_2_0) || (((buf[1] >> 1) & 0x3) == 0)) {
- /* Set switchers in PWM mode for Atlas 2.0 and lower */
- /* Setup the switcher mode for SW1 & SW2*/
- if (i2c_read(0x8, 28, 1, buf, 3)) {
- puts("setup_core_voltages: read PMIC@0x08:0x1C fail\n");
- return;
- }
- buf[2] = (buf[2] & (~0xF)) | 0x5;
- buf[1] = (buf[1] & (~0x3C)) | 0x14;
- if (i2c_write(0x8, 28, 1, buf, 3)) {
- puts("setup_core_voltages: write PMIC@0x08:0x1C fail\n");
- return;
- }
-
- /* Setup the switcher mode for SW3 & SW4*/
- if (i2c_read(0x8, 29, 1, buf, 3)) {
- puts("setup_core_voltages: read PMIC@0x08:0x1D fail\n");
- return;
- }
- buf[2] = (buf[2] & (~0xF)) | 0x5;
- buf[1] = (buf[1] & (~0xF)) | 0x5;
- if (i2c_write(0x8, 29, 1, buf, 3)) {
- puts("setup_core_voltages: write PMIC@0x08:0x1D fail\n");
- return;
- }
- } else {
- /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
- /* Setup the switcher mode for SW1 & SW2*/
- if (i2c_read(0x8, 28, 1, buf, 3)) {
- puts("setup_core_voltages: read PMIC@0x08:0x1C fail\n");
- return;
- }
- buf[2] = (buf[2] & (~0xF)) | 0x8;
- buf[1] = (buf[1] & (~0x3C)) | 0x20;
- if (i2c_write(0x8, 28, 1, buf, 3)) {
- puts("setup_core_voltages: write PMIC@0x08:0x1C fail\n");
- return;
- }
-
- /* Setup the switcher mode for SW3 & SW4*/
- if (i2c_read(0x8, 29, 1, buf, 3)) {
- puts("setup_core_voltages: read PMIC@0x08:0x1D fail\n");
- return;
- }
- buf[2] = (buf[2] & (~0xF)) | 0x8;
- buf[1] = (buf[1] & (~0xF)) | 0x8;
- if (i2c_write(0x8, 29, 1, buf, 3)) {
- puts("setup_core_voltages: write PMIC@0x08:0x1D fail\n");
- return;
- }
- }
-}
-
-#endif
-
-int board_init(void)
-{
- setup_boot_device();
- setup_soc_rev();
-
- gd->bd->bi_arch_number = MACH_TYPE_MX51_3DS; /* board id for linux */
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- setup_uart();
- setup_nfc();
- setup_expio();
-#ifdef CONFIG_I2C_MXC
- setup_i2c(I2C2_BASE_ADDR);
- setup_core_voltages();
-#endif
- return 0;
-}
-
-#ifdef BOARD_LATE_INIT
-
-#if defined(CONFIG_FSL_ANDROID) && defined(CONFIG_MXC_KPD)
-static int waiting_for_func_key_pressing(void)
-{
- struct kpp_key_info key_info = {0, 0};
- int switch_delay = CONFIG_ANDROID_BOOTMOD_DELAY;
- int state = 0, boot_mode_switch = 0;
-
- mxc_kpp_init();
-
- puts("Press home + power to enter recovery mode ...\n");
-
- while ((switch_delay > 0) && (!boot_mode_switch)) {
- int i;
-
- --switch_delay;
- /* delay 100 * 10ms */
- for (i = 0; !boot_mode_switch && i < 100; ++i) {
- /* A state machine to scan home + power key */
- /* Check for home + power */
- if (mxc_kpp_getc(&key_info)) {
- switch (state) {
- case 0:
- /* First press */
- if (TEST_HOME_KEY_DEPRESS(key_info.val, key_info.evt)) {
- /* Press Home */
- state = 1;
- } else if (TEST_POWER_KEY_DEPRESS(key_info.val, key_info.evt)) {
- state = 2;
- } else {
- state = 0;
- }
- break;
- case 1:
- /* Home is already pressed, try to detect Power */
- if (TEST_POWER_KEY_DEPRESS(key_info.val,
- key_info.evt)) {
- boot_mode_switch = 1;
- } else {
- if (TEST_HOME_KEY_DEPRESS(key_info.val,
- key_info.evt))
- state = 2;
- else
- state = 0;
- }
- break;
- case 2:
- /* Power is already pressed, try to detect Home */
- if (TEST_HOME_KEY_DEPRESS(key_info.val,
- key_info.evt)) {
- boot_mode_switch = 1;
- } else {
- if (TEST_POWER_KEY_DEPRESS(key_info.val,
- key_info.evt))
- state = 1;
- else
- state = 0;
- }
- break;
- default:
- break;
- }
-
- if (1 == boot_mode_switch)
- return 1;
- }
- }
- for (i = 0; i < 100; ++i)
- udelay(10000);
- }
-
- return 0;
-}
-
-static int switch_to_recovery_mode(void)
-{
- char *env = NULL;
- char *boot_args = NULL;
- char *boot_cmd = NULL;
-
- printf("Boot mode switched to recovery mode!\n");
-
- switch (get_boot_device()) {
- case MMC_BOOT:
- boot_args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC;
- boot_cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC;
- break;
- case NAND_BOOT:
- boot_args = CONFIG_ANDROID_RECOVERY_BOOTARGS_NAND;
- boot_cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_NAND;
- break;
- case SPI_NOR_BOOT:
- printf("Recovery mode not supported in SPI NOR boot\n");
- return -1;
- break;
- case UNKNOWN_BOOT:
- default:
- printf("Unknown boot device!\n");
- return -1;
- break;
- }
-
- env = getenv("bootargs_android_recovery");
- /* Set env to recovery mode */
- if (!env)
- setenv("bootargs_android", boot_args);
- else
- setenv("bootargs_android", env);
-
- env = getenv("bootcmd_android_recovery");
- if (!env)
- setenv("bootcmd_android", boot_cmd);
- else
- setenv("bootcmd_android", env);
- setenv("bootcmd", "run bootcmd_android");
-
- return 0;
-}
-
-static int check_mmc_recovery_cmd_file(int dev_num, int part_num, char *path)
-{
- block_dev_desc_t *dev_desc = NULL;
- struct mmc *mmc = find_mmc_device(dev_num);
- disk_partition_t info;
- ulong part_length = 0;
- int filelen = 0;
-
- memset(&info, 0, sizeof(disk_partition_t));
-
- dev_desc = get_dev("mmc", dev_num);
-
- if (NULL == dev_desc) {
- printf("** Block device MMC %d not supported\n",
- dev_num);
- return 0;
- }
-
- mmc_init(mmc);
-
- if (get_partition_info(dev_desc,
- part_num,
- &info)) {
- printf("** Bad partition %d **\n",
- part_num);
- return 0;
- }
-
- part_length = ext2fs_set_blk_dev(dev_desc,
- part_num);
- if (part_length == 0) {
- printf("** Bad partition - mmc 0:%d **\n",
- part_num);
- ext2fs_close();
- return 0;
- }
-
- if (!ext2fs_mount(part_length)) {
- printf("** Bad ext2 partition or disk - mmc 0:%d **\n",
- part_num);
- ext2fs_close();
- return 0;
- }
-
- filelen = ext2fs_open(path);
-
- ext2fs_close();
-
- return (filelen > 0) ? 1 : 0;
-}
-
-extern int ubifs_init(void);
-extern int ubifs_mount(char *vol_name);
-extern int ubifs_load(char *filename, u32 addr, u32 size);
-
-static int check_nand_recovery_cmd_file(char *mtd_part_name,
- char *ubi_part_name,
- char *path)
-{
- struct mtd_device *dev_desc = NULL;
- struct part_info *part = NULL;
- struct mtd_partition mtd_part;
- struct mtd_info *mtd_info = NULL;
- char mtd_dev[16] = { 0 };
- char mtd_buffer[80] = { 0 };
- u8 pnum = 0,
- read_test = 0;
- int err = 0,
- filelen = 0;
-
- memset(&mtd_part, 0, sizeof(struct mtd_partition));
-
- /* ========== ubi and mtd operations ========== */
- if (mtdparts_init() != 0) {
- printf("Error initializing mtdparts!\n");
- return 0;
- }
-
- if (find_dev_and_part(mtd_part_name, &dev_desc, &pnum, &part)) {
- printf("Partition %s not found!\n", mtd_part_name);
- return 0;
- }
- sprintf(mtd_dev, "%s%d",
- MTD_DEV_TYPE(dev_desc->id->type),
- dev_desc->id->num);
- mtd_info = get_mtd_device_nm(mtd_dev);
- if (IS_ERR(mtd_info)) {
- printf("Partition %s not found on device %s!\n",
- "nand", mtd_dev);
- return 0;
- }
-
- sprintf(mtd_buffer, "mtd=%d", pnum);
- memset(&mtd_part, 0, sizeof(mtd_part));
- mtd_part.name = mtd_buffer;
- mtd_part.size = part->size;
- mtd_part.offset = part->offset;
- add_mtd_partitions(mtd_info, &mtd_part, 1);
-
- err = ubi_mtd_param_parse(mtd_buffer, NULL);
- if (err) {
- del_mtd_partitions(mtd_info);
- return 0;
- }
-
- err = ubi_init();
- if (err) {
- del_mtd_partitions(mtd_info);
- return 0;
- }
-
- /* ========== ubifs operations ========== */
- /* Init ubifs */
- ubifs_init();
-
- if (ubifs_mount(ubi_part_name)) {
- printf("Mount ubifs volume %s fail!\n",
- ubi_part_name);
- return 0;
- }
-
- /* Try to read one byte for a read test. */
- if (ubifs_load(path, (u32)&read_test, 1)) {
- /* File not found */
- filelen = 0;
- } else
- filelen = 1;
-
- return filelen;
-}
-
-static int check_recovery_cmd_file(void)
-{
- int if_exist = 0;
- char *env = NULL;
-
- switch (get_boot_device()) {
- case MMC_BOOT:
- if_exist = check_mmc_recovery_cmd_file(0,
- CONFIG_ANDROID_CACHE_PARTITION_MMC,
- CONFIG_ANDROID_RECOVERY_CMD_FILE);
- break;
- case NAND_BOOT:
- env = getenv("mtdparts");
- if (!env)
- setenv("mtdparts", MTDPARTS_DEFAULT);
-
- env = getenv("mtdids");
- if (!env)
- setenv("mtdids", MTDIDS_DEFAULT);
-
- env = getenv("partition");
- if (!env)
- setenv("partition", MTD_ACTIVE_PART);
-
- /*
- if_exist = check_nand_recovery_cmd_file(CONFIG_ANDROID_UBIFS_PARTITION_NM,
- CONFIG_ANDROID_CACHE_PARTITION_NAND,
- CONFIG_ANDROID_RECOVERY_CMD_FILE);
- */
- break;
- case SPI_NOR_BOOT:
- return 0;
- break;
- case UNKNOWN_BOOT:
- default:
- return 0;
- break;
- }
-
- return if_exist;
-}
-#endif
-
-int board_late_init(void)
-{
-#if defined(CONFIG_FSL_ANDROID) && defined(CONFIG_MXC_KPD)
- if (waiting_for_func_key_pressing())
- switch_to_recovery_mode();
- else {
- if (check_recovery_cmd_file()) {
- puts("Recovery command file detected!\n");
- switch_to_recovery_mode();
- }
- }
-#endif
-
- return 0;
-}
-#endif
-
-int checkboard(void)
-{
- printf("Board: MX51 3STACK ");
-
- if (system_rev & CHIP_REV_2_0) {
- printf("2.0 [");
- } else if (system_rev & CHIP_REV_1_1) {
- printf("1.1 [");
- } else {
- printf("1.0 [");
- }
-
- switch (__REG(SRC_BASE_ADDR + 0x8)) {
- case 0x0001:
- printf("POR");
- break;
- case 0x0009:
- printf("RST");
- break;
- case 0x0010:
- case 0x0011:
- printf("WDOG");
- break;
- default:
- printf("unknown");
- }
- printf("]\n");
-
- printf("Boot Device: ");
- switch (get_boot_device()) {
- case NAND_BOOT:
- printf("NAND\n");
- break;
- case SPI_NOR_BOOT:
- printf("SPI NOR\n");
- break;
- case MMC_BOOT:
- printf("MMC\n");
- break;
- case UNKNOWN_BOOT:
- default:
- printf("UNKNOWN\n");
- break;
- }
-
- return 0;
-}
-
-#if defined(CONFIG_SMC911X)
-extern int smc911x_initialize(u8 dev_num, int base_addr);
-#endif
-
-#ifdef CONFIG_NET_MULTI
-int board_eth_init(bd_t *bis)
-{
- int rc = -ENODEV;
-#if defined(CONFIG_SMC911X)
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
-
- cpu_eth_init(bis);
-
- return rc;
-}
-#endif
-
-#ifdef CONFIG_CMD_MMC
-
-struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR, 1, 1},
-};
-
-#ifdef CONFIG_DYNAMIC_MMC_DEVNO
-int get_mmc_env_devno()
-{
- uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
- return (soc_sbmr & 0x00180000) ? 1 : 0;
-}
-#endif
-
-int esdhc_gpio_init(bd_t *bis)
-{
- u32 index = 0;
- s32 status = 0;
-
- for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
- ++index) {
- switch (index) {
- case 0:
- mxc_request_iomux(MX51_PIN_SD1_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA0,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA1,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA2,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA3,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- break;
- case 1:
- status = 1;
- break;
- case 2:
- status = 1;
- break;
- case 3:
- status = 1;
- break;
- default:
- status = 1;
- break;
- }
- status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
- }
-
- return status;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- if (!esdhc_gpio_init(bis))
- return fsl_esdhc_mmc_init(gd->bd);
- else
- return -1;
-}
-#endif
-
-#if defined(CONFIG_MXC_KPD)
-int setup_mxc_kpd(void)
-{
- mxc_request_iomux(MX51_PIN_KEY_COL0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_COL1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_COL2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_COL3, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_COL4, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_COL5, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_ROW0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_ROW1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_ROW2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_ROW3, IOMUX_CONFIG_ALT0);
-
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
- board/freescale/mx51_3stack/flash_header.o (.text.flasheader)
- cpu/arm_cortexa8/start.o
- board/freescale/mx51_3stack/libmx51_3stack.a (.text)
- lib_arm/libarm.a (.text)
- net/libnet.a (.text)
- drivers/mtd/libmtd.a (.text)
- drivers/mmc/libmmc.a (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o(.text)
-
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
+++ /dev/null
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2009 Freescale Semiconductor, Inc.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := mx51_bbg.o
-SOBJS := lowlevel_init.o flash_header.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __BOARD_FREESCALE_BOARD_IMX51_H__
-#define __BOARD_FREESCALE_BOARD_IMX51_H__
-
-/*!
- * @defgroup BRDCFG_MX51 Board Configuration Options
- * @ingroup MSL_MX51
- */
-
-/*!
- * @file mx51_3stack/board-imx51.h
- *
- * @brief This file contains all the board level configuration options.
- *
- * It currently hold the options defined for MX51 3Stack Platform.
- *
- * @ingroup BRDCFG_IMX51
- */
-
-/* CPLD offsets */
-#define PBC_LED_CTRL (0x20000)
-#define PBC_SB_STAT (0x20008)
-#define PBC_ID_AAAA (0x20040)
-#define PBC_ID_5555 (0x20048)
-#define PBC_VERSION (0x20050)
-#define PBC_ID_CAFE (0x20058)
-#define PBC_INT_STAT (0x20010)
-#define PBC_INT_MASK (0x20038)
-#define PBC_INT_REST (0x20020)
-#define PBC_SW_RESET (0x20060)
-
-/* LED switchs */
-#define LED_SWITCH_REG 0x00
-/* buttons */
-#define SWITCH_BUTTONS_REG 0x08
-/* status, interrupt */
-#define INTR_STATUS_REG 0x10
-#define INTR_MASK_REG 0x38
-#define INTR_RESET_REG 0x20
-/* magic word for debug CPLD */
-#define MAGIC_NUMBER1_REG 0x40
-#define MAGIC_NUMBER2_REG 0x48
-/* CPLD code version */
-#define CPLD_CODE_VER_REG 0x50
-/* magic word for debug CPLD */
-#define MAGIC_NUMBER3_REG 0x58
-/* module reset register*/
-#define MODULE_RESET_REG 0x60
-/* CPU ID and Personality ID */
-#define MCU_BOARD_ID_REG 0x68
-
-#endif /* __BOARD_FREESCALE_BOARD_IMX51_H__ */
+++ /dev/null
-LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
-
-sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp
-
-ifndef TEXT_BASE
- TEXT_BASE = 0x97800000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx51.h>
-#include "board-imx51.h"
-
-#ifdef CONFIG_FLASH_HEADER
-#ifndef CONFIG_FLASH_HEADER_OFFSET
-# error "Must define the offset of flash header"
-#endif
-#define MXC_DCD_ITEM(i, type, addr, val) \
-dcd_node_##i: \
- .word type ; \
- .word addr ; \
- .word val ; \
-
-.section ".text.flasheader", "x"
- b _start
- .org CONFIG_FLASH_HEADER_OFFSET
-app_code_jump_v: .word _start
-app_code_code_barker: .word CONFIG_FLASH_HEADER_BARKER
-app_code_csf: .word 0
-dcd_ptr_ptr: .word dcd_ptr
-super_root_key: .word 0
-dcd_ptr: .word dcd_array_start
-app_dest_ptr: .word TEXT_BASE
-dcd_array_start:
-magic: .word 0xB17219E9
-dcd_array_size: .word dcd_data_end - dcd_array_start - 8
-/* DCD */
-/* DDR2 IOMUX configuration */
-MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200)
-MXC_DCD_ITEM(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5)
-MXC_DCD_ITEM(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5)
-MXC_DCD_ITEM(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2)
-MXC_DCD_ITEM(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2)
-MXC_DCD_ITEM(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7)
-MXC_DCD_ITEM(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45)
-MXC_DCD_ITEM(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45)
-MXC_DCD_ITEM(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45)
-MXC_DCD_ITEM(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45)
-MXC_DCD_ITEM(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0)
-MXC_DCD_ITEM(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3)
-MXC_DCD_ITEM(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3)
-MXC_DCD_ITEM(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3)
-MXC_DCD_ITEM(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3)
-MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3)
-MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3)
-MXC_DCD_ITEM(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2)
-/* Set drive strength to MAX */
-MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x4)
-MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x4)
-MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x4)
-MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x4)
-/* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
-/* CAS=3, BL=4 */
-MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
-MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
-MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
-MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333584ab)
-MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333584ab)
-/* Init DRAM on CS0 */
-MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
-MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
-MXC_DCD_ITEM(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
-MXC_DCD_ITEM(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019)
-MXC_DCD_ITEM(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
-MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
-MXC_DCD_ITEM(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
-MXC_DCD_ITEM(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
-MXC_DCD_ITEM(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
-MXC_DCD_ITEM(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
-MXC_DCD_ITEM(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019)
-MXC_DCD_ITEM(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
-/* Init DRAM on CS1 */
-MXC_DCD_ITEM(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
-MXC_DCD_ITEM(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
-MXC_DCD_ITEM(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
-MXC_DCD_ITEM(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
-MXC_DCD_ITEM(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
-MXC_DCD_ITEM(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
-MXC_DCD_ITEM(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
-MXC_DCD_ITEM(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
-MXC_DCD_ITEM(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
-MXC_DCD_ITEM(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
-MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d)
-MXC_DCD_ITEM(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
-MXC_DCD_ITEM(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
-MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
-MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
-MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
-MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
-dcd_data_end:
-image_len: .word _end - TEXT_BASE
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx51.h>
-#include "board-imx51.h"
-
-/*
- * return soc version
- * 0x10: TO1
- * 0x20: TO2
- * 0x30: TO3
- */
-.macro check_soc_version ret, tmp
-.endm
-
-/*
- * L2CC Cache setup/invalidation/disable
- */
-.macro init_l2cc
- /* explicitly disable L2 cache */
- mrc 15, 0, r0, c1, c0, 1
- bic r0, r0, #0x2
- mcr 15, 0, r0, c1, c0, 1
-
- /* reconfigure L2 cache aux control reg */
- mov r0, #0xC0 /* tag RAM */
- add r0, r0, #0x4 /* data RAM */
- orr r0, r0, #(1 << 24) /* disable write allocate delay */
- orr r0, r0, #(1 << 23) /* disable write allocate combine */
- orr r0, r0, #(1 << 22) /* disable write allocate */
-
- ldr r1, =0x00000000
- ldr r3, [r1, #ROM_SI_REV]
- cmp r3, #0x10 /* r3 contains the silicon rev */
- orrls r0, r0, #(1 << 25) /* disable write combine for TO 2 and lower revs */
-
- mcr 15, 1, r0, c9, c0, 2
-.endm /* init_l2cc */
-
-/* AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.*/
-.macro init_aips
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- ldr r0, =AIPS1_BASE_ADDR
- ldr r1, =0x77777777
- str r1, [r0, #0x0]
- str r1, [r0, #0x4]
- ldr r0, =AIPS2_BASE_ADDR
- str r1, [r0, #0x0]
- str r1, [r0, #0x4]
- /*
- * Clear the on and off peripheral modules Supervisor Protect bit
- * for SDMA to access them. Did not change the AIPS control registers
- * (offset 0x20) access type
- */
-.endm /* init_aips */
-
-/* MAX (Multi-Layer AHB Crossbar Switch) setup */
-.macro init_max
-.endm /* init_max */
-
-/* M4IF setup */
-.macro init_m4if
- /* VPU and IPU given higher priority (0x4)
- * IPU accesses with ID=0x1 given highest priority (=0xA)
- */
- ldr r0, =M4IF_BASE_ADDR
-
- ldr r1, =0x00000203
- str r1, [r0, #0x40]
-
- ldr r1, =0x0
- str r1, [r0, #0x44]
-
- ldr r1, =0x00120125
- str r1, [r0, #0x9C]
-
- ldr r1, =0x001901A3
- str r1, [r0, #0x48]
-
-/*
- ldr r1, =0x00000a01
- str r1, [r0, #0x48]
- ldr r1, =0x00000404
- str r1, [r0, #0x40]
-*/
-.endm /* init_m4if */
-
-/* To support 133MHz DDR */
-.macro init_drive_strength
-.endm /* init_drive_strength */
-
-/* CPLD on CS5 setup */
-.macro init_debug_board
-.endm /* init_debug_board */
-
-.macro setup_pll pll, freq
- ldr r2, =\pll
- ldr r1, =0x00001232
- str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
- mov r1, #0x2
- str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
-
- str r3, [r2, #PLL_DP_OP]
- str r3, [r2, #PLL_DP_HFS_OP]
-
- str r4, [r2, #PLL_DP_MFD]
- str r4, [r2, #PLL_DP_HFS_MFD]
-
- str r5, [r2, #PLL_DP_MFN]
- str r5, [r2, #PLL_DP_HFS_MFN]
-
- ldr r1, =0x00001232
- str r1, [r2, #PLL_DP_CTL]
-1: ldr r1, [r2, #PLL_DP_CTL]
- ands r1, r1, #0x1
- beq 1b
-.endm
-
-.macro init_clock
- ldr r0, =CCM_BASE_ADDR
-
- /* Gate of clocks to the peripherals first */
- ldr r1, =0x3FFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- ldr r1, =0x0
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
-
- ldr r1, =0x00030000
- str r1, [r0, #CLKCTL_CCGR4]
- ldr r1, =0x00FFF030
- str r1, [r0, #CLKCTL_CCGR5]
- ldr r1, =0x00000300
- str r1, [r0, #CLKCTL_CCGR6]
-
- /* Disable IPU and HSC dividers */
- mov r1, #0x60000
- str r1, [r0, #CLKCTL_CCDR]
-
- /* Make sure to switch the DDR away from PLL 1 */
- ldr r1, =0x19239145
- str r1, [r0, #CLKCTL_CBCDR]
- /* make sure divider effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- /* Switch ARM to step clock */
- mov r1, #0x4
- str r1, [r0, #CLKCTL_CCSR]
- mov r3, #DP_OP_800
- mov r4, #DP_MFD_800
- mov r5, #DP_MFN_800
- setup_pll PLL1_BASE_ADDR
-
- mov r3, #DP_OP_665
- mov r4, #DP_MFD_665
- mov r5, #DP_MFN_665
- setup_pll PLL3_BASE_ADDR
-
- /* Switch peripheral to PLL 3 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x000010C0
- str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, =0x13239145
- str r1, [r0, #CLKCTL_CBCDR]
- mov r3, #DP_OP_665
- mov r4, #DP_MFD_665
- mov r5, #DP_MFN_665
- setup_pll PLL2_BASE_ADDR
-
- /* Switch peripheral to PLL2 */
- ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x19239145
- str r1, [r0, #CLKCTL_CBCDR]
- ldr r1, =0x000020C0
- str r1, [r0, #CLKCTL_CBCMR]
-
- mov r3, #DP_OP_216
- mov r4, #DP_MFD_216
- mov r5, #DP_MFN_216
- setup_pll PLL3_BASE_ADDR
-
-
- /* Set the platform clock dividers */
- ldr r0, =ARM_BASE_ADDR
- ldr r1, =0x00000725
- str r1, [r0, #0x14]
-
- ldr r0, =CCM_BASE_ADDR
- /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
- ldr r1, =0x0
- ldr r3, [r1, #ROM_SI_REV]
- cmp r3, #0x10
- movls r1, #0x1
- movhi r1, #0
- str r1, [r0, #CLKCTL_CACRR]
-
- /* Switch ARM back to PLL 1 */
- mov r1, #0
- str r1, [r0, #CLKCTL_CCSR]
-
- /* setup the rest */
- /* Use lp_apm (24MHz) source for perclk */
- ldr r1, =0x000020C2
- str r1, [r0, #CLKCTL_CBCMR]
- /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
- ldr r1, =0x59E35100
- str r1, [r0, #CLKCTL_CBCDR]
-
- /* Restore the default values in the Gate registers */
- ldr r1, =0xFFFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
- str r1, [r0, #CLKCTL_CCGR4]
- str r1, [r0, #CLKCTL_CCGR5]
- str r1, [r0, #CLKCTL_CCGR6]
-
- /* Use PLL 2 for UART's, get 66.5MHz from it */
- ldr r1, =0xA5A2A020
- str r1, [r0, #CLKCTL_CSCMR1]
- ldr r1, =0x00C30321
- str r1, [r0, #CLKCTL_CSCDR1]
-
- /* make sure divider effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- mov r1, #0x0
- str r1, [r0, #CLKCTL_CCDR]
-
- /* for cko - for ARM div by 8 */
- mov r1, #0x000A0000
- add r1, r1, #0x00000F0
- str r1, [r0, #CLKCTL_CCOSR]
-.endm
-
-.macro setup_wdog
- ldr r0, =WDOG1_BASE_ADDR
- mov r1, #0x30
- strh r1, [r0]
-.endm
-
-.section ".text.init", "x"
-
-.globl lowlevel_init
-lowlevel_init:
- ldr r0, =GPIO1_BASE_ADDR
- ldr r1, [r0, #0x0]
- orr r1, r1, #(1 << 23)
- str r1, [r0, #0x0]
- ldr r1, [r0, #0x4]
- orr r1, r1, #(1 << 23)
- str r1, [r0, #0x4]
-
-#ifdef ENABLE_IMPRECISE_ABORT
- mrs r1, spsr /* save old spsr */
- mrs r0, cpsr /* read out the cpsr */
- bic r0, r0, #0x100 /* clear the A bit */
- msr spsr, r0 /* update spsr */
- add lr, pc, #0x8 /* update lr */
- movs pc, lr /* update cpsr */
- nop
- nop
- nop
- nop
- msr spsr, r1 /* restore old spsr */
-#endif
-
- /* ARM errata ID #468414 */
- mrc 15, 0, r1, c1, c0, 1
- orr r1, r1, #(1 << 5) /* enable L1NEON bit */
- mcr 15, 0, r1, c1, c0, 1
-
- init_l2cc
-
- init_aips
-
- init_max
-
- init_m4if
-
- init_drive_strength
-
- init_clock
-
- init_debug_board
-
- /* return from mxc_nand_load */
- /* r12 saved upper lr*/
- b mxc_nand_load
-
-/* Board level setting value */
-DDR_PERCHARGE_CMD: .word 0x04008008
-DDR_REFRESH_CMD: .word 0x00008010
-DDR_LMR1_W: .word 0x00338018
-DDR_LMR_CMD: .word 0xB2220000
-DDR_TIMING_W: .word 0xB02567A9
-DDR_MISC_W: .word 0x000A0104
+++ /dev/null
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mx51.h>
-#include <asm/arch/mx51_pins.h>
-#include <asm/arch/iomux.h>
-#include <asm/errno.h>
-#include <i2c.h>
-#include <asm/arch/keypad.h>
-#include "board-imx51.h"
-#ifdef CONFIG_IMX_ECSPI
-#include <imx_spi.h>
-#include <asm/arch/imx_spi_pmic.h>
-#endif
-
-#include <asm/errno.h>
-
-#ifdef CONFIG_CMD_MMC
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#endif
-
-#ifdef CONFIG_ARCH_MMU
-#include <asm/mmu.h>
-#include <asm/arch/mmu.h>
-#endif
-
-#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-#include <asm/imx_iim.h>
-#endif
-
-#ifdef CONFIG_FSL_ANDROID
-#include <mxc_keyb.h>
-#include <part.h>
-#include <ext2fs.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <ubi_uboot.h>
-#include <jffs2/load_kernel.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static u32 system_rev;
-static enum boot_device boot_dev;
-u32 mx51_io_base_addr;
-
-static inline void setup_boot_device(void)
-{
- uint *fis_addr = (uint *)IRAM_BASE_ADDR;
-
- switch (*fis_addr) {
- case NAND_FLASH_BOOT:
- boot_dev = NAND_BOOT;
- break;
- case SPI_NOR_FLASH_BOOT:
- boot_dev = SPI_NOR_BOOT;
- break;
- case MMC_FLASH_BOOT:
- boot_dev = MMC_BOOT;
- break;
- default:
- {
- uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
- uint bt_mem_ctl = soc_sbmr & 0x00000003;
- uint bt_mem_type = (soc_sbmr & 0x00000180) >> 7;
-
- switch (bt_mem_ctl) {
- case 0x3:
- if (bt_mem_type == 0)
- boot_dev = MMC_BOOT;
- else if (bt_mem_type == 3)
- boot_dev = SPI_NOR_BOOT;
- else
- boot_dev = UNKNOWN_BOOT;
- break;
- case 0x1:
- boot_dev = NAND_BOOT;
- break;
- default:
- boot_dev = UNKNOWN_BOOT;
- }
- }
- break;
- }
-}
-
-enum boot_device get_boot_device(void)
-{
- return boot_dev;
-}
-
-u32 get_board_rev(void)
-{
- return system_rev;
-}
-
-static inline void setup_soc_rev(void)
-{
- int reg;
-#ifdef CONFIG_ARCH_MMU
- reg = __REG(0x20000000 + ROM_SI_REV); /* Virtual address */
-#else
- reg = __REG(ROM_SI_REV);
-#endif
-
- switch (reg) {
- case 0x02:
- system_rev = 0x51000 | CHIP_REV_1_1;
- break;
- case 0x10:
- system_rev = 0x51000 | CHIP_REV_2_0;
- break;
- case 0x20:
- system_rev = 0x51000 | CHIP_REV_3_0;
- break;
- default:
- system_rev = 0x51000 | CHIP_REV_1_0;
- }
-}
-
-static inline void set_board_rev(void)
-{
- if ((__REG(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
- system_rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
-
-}
-
-inline int is_soc_rev(int rev)
-{
- return (system_rev & 0xFF) - rev;
-}
-
-#ifdef CONFIG_ARCH_MMU
-void board_mmu_init(void)
-{
- unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
- unsigned long i;
-
- /*
- * Set the TTB register
- */
- asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_base) /*:*/);
-
- /*
- * Set the Domain Access Control Register
- */
- i = ARM_ACCESS_DACR_DEFAULT;
- asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i) /*:*/);
-
- /*
- * First clear all TT entries - ie Set them to Faulting
- */
- memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
- /* Actual Virtual Size Attributes Function */
- /* Base Base MB cached? buffered? access permissions */
- /* xxx00000 xxx00000 */
- X_ARM_MMU_SECTION(0x000, 0x200, 0x1,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* ROM */
- X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* IRAM */
- X_ARM_MMU_SECTION(0x300, 0x300, 0x100,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* GPU */
- X_ARM_MMU_SECTION(0x400, 0x400, 0x200,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
- X_ARM_MMU_SECTION(0x600, 0x600, 0x300,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* periperals */
- X_ARM_MMU_SECTION(0x900, 0x000, 0x1FF,
- ARM_CACHEABLE, ARM_BUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* SDRAM */
- X_ARM_MMU_SECTION(0x900, 0x900, 0x200,
- ARM_CACHEABLE, ARM_BUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* SDRAM */
- X_ARM_MMU_SECTION(0x900, 0xE00, 0x200,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
- X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
- X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
-
- /* Workaround for arm errata #709718 */
- /* Setup PRRR so device is always mapped to non-shared */
- asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
- i &= (~(3 << 0x10));
- asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
-
- /* Enable MMU */
- MMU_ON();
-}
-#endif
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-static void setup_uart(void)
-{
- unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
- PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
- mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
- mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
- /* enable GPIO1_9 for CLK0 and GPIO1_8 for CLK02 */
- writel(0x00000004, 0x73fa83e8);
- writel(0x00000004, 0x73fa83ec);
-}
-
-void setup_nfc(void)
-{
- /* Enable NFC IOMUX */
- mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0);
-}
-
-static void setup_expio(void)
-{
- u32 reg;
- /* CS5 setup */
- mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
- writel(0x00410089, WEIM_BASE_ADDR + 0x78 + CSGCR1);
- writel(0x00000002, WEIM_BASE_ADDR + 0x78 + CSGCR2);
- /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
- writel(0x32260000, WEIM_BASE_ADDR + 0x78 + CSRCR1);
- /* APR = 0 */
- writel(0x00000000, WEIM_BASE_ADDR + 0x78 + CSRCR2);
- /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
- * WCSA=0, WCSN=0
- */
- writel(0x72080F00, WEIM_BASE_ADDR + 0x78 + CSWCR1);
- if ((readw(CS5_BASE_ADDR + PBC_ID_AAAA) == 0xAAAA) &&
- (readw(CS5_BASE_ADDR + PBC_ID_5555) == 0x5555)) {
- if (is_soc_rev(CHIP_REV_2_0) < 0) {
- reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
- reg = (reg & (~0x70000)) | 0x30000;
- writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
- /* make sure divider effective */
- while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
- ;
- writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
- }
- mx51_io_base_addr = CS5_BASE_ADDR;
- } else {
- /* CS1 */
- writel(0x00410089, WEIM_BASE_ADDR + 0x18 + CSGCR1);
- writel(0x00000002, WEIM_BASE_ADDR + 0x18 + CSGCR2);
- /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
- writel(0x32260000, WEIM_BASE_ADDR + 0x18 + CSRCR1);
- /* APR=0 */
- writel(0x00000000, WEIM_BASE_ADDR + 0x18 + CSRCR2);
- /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
- * WEN=0, WCSA=0, WCSN=0
- */
- writel(0x72080F00, WEIM_BASE_ADDR + 0x18 + CSWCR1);
- mx51_io_base_addr = CS1_BASE_ADDR;
- }
-
- /* Reset interrupt status reg */
- writew(0x1F, mx51_io_base_addr + PBC_INT_REST);
- writew(0x00, mx51_io_base_addr + PBC_INT_REST);
- writew(0xFFFF, mx51_io_base_addr + PBC_INT_MASK);
-
- /* Reset the XUART and Ethernet controllers */
- reg = readw(mx51_io_base_addr + PBC_SW_RESET);
- reg |= 0x9;
- writew(reg, mx51_io_base_addr + PBC_SW_RESET);
- reg &= ~0x9;
- writew(reg, mx51_io_base_addr + PBC_SW_RESET);
-}
-
-#ifdef CONFIG_IMX_ECSPI
-s32 spi_get_cfg(struct imx_spi_dev_t *dev)
-{
- switch (dev->slave.cs) {
- case 0:
- /* pmic */
- dev->base = CSPI1_BASE_ADDR;
- dev->freq = 2500000;
- dev->ss_pol = IMX_SPI_ACTIVE_HIGH;
- dev->ss = 0;
- dev->fifo_sz = 64 * 4;
- dev->us_delay = 0;
- break;
- case 1:
- /* spi_nor */
- dev->base = CSPI1_BASE_ADDR;
- dev->freq = 2500000;
- dev->ss_pol = IMX_SPI_ACTIVE_LOW;
- dev->ss = 1;
- dev->fifo_sz = 64 * 4;
- dev->us_delay = 0;
- break;
- default:
- printf("Invalid Bus ID! \n");
- break;
- }
-
- return 0;
-}
-
-void spi_io_init(struct imx_spi_dev_t *dev)
-{
- switch (dev->base) {
- case CSPI1_BASE_ADDR:
- /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
- mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
-
- /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
-
- if (dev->ss == 0) {
- /* de-select SS1 of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
- /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
- } else if (dev->ss == 1) {
- /* de-select SS0 of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x85);
- /* 000: Select mux mode: ALT0 mux port: SS1 of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x105);
- }
-
- /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
-
- /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
- break;
- case CSPI2_BASE_ADDR:
- default:
- break;
- }
-}
-#endif
-
-#ifdef CONFIG_MXC_FEC
-
-#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-
-int fec_get_mac_addr(unsigned char *mac)
-{
- u32 *iim1_mac_base =
- (u32 *)(IIM_BASE_ADDR + IIM_BANK_AREA_1_OFFSET +
- CONFIG_IIM_MAC_ADDR_OFFSET);
- int i;
-
- for (i = 0; i < 6; ++i, ++iim1_mac_base)
- mac[i] = (u8)readl(iim1_mac_base);
-
- return 0;
-}
-#endif
-
-static void setup_fec(void)
-{
- /*FEC_MDIO*/
- writel(0x3, IOMUXC_BASE_ADDR + 0x0D4);
- writel(0x1FD, IOMUXC_BASE_ADDR + 0x0468);
- writel(0x0, IOMUXC_BASE_ADDR + 0x0954);
-
- /*FEC_MDC*/
- writel(0x2, IOMUXC_BASE_ADDR + 0x13C);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x0524);
-
- /* FEC RDATA[3] */
- writel(0x3, IOMUXC_BASE_ADDR + 0x0EC);
- writel(0x180, IOMUXC_BASE_ADDR + 0x0480);
- writel(0x0, IOMUXC_BASE_ADDR + 0x0964);
-
- /* FEC RDATA[2] */
- writel(0x3, IOMUXC_BASE_ADDR + 0x0E8);
- writel(0x180, IOMUXC_BASE_ADDR + 0x047C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x0960);
-
- /* FEC RDATA[1] */
- writel(0x3, IOMUXC_BASE_ADDR + 0x0d8);
- writel(0x180, IOMUXC_BASE_ADDR + 0x046C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x095C);
-
- /* FEC RDATA[0] */
- writel(0x2, IOMUXC_BASE_ADDR + 0x016C);
- writel(0x2180, IOMUXC_BASE_ADDR + 0x0554);
- writel(0x0, IOMUXC_BASE_ADDR + 0x0958);
-
- /* FEC TDATA[3] */
- writel(0x2, IOMUXC_BASE_ADDR + 0x148);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x0530);
-
- /* FEC TDATA[2] */
- writel(0x2, IOMUXC_BASE_ADDR + 0x144);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x052C);
-
- /* FEC TDATA[1] */
- writel(0x2, IOMUXC_BASE_ADDR + 0x140);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x0528);
-
- /* FEC TDATA[0] */
- writel(0x2, IOMUXC_BASE_ADDR + 0x0170);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x0558);
-
- /* FEC TX_EN */
- writel(0x1, IOMUXC_BASE_ADDR + 0x014C);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x0534);
-
- /* FEC TX_ER */
- writel(0x2, IOMUXC_BASE_ADDR + 0x0138);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x0520);
-
- /* FEC TX_CLK */
- writel(0x1, IOMUXC_BASE_ADDR + 0x0150);
- writel(0x2180, IOMUXC_BASE_ADDR + 0x0538);
- writel(0x0, IOMUXC_BASE_ADDR + 0x0974);
-
- /* FEC COL */
- writel(0x1, IOMUXC_BASE_ADDR + 0x0124);
- writel(0x2180, IOMUXC_BASE_ADDR + 0x0500);
- writel(0x0, IOMUXC_BASE_ADDR + 0x094c);
-
- /* FEC RX_CLK */
- writel(0x1, IOMUXC_BASE_ADDR + 0x0128);
- writel(0x2180, IOMUXC_BASE_ADDR + 0x0504);
- writel(0x0, IOMUXC_BASE_ADDR + 0x0968);
-
- /* FEC CRS */
- writel(0x3, IOMUXC_BASE_ADDR + 0x0f4);
- writel(0x180, IOMUXC_BASE_ADDR + 0x0488);
- writel(0x0, IOMUXC_BASE_ADDR + 0x0950);
-
- /* FEC RX_ER */
- writel(0x3, IOMUXC_BASE_ADDR + 0x0f0);
- writel(0x180, IOMUXC_BASE_ADDR + 0x0484);
- writel(0x0, IOMUXC_BASE_ADDR + 0x0970);
-
- /* FEC RX_DV */
- writel(0x2, IOMUXC_BASE_ADDR + 0x164);
- writel(0x2180, IOMUXC_BASE_ADDR + 0x054C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x096C);
-}
-#endif
-
-#ifdef CONFIG_I2C_MXC
-static void setup_i2c(unsigned int module_base)
-{
- unsigned int reg;
-
- switch (module_base) {
- case I2C1_BASE_ADDR:
- reg = IOMUXC_BASE_ADDR + 0x5c; /* i2c1 SDA */
- writel(0x14, reg);
- reg = IOMUXC_BASE_ADDR + 0x3f0;
- writel(0x10d, reg);
- reg = IOMUXC_BASE_ADDR + 0x9B4;
- writel(0x0, reg);
-
- reg = IOMUXC_BASE_ADDR + 0x68; /* i2c2 SCL */
- writel(0x14, reg);
- reg = IOMUXC_BASE_ADDR + 0x3fc;
- writel(0x10d, reg);
- reg = IOMUXC_BASE_ADDR + 0x9B0;
- writel(0x0, reg);
- break;
- case I2C2_BASE_ADDR:
- /* dummy here*/
- break;
- default:
- printf("Invalid I2C base: 0x%x\n", module_base);
- break;
- }
-}
-
-static void setup_core_voltage_i2c(void)
-{
- unsigned int reg;
- unsigned char buf[1] = { 0 };
-
- puts("PMIC Mode: linear\n");
-
- writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
- reg = readl(GPIO2_BASE_ADDR + 0x0);
- reg &= ~0x4000; /* Lower reset line */
- writel(reg, GPIO2_BASE_ADDR + 0x0);
-
- reg = readl(GPIO2_BASE_ADDR + 0x4);
- reg |= 0x4000; /* configure GPIO lines as output */
- writel(reg, GPIO2_BASE_ADDR + 0x4);
-
- /* Reset the ethernet controller over GPIO */
- writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
-
- /*Configure LDO4*/
- i2c_read(0x34, 0x12, 1, buf, 1);
- buf[0] = buf[0] | 0x40;
- if (i2c_write(0x34, 0x12, 1, buf, 1)) {
- puts("write to PMIC 0x12 failed!\n");
- return;
- }
- i2c_read(0x34, 0x12, 1, buf, 1);
- printf("PMIC 0x12: 0x%x \n", buf[0]);
-
- i2c_read(0x34, 0x10, 1, buf, 1);
- buf[0] = buf[0] | 0x40;
- if (i2c_write(0x34, 0x10, 1, buf, 1)) {
- puts("write to PMIC 0x10 failed!\n");
- return;
- }
- i2c_read(0x34, 0x10, 1, buf, 1);
- printf("PMIC 0x10: 0x%x \n", buf[0]);
-
- udelay(500);
-
- reg = readl(GPIO2_BASE_ADDR + 0x0);
- reg |= 0x4000;
- writel(reg, GPIO2_BASE_ADDR + 0x0);
-}
-#endif
-
-#ifdef CONFIG_IMX_ECSPI
-static void setup_core_voltage_spi(void)
-{
- struct spi_slave *slave;
- unsigned int val;
- unsigned int reg;
-
- puts("PMIC Mode: SPI\n");
-
-#define REV_ATLAS_LITE_1_0 0x8
-#define REV_ATLAS_LITE_1_1 0x9
-#define REV_ATLAS_LITE_2_0 0x10
-#define REV_ATLAS_LITE_2_1 0x11
-
- slave = spi_pmic_probe();
-
- /* Write needed to Power Gate 2 register */
- val = pmic_reg(slave, 34, 0, 0);
- val &= ~0x10000;
- pmic_reg(slave, 34, val, 1);
-
- /* Write needed to update Charger 0 */
- pmic_reg(slave, 48, 0x0023807F, 1);
-
- /* power up the system first */
- pmic_reg(slave, 34, 0x00200000, 1);
-
- if (is_soc_rev(CHIP_REV_2_0) >= 0) {
- /* Set core voltage to 1.1V */
- val = pmic_reg(slave, 24, 0, 0);
- val = (val & (~0x1F)) | 0x14;
- pmic_reg(slave, 24, val, 1);
-
- /* Setup VCC (SW2) to 1.25 */
- val = pmic_reg(slave, 25, 0, 0);
- val = (val & (~0x1F)) | 0x1A;
- pmic_reg(slave, 25, val, 1);
-
- /* Setup 1V2_DIG1 (SW3) to 1.25 */
- val = pmic_reg(slave, 26, 0, 0);
- val = (val & (~0x1F)) | 0x1A;
- pmic_reg(slave, 26, val, 1);
- udelay(50);
- /* Raise the core frequency to 800MHz */
- writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
- } else {
- /* TO 3.0 */
- /* Setup VCC (SW2) to 1.225 */
- val = pmic_reg(slave, 25, 0, 0);
- val = (val & (~0x1F)) | 0x19;
- pmic_reg(slave, 25, val, 1);
-
- /* Setup 1V2_DIG1 (SW3) to 1.2 */
- val = pmic_reg(slave, 26, 0, 0);
- val = (val & (~0x1F)) | 0x18;
- pmic_reg(slave, 26, val, 1);
- }
-
- if (((pmic_reg(slave, 7, 0, 0) & 0x1F) < REV_ATLAS_LITE_2_0) ||
- (((pmic_reg(slave, 7, 0, 0) >> 9) & 0x3) == 0)) {
- /* Set switchers in PWM mode for Atlas 2.0 and lower */
- /* Setup the switcher mode for SW1 & SW2*/
- val = pmic_reg(slave, 28, 0, 0);
- val = (val & (~0x3C0F)) | 0x1405;
- pmic_reg(slave, 28, val, 1);
-
- /* Setup the switcher mode for SW3 & SW4 */
- val = pmic_reg(slave, 29, 0, 0);
- val = (val & (~0xF0F)) | 0x505;
- pmic_reg(slave, 29, val, 1);
- } else {
- /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
- /* Setup the switcher mode for SW1 & SW2*/
- val = pmic_reg(slave, 28, 0, 0);
- val = (val & (~0x3C0F)) | 0x2008;
- pmic_reg(slave, 28, val, 1);
-
- /* Setup the switcher mode for SW3 & SW4 */
- val = pmic_reg(slave, 29, 0, 0);
- val = (val & (~0xF0F)) | 0x808;
- pmic_reg(slave, 29, val, 1);
- }
-
- /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
- val = pmic_reg(slave, 30, 0, 0);
- val &= ~0x34030;
- val |= 0x10020;
- pmic_reg(slave, 30, val, 1);
-
- /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
- val = pmic_reg(slave, 31, 0, 0);
- val &= ~0x1FC;
- val |= 0x1F4;
- pmic_reg(slave, 31, val, 1);
-
- /* Configure VGEN3 and VCAM regulators to use external PNP */
- val = 0x208;
- pmic_reg(slave, 33, val, 1);
- udelay(200);
-
- reg = readl(GPIO2_BASE_ADDR + 0x0);
- reg &= ~0x4000; /* Lower reset line */
- writel(reg, GPIO2_BASE_ADDR + 0x0);
-
- reg = readl(GPIO2_BASE_ADDR + 0x4);
- reg |= 0x4000; /* configure GPIO lines as output */
- writel(reg, GPIO2_BASE_ADDR + 0x4);
-
- /* Reset the ethernet controller over GPIO */
- writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
-
- /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
- val = 0x49249;
- pmic_reg(slave, 33, val, 1);
-
- udelay(500);
-
- reg = readl(GPIO2_BASE_ADDR + 0x0);
- reg |= 0x4000;
- writel(reg, GPIO2_BASE_ADDR + 0x0);
-
- spi_pmic_free(slave);
-}
-#endif
-
-#ifdef CONFIG_NET_MULTI
-
-int board_eth_init(bd_t *bis)
-{
- int rc = -ENODEV;
-
- return rc;
-}
-#endif
-
-#ifdef CONFIG_CMD_MMC
-
-struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR, 1, 1},
- {MMC_SDHC2_BASE_ADDR, 1, 1},
-};
-
-#ifdef CONFIG_DYNAMIC_MMC_DEVNO
-int get_mmc_env_devno()
-{
- uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
- return (soc_sbmr & 0x00180000) ? 1 : 0;
-}
-#endif
-
-int esdhc_gpio_init(bd_t *bis)
-{
- s32 status = 0;
- u32 index = 0;
-
- for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
- ++index) {
- switch (index) {
- case 0:
- mxc_request_iomux(MX51_PIN_SD1_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA0,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA1,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA2,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA3,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- break;
- case 1:
- mxc_request_iomux(MX51_PIN_SD2_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD2_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-
- mxc_request_iomux(MX51_PIN_SD2_DATA0,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD2_DATA1,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD2_DATA2,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD2_DATA3,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- break;
- default:
- printf("Warning: you configured more ESDHC controller"
- "(%d) as supported by the board(2)\n",
- CONFIG_SYS_FSL_ESDHC_NUM);
- return status;
- break;
- }
- status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
- }
-
- return status;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- if (!esdhc_gpio_init(bis))
- return 0;
- else
- return -1;
-}
-
-#endif
-
-#if defined(CONFIG_MXC_KPD)
-int setup_mxc_kpd(void)
-{
- mxc_request_iomux(MX51_PIN_KEY_COL0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_COL1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_COL2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_COL3, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_COL4, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_COL5, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_ROW0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_ROW1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_ROW2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_KEY_ROW3, IOMUX_CONFIG_ALT0);
-
- return 0;
-}
-#endif
-
-int board_init(void)
-{
-#ifdef CONFIG_MFG
-/* MFG firmware need reset usb to avoid host crash firstly */
-#define USBCMD 0x140
- int val = readl(OTG_BASE_ADDR + USBCMD);
- val &= ~0x1; /*RS bit*/
- writel(val, OTG_BASE_ADDR + USBCMD);
-#endif
- setup_boot_device();
- setup_soc_rev();
- set_board_rev();
-
- gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE; /* board id for linux */
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- setup_uart();
- setup_nfc();
- setup_expio();
-#ifdef CONFIG_MXC_FEC
- setup_fec();
-#endif
-#ifdef CONFIG_I2C_MXC
- setup_i2c(I2C1_BASE_ADDR);
-#endif
-
- return 0;
-}
-
-#ifdef BOARD_LATE_INIT
-#if defined(CONFIG_FSL_ANDROID) && defined(CONFIG_MXC_KPD)
-inline int waiting_for_func_key_pressing(void)
-{
- struct kpp_key_info key_info = {0, 0};
- int switch_delay = CONFIG_ANDROID_BOOTMOD_DELAY;
- int state = 0, boot_mode_switch = 0;
-
- mxc_kpp_init();
-
- puts("Press home + power to enter recovery mode ...\n");
-
- while ((switch_delay > 0) && (!boot_mode_switch)) {
- int i;
-
- --switch_delay;
- /* delay 100 * 10ms */
- for (i = 0; !boot_mode_switch && i < 100; ++i) {
- /* A state machine to scan home + power key */
- /* Check for home + power */
- if (mxc_kpp_getc(&key_info)) {
- switch (state) {
- case 0:
- /* First press */
- if (TEST_HOME_KEY_DEPRESS(key_info.val, key_info.evt)) {
- /* Press Home */
- state = 1;
- } else if (TEST_POWER_KEY_DEPRESS(key_info.val, key_info.evt)) {
- /* Press Power */
- state = 2;
- } else {
- state = 0;
- }
- break;
- case 1:
- /* Home is already pressed, try to detect Power */
- if (TEST_POWER_KEY_DEPRESS(key_info.val,
- key_info.evt)) {
- /* Switch */
- boot_mode_switch = 1;
- } else {
- if (TEST_HOME_KEY_DEPRESS(key_info.val,
- key_info.evt)) {
- /* Not switch */
- state = 2;
- } else
- state = 0;
- }
- break;
- case 2:
- /* Power is already pressed, try to detect Home */
- if (TEST_HOME_KEY_DEPRESS(key_info.val,
- key_info.evt)) {
- /* Switch */
- boot_mode_switch = 1;
- } else {
- if (TEST_POWER_KEY_DEPRESS(key_info.val,
- key_info.evt)) {
- /* Not switch */
- state = 1;
- } else
- state = 0;
- }
- break;
- default:
- break;
- }
-
- if (1 == boot_mode_switch)
- return 1;
- }
- }
- for (i = 0; i < 100; ++i)
- udelay(10000);
- }
-
- return 0;
-}
-
-inline int switch_to_recovery_mode(void)
-{
- char *env = NULL;
- char *boot_args = NULL;
- char *boot_cmd = NULL;
-
- printf("Boot mode switched to recovery mode!\n");
-
- switch (get_boot_device()) {
- case MMC_BOOT:
- boot_args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC;
- boot_cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC;
- break;
- case NAND_BOOT:
- printf("Recovery mode not supported in NAND boot\n");
- return -1;
- break;
- case SPI_NOR_BOOT:
- printf("Recovery mode not supported in SPI NOR boot\n");
- return -1;
- break;
- case UNKNOWN_BOOT:
- default:
- printf("Unknown boot device!\n");
- return -1;
- break;
- }
-
- env = getenv("bootargs_android_recovery");
- /* Set env to recovery mode */
- if (!env)
- setenv("bootargs_android", boot_args);
- else
- setenv("bootargs_android", env);
-
- env = getenv("bootcmd_android_recovery");
- if (!env)
- setenv("bootcmd_android", boot_cmd);
- else
- setenv("bootcmd_android", env);
- setenv("bootcmd", "run bootcmd_android");
-
- return 0;
-}
-
-inline int check_recovery_cmd_file(void)
-{
- disk_partition_t info;
- ulong part_length;
- int filelen;
-
- switch (get_boot_device()) {
- case MMC_BOOT:
- {
- block_dev_desc_t *dev_desc = NULL;
- struct mmc *mmc = find_mmc_device(0);
-
- dev_desc = get_dev("mmc", 0);
-
- if (NULL == dev_desc) {
- puts("** Block device MMC 0 not supported\n");
- return 0;
- }
-
- mmc_init(mmc);
-
- if (get_partition_info(dev_desc,
- CONFIG_ANDROID_CACHE_PARTITION_MMC,
- &info)) {
- printf("** Bad partition %d **\n",
- CONFIG_ANDROID_CACHE_PARTITION_MMC);
- return 0;
- }
-
- part_length = ext2fs_set_blk_dev(dev_desc,
- CONFIG_ANDROID_CACHE_PARTITION_MMC);
- if (part_length == 0) {
- printf("** Bad partition - mmc 0:%d **\n",
- CONFIG_ANDROID_CACHE_PARTITION_MMC);
- ext2fs_close();
- return 0;
- }
-
- if (!ext2fs_mount(part_length)) {
- printf("** Bad ext2 partition or disk - mmc 0:%d **\n",
- CONFIG_ANDROID_CACHE_PARTITION_MMC);
- ext2fs_close();
- return 0;
- }
-
- filelen = ext2fs_open(CONFIG_ANDROID_RECOVERY_CMD_FILE);
-
- ext2fs_close();
- }
- break;
- case NAND_BOOT:
- return 0;
- break;
- case SPI_NOR_BOOT:
- return 0;
- break;
- case UNKNOWN_BOOT:
- default:
- return 0;
- break;
- }
-
- return (filelen > 0) ? 1 : 0;
-
-}
-#endif
-
-int board_late_init(void)
-{
-#ifdef CONFIG_I2C_MXC
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- if (!i2c_probe(0x34))
- setup_core_voltage_i2c();
- else
-#endif
-#ifdef CONFIG_IMX_ECSPI
- setup_core_voltage_spi();
-#endif
-
-#if defined(CONFIG_FSL_ANDROID) && defined(CONFIG_MXC_KPD)
- if (waiting_for_func_key_pressing())
- switch_to_recovery_mode();
- else {
- if (check_recovery_cmd_file()) {
- puts("Recovery command file founded!\n");
- switch_to_recovery_mode();
- }
- }
-#endif
-
- return 0;
-}
-#endif
-
-int checkboard(void)
-{
- printf("Board: MX51 BABBAGE ");
-
- if (is_soc_rev(CHIP_REV_3_0) == 0) {
- printf("3.0 [");
- } else if ((is_soc_rev(CHIP_REV_2_0) == 0)
- && (system_rev & (BOARD_REV_2_0 << BOARD_VER_OFFSET))) {
- printf("2.5 [");
- } else if (is_soc_rev(CHIP_REV_2_0) == 0) {
- printf("2.0 [");
- } else if (is_soc_rev(CHIP_REV_1_1) == 0) {
- printf("1.1 [");
- } else {
- printf("1.0 [");
- }
-
- switch (__REG(SRC_BASE_ADDR + 0x8)) {
- case 0x0001:
- printf("POR");
- break;
- case 0x0009:
- printf("RST");
- break;
- case 0x0010:
- case 0x0011:
- printf("WDOG");
- break;
- default:
- printf("unknown");
- }
- printf("]\n");
-
- printf("Boot Device: ");
- switch (get_boot_device()) {
- case NAND_BOOT:
- printf("NAND\n");
- break;
- case SPI_NOR_BOOT:
- printf("SPI NOR\n");
- break;
- case MMC_BOOT:
- printf("MMC\n");
- break;
- case UNKNOWN_BOOT:
- default:
- printf("UNKNOWN\n");
- break;
- }
- return 0;
-}
-
+++ /dev/null
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
- board/freescale/mx51_bbg/flash_header.o (.text.flasheader)
- cpu/arm_cortexa8/start.o
- board/freescale/mx51_bbg/libmx51_bbg.a (.text)
- lib_arm/libarm.a (.text)
- net/libnet.a (.text)
- drivers/mtd/libmtd.a (.text)
- drivers/mmc/libmmc.a (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o(.text)
-
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
+++ /dev/null
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2010 Freescale Semiconductor, Inc.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := mx53_evk.o
-SOBJS := lowlevel_init.o flash_header.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
-
-TEXT_BASE = 0x77800000
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx53.h>
-
-#ifdef CONFIG_FLASH_HEADER
-#ifndef CONFIG_FLASH_HEADER_OFFSET
-# error "Must define the offset of flash header"
-#endif
-
-#define CPU_2_BE_32(l) \
- ((((l) & 0x000000FF) << 24) | \
- (((l) & 0x0000FF00) << 8) | \
- (((l) & 0x00FF0000) >> 8) | \
- (((l) & 0xFF000000) >> 24))
-
-#define MXC_DCD_ITEM(i, addr, val) \
-dcd_node_##i: \
- .word CPU_2_BE_32(addr) ; \
- .word CPU_2_BE_32(val) ; \
-
-.section ".text.flasheader", "x"
- b _start
- .org CONFIG_FLASH_HEADER_OFFSET
-ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
-app_code_jump_v: .word _start
-reserv1: .word 0x0
-dcd_ptr: .word dcd_hdr
-boot_data_ptr: .word boot_data
-self_ptr: .word ivt_header
-app_code_csf: .word 0x0
-reserv2: .word 0x0
-
-boot_data: .word 0x77800000
-image_len: .word _end - TEXT_BASE
-plugin: .word 0x0
-
-#if defined(CONFIG_MX53_EVK)
-dcd_hdr: .word 0x400802D2 /* Tag=0xD2, Len=64*8 + 4 + 4, Ver=0x40 */
-write_dcd_cmd: .word 0x040402CC /* Tag=0xCC, Len=64*8 + 4, Param=4 */
-
-/* DCD */
-MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00380000)
-MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x558, 0x00380040)
-MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x560, 0x00380000)
-MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x564, 0x00380040)
-MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x568, 0x00380040)
-MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x570, 0x00200000)
-MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x574, 0x00380000)
-MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x578, 0x00200000)
-MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x57c, 0x00380040)
-MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x580, 0x00380040)
-MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x584, 0x00380000)
-MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x588, 0x00380000)
-MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x590, 0x00380040)
-MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x594, 0x00380000)
-MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x6f0, 0x00380000)
-MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x6f4, 0x00000200)
-MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000)
-MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x714, 0x00000000)
-MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x718, 0x00380000)
-MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x71c, 0x00380000)
-MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x720, 0x00380000)
-MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x724, 0x06000000)
-MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x728, 0x00380000)
-MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x72c, 0x00380000)
-MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x088, 0x2b2f3031)
-MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x090, 0x40363333)
-MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0x098, 0x00000f00)
-MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x0f8, 0x00000800)
-MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x07c, 0x01310132)
-MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x080, 0x0133014b)
-MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x018, 0x000016d0)
-MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x000, 0xc4110000)
-MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x00c, 0x4d5122d2)
-MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x010, 0x92d18a22)
-MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x014, 0x00c70092)
-MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x02c, 0x000026d2)
-MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x030, 0x009f000e)
-MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x008, 0x12272000)
-MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x004, 0x00030012)
-MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x01c, 0x04008010)
-MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x01c, 0x00008032)
-MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x01c, 0x00008033)
-MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x01c, 0x00008031)
-MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x01c, 0x0b5280b0)
-MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x01c, 0x04008010)
-MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x01c, 0x00008020)
-MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x01c, 0x00008020)
-MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x01c, 0x0a528030)
-MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x01c, 0x03c68031)
-MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x01c, 0x00468031)
-MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x01c, 0x04008018)
-MXC_DCD_ITEM(52, ESDCTL_BASE_ADDR + 0x01c, 0x0000803a)
-MXC_DCD_ITEM(53, ESDCTL_BASE_ADDR + 0x01c, 0x0000803b)
-MXC_DCD_ITEM(54, ESDCTL_BASE_ADDR + 0x01c, 0x00008039)
-MXC_DCD_ITEM(55, ESDCTL_BASE_ADDR + 0x01c, 0x0b528138)
-MXC_DCD_ITEM(56, ESDCTL_BASE_ADDR + 0x01c, 0x04008018)
-MXC_DCD_ITEM(57, ESDCTL_BASE_ADDR + 0x01c, 0x00008028)
-MXC_DCD_ITEM(58, ESDCTL_BASE_ADDR + 0x01c, 0x00008028)
-MXC_DCD_ITEM(59, ESDCTL_BASE_ADDR + 0x01c, 0x0a528038)
-MXC_DCD_ITEM(60, ESDCTL_BASE_ADDR + 0x01c, 0x03c68039)
-MXC_DCD_ITEM(61, ESDCTL_BASE_ADDR + 0x01c, 0x00468039)
-MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x020, 0x00005800)
-MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x058, 0x00033337)
-MXC_DCD_ITEM(64, ESDCTL_BASE_ADDR + 0x01c, 0x00000000)
-
-#elif defined(CONFIG_MX53_ARM2) /*ARM2 board*/
-dcd_hdr: .word 0x400002D2 /* Tag=0xD2, Len=63*8 + 4 + 4, Ver=0x40 */
-write_dcd_cmd: .word 0x04FC01CC /* Tag=0xCC, Len=63*8 + 4, Param=4 */
-
-/* DCD */
-MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00380000)
-MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x558, 0x00380040)
-MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x560, 0x00380000)
-MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x564, 0x00380040)
-MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x568, 0x00380040)
-MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x570, 0x00380000)
-MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x574, 0x00380000)
-MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x578, 0x00380000)
-MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x57c, 0x00380040)
-MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x580, 0x00380040)
-MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x584, 0x00380000)
-MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x588, 0x00380000)
-MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x590, 0x00380040)
-MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x594, 0x00380000)
-MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x6f0, 0x00380000)
-MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x6f4, 0x00000200)
-MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000)
-MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x714, 0x00000000)
-MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x718, 0x00380000)
-MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x71c, 0x00380000)
-MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x720, 0x00380000)
-MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x724, 0x02000000)
-MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x728, 0x00380000)
-MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x72c, 0x00380000)
-MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x088, 0x2d313331)
-MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x090, 0x40363333)
-MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0x0f8, 0x00000800)
-MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x07c, 0x020c0211)
-MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x080, 0x014c0155)
-MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x018, 0x00001710)
-MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x000, 0xc4110000)
-MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x00c, 0x4d5122d2)
-MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x010, 0x92d18a22)
-MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x014, 0x00c70092)
-MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x02c, 0x000026d2)
-MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x030, 0x009f000e)
-MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x008, 0x12272000)
-MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x004, 0x00030012)
-MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x01c, 0x04008010)
-MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x01c, 0x00008032)
-MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x01c, 0x00008033)
-MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x01c, 0x00008031)
-MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x01c, 0x0b5280b0)
-MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x01c, 0x04008010)
-MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x01c, 0x00008020)
-MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x01c, 0x00008020)
-MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x01c, 0x0a528030)
-MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x01c, 0x03c68031)
-MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x01c, 0x00468031)
-MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x01c, 0x04008018)
-MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x01c, 0x0000803a)
-MXC_DCD_ITEM(52, ESDCTL_BASE_ADDR + 0x01c, 0x0000803b)
-MXC_DCD_ITEM(53, ESDCTL_BASE_ADDR + 0x01c, 0x00008039)
-MXC_DCD_ITEM(54, ESDCTL_BASE_ADDR + 0x01c, 0x0b528138)
-MXC_DCD_ITEM(55, ESDCTL_BASE_ADDR + 0x01c, 0x04008018)
-MXC_DCD_ITEM(56, ESDCTL_BASE_ADDR + 0x01c, 0x00008028)
-MXC_DCD_ITEM(57, ESDCTL_BASE_ADDR + 0x01c, 0x00008028)
-MXC_DCD_ITEM(58, ESDCTL_BASE_ADDR + 0x01c, 0x0a528038)
-MXC_DCD_ITEM(59, ESDCTL_BASE_ADDR + 0x01c, 0x03c68039)
-MXC_DCD_ITEM(60, ESDCTL_BASE_ADDR + 0x01c, 0x00468039)
-MXC_DCD_ITEM(61, ESDCTL_BASE_ADDR + 0x020, 0x00005800)
-MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x058, 0x00033337)
-MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x01c, 0x00000000)
-#elif defined(CONFIG_MX53_ARM2_DDR3)
-dcd_hdr: .word 0x40A001D2 /* Tag=0xD2, Len=51*8 + 4 + 4, Ver=0x40 */
-write_dcd_cmd: .word 0x049C01CC /* Tag=0xCC, Len=51*8 + 4, Param=4 */
-
-/* DCD */
-MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00300000)
-MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x558, 0x00300040)
-MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x560, 0x00300000)
-MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x564, 0x00300040)
-MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x568, 0x00300040)
-MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x570, 0x00300000)
-MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x574, 0x00300000)
-MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x578, 0x00300000)
-MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x57c, 0x00300040)
-MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x580, 0x00300040)
-MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x584, 0x00300000)
-MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x588, 0x00300000)
-MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x590, 0x00300040)
-MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x594, 0x00300000)
-MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x6f0, 0x00300000)
-MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x6f4, 0x00000000)
-MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000)
-MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x714, 0x00000000)
-MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x718, 0x00300000)
-MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x71c, 0x00300000)
-MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x720, 0x00300000)
-MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x724, 0x04000000)
-MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x728, 0x00300000)
-MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x72c, 0x00300000)
-MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x088, 0x32383535)
-MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x090, 0x40383538)
-MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0x07c, 0x0136014d)
-MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x080, 0x01510141)
-MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x018, 0x00091740)
-MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x000, 0xc4190000)
-MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x00c, 0x565a7543)
-MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x010, 0xb6ae8aa3)
-MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x014, 0x01ff00db)
-MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x02c, 0x000026d2)
-MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x030, 0x009f0e21)
-MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x008, 0x12272000)
-MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x004, 0x00030012)
-MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x01c, 0x00008032)
-MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x01c, 0x00008033)
-MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x01c, 0x00028031)
-MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x01c, 0x092080b0)
-MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x01c, 0x04008040)
-MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x01c, 0x0000803a)
-MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x01c, 0x0000803b)
-MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x01c, 0x00028039)
-MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x01c, 0x09208138)
-MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x01c, 0x04008048)
-MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x020, 0x00001800)
-MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x040, 0x04b80003)
-MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x058, 0x00022227)
-MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x01c, 0x00000000)
-#endif
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx53.h>
-
-/*
- * L2CC Cache setup/invalidation/disable
- */
-.macro init_l2cc
- /* explicitly disable L2 cache */
- mrc 15, 0, r0, c1, c0, 1
- bic r0, r0, #0x2
- mcr 15, 0, r0, c1, c0, 1
-
- /* reconfigure L2 cache aux control reg */
- mov r0, #0xC0 /* tag RAM */
- add r0, r0, #0x4 /* data RAM */
- orr r0, r0, #(1 << 24) /* disable write allocate delay */
- orr r0, r0, #(1 << 23) /* disable write allocate combine */
- orr r0, r0, #(1 << 22) /* disable write allocate */
-
- mcr 15, 1, r0, c9, c0, 2
-.endm /* init_l2cc */
-
-/* AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.*/
-.macro init_aips
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- ldr r0, =AIPS1_BASE_ADDR
- ldr r1, =0x77777777
- str r1, [r0, #0x0]
- str r1, [r0, #0x4]
- ldr r0, =AIPS2_BASE_ADDR
- str r1, [r0, #0x0]
- str r1, [r0, #0x4]
-.endm /* init_aips */
-
-.macro setup_pll pll, freq
- ldr r0, =\pll
- ldr r1, =0x00001232
- str r1, [r0, #PLL_DP_CTL]
- mov r1, #0x2
- str r1, [r0, #PLL_DP_CONFIG]
-
- ldr r1, W_DP_OP_\freq
- str r1, [r0, #PLL_DP_OP]
- str r1, [r0, #PLL_DP_HFS_OP]
-
- ldr r1, W_DP_MFD_\freq
- str r1, [r0, #PLL_DP_MFD]
- str r1, [r0, #PLL_DP_HFS_MFD]
-
- ldr r1, W_DP_MFN_\freq
- str r1, [r0, #PLL_DP_MFN]
- str r1, [r0, #PLL_DP_HFS_MFN]
-
- ldr r1, =0x00001232
- str r1, [r0, #PLL_DP_CTL]
-1: ldr r1, [r0, #PLL_DP_CTL]
- ands r1, r1, #0x1
- beq 1b
-.endm
-
-.macro init_clock
- ldr r0, CCM_BASE_ADDR_W
-
- /* Switch ARM to step clock */
- mov r1, #0x4
- str r1, [r0, #CLKCTL_CCSR]
-
- setup_pll PLL1_BASE_ADDR, 800
-
- setup_pll PLL3_BASE_ADDR, 400
-
- /* Switch peripheral to PLL3 */
- ldr r0, CCM_BASE_ADDR_W
- ldr r1, CCM_VAL_0x00015154
- str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, CCM_VAL_0x02888945
- orr r1, r1, #(1 << 16)
- str r1, [r0, #CLKCTL_CBCDR]
- /* make sure change is effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ
-
- /* Switch peripheral to PLL2 */
- ldr r0, CCM_BASE_ADDR_W
- ldr r1, CCM_VAL_0x00808145
- orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10)
- orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16)
- orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19)
- str r1, [r0, #CLKCTL_CBCDR]
-
- ldr r1, CCM_VAL_0x00016154
- str r1, [r0, #CLKCTL_CBCMR]
-
- /* make sure change is effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
-
- setup_pll PLL3_BASE_ADDR, 216
-
- /* Set the platform clock dividers */
- ldr r0, PLATFORM_BASE_ADDR_W
- ldr r1, PLATFORM_CLOCK_DIV_W
- str r1, [r0, #PLATFORM_ICGC]
-
- ldr r0, CCM_BASE_ADDR_W
- mov r1, #1
- str r1, [r0, #CLKCTL_CACRR]
-
- /* Switch ARM back to PLL 1. */
- mov r1, #0x0
- str r1, [r0, #CLKCTL_CCSR]
-
- ldr r1, [r0, #CLKCTL_CSCDR1]
- orr r1, r1, #0x3f
- eor r1, r1, #0x3f
- orr r1, r1, #0x21
- str r1, [r0, #CLKCTL_CSCDR1]
-
- /* Restore the default values in the Gate registers */
- ldr r1, =0xFFFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
- str r1, [r0, #CLKCTL_CCGR4]
- str r1, [r0, #CLKCTL_CCGR5]
- str r1, [r0, #CLKCTL_CCGR6]
- str r1, [r0, #CLKCTL_CCGR7]
-
- mov r1, #0x00000
- str r1, [r0, #CLKCTL_CCDR]
-
- /* for cko - for ARM div by 8 */
- mov r1, #0x000A0000
- add r1, r1, #0x00000F0
- str r1, [r0, #CLKCTL_CCOSR]
-.endm
-
-.section ".text.init", "x"
-
-.globl lowlevel_init
-lowlevel_init:
-
-#ifdef ENABLE_IMPRECISE_ABORT
- mrs r1, spsr /* save old spsr */
- mrs r0, cpsr /* read out the cpsr */
- bic r0, r0, #0x100 /* clear the A bit */
- msr spsr, r0 /* update spsr */
- add lr, pc, #0x8 /* update lr */
- movs pc, lr /* update cpsr */
- nop
- nop
- nop
- nop
- msr spsr, r1 /* restore old spsr */
-#endif
-
- /* ARM errata ID #468414 */
- mrc 15, 0, r1, c1, c0, 1
- orr r1, r1, #(1 << 5) /* enable L1NEON bit */
- mcr 15, 0, r1, c1, c0, 1
-
- init_l2cc
-
- init_aips
-
- init_clock
-
- mov pc, lr
-
-/* Board level setting value */
-CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
-CCM_VAL_0x00016154: .word 0x00016154
-CCM_VAL_0x00808145: .word 0x00808145
-CCM_VAL_0x00015154: .word 0x00015154
-CCM_VAL_0x02888945: .word 0x02888945
-W_DP_OP_800: .word DP_OP_800
-W_DP_MFD_800: .word DP_MFD_800
-W_DP_MFN_800: .word DP_MFN_800
-W_DP_OP_600: .word DP_OP_600
-W_DP_MFD_600: .word DP_MFD_600
-W_DP_MFN_600: .word DP_MFN_600
-W_DP_OP_400: .word DP_OP_400
-W_DP_MFD_400: .word DP_MFD_400
-W_DP_MFN_400: .word DP_MFN_400
-W_DP_OP_216: .word DP_OP_216
-W_DP_MFD_216: .word DP_MFD_216
-W_DP_MFN_216: .word DP_MFN_216
-PLATFORM_BASE_ADDR_W: .word ARM_BASE_ADDR
-PLATFORM_CLOCK_DIV_W: .word 0x00000124
+++ /dev/null
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mx53.h>
-#include <asm/arch/mx53_pins.h>
-#include <asm/arch/iomux.h>
-#include <asm/errno.h>
-#include <imx_spi.h>
-
-#if CONFIG_I2C_MXC
-#include <i2c.h>
-#endif
-
-#ifdef CONFIG_CMD_MMC
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#endif
-
-#ifdef CONFIG_ARCH_MMU
-#include <asm/mmu.h>
-#include <asm/arch/mmu.h>
-#endif
-
-#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-#include <asm/imx_iim.h>
-#endif
-
-#ifdef CONFIG_CMD_CLOCK
-#include <asm/clock.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static u32 system_rev;
-static enum boot_device boot_dev;
-
-static inline void setup_boot_device(void)
-{
- uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
- uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
- uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
-
- switch (bt_mem_ctl) {
- case 0x0:
- if (bt_mem_type)
- boot_dev = ONE_NAND_BOOT;
- else
- boot_dev = WEIM_NOR_BOOT;
- break;
- case 0x2:
- if (bt_mem_type)
- boot_dev = SATA_BOOT;
- else
- boot_dev = PATA_BOOT;
- break;
- case 0x3:
- if (bt_mem_type)
- boot_dev = SPI_NOR_BOOT;
- else
- boot_dev = I2C_BOOT;
- break;
- case 0x4:
- case 0x5:
- boot_dev = SD_BOOT;
- break;
- case 0x6:
- case 0x7:
- boot_dev = MMC_BOOT;
- break;
- case 0x8 ... 0xf:
- boot_dev = NAND_BOOT;
- break;
- default:
- boot_dev = UNKNOWN_BOOT;
- break;
- }
-}
-
-enum boot_device get_boot_device(void)
-{
- return boot_dev;
-}
-
-u32 get_board_rev(void)
-{
- return system_rev;
-}
-
-static inline void setup_soc_rev(void)
-{
- system_rev = 0x53000 | CHIP_REV_1_0;
-}
-
-static inline void setup_board_rev(int rev)
-{
- system_rev |= (rev & 0xF) << 8;
-}
-
-inline int is_soc_rev(int rev)
-{
- return (system_rev & 0xFF) - rev;
-}
-
-#ifdef CONFIG_ARCH_MMU
-void board_mmu_init(void)
-{
- unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
- unsigned long i;
-
- /*
- * Set the TTB register
- */
- asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
-
- /*
- * Set the Domain Access Control Register
- */
- i = ARM_ACCESS_DACR_DEFAULT;
- asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
-
- /*
- * First clear all TT entries - ie Set them to Faulting
- */
- memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
- /* Actual Virtual Size Attributes Function */
- /* Base Base MB cached? buffered? access permissions */
- /* xxx00000 xxx00000 */
- X_ARM_MMU_SECTION(0x000, 0x000, 0x10,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* ROM, 16M */
- X_ARM_MMU_SECTION(0x070, 0x070, 0x010,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* IRAM */
- X_ARM_MMU_SECTION(0x100, 0x100, 0x040,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* SATA */
- X_ARM_MMU_SECTION(0x180, 0x180, 0x100,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* IPUv3M */
- X_ARM_MMU_SECTION(0x200, 0x200, 0x200,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* GPU */
- X_ARM_MMU_SECTION(0x400, 0x400, 0x300,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* periperals */
- X_ARM_MMU_SECTION(0x700, 0x700, 0x400,
- ARM_CACHEABLE, ARM_BUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */
- X_ARM_MMU_SECTION(0x700, 0xB00, 0x400,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* CSD0 1G */
- X_ARM_MMU_SECTION(0xF00, 0xF00, 0x100,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
- X_ARM_MMU_SECTION(0xF7F, 0xF7F, 0x040,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* NAND Flash buffer */
- X_ARM_MMU_SECTION(0xF80, 0xF80, 0x001,
- ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
- ARM_ACCESS_PERM_RW_RW); /* iRam */
-
- /* Workaround for arm errata #709718 */
- /* Setup PRRR so device is always mapped to non-shared */
- asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
- i &= (~(3 << 0x10));
- asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
-
- /* Enable MMU */
- MMU_ON();
-}
-#endif
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-static void setup_uart(void)
-{
-
- /* UART1 RXD */
- mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D11, 0x1E4);
- mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
-
- /* UART1 TXD */
- mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D10, 0x1E4);
-}
-
-#ifdef CONFIG_I2C_MXC
-static void setup_i2c(unsigned int module_base)
-{
- switch (module_base) {
- case I2C1_BASE_ADDR:
- /* i2c1 SDA */
- mxc_request_iomux(MX53_PIN_CSI0_D8,
- IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
- mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
- INPUT_CTL_PATH0);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D8, PAD_CTL_SRE_FAST |
- PAD_CTL_ODE_OPENDRAIN_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_HYS_ENABLE);
- /* i2c1 SCL */
- mxc_request_iomux(MX53_PIN_CSI0_D9,
- IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
- mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
- INPUT_CTL_PATH0);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D9, PAD_CTL_SRE_FAST |
- PAD_CTL_ODE_OPENDRAIN_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_HYS_ENABLE);
- break;
- case I2C2_BASE_ADDR:
- /* i2c2 SDA */
- mxc_request_iomux(MX53_PIN_KEY_ROW3,
- IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
- mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
- INPUT_CTL_PATH0);
- mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
- PAD_CTL_SRE_FAST |
- PAD_CTL_ODE_OPENDRAIN_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_HYS_ENABLE);
-
- /* i2c2 SCL */
- mxc_request_iomux(MX53_PIN_KEY_COL3,
- IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
- mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
- INPUT_CTL_PATH0);
- mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
- PAD_CTL_SRE_FAST |
- PAD_CTL_ODE_OPENDRAIN_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
- PAD_CTL_HYS_ENABLE);
- break;
- default:
- printf("Invalid I2C base: 0x%x\n", module_base);
- break;
- }
-}
-
-void setup_core_voltages(void)
-{
- unsigned char buf[4] = { 0 };
-
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- /* Set core voltage VDDGP to 1.05V for 800MHZ */
- buf[0] = 0x45;
- buf[1] = 0x4a;
- buf[2] = 0x52;
- if (i2c_write(0x8, 24, 1, buf, 3))
- return;
-
- /* Set DDR voltage VDDA to 1.25V */
- buf[0] = 0;
- buf[1] = 0x63;
- buf[2] = 0x1a;
- if (i2c_write(0x8, 26, 1, buf, 3))
- return;
-
- /* Raise the core frequency to 800MHz */
- writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
-}
-
-#ifndef CONFIG_MX53_ARM2
-static int __read_adc_channel(unsigned int chan)
-{
- unsigned char buf[4] = { 0 };
-
- buf[0] = (0xb0 | ((chan & 0x1) << 3) | ((chan >> 1) & 0x7));
-
- /* LTC2495 need 410ms delay */
- udelay(410000);
-
- if (i2c_write(0x14, chan, 0, &buf[0], 1)) {
- printf("%s:i2c_write:error\n", __func__);
- return -1;
- }
-
- /* LTC2495 need 410ms delay*/
- udelay(410000);
-
- if (i2c_read(0x14, chan, 0, &buf[0], 3)) {
- printf("%s:i2c_read:error\n", __func__);
- return -1;
- }
-
- return buf[0] << 16 | buf[1] << 8 | buf[2];
-}
-
-static int __lookup_board_id(int adc_val)
-{
- int id;
-
- if (adc_val < 0x3FFFC0)
- id = 0;
- else if (adc_val < 0x461863)
- id = 1;
- else if (adc_val < 0x4C30C4)
- id = 2;
- else if (adc_val < 0x524926)
- id = 3;
- else if (adc_val < 0x586187)
- id = 4;
- else if (adc_val < 0x5E79E9)
- id = 5;
- else if (adc_val < 0x64924A)
- id = 6;
- else if (adc_val < 0x6AAAAC)
- id = 7;
- else if (adc_val < 0x70C30D)
- id = 8;
- else if (adc_val < 0x76DB6F)
- id = 9;
- else if (adc_val < 0x7CF3D0)
- id = 10;
- else if (adc_val < 0x830C32)
- id = 11;
- else if (adc_val < 0x892493)
- id = 12;
- else if (adc_val < 0x8F3CF5)
- id = 13;
- else if (adc_val < 0x955556)
- id = 14;
- else if (adc_val < 0x9B6DB8)
- id = 15;
- else if (adc_val < 0xA18619)
- id = 16;
- else if (adc_val < 0xA79E7B)
- id = 17;
- else if (adc_val < 0xADB6DC)
- id = 18;
- else if (adc_val < 0xB3CF3E)
- id = 19;
- else if (adc_val < 0xB9E79F)
- id = 20;
- else if (adc_val <= 0xC00000)
- id = 21;
- else
- return -1;
-
- return id;
-}
-
-static int __print_board_info(int id0, int id1)
-{
- int ret = 0;
-
- switch (id0) {
- case 21:
- switch (id1) {
- case 15:
- printf("MX53-EVK with DDR2 1GByte RevB\n");
-
- break;
- case 18:
- printf("MX53-EVK with DDR2 2GByte RevA1\n");
-
- break;
- case 19:
- printf("MX53-EVK with DDR2 2GByte RevA2\n");
- break;
- default:
- printf("Unkown board id1:%d\n", id1);
- ret = -1;
-
- break;
- }
-
- break;
- case 11:
- switch (id1) {
- case 1:
- printf("MX53 1.5V DDR3 x8 CPU Card, Rev. A\n");
-
- break;
- case 11:
- printf("MX53 1.8V DDR2 x8 CPU Card, Rev. A\n");
-
- break;
- default:
- printf("Unkown board id1:%d\n", id1);
- ret = -1;
-
- break;
- }
-
- break;
- default:
- printf("Unkown board id0:%d\n", id0);
-
- break;
- }
-
- return ret;
-}
-
-static int _identify_board_fix_up(int id0, int id1)
-{
- int ret = 0;
-
-#ifdef CONFIG_CMD_CLOCK
- /* For EVK RevB, set DDR to 400MHz */
- if (id0 == 21 && id1 == 15) {
- ret = clk_config(CONFIG_REF_CLK_FREQ, 400, PERIPH_CLK);
- if (ret < 0)
- return ret;
-
- ret = clk_config(CONFIG_REF_CLK_FREQ, 400, DDR_CLK);
- if (ret < 0)
- return ret;
-
- /* set up rev #2 for EVK RevB board */
- setup_board_rev(2);
- }
-#endif
- return ret;
-}
-
-int identify_board_id(void)
-{
- int ret = 0;
- int bd_id0, bd_id1;
-
-#define CPU_CHANNEL_ID0 0xc
-#define CPU_CHANNEL_ID1 0xd
-
- ret = bd_id0 = __read_adc_channel(CPU_CHANNEL_ID0);
- if (ret < 0)
- return ret;
-
- ret = bd_id1 = __read_adc_channel(CPU_CHANNEL_ID1);
- if (ret < 0)
- return ret;
-
- ret = bd_id0 = __lookup_board_id(bd_id0);
- if (ret < 0)
- return ret;
-
- ret = bd_id1 = __lookup_board_id(bd_id1);
- if (ret < 0)
- return ret;
-
- ret = __print_board_info(bd_id0, bd_id1);
- if (ret < 0)
- return ret;
-
- ret = _identify_board_fix_up(bd_id0, bd_id1);
-
- return ret;
-
-}
-#endif
-#endif
-
-#ifdef CONFIG_IMX_ECSPI
-s32 spi_get_cfg(struct imx_spi_dev_t *dev)
-{
- switch (dev->slave.cs) {
- case 0:
- /* pmic */
- dev->base = CSPI1_BASE_ADDR;
- dev->freq = 2500000;
- dev->ss_pol = IMX_SPI_ACTIVE_HIGH;
- dev->ss = 0;
- dev->fifo_sz = 64 * 4;
- dev->us_delay = 0;
- break;
- case 1:
- /* spi_nor */
- dev->base = CSPI1_BASE_ADDR;
- dev->freq = 2500000;
- dev->ss_pol = IMX_SPI_ACTIVE_LOW;
- dev->ss = 1;
- dev->fifo_sz = 64 * 4;
- dev->us_delay = 0;
- break;
- default:
- printf("Invalid Bus ID! \n");
- break;
- }
-
- return 0;
-}
-
-void spi_io_init(struct imx_spi_dev_t *dev)
-{
- switch (dev->base) {
- case CSPI1_BASE_ADDR:
- /* Select mux mode: ALT4 mux port: MOSI of instance: ecspi1 */
- mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT4);
- mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0x104);
- mxc_iomux_set_input(
- MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, 0x3);
-
- /* Select mux mode: ALT4 mux port: MISO of instance: ecspi1. */
- mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4);
- mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0x104);
- mxc_iomux_set_input(
- MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT, 0x3);
-
- if (dev->ss == 0) {
- /* de-select SS1 of instance: ecspi1. */
- mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0x1E4);
-
- /* mux mode: ALT4 mux port: SS0 of instance: ecspi1. */
- mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4);
- mxc_iomux_set_pad(MX53_PIN_EIM_EB2, 0x104);
- mxc_iomux_set_input(
- MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, 0x3);
- } else if (dev->ss == 1) {
- /* de-select SS0 of instance: ecspi1. */
- mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX53_PIN_EIM_EB2, 0x1E4);
-
- /* mux mode: ALT0 mux port: SS1 of instance: ecspi1. */
- mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
- mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0x104);
- mxc_iomux_set_input(
- MUX_IN_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT, 0x2);
- }
-
- /* Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
- mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4);
- mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0x104);
- mxc_iomux_set_input(
- MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x3);
-
- break;
- case CSPI2_BASE_ADDR:
- default:
-
- break;
- }
-}
-#endif
-
-#ifdef CONFIG_MXC_FEC
-
-#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-
-int fec_get_mac_addr(unsigned char *mac)
-{
- u32 *iim1_mac_base =
- (u32 *)(IIM_BASE_ADDR + IIM_BANK_AREA_1_OFFSET +
- CONFIG_IIM_MAC_ADDR_OFFSET);
- int i;
-
- for (i = 0; i < 6; ++i, ++iim1_mac_base)
- mac[i] = (u8)readl(iim1_mac_base);
-
- return 0;
-}
-#endif
-
-static void setup_fec(void)
-{
- volatile unsigned int reg;
-
- /*FEC_MDIO*/
- mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, 0x1FC);
- mxc_iomux_set_input(MUX_IN_FEC_FEC_MDI_SELECT_INPUT, 0x1);
-
- /*FEC_MDC*/
- mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_MDC, 0x004);
-
- /* FEC RXD1 */
- mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, 0x180);
-
- /* FEC RXD0 */
- mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, 0x180);
-
- /* FEC TXD1 */
- mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, 0x004);
-
- /* FEC TXD0 */
- mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, 0x004);
-
- /* FEC TX_EN */
- mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, 0x004);
-
- /* FEC TX_CLK */
- mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, 0x180);
-
- /* FEC RX_ER */
- mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, 0x180);
-
- /* FEC CRS */
- mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, 0x180);
-
- /* phy reset: gpio7-6 */
- mxc_request_iomux(MX53_PIN_ATA_DA_0, IOMUX_CONFIG_ALT1);
-
- reg = readl(GPIO7_BASE_ADDR + 0x0);
- reg &= ~0x40;
- writel(reg, GPIO7_BASE_ADDR + 0x0);
-
- reg = readl(GPIO7_BASE_ADDR + 0x4);
- reg |= 0x40;
- writel(reg, GPIO7_BASE_ADDR + 0x4);
-
- udelay(500);
-
- reg = readl(GPIO7_BASE_ADDR + 0x0);
- reg |= 0x40;
- writel(reg, GPIO7_BASE_ADDR + 0x0);
-
-}
-#endif
-
-#ifdef CONFIG_CMD_MMC
-
-struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR, 1, 1},
- {MMC_SDHC3_BASE_ADDR, 1, 1},
-};
-
-#ifdef CONFIG_DYNAMIC_MMC_DEVNO
-int get_mmc_env_devno()
-{
- uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
- return (soc_sbmr & 0x00300000) ? 1 : 0;
-}
-#endif
-
-
-int esdhc_gpio_init(bd_t *bis)
-{
- s32 status = 0;
- u32 index = 0;
-
- for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
- ++index) {
- switch (index) {
- case 0:
- mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA0,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA1,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA2,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA3,
- IOMUX_CONFIG_ALT0);
-
- mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
- mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
- break;
- case 1:
- mxc_request_iomux(MX53_PIN_ATA_RESET_B,
- IOMUX_CONFIG_ALT2);
- mxc_request_iomux(MX53_PIN_ATA_IORDY,
- IOMUX_CONFIG_ALT2);
- mxc_request_iomux(MX53_PIN_ATA_DATA8,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA9,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA10,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA11,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA0,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA1,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA2,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA3,
- IOMUX_CONFIG_ALT4);
-
- mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, 0x1E4);
- mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, 0xD4);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 0x1D4);
-
- break;
- default:
- printf("Warning: you configured more ESDHC controller"
- "(%d) as supported by the board(2)\n",
- CONFIG_SYS_FSL_ESDHC_NUM);
- return status;
- break;
- }
- status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
- }
-
- return status;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- if (!esdhc_gpio_init(bis))
- return 0;
- else
- return -1;
-}
-
-#endif
-
-int board_init(void)
-{
-#ifdef CONFIG_MFG
-/* MFG firmware need reset usb to avoid host crash firstly */
-#define USBCMD 0x140
- int val = readl(OTG_BASE_ADDR + USBCMD);
- val &= ~0x1; /*RS bit*/
- writel(val, OTG_BASE_ADDR + USBCMD);
-#endif
- setup_boot_device();
- setup_soc_rev();
-#if defined(CONFIG_MX53_ARM2) || defined(CONFIG_MX53_ARM2_DDR3)
- setup_board_rev(1);
-#endif
- gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK; /* board id for linux */
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- setup_uart();
- setup_fec();
-
-#ifdef CONFIG_I2C_MXC
- setup_i2c(CONFIG_SYS_I2C_PORT);
- setup_core_voltages();
-#endif
-
- return 0;
-}
-
-int board_late_init(void)
-{
- return 0;
-}
-
-int checkboard(void)
-{
- printf("Board: ");
-
-#ifdef CONFIG_MX53_ARM2
- printf("Board: MX53 ARMADILLO2 ");
- printf("1.0 [");
-#else
-#ifdef CONFIG_I2C_MXC
- identify_board_id();
-
- printf("Boot Reason: [");
-#endif
-#endif
-
- switch (__REG(SRC_BASE_ADDR + 0x8)) {
- case 0x0001:
- printf("POR");
- break;
- case 0x0009:
- printf("RST");
- break;
- case 0x0010:
- case 0x0011:
- printf("WDOG");
- break;
- default:
- printf("unknown");
- }
- printf("]\n");
-
- printf("Boot Device: ");
- switch (get_boot_device()) {
- case WEIM_NOR_BOOT:
- printf("NOR\n");
- break;
- case ONE_NAND_BOOT:
- printf("ONE NAND\n");
- break;
- case PATA_BOOT:
- printf("PATA\n");
- break;
- case SATA_BOOT:
- printf("SATA\n");
- break;
- case I2C_BOOT:
- printf("I2C\n");
- break;
- case SPI_NOR_BOOT:
- printf("SPI NOR\n");
- break;
- case SD_BOOT:
- printf("SD\n");
- break;
- case MMC_BOOT:
- printf("MMC\n");
- break;
- case NAND_BOOT:
- printf("NAND\n");
- break;
- case UNKNOWN_BOOT:
- default:
- printf("UNKNOWN\n");
- break;
- }
- return 0;
-}
+++ /dev/null
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
- board/freescale/mx53_evk/flash_header.o (.text.flasheader)
- cpu/arm_cortexa8/start.o
- board/freescale/mx53_evk/libmx53_evk.a (.text)
- lib_arm/libarm.a (.text)
- net/libnet.a (.text)
- drivers/mtd/libmtd.a (.text)
- drivers/mmc/libmmc.a (.text)
-
- . = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o(.text)
-
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2009 DENX Software Engineering
+# Author: John Rigby <jcrigby@gmail.com>
#
# See file CREDITS for list of people who contributed to this
# project.
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).o
COBJS := tx28.o
ifeq ($(CONFIG_CMD_ROMUPDATE),y)
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
-# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
-
LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
-TEXT_BASE = 0x47f80000
+CONFIG_SYS_TEXT_BASE = 0x47f80000
#include <common.h>
#include <malloc.h>
#include <nand.h>
+#include <errno.h>
#include <linux/err.h>
#include <asm/io.h>
#include <asm/sizes.h>
-#include <asm/errno.h>
-#include <asm/arch/mxs_gpmi-regs.h>
-#include <asm/arch/mxs_gpmi-bch-regs.h>
+#include <asm/arch/regs-base.h>
+#include <asm/arch/regs-gpmi.h>
+#include <asm/arch/regs-bch.h>
#define FCB_START_BLOCK 0
#define NUM_FCB_BLOCKS 1
u32 bb_num[2040 / 4];
};
-#define BF_VAL(v, bf) (((v) & BM_##bf) >> BP_##bf)
+#define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET)
static nand_info_t *mtd = &nand_info[0];
static struct mx28_fcb *create_fcb(void *buf, int fw1_start_block, int fw2_start_block,
size_t fw_size)
{
- volatile void *gpmi_base = __ioremap(GPMI_BASE_ADDR, SZ_4K, 1);
- volatile void *bch_base = __ioremap(BCH_BASE_ADDR, SZ_4K, 1);
+ volatile struct mx28_gpmi_regs *gpmi_base = __ioremap(MXS_GPMI_BASE, SZ_4K, 1);
+ volatile struct mx28_bch_regs *bch_base = __ioremap(MXS_BCH_BASE, SZ_4K, 1);
u32 fl0, fl1;
u32 t0, t1;
int metadata_size;
return ERR_PTR(-ENOMEM);
}
- fl0 = readl(bch_base + HW_BCH_FLASH0LAYOUT0);
- fl1 = readl(bch_base + HW_BCH_FLASH0LAYOUT1);
- t0 = readl(gpmi_base + HW_GPMI_TIMING0);
- t1 = readl(gpmi_base + HW_GPMI_TIMING1);
+ fl0 = readl(bch_base->hw_bch_flash0layout0);
+ fl1 = readl(bch_base->hw_bch_flash0layout1);
+ t0 = readl(gpmi_base->hw_gpmi_timing0);
+ t1 = readl(gpmi_base->hw_gpmi_timing1);
- metadata_size = BF_VAL(fl0, BCH_FLASH0LAYOUT0_META_SIZE);
+ metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
fcb = buf + ALIGN(metadata_size, 4);
fcb_offs = (void *)fcb - buf;
fcb->total_page_size = mtd->writesize + mtd->oobsize;
fcb->sectors_per_block = mtd->erasesize / mtd->writesize;
- fcb->ecc_block0_type = BF_VAL(fl0, BCH_FLASH0LAYOUT0_ECC0);
- fcb->ecc_block0_size = BF_VAL(fl0, BCH_FLASH0LAYOUT0_DATA0_SIZE);
- fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASH0LAYOUT1_ECCN);
- fcb->ecc_blockn_size = BF_VAL(fl1, BCH_FLASH0LAYOUT1_DATAN_SIZE);
+ fcb->ecc_block0_type = BF_VAL(fl0, BCH_FLASHLAYOUT0_ECC0);
+ fcb->ecc_block0_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_DATA0_SIZE);
+ fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASHLAYOUT1_ECCN);
+ fcb->ecc_blockn_size = BF_VAL(fl1, BCH_FLASHLAYOUT1_DATAN_SIZE);
- fcb->metadata_size = BF_VAL(fl0, BCH_FLASH0LAYOUT0_META_SIZE);
- fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASH0LAYOUT0_NBLOCKS);
- fcb->bch_mode = readl(bch_base + HW_BCH_MODE);
+ fcb->metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
+ fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASHLAYOUT0_NBLOCKS);
+ fcb->bch_mode = readl(bch_base->hw_bch_mode);
/*
fcb->boot_patch = 0;
fcb->patch_sectors = 0;
}
chip->select_chip(mtd, 0);
chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
- ret = chip->ecc.read_page_raw(mtd, chip, buf);
+ ret = chip->ecc.read_page_raw(mtd, chip, buf, page);
if (ret) {
printf("Failed to read FCB from page %u: %d\n", page, ret);
return ret;
extra_blocks * mtd->erasesize;
erase_opts.quiet = 1;
- printf("Erasing flash @ %08lx..%08lx\n", erase_opts.offset,
+ printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset,
erase_opts.offset + erase_opts.length - 1);
ret = nand_erase_opts(mtd, &erase_opts);
fcb->fw1_start_page * page_size,
fcb->fw1_start_page * page_size + size, addr);
ret = nand_write_skip_bad(mtd, fcb->fw1_start_page * page_size,
- &size, addr);
+ &size, addr, WITH_DROP_FFS);
if (ret) {
printf("Failed to program flash: %d\n", ret);
return ret;
printf("Programming redundant U-Boot image to block %lu\n",
fw2_start_block);
erase_opts.offset = fcb->fw2_start_page * page_size;
- printf("Erasing flash @ %08lx..%08lx\n", erase_opts.offset,
+ printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset,
erase_opts.offset + erase_opts.length - 1);
ret = nand_erase_opts(mtd, &erase_opts);
fcb->fw2_start_page * page_size,
fcb->fw2_start_page * page_size + size, addr);
ret = nand_write_skip_bad(mtd, fcb->fw2_start_page * page_size,
- &size, addr);
+ &size, addr, WITH_DROP_FFS);
if (ret) {
printf("Failed to program flash: %d\n", ret);
return ret;
*/
#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
#include <asm/arch/regs-pinctrl.h>
-#include <asm/arch/pinctrl.h>
#include <asm/arch/regs-clkctrl.h>
#include <asm/arch/regs-ocotp.h>
-#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
#include <mmc.h>
#include <imx_ssp_mmc.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_IMX_SSP_MMC
-
/* MMC pins */
-static struct pin_desc mmc0_pins_desc[] = {
- { PINID_SSP0_DATA0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_DATA1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_DATA2, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_DATA3, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_DATA4, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_DATA5, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_DATA6, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_DATA7, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_CMD, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_DETECT, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_SSP0_SCK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
-};
-
-static struct pin_group mmc0_pins = {
- .pins = mmc0_pins_desc,
- .nr_pins = ARRAY_SIZE(mmc0_pins_desc)
-};
-
-struct imx_ssp_mmc_cfg ssp_mmc_cfg[2] = {
- {REGS_SSP0_BASE, HW_CLKCTRL_SSP0, BM_CLKCTRL_CLKSEQ_BYPASS_SSP0},
- {REGS_SSP1_BASE, HW_CLKCTRL_SSP1, BM_CLKCTRL_CLKSEQ_BYPASS_SSP1},
+static iomux_cfg_t mmc0_pads[] = {
+ MX28_PAD_SSP0_DATA0__SSP0_D0,
+ MX28_PAD_SSP0_DATA1__SSP0_D1,
+ MX28_PAD_SSP0_DATA2__SSP0_D2,
+ MX28_PAD_SSP0_DATA3__SSP0_D3,
+ MX28_PAD_SSP0_DATA4__SSP0_D4,
+ MX28_PAD_SSP0_DATA5__SSP0_D5,
+ MX28_PAD_SSP0_DATA6__SSP0_D6,
+ MX28_PAD_SSP0_DATA7__SSP0_D7,
+ MX28_PAD_SSP0_CMD__SSP0_CMD,
+ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT,
+ MX28_PAD_SSP0_SCK__SSP0_SCK,
};
#endif
/* ENET pins */
-static struct pin_desc enet_pins_desc[] = {
- { PINID_ENET0_MDC, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_ENET0_MDIO, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_ENET0_RX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_ENET0_RXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_ENET0_RXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_ENET0_TX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_ENET0_TXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_ENET0_TXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
- { PINID_ENET_CLK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }
-};
-
-static struct pin_group enet_pins = {
- .pins = enet_pins_desc,
- .nr_pins = ARRAY_SIZE(enet_pins_desc),
+static iomux_cfg_t enet_pads[] = {
+ MX28_PAD_PWM4__GPIO_3_29,
+ MX28_PAD_ENET0_RX_CLK__GPIO_4_13,
+ MX28_PAD_ENET0_MDC__ENET0_MDC,
+ MX28_PAD_ENET0_MDIO__ENET0_MDIO,
+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN,
+ MX28_PAD_ENET0_RXD0__ENET0_RXD0,
+ MX28_PAD_ENET0_RXD1__ENET0_RXD1,
+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN,
+ MX28_PAD_ENET0_TXD0__ENET0_TXD0,
+ MX28_PAD_ENET0_TXD1__ENET0_TXD1,
+ MX28_PAD_ENET_CLK__CLKCTRL_ENET,
};
-static struct pin_desc duart_pins_desc[] = {
- { PINID_PWM0, PIN_GPIO, PAD_8MA, PAD_3V3, 1 },
- { PINID_PWM1, PIN_GPIO, PAD_8MA, PAD_3V3, 1 },
- { PINID_I2C0_SCL, PIN_GPIO, PAD_8MA, PAD_3V3, 1 },
- { PINID_I2C0_SDA, PIN_GPIO, PAD_8MA, PAD_3V3, 1 },
+static iomux_cfg_t duart_pads[] = {
+ MX28_PAD_PWM0__GPIO_3_16,
+ MX28_PAD_PWM1__GPIO_3_17,
+ MX28_PAD_I2C0_SCL__GPIO_3_24,
+ MX28_PAD_I2C0_SDA__GPIO_3_25,
- { PINID_AUART0_RTS, PIN_FUN3, PAD_8MA, PAD_3V3, 1 },
- { PINID_AUART0_CTS, PIN_FUN3, PAD_8MA, PAD_3V3, 1 },
- { PINID_AUART0_TX, PIN_FUN3, PAD_8MA, PAD_3V3, 1 },
- { PINID_AUART0_RX, PIN_FUN3, PAD_8MA, PAD_3V3, 1 },
+ MX28_PAD_AUART0_RTS__AUART0_RTS,
+ MX28_PAD_AUART0_CTS__AUART0_CTS,
+ MX28_PAD_AUART0_TX__AUART0_TX,
+ MX28_PAD_AUART0_RX__AUART0_RX,
};
-static struct pin_group duart_pins = {
- .pins = duart_pins_desc,
- .nr_pins = ARRAY_SIZE(duart_pins_desc),
-};
-
-static struct pin_desc gpmi_pins_desc[] = {
- { PINID_GPMI_D00, PIN_FUN1, },
- { PINID_GPMI_D01, PIN_FUN1, },
- { PINID_GPMI_D02, PIN_FUN1, },
- { PINID_GPMI_D03, PIN_FUN1, },
- { PINID_GPMI_D04, PIN_FUN1, },
- { PINID_GPMI_D05, PIN_FUN1, },
- { PINID_GPMI_D06, PIN_FUN1, },
- { PINID_GPMI_D07, PIN_FUN1, },
- { PINID_GPMI_CE0N, PIN_FUN1, },
- { PINID_GPMI_RDY0, PIN_FUN1, },
- { PINID_GPMI_RDN, PIN_FUN1, },
- { PINID_GPMI_WRN, PIN_FUN1, },
- { PINID_GPMI_ALE, PIN_FUN1, },
- { PINID_GPMI_CLE, PIN_FUN1, },
- { PINID_GPMI_RESETN, PIN_FUN1, },
-};
-
-static struct pin_group gpmi_pins = {
- .pins = gpmi_pins_desc,
- .nr_pins = ARRAY_SIZE(gpmi_pins_desc),
+static iomux_cfg_t gpmi_pads[] = {
+ MX28_PAD_GPMI_D00__GPMI_D0,
+ MX28_PAD_GPMI_D01__GPMI_D1,
+ MX28_PAD_GPMI_D02__GPMI_D2,
+ MX28_PAD_GPMI_D03__GPMI_D3,
+ MX28_PAD_GPMI_D04__GPMI_D4,
+ MX28_PAD_GPMI_D05__GPMI_D5,
+ MX28_PAD_GPMI_D06__GPMI_D6,
+ MX28_PAD_GPMI_D07__GPMI_D7,
+ MX28_PAD_GPMI_CE0N__GPMI_CE0N,
+ MX28_PAD_GPMI_RDY0__GPMI_READY0,
+ MX28_PAD_GPMI_RDN__GPMI_RDN,
+ MX28_PAD_GPMI_WRN__GPMI_WRN,
+ MX28_PAD_GPMI_ALE__GPMI_ALE,
+ MX28_PAD_GPMI_CLE__GPMI_CLE,
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN,
};
/*
*/
static void duart_init(void)
{
- pin_set_group(&duart_pins);
+ mx28_common_spl_init(&duart_pads, ARRAY_SIZE(duart_pads));
}
int board_init(void)
return 0;
}
-#ifdef CONFIG_IMX_SSP_MMC
-
#ifdef CONFIG_DYNAMIC_MMC_DEVNO
int get_mmc_env_devno(void)
{
}
#endif
-
-u32 ssp_mmc_is_wp(struct mmc *mmc)
-{
- return 0;
-}
-
-int ssp_mmc_gpio_init(bd_t *bis)
-{
- s32 status = 0;
- u32 index = 0;
-
- for (index = 0; index < CONFIG_SYS_SSP_MMC_NUM; index++) {
- switch (index) {
- case 0:
- /* Set up MMC pins */
- pin_set_group(&mmc0_pins);
- break;
-
- default:
- printf("Warning: more ssp mmc controllers configured(%d) than supported by the board(2)\n",
- CONFIG_SYS_SSP_MMC_NUM);
- return status;
- }
- status |= imx_ssp_mmc_initialize(bis, &ssp_mmc_cfg[index]);
- }
-
- return status;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- if (!ssp_mmc_gpio_init(bis))
- return 0;
- else
- return -1;
-}
-
-#endif
-
#if defined(CONFIG_MXC_FEC) && defined(CONFIG_GET_FEC_MAC_ADDR_FROM_IIM)
int fec_get_mac_addr(unsigned char *mac)
{
u32 val;
int timeout = 1000;
+ struct mx28_ocotp_regs *ocotp_regs =
+ (struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
/* set this bit to open the OTP banks for reading */
- REG_WR(REGS_OCOTP_BASE, HW_OCOTP_CTRL_SET,
- BM_OCOTP_CTRL_RD_BANK_OPEN);
+ writel(OCOTP_CTRL_RD_BANK_OPEN,
+ ocotp_regs->hw_ocotp_ctrl_set);
/* wait until OTP contents are readable */
- while (BM_OCOTP_CTRL_BUSY & REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CTRL)) {
+ while (OCOTP_CTRL_BUSY & readl(ocotp_regs->hw_ocotp_ctrl)) {
if (timeout-- < 0)
return -ETIMEDOUT;
udelay(100);
}
- val = REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CUSTn(0));
+ val = readl(ocotp_regs->hw_ocotp_cust0);
mac[0] = (val >> 24) & 0xFF;
mac[1] = (val >> 16) & 0xFF;
mac[2] = (val >> 8) & 0xFF;
mac[3] = (val >> 0) & 0xFF;
- val = REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CUSTn(1));
+ val = readl(ocotp_regs->hw_ocotp_cust1);
mac[4] = (val >> 24) & 0xFF;
mac[5] = (val >> 16) & 0xFF;
void enet_board_init(void)
{
/* Set up ENET pins */
- pin_set_group(&enet_pins);
+ mx28_common_spl_init(&enet_pads, ARRAY_SIZE(enet_pads));
/* Power on the external phy */
- pin_gpio_set(PINID_PWM4, 1);
- pin_gpio_direction(PINID_PWM4, 1);
- pin_set_type(PINID_PWM4, PIN_GPIO);
+ gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1);
/* Reset the external phy */
- pin_gpio_set(PINID_ENET0_RX_CLK, 0);
- pin_gpio_direction(PINID_ENET0_RX_CLK, 1);
- pin_set_type(PINID_ENET0_RX_CLK, PIN_GPIO);
+ gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
udelay(200);
- pin_gpio_set(PINID_ENET0_RX_CLK, 1);
+ gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
}
#ifdef CONFIG_MXS_NAND
int board_nand_init(struct mtd_info *mtd, struct nand_chip *chip)
{
- pin_set_group(&gpmi_pins);
+ mx28_common_spl_init(&gpmi_pads, ARRAY_SIZE(gpmi_pads));
return mxs_gpmi_nand_init(mtd, chip);
}
#endif
. = ALIGN(4);
.text :
{
- cpu/arm926ejs/start.o (.text)
+ arch/arm/cpu/arm926ejs/start.o (.text)
*(.text)
}
.rodata : { *(.rodata) }
jadecpu arm arm926ejs jadecpu syteco mb86r0x
mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg
tx25 arm arm926ejs tx25 karo mx25
+tx28 arm arm926ejs tx28 karo mx28
zmx25 arm arm926ejs zmx25 syteco mx25
imx27lite arm arm926ejs imx27lite logicpd mx27
magnesium arm arm926ejs imx27lite logicpd mx27
+++ /dev/null
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include <wince.h>
-
-DECLARE_GLOBAL_DATA_PTR; /* defines global data structure pointer */
-
-
-/*/////////////////////////////////////////////////////////////////////////////////////////////*/
-/* Local macro */
-
-/* Memory macro */
-
-/* #define CE_RAM_BASE 0x80100000 */
-/* #define CE_WINCE_VRAM_BASE 0x80000000 */
-/* #define CE_FIX_ADDRESS(a) (((a) - CE_WINCE_VRAM_BASE) + CE_RAM_BASE) */
-#define CE_FIX_ADDRESS(a) (a)
-
-/* Bin image parse states */
-
-#define CE_PS_RTI_ADDR 0
-#define CE_PS_RTI_LEN 1
-#define CE_PS_E_ADDR 2
-#define CE_PS_E_LEN 3
-#define CE_PS_E_CHKSUM 4
-#define CE_PS_E_DATA 5
-
-/* Min/max */
-
-#define CE_MIN(a, b) (((a) < (b)) ? (a) : (b))
-#define CE_MAX(a, b) (((a) > (b)) ? (a) : (b))
-
-// Macro string
-
-#define _STRMAC(s) #s
-#define STRMAC(s) _STRMAC(s)
-
-
-
-
-
-
-
-///////////////////////////////////////////////////////////////////////////////////////////////
-// Global data
-
-static ce_bin __attribute__ ((aligned (32))) g_bin;
-static ce_net __attribute__ ((aligned (32))) g_net;
-
-
-///////////////////////////////////////////////////////////////////////////////////////////////
-// Local proto
-
-
-
-
-///////////////////////////////////////////////////////////////////////////////////////////////
-// Implementation
-
-int ce_bin_load(void* image, int imglen)
-{
- ce_init_bin(&g_bin, image);
-
- g_bin.dataLen = imglen;
-
- if (ce_parse_bin(&g_bin) == CE_PR_EOF)
- {
- ce_prepare_run_bin(&g_bin);
- return 1;
- }
-
- return 0;
-}
-
-int ce_is_bin_image(void* image, int imglen)
-{
- if (imglen < CE_BIN_SIGN_LEN)
- {
- return 0;
- }
-
- return (memcmp(image, CE_BIN_SIGN, CE_BIN_SIGN_LEN) == 0);
-}
-
-void ce_bin_init_parser(void)
-{
- // No buffer address by now, will be specified
- // latter by the ce_bin_parse_next routine
-
- ce_init_bin(&g_bin, NULL);
-}
-
-int ce_bin_parse_next(void* parseBuffer, int len)
-{
- int rc;
-
- g_bin.data = (unsigned char*)parseBuffer;
- g_bin.dataLen = len;
- rc = ce_parse_bin(&g_bin);
-
- if (rc == CE_PR_EOF)
- {
- ce_prepare_run_bin(&g_bin);
- }
-
- return rc;
-}
-
-void ce_init_bin(ce_bin* bin, unsigned char* dataBuffer)
-{
- memset(bin, 0, sizeof(ce_bin));
-
- bin->data = dataBuffer;
- bin->parseState = CE_PS_RTI_ADDR;
- bin->parsePtr = (unsigned char*)&bin->rtiPhysAddr;
-}
-
-int ce_parse_bin(ce_bin* bin)
-{
- unsigned char* pbData = bin->data;
- int pbLen = bin->dataLen;
- int copyLen;
-
- #ifdef DEBUG
- printf("starting ce image parsing:\n\tbin->binLen: 0x%08X\n", bin->binLen);
- printf("\tpbData: 0x%08X pbLEN: 0x%08X\n", pbData, pbLen);
- #endif
-
- if (pbLen)
- {
- if (bin->binLen == 0)
- {
- // Check for the .BIN signature first
-
- if (!ce_is_bin_image(pbData, pbLen))
- {
- printf("Error: Invalid or corrupted .BIN image!\n");
-
- return CE_PR_ERROR;
- }
-
- printf("Loading Windows CE .BIN image ...\n");
-
- // Skip signature
-
- pbLen -= CE_BIN_SIGN_LEN;
- pbData += CE_BIN_SIGN_LEN;
- }
-
- while (pbLen)
- {
- switch (bin->parseState)
- {
- case CE_PS_RTI_ADDR:
- case CE_PS_RTI_LEN:
- case CE_PS_E_ADDR:
- case CE_PS_E_LEN:
- case CE_PS_E_CHKSUM:
-
- copyLen = CE_MIN(sizeof(unsigned int) - bin->parseLen, pbLen);
-
- memcpy(&bin->parsePtr[ bin->parseLen ], pbData, copyLen);
-
- bin->parseLen += copyLen;
- pbLen -= copyLen;
- pbData += copyLen;
-
- if (bin->parseLen == sizeof(unsigned int))
- {
- if (bin->parseState == CE_PS_RTI_ADDR)
- {
- bin->rtiPhysAddr = CE_FIX_ADDRESS(bin->rtiPhysAddr);
- }
- else if (bin->parseState == CE_PS_E_ADDR)
- {
- if (bin->ePhysAddr)
- {
- bin->ePhysAddr = CE_FIX_ADDRESS(bin->ePhysAddr);
- }
- }
-
- bin->parseState ++;
- bin->parseLen = 0;
- bin->parsePtr += sizeof(unsigned int);
-
- if (bin->parseState == CE_PS_E_DATA)
- {
- if (bin->ePhysAddr)
- {
- bin->parsePtr = (unsigned char*)(bin->ePhysAddr);
- bin->parseChkSum = 0;
- }
- else
- {
- // EOF
-
- pbLen = 0;
- bin->endOfBin = 1;
- }
- }
- }
-
- break;
-
- case CE_PS_E_DATA:
-
- if (bin->ePhysAddr)
- {
- copyLen = CE_MIN(bin->ePhysLen - bin->parseLen, pbLen);
- bin->parseLen += copyLen;
- pbLen -= copyLen;
-
- #ifdef DEBUG
- printf("copy %d bytes from: 0x%08X to: 0x%08X\n", copyLen, pbData, bin->parsePtr);
- #endif
- while (copyLen --)
- {
- bin->parseChkSum += *pbData;
- *bin->parsePtr ++ = *pbData ++;
- }
-
- if (bin->parseLen == bin->ePhysLen)
- {
- printf("Section [%02d]: address 0x%08X, size 0x%08X, checksum %s\n",
- bin->secion,
- bin->ePhysAddr,
- bin->ePhysLen,
- (bin->eChkSum == bin->parseChkSum) ? "ok" : "fail");
-
- if (bin->eChkSum != bin->parseChkSum)
- {
- // Checksum error!
-
- printf("Error: Checksum error, corrupted .BIN file!\n");
-
- bin->binLen = 0;
-
- return CE_PR_ERROR;
- }
-
- bin->secion ++;
- bin->parseState = CE_PS_E_ADDR;
- bin->parseLen = 0;
- bin->parsePtr = (unsigned char*)(&bin->ePhysAddr);
- }
- }
- else
- {
- bin->parseLen = 0;
- bin->endOfBin = 1;
- pbLen = 0;
- }
-
- break;
- }
- }
- }
-
- if (bin->endOfBin)
- {
- // Find entry point
-
- if (!ce_lookup_ep_bin(bin))
- {
- printf("Error: entry point not found!\n");
-
- bin->binLen = 0;
-
- return CE_PR_ERROR;
- }
-
- printf("Entry point: 0x%08X, address range: 0x%08X-0x%08X\n",
- bin->eEntryPoint,
- bin->rtiPhysAddr,
- bin->rtiPhysAddr + bin->rtiPhysLen);
-
- return CE_PR_EOF;
- }
-
- // Need more data
-
- bin->binLen += bin->dataLen;
-
- return CE_PR_MORE;
-}
-
-
-
-
-
-
-
-void ce_prepare_run_bin(ce_bin* bin)
-{
- ce_driver_globals* drv_glb;
- char *e, *s;
- char tmp[64];
- int i;
-
-
- // Clear os RAM area (if needed)
-
- //if (bin->edbgConfig.flags & EDBG_FL_CLEANBOOT)
- {
- #ifdef DEBUG
- printf("cleaning memory from 0x%08X to 0x%08X\n", bin->eRamStart, bin->eRamStart + bin->eRamLen);
- #endif
- printf("Preparing clean boot ... ");
- memset((void*)bin->eRamStart, 0, bin->eRamLen);
- printf("ok\n");
- }
-
- // Prepare driver globals (if needed)
-
- if (bin->eDrvGlb)
- {
- drv_glb = (ce_driver_globals*)bin->eDrvGlb;
-
- // Fill out driver globals
-
- memset(drv_glb, 0, sizeof(ce_driver_globals));
-
- // Signature
-
- drv_glb->signature = DRV_GLB_SIGNATURE;
-
- // No flags by now
-
- drv_glb->flags = 0;
-
- /* Local ethernet MAC address */
- i = getenv_r ("ethaddr", tmp, sizeof (tmp));
- s = (i > 0) ? tmp : 0;
-
- for (i = 0; i < 6; ++i) {
- drv_glb->macAddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
- if (s)
- s = (*e) ? e + 1 : e;
- }
-
-
- #ifdef DEBUG
- printf("got MAC address %02X:%02X:%02X:%02X:%02X:%02X from environment\n", drv_glb->macAddr[0],drv_glb->macAddr[1],drv_glb->macAddr[2],drv_glb->macAddr[3],drv_glb->macAddr[4],drv_glb->macAddr[5]);
- #endif
-
- /* Local IP address */
- drv_glb->ipAddr=(unsigned int)getenv_IPaddr("ipaddr");
- #ifdef DEBUG
- printf("got IP address ");
- print_IPaddr((IPaddr_t)drv_glb->ipAddr);
- printf(" from environment\n");
- #endif
-
- /* Subnet mask */
- drv_glb->ipMask=(unsigned long)getenv_IPaddr("netmask");
- #ifdef DEBUG
- printf("got IP mask ");
- print_IPaddr((IPaddr_t)drv_glb->ipMask);
- printf(" from environment\n");
- #endif
-
- /* Gateway config */
- drv_glb->ipGate=(unsigned long)getenv_IPaddr("gatewayip");
- #ifdef DEBUG
- printf("got gateway address ");
- print_IPaddr((IPaddr_t)drv_glb->ipGate);
- printf(" from environment\n");
- #endif
-
-
-
-
-
- // EDBG services config
-
- memcpy(&drv_glb->edbgConfig, &bin->edbgConfig, sizeof(bin->edbgConfig));
-
-
-
-
- }
-
-}
-
-
-int ce_lookup_ep_bin(ce_bin* bin)
-{
- ce_rom_hdr* header;
- ce_toc_entry* tentry;
- e32_rom* e32;
- unsigned int i;
-
- // Check image Table Of Contents (TOC) signature
-
- if (*(unsigned int*)(bin->rtiPhysAddr + ROM_SIGNATURE_OFFSET) != ROM_SIGNATURE)
- {
- // Error: Did not find image TOC signature!
-
- return 0;
- }
-
-
- // Lookup entry point
-
- header = (ce_rom_hdr*)CE_FIX_ADDRESS(*(unsigned int*)(bin->rtiPhysAddr + ROM_SIGNATURE_OFFSET + sizeof(unsigned int)));
- tentry = (ce_toc_entry*)(header + 1);
-
- for (i = 0; i < header->nummods; i ++)
- {
- // Look for 'nk.exe' module
-
- if (strcmp((char*)CE_FIX_ADDRESS(tentry[ i ].fileName), "nk.exe") == 0)
- {
- // Save entry point and RAM addresses
-
- e32 = (e32_rom*)CE_FIX_ADDRESS(tentry[ i ].e32Offset);
-
- bin->eEntryPoint = CE_FIX_ADDRESS(tentry[ i ].loadOffset) + e32->e32_entryrva;
- bin->eRamStart = CE_FIX_ADDRESS(header->ramStart);
- bin->eRamLen = header->ramEnd - header->ramStart;
-
- // Save driver_globals address
- // Must follow RAM section in CE config.bib file
- //
- // eg.
- //
- // RAM 80900000 03200000 RAM
- // DRV_GLB 83B00000 00001000 RESERVED
- //
-
- bin->eDrvGlb = CE_FIX_ADDRESS(header->ramEnd);
-
- return 1;
- }
- }
-
- // Error: Did not find 'nk.exe' module
-
- return 0;
-}
-
-
-
-
-typedef void (*CeEntryPointPtr)(void);
-
-
-
-void ce_run_bin(ce_bin* bin)
-{
- CeEntryPointPtr EnrtryPoint;
-
- printf("Launching Windows CE ...\n");
-
-
- EnrtryPoint = (CeEntryPointPtr)bin->eEntryPoint;
-
- EnrtryPoint();
-
-}
-
-int ce_boot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- unsigned long addr;
- unsigned long image_size;
- unsigned char *s;
-
-
- if (argc < 2) {
- printf ("myUsage:\n%s\n", cmdtp->usage);
- return 1;
- }
-
- addr = simple_strtoul(argv[1], NULL, 16);
- image_size = 0x7fffffff; /* actually we do not know the image size */
-
- printf ("## Booting Windows CE Image from address 0x%08lX ...\n", addr);
-
-
- /* check if there is a valid windows CE image */
- if (ce_is_bin_image((void *)addr, image_size))
- {
- if (!ce_bin_load((void*)addr, image_size))
- {
- /* Ops! Corrupted .BIN image! */
- /* Handle error here ... */
- printf("corrupted .BIN image !!!\n");
- return 1;
-
- }
- if ((s = getenv("autostart")) != NULL) {
- if (*s == 'n') {
- /*
- * just use bootce to load the image to SDRAM;
- * Do not start it automatically.
- */
- return 0;
- }
- }
- ce_run_bin(&g_bin); /* start the image */
-
- } else {
- printf("Image seems to be no valid Windows CE image !\n");
- return 1;
-
- }
- return 1; /* never reached - just to keep compiler happy */
-
-
-}
-
-
-
-U_BOOT_CMD(
- bootce, 2, 0, ce_boot,
- "bootce\t- Boot a Windows CE image from memory \n",
- "[args..]\n"
- "\taddr\t\t-boot image from address addr\n"
-);
-
-
-
-#if 1
-static void wince_handler (uchar * pkt, unsigned dest, unsigned src, unsigned len)
-{
-
-
- NetState = NETLOOP_SUCCESS; /* got input - quit net loop */
- if(!memcmp(g_net.data + g_net.align_offset, gd->bd->bi_enetaddr, 6)) {
- g_net.got_packet_4me=1;
- g_net.dataLen=len;
- } else {
- g_net.got_packet_4me=0;
- return;
- }
-
- if(1) {
- g_net.srvAddrRecv.sin_port = ntohs(*((unsigned short *)(g_net.data + ETHER_HDR_SIZE + IP_HDR_SIZE_NO_UDP + g_net.align_offset)));
- NetCopyIP(&g_net.srvAddrRecv.sin_addr, g_net.data + ETHER_HDR_SIZE + g_net.align_offset + 12);
- memcpy(NetServerEther, g_net.data + g_net.align_offset +6, 6);
-
- #if 0
- printf("received packet: buffer 0x%08X Laenge %d \n", (unsigned long) pkt, len);
- printf("from ");
- print_IPaddr(g_net.srvAddrRecv.sin_addr);
- printf(", port: %d\n", g_net.srvAddrRecv.sin_port);
-
-
-
- ce_dump_block(pkt, len);
-
- printf("Headers:\n");
- ce_dump_block(pkt - ETHER_HDR_SIZE - IP_HDR_SIZE, ETHER_HDR_SIZE + IP_HDR_SIZE);
- printf("\n\nmy port should be: %d\n", ntohs(*((unsigned short *)(g_net.data + ETHER_HDR_SIZE + IP_HDR_SIZE_NO_UDP + g_net.align_offset +2))));
- #endif
- }
-
-}
-
-
-
-/* returns packet lengt if successfull */
-int ce_recv_packet(char *buf, int len, struct sockaddr_in *from, struct sockaddr_in *local, struct timeval *timeout){
-
- int rxlength;
- ulong time_started;
-
-
-
- g_net.got_packet_4me=0;
- time_started = get_timer(0);
-
-
- NetRxPackets[0] = (uchar *)buf;
- NetSetHandler(wince_handler);
-
- while(1) {
- rxlength=eth_rx();
- if(g_net.got_packet_4me)
- return g_net.dataLen;
- /* check for timeout */
- if (get_timer(time_started) > timeout->tv_sec * CFG_HZ) {
- return -1;
- }
- }
-}
-
-
-
-int ce_recv_frame(ce_net* net, int timeout)
-{
- struct timeval timeo;
-
- // Setup timeout
-
- timeo.tv_sec = timeout;
- timeo.tv_usec = 0;
-
- /* Receive UDP packet */
-
- net->dataLen = ce_recv_packet(net->data+net->align_offset, sizeof(net->data)-net->align_offset, &net->srvAddrRecv, &net->locAddr, &timeo);
-
- if (net->dataLen < 0)
- {
- /* Error! No data available */
-
- net->dataLen = 0;
- }
-
- return net->dataLen;
-}
-
-int ce_process_download(ce_net* net, ce_bin* bin)
-{
- int ret = CE_PR_MORE;
-
- if (net->dataLen >= 2)
- {
- unsigned short command;
-
- command = ntohs(*(unsigned short*)(net->data+CE_DOFFSET));
-
- #ifdef DEBUG
- printf("command found: 0x%04X\n", command);
- #endif
-
- switch (command)
- {
- case EDBG_CMD_WRITE_REQ:
-
- if (!net->link)
- {
- // Check file name for WRITE request
- // CE EShell uses "boot.bin" file name
-
- /*printf(">>>>>>>> First Frame, IP: %s, port: %d\n",
- inet_ntoa((in_addr_t *)&net->srvAddrRecv),
- net->srvAddrRecv.sin_port);*/
-
- if (strncmp((char*)(net->data +CE_DOFFSET + 2), "boot.bin", 8) == 0)
- {
- // Some diag output
-
- if (net->verbose)
- {
- printf("Locked Down download link, IP: ");
- print_IPaddr(net->srvAddrRecv.sin_addr);
- printf(", port: %d\n", net->srvAddrRecv.sin_port);
- }
-
-
-
-
- if (net->verbose)
- {
- printf("Sending BOOTME request [%d] to ", (int)net->secNum);
- print_IPaddr(net->srvAddrSend.sin_addr);
- printf("\n");
- }
-
-
-
-
- // Lock down EShell download link
-
- net->locAddr.sin_port = (EDBG_DOWNLOAD_PORT + 1);
- net->srvAddrSend.sin_port = net->srvAddrRecv.sin_port;
- net->srvAddrSend.sin_addr = net->srvAddrRecv.sin_addr;
- net->link = 1;
- }
- else
- {
- // Unknown link
-
- net->srvAddrRecv.sin_port = 0;
- }
-
- // Return write ack
-
- if (net->link)
- {
- ce_send_write_ack(net);
- }
-
- break;
- }
-
- case EDBG_CMD_WRITE:
-
- /* Fix data len */
- bin->dataLen = net->dataLen - 4;
-
- // Parse next block of .bin file
-
- ret = ce_parse_bin(bin);
-
- // Request next block
-
- if (ret != CE_PR_ERROR)
- {
- net->blockNum ++;
-
- ce_send_write_ack(net);
- }
-
- break;
-
- case EDBG_CMD_READ_REQ:
-
- // Read requests are not supported
- // Do nothing ...
-
- break;
-
- case EDBG_CMD_ERROR:
-
- // Error condition on the host side
-
- printf("Error: unknown error on the host side\n");
-
- bin->binLen = 0;
- ret = CE_PR_ERROR;
-
- break;
- default:
- printf("unknown command 0x%04X ????\n", command);
- while(1);
- }
-
-
- }
-
- return ret;
-}
-
-
-
-void ce_init_edbg_link(ce_net* net)
-{
- /* Initialize EDBG link for commands */
-
- net->locAddr.sin_port = EDBG_DOWNLOAD_PORT;
- net->srvAddrSend.sin_port = EDBG_DOWNLOAD_PORT;
- net->srvAddrRecv.sin_port = 0;
- net->link = 0;
-}
-
-void ce_process_edbg(ce_net* net, ce_bin* bin)
-{
- eth_dbg_hdr* header;
-
-
-
- if (net->dataLen < sizeof(eth_dbg_hdr))
- {
- /* Bad packet */
-
- net->srvAddrRecv.sin_port = 0;
- return;
- }
-
- header = (eth_dbg_hdr*)(net->data + net->align_offset + ETHER_HDR_SIZE + IP_HDR_SIZE);
-
- if (header->id != EDBG_ID)
- {
- /* Bad packet */
-
- net->srvAddrRecv.sin_port = 0;
- return;
- }
-
- if (header->service != EDBG_SVC_ADMIN)
- {
- /* Unknown service */
-
- return;
- }
-
- if (!net->link)
- {
- /* Some diag output */
-
- if (net->verbose)
- {
- printf("Locked Down EDBG service link, IP: ");
- print_IPaddr(net->srvAddrRecv.sin_addr);
- printf(", port: %d\n", net->srvAddrRecv.sin_port);
- }
-
- /* Lock down EDBG link */
-
- net->srvAddrSend.sin_port = net->srvAddrRecv.sin_port;
- net->link = 1;
- }
-
- switch (header->cmd)
- {
- case EDBG_CMD_JUMPIMG:
-
- net->gotJumpingRequest = 1;
-
- if (net->verbose)
- {
- printf("Received JUMPING command\n");
- }
-
- /* Just pass through and copy CONFIG structure */
-
- case EDBG_CMD_OS_CONFIG:
-
- /* Copy config structure */
-
- memcpy(&bin->edbgConfig, header->data, sizeof(edbg_os_config_data));
-
- if (net->verbose)
- {
- printf("Received CONFIG command\n");
-
- if (bin->edbgConfig.flags & EDBG_FL_DBGMSG)
- {
- printf("--> Enabling DBGMSG service, IP: %d.%d.%d.%d, port: %d\n",
- (bin->edbgConfig.dbgMsgIPAddr >> 0) & 0xFF,
- (bin->edbgConfig.dbgMsgIPAddr >> 8) & 0xFF,
- (bin->edbgConfig.dbgMsgIPAddr >> 16) & 0xFF,
- (bin->edbgConfig.dbgMsgIPAddr >> 24) & 0xFF,
- (int)bin->edbgConfig.dbgMsgPort);
- }
-
- if (bin->edbgConfig.flags & EDBG_FL_PPSH)
- {
- printf("--> Enabling PPSH service, IP: %d.%d.%d.%d, port: %d\n",
- (bin->edbgConfig.ppshIPAddr >> 0) & 0xFF,
- (bin->edbgConfig.ppshIPAddr >> 8) & 0xFF,
- (bin->edbgConfig.ppshIPAddr >> 16) & 0xFF,
- (bin->edbgConfig.ppshIPAddr >> 24) & 0xFF,
- (int)bin->edbgConfig.ppshPort);
- }
-
- if (bin->edbgConfig.flags & EDBG_FL_KDBG)
- {
- printf("--> Enabling KDBG service, IP: %d.%d.%d.%d, port: %d\n",
- (bin->edbgConfig.kdbgIPAddr >> 0) & 0xFF,
- (bin->edbgConfig.kdbgIPAddr >> 8) & 0xFF,
- (bin->edbgConfig.kdbgIPAddr >> 16) & 0xFF,
- (bin->edbgConfig.kdbgIPAddr >> 24) & 0xFF,
- (int)bin->edbgConfig.kdbgPort);
- }
-
- if (bin->edbgConfig.flags & EDBG_FL_CLEANBOOT)
- {
- printf("--> Force clean boot\n");
- }
- }
-
- break;
-
- default:
- if (net->verbose) {
- printf("Received unknown command: %08X\n", header->cmd);
- }
- return;
- }
-
- /* Respond with ack */
- header->flags = EDBG_FL_FROM_DEV | EDBG_FL_ACK;
- net->dataLen = EDBG_DATA_OFFSET;
- ce_send_frame(net);
-}
-
-int ce_send_write_ack(ce_net* net)
-{
- unsigned short* wdata;
- unsigned long aligned_address;
-
- aligned_address=(unsigned long)net->data+ETHER_HDR_SIZE+IP_HDR_SIZE+net->align_offset;
-
- wdata = (unsigned short*)aligned_address;
- wdata[ 0 ] = htons(EDBG_CMD_WRITE_ACK);
- wdata[ 1 ] = htons(net->blockNum);
-
- net->dataLen = 4;
-
- return ce_send_frame(net);
-}
-
-
-
-int ce_send_frame(ce_net* net)
-{
- /* Send UDP packet */
- NetTxPacket = (uchar *)net->data + net->align_offset;
- return NetSendUDPPacket(NetServerEther, net->srvAddrSend.sin_addr, (int)net->srvAddrSend.sin_port, (int)net->locAddr.sin_port, net->dataLen);
-}
-
-
-
-
-
-
-
-int ce_send_bootme(ce_net* net)
-{
- eth_dbg_hdr* header;
- edbg_bootme_data* data;
-
- char *e, *s;
- int i;
- unsigned char tmp[64];
- unsigned char *macp;
-
- #ifdef DEBUG
- char *pkt;
- #endif
-
-
- /* Fill out BOOTME packet */
- memset(net->data, 0, PKTSIZE);
- header = (eth_dbg_hdr*)(net->data +CE_DOFFSET);
- data = (edbg_bootme_data*)header->data;
-
- header->id=EDBG_ID;
- header->service = EDBG_SVC_ADMIN;
- header->flags = EDBG_FL_FROM_DEV;
- header->seqNum = net->secNum ++;
- header->cmd = EDBG_CMD_BOOTME;
-
- data->versionMajor = 0;
- data->versionMinor = 0;
- data->cpuId = EDBG_CPU_TYPE_ARM;
- data->bootmeVer = EDBG_CURRENT_BOOTME_VERSION;
- data->bootFlags = 0;
- data->downloadPort = 0;
- data->svcPort = 0;
-
- macp=(unsigned char *)data->macAddr;
- /* MAC address from environment*/
- i = getenv_r ("ethaddr", tmp, sizeof (tmp));
- s = (i > 0) ? tmp : 0;
- for (i = 0; i < 6; ++i) {
- macp[i] = s ? simple_strtoul (s, &e, 16) : 0;
- if (s)
- s = (*e) ? e + 1 : e;
- }
-
- /* IP address from environment */
- data->ipAddr = (unsigned int)getenv_IPaddr("ipaddr");
-
- // Device name string (NULL terminated). Should include
- // platform and number based on Ether address (e.g. Odo42, CEPCLS2346, etc)
-
- // We will use lower MAC address segment to create device name
- // eg. MAC '00-0C-C6-69-09-05', device name 'Triton05'
-
- strcpy(data->platformId, "Triton");
- sprintf(data->deviceName, "%s%02X", data->platformId, macp[5]);
-
-
-#ifdef DEBUG
-
- printf("header->id: %08X\r\n", header->id);
- printf("header->service: %08X\r\n", header->service);
- printf("header->flags: %08X\r\n", header->flags);
- printf("header->seqNum: %08X\r\n", header->seqNum);
- printf("header->cmd: %08X\r\n\r\n", header->cmd);
-
- printf("data->versionMajor: %08X\r\n", data->versionMajor);
- printf("data->versionMinor: %08X\r\n", data->versionMinor);
- printf("data->cpuId: %08X\r\n", data->cpuId);
- printf("data->bootmeVer: %08X\r\n", data->bootmeVer);
- printf("data->bootFlags: %08X\r\n", data->bootFlags);
- printf("data->svcPort: %08X\r\n\r\n", data->svcPort);
-
- printf("data->macAddr: %02X-%02X-%02X-%02X-%02X-%02X\r\n",
- (data->macAddr[0] >> 0) & 0xFF,
- (data->macAddr[0] >> 8) & 0xFF,
- (data->macAddr[1] >> 0) & 0xFF,
- (data->macAddr[1] >> 8) & 0xFF,
- (data->macAddr[2] >> 0) & 0xFF,
- (data->macAddr[2] >> 8) & 0xFF);
-
- printf("data->ipAddr: %d.%d.%d.%d\r\n",
- (data->ipAddr >> 0) & 0xFF,
- (data->ipAddr >> 8) & 0xFF,
- (data->ipAddr >> 16) & 0xFF,
- (data->ipAddr >> 24) & 0xFF);
-
- printf("data->platformId: %s\r\n", data->platformId);
-
- printf("data->deviceName: %s\r\n", data->deviceName);
-
-#endif
-
-
- // Some diag output ...
-
- if (net->verbose)
- {
- printf("Sending BOOTME request [%d] to ", (int)net->secNum);
- print_IPaddr(net->srvAddrSend.sin_addr);
- printf("\n");
- }
-
- // Send packet
-
- net->dataLen = BOOTME_PKT_SIZE;
-
-
- #ifdef DEBUG
- printf("\n\n\nStart of buffer: 0x%08X\n", (unsigned long)net->data);
- printf("Start of ethernet buffer: 0x%08X\n", (unsigned long)net->data+net->align_offset);
- printf("Start of CE header: 0x%08X\n", (unsigned long)header);
- printf("Start of CE data: 0x%08X\n", (unsigned long)data);
-
- pkt = (uchar *)net->data+net->align_offset;
- printf("\n\npacket to send (ceconnect): \n");
- for(i=0; i<(net->dataLen+ETHER_HDR_SIZE+IP_HDR_SIZE); i++) {
- printf("0x%02X ", pkt[i]);
- if(!((i+1)%16))
- printf("\n");
- }
- printf("\n\n");
- #endif
-
- memcpy(NetServerEther, NetBcastAddr, 6);
-
- return ce_send_frame(net);
-}
-
-
-
-void ce_dump_block(unsigned char *ptr, int length) {
-
- int i;
- int j;
-
- for(i=0; i<length; i++) {
- if(!(i%16)) {
- printf("\n0x%08X: ", (unsigned long)ptr + i);
- }
-
- printf("0x%02X ", ptr[i]);
-
- if(!((i+1)%16)){
- printf(" ");
- for(j=i-15; j<i; j++){
- if((ptr[j]>0x1f) && (ptr[j]<0x7f)) {
- printf("%c", ptr[j]);
- } else {
- printf(".");
- }
- }
- }
-
- }
-
- printf("\n\n");
-}
-
-
-
-
-
-
-
-
-
-
-void ce_init_download_link(ce_net* net, ce_bin* bin, struct sockaddr_in* host_addr, int verbose)
-{
- unsigned long aligned_address;
- /* Initialize EDBG link for download */
-
-
- memset(net, 0, sizeof(ce_net));
-
- /* our buffer contains space for ethernet- ip- and udp- headers */
- /* calucalate an offset that our ce field is aligned to 4 bytes */
- aligned_address=(unsigned long)net->data; /* this is the start of our physical buffer */
- aligned_address += (ETHER_HDR_SIZE+IP_HDR_SIZE); /* we need 42 bytes room for headers (14 Ethernet , 20 IPv4, 8 UDP) */
- net->align_offset = 4-(aligned_address%4); /* want CE header aligned to 4 Byte boundary */
- if(net->align_offset == 4) {
- net->align_offset=0;
- }
-
- net->locAddr.sin_family = AF_INET;
- net->locAddr.sin_addr = getenv_IPaddr("ipaddr");
- net->locAddr.sin_port = EDBG_DOWNLOAD_PORT;
-
- net->srvAddrSend.sin_family = AF_INET;
- net->srvAddrSend.sin_port = EDBG_DOWNLOAD_PORT;
-
- net->srvAddrRecv.sin_family = AF_INET;
- net->srvAddrRecv.sin_port = 0;
-
- if (host_addr->sin_addr)
- {
- /* Use specified host address ... */
-
- net->srvAddrSend.sin_addr = host_addr->sin_addr;
- net->srvAddrRecv.sin_addr = host_addr->sin_addr;
- }
- else
- {
- /* ... or use default server address */
-
- net->srvAddrSend.sin_addr = getenv_IPaddr("serverip");
- net->srvAddrRecv.sin_addr = getenv_IPaddr("serverip");
- }
-
- net->verbose = verbose;
- /* Initialize .BIN parser */
- ce_init_bin(bin, net->data + CE_DOFFSET + 4);
-
-
-
- eth_halt();
-
-#ifdef CONFIG_NET_MULTI
- eth_set_current();
-#endif
- if (eth_init(gd->bd) < 0) {
- #ifdef ET_DEBUG
- puts("ceconnect: failed to init ethernet !\n");
- #endif
- eth_halt();
- return;
- }
- #ifdef ET_DEBUG
- puts("ceconnect: init ethernet done!\n");
- #endif
-
-
- memcpy (NetOurEther, gd->bd->bi_enetaddr, 6);
- NetCopyIP(&NetOurIP, &gd->bd->bi_ip_addr);
- NetOurGatewayIP = getenv_IPaddr ("gatewayip");
- NetOurSubnetMask= getenv_IPaddr ("netmask");
- NetServerIP = getenv_IPaddr ("serverip");
-
-}
-
-
-int ce_load(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- int i;
- int verbose, use_timeout;
- int timeout, recv_timeout, ret;
- struct sockaddr_in host_ip_addr;
-
- // -v verbose
-
- verbose = 0;
- use_timeout = 0;
- timeout = 0;
-
-
- for(i=0;i<argc;i++){
- if (strcmp(argv[i+1], "-v") == 0){
- verbose = 1;
- }
- }
-
-
- for(i=0;i<(argc-1);i++){
- if (strcmp(argv[i+1], "-t") == 0){
- use_timeout = 1;
- timeout = simple_strtoul(argv[i+2], NULL, 10);
- }
- }
-
- #ifdef DEBUG
- printf("verbose=%d, use_timeout=%d, timeout=%d\n", verbose, use_timeout, timeout);
- #endif
-
- // Check host IP address (if specified)
-
- *((unsigned int *)&host_ip_addr) = 0xFFFFFFFF;
-
-
- // Initialize download link
-
- ce_init_download_link(&g_net, &g_bin, &host_ip_addr, verbose);
-
- // Download loop
-
- while (1)
- {
- if (g_net.link)
- {
- recv_timeout = 3;
- }
- else
- {
- recv_timeout = 1;
-
- if (use_timeout)
- {
- if (timeout <= 0)
- {
- printf("CELOAD - Canceled, timeout\n");
- eth_halt();
- return 1;
- }
- } else {
- /* Try to catch ^C */
- #ifdef DEBUG
- puts("try to catch ^C\n");
- #endif
- if (ctrlc())
- {
- printf("CELOAD - canceled by user\n");
- eth_halt();
- return 1;
- }
- }
- #ifdef DEBUG
- puts("sending broadcast frame bootme\n");
- #endif
-
- if (ce_send_bootme(&g_net))
- {
- printf("CELOAD - error while sending BOOTME request\n");
- eth_halt();
- return 1;
- }
- printf("net state is: %d\n", NetState);
- if (verbose)
- {
- if (use_timeout)
- {
- printf("Waiting for connection, timeout %d sec\n", timeout);
- }
- else
- {
- printf("Waiting for connection, enter ^C to abort\n");
- }
- }
- }
-
- // Try to receive frame
-
- if (ce_recv_frame(&g_net, recv_timeout))
- {
- // Process received data
-
- ret = ce_process_download(&g_net, &g_bin);
-
- if (ret != CE_PR_MORE)
- {
- break;
- }
- }
- else if (use_timeout)
- {
- timeout -= recv_timeout;
- }
- }
-
- if (g_bin.binLen)
- {
- // Try to receive edbg commands from host
-
- ce_init_edbg_link(&g_net);
-
- if (verbose)
- {
- printf("Waiting for EDBG commands ...\n");
- }
-
- while (ce_recv_frame(&g_net, 3))
- {
- ce_process_edbg(&g_net, &g_bin);
- }
-
- // Prepare WinCE image for execution
-
- ce_prepare_run_bin(&g_bin);
-
- // Launch WinCE, if necessary
-
- if (g_net.gotJumpingRequest)
- {
- ce_run_bin(&g_bin);
- }
- }
- eth_halt();
- return 0;
-}
-
-
-
-
-
-
-
-U_BOOT_CMD(
- ceconnect, 2, 1, ce_load,
- "ceconnect - Set up a connection to the CE host PC over TCP/IP and download the run-time image\n",
- "ceconnect [-v] [-t <timeout>]\n"
- " -v verbose operation\n"
- " -t <timeout> - max wait time (#sec) for the connection\n"
-);
-
-#endif
-
-/* CFG_CMD_WINCE */
);
#else /* !CONFIG_GENERIC_MMC */
-<<<<<<< HEAD
-#ifdef CONFIG_BOOT_PARTITION_ACCESS
-#define MMC_PARTITION_SWITCH(mmc, part, enable_boot) \
- do { \
- if (IS_SD(mmc)) { \
- if (part > 1) {\
- printf( \
- "\nError: SD partition can only be 0 or 1\n");\
- return 1; \
- } \
- if (sd_switch_partition(mmc, part) < 0) { \
- if (part > 0) { \
- printf("\nError: Unable to switch SD "\
- "partition\n");\
- return 1; \
- } \
- } \
- } else { \
- if (mmc_switch_partition(mmc, part, enable_boot) \
- < 0) { \
- printf("Error: Fail to switch " \
- "partition to %d\n", part); \
- return 1; \
- } \
- } \
- } while (0)
-#endif
-
-=======
enum mmc_state {
MMC_INVALID,
MMC_READ,
MMC_WRITE,
MMC_ERASE,
};
->>>>>>> 9a3aae22edf1eda6326cc51c28631ca5c23b7706
static void print_mmcinfo(struct mmc *mmc)
{
printf("Device: %s\n", mmc->name);
mmc = find_mmc_device(curr_device);
if (mmc) {
-<<<<<<< HEAD
- if (mmc_init(mmc))
- puts("MMC card init failed!\n");
- else
- print_mmcinfo(mmc);
-=======
mmc_init(mmc);
print_mmcinfo(mmc);
} else {
printf("no mmc device at slot %x\n", curr_device);
return 1;
->>>>>>> 9a3aae22edf1eda6326cc51c28631ca5c23b7706
}
}
-<<<<<<< HEAD
-U_BOOT_CMD(mmcinfo, 2, 0, do_mmcinfo,
- "mmcinfo <dev num>-- display MMC info",
-=======
U_BOOT_CMD(
mmcinfo, 1, 0, do_mmcinfo,
"display MMC info",
" - device number of the device to dislay info of\n"
->>>>>>> 9a3aae22edf1eda6326cc51c28631ca5c23b7706
""
);
int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
-<<<<<<< HEAD
- int rc = 0;
-#ifdef CONFIG_BOOT_PARTITION_ACCESS
- u32 part = 0;
-#endif
-=======
enum mmc_state state;
->>>>>>> 9a3aae22edf1eda6326cc51c28631ca5c23b7706
if (argc < 2)
return cmd_usage(cmdtp);
puts("get mmc type error!\n");
return 1;
-<<<<<<< HEAD
-#ifdef CONFIG_BOOT_PARTITION_ACCESS
- case 7: /* Fall through */
- part = simple_strtoul(argv[6], NULL, 10);
-#endif
- default: /* at least 5 args */
- if (strcmp(argv[1], "read") == 0) {
- int dev = simple_strtoul(argv[2], NULL, 10);
- void *addr = (void *)simple_strtoul(argv[3], NULL, 16);
- u32 cnt = simple_strtoul(argv[5], NULL, 16);
- u32 n;
- u32 blk = simple_strtoul(argv[4], NULL, 16);
-
- struct mmc *mmc = find_mmc_device(dev);
-
- if (!mmc)
-=======
} else if (strcmp(argv[1], "list") == 0) {
print_mmc_devices('\n');
return 0;
if (part > PART_ACCESS_MASK) {
printf("#part_num shouldn't be larger"
" than %d\n", PART_ACCESS_MASK);
->>>>>>> 9a3aae22edf1eda6326cc51c28631ca5c23b7706
return 1;
}
} else
return cmd_usage(cmdtp);
-<<<<<<< HEAD
-#ifdef CONFIG_BOOT_PARTITION_ACCESS
- printf("\nMMC read: dev # %d, block # %d, "
- "count %d partition # %d ... \n",
- dev, blk, cnt, part);
-#else
- printf("\nMMC read: dev # %d, block # %d,"
- "count %d ... \n", dev, blk, cnt);
-#endif
-
- mmc_init(mmc);
-
-#ifdef CONFIG_BOOT_PARTITION_ACCESS
- if (((mmc->boot_config &
- EXT_CSD_BOOT_PARTITION_ACCESS_MASK) != part)
- || IS_SD(mmc)) {
- /*
- * After mmc_init, we now know whether
- * this is a eSD/eMMC which support boot
- * partition
- */
- MMC_PARTITION_SWITCH(mmc, part, 0);
- }
-#endif
-
- n = mmc->block_dev.block_read(dev, blk, cnt, addr);
-=======
mmc = find_mmc_device(dev);
if (!mmc) {
printf("no mmc device at slot %x\n", dev);
return 1;
}
->>>>>>> 9a3aae22edf1eda6326cc51c28631ca5c23b7706
mmc_init(mmc);
if (part != -1) {
return 1;
}
-<<<<<<< HEAD
- printf("%d blocks read: %s\n",
- n, (n==cnt) ? "OK" : "ERROR");
- return (n == cnt) ? 0 : 1;
- } else if (strcmp(argv[1], "write") == 0) {
- int dev = simple_strtoul(argv[2], NULL, 10);
- void *addr = (void *)simple_strtoul(argv[3], NULL, 16);
- u32 cnt = simple_strtoul(argv[5], NULL, 16);
- u32 n;
-
- struct mmc *mmc = find_mmc_device(dev);
-=======
if (part != mmc->part_num) {
ret = mmc_switch_part(dev, part);
if (!ret)
mmc->part_num = part;
->>>>>>> 9a3aae22edf1eda6326cc51c28631ca5c23b7706
printf("switch to partions #%d, %s\n",
part, (!ret) ? "OK" : "ERROR");
return 0;
}
-<<<<<<< HEAD
-#ifdef CONFIG_BOOT_PARTITION_ACCESS
- printf("\nMMC write: dev # %d, block # %d, "
- "count %d, partition # %d ... \n",
- dev, blk, cnt, part);
-#else
- printf("\nMMC write: dev # %d, block # %d, "
- "count %d ... \n",
- dev, blk, cnt);
-#endif
-=======
if (strcmp(argv[1], "read") == 0)
state = MMC_READ;
else if (strcmp(argv[1], "write") == 0)
printf("no mmc device at slot %x\n", curr_device);
return 1;
}
->>>>>>> 9a3aae22edf1eda6326cc51c28631ca5c23b7706
printf("\nMMC %s: dev # %d, block # %d, count %d ... ",
argv[1], curr_device, blk, cnt);
-<<<<<<< HEAD
-#ifdef CONFIG_BOOT_PARTITION_ACCESS
- if (((mmc->boot_config &
- EXT_CSD_BOOT_PARTITION_ACCESS_MASK) != part)
- || IS_SD(mmc)) {
- /*
- * After mmc_init, we now know whether this is a
- * eSD/eMMC which support boot partition
- */
- MMC_PARTITION_SWITCH(mmc, part, 1);
- }
-#endif
-
- n = mmc->block_dev.block_write(dev, blk, cnt, addr);
-=======
mmc_init(mmc);
->>>>>>> 9a3aae22edf1eda6326cc51c28631ca5c23b7706
switch (state) {
case MMC_READ:
U_BOOT_CMD(
mmc, 6, 1, do_mmcops,
"MMC sub system",
-<<<<<<< HEAD
- "mmc read <device num> addr blk# cnt\n"
- "mmc write <device num> addr blk# cnt\n"
- "mmc rescan <device num>\n"
-=======
"read addr blk# cnt\n"
"mmc write addr blk# cnt\n"
"mmc erase blk# cnt\n"
"mmc rescan\n"
"mmc part - lists available partition on current mmc device\n"
"mmc dev [dev] [part] - show or set current mmc device [partition]\n"
->>>>>>> 9a3aae22edf1eda6326cc51c28631ca5c23b7706
- "mmc list - lists available devices");
-#else
-U_BOOT_CMD(
- mmc, 7, 1, do_mmcops,
- "MMC sub system",
- "mmc read <device num> addr blk# cnt [partition]\n"
- "mmc write <device num> addr blk# cnt [partition]\n"
- "mmc rescan <device num>\n"
"mmc list - lists available devices");
#endif
+++ /dev/null
-/*
- * Copyright (C) 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx31-regs.h>
-
-.section ".text.load", "x"
-
-.macro wait_op_done
-1: ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
- beq 1b
-.endm
-
-data_output:
- strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
- mov r3, #FDO_PAGE_SPARE_VAL
- strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- wait_op_done
- bx lr
-
-send_addr:
- strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
- mov r3, #NAND_FLASH_CONFIG2_FADD_EN
- strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- wait_op_done
- bx lr
-
-send_cmd:
- strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
- mov r3, #NAND_FLASH_CONFIG2_FCMD_EN
- strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- wait_op_done
- bx lr
-
-
-nand_read_page:
-
- mov r7, lr
-
- mov r3, #0x0
- /* send command */
- bl send_cmd
- /* 5 cycles address input */
- mov r3, #0x0
- bl send_addr
- mov r3, #0x0
- bl send_addr
- mov r3, r0
- bl send_addr
- mov r3, #0x0
- bl send_addr
- mov r3, #0x0
- bl send_addr
- /* confirm read */
- mov r3, #0x30
- bl send_cmd
- /* data output */
- mov r8, #0x0
- mov r4, #0x4
-1:
- bl data_output
- add r8, r8, #0x01
- cmp r8, r4
- bne 1b
- ldrh r3, [r12, #ECC_STATUS_RESULT_REG_OFF]
- tst r3, #0x0a
- bne .
- mov pc, r7
-
-.global mxc_nand_load
-mxc_nand_load:
-
- /* Copy image from flash to SDRAM first */
- mov r0, #NFC_BASE_ADDR
- add r12, r0, #0xE00 /* register */
- add r2, r0, #0x800 /* 2K */
- ldr r1, __TEXT_BASE
-
-1: ldmia r0!, {r3-r10}
- stmia r1!, {r3-r10}
- cmp r0, r2
- blo 1b
- /* Jump to SDRAM */
- ldr r1, =0x0FFF
- and r0, pc, r1 /* offset of pc */
- ldr r1, __TEXT_BASE
- add r1, r1, #0x10
- add pc, r0, r1
- nop
- nop
- nop
- nop
-
-nand_copy_block:
-
- /* wait for boot complete */
-4:
- ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- tst r3, #0x8000
- beq 4b
-
- /* unlock buffer and blocks */
- mov r3, #0x02
- strh r3, [r12, #NFC_CONFIGURATION_REG_OFF]
- mov r3, #0x0
- strh r3, [r12, #UNLOCK_START_BLK_ADD_REG_OFF]
- mov r3, #0x800
- strh r3, [r12, #UNLOCK_END_BLK_ADD_REG_OFF]
- mov r3, #0x04
- strh r3, [r12, #NF_WR_PROT_REG_OFF]
- mov r3, #0x10
- strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
-
- /* read 1 block, 256K */
- mov r0, #0x01 /* page offset */
- ldr r11, __TEXT_BASE
- add r11, r11, #0x800
-
- mov r1, #NFC_BASE_ADDR
- add r2, r1, #0x800
-2:
- bl nand_read_page /* r0, r1, r2, r11 has been used */
- /* copy data from internal buffer */
-3: ldmia r1!, {r3-r10}
- stmia r11!, {r3-r10}
- cmp r1, r2
- blo 3b
-
- add r0, r0, #0x01
- cmp r0, #0x80
- mov r1, #NFC_BASE_ADDR
- bne 2b
-
- /* set pc to _set_env */
- ldr r11, __TEXT_BASE
- ldr r1, =0x7FF
- /* correct the lr */
- and r13, r13, r1
- add r13, r13, r11
- mov pc, r13
-
-__TEXT_BASE:
- .word TEXT_BASE
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(SOC).a
-
-COBJS = timer.o serial.o generic.o iomux.o
-SOBJS = mxc_nand_load.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all: $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__
-#define __CPU_ARM1136_MX35_CRM_REGS_H__
-
-/* Register bit definitions */
-#define MXC_CCM_CCMR_WFI (1 << 30)
-#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29)
-#define MXC_CCM_CCMR_VSTBY (1 << 28)
-#define MXC_CCM_CCMR_WBEN (1 << 27)
-#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20
-#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20)
-#define MXC_CCM_CCMR_ROMW_OFFSET 18
-#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18)
-#define MXC_CCM_CCMR_RAMW_OFFSET 21
-#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21)
-#define MXC_CCM_CCMR_LPM_OFFSET 14
-#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
-#define MXC_CCM_CCMR_UPE (1 << 9)
-#define MXC_CCM_CCMR_MPE (1 << 3)
-
-#define MXC_CCM_PDR0_PER_SEL (1 << 26)
-#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23)
-#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20
-#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20)
-#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16
-#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16)
-#define MXC_CCM_PDR0_CKIL_SEL (1 << 15)
-#define MXC_CCM_PDR0_PER_PODF_OFFSET 12
-#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12)
-#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9
-#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9)
-#define MXC_CCM_PDR0_AUTO_CON 0x1
-
-#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28
-#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28)
-#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22
-#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22)
-#define MXC_CCM_PDR1_MSHC_M_U (1 << 7)
-
-#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27
-#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27)
-#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24
-#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24)
-#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19
-#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19)
-#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16
-#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16)
-#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8
-#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8)
-#define MXC_CCM_PDR2_CSI_M_U (1 << 7)
-#define MXC_CCM_PDR2_SSI_M_U (1 << 6)
-#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0
-#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F)
-
-#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29
-#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29)
-#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23
-#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23)
-#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22)
-#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19
-#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19)
-#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16
-#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16)
-#define MXC_CCM_PDR3_UART_M_U (1 << 15)
-#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11
-#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11)
-#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8
-#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8)
-#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6)
-#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3
-#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3)
-#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0
-#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7)
-
-#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28
-#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28)
-#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25
-#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25)
-#define MXC_CCM_PDR4_USB_PODF_OFFSET 22
-#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22)
-#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19
-#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19)
-#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16
-#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16)
-#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13
-#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13)
-#define MXC_CCM_PDR4_UART_PODF_OFFSET 10
-#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10)
-#define MXC_CCM_PDR4_USB_M_U (1 << 9)
-
-/* Bit definitions for RCSR */
-#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29)
-#define MXC_CCM_RCSR_BUS_16BIT (1 << 29)
-#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27)
-#define MXC_CCM_RCSR_PAGE_512 (0 << 27)
-#define MXC_CCM_RCSR_PAGE_2K (1 << 27)
-#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27)
-#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27)
-#define MXC_CCM_RCSR_SOFT_RESET (1 << 15)
-#define MXC_CCM_RCSR_NF16B (1 << 14)
-#define MXC_CCM_RCSR_NFC_4K (1 << 9)
-#define MXC_CCM_RCSR_NFC_FMS (1 << 8)
-
-/* Bit definitions for both MCU, PERIPHERAL PLL control registers */
-#define MXC_CCM_PCTL_BRM 0x80000000
-#define MXC_CCM_PCTL_PD_OFFSET 26
-#define MXC_CCM_PCTL_PD_MASK (0xF << 26)
-#define MXC_CCM_PCTL_MFD_OFFSET 16
-#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16)
-#define MXC_CCM_PCTL_MFI_OFFSET 10
-#define MXC_CCM_PCTL_MFI_MASK (0xF << 10)
-#define MXC_CCM_PCTL_MFN_OFFSET 0
-#define MXC_CCM_PCTL_MFN_MASK 0x3FF
-
-/* Bit definitions for Audio clock mux register*/
-#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12
-#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12)
-#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8
-#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8)
-#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4
-#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4)
-#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0
-#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0)
-
-/* Bit definitions for Clock gating Register*/
-#define MXC_CCM_CGR0_ASRC_OFFSET 0
-#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0)
-#define MXC_CCM_CGR0_ATA_OFFSET 2
-#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2)
-#define MXC_CCM_CGR0_CAN1_OFFSET 6
-#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6)
-#define MXC_CCM_CGR0_CAN2_OFFSET 8
-#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8)
-#define MXC_CCM_CGR0_CSPI1_OFFSET 10
-#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10)
-#define MXC_CCM_CGR0_CSPI2_OFFSET 12
-#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12)
-#define MXC_CCM_CGR0_ECT_OFFSET 14
-#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14)
-#define MXC_CCM_CGR0_EMI_OFFSET 18
-#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18)
-#define MXC_CCM_CGR0_EPIT1_OFFSET 20
-#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20)
-#define MXC_CCM_CGR0_EPIT2_OFFSET 22
-#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22)
-#define MXC_CCM_CGR0_ESAI_OFFSET 24
-#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24)
-#define MXC_CCM_CGR0_ESDHC1_OFFSET 26
-#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26)
-#define MXC_CCM_CGR0_ESDHC2_OFFSET 28
-#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28)
-#define MXC_CCM_CGR0_ESDHC3_OFFSET 30
-#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30)
-
-#define MXC_CCM_CGR1_FEC_OFFSET 0
-#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0)
-#define MXC_CCM_CGR1_GPIO1_OFFSET 2
-#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2)
-#define MXC_CCM_CGR1_GPIO2_OFFSET 4
-#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4)
-#define MXC_CCM_CGR1_GPIO3_OFFSET 6
-#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6)
-#define MXC_CCM_CGR1_GPT_OFFSET 8
-#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8)
-#define MXC_CCM_CGR1_I2C1_OFFSET 10
-#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10)
-#define MXC_CCM_CGR1_I2C2_OFFSET 12
-#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12)
-#define MXC_CCM_CGR1_I2C3_OFFSET 14
-#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14)
-#define MXC_CCM_CGR1_IOMUXC_OFFSET 16
-#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16)
-#define MXC_CCM_CGR1_IPU_OFFSET 18
-#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18)
-#define MXC_CCM_CGR1_KPP_OFFSET 20
-#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20)
-#define MXC_CCM_CGR1_MLB_OFFSET 22
-#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22)
-#define MXC_CCM_CGR1_MSHC_OFFSET 24
-#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24)
-#define MXC_CCM_CGR1_OWIRE_OFFSET 26
-#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26)
-#define MXC_CCM_CGR1_PWM_OFFSET 28
-#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28)
-#define MXC_CCM_CGR1_RNGC_OFFSET 30
-#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30)
-
-#define MXC_CCM_CGR2_RTC_OFFSET 0
-#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0)
-#define MXC_CCM_CGR2_RTIC_OFFSET 2
-#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2)
-#define MXC_CCM_CGR2_SCC_OFFSET 4
-#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4)
-#define MXC_CCM_CGR2_SDMA_OFFSET 6
-#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6)
-#define MXC_CCM_CGR2_SPBA_OFFSET 8
-#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8)
-#define MXC_CCM_CGR2_SPDIF_OFFSET 10
-#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10)
-#define MXC_CCM_CGR2_SSI1_OFFSET 12
-#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12)
-#define MXC_CCM_CGR2_SSI2_OFFSET 14
-#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14)
-#define MXC_CCM_CGR2_UART1_OFFSET 16
-#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16)
-#define MXC_CCM_CGR2_UART2_OFFSET 18
-#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18)
-#define MXC_CCM_CGR2_UART3_OFFSET 20
-#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20)
-#define MXC_CCM_CGR2_USBOTG_OFFSET 22
-#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22)
-#define MXC_CCM_CGR2_WDOG_OFFSET 24
-#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24)
-#define MXC_CCM_CGR2_MAX_OFFSET 26
-#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26)
-#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26)
-#define MXC_CCM_CGR2_AUDMUX_OFFSET 30
-#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30)
-
-#define MXC_CCM_CGR3_CSI_OFFSET 0
-#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0)
-#define MXC_CCM_CGR3_IIM_OFFSET 2
-#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2)
-#define MXC_CCM_CGR3_GPU2D_OFFSET 4
-#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4)
-
-#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F
-#define MXC_CCM_COSR_CLKOSEL_OFFSET 0
-#define MXC_CCM_COSR_CLKOEN (1 << 5)
-#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6)
-#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 10)
-#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 10
-#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 13)
-#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 13
-#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16)
-#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16
-#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18)
-#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18
-#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20)
-#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20
-#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22)
-#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22
-#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24)
-#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26)
-#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26
-
-#endif /* __CPU_ARM1136_MX35_CRM_REGS_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/mx35.h>
-#include <asm/cache-cp15.h>
-#include "crm_regs.h"
-
-#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
-#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
-#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF)
-#define CLK_CODE_PATH(c) ((c) & 0xFF)
-
-#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
-
-static int g_clk_mux_auto[8] = {
- CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
- CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
-};
-
-static int g_clk_mux_consumer[16] = {
- CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
- -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
- CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
- -1, -1, CLK_CODE(4, 2, 0), -1,
-};
-
-static int hsp_div_table[3][16] = {
- {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
- {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
- {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
-};
-
-static u32 __get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
-{
- int *pclk_mux;
- if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
- pclk_mux = g_clk_mux_consumer +
- ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
- MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
- } else {
- pclk_mux = g_clk_mux_auto +
- ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
- MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
- }
-
- if ((*pclk_mux) == -1)
- return -1;
-
- if (fi && fd) {
- if (!CLK_CODE_PATH(*pclk_mux)) {
- *fi = *fd = 1;
- return CLK_CODE_ARM(*pclk_mux);
- }
- if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
- *fi = 3;
- *fd = 4;
- } else {
- *fi = 2;
- *fd = 3;
- }
- }
- return CLK_CODE_ARM(*pclk_mux);
-}
-
-static int __get_ahb_div(u32 pdr0)
-{
- int *pclk_mux;
-
- pclk_mux = g_clk_mux_consumer +
- ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
- MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
-
- if ((*pclk_mux) == -1)
- return -1;
-
- return CLK_CODE_AHB(*pclk_mux);
-}
-
-static u32 __decode_pll(u32 reg, u32 infreq)
-{
- u32 mfi = (reg >> 10) & 0xf;
- u32 mfn = reg & 0x3f;
- u32 mfd = (reg >> 16) & 0x3f;
- u32 pd = (reg >> 26) & 0xf;
-
- mfi = mfi <= 5 ? 5 : mfi;
- mfd += 1;
- pd += 1;
-
- return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
-}
-
-static u32 __get_mcu_main_clk(void)
-{
- u32 arm_div = 0, fi = 0, fd = 0;
- arm_div = __get_arm_div(__REG(CCM_BASE_ADDR + CLKCTL_PDR0), &fi, &fd);
- fi *=
- __decode_pll(__REG(MCU_PLL),
- CONFIG_MX35_HCLK_FREQ);
- return fi / (arm_div * fd);
-}
-
-static u32 __get_ipg_clk(void)
-{
- u32 freq = __get_mcu_main_clk();
- u32 pdr0 = __REG(CCM_BASE_ADDR + CLKCTL_PDR0);
-
- return freq / (__get_ahb_div(pdr0) * 2);
-}
-
-static u32 __get_ipg_per_clk(void)
-{
- u32 freq = __get_mcu_main_clk();
- u32 pdr0 = __REG(CCM_BASE_ADDR + CLKCTL_PDR0);
- u32 pdr4 = __REG(CCM_BASE_ADDR + CLKCTL_PDR4);
- u32 div;
- if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
- div = (CCM_GET_DIVIDER(pdr4,
- MXC_CCM_PDR4_PER0_PRDF_MASK,
- MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) *
- (CCM_GET_DIVIDER(pdr4,
- MXC_CCM_PDR4_PER0_PODF_MASK,
- MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
- } else {
- div = CCM_GET_DIVIDER(pdr0,
- MXC_CCM_PDR0_PER_PODF_MASK,
- MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
- freq /= __get_ahb_div(pdr0);
- }
- return freq / div;
-}
-
-static u32 __get_uart_clk(void)
-{
- u32 freq;
- u32 pdr4 = __REG(CCM_BASE_ADDR + CLKCTL_PDR4);
-
- if (__REG(CCM_BASE_ADDR + CLKCTL_PDR3) & MXC_CCM_PDR3_UART_M_U)
- freq = __get_mcu_main_clk();
- else
- freq = __decode_pll(__REG(PER_PLL),
- CONFIG_MX35_HCLK_FREQ);
- freq /= ((CCM_GET_DIVIDER(pdr4,
- MXC_CCM_PDR4_UART_PRDF_MASK,
- MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) *
- (CCM_GET_DIVIDER(pdr4,
- MXC_CCM_PDR4_UART_PODF_MASK,
- MXC_CCM_PDR4_UART_PODF_OFFSET) + 1));
- return freq;
-}
-
-unsigned int mxc_get_main_clock(enum mxc_main_clocks clk)
-{
- u32 nfc_pdf, hsp_podf;
- u32 pll, ret_val = 0, usb_prdf, usb_podf;
-
- u32 reg = readl(CCM_BASE_ADDR + CLKCTL_PDR0);
- u32 reg4 = readl(CCM_BASE_ADDR + CLKCTL_PDR4);
-
- reg |= 0x1;
-
- switch (clk) {
- case CPU_CLK:
- ret_val = __get_mcu_main_clk();
- break;
- case AHB_CLK:
- ret_val = __get_mcu_main_clk();
- break;
- case HSP_CLK:
- if (reg & CLKMODE_CONSUMER) {
- hsp_podf = (reg >> 20) & 0x3;
- pll = __get_mcu_main_clk();
- hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
- if(hsp_podf > 0 ) {
- ret_val = pll / hsp_podf;
- } else {
- puts("mismatch HSP with ARM clock setting\n");
- ret_val = 0;
- }
- } else {
- ret_val = __get_mcu_main_clk();
- }
- break;
- case IPG_CLK:
- ret_val = __get_ipg_clk();;
- break;
- case IPG_PER_CLK:
- ret_val = __get_ipg_per_clk();
- break;
- case NFC_CLK:
- nfc_pdf = (reg4 >> 28) & 0xF;
- pll = __get_mcu_main_clk();
- /* AHB/nfc_pdf */
- ret_val = pll / (nfc_pdf + 1);
- break;
- case USB_CLK:
- usb_prdf = (reg4 >> 25) & 0x7;
- usb_podf = (reg4 >> 22) & 0x7;
- if (reg4 & 0x200)
- pll = __get_mcu_main_clk();
- else
- pll = __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ);
-
- ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
- break;
- default:
- printf("Unknown clock: %d\n", clk);
- break;
- }
-
- return ret_val;
-}
-unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk)
-{
- u32 ret_val = 0, pdf, pre_pdf, clk_sel;
- u32 mpdr2 = readl(CCM_BASE_ADDR + CLKCTL_PDR2);
- u32 mpdr3 = readl(CCM_BASE_ADDR + CLKCTL_PDR3);
- u32 mpdr4 = readl(CCM_BASE_ADDR + CLKCTL_PDR4);
-
- switch (clk) {
- case UART1_BAUD:
- case UART2_BAUD:
- case UART3_BAUD:
- clk_sel = mpdr3 & (1 << 14);
- pre_pdf = (mpdr4 >> 13) & 0x7;
- pdf = (mpdr4 >> 10) & 0x7;
- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1));
- break;
- case SSI1_BAUD:
- pre_pdf = (mpdr2 >> 24) & 0x7;
- pdf = mpdr2 & 0x3F;
- clk_sel = mpdr2 & ( 1 << 6);
- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1));
- break;
- case SSI2_BAUD:
- pre_pdf = (mpdr2 >> 27) & 0x7;
- pdf = (mpdr2 >> 8)& 0x3F;
- clk_sel = mpdr2 & ( 1 << 6);
- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1));
- break;
- case CSI_BAUD:
- clk_sel = mpdr2 & (1 << 7);
- pre_pdf = (mpdr2 >> 16) & 0x7;
- pdf = (mpdr2 >> 19) & 0x7;
- ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1));
- break;
- case MSHC_CLK:
- pre_pdf = readl(CCM_BASE_ADDR + CLKCTL_PDR1);
- clk_sel = (pre_pdf & 0x80);
- pdf = (pre_pdf >> 22) & 0x3F;
- pre_pdf = (pre_pdf >> 28) & 0x7;
- ret_val = ((clk_sel != 0)? mxc_get_main_clock(CPU_CLK) :
- __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1));
- break;
- case ESDHC1_CLK:
- clk_sel = mpdr3 & 0x40;
- pre_pdf = mpdr3&0x7;
- pdf = (mpdr3>>3)&0x7;
- ret_val = ((clk_sel != 0)? mxc_get_main_clock(CPU_CLK) :
- __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1));
- break;
- case ESDHC2_CLK:
- clk_sel = mpdr3 & 0x40;
- pre_pdf = (mpdr3 >> 8)&0x7;
- pdf = (mpdr3 >> 11)&0x7;
- ret_val = ((clk_sel != 0)? mxc_get_main_clock(CPU_CLK) :
- __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1));
- break;
- case ESDHC3_CLK:
- clk_sel = mpdr3 & 0x40;
- pre_pdf = (mpdr3 >> 16)&0x7;
- pdf = (mpdr3 >> 19)&0x7;
- ret_val = ((clk_sel != 0)? mxc_get_main_clock(CPU_CLK) :
- __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1));
- break;
- case SPDIF_CLK:
- clk_sel = mpdr3 & 0x400000;
- pre_pdf = (mpdr3 >> 29)&0x7;
- pdf = (mpdr3 >> 23)&0x3F;
- ret_val = ((clk_sel != 0)? mxc_get_main_clock(CPU_CLK) :
- __decode_pll(__REG(PER_PLL), CONFIG_MX35_HCLK_FREQ)) / ((pre_pdf + 1) * (pdf + 1));
- break;
- default:
- printf("%s(): This clock: %d not supported yet \n",
- __FUNCTION__, clk);
- break;
- }
-
- return ret_val;
-}
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
- switch (clk) {
- case MXC_ARM_CLK:
- return __get_mcu_main_clk();
- case MXC_AHB_CLK:
- break;
- case MXC_IPG_CLK:
- return __get_ipg_clk();
- case MXC_IPG_PERCLK:
- return __get_ipg_per_clk();
- case MXC_UART_CLK:
- return __get_uart_clk();
- case MXC_ESDHC_CLK:
- return mxc_get_peri_clock(ESDHC1_CLK);
- case MXC_USB_CLK:
- return mxc_get_main_clock(USB_CLK);
- }
- return -1;
-}
-
-void mxc_dump_clocks(void)
-{
- u32 cpufreq = __get_mcu_main_clk();
- printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
- printf("ipg clock : %dHz\n", __get_ipg_clk());
- printf("ipg per clock : %dHz\n", __get_ipg_per_clk());
- printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- printf("CPU: Freescale i.MX35 at %d MHz\n",
- __get_mcu_main_clk() / 1000000);
- /* mxc_dump_clocks(); */
- return 0;
-}
-#endif
-
-#if defined(CONFIG_MXC_FEC)
-extern int mxc_fec_initialize(bd_t *bis);
-extern void mxc_fec_set_mac_from_env(char *mac_addr);
-#endif
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
- int rc = -ENODEV;
-
-#if defined(CONFIG_MXC_FEC)
- rc = mxc_fec_initialize(bis);
-#endif
-
- return rc;
-}
-
-#if defined(CONFIG_ARCH_CPU_INIT)
-int arch_cpu_init(void)
-{
- icache_enable();
- dcache_enable();
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/*!
- * @defgroup GPIO_MX35 Board GPIO and Muxing Setup
- * @ingroup MSL_MX35
- */
-/*!
- * @file mach-mx35/iomux.c
- *
- * @brief I/O Muxing control functions
- *
- * @ingroup GPIO_MX35
- */
-#include <common.h>
-#include <asm/arch/mx35.h>
-#include <asm/arch/mx35_pins.h>
-#include <asm/arch/iomux.h>
-
-/*!
- * IOMUX register (base) addresses
- */
-enum iomux_reg_addr {
- IOMUXGPR = IOMUXC_BASE_ADDR,
- /*!< General purpose */
- IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4,
- /*!< MUX control */
- IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324,
- /*!< last MUX control register */
- IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328,
- /*!< Pad control */
- IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794,
- /*!< last Pad control register */
- IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC,
- /*!< input select register */
- IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4,
- /*!< last input select register */
-};
-
-#define MUX_PIN_NUM_MAX \
- (((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1)
-#define MUX_INPUT_NUM_MUX \
- (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1)
-
-#define PIN_TO_IOMUX_INDEX(pin) ((PIN_TO_IOMUX_PAD(pin) - 0x328) >> 2)
-
-/*!
- * This function is used to configure a pin through the IOMUX module.
- * FIXED ME: for backward compatible. Will be static function!
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @param cfg an output function as defined in \b #iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
- if (mux_reg != NON_MUX_I) {
- mux_reg += IOMUXGPR;
- __REG(mux_reg) = cfg;
- }
-
- return 0;
-}
-
-/*!
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param cfg an input function as defined in \b #iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- int ret = iomux_config_mux(pin, cfg);
- return ret;
-}
-
-/*!
- * Release ownership for an IO pin
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param cfg an input function as defined in \b #iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*!
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @param config the ORed value of elements defined in \b #iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
- u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin);
-
- __REG(pad_reg) = config;
-}
-
-/*!
- * This function enables/disables the general purpose function for a particular
- * signal.
- *
- * @param gp one signal as defined in \b #iomux_gp_func_t
- * @param en \b #true to enable; \b #false to disable
- */
-void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en)
-{
- u32 l;
-
- l = __REG(IOMUXGPR);
- if (en)
- l |= gp;
- else
- l &= ~gp;
-
- __REG(IOMUXGPR) = l;
-}
-
-/*!
- * This function configures input path.
- *
- * @param input index of input select register as defined in \b
- * #iomux_input_select_t
- * @param config the binary value of elements defined in \b
- * #iomux_input_config_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
-{
- u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
-
- __REG(reg) = config;
-}
+++ /dev/null
-/*
- * (C) Copyright 2008 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx35.h>
-
-.macro nfc_cmd_input
- strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
- mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
- strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- bl do_wait_op_done
-.endm // nfc_cmd_input
-
-.macro do_addr_input
- and r3, r3, #0xFF
- strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
- mov r3, #NAND_FLASH_CONFIG2_FADD_EN
- strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- bl do_wait_op_done
-.endm // do_addr_input
-
-.section ".text.load", "x"
-.globl mxc_nand_load
-mxc_nand_load:
- ldr r2, U_BOOT_NAND_START
-1: ldmia r0!, {r3-r10}
- stmia r2!, {r3-r10}
- cmp r0, r1
- blo 1b
-
- ldr r1, CONST_0X0FFF
- ldr r2, U_BOOT_NAND_START
- and lr, lr, r1
- add lr, lr, r2
- and r12, r12, r1
- add r12, r12, r2
- add r2, r2, #0x8
- and r0, pc, r1
- add pc, r0, r2
- nop
- nop
- nop
- nop
- nop
- adr r0, SAVE_REGS
- str r12, [r0]
- str lr, [r0, #4]
-Copy_Main:
- mov r0, #NFC_BASE_ADDR
- add r12, r0, #0x1E00
- ldrh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
- orr r3, r3, #1
-
- /* Setting NFC */
- ldr r7, =CCM_BASE_ADDR
- ldr r1, [r7, #CLKCTL_RCSR]
- /*BUS WIDTH setting*/
- tst r1, #0x20000000
- orrne r1, r1, #0x4000
- biceq r1, r1, #0x4000
-
- /*4K PAGE*/
- tst r1, #0x10000000
- orrne r1, r1, #0x200
- bne 1f
- /*2K PAGE*/
- bic r1, r1, #0x200
- tst r1, #0x08000000
- orrne r1, r1, #0x100 /*2KB page size*/
- biceq r1, r1, #0x100 /*512B page size*/
- movne r2, #32 /*64 bytes*/
- moveq r2, #8 /*16 bytes*/
- b NAND_setup
-1:
- tst r1, #0x08000000
- bicne r3, r3, #1 /*Enable 8bit ECC mode*/
- movne r2, #109 /*218 bytes*/
- moveq r2, #64 /*128 bytes*/
-NAND_setup:
- str r1, [r7, #CLKCTL_RCSR]
- strh r2, [r12, #ECC_RSLT_SPARE_AREA_REG_OFF]
- strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
-
- //unlock internal buffer
- mov r3, #0x2
- strh r3, [r12, #NFC_CONFIGURATION_REG_OFF]
- //unlock nand device
- mov r3, #0
- strh r3, [r12, #UNLOCK_START_BLK_ADD_REG_OFF]
- sub r3, r3, #1
- strh r3, [r12, #UNLOCK_END_BLK_ADD_REG_OFF]
- mov r3, #4
- strh r3, [r12, #NF_WR_PROT_REG_OFF]
-
- /* r0: NFC base address. RAM buffer base address. [constantly]
- * r1: starting flash address to be copied. [constantly]
- * r2: page size. [Doesn't change]
- * r3: used as argument.
- * r11: starting SDRAM address for copying. [Updated constantly].
- * r12: NFC register base address. [constantly].
- * r13: end of SDRAM address for copying. [Doesn't change].
- */
-
- mov r1, #0x1000
- ldr r3, [r7, #CLKCTL_RCSR]
- tst r3, #0x200
- movne r2, #0x1000
- bne 1f
- tst r3, #0x100
- mov r1, #0x800 /*Strange Why is not 4K offset*/
- movne r2, #0x800
- moveq r2, #0x200
-1: /*Update the indicator of copy area */
- ldr r11, U_BOOT_NAND_START
- add r13, r11, #0x00088000; /*512K + 32K*/
- add r11, r11, r1
-
-Nfc_Read_Page:
- mov r3, #0x0
- nfc_cmd_input
-
- cmp r2, #0x800
- bhi nfc_addr_ops_4kb
- beq nfc_addr_ops_2kb
-
- mov r3, r1
- do_addr_input //1st addr cycle
- mov r3, r1, lsr #9
- do_addr_input //2nd addr cycle
- mov r3, r1, lsr #17
- do_addr_input //3rd addr cycle
- mov r3, r1, lsr #25
- do_addr_input //4th addr cycle
- b end_of_nfc_addr_ops
-
-nfc_addr_ops_2kb:
- mov r3, #0
- do_addr_input //1st addr cycle
- mov r3, #0
- do_addr_input //2nd addr cycle
- mov r3, r1, lsr #11
- do_addr_input //3rd addr cycle
- mov r3, r1, lsr #19
- do_addr_input //4th addr cycle
- mov r3, r1, lsr #27
- do_addr_input //5th addr cycle
-
- mov r3, #0x30
- nfc_cmd_input
- b end_of_nfc_addr_ops
-
-nfc_addr_ops_4kb:
- mov r3, #0
- do_addr_input //1st addr cycle
- mov r3, #0
- do_addr_input //2nd addr cycle
- mov r3, r1, lsr #12
- do_addr_input //3rd addr cycle
- mov r3, r1, lsr #20
- do_addr_input //4th addr cycle
- mov r3, r1, lsr #27
- do_addr_input //5th addr cycle
-
- mov r3, #0x30
- nfc_cmd_input
-
-end_of_nfc_addr_ops:
- mov r8, #0
- bl nfc_data_output
- bl do_wait_op_done
- // Check if x16/2kb page
- cmp r2, #0x800
- bhi nfc_addr_data_output_done_4k
- beq nfc_addr_data_output_done_2k
- beq nfc_addr_data_output_done_512
-
- // check for bad block
- // mov r3, r1, lsl #(32-17) // get rid of block number
- // cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
- b nfc_addr_data_output_done
-
-nfc_addr_data_output_done_4k:
-//TODO
- b nfc_addr_data_output_done
-
-nfc_addr_data_output_done_2k:
- // end of 4th
- // check for bad block
- //TODO mov r3, r1, lsl #(32-17) // get rid of block number
- // cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
- b nfc_addr_data_output_done
-
-nfc_addr_data_output_done_512:
- // check for bad block
- // TODO mov r3, r1, lsl #(32-5-9) // get rid of block number
- // TODO cmp r3, #(512 << (32-5-9)) // check if not page 0 or 1
-
-nfc_addr_data_output_done:
-Copy_Good_Blk:
- //copying page
- add r2, r2, #NFC_BASE_ADDR
-1: ldmia r0!, {r3-r10}
- stmia r11!, {r3-r10}
- cmp r0, r2
- blo 1b
- sub r2, r2, #NFC_BASE_ADDR
-
- cmp r11, r13
- bge NAND_Copy_Main_done
- // Check if x16/2kb page
- add r1, r1, r2
- mov r0, #NFC_BASE_ADDR
- b Nfc_Read_Page
-
-NAND_Copy_Main_done:
- adr r0, SAVE_REGS
- ldr r12, [r0]
- ldr lr, [r0, #4]
- mov pc, lr
-
-do_wait_op_done:
-1:
- ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
- beq 1b
- bx lr // do
-
-nfc_data_output:
- ldrh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
- orr r3, r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
- strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
-
- strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
-
- mov r3, #FDO_PAGE_SPARE_VAL
- strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- bx lr
-
-U_BOOT_NAND_START: .word TEXT_BASE
-CONST_0X0FFF: .word 0x0FFF
-SAVE_REGS: .word 0x0
- .word 0x0
+++ /dev/null
-/*
- * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
- *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-
-#if defined CONFIG_MX35_UART
-
-#include <asm/arch/mx35.h>
-
-#define __REG(x) (*((volatile u32 *)(x)))
-
-#define UART_PHYS CONFIG_MX35_UART
-
-/* Register definitions */
-#define URXD 0x0 /* Receiver Register */
-#define UTXD 0x40 /* Transmitter Register */
-#define UCR1 0x80 /* Control Register 1 */
-#define UCR2 0x84 /* Control Register 2 */
-#define UCR3 0x88 /* Control Register 3 */
-#define UCR4 0x8c /* Control Register 4 */
-#define UFCR 0x90 /* FIFO Control Register */
-#define USR1 0x94 /* Status Register 1 */
-#define USR2 0x98 /* Status Register 2 */
-#define UESC 0x9c /* Escape Character Register */
-#define UTIM 0xa0 /* Escape Timer Register */
-#define UBIR 0xa4 /* BRM Incremental Register */
-#define UBMR 0xa8 /* BRM Modulator Register */
-#define UBRC 0xac /* Baud Rate Count Register */
-#define UTS 0xb4 /* UART Test Register (mx31) */
-
-/* UART Control Register Bit Fields.*/
-#define URXD_CHARRDY (1<<15)
-#define URXD_ERR (1<<14)
-#define URXD_OVRRUN (1<<13)
-#define URXD_FRMERR (1<<12)
-#define URXD_BRK (1<<11)
-#define URXD_PRERR (1<<10)
-#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
-#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
-#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
-#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
-#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
-#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
-#define UCR1_IREN (1<<7) /* Infrared interface enable */
-#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
-#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
-#define UCR1_SNDBRK (1<<4) /* Send break */
-#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
-#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
-#define UCR1_DOZE (1<<1) /* Doze */
-#define UCR1_UARTEN (1<<0) /* UART enabled */
-#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
-#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
-#define UCR2_CTSC (1<<13) /* CTS pin control */
-#define UCR2_CTS (1<<12) /* Clear to send */
-#define UCR2_ESCEN (1<<11) /* Escape enable */
-#define UCR2_PREN (1<<8) /* Parity enable */
-#define UCR2_PROE (1<<7) /* Parity odd/even */
-#define UCR2_STPB (1<<6) /* Stop */
-#define UCR2_WS (1<<5) /* Word size */
-#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
-#define UCR2_TXEN (1<<2) /* Transmitter enabled */
-#define UCR2_RXEN (1<<1) /* Receiver enabled */
-#define UCR2_SRST (1<<0) /* SW reset */
-#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
-#define UCR3_PARERREN (1<<12) /* Parity enable */
-#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
-#define UCR3_DSR (1<<10) /* Data set ready */
-#define UCR3_DCD (1<<9) /* Data carrier detect */
-#define UCR3_RI (1<<8) /* Ring indicator */
-#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
-#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
-#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
-#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
-#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
-#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
-#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
-#define UCR3_BPEN (1<<0) /* Preset registers enable */
-#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
-#define UCR4_INVR (1<<9) /* Inverted infrared reception */
-#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
-#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
-#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
-#define UCR4_IRSC (1<<5) /* IR special case */
-#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
-#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
-#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
-#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
-#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
-#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
-#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
-#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
-#define USR1_RTSS (1<<14) /* RTS pin status */
-#define USR1_TRDY (1<<13)/* Transmitter ready interrupt/dma flag */
-#define USR1_RTSD (1<<12) /* RTS delta */
-#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
-#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
-#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
-#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
-#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
-#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
-#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
-#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
-#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
-#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
-#define USR2_IDLE (1<<12) /* Idle condition */
-#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
-#define USR2_WAKE (1<<7) /* Wake */
-#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
-#define USR2_TXDC (1<<3) /* Transmitter complete */
-#define USR2_BRCD (1<<2) /* Break condition */
-#define USR2_ORE (1<<1) /* Overrun error */
-#define USR2_RDR (1<<0) /* Recv data ready */
-#define UTS_FRCPERR (1<<13) /* Force parity error */
-#define UTS_LOOP (1<<12) /* Loop tx and rx */
-#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
-#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
-#define UTS_TXFULL (1<<4) /* TxFIFO full */
-#define UTS_RXFULL (1<<3) /* RxFIFO full */
-#define UTS_SOFTRST (1<<0) /* Software reset */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void serial_setbrg(void)
-{
- u32 clk = mxc_get_clock(MXC_UART_CLK);
-
- if (!gd->baudrate)
- gd->baudrate = CONFIG_BAUDRATE;
- __REG(UART_PHYS + UFCR) = 0x4 << 7; /* divide input clock by 2 */
- __REG(UART_PHYS + UBIR) = 0xf;
- __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
-}
-
-int serial_getc(void)
-{
- while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
- ;
- return __REG(UART_PHYS + URXD);
-}
-
-void serial_putc(const char c)
-{
- __REG(UART_PHYS + UTXD) = c;
-
- /* wait for transmitter to be ready */
- while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
- ;
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-int serial_tstc(void)
-{
- /* If receive fifo is empty, return false */
- if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
- return 0;
- return 1;
-}
-
-void serial_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init(void)
-{
- __REG(UART_PHYS + UCR1) = 0x0;
- __REG(UART_PHYS + UCR2) = 0x0;
-
- while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST))
- ;
-
- __REG(UART_PHYS + UCR3) = 0x0704;
- __REG(UART_PHYS + UCR4) = 0x8000;
- __REG(UART_PHYS + UESC) = 0x002b;
- __REG(UART_PHYS + UTIM) = 0x0;
-
- __REG(UART_PHYS + UTS) = 0x0;
-
- serial_setbrg();
-
- __REG(UART_PHYS + UCR2) =
- UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
-
- __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
-
- return 0;
-}
-
-#endif /* CONFIG_MX35 */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mx35.h>
-
-/* General purpose timers registers */
-#define GPTCR __REG(GPT1_BASE_ADDR) /* Control register */
-#define GPTPR __REG(GPT1_BASE_ADDR + 0x4) /* Prescaler register */
-#define GPTSR __REG(GPT1_BASE_ADDR + 0x8) /* Status register */
-#define GPTCNT __REG(GPT1_BASE_ADDR + 0x24) /* Counter register */
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR (1<<15) /* Software reset */
-#define GPTCR_FRR (1<<9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */
-#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */
-#define GPTCR_TEN (1) /* Timer enable */
-#define GPTPR_VAL (66)
-
-static inline void setup_gpt()
-{
- int i;
- static int init_done;
-
- if (init_done)
- return;
-
- init_done = 1;
-
- /* setup GP Timer 1 */
- GPTCR = GPTCR_SWR;
- for (i = 0; i < 100; i++)
- GPTCR = 0; /* We have no udelay by now */
- GPTPR = GPTPR_VAL; /* 66Mhz / 66 */
- /* Freerun Mode, PERCLK1 input */
- GPTCR |= GPTCR_CLKSOURCE_IPG | GPTCR_TEN;
-}
-
-int timer_init(void)
-{
- setup_gpt();
-
- return 0;
-}
-
-void reset_timer_masked(void)
-{
- GPTCR = 0;
- /* Freerun Mode, PERCLK1 input */
- GPTCR = GPTCR_CLKSOURCE_IPG | GPTCR_TEN;
-}
-
-inline ulong get_timer_masked(void)
-{
- ulong val = GPTCNT;
-
- return val;
-}
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
- ulong tmp;
-
- tmp = get_timer_masked();
-
- if (tmp <= (base * 1000)) {
- /* Overflow */
- tmp += (0xffffffff - base);
- }
-
- return (tmp / 1000) - base;
-}
-
-void set_timer(ulong t)
-{
-}
-
-/* delay x useconds AND perserve advance timstamp value */
-/* GPTCNT is now supposed to tick 1 by 1 us. */
-void udelay(unsigned long usec)
-{
- ulong tmp;
-
- setup_gpt();
-
- tmp = get_timer_masked(); /* get current timestamp */
-
- /* if setting this forward will roll time stamp */
- if ((usec + tmp + 1) < tmp) {
- /* reset "advancing" timestamp to 0, set lastinc value */
- reset_timer_masked();
- } else {
- /* else, set advancing stamp wake up time */
- tmp += usec;
- }
-
- while (get_timer_masked() < tmp) /* loop till event */
- /*NOP*/;
-}
-
-void reset_cpu(ulong addr)
-{
- __REG16(WDOG_BASE_ADDR) = 4;
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(SOC).a
-
-COBJS = timer.o spi.o
-SOBJS = reset.o
-
-SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
-START := $(addprefix $(obj),$(START))
-
-all: $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-PLATFORM_CPPFLAGS += -march=armv5te
-PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)
\ No newline at end of file
+++ /dev/null
-/*
- * Processor reset for Freescale MX23 SoC.
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * -----------------------------------------------------
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-.globl reset_cpu
-reset_cpu:
- ldr r0, POWER_CHARGE
- mov r1, #0x0
- str r1, [r0]
- ldr r0, POWER_MINPWR
- str r1, [r0]
- ldr r0, CLKCTRL_RESET
- mov r1, #0x1
- str r1, [r0]
-_loop_forever:
- b _loop_forever
-
-POWER_MINPWR:
- .word 0x80044020
-POWER_CHARGE:
- .word 0x80044030
-CLKCTRL_RESET:
- .word 0x80040120
-
+++ /dev/null
-/*
- * Copyright (C) 2008 Embedded Alley Solutions Inc.
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * Freescale MX23 SSP/SPI driver
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <asm/arch/spi.h>
-
-#define SPI_NUM_BUSES 2
-#define SPI_NUM_SLAVES 3
-
-/* Initalized in spi_init() depending on SSP port configuration */
-static unsigned long ssp_bases[SPI_NUM_BUSES];
-
-/* Set in spi_set_cfg() depending on which SSP port is being used */
-static unsigned long ssp_base = SSP1_BASE;
-
-/*
- * Init SSP port: SSP1 (@bus = 0) or SSP2 (@bus == 1)
- */
-static void ssp_spi_init(unsigned int bus)
-{
- u32 spi_div;
- u32 val = 0;
-
- if (bus >= SPI_NUM_BUSES) {
- printf("SPI bus %d doesn't exist\n", bus);
- return;
- }
-
- ssp_base = ssp_bases[bus];
-
- /* Reset block */
-
- /* Clear SFTRST */
- REG_CLR(ssp_base + SSP_CTRL0, CTRL0_SFTRST);
- while (REG_RD(ssp_base + SSP_CTRL0) & CTRL0_SFTRST)
- ;
-
- /* Clear CLKGATE */
- REG_CLR(ssp_base + SSP_CTRL0, CTRL0_CLKGATE);
-
- /* Set SFTRST and wait until CLKGATE is set */
- REG_SET(ssp_base + SSP_CTRL0, CTRL0_SFTRST);
- while (!(REG_RD(ssp_base + SSP_CTRL0) & CTRL0_CLKGATE))
- ;
-
- /* Clear SFTRST and CLKGATE */
- REG_CLR(ssp_base + SSP_CTRL0, CTRL0_SFTRST);
- REG_CLR(ssp_base + SSP_CTRL0, CTRL0_CLKGATE);
-
- /*
- * Set CLK to desired value
- */
-
- spi_div = ((CONFIG_SSP_CLK>>1) + CONFIG_SPI_CLK - 1) / CONFIG_SPI_CLK;
- val = (2 << TIMING_CLOCK_DIVIDE) | ((spi_div - 1) << TIMING_CLOCK_RATE);
- REG_WR(ssp_base + SSP_TIMING, val);
-
- /* Set transfer parameters */
-
- /* Set SSP SPI Master mode and word length to 8 bit */
- REG_WR(ssp_base + SSP_CTRL1, WORD_LENGTH8 | SSP_MODE_SPI);
-
- /* Set BUS_WIDTH to 1 bit and XFER_COUNT to 1 byte */
- REG_WR(ssp_base + SSP_CTRL0,
- BUS_WIDTH_SPI1 | (0x1 << CTRL0_XFER_COUNT));
-
- /*
- * Set BLOCK_SIZE and BLOCK_COUNT to 0, so that XFER_COUNT
- * reflects number of bytes to send. Disalbe other bits as
- * well
- */
- REG_WR(ssp_base + SSP_CMD0, 0x0);
-}
-
-/*
- * Init SSP ports, must be called first and only once
- */
-void spi_init(void)
-{
-#ifdef CONFIG_SPI_SSP1
- ssp_bases[0] = SSP1_BASE;
- ssp_spi_init(0);
-#endif
-
-#ifdef CONFIG_SPI_SSP2
- ssp_bases[1] = SSP2_BASE;
- ssp_spi_init(1);
-#endif
-}
-
-void spi_set_cfg(unsigned int bus, unsigned int cs, unsigned long mode)
-{
- u32 clr_mask = 0;
- u32 set_mask = 0;
-
- if (bus >= SPI_NUM_BUSES || cs >= SPI_NUM_SLAVES) {
- printf("SPI device %d:%d doesn't exist", bus, cs);
- return;
- }
-
- if (ssp_bases[bus] == 0) {
- printf("SSP port %d isn't in SPI mode\n", bus + 1);
- return;
- }
-
- /* Set SSP port to use */
- ssp_base = ssp_bases[bus];
-
- /* Set phase and polarity: HW_SSP_CTRL1 */
- if (mode & SPI_PHASE)
- set_mask |= CTRL1_PHASE;
- else
- clr_mask |= CTRL1_PHASE;
-
- if (mode & SPI_POLARITY)
- set_mask |= CTRL1_POLARITY;
- else
- clr_mask |= CTRL1_POLARITY;
-
- REG_SET(ssp_base + SSP_CTRL1, set_mask);
- REG_CLR(ssp_base + SSP_CTRL1, clr_mask);
-
- /* Set SSn number: HW_SSP_CTRL0 */
- REG_CLR(ssp_base + SSP_CTRL0, SPI_CS_CLR_MASK);
-
- switch (cs) {
- case 0:
- set_mask = SPI_CS0;
- break;
- case 1:
- set_mask = SPI_CS1;
- break;
- case 2:
- set_mask = SPI_CS2;
- break;
- }
-
- REG_SET(ssp_base + SSP_CTRL0, set_mask);
-}
-
-/* Read single data byte */
-static unsigned char spi_read(void)
-{
- unsigned char b = 0;
-
- /* Set XFER_LENGTH to 1 */
- REG_CLR(ssp_base + SSP_CTRL0, 0xffff);
- REG_SET(ssp_base + SSP_CTRL0, 1);
-
- /* Enable READ mode */
- REG_SET(ssp_base + SSP_CTRL0, CTRL0_READ);
-
- /* Set RUN bit */
- REG_SET(ssp_base + SSP_CTRL0, CTRL0_RUN);
-
-
- /* Set transfer */
- REG_SET(ssp_base + SSP_CTRL0, CTRL0_DATA_XFER);
-
- while (REG_RD(ssp_base + SSP_STATUS) & STATUS_FIFO_EMPTY)
- ;
-
- /* Read data byte */
- b = REG_RD(ssp_base + SSP_DATA) & 0xff;
-
- /* Wait until RUN bit is cleared */
- while (REG_RD(ssp_base + SSP_CTRL0) & CTRL0_RUN)
- ;
-
- return b;
-}
-
-/* Write single data byte */
-static void spi_write(unsigned char b)
-{
- /* Set XFER_LENGTH to 1 */
- REG_CLR(ssp_base + SSP_CTRL0, 0xffff);
- REG_SET(ssp_base + SSP_CTRL0, 1);
-
- /* Enable WRITE mode */
- REG_CLR(ssp_base + SSP_CTRL0, CTRL0_READ);
-
- /* Set RUN bit */
- REG_SET(ssp_base + SSP_CTRL0, CTRL0_RUN);
-
- /* Write data byte */
- REG_WR(ssp_base + SSP_DATA, b);
-
- /* Set transfer */
- REG_SET(ssp_base + SSP_CTRL0, CTRL0_DATA_XFER);
-
- /* Wait until RUN bit is cleared */
- while (REG_RD(ssp_base + SSP_CTRL0) & CTRL0_RUN)
- ;
-}
-
-static void spi_lock_cs(void)
-{
- REG_CLR(ssp_base + SSP_CTRL0, CTRL0_IGNORE_CRC);
- REG_SET(ssp_base + SSP_CTRL0, CTRL0_LOCK_CS);
-}
-
-static void spi_unlock_cs(void)
-{
- REG_CLR(ssp_base + SSP_CTRL0, CTRL0_LOCK_CS);
- REG_SET(ssp_base + SSP_CTRL0, CTRL0_IGNORE_CRC);
-}
-
-void spi_txrx(const char *dout, unsigned int tx_len, char *din,
- unsigned int rx_len, unsigned long flags)
-{
- int i;
-
- if (tx_len == 0 && rx_len == 0)
- return;
-
- if (flags & SPI_START)
- spi_lock_cs();
-
- for (i = 0; i < tx_len; i++) {
-
- /* Check if it is last data byte to transfer */
- if (flags & SPI_STOP && rx_len == 0 && i == tx_len - 1)
- spi_unlock_cs();
-
- spi_write(dout[i]);
- }
-
- for (i = 0; i < rx_len; i++) {
-
- /* Check if it is last data byte to transfer */
- if (flags & SPI_STOP && i == rx_len - 1)
- spi_unlock_cs();
-
- din[i] = spi_read();
- }
-}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mx23.h>
-#include <asm/arch/timrot.h>
-
-#define CONFIG_USE_TIMER0
-
-#if defined(CONFIG_USE_TIMER0)
-#define TIMCTRL TIMCTRL0
-#define TIMCOUNT TIMCOUNT0
-#elif defined(CONFIG_USE_TIMER1)
-#define TIMCTRL TIMCTRL1
-#define TIMCOUNT TIMCOUNT1
-#elif defined(CONFIG_USE_TIMER2)
-#define TIMCTRL TIMCTRL2
-#define TIMCOUNT TIMCOUNT2
-#elif defined(CONFIG_USE_TIMER3)
-#define TIMCTRL TIMCTRL3
-#define TIMCOUNT TIMCOUNT3
-#else
-#error "Define which MX23 timer to use"
-#endif
-
-#define TIMER_LOAD_VAL 0x0000ffff
-
-/* macro to read the 16 bit timer */
-#define READ_TIMER ((REG_RD(TIMROT_BASE + TIMCOUNT) & 0xffff0000) >> 16)
-
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init(void)
-{
- u32 val;
-
- /*
- * Reset Timers and Rotary Encoder module
- */
-
- /* Clear SFTRST */
- REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 31);
- while (REG_RD(TIMROT_BASE + ROTCTRL) & (1 << 31))
- ;
-
- /* Clear CLKGATE */
- REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 30);
-
- /* Set SFTRST and wait until CLKGATE is set */
- REG_SET(TIMROT_BASE + ROTCTRL, 1 << 31);
- while (!(REG_RD(TIMROT_BASE + ROTCTRL) & (1 << 30)))
- ;
-
- /* Clear SFTRST and CLKGATE */
- REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 31);
- REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 30);
-
- /*
- * Now initialize timer
- */
-
- /* Set fixed_count to 0 */
- REG_WR(TIMROT_BASE + TIMCOUNT, 0);
-
- /* set UPDATE bit and 1Khz frequency */
- REG_WR(TIMROT_BASE + TIMCTRL,
- TIMCTRL_RELOAD | TIMCTRL_UPDATE | TIMCTRL_SELECT_1KHZ);
-
- /* Set fixed_count to maximal value */
- REG_WR(TIMROT_BASE + TIMCOUNT, TIMER_LOAD_VAL);
-
- /* init the timestamp and lastdec value */
- reset_timer_masked();
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
-/* delay x useconds AND perserve advance timstamp value */
-void udelay(unsigned long usec)
-{
- ulong tmo, tmp;
-
- if (usec >= 1000) {
- /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000;
- /* start to normalize for usec to ticks per sec */
- tmo *= CONFIG_SYS_HZ;
- /* find number of "ticks" to wait to achieve target */
- tmo /= 1000;
- /* finish normalize. */
- } else {
- /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= (1000*1000);
- }
-
- tmp = get_timer(0);
- /* get current timestamp */
- if ((tmo + tmp + 1) < tmp)
- /* if setting this fordward will roll time stamp */
- reset_timer_masked();
- /* reset "advancing" timestamp to 0, set lastdec value */
- else
- tmo += tmp;
- /* else, set advancing stamp wake up time */
-
- while (get_timer_masked() < tmo)/* loop till event */
- /*NOP*/;
-}
-
-void reset_timer_masked(void)
-{
- /* reset time */
- lastdec = READ_TIMER; /* capure current decrementer value time */
- timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked(void)
-{
- ulong now = READ_TIMER; /* current tick value */
-
- if (lastdec >= now) { /* normal mode (non roll) */
- /* normal mode */
- timestamp += lastdec - now;
- /* move stamp fordward with absoulte diff ticks */
- } else {
- /* we have overflow of the count down timer */
- /* nts = ts + ld + (TLV - now)
- * ts=old stamp, ld=time that passed before passing through -1
- * (TLV-now) amount of time after passing though -1
- * nts = new "advancing time stamp"...it could also roll
- * and cause problems.
- */
- timestamp += lastdec + TIMER_LOAD_VAL - now + 1;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked(unsigned long usec)
-{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- if (usec >= 1000) {
- /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000;
- /* start to normalize for usec to ticks per sec */
- tmo *= CONFIG_SYS_HZ;
- /* find number of "ticks" to wait to achieve target */
- tmo /= 1000;
- /* finish normalize. */
- } else {
- /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= (1000*1000);
- }
-
- endtime = get_timer_masked() + tmo;
-
- do {
- ulong now = get_timer_masked();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- ulong tbclk;
-
- tbclk = CONFIG_SYS_HZ;
- return tbclk;
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(SOC).a
-
-COBJS = timer.o serial.o generic.o iomux.o gpio.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all: $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/arch/mx25-regs.h>
-
-static u32 mx25_decode_pll(u32 reg)
-{
- u32 mfi = (reg >> 10) & 0xf;
- u32 mfn = reg & 0x3ff;
- u32 mfd = (reg >> 16) & 0x3ff;
- u32 pd = (reg >> 26) & 0xf;
-
- u32 ref_clk = PLL_REF_CLK;
-
- mfi = mfi <= 5 ? 5 : mfi;
- mfd += 1;
- pd += 1;
-
- return ((2 * (ref_clk >> 10) * (mfi * mfd + mfn)) /
- (mfd * pd)) << 10;
-}
-
-static u32 mx25_get_mcu_main_clk(void)
-{
- u32 cctl = __REG(CCM_CCTL);
- u32 ret_val = mx25_decode_pll(__REG(CCM_MPCTL));
-
- if (cctl & CRM_CCTL_ARM_SRC) {
- ret_val *= 3;
- ret_val /= 4;
- }
-
- return ret_val;
-}
-
-static u32 mx25_get_ahb_clk(void)
-{
- u32 cctl = __REG(CCM_CCTL);
- u32 ahb_div = ((cctl >> CRM_CCTL_AHB_OFFSET) & 3) + 1;
-
- return mx25_get_mcu_main_clk()/ahb_div;
-}
-
-unsigned int mx25_get_ipg_clk(void)
-{
- return mx25_get_ahb_clk()/2;
-}
-
-unsigned int mx25_get_cspi_clk(void)
-{
- return mx25_get_ipg_clk();
-}
-
-void mx25_dump_clocks(void)
-{
- u32 cpufreq = mx25_get_mcu_main_clk();
- printf("mx25 cpu clock: %dMHz\n", cpufreq / 1000000);
- printf("ipg clock : %dHz\n", mx25_get_ipg_clk());
-}
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
- switch (clk) {
- case MXC_ARM_CLK:
- return mx25_get_mcu_main_clk();
- case MXC_AHB_CLK:
- return mx25_get_ahb_clk();
- break;
- case MXC_IPG_PERCLK:
- case MXC_IPG_CLK:
- return mx25_get_ipg_clk();
- case MXC_CSPI_CLK:
- return mx25_get_cspi_clk();
- case MXC_UART_CLK:
- break;
- case MXC_ESDHC_CLK:
- return mx25_get_ipg_clk();
- break;
- }
- return -1;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- printf("CPU: Freescale i.MX25 at %d MHz\n",
- mx25_get_mcu_main_clk() / 1000000);
- mx25_dump_clocks();
- return 0;
-}
-#endif
-
-#if defined(CONFIG_MXC_FEC)
-extern int mxc_fec_initialize(bd_t *bis);
-extern void mxc_fec_set_mac_from_env(char *mac_addr);
-#endif
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
- int rc = -ENODEV;
-
-#if defined(CONFIG_MXC_FEC)
- rc = mxc_fec_initialize(bis);
-#endif
-
- return rc;
-}
-
+++ /dev/null
-/*
- * (c) Copyright 2009 Freescale Semiconductors
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mx25.h>
-#include <asm/arch/mx25_pins.h>
-#include <asm/arch/gpio.h>
-
-enum gpio_reg {
- DR = 0x00,
- GDIR = 0x04,
- PSR = 0x08,
- ICR1 = 0x0C,
- ICR2 = 0x10,
- IMR = 0x14,
- ISR = 0x18,
-};
-
-struct gpio_port_addr {
- int num;
- int base;
-};
-
-struct gpio_port_addr gpio_port[4] = {
- {0, GPIO1_BASE},
- {1, GPIO2_BASE},
- {2, GPIO3_BASE},
- {3, GPIO4_BASE}
- };
-
-/*
- * Set a GPIO pin's direction
- * @param port pointer to a gpio_port
- * @param index gpio pin index value (0~31)
- * @param is_input 0 for output; non-zero for input
- */
-static void _set_gpio_direction(u32 port, u32 index, int is_input)
-{
- u32 reg = gpio_port[port].base + GDIR;
- u32 l;
-
- l = __REG(reg);
- if (is_input)
- l &= ~(1 << index);
- else
- l |= 1 << index;
- __REG(reg) = l;
-}
-
-
-/*!
- * Exported function to set a GPIO pin's direction
- * @param pin a name defined by \b iomux_pin_name_t
- * @param is_input 1 (or non-zero) for input; 0 for output
- */
-void mxc_set_gpio_direction(iomux_pin_name_t pin, int is_input)
-{
- u32 port;
- u32 gpio = IOMUX_TO_GPIO(pin);
-
- port = GPIO_TO_PORT(gpio);
- _set_gpio_direction(port, GPIO_TO_INDEX(gpio), is_input);
-}
-
-/*
- * Set a GPIO pin's data output
- * @param port number of gpio port
- * @param index gpio pin index value (0~31)
- * @param data value to be set (only 0 or 1 is valid)
- */
-static void _set_gpio_dataout(u32 port, u32 index, u32 data)
-{
- u32 reg = gpio_port[port].base + DR;
- u32 l = 0;
-
- l = (__REG(reg) & (~(1 << index))) | (data << index);
- __REG(reg) = l;
-}
-
-/*!
- * Exported function to set a GPIO pin's data output
- * @param pin a name defined by \b iomux_pin_name_t
- * @param data value to be set (only 0 or 1 is valid)
- */
-
-void mxc_set_gpio_dataout(iomux_pin_name_t pin, u32 data)
-{
- u32 port;
- u32 gpio = IOMUX_TO_GPIO(pin);
-
- port = GPIO_TO_PORT(gpio);
- _set_gpio_dataout(port, GPIO_TO_INDEX(gpio), (data == 0) ? 0 : 1);
-}
-
+++ /dev/null
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/*!
- * @defgroup GPIO_MX25 Board GPIO and Muxing Setup
- * @ingroup MSL_MX25
- */
-/*!
- * @file mach-mx25/iomux.c
- *
- * @brief I/O Muxing control functions
- *
- * @ingroup GPIO_MX25
- */
-
-#include <common.h>
-#include <asm/arch/mx25.h>
-#include <asm/arch/mx25_pins.h>
-#include <asm/arch/iomux.h>
-
-/*!
- * IOMUX register (base) addresses
- */
-enum iomux_reg_addr {
- IOMUXGPR = IOMUXC_BASE,
- /*!< General purpose */
- IOMUXSW_MUX_CTL = IOMUXC_BASE + 0x008,
- /*!< MUX control */
- IOMUXSW_MUX_END = IOMUXC_BASE + 0x228,
- /*!< last MUX control register */
- IOMUXSW_PAD_CTL = IOMUXC_BASE + 0x22C,
- /*!< Pad control */
- IOMUXSW_PAD_END = IOMUXC_BASE + 0x414,
- /*!< last Pad control register */
- IOMUXSW_INPUT_CTL = IOMUXC_BASE + 0x460,
- /*!< input select register */
- IOMUXSW_INPUT_END = IOMUXC_BASE + 0x580,
- /*!< last input select register */
-};
-
-#define MUX_PIN_NUM_MAX \
- (((IOMUXSW_MUX_END - IOMUXSW_MUX_CTL) >> 2) + 1)
-#define MUX_INPUT_NUM_MUX \
- (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1)
-
-#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
-
-#define MUX_USED 0x80
-
-/*!
- * This function is used to configure a pin through the IOMUX module.
- * FIXED ME: for backward compatible. Will be static function!
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @param cfg an output function as defined in \b #iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
- if (mux_reg != NON_MUX_I) {
- mux_reg += IOMUXGPR;
- __REG(mux_reg) = cfg;
- }
-
- return 0;
-}
-
-/*!
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param cfg an input function as defined in \b #iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- int ret = iomux_config_mux(pin, cfg);
- return ret;
-}
-
-/*!
- * Release ownership for an IO pin
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param cfg an input function as defined in \b #iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*!
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @param config the ORed value of elements defined in \b #iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
- u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin);
-
- __REG(pad_reg) = config;
-}
-
-/*!
- * This function enables/disables the general purpose function for a particular
- * signal.
- *
- * @param gp one signal as defined in \b #iomux_gp_func_t
- * @param en \b #true to enable; \b #false to disable
- */
-void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en)
-{
- u32 l;
-
- l = __REG(IOMUXGPR);
- if (en)
- l |= gp;
- else
- l &= ~gp;
-
- __REG(IOMUXGPR) = l;
-}
-
-/*!
- * This function configures input path.
- *
- * @param input index of input select register as defined in \b
- * #iomux_input_select_t
- * @param config the binary value of elements defined in \b
- * #iomux_input_config_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
-{
- u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
-
- __REG(reg) = config;
-}
-
+++ /dev/null
-/*
- * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-
-#if defined CONFIG_MX25_UART
-
-#include <asm/arch/mx25.h>
-
-#define __REG(x) (*((volatile u32 *)(x)))
-
-#ifdef CONFIG_MX25_UART1
-#define UART_PHYS 0x43f90000
-#else
-#error "define CONFIG_MX25_UARTx to use the mx25 UART driver"
-#endif
-
-/* Register definitions */
-#define URXD 0x0 /* Receiver Register */
-#define UTXD 0x40 /* Transmitter Register */
-#define UCR1 0x80 /* Control Register 1 */
-#define UCR2 0x84 /* Control Register 2 */
-#define UCR3 0x88 /* Control Register 3 */
-#define UCR4 0x8c /* Control Register 4 */
-#define UFCR 0x90 /* FIFO Control Register */
-#define USR1 0x94 /* Status Register 1 */
-#define USR2 0x98 /* Status Register 2 */
-#define UESC 0x9c /* Escape Character Register */
-#define UTIM 0xa0 /* Escape Timer Register */
-#define UBIR 0xa4 /* BRM Incremental Register */
-#define UBMR 0xa8 /* BRM Modulator Register */
-#define UBRC 0xac /* Baud Rate Count Register */
-#define UTS 0xb4 /* UART Test Register (mx25) */
-
-/* UART Control Register Bit Fields.*/
-#define URXD_CHARRDY (1<<15)
-#define URXD_ERR (1<<14)
-#define URXD_OVRRUN (1<<13)
-#define URXD_FRMERR (1<<12)
-#define URXD_BRK (1<<11)
-#define URXD_PRERR (1<<10)
-#define URXD_RX_DATA (0xFF)
-#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
-#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
-#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
-#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
-#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
-#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
-#define UCR1_IREN (1<<7) /* Infrared interface enable */
-#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
-#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
-#define UCR1_SNDBRK (1<<4) /* Send break */
-#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
-#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
-#define UCR1_DOZE (1<<1) /* Doze */
-#define UCR1_UARTEN (1<<0) /* UART enabled */
-#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
-#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
-#define UCR2_CTSC (1<<13) /* CTS pin control */
-#define UCR2_CTS (1<<12) /* Clear to send */
-#define UCR2_ESCEN (1<<11) /* Escape enable */
-#define UCR2_PREN (1<<8) /* Parity enable */
-#define UCR2_PROE (1<<7) /* Parity odd/even */
-#define UCR2_STPB (1<<6) /* Stop */
-#define UCR2_WS (1<<5) /* Word size */
-#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
-#define UCR2_TXEN (1<<2) /* Transmitter enabled */
-#define UCR2_RXEN (1<<1) /* Receiver enabled */
-#define UCR2_SRST (1<<0) /* SW reset */
-#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
-#define UCR3_PARERREN (1<<12) /* Parity enable */
-#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
-#define UCR3_DSR (1<<10) /* Data set ready */
-#define UCR3_DCD (1<<9) /* Data carrier detect */
-#define UCR3_RI (1<<8) /* Ring indicator */
-#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
-#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
-#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
-#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
-#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
-#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
-#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
-#define UCR3_BPEN (1<<0) /* Preset registers enable */
-#define UCR4_CTSTL_32 (32<<10)/* CTS trigger level (32 chars) */
-#define UCR4_INVR (1<<9) /* Inverted infrared reception */
-#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
-#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
-#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
-#define UCR4_IRSC (1<<5) /* IR special case */
-#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
-#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
-#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
-#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
-#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
-#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
-#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
-#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
-#define USR1_RTSS (1<<14) /* RTS pin status */
-#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
-#define USR1_RTSD (1<<12) /* RTS delta */
-#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
-#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
-#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
-#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
-#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
-#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
-#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
-#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
-#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
-#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
-#define USR2_IDLE (1<<12) /* Idle condition */
-#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
-#define USR2_WAKE (1<<7) /* Wake */
-#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
-#define USR2_TXDC (1<<3) /* Transmitter complete */
-#define USR2_BRCD (1<<2) /* Break condition */
-#define USR2_ORE (1<<1) /* Overrun error */
-#define USR2_RDR (1<<0) /* Recv data ready */
-#define UTS_FRCPERR (1<<13) /* Force parity error */
-#define UTS_LOOP (1<<12) /* Loop tx and rx */
-#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
-#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
-#define UTS_TXFULL (1<<4) /* TxFIFO full */
-#define UTS_RXFULL (1<<3) /* RxFIFO full */
-#define UTS_SOFTRST (1<<0) /* Software reset */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void serial_setbrg(void)
-{
- u32 clk = mx25_get_ipg_clk();
-
- if (!gd->baudrate)
- gd->baudrate = CONFIG_BAUDRATE;
-
- __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
- __REG(UART_PHYS + UBIR) = 0xf;
- __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
-
-}
-
-int serial_getc(void)
-{
- while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
- ;
-
- /* mask out status from upper word */
- return (__REG(UART_PHYS + URXD) & URXD_RX_DATA)
- ;
-}
-
-void serial_putc(const char c)
-{
- __REG(UART_PHYS + UTXD) = c;
-
- /* wait for transmitter to be ready */
- while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
- ;
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-int serial_tstc(void)
-{
- /* If receive fifo is empty, return false */
- if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
- return 0;
- return 1;
-}
-
-void serial_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init(void)
-{
- __REG(UART_PHYS + UCR1) = 0x0;
- __REG(UART_PHYS + UCR2) = 0x0;
-
- while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST))
- ;
-
- __REG(UART_PHYS + UCR3) = 0x0704;
- __REG(UART_PHYS + UCR4) = 0x8000;
- __REG(UART_PHYS + UESC) = 0x002b;
- __REG(UART_PHYS + UTIM) = 0x0;
-
- __REG(UART_PHYS + UTS) = 0x0;
-
- serial_setbrg();
-
- __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN |
- UCR2_TXEN | UCR2_SRST;
-
- __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
-
- return 0;
-}
-
-
-#endif /* CONFIG_MX25 */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mx25-regs.h>
-
-/* General purpose timers registers */
-#define GPTCR __REG(GPT1_BASE) /* Control register */
-#define GPTPR __REG(GPT1_BASE + 0x4) /* Prescaler register */
-#define GPTSR __REG(GPT1_BASE + 0x8) /* Status register */
-#define GPTCNT __REG(GPT1_BASE + 0x24) /* Counter register */
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR (1<<15) /* Software reset */
-#define GPTCR_FRR (1<<9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */
-#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */
-#define GPTCR_TEN (1) /* Timer enable */
-#define GPTPR_VAL (66)
-
-static inline void setup_gpt()
-{
- int i;
- static int init_done;
-
- if (init_done)
- return;
-
- init_done = 1;
-
- /* setup GP Timer 1 */
- GPTCR = GPTCR_SWR;
- for (i = 0; i < 100; i++)
- GPTCR = 0; /* We have no udelay by now */
- GPTPR = GPTPR_VAL; /* 66Mhz / 66 */
- /* Freerun Mode, PERCLK1 input */
- GPTCR |= GPTCR_CLKSOURCE_IPG | GPTCR_TEN;
-}
-
-int timer_init(void)
-{
- setup_gpt();
-
- return 0;
-}
-
-void reset_timer_masked(void)
-{
- GPTCR = 0;
- /* Freerun Mode, PERCLK1 input */
- GPTCR = GPTCR_CLKSOURCE_IPG | GPTCR_TEN;
-}
-
-inline ulong get_timer_masked(void)
-{
- ulong val = GPTCNT;
-
- return val;
-}
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
- ulong tmp;
-
- tmp = get_timer_masked();
-
- if (tmp <= (base * 1000)) {
- /* Overflow */
- tmp += (0xffffffff - base);
- }
-
- return (tmp / 1000) - base;
-}
-
-void set_timer(ulong t)
-{
-}
-
-/* delay x useconds AND perserve advance timstamp value */
-/* GPTCNT is now supposed to tick 1 by 1 us. */
-void udelay(unsigned long usec)
-{
- ulong tmp;
-
- setup_gpt();
-
- tmp = get_timer_masked(); /* get current timestamp */
-
- /* if setting this forward will roll time stamp */
- if ((usec + tmp + 1) < tmp) {
- /* reset "advancing" timestamp to 0, set lastinc value */
- reset_timer_masked();
- } else {
- /* else, set advancing stamp wake up time */
- tmp += usec;
- }
-
- while (get_timer_masked() < tmp) /* loop till event */
- /*NOP*/;
-}
-
-void reset_cpu(ulong addr)
-{
- __REG16(WDOG_BASE) = 4;
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(SOC).a
-
-COBJS = timer.o serial.o generic.o pinctrl.o mmcops.o
-SOBJS = reset.o
-
-SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
-START := $(addprefix $(obj),$(START))
-
-all: $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-PLATFORM_CPPFLAGS += -march=armv5te
-PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/arch/regs-clkctrl.h>
-#include <asm/cache-cp15.h>
-#include <asm/io.h>
-#include <asm/fec.h>
-
-#define MXS_MODULE_SFTRST (1 << 31)
-#define MXS_MODULE_CLKGATE (1 << 30)
-
-static inline void __mxs_clrl(u32 mask, volatile void *addr)
-{
- __raw_writel(mask, addr + MXS_CLR_ADDR);
-}
-
-static inline void __mxs_setl(u32 mask, volatile void *addr)
-{
- __raw_writel(mask, addr + MXS_SET_ADDR);
-}
-
-/*
- * Clear the bit and poll it cleared. This is usually called with
- * a reset address and mask being either SFTRST(bit 31) or CLKGATE
- * (bit 30).
- */
-static int clear_poll_bit(volatile void *addr, u32 mask)
-{
- int timeout = 0x400;
-
- /* clear the bit */
- __mxs_clrl(mask, addr);
-
- /*
- * SFTRST needs 3 GPMI clocks to settle, the reference manual
- * recommends to wait 1us.
- */
- udelay(1);
-
- /* poll the bit becoming clear */
- while ((__raw_readl(addr) & mask) && --timeout)
- udelay(1);
-
- return !timeout;
-}
-
-int mxs_reset_block(volatile void *reset_addr)
-{
- int ret;
- int timeout = 0x400000;
-
- /* clear and poll SFTRST */
- ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST);
- if (ret)
- goto error;
-
- /* clear CLKGATE */
- __mxs_clrl(MXS_MODULE_CLKGATE, reset_addr);
-
- /* set SFTRST to reset the block */
- __mxs_setl(MXS_MODULE_SFTRST, reset_addr);
- udelay(1);
-
- /* poll CLKGATE becoming set */
- while ((!(__raw_readl(reset_addr) & MXS_MODULE_CLKGATE)) && --timeout)
- udelay(1);
-
- if (!timeout)
- goto error;
-
- /* clear and poll SFTRST */
- ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST);
- if (ret)
- goto error;
-
- /* clear and poll CLKGATE */
- ret = clear_poll_bit(reset_addr, MXS_MODULE_CLKGATE);
- if (ret)
- goto error;
-
- return 0;
-
-error:
- printf("%s(%p): module reset timeout\n", __func__, reset_addr);
- return -ETIMEDOUT;
-}
-
-static u32 mx28_get_pclk(void)
-{
- const u32 xtal = 24, ref = 480;
- u32 clkfrac, clkseq, clkctrl;
- u32 frac, div;
- u32 pclk;
-
- clkfrac = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0);
- clkseq = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_CLKSEQ);
- clkctrl = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_CPU);
-
- if (clkctrl & (BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN |
- BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN)) {
- /* No support of fractional divider calculation */
- pclk = 0;
- } else {
- if (clkseq & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) {
- /* xtal path */
- div = (clkctrl & BM_CLKCTRL_CPU_DIV_XTAL) >>
- BP_CLKCTRL_CPU_DIV_XTAL;
- pclk = xtal / div;
- } else {
- /* ref path */
- frac = (clkfrac & BM_CLKCTRL_FRAC0_CPUFRAC) >>
- BP_CLKCTRL_FRAC0_CPUFRAC;
- div = (clkctrl & BM_CLKCTRL_CPU_DIV_CPU) >>
- BP_CLKCTRL_CPU_DIV_CPU;
- pclk = (ref * 18 / frac) / div;
- }
- }
-
- return pclk;
-}
-
-static u32 mx28_get_hclk(void)
-{
- u32 clkctrl, div, hclk;
-
- clkctrl = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_HBUS);
-
- if (clkctrl & BM_CLKCTRL_HBUS_DIV_FRAC_EN) {
- /* No support of fractional divider calculation */
- hclk = 0;
- } else {
- div = (clkctrl & BM_CLKCTRL_HBUS_DIV) >>
- BP_CLKCTRL_HBUS_DIV;
- hclk = mx28_get_pclk() / div;
- }
-
- return hclk;
-}
-
-static u32 mx28_get_emiclk(void)
-{
- const u32 xtal = 24, ref = 480;
- u32 clkfrac, clkseq, clkctrl;
- u32 frac, div;
- u32 emiclk;
-
- clkfrac = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0);
- clkseq = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_CLKSEQ);
- clkctrl = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_EMI);
-
- if (clkseq & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) {
- /* xtal path */
- div = (clkctrl & BM_CLKCTRL_EMI_DIV_XTAL) >>
- BP_CLKCTRL_EMI_DIV_XTAL;
- emiclk = xtal / div;
- } else {
- /* ref path */
- frac = (clkfrac & BM_CLKCTRL_FRAC0_EMIFRAC) >>
- BP_CLKCTRL_FRAC0_EMIFRAC;
- div = (clkctrl & BM_CLKCTRL_EMI_DIV_EMI) >>
- BP_CLKCTRL_EMI_DIV_EMI;
- emiclk = (ref * 18 / frac) / div;
- }
-
- return emiclk;
-}
-
-static inline void __enable_gpmi_clk(void)
-{
- /* Clear bypass bit*/
- REG_SET(REGS_CLKCTRL_BASE, HW_CLKCTRL_CLKSEQ,
- BM_CLKCTRL_CLKSEQ_BYPASS_GPMI);
- /* Set gpmi clock to ref_gpmi/12 */
- REG_WR(REGS_CLKCTRL_BASE, HW_CLKCTRL_GPMI,
- (REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_GPMI) &
- (~(BM_CLKCTRL_GPMI_DIV |
- ~BM_CLKCTRL_GPMI_CLKGATE))) |
- 1);
-}
-
-static u32 mx28_get_gpmiclk(void)
-{
- const u32 xtal = 24, ref = 480;
- u32 clkfrac, clkseq, clkctrl;
- u32 frac, div;
- u32 gpmiclk;
- /* Enable gpmi clock */
- __enable_gpmi_clk();
-
- clkfrac = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC1);
- clkseq = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_CLKSEQ);
- clkctrl = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_GPMI);
-
- if (clkseq & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) {
- /* xtal path */
- div = (clkctrl & BM_CLKCTRL_GPMI_DIV) >>
- BP_CLKCTRL_GPMI_DIV;
- gpmiclk = xtal / div;
- } else {
- /* ref path */
- frac = (clkfrac & BM_CLKCTRL_FRAC1_GPMIFRAC) >>
- BP_CLKCTRL_FRAC1_GPMIFRAC;
- div = (clkctrl & BM_CLKCTRL_GPMI_DIV) >>
- BP_CLKCTRL_GPMI_DIV;
- gpmiclk = (ref * 18 / frac) / div;
- }
-
- return gpmiclk;
-}
-
-u32 mxc_get_clock(enum mxc_clock clk)
-{
- switch (clk) {
- case MXC_ARM_CLK:
- return mx28_get_pclk() * 1000000;
- case MXC_GPMI_CLK:
- return mx28_get_gpmiclk() * 1000000;
- case MXC_AHB_CLK:
- case MXC_IPG_CLK:
- return mx28_get_hclk() * 1000000;
- }
-
- return 0;
-}
-
-#if defined(CONFIG_ARCH_CPU_INIT)
-int arch_cpu_init(void)
-{
- icache_enable();
- dcache_enable();
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- printf("Freescale i.MX28 family\n");
- printf("CPU: %d MHz\n", mx28_get_pclk());
- printf("BUS: %d MHz\n", mx28_get_hclk());
- printf("EMI: %d MHz\n", mx28_get_emiclk());
- printf("GPMI: %d MHz\n", mx28_get_gpmiclk());
- return 0;
-}
-#endif
-
-/*
- * Initializes on-chip ethernet controllers.
- */
-int cpu_eth_init(bd_t *bis)
-{
- int rc = ENODEV;
-#if defined(CONFIG_MXC_FEC)
- rc = mxc_fec_initialize(bis);
-
- /* Turn on ENET clocks */
- REG_WR(REGS_CLKCTRL_BASE, HW_CLKCTRL_ENET,
- REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_ENET) &
- ~(BM_CLKCTRL_ENET_SLEEP | BM_CLKCTRL_ENET_DISABLE));
-
- /* Set up ENET PLL for 50 MHz */
- REG_SET(REGS_CLKCTRL_BASE, HW_CLKCTRL_PLL2CTRL0,
- BM_CLKCTRL_PLL2CTRL0_POWER); /* Power on ENET PLL */
- udelay(10); /* Wait 10 us */
- REG_CLR(REGS_CLKCTRL_BASE, HW_CLKCTRL_PLL2CTRL0,
- BM_CLKCTRL_PLL2CTRL0_CLKGATE); /* Gate on ENET PLL */
- REG_WR(REGS_CLKCTRL_BASE, HW_CLKCTRL_ENET,
- REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_ENET) |
- BM_CLKCTRL_ENET_CLK_OUT_EN); /* Enable pad output */
-
- /* Board level init */
- enet_board_init();
-#endif
- return rc;
-}
-
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <command.h>
-#include <exports.h>
-#include <mmc.h>
-
-#ifdef CONFIG_GENERIC_MMC
-#define MMCOPS_DEBUG
-
-#define MBR_SIGNATURE 0xaa55
-#define MBR_SECTOR_COUNT (CONFIG_ENV_OFFSET >> 9)
-/* 1. RSV partition (env and uImage) */
-#define RSVPART_SECTOR_OFFSET (MBR_SECTOR_COUNT)
-#define RSVPART_SECTOR_COUNT 0x3ffe /* 8 MB */
-/* 2. FAT partition */
-#define FATPART_FILESYS 0xb
-#define FATPART_SECTOR_OFFSET (RSVPART_SECTOR_OFFSET + RSVPART_SECTOR_COUNT)
-#define FATPART_SECTOR_COUNT 0x10000 /* 32 MB (minimal) */
-/* 3. EXT partition */
-#define EXTPART_FILESYS 0x83
-#define EXTPART_SECTOR_COUNT 0xc0000 /* 384 MB */
-/* 4. SB partition (uboot.sb or linux.sb) */
-#define SBPART_FILESYS 'S'
-#define SBPART_SECTOR_COUNT 0x4000 /* 8 MB */
-#define CB_SIGNATURE 0x00112233
-#define CB_SECTOR_COUNT 2
-
-#define MAX_CYLINDERS 1024
-#define MAX_HEADS 256
-#define MAX_SECTORS 63
-
-struct partition {
- u8 boot_flag;
- u8 start_head;
- u8 start_sector;
- u8 start_cylinder;
- u8 file_system;
- u8 end_head;
- u8 end_sector;
- u8 end_cylinder;
- u32 sector_offset;
- u32 sector_count;
-} __attribute__ ((__packed__));
-
-struct partition_table {
- u8 reserved[446];
- struct partition partitions[4];
- u16 signature;
-};
-
-struct drive_info {
- u32 chip_num;
- u32 drive_type;
- u32 drive_tag;
- u32 sector_offset;
- u32 sector_count;
-};
-
-struct config_block {
- u32 signature;
- u32 primary_tag;
- u32 secondary_tag;
- u32 num_copies;
- struct drive_info drive_info[2];
-};
-
-static int mmc_format(int dev)
-{
- int rc = 0;
- u8 *buf = 0;
- u32 i, cnt, total_sectors;
- u32 offset[4];
- struct config_block *cb;
- struct partition_table *mbr;
- struct mmc *mmc = find_mmc_device(dev);
-
- /* Warning */
- printf("WARN: Data on card will get lost with format.\n"
- "Continue? (y/n)");
- char ch = getc();
- printf("\n");
- if (ch != 'y') {
- rc = -1;
- goto out;
- }
-
- /* Allocate sector buffer */
- buf = malloc(mmc->read_bl_len);
- if (!buf) {
- printf("%s[%d]: malloc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
- memset(buf, 0, mmc->read_bl_len);
-
- /* Erase the first sector of each partition */
- cnt = mmc->block_dev.block_read(dev, 0, 1, buf);
- if (cnt != 1) {
- printf("%s[%d]: read mmc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
- mbr = (struct partition_table *)buf;
- if (mbr->signature == MBR_SIGNATURE) {
- /* Get sector offset of each partition */
- for (i = 0; i < 4; i++)
- offset[i] = mbr->partitions[i].sector_offset;
- /* Erase */
- memset(buf, 0, mmc->read_bl_len);
- for (i = 0; i < 4; i++) {
- if (offset[i] > 0) {
- cnt = mmc->block_dev.block_write(dev,
- offset[i], 1, buf);
- if (cnt != 1) {
- printf("%s[%d]: write mmc error\n",
- __func__, __LINE__);
- rc = -1;
- goto out;
- }
- }
- }
- }
-
- /* Get total sectors */
- total_sectors = mmc->capacity >> 9;
- if (RSVPART_SECTOR_COUNT + SBPART_SECTOR_COUNT > total_sectors) {
- printf("Card capacity is too low to format\n");
- rc = -1;
- goto out;
- }
-
- /* Write config block */
- cb = (struct config_block *)buf;
- cb->signature = CB_SIGNATURE;
- cb->num_copies = 2;
- cb->primary_tag = 0x1;
- cb->secondary_tag = 0x2;
- cb->drive_info[0].chip_num = 0;
- cb->drive_info[0].drive_type = 0;
- cb->drive_info[0].drive_tag = 0x1;
- cb->drive_info[0].sector_count = SBPART_SECTOR_COUNT - CB_SECTOR_COUNT;
- cb->drive_info[0].sector_offset =
- total_sectors - cb->drive_info[0].sector_count;
- cb->drive_info[1].chip_num = 0;
- cb->drive_info[1].drive_type = 0;
- cb->drive_info[1].drive_tag = 0x2;
- cb->drive_info[1].sector_count = SBPART_SECTOR_COUNT - CB_SECTOR_COUNT;
- cb->drive_info[1].sector_offset =
- total_sectors - cb->drive_info[1].sector_count;
-
- cnt = mmc->block_dev.block_write(dev,
- total_sectors - SBPART_SECTOR_COUNT, 1, (void *)cb);
- if (cnt != 1) {
- printf("%s[%d]: write mmc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
-
- /* Prepare for MBR */
- memset(buf, 0, mmc->read_bl_len);
- mbr = (struct partition_table *)buf;
-
- /* RSV partition */
- mbr->partitions[0].sector_offset = RSVPART_SECTOR_OFFSET;
- mbr->partitions[0].sector_count = RSVPART_SECTOR_COUNT;
-
- /* SB partition */
- mbr->partitions[3].file_system = SBPART_FILESYS;
- mbr->partitions[3].sector_offset = total_sectors - SBPART_SECTOR_COUNT;
- mbr->partitions[3].sector_count = SBPART_SECTOR_COUNT;
-
- /* EXT partition */
- if (EXTPART_SECTOR_COUNT + SBPART_SECTOR_COUNT +
- RSVPART_SECTOR_COUNT > total_sectors) {
-#ifdef MMCOPS_DEBUG
- printf("No room for EXT partition\n");
-#endif
- } else {
- mbr->partitions[2].file_system = EXTPART_FILESYS;
- mbr->partitions[2].sector_offset = total_sectors -
- SBPART_SECTOR_COUNT - EXTPART_SECTOR_COUNT;
- mbr->partitions[2].sector_count = EXTPART_SECTOR_COUNT;
- }
-
- /* FAT partition */
- if (FATPART_SECTOR_COUNT + MBR_SECTOR_COUNT +
- mbr->partitions[0].sector_count +
- mbr->partitions[2].sector_count +
- mbr->partitions[3].sector_count > total_sectors) {
-#ifdef MMCOPS_DEBUG
- printf("No room for FAT partition\n");
-#endif
- goto out;
- }
- mbr->partitions[1].file_system = FATPART_FILESYS;
- mbr->partitions[1].sector_offset = FATPART_SECTOR_OFFSET;
- mbr->partitions[1].sector_count = total_sectors - MBR_SECTOR_COUNT -
- mbr->partitions[0].sector_count -
- mbr->partitions[2].sector_count -
- mbr->partitions[3].sector_count;
-
-out:
- if (rc == 0) {
- /* Write MBR */
- mbr->signature = MBR_SIGNATURE;
- cnt = mmc->block_dev.block_write(dev, 0, 1, (void *)mbr);
- if (cnt != 1) {
- printf("%s[%d]: write mmc error\n", __func__, __LINE__);
- rc = -1;
- } else
- printf("Done.\n");
- }
-
- if (!buf)
- free(buf);
- return rc;
-}
-
-static int install_sbimage(int dev, void *addr, u32 size)
-{
- int rc = 0;
- u8 *buf = 0;
- u32 cnt, offset, cb_offset, sectors, not_format = 0;
- struct config_block *cb;
- struct partition_table *mbr;
- struct mmc *mmc = find_mmc_device(dev);
-
- /* Allocate sector buffer */
- buf = malloc(mmc->read_bl_len);
- if (!buf) {
- printf("%s[%d]: malloc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
-
- /* Check partition */
- offset = 0;
- cnt = mmc->block_dev.block_read(dev, offset, 1, buf);
- if (cnt != 1) {
- printf("%s[%d]: read mmc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
- mbr = (struct partition_table *)buf;
- if ((mbr->signature != MBR_SIGNATURE) ||
- (mbr->partitions[3].file_system != SBPART_FILESYS))
- not_format = 1;
-
- /* Check config block */
- offset = mbr->partitions[3].sector_offset;
- cb_offset = offset; /* Save for later use */
- cnt = mmc->block_dev.block_read(dev, offset, 1, buf);
- if (cnt != 1) {
- printf("%s[%d]: read mmc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
- cb = (struct config_block *)buf;
- if (cb->signature != CB_SIGNATURE)
- not_format = 1;
-
- /* Not formatted */
- if (not_format) {
- printf("Card is not formatted yet\n");
- rc = -1;
- goto out;
- }
-
- /* Calculate sectors of image */
- sectors = size / mmc->read_bl_len;
- if (size % mmc->read_bl_len)
- sectors++;
-
- /* Write image */
- offset = cb->drive_info[0].sector_offset;
- cnt = mmc->block_dev.block_write(dev, offset, sectors, addr);
- if (cnt != sectors) {
- printf("%s[%d]: write mmc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
- /* Verify */
- cnt = mmc->block_dev.block_read(dev, offset, sectors,
- addr + sectors * mmc->read_bl_len);
- if (cnt != sectors) {
- printf("%s[%d]: read mmc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
- if (memcmp(addr, addr + sectors * mmc->read_bl_len,
- sectors * mmc->read_bl_len)) {
- printf("Verifying sbImage write fails\n");
- rc = -1;
- goto out;
- }
-
- /* Redundant one */
- offset += sectors;
- cnt = mmc->block_dev.block_write(dev, offset, sectors, addr);
- if (cnt != sectors) {
- printf("%s[%d]: write mmc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
- /* Verify */
- cnt = mmc->block_dev.block_read(dev, offset, sectors,
- addr + sectors * mmc->read_bl_len);
- if (cnt != sectors) {
- printf("%s[%d]: read mmc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
- if (memcmp(addr, addr + sectors * mmc->read_bl_len,
- sectors * mmc->read_bl_len)) {
- printf("Verifying redundant sbImage write fails");
- rc = -1;
- goto out;
- }
-
- /* Update config block */
- cb->drive_info[0].sector_count = sectors;
- cb->drive_info[1].sector_count = sectors;
- cb->drive_info[1].sector_offset = offset;
- cnt = mmc->block_dev.block_write(dev, cb_offset, 1, (void *)cb);
- if (cnt != 1) {
- printf("%s[%d]: write mmc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
-
- /* Done */
- printf("Done: %d (%x hex) sectors written at %d (%x hex)\n",
- sectors, sectors, offset - sectors, offset - sectors);
-
-out:
- if (!buf)
- free(buf);
- return rc;
-}
-
-static int install_uimage(int dev, void *addr, u32 size)
-{
- int rc = 0;
- u8 *buf = 0;
- u32 cnt, offset, sectors;
- struct partition_table *mbr;
- struct mmc *mmc = find_mmc_device(dev);
-
- /* Calculate sectors of uImage */
- sectors = size / mmc->read_bl_len;
- if (size % mmc->read_bl_len)
- sectors++;
-
- /* Allocate sector buffer */
- buf = malloc(mmc->read_bl_len);
- if (!buf) {
- printf("%s[%d]: malloc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
-
- /* Check partition */
- offset = 0;
- cnt = mmc->block_dev.block_read(dev, offset, 1, buf);
- if (cnt != 1) {
- printf("%s[%d]: read mmc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
- mbr = (struct partition_table *)buf;
- if (mbr->signature != MBR_SIGNATURE) {
- printf("No valid partition table\n");
- rc = -1;
- goto out;
- }
- if (mbr->partitions[0].sector_count < sectors) {
- printf("No enough uImage partition room\n");
- rc = -1;
- goto out;
- }
-
- /* Write uImage */
- offset = mbr->partitions[0].sector_offset + (CONFIG_ENV_SIZE >> 9);
- cnt = mmc->block_dev.block_write(dev, offset, sectors, addr);
- if (cnt != sectors) {
- printf("%s[%d]: write mmc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
- /* Verify */
- cnt = mmc->block_dev.block_read(dev, offset, sectors,
- addr + sectors * mmc->read_bl_len);
- if (cnt != sectors) {
- printf("%s[%d]: read mmc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
- if (memcmp(addr, addr + sectors * mmc->read_bl_len,
- sectors * mmc->read_bl_len)) {
- printf("Verifying uImage write fails");
- rc = -1;
- goto out;
- }
-
- /* Done */
- printf("Done: %d (%x hex) sectors written at %d (%x hex)\n",
- sectors, sectors, offset, offset);
-
-out:
- if (!buf)
- free(buf);
- return rc;
-}
-
-static int install_rootfs(int dev, void *addr, u32 size)
-{
- int rc = 0;
- u8 *buf = 0;
- u32 cnt, offset, sectors;
- struct partition_table *mbr;
- struct mmc *mmc = find_mmc_device(dev);
-
- /* Calculate sectors of rootfs */
- sectors = size / mmc->read_bl_len;
- if (size % mmc->read_bl_len)
- sectors++;
-
- /* Allocate sector buffer */
- buf = malloc(mmc->read_bl_len);
- if (!buf) {
- printf("%s[%d]: malloc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
-
- /* Check partition */
- offset = 0;
- cnt = mmc->block_dev.block_read(dev, offset, 1, buf);
- if (cnt != 1) {
- printf("%s[%d]: read mmc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
- mbr = (struct partition_table *)buf;
- if ((mbr->signature != MBR_SIGNATURE) ||
- (mbr->partitions[2].file_system != EXTPART_FILESYS)) {
- printf("No rootfs partition\n");
- rc = -1;
- goto out;
- }
- if (mbr->partitions[2].sector_count < sectors) {
- printf("No enough rootfs partition room\n");
- rc = -1;
- goto out;
- }
-
- /* Write rootfs */
- offset = mbr->partitions[2].sector_offset;
- cnt = mmc->block_dev.block_write(dev, offset, sectors, addr);
- if (cnt != sectors) {
- printf("%s[%d]: write mmc error\n", __func__, __LINE__);
- rc = -1;
- goto out;
- }
-
- /* Done */
- printf("Done: %d (%x hex) sectors written at %d (%x hex)\n",
- sectors, sectors, offset, offset);
-
-out:
- if (!buf)
- free(buf);
- return rc;
-}
-
-int do_mxs_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- int dev = 0;
- struct mmc *mmc;
-
- if (argc < 2)
- goto err_out;
-
- if (strcmp(argv[1], "format") &&
- strcmp(argv[1], "install"))
- goto err_out;
-
- if (argc == 2) { /* list */
- print_mmc_devices('\n');
- return 0;
- }
-
- /* Find and init mmc */
- dev = simple_strtoul(argv[2], NULL, 10);
- mmc = find_mmc_device(dev);
- if (!mmc) {
- printf("%s[%d]: find mmc error\n", __func__, __LINE__);
- return -1;
- }
- if (mmc_init(mmc)) {
- printf("%s[%d]: init mmc error\n", __func__, __LINE__);
- return -1;
- }
-
- if (!strcmp(argv[1], "format"))
- mmc_format(dev);
- if (argc == 3) /* rescan (mmc_init) */
- return 0;
-
- if (argc != 6)
- goto err_out;
-
- if (!strcmp(argv[1], "install")) {
- void *addr = (void *)simple_strtoul(argv[3], NULL, 16);
- u32 size = simple_strtoul(argv[4], NULL, 16);
-
- if (!strcmp(argv[5], "sbImage"))
- return install_sbimage(dev, addr, size);
- else if (!strcmp(argv[5], "uImage"))
- return install_uimage(dev, addr, size);
- else if (!strcmp(argv[5], "rootfs"))
- return install_rootfs(dev, addr, size);
- }
-
-err_out:
- printf("Usage:\n%s\n", cmdtp->usage);
- return -1;
-}
-
-U_BOOT_CMD(
- mxs_mmc, 6, 1, do_mxs_mmcops,
- "MXS specific MMC sub system",
- "mxs_mmc format <device num>\n"
- "mxs_mmc install <device num> addr size sbImage/uImage/rootfs\n");
-#endif /* CONFIG_GENERIC_MMC */
+++ /dev/null
-/*
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/arch/regs-pinctrl.h>
-#include <asm/arch/pinctrl.h>
-
-void pin_gpio_direction(u32 id, u32 output)
-{
- u32 addr;
- u32 bank = PINID_2_BANK(id);
- u32 pin = PINID_2_PIN(id);
-
- addr = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0;
- addr += 0x10 * bank;
- if (output)
- REG_SET_ADDR(addr, 1 << pin);
- else
- REG_CLR_ADDR(addr, 1 << pin);
-}
-
-u32 pin_gpio_get(u32 id)
-{
- u32 addr, val;
- u32 bank = PINID_2_BANK(id);
- u32 pin = PINID_2_PIN(id);
-
- addr = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0;
- addr += 0x10 * bank;
- val = REG_RD_ADDR(addr);
-
- return !!(val & (1 << pin));
-}
-
-void pin_gpio_set(u32 id, u32 val)
-{
- u32 addr;
- u32 bank = PINID_2_BANK(id);
- u32 pin = PINID_2_PIN(id);
-
- addr = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0;
- addr += 0x10 * bank;
- if (val)
- REG_SET_ADDR(addr, 1 << pin);
- else
- REG_CLR_ADDR(addr, 1 << pin);
-}
-
-void pin_set_strength(u32 id, enum pad_strength strength)
-{
- u32 addr;
- u32 bank = PINID_2_BANK(id);
- u32 pin = PINID_2_PIN(id);
- u32 val;
-
- addr = REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0;
- addr += 0x40 * bank + 0x10 * (pin >> 3);
- pin &= 0x7;
-
- /* Don't use REG_CLR_ADDR/REG_SET_ADDR to prevent unwanted pin state transitions */
- val = REG_RD_ADDR(addr);
- val &= ~(0x7 << (pin * 4));
- val |= (strength & 0x7) << (pin * 4);
- REG_WR_ADDR(addr, val);
-}
-
-void pin_set_voltage(u32 id, enum pad_voltage volt)
-{
- u32 addr;
- u32 bank = PINID_2_BANK(id);
- u32 pin = PINID_2_PIN(id);
-
- addr = REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0;
- addr += 0x40 * bank + 0x10 * (pin >> 3);
- pin &= 0x7;
- if (volt == PAD_1V8)
- REG_CLR_ADDR(addr, 1 << (pin * 4 + 2));
- else
- REG_SET_ADDR(addr, 1 << (pin * 4 + 2));
-}
-
-void pin_set_pullup(u32 id, u32 pullup)
-{
- u32 addr;
- u32 bank = PINID_2_BANK(id);
- u32 pin = PINID_2_PIN(id);
-
- addr = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0;
- addr += 0x10 * bank;
- if (pullup)
- REG_SET_ADDR(addr, 1 << pin);
- else
- REG_CLR_ADDR(addr, 1 << pin);
-}
-
-void pin_set_type(u32 id, enum pin_fun cfg)
-{
- u32 addr;
- u32 bank = PINID_2_BANK(id);
- u32 pin = PINID_2_PIN(id);
- u32 val;
-
- addr = REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0;
- addr += 0x20 * bank + 0x10 * (pin >> 4);
- pin &= 0xf;
-
- /* Don't use _CLR/_SET to prevent unwanted pin state transitions */
- val = REG_RD_ADDR(addr);
- val &= ~(0x3 << (pin * 2));
- val |= (cfg & 0x3) << (pin * 2);
- REG_WR_ADDR(addr, val);
-}
-
-void pin_set_group(struct pin_group *pin_group)
-{
- u32 p;
- struct pin_desc *pin;
-
- for (p = 0; p < pin_group->nr_pins; p++) {
- pin = &pin_group->pins[p];
- pin_set_type(pin->id, pin->fun);
- pin_set_strength(pin->id, pin->strength);
- pin_set_voltage(pin->id, pin->voltage);
- pin_set_pullup(pin->id, pin->pullup);
- }
-}
+++ /dev/null
-/*
- * Processor reset for Freescale i.MX28 SoC.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * -----------------------------------------------------
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-.globl reset_cpu
-reset_cpu:
- ldr r0, POWER_CHARGE
- mov r1, #0x0
- str r1, [r0]
- ldr r0, POWER_MINPWR
- str r1, [r0]
- ldr r0, CLKCTRL_RESET
- mov r1, #0x1
- str r1, [r0]
-_loop_forever:
- b _loop_forever
-
-POWER_MINPWR:
- .word 0x80044020
-POWER_CHARGE:
- .word 0x80044030
-CLKCTRL_RESET:
- .word 0x800401e0
-
+++ /dev/null
-/*
- * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-#include <common.h>
-#include <asm/arch/regs-uartdbg.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Set baud rate. The settings are always 8n1:
- * 8 data bits, no parity, 1 stop bit
- */
-void serial_setbrg(void)
-{
- u32 cr;
- u32 quot;
-
- /* Disable everything */
- cr = REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGCR);
- REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR, 0);
-
- /* Calculate and set baudrate */
- quot = (CONFIG_UARTDBG_CLK * 4) / gd->baudrate;
- REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGFBRD, quot & 0x3f);
- REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGIBRD, quot >> 6);
-
- /* Set 8n1 mode, enable FIFOs */
- REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGLCR_H,
- BM_UARTDBGLCR_H_WLEN | BM_UARTDBGLCR_H_FEN);
-
- /* Enable Debug UART */
- REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR, cr);
-}
-
-int serial_init(void)
-{
- /* Disable UART */
- REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR, 0);
-
- /* Mask interrupts */
- REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGIMSC, 0);
-
- /* Set default baudrate */
- serial_setbrg();
-
- /* Enable UART */
- REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGCR,
- BM_UARTDBGCR_TXE | BM_UARTDBGCR_RXE | BM_UARTDBGCR_UARTEN);
-
- return 0;
-}
-
-/* Send a character */
-void serial_putc(const char c)
-{
- /* Wait for room in TX FIFO */
- while (REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGFR) & BM_UARTDBGFR_TXFF)
- ;
-
- /* Write the data byte */
- REG_WR(REGS_UARTDBG_BASE, HW_UARTDBGDR, c);
-
- if (c == '\n')
- serial_putc('\r');
-}
-
-void serial_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
-/* Test whether a character is in TX buffer */
-int serial_tstc(void)
-{
- /* Check if RX FIFO is not empty */
- return !(REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGFR) & BM_UARTDBGFR_RXFE);
-}
-
-/* Receive character */
-int serial_getc(void)
-{
- /* Wait while TX FIFO is empty */
- while (REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGFR) & BM_UARTDBGFR_RXFE)
- ;
-
- /* Read data byte */
- return REG_RD(REGS_UARTDBG_BASE, HW_UARTDBGDR) & 0xff;
-}
-
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/regs-timrot.h>
-
-/*
- * TIMROT gets 4 timer instances
- * Define N as 0..3 to specify
- */
-#define N 0
-
-/* Ticks per second */
-#define CONFIG_SYS_HZ 1000
-
-/* Maximum fixed count */
-#define TIMER_LOAD_VAL 0xffffffff
-
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init(void)
-{
- /*
- * Reset Timers and Rotary Encoder module
- */
-
- /* Clear SFTRST */
- REG_CLR(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL, 1 << 31);
- while (REG_RD(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL) & (1 << 31))
- ;
-
- /* Clear CLKGATE */
- REG_CLR(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL, 1 << 30);
-
- /* Set SFTRST and wait until CLKGATE is set */
- REG_SET(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL, 1 << 31);
- while (!(REG_RD(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL) & (1 << 30)))
- ;
-
- /* Clear SFTRST and CLKGATE */
- REG_CLR(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL, 1 << 31);
- REG_CLR(REGS_TIMROT_BASE, HW_TIMROT_ROTCTRL, 1 << 30);
-
- /*
- * Now initialize timer
- */
-
- /* Set fixed_count to 0 */
- REG_WR(REGS_TIMROT_BASE, HW_TIMROT_FIXED_COUNTn(N), 0);
-
- /* set UPDATE bit and 1Khz frequency */
- REG_WR(REGS_TIMROT_BASE, HW_TIMROT_TIMCTRLn(N),
- BM_TIMROT_TIMCTRLn_RELOAD | BM_TIMROT_TIMCTRLn_UPDATE |
- BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL);
-
- /* Set fixed_count to maximal value */
- REG_WR(REGS_TIMROT_BASE, HW_TIMROT_FIXED_COUNTn(N), TIMER_LOAD_VAL);
-
- /* init the timestamp and lastdec value */
- reset_timer_masked();
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
- timestamp = t;
-}
-
-/* delay x useconds AND perserve advance timstamp value */
-void udelay(unsigned long usec)
-{
- ulong tmo, tmp;
-
- if (usec >= 1000) {
- /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000;
- /* start to normalize for usec to ticks per sec */
- tmo *= CONFIG_SYS_HZ;
- /* find number of "ticks" to wait to achieve target */
- tmo /= 1000;
- /* finish normalize. */
- } else {
- /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= (1000*1000);
- }
-
- tmp = get_timer(0);
- /* get current timestamp */
- if ((tmo + tmp + 1) < tmp)
- /* if setting this fordward will roll time stamp */
- reset_timer_masked();
- /* reset "advancing" timestamp to 0, set lastdec value */
- else
- tmo += tmp;
- /* else, set advancing stamp wake up time */
-
- while (get_timer_masked() < tmo)/* loop till event */
- /*NOP*/;
-}
-
-void reset_timer_masked(void)
-{
- /* capure current decrementer value time */
- lastdec = REG_RD(REGS_TIMROT_BASE, HW_TIMROT_RUNNING_COUNTn(N));
- /* start "advancing" time stamp from 0 */
- timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
- /* current tick value */
- ulong now = REG_RD(REGS_TIMROT_BASE, HW_TIMROT_RUNNING_COUNTn(N));
-
- if (lastdec >= now) { /* normal mode (non roll) */
- /* normal mode */
- timestamp += lastdec - now;
- /* move stamp fordward with absoulte diff ticks */
- } else {
- /* we have overflow of the count down timer */
- /* nts = ts + ld + (TLV - now)
- * ts=old stamp, ld=time that passed before passing through -1
- * (TLV-now) amount of time after passing though -1
- * nts = new "advancing time stamp"...it could also roll
- * and cause problems.
- */
- timestamp += lastdec + TIMER_LOAD_VAL - now + 1;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked(unsigned long usec)
-{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- if (usec >= 1000) {
- /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000;
- /* start to normalize for usec to ticks per sec */
- tmo *= CONFIG_SYS_HZ;
- /* find number of "ticks" to wait to achieve target */
- tmo /= 1000;
- /* finish normalize. */
- } else {
- /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= (1000*1000);
- }
-
- endtime = get_timer_masked() + tmo;
-
- do {
- ulong now = get_timer_masked();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- ulong tbclk;
-
- tbclk = CONFIG_SYS_HZ;
- return tbclk;
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2010 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(SOC).a
-
-COBJS = interrupts.o serial.o generic.o iomux.o timer.o cache.o
-COBJS += $(COBJS-y)
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all: $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/cache.h>
-
-void l2_cache_enable(void)
-{
- asm("mrc 15, 0, r0, c1, c0, 1");
- asm("orr r0, r0, #0x2");
- asm("mcr 15, 0, r0, c1, c0, 1");
-}
-
-void l2_cache_disable(void)
-{
- asm("mrc 15, 0, r0, c1, c0, 1");
- asm("bic r0, r0, #0x2");
- asm("mcr 15, 0, r0, c1, c0, 1");
-}
-
-/*dummy function for L2 ON*/
-u32 get_device_type(void)
-{
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __ARCH_ARM_MACH_MX50_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX50_CRM_REGS_H__
-
-#define MXC_CCM_BASE CCM_BASE_ADDR
-#define MXC_DPLL1_BASE PLL1_BASE_ADDR
-#define MXC_DPLL2_BASE PLL2_BASE_ADDR
-#define MXC_DPLL3_BASE PLL3_BASE_ADDR
-
-/* PLL Register Offsets */
-#define MXC_PLL_DP_CTL 0x00
-#define MXC_PLL_DP_CONFIG 0x04
-#define MXC_PLL_DP_OP 0x08
-#define MXC_PLL_DP_MFD 0x0C
-#define MXC_PLL_DP_MFN 0x10
-#define MXC_PLL_DP_MFNMINUS 0x14
-#define MXC_PLL_DP_MFNPLUS 0x18
-#define MXC_PLL_DP_HFS_OP 0x1C
-#define MXC_PLL_DP_HFS_MFD 0x20
-#define MXC_PLL_DP_HFS_MFN 0x24
-#define MXC_PLL_DP_MFN_TOGC 0x28
-#define MXC_PLL_DP_DESTAT 0x2c
-
-/* PLL Register Bit definitions */
-#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
-#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
-#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
-#define MXC_PLL_DP_CTL_ADE 0x800
-#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
-#define MXC_PLL_DP_CTL_HFSM 0x80
-#define MXC_PLL_DP_CTL_PRE 0x40
-#define MXC_PLL_DP_CTL_UPEN 0x20
-#define MXC_PLL_DP_CTL_RST 0x10
-#define MXC_PLL_DP_CTL_RCP 0x8
-#define MXC_PLL_DP_CTL_PLM 0x4
-#define MXC_PLL_DP_CTL_BRM0 0x2
-#define MXC_PLL_DP_CTL_LRF 0x1
-
-#define MXC_PLL_DP_CONFIG_BIST 0x8
-#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
-#define MXC_PLL_DP_CONFIG_AREN 0x2
-#define MXC_PLL_DP_CONFIG_LDREQ 0x1
-
-#define MXC_PLL_DP_OP_MFI_OFFSET 4
-#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
-#define MXC_PLL_DP_OP_PDF_OFFSET 0
-#define MXC_PLL_DP_OP_PDF_MASK 0xF
-
-#define MXC_PLL_DP_MFD_OFFSET 0
-#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_OFFSET 0x0
-#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
-#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
-#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
-#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
-
-#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
-#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
-
-/* Register addresses of CCM*/
-#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00)
-#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04) /* Reserved */
-#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08)
-#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C)
-#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10)
-#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14)
-#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18)
-#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C)
-#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20) /* Reserved */
-#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24)
-#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28)
-#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C)
-#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30) /* Reserved */
-#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34) /* Reserved */
-#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38)
-#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C) /* Reserved */
-#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40) /* Reserved */
-#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44) /* Reserved */
-#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48)
-#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C)
-#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50)
-#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54)
-#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58)
-#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C)
-#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60)
-#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64) /* Reserved */
-#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68)
-#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C)
-#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70)
-#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74)
-#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78)
-#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C)
-#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80)
-#define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x84)
-#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x88)
-#define MXC_CCM_CSR2 (MXC_CCM_BASE + 0x8C)
-#define MXC_CCM_CLKSEQ_BYPASS (MXC_CCM_BASE + 0x90)
-#define MXC_CCM_CLK_SYS (MXC_CCM_BASE + 0x94)
-#define MXC_CCM_CLK_DDR (MXC_CCM_BASE + 0x98)
-
-/* Define the bits in register CCR */
-#define MXC_CCM_CCR_COSC_EN (1 << 12)
-#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
-#define MXC_CCM_CCR_OSCNT_OFFSET (0)
-#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
-
-/* Define the bits in register CSR */
-#define MXC_CCM_CSR_COSR_READY (1 << 5)
-#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
-#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
-#define MXC_CCM_CSR_TEMP_MON_ALARM (1 << 1)
-#define MXC_CCM_CSR_REF_EN_B (1 << 0)
-
-/* Define the bits in register CCSR */
-#define MXC_CCM_CCSR_PLL3_PFD_EN (0x1 << 13)
-#define MXC_CCM_CCSR_PLL2_PFD_EN (0x1 << 12)
-#define MXC_CCM_CCSR_PLL1_PFD_EN (0x1 << 11)
-#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 10)
-#define MXC_CCM_CCSR_LP_APM_SEL_OFFSET (1)
-#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
-#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
-#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
-#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
-#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
-#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
-#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
-#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
-#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
-
-/* Define the bits in register CACRR */
-#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
-#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
-
-/* Define the bits in register CBCDR */
-#define MXC_CCM_CBCDR_WEIM_CLK_SEL (0x1 << 27)
-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL_OFFSET (25)
-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x3 << 25)
-#define MXC_CCM_CBCDR_WEIM_PODF_OFFSET (22)
-#define MXC_CCM_CBCDR_WEIM_PODF_MASK (7 << 22)
-#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
-#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
-#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
-#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
-#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
-#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
-#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
-#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
-#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
-#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
-
-/* Define the bits in register CBCMR */
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (16)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
-#define MXC_CCM_CBCMR_DBG_APB_CLK_SEL_OFFSET (2)
-#define MXC_CCM_CBCMR_DBG_APB_CLK_SEL_MASK (0x3 << 2)
-#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
-#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
-#define MXC_CCM_CBCMR_LP_APM_SEL_OFFSET (0x1)
-
-/* Define the bits in register CSCMR1 */
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
-#define MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET (21)
-#define MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 21)
-#define MXC_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 20)
-#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET (16)
-#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK (0x7 << 16)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
-#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
-#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
-
-/* Define the bits in register CSCDR1 */
-#define MXC_CCM_CSCDR1_ESDHC3_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CSCDR1_ESDHC3_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC3_CLK_PODF_OFFSET (19)
-#define MXC_CCM_CSCDR1_ESDHC3_CLK_PODF_MASK (0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC1_CLK_PRED_OFFSET (16)
-#define MXC_CCM_CSCDR1_ESDHC1_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
-#define MXC_CCM_CSCDR1_ESDHC1_CLK_PODF_OFFSET (11)
-#define MXC_CCM_CSCDR1_ESDHC1_CLK_PODF_MASK (0x7 << 11)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
-
-/* Define the bits in register CS1CDR and CS2CDR */
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
-
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
-
-/* Define the bits in register CSCDR2 */
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
-
-/* Define the bits in register CDHIPR */
-#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
-#define MXC_CCM_CDHIPR_WEIM_CLK_SEL_BUSY (1 << 6)
-#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
-#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
-#define MXC_CCM_CDHIPR_WEIM_PODF_BUSY (1 << 2)
-#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
-#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
-
-/* Define the bits in register CDCR */
-
-#define MXC_CCM_CDCR_SW_PERIPH_CLK_DIV_REQ_STATUS (0x1 << 7)
-#define MXC_CCM_CDCR_SW_PERIPH_CLK_DIV_REQ (0x1 << 6)
-#define MXC_CCM_CDCR_SW_DVFS_EN (0x1 << 5)
-#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
-
-/* Define the bits in register CLPCR */
-#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
-#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 24)
-#define MXC_CCM_CLPCR_BYPASS_RNGB_LPM_HS (0x1 << 23)
-#define MXC_CCM_CLPCR_BYPASS_WEIM_LPM_HS (0x1 << 19)
-#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
-#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
-#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
-#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
-#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
-#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
-#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
-#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (0x1 << 2)
-#define MXC_CCM_CLPCR_LPM_OFFSET (0)
-#define MXC_CCM_CLPCR_LPM_MASK (0x3)
-
-/* Define the bits in register CISR */
-#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 26)
-#define MXC_CCM_CISR_TEMP_MON_ALARM (0x1 << 25)
-#define MXC_CCM_CISR_WEIM_CLK_SEL_LOADED (0x1 << 23)
-#define MXC_CCM_CISR_PER_CLK_SEL_LOADED (0x1 << 22)
-#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
-#define MXC_CCM_CISR_WEIM_PODF_LOADED (0x1 << 19)
-#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
-#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
-#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
-#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
-#define MXC_CCM_CISR_CAMP1_READY (0x1 << 4)
-#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
-#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
-#define MXC_CCM_CISR_LRF_PLL1 (0x1)
-
-/* Define the bits in register CIMR */
-#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 26)
-#define MXC_CCM_CIMR_MASK_TEMP_MON_ALARM (0x1 << 25)
-#define MXC_CCM_CIMR_MASK_WEIM_CLK_SEL_LOADED (0x1 << 23)
-#define MXC_CCM_CIMR_MASK_PER_CLK_SEL_LOADED (0x1 << 22)
-#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (0x1 << 20)
-#define MXC_CCM_CIMR_MASK_WEIM_PODF_LOADED (0x1 << 19)
-#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
-#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
-#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
-#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 6)
-#define MXC_CCM_CIMR_MASK_CAMP1_READY (0x1 << 4)
-#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
-#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
-#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
-
-/* Define the bits in register CCOSR */
-#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
-#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
-#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
-#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
-#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
-#define MXC_CCM_CCOSR_CKO1_SLOW_SEL (0x1 << 8)
-#define MXC_CCM_CCOSR_CKO1_EN (0x1 << 7)
-#define MXC_CCM_CCOSR_CKO1_DIV_OFFSET (4)
-#define MXC_CCM_CCOSR_CKO1_DIV_MASK (0x7 << 4)
-#define MXC_CCM_CCOSR_CKO1_SEL_OFFSET (0)
-#define MXC_CCM_CCOSR_CKO1_SEL_MASK (0xF)
-
-/* Define the bits in registers CCGRx */
-#define MXC_CCM_CCGR_CG_MASK 0x3
-
-#define MXC_CCM_CCGR0_CG15_OFFSET 30
-#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
-#define MXC_CCM_CCGR0_CG14_OFFSET 28
-#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR0_CG13_OFFSET 26
-#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR0_CG12_OFFSET 24
-#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR0_CG11_OFFSET 22
-#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR0_CG10_OFFSET 20
-#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR0_CG9_OFFSET 18
-#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR0_CG8_OFFSET 16
-#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR0_CG7_OFFSET 14
-#define MXC_CCM_CCGR0_CG6_OFFSET 12
-#define MXC_CCM_CCGR0_CG5_OFFSET 10
-#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
-#define MXC_CCM_CCGR0_CG4_OFFSET 8
-#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
-#define MXC_CCM_CCGR0_CG3_OFFSET 6
-#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
-#define MXC_CCM_CCGR0_CG2_OFFSET 4
-#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR0_CG1_OFFSET 2
-#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
-#define MXC_CCM_CCGR0_CG0_OFFSET 0
-#define MXC_CCM_CCGR0_CG0_MASK 0x3
-
-#define MXC_CCM_CCGR1_CG15_OFFSET 30
-#define MXC_CCM_CCGR1_CG14_OFFSET 28
-#define MXC_CCM_CCGR1_CG13_OFFSET 26
-#define MXC_CCM_CCGR1_CG12_OFFSET 24
-#define MXC_CCM_CCGR1_CG11_OFFSET 22
-#define MXC_CCM_CCGR1_CG10_OFFSET 20
-#define MXC_CCM_CCGR1_CG9_OFFSET 18
-#define MXC_CCM_CCGR1_CG8_OFFSET 16
-#define MXC_CCM_CCGR1_CG7_OFFSET 14
-#define MXC_CCM_CCGR1_CG6_OFFSET 12
-#define MXC_CCM_CCGR1_CG5_OFFSET 10
-#define MXC_CCM_CCGR1_CG4_OFFSET 8
-#define MXC_CCM_CCGR1_CG3_OFFSET 6
-#define MXC_CCM_CCGR1_CG2_OFFSET 4
-#define MXC_CCM_CCGR1_CG1_OFFSET 2
-#define MXC_CCM_CCGR1_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR2_CG15_OFFSET 30
-#define MXC_CCM_CCGR2_CG14_OFFSET 28
-#define MXC_CCM_CCGR2_CG13_OFFSET 26
-#define MXC_CCM_CCGR2_CG12_OFFSET 24
-#define MXC_CCM_CCGR2_CG11_OFFSET 22
-#define MXC_CCM_CCGR2_CG10_OFFSET 20
-#define MXC_CCM_CCGR2_CG9_OFFSET 18
-#define MXC_CCM_CCGR2_CG8_OFFSET 16
-#define MXC_CCM_CCGR2_CG7_OFFSET 14
-#define MXC_CCM_CCGR2_CG6_OFFSET 12
-#define MXC_CCM_CCGR2_CG5_OFFSET 10
-#define MXC_CCM_CCGR2_CG4_OFFSET 8
-#define MXC_CCM_CCGR2_CG3_OFFSET 6
-#define MXC_CCM_CCGR2_CG2_OFFSET 4
-#define MXC_CCM_CCGR2_CG1_OFFSET 2
-#define MXC_CCM_CCGR2_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR3_CG15_OFFSET 30
-#define MXC_CCM_CCGR3_CG14_OFFSET 28
-#define MXC_CCM_CCGR3_CG13_OFFSET 26
-#define MXC_CCM_CCGR3_CG12_OFFSET 24
-#define MXC_CCM_CCGR3_CG11_OFFSET 22
-#define MXC_CCM_CCGR3_CG10_OFFSET 20
-#define MXC_CCM_CCGR3_CG9_OFFSET 18
-#define MXC_CCM_CCGR3_CG8_OFFSET 16
-#define MXC_CCM_CCGR3_CG7_OFFSET 14
-#define MXC_CCM_CCGR3_CG6_OFFSET 12
-#define MXC_CCM_CCGR3_CG5_OFFSET 10
-#define MXC_CCM_CCGR3_CG4_OFFSET 8
-#define MXC_CCM_CCGR3_CG3_OFFSET 6
-#define MXC_CCM_CCGR3_CG2_OFFSET 4
-#define MXC_CCM_CCGR3_CG1_OFFSET 2
-#define MXC_CCM_CCGR3_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR4_CG15_OFFSET 30
-#define MXC_CCM_CCGR4_CG14_OFFSET 28
-#define MXC_CCM_CCGR4_CG13_OFFSET 26
-#define MXC_CCM_CCGR4_CG12_OFFSET 24
-#define MXC_CCM_CCGR4_CG11_OFFSET 22
-#define MXC_CCM_CCGR4_CG10_OFFSET 20
-#define MXC_CCM_CCGR4_CG9_OFFSET 18
-#define MXC_CCM_CCGR4_CG8_OFFSET 16
-#define MXC_CCM_CCGR4_CG7_OFFSET 14
-#define MXC_CCM_CCGR4_CG6_OFFSET 12
-#define MXC_CCM_CCGR4_CG5_OFFSET 10
-#define MXC_CCM_CCGR4_CG4_OFFSET 8
-#define MXC_CCM_CCGR4_CG3_OFFSET 6
-#define MXC_CCM_CCGR4_CG2_OFFSET 4
-#define MXC_CCM_CCGR4_CG1_OFFSET 2
-#define MXC_CCM_CCGR4_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR5_CG15_OFFSET 30
-#define MXC_CCM_CCGR5_CG14_OFFSET 28
-#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR5_CG13_OFFSET 26
-#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR5_CG12_OFFSET 24
-#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR5_CG11_OFFSET 22
-#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR5_CG10_OFFSET 20
-#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR5_CG9_OFFSET 18
-#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR5_CG8_OFFSET 16
-#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR5_CG7_OFFSET 14
-#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
-#define MXC_CCM_CCGR5_CG6_1_OFFSET 12
-#define MXC_CCM_CCGR5_CG6_2_OFFSET 13
-#define MXC_CCM_CCGR5_CG6_OFFSET 12
-#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12)
-#define MXC_CCM_CCGR5_CG5_OFFSET 10
-#define MXC_CCM_CCGR5_CG4_OFFSET 8
-#define MXC_CCM_CCGR5_CG3_OFFSET 6
-#define MXC_CCM_CCGR5_CG2_OFFSET 4
-#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR5_CG1_OFFSET 2
-#define MXC_CCM_CCGR5_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR6_CG15_OFFSET 30
-#define MXC_CCM_CCGR6_CG14_OFFSET 28
-#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR6_CG13_OFFSET 26
-#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR6_CG12_OFFSET 24
-#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR6_CG11_OFFSET 22
-#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR6_CG10_OFFSET 20
-#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR6_CG9_OFFSET 18
-#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR6_CG8_OFFSET 16
-#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR6_CG7_OFFSET 14
-#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14)
-#define MXC_CCM_CCGR6_CG6_OFFSET 12
-#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12)
-#define MXC_CCM_CCGR6_CG5_OFFSET 10
-#define MXC_CCM_CCGR6_CG5_MASK (0x3 << 10)
-#define MXC_CCM_CCGR6_CG4_OFFSET 8
-#define MXC_CCM_CCGR6_CG4_MASK (0x3 << 8)
-#define MXC_CCM_CCGR6_CG3_OFFSET 6
-#define MXC_CCM_CCGR6_CG2_OFFSET 4
-#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR6_CG1_OFFSET 2
-#define MXC_CCM_CCGR6_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR7_CG15_OFFSET 30
-#define MXC_CCM_CCGR7_CG14_OFFSET 28
-#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR7_CG13_OFFSET 26
-#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR7_CG12_OFFSET 24
-#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR7_CG11_OFFSET 22
-#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR7_CG10_OFFSET 20
-#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR7_CG9_OFFSET 18
-#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR7_CG8_OFFSET 16
-#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR7_CG7_OFFSET 14
-#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14)
-#define MXC_CCM_CCGR7_CG6_OFFSET 12
-#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12)
-#define MXC_CCM_CCGR7_CG5_OFFSET 10
-#define MXC_CCM_CCGR7_CG4_OFFSET 8
-#define MXC_CCM_CCGR7_CG3_OFFSET 6
-#define MXC_CCM_CCGR7_CG2_OFFSET 4
-#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR7_CG1_OFFSET 2
-#define MXC_CCM_CCGR7_CG0_OFFSET 0
-
-/* Define the bits in registers CLKSEQ_BYPASS */
-#define MXC_CCM_CLKSEQ_BYPASS_ELCDIF_PIX_OFFSET 14
-#define MXC_CCM_CLKSEQ_BYPASS_ELCDIF_PIX_MASK (0x3 << 14)
-#define MXC_CCM_CLKSEQ_BYPASS_EPDC_PIX_OFFSET 12
-#define MXC_CCM_CLKSEQ_BYPASS_EPDC_PIX_MASK (0x3 << 12)
-#define MXC_CCM_CLKSEQ_BYPASS_MSHCX_OFFSET 10
-#define MXC_CCM_CLKSEQ_BYPASS_MSHCX_MASK (0x3 << 10)
-#define MXC_CCM_CLKSEQ_BYPASS_BCH_OFFSET 8
-#define MXC_CCM_CLKSEQ_BYPASS_BCH_MASK (0x3 << 8)
-#define MXC_CCM_CLKSEQ_BYPASS_GPMI_OFFSET 6
-#define MXC_CCM_CLKSEQ_BYPASS_GPMI_MASK (0x3 << 6)
-#define MXC_CCM_CLKSEQ_BYPASS_EPDC_OFFSET 4
-#define MXC_CCM_CLKSEQ_BYPASS_EPDC_MASK (0x3 << 4)
-#define MXC_CCM_CLKSEQ_BYPASS_DISPLY_AXI_OFFSET 2
-#define MXC_CCM_CLKSEQ_BYPASS_DISPLY_AXI_MASK (0x3 << 2)
-#define MXC_CCM_CLKSEQ_BYPASS_SYS_CLK_1 (0x1 << 1)
-#define MXC_CCM_CLKSEQ_BYPASS_SYS_CLK_0 (0x1 << 0)
-
-/* Define the bits in registers CLK_SYS */
-#define MXC_CCM_CLK_SYS_XTAL_CLKGATE_OFFSET 30
-#define MXC_CCM_CLK_SYS_XTAL_CLKGATE_MASK (0x3 << 30)
-#define MXC_CCM_CLK_SYS_PLL_CLKGATE_OFFSET 28
-#define MXC_CCM_CLK_SYS_PLL_CLKGATE_MASK (0x3 << 28)
-#define MXC_CCM_CLK_SYS_DIV_XTAL_OFFSET 6
-#define MXC_CCM_CLK_SYS_DIV_XTAL_MASK (0xf << 6)
-#define MXC_CCM_CLK_SYS_DIV_PLL_OFFSET 0
-#define MXC_CCM_CLK_SYS_DIV_PLL_MASK (0x3f << 0)
-
-/* Define the bits in registers CLK_DDR */
-#define MXC_CCM_CLK_DDR_DDR_CLKGATE_OFFSET (30)
-#define MXC_CCM_CLK_DDR_DDR_CLKGATE_MASK (0x3 << 30)
-#define MXC_CCM_CLK_DDR_DDR_PFD_SEL (1 << 6)
-#define MXC_CCM_CLK_DDR_DDR_DIV_PLL_OFFSET (0)
-#define MXC_CCM_CLK_DDR_DDR_DIV_PLL_MASK (0x3F)
-
-
-#define MXC_GPC_BASE (IO_ADDRESS(GPC_BASE_ADDR))
-#define MXC_DPTC_LP_BASE (MXC_GPC_BASE + 0x80)
-#define MXC_DPTC_GP_BASE (MXC_GPC_BASE + 0x100)
-#define MXC_DVFS_CORE_BASE (MXC_GPC_BASE + 0x180)
-#define MXC_DVFS_PER_BASE (MXC_GPC_BASE + 0x1C4)
-#define MXC_PGC_IPU_BASE (MXC_GPC_BASE + 0x220)
-#define MXC_PGC_VPU_BASE (MXC_GPC_BASE + 0x240)
-#define MXC_PGC_GPU_BASE (MXC_GPC_BASE + 0x260)
-#define MXC_SRPG_NEON_BASE (MXC_GPC_BASE + 0x280)
-#define MXC_SRPG_ARM_BASE (MXC_GPC_BASE + 0x2A0)
-#define MXC_SRPG_EMPGC0_BASE (MXC_GPC_BASE + 0x2C0)
-#define MXC_SRPG_EMPGC1_BASE (MXC_GPC_BASE + 0x2D0)
-#define MXC_SRPG_MEGAMIX_BASE (MXC_GPC_BASE + 0x2E0)
-#define MXC_SRPG_EMI_BASE (MXC_GPC_BASE + 0x300)
-
-/* DVFS CORE */
-#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
-#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
-#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
-#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
-#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
-#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
-#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
-#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
-#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
-#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
-#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
-#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
-#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
-#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
-#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
-#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
-#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
-
-/* DVFS PER */
-#define MXC_DVFSPER_LTR0 (MXC_DVFS_PER_BASE)
-#define MXC_DVFSPER_LTR1 (MXC_DVFS_PER_BASE + 0x04)
-#define MXC_DVFSPER_LTR2 (MXC_DVFS_PER_BASE + 0x08)
-#define MXC_DVFSPER_LTR3 (MXC_DVFS_PER_BASE + 0x0C)
-#define MXC_DVFSPER_LTBR0 (MXC_DVFS_PER_BASE + 0x10)
-#define MXC_DVFSPER_LTBR1 (MXC_DVFS_PER_BASE + 0x14)
-#define MXC_DVFSPER_PMCR0 (MXC_DVFS_PER_BASE + 0x18)
-#define MXC_DVFSPER_PMCR1 (MXC_DVFS_PER_BASE + 0x1C)
-
-/* GPC */
-#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0)
-#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4)
-#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8)
-#define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC)
-#define MXC_GPC_NEON (MXC_GPC_BASE + 0x10)
-
-/* PGC */
-#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
-#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
-#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
-#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
-#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
-#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
-
-#define MXC_PGCR_PCR 1
-#define MXC_SRPGCR_PCR 1
-#define MXC_EMPGCR_PCR 1
-#define MXC_PGSR_PSR 1
-
-
-#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
-#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
-
-/* SRPG */
-#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
-#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
-#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
-
-#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
-#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
-#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
-
-#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
-#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
-#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
-
-#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
-#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
-#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
-
-#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
-#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
-#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
-
-#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
-#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
-#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
-
-#endif /* __ARCH_ARM_MACH_MX50_CRM_REGS_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mx50.h>
-#include <asm/errno.h>
-#include <asm/io.h>
-#include "crm_regs.h"
-#ifdef CONFIG_CMD_CLOCK
-#include <asm/clock.h>
-#endif
-#include <div64.h>
-#ifdef CONFIG_ARCH_CPU_INIT
-#include <asm/cache-cp15.h>
-#endif
-
-enum pll_clocks {
- PLL1_CLK = MXC_DPLL1_BASE,
- PLL2_CLK = MXC_DPLL2_BASE,
- PLL3_CLK = MXC_DPLL3_BASE,
-};
-
-enum pll_sw_clocks {
- PLL1_SW_CLK,
- PLL2_SW_CLK,
- PLL3_SW_CLK,
-};
-
-#define AHB_CLK_ROOT 133333333
-#define IPG_CLK_ROOT 66666666
-#define IPG_PER_CLK_ROOT 40000000
-
-#ifdef CONFIG_CMD_CLOCK
-#define SZ_DEC_1M 1000000
-#define PLL_PD_MAX 16 /* Actual pd+1 */
-#define PLL_MFI_MAX 15
-#define PLL_MFI_MIN 5
-#define ARM_DIV_MAX 8
-#define IPG_DIV_MAX 4
-#define AHB_DIV_MAX 8
-#define EMI_DIV_MAX 8
-#define NFC_DIV_MAX 8
-
-struct fixed_pll_mfd {
- u32 ref_clk_hz;
- u32 mfd;
-};
-
-const struct fixed_pll_mfd fixed_mfd[4] = {
- {0, 0}, /* reserved */
- {0, 0}, /* reserved */
- {CONFIG_MX50_HCLK_FREQ, 24 * 16}, /* 384 */
- {0, 0}, /* reserved */
-};
-
-struct pll_param {
- u32 pd;
- u32 mfi;
- u32 mfn;
- u32 mfd;
-};
-
-#define PLL_FREQ_MAX(_ref_clk_) \
- (4 * _ref_clk_ * PLL_MFI_MAX)
-#define PLL_FREQ_MIN(_ref_clk_) \
- ((2 * _ref_clk_ * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
-#define MAX_DDR_CLK 420000000
-#define AHB_CLK_MAX 133333333
-#define IPG_CLK_MAX (AHB_CLK_MAX / 2)
-#define NFC_CLK_MAX 25000000
-#define HSP_CLK_MAX 133333333
-#endif
-
-static u32 __decode_pll(enum pll_clocks pll, u32 infreq)
-{
- long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
- unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
- s64 temp;
-
- dp_ctl = __REG(pll + MXC_PLL_DP_CTL);
- pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
- dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
-
- if (pll_hfsm == 0) {
- dp_op = __REG(pll + MXC_PLL_DP_OP);
- dp_mfd = __REG(pll + MXC_PLL_DP_MFD);
- dp_mfn = __REG(pll + MXC_PLL_DP_MFN);
- } else {
- dp_op = __REG(pll + MXC_PLL_DP_HFS_OP);
- dp_mfd = __REG(pll + MXC_PLL_DP_HFS_MFD);
- dp_mfn = __REG(pll + MXC_PLL_DP_HFS_MFN);
- }
- pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
- mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
- mfi = (mfi <= 5) ? 5 : mfi;
- mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
- mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
- /* Sign extend to 32-bits */
- if (mfn >= 0x04000000) {
- mfn |= 0xFC000000;
- mfn_abs = -mfn;
- }
-
- ref_clk = 2 * infreq;
- if (dbl != 0)
- ref_clk *= 2;
-
- ref_clk /= (pdf + 1);
- temp = (u64) ref_clk * mfn_abs;
- do_div(temp, mfd + 1);
- if (mfn < 0)
- temp = -temp;
- temp = (ref_clk * mfi) + temp;
-
- return temp;
-}
-
-static u32 __get_mcu_main_clk(void)
-{
- u32 reg, freq;
- reg = (__REG(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
- MXC_CCM_CACRR_ARM_PODF_OFFSET;
- freq = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ);
- return freq / (reg + 1);
-}
-
-/*
- * This function returns the low power audio clock.
- */
-u32 __get_lp_apm(void)
-{
- u32 ret_val = 0;
- u32 cbcmr = __REG(MXC_CCM_CBCMR);
-
- if (((cbcmr >> MXC_CCM_CBCMR_LP_APM_SEL_OFFSET) & 0x1) == 0)
- ret_val = CONFIG_MX50_HCLK_FREQ;
- else
- ret_val = ((32768 * 1024));
-
- return ret_val;
-}
-
-static u32 __get_periph_clk(void)
-{
- u32 reg;
- reg = __REG(MXC_CCM_CBCDR);
-
- switch ((reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL_MASK) >>
- MXC_CCM_CBCDR_PERIPH_CLK_SEL_OFFSET) {
- case 0:
- return __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ);
- case 1:
- return __decode_pll(PLL2_CLK, CONFIG_MX50_HCLK_FREQ);
- case 2:
- return __decode_pll(PLL3_CLK, CONFIG_MX50_HCLK_FREQ);
- default:
- return __get_lp_apm();
- }
-}
-
-static u32 __get_ipg_clk(void)
-{
- u32 ahb_podf, ipg_podf;
-
- ahb_podf = __REG(MXC_CCM_CBCDR);
- ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
- MXC_CCM_CBCDR_IPG_PODF_OFFSET;
- ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
- MXC_CCM_CBCDR_AHB_PODF_OFFSET;
- return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
-}
-
-static u32 __get_ipg_per_clk(void)
-{
- u32 pred1, pred2, podf, clk;
- if (__REG(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
- return __get_ipg_clk();
-
- clk = __REG(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL ?
- __get_lp_apm() : __get_periph_clk();
-
- podf = __REG(MXC_CCM_CBCDR);
- pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
- pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
- podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
-
- return clk / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
-}
-
-static u32 __get_uart_clk(void)
-{
- u32 freq = 0, reg, pred, podf;
- reg = __REG(MXC_CCM_CSCMR1);
- switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
- MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
- case 0x0:
- freq = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ);
- break;
- case 0x1:
- freq = __decode_pll(PLL2_CLK, CONFIG_MX50_HCLK_FREQ);
- break;
- case 0x2:
- freq = __decode_pll(PLL3_CLK, CONFIG_MX50_HCLK_FREQ);
- break;
- case 0x3:
- freq = __get_lp_apm();
- break;
- default:
- break;
- }
-
- reg = __REG(MXC_CCM_CSCDR1);
-
- pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
- MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
-
- podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
- MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
- freq /= (pred + 1) * (podf + 1);
-
- return freq;
-}
-
-
-static u32 __get_cspi_clk(void)
-{
- u32 ret_val = 0, pdf, pre_pdf, clk_sel, div;
- u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
- u32 cscdr2 = __REG(MXC_CCM_CSCDR2);
-
- pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
- >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
- pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
- >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
- clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
- >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
-
- div = (pre_pdf + 1) * (pdf + 1);
-
- switch (clk_sel) {
- case 0:
- ret_val = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ) / div;
- break;
- case 1:
- ret_val = __decode_pll(PLL2_CLK, CONFIG_MX50_HCLK_FREQ) / div;
- break;
- case 2:
- ret_val = __decode_pll(PLL3_CLK, CONFIG_MX50_HCLK_FREQ) / div;
- break;
- default:
- ret_val = __get_lp_apm() / div;
- break;
- }
-
- return ret_val;
-}
-
-static u32 __get_axi_a_clk(void)
-{
- u32 cbcdr = __REG(MXC_CCM_CBCDR);
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
- >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
-
- return __get_periph_clk() / (pdf + 1);
-}
-
-static u32 __get_axi_b_clk(void)
-{
- u32 cbcdr = __REG(MXC_CCM_CBCDR);
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
- >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
-
- return __get_periph_clk() / (pdf + 1);
-}
-
-static u32 __get_ahb_clk(void)
-{
- u32 cbcdr = __REG(MXC_CCM_CBCDR);
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_AHB_PODF_MASK) \
- >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
-
- return __get_periph_clk() / (pdf + 1);
-}
-
-
-static u32 __get_emi_slow_clk(void)
-{
- u32 cbcdr = __REG(MXC_CCM_CBCDR);
- u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_WEIM_CLK_SEL;
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_WEIM_PODF_MASK) \
- >> MXC_CCM_CBCDR_WEIM_PODF_OFFSET;
-
- if (emi_clk_sel)
- return __get_ahb_clk() / (pdf + 1);
-
- return __get_periph_clk() / (pdf + 1);
-}
-
-static u32 __get_sys_clk(void)
-{
- u32 ret_val = 0, clk, sys_pll_div;
- u32 clkseq_bypass = __REG(MXC_CCM_CLKSEQ_BYPASS);
-
- /* Fixme Not handle OSC and PFD1 mux */
- if ((clkseq_bypass & MXC_CCM_CLKSEQ_BYPASS_SYS_CLK_1) &&
- clkseq_bypass & MXC_CCM_CLKSEQ_BYPASS_SYS_CLK_0) {
- sys_pll_div = __REG(MXC_CCM_CLK_SYS) \
- & MXC_CCM_CLK_SYS_DIV_PLL_MASK;
- clk = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ);
- if (sys_pll_div)
- clk /= sys_pll_div;
- ret_val = clk;
- } else if ((clkseq_bypass & MXC_CCM_CLKSEQ_BYPASS_SYS_CLK_0) == 0) {
- ret_val = CONFIG_MX50_HCLK_FREQ; /* OSC */
- } else {
-
- printf("Warning, Fixme Not handle PFD1 mux\n");
- }
-
- return ret_val;
-
-}
-static u32 __get_ddr_clk(void)
-{
- u32 ret_val = 0, clk, ddr_pll_div;
- u32 clk_ddr = __REG(MXC_CCM_CLK_DDR);
- u32 ddr_clk_sel = clk_ddr & MXC_CCM_CLK_DDR_DDR_PFD_SEL;
-
- if (!ddr_clk_sel) {
- ddr_pll_div = clk_ddr & \
- MXC_CCM_CLK_DDR_DDR_DIV_PLL_MASK;
- clk = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ);
- if (ddr_pll_div)
- clk /= ddr_pll_div;
- ret_val = clk;
- } else {
-
- printf("Warning, Fixme Not handle PFD1 mux\n");
- }
-
- return ret_val;
-}
-
-#ifdef CONFIG_CMD_MMC
-static u32 __get_esdhc1_clk(void)
-{
- u32 ret_val = 0, div, pre_pdf, pdf;
- u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
- u32 cscdr1 = __REG(MXC_CCM_CSCDR1);
- u32 esdh1_clk_sel;
-
- esdh1_clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK) \
- >> MXC_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
- pre_pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC1_CLK_PRED_MASK) \
- >> MXC_CCM_CSCDR1_ESDHC1_CLK_PRED_OFFSET;
- pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC1_CLK_PODF_MASK) \
- >> MXC_CCM_CSCDR1_ESDHC1_CLK_PODF_OFFSET ;
-
- div = (pre_pdf + 1) * (pdf + 1);
-
- switch (esdh1_clk_sel) {
- case 0:
- ret_val = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ);
- break;
- case 1:
- ret_val = __decode_pll(PLL2_CLK, CONFIG_MX50_HCLK_FREQ);
- break;
- case 2:
- ret_val = __decode_pll(PLL3_CLK, CONFIG_MX50_HCLK_FREQ);
- break;
- case 3:
- ret_val = __get_lp_apm();
- break;
- default:
- break;
- }
-
- ret_val /= div;
-
- return ret_val;
-}
-
-static u32 __get_esdhc3_clk(void)
-{
- u32 ret_val = 0, div, pre_pdf, pdf;
- u32 esdh3_clk_sel;
- u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
- u32 cscdr1 = __REG(MXC_CCM_CSCDR1);
- esdh3_clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK) \
- >> MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET;
- pre_pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC3_CLK_PRED_MASK) \
- >> MXC_CCM_CSCDR1_ESDHC3_CLK_PRED_OFFSET;
- pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC3_CLK_PODF_MASK) \
- >> MXC_CCM_CSCDR1_ESDHC3_CLK_PODF_OFFSET ;
-
- div = (pre_pdf + 1) * (pdf + 1);
-
- switch (esdh3_clk_sel) {
- case 0:
- ret_val = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ);
- break;
- case 1:
- ret_val = __decode_pll(PLL2_CLK, CONFIG_MX50_HCLK_FREQ);
- break;
- case 2:
- ret_val = __decode_pll(PLL3_CLK, CONFIG_MX50_HCLK_FREQ);
- break;
- case 3:
- ret_val = __get_lp_apm();
- break;
- case 5 ... 8:
- puts("Warning, Fixme,not handle PFD mux\n");
-
- break;
- default:
- break;
- }
-
- ret_val /= div;
-
- return ret_val;
-}
-
-static u32 __get_esdhc2_clk(void)
-{
- u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
- u32 esdh2_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ESDHC2_CLK_SEL;
- if (esdh2_clk_sel)
- return __get_esdhc3_clk();
-
- return __get_esdhc1_clk();
-}
-
-static u32 __get_esdhc4_clk(void)
-{
- u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
- u32 esdh4_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
- if (esdh4_clk_sel)
- return __get_esdhc3_clk();
-
- return __get_esdhc1_clk();
-}
-#endif
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
- switch (clk) {
- case MXC_ARM_CLK:
- return __get_mcu_main_clk();
- case MXC_PER_CLK:
- return __get_periph_clk();
- case MXC_AHB_CLK:
- return __get_ahb_clk();
- case MXC_IPG_CLK:
- return __get_ipg_clk();
- case MXC_IPG_PERCLK:
- return __get_ipg_per_clk();
- case MXC_UART_CLK:
- return __get_uart_clk();
-#ifdef CONFIG_IMX_CSPI
- case MXC_CSPI_CLK:
- return __get_cspi_clk();
-#endif
- case MXC_AXI_A_CLK:
- return __get_axi_a_clk();
- case MXC_AXI_B_CLK:
- return __get_axi_b_clk();
- case MXC_EMI_SLOW_CLK:
- return __get_emi_slow_clk();
- case MXC_DDR_CLK:
- return __get_ddr_clk();
-#ifdef CONFIG_CMD_MMC
- case MXC_ESDHC_CLK:
- return __get_esdhc1_clk();
- case MXC_ESDHC2_CLK:
- return __get_esdhc2_clk();
- case MXC_ESDHC3_CLK:
- return __get_esdhc3_clk();
- case MXC_ESDHC4_CLK:
- return __get_esdhc4_clk();
-#endif
- default:
- break;
- }
- return -1;
-}
-
-void mxc_dump_clocks(void)
-{
- u32 freq;
- freq = __decode_pll(PLL1_CLK, CONFIG_MX50_HCLK_FREQ);
- printf("mx50 pll1: %dMHz\n", freq / 1000000);
- freq = __decode_pll(PLL2_CLK, CONFIG_MX50_HCLK_FREQ);
- printf("mx50 pll2: %dMHz\n", freq / 1000000);
- freq = __decode_pll(PLL3_CLK, CONFIG_MX50_HCLK_FREQ);
- printf("mx50 pll3: %dMHz\n", freq / 1000000);
- printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
- printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
- printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
-#ifdef CONFIG_IMX_ECSPI
- printf("cspi clock : %dHz\n", mxc_get_clock(MXC_CSPI_CLK));
-#endif
- printf("ahb clock : %dHz\n", mxc_get_clock(MXC_AHB_CLK));
- printf("axi_a clock : %dHz\n", mxc_get_clock(MXC_AXI_A_CLK));
- printf("axi_b clock : %dHz\n", mxc_get_clock(MXC_AXI_B_CLK));
- printf("weim_clock : %dHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK));
- printf("ddr clock : %dHz\n", mxc_get_clock(MXC_DDR_CLK));
-#ifdef CONFIG_CMD_MMC
- printf("esdhc1 clock : %dHz\n", mxc_get_clock(MXC_ESDHC_CLK));
- printf("esdhc2 clock : %dHz\n", mxc_get_clock(MXC_ESDHC2_CLK));
- printf("esdhc3 clock : %dHz\n", mxc_get_clock(MXC_ESDHC3_CLK));
- printf("esdhc4 clock : %dHz\n", mxc_get_clock(MXC_ESDHC4_CLK));
-#endif
-}
-
-#ifdef CONFIG_CMD_CLOCK
-/* precondition: m>0 and n>0. Let g=gcd(m,n). */
-static int gcd(int m, int n)
-{
- int t;
- while (m > 0) {
- if (n > m) {
- t = m;
- m = n;
- n = t;
- } /* swap */
- m -= n;
- }
- return n;
-}
-
-/*!
- * This is to calculate various parameters based on reference clock and
- * targeted clock based on the equation:
- * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
- * This calculation is based on a fixed MFD value for simplicity.
- *
- * @param ref reference clock freq in Hz
- * @param target targeted clock in Hz
- * @param pll pll_param structure.
- *
- * @return 0 if successful; non-zero otherwise.
- */
-static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
-{
- u64 pd, mfi = 1, mfn, mfd, t1;
- u32 n_target = target;
- u32 n_ref = ref, i;
-
- /*
- * Make sure targeted freq is in the valid range.
- * Otherwise the following calculation might be wrong!!!
- */
- if (n_target < PLL_FREQ_MIN(ref) ||
- n_target > PLL_FREQ_MAX(ref)) {
- printf("Targeted peripheral clock should be"
- "within [%d - %d]\n",
- PLL_FREQ_MIN(ref) / SZ_DEC_1M,
- PLL_FREQ_MAX(ref) / SZ_DEC_1M);
- return -1;
- }
-
- for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
- if (fixed_mfd[i].ref_clk_hz == ref) {
- mfd = fixed_mfd[i].mfd;
- break;
- }
- }
-
- if (i == ARRAY_SIZE(fixed_mfd))
- return -1;
-
- /* Use n_target and n_ref to avoid overflow */
- for (pd = 1; pd <= PLL_PD_MAX; pd++) {
- t1 = n_target * pd;
- do_div(t1, (4 * n_ref));
- mfi = t1;
- if (mfi > PLL_MFI_MAX)
- return -1;
- else if (mfi < 5)
- continue;
- break;
- }
- /* Now got pd and mfi already */
- /*
- mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
- */
- t1 = n_target * pd;
- do_div(t1, 4);
- t1 -= n_ref * mfi;
- t1 *= mfd;
- do_div(t1, n_ref);
- mfn = t1;
-#ifdef CMD_CLOCK_DEBUG
- printf("%d: ref=%d, target=%d, pd=%d,"
- "mfi=%d,mfn=%d, mfd=%d\n",
- __LINE__, ref, (u32)n_target,
- (u32)pd, (u32)mfi, (u32)mfn,
- (u32)mfd);
-#endif
- i = 1;
- if (mfn != 0)
- i = gcd(mfd, mfn);
- pll->pd = (u32)pd;
- pll->mfi = (u32)mfi;
- do_div(mfn, i);
- pll->mfn = (u32)mfn;
- do_div(mfd, i);
- pll->mfd = (u32)mfd;
-
- return 0;
-}
-
-int clk_info(u32 clk_type)
-{
- switch (clk_type) {
- case CPU_CLK:
- printf("CPU Clock: %dHz\n",
- mxc_get_clock(MXC_ARM_CLK));
- break;
- case PERIPH_CLK:
- printf("Peripheral Clock: %dHz\n",
- mxc_get_clock(MXC_PER_CLK));
- break;
- case AHB_CLK:
- printf("AHB Clock: %dHz\n",
- mxc_get_clock(MXC_AHB_CLK));
- break;
- case IPG_CLK:
- printf("IPG Clock: %dHz\n",
- mxc_get_clock(MXC_IPG_CLK));
- break;
- case IPG_PERCLK:
- printf("IPG_PER Clock: %dHz\n",
- mxc_get_clock(MXC_IPG_PERCLK));
- break;
- case UART_CLK:
- printf("UART Clock: %dHz\n",
- mxc_get_clock(MXC_UART_CLK));
- break;
- case CSPI_CLK:
- printf("CSPI Clock: %dHz\n",
- mxc_get_clock(MXC_CSPI_CLK));
- break;
- case DDR_CLK:
- printf("DDR Clock: %dHz\n",
- mxc_get_clock(MXC_DDR_CLK));
- break;
- case ALL_CLK:
- printf("cpu clock: %dMHz\n",
- mxc_get_clock(MXC_ARM_CLK) / SZ_DEC_1M);
- mxc_dump_clocks();
- break;
- default:
- printf("Unsupported clock type! :(\n");
- }
-
- return 0;
-}
-
-#define calc_div(target_clk, src_clk, limit) ({ \
- u32 tmp = 0; \
- if ((src_clk % target_clk) <= 100) \
- tmp = src_clk / target_clk; \
- else \
- tmp = (src_clk / target_clk) + 1; \
- if (tmp > limit) \
- tmp = limit; \
- (tmp - 1); \
- })
-
-u32 calc_per_cbcdr_val(u32 per_clk, u32 cbcmr)
-{
- u32 cbcdr = __REG(MXC_CCM_CBCDR);
- u32 tmp_clk = 0, div = 0, clk_sel = 0;
-
- cbcdr &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
-
- /* emi_slow_podf divider */
- tmp_clk = __get_emi_slow_clk();
- clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
- if (clk_sel) {
- div = calc_div(tmp_clk, per_clk, 8);
- cbcdr &= ~MXC_CCM_CBCDR_EMI_PODF_MASK;
- cbcdr |= (div << MXC_CCM_CBCDR_EMI_PODF_OFFSET);
- }
-
- /* axi_b_podf divider */
- tmp_clk = __get_axi_b_clk();
- div = calc_div(tmp_clk, per_clk, 8);
- cbcdr &= ~MXC_CCM_CBCDR_AXI_B_PODF_MASK;
- cbcdr |= (div << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET);
-
- /* axi_b_podf divider */
- tmp_clk = __get_axi_a_clk();
- div = calc_div(tmp_clk, per_clk, 8);
- cbcdr &= ~MXC_CCM_CBCDR_AXI_A_PODF_MASK;
- cbcdr |= (div << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET);
-
- /* ahb podf divider */
- tmp_clk = AHB_CLK_ROOT;
- div = calc_div(tmp_clk, per_clk, 8);
- cbcdr &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
- cbcdr |= (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET);
-
- return cbcdr;
-}
-
-#define CHANGE_PLL_SETTINGS(base, pd, mfi, mfn, mfd) \
- { \
- writel(0x1232, base + PLL_DP_CTL); \
- writel(0x2, base + PLL_DP_CONFIG); \
- writel(((pd - 1) << 0) | (mfi << 4), \
- base + PLL_DP_OP); \
- writel(mfn, base + PLL_DP_MFN); \
- writel(mfd - 1, base + PLL_DP_MFD); \
- writel(((pd - 1) << 0) | (mfi << 4), \
- base + PLL_DP_HFS_OP); \
- writel(mfn, base + PLL_DP_HFS_MFN); \
- writel(mfd - 1, base + PLL_DP_HFS_MFD); \
- writel(0x1232, base + PLL_DP_CTL); \
- while (!readl(base + PLL_DP_CTL) & 0x1) \
- ; \
- }
-
-int config_pll_clk(enum pll_clocks pll, struct pll_param *pll_param)
-{
- u32 ccsr = readl(CCM_BASE_ADDR + CLKCTL_CCSR);
- u32 pll_base = pll;
-
- switch (pll) {
- case PLL1_CLK:
- /* Switch ARM to PLL2 clock */
- writel(ccsr | 0x4, CCM_BASE_ADDR + CLKCTL_CCSR);
- CHANGE_PLL_SETTINGS(pll_base, pll_param->pd,
- pll_param->mfi, pll_param->mfn,
- pll_param->mfd);
- /* Switch back */
- writel(ccsr & ~0x4, CCM_BASE_ADDR + CLKCTL_CCSR);
- break;
- case PLL2_CLK:
- /* Switch to pll2 bypass clock */
- writel(ccsr | 0x2, CCM_BASE_ADDR + CLKCTL_CCSR);
- CHANGE_PLL_SETTINGS(pll_base, pll_param->pd,
- pll_param->mfi, pll_param->mfn,
- pll_param->mfd);
- /* Switch back */
- writel(ccsr & ~0x2, CCM_BASE_ADDR + CLKCTL_CCSR);
- break;
- case PLL3_CLK:
- /* Switch to pll3 bypass clock */
- writel(ccsr | 0x1, CCM_BASE_ADDR + CLKCTL_CCSR);
- CHANGE_PLL_SETTINGS(pll_base, pll_param->pd,
- pll_param->mfi, pll_param->mfn,
- pll_param->mfd);
- /* Switch back */
- writel(ccsr & ~0x1, CCM_BASE_ADDR + CLKCTL_CCSR);
- break;
- default:
- return -1;
- }
-
- return 0;
-}
-
-int config_core_clk(u32 ref, u32 freq)
-{
- int ret = 0;
- u32 pll = 0;
- struct pll_param pll_param;
-
- memset(&pll_param, 0, sizeof(struct pll_param));
-
- /* The case that periph uses PLL1 is not considered here */
- pll = freq;
- ret = calc_pll_params(ref, pll, &pll_param);
- if (ret != 0) {
- printf("Can't find pll parameters: %d\n",
- ret);
- return ret;
- }
-
- return config_pll_clk(PLL1_CLK, &pll_param);
-}
-
-int config_periph_clk(u32 ref, u32 freq)
-{
- int ret = 0;
- u32 pll = freq;
- struct pll_param pll_param;
-
- memset(&pll_param, 0, sizeof(struct pll_param));
-
- if (__REG(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
- /* Actually this case is not considered here */
- ret = calc_pll_params(ref, pll, &pll_param);
- if (ret != 0) {
- printf("Can't find pll parameters: %d\n",
- ret);
- return ret;
- }
- switch ((__REG(MXC_CCM_CBCMR) & \
- MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
- MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
- case 0:
- return config_pll_clk(PLL1_CLK, &pll_param);
- break;
- case 1:
- return config_pll_clk(PLL3_CLK, &pll_param);
- break;
- default:
- return -1;
- }
- } else {
- u32 old_cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
- u32 new_cbcdr = calc_per_cbcdr_val(pll, old_cbcmr);
-
- /* Switch peripheral to PLL3 */
- writel(0x00015154, CCM_BASE_ADDR + CLKCTL_CBCMR);
- writel(0x02888945, CCM_BASE_ADDR + CLKCTL_CBCDR);
-
- /* Make sure change is effective */
- while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
- ;
-
- /* Setup PLL2 */
- ret = calc_pll_params(ref, pll, &pll_param);
- if (ret != 0) {
- printf("Can't find pll parameters: %d\n",
- ret);
- return ret;
- }
- config_pll_clk(PLL2_CLK, &pll_param);
-
- /* Switch peripheral back */
- writel(new_cbcdr, CCM_BASE_ADDR + CLKCTL_CBCDR);
- writel(old_cbcmr, CCM_BASE_ADDR + CLKCTL_CBCMR);
-
- /* Make sure change is effective */
- while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
- ;
- puts("\n");
- }
-
- return 0;
-}
-
-int config_ddr_clk(u32 emi_clk)
-{
- u32 clk_src;
- s32 shift = 0, clk_sel, div = 1;
- u32 cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
- u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
-
- if (emi_clk > MAX_DDR_CLK) {
- printf("DDR clock should be less than"
- "%d MHz, assuming max value \n",
- (MAX_DDR_CLK / SZ_DEC_1M));
- emi_clk = MAX_DDR_CLK;
- }
-
- clk_src = __get_periph_clk();
- /* Find DDR clock input */
- clk_sel = (cbcmr >> 10) & 0x3;
- switch (clk_sel) {
- case 0:
- shift = 16;
- break;
- case 1:
- shift = 19;
- break;
- case 2:
- shift = 22;
- break;
- case 3:
- shift = 10;
- break;
- default:
- return -1;
- }
-
- if ((clk_src % emi_clk) == 0)
- div = clk_src / emi_clk;
- else
- div = (clk_src / emi_clk) + 1;
- if (div > 8)
- div = 8;
-
- cbcdr = cbcdr & ~(0x7 << shift);
- cbcdr |= ((div - 1) << shift);
- writel(cbcdr, CCM_BASE_ADDR + CLKCTL_CBCDR);
- while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
- ;
- writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
-
- return 0;
-}
-
-/*!
- * This function assumes the expected core clock has to be changed by
- * modifying the PLL. This is NOT true always but for most of the times,
- * it is. So it assumes the PLL output freq is the same as the expected
- * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
- * In the latter case, it will try to increase the presc value until
- * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
- * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
- * on the targeted PLL and reference input clock to the PLL. Lastly,
- * it sets the register based on these values along with the dividers.
- * Note 1) There is no value checking for the passed-in divider values
- * so the caller has to make sure those values are sensible.
- * 2) Also adjust the NFC divider such that the NFC clock doesn't
- * exceed NFC_CLK_MAX.
- * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
- * 177MHz for higher voltage, this function fixes the max to 133MHz.
- * 4) This function should not have allowed diag_printf() calls since
- * the serial driver has been stoped. But leave then here to allow
- * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
- *
- * @param ref pll input reference clock (24MHz)
- * @param freq core clock in Hz
- * @param clk_type clock type, e.g CPU_CLK, DDR_CLK, etc.
- * @return 0 if successful; non-zero otherwise
- */
-int clk_config(u32 ref, u32 freq, u32 clk_type)
-{
- freq *= SZ_DEC_1M;
-
- switch (clk_type) {
- case CPU_CLK:
- if (config_core_clk(ref, freq))
- return -1;
- break;
- case PERIPH_CLK:
- if (config_periph_clk(ref, freq))
- return -1;
- break;
- case DDR_CLK:
- if (config_ddr_clk(freq))
- return -1;
- break;
- default:
- printf("Unsupported or invalid clock type! :(\n");
- }
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- printf("CPU: Freescale i.MX50 family %d.%dV at %d MHz\n",
- (get_board_rev() & 0xFF) >> 4,
- (get_board_rev() & 0xF),
- __get_mcu_main_clk() / 1000000);
-#ifndef CONFIG_CMD_CLOCK
- mxc_dump_clocks();
-#endif
- return 0;
-}
-#endif
-
-#if defined(CONFIG_MXC_FEC)
-extern int mxc_fec_initialize(bd_t *bis);
-extern void mxc_fec_set_mac_from_env(char *mac_addr);
-#endif
-
-int cpu_eth_init(bd_t *bis)
-{
- int rc = -ENODEV;
-#if defined(CONFIG_MXC_FEC)
- rc = mxc_fec_initialize(bis);
-#endif
- return rc;
-}
-
-#if defined(CONFIG_ARCH_CPU_INIT)
-int arch_cpu_init(void)
-{
- icache_enable();
- dcache_enable();
-
-#ifdef CONFIG_L2_OFF
- l2_cache_disable();
-#else
- l2_cache_enable();
-#endif
- return 0;
-}
-#endif
-
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mx50.h>
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int interrupt_init(void)
-{
- return 0;
-}
-
-void reset_cpu(ulong addr)
-{
- __REG16(WDOG1_BASE_ADDR) = 4;
-}
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mx50.h>
-#include <asm/arch/mx50_pins.h>
-#include <asm/arch/iomux.h>
-
-/*!
- * IOMUX register (base) addresses
- */
-enum iomux_reg_addr {
- IOMUXGPR0 = IOMUXC_BASE_ADDR,
- IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
- IOMUXGPR2 = IOMUXC_BASE_ADDR + 0x008,
- IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
- IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
- IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
- IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START,
-};
-
-static inline u32 _get_mux_reg(iomux_pin_name_t pin)
-{
- u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
- mux_reg += IOMUXSW_MUX_CTL;
-
- return mux_reg;
-}
-
-static inline u32 _get_pad_reg(iomux_pin_name_t pin)
-{
- u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
-
- pad_reg += IOMUXSW_PAD_CTL;
-
- return pad_reg;
-}
-
-static inline u32 _get_mux_end(void)
-{
- return IOMUXSW_MUX_END;
-}
-
-/*!
- * This function is used to configure a pin through the IOMUX module.
- * FIXED ME: for backward compatible. Will be static function!
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @param cfg an output function as defined in \b #iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- u32 mux_reg = _get_mux_reg(pin);
-
- if ((mux_reg > _get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
- return -1;
- if (cfg == IOMUX_CONFIG_GPIO)
- writel(PIN_TO_ALT_GPIO(pin), mux_reg);
- else
- writel(cfg, mux_reg);
-
- return 0;
-}
-
-/*!
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param cfg an input function as defined in \b #iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- int ret = iomux_config_mux(pin, cfg);
-
- return ret;
-}
-
-/*!
- * Release ownership for an IO pin
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param cfg an input function as defined in \b #iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*!
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @param config the ORed value of elements defined in \b #iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
- u32 pad_reg = _get_pad_reg(pin);
-
- writel(config, pad_reg);
-}
-
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
-{
- u32 pad_reg = _get_pad_reg(pin);
-
- return readl(pad_reg);
-}
-/*!
- * This function configures input path.
- *
- * @param input index of input select register as defined in \b
- * #iomux_input_select_t
- * @param config the binary value of elements defined in \b
- * #iomux_input_config_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
-{
- u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
-
- writel(config, reg);
-}
+++ /dev/null
-/*
- * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
- *
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-
-#if defined CONFIG_MX50_UART
-
-#include <asm/arch/mx50.h>
-
-#ifdef CONFIG_MX50_UART1
-#define UART_PHYS UART1_BASE_ADDR
-#elif defined(CONFIG_MX50_UART2)
-#define UART_PHYS UART2_BASE_ADDR
-#elif defined(CONFIG_MX50_UART3)
-#define UART_PHYS UART3_BASE_ADDR
-#else
-#error "define CFG_MX50_UARTx to use the mx50 UART driver"
-#endif
-
-/* Register definitions */
-#define URXD 0x0 /* Receiver Register */
-#define UTXD 0x40 /* Transmitter Register */
-#define UCR1 0x80 /* Control Register 1 */
-#define UCR2 0x84 /* Control Register 2 */
-#define UCR3 0x88 /* Control Register 3 */
-#define UCR4 0x8c /* Control Register 4 */
-#define UFCR 0x90 /* FIFO Control Register */
-#define USR1 0x94 /* Status Register 1 */
-#define USR2 0x98 /* Status Register 2 */
-#define UESC 0x9c /* Escape Character Register */
-#define UTIM 0xa0 /* Escape Timer Register */
-#define UBIR 0xa4 /* BRM Incremental Register */
-#define UBMR 0xa8 /* BRM Modulator Register */
-#define UBRC 0xac /* Baud Rate Count Register */
-#define UTS 0xb4 /* UART Test Register (mx31) */
-
-/* UART Control Register Bit Fields.*/
-#define URXD_CHARRDY (1<<15)
-#define URXD_ERR (1<<14)
-#define URXD_OVRRUN (1<<13)
-#define URXD_FRMERR (1<<12)
-#define URXD_BRK (1<<11)
-#define URXD_PRERR (1<<10)
-#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
-#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
-#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
-#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
-#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
-#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
-#define UCR1_IREN (1<<7) /* Infrared interface enable */
-#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
-#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
-#define UCR1_SNDBRK (1<<4) /* Send break */
-#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
-#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
-#define UCR1_DOZE (1<<1) /* Doze */
-#define UCR1_UARTEN (1<<0) /* UART enabled */
-#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
-#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
-#define UCR2_CTSC (1<<13) /* CTS pin control */
-#define UCR2_CTS (1<<12) /* Clear to send */
-#define UCR2_ESCEN (1<<11) /* Escape enable */
-#define UCR2_PREN (1<<8) /* Parity enable */
-#define UCR2_PROE (1<<7) /* Parity odd/even */
-#define UCR2_STPB (1<<6) /* Stop */
-#define UCR2_WS (1<<5) /* Word size */
-#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
-#define UCR2_TXEN (1<<2) /* Transmitter enabled */
-#define UCR2_RXEN (1<<1) /* Receiver enabled */
-#define UCR2_SRST (1<<0) /* SW reset */
-#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
-#define UCR3_PARERREN (1<<12) /* Parity enable */
-#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
-#define UCR3_DSR (1<<10) /* Data set ready */
-#define UCR3_DCD (1<<9) /* Data carrier detect */
-#define UCR3_RI (1<<8) /* Ring indicator */
-#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
-#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
-#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
-#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
-#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
-#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
-#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
-#define UCR3_BPEN (1<<0) /* Preset registers enable */
-#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
-#define UCR4_INVR (1<<9) /* Inverted infrared reception */
-#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
-#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
-#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
-#define UCR4_IRSC (1<<5) /* IR special case */
-#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
-#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
-#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
-#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
-#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
-#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
-#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
-#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
-#define USR1_RTSS (1<<14) /* RTS pin status */
-#define USR1_TRDY (1<<13)/* Transmitter ready interrupt/dma flag */
-#define USR1_RTSD (1<<12) /* RTS delta */
-#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
-#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
-#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
-#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
-#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
-#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
-#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
-#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
-#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
-#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
-#define USR2_IDLE (1<<12) /* Idle condition */
-#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
-#define USR2_WAKE (1<<7) /* Wake */
-#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
-#define USR2_TXDC (1<<3) /* Transmitter complete */
-#define USR2_BRCD (1<<2) /* Break condition */
-#define USR2_ORE (1<<1) /* Overrun error */
-#define USR2_RDR (1<<0) /* Recv data ready */
-#define UTS_FRCPERR (1<<13) /* Force parity error */
-#define UTS_LOOP (1<<12) /* Loop tx and rx */
-#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
-#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
-#define UTS_TXFULL (1<<4) /* TxFIFO full */
-#define UTS_RXFULL (1<<3) /* RxFIFO full */
-#define UTS_SOFTRST (1<<0) /* Software reset */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void serial_setbrg(void)
-{
- u32 clk = mxc_get_clock(MXC_UART_CLK);
-
- if (!gd->baudrate)
- gd->baudrate = CONFIG_BAUDRATE;
- __REG(UART_PHYS + UFCR) = 0x4 << 7; /* divide input clock by 2 */
- __REG(UART_PHYS + UBIR) = 0xf;
- __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
-}
-
-int serial_getc(void)
-{
- while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
- ;
- return __REG(UART_PHYS + URXD);
-}
-
-void serial_putc(const char c)
-{
- __REG(UART_PHYS + UTXD) = c;
-
- /* wait for transmitter to be ready */
- while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
- ;
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-int serial_tstc(void)
-{
- /* If receive fifo is empty, return false */
- if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
- return 0;
- return 1;
-}
-
-void serial_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init(void)
-{
- __REG(UART_PHYS + UCR1) = 0x0;
- __REG(UART_PHYS + UCR2) = 0x0;
-
- while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST))
- ;
-
- __REG(UART_PHYS + UCR3) = 0x0704;
- __REG(UART_PHYS + UCR4) = 0x8000;
- __REG(UART_PHYS + UESC) = 0x002b;
- __REG(UART_PHYS + UTIM) = 0x0;
-
- __REG(UART_PHYS + UTS) = 0x0;
-
- serial_setbrg();
-
- __REG(UART_PHYS + UCR2) =
- UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
-
- __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
-
- return 0;
-}
-
-#endif /* CONFIG_MX50_UART */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mx50.h>
-
-/* General purpose timers registers */
-#define GPTCR __REG(GPT1_BASE_ADDR) /* Control register */
-#define GPTPR __REG(GPT1_BASE_ADDR + 0x4) /* Prescaler register */
-#define GPTSR __REG(GPT1_BASE_ADDR + 0x8) /* Status register */
-#define GPTCNT __REG(GPT1_BASE_ADDR + 0x24) /* Counter register */
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR (1<<15) /* Software reset */
-#define GPTCR_FRR (1<<9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */
-#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */
-#define GPTCR_TEN (1) /* Timer enable */
-#define GPTPR_VAL (50)
-
-static inline void setup_gpt(void)
-{
- int i;
- static int init_done;
-
- if (init_done)
- return;
-
- init_done = 1;
-
- /* setup GP Timer 1 */
- GPTCR = GPTCR_SWR;
- for (i = 0; i < 100; i++)
- GPTCR = 0; /* We have no udelay by now */
- GPTPR = GPTPR_VAL; /* 50Mhz / 50 */
- /* Freerun Mode, PERCLK1 input */
- GPTCR |= GPTCR_CLKSOURCE_IPG | GPTCR_TEN;
-}
-
-int timer_init(void)
-{
- setup_gpt();
-
- return 0;
-}
-
-void reset_timer_masked(void)
-{
- GPTCR = 0;
- /* Freerun Mode, PERCLK1 input */
- GPTCR = GPTCR_CLKSOURCE_IPG | GPTCR_TEN;
-}
-
-inline ulong get_timer_masked(void)
-{
- ulong val = GPTCNT;
-
- return val;
-}
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
- ulong tmp;
-
- tmp = get_timer_masked();
-
- if (tmp <= (base * 1000)) {
- /* Overflow */
- tmp += (0xffffffff - base);
- }
-
- return (tmp / 1000) - base;
-}
-
-void set_timer(ulong t)
-{
-}
-
-/* delay x useconds AND perserve advance timstamp value */
-/* GPTCNT is now supposed to tick 1 by 1 us. */
-void udelay(unsigned long usec)
-{
- ulong tmp;
-
- setup_gpt();
-
- tmp = get_timer_masked(); /* get current timestamp */
-
- /* if setting this forward will roll time stamp */
- if ((usec + tmp + 1) < tmp) {
- /* reset "advancing" timestamp to 0, set lastinc value */
- reset_timer_masked();
- } else {
- /* else, set advancing stamp wake up time */
- tmp += usec;
- }
-
- while (get_timer_masked() < tmp) /* loop till event */
- /*NOP*/;
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2009 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(SOC).a
-
-COBJS = interrupts.o serial.o generic.o iomux.o timer.o cache.o
-COBJS-$(CONFIG_CMD_FUSE) += cmd_fuse.o
-COBJS-$(CONFIG_IMX_FUSE) += imx_fuse.o
-COBJS += $(COBJS-y)
-SOBJS = mxc_nand_load.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all: $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/cache.h>
-
-void l2_cache_enable(void)
-{
- asm("mrc 15, 0, r0, c1, c0, 1");
- asm("orr r0, r0, #0x2");
- asm("mcr 15, 0, r0, c1, c0, 1");
-}
-
-void l2_cache_disable(void)
-{
- asm("mrc 15, 0, r0, c1, c0, 1");
- asm("bic r0, r0, #0x2");
- asm("mcr 15, 0, r0, c1, c0, 1");
-}
-
-/*dummy function for L2 ON*/
-u32 get_device_type(void)
-{
- return 0;
-}
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-
-#define MXC_CCM_BASE CCM_BASE_ADDR
-#define MXC_DPLL1_BASE PLL1_BASE_ADDR
-#define MXC_DPLL2_BASE PLL2_BASE_ADDR
-#define MXC_DPLL3_BASE PLL3_BASE_ADDR
-
-/* PLL Register Offsets */
-#define MXC_PLL_DP_CTL 0x00
-#define MXC_PLL_DP_CONFIG 0x04
-#define MXC_PLL_DP_OP 0x08
-#define MXC_PLL_DP_MFD 0x0C
-#define MXC_PLL_DP_MFN 0x10
-#define MXC_PLL_DP_MFNMINUS 0x14
-#define MXC_PLL_DP_MFNPLUS 0x18
-#define MXC_PLL_DP_HFS_OP 0x1C
-#define MXC_PLL_DP_HFS_MFD 0x20
-#define MXC_PLL_DP_HFS_MFN 0x24
-#define MXC_PLL_DP_MFN_TOGC 0x28
-#define MXC_PLL_DP_DESTAT 0x2c
-
-/* PLL Register Bit definitions */
-#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
-#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
-#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
-#define MXC_PLL_DP_CTL_ADE 0x800
-#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
-#define MXC_PLL_DP_CTL_HFSM 0x80
-#define MXC_PLL_DP_CTL_PRE 0x40
-#define MXC_PLL_DP_CTL_UPEN 0x20
-#define MXC_PLL_DP_CTL_RST 0x10
-#define MXC_PLL_DP_CTL_RCP 0x8
-#define MXC_PLL_DP_CTL_PLM 0x4
-#define MXC_PLL_DP_CTL_BRM0 0x2
-#define MXC_PLL_DP_CTL_LRF 0x1
-
-#define MXC_PLL_DP_CONFIG_BIST 0x8
-#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
-#define MXC_PLL_DP_CONFIG_AREN 0x2
-#define MXC_PLL_DP_CONFIG_LDREQ 0x1
-
-#define MXC_PLL_DP_OP_MFI_OFFSET 4
-#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
-#define MXC_PLL_DP_OP_PDF_OFFSET 0
-#define MXC_PLL_DP_OP_PDF_MASK 0xF
-
-#define MXC_PLL_DP_MFD_OFFSET 0
-#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_OFFSET 0x0
-#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
-#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
-#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
-#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
-
-#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
-#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
-
-/* Register addresses of CCM*/
-#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00)
-#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04)
-#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08)
-#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C)
-#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10)
-#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14)
-#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18)
-#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C)
-#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20)
-#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24)
-#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28)
-#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C)
-#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30)
-#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34)
-#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38)
-#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C)
-#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40)
-#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44)
-#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48)
-#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C)
-#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50)
-#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54)
-#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58)
-#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C)
-#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60)
-#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64)
-#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68)
-#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C)
-#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70)
-#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74)
-#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78)
-#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C)
-#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80)
-#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x84)
-
-/* Define the bits in register CCR */
-#define MXC_CCM_CCR_COSC_EN (1 << 12)
-#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
-#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
-#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
-#define MXC_CCM_CCR_FPM_EN (1 << 8)
-#define MXC_CCM_CCR_OSCNT_OFFSET (0)
-#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
-
-/* Define the bits in register CCDR */
-#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
-#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
-#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
-
-/* Define the bits in register CSR */
-#define MXC_CCM_CSR_COSR_READY (1 << 5)
-#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
-#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
-#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
-#define MXC_CCM_CSR_FPM_READY (1 << 1)
-#define MXC_CCM_CSR_REF_EN_B (1 << 0)
-
-/* Define the bits in register CCSR */
-#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
-#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
-#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
-#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
-#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
-#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
-#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
-#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
-#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
-#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
-
-/* Define the bits in register CACRR */
-#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
-#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
-
-/* Define the bits in register CBCDR */
-#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
-#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
-#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
-#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
-#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
-#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
-#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
-#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
-#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
-#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
-#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
-#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
-#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
-#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
-#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
-
-/* Define the bits in register CBCMR */
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
-#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
-#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
-
-/* Define the bits in register CSCMR1 */
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
-#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
-#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
-#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
-#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
-#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
-#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
-
-/* Define the bits in register CSCMR2 */
-#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET (26)
-#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK (0x7 << 26)
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
-#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
-#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
-#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
-#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
-#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
-#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
-#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
-#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
-#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
-#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
-#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
-#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
-#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
-#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
-#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
-#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
-#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
-#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
-#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
-#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
-#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
-
-/* Define the bits in register CSCDR1 */
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
-
-/* Define the bits in register CS1CDR and CS2CDR */
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
-
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
-
-/* Define the bits in register CDCDR */
-#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
-#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
-#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
-#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
-#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
-#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
-
-/* Define the bits in register CHSCCDR */
-#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
-#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
-#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
-#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
-
-/* Define the bits in register CSCDR2 */
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
-#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
-#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
-#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
-
-/* Define the bits in register CSCDR3 */
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
-
-/* Define the bits in register CSCDR4 */
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
-
-/* Define the bits in register CDHIPR */
-#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
-#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
-#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
-#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
-#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
-#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
-#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
-#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
-
-/* Define the bits in register CDCR */
-#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
-
-/* Define the bits in register CLPCR */
-#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
-#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
-#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
-#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
-#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
-#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
-#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
-#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
-#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
-#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
-#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
-#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
-#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
-#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
-#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
-#define MXC_CCM_CLPCR_LPM_OFFSET (0)
-#define MXC_CCM_CLPCR_LPM_MASK (0x3)
-
-/* Define the bits in register CISR */
-#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
-#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
-#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
-#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
-#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
-#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
-#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
-#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
-#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
-#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
-#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
-#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
-#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
-#define MXC_CCM_CISR_LRF_PLL1 (0x1)
-
-/* Define the bits in register CIMR */
-#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
-#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
-#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
-#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
-#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
-#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
-#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
-#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
-#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
-#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
-#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
-#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
-#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
-
-/* Define the bits in register CCOSR */
-#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
-#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
-#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
-#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
-#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
-#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
-#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
-#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
-#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
-#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
-
-/* Define the bits in registers CGPR */
-#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
-#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
-#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
-#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
-
-/* Define the bits in registers CCGRx */
-#define MXC_CCM_CCGR_CG_MASK 0x3
-
-#define MXC_CCM_CCGR0_CG15_OFFSET 30
-#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
-#define MXC_CCM_CCGR0_CG14_OFFSET 28
-#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR0_CG13_OFFSET 26
-#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR0_CG12_OFFSET 24
-#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR0_CG11_OFFSET 22
-#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR0_CG10_OFFSET 20
-#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR0_CG9_OFFSET 18
-#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR0_CG8_OFFSET 16
-#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR0_CG7_OFFSET 14
-#define MXC_CCM_CCGR0_CG6_OFFSET 12
-#define MXC_CCM_CCGR0_CG5_OFFSET 10
-#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
-#define MXC_CCM_CCGR0_CG4_OFFSET 8
-#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
-#define MXC_CCM_CCGR0_CG3_OFFSET 6
-#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
-#define MXC_CCM_CCGR0_CG2_OFFSET 4
-#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR0_CG1_OFFSET 2
-#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
-#define MXC_CCM_CCGR0_CG0_OFFSET 0
-#define MXC_CCM_CCGR0_CG0_MASK 0x3
-
-#define MXC_CCM_CCGR1_CG15_OFFSET 30
-#define MXC_CCM_CCGR1_CG14_OFFSET 28
-#define MXC_CCM_CCGR1_CG13_OFFSET 26
-#define MXC_CCM_CCGR1_CG12_OFFSET 24
-#define MXC_CCM_CCGR1_CG11_OFFSET 22
-#define MXC_CCM_CCGR1_CG10_OFFSET 20
-#define MXC_CCM_CCGR1_CG9_OFFSET 18
-#define MXC_CCM_CCGR1_CG8_OFFSET 16
-#define MXC_CCM_CCGR1_CG7_OFFSET 14
-#define MXC_CCM_CCGR1_CG6_OFFSET 12
-#define MXC_CCM_CCGR1_CG5_OFFSET 10
-#define MXC_CCM_CCGR1_CG4_OFFSET 8
-#define MXC_CCM_CCGR1_CG3_OFFSET 6
-#define MXC_CCM_CCGR1_CG2_OFFSET 4
-#define MXC_CCM_CCGR1_CG1_OFFSET 2
-#define MXC_CCM_CCGR1_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR2_CG15_OFFSET 30
-#define MXC_CCM_CCGR2_CG14_OFFSET 28
-#define MXC_CCM_CCGR2_CG13_OFFSET 26
-#define MXC_CCM_CCGR2_CG12_OFFSET 24
-#define MXC_CCM_CCGR2_CG11_OFFSET 22
-#define MXC_CCM_CCGR2_CG10_OFFSET 20
-#define MXC_CCM_CCGR2_CG9_OFFSET 18
-#define MXC_CCM_CCGR2_CG8_OFFSET 16
-#define MXC_CCM_CCGR2_CG7_OFFSET 14
-#define MXC_CCM_CCGR2_CG6_OFFSET 12
-#define MXC_CCM_CCGR2_CG5_OFFSET 10
-#define MXC_CCM_CCGR2_CG4_OFFSET 8
-#define MXC_CCM_CCGR2_CG3_OFFSET 6
-#define MXC_CCM_CCGR2_CG2_OFFSET 4
-#define MXC_CCM_CCGR2_CG1_OFFSET 2
-#define MXC_CCM_CCGR2_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR3_CG15_OFFSET 30
-#define MXC_CCM_CCGR3_CG14_OFFSET 28
-#define MXC_CCM_CCGR3_CG13_OFFSET 26
-#define MXC_CCM_CCGR3_CG12_OFFSET 24
-#define MXC_CCM_CCGR3_CG11_OFFSET 22
-#define MXC_CCM_CCGR3_CG10_OFFSET 20
-#define MXC_CCM_CCGR3_CG9_OFFSET 18
-#define MXC_CCM_CCGR3_CG8_OFFSET 16
-#define MXC_CCM_CCGR3_CG7_OFFSET 14
-#define MXC_CCM_CCGR3_CG6_OFFSET 12
-#define MXC_CCM_CCGR3_CG5_OFFSET 10
-#define MXC_CCM_CCGR3_CG4_OFFSET 8
-#define MXC_CCM_CCGR3_CG3_OFFSET 6
-#define MXC_CCM_CCGR3_CG2_OFFSET 4
-#define MXC_CCM_CCGR3_CG1_OFFSET 2
-#define MXC_CCM_CCGR3_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR4_CG15_OFFSET 30
-#define MXC_CCM_CCGR4_CG14_OFFSET 28
-#define MXC_CCM_CCGR4_CG13_OFFSET 26
-#define MXC_CCM_CCGR4_CG12_OFFSET 24
-#define MXC_CCM_CCGR4_CG11_OFFSET 22
-#define MXC_CCM_CCGR4_CG10_OFFSET 20
-#define MXC_CCM_CCGR4_CG9_OFFSET 18
-#define MXC_CCM_CCGR4_CG8_OFFSET 16
-#define MXC_CCM_CCGR4_CG7_OFFSET 14
-#define MXC_CCM_CCGR4_CG6_OFFSET 12
-#define MXC_CCM_CCGR4_CG5_OFFSET 10
-#define MXC_CCM_CCGR4_CG4_OFFSET 8
-#define MXC_CCM_CCGR4_CG3_OFFSET 6
-#define MXC_CCM_CCGR4_CG2_OFFSET 4
-#define MXC_CCM_CCGR4_CG1_OFFSET 2
-#define MXC_CCM_CCGR4_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR5_CG15_OFFSET 30
-#define MXC_CCM_CCGR5_CG14_OFFSET 28
-#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR5_CG13_OFFSET 26
-#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR5_CG12_OFFSET 24
-#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR5_CG11_OFFSET 22
-#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR5_CG10_OFFSET 20
-#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR5_CG9_OFFSET 18
-#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR5_CG8_OFFSET 16
-#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR5_CG7_OFFSET 14
-#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
-#define MXC_CCM_CCGR5_CG6_OFFSET 12
-#define MXC_CCM_CCGR5_CG5_OFFSET 10
-#define MXC_CCM_CCGR5_CG4_OFFSET 8
-#define MXC_CCM_CCGR5_CG3_OFFSET 6
-#define MXC_CCM_CCGR5_CG2_OFFSET 4
-#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR5_CG1_OFFSET 2
-#define MXC_CCM_CCGR5_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR6_CG4_OFFSET 8
-#define MXC_CCM_CCGR6_CG4_MASK (0x3 << 8)
-#define MXC_CCM_CCGR6_CG3_OFFSET 6
-#define MXC_CCM_CCGR6_CG2_OFFSET 4
-#define MXC_CCM_CCGR6_CG1_OFFSET 2
-#define MXC_CCM_CCGR6_CG0_OFFSET 0
-
-#define MXC_CORTEXA8_BASE ARM_BASE_ADDR
-#define MXC_GPC_BASE GPC_BASE_ADDR
-#define MXC_DPTC_LP_BASE (GPC_BASE_ADDR + 0x80)
-#define MXC_DPTC_GP_BASE (GPC_BASE_ADDR + 0x100)
-#define MXC_DVFS_CORE_BASE (GPC_BASE_ADDR + 0x180)
-#define MXC_DPTC_PER_BASE (GPC_BASE_ADDR + 0x1C0)
-#define MXC_PGC_IPU_BASE (GPC_BASE_ADDR + 0x220)
-#define MXC_PGC_VPU_BASE (GPC_BASE_ADDR + 0x240)
-#define MXC_PGC_GPU_BASE (GPC_BASE_ADDR + 0x260)
-#define MXC_SRPG_NEON_BASE (GPC_BASE_ADDR + 0x280)
-#define MXC_SRPG_ARM_BASE (GPC_BASE_ADDR + 0x2A0)
-#define MXC_SRPG_EMPGC0_BASE (GPC_BASE_ADDR + 0x2C0)
-#define MXC_SRPG_EMPGC1_BASE (GPC_BASE_ADDR + 0x2D0)
-#define MXC_SRPG_MEGAMIX_BASE (GPC_BASE_ADDR + 0x2E0)
-#define MXC_SRPG_EMI_BASE (GPC_BASE_ADDR + 0x300)
-
-/* CORTEXA8 platform */
-#define MXC_CORTEXA8_PLAT_PVID (MXC_CORTEXA8_BASE + 0x0)
-#define MXC_CORTEXA8_PLAT_GPC (MXC_CORTEXA8_BASE + 0x4)
-#define MXC_CORTEXA8_PLAT_PIC (MXC_CORTEXA8_BASE + 0x8)
-#define MXC_CORTEXA8_PLAT_LPC (MXC_CORTEXA8_BASE + 0xC)
-#define MXC_CORTEXA8_PLAT_NEON_LPC (MXC_CORTEXA8_BASE + 0x10)
-#define MXC_CORTEXA8_PLAT_ICGC (MXC_CORTEXA8_BASE + 0x14)
-#define MXC_CORTEXA8_PLAT_AMC (MXC_CORTEXA8_BASE + 0x18)
-#define MXC_CORTEXA8_PLAT_NMC (MXC_CORTEXA8_BASE + 0x20)
-#define MXC_CORTEXA8_PLAT_NMS (MXC_CORTEXA8_BASE + 0x24)
-
-/* DVFS CORE */
-#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
-#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
-#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
-#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
-#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
-#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
-#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
-#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
-#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
-#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
-#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
-#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
-#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
-#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
-#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
-#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
-#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
-
-/* GPC */
-#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0)
-#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4)
-#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8)
-#define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC)
-#define MXC_GPC_NEON (MXC_GPC_BASE + 0x10)
-#define MXC_GPC_PGR_ARMPG_OFFSET 8
-#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
-
-/* PGC */
-#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
-#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
-#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
-#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
-#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
-#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
-
-#define MXC_PGCR_PCR 1
-#define MXC_SRPGCR_PCR 1
-#define MXC_EMPGCR_PCR 1
-#define MXC_PGSR_PSR 1
-
-
-#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
-#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
-
-/* SRPG */
-#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
-#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
-#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
-
-#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
-#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
-#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
-
-#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
-#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
-#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
-
-#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
-#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
-#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
-
-#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
-#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
-#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
-
-#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
-#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
-#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
-
-#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mx51.h>
-#include <asm/errno.h>
-#ifdef CONFIG_ARCH_CPU_INIT
-#include <asm/cache-cp15.h>
-#endif
-#include "crm_regs.h"
-
-enum pll_clocks {
-PLL1_CLK = MXC_DPLL1_BASE,
-PLL2_CLK = MXC_DPLL2_BASE,
-PLL3_CLK = MXC_DPLL3_BASE,
-};
-
-enum pll_sw_clocks {
-PLL1_SW_CLK,
-PLL2_SW_CLK,
-PLL3_SW_CLK,
-};
-
-static u32 __decode_pll(enum pll_clocks pll, u32 infreq)
-{
- u32 mfi, mfn, mfd, pd;
-
- mfn = __REG(pll + MXC_PLL_DP_MFN);
- mfd = __REG(pll + MXC_PLL_DP_MFD) + 1;
- mfi = __REG(pll + MXC_PLL_DP_OP);
- pd = (mfi & 0xF) + 1;
- mfi = (mfi >> 4) & 0xF;
- mfi = (mfi >= 5) ? mfi : 5;
-
- return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
-}
-
-static u32 __get_mcu_main_clk(void)
-{
- u32 reg, freq;
- reg = (__REG(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
- MXC_CCM_CACRR_ARM_PODF_OFFSET;
- freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
- return freq / (reg + 1);
-}
-
-static u32 __get_periph_clk(void)
-{
- u32 reg;
- reg = __REG(MXC_CCM_CBCDR);
- if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
- reg = __REG(MXC_CCM_CBCMR);
- switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
- MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
- case 0:
- return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
- case 1:
- return __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
- default:
- return 0;
- }
- }
- return __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
-}
-
-static u32 __get_ipg_clk(void)
-{
- u32 ahb_podf, ipg_podf;
-
- ahb_podf = __REG(MXC_CCM_CBCDR);
- ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
- MXC_CCM_CBCDR_IPG_PODF_OFFSET;
- ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
- MXC_CCM_CBCDR_AHB_PODF_OFFSET;
- return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
-}
-
-static u32 __get_ipg_per_clk(void)
-{
- u32 pred1, pred2, podf;
- if (__REG(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
- return __get_ipg_clk();
- /* Fixme: not handle what about lpm*/
- podf = __REG(MXC_CCM_CBCDR);
- pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
- pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
- podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
-
- return __get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
-}
-
-static u32 __get_uart_clk(void)
-{
- unsigned int freq, reg, pred, podf;
- reg = __REG(MXC_CCM_CSCMR1);
- switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
- MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
- case 0x0:
- freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
- break;
- case 0x1:
- freq = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
- break;
- case 0x2:
- freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
- break;
- default:
- return 66500000;
- }
-
- reg = __REG(MXC_CCM_CSCDR1);
-
- pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
- MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
-
- podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
- MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
- freq /= (pred + 1) * (podf + 1);
-
- return freq;
-}
-
-/*!
-+ * This function returns the low power audio clock.
-+ */
-u32 get_lp_apm(void)
-{
- u32 ret_val = 0;
- u32 ccsr = __REG(MXC_CCM_CCSR);
-
- if (((ccsr >> 9) & 1) == 0)
- ret_val = CONFIG_MX51_HCLK_FREQ;
- else
- ret_val = ((32768 * 1024));
-
- return ret_val;
-}
-
-static u32 __get_cspi_clk(void)
-{
- u32 ret_val = 0, pdf, pre_pdf, clk_sel;
- u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
- u32 cscdr2 = __REG(MXC_CCM_CSCDR2);
-
- pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
- >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
- pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
- >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
- clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
- >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
-
- switch (clk_sel) {
- case 0:
- ret_val = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1));
- break;
- case 1:
- ret_val = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1));
- break;
- case 2:
- ret_val = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1));
- break;
- default:
- ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
- break;
- }
-
- return ret_val;
-}
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
- switch (clk) {
- case MXC_ARM_CLK:
- return __get_mcu_main_clk();
- case MXC_AHB_CLK:
- break;
- case MXC_IPG_CLK:
- return __get_ipg_clk();
- case MXC_IPG_PERCLK:
- return __get_ipg_per_clk();
- case MXC_UART_CLK:
- return __get_uart_clk();
- case MXC_CSPI_CLK:
- return __get_cspi_clk();
- case MXC_FEC_CLK:
- return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
- case MXC_ESDHC_CLK:
- return __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
- default:
- break;
- }
- return -1;
-}
-
-void mxc_dump_clocks(void)
-{
- u32 freq;
- freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
- printf("mx51 pll1: %dMHz\n", freq / 1000000);
- freq = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
- printf("mx51 pll2: %dMHz\n", freq / 1000000);
- freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
- printf("mx51 pll3: %dMHz\n", freq / 1000000);
- printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
- printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
- printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
- printf("cspi clock : %dHz\n", mxc_get_clock(MXC_CSPI_CLK));
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- printf("CPU: Freescale i.MX51 family %d.%dV at %d MHz\n",
- (get_board_rev() & 0xFF) >> 4,
- (get_board_rev() & 0xF),
- __get_mcu_main_clk() / 1000000);
- mxc_dump_clocks();
- return 0;
-}
-#endif
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-#if defined(CONFIG_MXC_FEC)
-extern int mxc_fec_initialize(bd_t *bis);
-extern void mxc_fec_set_mac_from_env(char *mac_addr);
-#endif
-
-int cpu_eth_init(bd_t *bis)
-{
- int rc = -ENODEV;
-
-#if defined(CONFIG_MXC_FEC)
- rc = mxc_fec_initialize(bis);
-#endif
-
- return rc;
-}
-
-#if defined(CONFIG_ARCH_CPU_INIT)
-int arch_cpu_init(void)
-{
- icache_enable();
- dcache_enable();
-#ifdef CONFIG_L2_OFF
- l2_cache_disable();
-#else
- l2_cache_enable();
-#endif
- return 0;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mx51.h>
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int interrupt_init(void)
-{
- return 0;
-}
-
-void reset_cpu(ulong addr)
-{
- /* workaround for ENGcm09397 - Fix SPI NOR reset issue*/
- /* de-select SS0 of instance: eCSPI1 */
- writel(0x3, IOMUXC_BASE_ADDR + 0x218);
- writel(0x85, IOMUXC_BASE_ADDR + 0x608);
- /* de-select SS1 of instance: ecspi1 */
- writel(0x3, IOMUXC_BASE_ADDR + 0x21C);
- writel(0x85, IOMUXC_BASE_ADDR + 0x60C);
-
- __REG16(WDOG1_BASE_ADDR) = 4;
-}
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/*!
- * @defgroup GPIO_MX51 Board GPIO and Muxing Setup
- * @ingroup MSL_MX51
- */
-/*!
- * @file mach-mx51/iomux.c
- *
- * @brief I/O Muxing control functions
- *
- * @ingroup GPIO_MX51
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mx51.h>
-#include <asm/arch/mx51_pins.h>
-#include <asm/arch/iomux.h>
-
-/*!
- * IOMUX register (base) addresses
- */
-enum iomux_reg_addr {
- IOMUXGPR0 = IOMUXC_BASE_ADDR,
- IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
- IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
- IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
- IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
- IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR,
-};
-
-#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
-
-static inline u32 _get_mux_reg(iomux_pin_name_t pin)
-{
- u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
- if (is_soc_rev(CHIP_REV_2_0) < 0) {
- if ((pin == MX51_PIN_NANDF_RB5) ||
- (pin == MX51_PIN_NANDF_RB6) ||
- (pin == MX51_PIN_NANDF_RB7))
- ; /* Do nothing */
- else if (mux_reg >= 0x2FC)
- mux_reg += 8;
- else if (mux_reg >= 0x130)
- mux_reg += 0xC;
- }
- mux_reg += IOMUXSW_MUX_CTL;
- return mux_reg;
-}
-
-static inline u32 _get_pad_reg(iomux_pin_name_t pin)
-{
- u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
-
- if (is_soc_rev(CHIP_REV_2_0) < 0) {
- if ((pin == MX51_PIN_NANDF_RB5) ||
- (pin == MX51_PIN_NANDF_RB6) ||
- (pin == MX51_PIN_NANDF_RB7))
- ; /* Do nothing */
- else if (pad_reg == 0x4D0 - PAD_I_START)
- pad_reg += 0x4C;
- else if (pad_reg == 0x860 - PAD_I_START)
- pad_reg += 0x9C;
- else if (pad_reg >= 0x804 - PAD_I_START)
- pad_reg += 0xB0;
- else if (pad_reg >= 0x7FC - PAD_I_START)
- pad_reg += 0xB4;
- else if (pad_reg >= 0x4E4 - PAD_I_START)
- pad_reg += 0xCC;
- else
- pad_reg += 8;
- }
- pad_reg += IOMUXSW_PAD_CTL;
- return pad_reg;
-}
-
-static inline u32 _get_mux_end()
-{
- if (is_soc_rev(CHIP_REV_2_0) < 0)
- return IOMUXC_BASE_ADDR + (0x3F8 - 4);
- else
- return IOMUXC_BASE_ADDR + (0x3F0 - 4);
-}
-
-/*!
- * This function is used to configure a pin through the IOMUX module.
- * FIXED ME: for backward compatible. Will be static function!
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @param cfg an output function as defined in \b #iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- u32 mux_reg = _get_mux_reg(pin);
-
- if ((mux_reg > _get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
- return -1;
- if (cfg == IOMUX_CONFIG_GPIO)
- writel(PIN_TO_ALT_GPIO(pin), mux_reg);
- else
- writel(cfg, mux_reg);
-
- return 0;
-}
-
-/*!
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param cfg an input function as defined in \b #iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- int ret = iomux_config_mux(pin, cfg);
- return ret;
-}
-
-/*!
- * Release ownership for an IO pin
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param cfg an input function as defined in \b #iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*!
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @param config the ORed value of elements defined in \b #iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
- u32 pad_reg = _get_pad_reg(pin);
- writel(config, pad_reg);
-}
-
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
-{
- u32 pad_reg = _get_pad_reg(pin);
- return readl(pad_reg);
-}
-/*!
- * This function configures input path.
- *
- * @param input index of input select register as defined in \b
- * #iomux_input_select_t
- * @param config the binary value of elements defined in \b
- * #iomux_input_config_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
-{
- u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
-
- if (is_soc_rev(CHIP_REV_2_0) < 0) {
- if (input == MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT)
- input -= 4;
- else if (input ==
- MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT)
- input -= 3;
- else if (input >= MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT)
- input -= 2;
- else if (input >=
- MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT)
- input -= 5;
- else if (input >=
- MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT)
- input -= 3;
- else if (input >= MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT)
- input -= 2;
- else if (input >= MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT)
- input -= 1;
-
- reg += INPUT_CTL_START_TO1;
- } else {
- reg += INPUT_CTL_START;
- }
-
- writel(config, reg);
-}
+++ /dev/null
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx51.h>
-.macro do_wait_op_done
-1: ldr r7, [r3, #0x2C]
- ands r7, r7, #0x80000000
- beq 1b
- mov r7, #0x0
- str r7, [r3, #0x2C]
-.endm // do_wait_op_done
-
-.section ".text.load", "x"
-.globl mxc_nand_load
-/*
- * R0: NFC BUF base address
- * R1: NFC BUF data end address
- * R2: RAM destination offset address
- * R3: NFC IP control register base
- * R4: NAND block address
- * R5: RAM destination end address
- * R6: NFC DATA register base
- * R7 - r14: 8 working buffer registers
- */
-mxc_nand_load:
- ldr r0, =NFC_BASE_ADDR_AXI
- add r1, r0, #NFC_BUF_SIZE
-
- /* For non-nand-boot, directly quit */
- cmp pc, r0
- movlo pc, lr
- cmp pc, r1
- movhi pc, lr
-
- mov r4, #NFC_BUF_SIZE
- /* Get NAND page size */
- ldr r3, =NFC_BASE_ADDR
- ldr r2, [r3, #0x24]
- and r2, r2, #0x3
- cmp r2, #1
- moveq r2, #0x800
- movlt r2, #0x200
- adrls r5, NFC_PAGE_MODE
- strls r2, [r5]
- /* Get actually pre-loading size*/
- subls r1, r1, #0x800
- subls r4, r4, #0x800
-
- /* r1 ~ r3, r12, lr(r14) must not change in relocated operation */
- ldr r2, U_BOOT_NAND_START
-1: ldmia r0!, {r5-r11, r13}
- stmia r2!, {r5-r11, r13}
- cmp r0, r1
- blo 1b
-
- ldr r0, CONST_0X0FFF
- ldr r5, U_BOOT_NAND_START
- and lr, lr, r0
- add lr, lr, r5
- and r12, r12, r0
- add r12, r12, r5
- add r5, r5, #0x8
- and r0, pc, r0
- add pc, r5, r0
- nop
- nop
- nop
- nop
- nop
- adr r0, SAVE_REGS /* Save r12 & R14(lr) */
- str r12, [r0]
- str lr, [r0, #4]
-Copy_Main:
- ldr r0, =NFC_BASE_ADDR_AXI
-
- add r6, r0, #0x1E00
- ldr r5, =_end /* Try get right image size */
- add r5, r2, #0x00040000 /* Fixme to get actual image size */
-
- mov r7, #0xFF000000
- add r7, r7, #0x00FF0000
- str r7, [r3, #0x4]
- str r7, [r3, #0x8]
- str r7, [r3, #0xC]
- str r7, [r3, #0x10]
- str r7, [r3, #0x14]
- str r7, [r3, #0x18]
- str r7, [r3, #0x1C]
- str r7, [r3, #0x20]
- mov r8, #0x7
- mov r7, #0x84
-1: add r9, r7, r8, lsr #3
- str r9, [r3, #0x0]
- subs r8, r8, #0x01
- bne 1b
-
- mov r7, #0
- str r7, [r3, #0x2C]
-
- ldr r7, NFC_PAGE_MODE
-Read_Page:
- /* start_nfc_addr_ops1(pg_no, pg_off) */
- cmp r7, #0x800
- movgt r7, r4, lsr #12 /* Get the page number for 4K page */
- moveq r7, r4, lsr #11 /* Get the page number for 2K page */
- mov r7, r7, lsl #16
- str r7, [r6, #0x04] /* Set the address */
-
- /* writel((FLASH_Read_Mode1_LG << 8) | FLASH_Read_Mode1, NAND_CMD_REG)*/
- mov r7, #0x3000
- str r7, [r6,#0x0]
-
- /* writel(0x00000000, NAND_CONFIGURATION1_REG) */
- mov r7, #0x0
- str r7, [r6, #0x34]
-
- /* start auto-read
- * writel(NAND_LAUNCH_AUTO_READ, NAND_LAUNCH_REG);
- */
- mov r7, #0x80
- str r7, [r6, #0x40]
-
- do_wait_op_done
-
-Copy_Good_Blk:
-1: ldmia r0!, {r7-r14}
- stmia r2!, {r7-r14}
- cmp r0, r1
- blo 1b
- cmp r2, r5
- bge Copy_Main_done
- ldr r7, NFC_PAGE_MODE
- add r4, r4, r7
- ldr r0, =NFC_BASE_ADDR_AXI
- b Read_Page
-
-Copy_Main_done:
- adr r0, SAVE_REGS
- ldr r12, [r0]
- ldr lr, [r0, #4]
- mov pc, lr
-
-U_BOOT_NAND_START: .word TEXT_BASE
-CONST_0X0FFF: .word 0x0FFF
-NFC_PAGE_MODE: .word 0x1000
-SAVE_REGS: .word 0x0
- .word 0x0
+++ /dev/null
-/*
- * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-
-#if defined CONFIG_MX51_UART
-
-#include <asm/arch/mx51.h>
-
-#ifdef CONFIG_MX51_UART1
-#define UART_PHYS UART1_BASE_ADDR
-#elif defined(CONFIG_MX51_UART2)
-#define UART_PHYS UART2_BASE_ADDR
-#elif defined(CONFIG_MX51_UART3)
-#define UART_PHYS UART3_BASE_ADDR
-#else
-#error "define CFG_MX51_UARTx to use the mx51 UART driver"
-#endif
-
-/* Register definitions */
-#define URXD 0x0 /* Receiver Register */
-#define UTXD 0x40 /* Transmitter Register */
-#define UCR1 0x80 /* Control Register 1 */
-#define UCR2 0x84 /* Control Register 2 */
-#define UCR3 0x88 /* Control Register 3 */
-#define UCR4 0x8c /* Control Register 4 */
-#define UFCR 0x90 /* FIFO Control Register */
-#define USR1 0x94 /* Status Register 1 */
-#define USR2 0x98 /* Status Register 2 */
-#define UESC 0x9c /* Escape Character Register */
-#define UTIM 0xa0 /* Escape Timer Register */
-#define UBIR 0xa4 /* BRM Incremental Register */
-#define UBMR 0xa8 /* BRM Modulator Register */
-#define UBRC 0xac /* Baud Rate Count Register */
-#define UTS 0xb4 /* UART Test Register (mx31) */
-
-/* UART Control Register Bit Fields.*/
-#define URXD_CHARRDY (1<<15)
-#define URXD_ERR (1<<14)
-#define URXD_OVRRUN (1<<13)
-#define URXD_FRMERR (1<<12)
-#define URXD_BRK (1<<11)
-#define URXD_PRERR (1<<10)
-#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
-#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
-#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
-#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
-#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
-#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
-#define UCR1_IREN (1<<7) /* Infrared interface enable */
-#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
-#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
-#define UCR1_SNDBRK (1<<4) /* Send break */
-#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
-#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
-#define UCR1_DOZE (1<<1) /* Doze */
-#define UCR1_UARTEN (1<<0) /* UART enabled */
-#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
-#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
-#define UCR2_CTSC (1<<13) /* CTS pin control */
-#define UCR2_CTS (1<<12) /* Clear to send */
-#define UCR2_ESCEN (1<<11) /* Escape enable */
-#define UCR2_PREN (1<<8) /* Parity enable */
-#define UCR2_PROE (1<<7) /* Parity odd/even */
-#define UCR2_STPB (1<<6) /* Stop */
-#define UCR2_WS (1<<5) /* Word size */
-#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
-#define UCR2_TXEN (1<<2) /* Transmitter enabled */
-#define UCR2_RXEN (1<<1) /* Receiver enabled */
-#define UCR2_SRST (1<<0) /* SW reset */
-#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
-#define UCR3_PARERREN (1<<12) /* Parity enable */
-#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
-#define UCR3_DSR (1<<10) /* Data set ready */
-#define UCR3_DCD (1<<9) /* Data carrier detect */
-#define UCR3_RI (1<<8) /* Ring indicator */
-#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
-#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
-#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
-#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
-#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
-#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
-#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
-#define UCR3_BPEN (1<<0) /* Preset registers enable */
-#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
-#define UCR4_INVR (1<<9) /* Inverted infrared reception */
-#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
-#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
-#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
-#define UCR4_IRSC (1<<5) /* IR special case */
-#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
-#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
-#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
-#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
-#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
-#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
-#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
-#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
-#define USR1_RTSS (1<<14) /* RTS pin status */
-#define USR1_TRDY (1<<13)/* Transmitter ready interrupt/dma flag */
-#define USR1_RTSD (1<<12) /* RTS delta */
-#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
-#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
-#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
-#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
-#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
-#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
-#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
-#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
-#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
-#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
-#define USR2_IDLE (1<<12) /* Idle condition */
-#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
-#define USR2_WAKE (1<<7) /* Wake */
-#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
-#define USR2_TXDC (1<<3) /* Transmitter complete */
-#define USR2_BRCD (1<<2) /* Break condition */
-#define USR2_ORE (1<<1) /* Overrun error */
-#define USR2_RDR (1<<0) /* Recv data ready */
-#define UTS_FRCPERR (1<<13) /* Force parity error */
-#define UTS_LOOP (1<<12) /* Loop tx and rx */
-#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
-#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
-#define UTS_TXFULL (1<<4) /* TxFIFO full */
-#define UTS_RXFULL (1<<3) /* RxFIFO full */
-#define UTS_SOFTRST (1<<0) /* Software reset */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void serial_setbrg(void)
-{
- u32 clk = mxc_get_clock(MXC_UART_CLK);
-
- if (!gd->baudrate)
- gd->baudrate = CONFIG_BAUDRATE;
- __REG(UART_PHYS + UFCR) = 0x4 << 7; /* divide input clock by 2 */
- __REG(UART_PHYS + UBIR) = 0xf;
- __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
-}
-
-int serial_getc(void)
-{
- while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
- ;
- return __REG(UART_PHYS + URXD);
-}
-
-void serial_putc(const char c)
-{
- __REG(UART_PHYS + UTXD) = c;
-
- /* wait for transmitter to be ready */
- while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
- ;
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-int serial_tstc(void)
-{
- /* If receive fifo is empty, return false */
- if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
- return 0;
- return 1;
-}
-
-void serial_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init(void)
-{
- __REG(UART_PHYS + UCR1) = 0x0;
- __REG(UART_PHYS + UCR2) = 0x0;
-
- while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST))
- ;
-
- __REG(UART_PHYS + UCR3) = 0x0704;
- __REG(UART_PHYS + UCR4) = 0x8000;
- __REG(UART_PHYS + UESC) = 0x002b;
- __REG(UART_PHYS + UTIM) = 0x0;
-
- __REG(UART_PHYS + UTS) = 0x0;
-
- serial_setbrg();
-
- __REG(UART_PHYS + UCR2) =
- UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
-
- __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
-
- return 0;
-}
-
-#endif /* CONFIG_MX51_UART */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mx51.h>
-
-/* General purpose timers registers */
-#define GPTCR __REG(GPT1_BASE_ADDR) /* Control register */
-#define GPTPR __REG(GPT1_BASE_ADDR + 0x4) /* Prescaler register */
-#define GPTSR __REG(GPT1_BASE_ADDR + 0x8) /* Status register */
-#define GPTCNT __REG(GPT1_BASE_ADDR + 0x24) /* Counter register */
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR (1<<15) /* Software reset */
-#define GPTCR_FRR (1<<9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */
-#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */
-#define GPTCR_TEN (1) /* Timer enable */
-#define GPTPR_VAL (66)
-
-static inline void setup_gpt()
-{
- int i;
- static int init_done;
-
- if (init_done)
- return;
-
- init_done = 1;
-
- /* setup GP Timer 1 */
- GPTCR = GPTCR_SWR;
- for (i = 0; i < 100; i++)
- GPTCR = 0; /* We have no udelay by now */
- GPTPR = GPTPR_VAL; /* 66Mhz / 66 */
- /* Freerun Mode, PERCLK1 input */
- GPTCR |= GPTCR_CLKSOURCE_IPG | GPTCR_TEN;
-}
-
-int timer_init(void)
-{
- setup_gpt();
-
- return 0;
-}
-
-void reset_timer_masked(void)
-{
- GPTCR = 0;
- /* Freerun Mode, PERCLK1 input */
- GPTCR = GPTCR_CLKSOURCE_IPG | GPTCR_TEN;
-}
-
-inline ulong get_timer_masked(void)
-{
- ulong val = GPTCNT;
-
- return val;
-}
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
- ulong tmp;
-
- tmp = get_timer_masked();
-
- if (tmp <= (base * 1000)) {
- /* Overflow */
- tmp += (0xffffffff - base);
- }
-
- return (tmp / 1000) - base;
-}
-
-void set_timer(ulong t)
-{
-}
-
-/* delay x useconds AND perserve advance timstamp value */
-/* GPTCNT is now supposed to tick 1 by 1 us. */
-void udelay(unsigned long usec)
-{
- ulong tmp;
-
- setup_gpt();
-
- tmp = get_timer_masked(); /* get current timestamp */
-
- /* if setting this forward will roll time stamp */
- if ((usec + tmp + 1) < tmp) {
- /* reset "advancing" timestamp to 0, set lastinc value */
- reset_timer_masked();
- } else {
- /* else, set advancing stamp wake up time */
- tmp += usec;
- }
-
- while (get_timer_masked() < tmp) /* loop till event */
- /*NOP*/;
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2010 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(SOC).a
-
-COBJS = interrupts.o serial.o generic.o iomux.o timer.o cache.o
-COBJS += $(COBJS-y)
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-
-all: $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/cache.h>
-
-void l2_cache_enable(void)
-{
- asm("mrc 15, 0, r0, c1, c0, 1");
- asm("orr r0, r0, #0x2");
- asm("mcr 15, 0, r0, c1, c0, 1");
-}
-
-void l2_cache_disable(void)
-{
- asm("mrc 15, 0, r0, c1, c0, 1");
- asm("bic r0, r0, #0x2");
- asm("mcr 15, 0, r0, c1, c0, 1");
-}
-
-/*dummy function for L2 ON*/
-u32 get_device_type(void)
-{
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __ARCH_ARM_MACH_MX53_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX53_CRM_REGS_H__
-
-#define MXC_CCM_BASE CCM_BASE_ADDR
-#define MXC_DPLL1_BASE PLL1_BASE_ADDR
-#define MXC_DPLL2_BASE PLL2_BASE_ADDR
-#define MXC_DPLL3_BASE PLL3_BASE_ADDR
-#define MXC_DPLL4_BASE PLL4_BASE_ADDR
-
-/* PLL Register Offsets */
-#define MXC_PLL_DP_CTL 0x00
-#define MXC_PLL_DP_CONFIG 0x04
-#define MXC_PLL_DP_OP 0x08
-#define MXC_PLL_DP_MFD 0x0C
-#define MXC_PLL_DP_MFN 0x10
-#define MXC_PLL_DP_MFNMINUS 0x14
-#define MXC_PLL_DP_MFNPLUS 0x18
-#define MXC_PLL_DP_HFS_OP 0x1C
-#define MXC_PLL_DP_HFS_MFD 0x20
-#define MXC_PLL_DP_HFS_MFN 0x24
-#define MXC_PLL_DP_MFN_TOGC 0x28
-#define MXC_PLL_DP_DESTAT 0x2c
-
-/* PLL Register Bit definitions */
-#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
-#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
-#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
-#define MXC_PLL_DP_CTL_ADE 0x800
-#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
-#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
-#define MXC_PLL_DP_CTL_HFSM 0x80
-#define MXC_PLL_DP_CTL_PRE 0x40
-#define MXC_PLL_DP_CTL_UPEN 0x20
-#define MXC_PLL_DP_CTL_RST 0x10
-#define MXC_PLL_DP_CTL_RCP 0x8
-#define MXC_PLL_DP_CTL_PLM 0x4
-#define MXC_PLL_DP_CTL_BRM0 0x2
-#define MXC_PLL_DP_CTL_LRF 0x1
-
-#define MXC_PLL_DP_CONFIG_BIST 0x8
-#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
-#define MXC_PLL_DP_CONFIG_AREN 0x2
-#define MXC_PLL_DP_CONFIG_LDREQ 0x1
-
-#define MXC_PLL_DP_OP_MFI_OFFSET 4
-#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
-#define MXC_PLL_DP_OP_PDF_OFFSET 0
-#define MXC_PLL_DP_OP_PDF_MASK 0xF
-
-#define MXC_PLL_DP_MFD_OFFSET 0
-#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_OFFSET 0x0
-#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
-
-#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
-#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
-#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
-#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
-
-#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
-#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
-
-/* Register addresses of CCM*/
-#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00)
-#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04)
-#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08)
-#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C)
-#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10)
-#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14)
-#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18)
-#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C)
-#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20)
-#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24)
-#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28)
-#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C)
-#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30)
-#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34)
-#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38)
-#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C)
-#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40)
-#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44)
-#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48)
-#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C)
-#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50)
-#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54)
-#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58)
-#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C)
-#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60)
-#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64)
-#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68)
-#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C)
-#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70)
-#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74)
-#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78)
-#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C)
-#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80)
-#define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x80)
-#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x88)
-
-/* Define the bits in register CCR */
-#define MXC_CCM_CCR_COSC_EN (1 << 12)
-#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
-#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
-#define MXC_CCM_CCR_FPM_EN (1 << 8)
-#define MXC_CCM_CCR_OSCNT_OFFSET (0)
-#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
-
-/* Define the bits in register CCDR */
-#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 21)
-#define MXC_CCM_CCDR_EMI_HS_INT2_MASK (0x1 << 20)
-#define MXC_CCM_CCDR_EMI_HS_INT1_MASK (0x1 << 19)
-#define MXC_CCM_CCDR_EMI_HS_SLOW_MASK (0x1 << 18)
-#define MXC_CCM_CCDR_EMI_HS_FAST_MASK (0x1 << 17)
-#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
-
-/* Define the bits in register CSR */
-#define MXC_CCM_CSR_COSR_READY (1 << 5)
-#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
-#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
-#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
-#define MXC_CCM_CSR_TEMP_MON_ALARM (1 << 1)
-#define MXC_CCM_CSR_REF_EN_B (1 << 0)
-
-/* Define the bits in register CCSR */
-#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 10)
-#define MXC_CCM_CCSR_LP_APM_SEL_OFFSET 10
-#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (1 << 9)
-#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
-#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
-#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
-#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
-#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
-#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
-#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
-#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
-#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
-
-/* Define the bits in register CACRR */
-#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
-#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
-
-/* Define the bits in register CBCDR */
-#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
-#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
-#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
-#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27)
-#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
-#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
-#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
-#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
-#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
-#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
-#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
-#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
-#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
-#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
-#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
-#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
-#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
-#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
-#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
-
-/* Define the bits in register CBCMR */
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (16)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
-#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
-#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL_OFFSET (1)
-#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
-#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL_OFFSET (0)
-
-/* Define the bits in register CSCMR1 */
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
-#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
-#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
-#define MXC_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
-#define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET (16)
-#define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK (0x3 << 16)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
-#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
-#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
-#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
-#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
-#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
-
-/* Define the bits in register CSCMR2 */
-#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
-#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
-#define MXC_CCM_CSCMR2_ASRC_CLK_SEL (1<<21)
-#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET (19)
-#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
-#define MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET (16)
-#define MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK (0x7 << 16)
-#define MXC_CCM_CSCMR2_IEEE_CLK_SEL_OFFSET (14)
-#define MXC_CCM_CSCMR2_IEEE_CLK_SEL_MASK (0x3 << 14)
-#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
-#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
-#define MXC_CCM_CSCMR2_LBD_DI1_IPU_DIV (0x1 << 11)
-#define MXC_CCM_CSCMR2_LBD_DI0_IPU_DIV (0x1 << 10)
-#define MXC_CCM_CSCMR2_LBD_DI1_CLK_SEL (0x1 << 9)
-#define MXC_CCM_CSCMR2_LBD_DI0_CLK_SEL (0x1 << 8)
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET (6)
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 6)
-#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
-#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
-#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
-#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
-#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
-#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
-
-/* Define the bits in register CSCDR1 */
-#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET (19)
-#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK (0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
-#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
-
-/* Define the bits in register CS1CDR and CS2CDR */
-#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET (25)
-#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
-#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET (9)
-#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x7 << 9)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
-
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
-
-/* Define the bits in register CDCDR */
-#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
-#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
-#define MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET (16)
-#define MXC_CCM_CDCDR_DI_PLL4_PODF_MASK (0x7 << 16)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
-#define MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CDCDR_DI1_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
-#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
-#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
-#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
-
-/* Define the bits in register CHSCCDR */
-#define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_OFFSET (6)
-#define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_MASK (0x3 << 6)
-#define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_OFFSET (4)
-#define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_MASK (0x3 << 4)
-#define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_OFFSET (2)
-#define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_MASK (0x3 << 2)
-#define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_OFFSET (0)
-#define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_MASK (0x3)
-
-/* Define the bits in register CSCDR2 */
-#define MXC_CCM_CSCDR2_ASRC_CLK_PRED_OFFSET (28)
-#define MXC_CCM_CSCDR2_ASRC_CLK_PRED_MASK (0x7 << 28)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
-#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
-#define MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET (9)
-#define MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK (0x3F << 9)
-#define MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CSCDR2_IEEE_CLK_PODF_MASK (0x3F)
-
-/* Define the bits in register CSCDR3 */
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
-
-/* Define the bits in register CSCDR4 */
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
-
-/* Define the bits in register CDHIPR */
-#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
-#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
-#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
-#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
-#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
-#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
-#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
-#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
-#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
-#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
-
-/* Define the bits in register CDCR */
-#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
-
-/* Define the bits in register CLPCR */
-#define MXC_CCM_CLPCR_BYPASS_CAN2_LPM_HS (0x1 << 27)
-#define MXC_CCM_CLPCR_BYPASS_CAN1_LPM_HS (0x1 << 27)
-#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 26)
-#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
-#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 24)
-#define MXC_CCM_CLPCR_BYPASS_EMI_INT2_LPM_HS (0x1 << 23)
-#define MXC_CCM_CLPCR_BYPASS_EMI_INT1_LPM_HS (0x1 << 22)
-#define MXC_CCM_CLPCR_BYPASS_EMI_SLOW_LPM_HS (0x1 << 21)
-#define MXC_CCM_CLPCR_BYPASS_EMI_FAST_LPM_HS (0x1 << 20)
-#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
-#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
-#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
-#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
-#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
-#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
-#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
-#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
-#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
-#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
-#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
-#define MXC_CCM_CLPCR_LPM_OFFSET (0)
-#define MXC_CCM_CLPCR_LPM_MASK (0x3)
-
-/* Define the bits in register CISR */
-#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 26)
-#define MXC_CCM_CISR_TEMP_MON_ALARM (0x1 << 25)
-#define MXC_CCM_CISR_EMI_CLK_SEL_LOADED (0x1 << 23)
-#define MXC_CCM_CISR_PER_CLK_SEL_LOADED (0x1 << 22)
-#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
-#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
-#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
-#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
-#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
-#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
-#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
-#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
-#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
-#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
-#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
-#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
-#define MXC_CCM_CISR_LRF_PLL1 (0x1)
-
-/* Define the bits in register CIMR */
-#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 26)
-#define MXC_CCM_CIMR_MASK_TEMP_MON_ALARM (0x1 << 25)
-#define MXC_CCM_CIMR_MASK_EMI_CLK_SEL_LOADED (0x1 << 23)
-#define MXC_CCM_CIMR_MASK_PER_CLK_SEL_LOADED (0x1 << 22)
-#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
-#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (0x1 << 20)
-#define MXC_CCM_CIMR_MASK_EMI_SLOW_PODF_LOADED (0x1 << 19)
-#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
-#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
-#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
-#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 6)
-#define MXC_CCM_CIMR_MASK_CAMP2_READY (0x1 << 5)
-#define MXC_CCM_CIMR_MASK_CAMP1_READY (0x1 << 4)
-#define MXC_CCM_CIMR_MASK_LRF_PLL4 (0x1 << 3)
-#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
-#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
-#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
-
-/* Define the bits in register CCOSR */
-#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
-#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
-#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
-#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
-#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
-#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
-#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
-#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
-#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
-#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
-
-/* Define the bits in registers CGPR */
-#define MXC_CCM_CGPR_ARM_CLK_INPUT_SEL (0x1 << 24)
-#define MXC_CCM_CGPR_ARM_ASYNC_REF_EN (0x1 << 23)
-#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
-#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
-#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
-#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
-
-/* Define the bits in registers CCGRx */
-#define MXC_CCM_CCGR_CG_MASK 0x3
-
-#define MXC_CCM_CCGR0_CG15_OFFSET 30
-#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
-#define MXC_CCM_CCGR0_CG14_OFFSET 28
-#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR0_CG13_OFFSET 26
-#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR0_CG12_OFFSET 24
-#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR0_CG11_OFFSET 22
-#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR0_CG10_OFFSET 20
-#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR0_CG9_OFFSET 18
-#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR0_CG8_OFFSET 16
-#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR0_CG7_OFFSET 14
-#define MXC_CCM_CCGR0_CG6_OFFSET 12
-#define MXC_CCM_CCGR0_CG5_OFFSET 10
-#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
-#define MXC_CCM_CCGR0_CG4_OFFSET 8
-#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
-#define MXC_CCM_CCGR0_CG3_OFFSET 6
-#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
-#define MXC_CCM_CCGR0_CG2_OFFSET 4
-#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR0_CG1_OFFSET 2
-#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
-#define MXC_CCM_CCGR0_CG0_OFFSET 0
-#define MXC_CCM_CCGR0_CG0_MASK 0x3
-
-#define MXC_CCM_CCGR1_CG15_OFFSET 30
-#define MXC_CCM_CCGR1_CG14_OFFSET 28
-#define MXC_CCM_CCGR1_CG13_OFFSET 26
-#define MXC_CCM_CCGR1_CG12_OFFSET 24
-#define MXC_CCM_CCGR1_CG11_OFFSET 22
-#define MXC_CCM_CCGR1_CG10_OFFSET 20
-#define MXC_CCM_CCGR1_CG9_OFFSET 18
-#define MXC_CCM_CCGR1_CG8_OFFSET 16
-#define MXC_CCM_CCGR1_CG7_OFFSET 14
-#define MXC_CCM_CCGR1_CG6_OFFSET 12
-#define MXC_CCM_CCGR1_CG5_OFFSET 10
-#define MXC_CCM_CCGR1_CG4_OFFSET 8
-#define MXC_CCM_CCGR1_CG3_OFFSET 6
-#define MXC_CCM_CCGR1_CG2_OFFSET 4
-#define MXC_CCM_CCGR1_CG1_OFFSET 2
-#define MXC_CCM_CCGR1_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR2_CG15_OFFSET 30
-#define MXC_CCM_CCGR2_CG14_OFFSET 28
-#define MXC_CCM_CCGR2_CG13_OFFSET 26
-#define MXC_CCM_CCGR2_CG12_OFFSET 24
-#define MXC_CCM_CCGR2_CG11_OFFSET 22
-#define MXC_CCM_CCGR2_CG10_OFFSET 20
-#define MXC_CCM_CCGR2_CG9_OFFSET 18
-#define MXC_CCM_CCGR2_CG8_OFFSET 16
-#define MXC_CCM_CCGR2_CG7_OFFSET 14
-#define MXC_CCM_CCGR2_CG6_OFFSET 12
-#define MXC_CCM_CCGR2_CG5_OFFSET 10
-#define MXC_CCM_CCGR2_CG4_OFFSET 8
-#define MXC_CCM_CCGR2_CG3_OFFSET 6
-#define MXC_CCM_CCGR2_CG2_OFFSET 4
-#define MXC_CCM_CCGR2_CG1_OFFSET 2
-#define MXC_CCM_CCGR2_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR3_CG15_OFFSET 30
-#define MXC_CCM_CCGR3_CG14_OFFSET 28
-#define MXC_CCM_CCGR3_CG13_OFFSET 26
-#define MXC_CCM_CCGR3_CG12_OFFSET 24
-#define MXC_CCM_CCGR3_CG11_OFFSET 22
-#define MXC_CCM_CCGR3_CG10_OFFSET 20
-#define MXC_CCM_CCGR3_CG9_OFFSET 18
-#define MXC_CCM_CCGR3_CG8_OFFSET 16
-#define MXC_CCM_CCGR3_CG7_OFFSET 14
-#define MXC_CCM_CCGR3_CG6_OFFSET 12
-#define MXC_CCM_CCGR3_CG5_OFFSET 10
-#define MXC_CCM_CCGR3_CG4_OFFSET 8
-#define MXC_CCM_CCGR3_CG3_OFFSET 6
-#define MXC_CCM_CCGR3_CG2_OFFSET 4
-#define MXC_CCM_CCGR3_CG1_OFFSET 2
-#define MXC_CCM_CCGR3_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR4_CG15_OFFSET 30
-#define MXC_CCM_CCGR4_CG14_OFFSET 28
-#define MXC_CCM_CCGR4_CG13_OFFSET 26
-#define MXC_CCM_CCGR4_CG12_OFFSET 24
-#define MXC_CCM_CCGR4_CG11_OFFSET 22
-#define MXC_CCM_CCGR4_CG10_OFFSET 20
-#define MXC_CCM_CCGR4_CG9_OFFSET 18
-#define MXC_CCM_CCGR4_CG8_OFFSET 16
-#define MXC_CCM_CCGR4_CG7_OFFSET 14
-#define MXC_CCM_CCGR4_CG6_OFFSET 12
-#define MXC_CCM_CCGR4_CG5_OFFSET 10
-#define MXC_CCM_CCGR4_CG4_OFFSET 8
-#define MXC_CCM_CCGR4_CG3_OFFSET 6
-#define MXC_CCM_CCGR4_CG2_OFFSET 4
-#define MXC_CCM_CCGR4_CG1_OFFSET 2
-#define MXC_CCM_CCGR4_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR5_CG15_OFFSET 30
-#define MXC_CCM_CCGR5_CG14_OFFSET 28
-#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR5_CG13_OFFSET 26
-#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR5_CG12_OFFSET 24
-#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR5_CG11_OFFSET 22
-#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR5_CG10_OFFSET 20
-#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR5_CG9_OFFSET 18
-#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR5_CG8_OFFSET 16
-#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR5_CG7_OFFSET 14
-#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
-#define MXC_CCM_CCGR5_CG6_OFFSET 12
-#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12)
-#define MXC_CCM_CCGR5_CG5_OFFSET 10
-#define MXC_CCM_CCGR5_CG4_OFFSET 8
-#define MXC_CCM_CCGR5_CG3_OFFSET 6
-#define MXC_CCM_CCGR5_CG2_OFFSET 4
-#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR5_CG1_OFFSET 2
-#define MXC_CCM_CCGR5_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR6_CG15_OFFSET 30
-#define MXC_CCM_CCGR6_CG14_OFFSET 28
-#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR6_CG13_OFFSET 26
-#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR6_CG12_OFFSET 24
-#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR6_CG11_OFFSET 22
-#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR6_CG10_OFFSET 20
-#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR6_CG9_OFFSET 18
-#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR6_CG8_OFFSET 16
-#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR6_CG7_OFFSET 14
-#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14)
-#define MXC_CCM_CCGR6_CG6_OFFSET 12
-#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12)
-#define MXC_CCM_CCGR6_CG5_OFFSET 10
-#define MXC_CCM_CCGR6_CG4_OFFSET 8
-#define MXC_CCM_CCGR6_CG3_OFFSET 6
-#define MXC_CCM_CCGR6_CG2_OFFSET 4
-#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR6_CG1_OFFSET 2
-#define MXC_CCM_CCGR6_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR7_CG15_OFFSET 30
-#define MXC_CCM_CCGR7_CG14_OFFSET 28
-#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR7_CG13_OFFSET 26
-#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR7_CG12_OFFSET 24
-#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR7_CG11_OFFSET 22
-#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR7_CG10_OFFSET 20
-#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR7_CG9_OFFSET 18
-#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR7_CG8_OFFSET 16
-#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR7_CG7_OFFSET 14
-#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14)
-#define MXC_CCM_CCGR7_CG6_OFFSET 12
-#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12)
-#define MXC_CCM_CCGR7_CG5_OFFSET 10
-#define MXC_CCM_CCGR7_CG4_OFFSET 8
-#define MXC_CCM_CCGR7_CG3_OFFSET 6
-#define MXC_CCM_CCGR7_CG2_OFFSET 4
-#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR7_CG1_OFFSET 2
-#define MXC_CCM_CCGR7_CG0_OFFSET 0
-
-#define MXC_GPC_BASE (IO_ADDRESS(GPC_BASE_ADDR))
-#define MXC_DPTC_LP_BASE (MXC_GPC_BASE + 0x80)
-#define MXC_DPTC_GP_BASE (MXC_GPC_BASE + 0x100)
-#define MXC_DVFS_CORE_BASE (MXC_GPC_BASE + 0x180)
-#define MXC_DVFS_PER_BASE (MXC_GPC_BASE + 0x1C4)
-#define MXC_PGC_IPU_BASE (MXC_GPC_BASE + 0x220)
-#define MXC_PGC_VPU_BASE (MXC_GPC_BASE + 0x240)
-#define MXC_PGC_GPU_BASE (MXC_GPC_BASE + 0x260)
-#define MXC_SRPG_NEON_BASE (MXC_GPC_BASE + 0x280)
-#define MXC_SRPG_ARM_BASE (MXC_GPC_BASE + 0x2A0)
-#define MXC_SRPG_EMPGC0_BASE (MXC_GPC_BASE + 0x2C0)
-#define MXC_SRPG_EMPGC1_BASE (MXC_GPC_BASE + 0x2D0)
-#define MXC_SRPG_MEGAMIX_BASE (MXC_GPC_BASE + 0x2E0)
-#define MXC_SRPG_EMI_BASE (MXC_GPC_BASE + 0x300)
-
-/* DVFS CORE */
-#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
-#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
-#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
-#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
-#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
-#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
-#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
-#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
-#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
-#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
-#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
-#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
-#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
-#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
-#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
-#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
-#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
-
-/* DVFS PER */
-#define MXC_DVFSPER_LTR0 (MXC_DVFS_PER_BASE)
-#define MXC_DVFSPER_LTR1 (MXC_DVFS_PER_BASE + 0x04)
-#define MXC_DVFSPER_LTR2 (MXC_DVFS_PER_BASE + 0x08)
-#define MXC_DVFSPER_LTR3 (MXC_DVFS_PER_BASE + 0x0C)
-#define MXC_DVFSPER_LTBR0 (MXC_DVFS_PER_BASE + 0x10)
-#define MXC_DVFSPER_LTBR1 (MXC_DVFS_PER_BASE + 0x14)
-#define MXC_DVFSPER_PMCR0 (MXC_DVFS_PER_BASE + 0x18)
-#define MXC_DVFSPER_PMCR1 (MXC_DVFS_PER_BASE + 0x1C)
-
-/* GPC */
-#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0)
-#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4)
-#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8)
-#define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC)
-#define MXC_GPC_NEON (MXC_GPC_BASE + 0x10)
-
-/* PGC */
-#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
-#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
-#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
-#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
-#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
-#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
-
-#define MXC_PGCR_PCR 1
-#define MXC_SRPGCR_PCR 1
-#define MXC_EMPGCR_PCR 1
-#define MXC_PGSR_PSR 1
-
-
-#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
-#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
-
-/* SRPG */
-#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
-#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
-#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
-
-#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
-#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
-#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
-
-#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
-#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
-#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
-
-#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
-#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
-#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
-
-#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
-#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
-#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
-
-#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
-#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
-#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
-
-#endif /* __ARCH_ARM_MACH_MX53_CRM_REGS_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mx53.h>
-#include <asm/errno.h>
-#include <asm/io.h>
-#include "crm_regs.h"
-#ifdef CONFIG_CMD_CLOCK
-#include <asm/clock.h>
-#endif
-#include <div64.h>
-#ifdef CONFIG_ARCH_CPU_INIT
-#include <asm/cache-cp15.h>
-#endif
-
-enum pll_clocks {
- PLL1_CLK = MXC_DPLL1_BASE,
- PLL2_CLK = MXC_DPLL2_BASE,
- PLL3_CLK = MXC_DPLL3_BASE,
- PLL4_CLK = MXC_DPLL4_BASE,
-};
-
-enum pll_sw_clocks {
- PLL1_SW_CLK,
- PLL2_SW_CLK,
- PLL3_SW_CLK,
- PLL4_SW_CLK,
-};
-
-#define AHB_CLK_ROOT 133333333
-#define IPG_CLK_ROOT 66666666
-#define IPG_PER_CLK_ROOT 40000000
-
-#ifdef CONFIG_CMD_CLOCK
-#define SZ_DEC_1M 1000000
-#define PLL_PD_MAX 16 /* Actual pd+1 */
-#define PLL_MFI_MAX 15
-#define PLL_MFI_MIN 5
-#define ARM_DIV_MAX 8
-#define IPG_DIV_MAX 4
-#define AHB_DIV_MAX 8
-#define EMI_DIV_MAX 8
-#define NFC_DIV_MAX 8
-
-struct fixed_pll_mfd {
- u32 ref_clk_hz;
- u32 mfd;
-};
-
-const struct fixed_pll_mfd fixed_mfd[4] = {
- {0, 0}, /* reserved */
- {0, 0}, /* reserved */
- {CONFIG_MX53_HCLK_FREQ, 24 * 16}, /* 384 */
- {0, 0}, /* reserved */
-};
-
-struct pll_param {
- u32 pd;
- u32 mfi;
- u32 mfn;
- u32 mfd;
-};
-
-#define PLL_FREQ_MAX(_ref_clk_) \
- (4 * _ref_clk_ * PLL_MFI_MAX)
-#define PLL_FREQ_MIN(_ref_clk_) \
- ((2 * _ref_clk_ * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
-#define MAX_DDR_CLK 420000000
-#define AHB_CLK_MAX 133333333
-#define IPG_CLK_MAX (AHB_CLK_MAX / 2)
-#define NFC_CLK_MAX 25000000
-#define HSP_CLK_MAX 133333333
-#endif
-
-static u32 __decode_pll(enum pll_clocks pll, u32 infreq)
-{
- u32 mfi, mfn, mfd, pd;
-
- mfn = __REG(pll + MXC_PLL_DP_MFN);
- mfd = __REG(pll + MXC_PLL_DP_MFD) + 1;
- mfi = __REG(pll + MXC_PLL_DP_OP);
- pd = (mfi & 0xF) + 1;
- mfi = (mfi >> 4) & 0xF;
- mfi = (mfi >= 5) ? mfi : 5;
-
- return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
-}
-
-static u32 __get_mcu_main_clk(void)
-{
- u32 reg, freq;
- reg = (__REG(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
- MXC_CCM_CACRR_ARM_PODF_OFFSET;
- freq = __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ);
- return freq / (reg + 1);
-}
-
-static u32 __get_periph_clk(void)
-{
- u32 reg;
- reg = __REG(MXC_CCM_CBCDR);
- if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
- reg = __REG(MXC_CCM_CBCMR);
- switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
- MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
- case 0:
- return __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ);
- case 1:
- return __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ);
- default:
- return 0;
- }
- }
- return __decode_pll(PLL2_CLK, CONFIG_MX53_HCLK_FREQ);
-}
-
-static u32 __get_ipg_clk(void)
-{
- u32 ahb_podf, ipg_podf;
-
- ahb_podf = __REG(MXC_CCM_CBCDR);
- ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
- MXC_CCM_CBCDR_IPG_PODF_OFFSET;
- ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
- MXC_CCM_CBCDR_AHB_PODF_OFFSET;
- return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
-}
-
-static u32 __get_ipg_per_clk(void)
-{
- u32 pred1, pred2, podf;
- if (__REG(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
- return __get_ipg_clk();
- /* Fixme: not handle what about lpm */
- podf = __REG(MXC_CCM_CBCDR);
- pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
- pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
- podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
-
- return __get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
-}
-
-/*!
- * This function returns the low power audio clock.
- */
-static u32 __get_lp_apm(void)
-{
- u32 ret_val = 0;
- u32 ccsr = __REG(MXC_CCM_CCSR);
-
- if (((ccsr >> MXC_CCM_CCSR_LP_APM_SEL_OFFSET) & 1) == 0)
- ret_val = CONFIG_MX53_HCLK_FREQ;
- else
- ret_val = ((32768 * 1024));
-
- return ret_val;
-}
-
-/*
-static u32 __get_perclk_lp_apm(void)
-{
- u32 ret_val = 0;
- u32 cbcmr = __REG(MXC_CCM_CBCMR);
- u32 clk_sel = (cbcmr & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) \
- >> MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL_OFFSET;
-
- switch (clk_sel) {
- case 0:
- ret_val = __get_periph_clk();
- break;
- case 1:
- ret_val = __get_lp_apm();
- break;
- default:
- break;
- }
-
- return ret_val;
-}
-*/
-
-static u32 __get_uart_clk(void)
-{
- u32 freq = 0, reg, pred, podf;
- reg = __REG(MXC_CCM_CSCMR1);
- switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
- MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
- case 0x0:
- freq = __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ);
- break;
- case 0x1:
- freq = __decode_pll(PLL2_CLK, CONFIG_MX53_HCLK_FREQ);
- break;
- case 0x2:
- freq = __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ);
- break;
- case 0x4:
- freq = __get_lp_apm();
- break;
- default:
- break;
- }
-
- reg = __REG(MXC_CCM_CSCDR1);
-
- pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
- MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
-
- podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
- MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
- freq /= (pred + 1) * (podf + 1);
-
- return freq;
-}
-
-
-static u32 __get_cspi_clk(void)
-{
- u32 ret_val = 0, pdf, pre_pdf, clk_sel, div;
- u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
- u32 cscdr2 = __REG(MXC_CCM_CSCDR2);
-
- pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
- >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
- pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
- >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
- clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
- >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
-
- div = (pre_pdf + 1) * (pdf + 1);
-
- switch (clk_sel) {
- case 0:
- ret_val = __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ) / div;
- break;
- case 1:
- ret_val = __decode_pll(PLL2_CLK, CONFIG_MX53_HCLK_FREQ) / div;
- break;
- case 2:
- ret_val = __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ) / div;
- break;
- default:
- ret_val = __get_lp_apm() / div;
- break;
- }
-
- return ret_val;
-}
-
-static u32 __get_axi_a_clk(void)
-{
- u32 cbcdr = __REG(MXC_CCM_CBCDR);
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
- >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
-
- return __get_periph_clk() / (pdf + 1);
-}
-
-static u32 __get_axi_b_clk(void)
-{
- u32 cbcdr = __REG(MXC_CCM_CBCDR);
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
- >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
-
- return __get_periph_clk() / (pdf + 1);
-}
-
-static u32 __get_ahb_clk(void)
-{
- u32 cbcdr = __REG(MXC_CCM_CBCDR);
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_AHB_PODF_MASK) \
- >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
-
- return __get_periph_clk() / (pdf + 1);
-}
-
-
-static u32 __get_emi_slow_clk(void)
-{
- u32 cbcdr = __REG(MXC_CCM_CBCDR);
- u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
- >> MXC_CCM_CBCDR_EMI_PODF_OFFSET;
-
- if (emi_clk_sel)
- return __get_ahb_clk() / (pdf + 1);
-
- return __get_periph_clk() / (pdf + 1);
-}
-
-/*
-static u32 __get_nfc_clk(void)
-{
- u32 cbcdr = __REG(MXC_CCM_CBCDR);
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_NFC_PODF_MASK) \
- >> MXC_CCM_CBCDR_NFC_PODF_OFFSET;
-
- return __get_emi_slow_clk() / (pdf + 1);
-}
-*/
-
-static u32 __get_ddr_clk(void)
-{
- u32 ret_val = 0;
- u32 cbcmr = __REG(MXC_CCM_CBCMR);
- u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
- >> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
-
- switch (ddr_clk_sel) {
- case 0:
- ret_val = __get_axi_a_clk();
- break;
- case 1:
- ret_val = __get_axi_b_clk();
- break;
- case 2:
- ret_val = __get_emi_slow_clk();
- break;
- case 3:
- ret_val = __get_ahb_clk();
- break;
- default:
- break;
- }
-
- return ret_val;
-}
-
-static u32 __get_esdhc1_clk(void)
-{
- u32 ret_val = 0, div, pre_pdf, pdf;
- u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
- u32 cscdr1 = __REG(MXC_CCM_CSCDR1);
- u32 esdh1_clk_sel;
-
- esdh1_clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK) \
- >> MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET;
- pre_pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) \
- >> MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET;
- pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) \
- >> MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET ;
-
- div = (pre_pdf + 1) * (pdf + 1);
-
- switch (esdh1_clk_sel) {
- case 0:
- ret_val = __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ);
- break;
- case 1:
- ret_val = __decode_pll(PLL2_CLK, CONFIG_MX53_HCLK_FREQ);
- break;
- case 2:
- ret_val = __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ);
- break;
- case 3:
- ret_val = __get_lp_apm();
- break;
- default:
- break;
- }
-
- ret_val /= div;
-
- return ret_val;
-}
-
-static u32 __get_esdhc3_clk(void)
-{
- u32 ret_val = 0, div, pre_pdf, pdf;
- u32 esdh3_clk_sel;
- u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
- u32 cscdr1 = __REG(MXC_CCM_CSCDR1);
- esdh3_clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK) \
- >> MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET;
- pre_pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK) \
- >> MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET;
- pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK) \
- >> MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET ;
-
- div = (pre_pdf + 1) * (pdf + 1);
-
- switch (esdh3_clk_sel) {
- case 0:
- ret_val = __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ);
- break;
- case 1:
- ret_val = __decode_pll(PLL2_CLK, CONFIG_MX53_HCLK_FREQ);
- break;
- case 2:
- ret_val = __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ);
- break;
- case 3:
- ret_val = __get_lp_apm();
- break;
- default:
- break;
- }
-
- ret_val /= div;
-
- return ret_val;
-}
-
-static u32 __get_esdhc2_clk(void)
-{
- u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
- u32 esdh2_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ESDHC2_CLK_SEL;
- if (esdh2_clk_sel)
- return __get_esdhc3_clk();
-
- return __get_esdhc1_clk();
-}
-
-static u32 __get_esdhc4_clk(void)
-{
- u32 cscmr1 = __REG(MXC_CCM_CSCMR1);
- u32 esdh4_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
- if (esdh4_clk_sel)
- return __get_esdhc3_clk();
-
- return __get_esdhc1_clk();
-}
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
- switch (clk) {
- case MXC_ARM_CLK:
- return __get_mcu_main_clk();
- case MXC_PER_CLK:
- return __get_periph_clk();
- case MXC_AHB_CLK:
- return __get_ahb_clk();
- case MXC_IPG_CLK:
- return __get_ipg_clk();
- case MXC_IPG_PERCLK:
- return __get_ipg_per_clk();
- case MXC_UART_CLK:
- return __get_uart_clk();
- case MXC_CSPI_CLK:
- return __get_cspi_clk();
- case MXC_AXI_A_CLK:
- return __get_axi_a_clk();
- case MXC_AXI_B_CLK:
- return __get_axi_b_clk();
- case MXC_EMI_SLOW_CLK:
- return __get_emi_slow_clk();
- case MXC_DDR_CLK:
- return __get_ddr_clk();
- case MXC_ESDHC_CLK:
- return __get_esdhc1_clk();
- case MXC_ESDHC2_CLK:
- return __get_esdhc2_clk();
- case MXC_ESDHC3_CLK:
- return __get_esdhc3_clk();
- case MXC_ESDHC4_CLK:
- return __get_esdhc4_clk();
- case MXC_SATA_CLK:
- return __get_ahb_clk();
- default:
- break;
- }
- return -1;
-}
-
-void mxc_dump_clocks(void)
-{
- u32 freq;
- freq = __decode_pll(PLL1_CLK, CONFIG_MX53_HCLK_FREQ);
- printf("mx53 pll1: %dMHz\n", freq / 1000000);
- freq = __decode_pll(PLL2_CLK, CONFIG_MX53_HCLK_FREQ);
- printf("mx53 pll2: %dMHz\n", freq / 1000000);
- freq = __decode_pll(PLL3_CLK, CONFIG_MX53_HCLK_FREQ);
- printf("mx53 pll3: %dMHz\n", freq / 1000000);
- printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
- printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
- printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
- printf("cspi clock : %dHz\n", mxc_get_clock(MXC_CSPI_CLK));
- printf("ahb clock : %dHz\n", mxc_get_clock(MXC_AHB_CLK));
- printf("axi_a clock : %dHz\n", mxc_get_clock(MXC_AXI_A_CLK));
- printf("axi_b clock : %dHz\n", mxc_get_clock(MXC_AXI_B_CLK));
- printf("emi_slow clock: %dHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK));
- printf("ddr clock : %dHz\n", mxc_get_clock(MXC_DDR_CLK));
- printf("esdhc1 clock : %dHz\n", mxc_get_clock(MXC_ESDHC_CLK));
- printf("esdhc2 clock : %dHz\n", mxc_get_clock(MXC_ESDHC2_CLK));
- printf("esdhc3 clock : %dHz\n", mxc_get_clock(MXC_ESDHC3_CLK));
- printf("esdhc4 clock : %dHz\n", mxc_get_clock(MXC_ESDHC4_CLK));
-}
-
-#ifdef CONFIG_CMD_CLOCK
-/* precondition: m>0 and n>0. Let g=gcd(m,n). */
-static int gcd(int m, int n)
-{
- int t;
- while (m > 0) {
- if (n > m) {
- t = m;
- m = n;
- n = t;
- } /* swap */
- m -= n;
- }
- return n;
-}
-
-/*!
- * This is to calculate various parameters based on reference clock and
- * targeted clock based on the equation:
- * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
- * This calculation is based on a fixed MFD value for simplicity.
- *
- * @param ref reference clock freq in Hz
- * @param target targeted clock in Hz
- * @param pll pll_param structure.
- *
- * @return 0 if successful; non-zero otherwise.
- */
-static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
-{
- u64 pd, mfi = 1, mfn, mfd, t1;
- u32 n_target = target;
- u32 n_ref = ref, i;
-
- /*
- * Make sure targeted freq is in the valid range.
- * Otherwise the following calculation might be wrong!!!
- */
- if (n_target < PLL_FREQ_MIN(ref) ||
- n_target > PLL_FREQ_MAX(ref)) {
- printf("Targeted peripheral clock should be"
- "within [%d - %d]\n",
- PLL_FREQ_MIN(ref) / SZ_DEC_1M,
- PLL_FREQ_MAX(ref) / SZ_DEC_1M);
- return -1;
- }
-
- for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
- if (fixed_mfd[i].ref_clk_hz == ref) {
- mfd = fixed_mfd[i].mfd;
- break;
- }
- }
-
- if (i == ARRAY_SIZE(fixed_mfd))
- return -1;
-
- /* Use n_target and n_ref to avoid overflow */
- for (pd = 1; pd <= PLL_PD_MAX; pd++) {
- t1 = n_target * pd;
- do_div(t1, (4 * n_ref));
- mfi = t1;
- if (mfi > PLL_MFI_MAX)
- return -1;
- else if (mfi < 5)
- continue;
- break;
- }
- /* Now got pd and mfi already */
- /*
- mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
- */
- t1 = n_target * pd;
- do_div(t1, 4);
- t1 -= n_ref * mfi;
- t1 *= mfd;
- do_div(t1, n_ref);
- mfn = t1;
-#ifdef CMD_CLOCK_DEBUG
- printf("%d: ref=%d, target=%d, pd=%d,"
- "mfi=%d,mfn=%d, mfd=%d\n",
- __LINE__, ref, (u32)n_target,
- (u32)pd, (u32)mfi, (u32)mfn,
- (u32)mfd);
-#endif
- i = 1;
- if (mfn != 0)
- i = gcd(mfd, mfn);
- pll->pd = (u32)pd;
- pll->mfi = (u32)mfi;
- do_div(mfn, i);
- pll->mfn = (u32)mfn;
- do_div(mfd, i);
- pll->mfd = (u32)mfd;
-
- return 0;
-}
-
-int clk_info(u32 clk_type)
-{
- switch (clk_type) {
- case CPU_CLK:
- printf("CPU Clock: %dHz\n",
- mxc_get_clock(MXC_ARM_CLK));
- break;
- case PERIPH_CLK:
- printf("Peripheral Clock: %dHz\n",
- mxc_get_clock(MXC_PER_CLK));
- break;
- case AHB_CLK:
- printf("AHB Clock: %dHz\n",
- mxc_get_clock(MXC_AHB_CLK));
- break;
- case IPG_CLK:
- printf("IPG Clock: %dHz\n",
- mxc_get_clock(MXC_IPG_CLK));
- break;
- case IPG_PERCLK:
- printf("IPG_PER Clock: %dHz\n",
- mxc_get_clock(MXC_IPG_PERCLK));
- break;
- case UART_CLK:
- printf("UART Clock: %dHz\n",
- mxc_get_clock(MXC_UART_CLK));
- break;
- case CSPI_CLK:
- printf("CSPI Clock: %dHz\n",
- mxc_get_clock(MXC_CSPI_CLK));
- break;
- case DDR_CLK:
- printf("DDR Clock: %dHz\n",
- mxc_get_clock(MXC_DDR_CLK));
- break;
- case ALL_CLK:
- printf("cpu clock: %dMHz\n",
- mxc_get_clock(MXC_ARM_CLK) / SZ_DEC_1M);
- mxc_dump_clocks();
- break;
- default:
- printf("Unsupported clock type! :(\n");
- }
-
- return 0;
-}
-
-#define calc_div(target_clk, src_clk, limit) ({ \
- u32 tmp = 0; \
- if ((src_clk % target_clk) <= 100) \
- tmp = src_clk / target_clk; \
- else \
- tmp = (src_clk / target_clk) + 1; \
- if (tmp > limit) \
- tmp = limit; \
- (tmp - 1); \
- })
-
-u32 calc_per_cbcdr_val(u32 per_clk, u32 cbcmr)
-{
- u32 cbcdr = __REG(MXC_CCM_CBCDR);
- u32 tmp_clk = 0, div = 0, clk_sel = 0;
-
- cbcdr &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
-
- /* emi_slow_podf divider */
- tmp_clk = __get_emi_slow_clk();
- clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
- if (clk_sel) {
- div = calc_div(tmp_clk, per_clk, 8);
- cbcdr &= ~MXC_CCM_CBCDR_EMI_PODF_MASK;
- cbcdr |= (div << MXC_CCM_CBCDR_EMI_PODF_OFFSET);
- }
-
- /* axi_b_podf divider */
- tmp_clk = __get_axi_b_clk();
- div = calc_div(tmp_clk, per_clk, 8);
- cbcdr &= ~MXC_CCM_CBCDR_AXI_B_PODF_MASK;
- cbcdr |= (div << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET);
-
- /* axi_b_podf divider */
- tmp_clk = __get_axi_a_clk();
- div = calc_div(tmp_clk, per_clk, 8);
- cbcdr &= ~MXC_CCM_CBCDR_AXI_A_PODF_MASK;
- cbcdr |= (div << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET);
-
- /* ahb podf divider */
- tmp_clk = AHB_CLK_ROOT;
- div = calc_div(tmp_clk, per_clk, 8);
- cbcdr &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
- cbcdr |= (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET);
-
- return cbcdr;
-}
-
-#define CHANGE_PLL_SETTINGS(base, pd, mfi, mfn, mfd) \
- { \
- writel(0x1232, base + PLL_DP_CTL); \
- writel(0x2, base + PLL_DP_CONFIG); \
- writel(((pd - 1) << 0) | (mfi << 4), \
- base + PLL_DP_OP); \
- writel(mfn, base + PLL_DP_MFN); \
- writel(mfd - 1, base + PLL_DP_MFD); \
- writel(((pd - 1) << 0) | (mfi << 4), \
- base + PLL_DP_HFS_OP); \
- writel(mfn, base + PLL_DP_HFS_MFN); \
- writel(mfd - 1, base + PLL_DP_HFS_MFD); \
- writel(0x1232, base + PLL_DP_CTL); \
- while (!readl(base + PLL_DP_CTL) & 0x1) \
- ; \
- }
-
-int config_pll_clk(enum pll_clocks pll, struct pll_param *pll_param)
-{
- u32 ccsr = readl(CCM_BASE_ADDR + CLKCTL_CCSR);
- u32 pll_base = pll;
-
- switch (pll) {
- case PLL1_CLK:
- /* Switch ARM to PLL2 clock */
- writel(ccsr | 0x4, CCM_BASE_ADDR + CLKCTL_CCSR);
- CHANGE_PLL_SETTINGS(pll_base, pll_param->pd,
- pll_param->mfi, pll_param->mfn,
- pll_param->mfd);
- /* Switch back */
- writel(ccsr & ~0x4, CCM_BASE_ADDR + CLKCTL_CCSR);
- break;
- case PLL2_CLK:
- /* Switch to pll2 bypass clock */
- writel(ccsr | 0x2, CCM_BASE_ADDR + CLKCTL_CCSR);
- CHANGE_PLL_SETTINGS(pll_base, pll_param->pd,
- pll_param->mfi, pll_param->mfn,
- pll_param->mfd);
- /* Switch back */
- writel(ccsr & ~0x2, CCM_BASE_ADDR + CLKCTL_CCSR);
- break;
- case PLL3_CLK:
- /* Switch to pll3 bypass clock */
- writel(ccsr | 0x1, CCM_BASE_ADDR + CLKCTL_CCSR);
- CHANGE_PLL_SETTINGS(pll_base, pll_param->pd,
- pll_param->mfi, pll_param->mfn,
- pll_param->mfd);
- /* Switch back */
- writel(ccsr & ~0x1, CCM_BASE_ADDR + CLKCTL_CCSR);
- break;
- case PLL4_CLK:
- /* Switch to pll4 bypass clock */
- writel(ccsr | 0x20, CCM_BASE_ADDR + CLKCTL_CCSR);
- CHANGE_PLL_SETTINGS(pll_base, pll_param->pd,
- pll_param->mfi, pll_param->mfn,
- pll_param->mfd);
- /* Switch back */
- writel(ccsr & ~0x20, CCM_BASE_ADDR + CLKCTL_CCSR);
- break;
- default:
- return -1;
- }
-
- return 0;
-}
-
-int config_core_clk(u32 ref, u32 freq)
-{
- int ret = 0;
- u32 pll = 0;
- struct pll_param pll_param;
-
- memset(&pll_param, 0, sizeof(struct pll_param));
-
- /* The case that periph uses PLL1 is not considered here */
- pll = freq;
- ret = calc_pll_params(ref, pll, &pll_param);
- if (ret != 0) {
- printf("Can't find pll parameters: %d\n",
- ret);
- return ret;
- }
-
- return config_pll_clk(PLL1_CLK, &pll_param);
-}
-
-int config_periph_clk(u32 ref, u32 freq)
-{
- int ret = 0;
- u32 pll = freq;
- struct pll_param pll_param;
-
- memset(&pll_param, 0, sizeof(struct pll_param));
-
- if (__REG(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
- /* Actually this case is not considered here */
- ret = calc_pll_params(ref, pll, &pll_param);
- if (ret != 0) {
- printf("Can't find pll parameters: %d\n",
- ret);
- return ret;
- }
- switch ((__REG(MXC_CCM_CBCMR) & \
- MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
- MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
- case 0:
- return config_pll_clk(PLL1_CLK, &pll_param);
- break;
- case 1:
- return config_pll_clk(PLL3_CLK, &pll_param);
- break;
- default:
- return -1;
- }
- } else {
- u32 old_cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
- u32 new_cbcdr = calc_per_cbcdr_val(pll, old_cbcmr);
-
- /* Switch peripheral to PLL3 */
- writel(0x00015154, CCM_BASE_ADDR + CLKCTL_CBCMR);
- writel(0x02888945, CCM_BASE_ADDR + CLKCTL_CBCDR);
-
- /* Make sure change is effective */
- while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
- ;
-
- /* Setup PLL2 */
- ret = calc_pll_params(ref, pll, &pll_param);
- if (ret != 0) {
- printf("Can't find pll parameters: %d\n",
- ret);
- return ret;
- }
- config_pll_clk(PLL2_CLK, &pll_param);
-
- /* Switch peripheral back */
- writel(new_cbcdr, CCM_BASE_ADDR + CLKCTL_CBCDR);
- writel(old_cbcmr, CCM_BASE_ADDR + CLKCTL_CBCMR);
-
- /* Make sure change is effective */
- while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
- ;
- puts("\n");
- }
-
- return 0;
-}
-
-int config_ddr_clk(u32 emi_clk)
-{
- u32 clk_src;
- s32 shift = 0, clk_sel, div = 1;
- u32 cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
- u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
-
- if (emi_clk > MAX_DDR_CLK) {
- printf("DDR clock should be less than"
- "%d MHz, assuming max value \n",
- (MAX_DDR_CLK / SZ_DEC_1M));
- emi_clk = MAX_DDR_CLK;
- }
-
- clk_src = __get_periph_clk();
- /* Find DDR clock input */
- clk_sel = (cbcmr >> 10) & 0x3;
- switch (clk_sel) {
- case 0:
- shift = 16;
- break;
- case 1:
- shift = 19;
- break;
- case 2:
- shift = 22;
- break;
- case 3:
- shift = 10;
- break;
- default:
- return -1;
- }
-
- if ((clk_src % emi_clk) == 0)
- div = clk_src / emi_clk;
- else
- div = (clk_src / emi_clk) + 1;
- if (div > 8)
- div = 8;
-
- cbcdr = cbcdr & ~(0x7 << shift);
- cbcdr |= ((div - 1) << shift);
- writel(cbcdr, CCM_BASE_ADDR + CLKCTL_CBCDR);
- while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
- ;
- writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
-
- return 0;
-}
-
-/*!
- * This function assumes the expected core clock has to be changed by
- * modifying the PLL. This is NOT true always but for most of the times,
- * it is. So it assumes the PLL output freq is the same as the expected
- * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
- * In the latter case, it will try to increase the presc value until
- * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
- * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
- * on the targeted PLL and reference input clock to the PLL. Lastly,
- * it sets the register based on these values along with the dividers.
- * Note 1) There is no value checking for the passed-in divider values
- * so the caller has to make sure those values are sensible.
- * 2) Also adjust the NFC divider such that the NFC clock doesn't
- * exceed NFC_CLK_MAX.
- * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
- * 177MHz for higher voltage, this function fixes the max to 133MHz.
- * 4) This function should not have allowed diag_printf() calls since
- * the serial driver has been stoped. But leave then here to allow
- * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
- *
- * @param ref pll input reference clock (24MHz)
- * @param freq core clock in Hz
- * @param clk_type clock type, e.g CPU_CLK, DDR_CLK, etc.
- * @return 0 if successful; non-zero otherwise
- */
-int clk_config(u32 ref, u32 freq, u32 clk_type)
-{
- freq *= SZ_DEC_1M;
-
- switch (clk_type) {
- case CPU_CLK:
- if (config_core_clk(ref, freq))
- return -1;
- break;
- case PERIPH_CLK:
- if (config_periph_clk(ref, freq))
- return -1;
- break;
- case DDR_CLK:
- if (config_ddr_clk(freq))
- return -1;
- break;
- default:
- printf("Unsupported or invalid clock type! :(\n");
- }
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- printf("CPU: Freescale i.MX53 family %d.%dV at %d MHz\n",
- (get_board_rev() & 0xFF) >> 4,
- (get_board_rev() & 0xF),
- __get_mcu_main_clk() / 1000000);
- return 0;
-}
-#endif
-
-#if defined(CONFIG_MXC_FEC)
-extern int mxc_fec_initialize(bd_t *bis);
-extern void mxc_fec_set_mac_from_env(char *mac_addr);
-#endif
-
-int cpu_eth_init(bd_t *bis)
-{
- int rc = -ENODEV;
-#if defined(CONFIG_MXC_FEC)
- rc = mxc_fec_initialize(bis);
-#endif
- return rc;
-}
-
-#if defined(CONFIG_ARCH_CPU_INIT)
-int arch_cpu_init(void)
-{
- icache_enable();
- dcache_enable();
-
-#ifdef CONFIG_L2_OFF
- l2_cache_disable();
-#else
- l2_cache_enable();
-#endif
- return 0;
-}
-#endif
-
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mx53.h>
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int interrupt_init(void)
-{
- return 0;
-}
-
-void reset_cpu(ulong addr)
-{
- __REG16(WDOG1_BASE_ADDR) = 4;
-}
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/*!
- * @defgroup GPIO_MX53 Board GPIO and Muxing Setup
- * @ingroup MSL_MX53
- */
-/*!
- * @file mach-mx53/iomux.c
- *
- * @brief I/O Muxing control functions
- *
- * @ingroup GPIO_MX53
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mx53.h>
-#include <asm/arch/mx53_pins.h>
-#include <asm/arch/iomux.h>
-
-/*!
- * IOMUX register (base) addresses
- */
-enum iomux_reg_addr {
- IOMUXGPR0 = IOMUXC_BASE_ADDR,
- IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
- IOMUXGPR2 = IOMUXC_BASE_ADDR + 0x008,
- IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
- IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
- IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
- IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START,
-};
-
-static inline u32 _get_mux_reg(iomux_pin_name_t pin)
-{
- u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
- mux_reg += IOMUXSW_MUX_CTL;
-
- return mux_reg;
-}
-
-static inline u32 _get_pad_reg(iomux_pin_name_t pin)
-{
- u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
-
- pad_reg += IOMUXSW_PAD_CTL;
-
- return pad_reg;
-}
-
-static inline u32 _get_mux_end(void)
-{
- return IOMUXSW_MUX_END;
-}
-
-/*!
- * This function is used to configure a pin through the IOMUX module.
- * FIXED ME: for backward compatible. Will be static function!
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @param cfg an output function as defined in \b #iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- u32 mux_reg = _get_mux_reg(pin);
-
- if ((mux_reg > _get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
- return -1;
- if (cfg == IOMUX_CONFIG_GPIO)
- writel(PIN_TO_ALT_GPIO(pin), mux_reg);
- else
- writel(cfg, mux_reg);
-
- return 0;
-}
-
-/*!
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param cfg an input function as defined in \b #iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- int ret = iomux_config_mux(pin, cfg);
-
- return ret;
-}
-
-/*!
- * Release ownership for an IO pin
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param cfg an input function as defined in \b #iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*!
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @param config the ORed value of elements defined in \b #iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
- u32 pad_reg = _get_pad_reg(pin);
-
- writel(config, pad_reg);
-}
-
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
-{
- u32 pad_reg = _get_pad_reg(pin);
-
- return readl(pad_reg);
-}
-/*!
- * This function configures input path.
- *
- * @param input index of input select register as defined in \b
- * #iomux_input_select_t
- * @param config the binary value of elements defined in \b
- * #iomux_input_config_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
-{
- u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
-
- writel(config, reg);
-}
+++ /dev/null
-/*
- * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
- *
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-
-#if defined CONFIG_MX53_UART
-
-#include <asm/arch/mx53.h>
-
-#ifdef CONFIG_MX53_UART1
-#define UART_PHYS UART1_BASE_ADDR
-#elif defined(CONFIG_MX53_UART2)
-#define UART_PHYS UART2_BASE_ADDR
-#elif defined(CONFIG_MX53_UART3)
-#define UART_PHYS UART3_BASE_ADDR
-#else
-#error "define CFG_MX53_UARTx to use the mx53 UART driver"
-#endif
-
-/* Register definitions */
-#define URXD 0x0 /* Receiver Register */
-#define UTXD 0x40 /* Transmitter Register */
-#define UCR1 0x80 /* Control Register 1 */
-#define UCR2 0x84 /* Control Register 2 */
-#define UCR3 0x88 /* Control Register 3 */
-#define UCR4 0x8c /* Control Register 4 */
-#define UFCR 0x90 /* FIFO Control Register */
-#define USR1 0x94 /* Status Register 1 */
-#define USR2 0x98 /* Status Register 2 */
-#define UESC 0x9c /* Escape Character Register */
-#define UTIM 0xa0 /* Escape Timer Register */
-#define UBIR 0xa4 /* BRM Incremental Register */
-#define UBMR 0xa8 /* BRM Modulator Register */
-#define UBRC 0xac /* Baud Rate Count Register */
-#define UTS 0xb4 /* UART Test Register (mx31) */
-
-/* UART Control Register Bit Fields.*/
-#define URXD_CHARRDY (1<<15)
-#define URXD_ERR (1<<14)
-#define URXD_OVRRUN (1<<13)
-#define URXD_FRMERR (1<<12)
-#define URXD_BRK (1<<11)
-#define URXD_PRERR (1<<10)
-#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
-#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
-#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
-#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
-#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
-#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
-#define UCR1_IREN (1<<7) /* Infrared interface enable */
-#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
-#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
-#define UCR1_SNDBRK (1<<4) /* Send break */
-#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
-#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
-#define UCR1_DOZE (1<<1) /* Doze */
-#define UCR1_UARTEN (1<<0) /* UART enabled */
-#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
-#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
-#define UCR2_CTSC (1<<13) /* CTS pin control */
-#define UCR2_CTS (1<<12) /* Clear to send */
-#define UCR2_ESCEN (1<<11) /* Escape enable */
-#define UCR2_PREN (1<<8) /* Parity enable */
-#define UCR2_PROE (1<<7) /* Parity odd/even */
-#define UCR2_STPB (1<<6) /* Stop */
-#define UCR2_WS (1<<5) /* Word size */
-#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
-#define UCR2_TXEN (1<<2) /* Transmitter enabled */
-#define UCR2_RXEN (1<<1) /* Receiver enabled */
-#define UCR2_SRST (1<<0) /* SW reset */
-#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
-#define UCR3_PARERREN (1<<12) /* Parity enable */
-#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
-#define UCR3_DSR (1<<10) /* Data set ready */
-#define UCR3_DCD (1<<9) /* Data carrier detect */
-#define UCR3_RI (1<<8) /* Ring indicator */
-#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
-#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
-#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
-#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
-#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
-#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
-#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
-#define UCR3_BPEN (1<<0) /* Preset registers enable */
-#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
-#define UCR4_INVR (1<<9) /* Inverted infrared reception */
-#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
-#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
-#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
-#define UCR4_IRSC (1<<5) /* IR special case */
-#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
-#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
-#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
-#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
-#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
-#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
-#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
-#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
-#define USR1_RTSS (1<<14) /* RTS pin status */
-#define USR1_TRDY (1<<13)/* Transmitter ready interrupt/dma flag */
-#define USR1_RTSD (1<<12) /* RTS delta */
-#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
-#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
-#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
-#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
-#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
-#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
-#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
-#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
-#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
-#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
-#define USR2_IDLE (1<<12) /* Idle condition */
-#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
-#define USR2_WAKE (1<<7) /* Wake */
-#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
-#define USR2_TXDC (1<<3) /* Transmitter complete */
-#define USR2_BRCD (1<<2) /* Break condition */
-#define USR2_ORE (1<<1) /* Overrun error */
-#define USR2_RDR (1<<0) /* Recv data ready */
-#define UTS_FRCPERR (1<<13) /* Force parity error */
-#define UTS_LOOP (1<<12) /* Loop tx and rx */
-#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
-#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
-#define UTS_TXFULL (1<<4) /* TxFIFO full */
-#define UTS_RXFULL (1<<3) /* RxFIFO full */
-#define UTS_SOFTRST (1<<0) /* Software reset */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void serial_setbrg(void)
-{
- u32 clk = mxc_get_clock(MXC_UART_CLK);
-
- if (!gd->baudrate)
- gd->baudrate = CONFIG_BAUDRATE;
- __REG(UART_PHYS + UFCR) = 0x4 << 7; /* divide input clock by 2 */
- __REG(UART_PHYS + UBIR) = 0xf;
- __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
-}
-
-int serial_getc(void)
-{
- while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
- ;
- return __REG(UART_PHYS + URXD);
-}
-
-void serial_putc(const char c)
-{
- __REG(UART_PHYS + UTXD) = c;
-
- /* wait for transmitter to be ready */
- while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
- ;
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-int serial_tstc(void)
-{
- /* If receive fifo is empty, return false */
- if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
- return 0;
- return 1;
-}
-
-void serial_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init(void)
-{
- __REG(UART_PHYS + UCR1) = 0x0;
- __REG(UART_PHYS + UCR2) = 0x0;
-
- while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST))
- ;
-
- __REG(UART_PHYS + UCR3) = 0x0704;
- __REG(UART_PHYS + UCR4) = 0x8000;
- __REG(UART_PHYS + UESC) = 0x002b;
- __REG(UART_PHYS + UTIM) = 0x0;
-
- __REG(UART_PHYS + UTS) = 0x0;
-
- serial_setbrg();
-
- __REG(UART_PHYS + UCR2) =
- UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
-
- __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
-
- return 0;
-}
-
-#endif /* CONFIG_MX53_UART */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mx53.h>
-
-/* General purpose timers registers */
-#define GPTCR __REG(GPT1_BASE_ADDR) /* Control register */
-#define GPTPR __REG(GPT1_BASE_ADDR + 0x4) /* Prescaler register */
-#define GPTSR __REG(GPT1_BASE_ADDR + 0x8) /* Status register */
-#define GPTCNT __REG(GPT1_BASE_ADDR + 0x24) /* Counter register */
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR (1<<15) /* Software reset */
-#define GPTCR_FRR (1<<9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */
-#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */
-#define GPTCR_TEN (1) /* Timer enable */
-#define GPTPR_VAL (50)
-
-static inline void setup_gpt(void)
-{
- int i;
- static int init_done;
-
- if (init_done)
- return;
-
- init_done = 1;
-
- /* setup GP Timer 1 */
- GPTCR = GPTCR_SWR;
- for (i = 0; i < 100; i++)
- GPTCR = 0; /* We have no udelay by now */
- GPTPR = GPTPR_VAL; /* 50Mhz / 50 */
- /* Freerun Mode, PERCLK1 input */
- GPTCR |= GPTCR_CLKSOURCE_IPG | GPTCR_TEN;
-}
-
-int timer_init(void)
-{
- setup_gpt();
-
- return 0;
-}
-
-void reset_timer_masked(void)
-{
- GPTCR = 0;
- /* Freerun Mode, PERCLK1 input */
- GPTCR = GPTCR_CLKSOURCE_IPG | GPTCR_TEN;
-}
-
-inline ulong get_timer_masked(void)
-{
- ulong val = GPTCNT;
-
- return val;
-}
-
-void reset_timer(void)
-{
- reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
- ulong tmp;
-
- tmp = get_timer_masked();
-
- if (tmp <= (base * 1000)) {
- /* Overflow */
- tmp += (0xffffffff - base);
- }
-
- return (tmp / 1000) - base;
-}
-
-void set_timer(ulong t)
-{
-}
-
-/* delay x useconds AND perserve advance timstamp value */
-/* GPTCNT is now supposed to tick 1 by 1 us. */
-void udelay(unsigned long usec)
-{
- ulong tmp;
-
- setup_gpt();
-
- tmp = get_timer_masked(); /* get current timestamp */
-
- /* if setting this forward will roll time stamp */
- if ((usec + tmp + 1) < tmp) {
- /* reset "advancing" timestamp to 0, set lastinc value */
- reset_timer_masked();
- } else {
- /* else, set advancing stamp wake up time */
- tmp += usec;
- }
-
- while (get_timer_masked() < tmp) /* loop till event */
- /*NOP*/;
-}
COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
-COBJS-$(CONFIG_MX31_NAND) += mx31_nand.o
-COBJS-$(CONFIG_MXC_NAND) += mxc_nand.o nand_device_info.o
-COBJS-$(CONFIG_MXS_NAND) += mxs_gpmi.o
endif
COBJS := $(COBJS-y)
+++ /dev/null
-/*
- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm-arm/arch/mx31-regs.h>
-
-/*
- * Define delays in microsec for NAND device operations
- */
-#define TROP_US_DELAY 2000
-
-/*
- * Macros to get byte and bit positions of ECC
- */
-#define COLPOS(x) ((x) >> 4)
-#define BITPOS(x) ((x) & 0xf)
-
-/* Define single bit Error positions in Main & Spare area */
-#define MAIN_SINGLEBIT_ERROR 0x4
-#define SPARE_SINGLEBIT_ERROR 0x1
-
-struct nand_info {
- int oob;
- int read_status;
- int largepage;
- u16 col;
-};
-
-static struct nand_info nandinfo;
-static int ecc_disabled;
-
-/*
- * OOB placement block for use with hardware ecc generation
- */
-static struct nand_ecclayout nand_hw_eccoob_8 = {
- .eccbytes = 5,
- .eccpos = {6, 7, 8, 9, 10},
- .oobfree = {
- {0, 5},
- {11, 5}
- }
-};
-
-static struct nand_ecclayout nand_hw_eccoob_2k = {
- .eccbytes = 20,
- .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
- 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
- .oobfree = {
- {0, 5},
- {11, 10},
- {27, 10},
- {43, 10},
- {59, 5}
- }
-};
-
-/* Define some generic bad / good block scan pattern which are used
- * while scanning a device for factory marked good / bad blocks. */
-static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
-
-static struct nand_bbt_descr smallpage_memorybased = {
- .options = NAND_BBT_SCAN2NDPAGE,
- .offs = 5,
- .len = 1,
- .pattern = scan_ff_pattern
-};
-
-static struct nand_bbt_descr largepage_memorybased = {
- .options = 0,
- .offs = 0,
- .len = 2,
- .pattern = scan_ff_pattern
-};
-
-/* Generic flash bbt decriptors */
-static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
-static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
-
-static struct nand_bbt_descr bbt_main_descr = {
- .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
- | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
- .offs = 0,
- .len = 4,
- .veroffs = 4,
- .maxblocks = 4,
- .pattern = bbt_pattern
-};
-
-static struct nand_bbt_descr bbt_mirror_descr = {
- .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
- | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
- .offs = 0,
- .len = 4,
- .veroffs = 4,
- .maxblocks = 4,
- .pattern = mirror_pattern
-};
-
-/**
- * memcpy variant that copies 32 bit words. This is needed since the
- * NFC only allows 32 bit accesses. Added for U-boot.
- */
-static void *memcpy_32(void *dest, const void *src, size_t n)
-{
- u32 *dst_32 = (u32 *) dest;
- const u32 *src_32 = (u32 *) src;
-
- while (n > 0) {
- *dst_32++ = *src_32++;
- n -= 4;
- }
-
- return dest;
-}
-
-/**
- * This function polls the NANDFC to wait for the basic operation to
- * complete by checking the INT bit of config2 register.
- *
- * @param max_retries number of retry attempts (separated by 1 us)
- */
-static void wait_op_done(int max_retries)
-{
- while (max_retries-- > 0) {
- if (NFC_CONFIG2 & NFC_INT) {
- NFC_CONFIG2 &= ~NFC_INT;
- break;
- }
- udelay(1);
- }
- if (max_retries <= 0)
- MTDDEBUG(MTD_DEBUG_LEVEL0, "wait: INT not set\n");
-}
-
-/**
- * This function issues the specified command to the NAND device and
- * waits for completion.
- *
- * @param cmd command for NAND Flash
- */
-static void send_cmd(u16 cmd)
-{
- MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(0x%x)\n", cmd);
-
- NFC_FLASH_CMD = (u16) cmd;
- NFC_CONFIG2 = NFC_CMD;
-
- /* Wait for operation to complete */
- wait_op_done(TROP_US_DELAY);
-}
-
-/**
- * This function sends an address (or partial address) to the
- * NAND device. The address is used to select the source/destination for
- * a NAND command.
- *
- * @param addr address to be written to NFC.
- * @param islast 1 if this is the last address cycle for command
- */
-static void send_addr(u16 addr)
-{
- MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(0x%x %d)\n", addr);
-
- NFC_FLASH_ADDR = addr;
- NFC_CONFIG2 = NFC_ADDR;
-
- /* Wait for operation to complete */
- wait_op_done(TROP_US_DELAY);
-}
-
-/**
- * This function requests the NANDFC to initate the transfer
- * of data currently in the NANDFC RAM buffer to the NAND device.
- *
- * @param buf_id Specify Internal RAM Buffer number (0-3)
- * @param oob set to 1 if only the spare area is transferred
- */
-static void send_prog_page(u8 buf_id)
-{
- MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", nandinfo.oob);
-
- /* NANDFC buffer 0 is used for page read/write */
-
- NFC_BUF_ADDR = buf_id;
-
- /* Configure spare or page+spare access */
- if (!nandinfo.largepage) {
- if (nandinfo.oob)
- NFC_CONFIG1 |= NFC_SP_EN;
- else
- NFC_CONFIG1 &= ~NFC_SP_EN;
- }
- NFC_CONFIG2 = NFC_INPUT;
-
- /* Wait for operation to complete */
- wait_op_done(TROP_US_DELAY);
-}
-
-/**
- * This function will correct the single bit ECC error
- *
- * @param buf_id Specify Internal RAM Buffer number (0-3)
- * @param eccpos Ecc byte and bit position
- * @param oob set to 1 if only spare area needs correction
- */
-static void mxc_nd_correct_error(u8 buf_id, u16 eccpos, int oob)
-{
- u16 col;
- u8 pos;
- u16 *buf;
-
- /* Get col & bit position of error
- these macros works for both 8 & 16 bits */
- col = COLPOS(eccpos); /* Get half-word position */
- pos = BITPOS(eccpos); /* Get bit position */
-
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "mxc_nd_correct_error (col=%d pos=%d)\n", col, pos);
-
- /* Set the pointer for main / spare area */
- if (!oob)
- buf = (u16 *)(MAIN_AREA0 + col + (256 * buf_id));
- else
- buf = (u16 *)(SPARE_AREA0 + col + (8 * buf_id));
-
- /* Fix the data */
- *buf ^= 1 << pos;
-}
-
-/**
- * This function will maintains state of single bit Error
- * in Main & spare area
- *
- * @param buf_id Specify Internal RAM Buffer number (0-3)
- * @param spare set to 1 if only spare area needs correction
- */
-static void mxc_nd_correct_ecc(u8 buf_id, int spare)
-{
- u16 value, ecc_status;
-
- /* Read the ECC result */
- ecc_status = NFC_ECC_STATUS_RESULT;
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "mxc_nd_correct_ecc (Ecc status=%x)\n", ecc_status);
-
- if (((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR)
- || ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR)) {
- if (ecc_disabled) {
- if ((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR) {
- value = NFC_RSLTMAIN_AREA;
- /* Correct single bit error in Mainarea
- NFC will not correct the error in
- current page */
- mxc_nd_correct_error(buf_id, value, 0);
- }
- if ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR) {
- value = NFC_RSLTSPARE_AREA;
- /* Correct single bit error in Mainarea
- NFC will not correct the error in
- current page */
- mxc_nd_correct_error(buf_id, value, 1);
- }
-
- } else {
- /* Disable ECC */
- NFC_CONFIG1 &= ~NFC_ECC_EN;
- ecc_disabled = 1;
- }
- } else if (ecc_status == 0) {
- if (ecc_disabled) {
- /* Enable ECC */
- NFC_CONFIG1 |= NFC_ECC_EN;
- ecc_disabled = 0;
- }
- } /* else 2-bit Error. Do nothing */
-}
-
-/**
- * This function requests the NANDFC to initated the transfer
- * of data from the NAND device into in the NANDFC ram buffer.
- *
- * @param buf_id Specify Internal RAM Buffer number (0-3)
- * @param oob set 1 if only the spare area is
- * transferred
- */
-static void send_read_page(u8 buf_id)
-{
- MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", nandinfo.oob);
-
- /* NANDFC buffer 0 is used for page read/write */
- NFC_BUF_ADDR = buf_id;
-
- /* Configure spare or page+spare access */
- if (!nandinfo.largepage) {
- if (nandinfo.oob)
- NFC_CONFIG1 |= NFC_SP_EN;
- else
- NFC_CONFIG1 &= ~NFC_SP_EN;
- }
-
- NFC_CONFIG2 = NFC_OUTPUT;
-
- /* Wait for operation to complete */
- wait_op_done(TROP_US_DELAY);
-
- /* If there are single bit errors in
- two consecutive page reads then
- the error is not corrected by the
- NFC for the second page.
- Correct single bit error in driver */
-
- mxc_nd_correct_ecc(buf_id, nandinfo.oob);
-}
-
-/**
- * This function requests the NANDFC to perform a read of the
- * NAND device ID.
- */
-static void send_read_id(void)
-{
- /* NANDFC buffer 0 is used for device ID output */
- NFC_BUF_ADDR = 0x0;
-
- /* Read ID into main buffer */
- NFC_CONFIG1 &= ~NFC_SP_EN;
- NFC_CONFIG2 = NFC_ID;
-
- /* Wait for operation to complete */
- wait_op_done(TROP_US_DELAY);
-}
-
-/**
- * This function requests the NANDFC to perform a read of the
- * NAND device status and returns the current status.
- *
- * @return device status
- */
-static u16 get_dev_status(void)
-{
- volatile u16 *mainbuf = MAIN_AREA1;
- u32 store;
- u16 ret;
- /* Issue status request to NAND device */
-
- /* store the main area1 first word, later do recovery */
- store = *((u32 *) mainbuf);
- /*
- * NANDFC buffer 1 is used for device status to prevent
- * corruption of read/write buffer on status requests.
- */
- NFC_BUF_ADDR = 1;
-
- /* Read status into main buffer */
- NFC_CONFIG1 &= ~NFC_SP_EN;
- NFC_CONFIG2 = NFC_STATUS;
-
- /* Wait for operation to complete */
- wait_op_done(TROP_US_DELAY);
-
- /* Status is placed in first word of main buffer */
- /* get status, then recovery area 1 data */
- ret = mainbuf[0];
- *((u32 *) mainbuf) = store;
-
- return ret;
-}
-
-static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
-{
- /*
- * If HW ECC is enabled, we turn it on during init. There is
- * no need to enable again here.
- */
-}
-
-static int mxc_nand_correct_data(struct mtd_info *mtd, unsigned char *dat,
- unsigned char *read_ecc, unsigned char *calc_ecc)
-{
- /*
- * 1-Bit errors are automatically corrected in HW. No need for
- * additional correction. 2-Bit errors cannot be corrected by
- * HW ECC, so we need to return failure
- */
- u16 ecc_status = NFC_ECC_STATUS_RESULT;
-
- if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
- MTDDEBUG(MTD_DEBUG_LEVEL0,
- "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
- return -1;
- }
-
- return 0;
-}
-
-static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const unsigned char *dat,
- unsigned char *ecc_code)
-{
- /*
- * Just return success. HW ECC does not read/write the NFC spare
- * buffer. Only the FLASH spare area contains the calcuated ECC.
- */
- return 0;
-}
-
-/**
- * This function reads byte from the NAND Flash
- *
- * @param mtd MTD structure for the NAND Flash
- *
- * @return data read from the NAND Flash
- */
-static unsigned char mxc_nand_read_byte(struct mtd_info *mtd)
-{
- unsigned char ret_val = 0;
- u16 col, rd_word;
- volatile u16 *mainbuf = MAIN_AREA0;
- volatile u16 *sparebuf = SPARE_AREA0;
-
- /* Check for status request */
- if (nandinfo.read_status)
- return get_dev_status() & 0xFF;
-
- /* Get column for 16-bit access */
- col = nandinfo.col >> 1;
-
- /* If we are accessing the spare region */
- if (nandinfo.oob)
- rd_word = sparebuf[col];
- else
- rd_word = mainbuf[col];
-
- /* Pick upper/lower byte of word from RAM buffer */
- if (nandinfo.col & 0x1)
- ret_val = (rd_word >> 8) & 0xFF;
- else
- ret_val = rd_word & 0xFF;
-
- /* Update saved column address */
- nandinfo.col++;
-
- return ret_val;
-}
-
-/**
- * This function reads word from the NAND Flash
- *
- * @param mtd MTD structure for the NAND Flash
- *
- * @return data read from the NAND Flash
- */
-static u16 mxc_nand_read_word(struct mtd_info *mtd)
-{
- u16 col;
- u16 rd_word, ret_val;
- volatile u16 *p;
-
- MTDDEBUG(MTD_DEBUG_LEVEL3, "mxc_nand_read_word(col = %d)\n", nandinfo.col);
-
- col = nandinfo.col;
- /* Adjust saved column address */
- if (col < mtd->writesize && nandinfo.oob)
- col += mtd->writesize;
-
- if (col < mtd->writesize)
- p = (MAIN_AREA0) + (col >> 1);
- else
- p = (SPARE_AREA0) + ((col - mtd->writesize) >> 1);
-
- if (col & 1) {
- rd_word = *p;
- ret_val = (rd_word >> 8) & 0xff;
- rd_word = *(p + 1);
- ret_val |= (rd_word << 8) & 0xff00;
-
- } else
- ret_val = *p;
-
- /* Update saved column address */
- nandinfo.col = col + 2;
-
- return ret_val;
-}
-
-/**
- * This function writes data of length \b len to buffer \b buf. The data
- * to be written on NAND Flash is first copied to RAMbuffer. After the
- * Data Input Operation by the NFC, the data is written to NAND Flash.
- *
- * @param mtd MTD structure for the NAND Flash
- * @param buf data to be written to NAND Flash
- * @param len number of bytes to be written
- */
-static void mxc_nand_write_buf(struct mtd_info *mtd,
- const unsigned char *buf, int len)
-{
- int n;
- int col;
- int i = 0;
-
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "mxc_nand_write_buf(col = %d, len = %d)\n", nandinfo.col, len);
-
- col = nandinfo.col;
-
- /* Adjust saved column address */
- if (col < mtd->writesize && nandinfo.oob)
- col += mtd->writesize;
-
- n = mtd->writesize + mtd->oobsize - col;
- if (len > mtd->writesize + mtd->oobsize - col)
- MTDDEBUG(MTD_DEBUG_LEVEL1, "Error: too much data.\n");
-
- n = min(len, n);
-
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "%s:%d: col = %d, n = %d\n", __FUNCTION__, __LINE__, col, n);
-
- while (n) {
- volatile u32 *p;
- if (col < mtd->writesize)
- p = (volatile u32 *)((ulong) (MAIN_AREA0) + (col & ~3));
- else
- p = (volatile u32 *)((ulong) (SPARE_AREA0) -
- mtd->writesize + (col & ~3));
-
- MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n",
- __FUNCTION__, __LINE__, p);
-
- if (((col | (int)&buf[i]) & 3) || n < 16) {
- u32 data = 0;
-
- if (col & 3 || n < 4)
- data = *p;
-
- switch (col & 3) {
- case 0:
- if (n) {
- data = (data & 0xffffff00) |
- (buf[i++] << 0);
- n--;
- col++;
- }
- case 1:
- if (n) {
- data = (data & 0xffff00ff) |
- (buf[i++] << 8);
- n--;
- col++;
- }
- case 2:
- if (n) {
- data = (data & 0xff00ffff) |
- (buf[i++] << 16);
- n--;
- col++;
- }
- case 3:
- if (n) {
- data = (data & 0x00ffffff) |
- (buf[i++] << 24);
- n--;
- col++;
- }
- }
-
- *p = data;
- } else {
- int m = mtd->writesize - col;
-
- if (col >= mtd->writesize)
- m += mtd->oobsize;
-
- m = min(n, m) & ~3;
-
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
- __FUNCTION__, __LINE__, n, m, i, col);
-
- memcpy_32((void *)(p), &buf[i], m);
- col += m;
- i += m;
- n -= m;
- }
- }
- /* Update saved column address */
- nandinfo.col = col;
-}
-
-/**
- * This function id is used to read the data buffer from the NAND Flash. To
- * read the data from NAND Flash first the data output cycle is initiated by
- * the NFC, which copies the data to RAMbuffer. This data of length \b len is
- * then copied to buffer \b buf.
- *
- * @param mtd MTD structure for the NAND Flash
- * @param buf data to be read from NAND Flash
- * @param len number of bytes to be read
- */
-static void mxc_nand_read_buf(struct mtd_info *mtd, unsigned char *buf, int len)
-{
- int n;
- int col;
- int i = 0;
-
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "mxc_nand_read_buf(col = %d, len = %d)\n", nandinfo.col, len);
-
- col = nandinfo.col;
- /**
- * Adjust saved column address
- * for nand_read_oob will pass col within oobsize
- */
- if (col < mtd->writesize && nandinfo.oob)
- col += mtd->writesize;
-
- n = mtd->writesize + mtd->oobsize - col;
- n = min(len, n);
-
- while (n) {
- volatile u32 *p;
-
- if (col < mtd->writesize)
- p = (volatile u32 *)((ulong) (MAIN_AREA0) + (col & ~3));
- else
- p = (volatile u32 *)((ulong) (SPARE_AREA0) -
- mtd->writesize + (col & ~3));
-
- if (((col | (int)&buf[i]) & 3) || n < 16) {
- u32 data;
-
- data = *p;
- switch (col & 3) {
- case 0:
- if (n) {
- buf[i++] = (u8) (data);
- n--;
- col++;
- }
- case 1:
- if (n) {
- buf[i++] = (u8) (data >> 8);
- n--;
- col++;
- }
- case 2:
- if (n) {
- buf[i++] = (u8) (data >> 16);
- n--;
- col++;
- }
- case 3:
- if (n) {
- buf[i++] = (u8) (data >> 24);
- n--;
- col++;
- }
- }
- } else {
- int m = mtd->writesize - col;
-
- if (col >= mtd->writesize)
- m += mtd->oobsize;
-
- m = min(n, m) & ~3;
- memcpy_32(&buf[i], (void *)(p), m);
- col += m;
- i += m;
- n -= m;
- }
- }
- /* Update saved column address */
- nandinfo.col = col;
-}
-
-/**
- * This function is used by the upper layer to verify the data in NAND Flash
- * with the data in the \b buf.
- *
- * @param mtd MTD structure for the NAND Flash
- * @param buf data to be verified
- * @param len length of the data to be verified
- *
- * @return -EFAULT if error else 0
- */
-static int
-mxc_nand_verify_buf(struct mtd_info *mtd, const unsigned char *buf, int len)
-{
- return -1; /* Was -EFAULT */
-}
-
-/**
- * This function is used by upper layer for select and deselect of the NAND
- * chip.
- *
- * @param mtd MTD structure for the NAND Flash
- * @param chip val indicating select or deselect
- */
-static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
-{
-}
-
-/**
- * This function is used by the upper layer to write command to NAND Flash
- * for different operations to be carried out on NAND Flash
- *
- * @param mtd MTD structure for the NAND Flash
- * @param command command for NAND Flash
- * @param column column offset for the page read
- * @param page_addr page to be read from NAND Flash
- */
-static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
- int column, int page_addr)
-{
- MTDDEBUG(MTD_DEBUG_LEVEL3,
- "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
- command, column, page_addr);
-
- /* Reset command state information */
- nandinfo.read_status = 0;
- nandinfo.oob = 0;
-
- /* Command pre-processing step */
- switch (command) {
-
- case NAND_CMD_STATUS:
- nandinfo.col = 0;
- nandinfo.read_status = 1;
- break;
-
- case NAND_CMD_READ0:
- nandinfo.col = column;
- break;
-
- case NAND_CMD_READOOB:
- nandinfo.col = column;
- nandinfo.oob = 1;
- if (nandinfo.largepage)
- command = NAND_CMD_READ0;
- break;
-
- case NAND_CMD_SEQIN:
- if (column >= mtd->writesize) {
- /* write oob routine caller */
- if (nandinfo.largepage) {
- /*
- * FIXME: before send SEQIN command for
- * write OOB, we must read one page out.
- * For 2K nand has no READ1 command to set
- * current HW pointer to spare area, we must
- * write the whole page including OOB together.
- */
- /* call itself to read a page */
- mxc_nand_command(mtd, NAND_CMD_READ0, 0,
- page_addr);
- }
- nandinfo.col = column - mtd->writesize;
- nandinfo.oob = 1;
- /* Set program pointer to spare region */
- if (!nandinfo.largepage)
- send_cmd(NAND_CMD_READOOB);
- } else {
- nandinfo.oob = 0;
- nandinfo.col = column;
- /* Set program pointer to page start */
- if (!nandinfo.largepage)
- send_cmd(NAND_CMD_READ0);
- }
- break;
-
- case NAND_CMD_PAGEPROG:
- if (ecc_disabled) {
- /* Enable Ecc for page writes */
- NFC_CONFIG1 |= NFC_ECC_EN;
- }
- send_prog_page(0);
-
- if (nandinfo.largepage) {
- /* data in 4 areas datas */
- send_prog_page(1);
- send_prog_page(2);
- send_prog_page(3);
- }
-
- break;
-
- case NAND_CMD_ERASE1:
- break;
- }
-
- /*
- * Write out the command to the device.
- */
- send_cmd(command);
-
- /*
- * Write out column address, if necessary
- */
- if (column != -1) {
- /*
- * MXC NANDFC can only perform full page+spare or
- * spare-only read/write. When the upper layers
- * layers perform a read/write buf operation,
- * we will used the saved column adress to index into
- * the full page.
- */
- send_addr(0);
- if (nandinfo.largepage)
- /* another col addr cycle for 2k page */
- send_addr(0);
- }
-
- /*
- * Write out page address, if necessary
- */
- if (page_addr != -1) {
- /* paddr_0 - p_addr_7 */
- send_addr((page_addr & 0xff));
-
- if (nandinfo.largepage) {
- /* One more address cycle for higher
- * density devices */
-
- if (mtd->size >= 0x10000000) {
- /* paddr_8 - paddr_15 */
- send_addr((page_addr >> 8) & 0xff);
- send_addr((page_addr >> 16) & 0xff);
- } else
- /* paddr_8 - paddr_15 */
- send_addr((page_addr >> 8) & 0xff);
- } else {
- /* One more address cycle for higher
- * density devices */
-
- if (mtd->size >= 0x4000000) {
- /* paddr_8 - paddr_15 */
- send_addr((page_addr >> 8) & 0xff);
- send_addr((page_addr >> 16) & 0xff);
- } else
- /* paddr_8 - paddr_15 */
- send_addr((page_addr >> 8) & 0xff);
- }
- }
-
- /*
- * Command post-processing step
- */
- switch (command) {
-
- case NAND_CMD_RESET:
- break;
-
- case NAND_CMD_READOOB:
- case NAND_CMD_READ0:
- if (nandinfo.largepage) {
- /* send read confirm command */
- send_cmd(NAND_CMD_READSTART);
- /* read for each AREA */
- send_read_page(0);
- send_read_page(1);
- send_read_page(2);
- send_read_page(3);
- } else
- send_read_page(0);
- break;
-
- case NAND_CMD_READID:
- send_read_id();
- nandinfo.col = column;
- break;
-
- case NAND_CMD_PAGEPROG:
- if (ecc_disabled) {
- /* Disable Ecc after page writes */
- NFC_CONFIG1 &= ~NFC_ECC_EN;
- }
- break;
-
- case NAND_CMD_ERASE2:
- break;
- }
-}
-
-static int mxc_nand_scan_bbt(struct mtd_info *mtd)
-{
- struct nand_chip *this = mtd->priv;
-
- /* Config before scanning */
- /* Do not rely on NFMS_BIT, set/clear NFMS bit based
- * on mtd->writesize */
- if (mtd->writesize == 2048)
- NFMS |= 1 << NFMS_BIT;
- else if ((NFMS >> NFMS_BIT) & 0x1)
- NFMS &= ~(1 << NFMS_BIT);
-
- /* use flash based bbt */
- this->bbt_td = &bbt_main_descr;
- this->bbt_md = &bbt_mirror_descr;
-
- /* update flash based bbt */
- this->options |= NAND_USE_FLASH_BBT;
-
- if (!this->badblock_pattern) {
- if (nandinfo.largepage)
- this->badblock_pattern = &smallpage_memorybased;
- else
- this->badblock_pattern = (mtd->writesize > 512) ?
- &largepage_memorybased : &smallpage_memorybased;
- }
- /* Build bad block table */
- return nand_scan_bbt(mtd, this->badblock_pattern);
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- nand->chip_delay = 0;
-
- nand->cmdfunc = mxc_nand_command;
- nand->select_chip = mxc_nand_select_chip;
- nand->read_byte = mxc_nand_read_byte;
- nand->read_word = mxc_nand_read_word;
- nand->write_buf = mxc_nand_write_buf;
- nand->read_buf = mxc_nand_read_buf;
- nand->verify_buf = mxc_nand_verify_buf;
- nand->scan_bbt = mxc_nand_scan_bbt;
- nand->ecc.calculate = mxc_nand_calculate_ecc;
- nand->ecc.correct = mxc_nand_correct_data;
- nand->ecc.hwctl = mxc_nand_enable_hwecc;
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.bytes = 3;
- nand->ecc.size = 512;
-
- /* Reset NAND */
- NFC_CONFIG1 |= NFC_INT_MSK | NFC_RST | NFC_ECC_EN;
-
- /* Unlock the internal RAM buffer */
- NFC_CONFIG = 0x2;
-
- /* Block to be unlocked */
- NFC_UNLOCKSTART_BLKADDR = 0x0;
- NFC_UNLOCKEND_BLKADDR = 0x4000;
-
- /* Unlock Block Command for given address range */
- NFC_WRPROT = 0x4;
-
- /* Only 8 bit bus support for now */
- nand->options |= 0;
-
- if ((NFMS >> NFMS_BIT) & 1) {
- nandinfo.largepage = 1;
- nand->ecc.layout = &nand_hw_eccoob_2k;
- } else {
- nandinfo.largepage = 0;
- nand->ecc.layout = &nand_hw_eccoob_8;
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * Freescale GPMI NFC NAND Flash Driver
- *
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- * Copyright (C) 2008 Embedded Alley Solutions, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <watchdog.h>
-#include <linux/err.h>
-#include <linux/mtd/compat.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ecc.h>
-
-#ifdef CONFIG_MTD_PARTITIONS
-#include <linux/mtd/partitions.h>
-#endif
-
-#include <asm/sizes.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/dma-mapping.h>
-#include <asm/arch/mx28.h>
-
-#ifdef CONFIG_JFFS2_NAND
-#include <jffs2/jffs2.h>
-#endif
-
-#include <asm/arch/regs-clkctrl.h>
-#include <asm/arch/mxs_gpmi-regs.h>
-#include <asm/arch/mxs_gpmi-bch-regs.h>
-
-#ifdef _DEBUG
-static int debug = 1;
-#define dbg_lvl(l) (debug > (l))
-#define DBG(l, fmt...) do { if (dbg_lvl(l)) printk(KERN_DEBUG fmt); } while (0)
-#else
-#define dbg_lvl(n) 0
-#define DBG(l, fmt...) do { } while (0)
-#endif
-
-#define dma_timeout 1000
-#define create_bbt 1
-
-#define MAX_CHIP_COUNT CONFIG_SYS_MAX_NAND_DEVICE
-#define COMMAND_BUFFER_SIZE 10
-#define MAX_PIO_WORDS 16
-
-/* dmaengine interface */
-enum dma_status {
- DMA_SUCCESS,
- DMA_IN_PROGRESS,
- DMA_PAUSED,
- DMA_ERROR,
-};
-
-/* MXS APBH DMA controller interface */
-#define HW_APBHX_CTRL0 0x000
-#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
-#define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
-#define BP_APBH_CTRL0_CLKGATE_CHANNEL 8
-#define BP_APBH_CTRL0_RESET_CHANNEL 16
-#define HW_APBHX_CTRL1 0x010
-#define HW_APBHX_CTRL2 0x020
-#define HW_APBHX_CHANNEL_CTRL 0x030
-#define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
-#define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800)
-#define HW_APBX_VERSION 0x800
-#define BP_APBHX_VERSION_MAJOR 24
-#define HW_APBHX_CHn_NXTCMDAR(n) (0x110 + (n) * 0x70)
-#define HW_APBHX_CHn_SEMA(n) (0x140 + (n) * 0x70)
-
-/*
- * ccw bits definitions
- *
- * COMMAND: 0..1 (2)
- * CHAIN: 2 (1)
- * IRQ: 3 (1)
- * NAND_LOCK: 4 (1) - not implemented
- * NAND_WAIT4READY: 5 (1) - not implemented
- * DEC_SEM: 6 (1)
- * WAIT4END: 7 (1)
- * HALT_ON_TERMINATE: 8 (1)
- * TERMINATE_FLUSH: 9 (1)
- * RESERVED: 10..11 (2)
- * PIO_NUM: 12..15 (4)
- */
-#define BP_CCW_COMMAND 0
-#define BM_CCW_COMMAND (3 << 0)
-#define CCW_CHAIN (1 << 2)
-#define CCW_IRQ (1 << 3)
-#define CCW_DEC_SEM (1 << 6)
-#define CCW_WAIT4END (1 << 7)
-#define CCW_HALT_ON_TERM (1 << 8)
-#define CCW_TERM_FLUSH (1 << 9)
-#define BP_CCW_PIO_NUM 12
-#define BM_CCW_PIO_NUM (0xf << 12)
-
-#define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
-
-#define MXS_DMA_CMD_NO_XFER 0
-#define MXS_DMA_CMD_WRITE 1
-#define MXS_DMA_CMD_READ 2
-#define MXS_DMA_CMD_DMA_SENSE 3
-
-struct mxs_dma_ccw {
- u32 next;
- u16 bits;
- u16 xfer_bytes;
-#define MAX_XFER_BYTES 0xff00
- u32 bufaddr;
-#define MXS_PIO_WORDS 16
- u32 pio_words[MXS_PIO_WORDS];
-};
-
-#define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw))
-
-struct mxs_dma_chan {
- struct mxs_dma_engine *mxs_dma;
- int chan_id;
- struct mxs_dma_ccw *ccw;
- int ccw_idx;
- unsigned long ccw_phys;
- enum dma_status status;
-#define MXS_DMA_SG_LOOP (1 << 0)
-};
-
-#define MXS_DMA_CHANNELS 16
-#define MXS_DMA_CHANNELS_MASK 0xffff
-
-struct mxs_dma_engine {
- int dev_id;
- void __iomem *base;
- struct mxs_dma_chan mxs_chans[MAX_CHIP_COUNT];
-};
-
-struct mxs_gpmi {
- struct mxs_dma_engine mxs_dma;
- void __iomem *gpmi_regs;
- void __iomem *bch_regs;
- void __iomem *dma_regs;
-
- unsigned int chip_count;
-
- struct mtd_partition *parts;
- unsigned int nr_parts;
- struct mtd_info *mtd;
- struct nand_chip *chip;
- struct nand_ecclayout ecc_layout;
-
- int current_chip;
-
- void *page_buf;
- void *oob_buf;
- void *data_buf;
-
- int command_length;
- u32 pio_data[MAX_PIO_WORDS];
- u8 cmd_buf[COMMAND_BUFFER_SIZE];
-
- unsigned block0_ecc_strength:5,
- blockn_ecc_strength:5,
- swap_block_mark:1,
- block_mark_bit_offset:3,
- block_mark_byte_offset:14;
-};
-
-static uint8_t scan_ff_pattern[] = { 0xff };
-static struct nand_bbt_descr gpmi_bbt_descr = {
- .options = 0,
- .offs = 0,
- .len = 1,
- .pattern = scan_ff_pattern
-};
-
-static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
-static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
-
-static struct nand_bbt_descr mxs_gpmi_bbt_main_descr = {
- .options = NAND_BBT_LASTBLOCK | NAND_BBT_2BIT |
- NAND_BBT_VERSION | NAND_BBT_PERCHIP |
- NAND_BBT_NO_OOB,
- .offs = 0,
- .len = 4,
- .veroffs = 4,
- .maxblocks = 4,
- .pattern = bbt_pattern,
-};
-
-static struct nand_bbt_descr mxs_gpmi_bbt_mirror_descr = {
- .options = NAND_BBT_LASTBLOCK | NAND_BBT_2BIT |
- NAND_BBT_VERSION | NAND_BBT_PERCHIP |
- NAND_BBT_NO_OOB,
- .offs = 0,
- .len = 4,
- .veroffs = 4,
- .maxblocks = 4,
- .pattern = mirror_pattern,
-};
-
-/* MXS DMA implementation */
-#ifdef _DEBUG
-static inline u32 __mxs_dma_readl(struct mxs_dma_engine *mxs_dma,
- unsigned int reg,
- const char *name, const char *fn, int ln)
-{
- u32 val;
- void __iomem *addr = mxs_dma->base + reg;
-
- val = readl(addr);
- DBG(3, "%s@%d: Read %08x from %s[%08x]\n", fn, ln, val, name,
- APBHDMA_BASE_ADDR + reg);
- return val;
-}
-#define mxs_dma_readl(t, r) __mxs_dma_readl(t, r, #r, __func__, __LINE__)
-
-static inline void __mxs_dma_writel(u32 val,
- struct mxs_dma_engine *mxs_dma, unsigned int reg,
- const char *name, const char *fn, int ln)
-{
- void __iomem *addr = mxs_dma->base + reg;
-
- DBG(3, "%s@%d: Writing %08x to %s[%08x]\n", fn, ln, val, name,
- APBHDMA_BASE_ADDR + reg);
- writel(val, addr);
-}
-#define mxs_dma_writel(v, t, r) __mxs_dma_writel(v, t, r, #r, __func__, __LINE__)
-#else
-static inline u32 mxs_dma_readl(struct mxs_dma_engine *mxs_dma,
- unsigned int reg)
-{
- BUG_ON(mxs_dma->base == NULL);
- return readl(mxs_dma->base + reg);
-}
-
-static inline void mxs_dma_writel(u32 val, struct mxs_dma_engine *mxs_dma,
- unsigned int reg)
-{
- BUG_ON(mxs_dma->base == NULL);
- writel(val, mxs_dma->base + reg);
-}
-#endif
-
-static inline void mxs_dma_clkgate(struct mxs_dma_chan *mxs_chan, int enable)
-{
- struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
- int chan_id = mxs_chan->chan_id;
- int set_clr = enable ? MXS_CLR_ADDR : MXS_SET_ADDR;
-
- /* enable apbh channel clock */
- mxs_dma_writel(1 << chan_id,
- mxs_dma, HW_APBHX_CTRL0 + set_clr);
-}
-
-static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
-{
- struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
- int chan_id = mxs_chan->chan_id;
-
- mxs_dma_writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
- mxs_dma, HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
-}
-
-static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
-{
- struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
- int chan_id = mxs_chan->chan_id;
-
- /* clkgate needs to be enabled before writing other registers */
- mxs_dma_clkgate(mxs_chan, 1);
-
- /* set cmd_addr up */
- mxs_dma_writel(mxs_chan->ccw_phys,
- mxs_dma, HW_APBHX_CHn_NXTCMDAR(chan_id));
-
- /* write 1 to SEMA to kick off the channel */
- mxs_dma_writel(1, mxs_dma, HW_APBHX_CHn_SEMA(chan_id));
-}
-
-static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan)
-{
- /* disable apbh channel clock */
- mxs_dma_clkgate(mxs_chan, 0);
-
- mxs_chan->status = DMA_SUCCESS;
-}
-
-#ifdef _DEBUG
-static inline u32 __mxs_gpmi_readl(struct mxs_gpmi *gpmi,
- unsigned int reg,
- const char *name, const char *fn, int ln)
-{
- u32 val;
- void __iomem *addr = gpmi->gpmi_regs + reg;
-
- val = readl(addr);
- DBG(3, "%s@%d: Read %08x from %s[%08x]\n", fn, ln, val, name,
- GPMI_BASE_ADDR + reg);
- return val;
-}
-#define mxs_gpmi_readl(t, r) __mxs_gpmi_readl(t, r, #r, __func__, __LINE__)
-
-static inline void __mxs_gpmi_writel(u32 val,
- struct mxs_gpmi *gpmi, unsigned int reg,
- const char *name, const char *fn, int ln)
-{
- void __iomem *addr = gpmi->gpmi_regs + reg;
-
- DBG(3, "%s@%d: Writing %08x to %s[%08x]\n", fn, ln, val, name,
- GPMI_BASE_ADDR + reg);
- writel(val, addr);
-}
-#define mxs_gpmi_writel(v, t, r) __mxs_gpmi_writel(v, t, r, #r, __func__, __LINE__)
-
-static inline u32 __mxs_bch_readl(struct mxs_gpmi *gpmi,
- unsigned int reg, const char *name,
- const char *fn, int ln)
-{
- u32 val;
- void __iomem *addr = gpmi->bch_regs + reg;
-
- val = readl(addr);
- DBG(3, "%s@%d: Read %08x from %s[%08x]\n", fn, ln, val, name,
- BCH_BASE_ADDR + reg);
- return val;
-}
-#define mxs_bch_readl(t, r) __mxs_bch_readl(t, r, #r, __func__, __LINE__)
-
-static inline void __mxs_bch_writel(u32 val,
- struct mxs_gpmi *gpmi, unsigned int reg,
- const char *name, const char *fn, int ln)
-{
- void __iomem *addr = gpmi->bch_regs + reg;
-
- DBG(3, "%s@%d: Writing %08x to %s[%08x]\n", fn, ln, val, name,
- BCH_BASE_ADDR + reg);
- writel(val, addr);
-}
-#define mxs_bch_writel(v, t, r) __mxs_bch_writel(v, t, r, #r, __func__, __LINE__)
-#else
-static inline u32 mxs_gpmi_readl(struct mxs_gpmi *gpmi, unsigned int reg)
-{
- return readl(gpmi->gpmi_regs + reg);
-}
-
-static inline void mxs_gpmi_writel(u32 val,
- struct mxs_gpmi *gpmi, unsigned int reg)
-{
- writel(val, gpmi->gpmi_regs + reg);
-}
-
-static inline u32 mxs_bch_readl(struct mxs_gpmi *gpmi, unsigned int reg)
-{
- return readl(gpmi->bch_regs + reg);
-}
-
-static inline void mxs_bch_writel(u32 val,
- struct mxs_gpmi *gpmi, unsigned int reg)
-{
- writel(val, gpmi->bch_regs + reg);
-}
-#endif
-
-static inline struct mxs_dma_chan *mxs_gpmi_dma_chan(struct mxs_gpmi *gpmi,
- unsigned int dma_channel)
-{
- BUG_ON(dma_channel >= ARRAY_SIZE(gpmi->mxs_dma.mxs_chans));
- DBG(3, "%s: DMA chan[%d]=%p[%d]\n", __func__,
- dma_channel, &gpmi->mxs_dma.mxs_chans[dma_channel],
- gpmi->mxs_dma.mxs_chans[dma_channel].chan_id);
- return &gpmi->mxs_dma.mxs_chans[dma_channel];
-}
-
-#define DUMP_DMA_CONTEXT
-
-static int first = 1;
-#ifdef DUMP_DMA_CONTEXT
-
-#define APBH_DMA_PHYS_ADDR (MXS_IO_BASE_ADDR + 0x004000)
-
-static void dump_dma_context(struct mxs_gpmi *gpmi, const char *title)
-{
- void *q;
- u32 *p;
- unsigned int i;
-
- if (!dbg_lvl(3))
- return;
-
- DBG(0, "%s: %s\n", __func__, title);
-
- DBG(0, "%s: GPMI:\n", __func__);
- {
- void __iomem *GPMI = gpmi->gpmi_regs;
- static u32 old[13];
-
- p = q = GPMI;
-
- for (i = 0; i < ARRAY_SIZE(old); i++) {
- u32 val = readl(gpmi->gpmi_regs + i * 0x10);
-
- if (first || val != old[i]) {
- if (first)
- DBG(0, " [%p] 0x%08x\n",
- p, val);
- else
- DBG(0, " [%p] 0x%08x -> 0x%08x\n",
- p, old[i], val);
- old[i] = val;
- }
- q += 0x10;
- p = q;
- }
- }
-
- DBG(0, "%s: BCH:\n", __func__);
- {
- void *BCH = gpmi->bch_regs;
- static u32 old[22];
-
- p = q = BCH;
-
- for (i = 0; i < ARRAY_SIZE(old); i++) {
- u32 val = readl(gpmi->bch_regs + i * 0x10);
-
- if (first || val != old[i]) {
- if (first)
- DBG(0, " [%p] 0x%08x\n",
- q, val);
- else
- DBG(0, " [%p] 0x%08x -> 0x%08x\n",
- q, old[i], val);
- old[i] = val;
- }
- q += 0x10;
- p = q;
- }
- }
-
- DBG(0, "%s: APBH:\n", __func__);
- {
- void *APBH = gpmi->dma_regs;
- static u32 old[7];
- static u32 chan[16][7];
-
- p = q = APBH;
-
- for (i = 0; i < ARRAY_SIZE(old); i++) {
- u32 val = readl(gpmi->dma_regs + i * 0x10);
-
- if (first || val != old[i]) {
- if (first)
- DBG(0, " [%p] 0x%08x\n",
- q, val);
- else
- DBG(0, " [%p] 0x%08x -> 0x%08x\n",
- q, old[i], val);
- old[i] = val;
- }
- q += 0x10;
- p = q;
- }
- for (i = 0; i < ARRAY_SIZE(chan); i++) {
- int j;
-
- printk("CHAN %2d:\n", i);
- for (j = 0; j < ARRAY_SIZE(chan[i]); j++) {
- u32 val;
-
- p = q = APBH + 0x100 + i * 0x70 + j * 0x10;
-
- val = readl(gpmi->dma_regs + 0x100 + i * 0x70 + j * 0x10);
-
- if (first || val != chan[i][j]) {
- if (first)
- DBG(0, " [%p] 0x%08x\n",
- q, val);
- else
- DBG(0, " [%p] 0x%08x -> 0x%08x\n",
- q, chan[i][j], val);
- chan[i][j] = val;
- }
- q += 0x10;
- p = q;
- }
- }
- }
- first = 0;
-}
-#else
-static inline void dump_dma_context(struct mxs_gpmi *gpmi, char *title)
-{
-}
-#endif
-
-static int mxs_gpmi_init_hw(struct mxs_gpmi *gpmi)
-{
- dump_dma_context(gpmi, "BEFORE INIT");
-
- if (mxs_gpmi_readl(gpmi, HW_GPMI_CTRL0) & 0xc0000000) {
- DBG(0, "%s: Resetting GPMI\n", __func__);
- mxs_reset_block(gpmi->gpmi_regs);
- }
-
- mxs_gpmi_writel(BM_GPMI_CTRL1_GPMI_MODE, gpmi, HW_GPMI_CTRL1_CLR);
- mxs_gpmi_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
- gpmi, HW_GPMI_CTRL1_SET);
-
- /* Disable write protection and Select BCH ECC */
- mxs_gpmi_writel(BM_GPMI_CTRL1_DEV_RESET | BM_GPMI_CTRL1_BCH_MODE,
- gpmi, HW_GPMI_CTRL1_SET);
-
- /* Select BCH ECC. */
- mxs_gpmi_writel(BM_GPMI_CTRL1_BCH_MODE,
- gpmi, HW_GPMI_CTRL1_SET);
-
- dump_dma_context(gpmi, "AFTER INIT");
- return 0;
-}
-
-static int mxs_dma_chan_init(struct mxs_dma_chan *mxs_chan, int chan_id)
-{
- mxs_chan->ccw = dma_alloc_coherent(PAGE_SIZE, &mxs_chan->ccw_phys);
- if (mxs_chan->ccw == NULL)
- return -ENOMEM;
-
- DBG(0, "%s: mxs_chan[%d]=%p ccw=%p\n", __func__,
- chan_id, mxs_chan, mxs_chan->ccw);
-
- memset(mxs_chan->ccw, 0, PAGE_SIZE);
- mxs_chan->chan_id = chan_id;
-
- mxs_dma_clkgate(mxs_chan, 1);
- mxs_dma_reset_chan(mxs_chan);
- mxs_dma_clkgate(mxs_chan, 0);
- return 0;
-}
-
-static int mxs_dma_init(struct mxs_gpmi *gpmi, int dma_chan,
- int num_dma_channels)
-{
- int ret;
- struct mxs_dma_engine *mxs_dma = &gpmi->mxs_dma;
- int i;
-
- writel(readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI) & ~BM_CLKCTRL_GPMI_CLKGATE,
- CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
-
- mxs_dma->base = gpmi->dma_regs;
-
- ret = mxs_reset_block(mxs_dma->base);
- if (ret) {
- printk(KERN_ERR "%s: Failed to reset APBH DMA controller\n", __func__);
- return ret;
- }
-
- mxs_dma_writel(BM_APBH_CTRL0_APB_BURST_EN,
- mxs_dma, HW_APBHX_CTRL0 + MXS_SET_ADDR);
- mxs_dma_writel(BM_APBH_CTRL0_APB_BURST8_EN,
- mxs_dma, HW_APBHX_CTRL0 + MXS_SET_ADDR);
-
- for (i = 0; i < num_dma_channels; i++) {
- struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];
-
- mxs_chan->mxs_dma = mxs_dma;
- ret = mxs_dma_chan_init(mxs_chan, dma_chan + i);
- if (ret)
- return ret;
- }
- return 0;
-}
-
-static int mxs_dma_prep_slave(struct mxs_dma_chan *mxs_chan, void *buffer,
- dma_addr_t buf_dma, int len,
- enum dma_data_direction direction,
- int append)
-{
- int ret;
- int idx = append ? mxs_chan->ccw_idx : 0;
- struct mxs_dma_ccw *ccw;
-
- DBG(1, "%s: mxs_chan=%p status=%d append=%d ccw=%p\n", __func__,
- mxs_chan, mxs_chan->status, append, mxs_chan->ccw);
-
- BUG_ON(mxs_chan->ccw == NULL);
- BUG_ON(mxs_chan == NULL);
-
- if (mxs_chan->status == DMA_IN_PROGRESS && !append)
- return -EBUSY;
-
- if (mxs_chan->status != DMA_IN_PROGRESS && append) {
- ret = -EINVAL;
- goto err_out;
- }
-
- if (idx >= NUM_CCW) {
- printk(KERN_ERR "maximum number of segments exceeded: %d > %d\n",
- idx, NUM_CCW);
- ret = -EINVAL;
- goto err_out;
- }
-
- mxs_chan->status = DMA_IN_PROGRESS;
-
- if (append) {
- BUG_ON(idx < 1);
- ccw = &mxs_chan->ccw[idx - 1];
- ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
- ccw->bits |= CCW_CHAIN;
- ccw->bits &= ~CCW_IRQ;
- ccw->bits &= ~CCW_DEC_SEM;
- ccw->bits &= ~CCW_WAIT4END;
-
- DBG(3, "%s: Appending sg to list[%d]@%p: next=0x%08x bits=0x%08x\n",
- __func__, idx, ccw, ccw->next, ccw->bits);
- } else {
- idx = 0;
- }
- ccw = &mxs_chan->ccw[idx++];
- if (direction == DMA_NONE) {
- int j;
- u32 *pio = buffer;
-
- for (j = 0; j < len; j++)
- ccw->pio_words[j] = *pio++;
-
- if (dbg_lvl(3)) {
- DBG(0, "%s: Storing %d PIO words in ccw[%d]@%p:", __func__,
- len, idx - 1, ccw);
- for (j = 0; j < len; j++) {
- printk(" %08x", ccw->pio_words[j]);
- }
- printk("\n");
- }
- ccw->bits = 0;
- ccw->bits |= CCW_IRQ;
- ccw->bits |= CCW_DEC_SEM;
- ccw->bits |= CCW_WAIT4END;
- ccw->bits |= CCW_HALT_ON_TERM;
- ccw->bits |= CCW_TERM_FLUSH;
- ccw->bits |= BF_CCW(len, PIO_NUM);
- ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
- } else {
- if (len > MAX_XFER_BYTES) {
- printk(KERN_ERR "maximum bytes for sg entry exceeded: %d > %d\n",
- len, MAX_XFER_BYTES);
- ret = -EINVAL;
- goto err_out;
- }
-
- ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
- ccw->bufaddr = buf_dma;
- ccw->xfer_bytes = len;
-
- ccw->bits = 0;
- ccw->bits |= CCW_CHAIN;
- ccw->bits |= CCW_HALT_ON_TERM;
- ccw->bits |= CCW_TERM_FLUSH;
- ccw->bits |= BF_CCW(direction == DMA_FROM_DEVICE ?
- MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
- COMMAND);
-
- ccw->bits &= ~CCW_CHAIN;
- ccw->bits |= CCW_IRQ;
- ccw->bits |= CCW_DEC_SEM;
- ccw->bits |= CCW_WAIT4END;
- DBG(3, "%s: DMA descriptor: ccw=%p next=0x%08x bufadr=%08x xfer_bytes=%08x bits=0x%08x\n",
- __func__, ccw, ccw->next, ccw->bufaddr,
- ccw->xfer_bytes, ccw->bits);
- }
-
- mxs_chan->ccw_idx = idx;
-
- return 0;
-
-err_out:
- mxs_chan->ccw_idx = 0;
- mxs_chan->status = DMA_ERROR;
- return ret;
-}
-
-static int mxs_dma_submit(struct mxs_gpmi *gpmi, struct mxs_dma_chan *mxs_chan)
-{
- int ret;
- int first = 1;
- u32 stat1, stat2;
- int chan_id = mxs_chan->chan_id;
- u32 chan_mask = 1 << chan_id;
- struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
- long timeout = 1000;
-
- dump_dma_context(gpmi, "BEFORE");
-
- mxs_dma_enable_chan(mxs_chan);
-
- dump_dma_context(gpmi, "WITHIN");
-
- while (1) {
- stat1 = mxs_dma_readl(mxs_dma, HW_APBHX_CTRL1);
- stat2 = mxs_dma_readl(mxs_dma, HW_APBHX_CTRL2);
- if ((stat1 & chan_mask) || (stat2 & chan_mask)) {
- break;
- }
- if (first) {
- DBG(1, "Waiting for DMA channel %d to finish\n",
- chan_id);
- first = 0;
- }
- if (timeout-- < 0)
- return -ETIME;
- udelay(100);
- }
-
- dump_dma_context(gpmi, "AFTER");
-
- mxs_dma_writel(chan_mask, mxs_dma, HW_APBHX_CTRL1 + MXS_CLR_ADDR);
- mxs_dma_writel(chan_mask, mxs_dma, HW_APBHX_CTRL2 + MXS_CLR_ADDR);
- stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) |
- (~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1);
- if (stat2 & chan_mask) {
- printk(KERN_ERR "DMA error in channel %d\n", chan_id);
- ret = -EIO;
- } else if (stat1 & chan_mask) {
- DBG(0, "DMA channel %d finished\n", chan_id);
- ret = 0;
- } else {
- printk(KERN_ERR "DMA channel %d early termination\n", chan_id);
- ret = -EINVAL;
- }
- mxs_chan->status = ret == 0 ? DMA_SUCCESS : DMA_ERROR;
- return ret;
-}
-
-static void mxs_dma_terminate_all(struct mxs_dma_chan *mxs_chan)
-{
- mxs_dma_disable_chan(mxs_chan);
-}
-
-static int poll_bit(void __iomem *addr, unsigned int mask, long timeout)
-{
- while (!(readl(addr) & mask)) {
- udelay(1000);
- timeout--;
- }
- return timeout == 0 ? -ETIME : 0;
-}
-
-static int mxs_gpmi_dma_go(struct mxs_gpmi *gpmi,
- int wait_for_bch)
-{
- int error;
- struct mxs_dma_chan *mxs_chan = mxs_gpmi_dma_chan(gpmi,
- gpmi->current_chip);
-
- DBG(1, "> %s\n", __func__);
-
- error = mxs_dma_submit(gpmi, mxs_chan);
- DBG(1, "%s: mxs_dma_submit returned %d\n", __func__,
- error);
- if (error)
- goto err;
-
- if (wait_for_bch) {
- DBG(1, "%s: Waiting for BCH completion\n", __func__);
- error = poll_bit(gpmi->bch_regs + HW_BCH_CTRL,
- BM_BCH_CTRL_COMPLETE_IRQ,
- dma_timeout);
- DBG(1, "%s: poll_bit returned %d\n", __func__,
- error);
- DBG(1, "%s: BCH status %08x\n", __func__,
- mxs_bch_readl(gpmi, HW_BCH_STATUS0));
- if (mxs_bch_readl(gpmi, HW_BCH_CTRL) & BM_BCH_CTRL_COMPLETE_IRQ) {
- DBG(1, "%s: Clearing BCH IRQ\n", __func__);
- mxs_bch_writel(BM_BCH_CTRL_COMPLETE_IRQ, gpmi, HW_BCH_CTRL_CLR);
- }
-
- if (error)
- goto err;
- }
-out:
- DBG(1, "< %s: %d\n", __func__, error);
- return error;
-
-err:
- {
- struct mxs_dma_chan *mxs_chan = mxs_gpmi_dma_chan(gpmi,
- gpmi->current_chip);
- dump_dma_context(gpmi, "ERROR");
- mxs_dma_terminate_all(mxs_chan);
- }
- goto out;
-}
-
-int mxs_gpmi_dma_setup(struct mxs_gpmi *gpmi, void *buffer, int length,
- int pio_words, enum dma_data_direction dir, int append)
-
-{
- int ret;
- struct mxs_dma_chan *mxs_chan;
- dma_addr_t buf_dma;
-
- mxs_chan = mxs_gpmi_dma_chan(gpmi, gpmi->current_chip);
- if (mxs_chan == NULL)
- return -EINVAL;
-
- DBG(1, "%s: buffer=%p len=%u pio=%d append=%d\n", __func__,
- buffer, length, pio_words, append);
-
- if (pio_words) {
- ret = mxs_dma_prep_slave(mxs_chan, gpmi->pio_data, ~0,
- pio_words, DMA_NONE, append);
- if (ret) {
- mxs_dma_terminate_all(mxs_chan);
- printk(KERN_ERR
- "%s: Failed to setup DMA PIO xfer for %d words: %d\n",
- __func__, pio_words, ret);
- return ret;
- }
- if (buffer == NULL)
- return ret;
-
- append = 1;
- }
-
-#if 0
- if (dir == DMA_FROM_DEVICE)
- memset(buffer, 0x55, length);
-#endif
- buf_dma = dma_map_single(buffer, length, dir);
-
- DBG(1, "%s: buffer=%p dma_addr=%08x\n", __func__, buffer, buf_dma);
-
- ret = mxs_dma_prep_slave(mxs_chan, buffer, buf_dma, length, dir, append);
- if (ret) {
- mxs_dma_terminate_all(mxs_chan);
- DBG(1, "%s: mxs_dma_prep_slave() returned %d\n",
- __func__, ret);
- dma_unmap_single(buffer, length, dir);
- }
- return ret;
-}
-
-static int mxs_gpmi_dma_xfer(struct mxs_gpmi *gpmi,
- void *buffer, int length, int pio_words,
- enum dma_data_direction dir)
-{
- int ret;
-
- ret = mxs_gpmi_dma_setup(gpmi, buffer, length,
- pio_words, dir, 0);
-
- if (ret) {
- DBG(1, "%s: mxs_gpmi_dma_setup() returned %d\n",
- __func__, ret);
- return ret;
- }
-
- DBG(1, "%s: starting DMA xfer\n", __func__);
- ret = mxs_gpmi_dma_go(gpmi, 0);
-
- DBG(1, "%s: DMA xfer done: %d\n", __func__, ret);
- return ret;
-}
-
-/* low level accessor functions */
-static int mxs_gpmi_read_data(struct mxs_gpmi *gpmi, int cs,
- void *buffer, size_t length)
-{
- int ret;
- u32 command_mode;
- u32 address;
-
- DBG(2, "%s: buf=%p len=%d\n", __func__, buffer, length);
-
- memset(buffer, 0x44, length);
-
- command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
- address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
-
- gpmi->pio_data[0] =
- BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
- BF_GPMI_CTRL0_CS_V1(cs) |
- BM_GPMI_CTRL0_WORD_LENGTH |
- BF_GPMI_CTRL0_ADDRESS(address) |
- BF_GPMI_CTRL0_XFER_COUNT(length);
- gpmi->pio_data[1] = 0;
-
- ret = mxs_gpmi_dma_xfer(gpmi, buffer, length, 2, DMA_FROM_DEVICE);
- return ret;
-}
-
-/* mtd layer interface */
-static void mxs_gpmi_select_chip(struct mtd_info *mtd, int cs)
-{
- struct nand_chip *chip = mtd->priv;
- struct mxs_gpmi *gpmi = chip->priv;
-
- gpmi->current_chip = cs;
-}
-
-static int mxs_gpmi_dev_ready(struct mtd_info *mtd)
-{
- int ready;
- struct nand_chip *chip = mtd->priv;
- struct mxs_gpmi *gpmi = chip->priv;
- u32 mask;
- u32 reg;
- int cs = gpmi->current_chip;
-
- if (cs < 0)
- return 0;
-
- DBG(1, "> %s\n", __func__);
-
- mask = BF_GPMI_STAT_READY_BUSY(1 << cs);
- reg = mxs_gpmi_readl(gpmi, HW_GPMI_STAT);
-
- ready = !!(reg & mask);
- DBG(1, "< %s: %d\n", __func__, ready);
- return ready;
-}
-
-static void mxs_gpmi_swap_bb_mark(struct mxs_gpmi *gpmi,
- void *payload, void *auxiliary)
-{
- unsigned char *p = payload + gpmi->block_mark_byte_offset;
- unsigned char *a = auxiliary;
- unsigned int bit = gpmi->block_mark_bit_offset;
- unsigned char mask;
- unsigned char from_data;
- unsigned char from_oob;
-
- /*
- * Get the byte from the data area that overlays the block mark. Since
- * the ECC engine applies its own view to the bits in the page, the
- * physical block mark won't (in general) appear on a byte boundary in
- * the data.
- */
- from_data = (p[0] >> bit) | (p[1] << (8 - bit));
-
- /* Get the byte from the OOB. */
- from_oob = a[0];
-
- /* Swap them. */
- a[0] = from_data;
-
- mask = (0x1 << bit) - 1;
- p[0] = (p[0] & mask) | (from_oob << bit);
-
- mask = ~0 << bit;
- p[1] = (p[1] & mask) | (from_oob >> (8 - bit));
-}
-
-static int mxs_gpmi_read_page(struct mtd_info *mtd, struct nand_chip *chip,
- uint8_t *buf)
-{
- int ret = -1;
- struct mxs_gpmi *gpmi = chip->priv;
- int cs = gpmi->current_chip;
- u32 command_mode;
- u32 address;
- u32 ecc_command;
- u32 buffer_mask;
- dma_addr_t buf_dma;
- dma_addr_t oob_dma;
-
- DBG(3, "%s: read page to buffer %p\n", __func__, buf);
-
- buf_dma = dma_map_single(gpmi->page_buf, mtd->writesize,
- DMA_FROM_DEVICE);
-
- oob_dma = dma_map_single(gpmi->oob_buf, mtd->oobsize,
- DMA_FROM_DEVICE);
-
- command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
- address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
-
- gpmi->pio_data[0] =
- BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
- BF_GPMI_CTRL0_CS_V1(cs) |
- BM_GPMI_CTRL0_WORD_LENGTH |
- BF_GPMI_CTRL0_ADDRESS(address) |
- BF_GPMI_CTRL0_XFER_COUNT(0);
- gpmi->pio_data[1] = 0;
-
- ret = mxs_gpmi_dma_setup(gpmi, NULL, 0, 2, DMA_NONE, 0);
- if (ret) {
- goto unmap;
- }
-
- command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
- address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
- ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__DECODE;
- buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
- BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
-
- gpmi->pio_data[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
- BM_GPMI_CTRL0_WORD_LENGTH |
- BF_GPMI_CTRL0_CS_V1(cs) |
- BF_GPMI_CTRL0_ADDRESS(address) |
- BF_GPMI_CTRL0_XFER_COUNT(mtd->writesize + mtd->oobsize);
-
- gpmi->pio_data[1] = 0;
-
- gpmi->pio_data[2] = BM_GPMI_ECCCTRL_ENABLE_ECC |
- BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) |
- BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
-
- gpmi->pio_data[3] = mtd->writesize + mtd->oobsize;
- gpmi->pio_data[4] = buf_dma;
- gpmi->pio_data[5] = oob_dma;
-
- ret = mxs_gpmi_dma_setup(gpmi, NULL, 0, 6, DMA_NONE, 1);
- if (ret) {
- goto unmap;
- }
-
- command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
- address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
-
- gpmi->pio_data[0] =
- BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
- BM_GPMI_CTRL0_WORD_LENGTH |
- BF_GPMI_CTRL0_CS_V1(cs) |
- BF_GPMI_CTRL0_ADDRESS(address) |
- BF_GPMI_CTRL0_XFER_COUNT(mtd->writesize + mtd->oobsize);
-
- gpmi->pio_data[1] = 0;
-
- ret = mxs_gpmi_dma_setup(gpmi, NULL, 0, 2, DMA_NONE, 1);
- if (ret == 0) {
- ret = mxs_gpmi_dma_go(gpmi, 1);
- }
-unmap:
- dma_unmap_single(gpmi->oob_buf, mtd->oobsize,
- DMA_FROM_DEVICE);
- dma_unmap_single(gpmi->page_buf, mtd->writesize,
- DMA_FROM_DEVICE);
- {
-#define STATUS_GOOD 0x00
-#define STATUS_ERASED 0xff
-#define STATUS_UNCORRECTABLE 0xfe
- /* Loop over status bytes, accumulating ECC status. */
- struct nand_chip *chip = mtd->priv;
- int failed = 0;
- int corrected = 0;
- u8 *status = gpmi->oob_buf + mtd->oobavail;
- int i;
-
- for (i = 0; i < mtd->writesize / chip->ecc.size; i++, status++) {
- if ((*status == STATUS_GOOD) || (*status == STATUS_ERASED))
- continue;
-
- if (*status == STATUS_UNCORRECTABLE) {
- failed++;
- continue;
- }
- corrected += *status;
- }
- /*
- * Propagate ECC status to the owning MTD only when failed or
- * corrected times nearly reaches our ECC correction threshold.
- */
- if (failed || corrected >= (chip->ecc.size - 1)) {
- DBG(0, "%s: ECC failures: %d\n", __func__, failed);
- mtd->ecc_stats.failed += failed;
- mtd->ecc_stats.corrected += corrected;
- }
- }
- if (ret == 0) {
- if (gpmi->swap_block_mark)
- mxs_gpmi_swap_bb_mark(gpmi, gpmi->page_buf, gpmi->oob_buf);
- if (buf) {
- memcpy(buf, gpmi->page_buf, mtd->writesize);
- }
- } else {
- printk(KERN_ERR "%s: FAILED to read page to buffer %p\n", __func__, buf);
- }
- return ret;
-}
-
-static int mxs_gpmi_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
- int page, int sndcmd)
-{
- DBG(3, "%s: reading OOB of page %d\n", __func__, page);
-
- memset(chip->oob_poi, dbg_lvl(0) ? 0xfe : 0xff, mtd->oobsize);
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
- chip->read_buf(mtd, chip->oob_poi, mtd->oobavail);
- return 1;
-}
-
-static void mxs_gpmi_write_page(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf)
-{
- int ret = -1;
- struct mxs_gpmi *gpmi = chip->priv;
- int cs = gpmi->current_chip;
- u32 command_mode;
- u32 address;
- u32 ecc_command;
- u32 buffer_mask;
- dma_addr_t buf_dma;
- dma_addr_t oob_dma;
-
- DBG(3, "%s: Writing buffer %p\n", __func__, buf);
-
- memset(gpmi->oob_buf + mtd->oobavail, dbg_lvl(0) ? 0xef : 0xff,
- mtd->oobsize - mtd->oobavail);
-
- if (buf)
- memcpy(gpmi->page_buf, buf, mtd->writesize);
-
- if (gpmi->swap_block_mark)
- mxs_gpmi_swap_bb_mark(gpmi, gpmi->page_buf, gpmi->oob_buf);
-
- buf_dma = dma_map_single(gpmi->page_buf, mtd->writesize,
- DMA_TO_DEVICE);
-
- oob_dma = dma_map_single(gpmi->oob_buf, mtd->oobsize,
- DMA_TO_DEVICE);
-
- command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
- address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
- ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__ENCODE;
- buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
- BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
-
- gpmi->pio_data[0] =
- BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
- BM_GPMI_CTRL0_WORD_LENGTH |
- BF_GPMI_CTRL0_CS_V1(cs) |
- BF_GPMI_CTRL0_ADDRESS(address) |
- BF_GPMI_CTRL0_XFER_COUNT(0);
- gpmi->pio_data[1] = 0;
- gpmi->pio_data[2] =
- BM_GPMI_ECCCTRL_ENABLE_ECC |
- BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) |
- BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
- gpmi->pio_data[3] = mtd->writesize + mtd->oobsize;
- gpmi->pio_data[4] = buf_dma;
- gpmi->pio_data[5] = oob_dma;
-
- ret = mxs_gpmi_dma_setup(gpmi, NULL, 0, 6, DMA_NONE, 0);
- if (ret == 0) {
- ret = mxs_gpmi_dma_go(gpmi, 1);
- }
-
- dma_unmap_single(gpmi->oob_buf, mtd->oobsize,
- DMA_TO_DEVICE);
- dma_unmap_single(gpmi->page_buf, mtd->writesize,
- DMA_TO_DEVICE);
- if (ret) {
- printk(KERN_ERR "%s: FAILED!\n", __func__);
- }
-}
-
-static int mxs_gpmi_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
- int page)
-{
- return -EINVAL;
-}
-
-#if 0
-static void mxs_gpmi_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf)
-{
- memcpy(gpmi->page_buf, buf, mtd->writesize);
-
-}
-#endif
-
-static void mxs_gpmi_read_buf(struct mtd_info *mtd, u_char *buf, int len)
-{
- struct nand_chip *chip = mtd->priv;
- struct mxs_gpmi *gpmi = chip->priv;
- void *xfer_buf;
- int ret = 0;
-
- if (len > mtd->writesize + mtd->oobsize) {
- DBG(0, "%s: Allocating temporary buffer\n", __func__);
- xfer_buf = kzalloc(len, GFP_KERNEL);
- if (xfer_buf == NULL) {
- printk(KERN_ERR
- "Failed to allocate %u byte for xfer buffer\n",
- len);
- memset(buf, 0xee, len);
- }
- } else {
- xfer_buf = buf;
- }
-
- DBG(3, "%s: reading %u byte to %p(%p)\n", __func__,
- len, buf, xfer_buf);
-
- ret = mxs_gpmi_read_data(gpmi, gpmi->current_chip, xfer_buf, len);
- if (xfer_buf != buf) {
- if (ret == 0) {
- memcpy(buf, xfer_buf, len);
- }
- kfree(xfer_buf);
- }
- DBG(1, "< %s %d\n", __func__, ret);
-}
-
-static u_char mxs_gpmi_read_byte(struct mtd_info *mtd)
-{
- struct nand_chip *chip = mtd->priv;
- struct mxs_gpmi *gpmi = chip->priv;
- u_char *buf = (u_char *)gpmi->pio_data;
-
- mxs_gpmi_read_buf(mtd, buf, 1);
- return *buf;
-}
-
-static void mxs_gpmi_write_buf(struct mtd_info *mtd, const u_char *buf,
- int len)
-{
- int ret;
- struct nand_chip *chip = mtd->priv;
- struct mxs_gpmi *gpmi = chip->priv;
- void *xfer_buf = (void *)buf; /* cast away the 'const' */
-#if 1
- u32 command_mode;
- u32 address;
- int cs = gpmi->current_chip;
-
- DBG(3, "%s: writing %u byte from %p\n", __func__, len, buf);
-
- command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
- address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
-
- gpmi->pio_data[0] =
- BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
- BF_GPMI_CTRL0_CS_V1(cs) |
- BM_GPMI_CTRL0_WORD_LENGTH |
- BF_GPMI_CTRL0_ADDRESS(address) |
- BF_GPMI_CTRL0_XFER_COUNT(len);
- gpmi->pio_data[1] = 0;
-
- ret = mxs_gpmi_dma_xfer(gpmi, xfer_buf, len, 2, DMA_TO_DEVICE);
-#else
- ret = mxs_gpmi_send_data(gpmi, gpmi->current_chip, xfer_buf, len);
-#endif
- if (ret)
- printk(KERN_ERR "%s: Failed to write %u byte from %p\n", __func__,
- len, buf);
-}
-
-static int mxs_gpmi_scan_bbt(struct mtd_info *mtd)
-{
- int ret;
-
- DBG(0, "%s: \n", __func__);
- ret = nand_scan_bbt(mtd, create_bbt ? &gpmi_bbt_descr : NULL);
- DBG(0, "%s: nand_scan_bbt() returned %d\n", __func__, ret);
- return ret;
-}
-
-static int mxs_gpmi_send_command(struct mxs_gpmi *gpmi, unsigned cs,
- void *buffer, unsigned int length)
-{
- int error;
- u32 command_mode;
- u32 address;
-
- DBG(1, "%s: Sending NAND command\n", __func__);
-
- command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
- address = BV_GPMI_CTRL0_ADDRESS__NAND_CLE;
-
- gpmi->pio_data[0] =
- BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
- BF_GPMI_CTRL0_CS_V1(cs) |
- BM_GPMI_CTRL0_WORD_LENGTH |
- BF_GPMI_CTRL0_ADDRESS(address) |
- BM_GPMI_CTRL0_ADDRESS_INCREMENT |
- BF_GPMI_CTRL0_XFER_COUNT(length);
-
- gpmi->pio_data[1] = 0;
-
- gpmi->pio_data[2] = 0;
-
- error = mxs_gpmi_dma_xfer(gpmi, buffer, length, 3,
- DMA_TO_DEVICE);
- if (error)
- printk(KERN_ERR "[%s] DMA error\n", __func__);
-
- return error;
-}
-
-static void mxs_gpmi_cmdctrl(struct mtd_info *mtd,
- int data, unsigned int ctrl)
-{
- int ret;
- struct nand_chip *chip = mtd->priv;
- struct mxs_gpmi *gpmi = chip->priv;
- unsigned int i;
-
- DBG(2, "%s: data=%04x ctrl=%04x\n", __func__,
- data, ctrl);
- /*
- * Every operation begins with a command byte and a series of zero or
- * more address bytes. These are distinguished by either the Address
- * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
- * asserted. When MTD is ready to execute the command, it will deassert
- * both latch enables.
- *
- * Rather than run a separate DMA operation for every single byte, we
- * queue them up and run a single DMA operation for the entire series
- * of command and data bytes.
- */
- if ((ctrl & (NAND_ALE | NAND_CLE))) {
- if (data != NAND_CMD_NONE) {
- DBG(3, "%s: Storing cmd byte %02x\n", __func__, data & 0xff);
- gpmi->cmd_buf[gpmi->command_length++] = data;
- }
- return;
- }
- /*
- * If control arrives here, MTD has deasserted both the ALE and CLE,
- * which means it's ready to run an operation. Check if we have any
- * bytes to send.
- */
- if (gpmi->command_length == 0)
- return;
-
- DBG(1, "%s: sending command...\n", __func__);
- for (i = 0; i < gpmi->command_length; i++)
- DBG(2, " 0x%02x", gpmi->cmd_buf[i]);
- DBG(2, "\n");
-
- ret = mxs_gpmi_send_command(gpmi,
- gpmi->current_chip, gpmi->cmd_buf,
- gpmi->command_length);
- if (ret) {
- printk(KERN_ERR "[%s] Chip: %u, Error %d\n",
- __func__, gpmi->current_chip, ret);
- }
-
- gpmi->command_length = 0;
- DBG(1, "%s: ...Finished\n", __func__);
-}
-
-static int mxs_gpmi_set_ecclayout(struct mxs_gpmi *gpmi,
- int page_size, int oob_size)
-{
- struct nand_chip *chip = gpmi->chip;
- struct mtd_info *mtd = gpmi->mtd;
- struct nand_ecclayout *layout = &gpmi->ecc_layout;
- const int meta_size = 10;
- const int block0_size = 512;
- const int blockn_size = 512;
- const int fl0_nblocks = (mtd->writesize >> 9) - !!block0_size;
- int i;
-
- chip->ecc.mode = NAND_ECC_HW;
- chip->ecc.size = blockn_size;
- chip->ecc.layout = layout;
-
- chip->bbt_td = &mxs_gpmi_bbt_main_descr;
- chip->bbt_md = &mxs_gpmi_bbt_mirror_descr;
-
- if (create_bbt) {
- chip->bbt_td->options |= NAND_BBT_WRITE | NAND_BBT_CREATE;
- chip->bbt_md->options |= NAND_BBT_WRITE | NAND_BBT_CREATE;
- }
-
- switch (page_size) {
- case 2048:
- /* default GPMI OOB layout */
- layout->eccbytes = 4 * 10 + 9;
- gpmi->block0_ecc_strength = 8;
- gpmi->blockn_ecc_strength = 8;
- break;
-
- case 4096:
- if (mtd->oobsize == 128) {
- gpmi->block0_ecc_strength = 8;
- gpmi->blockn_ecc_strength = 8;
- } else {
- gpmi->block0_ecc_strength = 16;
- gpmi->blockn_ecc_strength = 16;
- }
- break;
-
- case 8192:
- gpmi->block0_ecc_strength = 24;
- gpmi->blockn_ecc_strength = 24;
- break;
-
- default:
- printk(KERN_ERR "unsupported page size: %u\n", page_size);
- return -EINVAL;
- }
-
- {
- int chunk0_data_size_in_bits = block0_size * 8;
- int chunk0_ecc_size_in_bits = gpmi->block0_ecc_strength * 13;
- int chunkn_data_size_in_bits = blockn_size * 8;
- int chunkn_ecc_size_in_bits = gpmi->blockn_ecc_strength * 13;
- int chunkn_total_size_in_bits = chunkn_data_size_in_bits +
- chunkn_ecc_size_in_bits;
-
- /* Compute the bit offset of the block mark within the physical page. */
- int block_mark_bit_offset = mtd->writesize * 8;
-
- /* Subtract the metadata bits. */
- block_mark_bit_offset -= meta_size * 8;
-
- /* if the first block is metadata only,
- * subtract the number of ecc bits of that block
- */
- if (block0_size == 0) {
- block_mark_bit_offset -= chunk0_ecc_size_in_bits;
- }
- /*
- * Compute the chunk number (starting at zero) in which the block mark
- * appears.
- */
- int block_mark_chunk_number =
- block_mark_bit_offset / chunkn_total_size_in_bits;
-
- /*
- * Compute the bit offset of the block mark within its chunk, and
- * validate it.
- */
- int block_mark_chunk_bit_offset = block_mark_bit_offset -
- (block_mark_chunk_number * chunkn_total_size_in_bits);
-
- if (block_mark_chunk_bit_offset > chunkn_data_size_in_bits) {
- /*
- * If control arrives here, the block mark actually appears in
- * the ECC bits of this chunk. This wont' work.
- */
- printf("Unsupported page geometry (block mark in ECC): %u:%u",
- mtd->writesize, mtd->oobsize);
- return -EINVAL;
- }
-
- /*
- * Now that we know the chunk number in which the block mark appears,
- * we can subtract all the ECC bits that appear before it.
- */
- block_mark_bit_offset -= block_mark_chunk_number *
- chunkn_ecc_size_in_bits;
-
- /*
- * We now know the absolute bit offset of the block mark within the
- * ECC-based data. We can now compute the byte offset and the bit
- * offset within the byte.
- */
- gpmi->block_mark_byte_offset = block_mark_bit_offset / 8;
- gpmi->block_mark_bit_offset = block_mark_bit_offset % 8;
-
- DBG(0, "NAND geometry:\n");
- DBG(0, "page size : %5u byte\n", mtd->writesize);
- DBG(0, "oob size : %5u byte\n", mtd->oobsize);
- DBG(0, "erase size : %5u byte\n", mtd->erasesize);
- DBG(0, "metadata : %5u byte\n", meta_size);
- DBG(0, "ECC:\n");
- DBG(0, "chunk0 level: %5u\n", gpmi->block0_ecc_strength);
- DBG(0, "chunk0 data : %5u bit (%5u byte)\n",
- chunk0_data_size_in_bits,
- DIV_ROUND_UP(chunk0_data_size_in_bits, 8));
- DBG(0, "chunk0 ECC : %5u bit (%5u byte)\n",
- chunk0_ecc_size_in_bits,
- DIV_ROUND_UP(chunk0_ecc_size_in_bits, 8));
-
- DBG(0, "chunkn level: %5u\n", gpmi->blockn_ecc_strength);
- DBG(0, "chunkn data : %5u bit (%5u byte)\n",
- chunkn_data_size_in_bits,
- DIV_ROUND_UP(chunkn_data_size_in_bits, 8));
- DBG(0, "chunkn ECC : %5u bit (%5u byte)\n",
- chunkn_ecc_size_in_bits,
- DIV_ROUND_UP(chunkn_ecc_size_in_bits, 8));
- DBG(0, "BB chunk : %5d\n", block_mark_chunk_number);
- DBG(0, "BB byte offs: %5u\n", gpmi->block_mark_byte_offset);
- DBG(0, "BB bit offs : %5u\n", gpmi->block_mark_bit_offset);
- }
-
- for (i = 0; i < layout->eccbytes; i++) {
- layout->eccpos[i] = mtd->oobsize - i - 1;
- }
- layout->oobfree[0].length = meta_size;
-
- chip->ecc.bytes = layout->eccbytes;
-
- DBG(0, "%s: Resetting BCH\n", __func__);
- mxs_reset_block(gpmi->bch_regs);
-
- mxs_bch_writel(
- BF_BCH_FLASH0LAYOUT0_NBLOCKS(fl0_nblocks) |
- BF_BCH_FLASH0LAYOUT0_META_SIZE(meta_size) |
- BF_BCH_FLASH0LAYOUT0_ECC0(gpmi->block0_ecc_strength >> 1) |
- BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block0_size),
- gpmi, HW_BCH_FLASH0LAYOUT0);
-
- mxs_bch_writel(
- BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(mtd->writesize + mtd->oobsize) |
- BF_BCH_FLASH0LAYOUT1_ECCN(gpmi->blockn_ecc_strength >> 1) |
- BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(blockn_size),
- gpmi, HW_BCH_FLASH0LAYOUT1);
-
- mxs_bch_writel(0, gpmi, HW_BCH_LAYOUTSELECT);
-
- mxs_bch_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN, gpmi, HW_BCH_CTRL_SET);
- return 0;
-}
-
-int mxs_gpmi_nand_init(struct mtd_info *mtd, struct nand_chip *chip)
-{
- int ret;
- struct mxs_gpmi *gpmi;
-
- gpmi = kzalloc(sizeof(struct mxs_gpmi), GFP_KERNEL);
- if (gpmi == NULL) {
- ret = -ENOMEM;
- return ret;
- }
- gpmi->mtd = mtd;
- gpmi->chip = chip;
-
- gpmi->chip_count = CONFIG_SYS_MAX_NAND_DEVICE;
- gpmi->swap_block_mark = 1;
-
- gpmi->gpmi_regs = __ioremap(GPMI_BASE_ADDR, SZ_4K, 1);
- if (gpmi->gpmi_regs == NULL) {
- ret = -ENOMEM;
- goto out;
- }
-
- gpmi->bch_regs = __ioremap(BCH_BASE_ADDR, SZ_4K, 1);
- if (gpmi->bch_regs == NULL) {
- ret = -ENOMEM;
- goto out;
- }
-
- gpmi->dma_regs = __ioremap(APBHDMA_BASE_ADDR, SZ_4K, 1);
- if (gpmi->dma_regs == NULL) {
- ret = -ENOMEM;
- goto out;
- }
-
- ret = mxs_dma_init(gpmi, CONFIG_SYS_MXS_DMA_CHANNEL,
- CONFIG_SYS_MAX_NAND_DEVICE);
- if (ret)
- goto out;
-
- ret = mxs_gpmi_init_hw(gpmi);
- if (ret)
- goto out;
-
- chip->priv = gpmi;
-
- chip->select_chip = mxs_gpmi_select_chip;
- chip->cmd_ctrl = mxs_gpmi_cmdctrl;
- chip->dev_ready = mxs_gpmi_dev_ready;
-
- chip->read_byte = mxs_gpmi_read_byte;
- chip->read_buf = mxs_gpmi_read_buf;
- chip->write_buf = mxs_gpmi_write_buf;
-
- chip->scan_bbt = mxs_gpmi_scan_bbt;
-
- chip->options |= NAND_NO_SUBPAGE_WRITE;
- chip->options |= NAND_USE_FLASH_BBT | NAND_USE_FLASH_BBT_NO_OOB;
-
- chip->ecc.read_page = mxs_gpmi_read_page;
- chip->ecc.read_oob = mxs_gpmi_read_oob;
- chip->ecc.write_page = mxs_gpmi_write_page;
- chip->ecc.write_oob = mxs_gpmi_write_oob;
-
- DBG(0, "%s: Scanning for NAND chips\n", __func__);
- ret = nand_scan_ident(mtd, gpmi->chip_count);
- if (ret) {
- DBG(0, "%s: Failed to scan for NAND chips\n", __func__);
- goto out;
- }
- DBG(0, "%s: pagesize=%d oobsize=%d\n", __func__,
- mtd->writesize, mtd->oobsize);
-
- gpmi->page_buf = kzalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
- if (gpmi->page_buf == NULL) {
- ret = -ENOMEM;
- return ret;
- }
- gpmi->oob_buf = gpmi->page_buf + mtd->writesize;
-
- ret = mxs_gpmi_set_ecclayout(gpmi, mtd->writesize, mtd->oobsize);
- if (ret) {
- DBG(0, "%s: Unsupported ECC layout\n", __func__);
- return ret;
- }
- DBG(0, "%s: NAND scan succeeded\n", __func__);
- return 0;
-out:
- kfree(gpmi);
- return ret;
-}
+++ /dev/null
-/*
- * Freescale GPMI NFC NAND Flash Driver
- *
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- * Copyright (C) 2008 Embedded Alley Solutions, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __DRIVERS_MTD_NAND_GPMI_NFC_H
-#define __DRIVERS_MTD_NAND_GPMI_NFC_H
-
-/*
- *------------------------------------------------------------------------------
- * Fundamental Macros
- *------------------------------------------------------------------------------
- */
-
-#define NFC_DMA_DESCRIPTOR_COUNT 4
-
-/* Define this macro to enable detailed information messages. */
-#define DETAILED_INFO
-
-/* Define this macro to enable event reporting. */
-/*#define EVENT_REPORTING*/
-
-/*
- *------------------------------------------------------------------------------
- * Fundamental Data Structures
- *------------------------------------------------------------------------------
- */
-
-#define COMMAND_BUFFER_SIZE 10
-
-/**
- * struct gpmi_nfc_timing - GPMI NFC timing parameters.
- *
- * This structure contains the fundamental timing attributes for the NAND Flash
- * bus and the GPMI NFC hardware.
- *
- * @data_setup_in_ns: The data setup time, in nanoseconds. Usually the
- * maximum of tDS and tWP. A negative value
- * indicates this characteristic isn't known.
- * @data_hold_in_ns: The data hold time, in nanoseconds. Usually the
- * maximum of tDH, tWH and tREH. A negative value
- * indicates this characteristic isn't known.
- * @address_setup_in_ns: The address setup time, in nanoseconds. Usually
- * the maximum of tCLS, tCS and tALS. A negative
- * value indicates this characteristic isn't known.
- * @gpmi_sample_time_in_ns: A GPMI-specific timing parameter. A negative
- * value indicates this characteristic isn't known.
- * @tREA_in_ns: tREA, in nanoseconds, from the data sheet. A
- * negative value indicates this characteristic
- * isn't known.
- * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet. A
- * negative value indicates this characteristic
- * isn't known.
- * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet. A
- * negative value indicates this characteristic
- * isn't known.
- */
-struct gpmi_nfc_timing {
- int8_t data_setup_in_ns;
- int8_t data_hold_in_ns;
- int8_t address_setup_in_ns;
- int8_t gpmi_sample_delay_in_ns;
- int8_t tREA_in_ns;
- int8_t tRLOH_in_ns;
- int8_t tRHOH_in_ns;
-};
-#if 0
-enum nand_device_cell_technology {
- NAND_DEVICE_CELL_TECH_SLC = 0,
- NAND_DEVICE_CELL_TECH_MLC = 1,
-};
-
-struct nand_device_info {
- /* End of table marker */
- bool end_of_table;
-
- /* Manufacturer and Device codes */
- uint8_t manufacturer_code;
- uint8_t device_code;
-
- /* Technology */
- enum nand_device_cell_technology cell_technology;
-
- /* Geometry */
- uint64_t chip_size_in_bytes;
- uint32_t block_size_in_pages;
- uint16_t page_total_size_in_bytes;
-
- /* ECC */
- uint8_t ecc_strength_in_bits;
- uint16_t ecc_size_in_bytes;
-
- /* Timing */
- int8_t data_setup_in_ns;
- int8_t data_hold_in_ns;
- int8_t address_setup_in_ns;
- int8_t gpmi_sample_delay_in_ns;
- int8_t tREA_in_ns;
- int8_t tRLOH_in_ns;
- int8_t tRHOH_in_ns;
-
- /* human readable device description */
- const char *description;
-};
-
-/**
- * struct gpmi_nfc_data - i.MX NFC per-device data.
- *
- * Note that the "device" managed by this driver represents the NAND Flash
- * controller *and* the NAND Flash medium behind it. Thus, the per-device data
- * structure has information about the controller, the chips to which it is
- * connected, and properties of the medium as a whole.
- *
- * @dev: A pointer to the owning struct device.
- * @pdev: A pointer to the owning struct platform_device.
- * @pdata: A pointer to the device's platform data.
- * @device_info: A structure that contains detailed information about
- * the NAND Flash device.
- * @nfc: A pointer to a structure that represents the underlying
- * NFC hardware.
- * @rom: A pointer to a structure that represents the underlying
- * Boot ROM.
- * @mil: A collection of information used by the MTD Interface
- * Layer.
- */
-struct gpmi_nfc_data {
- /* System Interface */
- struct device *dev;
- struct platform_device *pdev;
- struct gpmi_nfc_platform_data *pdata;
-
- /* Resources */
- struct clk *clock;
- void __iomem *gpmi_regs;
- void __iomem *bch_regs;
- unsigned int bch_interrupt;
- unsigned int dma_low_channel;
- unsigned int dma_high_channel;
- unsigned int dma_interrupt;
-
-// struct resources resources;
-
- /* NFC HAL */
- /* Hardware attributes. */
- unsigned int max_chip_count;
-
- /* Working variables. */
- struct mxs_dma_desc *dma_descriptors[NFC_DMA_DESCRIPTOR_COUNT];
- int isr_dma_channel;
- struct completion dma_done;
- struct completion bch_done;
- struct gpmi_nfc_timing timing;
-// struct nfc_hal *nfc;
- int current_chip;
-
- /* MTD Interface Layer */
- struct mtd_info mtd;
- struct nand_chip chip;
- struct nand_ecclayout oob_layout;
- struct mtd_partition *partitions;
- unsigned int partition_count;
-
- /* DMA Buffers */
- u8 *cmd_virt;
- dma_addr_t cmd_phys;
- unsigned int command_length;
-
- void *page_buffer_virt;
- dma_addr_t page_buffer_phys;
- unsigned int page_buffer_size;
-
- void *payload_virt;
- dma_addr_t payload_phys;
-
- void *auxiliary_virt;
- dma_addr_t auxiliary_phys;
-};
-
-/**
- * struct nfc_hal - GPMI NFC HAL
- *
- * This structure embodies an abstract interface to the underlying NFC hardware.
- *
- * @version: The NFC hardware version.
- * @description: A pointer to a human-readable description of
- * the NFC hardware.
- * @max_chip_count: The maximum number of chips the NFC can
- * possibly support (this value is a constant
- * for each NFC version). This may *not* be the
- * actual number of chips connected.
- * @max_data_setup_cycles: The maximum number of data setup cycles
- * that can be expressed in the hardware.
- * @max_data_sample_delay_cycles: The maximum number of data sample delay
- * cycles that can be expressed in the hardware.
- * @max_dll_clock_period_in_ns: The maximum period of the GPMI clock that the
- * sample delay DLL hardware can possibly work
- * with (the DLL is unusable with longer
- * periods). At HALF this value, the DLL must be
- * configured to use half-periods.
- * @dma_descriptors: A pool of DMA descriptors.
- * @isr_dma_channel: The DMA channel with which the NFC HAL is
- * working. We record this here so the ISR knows
- * which DMA channel to acknowledge.
- * @dma_done: The completion structure used for DMA
- * interrupts.
- * @bch_done: The completion structure used for BCH
- * interrupts.
- * @timing: The current timing configuration.
- * @init: Initializes the NFC hardware and data
- * structures. This function will be called
- * after everything has been set up for
- * communication with the NFC itself, but before
- * the platform has set up off-chip
- * communication. Thus, this function must not
- * attempt to communicate with the NAND Flash
- * hardware.
- * @set_geometry: Configures the NFC hardware and data
- * structures to match the physical NAND Flash
- * geometry.
- * @set_geometry: Configures the NFC hardware and data
- * structures to match the physical NAND Flash
- * geometry.
- * @exit: Shuts down the NFC hardware and data
- * structures. This function will be called
- * after the platform has shut down off-chip
- * communication but while communication with
- * the NFC itself still works.
- * @clear_bch: Clears a BCH interrupt (intended to be called
- * by a more general interrupt handler to do
- * device-specific clearing).
- * @is_ready: Returns true if the given chip is ready.
- * @begin: Begins an interaction with the NFC. This
- * function must be called before *any* of the
- * following functions so the NFC can prepare
- * itself.
- * @end: Ends interaction with the NFC. This function
- * should be called to give the NFC a chance to,
- * among other things, enter a lower-power
- * state.
- * @send_command: Sends the given buffer of command bytes.
- * @send_data: Sends the given buffer of data bytes.
- * @read_data: Reads data bytes into the given buffer.
- * @send_page: Sends the given given data and OOB bytes,
- * using the ECC engine.
- * @read_page: Reads a page through the ECC engine and
- * delivers the data and OOB bytes to the given
- * buffers.
- */
-
-struct nfc_hal {
- /* Hardware attributes. */
- const unsigned int version;
- const char *description;
- const unsigned int max_chip_count;
- const unsigned int max_data_setup_cycles;
- const unsigned int max_data_sample_delay_cycles;
- const unsigned int max_dll_clock_period_in_ns;
-
- /* Working variables. */
- struct mxs_dma_desc *dma_descriptors[NFC_DMA_DESCRIPTOR_COUNT];
- int isr_dma_channel;
- struct completion dma_done;
- struct completion bch_done;
- struct gpmi_nfc_timing timing;
-
- /* Configuration functions. */
- int (*init) (struct gpmi_nfc_data *);
- int (*set_geometry)(struct gpmi_nfc_data *);
- int (*set_timing) (struct gpmi_nfc_data *,
- const struct gpmi_nfc_timing *);
- void (*exit) (struct gpmi_nfc_data *);
-
- /* Call these functions to begin and end I/O. */
-
- void (*begin) (struct gpmi_nfc_data *);
- void (*end) (struct gpmi_nfc_data *);
-
- /* Call these I/O functions only between begin() and end(). */
-
- void (*clear_bch) (struct gpmi_nfc_data *);
- int (*is_ready) (struct gpmi_nfc_data *, unsigned chip);
- int (*send_command)(struct gpmi_nfc_data *, unsigned chip,
- dma_addr_t buffer, unsigned length);
- int (*send_data) (struct gpmi_nfc_data *, unsigned chip,
- dma_addr_t buffer, unsigned length);
- int (*read_data) (struct gpmi_nfc_data *, unsigned chip,
- dma_addr_t buffer, unsigned length);
- int (*send_page) (struct gpmi_nfc_data *, unsigned chip,
- dma_addr_t payload, dma_addr_t auxiliary);
- int (*read_page) (struct gpmi_nfc_data *, unsigned chip,
- dma_addr_t payload, dma_addr_t auxiliary);
-};
-
-/**
- * struct boot_rom_helper - Boot ROM Helper
- *
- * This structure embodies the interface to an object that assists the driver
- * in making decisions that relate to the Boot ROM.
- *
- * @version: The Boot ROM version.
- * @description: A pointer to a human-readable description of the
- * Boot ROM.
- * @swap_block_mark: Indicates that the Boot ROM will swap the block
- * mark with the first byte of the OOB.
- * @set_geometry: Configures the Boot ROM geometry.
- * @check_transcription_stamp: Checks for a transcription stamp. This pointer
- * is ignored if swap_block_mark is set.
- * @write_transcription_stamp: Writes a transcription stamp. This pointer
- * is ignored if swap_block_mark is set.
- */
-
-struct boot_rom_helper {
- const unsigned int version;
- const char *description;
- const int swap_block_mark;
- int (*set_geometry) (struct gpmi_nfc_data *);
- int (*check_transcription_stamp)(struct gpmi_nfc_data *);
- int (*write_transcription_stamp)(struct gpmi_nfc_data *);
-};
-
-/*
- *------------------------------------------------------------------------------
- * External Symbols
- *------------------------------------------------------------------------------
- */
-
-/* Event Reporting */
-
-#if defined(EVENT_REPORTING)
-#if 0
- extern void gpmi_nfc_start_event_trace(char *description);
- extern void gpmi_nfc_add_event(char *description, int delta);
- extern void gpmi_nfc_stop_event_trace(char *description);
- extern void gpmi_nfc_dump_event_trace(void);
-#endif
-#else
- #define gpmi_nfc_start_event_trace(description) do {} while (0)
- #define gpmi_nfc_add_event(description, delta) do {} while (0)
- #define gpmi_nfc_stop_event_trace(description) do {} while (0)
- #define gpmi_nfc_dump_event_trace() do {} while (0)
-#endif /* EVENT_REPORTING */
-
-#endif /* 0 */
-
-#endif /* __DRIVERS_MTD_NAND_GPMI_NFC_H */
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <asm/sizes.h>
-#include <linux/mtd/nand.h>
-#include <common.h>
-#include "nand_device_info.h"
-
-/*
- * Type 2
- */
-static struct nand_device_info nand_device_info_table_type_2[] =
-{
- {
- .end_of_table = false,
- .manufacturer_code = 0x20,
- .device_code = 0xf1,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 128LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 30,
- .data_hold_in_ns = 20,
- .address_setup_in_ns = 25,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "NAND01GW3",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xad,
- .device_code = 0xf1,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 128LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 45,
- .data_hold_in_ns = 30,
- .address_setup_in_ns = 25,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0xf1,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 128LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 30,
- .data_hold_in_ns = 20,
- .address_setup_in_ns = 10,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xf1,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 128LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 35,
- .data_hold_in_ns = 25,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "K9F1F08",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x98,
- .device_code = 0xf1,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 128LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 30,
- .data_hold_in_ns = 20,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "TC58NVG0S3",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x45,
- .device_code = 0xf1,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 128LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 45,
- .data_hold_in_ns = 32,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x20,
- .device_code = 0xda,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 256LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 30,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "NAND02GW3",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xad,
- .device_code = 0xda,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 256LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 30,
- .data_hold_in_ns = 25,
- .address_setup_in_ns = 10,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "HY27UF082G2M, HY27UG082G2M, HY27UG082G1M",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0xda,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 256LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 10,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "MT29F2G08",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xda,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 256LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "K9F2G08U0M",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x98,
- .device_code = 0xda,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 256LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 30,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "TC58NVG1S3",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x45,
- .device_code = 0xda,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 256LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 45,
- .data_hold_in_ns = 32,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x20,
- .device_code = 0xdc,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 512LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 45,
- .data_hold_in_ns = 30,
- .address_setup_in_ns = 10,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xad,
- .device_code = 0xdc,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 512LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 45,
- .data_hold_in_ns = 30,
- .address_setup_in_ns = 10,
- .gpmi_sample_delay_in_ns = 10,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "HY27UH084G2M, HY27UG084G2M, HY27UH084G1M",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0xdc,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 512LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 10,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "MT29F4G08",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xdc,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 512LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 25,
- .data_hold_in_ns = 25,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x98,
- .device_code = 0xdc,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 512LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 25,
- .data_hold_in_ns = 25,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "TH58NVG2S3",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x45,
- .device_code = 0xdc,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 512LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 45,
- .data_hold_in_ns = 32,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xad,
- .device_code = 0xd3,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 1LL*SZ_1G,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 30,
- .data_hold_in_ns = 25,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "HY27UH088G2M",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x20,
- .device_code = 0xd3,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 1LL*SZ_1G,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 45,
- .data_hold_in_ns = 30,
- .address_setup_in_ns = 10,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "NAND08GW3BxANx",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0xd3,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 1LL*SZ_1G,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 25,
- .data_hold_in_ns = 15,
- .address_setup_in_ns = 10,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "MT29F8G08FABWG",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x98,
- .device_code = 0xd3,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 1LL*SZ_1G,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 45,
- .data_hold_in_ns = 32,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x20,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 45,
- .data_hold_in_ns = 30,
- .address_setup_in_ns = 10,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xad,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 25,
- .data_hold_in_ns = 30,
- .address_setup_in_ns = 10,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 45,
- .data_hold_in_ns = 32,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {true}
-};
-
-/*
- * Large MLC
- */
-static struct nand_device_info nand_device_info_table_large_mlc[] =
-{
- {
- .end_of_table = false,
- .manufacturer_code = 0x98,
- .device_code = 0xda,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 256LL*SZ_1M,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 30,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "TC58NVG1D4BFT00",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x45,
- .device_code = 0xda,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 256LL*SZ_1M,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 30,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x45,
- .device_code = 0xdc,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 512LL*SZ_1M,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 30,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x98,
- .device_code = 0xd3,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 1LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 35,
- .data_hold_in_ns = 30,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "TH58NVG3D4xFT00",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x45,
- .device_code = 0xd3,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 1LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 35,
- .data_hold_in_ns = 20,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x98,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 35,
- .data_hold_in_ns = 15,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "TH58NVG4D4xFT00",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x45,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 35,
- .data_hold_in_ns = 15,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x98,
- .device_code = 0xdc,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 512LL*SZ_1M,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 30,
- .address_setup_in_ns = 0,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "TC58NVG2D4BFT00",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xdc,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 512LL*SZ_1M,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 25,
- .data_hold_in_ns = 15,
- .address_setup_in_ns = 25,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "K9G4G08U0M",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xad,
- .device_code = 0xdc,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 512LL*SZ_1M,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 45,
- .data_hold_in_ns = 25,
- .address_setup_in_ns = 50,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "HY27UT084G2M, HY27UU088G5M",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x20,
- .device_code = 0xdc,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 512LL*SZ_1M,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 40,
- .data_hold_in_ns = 20,
- .address_setup_in_ns = 30,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "NAND04GW3C2AN1E",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xd3,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 1LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 15,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "K9G8G08U0M, K9HAG08U1M",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xad,
- .device_code = 0xd3,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 1LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 60,
- .data_hold_in_ns = 30,
- .address_setup_in_ns = 50,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "HY27UV08AG5M",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0xd3,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 1LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 15,
- .address_setup_in_ns = 15,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "Intel JS29F08G08AAMiB1 and Micron MT29F8G08MAA; "
- "Intel JS29F08G08CAMiB1 and Micron MT29F16G08QAA",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 15,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "K9LAG08U0M K9HBG08U1M K9GAG08U0M",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 15,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "Intel JS29F32G08FAMiB1 and Micron MT29F32G08TAA",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0xdc,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 512LL*SZ_1M,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 20,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "MT29F4G08",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x89,
- .device_code = 0xd3,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 1LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 15,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "JS29F08G08AAMiB2, JS29F08G08CAMiB2",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x89,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 15,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "JS29F32G08FAMiB2",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xad,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "HY27UW08CGFM",
- },
- {true}
-};
-
-/*
- * Type 7
- */
-static struct nand_device_info nand_device_info_table_type_7[] =
-{
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0xd3,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 1LL*SZ_1G,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 25,
- .data_hold_in_ns = 15,
- .address_setup_in_ns = 10,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "MT29F8G08FABWG",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0xdc,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 512LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 10,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "MT29F4G08AAA",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xdc,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 512LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 12,
- .address_setup_in_ns = 25,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "K9F4G08",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xd3,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 1LL*SZ_1G,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 25,
- .data_hold_in_ns = 15,
- .address_setup_in_ns = 35,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "K9K8G08UXM, K9NBG08U5A, K9WAG08U1A",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 12,
- .address_setup_in_ns = 25,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "K9WAG08UXM",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xda,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 256LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "K9F2G08U0A",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xf1,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 128LL*SZ_1M,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 2*SZ_1K + 64,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 12,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "K9F1F08",
- },
- {true}
-};
-
-/*
- * Type 8
- */
-static struct nand_device_info nand_device_info_table_type_8[] =
-{
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 128,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "K9GAG08U0M",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xd7,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 4LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 128,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 15,
- .address_setup_in_ns = 25,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "K9LBG08U0M (32Gb), K9HCG08U1M (64Gb), K9MDG08U5M (128Gb)",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xad,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 128,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 20,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 0,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "H27UAG, H27UBG",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xad,
- .device_code = 0xd7,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 4LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 128,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 23,
- .data_hold_in_ns = 20,
- .address_setup_in_ns = 25,
- .gpmi_sample_delay_in_ns = 0,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "H27UCG",
- },
- {true}
-};
-
-/*
- * Type 9
- */
-static struct nand_device_info nand_device_info_table_type_9[] =
-{
- {
- .end_of_table = false,
- .manufacturer_code = 0x98,
- .device_code = 0xd3,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 1LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 218,
- .ecc_strength_in_bits = 8,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 15,
- .address_setup_in_ns = 10,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "TC58NVG3D1DTG00",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x98,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 218,
- .ecc_strength_in_bits = 8,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 15,
- .address_setup_in_ns = 10,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "TC58NVG4D1DTG00",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x98,
- .device_code = 0xd7,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 4LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 218,
- .ecc_strength_in_bits = 8,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 15,
- .address_setup_in_ns = 10,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "TH58NVG6D1DTG20",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x89,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 218,
- .ecc_strength_in_bits = 8,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 10,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 15,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "JS29F16G08AAMC1, JS29F32G08CAMC1",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 218,
- .ecc_strength_in_bits = 8,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 15,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "MT29F16G08MAA, MT29F32G08QAA",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0xd7,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 4LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 218,
- .ecc_strength_in_bits = 8,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 15,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "MT29F64G08TAA (32Gb), MT29F32G08CBAAA (32Gb) MT29F64G08CFAAA (64Gb)",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0xd9,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 8LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 218,
- .ecc_strength_in_bits = 8,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 10,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 15,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "MT29F128G08CJAAA",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x89,
- .device_code = 0xd7,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 4LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 218,
- .ecc_strength_in_bits = 8,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 10,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 15,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "JSF64G08FAMC1",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xd7,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 4LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 218,
- .ecc_strength_in_bits = 8,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 25,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "K9LBG08U0D",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 218,
- .ecc_strength_in_bits = 8,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "K9GAG08U0D, K9LBG08U1D, K9HCG08U5D",
- },
- {true}
-};
-
-/*
- * Type 10
- */
-static struct nand_device_info nand_device_info_table_type_10[] =
-{
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xd3,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 1LL*SZ_1G,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 4*SZ_1K + 128,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xd5,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 4*SZ_1K + 128,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 25,
- .data_hold_in_ns = 15,
- .address_setup_in_ns = 30,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- "K9NCG08U5M",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xd7,
- .cell_technology = NAND_DEVICE_CELL_TECH_SLC,
- .chip_size_in_bytes = 4LL*SZ_1G,
- .block_size_in_pages = 64,
- .page_total_size_in_bytes = 4*SZ_1K + 128,
- .ecc_strength_in_bits = 4,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 15,
- .address_setup_in_ns = 25,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = -1,
- .tRLOH_in_ns = -1,
- .tRHOH_in_ns = -1,
- NULL,
- },
- {true}
-};
-
-/*
- * Type 11
- */
-static struct nand_device_info nand_device_info_table_type_11[] =
-{
- {
- .end_of_table = false,
- .manufacturer_code = 0x98,
- .device_code = 0xd7,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 4LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 8*SZ_1K + 376,
- .ecc_strength_in_bits = 14,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 8,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = 20,
- .tRLOH_in_ns = 5,
- .tRHOH_in_ns = 25,
- "TC58NVG5D2ELAM8 (4GB), TH58NVG6D2ELAM8 (8GB)",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x98,
- .device_code = 0xde,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 8LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 8*SZ_1K + 376,
- .ecc_strength_in_bits = 14,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 8,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = 20,
- .tRLOH_in_ns = 5,
- .tRHOH_in_ns = 25,
- "TH58NVG7D2ELAM8",
- },
- {true}
-};
-
-/*
- * Type 15
- */
-static struct nand_device_info nand_device_info_table_type_15[] =
-{
- {
- .end_of_table = false,
- .manufacturer_code = 0xec,
- .device_code = 0xd7,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 4LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 8*SZ_1K + 436,
- .ecc_strength_in_bits = 16,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 20,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 25,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = 25,
- .tRLOH_in_ns = 5,
- .tRHOH_in_ns = 15,
- "K9GBG08U0M (4GB, 1CE); K9LCG08U1M (8GB, 2CE); K9HDG08U5M (16GB, 4CE)",
- },
- {true}
-};
-
-/*
- * BCH ECC12
- */
-static struct nand_device_info nand_device_info_table_bch_ecc12[] =
-{
- {
- .end_of_table = false,
- .manufacturer_code = 0xad,
- .device_code = 0xd7,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 4LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 224,
- .ecc_strength_in_bits = 12,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = 20,
- .tRLOH_in_ns = 5,
- .tRHOH_in_ns = 15,
- "H27UBG8T2M (4GB, 1CE), H27UCG8UDM (8GB, 2CE), H27UDG8VEM (16GB, 4CE)",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0xad,
- .device_code = 0xde,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 8LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 224,
- .ecc_strength_in_bits = 12,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = 20,
- .tRLOH_in_ns = 5,
- .tRHOH_in_ns = 15,
- "H27UEG8YEM (32GB, 4CE)",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0xd7,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 4LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 218,
- .ecc_strength_in_bits = 12,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 10,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 15,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = 16,
- .tRLOH_in_ns = 5,
- .tRHOH_in_ns = 15,
- "MT29F32G08CBAAA (4GB, 1CE), MT29F64G08CFAAA (8GB, 2CE)",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0xd9,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 8LL*SZ_1G,
- .block_size_in_pages = 128,
- .page_total_size_in_bytes = 4*SZ_1K + 218,
- .ecc_strength_in_bits = 12,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 10,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 15,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = 16,
- .tRLOH_in_ns = 5,
- .tRHOH_in_ns = 15,
- "MT29F128G08CJAAA (16GB, 2CE)",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0x48,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 2LL*SZ_1G,
- .block_size_in_pages = 256,
- .page_total_size_in_bytes = 4*SZ_1K + 224,
- .ecc_strength_in_bits = 12,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = 20,
- .tRLOH_in_ns = 5,
- .tRHOH_in_ns = 15,
- "MT29F16G08CBABA (2GB, 1CE)",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0x68,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 4LL*SZ_1G,
- .block_size_in_pages = 256,
- .page_total_size_in_bytes = 4*SZ_1K + 224,
- .ecc_strength_in_bits = 12,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = 20,
- .tRLOH_in_ns = 5,
- .tRHOH_in_ns = 15,
- "MT29F32G08CBABA (4GB, 1CE); "
- "MT29F64G08CEABA (8GB, 2CE); "
- "MT29F64G08CFABA (8GB, 2CE)",
- },
- {
- .end_of_table = false,
- .manufacturer_code = 0x2c,
- .device_code = 0x88,
- .cell_technology = NAND_DEVICE_CELL_TECH_MLC,
- .chip_size_in_bytes = 8LL*SZ_1G,
- .block_size_in_pages = 256,
- .page_total_size_in_bytes = 4*SZ_1K + 224,
- .ecc_strength_in_bits = 12,
- .ecc_size_in_bytes = 512,
- .data_setup_in_ns = 15,
- .data_hold_in_ns = 10,
- .address_setup_in_ns = 20,
- .gpmi_sample_delay_in_ns = 6,
- .tREA_in_ns = 20,
- .tRLOH_in_ns = 5,
- .tRHOH_in_ns = 15,
- "MT29F128G08CJABA (16GB, 2CE); "
- "MT29F128G08CKABA (16GB, 2CE); "
- "MT29F256G08CUABA (32GB, 4CE)",
- },
- {true}
-};
-
-/*
- * The following macros make it convenient to extract information from an ID
- * byte array. All these macros begin with the prefix "ID_".
- *
- * Macros of the form:
- *
- * ID_GET_[<manufacturer>_[<modifier>_]]<field>
- *
- * extract the given field from an ID byte array. Macros of the form:
- *
- * ID_[<manufacturer>_[<modifier>_]]<field>_<meaning>
- *
- * contain the value for the given field that has the given meaning.
- *
- * If the <manufacturer> appears, it means this macro represents a view of this
- * field that is specific to the given manufacturer.
- *
- * If the <modifier> appears, it means this macro represents a view of this
- * field that the given manufacturer applies only under specific conditions.
- *
- * Here is a simple example:
- *
- * ID_PAGE_SIZE_CODE_2K
- *
- * This macro has the value of the "Page Size" field that indicates the page
- * size is 2K.
- *
- * A more complicated example:
- *
- * ID_SAMSUNG_6_BYTE_PAGE_SIZE_CODE_8K (0x2)
- *
- * This macro has the value of the "Page Size" field for Samsung parts that
- * indicates the page size is 8K. However, this interpretation is only correct
- * for devices that return 6 ID bytes.
- */
-
-/* Byte 1 ------------------------------------------------------------------- */
-
-#define ID_GET_BYTE_1(id) ((id)[0])
-
-#define ID_GET_MFR_CODE(id) ID_GET_BYTE_1(id)
-
-/* Byte 2 ------------------------------------------------------------------- */
-
-#define ID_GET_BYTE_2(id) ((id)[1])
-
-#define ID_GET_DEVICE_CODE(id) ID_GET_BYTE_2(id)
- #define ID_SAMSUNG_DEVICE_CODE_1_GBIT (0xf1)
- #define ID_SAMSUNG_DEVICE_CODE_2_GBIT (0xda)
- #define ID_HYNIX_DEVICE_CODE_ECC12 (0xd7)
- #define ID_HYNIX_DEVICE_CODE_ECC12_LARGE (0xde)
- #define ID_MICRON_DEVICE_CODE_ECC12 (0xd7) /* ECC12 */
- #define ID_MICRON_DEVICE_CODE_ECC12_LARGE (0xd9) /* ECC12 8GB/CE */
- #define ID_MICRON_DEVICE_CODE_ECC12_2GB_PER_CE (0x48) /* L63B 2GB/CE */
- #define ID_MICRON_DEVICE_CODE_ECC12_4GB_PER_CE (0x68) /* L63B 4GB/CE */
- #define ID_MICRON_DEVICE_CODE_ECC12_8GB_PER_CE (0x88) /* L63B 8GB/CE */
-
-/* Byte 3 ------------------------------------------------------------------- */
-
-#define ID_GET_BYTE_3(id) ((id)[2])
-
-#define ID_GET_DIE_COUNT_CODE(id) ((ID_GET_BYTE_3(id) >> 0) & 0x3)
-
-#define ID_GET_CELL_TYPE_CODE(id) ((ID_GET_BYTE_3(id) >> 2) & 0x3)
- #define ID_CELL_TYPE_CODE_SLC (0x0) /* All others => MLC. */
-
-#define ID_GET_SAMSUNG_SIMUL_PROG(id) ((ID_GET_BYTE_3(id) >> 4) & 0x3)
-
-#define ID_GET_MICRON_SIMUL_PROG(id) ((ID_GET_BYTE_3(id) >> 4) & 0x3)
-
-#define ID_GET_CACHE_PROGRAM(id) ((ID_GET_BYTE_3(id) >> 7) & 0x1)
-
-/* Byte 4 ------------------------------------------------------------------- */
-
-#define ID_GET_BYTE_4(id) ((id)[3])
- #define ID_HYNIX_BYTE_4_ECC12_DEVICE (0x25)
-
-#define ID_GET_PAGE_SIZE_CODE(id) ((ID_GET_BYTE_4(id) >> 0) & 0x3)
- #define ID_PAGE_SIZE_CODE_1K (0x0)
- #define ID_PAGE_SIZE_CODE_2K (0x1)
- #define ID_PAGE_SIZE_CODE_4K (0x2)
- #define ID_PAGE_SIZE_CODE_8K (0x3)
- #define ID_SAMSUNG_6_BYTE_PAGE_SIZE_CODE_8K (0x2)
-
-#define ID_GET_OOB_SIZE_CODE(id) ((ID_GET_BYTE_4(id) >> 2) & 0x1)
-
-#define ID_GET_BLOCK_SIZE_CODE(id) ((ID_GET_BYTE_4(id) >> 4) & 0x3)
-
-/* Byte 5 ------------------------------------------------------------------- */
-
-#define ID_GET_BYTE_5(id) ((id)[4])
- #define ID_MICRON_BYTE_5_ECC12 (0x84)
-
-#define ID_GET_SAMSUNG_ECC_LEVEL_CODE(id) ((ID_GET_BYTE_5(id) >> 4) & 0x7)
- #define ID_SAMSUNG_ECC_LEVEL_CODE_8 (0x03)
- #define ID_SAMSUNG_ECC_LEVEL_CODE_24 (0x05)
-
-#define ID_GET_PLANE_COUNT_CODE(id) ((ID_GET_BYTE_5(id) >> 2) & 0x3)
-
-/* Byte 6 ------------------------------------------------------------------- */
-
-#define ID_GET_BYTE_6(id) ((id)[5])
- #define ID_TOSHIBA_BYTE_6_PAGE_SIZE_CODE_8K (0x54)
- #define ID_TOSHIBA_BYTE_6_PAGE_SIZE_CODE_4K (0x13)
-
-#define ID_GET_SAMSUNG_DEVICE_VERSION_CODE(id) ((ID_GET_BYTE_6(id)>>0) & 0x7)
- #define ID_SAMSUNG_DEVICE_VERSION_CODE_40NM (0x01)
-
-/* -------------------------------------------------------------------------- */
-
-void nand_device_print_info(struct nand_device_info *info)
-{
- unsigned i;
- const char *mfr_name;
- const char *cell_technology_name;
- uint64_t chip_size;
- const char *chip_size_units;
- unsigned page_data_size_in_bytes;
- unsigned page_oob_size_in_bytes;
-
- /* Check for nonsense. */
-
- if (!info)
- return;
-
- /* Prepare the manufacturer name. */
-
- mfr_name = "Unknown";
-
- for (i = 0; nand_manuf_ids[i].id; i++) {
- if (nand_manuf_ids[i].id == info->manufacturer_code) {
- mfr_name = nand_manuf_ids[i].name;
- break;
- }
- }
-
- /* Prepare the name of the cell technology. */
-
- switch (info->cell_technology) {
- case NAND_DEVICE_CELL_TECH_SLC:
- cell_technology_name = "SLC";
- break;
- case NAND_DEVICE_CELL_TECH_MLC:
- cell_technology_name = "MLC";
- break;
- default:
- cell_technology_name = "Unknown";
- break;
- }
-
- /* Prepare the chip size. */
-
- if ((info->chip_size_in_bytes >= SZ_1G) &&
- !(info->chip_size_in_bytes % SZ_1G)) {
- chip_size = info->chip_size_in_bytes / ((uint64_t) SZ_1G);
- chip_size_units = "GiB";
- } else if ((info->chip_size_in_bytes >= SZ_1M) &&
- !(info->chip_size_in_bytes % SZ_1M)) {
- chip_size = info->chip_size_in_bytes / ((uint64_t) SZ_1M);
- chip_size_units = "MiB";
- } else {
- chip_size = info->chip_size_in_bytes;
- chip_size_units = "B";
- }
-
- /* Prepare the page geometry. */
-
- page_data_size_in_bytes = info->page_total_size_in_bytes & ~0x3ff;
- page_oob_size_in_bytes = info->page_total_size_in_bytes & 0x3ff;
-
- /* Print the information. */
-
- printk(KERN_INFO "Manufacturer : %s (0x%02x)\n", mfr_name,
- info->manufacturer_code);
- printk(KERN_INFO "Device Code : 0x%02x\n", info->device_code);
- printk(KERN_INFO "Cell Technology : %s\n", cell_technology_name);
- printk(KERN_INFO "Chip Size : %u %s\n", (u32)chip_size,
- chip_size_units);
- printk(KERN_INFO "Pages per Block : %u\n",
- info->block_size_in_pages);
- printk(KERN_INFO "Page Geometry : %u+%u\n", page_data_size_in_bytes,
- page_oob_size_in_bytes);
- printk(KERN_INFO "ECC Strength : %u bits\n",
- info->ecc_strength_in_bits);
- printk(KERN_INFO "ECC Size : %u B\n", info->ecc_size_in_bytes);
- printk(KERN_INFO "Data Setup Time : %u ns\n", info->data_setup_in_ns);
- printk(KERN_INFO "Data Hold Time : %u ns\n", info->data_hold_in_ns);
- printk(KERN_INFO "Address Setup Time: %u ns\n",
- info->address_setup_in_ns);
- printk(KERN_INFO "GPMI Sample Delay : %u ns\n",
- info->gpmi_sample_delay_in_ns);
- if (info->tREA_in_ns >= 0)
- printk(KERN_INFO "tREA : %u ns\n",
- info->tREA_in_ns);
- else
- printk(KERN_INFO "tREA : Unknown\n");
- if (info->tREA_in_ns >= 0)
- printk(KERN_INFO "tRLOH : %u ns\n",
- info->tRLOH_in_ns);
- else
- printk(KERN_INFO "tRLOH : Unknown\n");
- if (info->tREA_in_ns >= 0)
- printk(KERN_INFO "tRHOH : %u ns\n",
- info->tRHOH_in_ns);
- else
- printk(KERN_INFO "tRHOH : Unknown\n");
- if (info->description)
- printk(KERN_INFO "Description : %s\n", info->description);
- else
- printk(KERN_INFO "Description : <None>\n");
-
-}
-
-static struct nand_device_info *nand_device_info_search(
- struct nand_device_info *table, uint8_t mfr_code, uint8_t device_code)
-{
-
- for (; !table->end_of_table; table++) {
- if (table->manufacturer_code != mfr_code)
- continue;
- if (table->device_code != device_code)
- continue;
- return table;
- }
-
- return 0;
-
-}
-
-static struct nand_device_info *nand_device_info_fn_toshiba(const uint8_t id[])
-{
- struct nand_device_info *table;
-
- /* Check for an SLC device. */
-
- if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) {
- /* Type 2 */
- return nand_device_info_search(nand_device_info_table_type_2,
- ID_GET_MFR_CODE(id), ID_GET_DEVICE_CODE(id));
- }
-
- /*
- * Look for 8K page Toshiba MLC devices.
- *
- * The page size field in byte 4 can't be used because the field was
- * redefined in the 8K parts so the value meaning "8K page" is the same
- * as the value meaning "4K page" on the 4K page devices.
- *
- * The only identifiable difference between the 4K and 8K page Toshiba
- * devices with a device code of 0xd7 is the undocumented 6th ID byte.
- * The 4K device returns a value of 0x13 and the 8K a value of 0x54.
- * Toshiba has verified that this is an acceptable method to distinguish
- * the two device families.
- */
-
- if (ID_GET_BYTE_6(id) == ID_TOSHIBA_BYTE_6_PAGE_SIZE_CODE_8K) {
- /* Type 11 */
- table = nand_device_info_table_type_11;
- } else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
- /* Type 9 */
- table = nand_device_info_table_type_9;
- } else {
- /* Large MLC */
- table = nand_device_info_table_large_mlc;
- }
-
- return nand_device_info_search(table, ID_GET_MFR_CODE(id),
- ID_GET_DEVICE_CODE(id));
-
-}
-
-static struct nand_device_info *nand_device_info_fn_samsung(const uint8_t id[])
-{
- struct nand_device_info *table;
-
- /* Check for an MLC device. */
-
- if (ID_GET_CELL_TYPE_CODE(id) != ID_CELL_TYPE_CODE_SLC) {
-
- /* Is this a Samsung 8K Page MLC device with 16 bit ECC? */
- if ((ID_GET_SAMSUNG_ECC_LEVEL_CODE(id) ==
- ID_SAMSUNG_ECC_LEVEL_CODE_24) &&
- (ID_GET_PAGE_SIZE_CODE(id) ==
- ID_SAMSUNG_6_BYTE_PAGE_SIZE_CODE_8K)) {
- /* Type 15 */
- table = nand_device_info_table_type_15;
- }
- /* Is this a Samsung 42nm ECC8 device with a 6 byte ID? */
- else if ((ID_GET_SAMSUNG_ECC_LEVEL_CODE(id) ==
- ID_SAMSUNG_ECC_LEVEL_CODE_8) &&
- (ID_GET_SAMSUNG_DEVICE_VERSION_CODE(id) ==
- ID_SAMSUNG_DEVICE_VERSION_CODE_40NM)) {
- /* Type 9 */
- table = nand_device_info_table_type_9;
- } else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
- /* Type 8 */
- table = nand_device_info_table_type_8;
- } else {
- /* Large MLC */
- table = nand_device_info_table_large_mlc;
- }
-
- } else {
-
- /* Check the page size first. */
- if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
- /* Type 10 */
- table = nand_device_info_table_type_10;
- }
- /* Check the chip size. */
- else if (ID_GET_DEVICE_CODE(id) ==
- ID_SAMSUNG_DEVICE_CODE_1_GBIT) {
- if (!ID_GET_CACHE_PROGRAM(id)) {
- /*
- * 128 MiB Samsung chips without cache program
- * are Type 7.
- *
- * The K9F1G08U0B does not support multi-plane
- * program, so the if statement below cannot be
- * used to identify it.
- */
- table = nand_device_info_table_type_7;
-
- } else {
- /* Smaller sizes are Type 2 by default. */
- table = nand_device_info_table_type_2;
- }
- } else {
- /* Check number of simultaneously programmed pages. */
- if (ID_GET_SAMSUNG_SIMUL_PROG(id) &&
- ID_GET_PLANE_COUNT_CODE(id)) {
- /* Type 7 */
- table = nand_device_info_table_type_7;
- } else {
- /* Type 2 */
- table = nand_device_info_table_type_2;
- }
-
- }
-
- }
-
- return nand_device_info_search(table, ID_GET_MFR_CODE(id),
- ID_GET_DEVICE_CODE(id));
-
-}
-
-static struct nand_device_info *nand_device_info_fn_stmicro(const uint8_t id[])
-{
- struct nand_device_info *table;
-
- /* Check for an SLC device. */
-
- if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC)
- /* Type 2 */
- table = nand_device_info_table_type_2;
- else
- /* Large MLC */
- table = nand_device_info_table_large_mlc;
-
- return nand_device_info_search(table, ID_GET_MFR_CODE(id),
- ID_GET_DEVICE_CODE(id));
-
-}
-
-static struct nand_device_info *nand_device_info_fn_hynix(const uint8_t id[])
-{
- struct nand_device_info *table;
-
- /* Check for an SLC device. */
-
- if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) {
- /* Type 2 */
- return nand_device_info_search(nand_device_info_table_type_2,
- ID_GET_MFR_CODE(id), ID_GET_DEVICE_CODE(id));
- }
-
- /*
- * Check for ECC12 devices.
- *
- * We look at the 4th ID byte to distinguish some Hynix ECC12 devices
- * from the similar ECC8 part. For example H27UBG8T2M (ECC12) 4th byte
- * is 0x25, whereas H27UDG8WFM (ECC8) 4th byte is 0xB6.
- */
-
- if ((ID_GET_DEVICE_CODE(id) == ID_HYNIX_DEVICE_CODE_ECC12 &&
- ID_GET_BYTE_4(id) == ID_HYNIX_BYTE_4_ECC12_DEVICE) ||
- (ID_GET_DEVICE_CODE(id) == ID_HYNIX_DEVICE_CODE_ECC12_LARGE)) {
- /* BCH ECC 12 */
- table = nand_device_info_table_bch_ecc12;
- } else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
- /*
- * So far, all other Samsung and Hynix 4K page devices are
- * Type 8.
- */
- table = nand_device_info_table_type_8;
- } else
- /* Large MLC */
- table = nand_device_info_table_large_mlc;
-
- return nand_device_info_search(table, ID_GET_MFR_CODE(id),
- ID_GET_DEVICE_CODE(id));
-
-}
-
-static struct nand_device_info *nand_device_info_fn_micron(const uint8_t id[])
-{
- struct nand_device_info *table;
-
- /* Check for an SLC device. */
-
- if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) {
-
- /* Check number of simultaneously programmed pages. */
-
- if (ID_GET_MICRON_SIMUL_PROG(id)) {
- /* Type 7 */
- table = nand_device_info_table_type_7;
- } else {
- /* Zero simultaneously programmed pages means Type 2. */
- table = nand_device_info_table_type_2;
- }
-
- return nand_device_info_search(table, ID_GET_MFR_CODE(id),
- ID_GET_DEVICE_CODE(id));
-
- }
-
- /*
- * We look at the 5th ID byte to distinguish some Micron ECC12 NANDs
- * from the similar ECC8 part.
- *
- * For example MT29F64G08CFAAA (ECC12) 5th byte is 0x84, whereas
- * MT29F64G08TAA (ECC8) 5th byte is 0x78.
- *
- * We also have a special case for the Micron L63B family
- * (256 page/block), which has unique device codes but no ID fields that
- * can easily be used to distinguish the family.
- */
-
- if ((ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12 &&
- ID_GET_BYTE_5(id) == ID_MICRON_BYTE_5_ECC12) ||
- (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_LARGE) ||
- (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_2GB_PER_CE) ||
- (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_4GB_PER_CE) ||
- (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_8GB_PER_CE)) {
- /* BCH ECC 12 */
- table = nand_device_info_table_bch_ecc12;
- } else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
- /* Toshiba devices with 4K pages are Type 9. */
- table = nand_device_info_table_type_9;
- } else {
- /* Large MLC */
- table = nand_device_info_table_large_mlc;
- }
-
- return nand_device_info_search(table, ID_GET_MFR_CODE(id),
- ID_GET_DEVICE_CODE(id));
-
-}
-
-static struct nand_device_info *nand_device_info_fn_sandisk(const uint8_t id[])
-{
- struct nand_device_info *table;
-
- if (ID_GET_CELL_TYPE_CODE(id) != ID_CELL_TYPE_CODE_SLC) {
- /* Large MLC */
- table = nand_device_info_table_large_mlc;
- } else {
- /* Type 2 */
- table = nand_device_info_table_type_2;
- }
-
- return nand_device_info_search(table, ID_GET_MFR_CODE(id),
- ID_GET_DEVICE_CODE(id));
-
-}
-
-static struct nand_device_info *nand_device_info_fn_intel(const uint8_t id[])
-{
- struct nand_device_info *table;
-
- /* Check for an SLC device. */
-
- if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) {
- /* Type 2 */
- return nand_device_info_search(nand_device_info_table_type_2,
- ID_GET_MFR_CODE(id), ID_GET_DEVICE_CODE(id));
- }
-
- if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) {
- /* Type 9 */
- table = nand_device_info_table_type_9;
- } else {
- /* Large MLC */
- table = nand_device_info_table_large_mlc;
- }
-
- return nand_device_info_search(table, ID_GET_MFR_CODE(id),
- ID_GET_DEVICE_CODE(id));
-
-}
-
-/**
- * struct nand_device_type_info - Information about a NAND Flash type.
- *
- * @name: A human-readable name for this type.
- * @table: The device info table for this type.
- */
-
-struct nand_device_type_info {
- struct nand_device_info *table;
- const char *name;
-};
-
-/*
- * A table that maps manufacturer IDs to device information tables.
- */
-
-static struct nand_device_type_info nand_device_type_directory[] =
-{
- {nand_device_info_table_type_2, "Type 2" },
- {nand_device_info_table_large_mlc, "Large MLC"},
- {nand_device_info_table_type_7, "Type 7" },
- {nand_device_info_table_type_8, "Type 8" },
- {nand_device_info_table_type_9, "Type 9" },
- {nand_device_info_table_type_10, "Type 10" },
- {nand_device_info_table_type_11, "Type 11" },
- {nand_device_info_table_type_15, "Type 15" },
- {nand_device_info_table_bch_ecc12, "BCH ECC12"},
- {0, 0},
-};
-
-/**
- * struct nand_device_mfr_info - Information about a NAND Flash manufacturer.
- *
- * @id: The value of the first NAND Flash ID byte, which identifies the
- * manufacturer.
- * @fn: A pointer to a function to use for identifying devices from the
- * given manufacturer.
- */
-
-struct nand_device_mfr_info {
- uint8_t id;
- struct nand_device_info *(*fn)(const uint8_t id[]);
-};
-
-/*
- * A table that maps manufacturer IDs to device information tables.
- */
-
-static struct nand_device_mfr_info nand_device_mfr_directory[] =
-{
- {
- .id = NAND_MFR_TOSHIBA,
- .fn = nand_device_info_fn_toshiba,
- },
- {
- .id = NAND_MFR_SAMSUNG,
- .fn = nand_device_info_fn_samsung,
- },
- {
- .id = NAND_MFR_FUJITSU,
- .fn = 0,
- },
- {
- .id = NAND_MFR_NATIONAL,
- .fn = 0,
- },
- {
- .id = NAND_MFR_RENESAS,
- .fn = 0,
- },
- {
- .id = NAND_MFR_STMICRO,
- .fn = nand_device_info_fn_stmicro,
- },
- {
- .id = NAND_MFR_HYNIX,
- .fn = nand_device_info_fn_hynix,
- },
- {
- .id = NAND_MFR_MICRON,
- .fn = nand_device_info_fn_micron,
- },
- {
- .id = NAND_MFR_AMD,
- .fn = 0,
- },
- {
- .id = NAND_MFR_SANDISK,
- .fn = nand_device_info_fn_sandisk,
- },
- {
- .id = NAND_MFR_INTEL,
- .fn = nand_device_info_fn_intel,
- },
- {0, 0}
-};
-
-/**
- * nand_device_info_test_table - Validate a device info table.
- *
- * This function runs tests on the given device info table to check that it
- * meets the current assumptions.
- */
-
-static void nand_device_info_test_table(
- struct nand_device_info *table, const char * name)
-{
- unsigned i;
- unsigned j;
- uint8_t mfr_code;
- uint8_t device_code;
-
- /* Loop over entries in this table. */
-
- for (i = 0; !table[i].end_of_table; i++) {
-
- /* Get discriminating attributes of the current device. */
-
- mfr_code = table[i].manufacturer_code;
- device_code = table[i].device_code;
-
- /* Compare with the remaining devices in this table. */
-
- for (j = i + 1; !table[j].end_of_table; j++) {
- if ((mfr_code == table[j].manufacturer_code) &&
- (device_code == table[j].device_code))
- goto error;
- }
-
- }
-
- return;
-
-error:
-
- printk(KERN_EMERG
- "\n== NAND Flash device info table failed validity check ==\n");
-
- printk(KERN_EMERG "\nDevice Info Table: %s\n", name);
- printk(KERN_EMERG "\nTable Index %u\n", i);
- nand_device_print_info(table + i);
- printk(KERN_EMERG "\nTable Index %u\n", j);
- nand_device_print_info(table + j);
- printk(KERN_EMERG "\n");
-
- BUG();
-
-}
-
-/**
- * nand_device_info_test_data - Test the NAND Flash device data.
- */
-
-static void nand_device_info_test_data(void)
-{
-
- unsigned i;
-
- for (i = 0; nand_device_type_directory[i].name; i++) {
- nand_device_info_test_table(
- nand_device_type_directory[i].table,
- nand_device_type_directory[i].name);
- }
-
-}
-
-struct nand_device_info *nand_device_get_info(const uint8_t id[])
-{
- unsigned i;
- uint8_t mfr_id = ID_GET_MFR_CODE(id);
- struct nand_device_info *(*fn)(const uint8_t id[]) = 0;
-
- /* Test the data. */
-
- nand_device_info_test_data();
-
- /* Look for information about this manufacturer. */
-
- for (i = 0; nand_device_mfr_directory[i].id; i++) {
- if (nand_device_mfr_directory[i].id == mfr_id) {
- fn = nand_device_mfr_directory[i].fn;
- break;
- }
- }
-
- if (!fn)
- return 0;
-
- /*
- * If control arrives here, we found both a table of device information,
- * and a function we can use to identify the current device. Attempt to
- * identify the device and return the result.
- */
-
- return fn(id);
-
-}
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __DRIVERS_NAND_DEVICE_INFO_H
-#define __DRIVERS_NAND_DEVICE_INFO_H
-
- /*
- * The number of ID bytes to read from the NAND Flash device and hand over to
- * the identification system.
- */
-
-#define NAND_DEVICE_ID_BYTE_COUNT (6)
-
-#define bool int
-#define false 0
-#define true 1
-
- /*
- * The number of ID bytes to read from the NAND Flash device and hand over to
- * the identification system.
- */
-
-enum nand_device_cell_technology {
- NAND_DEVICE_CELL_TECH_SLC = 0,
- NAND_DEVICE_CELL_TECH_MLC = 1,
-};
-
-/**
- * struct nand_device_info - Information about a single NAND Flash device.
- *
- * This structure contains all the *essential* information about a NAND Flash
- * device, derived from the device's data sheet. For each manufacturer, we have
- * an array of these structures.
- *
- * @end_of_table: If true, marks the end of a table of device
- * information.
- * @manufacturer_code: The manufacturer code (1st ID byte) reported by
- * the device.
- * @device_code: The device code (2nd ID byte) reported by the
- * device.
- * @cell_technology: The storage cell technology.
- * @chip_size_in_bytes: The total size of the storage behind a single
- * chip select, in bytes. Notice that this is *not*
- * necessarily the total size of the storage in a
- * *package*, which may contain several chips.
- * @block_size_in_pages: The number of pages in a block.
- * @page_total_size_in_bytes: The total size of a page, in bytes, including
- * both the data and the OOB.
- * @ecc_strength_in_bits: The strength of the ECC called for by the
- * manufacturer, in number of correctable bits.
- * @ecc_size_in_bytes: The size of the data block over which the
- * manufacturer calls for the given ECC algorithm
- * and strength.
- * @data_setup_in_ns: The data setup time, in nanoseconds. Usually the
- * maximum of tDS and tWP. A negative value
- * indicates this characteristic isn't known.
- * @data_hold_in_ns: The data hold time, in nanoseconds. Usually the
- * maximum of tDH, tWH and tREH. A negative value
- * indicates this characteristic isn't known.
- * @address_setup_in_ns: The address setup time, in nanoseconds. Usually
- * the maximum of tCLS, tCS and tALS. A negative
- * value indicates this characteristic isn't known.
- * @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative
- * value indicates this characteristic isn't known.
- * @tREA_in_ns: tREA, in nanoseconds, from the data sheet. A
- * negative value indicates this characteristic
- * isn't known.
- * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet. A
- * negative value indicates this characteristic
- * isn't known.
- * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet. A
- * negative value indicates this characteristic
- * isn't known.
- */
-
-struct nand_device_info {
-
- /* End of table marker */
-
- bool end_of_table;
-
- /* Manufacturer and Device codes */
-
- uint8_t manufacturer_code;
- uint8_t device_code;
-
- /* Technology */
-
- enum nand_device_cell_technology cell_technology;
-
- /* Geometry */
-
- uint64_t chip_size_in_bytes;
- uint32_t block_size_in_pages;
- uint16_t page_total_size_in_bytes;
-
- /* ECC */
-
- uint8_t ecc_strength_in_bits;
- uint16_t ecc_size_in_bytes;
-
- /* Timing */
-
- int8_t data_setup_in_ns;
- int8_t data_hold_in_ns;
- int8_t address_setup_in_ns;
- int8_t gpmi_sample_delay_in_ns;
- int8_t tREA_in_ns;
- int8_t tRLOH_in_ns;
- int8_t tRHOH_in_ns;
-
- /* Description */
-
- const char *description;
-
-};
-
-/**
- * nand_device_get_info - Get info about a device based on ID bytes.
- *
- * @id_bytes: An array of NAND_DEVICE_ID_BYTE_COUNT ID bytes retrieved from the
- * NAND Flash device.
- */
-
-struct nand_device_info *nand_device_get_info(const uint8_t id_bytes[]);
-
-/**
- * nand_device_print_info - Prints information about a NAND Flash device.
- *
- * @info A pointer to a NAND Flash device information structure.
- */
-
-void nand_device_print_info(struct nand_device_info *info);
-
-#endif
COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
-<<<<<<< HEAD
-COBJS-$(CONFIG_IMX_ECSPI) += imx_ecspi.o
-COBJS-$(CONFIG_IMX_CSPI) += imx_cspi.o
-COBJS-$(CONFIG_IMX_SPI_PMIC) += imx_spi_pmic.o
-COBJS-$(CONFIG_IMX_SPI_CPLD) += imx_spi_cpld.o
-=======
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
COBJS-$(CONFIG_TEGRA2_SPI) += tegra2_spi.o
->>>>>>> 9a3aae22edf1eda6326cc51c28631ca5c23b7706
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
+++ /dev/null
-/*
- * Copyright (C) 2008 Embedded Alley Solutions Inc.
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * Clock control register descriptions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef CLKCTRL_H
-#define CLKCTRL_H
-
-#include <asm/arch/mx23.h>
-
-#define CLKCTRL_BASE (MX23_REGS_BASE + 0x40000)
-
-#define CLKCTRL_PLLCTRL0 0x000
-#define CLKCTRL_PLLCTRL1 0x010
-#define CLKCTRL_CPU 0x020
-#define CLKCTRL_HBUS 0x030
-#define CLKCTRL_XBUS 0x040
-#define CLKCTRL_XTAL 0x050
-#define CLKCTRL_PIX 0x060
-#define CLKCTRL_SSP 0x070
-#define CLKCTRL_GPMI 0x080
-#define CLKCTRL_SPDIF 0x090
-#define CLKCTRL_EMI 0x0a0
-#define CLKCTRL_IR 0x0b0
-#define CLKCTRL_SAIF 0x0c0
-#define CLKCTRL_TV 0x0d0
-#define CLKCTRL_ETM 0x0e0
-#define CLKCTRL_FRAC 0x0f0
-#define CLKCTRL_FRAC1 0x100
-#define CLKCTRL_CLKSEQ 0x110
-#define CLKCTRL_RESET 0x120
-#define CLKCTRL_STATUS 0x130
-#define CLKCTRL_VERSION 0x140
-
-/* CLKCTRL_SSP register bits, bit fields and values */
-#define SSP_CLKGATE (1 << 31)
-#define SSP_BUSY (1 << 29)
-#define SSP_DIV_FRAC_EN (1 << 9)
-#define SSP_DIV 0
-
-/* CLKCTRL_FRAC register bits, bit fields and values */
-#define FRAC_CLKGATEIO (1 << 31)
-#define FRAC_IOFRAC 24
-
-/* CLKCTRL_FRAC register bits, bit fields and values */
-#define CLKSEQ_BYPASS_SSP (1 << 5)
-
-#endif /* CLKCTRL_H */
+++ /dev/null
-/*
- * Copyright (C) 2008 Embedded Alley Solutions Inc.
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * Debug UART register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef DBGUART_H
-#define DBGUART_H
-
-#include <asm/arch/mx23.h>
-
-#define DBGUART_BASE (MX23_REGS_BASE + 0x00070000)
-
-#endif /* DBGUART_H */
+++ /dev/null
-/*
- * Copyright (C) 2008 Embedded Alley Solutions Inc.
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef MX23_H
-#define MX23_H
-
-/*
- * Most of 378x SoC registers are associated with four addresses
- * used for different operations - read/write, set, clear and toggle bits.
- *
- * Some of registers do not implement such feature and, thus, should be
- * accessed/manipulated via single address in common way.
- */
-#define REG_RD(x) (*(volatile unsigned int *)(x))
-#define REG_WR(x, v) ((*(volatile unsigned int *)(x)) = (v))
-#define REG_SET(x, v) ((*(volatile unsigned int *)((x) + 0x04)) = (v))
-#define REG_CLR(x, v) ((*(volatile unsigned int *)((x) + 0x08)) = (v))
-#define REG_TOG(x, v) ((*(volatile unsigned int *)((x) + 0x0c)) = (v))
-
-#define MX23_OCRAM_BASE 0x00000000
-#define MX23_SDRAM_BASE 0x40000000
-#define MX23_REGS_BASE 0x80000000
-
-#endif /* STMP378X_H */
+++ /dev/null
-/* Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * On-Chip OTP register descriptions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef OCOTP_H
-#define OCOTP_H
-
-#include <asm/arch/mx23.h>
-
-#define OCOTP_BASE (MX23_REGS_BASE + 0x2c000)
-
-#define OCOTP_CTRL 0x000
-#define OCOTP_CTRL_SET 0x004
-#define OCOTP_CTRL_CLR 0x008
-#define OCOTP_CTRL_TOG 0x00c
-#define OCOTP_DATA 0x010
-#define OCOTP_CUST0 0x020
-#define OCOTP_CUST1 0x030
-#define OCOTP_CUST2 0x040
-#define OCOTP_CUST3 0x050
-#define OCOTP_CRYPTO1 0x070
-#define OCOTP_CRYPTO2 0x080
-#define OCOTP_CRYPTO3 0x090
-#define OCOTP_HWCAP0 0x0a0
-#define OCOTP_HWCAP1 0x0b0
-#define OCOTP_HWCAP2 0x0c0
-#define OCOTP_HWCAP3 0x0d0
-#define OCOTP_HWCAP4 0x0e0
-#define OCOTP_HWCAP5 0x0f0
-#define OCOTP_SWCAP 0x100
-#define OCOTP_CUSTCAP 0x110
-#define OCOTP_LOCK 0x120
-#define OCOTP_OPS0 0x130
-#define OCOTP_OPS1 0x140
-#define OCOTP_OPS2 0x150
-#define OCOTP_OPS3 0x160
-#define OCOTP_UN0 0x170
-#define OCOTP_UN1 0x180
-#define OCOTP_UN2 0x190
-#define OCOTP_ROM0 0x1a0
-#define OCOTP_ROM1 0x1b0
-#define OCOTP_ROM2 0x1c0
-#define OCOTP_ROM3 0x1d0
-#define OCOTP_ROM4 0x1e0
-#define OCOTP_ROM5 0x1f0
-#define OCOTP_ROM6 0x200
-#define OCOTP_ROM7 0x210
-#define OCOTP_VERSION 0x220
-
-
-/* OCOTP_CTRL register bits, bit fields and values */
-#define CTRL_RD_BANK_OPEN (1 << 12)
-#define CTRL_BUSY (8 << 12)
-
-#endif /* OCOTP_H */
+++ /dev/null
-/*
- * Copyright (C) 2008 Embedded Alley Solutions Inc.
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * Clock control register descriptions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef PINMUX_H
-#define PINMUX_H
-
-#include <asm/arch/mx23.h>
-
-#define PINCTRL_BASE (MX23_REGS_BASE + 0x18000)
-
-#define PINCTRL_CTRL 0x000
-#define PINCTRL_MUXSEL(n) (0x100 + 0x10*(n))
-#define PINCTRL_DRIVE(n) (0x200 + 0x10*(n))
-#define PINCTRL_PULL(n) (0x400 + 0x10*(n))
-#define PINCTRL_DOUT(n) (0x500 + 0x10*(n))
-#define PINCTRL_DIN(n) (0x600 + 0x10*(n))
-#define PINCTRL_DOE(n) (0x700 + 0x10*(n))
-#define PINCTRL_PIN2IRQ(n) (0x800 + 0x10*(n))
-#define PINCTRL_IRQEN(n) (0x900 + 0x10*(n))
-#define PINCTRL_IRQLEVEL(n) (0xa00 + 0x10*(n))
-#define PINCTRL_IRQPOL(n) (0xb00 + 0x10*(n))
-#define PINCTRL_IRQSTAT(n) (0xc00 + 0x10*(n))
-
-#endif /* PINMUX_H */
+++ /dev/null
-/*
- * Copyright (C) 2008 Embedded Alley Solutions Inc.
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * SSP/SPI driver
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef SPI_H
-#define SPI_H
-
-#include <config.h>
-#include <common.h>
-#include <asm/arch/ssp.h>
-
-/*
- * Flags to set SPI mode
- */
-#define SPI_PHASE 0x1 /* Set phase to 1 */
-#define SPI_POLARITY 0x2 /* Set polarity to 1 */
-
-/* Various flags to control SPI transfers */
-#define SPI_START 0x1 /* Lock CS signal */
-#define SPI_STOP 0x2 /* Unlock CS signal */
-
-/*
- * Init SSPx interface, must be called first
- */
-void spi_init(void);
-
-/*
- * Set phase, polarity and CS number (SS0, SS1, SS2)
- */
-void spi_set_cfg(unsigned int bus, unsigned int cs, unsigned long mode);
-
-
-/*
- * Send @rx_len bytes from @dout, then receive @rx_len bytes
- * saving them to @din
- */
-void spi_txrx(const char *dout, unsigned int tx_len, char *din,
- unsigned int rx_len, unsigned long flags);
-
-
-/* Lock/unlock SPI bus */
-static inline void spi_lock(void)
-{
- disable_interrupts();
-}
-
-static inline void spi_unlock(void)
-{
- enable_interrupts();
-}
-
-#endif /* SPI_H */
+++ /dev/null
-/*
- * Copyright (C) 2008 Embedded Alley Solutions Inc.
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * SSP register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef SSP_H
-#define SSP_H
-
-#include <asm/arch/mx23.h>
-
-#define SSP1_BASE (MX23_REGS_BASE + 0x10000)
-#define SSP2_BASE (MX23_REGS_BASE + 0x34000)
-
-#define SSP_CTRL0 0x000
-#define SSP_CMD0 0x010
-#define SSP_CMD1 0x020
-#define SSP_COMPREF 0x030
-#define SSP_COMPMASK 0x040
-#define SSP_TIMING 0x050
-#define SSP_CTRL1 0x060
-#define SSP_DATA 0x070
-#define SSP_SDRESP0 0x080
-#define SSP_SDRESP1 0x090
-#define SSP_SDRESP2 0x0a0
-#define SSP_SDRESP3 0x0b0
-#define SSP_STATUS 0x0c0
-#define SSP_DEBUG 0x100
-#define SSP_VERSION 0x110
-
-/* CTRL0 bits, bit fields and values */
-#define CTRL0_SFTRST (0x1 << 31)
-#define CTRL0_CLKGATE (0x1 << 30)
-#define CTRL0_RUN (0x1 << 29)
-#define CTRL0_LOCK_CS (0x1 << 27)
-#define CTRL0_IGNORE_CRC (0x1 << 26)
-#define CTRL0_DATA_XFER (0x1 << 24)
-#define CTRL0_READ (0x1 << 25)
-#define CTRL0_BUS_WIDTH 22
-#define CTRL0_WAIT_FOR_IRQ (0x1 << 21)
-#define CTRL0_WAIT_FOR_CMD (0x1 << 20)
-#define CTRL0_XFER_COUNT 0
-
-#define BUS_WIDTH_SPI1 (0x0 << CTRL0_BUS_WIDTH)
-#define BUS_WIDTH_SPI4 (0x1 << CTRL0_BUS_WIDTH)
-#define BUS_WIDTH_SPI8 (0x2 << CTRL0_BUS_WIDTH)
-
-#define SPI_CS0 0x0
-#define SPI_CS1 CTRL0_WAIT_FOR_CMD
-#define SPI_CS2 CTRL0_WAIT_FOR_IRQ
-#define SPI_CS_CLR_MASK (CTRL0_WAIT_FOR_CMD | CTRL0_WAIT_FOR_IRQ)
-
-/* CMD0 bits, bit fields and values */
-#define CMD0_BLOCK_SIZE 16
-#define CMD0_BLOCK_COUNT 12
-#define CMD0_CMD 0
-
-/* TIMING bits, bit fields and values */
-#define TIMING_TIMEOUT 16
-#define TIMING_CLOCK_DIVIDE 8
-#define TIMING_CLOCK_RATE 0
-
-/* CTRL1 bits, bit fields and values */
-#define CTRL1_DMA_ENABLE (0x1 << 13)
-#define CTRL1_PHASE (0x1 << 10)
-#define CTRL1_POLARITY (0x1 << 9)
-#define CTRL1_SLAVE_MODE (0x1 << 8)
-#define CTRL1_WORD_LENGTH 4
-#define CTRL1_SSP_MODE 0
-
-#define WORD_LENGTH4 (0x3 << CTRL1_WORD_LENGTH)
-#define WORD_LENGTH8 (0x7 << CTRL1_WORD_LENGTH)
-#define WORD_LENGTH16 (0xF << CTRL1_WORD_LENGTH)
-
-#define SSP_MODE_SPI (0x0 << CTRL1_SSP_MODE)
-#define SSP_MODE_SSI (0x1 << CTRL1_SSP_MODE)
-#define SSP_MODE_SD_MMC (0x3 << CTRL1_SSP_MODE)
-#define SSP_MODE_MS (0x4 << CTRL1_SSP_MODE)
-#define SSP_MODE_ATA (0x7 << CTRL1_SSP_MODE)
-
-/* CTRL1 bits, bit fields and values */
-#define STATUS_FIFO_EMPTY (1 << 5)
-#define STATUS_FIFO_FULL (1 << 8)
-
-#endif /* SSP_H */
+++ /dev/null
-/*
- * Copyright (C) 2008 Embedded Alley Solutions Inc.
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * Timers and rotary encoder register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef TIMROT_H
-#define TIMROT_H
-
-#include <asm/arch/mx23.h>
-
-#define TIMROT_BASE (MX23_REGS_BASE + 0x00068000)
-
-/* Timer and rotary encoder register offsets */
-#define ROTCTRL 0x0
-#define ROTCOUNT 0x10
-#define TIMCTRL0 0x20
-#define TIMCOUNT0 0x30
-#define TIMCTRL1 0x40
-#define TIMCOUNT1 0x50
-#define TIMCTRL2 0x60
-#define TIMCOUNT2 0x70
-#define TIMCTRL3 0x80
-#define TIMCTRL3 0x90
-
-/* TIMCTRL bits, bit fields and values */
-#define TIMCTRL_SELECT 0
-#define TIMCTRL_PRESCALE 4
-#define TIMCTRL_RELOAD (1 << 6)
-#define TIMCTRL_UPDATE (1 << 7)
-#define TIMCTRL_POLARITY (1 << 8)
-#define TIMCTRL_IRQEN (1 << 14)
-#define TIMCTRL_IRQ (1 << 15)
-
-#define TIMCTRL_SELECT_PWM0 (0x1 << TIMCTRL_SELECT)
-#define TIMCTRL_SELECT_PWM1 (0x2 << TIMCTRL_SELECT)
-#define TIMCTRL_SELECT_PWM2 (0x3 << TIMCTRL_SELECT)
-#define TIMCTRL_SELECT_PWM3 (0x4 << TIMCTRL_SELECT)
-#define TIMCTRL_SELECT_PWM4 (0x5 << TIMCTRL_SELECT)
-#define TIMCTRL_SELECT_ROTARYA (0x6 << TIMCTRL_SELECT)
-#define TIMCTRL_SELECT_ROTARYB (0x7 << TIMCTRL_SELECT)
-#define TIMCTRL_SELECT_32KHZ (0x8 << TIMCTRL_SELECT)
-#define TIMCTRL_SELECT_8KHZ (0x9 << TIMCTRL_SELECT)
-#define TIMCTRL_SELECT_4KHZ (0xa << TIMCTRL_SELECT)
-#define TIMCTRL_SELECT_1KHZ (0xb << TIMCTRL_SELECT)
-#define TIMCTRL_SELECT_ALWAYS (0xc << TIMCTRL_SELECT)
-
-#endif /* TIMROT_H */
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __MACH_MX25_GPIO_H__
-#define __MACH_MX25_GPIO_H__
-
-#include <asm/arch/mx25.h>
-
-static void _set_gpio_direction(u32 port, u32 index, int is_input);
-
-void mxc_set_gpio_direction(iomux_pin_name_t pin, int is_input);
-
-static void _set_gpio_dataout(u32 port, u32 index, u32 data);
-
-void mxc_set_gpio_dataout(iomux_pin_name_t pin, u32 data);
-
-/*!
- * @file mach-mx25/gpio.h
- *
- * @brief Simple GPIO definitions and functions
- *
- * @ingroup GPIO_MX25
- */
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _IMX_SPI_CPLD_H_
-#define _IMX_SPI_CPLD_H_
-
-#include <linux/types.h>
-
-#define PBC_LED_CTRL 0x20000
-#define PBC_SB_STAT 0x20008
-#define PBC_ID_AAAA 0x20040
-#define PBC_ID_5555 0x20048
-#define PBC_VERSION 0x20050
-#define PBC_ID_CAFE 0x20058
-#define PBC_INT_STAT 0x20010
-#define PBC_INT_MASK 0x20038
-#define PBC_INT_REST 0x20020
-#define PBC_SW_RESET 0x20060
-
-void cpld_reg_write(u32 offset, u32 val);
-u32 cpld_reg_read(u32 offset);
-struct spi_slave *spi_cpld_probe();
-void spi_cpld_free(struct spi_slave *slave);
-unsigned int cpld_reg_xfer(unsigned int reg, unsigned int val,
- unsigned int read);
-
-#endif /* _IMX_SPI_CPLD_H_ */
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __MACH_MX25_IOMUX_H__
-#define __MACH_MX25_IOMUX_H__
-
-#include <asm/arch/mx25.h>
-
-/*!
- * @file mach-mx25/iomux.h
- *
- * @brief I/O Muxing control definitions and functions
- *
- * @ingroup GPIO_MX25
- */
-
-/*!
- * IOMUX functions
- * SW_MUX_CTL
- */
-typedef enum iomux_pin_config {
- MUX_CONFIG_FUNC = 0, /*!< used as function */
- MUX_CONFIG_ALT1, /*!< used as alternate function 1 */
- MUX_CONFIG_ALT2, /*!< used as alternate function 2 */
- MUX_CONFIG_ALT3, /*!< used as alternate function 3 */
- MUX_CONFIG_ALT4, /*!< used as alternate function 4 */
- MUX_CONFIG_ALT5, /*!< used as alternate function 5 */
- MUX_CONFIG_ALT6, /*!< used as alternate function 6 */
- MUX_CONFIG_ALT7, /*!< used as alternate function 7 */
- MUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
- MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /*!< used as GPIO */
-} iomux_pin_cfg_t;
-
-/*!
- * IOMUX pad functions
- * SW_PAD_CTL
- */
-typedef enum iomux_pad_config {
- PAD_CTL_DRV_3_3V = 0x0 << 13,
- PAD_CTL_DRV_1_8V = 0x1 << 13,
- PAD_CTL_HYS_CMOS = 0x0 << 8,
- PAD_CTL_HYS_SCHMITZ = 0x1 << 8,
- PAD_CTL_PKE_NONE = 0x0 << 7,
- PAD_CTL_PKE_ENABLE = 0x1 << 7,
- PAD_CTL_PUE_KEEPER = 0x0 << 6,
- PAD_CTL_PUE_PUD = 0x1 << 6,
- PAD_CTL_100K_PD = 0x0 << 4,
- PAD_CTL_47K_PU = 0x1 << 4,
- PAD_CTL_100K_PU = 0x2 << 4,
- PAD_CTL_22K_PU = 0x3 << 4,
- PAD_CTL_ODE_CMOS = 0x0 << 3,
- PAD_CTL_ODE_OpenDrain = 0x1 << 3,
- PAD_CTL_DRV_NORMAL = 0x0 << 1,
- PAD_CTL_DRV_HIGH = 0x1 << 1,
- PAD_CTL_DRV_MAX = 0x2 << 1,
- PAD_CTL_SRE_SLOW = 0x0 << 0,
- PAD_CTL_SRE_FAST = 0x1 << 0
-} iomux_pad_config_t;
-
-/*!
- * IOMUX general purpose functions
- * IOMUXC_GPR1
- */
-typedef enum iomux_gp_func {
- MUX_SDCTL_CSD0_SEL = 0x1 << 0,
- MUX_SDCTL_CSD1_SEL = 0x1 << 1,
-} iomux_gp_func_t;
-
-/*!
- * IOMUX SELECT_INPUT register index
- * Base register is IOMUXSW_INPUT_CTL in iomux.c
- */
-typedef enum iomux_input_select {
- MUX_IN_AUDMUX_P4_INPUT_DA_AMX = 0,
- MUX_IN_AUDMUX_P4_INPUT_DB_AMX,
- MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX,
- MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX,
- MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX,
- MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX,
- MUX_IN_AUDMUX_P7_INPUT_DA_AMX,
- MUX_IN_AUDMUX_P7_INPUT_TXFS_AMX,
- MUX_IN_CAN1_IPP_IND_CANRX,
- MUX_IN_CAN2_IPP_IND_CANRX,
- MUX_IN_CSI_IPP_CSI_D_0,
- MUX_IN_CSI_IPP_CSI_D_1,
- MUX_IN_CSPI1_IPP_IND_SS3_B,
- MUX_IN_CSPI2_IPP_CSPI_CLK_IN,
- MUX_IN_CSPI2_IPP_IND_DATAREADY_B,
- MUX_IN_CSPI2_IPP_IND_MISO,
- MUX_IN_CSPI2_IPP_IND_MOSI,
- MUX_IN_CSPI2_IPP_IND_SS0_B,
- MUX_IN_CSPI2_IPP_IND_SS1_B,
- MUX_IN_CSPI3_IPP_CSPI_CLK_IN,
- MUX_IN_CSPI3_IPP_IND_DATAREADY_B,
- MUX_IN_CSPI3_IPP_IND_MISO,
- MUX_IN_CSPI3_IPP_IND_MOSI,
- MUX_IN_CSPI3_IPP_IND_SS0_B,
- MUX_IN_CSPI3_IPP_IND_SS1_B,
- MUX_IN_CSPI3_IPP_IND_SS2_B,
- MUX_IN_CSPI3_IPP_IND_SS3_B,
- MUX_IN_ESDHC1_IPP_DAT4_IN,
- MUX_IN_ESDHC1_IPP_DAT5_IN,
- MUX_IN_ESDHC1_IPP_DAT6_IN,
- MUX_IN_ESDHC1_IPP_DAT7_IN,
- MUX_IN_ESDHC2_IPP_CARD_CLK_IN,
- MUX_IN_ESDHC2_IPP_CMD_IN,
- MUX_IN_ESDHC2_IPP_DAT0_IN,
- MUX_IN_ESDHC2_IPP_DAT1_IN,
- MUX_IN_ESDHC2_IPP_DAT2_IN,
- MUX_IN_ESDHC2_IPP_DAT3_IN,
- MUX_IN_ESDHC2_IPP_DAT4_IN,
- MUX_IN_ESDHC2_IPP_DAT5_IN,
- MUX_IN_ESDHC2_IPP_DAT6_IN,
- MUX_IN_ESDHC2_IPP_DAT7_IN,
- MUX_IN_FEC_FEC_COL,
- MUX_IN_FEC_FEC_CRS,
- MUX_IN_FEC_FEC_RDATA_2,
- MUX_IN_FEC_FEC_RDATA_3,
- MUX_IN_FEC_FEC_RX_CLK,
- MUX_IN_FEC_FEC_RX_ER,
- MUX_IN_I2C2_IPP_SCL_IN,
- MUX_IN_I2C2_IPP_SDA_IN,
- MUX_IN_I2C3_IPP_SCL_IN,
- MUX_IN_I2C3_IPP_SDA_IN,
- MUX_IN_KPP_IPP_IND_COL_4,
- MUX_IN_KPP_IPP_IND_COL_5,
- MUX_IN_KPP_IPP_IND_COL_6,
- MUX_IN_KPP_IPP_IND_COL_7,
- MUX_IN_KPP_IPP_IND_ROW_4,
- MUX_IN_KPP_IPP_IND_ROW_5,
- MUX_IN_KPP_IPP_IND_ROW_6,
- MUX_IN_KPP_IPP_IND_ROW_7,
- MUX_IN_SIM1_PIN_SIM_RCVD1_IN,
- MUX_IN_SIM1_PIN_SIM_SIMPD1,
- MUX_IN_SIM1_SIM_RCVD1_IO,
- MUX_IN_SIM2_PIN_SIM_RCVD1_IN,
- MUX_IN_SIM2_PIN_SIM_SIMPD1,
- MUX_IN_SIM2_SIM_RCVD1_IO,
- MUX_IN_UART3_IPP_UART_RTS_B,
- MUX_IN_UART3_IPP_UART_RXD_MUX,
- MUX_IN_UART4_IPP_UART_RTS_B,
- MUX_IN_UART4_IPP_UART_RXD_MUX,
- MUX_IN_UART5_IPP_UART_RTS_B,
- MUX_IN_UART5_IPP_UART_RXD_MUX,
- MUX_IN_USB_TOP_IPP_IND_OTG_USB_OC,
- MUX_IN_USB_TOP_IPP_IND_UH2_USB_OC,
-} iomux_input_select_t;
-
-/*!
- * IOMUX input functions
- * SW_SELECT_INPUT bits 2-0
- */
-typedef enum iomux_input_config {
- INPUT_CTL_PATH0 = 0x0,
- INPUT_CTL_PATH1,
- INPUT_CTL_PATH2,
- INPUT_CTL_PATH3,
- INPUT_CTL_PATH4,
- INPUT_CTL_PATH5,
- INPUT_CTL_PATH6,
- INPUT_CTL_PATH7,
-} iomux_input_cfg_t;
-
-/*!
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param cfg an input function as defined in \b #iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
-
-/*!
- * Release ownership for an IO pin
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param cfg an input function as defined in \b #iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
-
-/*!
- * This function enables/disables the general purpose function for a particular
- * signal.
- *
- * @param gp one signal as defined in \b #iomux_gp_func_t
- * @param en \b #true to enable; \b #false to disable
- */
-void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en);
-
-/*!
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @param config the ORed value of elements defined in \b
- * #iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
-
-/*!
- * This function configures input path.
- *
- * @param input index of input select register as defined in \b
- * #iomux_input_select_t
- * @param config the binary value of elements defined in \b
- * #iomux_input_cfg_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-#endif
+++ /dev/null
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MX25_REGS_H
-#define __ASM_ARCH_MX25_REGS_H
-
-#define __REG(x) (*((volatile u32 *)(x)))
-#define __REG16(x) (*((volatile u16 *)(x)))
-#define __REG8(x) (*((volatile u8 *)(x)))
-
-/*
- * AIPS 1
- */
-#define AIPS1_BASE 0x43F00000
-#define AIPS1_CTRL_BASE AIPS1_BASE
-#define MAX_BASE 0x43F04000
-#define CLKCTL_BASE 0x43F08000
-#define ETB_SLOT4_BASE 0x43F0C000
-#define ETB_SLOT5_BASE 0x43F1000l
-#define ECT_CTIO_BASE 0x43F18000
-#define I2C1_BASE 0x43F80000
-#define I2C3_BASE 0x43F84000
-#define CAN1_BASE 0x43F88000
-#define CAN2_BASE 0x43F8C000
-#define UART1_BASE 0x43F90000
-#define UART2_BASE 0x43F94000
-#define I2C2_BASE 0x43F98000
-#define OWIRE_BASE 0x43F9C000
-#define CSPI1_BASE 0x43FA4000
-#define KPP_BASE 0x43FA8000
-#define IOMUXC_BASE 0x43FAC000
-#define AUDMUX_BASE 0x43FB0000
-#define ECT_IP1_BASE 0x43FB8000
-#define ECT_IP2_BASE 0x43FBC000
-
-/*
- * SPBA
- */
-#define SPBA_BASE 0x50000000
-#define CSPI3_BASE 0x50040000
-#define UART4_BASE 0x50008000
-#define UART3_BASE 0x5000C000
-#define CSPI2_BASE 0x50010000
-#define SSI2_BASE 0x50014000
-#define ESAI_BASE 0x50018000
-#define ATA_DMA_BASE 0x50020000
-#define SIM1_BASE 0x50024000
-#define SIM2_BASE 0x50028000
-#define UART5_BASE 0x5002C000
-#define TSC_BASE 0x50030000
-#define SSI1_BASE 0x50034000
-#define FEC_BASE 0x50038000
-#define SOC_FEC FEC_BASE
-#define SPBA_CTRL_BASE 0x5003C000
-
-/*
- * AIPS 2
- */
-#define AIPS2_BASE 0x53F00000
-#define AIPS2_CTRL_BASE AIPS2_BASE
-#define CCM_BASE 0x53F80000
-#define GPT4_BASE 0x53F84000
-#define GPT3_BASE 0x53F88000
-#define GPT2_BASE 0x53F8C000
-#define GPT1_BASE 0x53F90000
-#define EPIT1_BASE 0x53F94000
-#define EPIT2_BASE 0x53F98000
-#define GPIO4_BASE 0x53F9C000
-#define PWM2_BASE 0x53FA0000
-#define GPIO3_BASE 0x53FA4000
-#define PWM3_BASE 0x53FA8000
-#define SCC_BASE 0x53FAC000
-#define SCM_BASE 0x53FAE000
-#define SMN_BASE 0x53FAF000
-#define RNGD_BASE 0x53FB0000
-#define MMC_SDHC1_BASE 0x53FB4000
-#define MMC_SDHC2_BASE 0x53FB8000
-#define ESDHC1_REG_BASE MMC_SDHC1_BASE
-#define LCDC_BASE 0x53FBC000
-#define SLCDC_BASE 0x53FC0000
-#define PWM4_BASE 0x53FC8000
-#define GPIO1_BASE 0x53FCC000
-#define GPIO2_BASE 0x53FD0000
-#define SDMA_BASE 0x53FD4000
-#define WDOG_BASE 0x53FDC000
-#define PWM1_BASE 0x53FE0000
-#define RTIC_BASE 0x53FEC000
-#define IIM_BASE 0x53FF0000
-#define USB_BASE 0x53FF4000
-#define CSI_BASE 0x53FF8000
-#define DRYICE_BASE 0x53FFC000
-
-/*
- * ROMPATCH and ASIC
- */
-#define ROMPATCH_BASE 0x60000000
-#define ROMPATCH_REV 0x40
-#define ASIC_BASE 0x68000000
-
-#define RAM_BASE 0x78000000
-
-/*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
- */
-#define EXT_MEM_CTRL_BASE 0xB8000000
-#define ESDCTL_BASE 0xB8001000
-#define WEIM_BASE 0xB8002000
-#define WEIM_CTRL_CS0 WEIM_BASE
-#define WEIM_CTRL_CS1 (WEIM_BASE + 0x10)
-#define WEIM_CTRL_CS2 (WEIM_BASE + 0x20)
-#define WEIM_CTRL_CS3 (WEIM_BASE + 0x30)
-#define WEIM_CTRL_CS4 (WEIM_BASE + 0x40)
-#define WEIM_CTRL_CS5 (WEIM_BASE + 0x50)
-#define M3IF_BASE 0xB8003000
-#define EMI_BASE 0xB8004000
-
-#define NFC_BASE_ADDR 0xBB000000
-/*
- * Memory regions and CS
- */
-#define CSD0_BASE 0x80000000
-#define CSD1_BASE 0x90000000
-#define CS0_BASE 0xA0000000
-#define CS1_BASE 0xA8000000
-#define CS2_BASE 0xB0000000
-#define CS3_BASE 0xB2000000
-#define CS4_BASE 0xB4000000
-#define CS5_BASE 0xB6000000
-
-/* CCM */
-#define CCM_MPCTL (CCM_BASE + 0x00)
-#define CCM_UPCTL (CCM_BASE + 0x04)
-#define CCM_CCTL (CCM_BASE + 0x08)
-#define CCM_CGR0 (CCM_BASE + 0x0C)
-#define CCM_CGR1 (CCM_BASE + 0x10)
-#define CCM_CGR2 (CCM_BASE + 0x14)
-#define CCM_PCDR0 (CCM_BASE + 0x18)
-#define CCM_PCDR1 (CCM_BASE + 0x1C)
-#define CCM_PCDR2 (CCM_BASE + 0x20)
-#define CCM_PCDR3 (CCM_BASE + 0x24)
-#define CCM_RCSR (CCM_BASE + 0x28)
-#define CCM_CRDR (CCM_BASE + 0x2C)
-#define CCM_DCVR0 (CCM_BASE + 0x30)
-#define CCM_DCVR1 (CCM_BASE + 0x34)
-#define CCM_DCVR2 (CCM_BASE + 0x38)
-#define CCM_DCVR3 (CCM_BASE + 0x3C)
-#define CCM_LTR0 (CCM_BASE + 0x40)
-#define CCM_LTR1 (CCM_BASE + 0x44)
-#define CCM_LTR2 (CCM_BASE + 0x48)
-#define CCM_LTR3 (CCM_BASE + 0x4C)
-#define CCM_LTBR0 (CCM_BASE + 0x50)
-#define CCM_LTBR1 (CCM_BASE + 0x54)
-#define CCM_PCMR0 (CCM_BASE + 0x58)
-#define CCM_PCMR1 (CCM_BASE + 0x5C)
-#define CCM_PCMR2 (CCM_BASE + 0x60)
-#define CCM_MCR (CCM_BASE + 0x64)
-#define CCM_LPIMR0 (CCM_BASE + 0x68)
-#define CCM_LPIMR1 (CCM_BASE + 0x6C)
-
-#define CRM_CCTL_ARM_SRC (1 << 14)
-#define CRM_CCTL_AHB_OFFSET 28
-
-
-#define FREQ_24MHZ 24000000
-#define PLL_REF_CLK FREQ_24MHZ
-
-/*
- * FIXME - Constants verified up to this point.
- * Offsets and derived constants below should be confirmed.
- */
-
-#define CLKMODE_AUTO 0
-#define CLKMODE_CONSUMER 1
-
-/* WEIM - CS0 */
-#define CSCRU 0x00
-#define CSCRL 0x04
-#define CSCRA 0x08
-
-#define CHIP_REV_1_0 0x0 /* PASS 1.0 */
-#define CHIP_REV_1_1 0x1 /* PASS 1.1 */
-#define CHIP_REV_2_0 0x2 /* PASS 2.0 */
-#define CHIP_LATEST CHIP_REV_1_1
-
-#define IIM_STAT 0x00
-#define IIM_STAT_BUSY (1 << 7)
-#define IIM_STAT_PRGD (1 << 1)
-#define IIM_STAT_SNSD (1 << 0)
-#define IIM_STATM 0x04
-#define IIM_ERR 0x08
-#define IIM_ERR_PRGE (1 << 7)
-#define IIM_ERR_WPE (1 << 6)
-#define IIM_ERR_OPE (1 << 5)
-#define IIM_ERR_RPE (1 << 4)
-#define IIM_ERR_WLRE (1 << 3)
-#define IIM_ERR_SNSE (1 << 2)
-#define IIM_ERR_PARITYE (1 << 1)
-#define IIM_EMASK 0x0C
-#define IIM_FCTL 0x10
-#define IIM_UAF 0x14
-#define IIM_LA 0x18
-#define IIM_SDAT 0x1C
-#define IIM_PREV 0x20
-#define IIM_SREV 0x24
-#define IIM_PREG_P 0x28
-#define IIM_SCS0 0x2C
-#define IIM_SCS1 0x30
-#define IIM_SCS2 0x34
-#define IIM_SCS3 0x38
-
-#define EPIT_BASE EPIT1_BASE
-#define EPITCR 0x00
-#define EPITSR 0x04
-#define EPITLR 0x08
-#define EPITCMPR 0x0C
-#define EPITCNR 0x10
-
-#define GPT_BASE GPT1_BASE
-/*#define GPTCR 0x00
-#define GPTPR 0x04
-#define GPTSR 0x08
-#define GPTIR 0x0C
-#define GPTOCR1 0x10
-#define GPTOCR2 0x14
-#define GPTOCR3 0x18
-#define GPTICR1 0x1C
-#define GPTICR2 0x20
-#define GPTCNT 0x24*/
-
-/* ESDCTL */
-#define ESDCTL_ESDCTL0 0x00
-#define ESDCTL_ESDCFG0 0x04
-#define ESDCTL_ESDCTL1 0x08
-#define ESDCTL_ESDCFG1 0x0C
-#define ESDCTL_ESDMISC 0x10
-
-/* DRYICE */
-#define DRYICE_DTCMR 0x00
-#define DRYICE_DTCLR 0x04
-#define DRYICE_DCAMR 0x08
-#define DRYICE_DCALR 0x0C
-#define DRYICE_DCR 0x10
-#define DRYICE_DSR 0x14
-#define DRYICE_DIER 0x18
-#define DRYICE_DMCR 0x1C
-#define DRYICE_DKSR 0x20
-#define DRYICE_DKCR 0x24
-#define DRYICE_DTCR 0x28
-#define DRYICE_DACR 0x2C
-#define DRYICE_DGPR 0x3C
-#define DRYICE_DPKR0 0x40
-#define DRYICE_DPKR1 0x44
-#define DRYICE_DPKR2 0x48
-#define DRYICE_DPKR3 0x4C
-#define DRYICE_DPKR4 0x50
-#define DRYICE_DPKR5 0x54
-#define DRYICE_DPKR6 0x58
-#define DRYICE_DPKR7 0x5C
-#define DRYICE_DRKR0 0x60
-#define DRYICE_DRKR1 0x64
-#define DRYICE_DRKR2 0x68
-#define DRYICE_DRKR3 0x6C
-#define DRYICE_DRKR4 0x70
-#define DRYICE_DRKR5 0x74
-#define DRYICE_DRKR6 0x78
-#define DRYICE_DRKR7 0x7C
-
-/* GPIO */
-#define GPIO_DR 0x00
-#define GPIO_GDIR 0x04
-#define GPIO_PSR0 0x08
-#define GPIO_ICR1 0x0C
-#define GPIO_ICR2 0x10
-#define GPIO_IMR 0x14
-#define GPIO_ISR 0x18
-#define GPIO_EDGE_SEL 0x1C
-
-
-#if (PLL_REF_CLK != 24000000)
-#error Wrong PLL reference clock! The following macros will not work.
-#endif
-
-/* Assuming 24MHz input clock */
-/* PD MFD MFI MFN */
-#define MPCTL_PARAM_399 (((1-1) << 26) + ((16-1) << 16) + \
- (8 << 10) + (5 << 0))
-#define MPCTL_PARAM_532 ((1 << 31) + ((1-1) << 26) + \
- ((12-1) << 16) + (11 << 10) + (1 << 0))
-#define MPCTL_PARAM_665 (((1-1) << 26) + ((48-1) << 16) + \
- (13 << 10) + (41 << 0))
-
-/* UPCTL PD MFD MFI MFN */
-#define UPCTL_PARAM_300 (((1-1) << 26) + ((4-1) << 16) + \
- (6 << 10) + (1 << 0))
-
-#define NFC_V1_1
-
-#define NAND_REG_BASE (NFC_BASE + 0x1E00)
-#define NFC_BUFSIZE_REG_OFF (0 + 0x00)
-#define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04)
-#define NAND_FLASH_ADD_REG_OFF (0 + 0x06)
-#define NAND_FLASH_CMD_REG_OFF (0 + 0x08)
-#define NFC_CONFIGURATION_REG_OFF (0 + 0x0A)
-#define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C)
-#define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E)
-#define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10)
-#define NF_WR_PROT_REG_OFF (0 + 0x12)
-#define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18)
-#define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A)
-#define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C)
-#define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x20)
-#define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x22)
-#define RAM_BUFFER_ADDRESS_RBA_3 0x3
-#define NFC_BUFSIZE_1KB 0x0
-#define NFC_BUFSIZE_2KB 0x1
-#define NFC_CONFIGURATION_UNLOCKED 0x2
-#define ECC_STATUS_RESULT_NO_ERR 0x0
-#define ECC_STATUS_RESULT_1BIT_ERR 0x1
-#define ECC_STATUS_RESULT_2BIT_ERR 0x2
-#define NF_WR_PROT_UNLOCK 0x4
-#define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7)
-#define NAND_FLASH_CONFIG1_RST (1 << 6)
-#define NAND_FLASH_CONFIG1_BIG (1 << 5)
-#define NAND_FLASH_CONFIG1_INT_MSK (1 << 4)
-#define NAND_FLASH_CONFIG1_ECC_EN (1 << 3)
-#define NAND_FLASH_CONFIG1_SP_EN (1 << 2)
-#define NAND_FLASH_CONFIG2_INT_DONE (1 << 15)
-#define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3)
-#define NAND_FLASH_CONFIG2_FDO_ID (2 << 3)
-#define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3)
-#define NAND_FLASH_CONFIG2_FDI_EN (1 << 2)
-#define NAND_FLASH_CONFIG2_FADD_EN (1 << 1)
-#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
-#define FDO_PAGE_SPARE_VAL 0x8
-#define NAND_BUF_NUM 8
-
-#define MXC_NAND_BASE_DUMMY 0x00000000
-#define MXC_MMC_BASE_DUMMY 0x00000000
-#define NOR_FLASH_BOOT 0
-#define NAND_FLASH_BOOT 0x10000000
-#define SDRAM_NON_FLASH_BOOT 0x20000000
-#define MMC_FLASH_BOOT 0x40000000
-#define MXCBOOT_FLAG_REG (CSI_BASE_ADDR + 0x28)
-#define MXCFIS_NOTHING 0x00000000
-#define MXCFIS_NAND 0x10000000
-#define MXCFIS_NOR 0x20000000
-#define MXCFIS_MMC 0x40000000
-#define MXCFIS_FLAG_REG (CSI_BASE_ADDR + 0x2C)
-
-/*!
- * * NFMS bit in RCSR register for pagesize of nandflash
- * */
-#define NFMS (*((volatile u32 *)(CCM_BASE+0x28)))
-#define NFMS_BIT 8
-#define NFMS_NF_DWIDTH 14
-#define NFMS_NF_PG_SZ 8
-
-#endif
+++ /dev/null
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * (C) Copyright 2009 Freescale Semiconductor
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MX25_H
-#define __ASM_ARCH_MX25_H
-#ifndef __ASSEMBLER__
-
-#define GPIO_PORT_NUM 3
-#define GPIO_NUM_PIN 32
-
-enum mxc_clock {
- MXC_ARM_CLK = 0,
- MXC_AHB_CLK,
- MXC_IPG_CLK,
- MXC_IPG_PERCLK,
- MXC_UART_CLK,
- MXC_CSPI_CLK,
- MXC_ESDHC_CLK,
-};
-
-extern unsigned int mx25_get_ipg_clk(void);
-extern unsigned int mxc_get_clock(enum mxc_clock clk);
-#endif
-#endif /* __ASM_ARCH_MX25_H */
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_ARCH_MXC_MX25_PINS_H__
-#define __ASM_ARCH_MXC_MX25_PINS_H__
-
-/*!
- * @file arch-mxc/mx25_pins.h
- *
- * @brief MX25 I/O Pin List
- *
- * @ingroup GPIO_MX25
- */
-
-#ifndef __ASSEMBLY__
-
-/*!
- * @name IOMUX/PAD Bit field definitions
- */
-
-/*! @{ */
-
-/*!
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P | IO_I | RSVD | PAD_I | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 7 contains MUX_I used to identify the register
- * offset (base is IOMUX_module_base ) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. Similar field
- * definitions are used for the pad control register. For example,
- * MX25_PIN_A14 is defined in the enumeration:
- * ( 0x10 << MUX_I) | ( 0x230 << PAD_I)
- * So the absolute address is: IOMUX_module_base + 0x10.
- * The pad control register offset is: 0x230.
- */
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I 0
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I 10
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * reserved filed
- */
-#define RSVD_I 21
-
-#define MUX_IO_P 29
-#define MUX_IO_I 24
-#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
- GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
- ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
-#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
-#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
-
-#define NON_GPIO_I 0x7
-#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1)
-#define NON_MUX_I PIN_TO_MUX_MASK
-
-#define _MXC_BUILD_PIN(gp, gi, mi, pi) \
- (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
- ((mi) << MUX_I) | ((pi) << PAD_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \
- _MXC_BUILD_PIN(gp, gi, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
- _MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
-
-/*! @} End IOMUX/PAD Bit field definitions */
-
-typedef enum iomux_pins {
- MX25_PIN_A10 = _MXC_BUILD_GPIO_PIN(3, 0, 0x8, 0x0),
- MX25_PIN_A13 = _MXC_BUILD_GPIO_PIN(3, 1, 0x0c, 0x22C),
- MX25_PIN_A14 = _MXC_BUILD_GPIO_PIN(1, 0, 0x10, 0x230),
- MX25_PIN_A15 = _MXC_BUILD_GPIO_PIN(1, 1, 0x14, 0x234),
- MX25_PIN_A16 = _MXC_BUILD_GPIO_PIN(1, 2, 0x18, 0x0),
- MX25_PIN_A17 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1c, 0x238),
- MX25_PIN_A18 = _MXC_BUILD_GPIO_PIN(1, 4, 0x20, 0x23c),
- MX25_PIN_A19 = _MXC_BUILD_GPIO_PIN(1, 5, 0x24, 0x240),
- MX25_PIN_A20 = _MXC_BUILD_GPIO_PIN(1, 6, 0x28, 0x244),
- MX25_PIN_A21 = _MXC_BUILD_GPIO_PIN(1, 7, 0x2c, 0x248),
- MX25_PIN_A22 = _MXC_BUILD_GPIO_PIN(1, 8, 0x30, 0x0),
- MX25_PIN_A23 = _MXC_BUILD_GPIO_PIN(1, 9, 0x34, 0x24c),
- MX25_PIN_A24 = _MXC_BUILD_GPIO_PIN(1, 10, 0x38, 0x250),
- MX25_PIN_A25 = _MXC_BUILD_GPIO_PIN(1, 11, 0x3c, 0x254),
- MX25_PIN_EB0 = _MXC_BUILD_GPIO_PIN(1, 12, 0x40, 0x258),
- MX25_PIN_EB1 = _MXC_BUILD_GPIO_PIN(1, 13, 0x44, 0x25c),
- MX25_PIN_OE = _MXC_BUILD_GPIO_PIN(1, 14, 0x48, 0x260),
- MX25_PIN_CS0 = _MXC_BUILD_GPIO_PIN(3, 2, 0x4c, 0x0),
- MX25_PIN_CS1 = _MXC_BUILD_GPIO_PIN(3, 3, 0x50, 0x0),
- MX25_PIN_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 0x54, 0x264),
- MX25_PIN_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 0x58, 0x268),
- MX25_PIN_NF_CE0 = _MXC_BUILD_GPIO_PIN(2, 22, 0x5c, 0x26c),
- MX25_PIN_ECB = _MXC_BUILD_GPIO_PIN(2, 23, 0x60, 0x270),
- MX25_PIN_LBA = _MXC_BUILD_GPIO_PIN(2, 24, 0x64, 0x274),
- MX25_PIN_BCLK = _MXC_BUILD_GPIO_PIN(3, 4, 0x68, 0x0),
- MX25_PIN_RW = _MXC_BUILD_GPIO_PIN(2, 25, 0x6c, 0x278),
- MX25_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(2, 26, 0x70, 0x0),
- MX25_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(2, 27, 0x74, 0x0),
- MX25_PIN_NFALE = _MXC_BUILD_GPIO_PIN(2, 28, 0x78, 0x0),
- MX25_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(2, 29, 0x7c, 0x0),
- MX25_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(2, 30, 0x80, 0x0),
- MX25_PIN_NFRB = _MXC_BUILD_GPIO_PIN(2, 31, 0x84, 0x27c),
- MX25_PIN_D15 = _MXC_BUILD_GPIO_PIN(3, 5, 0x88, 0x280),
- MX25_PIN_D14 = _MXC_BUILD_GPIO_PIN(3, 6, 0x8c, 0x284),
- MX25_PIN_D13 = _MXC_BUILD_GPIO_PIN(3, 7, 0x90, 0x288),
- MX25_PIN_D12 = _MXC_BUILD_GPIO_PIN(3, 8, 0x94, 0x28c),
- MX25_PIN_D11 = _MXC_BUILD_GPIO_PIN(3, 9, 0x98, 0x290),
- MX25_PIN_D10 = _MXC_BUILD_GPIO_PIN(3, 10, 0x9c, 0x294),
- MX25_PIN_D9 = _MXC_BUILD_GPIO_PIN(3, 11, 0xa0, 0x298),
- MX25_PIN_D8 = _MXC_BUILD_GPIO_PIN(3, 12, 0xa4, 0x29c),
- MX25_PIN_D7 = _MXC_BUILD_GPIO_PIN(3, 13, 0xa8, 0x2a0),
- MX25_PIN_D6 = _MXC_BUILD_GPIO_PIN(3, 14, 0xac, 0x2a4),
- MX25_PIN_D5 = _MXC_BUILD_GPIO_PIN(3, 15, 0xb0, 0x2a8),
- MX25_PIN_D4 = _MXC_BUILD_GPIO_PIN(3, 16, 0xb4, 0x2ac),
- MX25_PIN_D3 = _MXC_BUILD_GPIO_PIN(3, 17, 0xb8, 0x2b0),
- MX25_PIN_D2 = _MXC_BUILD_GPIO_PIN(3, 18, 0xbc, 0x2b4),
- MX25_PIN_D1 = _MXC_BUILD_GPIO_PIN(3, 19, 0xc0, 0x2b8),
- MX25_PIN_D0 = _MXC_BUILD_GPIO_PIN(3, 20, 0xc4, 0x2bc),
- MX25_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 15, 0xc8, 0x2c0),
- MX25_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 16, 0xcc, 0x2c4),
- MX25_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 17, 0xd0, 0x2c8),
- MX25_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 18, 0xd4, 0x2cc),
- MX25_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 19, 0xd8, 0x2d0),
- MX25_PIN_LD5 = _MXC_BUILD_GPIO_PIN(0, 19, 0xdc, 0x2d4),
- MX25_PIN_LD6 = _MXC_BUILD_GPIO_PIN(0, 20, 0xe0, 0x2d8),
- MX25_PIN_LD7 = _MXC_BUILD_GPIO_PIN(0, 21, 0xe4, 0x2dc),
- MX25_PIN_LD8 = _MXC_BUILD_NON_GPIO_PIN(0xe8, 0x2e0),
- MX25_PIN_LD9 = _MXC_BUILD_NON_GPIO_PIN(0xec, 0x2e4),
- MX25_PIN_LD10 = _MXC_BUILD_NON_GPIO_PIN(0xf0, 0x2e8),
- MX25_PIN_LD11 = _MXC_BUILD_NON_GPIO_PIN(0xf4, 0x2ec),
- MX25_PIN_LD12 = _MXC_BUILD_NON_GPIO_PIN(0xf8, 0x2f0),
- MX25_PIN_LD13 = _MXC_BUILD_NON_GPIO_PIN(0xfc, 0x2f4),
- MX25_PIN_LD14 = _MXC_BUILD_NON_GPIO_PIN(0x100, 0x2f8),
- MX25_PIN_LD15 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x2fc),
- MX25_PIN_HSYNC = _MXC_BUILD_GPIO_PIN(0, 22, 0x108, 0x300),
- MX25_PIN_VSYNC = _MXC_BUILD_GPIO_PIN(0, 23, 0x10c, 0x304),
- MX25_PIN_LSCLK = _MXC_BUILD_GPIO_PIN(0, 24, 0x110, 0x308),
- MX25_PIN_OE_ACD = _MXC_BUILD_GPIO_PIN(0, 25, 0x114, 0x30c),
- MX25_PIN_CONTRAST = _MXC_BUILD_NON_GPIO_PIN(0x118, 0x310),
- MX25_PIN_PWM = _MXC_BUILD_GPIO_PIN(0, 26, 0x11c, 0x314),
- MX25_PIN_CSI_D2 = _MXC_BUILD_GPIO_PIN(0, 27, 0x120, 0x318),
- MX25_PIN_CSI_D3 = _MXC_BUILD_GPIO_PIN(0, 28, 0x124, 0x31c),
- MX25_PIN_CSI_D4 = _MXC_BUILD_GPIO_PIN(0, 29, 0x128, 0x320),
- MX25_PIN_CSI_D5 = _MXC_BUILD_GPIO_PIN(0, 30, 0x12c, 0x324),
- MX25_PIN_CSI_D6 = _MXC_BUILD_GPIO_PIN(0, 31, 0x130, 0x328),
- MX25_PIN_CSI_D7 = _MXC_BUILD_GPIO_PIN(0, 6, 0x134, 0x32c),
- MX25_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 7, 0x138, 0x330),
- MX25_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(3, 21, 0x13c, 0x334),
- MX25_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 8, 0x140, 0x338),
- MX25_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 9, 0x144, 0x33c),
- MX25_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 10, 0x148, 0x340),
- MX25_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 11, 0x14c, 0x344),
- MX25_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(0, 12, 0x150, 0x348),
- MX25_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(0, 13, 0x154, 0x34c),
- MX25_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 14, 0x158, 0x350),
- MX25_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 15, 0x15c, 0x354),
- MX25_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 16, 0x160, 0x358),
- MX25_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 17, 0x164, 0x35c),
- MX25_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(0, 18, 0x168, 0x360),
- MX25_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(1, 22, 0x16c, 0x364),
- MX25_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 22, 0x170, 0x368),
- MX25_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 23, 0x174, 0x36c),
- MX25_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 24, 0x178, 0x370),
- MX25_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 25, 0x17c, 0x374),
- MX25_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(3, 26, 0x180, 0x378),
- MX25_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(3, 27, 0x184, 0x37c),
- MX25_PIN_UART2_RTS = _MXC_BUILD_GPIO_PIN(3, 28, 0x188, 0x380),
- MX25_PIN_UART2_CTS = _MXC_BUILD_GPIO_PIN(3, 29, 0x18c, 0x384),
- MX25_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(1, 23, 0x190, 0x388),
- MX25_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x194, 0x38c),
- MX25_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(1, 25, 0x198, 0x390),
- MX25_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(1, 26, 0x19c, 0x394),
- MX25_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(1, 27, 0x1a0, 0x398),
- MX25_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(1, 28, 0x1a4, 0x39c),
- MX25_PIN_KPP_ROW0 = _MXC_BUILD_GPIO_PIN(1, 29, 0x1a8, 0x3a0),
- MX25_PIN_KPP_ROW1 = _MXC_BUILD_GPIO_PIN(1, 30, 0x1ac, 0x3a4),
- MX25_PIN_KPP_ROW2 = _MXC_BUILD_GPIO_PIN(1, 31, 0x1b0, 0x3a8),
- MX25_PIN_KPP_ROW3 = _MXC_BUILD_GPIO_PIN(2, 0, 0x1b4, 0x3ac),
- MX25_PIN_KPP_COL0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1b8, 0x3b0),
- MX25_PIN_KPP_COL1 = _MXC_BUILD_GPIO_PIN(2, 2, 0x1bc, 0x3b4),
- MX25_PIN_KPP_COL2 = _MXC_BUILD_GPIO_PIN(2, 3, 0x1c0, 0x3b8),
- MX25_PIN_KPP_COL3 = _MXC_BUILD_GPIO_PIN(2, 4, 0x1c4, 0x3bc),
- MX25_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 5, 0x1c8, 0x3c0),
- MX25_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 6, 0x1cc, 0x3c4),
- MX25_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 7, 0x1d0, 0x3c8),
- MX25_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x1d4, 0x3cc),
- MX25_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 9, 0x1d8, 0x3d0),
- MX25_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x1dc, 0x3d4),
- MX25_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 11, 0x1e0, 0x3d8),
- MX25_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 12, 0x1e4, 0x3dc),
- MX25_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 13, 0x1e8, 0x3e0),
- MX25_PIN_RTCK = _MXC_BUILD_GPIO_PIN(2, 14, 0x1ec, 0x3e4),
- MX25_PIN_DE_B = _MXC_BUILD_GPIO_PIN(1, 20, 0x1f0, 0x3ec),
- MX25_PIN_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3e8),
- MX25_PIN_GPIO_A = _MXC_BUILD_GPIO_PIN(0, 0, 0x1f4, 0x3f0),
- MX25_PIN_GPIO_B = _MXC_BUILD_GPIO_PIN(0, 1, 0x1f8, 0x3f4),
- MX25_PIN_GPIO_C = _MXC_BUILD_GPIO_PIN(0, 2, 0x1fc, 0x3f8),
- MX25_PIN_GPIO_D = _MXC_BUILD_GPIO_PIN(0, 3, 0x200, 0x3fc),
- MX25_PIN_GPIO_E = _MXC_BUILD_GPIO_PIN(0, 4, 0x204, 0x400),
- MX25_PIN_GPIO_F = _MXC_BUILD_GPIO_PIN(0, 5, 0x208, 0x404),
- MX25_PIN_EXT_ARMCLK = _MXC_BUILD_GPIO_PIN(2, 15, 0x20c, 0x0),
- MX25_PIN_UPLL_BYPCLK = _MXC_BUILD_GPIO_PIN(2, 16, 0x210, 0x0),
- MX25_PIN_VSTBY_REQ = _MXC_BUILD_GPIO_PIN(2, 17, 0x214, 0x408),
- MX25_PIN_VSTBY_ACK = _MXC_BUILD_GPIO_PIN(2, 18, 0x218, 0x40c),
- MX25_PIN_POWER_FAIL = _MXC_BUILD_GPIO_PIN(2, 19, 0x21c, 0x410),
- MX25_PIN_CLKO = _MXC_BUILD_GPIO_PIN(1, 21, 0x220, 0x414),
- MX25_PIN_BOOT_MODE0 = _MXC_BUILD_GPIO_PIN(3, 30, 0x224, 0x0),
- MX25_PIN_BOOT_MODE1 = _MXC_BUILD_GPIO_PIN(3, 31, 0x228, 0x0),
-
- MX25_PIN_CTL_GRP_DVS_MISC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x418),
- MX25_PIN_CTL_GRP_DSE_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x41c),
- MX25_PIN_CTL_GRP_DVS_JTAG = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x420),
- MX25_PIN_CTL_GRP_DSE_NFC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x424),
- MX25_PIN_CTL_GRP_DSE_CSI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x428),
- MX25_PIN_CTL_GRP_DSE_WEIM = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x42c),
- MX25_PIN_CTL_GRP_DSE_DDR = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x430),
- MX25_PIN_CTL_GRP_DVS_CRM = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x434),
- MX25_PIN_CTL_GRP_DSE_KPP = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x438),
- MX25_PIN_CTL_GRP_DSE_SDHC1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43c),
- MX25_PIN_CTL_GRP_DSE_LCD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440),
- MX25_PIN_CTL_GRP_DSE_UART = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444),
- MX25_PIN_CTL_GRP_DVS_NFC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448),
- MX25_PIN_CTL_GRP_DVS_CSI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44c),
- MX25_PIN_CTL_GRP_DSE_CSPI1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450),
- MX25_PIN_CTL_GRP_DDRTYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454),
- MX25_PIN_CTL_GRP_DVS_SDHC1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x458),
- MX25_PIN_CTL_GRP_DVS_LCD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x45c)
-} iomux_pin_name_t;
-
-#endif
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/*!
- * @file mxc_nd2.h
- *
- * @brief This file contains the NAND Flash Controller register information.
- *
- *
- * @ingroup NAND_MTD
- */
-
-#ifndef __MXC_NAND_H__
-#define __MXC_NAND_H__
-
-#include <asm/arch/mx25-regs.h>
-
-#define IS_2K_PAGE_NAND ((mtd->writesize / info->num_of_intlv) \
- == NAND_PAGESIZE_2KB)
-#define IS_4K_PAGE_NAND ((mtd->writesize / info->num_of_intlv) \
- == NAND_PAGESIZE_4KB)
-#define IS_LARGE_PAGE_NAND ((mtd->writesize / info->num_of_intlv) > 512)
-
-#define GET_NAND_OOB_SIZE (mtd->oobsize / info->num_of_intlv)
-#define GET_NAND_PAGE_SIZE (mtd->writesize / info->num_of_intlv)
-
-/*
- * main area for bad block marker is in the last data section
- * the spare area for swapped bad block marker is the second
- * byte of last spare section
- */
-#define NAND_SECTIONS (GET_NAND_PAGE_SIZE >> 9)
-#define NAND_OOB_PER_SECTION (((GET_NAND_OOB_SIZE / NAND_SECTIONS) >> 1) << 1)
-#define NAND_CHUNKS (GET_NAND_PAGE_SIZE / (512 + NAND_OOB_PER_SECTION))
-
-#define BAD_BLK_MARKER_MAIN_OFFS \
- (GET_NAND_PAGE_SIZE - NAND_CHUNKS * NAND_OOB_PER_SECTION)
-
-#define BAD_BLK_MARKER_SP_OFFS (NAND_CHUNKS * SPARE_LEN)
-
-#define BAD_BLK_MARKER_OOB_OFFS (NAND_CHUNKS * NAND_OOB_PER_SECTION)
-
-#define BAD_BLK_MARKER_MAIN \
- ((u32)MAIN_AREA0 + BAD_BLK_MARKER_MAIN_OFFS)
-
-#define BAD_BLK_MARKER_SP \
- ((u32)SPARE_AREA0 + BAD_BLK_MARKER_SP_OFFS)
-
-#define NAND_PAGESIZE_2KB 2048
-#define NAND_PAGESIZE_4KB 4096
-#define NAND_MAX_PAGESIZE 4096
-
-/*
- * Addresses for NFC registers
- */
-#define NFC_REG_BASE (NFC_BASE_ADDR + 0x1000)
-#define NFC_BUF_ADDR (NFC_REG_BASE + 0xE04)
-#define NFC_FLASH_ADDR (NFC_REG_BASE + 0xE06)
-#define NFC_FLASH_CMD (NFC_REG_BASE + 0xE08)
-#define NFC_CONFIG (NFC_REG_BASE + 0xE0A)
-#define NFC_ECC_STATUS_RESULT (NFC_REG_BASE + 0xE0C)
-#define NFC_SPAS (NFC_REG_BASE + 0xE10)
-#define NFC_WRPROT (NFC_REG_BASE + 0xE12)
-#define NFC_UNLOCKSTART_BLKADDR (NFC_REG_BASE + 0xE20)
-#define NFC_UNLOCKEND_BLKADDR (NFC_REG_BASE + 0xE22)
-#define NFC_CONFIG1 (NFC_REG_BASE + 0xE1A)
-#define NFC_CONFIG2 (NFC_REG_BASE + 0xE1C)
-
-/*!
- * Addresses for NFC RAM BUFFER Main area 0
- */
-#define MAIN_AREA0 (u16 *)(NFC_BASE_ADDR + 0x000)
-#define MAIN_AREA1 (u16 *)(NFC_BASE_ADDR + 0x200)
-
-/*!
- * Addresses for NFC SPARE BUFFER Spare area 0
- */
-#define SPARE_AREA0 (u16 *)(NFC_BASE_ADDR + 0x1000)
-#define SPARE_LEN 64
-#define SPARE_COUNT 8
-#define SPARE_SIZE (SPARE_LEN * SPARE_COUNT)
-
-
-#define SPAS_SHIFT (0)
-#define SPAS_MASK (0xFF00)
-#define IS_4BIT_ECC \
- ((raw_read(REG_NFC_ECC_MODE) & NFC_ECC_MODE_4) >> 0)
-
-#define NFC_SET_SPAS(v) \
- raw_write(((raw_read(REG_NFC_SPAS) & SPAS_MASK) | \
- ((v<<SPAS_SHIFT))), \
- REG_NFC_SPAS)
-
-#define NFC_SET_ECC_MODE(v) \
-do { \
- if ((v) == NFC_SPAS_218) { \
- raw_write((raw_read(REG_NFC_ECC_MODE) & \
- NFC_ECC_MODE_8), \
- REG_NFC_ECC_MODE); \
- } else { \
- raw_write((raw_read(REG_NFC_ECC_MODE) | \
- NFC_ECC_MODE_4), \
- REG_NFC_ECC_MODE); \
- } \
-} while (0)
-
-#define GET_ECC_STATUS() \
- __raw_readl(REG_NFC_ECC_STATUS_RESULT);
-
-#define NFC_SET_NFMS(v) \
-do { \
- if (((v) & (1 << NFMS_NF_PG_SZ))) { \
- if (IS_2K_PAGE_NAND) { \
- (NFMS |= 0x00000100); \
- (NFMS &= ~0x00000200); \
- NFC_SET_SPAS(NFC_SPAS_64); \
- } else if (IS_4K_PAGE_NAND) { \
- (NFMS &= ~0x00000100); \
- (NFMS |= 0x00000200); \
- GET_NAND_OOB_SIZE == 128 ? \
- NFC_SET_SPAS(NFC_SPAS_128) : \
- NFC_SET_SPAS(NFC_SPAS_218); \
- } else { \
- printk(KERN_ERR "Err for setting page/oob size"); \
- } \
- NFC_SET_ECC_MODE(GET_NAND_OOB_SIZE >> 1); \
- } \
-} while (0)
-
-
-#define WRITE_NFC_IP_REG(val, reg) \
- raw_write((raw_read(REG_NFC_OPS_STAT) & ~NFC_OPS_STAT), \
- REG_NFC_OPS_STAT)
-
-#define GET_NFC_ECC_STATUS() \
- raw_read(REG_NFC_ECC_STATUS_RESULT);
-
-/*!
- * Set INT to 0, Set 1 to specific operation bit, rest to 0 in LAUNCH_NFC
- * Register for Specific operation
- */
-#define NFC_CMD 0x1
-#define NFC_ADDR 0x2
-#define NFC_INPUT 0x4
-#define NFC_OUTPUT 0x8
-#define NFC_ID 0x10
-#define NFC_STATUS 0x20
-
-/* Bit Definitions */
-#define NFC_OPS_STAT (1 << 15)
-#define NFC_SP_EN (1 << 2)
-#define NFC_ECC_EN (1 << 3)
-#define NFC_INT_MSK (1 << 4)
-#define NFC_BIG (1 << 5)
-#define NFC_RST (1 << 6)
-#define NFC_CE (1 << 7)
-#define NFC_ONE_CYCLE (1 << 8)
-#define NFC_BLS_LOCKED 0
-#define NFC_BLS_LOCKED_DEFAULT 1
-#define NFC_BLS_UNLCOKED 2
-#define NFC_WPC_LOCK_TIGHT 1
-#define NFC_WPC_LOCK (1 << 1)
-#define NFC_WPC_UNLOCK (1 << 2)
-#define NFC_FLASH_ADDR_SHIFT 0
-#define NFC_UNLOCK_END_ADDR_SHIFT 0
-
-#define NFC_ECC_MODE_4 (1<<0)
-#define NFC_ECC_MODE_8 (~(1<<0))
-#define NFC_SPAS_16 8
-#define NFC_SPAS_64 32
-#define NFC_SPAS_128 64
-#define NFC_SPAS_218 109
-
-/* NFC Register Mapping */
-#define REG_NFC_OPS_STAT NFC_CONFIG2
-#define REG_NFC_INTRRUPT NFC_CONFIG1
-#define REG_NFC_FLASH_ADDR NFC_FLASH_ADDR
-#define REG_NFC_FLASH_CMD NFC_FLASH_CMD
-#define REG_NFC_OPS NFC_CONFIG2
-#define REG_NFC_SET_RBA NFC_BUF_ADDR
-#define REG_NFC_ECC_EN NFC_CONFIG1
-#define REG_NFC_ECC_STATUS_RESULT NFC_ECC_STATUS_RESULT
-#define REG_NFC_CE NFC_CONFIG1
-#define REG_NFC_SP_EN NFC_CONFIG1
-#define REG_NFC_BLS NFC_CONFIG
-#define REG_NFC_WPC NFC_WRPROT
-#define REG_START_BLKADDR NFC_UNLOCKSTART_BLKADDR
-#define REG_END_BLKADDR NFC_UNLOCKEND_BLKADDR
-#define REG_NFC_RST NFC_CONFIG1
-#define REG_NFC_ECC_MODE NFC_CONFIG1
-#define REG_NFC_SPAS NFC_SPAS
-
-
-/* NFC V1/V2 Specific MACRO functions definitions */
-
-#define raw_write(v, a) __raw_writew(v, a)
-#define raw_read(a) __raw_readw(a)
-
-#define NFC_SET_BLS(val) val
-
-#define UNLOCK_ADDR(start_addr, end_addr) \
-{ \
- raw_write(start_addr, REG_START_BLKADDR); \
- raw_write(end_addr, REG_END_BLKADDR); \
-}
-
-#define NFC_SET_NFC_ACTIVE_CS(val)
-#define NFC_SET_WPC(val) val
-
-/* NULL Definitions */
-#define ACK_OPS
-#define NFC_SET_RBA(val) raw_write(val, REG_NFC_SET_RBA);
-
-#define READ_PAGE() send_read_page(0)
-#define PROG_PAGE() send_prog_page(0)
-#define CHECK_NFC_RB 1
-
-#endif /* __MXC_NAND_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2008 Embedded Alley Solutions Inc.
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __MX28_H
-#define __MX28_H
-
-#ifndef __ASSEMBLER__
-enum mxc_clock {
- MXC_ARM_CLK = 0,
- MXC_AHB_CLK,
- MXC_IPG_CLK,
- MXC_GPMI_CLK,
-};
-
-unsigned int mxc_get_clock(enum mxc_clock clk);
-void enet_board_init(void);
-
-extern int mxs_reset_block(volatile void *addr);
-#endif
-
-/*
- * Most of i.MX28 SoC registers are associated with four addresses
- * used for different operations - read/write, set, clear and toggle bits.
- *
- * Some of registers do not implement such feature and, thus, should be
- * accessed/manipulated via single address in common way.
- */
-#define REG_RD(base, reg) \
- (*(volatile unsigned int *)((base) + (reg)))
-#define REG_WR(base, reg, value) \
- ((*(volatile unsigned int *)((base) + (reg))) = (value))
-#define REG_SET(base, reg, value) \
- ((*(volatile unsigned int *)((base) + (reg ## _SET))) = (value))
-#define REG_CLR(base, reg, value) \
- ((*(volatile unsigned int *)((base) + (reg ## _CLR))) = (value))
-#define REG_TOG(base, reg, value) \
- ((*(volatile unsigned int *)((base) + (reg ## _TOG))) = (value))
-
-#define REG_RD_ADDR(addr) \
- (*(volatile unsigned int *)((addr)))
-#define REG_WR_ADDR(addr, value) \
- ((*(volatile unsigned int *)((addr))) = (value))
-#define REG_SET_ADDR(addr, value) \
- ((*(volatile unsigned int *)((addr) + 0x4)) = (value))
-#define REG_CLR_ADDR(addr, value) \
- ((*(volatile unsigned int *)((addr) + 0x8)) = (value))
-#define REG_TOG_ADDR(addr, value) \
- ((*(volatile unsigned int *)((addr) + 0xc)) = (value))
-
-/*
- * Register base address
- */
-#define REGS_ICOL_BASE 0x80000000
-#define REGS_HSADC_BASE 0x80002000
-#define REGS_APBH_BASE 0x80004000
-#define REGS_PERFMON_BASE 0x80006000
-#define REGS_BCH_BASE 0x8000A000
-#define REGS_GPMI_BASE 0x8000C000
-#define REGS_SSP0_BASE 0x80010000
-#define REGS_SSP1_BASE 0x80012000
-#define REGS_SSP2_BASE 0x80014000
-#define REGS_SSP3_BASE 0x80016000
-#define REGS_PINCTRL_BASE 0x80018000
-#define REGS_DIGCTL_BASE 0x8001C000
-#define REGS_ETM_BASE 0x80022000
-#define REGS_APBX_BASE 0x80024000
-#define REGS_DCP_BASE 0x80028000
-#define REGS_PXP_BASE 0x8002A000
-#define REGS_OCOTP_BASE 0x8002C000
-#define REGS_AXI_AHB0_BASE 0x8002E000
-#define REGS_LCDIF_BASE 0x80030000
-#define REGS_CAN0_BASE 0x80032000
-#define REGS_CAN1_BASE 0x80034000
-#define REGS_SIMDBG_BASE 0x8003C000
-#define REGS_SIMGPMISEL_BASE 0x8003C200
-#define REGS_SIMSSPSEL_BASE 0x8003C300
-#define REGS_SIMMEMSEL_BASE 0x8003C400
-#define REGS_GPIOMON_BASE 0x8003C500
-#define REGS_SIMENET_BASE 0x8003C700
-#define REGS_ARMJTAG_BASE 0x8003C800
-#define REGS_CLKCTRL_BASE 0x80040000
-#define REGS_SAIF0_BASE 0x80042000
-#define REGS_POWER_BASE 0x80044000
-#define REGS_SAIF1_BASE 0x80046000
-#define REGS_LRADC_BASE 0x80050000
-#define REGS_SPDIF_BASE 0x80054000
-#define REGS_RTC_BASE 0x80056000
-#define REGS_I2C0_BASE 0x80058000
-#define REGS_I2C1_BASE 0x8005A000
-#define REGS_PWM_BASE 0x80064000
-#define REGS_TIMROT_BASE 0x80068000
-#define REGS_UARTAPP0_BASE 0x8006A000
-#define REGS_UARTAPP1_BASE 0x8006C000
-#define REGS_UARTAPP2_BASE 0x8006E000
-#define REGS_UARTAPP3_BASE 0x80070000
-#define REGS_UARTAPP4_BASE 0x80072000
-#define REGS_UARTDBG_BASE 0x80074000
-#define REGS_USBPHY0_BASE 0x8007C000
-#define REGS_USBPHY1_BASE 0x8007E000
-#define REGS_USBCTRL0_BASE 0x80080000
-#define REGS_USBCTRL1_BASE 0x80090000
-#define REGS_DFLPT_BASE 0x800C0000
-#define REGS_DRAM_BASE 0x800E0000
-#define REGS_ENET_BASE 0x800F0000
-
-#define BCH_BASE_ADDR REGS_BCH_BASE
-#define GPMI_BASE_ADDR REGS_GPMI_BASE
-#define APBHDMA_BASE_ADDR REGS_APBH_BASE
-#define CLKCTRL_BASE_ADDR REGS_CLKCTRL_BASE
-
-#define MXS_SET_ADDR 0x04
-#define MXS_CLR_ADDR 0x08
-#define MXS_TOG_ADDR 0x0c
-
-#endif /* __MX28_H */
+++ /dev/null
-/*
- * Freescale GPMI NFC NAND Flash Driver
- *
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Xml Revision: 2.5
- * Template revision: 26195
- */
-
-#ifndef __GPMI_NFC_BCH_REGS_H
-#define __GPMI_NFC_BCH_REGS_H
-
-#define HW_BCH_CTRL 0x000
-#define HW_BCH_CTRL_SET 0x004
-#define HW_BCH_CTRL_CLR 0x008
-#define HW_BCH_CTRL_TOG 0x00c
-
-#define BM_BCH_CTRL_SFTRST (1 << 31)
-#define BM_BCH_CTRL_CLKGATE (1 << 30)
-#define BM_BCH_CTRL_DEBUGSYNDROME (1 << 22)
-#define BP_BCH_CTRL_M2M_LAYOUT 18
-#define BM_BCH_CTRL_M2M_LAYOUT (1 << BP_BCH_CTRL_M2M_LAYOUT)
-#define BF_BCH_CTRL_M2M_LAYOUT(v) (((v) << BP_BCH_CTRL_M2M_LAYOUT) & BM_BCH_CTRL_M2M_LAYOUT)
-#define BM_BCH_CTRL_M2M_ENCODE (1 << 17)
-#define BM_BCH_CTRL_M2M_ENABLE (1 << 16)
-#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10)
-#define BM_BCH_CTRL_COMPLETE_IRQ_EN (1 << 8)
-#define BM_BCH_CTRL_BM_ERROR_IRQ (1 << 3)
-#define BM_BCH_CTRL_DEBUG_STALL_IRQ (1 << 2)
-#define BM_BCH_CTRL_COMPLETE_IRQ (1 << 0)
-
-#define HW_BCH_STATUS0 0x010
-
-#define BP_BCH_STATUS0_HANDLE 20
-#define BM_BCH_STATUS0_HANDLE (0xFFF << BP_BCH_STATUS0_HANDLE)
-#define BF_BCH_STATUS0_HANDLE(v) (((v) << BP_BCH_STATUS0_HANDLE) & BM_BCH_STATUS0_HANDLE)
-#define BP_BCH_STATUS0_COMPLETED_CE 16
-#define BM_BCH_STATUS0_COMPLETED_CE (0x000F << BP_BCH_STATUS0_COMPLETED_CE)
-#define BF_BCH_STATUS0_COMPLETED_CE(v) (((v) << BP_BCH_STATUS0_COMPLETED_CE) & BM_BCH_STATUS0_COMPLETED_CE)
-#define BP_BCH_STATUS0_STATUS_BLK0 8
-#define BM_BCH_STATUS0_STATUS_BLK0 (0xFF << BP_BCH_STATUS0_STATUS_BLK0)
-#define BF_BCH_STATUS0_STATUS_BLK0(v) (((v) << BP_BCH_STATUS0_STATUS_BLK0) & BM_BCH_STATUS0_STATUS_BLK0)
-#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x00
-#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x01
-#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x02
-#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x03
-#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x04
-#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE
-#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xFF
-#define BM_BCH_STATUS0_ALLONES (1 << 4)
-#define BM_BCH_STATUS0_CORRECTED (1 << 3)
-#define BM_BCH_STATUS0_UNCORRECTABLE (1 << 2)
-
-#define HW_BCH_MODE 0x020
-
-#define BP_BCH_MODE_ERASE_THRESHOLD 0
-#define BM_BCH_MODE_ERASE_THRESHOLD (0xFF << BP_BCH_MODE_ERASE_THRESHOLD)
-#define BF_BCH_MODE_ERASE_THRESHOLD(v) (((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD)
-
-#define HW_BCH_ENCODEPTR 0x030
-
-#define BP_BCH_ENCODEPTR_ADDR 0
-#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF
-#define BF_BCH_ENCODEPTR_ADDR(v) (v)
-
-#define HW_BCH_DATAPTR 0x040
-
-#define BP_BCH_DATAPTR_ADDR 0
-#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF
-#define BF_BCH_DATAPTR_ADDR(v) (v)
-
-#define HW_BCH_METAPTR 0x050
-
-#define BP_BCH_METAPTR_ADDR 0
-#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF
-#define BF_BCH_METAPTR_ADDR(v) (v)
-
-#define HW_BCH_LAYOUTSELECT 0x070
-
-#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30
-#define BM_BCH_LAYOUTSELECT_CS15_SELECT (0x3 << BP_BCH_LAYOUTSELECT_CS15_SELECT)
-#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) (((v) << BP_BCH_LAYOUTSELECT_CS15_SELECT) & \
- BM_BCH_LAYOUTSELECT_CS15_SELECT)
-#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28
-#define BM_BCH_LAYOUTSELECT_CS14_SELECT (0x3 << BP_BCH_LAYOUTSELECT_CS14_SELECT)
-#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) (((v) << BP_BCH_LAYOUTSELECT_CS14_SELECT) & \
- BM_BCH_LAYOUTSELECT_CS14_SELECT)
-#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26
-#define BM_BCH_LAYOUTSELECT_CS13_SELECT (0x3 << BP_BCH_LAYOUTSELECT_CS13_SELECT)
-#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) (((v) << BP_BCH_LAYOUTSELECT_CS13_SELECT) & \
- BM_BCH_LAYOUTSELECT_CS13_SELECT)
-#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24
-#define BM_BCH_LAYOUTSELECT_CS12_SELECT (0x3 << BP_BCH_LAYOUTSELECT_CS12_SELECT)
-#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) (((v) << BP_BCH_LAYOUTSELECT_CS12_SELECT) & \
- BM_BCH_LAYOUTSELECT_CS12_SELECT)
-#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22
-#define BM_BCH_LAYOUTSELECT_CS11_SELECT (0x3 << BP_BCH_LAYOUTSELECT_CS11_SELECT)
-#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) (((v) << BP_BCH_LAYOUTSELECT_CS11_SELECT) & \
- BM_BCH_LAYOUTSELECT_CS11_SELECT)
-#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20
-#define BM_BCH_LAYOUTSELECT_CS10_SELECT (0x3 << BP_BCH_LAYOUTSELECT_CS10_SELECT)
-#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) (((v) << BP_BCH_LAYOUTSELECT_CS10_SELECT) & \
- BM_BCH_LAYOUTSELECT_CS10_SELECT)
-#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18
-#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000
-#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) (((v) << 18) & \
- BM_BCH_LAYOUTSELECT_CS9_SELECT)
-#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16
-#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000
-#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) (((v) << 16) & \
- BM_BCH_LAYOUTSELECT_CS8_SELECT)
-#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14
-#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000
-#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) (((v) << 14) & \
- BM_BCH_LAYOUTSELECT_CS7_SELECT)
-#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12
-#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000
-#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) (((v) << 12) & \
- BM_BCH_LAYOUTSELECT_CS6_SELECT)
-#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10
-#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00
-#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) (((v) << 10) & \
- BM_BCH_LAYOUTSELECT_CS5_SELECT)
-#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8
-#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300
-#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) (((v) << 8) & \
- BM_BCH_LAYOUTSELECT_CS4_SELECT)
-#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6
-#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0
-#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) (((v) << 6) & \
- BM_BCH_LAYOUTSELECT_CS3_SELECT)
-#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4
-#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030
-#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) (((v) << 4) & \
- BM_BCH_LAYOUTSELECT_CS2_SELECT)
-#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2
-#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C
-#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) (((v) << 2) & \
- BM_BCH_LAYOUTSELECT_CS1_SELECT)
-#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0
-#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003
-#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) (((v) << 0) & \
- BM_BCH_LAYOUTSELECT_CS0_SELECT)
-
-#define HW_BCH_FLASH0LAYOUT0 0x080
-
-#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24
-#define BM_BCH_FLASH0LAYOUT0_NBLOCKS (0xFF << BP_BCH_FLASH0LAYOUT0_NBLOCKS)
-#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) (((v) << BP_BCH_FLASH0LAYOUT0_NBLOCKS) & \
- BM_BCH_FLASH0LAYOUT0_NBLOCKS)
-#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16
-#define BM_BCH_FLASH0LAYOUT0_META_SIZE (0xFF << BP_BCH_FLASH0LAYOUT0_META_SIZE)
-#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) (((v) << BP_BCH_FLASH0LAYOUT0_META_SIZE) & \
- BM_BCH_FLASH0LAYOUT0_META_SIZE)
-#define BP_BCH_FLASH0LAYOUT0_ECC0 12
-#define BM_BCH_FLASH0LAYOUT0_ECC0 (0xF << BP_BCH_FLASH0LAYOUT0_ECC0)
-#define BF_BCH_FLASH0LAYOUT0_ECC0(v) (((v) << BP_BCH_FLASH0LAYOUT0_ECC0) & \
- BM_BCH_FLASH0LAYOUT0_ECC0)
-#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9
-#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA
-#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
-#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE (0xFFF << BP_BCH_FLASH0LAYOUT0_DATA0_SIZE)
-#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) (((v) << BP_BCH_FLASH0LAYOUT0_DATA0_SIZE) & \
- BM_BCH_FLASH0LAYOUT0_DATA0_SIZE)
-
-#define HW_BCH_FLASH0LAYOUT1 0x090
-
-#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16
-#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE (0xFFFF << BP_BCH_FLASH0LAYOUT1_PAGE_SIZE)
-#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) (((v) << BP_BCH_FLASH0LAYOUT1_PAGE_SIZE) & \
- BM_BCH_FLASH0LAYOUT1_PAGE_SIZE)
-#define BP_BCH_FLASH0LAYOUT1_ECCN 12
-#define BM_BCH_FLASH0LAYOUT1_ECCN (0xF << BP_BCH_FLASH0LAYOUT1_ECCN)
-#define BF_BCH_FLASH0LAYOUT1_ECCN(v) (((v) << BP_BCH_FLASH0LAYOUT1_ECCN) & \
- BM_BCH_FLASH0LAYOUT1_ECCN)
-#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9
-#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA
-#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
-#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE (0xFFF << BP_BCH_FLASH0LAYOUT1_DATAN_SIZE)
-#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) (((v) << BP_BCH_FLASH0LAYOUT1_DATAN_SIZE) & \
- BM_BCH_FLASH0LAYOUT1_DATAN_SIZE)
-
-#define HW_BCH_FLASH1LAYOUT0 0x0a0
-
-#define HW_BCH_FLASH1LAYOUT1 0x0b0
-
-#define HW_BCH_FLASH2LAYOUT0 0x0c0
-
-#define HW_BCH_FLASH2LAYOUT1 0x0d0
-
-#define HW_BCH_FLASH3LAYOUT0 0x0e0
-
-#define HW_BCH_FLASH3LAYOUT1 0x0f0
-
-#if 0
-#define HW_BCH_DEBUG0 0x100
-#define HW_BCH_DEBUG0_SET 0x104
-#define HW_BCH_DEBUG0_CLR 0x108
-#define HW_BCH_DEBUG0_TOG 0x10c
-
-#define BM_BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26)
-#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25)
-#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16
-#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL (0x1FF << BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL)
-#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) (((v) << BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL) & \
- BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL)
-#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0
-#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
-#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15)
-#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14)
-#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1
-#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1
-#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13)
-#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1
-#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1
-#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000
-#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800
-#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0
-#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1
-#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400
-#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200
-#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0
-#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1
-#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100
-#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0
-#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1
-#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0
-#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F
-#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) (((v) << BP_BCH_DEBUG0_DEBUG_REG_SELECT) & \
- BM_BCH_DEBUG0_DEBUG_REG_SELECT)
-
-#define HW_BCH_DBGKESREAD 0x110
-
-#define BP_BCH_DBGKESREAD_VALUES 0
-#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF
-#define BF_BCH_DBGKESREAD_VALUES(v) (v)
-
-#define HW_BCH_DBGCSFEREAD 0x120
-
-#define BP_BCH_DBGCSFEREAD_VALUES 0
-#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF
-#define BF_BCH_DBGCSFEREAD_VALUES(v) (v)
-
-#define HW_BCH_DBGSYNDGENREAD 0x130
-
-#define BP_BCH_DBGSYNDGENREAD_VALUES 0
-#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF
-#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (v)
-
-#define HW_BCH_DBGAHBMREAD 0x140
-
-#define BP_BCH_DBGAHBMREAD_VALUES 0
-#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF
-#define BF_BCH_DBGAHBMREAD_VALUES(v) (v)
-
-#define HW_BCH_BLOCKNAME 0x150
-
-#define BP_BCH_BLOCKNAME_NAME 0
-#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF
-#define BF_BCH_BLOCKNAME_NAME(v) (v)
-#endif
-
-#define HW_BCH_VERSION 0x160
-
-#define BP_BCH_VERSION_MAJOR 24
-#define BM_BCH_VERSION_MAJOR (0xFF << BP_BCH_VERSION_MAJOR)
-#define BF_BCH_VERSION_MAJOR(v) (((v) << BP_BCH_VERSION_MAJOR) & \
- BM_BCH_VERSION_MAJOR)
-#define BP_BCH_VERSION_MINOR 16
-#define BM_BCH_VERSION_MINOR (0xFF << BP_BCH_VERSION_MINOR)
-#define BF_BCH_VERSION_MINOR(v) (((v) << BP_BCH_VERSION_MINOR) & \
- BM_BCH_VERSION_MINOR)
-#define BP_BCH_VERSION_STEP 0
-#define BM_BCH_VERSION_STEP (0xFFFF << BP_BCH_VERSION_STEP)
-#define BF_BCH_VERSION_STEP(v) (((v) << BP_BCH_VERSION_STEP) & \
- BM_BCH_VERSION_STEP)
-
-#endif
+++ /dev/null
-/*
- * Freescale GPMI NFC NAND Flash Driver
- *
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Xml Revision: 2.2
- * Template revision: 26195
- */
-
-#ifndef __GPMI_NFC_GPMI_REGS_H
-#define __GPMI_NFC_GPMI_REGS_H
-
-/*============================================================================*/
-
-#define HW_GPMI_CTRL0 0x00000000
-#define HW_GPMI_CTRL0_SET 0x00000004
-#define HW_GPMI_CTRL0_CLR 0x00000008
-#define HW_GPMI_CTRL0_TOG 0x0000000c
-
-#define BM_GPMI_CTRL0_SFTRST (1 << 31)
-#define BV_GPMI_CTRL0_SFTRST__RUN 0x0
-#define BV_GPMI_CTRL0_SFTRST__RESET 0x1
-#define BM_GPMI_CTRL0_CLKGATE (1 << 30)
-#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0
-#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1
-#define BM_GPMI_CTRL0_RUN (1 << 29)
-#define BV_GPMI_CTRL0_RUN__IDLE 0x0
-#define BV_GPMI_CTRL0_RUN__BUSY 0x1
-#define BM_GPMI_CTRL0_DEV_IRQ_EN (1 << 28)
-/* V0 */
-#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN (1 << 27)
-/* V1 */
-#define BM_GPMI_CTRL0_LOCK_CS_V1 (1 << 27)
-
-#define BM_GPMI_CTRL0_UDMA (1 << 26)
-#define BP_GPMI_CTRL0_COMMAND_MODE 24
-#define BM_GPMI_CTRL0_COMMAND_MODE (0x3 << BP_GPMI_CTRL0_COMMAND_MODE)
-#define BF_GPMI_CTRL0_COMMAND_MODE(v) \
- (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE)
-#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
-#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
-#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
-#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
-#define BP_GPMI_CTRL0_WORD_LENGTH 23
-#define BM_GPMI_CTRL0_WORD_LENGTH (1 << BP_GPMI_CTRL0_WORD_LENGTH)
-#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT (0x0 << BP_GPMI_CTRL0_WORD_LENGTH)
-#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT (0x1 << BP_GPMI_CTRL0_WORD_LENGTH__8_BIT)
-#define BP_GPMI_CTRL0_CS 20
-/* V0 */
-#define BM_GPMI_CTRL0_LOCK_CS (1 << 22)
-#define BM_GPMI_CTRL0_CS (0x3 << BP_GPMI_CTRL0_CS)
-#define BF_GPMI_CTRL0_CS(v) (((v) << BP_GPMI_CTRL0_CS) & BM_GPMI_CTRL0_CS)
-/* V1 */
-#define BM_GPMI_CTRL0_CS_V1 (0x7 << BP_GPMI_CTRL0_CS)
-#define BF_GPMI_CTRL0_CS_V1(v) (((v) << BP_GPMI_CTRL0_CS) & BM_GPMI_CTRL0_CS_V1)
-
-#define BP_GPMI_CTRL0_ADDRESS 17
-#define BM_GPMI_CTRL0_ADDRESS (0x7 << BP_GPMI_CTRL0_ADDRESS)
-#define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & BM_GPMI_CTRL0_ADDRESS)
-#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
-#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
-#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
-#define BM_GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16)
-#define BP_GPMI_CTRL0_XFER_COUNT 0
-#define BM_GPMI_CTRL0_XFER_COUNT (0xFFFF << BP_GPMI_CTRL0_XFER_COUNT)
-#define BF_GPMI_CTRL0_XFER_COUNT(v) \
- (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT)
-
-/*============================================================================*/
-
-#define HW_GPMI_COMPARE 0x00000010
-
-#define BP_GPMI_COMPARE_MASK 16
-#define BM_GPMI_COMPARE_MASK (0xFFFF << BP_GPMI_COMPARE_MASK)
-#define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & BM_GPMI_COMPARE_MASK)
-#define BP_GPMI_COMPARE_REFERENCE 0
-#define BM_GPMI_COMPARE_REFERENCE (0xFFFF << BP_GPMI_COMPARE_REFERENCE)
-#define BF_GPMI_COMPARE_REFERENCE(v) (((v) << 0) & BM_GPMI_COMPARE_REFERENCE)
-
-/*============================================================================*/
-
-#define HW_GPMI_ECCCTRL 0x00000020
-#define HW_GPMI_ECCCTRL_SET 0x00000024
-#define HW_GPMI_ECCCTRL_CLR 0x00000028
-#define HW_GPMI_ECCCTRL_TOG 0x0000002c
-
-#define BP_GPMI_ECCCTRL_HANDLE 16
-#define BM_GPMI_ECCCTRL_HANDLE (0xFFFF << BP_GPMI_ECCCTRL_HANDLE)
-#define BF_GPMI_ECCCTRL_HANDLE(v) (((v) << BP_GPMI_ECCCTRL_HANDLE) & BM_GPMI_ECCCTRL_HANDLE)
-#define BP_GPMI_ECCCTRL_ECC_CMD 13
-#define BM_GPMI_ECCCTRL_ECC_CMD (3 << BP_GPMI_ECCCTRL_ECC_CMD)
-#define BF_GPMI_ECCCTRL_ECC_CMD(v) (((v) << BP_GPMI_ECCCTRL_ECC_CMD) & BM_GPMI_ECCCTRL_ECC_CMD)
-/* V0 */
-#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0x0
-#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 0x1
-#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 0x2
-#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 0x3
-#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE 0x0
-#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE 0x1
-/* V1 */
-#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE 0x0
-#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE 0x1
-
-#define BM_GPMI_ECCCTRL_ENABLE_ECC (1 << 12)
-#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
-#define BM_GPMI_ECCCTRL_BUFFER_MASK (0x1FF << BP_GPMI_ECCCTRL_BUFFER_MASK)
-#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK)
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF
-/* V0 */
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY 0x100
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7 0x080
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6 0x040
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5 0x020
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4 0x010
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3 0x008
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2 0x004
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1 0x002
-#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0 0x001
-
-/*============================================================================*/
-
-#define HW_GPMI_ECCCOUNT 0x00000030
-
-#define BP_GPMI_ECCCOUNT_COUNT 0
-#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF
-#define BF_GPMI_ECCCOUNT_COUNT(v) (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT)
-
-/*============================================================================*/
-
-#define HW_GPMI_PAYLOAD 0x00000040
-
-#define BP_GPMI_PAYLOAD_ADDRESS 2
-#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC
-#define BF_GPMI_PAYLOAD_ADDRESS(v) (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS)
-
-/*============================================================================*/
-
-#define HW_GPMI_AUXILIARY 0x00000050
-
-#define BP_GPMI_AUXILIARY_ADDRESS 2
-#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC
-#define BF_GPMI_AUXILIARY_ADDRESS(v) (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS)
-
-/*============================================================================*/
-
-#define HW_GPMI_CTRL1 0x00000060
-#define HW_GPMI_CTRL1_SET 0x00000064
-#define HW_GPMI_CTRL1_CLR 0x00000068
-#define HW_GPMI_CTRL1_TOG 0x0000006c
-
-/* V0 */
-#define BM_GPMI_CTRL1_CE3_SEL (1 << 23)
-#define BM_GPMI_CTRL1_CE2_SEL (1 << 22)
-#define BM_GPMI_CTRL1_CE1_SEL (1 << 21)
-#define BM_GPMI_CTRL1_CE0_SEL (1 << 20)
-/* V1 */
-#define BM_GPMI_CTRL1_DECOUPLE_CS (1 << 24)
-#define BP_GPMI_CTRL1_WRN_DLY_SEL 22
-#define BM_GPMI_CTRL1_WRN_DLY_SEL (3 << BP_GPMI_CTRL1_WRN_DLY_SEL)
-#define BF_GPMI_CTRL1_WRN_DLY_SEL(v) (((v) << BP_GPMI_CTRL1_WRN_DLY_SEL) & BM_GPMI_CTRL1_WRN_DLY_SEL)
-#define BM_GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20)
-
-#define BM_GPMI_CTRL1_GANGED_RDYBUSY (1 << 19)
-/* V0 */
-#define BP_GPMI_CTRL1_RDN_DELAY 12
-#define BM_GPMI_CTRL1_RDN_DELAY (0xf << BP_GPMI_CTRL1_RDN_DELAY)
-
-#define BM_GPMI_CTRL1_BCH_MODE (1 << 18)
-#define BP_GPMI_CTRL1_DLL_ENABLE 17
-#define BM_GPMI_CTRL1_DLL_ENABLE (1 << BP_GPMI_CTRL1_DLL_ENABLE)
-#define BP_GPMI_CTRL1_HALF_PERIOD 16
-#define BM_GPMI_CTRL1_HALF_PERIOD (1 << BP_GPMI_CTRL1_HALF_PERIOD)
-#define BP_GPMI_CTRL1_RDN_DELAY 12
-#define BM_GPMI_CTRL1_RDN_DELAY (0xf << BP_GPMI_CTRL1_RDN_DELAY)
-#define BF_GPMI_CTRL1_RDN_DELAY(v) (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY)
-#define BM_GPMI_CTRL1_DMA2ECC_MODE (1 << 11)
-#define BM_GPMI_CTRL1_DEV_IRQ (1 << 10)
-#define BM_GPMI_CTRL1_TIMEOUT_IRQ (1 << 9)
-#define BM_GPMI_CTRL1_BURST_EN (1 << 8)
-/* V0 */
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 (1 << 7)
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 (1 << 6)
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 (1 << 5)
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 (1 << 4)
-/* V1 */
-#define BM_GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7)
-#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 4
-#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL (0x7 << BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL)
-#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v) \
- (((v) << BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL)
-
-#define BM_GPMI_CTRL1_DEV_RESET (1 << 3)
-#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2)
-#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0
-#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
-#define BM_GPMI_CTRL1_CAMERA_MODE (1 << 1)
-#define BP_GPMI_CTRL1_GPMI_MODE 0
-#define BM_GPMI_CTRL1_GPMI_MODE (0x1 << BP_GPMI_CTRL1_GPMI_MODE)
-#define BV_GPMI_CTRL1_GPMI_MODE__NAND (0x0 << BP_GPMI_CTRL1_GPMI_MODE)
-#define BV_GPMI_CTRL1_GPMI_MODE__ATA (0x1 << BP_GPMI_CTRL1_GPMI_MODE)
-
-/*============================================================================*/
-
-#define HW_GPMI_TIMING0 0x00000070
-
-#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
-#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000
-#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \
- (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP)
-#define BP_GPMI_TIMING0_DATA_HOLD 8
-#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
-#define BF_GPMI_TIMING0_DATA_HOLD(v) \
- (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD)
-#define BP_GPMI_TIMING0_DATA_SETUP 0
-#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
-#define BF_GPMI_TIMING0_DATA_SETUP(v) \
- (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP)
-
-/*============================================================================*/
-
-#define HW_GPMI_TIMING1 0x00000080
-
-#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
-#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
-#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \
- (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT)
-
-/*============================================================================*/
-
-#define HW_GPMI_TIMING2 0x00000090
-
-#define BP_GPMI_TIMING2_UDMA_TRP 24
-#define BM_GPMI_TIMING2_UDMA_TRP 0xFF000000
-#define BF_GPMI_TIMING2_UDMA_TRP(v) \
- (((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP)
-#define BP_GPMI_TIMING2_UDMA_ENV 16
-#define BM_GPMI_TIMING2_UDMA_ENV 0x00FF0000
-#define BF_GPMI_TIMING2_UDMA_ENV(v) \
- (((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV)
-#define BP_GPMI_TIMING2_UDMA_HOLD 8
-#define BM_GPMI_TIMING2_UDMA_HOLD 0x0000FF00
-#define BF_GPMI_TIMING2_UDMA_HOLD(v) \
- (((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD)
-#define BP_GPMI_TIMING2_UDMA_SETUP 0
-#define BM_GPMI_TIMING2_UDMA_SETUP 0x000000FF
-#define BF_GPMI_TIMING2_UDMA_SETUP(v) \
- (((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP)
-
-/*============================================================================*/
-
-#define HW_GPMI_DATA 0x000000a0
-#define HW_GPMI_STAT 0x000000b0
-
-/* V0 */
-#define BM_GPMI_STAT_PRESENT (1 << 31)
-#define BP_GPMI_STAT_RDY_TIMEOUT 8
-#define BM_GPMI_STAT_RDY_TIMEOUT (0xf << BP_GPMI_STAT_RDY_TIMEOUT)
-#define BF_GPMI_STAT_RDY_TIMEOUT(v) \
- (((v) << BP_GPMI_STAT_RDY_TIMEOUT) & BM_GPMI_STAT_RDY_TIMEOUT)
-#define BM_GPMI_STAT_ATA_IRQ (1 << 7)
-#define BM_GPMI_STAT_INVALID_BUFFER_MASK (1 << 6)
-#define BM_GPMI_STAT_FIFO_EMPTY (1 << 5)
-#define BM_GPMI_STAT_FIFO_FULL (1 << 4)
-#define BM_GPMI_STAT_DEV3_ERROR (1 << 3)
-#define BM_GPMI_STAT_DEV2_ERROR (1 << 2)
-#define BM_GPMI_STAT_DEV1_ERROR (1 << 1)
-#define BM_GPMI_STAT_DEERROR (1 << 0)
-/* V1 */
-#define BP_GPMI_STAT_READY_BUSY 24
-#define BM_GPMI_STAT_READY_BUSY (0xFF << BP_GPMI_STAT_READY_BUSY)
-#define BF_GPMI_STAT_READY_BUSY(v) \
- (((v) << BP_GPMI_STAT_READY_BUSY) & BM_GPMI_STAT_READY_BUSY)
-#define BP_GPMI_STAT_RDY_TIMEOUT_V1 16
-#define BM_GPMI_STAT_RDY_TIMEOUT_V1 (0xFF << BP_GPMI_STAT_RDY_TIMEOUT_V1)
-#define BF_GPMI_STAT_RDY_TIMEOUT_V1(v) (((v) << BM_GPMI_STAT_RDY_TIMEOUT_V1) & BM_GPMI_STAT_RDY_TIMEOUT_V1)
-#define BM_GPMI_STAT_DEV7_ERROR (1 << 15)
-#define BM_GPMI_STAT_DEV6_ERROR (1 << 14)
-#define BM_GPMI_STAT_DEV5_ERROR (1 << 13)
-#define BM_GPMI_STAT_DEV4_ERROR (1 << 12)
-#define BM_GPMI_STAT_DEV3_ERROR_V1 (1 << 11)
-#define BM_GPMI_STAT_DEV2_ERROR_V1 (1 << 10)
-#define BM_GPMI_STAT_DEERROR_V1 (1 << 9)
-#define BM_GPMI_STAT_DEV0_ERROR (1 << 5)
-#define BM_GPMI_STAT_ATA_IRQ_V1 (1 << 4)
-#define BM_GPMI_STAT_INVALID_BUFFER_MASK_V1 (1 << 3)
-#define BM_GPMI_STAT_FIFO_EMPTY_V1 (1 << 2)
-#define BM_GPMI_STAT_FIFO_FULL_V1 (1 << 1)
-#define BM_GPMI_STAT_PRESENT_V1 (1 << 0)
-
-/*============================================================================*/
-
-#define HW_GPMI_DEBUG 0x000000c0
-
-/* V0 */
-#define BM_GPMI_DEBUG_READY3 (1 << 31)
-#define BM_GPMI_DEBUG_READY2 (1 << 30)
-#define BM_GPMI_DEBUG_READY1 (1 << 29)
-#define BM_GPMI_DEBUG_READY0 (1 << 28)
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3 (1 << 27)
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2 (1 << 26)
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1 (1 << 25)
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0 (1 << 24)
-#define BM_GPMI_DEBUG_SENSE3 (1 << 23)
-#define BM_GPMI_DEBUG_SENSE2 (1 << 22)
-#define BM_GPMI_DEBUG_SENSE1 (1 << 21)
-#define BM_GPMI_DEBUG_SENSE0 (1 << 20)
-#define BM_GPMI_DEBUG_DMAREQ3 (1 << 19)
-#define BM_GPMI_DEBUG_DMAREQ2 (1 << 18)
-#define BM_GPMI_DEBUG_DMAREQ1 (1 << 17)
-#define BM_GPMI_DEBUG_DMAREQ0 (1 << 16)
-#define BP_GPMI_DEBUG_CMD_END (1 << 12)
-#define BM_GPMI_DEBUG_CMD_END (0xF << BP_GPMI_DEBUG_CMD_END)
-#define BF_GPMI_DEBUG_CMD_END(v) \
- (((v) << BP_GPMI_DEBUG_CMD_END) & BM_GPMI_DEBUG_CMD_END)
-#define BP_GPMI_DEBUG_UDMA_STATE 8
-#define BM_GPMI_DEBUG_UDMA_STATE (0xf << BP_GPMI_DEBUG_UDMA_STATE)
-#define BF_GPMI_DEBUG_UDMA_STATE(v) \
- (((v) << BP_GPMI_DEBUG_UDMA_STATE) & BM_GPMI_DEBUG_UDMA_STATE)
-#define BM_GPMI_DEBUG_BUSY (1 << 7)
-#define BP_GPMI_DEBUG_PIN_STATE 4
-#define BM_GPMI_DEBUG_PIN_STATE (0x7 << BP_GPMI_DEBUG_PIN_STATE)
-#define BF_GPMI_DEBUG_PIN_STATE(v) \
- (((v) << BP_GPMI_DEBUG_PIN_STATE) & BM_GPMI_DEBUG_PIN_STATE)
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE 0x0
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR 0x2
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL 0x3
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD 0x6
-#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE 0x7
-#define BP_GPMI_DEBUG_MAIN_STATE 0
-#define BM_GPMI_DEBUG_MAIN_STATE (0xF << BP_GPMI_DEBUG_MAIN_STATE)
-#define BF_GPMI_DEBUG_MAIN_STATE(v) \
- (((v) << BP_GPMI_DEBUG_MAIN_STATE) & BM_GPMI_DEBUG_MAIN_STATE)
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE 0x0
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP 0x9
-#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE 0xA
-/* V1 */
-#define BP_GPMI_DEBUG_WAIT_FOR_READY_END 24
-#define BM_GPMI_DEBUG_WAIT_FOR_READY_END (0xFF << BP_GPMI_DEBUG_WAIT_FOR_READY_END)
-#define BF_GPMI_DEBUG_WAIT_FOR_READY_END(v) \
- (((v) << BP_GPMI_DEBUG_WAIT_FOR_READY_END) & BM_GPMI_DEBUG_WAIT_FOR_READY_END)
-#define BP_GPMI_DEBUG_DMA_SENSE 16
-#define BM_GPMI_DEBUG_DMA_SENSE (0xFF << BP_GPMI_DEBUG_DMA_SENSE)
-#define BF_GPMI_DEBUG_DMA_SENSE(v) \
- (((v) << BP_GPMI_DEBUG_DMA_SENSE) & BM_GPMI_DEBUG_DMA_SENSE)
-#define BP_GPMI_DEBUG_DMAREQ 8
-#define BM_GPMI_DEBUG_DMAREQ (0xFF << BP_GPMI_DEBUG_DMAREQ)
-#define BF_GPMI_DEBUG_DMAREQ(v) \
- (((v) << BP_GPMI_DEBUG_DMAREQ) & BM_GPMI_DEBUG_DMAREQ)
-#define BP_GPMI_DEBUG_CMD_END_V1 0
-#define BM_GPMI_DEBUG_CMD_END_V1 (0xFF << BP_GPMI_DEBUG_CMD_END)
-#define BF_GPMI_DEBUG_CMD_END_V1(v) \
- (((v) << BP_GPMI_DEBUG_CMD_END) & BM_GPMI_DEBUG_CMD_END)
-
-/*============================================================================*/
-
-#define HW_GPMI_VERSION 0x000000d0
-
-#define BP_GPMI_VERSION_MAJOR 24
-#define BM_GPMI_VERSION_MAJOR (0xFF << BP_GPMI_VERSION_MAJOR)
-#define BF_GPMI_VERSION_MAJOR(v) (((v) << BP_GPMI_VERSION_MAJOR) & BM_GPMI_VERSION_MAJOR)
-#define BP_GPMI_VERSION_MINOR 16
-#define BM_GPMI_VERSION_MINOR (0xFF << BP_GPMI_VERSION_MINOR)
-#define BF_GPMI_VERSION_MINOR(v) (((v) << BP_GPMI_VERSION_MINOR) & BM_GPMI_VERSION_MINOR)
-#define BP_GPMI_VERSION_STEP 0
-#define BM_GPMI_VERSION_STEP (0xFFFF << BP_GPMI_VERSION_STEP)
-#define BF_GPMI_VERSION_STEP(v) (((v) << BP_GPMI_VERSION_STEP) & BM_GPMI_VERSION_STEP)
-
-/*============================================================================*/
-
-#define HW_GPMI_DEBUG2 0x000000e0
-
-/* V1 */
-#define BP_GPMI_DEBUG2_UDMA_STATE 24
-#define BM_GPMI_DEBUG2_UDMA_STATE (0xF << BP_GPMI_DEBUG2_UDMA_STATE)
-#define BF_GPMI_DEBUG2_UDMA_STATE(v) \
- (((v) << BP_GPMI_DEBUG2_UDMA_STATE) & BM_GPMI_DEBUG2_UDMA_STATE)
-#define BM_GPMI_DEBUG2_BUSY (1 << 23)
-#define BP_GPMI_DEBUG2_PIN_STATE 20
-#define BM_GPMI_DEBUG2_PIN_STATE (0x7 << BP_GPMI_DEBUG2_PIN_STATE)
-#define BF_GPMI_DEBUG2_PIN_STATE(v) \
- (((v) << BP_GPMI_DEBUG2_PIN_STATE) & BM_GPMI_DEBUG2_PIN_STATE)
-#define BV_GPMI_DEBUG2_PIN_STATE__PSM_IDLE 0x0
-#define BV_GPMI_DEBUG2_PIN_STATE__PSM_BYTCNT 0x1
-#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ADDR 0x2
-#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STALL 0x3
-#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STROBE 0x4
-#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ATARDY 0x5
-#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DHOLD 0x6
-#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DONE 0x7
-#define BP_GPMI_DEBUG2_MAIN_STATE 16
-#define BM_GPMI_DEBUG2_MAIN_STATE (0xF << BP_GPMI_DEBUG2_MAIN_STATE)
-#define BF_GPMI_DEBUG2_MAIN_STATE(v) \
- (((v) << BP_GPMI_DEBUG2_MAIN_STATE) & BM_GPMI_DEBUG2_MAIN_STATE)
-#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_IDLE 0x0
-#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_BYTCNT 0x1
-#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFE 0x2
-#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFR 0x3
-#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAREQ 0x4
-#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAACK 0x5
-#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFF 0x6
-#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDFIFO 0x7
-#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDDMAR 0x8
-#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_RDCMP 0x9
-#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DONE 0xA
-#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12
-#define BM_GPMI_DEBUG2_SYND2GPMI_BE (0xF << BP_GPMI_DEBUG2_SYND2GPMI_BE)
-#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) (((v) << BP_GPMI_DEBUG2_SYND2GPMI_BE) & BM_GPMI_DEBUG2_SYND2GPMI_BE)
-#define BM_GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11)
-#define BM_GPMI_DEBUG2_GPMI2SYND_READY (1 << 10)
-#define BM_GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9)
-#define BM_GPMI_DEBUG2_SYND2GPMI_READY (1 << 8)
-#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7)
-#define BM_GPMI_DEBUG2_UPDATE_WINDOW (1 << 6)
-#define BP_GPMI_DEBUG2_RDN_TAP 0
-#define BM_GPMI_DEBUG2_RDN_TAP (0x3F << BP_GPMI_DEBUG2_RDN_TAP)
-#define BF_GPMI_DEBUG2_RDN_TAP(v) (((v) << BP_GPMI_DEBUG2_RDN_TAP) & BM_GPMI_DEBUG2_RDN_TAP)
-
-/*============================================================================*/
-
-#define HW_GPMI_DEBUG3 0x000000f0
-
-#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16
-#define BM_GPMI_DEBUG3_APB_WORD_CNTR (0xFFFF << BP_GPMI_DEBUG3_APB_WORD_CNTR)
-#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) (((v) << )BP_GPMI_DEBUG3_APB_WORD_CNTR & BM_GPMI_DEBUG3_APB_WORD_CNTR)
-#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0
-#define BM_GPMI_DEBUG3_DEV_WORD_CNTR (0xFFFF << BP_GPMI_DEBUG3_DEV_WORD_CNTR)
-#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) (((v) << BP_GPMI_DEBUG3_DEV_WORD_CNTR) & BM_GPMI_DEBUG3_DEV_WORD_CNTR)
-
-/*============================================================================*/
-#endif
+++ /dev/null
-/*
- *
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __PINCTRL_H
-#define __PINCTRL_H
-
-#define PIN_BITS 5
-#define PINS_PER_BANK (1 << PIN_BITS)
-#define PINID_2_BANK(id) ((id) >> PIN_BITS)
-#define PINID_2_PIN(id) ((id) & (PINS_PER_BANK - 1))
-#define PINID_ENCODE(bank, pin) (((bank) << PIN_BITS) + (pin))
-
-/*
- * Each pin may be routed up to four different HW interfaces
- * including GPIO
- */
-enum pin_fun {
- PIN_FUN1 = 0,
- PIN_FUN2,
- PIN_FUN3,
- PIN_GPIO
-};
-
-/*
- * Each pin may have different output drive strength in range from
- * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths.
- */
-enum pad_strength {
- PAD_4MA = 0,
- PAD_8MA,
- PAD_12MA,
- PAD_RESV
-};
-
-/*
- * Each pin can be programmed for 1.8V or 3.3V
- */
-enum pad_voltage {
- PAD_1V8 = 0,
- PAD_3V3
-};
-
-/*
- * Structure to define a group of pins and their parameters
- */
-struct pin_desc {
- u32 id;
- enum pin_fun fun;
- enum pad_strength strength;
- enum pad_voltage voltage;
- u32 pullup:1;
-};
-
-struct pin_group {
- struct pin_desc *pins;
- int nr_pins;
-};
-
-extern void pin_gpio_direction(u32 id, u32 output);
-extern u32 pin_gpio_get(u32 id);
-extern void pin_gpio_set(u32 id, u32 val);
-extern void pin_set_type(u32 id, enum pin_fun cfg);
-extern void pin_set_strength(u32 id, enum pad_strength strength);
-extern void pin_set_voltage(u32 id, enum pad_voltage volt);
-extern void pin_set_pullup(u32 id, u32 pullup);
-extern void pin_set_group(struct pin_group *pin_group);
-
-/*
- * Definitions of all i.MX28 pins
- */
-/* Bank 0 */
-#define PINID_GPMI_D00 PINID_ENCODE(0, 0)
-#define PINID_GPMI_D01 PINID_ENCODE(0, 1)
-#define PINID_GPMI_D02 PINID_ENCODE(0, 2)
-#define PINID_GPMI_D03 PINID_ENCODE(0, 3)
-#define PINID_GPMI_D04 PINID_ENCODE(0, 4)
-#define PINID_GPMI_D05 PINID_ENCODE(0, 5)
-#define PINID_GPMI_D06 PINID_ENCODE(0, 6)
-#define PINID_GPMI_D07 PINID_ENCODE(0, 7)
-#define PINID_GPMI_CE0N PINID_ENCODE(0, 16)
-#define PINID_GPMI_CE1N PINID_ENCODE(0, 17)
-#define PINID_GPMI_CE2N PINID_ENCODE(0, 18)
-#define PINID_GPMI_CE3N PINID_ENCODE(0, 19)
-#define PINID_GPMI_RDY0 PINID_ENCODE(0, 20)
-#define PINID_GPMI_RDY1 PINID_ENCODE(0, 21)
-#define PINID_GPMI_RDY2 PINID_ENCODE(0, 22)
-#define PINID_GPMI_RDY3 PINID_ENCODE(0, 23)
-#define PINID_GPMI_RDN PINID_ENCODE(0, 24)
-#define PINID_GPMI_WRN PINID_ENCODE(0, 25)
-#define PINID_GPMI_ALE PINID_ENCODE(0, 26)
-#define PINID_GPMI_CLE PINID_ENCODE(0, 27)
-#define PINID_GPMI_RESETN PINID_ENCODE(0, 28)
-
-/* Bank 1 */
-#define PINID_LCD_D00 PINID_ENCODE(1, 0)
-#define PINID_LCD_D01 PINID_ENCODE(1, 1)
-#define PINID_LCD_D02 PINID_ENCODE(1, 2)
-#define PINID_LCD_D03 PINID_ENCODE(1, 3)
-#define PINID_LCD_D04 PINID_ENCODE(1, 4)
-#define PINID_LCD_D05 PINID_ENCODE(1, 5)
-#define PINID_LCD_D06 PINID_ENCODE(1, 6)
-#define PINID_LCD_D07 PINID_ENCODE(1, 7)
-#define PINID_LCD_D08 PINID_ENCODE(1, 8)
-#define PINID_LCD_D09 PINID_ENCODE(1, 9)
-#define PINID_LCD_D10 PINID_ENCODE(1, 10)
-#define PINID_LCD_D11 PINID_ENCODE(1, 11)
-#define PINID_LCD_D12 PINID_ENCODE(1, 12)
-#define PINID_LCD_D13 PINID_ENCODE(1, 13)
-#define PINID_LCD_D14 PINID_ENCODE(1, 14)
-#define PINID_LCD_D15 PINID_ENCODE(1, 15)
-#define PINID_LCD_D16 PINID_ENCODE(1, 16)
-#define PINID_LCD_D17 PINID_ENCODE(1, 17)
-#define PINID_LCD_D18 PINID_ENCODE(1, 18)
-#define PINID_LCD_D19 PINID_ENCODE(1, 19)
-#define PINID_LCD_D20 PINID_ENCODE(1, 20)
-#define PINID_LCD_D21 PINID_ENCODE(1, 21)
-#define PINID_LCD_D22 PINID_ENCODE(1, 22)
-#define PINID_LCD_D23 PINID_ENCODE(1, 23)
-#define PINID_LCD_RD_E PINID_ENCODE(1, 24)
-#define PINID_LCD_WR_RWN PINID_ENCODE(1, 25)
-#define PINID_LCD_RS PINID_ENCODE(1, 26)
-#define PINID_LCD_CS PINID_ENCODE(1, 27)
-#define PINID_LCD_VSYNC PINID_ENCODE(1, 28)
-#define PINID_LCD_HSYNC PINID_ENCODE(1, 29)
-#define PINID_LCD_DOTCK PINID_ENCODE(1, 30)
-#define PINID_LCD_ENABLE PINID_ENCODE(1, 31)
-
-/* Bank 2 */
-#define PINID_SSP0_DATA0 PINID_ENCODE(2, 0)
-#define PINID_SSP0_DATA1 PINID_ENCODE(2, 1)
-#define PINID_SSP0_DATA2 PINID_ENCODE(2, 2)
-#define PINID_SSP0_DATA3 PINID_ENCODE(2, 3)
-#define PINID_SSP0_DATA4 PINID_ENCODE(2, 4)
-#define PINID_SSP0_DATA5 PINID_ENCODE(2, 5)
-#define PINID_SSP0_DATA6 PINID_ENCODE(2, 6)
-#define PINID_SSP0_DATA7 PINID_ENCODE(2, 7)
-#define PINID_SSP0_CMD PINID_ENCODE(2, 8)
-#define PINID_SSP0_DETECT PINID_ENCODE(2, 9)
-#define PINID_SSP0_SCK PINID_ENCODE(2, 10)
-#define PINID_SSP1_SCK PINID_ENCODE(2, 12)
-#define PINID_SSP1_CMD PINID_ENCODE(2, 13)
-#define PINID_SSP1_DATA0 PINID_ENCODE(2, 14)
-#define PINID_SSP1_DATA3 PINID_ENCODE(2, 15)
-#define PINID_SSP2_SCK PINID_ENCODE(2, 16)
-#define PINID_SSP2_MOSI PINID_ENCODE(2, 17)
-#define PINID_SSP2_MISO PINID_ENCODE(2, 18)
-#define PINID_SSP2_SS0 PINID_ENCODE(2, 19)
-#define PINID_SSP2_SS1 PINID_ENCODE(2, 20)
-#define PINID_SSP2_SS2 PINID_ENCODE(2, 21)
-#define PINID_SSP3_SCK PINID_ENCODE(2, 24)
-#define PINID_SSP3_MOSI PINID_ENCODE(2, 25)
-#define PINID_SSP3_MISO PINID_ENCODE(2, 26)
-#define PINID_SSP3_SS0 PINID_ENCODE(2, 27)
-
-/* Bank 3 */
-#define PINID_AUART0_RX PINID_ENCODE(3, 0)
-#define PINID_AUART0_TX PINID_ENCODE(3, 1)
-#define PINID_AUART0_CTS PINID_ENCODE(3, 2)
-#define PINID_AUART0_RTS PINID_ENCODE(3, 3)
-#define PINID_AUART1_RX PINID_ENCODE(3, 4)
-#define PINID_AUART1_TX PINID_ENCODE(3, 5)
-#define PINID_AUART1_CTS PINID_ENCODE(3, 6)
-#define PINID_AUART1_RTS PINID_ENCODE(3, 7)
-#define PINID_AUART2_RX PINID_ENCODE(3, 8)
-#define PINID_AUART2_TX PINID_ENCODE(3, 9)
-#define PINID_AUART2_CTS PINID_ENCODE(3, 10)
-#define PINID_AUART2_RTS PINID_ENCODE(3, 11)
-#define PINID_AUART3_RX PINID_ENCODE(3, 12)
-#define PINID_AUART3_TX PINID_ENCODE(3, 13)
-#define PINID_AUART3_CTS PINID_ENCODE(3, 14)
-#define PINID_AUART3_RTS PINID_ENCODE(3, 15)
-#define PINID_PWM0 PINID_ENCODE(3, 16)
-#define PINID_PWM1 PINID_ENCODE(3, 17)
-#define PINID_PWM2 PINID_ENCODE(3, 18)
-#define PINID_SAIF0_MCLK PINID_ENCODE(3, 20)
-#define PINID_SAIF0_LRCLK PINID_ENCODE(3, 21)
-#define PINID_SAIF0_BITCLK PINID_ENCODE(3, 22)
-#define PINID_SAIF0_SDATA0 PINID_ENCODE(3, 23)
-#define PINID_I2C0_SCL PINID_ENCODE(3, 24)
-#define PINID_I2C0_SDA PINID_ENCODE(3, 25)
-#define PINID_SAIF1_SDATA0 PINID_ENCODE(3, 26)
-#define PINID_SPDIF PINID_ENCODE(3, 27)
-#define PINID_PWM3 PINID_ENCODE(3, 28)
-#define PINID_PWM4 PINID_ENCODE(3, 29)
-#define PINID_LCD_RESET PINID_ENCODE(3, 30)
-
-/* Bank 4 */
-#define PINID_ENET0_MDC PINID_ENCODE(4, 0)
-#define PINID_ENET0_MDIO PINID_ENCODE(4, 1)
-#define PINID_ENET0_RX_EN PINID_ENCODE(4, 2)
-#define PINID_ENET0_RXD0 PINID_ENCODE(4, 3)
-#define PINID_ENET0_RXD1 PINID_ENCODE(4, 4)
-#define PINID_ENET0_TX_CLK PINID_ENCODE(4, 5)
-#define PINID_ENET0_TX_EN PINID_ENCODE(4, 6)
-#define PINID_ENET0_TXD0 PINID_ENCODE(4, 7)
-#define PINID_ENET0_TXD1 PINID_ENCODE(4, 8)
-#define PINID_ENET0_RXD2 PINID_ENCODE(4, 9)
-#define PINID_ENET0_RXD3 PINID_ENCODE(4, 10)
-#define PINID_ENET0_TXD2 PINID_ENCODE(4, 11)
-#define PINID_ENET0_TXD3 PINID_ENCODE(4, 12)
-#define PINID_ENET0_RX_CLK PINID_ENCODE(4, 13)
-#define PINID_ENET0_COL PINID_ENCODE(4, 14)
-#define PINID_ENET0_CRS PINID_ENCODE(4, 15)
-#define PINID_ENET_CLK PINID_ENCODE(4, 16)
-#define PINID_JTAG_RTCK PINID_ENCODE(4, 20)
-
-#endif
+++ /dev/null
-/*
- * Freescale CLKCTRL Register Definitions
- *
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * This file is created by xml file. Don't Edit it.
- *
- * Xml Revision: 1.48
- * Template revision: 26195
- */
-
-#ifndef __ARCH_ARM___CLKCTRL_H
-#define __ARCH_ARM___CLKCTRL_H
-
-
-#define HW_CLKCTRL_PLL0CTRL0 (0x00000000)
-#define HW_CLKCTRL_PLL0CTRL0_SET (0x00000004)
-#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008)
-#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c)
-
-#define BP_CLKCTRL_PLL0CTRL0_RSRVD6 30
-#define BM_CLKCTRL_PLL0CTRL0_RSRVD6 0xC0000000
-#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \
- (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6)
-#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28
-#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000
-#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \
- (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL)
-#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT 0x0
-#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1
-#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2
-#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL0CTRL0_RSRVD5 26
-#define BM_CLKCTRL_PLL0CTRL0_RSRVD5 0x0C000000
-#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v) \
- (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5)
-#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24
-#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000
-#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \
- (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL)
-#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT 0x0
-#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1
-#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2
-#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL0CTRL0_RSRVD4 22
-#define BM_CLKCTRL_PLL0CTRL0_RSRVD4 0x00C00000
-#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v) \
- (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4)
-#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20
-#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000
-#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \
- (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL)
-#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT 0x0
-#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1
-#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2
-#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_PLL0CTRL0_RSRVD3 0x00080000
-#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000
-#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000
-#define BP_CLKCTRL_PLL0CTRL0_RSRVD1 0
-#define BM_CLKCTRL_PLL0CTRL0_RSRVD1 0x0001FFFF
-#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v) \
- (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1)
-
-#define HW_CLKCTRL_PLL0CTRL1 (0x00000010)
-
-#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000
-#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000
-#define BP_CLKCTRL_PLL0CTRL1_RSRVD1 16
-#define BM_CLKCTRL_PLL0CTRL1_RSRVD1 0x3FFF0000
-#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v) \
- (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1)
-#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0
-#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF
-#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \
- (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT)
-
-#define HW_CLKCTRL_PLL1CTRL0 (0x00000020)
-#define HW_CLKCTRL_PLL1CTRL0_SET (0x00000024)
-#define HW_CLKCTRL_PLL1CTRL0_CLR (0x00000028)
-#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c)
-
-#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000
-#define BM_CLKCTRL_PLL1CTRL0_RSRVD6 0x40000000
-#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28
-#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000
-#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \
- (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL)
-#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT 0x0
-#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1
-#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2
-#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL1CTRL0_RSRVD5 26
-#define BM_CLKCTRL_PLL1CTRL0_RSRVD5 0x0C000000
-#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v) \
- (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5)
-#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24
-#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000
-#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \
- (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL)
-#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT 0x0
-#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1
-#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2
-#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL1CTRL0_RSRVD4 22
-#define BM_CLKCTRL_PLL1CTRL0_RSRVD4 0x00C00000
-#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v) \
- (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4)
-#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20
-#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000
-#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \
- (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL)
-#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT 0x0
-#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1
-#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2
-#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_PLL1CTRL0_RSRVD3 0x00080000
-#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000
-#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000
-#define BP_CLKCTRL_PLL1CTRL0_RSRVD1 0
-#define BM_CLKCTRL_PLL1CTRL0_RSRVD1 0x0001FFFF
-#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v) \
- (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1)
-
-#define HW_CLKCTRL_PLL1CTRL1 (0x00000030)
-
-#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000
-#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000
-#define BP_CLKCTRL_PLL1CTRL1_RSRVD1 16
-#define BM_CLKCTRL_PLL1CTRL1_RSRVD1 0x3FFF0000
-#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v) \
- (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1)
-#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0
-#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF
-#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \
- (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT)
-
-#define HW_CLKCTRL_PLL2CTRL0 (0x00000040)
-#define HW_CLKCTRL_PLL2CTRL0_SET (0x00000044)
-#define HW_CLKCTRL_PLL2CTRL0_CLR (0x00000048)
-#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c)
-
-#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000
-#define BM_CLKCTRL_PLL2CTRL0_RSRVD3 0x40000000
-#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28
-#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000
-#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \
- (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL)
-#define BM_CLKCTRL_PLL2CTRL0_RSRVD2 0x08000000
-#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000
-#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24
-#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000
-#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \
- (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL)
-#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000
-#define BP_CLKCTRL_PLL2CTRL0_RSRVD1 0
-#define BM_CLKCTRL_PLL2CTRL0_RSRVD1 0x007FFFFF
-#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v) \
- (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1)
-
-#define HW_CLKCTRL_CPU (0x00000050)
-#define HW_CLKCTRL_CPU_SET (0x00000054)
-#define HW_CLKCTRL_CPU_CLR (0x00000058)
-#define HW_CLKCTRL_CPU_TOG (0x0000005c)
-
-#define BP_CLKCTRL_CPU_RSRVD5 30
-#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000
-#define BF_CLKCTRL_CPU_RSRVD5(v) \
- (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
-#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
-#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
-#define BM_CLKCTRL_CPU_RSRVD4 0x08000000
-#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
-#define BP_CLKCTRL_CPU_DIV_XTAL 16
-#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
-#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
- (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
-#define BP_CLKCTRL_CPU_RSRVD3 13
-#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000
-#define BF_CLKCTRL_CPU_RSRVD3(v) \
- (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
-#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
-#define BM_CLKCTRL_CPU_RSRVD2 0x00000800
-#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
-#define BP_CLKCTRL_CPU_RSRVD1 6
-#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0
-#define BF_CLKCTRL_CPU_RSRVD1(v) \
- (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
-#define BP_CLKCTRL_CPU_DIV_CPU 0
-#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
-#define BF_CLKCTRL_CPU_DIV_CPU(v) \
- (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
-
-#define HW_CLKCTRL_HBUS (0x00000060)
-#define HW_CLKCTRL_HBUS_SET (0x00000064)
-#define HW_CLKCTRL_HBUS_CLR (0x00000068)
-#define HW_CLKCTRL_HBUS_TOG (0x0000006c)
-
-#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000
-#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000
-#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000
-#define BM_CLKCTRL_HBUS_RSRVD2 0x10000000
-#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000
-#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
-#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
-#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000
-#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000
-#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
-#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
-#define BM_CLKCTRL_HBUS_ASM_ENABLE 0x00100000
-#define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE 0x00080000
-#define BP_CLKCTRL_HBUS_SLOW_DIV 16
-#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
-#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
- (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
-#define BP_CLKCTRL_HBUS_RSRVD1 6
-#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0
-#define BF_CLKCTRL_HBUS_RSRVD1(v) \
- (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
-#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
-#define BP_CLKCTRL_HBUS_DIV 0
-#define BM_CLKCTRL_HBUS_DIV 0x0000001F
-#define BF_CLKCTRL_HBUS_DIV(v) \
- (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
-
-#define HW_CLKCTRL_XBUS (0x00000070)
-
-#define BM_CLKCTRL_XBUS_BUSY 0x80000000
-#define BP_CLKCTRL_XBUS_RSRVD1 12
-#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF000
-#define BF_CLKCTRL_XBUS_RSRVD1(v) \
- (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1)
-#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800
-#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
-#define BP_CLKCTRL_XBUS_DIV 0
-#define BM_CLKCTRL_XBUS_DIV 0x000003FF
-#define BF_CLKCTRL_XBUS_DIV(v) \
- (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
-
-#define HW_CLKCTRL_XTAL (0x00000080)
-#define HW_CLKCTRL_XTAL_SET (0x00000084)
-#define HW_CLKCTRL_XTAL_CLR (0x00000088)
-#define HW_CLKCTRL_XTAL_TOG (0x0000008c)
-
-#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
-#define BM_CLKCTRL_XTAL_RSRVD3 0x40000000
-#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
-#define BP_CLKCTRL_XTAL_RSRVD2 27
-#define BM_CLKCTRL_XTAL_RSRVD2 0x18000000
-#define BF_CLKCTRL_XTAL_RSRVD2(v) \
- (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2)
-#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
-#define BP_CLKCTRL_XTAL_RSRVD1 2
-#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC
-#define BF_CLKCTRL_XTAL_RSRVD1(v) \
- (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
-#define BP_CLKCTRL_XTAL_DIV_UART 0
-#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
-#define BF_CLKCTRL_XTAL_DIV_UART(v) \
- (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
-
-#define HW_CLKCTRL_SSP0 (0x00000090)
-
-#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP0_RSRVD2 0x40000000
-#define BM_CLKCTRL_SSP0_BUSY 0x20000000
-#define BP_CLKCTRL_SSP0_RSRVD1 10
-#define BM_CLKCTRL_SSP0_RSRVD1 0x1FFFFC00
-#define BF_CLKCTRL_SSP0_RSRVD1(v) \
- (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1)
-#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200
-#define BP_CLKCTRL_SSP0_DIV 0
-#define BM_CLKCTRL_SSP0_DIV 0x000001FF
-#define BF_CLKCTRL_SSP0_DIV(v) \
- (((v) << 0) & BM_CLKCTRL_SSP0_DIV)
-
-#define HW_CLKCTRL_SSP1 (0x000000a0)
-
-#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP1_RSRVD2 0x40000000
-#define BM_CLKCTRL_SSP1_BUSY 0x20000000
-#define BP_CLKCTRL_SSP1_RSRVD1 10
-#define BM_CLKCTRL_SSP1_RSRVD1 0x1FFFFC00
-#define BF_CLKCTRL_SSP1_RSRVD1(v) \
- (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1)
-#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200
-#define BP_CLKCTRL_SSP1_DIV 0
-#define BM_CLKCTRL_SSP1_DIV 0x000001FF
-#define BF_CLKCTRL_SSP1_DIV(v) \
- (((v) << 0) & BM_CLKCTRL_SSP1_DIV)
-
-#define HW_CLKCTRL_SSP2 (0x000000b0)
-
-#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP2_RSRVD2 0x40000000
-#define BM_CLKCTRL_SSP2_BUSY 0x20000000
-#define BP_CLKCTRL_SSP2_RSRVD1 10
-#define BM_CLKCTRL_SSP2_RSRVD1 0x1FFFFC00
-#define BF_CLKCTRL_SSP2_RSRVD1(v) \
- (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1)
-#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200
-#define BP_CLKCTRL_SSP2_DIV 0
-#define BM_CLKCTRL_SSP2_DIV 0x000001FF
-#define BF_CLKCTRL_SSP2_DIV(v) \
- (((v) << 0) & BM_CLKCTRL_SSP2_DIV)
-
-#define HW_CLKCTRL_SSP3 (0x000000c0)
-
-#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP3_RSRVD2 0x40000000
-#define BM_CLKCTRL_SSP3_BUSY 0x20000000
-#define BP_CLKCTRL_SSP3_RSRVD1 10
-#define BM_CLKCTRL_SSP3_RSRVD1 0x1FFFFC00
-#define BF_CLKCTRL_SSP3_RSRVD1(v) \
- (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1)
-#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200
-#define BP_CLKCTRL_SSP3_DIV 0
-#define BM_CLKCTRL_SSP3_DIV 0x000001FF
-#define BF_CLKCTRL_SSP3_DIV(v) \
- (((v) << 0) & BM_CLKCTRL_SSP3_DIV)
-
-#define HW_CLKCTRL_GPMI (0x000000d0)
-
-#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
-#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000
-#define BM_CLKCTRL_GPMI_BUSY 0x20000000
-#define BP_CLKCTRL_GPMI_RSRVD1 11
-#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800
-#define BF_CLKCTRL_GPMI_RSRVD1(v) \
- (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
-#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
-#define BP_CLKCTRL_GPMI_DIV 0
-#define BM_CLKCTRL_GPMI_DIV 0x000003FF
-#define BF_CLKCTRL_GPMI_DIV(v) \
- (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
-
-#define HW_CLKCTRL_SPDIF (0x000000e0)
-
-#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
-#define BP_CLKCTRL_SPDIF_RSRVD 0
-#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF
-#define BF_CLKCTRL_SPDIF_RSRVD(v) \
- (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
-
-#define HW_CLKCTRL_EMI (0x000000f0)
-
-#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
-#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000
-#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
-#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
-#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
-#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
-#define BP_CLKCTRL_EMI_RSRVD3 18
-#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000
-#define BF_CLKCTRL_EMI_RSRVD3(v) \
- (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
-#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
-#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
-#define BP_CLKCTRL_EMI_RSRVD2 12
-#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000
-#define BF_CLKCTRL_EMI_RSRVD2(v) \
- (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
-#define BP_CLKCTRL_EMI_DIV_XTAL 8
-#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
-#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
- (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
-#define BP_CLKCTRL_EMI_RSRVD1 6
-#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0
-#define BF_CLKCTRL_EMI_RSRVD1(v) \
- (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
-#define BP_CLKCTRL_EMI_DIV_EMI 0
-#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
-#define BF_CLKCTRL_EMI_DIV_EMI(v) \
- (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
-
-#define HW_CLKCTRL_SAIF0 (0x00000100)
-
-#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000
-#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000
-#define BM_CLKCTRL_SAIF0_BUSY 0x20000000
-#define BP_CLKCTRL_SAIF0_RSRVD1 17
-#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000
-#define BF_CLKCTRL_SAIF0_RSRVD1(v) \
- (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1)
-#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000
-#define BP_CLKCTRL_SAIF0_DIV 0
-#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF
-#define BF_CLKCTRL_SAIF0_DIV(v) \
- (((v) << 0) & BM_CLKCTRL_SAIF0_DIV)
-
-#define HW_CLKCTRL_SAIF1 (0x00000110)
-
-#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000
-#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000
-#define BM_CLKCTRL_SAIF1_BUSY 0x20000000
-#define BP_CLKCTRL_SAIF1_RSRVD1 17
-#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000
-#define BF_CLKCTRL_SAIF1_RSRVD1(v) \
- (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1)
-#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000
-#define BP_CLKCTRL_SAIF1_DIV 0
-#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF
-#define BF_CLKCTRL_SAIF1_DIV(v) \
- (((v) << 0) & BM_CLKCTRL_SAIF1_DIV)
-
-#define HW_CLKCTRL_DIS_LCDIF (0x00000120)
-
-#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000
-#define BM_CLKCTRL_DIS_LCDIF_RSRVD2 0x40000000
-#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000
-#define BP_CLKCTRL_DIS_LCDIF_RSRVD1 14
-#define BM_CLKCTRL_DIS_LCDIF_RSRVD1 0x1FFFC000
-#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v) \
- (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1)
-#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000
-#define BP_CLKCTRL_DIS_LCDIF_DIV 0
-#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF
-#define BF_CLKCTRL_DIS_LCDIF_DIV(v) \
- (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV)
-
-#define HW_CLKCTRL_ETM (0x00000130)
-
-#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
-#define BM_CLKCTRL_ETM_RSRVD2 0x40000000
-#define BM_CLKCTRL_ETM_BUSY 0x20000000
-#define BP_CLKCTRL_ETM_RSRVD1 8
-#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF00
-#define BF_CLKCTRL_ETM_RSRVD1(v) \
- (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1)
-#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080
-#define BP_CLKCTRL_ETM_DIV 0
-#define BM_CLKCTRL_ETM_DIV 0x0000007F
-#define BF_CLKCTRL_ETM_DIV(v) \
- (((v) << 0) & BM_CLKCTRL_ETM_DIV)
-
-#define HW_CLKCTRL_ENET (0x00000140)
-
-#define BM_CLKCTRL_ENET_SLEEP 0x80000000
-#define BM_CLKCTRL_ENET_DISABLE 0x40000000
-#define BM_CLKCTRL_ENET_STATUS 0x20000000
-#define BM_CLKCTRL_ENET_RSRVD1 0x10000000
-#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000
-#define BP_CLKCTRL_ENET_DIV_TIME 21
-#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000
-#define BF_CLKCTRL_ENET_DIV_TIME(v) \
- (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME)
-#define BP_CLKCTRL_ENET_TIME_SEL 19
-#define BM_CLKCTRL_ENET_TIME_SEL 0x00180000
-#define BF_CLKCTRL_ENET_TIME_SEL(v) \
- (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL)
-#define BV_CLKCTRL_ENET_TIME_SEL__XTAL 0x0
-#define BV_CLKCTRL_ENET_TIME_SEL__PLL 0x1
-#define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK 0x2
-#define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000
-#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000
-#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000
-#define BP_CLKCTRL_ENET_RSRVD0 0
-#define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF
-#define BF_CLKCTRL_ENET_RSRVD0(v) \
- (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0)
-
-#define HW_CLKCTRL_HSADC (0x00000150)
-
-#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000
-#define BM_CLKCTRL_HSADC_RESETB 0x40000000
-#define BP_CLKCTRL_HSADC_FREQDIV 28
-#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000
-#define BF_CLKCTRL_HSADC_FREQDIV(v) \
- (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV)
-#define BP_CLKCTRL_HSADC_RSRVD1 0
-#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF
-#define BF_CLKCTRL_HSADC_RSRVD1(v) \
- (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1)
-
-#define HW_CLKCTRL_FLEXCAN (0x00000160)
-
-#define BM_CLKCTRL_FLEXCAN_RSRVD2 0x80000000
-#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000
-#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000
-#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000
-#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000
-#define BP_CLKCTRL_FLEXCAN_RSRVD1 0
-#define BM_CLKCTRL_FLEXCAN_RSRVD1 0x07FFFFFF
-#define BF_CLKCTRL_FLEXCAN_RSRVD1(v) \
- (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1)
-
-#define HW_CLKCTRL_FRAC0 (0x000001b0)
-#define HW_CLKCTRL_FRAC0_SET (0x000001b4)
-#define HW_CLKCTRL_FRAC0_CLR (0x000001b8)
-#define HW_CLKCTRL_FRAC0_TOG (0x000001bc)
-
-#define BM_CLKCTRL_FRAC0_CLKGATEIO0 0x80000000
-#define BM_CLKCTRL_FRAC0_IO0_STABLE 0x40000000
-#define BP_CLKCTRL_FRAC0_IO0FRAC 24
-#define BM_CLKCTRL_FRAC0_IO0FRAC 0x3F000000
-#define BF_CLKCTRL_FRAC0_IO0FRAC(v) \
- (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC)
-#define BM_CLKCTRL_FRAC0_CLKGATEIO1 0x00800000
-#define BM_CLKCTRL_FRAC0_IO1_STABLE 0x00400000
-#define BP_CLKCTRL_FRAC0_IO1FRAC 16
-#define BM_CLKCTRL_FRAC0_IO1FRAC 0x003F0000
-#define BF_CLKCTRL_FRAC0_IO1FRAC(v) \
- (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC)
-#define BM_CLKCTRL_FRAC0_CLKGATEEMI 0x00008000
-#define BM_CLKCTRL_FRAC0_EMI_STABLE 0x00004000
-#define BP_CLKCTRL_FRAC0_EMIFRAC 8
-#define BM_CLKCTRL_FRAC0_EMIFRAC 0x00003F00
-#define BF_CLKCTRL_FRAC0_EMIFRAC(v) \
- (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC)
-#define BM_CLKCTRL_FRAC0_CLKGATECPU 0x00000080
-#define BM_CLKCTRL_FRAC0_CPU_STABLE 0x00000040
-#define BP_CLKCTRL_FRAC0_CPUFRAC 0
-#define BM_CLKCTRL_FRAC0_CPUFRAC 0x0000003F
-#define BF_CLKCTRL_FRAC0_CPUFRAC(v) \
- (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC)
-
-#define HW_CLKCTRL_FRAC1 (0x000001c0)
-#define HW_CLKCTRL_FRAC1_SET (0x000001c4)
-#define HW_CLKCTRL_FRAC1_CLR (0x000001c8)
-#define HW_CLKCTRL_FRAC1_TOG (0x000001cc)
-
-#define BP_CLKCTRL_FRAC1_RSRVD2 24
-#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000
-#define BF_CLKCTRL_FRAC1_RSRVD2(v) \
- (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2)
-#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000
-#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000
-#define BP_CLKCTRL_FRAC1_GPMIFRAC 16
-#define BM_CLKCTRL_FRAC1_GPMIFRAC 0x003F0000
-#define BF_CLKCTRL_FRAC1_GPMIFRAC(v) \
- (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC)
-#define BM_CLKCTRL_FRAC1_CLKGATEHSADC 0x00008000
-#define BM_CLKCTRL_FRAC1_HSADC_STABLE 0x00004000
-#define BP_CLKCTRL_FRAC1_HSADCFRAC 8
-#define BM_CLKCTRL_FRAC1_HSADCFRAC 0x00003F00
-#define BF_CLKCTRL_FRAC1_HSADCFRAC(v) \
- (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC)
-#define BM_CLKCTRL_FRAC1_CLKGATEPIX 0x00000080
-#define BM_CLKCTRL_FRAC1_PIX_STABLE 0x00000040
-#define BP_CLKCTRL_FRAC1_PIXFRAC 0
-#define BM_CLKCTRL_FRAC1_PIXFRAC 0x0000003F
-#define BF_CLKCTRL_FRAC1_PIXFRAC(v) \
- (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC)
-
-#define HW_CLKCTRL_CLKSEQ (0x000001d0)
-#define HW_CLKCTRL_CLKSEQ_SET (0x000001d4)
-#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8)
-#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc)
-
-#define BP_CLKCTRL_CLKSEQ_RSRVD0 19
-#define BM_CLKCTRL_CLKSEQ_RSRVD0 0xFFF80000
-#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \
- (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0)
-#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000
-#define BP_CLKCTRL_CLKSEQ_RSRVD1 15
-#define BM_CLKCTRL_CLKSEQ_RSRVD1 0x00038000
-#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
- (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1)
-#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000
-#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1
-#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0
-#define BP_CLKCTRL_CLKSEQ_RSRVD2 9
-#define BM_CLKCTRL_CLKSEQ_RSRVD2 0x00003E00
-#define BF_CLKCTRL_CLKSEQ_RSRVD2(v) \
- (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2)
-#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
-#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2 0x00000020
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1 0x00000010
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0 0x00000008
-#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000004
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1 0x00000002
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0 0x00000001
-
-#define HW_CLKCTRL_RESET (0x000001e0)
-
-#define BP_CLKCTRL_RESET_RSRVD 6
-#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFC0
-#define BF_CLKCTRL_RESET_RSRVD(v) \
- (((v) << 6) & BM_CLKCTRL_RESET_RSRVD)
-#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020
-#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010
-#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008
-#define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT 0x00000004
-#define BM_CLKCTRL_RESET_CHIP 0x00000002
-#define BM_CLKCTRL_RESET_DIG 0x00000001
-
-#define HW_CLKCTRL_STATUS (0x000001f0)
-
-#define BP_CLKCTRL_STATUS_CPU_LIMIT 30
-#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
-#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
- (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
-#define BP_CLKCTRL_STATUS_RSRVD 0
-#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
-#define BF_CLKCTRL_STATUS_RSRVD(v) \
- (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
-
-#define HW_CLKCTRL_VERSION (0x00000200)
-
-#define BP_CLKCTRL_VERSION_MAJOR 24
-#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000
-#define BF_CLKCTRL_VERSION_MAJOR(v) \
- (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
-#define BP_CLKCTRL_VERSION_MINOR 16
-#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000
-#define BF_CLKCTRL_VERSION_MINOR(v) \
- (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
-#define BP_CLKCTRL_VERSION_STEP 0
-#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
-#define BF_CLKCTRL_VERSION_STEP(v) \
- (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
-#endif /* __ARCH_ARM___CLKCTRL_H */
+++ /dev/null
-/*
- * Freescale ENET Register Definitions
- *
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * This file is created by xml file. Don't Edit it.
- *
- * Xml Revision: 1.32
- * Template revision: 26195
- */
-
-#ifndef __ARCH_ARM___ENET_H
-#define __ARCH_ARM___ENET_H
-
-
-#define HW_ENET_MAC0_EIR (0x00000000)
-
-#define BM_ENET_MAC0_EIR_RSRVD0 0x80000000
-#define BM_ENET_MAC0_EIR_BABR 0x40000000
-#define BM_ENET_MAC0_EIR_BABT 0x20000000
-#define BM_ENET_MAC0_EIR_GRA 0x10000000
-#define BM_ENET_MAC0_EIR_TXF 0x08000000
-#define BM_ENET_MAC0_EIR_TXB 0x04000000
-#define BM_ENET_MAC0_EIR_RXF 0x02000000
-#define BM_ENET_MAC0_EIR_RXB 0x01000000
-#define BM_ENET_MAC0_EIR_MII 0x00800000
-#define BM_ENET_MAC0_EIR_EBERR 0x00400000
-#define BM_ENET_MAC0_EIR_LC 0x00200000
-#define BM_ENET_MAC0_EIR_RL 0x00100000
-#define BM_ENET_MAC0_EIR_UN 0x00080000
-#define BM_ENET_MAC0_EIR_PLR 0x00040000
-#define BM_ENET_MAC0_EIR_WAKEUP 0x00020000
-#define BM_ENET_MAC0_EIR_TS_AVAIL 0x00010000
-#define BM_ENET_MAC0_EIR_TS_TIMER 0x00008000
-#define BP_ENET_MAC0_EIR_RSRVD1 0
-#define BM_ENET_MAC0_EIR_RSRVD1 0x00007FFF
-#define BF_ENET_MAC0_EIR_RSRVD1(v) \
- (((v) << 0) & BM_ENET_MAC0_EIR_RSRVD1)
-
-#define HW_ENET_MAC0_EIMR (0x00000004)
-
-#define BP_ENET_MAC0_EIMR_EIMR 0
-#define BM_ENET_MAC0_EIMR_EIMR 0xFFFFFFFF
-#define BF_ENET_MAC0_EIMR_EIMR(v) (v)
-
-#define HW_ENET_MAC0_RDAR (0x0000000c)
-
-#define BP_ENET_MAC0_RDAR_RSRVD0 25
-#define BM_ENET_MAC0_RDAR_RSRVD0 0xFE000000
-#define BF_ENET_MAC0_RDAR_RSRVD0(v) \
- (((v) << 25) & BM_ENET_MAC0_RDAR_RSRVD0)
-#define BM_ENET_MAC0_RDAR_RDAR 0x01000000
-#define BP_ENET_MAC0_RDAR_RSRVD1 0
-#define BM_ENET_MAC0_RDAR_RSRVD1 0x00FFFFFF
-#define BF_ENET_MAC0_RDAR_RSRVD1(v) \
- (((v) << 0) & BM_ENET_MAC0_RDAR_RSRVD1)
-
-#define HW_ENET_MAC0_TDAR (0x00000010)
-
-#define BP_ENET_MAC0_TDAR_RSRVD0 25
-#define BM_ENET_MAC0_TDAR_RSRVD0 0xFE000000
-#define BF_ENET_MAC0_TDAR_RSRVD0(v) \
- (((v) << 25) & BM_ENET_MAC0_TDAR_RSRVD0)
-#define BM_ENET_MAC0_TDAR_TDAR 0x01000000
-#define BP_ENET_MAC0_TDAR_RSRVD1 0
-#define BM_ENET_MAC0_TDAR_RSRVD1 0x00FFFFFF
-#define BF_ENET_MAC0_TDAR_RSRVD1(v) \
- (((v) << 0) & BM_ENET_MAC0_TDAR_RSRVD1)
-
-#define HW_ENET_MAC0_ECR (0x00000020)
-
-#define BP_ENET_MAC0_ECR_RSRVD0 7
-#define BM_ENET_MAC0_ECR_RSRVD0 0xFFFFFF80
-#define BF_ENET_MAC0_ECR_RSRVD0(v) \
- (((v) << 7) & BM_ENET_MAC0_ECR_RSRVD0)
-#define BM_ENET_MAC0_ECR_DBG_EN 0x00000040
-#define BM_ENET_MAC0_ECR_ETH_SPEED 0x00000020
-#define BM_ENET_MAC0_ECR_ENA_1588 0x00000010
-#define BM_ENET_MAC0_ECR_SLEEP 0x00000008
-#define BM_ENET_MAC0_ECR_MAGIC_ENA 0x00000004
-#define BM_ENET_MAC0_ECR_ETHER_EN 0x00000002
-#define BM_ENET_MAC0_ECR_RESET 0x00000001
-
-#define HW_ENET_MAC0_MMFR (0x0000003c)
-
-#define BP_ENET_MAC0_MMFR_ST 30
-#define BM_ENET_MAC0_MMFR_ST 0xC0000000
-#define BF_ENET_MAC0_MMFR_ST(v) \
- (((v) << 30) & BM_ENET_MAC0_MMFR_ST)
-#define BP_ENET_MAC0_MMFR_OP 28
-#define BM_ENET_MAC0_MMFR_OP 0x30000000
-#define BF_ENET_MAC0_MMFR_OP(v) \
- (((v) << 28) & BM_ENET_MAC0_MMFR_OP)
-#define BP_ENET_MAC0_MMFR_PA 23
-#define BM_ENET_MAC0_MMFR_PA 0x0F800000
-#define BF_ENET_MAC0_MMFR_PA(v) \
- (((v) << 23) & BM_ENET_MAC0_MMFR_PA)
-#define BP_ENET_MAC0_MMFR_RA 18
-#define BM_ENET_MAC0_MMFR_RA 0x007C0000
-#define BF_ENET_MAC0_MMFR_RA(v) \
- (((v) << 18) & BM_ENET_MAC0_MMFR_RA)
-#define BP_ENET_MAC0_MMFR_TA 16
-#define BM_ENET_MAC0_MMFR_TA 0x00030000
-#define BF_ENET_MAC0_MMFR_TA(v) \
- (((v) << 16) & BM_ENET_MAC0_MMFR_TA)
-#define BP_ENET_MAC0_MMFR_DATA 0
-#define BM_ENET_MAC0_MMFR_DATA 0x0000FFFF
-#define BF_ENET_MAC0_MMFR_DATA(v) \
- (((v) << 0) & BM_ENET_MAC0_MMFR_DATA)
-
-#define HW_ENET_MAC0_MSCR (0x00000040)
-
-#define BP_ENET_MAC0_MSCR_RSRVD0 11
-#define BM_ENET_MAC0_MSCR_RSRVD0 0xFFFFF800
-#define BF_ENET_MAC0_MSCR_RSRVD0(v) \
- (((v) << 11) & BM_ENET_MAC0_MSCR_RSRVD0)
-#define BP_ENET_MAC0_MSCR_HOLDTIME 8
-#define BM_ENET_MAC0_MSCR_HOLDTIME 0x00000700
-#define BF_ENET_MAC0_MSCR_HOLDTIME(v) \
- (((v) << 8) & BM_ENET_MAC0_MSCR_HOLDTIME)
-#define BM_ENET_MAC0_MSCR_DIS_PRE 0x00000080
-#define BP_ENET_MAC0_MSCR_MII_SPEED 1
-#define BM_ENET_MAC0_MSCR_MII_SPEED 0x0000007E
-#define BF_ENET_MAC0_MSCR_MII_SPEED(v) \
- (((v) << 1) & BM_ENET_MAC0_MSCR_MII_SPEED)
-#define BM_ENET_MAC0_MSCR_RSRVD1 0x00000001
-
-#define HW_ENET_MAC0_MIBC (0x00000060)
-
-#define BM_ENET_MAC0_MIBC_MIB_DIS 0x80000000
-#define BM_ENET_MAC0_MIBC_MIB_IDLE 0x40000000
-#define BM_ENET_MAC0_MIBC_MIB_CLEAR 0x20000000
-#define BP_ENET_MAC0_MIBC_RSRVD0 0
-#define BM_ENET_MAC0_MIBC_RSRVD0 0x1FFFFFFF
-#define BF_ENET_MAC0_MIBC_RSRVD0(v) \
- (((v) << 0) & BM_ENET_MAC0_MIBC_RSRVD0)
-
-#define HW_ENET_MAC0_RCR (0x00000080)
-
-#define BM_ENET_MAC0_RCR_GRS 0x80000000
-#define BM_ENET_MAC0_RCR_NO_LGTH_CHECK 0x40000000
-#define BP_ENET_MAC0_RCR_MAX_FL 16
-#define BM_ENET_MAC0_RCR_MAX_FL 0x3FFF0000
-#define BF_ENET_MAC0_RCR_MAX_FL(v) \
- (((v) << 16) & BM_ENET_MAC0_RCR_MAX_FL)
-#define BM_ENET_MAC0_RCR_CNTL_FRM_ENA 0x00008000
-#define BM_ENET_MAC0_RCR_CRC_FWD 0x00004000
-#define BM_ENET_MAC0_RCR_PAUSE_FWD 0x00002000
-#define BM_ENET_MAC0_RCR_PAD_EN 0x00001000
-#define BM_ENET_MAC0_RCR_RMII_ECHO 0x00000800
-#define BM_ENET_MAC0_RCR_RMII_LOOP 0x00000400
-#define BM_ENET_MAC0_RCR_RMII_10T 0x00000200
-#define BM_ENET_MAC0_RCR_RMII_MODE 0x00000100
-#define BM_ENET_MAC0_RCR_SGMII_ENA 0x00000080
-#define BM_ENET_MAC0_RCR_RGMII_ENA 0x00000040
-#define BM_ENET_MAC0_RCR_FCE 0x00000020
-#define BM_ENET_MAC0_RCR_BC_REJ 0x00000010
-#define BM_ENET_MAC0_RCR_PROM 0x00000008
-#define BM_ENET_MAC0_RCR_MII_MODE 0x00000004
-#define BM_ENET_MAC0_RCR_DRT 0x00000002
-#define BM_ENET_MAC0_RCR_LOOP 0x00000001
-
-#define HW_ENET_MAC0_TCR (0x000000c0)
-
-#define BP_ENET_MAC0_TCR_RSRVD0 10
-#define BM_ENET_MAC0_TCR_RSRVD0 0xFFFFFC00
-#define BF_ENET_MAC0_TCR_RSRVD0(v) \
- (((v) << 10) & BM_ENET_MAC0_TCR_RSRVD0)
-#define BM_ENET_MAC0_TCR_TX_CRC_FWD 0x00000200
-#define BM_ENET_MAC0_TCR_TX_ADDR_INS 0x00000100
-#define BP_ENET_MAC0_TCR_TX_ADDR_SEL 5
-#define BM_ENET_MAC0_TCR_TX_ADDR_SEL 0x000000E0
-#define BF_ENET_MAC0_TCR_TX_ADDR_SEL(v) \
- (((v) << 5) & BM_ENET_MAC0_TCR_TX_ADDR_SEL)
-#define BM_ENET_MAC0_TCR_RFC_PAUSE 0x00000010
-#define BM_ENET_MAC0_TCR_TFC_PAUSE 0x00000008
-#define BM_ENET_MAC0_TCR_FEDN 0x00000004
-#define BM_ENET_MAC0_TCR_HBC 0x00000002
-#define BM_ENET_MAC0_TCR_GTS 0x00000001
-
-#define HW_ENET_MAC0_PALR (0x000000e0)
-
-#define BP_ENET_MAC0_PALR_PADDR1 0
-#define BM_ENET_MAC0_PALR_PADDR1 0xFFFFFFFF
-#define BF_ENET_MAC0_PALR_PADDR1(v) (v)
-
-#define HW_ENET_MAC0_PAUR (0x000000e4)
-
-#define BP_ENET_MAC0_PAUR_PADDR2 16
-#define BM_ENET_MAC0_PAUR_PADDR2 0xFFFF0000
-#define BF_ENET_MAC0_PAUR_PADDR2(v) \
- (((v) << 16) & BM_ENET_MAC0_PAUR_PADDR2)
-#define BP_ENET_MAC0_PAUR_TYPE 0
-#define BM_ENET_MAC0_PAUR_TYPE 0x0000FFFF
-#define BF_ENET_MAC0_PAUR_TYPE(v) \
- (((v) << 0) & BM_ENET_MAC0_PAUR_TYPE)
-
-#define HW_ENET_MAC0_OPD (0x000000e8)
-
-#define BP_ENET_MAC0_OPD_OPCODE 16
-#define BM_ENET_MAC0_OPD_OPCODE 0xFFFF0000
-#define BF_ENET_MAC0_OPD_OPCODE(v) \
- (((v) << 16) & BM_ENET_MAC0_OPD_OPCODE)
-#define BP_ENET_MAC0_OPD_PAUSE_DUR 0
-#define BM_ENET_MAC0_OPD_PAUSE_DUR 0x0000FFFF
-#define BF_ENET_MAC0_OPD_PAUSE_DUR(v) \
- (((v) << 0) & BM_ENET_MAC0_OPD_PAUSE_DUR)
-
-#define HW_ENET_MAC0_IAUR (0x00000114)
-
-#define BP_ENET_MAC0_IAUR_IADDR1 0
-#define BM_ENET_MAC0_IAUR_IADDR1 0xFFFFFFFF
-#define BF_ENET_MAC0_IAUR_IADDR1(v) (v)
-
-#define HW_ENET_MAC0_IALR (0x00000118)
-
-#define BP_ENET_MAC0_IALR_IADDR2 0
-#define BM_ENET_MAC0_IALR_IADDR2 0xFFFFFFFF
-#define BF_ENET_MAC0_IALR_IADDR2(v) (v)
-
-#define HW_ENET_MAC0_GAUR (0x0000011c)
-
-#define BP_ENET_MAC0_GAUR_GADDR1 0
-#define BM_ENET_MAC0_GAUR_GADDR1 0xFFFFFFFF
-#define BF_ENET_MAC0_GAUR_GADDR1(v) (v)
-
-#define HW_ENET_MAC0_GALR (0x00000120)
-
-#define BP_ENET_MAC0_GALR_GADDR2 0
-#define BM_ENET_MAC0_GALR_GADDR2 0xFFFFFFFF
-#define BF_ENET_MAC0_GALR_GADDR2(v) (v)
-
-#define HW_ENET_MAC0_TFW_SFCR (0x00000140)
-
-#define BP_ENET_MAC0_TFW_SFCR_RSRVD0 9
-#define BM_ENET_MAC0_TFW_SFCR_RSRVD0 0xFFFFFE00
-#define BF_ENET_MAC0_TFW_SFCR_RSRVD0(v) \
- (((v) << 9) & BM_ENET_MAC0_TFW_SFCR_RSRVD0)
-#define BM_ENET_MAC0_TFW_SFCR_STR_FWD 0x00000100
-#define BP_ENET_MAC0_TFW_SFCR_RSRVD1 6
-#define BM_ENET_MAC0_TFW_SFCR_RSRVD1 0x000000C0
-#define BF_ENET_MAC0_TFW_SFCR_RSRVD1(v) \
- (((v) << 6) & BM_ENET_MAC0_TFW_SFCR_RSRVD1)
-#define BP_ENET_MAC0_TFW_SFCR_TFWR 0
-#define BM_ENET_MAC0_TFW_SFCR_TFWR 0x0000003F
-#define BF_ENET_MAC0_TFW_SFCR_TFWR(v) \
- (((v) << 0) & BM_ENET_MAC0_TFW_SFCR_TFWR)
-
-#define HW_ENET_MAC0_FRBR (0x00000148)
-
-#define BP_ENET_MAC0_FRBR_RSRVD0 10
-#define BM_ENET_MAC0_FRBR_RSRVD0 0xFFFFFC00
-#define BF_ENET_MAC0_FRBR_RSRVD0(v) \
- (((v) << 10) & BM_ENET_MAC0_FRBR_RSRVD0)
-#define BP_ENET_MAC0_FRBR_R_BOUND 2
-#define BM_ENET_MAC0_FRBR_R_BOUND 0x000003FC
-#define BF_ENET_MAC0_FRBR_R_BOUND(v) \
- (((v) << 2) & BM_ENET_MAC0_FRBR_R_BOUND)
-#define BP_ENET_MAC0_FRBR_RSRVD1 0
-#define BM_ENET_MAC0_FRBR_RSRVD1 0x00000003
-#define BF_ENET_MAC0_FRBR_RSRVD1(v) \
- (((v) << 0) & BM_ENET_MAC0_FRBR_RSRVD1)
-
-#define HW_ENET_MAC0_FRSR (0x0000014c)
-
-#define BP_ENET_MAC0_FRSR_RSRVD0 11
-#define BM_ENET_MAC0_FRSR_RSRVD0 0xFFFFF800
-#define BF_ENET_MAC0_FRSR_RSRVD0(v) \
- (((v) << 11) & BM_ENET_MAC0_FRSR_RSRVD0)
-#define BM_ENET_MAC0_FRSR_RSRVD1 0x00000400
-#define BP_ENET_MAC0_FRSR_R_FSTART 2
-#define BM_ENET_MAC0_FRSR_R_FSTART 0x000003FC
-#define BF_ENET_MAC0_FRSR_R_FSTART(v) \
- (((v) << 2) & BM_ENET_MAC0_FRSR_R_FSTART)
-#define BP_ENET_MAC0_FRSR_RSRVD2 0
-#define BM_ENET_MAC0_FRSR_RSRVD2 0x00000003
-#define BF_ENET_MAC0_FRSR_RSRVD2(v) \
- (((v) << 0) & BM_ENET_MAC0_FRSR_RSRVD2)
-
-#define HW_ENET_MAC0_ERDSR (0x0000017c)
-
-#define BP_ENET_MAC0_ERDSR_R_DES_START 2
-#define BM_ENET_MAC0_ERDSR_R_DES_START 0xFFFFFFFC
-#define BF_ENET_MAC0_ERDSR_R_DES_START(v) \
- (((v) << 2) & BM_ENET_MAC0_ERDSR_R_DES_START)
-#define BP_ENET_MAC0_ERDSR_RSRVD0 0
-#define BM_ENET_MAC0_ERDSR_RSRVD0 0x00000003
-#define BF_ENET_MAC0_ERDSR_RSRVD0(v) \
- (((v) << 0) & BM_ENET_MAC0_ERDSR_RSRVD0)
-
-#define HW_ENET_MAC0_ETDSR (0x00000180)
-
-#define BP_ENET_MAC0_ETDSR_X_DES_START 2
-#define BM_ENET_MAC0_ETDSR_X_DES_START 0xFFFFFFFC
-#define BF_ENET_MAC0_ETDSR_X_DES_START(v) \
- (((v) << 2) & BM_ENET_MAC0_ETDSR_X_DES_START)
-#define BP_ENET_MAC0_ETDSR_RSRVD0 0
-#define BM_ENET_MAC0_ETDSR_RSRVD0 0x00000003
-#define BF_ENET_MAC0_ETDSR_RSRVD0(v) \
- (((v) << 0) & BM_ENET_MAC0_ETDSR_RSRVD0)
-
-#define HW_ENET_MAC0_EMRBR (0x00000184)
-
-#define BP_ENET_MAC0_EMRBR_RSRVD0 11
-#define BM_ENET_MAC0_EMRBR_RSRVD0 0xFFFFF800
-#define BF_ENET_MAC0_EMRBR_RSRVD0(v) \
- (((v) << 11) & BM_ENET_MAC0_EMRBR_RSRVD0)
-#define BP_ENET_MAC0_EMRBR_R_BUF_SIZE 4
-#define BM_ENET_MAC0_EMRBR_R_BUF_SIZE 0x000007F0
-#define BF_ENET_MAC0_EMRBR_R_BUF_SIZE(v) \
- (((v) << 4) & BM_ENET_MAC0_EMRBR_R_BUF_SIZE)
-#define BP_ENET_MAC0_EMRBR_RSRVD1 0
-#define BM_ENET_MAC0_EMRBR_RSRVD1 0x0000000F
-#define BF_ENET_MAC0_EMRBR_RSRVD1(v) \
- (((v) << 0) & BM_ENET_MAC0_EMRBR_RSRVD1)
-
-#define HW_ENET_MAC0_RX_SECTION_FULL (0x0000018c)
-
-#define BP_ENET_MAC0_RX_SECTION_FULL_RSRVD0 8
-#define BM_ENET_MAC0_RX_SECTION_FULL_RSRVD0 0xFFFFFF00
-#define BF_ENET_MAC0_RX_SECTION_FULL_RSRVD0(v) \
- (((v) << 8) & BM_ENET_MAC0_RX_SECTION_FULL_RSRVD0)
-#define BP_ENET_MAC0_RX_SECTION_FULL_RX_SECTION_FULL 0
-#define BM_ENET_MAC0_RX_SECTION_FULL_RX_SECTION_FULL 0x000000FF
-#define BF_ENET_MAC0_RX_SECTION_FULL_RX_SECTION_FULL(v) \
- (((v) << 0) & BM_ENET_MAC0_RX_SECTION_FULL_RX_SECTION_FULL)
-
-#define HW_ENET_MAC0_RX_SECTION_EMPTY (0x00000190)
-
-#define BP_ENET_MAC0_RX_SECTION_EMPTY_RSRVD0 8
-#define BM_ENET_MAC0_RX_SECTION_EMPTY_RSRVD0 0xFFFFFF00
-#define BF_ENET_MAC0_RX_SECTION_EMPTY_RSRVD0(v) \
- (((v) << 8) & BM_ENET_MAC0_RX_SECTION_EMPTY_RSRVD0)
-#define BP_ENET_MAC0_RX_SECTION_EMPTY_RX_SECTION_EMPTY 0
-#define BM_ENET_MAC0_RX_SECTION_EMPTY_RX_SECTION_EMPTY 0x000000FF
-#define BF_ENET_MAC0_RX_SECTION_EMPTY_RX_SECTION_EMPTY(v) \
- (((v) << 0) & BM_ENET_MAC0_RX_SECTION_EMPTY_RX_SECTION_EMPTY)
-
-#define HW_ENET_MAC0_RX_ALMOST_EMPTY (0x00000194)
-
-#define BP_ENET_MAC0_RX_ALMOST_EMPTY_RSRVD0 8
-#define BM_ENET_MAC0_RX_ALMOST_EMPTY_RSRVD0 0xFFFFFF00
-#define BF_ENET_MAC0_RX_ALMOST_EMPTY_RSRVD0(v) \
- (((v) << 8) & BM_ENET_MAC0_RX_ALMOST_EMPTY_RSRVD0)
-#define BP_ENET_MAC0_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY 0
-#define BM_ENET_MAC0_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY 0x000000FF
-#define BF_ENET_MAC0_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY(v) \
- (((v) << 0) & BM_ENET_MAC0_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY)
-
-#define HW_ENET_MAC0_RX_ALMOST_FULL (0x00000198)
-
-#define BP_ENET_MAC0_RX_ALMOST_FULL_RSRVD0 8
-#define BM_ENET_MAC0_RX_ALMOST_FULL_RSRVD0 0xFFFFFF00
-#define BF_ENET_MAC0_RX_ALMOST_FULL_RSRVD0(v) \
- (((v) << 8) & BM_ENET_MAC0_RX_ALMOST_FULL_RSRVD0)
-#define BP_ENET_MAC0_RX_ALMOST_FULL_RX_ALMOST_FULL 0
-#define BM_ENET_MAC0_RX_ALMOST_FULL_RX_ALMOST_FULL 0x000000FF
-#define BF_ENET_MAC0_RX_ALMOST_FULL_RX_ALMOST_FULL(v) \
- (((v) << 0) & BM_ENET_MAC0_RX_ALMOST_FULL_RX_ALMOST_FULL)
-
-#define HW_ENET_MAC0_TX_SECTION_EMPTY (0x0000019c)
-
-#define BP_ENET_MAC0_TX_SECTION_EMPTY_RSRVD0 8
-#define BM_ENET_MAC0_TX_SECTION_EMPTY_RSRVD0 0xFFFFFF00
-#define BF_ENET_MAC0_TX_SECTION_EMPTY_RSRVD0(v) \
- (((v) << 8) & BM_ENET_MAC0_TX_SECTION_EMPTY_RSRVD0)
-#define BP_ENET_MAC0_TX_SECTION_EMPTY_TX_SECTION_EMPTY 0
-#define BM_ENET_MAC0_TX_SECTION_EMPTY_TX_SECTION_EMPTY 0x000000FF
-#define BF_ENET_MAC0_TX_SECTION_EMPTY_TX_SECTION_EMPTY(v) \
- (((v) << 0) & BM_ENET_MAC0_TX_SECTION_EMPTY_TX_SECTION_EMPTY)
-
-#define HW_ENET_MAC0_TX_ALMOST_EMPTY (0x000001a0)
-
-#define BP_ENET_MAC0_TX_ALMOST_EMPTY_RSRVD0 8
-#define BM_ENET_MAC0_TX_ALMOST_EMPTY_RSRVD0 0xFFFFFF00
-#define BF_ENET_MAC0_TX_ALMOST_EMPTY_RSRVD0(v) \
- (((v) << 8) & BM_ENET_MAC0_TX_ALMOST_EMPTY_RSRVD0)
-#define BP_ENET_MAC0_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY 0
-#define BM_ENET_MAC0_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY 0x000000FF
-#define BF_ENET_MAC0_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY(v) \
- (((v) << 0) & BM_ENET_MAC0_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY)
-
-#define HW_ENET_MAC0_TX_ALMOST_FULL (0x000001a4)
-
-#define BP_ENET_MAC0_TX_ALMOST_FULL_RSRVD0 8
-#define BM_ENET_MAC0_TX_ALMOST_FULL_RSRVD0 0xFFFFFF00
-#define BF_ENET_MAC0_TX_ALMOST_FULL_RSRVD0(v) \
- (((v) << 8) & BM_ENET_MAC0_TX_ALMOST_FULL_RSRVD0)
-#define BP_ENET_MAC0_TX_ALMOST_FULL_TX_ALMOST_FULL 0
-#define BM_ENET_MAC0_TX_ALMOST_FULL_TX_ALMOST_FULL 0x000000FF
-#define BF_ENET_MAC0_TX_ALMOST_FULL_TX_ALMOST_FULL(v) \
- (((v) << 0) & BM_ENET_MAC0_TX_ALMOST_FULL_TX_ALMOST_FULL)
-
-#define HW_ENET_MAC0_TX_IPG_LENGTH (0x000001a8)
-
-#define BP_ENET_MAC0_TX_IPG_LENGTH_RSRVD0 5
-#define BM_ENET_MAC0_TX_IPG_LENGTH_RSRVD0 0xFFFFFFE0
-#define BF_ENET_MAC0_TX_IPG_LENGTH_RSRVD0(v) \
- (((v) << 5) & BM_ENET_MAC0_TX_IPG_LENGTH_RSRVD0)
-#define BP_ENET_MAC0_TX_IPG_LENGTH_TX_IPG_LENGTH 0
-#define BM_ENET_MAC0_TX_IPG_LENGTH_TX_IPG_LENGTH 0x0000001F
-#define BF_ENET_MAC0_TX_IPG_LENGTH_TX_IPG_LENGTH(v) \
- (((v) << 0) & BM_ENET_MAC0_TX_IPG_LENGTH_TX_IPG_LENGTH)
-
-#define HW_ENET_MAC0_TRUNC_FL (0x000001ac)
-
-#define BP_ENET_MAC0_TRUNC_FL_RSRVD0 14
-#define BM_ENET_MAC0_TRUNC_FL_RSRVD0 0xFFFFC000
-#define BF_ENET_MAC0_TRUNC_FL_RSRVD0(v) \
- (((v) << 14) & BM_ENET_MAC0_TRUNC_FL_RSRVD0)
-#define BP_ENET_MAC0_TRUNC_FL_TRUNC_FL 0
-#define BM_ENET_MAC0_TRUNC_FL_TRUNC_FL 0x00003FFF
-#define BF_ENET_MAC0_TRUNC_FL_TRUNC_FL(v) \
- (((v) << 0) & BM_ENET_MAC0_TRUNC_FL_TRUNC_FL)
-
-#define HW_ENET_MAC0_IPACCTXCONF (0x000001bc)
-
-#define BP_ENET_MAC0_IPACCTXCONF_RSRVD0 5
-#define BM_ENET_MAC0_IPACCTXCONF_RSRVD0 0xFFFFFFE0
-#define BF_ENET_MAC0_IPACCTXCONF_RSRVD0(v) \
- (((v) << 5) & BM_ENET_MAC0_IPACCTXCONF_RSRVD0)
-#define BM_ENET_MAC0_IPACCTXCONF_TX_PROTCHK_INS 0x00000010
-#define BM_ENET_MAC0_IPACCTXCONF_TX_IPCHK_INS 0x00000008
-#define BP_ENET_MAC0_IPACCTXCONF_RSRVD1 1
-#define BM_ENET_MAC0_IPACCTXCONF_RSRVD1 0x00000006
-#define BF_ENET_MAC0_IPACCTXCONF_RSRVD1(v) \
- (((v) << 1) & BM_ENET_MAC0_IPACCTXCONF_RSRVD1)
-#define BM_ENET_MAC0_IPACCTXCONF_SHIFT16 0x00000001
-
-#define HW_ENET_MAC0_IPACCRXCONF (0x000001c0)
-
-#define BP_ENET_MAC0_IPACCRXCONF_RSRVD0 8
-#define BM_ENET_MAC0_IPACCRXCONF_RSRVD0 0xFFFFFF00
-#define BF_ENET_MAC0_IPACCRXCONF_RSRVD0(v) \
- (((v) << 8) & BM_ENET_MAC0_IPACCRXCONF_RSRVD0)
-#define BM_ENET_MAC0_IPACCRXCONF_SHIFT16 0x00000080
-#define BM_ENET_MAC0_IPACCRXCONF_RX_LINEERR_DISC 0x00000040
-#define BP_ENET_MAC0_IPACCRXCONF_RSRVD1 3
-#define BM_ENET_MAC0_IPACCRXCONF_RSRVD1 0x00000038
-#define BF_ENET_MAC0_IPACCRXCONF_RSRVD1(v) \
- (((v) << 3) & BM_ENET_MAC0_IPACCRXCONF_RSRVD1)
-#define BM_ENET_MAC0_IPACCRXCONF_RX_PROTERR_DISCARD 0x00000004
-#define BM_ENET_MAC0_IPACCRXCONF_RX_IPERR_DISCARD 0x00000002
-#define BM_ENET_MAC0_IPACCRXCONF_RX_IP_PAD_REMOVE 0x00000001
-
-#define HW_ENET_MAC0_RMON_T_DROP (0x000001fc)
-
-#define BP_ENET_MAC0_RMON_T_DROP_RMON_T_DROP 0
-#define BM_ENET_MAC0_RMON_T_DROP_RMON_T_DROP 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_DROP_RMON_T_DROP(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_PACKETS (0x00000200)
-
-#define BP_ENET_MAC0_RMON_T_PACKETS_RMON_T_PACKETS 0
-#define BM_ENET_MAC0_RMON_T_PACKETS_RMON_T_PACKETS 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_PACKETS_RMON_T_PACKETS(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_BC_PKT (0x00000204)
-
-#define BP_ENET_MAC0_RMON_T_BC_PKT_RMON_T_BC_PKT 0
-#define BM_ENET_MAC0_RMON_T_BC_PKT_RMON_T_BC_PKT 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_BC_PKT_RMON_T_BC_PKT(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_MC_PKT (0x00000208)
-
-#define BP_ENET_MAC0_RMON_T_MC_PKT_RMON_T_MC_PKT 0
-#define BM_ENET_MAC0_RMON_T_MC_PKT_RMON_T_MC_PKT 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_MC_PKT_RMON_T_MC_PKT(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_CRC_ALIGN (0x0000020c)
-
-#define BP_ENET_MAC0_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN 0
-#define BM_ENET_MAC0_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_UNDERSIZE (0x00000210)
-
-#define BP_ENET_MAC0_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE 0
-#define BM_ENET_MAC0_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_OVERSIZE (0x00000214)
-
-#define BP_ENET_MAC0_RMON_T_OVERSIZE_RMON_T_OVERSIZE 0
-#define BM_ENET_MAC0_RMON_T_OVERSIZE_RMON_T_OVERSIZE 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_OVERSIZE_RMON_T_OVERSIZE(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_FRAG (0x00000218)
-
-#define BP_ENET_MAC0_RMON_T_FRAG_RMON_T_FRAG 0
-#define BM_ENET_MAC0_RMON_T_FRAG_RMON_T_FRAG 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_FRAG_RMON_T_FRAG(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_JAB (0x0000021c)
-
-#define BP_ENET_MAC0_RMON_T_JAB_RMON_T_JAB 0
-#define BM_ENET_MAC0_RMON_T_JAB_RMON_T_JAB 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_JAB_RMON_T_JAB(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_COL (0x00000220)
-
-#define BP_ENET_MAC0_RMON_T_COL_RMON_T_COL 0
-#define BM_ENET_MAC0_RMON_T_COL_RMON_T_COL 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_COL_RMON_T_COL(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_P64 (0x00000224)
-
-#define BP_ENET_MAC0_RMON_T_P64_RMON_T_P64 0
-#define BM_ENET_MAC0_RMON_T_P64_RMON_T_P64 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_P64_RMON_T_P64(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_P65TO127N (0x00000228)
-
-#define BP_ENET_MAC0_RMON_T_P65TO127N_RMON_T_P65TO127N 0
-#define BM_ENET_MAC0_RMON_T_P65TO127N_RMON_T_P65TO127N 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_P65TO127N_RMON_T_P65TO127N(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_P128TO255N (0x0000022c)
-
-#define BP_ENET_MAC0_RMON_T_P128TO255N_RMON_T_P128TO255N 0
-#define BM_ENET_MAC0_RMON_T_P128TO255N_RMON_T_P128TO255N 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_P128TO255N_RMON_T_P128TO255N(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_P256TO511 (0x00000230)
-
-#define BP_ENET_MAC0_RMON_T_P256TO511_RMON_T_P256TO511 0
-#define BM_ENET_MAC0_RMON_T_P256TO511_RMON_T_P256TO511 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_P256TO511_RMON_T_P256TO511(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_P512TO1023 (0x00000234)
-
-#define BP_ENET_MAC0_RMON_T_P512TO1023_RMON_T_P512TO1023 0
-#define BM_ENET_MAC0_RMON_T_P512TO1023_RMON_T_P512TO1023 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_P512TO1023_RMON_T_P512TO1023(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_P1024TO2047 (0x00000238)
-
-#define BP_ENET_MAC0_RMON_T_P1024TO2047_RMON_T_P1024TO2047 0
-#define BM_ENET_MAC0_RMON_T_P1024TO2047_RMON_T_P1024TO2047 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_P1024TO2047_RMON_T_P1024TO2047(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_P_GTE2048 (0x0000023c)
-
-#define BP_ENET_MAC0_RMON_T_P_GTE2048_RMON_T_P_GTE2048 0
-#define BM_ENET_MAC0_RMON_T_P_GTE2048_RMON_T_P_GTE2048 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_P_GTE2048_RMON_T_P_GTE2048(v) (v)
-
-#define HW_ENET_MAC0_RMON_T_OCTETS (0x00000240)
-
-#define BP_ENET_MAC0_RMON_T_OCTETS_RMON_T_OCTETS 0
-#define BM_ENET_MAC0_RMON_T_OCTETS_RMON_T_OCTETS 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_T_OCTETS_RMON_T_OCTETS(v) (v)
-
-#define HW_ENET_MAC0_IEEE_T_DROP (0x00000244)
-
-#define BP_ENET_MAC0_IEEE_T_DROP_IEEE_T_DROP 0
-#define BM_ENET_MAC0_IEEE_T_DROP_IEEE_T_DROP 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_T_DROP_IEEE_T_DROP(v) (v)
-
-#define HW_ENET_MAC0_IEEE_T_FRAME_OK (0x00000248)
-
-#define BP_ENET_MAC0_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK 0
-#define BM_ENET_MAC0_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK(v) (v)
-
-#define HW_ENET_MAC0_IEEE_T_1COL (0x0000024c)
-
-#define BP_ENET_MAC0_IEEE_T_1COL_IEEE_T_1COL 0
-#define BM_ENET_MAC0_IEEE_T_1COL_IEEE_T_1COL 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_T_1COL_IEEE_T_1COL(v) (v)
-
-#define HW_ENET_MAC0_IEEE_T_MCOL (0x00000250)
-
-#define BP_ENET_MAC0_IEEE_T_MCOL_IEEE_T_MCOL 0
-#define BM_ENET_MAC0_IEEE_T_MCOL_IEEE_T_MCOL 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_T_MCOL_IEEE_T_MCOL(v) (v)
-
-#define HW_ENET_MAC0_IEEE_T_DEF (0x00000254)
-
-#define BP_ENET_MAC0_IEEE_T_DEF_IEEE_T_DEF 0
-#define BM_ENET_MAC0_IEEE_T_DEF_IEEE_T_DEF 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_T_DEF_IEEE_T_DEF(v) (v)
-
-#define HW_ENET_MAC0_IEEE_T_LCOL (0x00000258)
-
-#define BP_ENET_MAC0_IEEE_T_LCOL_IEEE_T_LCOL 0
-#define BM_ENET_MAC0_IEEE_T_LCOL_IEEE_T_LCOL 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_T_LCOL_IEEE_T_LCOL(v) (v)
-
-#define HW_ENET_MAC0_IEEE_T_EXCOL (0x0000025c)
-
-#define BP_ENET_MAC0_IEEE_T_EXCOL_IEEE_T_EXCOL 0
-#define BM_ENET_MAC0_IEEE_T_EXCOL_IEEE_T_EXCOL 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_T_EXCOL_IEEE_T_EXCOL(v) (v)
-
-#define HW_ENET_MAC0_IEEE_T_MACERR (0x00000260)
-
-#define BP_ENET_MAC0_IEEE_T_MACERR_IEEE_T_MACERR 0
-#define BM_ENET_MAC0_IEEE_T_MACERR_IEEE_T_MACERR 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_T_MACERR_IEEE_T_MACERR(v) (v)
-
-#define HW_ENET_MAC0_IEEE_T_CSERR (0x00000264)
-
-#define BP_ENET_MAC0_IEEE_T_CSERR_IEEE_T_CSERR 0
-#define BM_ENET_MAC0_IEEE_T_CSERR_IEEE_T_CSERR 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_T_CSERR_IEEE_T_CSERR(v) (v)
-
-#define HW_ENET_MAC0_IEEE_T_SQE (0x00000268)
-
-#define BP_ENET_MAC0_IEEE_T_SQE_IEEE_T_SQE 0
-#define BM_ENET_MAC0_IEEE_T_SQE_IEEE_T_SQE 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_T_SQE_IEEE_T_SQE(v) (v)
-
-#define HW_ENET_MAC0_IEEE_T_FDXFC (0x0000026c)
-
-#define BP_ENET_MAC0_IEEE_T_FDXFC_IEEE_T_FDXFC 0
-#define BM_ENET_MAC0_IEEE_T_FDXFC_IEEE_T_FDXFC 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_T_FDXFC_IEEE_T_FDXFC(v) (v)
-
-#define HW_ENET_MAC0_IEEE_T_OCTETS_OK (0x00000270)
-
-#define BP_ENET_MAC0_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK 0
-#define BM_ENET_MAC0_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK(v) (v)
-
-#define HW_ENET_MAC0_RMON_R_PACKETS (0x00000280)
-
-#define BP_ENET_MAC0_RMON_R_PACKETS_RMON_R_PACKETS 0
-#define BM_ENET_MAC0_RMON_R_PACKETS_RMON_R_PACKETS 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_R_PACKETS_RMON_R_PACKETS(v) (v)
-
-#define HW_ENET_MAC0_RMON_R_BC_PKT (0x00000284)
-
-#define BP_ENET_MAC0_RMON_R_BC_PKT_RMON_R_BC_PKT 0
-#define BM_ENET_MAC0_RMON_R_BC_PKT_RMON_R_BC_PKT 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_R_BC_PKT_RMON_R_BC_PKT(v) (v)
-
-#define HW_ENET_MAC0_RMON_R_MC_PKT (0x00000288)
-
-#define BP_ENET_MAC0_RMON_R_MC_PKT_RMON_R_MC_PKT 0
-#define BM_ENET_MAC0_RMON_R_MC_PKT_RMON_R_MC_PKT 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_R_MC_PKT_RMON_R_MC_PKT(v) (v)
-
-#define HW_ENET_MAC0_RMON_R_CRC_ALIGN (0x0000028c)
-
-#define BP_ENET_MAC0_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN 0
-#define BM_ENET_MAC0_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN(v) (v)
-
-#define HW_ENET_MAC0_RMON_R_UNDERSIZE (0x00000290)
-
-#define BP_ENET_MAC0_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE 0
-#define BM_ENET_MAC0_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE(v) (v)
-
-#define HW_ENET_MAC0_RMON_R_OVERSIZE (0x00000294)
-
-#define BP_ENET_MAC0_RMON_R_OVERSIZE_RMON_R_OVERSIZE 0
-#define BM_ENET_MAC0_RMON_R_OVERSIZE_RMON_R_OVERSIZE 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_R_OVERSIZE_RMON_R_OVERSIZE(v) (v)
-
-#define HW_ENET_MAC0_RMON_R_FRAG (0x00000298)
-
-#define BP_ENET_MAC0_RMON_R_FRAG_RMON_R_FRAG 0
-#define BM_ENET_MAC0_RMON_R_FRAG_RMON_R_FRAG 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_R_FRAG_RMON_R_FRAG(v) (v)
-
-#define HW_ENET_MAC0_RMON_R_JAB (0x0000029c)
-
-#define BP_ENET_MAC0_RMON_R_JAB_RMON_R_JAB 0
-#define BM_ENET_MAC0_RMON_R_JAB_RMON_R_JAB 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_R_JAB_RMON_R_JAB(v) (v)
-
-#define HW_ENET_MAC0_RMON_R_P64 (0x000002a4)
-
-#define BP_ENET_MAC0_RMON_R_P64_RMON_R_P64 0
-#define BM_ENET_MAC0_RMON_R_P64_RMON_R_P64 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_R_P64_RMON_R_P64(v) (v)
-
-#define HW_ENET_MAC0_RMON_R_P65TO127 (0x000002a8)
-
-#define BP_ENET_MAC0_RMON_R_P65TO127_RMON_R_P65TO127 0
-#define BM_ENET_MAC0_RMON_R_P65TO127_RMON_R_P65TO127 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_R_P65TO127_RMON_R_P65TO127(v) (v)
-
-#define HW_ENET_MAC0_RMON_R_P128TO255 (0x000002ac)
-
-#define BP_ENET_MAC0_RMON_R_P128TO255_RMON_R_P128TO255 0
-#define BM_ENET_MAC0_RMON_R_P128TO255_RMON_R_P128TO255 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_R_P128TO255_RMON_R_P128TO255(v) (v)
-
-#define HW_ENET_MAC0_RMON_R_P256TO511 (0x000002b0)
-
-#define BP_ENET_MAC0_RMON_R_P256TO511_RMON_R_P256TO511 0
-#define BM_ENET_MAC0_RMON_R_P256TO511_RMON_R_P256TO511 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_R_P256TO511_RMON_R_P256TO511(v) (v)
-
-#define HW_ENET_MAC0_RMON_R_P512TO1023 (0x000002b4)
-
-#define BP_ENET_MAC0_RMON_R_P512TO1023_RMON_R_P512TO1023 0
-#define BM_ENET_MAC0_RMON_R_P512TO1023_RMON_R_P512TO1023 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_R_P512TO1023_RMON_R_P512TO1023(v) (v)
-
-#define HW_ENET_MAC0_RMON_R_P1024TO2047 (0x000002b8)
-
-#define BP_ENET_MAC0_RMON_R_P1024TO2047_RMON_R_P1024TO2047 0
-#define BM_ENET_MAC0_RMON_R_P1024TO2047_RMON_R_P1024TO2047 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_R_P1024TO2047_RMON_R_P1024TO2047(v) (v)
-
-#define HW_ENET_MAC0_RMON_R_P_GTE2048 (0x000002bc)
-
-#define BP_ENET_MAC0_RMON_R_P_GTE2048_RMON_R_P_GTE2048 0
-#define BM_ENET_MAC0_RMON_R_P_GTE2048_RMON_R_P_GTE2048 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_R_P_GTE2048_RMON_R_P_GTE2048(v) (v)
-
-#define HW_ENET_MAC0_RMON_R_OCTETS (0x000002c0)
-
-#define BP_ENET_MAC0_RMON_R_OCTETS_RMON_R_OCTETS 0
-#define BM_ENET_MAC0_RMON_R_OCTETS_RMON_R_OCTETS 0xFFFFFFFF
-#define BF_ENET_MAC0_RMON_R_OCTETS_RMON_R_OCTETS(v) (v)
-
-#define HW_ENET_MAC0_IEEE_R_DROP (0x000002c4)
-
-#define BP_ENET_MAC0_IEEE_R_DROP_IEEE_R_DROP 0
-#define BM_ENET_MAC0_IEEE_R_DROP_IEEE_R_DROP 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_R_DROP_IEEE_R_DROP(v) (v)
-
-#define HW_ENET_MAC0_IEEE_R_FRAME_OK (0x000002c8)
-
-#define BP_ENET_MAC0_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK 0
-#define BM_ENET_MAC0_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK(v) (v)
-
-#define HW_ENET_MAC0_IEEE_R_CRC (0x000002cc)
-
-#define BP_ENET_MAC0_IEEE_R_CRC_IEEE_R_CRC 0
-#define BM_ENET_MAC0_IEEE_R_CRC_IEEE_R_CRC 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_R_CRC_IEEE_R_CRC(v) (v)
-
-#define HW_ENET_MAC0_IEEE_R_ALIGN (0x000002d0)
-
-#define BP_ENET_MAC0_IEEE_R_ALIGN_IEEE_R_ALIGN 0
-#define BM_ENET_MAC0_IEEE_R_ALIGN_IEEE_R_ALIGN 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_R_ALIGN_IEEE_R_ALIGN(v) (v)
-
-#define HW_ENET_MAC0_IEEE_R_MACERR (0x000002d4)
-
-#define BP_ENET_MAC0_IEEE_R_MACERR_IEEE_R_MACERR 0
-#define BM_ENET_MAC0_IEEE_R_MACERR_IEEE_R_MACERR 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_R_MACERR_IEEE_R_MACERR(v) (v)
-
-#define HW_ENET_MAC0_IEEE_R_FDXFC (0x000002d8)
-
-#define BP_ENET_MAC0_IEEE_R_FDXFC_IEEE_R_FDXFC 0
-#define BM_ENET_MAC0_IEEE_R_FDXFC_IEEE_R_FDXFC 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_R_FDXFC_IEEE_R_FDXFC(v) (v)
-
-#define HW_ENET_MAC0_IEEE_R_OCTETS_OK (0x000002dc)
-
-#define BP_ENET_MAC0_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK 0
-#define BM_ENET_MAC0_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK 0xFFFFFFFF
-#define BF_ENET_MAC0_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK(v) (v)
-
-#define HW_ENET_MAC0_ATIME_CTRL (0x000003fc)
-
-#define BP_ENET_MAC0_ATIME_CTRL_RSRVD0 14
-#define BM_ENET_MAC0_ATIME_CTRL_RSRVD0 0xFFFFC000
-#define BF_ENET_MAC0_ATIME_CTRL_RSRVD0(v) \
- (((v) << 14) & BM_ENET_MAC0_ATIME_CTRL_RSRVD0)
-#define BM_ENET_MAC0_ATIME_CTRL_FRC_SLAVE 0x00002000
-#define BM_ENET_MAC0_ATIME_CTRL_RSRVD1 0x00001000
-#define BM_ENET_MAC0_ATIME_CTRL_CAPTURE 0x00000800
-#define BM_ENET_MAC0_ATIME_CTRL_RSRVD2 0x00000400
-#define BM_ENET_MAC0_ATIME_CTRL_RESTART 0x00000200
-#define BM_ENET_MAC0_ATIME_CTRL_RSRVD3 0x00000100
-#define BM_ENET_MAC0_ATIME_CTRL_PIN_PERIOD_ENA 0x00000080
-#define BM_ENET_MAC0_ATIME_CTRL_RSRVD4 0x00000040
-#define BM_ENET_MAC0_ATIME_CTRL_EVT_PERIOD_RST 0x00000020
-#define BM_ENET_MAC0_ATIME_CTRL_EVT_PERIOD_ENA 0x00000010
-#define BM_ENET_MAC0_ATIME_CTRL_EVT_OFFSET_RST 0x00000008
-#define BM_ENET_MAC0_ATIME_CTRL_EVT_OFFSET_ENA 0x00000004
-#define BM_ENET_MAC0_ATIME_CTRL_ONE_SHOT 0x00000002
-#define BM_ENET_MAC0_ATIME_CTRL_ENABLE 0x00000001
-
-#define HW_ENET_MAC0_ATIME (0x00000400)
-
-#define BP_ENET_MAC0_ATIME_ATIME 0
-#define BM_ENET_MAC0_ATIME_ATIME 0xFFFFFFFF
-#define BF_ENET_MAC0_ATIME_ATIME(v) (v)
-
-#define HW_ENET_MAC0_ATIME_EVT_OFFSET (0x00000404)
-
-#define BP_ENET_MAC0_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET 0
-#define BM_ENET_MAC0_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET 0xFFFFFFFF
-#define BF_ENET_MAC0_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET(v) (v)
-
-#define HW_ENET_MAC0_ATIME_EVT_PERIOD (0x00000408)
-
-#define BP_ENET_MAC0_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD 0
-#define BM_ENET_MAC0_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD 0xFFFFFFFF
-#define BF_ENET_MAC0_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD(v) (v)
-
-#define HW_ENET_MAC0_ATIME_CORR (0x0000040c)
-
-#define BM_ENET_MAC0_ATIME_CORR_RSRVD0 0x80000000
-#define BP_ENET_MAC0_ATIME_CORR_ATIME_CORR 0
-#define BM_ENET_MAC0_ATIME_CORR_ATIME_CORR 0x7FFFFFFF
-#define BF_ENET_MAC0_ATIME_CORR_ATIME_CORR(v) \
- (((v) << 0) & BM_ENET_MAC0_ATIME_CORR_ATIME_CORR)
-
-#define HW_ENET_MAC0_ATIME_INC (0x00000410)
-
-#define BP_ENET_MAC0_ATIME_INC_RSRVD0 15
-#define BM_ENET_MAC0_ATIME_INC_RSRVD0 0xFFFF8000
-#define BF_ENET_MAC0_ATIME_INC_RSRVD0(v) \
- (((v) << 15) & BM_ENET_MAC0_ATIME_INC_RSRVD0)
-#define BP_ENET_MAC0_ATIME_INC_ATIME_INC_CORR 8
-#define BM_ENET_MAC0_ATIME_INC_ATIME_INC_CORR 0x00007F00
-#define BF_ENET_MAC0_ATIME_INC_ATIME_INC_CORR(v) \
- (((v) << 8) & BM_ENET_MAC0_ATIME_INC_ATIME_INC_CORR)
-#define BM_ENET_MAC0_ATIME_INC_RSRVD1 0x00000080
-#define BP_ENET_MAC0_ATIME_INC_ATIME_INC 0
-#define BM_ENET_MAC0_ATIME_INC_ATIME_INC 0x0000007F
-#define BF_ENET_MAC0_ATIME_INC_ATIME_INC(v) \
- (((v) << 0) & BM_ENET_MAC0_ATIME_INC_ATIME_INC)
-
-#define HW_ENET_MAC0_TS_TIMESTAMP (0x00000414)
-
-#define BP_ENET_MAC0_TS_TIMESTAMP_TS_TIMESTAMP 0
-#define BM_ENET_MAC0_TS_TIMESTAMP_TS_TIMESTAMP 0xFFFFFFFF
-#define BF_ENET_MAC0_TS_TIMESTAMP_TS_TIMESTAMP(v) (v)
-
-#define HW_ENET_MAC0_SMAC_0_0 (0x000004fc)
-
-#define BP_ENET_MAC0_SMAC_0_0_SMAC_0_0 0
-#define BM_ENET_MAC0_SMAC_0_0_SMAC_0_0 0xFFFFFFFF
-#define BF_ENET_MAC0_SMAC_0_0_SMAC_0_0(v) (v)
-
-#define HW_ENET_MAC0_SMAC_0_1 (0x00000500)
-
-#define BP_ENET_MAC0_SMAC_0_1_SMAC_0_1 0
-#define BM_ENET_MAC0_SMAC_0_1_SMAC_0_1 0xFFFFFFFF
-#define BF_ENET_MAC0_SMAC_0_1_SMAC_0_1(v) (v)
-
-#define HW_ENET_MAC0_SMAC_1_0 (0x00000504)
-
-#define BP_ENET_MAC0_SMAC_1_0_SMAC_1_0 0
-#define BM_ENET_MAC0_SMAC_1_0_SMAC_1_0 0xFFFFFFFF
-#define BF_ENET_MAC0_SMAC_1_0_SMAC_1_0(v) (v)
-
-#define HW_ENET_MAC0_SMAC_1_1 (0x00000508)
-
-#define BP_ENET_MAC0_SMAC_1_1_SMAC_1_1 0
-#define BM_ENET_MAC0_SMAC_1_1_SMAC_1_1 0xFFFFFFFF
-#define BF_ENET_MAC0_SMAC_1_1_SMAC_1_1(v) (v)
-
-#define HW_ENET_MAC0_SMAC_2_0 (0x0000050c)
-
-#define BP_ENET_MAC0_SMAC_2_0_SMAC_2_0 0
-#define BM_ENET_MAC0_SMAC_2_0_SMAC_2_0 0xFFFFFFFF
-#define BF_ENET_MAC0_SMAC_2_0_SMAC_2_0(v) (v)
-
-#define HW_ENET_MAC0_SMAC_2_1 (0x00000510)
-
-#define BP_ENET_MAC0_SMAC_2_1_SMAC_2_1 0
-#define BM_ENET_MAC0_SMAC_2_1_SMAC_2_1 0xFFFFFFFF
-#define BF_ENET_MAC0_SMAC_2_1_SMAC_2_1(v) (v)
-
-#define HW_ENET_MAC0_SMAC_3_0 (0x00000514)
-
-#define BP_ENET_MAC0_SMAC_3_0_SMAC_3_0 0
-#define BM_ENET_MAC0_SMAC_3_0_SMAC_3_0 0xFFFFFFFF
-#define BF_ENET_MAC0_SMAC_3_0_SMAC_3_0(v) (v)
-
-#define HW_ENET_MAC0_SMAC_3_1 (0x00000518)
-
-#define BP_ENET_MAC0_SMAC_3_1_SMAC_3_1 0
-#define BM_ENET_MAC0_SMAC_3_1_SMAC_3_1 0xFFFFFFFF
-#define BF_ENET_MAC0_SMAC_3_1_SMAC_3_1(v) (v)
-
-#define HW_ENET_MAC0_COMP_REG_0 (0x000005fc)
-
-#define BP_ENET_MAC0_COMP_REG_0_COMP_REG_0 0
-#define BM_ENET_MAC0_COMP_REG_0_COMP_REG_0 0xFFFFFFFF
-#define BF_ENET_MAC0_COMP_REG_0_COMP_REG_0(v) (v)
-
-#define HW_ENET_MAC0_COMP_REG_1 (0x00000600)
-
-#define BP_ENET_MAC0_COMP_REG_1_COMP_REG_1 0
-#define BM_ENET_MAC0_COMP_REG_1_COMP_REG_1 0xFFFFFFFF
-#define BF_ENET_MAC0_COMP_REG_1_COMP_REG_1(v) (v)
-
-#define HW_ENET_MAC0_COMP_REG_2 (0x00000604)
-
-#define BP_ENET_MAC0_COMP_REG_2_COMP_REG_2 0
-#define BM_ENET_MAC0_COMP_REG_2_COMP_REG_2 0xFFFFFFFF
-#define BF_ENET_MAC0_COMP_REG_2_COMP_REG_2(v) (v)
-
-#define HW_ENET_MAC0_COMP_REG_3 (0x00000608)
-
-#define BP_ENET_MAC0_COMP_REG_3_COMP_REG_3 0
-#define BM_ENET_MAC0_COMP_REG_3_COMP_REG_3 0xFFFFFFFF
-#define BF_ENET_MAC0_COMP_REG_3_COMP_REG_3(v) (v)
-
-#define HW_ENET_MAC0_CAPT_REG_0 (0x0000063c)
-
-#define BP_ENET_MAC0_CAPT_REG_0_CAPT_REG_0 0
-#define BM_ENET_MAC0_CAPT_REG_0_CAPT_REG_0 0xFFFFFFFF
-#define BF_ENET_MAC0_CAPT_REG_0_CAPT_REG_0(v) (v)
-
-#define HW_ENET_MAC0_CAPT_REG_1 (0x00000640)
-
-#define BP_ENET_MAC0_CAPT_REG_1_CAPT_REG_1 0
-#define BM_ENET_MAC0_CAPT_REG_1_CAPT_REG_1 0xFFFFFFFF
-#define BF_ENET_MAC0_CAPT_REG_1_CAPT_REG_1(v) (v)
-
-#define HW_ENET_MAC0_CAPT_REG_2 (0x00000644)
-
-#define BP_ENET_MAC0_CAPT_REG_2_CAPT_REG_2 0
-#define BM_ENET_MAC0_CAPT_REG_2_CAPT_REG_2 0xFFFFFFFF
-#define BF_ENET_MAC0_CAPT_REG_2_CAPT_REG_2(v) (v)
-
-#define HW_ENET_MAC0_CAPT_REG_3 (0x00000648)
-
-#define BP_ENET_MAC0_CAPT_REG_3_CAPT_REG_3 0
-#define BM_ENET_MAC0_CAPT_REG_3_CAPT_REG_3 0xFFFFFFFF
-#define BF_ENET_MAC0_CAPT_REG_3_CAPT_REG_3(v) (v)
-
-#define HW_ENET_MAC0_CCB_INT (0x0000067c)
-
-#define BP_ENET_MAC0_CCB_INT_RSRVD0 20
-#define BM_ENET_MAC0_CCB_INT_RSRVD0 0xFFF00000
-#define BF_ENET_MAC0_CCB_INT_RSRVD0(v) \
- (((v) << 20) & BM_ENET_MAC0_CCB_INT_RSRVD0)
-#define BM_ENET_MAC0_CCB_INT_COMPARE3 0x00080000
-#define BM_ENET_MAC0_CCB_INT_COMPARE2 0x00040000
-#define BM_ENET_MAC0_CCB_INT_COMPARE1 0x00020000
-#define BM_ENET_MAC0_CCB_INT_COMPARE0 0x00010000
-#define BP_ENET_MAC0_CCB_INT_RSRVD1 4
-#define BM_ENET_MAC0_CCB_INT_RSRVD1 0x0000FFF0
-#define BF_ENET_MAC0_CCB_INT_RSRVD1(v) \
- (((v) << 4) & BM_ENET_MAC0_CCB_INT_RSRVD1)
-#define BM_ENET_MAC0_CCB_INT_CAPTURE3 0x00000008
-#define BM_ENET_MAC0_CCB_INT_CAPTURE2 0x00000004
-#define BM_ENET_MAC0_CCB_INT_CAPTURE1 0x00000002
-#define BM_ENET_MAC0_CCB_INT_CAPTURE0 0x00000001
-
-#define HW_ENET_MAC0_CCB_INT_MASK (0x00000680)
-
-#define BP_ENET_MAC0_CCB_INT_MASK_RSRVD0 20
-#define BM_ENET_MAC0_CCB_INT_MASK_RSRVD0 0xFFF00000
-#define BF_ENET_MAC0_CCB_INT_MASK_RSRVD0(v) \
- (((v) << 20) & BM_ENET_MAC0_CCB_INT_MASK_RSRVD0)
-#define BM_ENET_MAC0_CCB_INT_MASK_COMPARE3 0x00080000
-#define BM_ENET_MAC0_CCB_INT_MASK_COMPARE2 0x00040000
-#define BM_ENET_MAC0_CCB_INT_MASK_COMPARE1 0x00020000
-#define BM_ENET_MAC0_CCB_INT_MASK_COMPARE0 0x00010000
-#define BP_ENET_MAC0_CCB_INT_MASK_RSRVD1 4
-#define BM_ENET_MAC0_CCB_INT_MASK_RSRVD1 0x0000FFF0
-#define BF_ENET_MAC0_CCB_INT_MASK_RSRVD1(v) \
- (((v) << 4) & BM_ENET_MAC0_CCB_INT_MASK_RSRVD1)
-#define BM_ENET_MAC0_CCB_INT_MASK_CAPTURE3 0x00000008
-#define BM_ENET_MAC0_CCB_INT_MASK_CAPTURE2 0x00000004
-#define BM_ENET_MAC0_CCB_INT_MASK_CAPTURE1 0x00000002
-#define BM_ENET_MAC0_CCB_INT_MASK_CAPTURE0 0x00000001
-
-#define HW_ENET_MAC1_EIR (0x00004000)
-
-#define BM_ENET_MAC1_EIR_RSRVD0 0x80000000
-#define BM_ENET_MAC1_EIR_BABR 0x40000000
-#define BM_ENET_MAC1_EIR_BABT 0x20000000
-#define BM_ENET_MAC1_EIR_GRA 0x10000000
-#define BM_ENET_MAC1_EIR_TXF 0x08000000
-#define BM_ENET_MAC1_EIR_TXB 0x04000000
-#define BM_ENET_MAC1_EIR_RXF 0x02000000
-#define BM_ENET_MAC1_EIR_RXB 0x01000000
-#define BM_ENET_MAC1_EIR_MII 0x00800000
-#define BM_ENET_MAC1_EIR_EBERR 0x00400000
-#define BM_ENET_MAC1_EIR_LC 0x00200000
-#define BM_ENET_MAC1_EIR_RL 0x00100000
-#define BM_ENET_MAC1_EIR_UN 0x00080000
-#define BM_ENET_MAC1_EIR_PLR 0x00040000
-#define BM_ENET_MAC1_EIR_WAKEUP 0x00020000
-#define BM_ENET_MAC1_EIR_TS_AVAIL 0x00010000
-#define BM_ENET_MAC1_EIR_TS_TIMER 0x00008000
-#define BP_ENET_MAC1_EIR_RSRVD1 0
-#define BM_ENET_MAC1_EIR_RSRVD1 0x00007FFF
-#define BF_ENET_MAC1_EIR_RSRVD1(v) \
- (((v) << 0) & BM_ENET_MAC1_EIR_RSRVD1)
-
-#define HW_ENET_MAC1_EIMR (0x00004004)
-
-#define BP_ENET_MAC1_EIMR_EIMR 0
-#define BM_ENET_MAC1_EIMR_EIMR 0xFFFFFFFF
-#define BF_ENET_MAC1_EIMR_EIMR(v) (v)
-
-#define HW_ENET_MAC1_RDAR (0x0000400c)
-
-#define BP_ENET_MAC1_RDAR_RSRVD0 25
-#define BM_ENET_MAC1_RDAR_RSRVD0 0xFE000000
-#define BF_ENET_MAC1_RDAR_RSRVD0(v) \
- (((v) << 25) & BM_ENET_MAC1_RDAR_RSRVD0)
-#define BM_ENET_MAC1_RDAR_RDAR 0x01000000
-#define BP_ENET_MAC1_RDAR_RSRVD1 0
-#define BM_ENET_MAC1_RDAR_RSRVD1 0x00FFFFFF
-#define BF_ENET_MAC1_RDAR_RSRVD1(v) \
- (((v) << 0) & BM_ENET_MAC1_RDAR_RSRVD1)
-
-#define HW_ENET_MAC1_TDAR (0x00004010)
-
-#define BP_ENET_MAC1_TDAR_RSRVD0 25
-#define BM_ENET_MAC1_TDAR_RSRVD0 0xFE000000
-#define BF_ENET_MAC1_TDAR_RSRVD0(v) \
- (((v) << 25) & BM_ENET_MAC1_TDAR_RSRVD0)
-#define BM_ENET_MAC1_TDAR_TDAR 0x01000000
-#define BP_ENET_MAC1_TDAR_RSRVD1 0
-#define BM_ENET_MAC1_TDAR_RSRVD1 0x00FFFFFF
-#define BF_ENET_MAC1_TDAR_RSRVD1(v) \
- (((v) << 0) & BM_ENET_MAC1_TDAR_RSRVD1)
-
-#define HW_ENET_MAC1_ECR (0x00004020)
-
-#define BP_ENET_MAC1_ECR_RSRVD0 7
-#define BM_ENET_MAC1_ECR_RSRVD0 0xFFFFFF80
-#define BF_ENET_MAC1_ECR_RSRVD0(v) \
- (((v) << 7) & BM_ENET_MAC1_ECR_RSRVD0)
-#define BM_ENET_MAC1_ECR_DBG_EN 0x00000040
-#define BM_ENET_MAC1_ECR_ETH_SPEED 0x00000020
-#define BM_ENET_MAC1_ECR_ENA_1588 0x00000010
-#define BM_ENET_MAC1_ECR_SLEEP 0x00000008
-#define BM_ENET_MAC1_ECR_MAGIC_ENA 0x00000004
-#define BM_ENET_MAC1_ECR_ETHER_EN 0x00000002
-#define BM_ENET_MAC1_ECR_RESET 0x00000001
-
-#define HW_ENET_MAC1_MMFR (0x0000403c)
-
-#define BP_ENET_MAC1_MMFR_ST 30
-#define BM_ENET_MAC1_MMFR_ST 0xC0000000
-#define BF_ENET_MAC1_MMFR_ST(v) \
- (((v) << 30) & BM_ENET_MAC1_MMFR_ST)
-#define BP_ENET_MAC1_MMFR_OP 28
-#define BM_ENET_MAC1_MMFR_OP 0x30000000
-#define BF_ENET_MAC1_MMFR_OP(v) \
- (((v) << 28) & BM_ENET_MAC1_MMFR_OP)
-#define BP_ENET_MAC1_MMFR_PA 23
-#define BM_ENET_MAC1_MMFR_PA 0x0F800000
-#define BF_ENET_MAC1_MMFR_PA(v) \
- (((v) << 23) & BM_ENET_MAC1_MMFR_PA)
-#define BP_ENET_MAC1_MMFR_RA 18
-#define BM_ENET_MAC1_MMFR_RA 0x007C0000
-#define BF_ENET_MAC1_MMFR_RA(v) \
- (((v) << 18) & BM_ENET_MAC1_MMFR_RA)
-#define BP_ENET_MAC1_MMFR_TA 16
-#define BM_ENET_MAC1_MMFR_TA 0x00030000
-#define BF_ENET_MAC1_MMFR_TA(v) \
- (((v) << 16) & BM_ENET_MAC1_MMFR_TA)
-#define BP_ENET_MAC1_MMFR_DATA 0
-#define BM_ENET_MAC1_MMFR_DATA 0x0000FFFF
-#define BF_ENET_MAC1_MMFR_DATA(v) \
- (((v) << 0) & BM_ENET_MAC1_MMFR_DATA)
-
-#define HW_ENET_MAC1_MSCR (0x00004040)
-
-#define BP_ENET_MAC1_MSCR_RSRVD0 11
-#define BM_ENET_MAC1_MSCR_RSRVD0 0xFFFFF800
-#define BF_ENET_MAC1_MSCR_RSRVD0(v) \
- (((v) << 11) & BM_ENET_MAC1_MSCR_RSRVD0)
-#define BP_ENET_MAC1_MSCR_HOLDTIME 8
-#define BM_ENET_MAC1_MSCR_HOLDTIME 0x00000700
-#define BF_ENET_MAC1_MSCR_HOLDTIME(v) \
- (((v) << 8) & BM_ENET_MAC1_MSCR_HOLDTIME)
-#define BM_ENET_MAC1_MSCR_DIS_PRE 0x00000080
-#define BP_ENET_MAC1_MSCR_MII_SPEED 1
-#define BM_ENET_MAC1_MSCR_MII_SPEED 0x0000007E
-#define BF_ENET_MAC1_MSCR_MII_SPEED(v) \
- (((v) << 1) & BM_ENET_MAC1_MSCR_MII_SPEED)
-#define BM_ENET_MAC1_MSCR_RSRVD1 0x00000001
-
-#define HW_ENET_MAC1_MIBC (0x00004060)
-
-#define BM_ENET_MAC1_MIBC_MIB_DIS 0x80000000
-#define BM_ENET_MAC1_MIBC_MIB_IDLE 0x40000000
-#define BM_ENET_MAC1_MIBC_MIB_CLEAR 0x20000000
-#define BP_ENET_MAC1_MIBC_RSRVD0 0
-#define BM_ENET_MAC1_MIBC_RSRVD0 0x1FFFFFFF
-#define BF_ENET_MAC1_MIBC_RSRVD0(v) \
- (((v) << 0) & BM_ENET_MAC1_MIBC_RSRVD0)
-
-#define HW_ENET_MAC1_RCR (0x00004080)
-
-#define BM_ENET_MAC1_RCR_GRS 0x80000000
-#define BM_ENET_MAC1_RCR_NO_LGTH_CHECK 0x40000000
-#define BP_ENET_MAC1_RCR_MAX_FL 16
-#define BM_ENET_MAC1_RCR_MAX_FL 0x3FFF0000
-#define BF_ENET_MAC1_RCR_MAX_FL(v) \
- (((v) << 16) & BM_ENET_MAC1_RCR_MAX_FL)
-#define BM_ENET_MAC1_RCR_CNTL_FRM_ENA 0x00008000
-#define BM_ENET_MAC1_RCR_CRC_FWD 0x00004000
-#define BM_ENET_MAC1_RCR_PAUSE_FWD 0x00002000
-#define BM_ENET_MAC1_RCR_PAD_EN 0x00001000
-#define BM_ENET_MAC1_RCR_RMII_ECHO 0x00000800
-#define BM_ENET_MAC1_RCR_RMII_LOOP 0x00000400
-#define BM_ENET_MAC1_RCR_RMII_10T 0x00000200
-#define BM_ENET_MAC1_RCR_RMII_MODE 0x00000100
-#define BM_ENET_MAC1_RCR_SGMII_ENA 0x00000080
-#define BM_ENET_MAC1_RCR_RGMII_ENA 0x00000040
-#define BM_ENET_MAC1_RCR_FCE 0x00000020
-#define BM_ENET_MAC1_RCR_BC_REJ 0x00000010
-#define BM_ENET_MAC1_RCR_PROM 0x00000008
-#define BM_ENET_MAC1_RCR_MII_MODE 0x00000004
-#define BM_ENET_MAC1_RCR_DRT 0x00000002
-#define BM_ENET_MAC1_RCR_LOOP 0x00000001
-
-#define HW_ENET_MAC1_TCR (0x000040c0)
-
-#define BP_ENET_MAC1_TCR_RSRVD0 10
-#define BM_ENET_MAC1_TCR_RSRVD0 0xFFFFFC00
-#define BF_ENET_MAC1_TCR_RSRVD0(v) \
- (((v) << 10) & BM_ENET_MAC1_TCR_RSRVD0)
-#define BM_ENET_MAC1_TCR_TX_CRC_FWD 0x00000200
-#define BM_ENET_MAC1_TCR_TX_ADDR_INS 0x00000100
-#define BP_ENET_MAC1_TCR_TX_ADDR_SEL 5
-#define BM_ENET_MAC1_TCR_TX_ADDR_SEL 0x000000E0
-#define BF_ENET_MAC1_TCR_TX_ADDR_SEL(v) \
- (((v) << 5) & BM_ENET_MAC1_TCR_TX_ADDR_SEL)
-#define BM_ENET_MAC1_TCR_RFC_PAUSE 0x00000010
-#define BM_ENET_MAC1_TCR_TFC_PAUSE 0x00000008
-#define BM_ENET_MAC1_TCR_FEDN 0x00000004
-#define BM_ENET_MAC1_TCR_HBC 0x00000002
-#define BM_ENET_MAC1_TCR_GTS 0x00000001
-
-#define HW_ENET_MAC1_PALR (0x000040e0)
-
-#define BP_ENET_MAC1_PALR_PADDR1 0
-#define BM_ENET_MAC1_PALR_PADDR1 0xFFFFFFFF
-#define BF_ENET_MAC1_PALR_PADDR1(v) (v)
-
-#define HW_ENET_MAC1_PAUR (0x000040e4)
-
-#define BP_ENET_MAC1_PAUR_PADDR2 16
-#define BM_ENET_MAC1_PAUR_PADDR2 0xFFFF0000
-#define BF_ENET_MAC1_PAUR_PADDR2(v) \
- (((v) << 16) & BM_ENET_MAC1_PAUR_PADDR2)
-#define BP_ENET_MAC1_PAUR_TYPE 0
-#define BM_ENET_MAC1_PAUR_TYPE 0x0000FFFF
-#define BF_ENET_MAC1_PAUR_TYPE(v) \
- (((v) << 0) & BM_ENET_MAC1_PAUR_TYPE)
-
-#define HW_ENET_MAC1_OPD (0x000040e8)
-
-#define BP_ENET_MAC1_OPD_OPCODE 16
-#define BM_ENET_MAC1_OPD_OPCODE 0xFFFF0000
-#define BF_ENET_MAC1_OPD_OPCODE(v) \
- (((v) << 16) & BM_ENET_MAC1_OPD_OPCODE)
-#define BP_ENET_MAC1_OPD_PAUSE_DUR 0
-#define BM_ENET_MAC1_OPD_PAUSE_DUR 0x0000FFFF
-#define BF_ENET_MAC1_OPD_PAUSE_DUR(v) \
- (((v) << 0) & BM_ENET_MAC1_OPD_PAUSE_DUR)
-
-#define HW_ENET_MAC1_IAUR (0x00004114)
-
-#define BP_ENET_MAC1_IAUR_IADDR1 0
-#define BM_ENET_MAC1_IAUR_IADDR1 0xFFFFFFFF
-#define BF_ENET_MAC1_IAUR_IADDR1(v) (v)
-
-#define HW_ENET_MAC1_IALR (0x00004118)
-
-#define BP_ENET_MAC1_IALR_IADDR2 0
-#define BM_ENET_MAC1_IALR_IADDR2 0xFFFFFFFF
-#define BF_ENET_MAC1_IALR_IADDR2(v) (v)
-
-#define HW_ENET_MAC1_GAUR (0x0000411c)
-
-#define BP_ENET_MAC1_GAUR_GADDR1 0
-#define BM_ENET_MAC1_GAUR_GADDR1 0xFFFFFFFF
-#define BF_ENET_MAC1_GAUR_GADDR1(v) (v)
-
-#define HW_ENET_MAC1_GALR (0x00004120)
-
-#define BP_ENET_MAC1_GALR_GADDR2 0
-#define BM_ENET_MAC1_GALR_GADDR2 0xFFFFFFFF
-#define BF_ENET_MAC1_GALR_GADDR2(v) (v)
-
-#define HW_ENET_MAC1_TFW_SFCR (0x00004140)
-
-#define BP_ENET_MAC1_TFW_SFCR_RSRVD0 9
-#define BM_ENET_MAC1_TFW_SFCR_RSRVD0 0xFFFFFE00
-#define BF_ENET_MAC1_TFW_SFCR_RSRVD0(v) \
- (((v) << 9) & BM_ENET_MAC1_TFW_SFCR_RSRVD0)
-#define BM_ENET_MAC1_TFW_SFCR_STR_FWD 0x00000100
-#define BP_ENET_MAC1_TFW_SFCR_RSRVD1 6
-#define BM_ENET_MAC1_TFW_SFCR_RSRVD1 0x000000C0
-#define BF_ENET_MAC1_TFW_SFCR_RSRVD1(v) \
- (((v) << 6) & BM_ENET_MAC1_TFW_SFCR_RSRVD1)
-#define BP_ENET_MAC1_TFW_SFCR_TFWR 0
-#define BM_ENET_MAC1_TFW_SFCR_TFWR 0x0000003F
-#define BF_ENET_MAC1_TFW_SFCR_TFWR(v) \
- (((v) << 0) & BM_ENET_MAC1_TFW_SFCR_TFWR)
-
-#define HW_ENET_MAC1_FRBR (0x00004148)
-
-#define BP_ENET_MAC1_FRBR_RSRVD0 10
-#define BM_ENET_MAC1_FRBR_RSRVD0 0xFFFFFC00
-#define BF_ENET_MAC1_FRBR_RSRVD0(v) \
- (((v) << 10) & BM_ENET_MAC1_FRBR_RSRVD0)
-#define BP_ENET_MAC1_FRBR_R_BOUND 2
-#define BM_ENET_MAC1_FRBR_R_BOUND 0x000003FC
-#define BF_ENET_MAC1_FRBR_R_BOUND(v) \
- (((v) << 2) & BM_ENET_MAC1_FRBR_R_BOUND)
-#define BP_ENET_MAC1_FRBR_RSRVD1 0
-#define BM_ENET_MAC1_FRBR_RSRVD1 0x00000003
-#define BF_ENET_MAC1_FRBR_RSRVD1(v) \
- (((v) << 0) & BM_ENET_MAC1_FRBR_RSRVD1)
-
-#define HW_ENET_MAC1_FRSR (0x0000414c)
-
-#define BP_ENET_MAC1_FRSR_RSRVD0 11
-#define BM_ENET_MAC1_FRSR_RSRVD0 0xFFFFF800
-#define BF_ENET_MAC1_FRSR_RSRVD0(v) \
- (((v) << 11) & BM_ENET_MAC1_FRSR_RSRVD0)
-#define BM_ENET_MAC1_FRSR_RSRVD1 0x00000400
-#define BP_ENET_MAC1_FRSR_R_FSTART 2
-#define BM_ENET_MAC1_FRSR_R_FSTART 0x000003FC
-#define BF_ENET_MAC1_FRSR_R_FSTART(v) \
- (((v) << 2) & BM_ENET_MAC1_FRSR_R_FSTART)
-#define BP_ENET_MAC1_FRSR_RSRVD2 0
-#define BM_ENET_MAC1_FRSR_RSRVD2 0x00000003
-#define BF_ENET_MAC1_FRSR_RSRVD2(v) \
- (((v) << 0) & BM_ENET_MAC1_FRSR_RSRVD2)
-
-#define HW_ENET_MAC1_ERDSR (0x0000417c)
-
-#define BP_ENET_MAC1_ERDSR_R_DES_START 2
-#define BM_ENET_MAC1_ERDSR_R_DES_START 0xFFFFFFFC
-#define BF_ENET_MAC1_ERDSR_R_DES_START(v) \
- (((v) << 2) & BM_ENET_MAC1_ERDSR_R_DES_START)
-#define BP_ENET_MAC1_ERDSR_RSRVD0 0
-#define BM_ENET_MAC1_ERDSR_RSRVD0 0x00000003
-#define BF_ENET_MAC1_ERDSR_RSRVD0(v) \
- (((v) << 0) & BM_ENET_MAC1_ERDSR_RSRVD0)
-
-#define HW_ENET_MAC1_ETDSR (0x00004180)
-
-#define BP_ENET_MAC1_ETDSR_X_DES_START 2
-#define BM_ENET_MAC1_ETDSR_X_DES_START 0xFFFFFFFC
-#define BF_ENET_MAC1_ETDSR_X_DES_START(v) \
- (((v) << 2) & BM_ENET_MAC1_ETDSR_X_DES_START)
-#define BP_ENET_MAC1_ETDSR_RSRVD0 0
-#define BM_ENET_MAC1_ETDSR_RSRVD0 0x00000003
-#define BF_ENET_MAC1_ETDSR_RSRVD0(v) \
- (((v) << 0) & BM_ENET_MAC1_ETDSR_RSRVD0)
-
-#define HW_ENET_MAC1_EMRBR (0x00004184)
-
-#define BP_ENET_MAC1_EMRBR_RSRVD0 11
-#define BM_ENET_MAC1_EMRBR_RSRVD0 0xFFFFF800
-#define BF_ENET_MAC1_EMRBR_RSRVD0(v) \
- (((v) << 11) & BM_ENET_MAC1_EMRBR_RSRVD0)
-#define BP_ENET_MAC1_EMRBR_R_BUF_SIZE 4
-#define BM_ENET_MAC1_EMRBR_R_BUF_SIZE 0x000007F0
-#define BF_ENET_MAC1_EMRBR_R_BUF_SIZE(v) \
- (((v) << 4) & BM_ENET_MAC1_EMRBR_R_BUF_SIZE)
-#define BP_ENET_MAC1_EMRBR_RSRVD1 0
-#define BM_ENET_MAC1_EMRBR_RSRVD1 0x0000000F
-#define BF_ENET_MAC1_EMRBR_RSRVD1(v) \
- (((v) << 0) & BM_ENET_MAC1_EMRBR_RSRVD1)
-
-#define HW_ENET_MAC1_RX_SECTION_FULL (0x0000418c)
-
-#define BP_ENET_MAC1_RX_SECTION_FULL_RSRVD0 8
-#define BM_ENET_MAC1_RX_SECTION_FULL_RSRVD0 0xFFFFFF00
-#define BF_ENET_MAC1_RX_SECTION_FULL_RSRVD0(v) \
- (((v) << 8) & BM_ENET_MAC1_RX_SECTION_FULL_RSRVD0)
-#define BP_ENET_MAC1_RX_SECTION_FULL_RX_SECTION_FULL 0
-#define BM_ENET_MAC1_RX_SECTION_FULL_RX_SECTION_FULL 0x000000FF
-#define BF_ENET_MAC1_RX_SECTION_FULL_RX_SECTION_FULL(v) \
- (((v) << 0) & BM_ENET_MAC1_RX_SECTION_FULL_RX_SECTION_FULL)
-
-#define HW_ENET_MAC1_RX_SECTION_EMPTY (0x00004190)
-
-#define BP_ENET_MAC1_RX_SECTION_EMPTY_RSRVD0 8
-#define BM_ENET_MAC1_RX_SECTION_EMPTY_RSRVD0 0xFFFFFF00
-#define BF_ENET_MAC1_RX_SECTION_EMPTY_RSRVD0(v) \
- (((v) << 8) & BM_ENET_MAC1_RX_SECTION_EMPTY_RSRVD0)
-#define BP_ENET_MAC1_RX_SECTION_EMPTY_RX_SECTION_EMPTY 0
-#define BM_ENET_MAC1_RX_SECTION_EMPTY_RX_SECTION_EMPTY 0x000000FF
-#define BF_ENET_MAC1_RX_SECTION_EMPTY_RX_SECTION_EMPTY(v) \
- (((v) << 0) & BM_ENET_MAC1_RX_SECTION_EMPTY_RX_SECTION_EMPTY)
-
-#define HW_ENET_MAC1_RX_ALMOST_EMPTY (0x00004194)
-
-#define BP_ENET_MAC1_RX_ALMOST_EMPTY_RSRVD0 8
-#define BM_ENET_MAC1_RX_ALMOST_EMPTY_RSRVD0 0xFFFFFF00
-#define BF_ENET_MAC1_RX_ALMOST_EMPTY_RSRVD0(v) \
- (((v) << 8) & BM_ENET_MAC1_RX_ALMOST_EMPTY_RSRVD0)
-#define BP_ENET_MAC1_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY 0
-#define BM_ENET_MAC1_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY 0x000000FF
-#define BF_ENET_MAC1_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY(v) \
- (((v) << 0) & BM_ENET_MAC1_RX_ALMOST_EMPTY_RX_ALMOST_EMPTY)
-
-#define HW_ENET_MAC1_RX_ALMOST_FULL (0x00004198)
-
-#define BP_ENET_MAC1_RX_ALMOST_FULL_RSRVD0 8
-#define BM_ENET_MAC1_RX_ALMOST_FULL_RSRVD0 0xFFFFFF00
-#define BF_ENET_MAC1_RX_ALMOST_FULL_RSRVD0(v) \
- (((v) << 8) & BM_ENET_MAC1_RX_ALMOST_FULL_RSRVD0)
-#define BP_ENET_MAC1_RX_ALMOST_FULL_RX_ALMOST_FULL 0
-#define BM_ENET_MAC1_RX_ALMOST_FULL_RX_ALMOST_FULL 0x000000FF
-#define BF_ENET_MAC1_RX_ALMOST_FULL_RX_ALMOST_FULL(v) \
- (((v) << 0) & BM_ENET_MAC1_RX_ALMOST_FULL_RX_ALMOST_FULL)
-
-#define HW_ENET_MAC1_TX_SECTION_EMPTY (0x0000419c)
-
-#define BP_ENET_MAC1_TX_SECTION_EMPTY_RSRVD0 8
-#define BM_ENET_MAC1_TX_SECTION_EMPTY_RSRVD0 0xFFFFFF00
-#define BF_ENET_MAC1_TX_SECTION_EMPTY_RSRVD0(v) \
- (((v) << 8) & BM_ENET_MAC1_TX_SECTION_EMPTY_RSRVD0)
-#define BP_ENET_MAC1_TX_SECTION_EMPTY_TX_SECTION_EMPTY 0
-#define BM_ENET_MAC1_TX_SECTION_EMPTY_TX_SECTION_EMPTY 0x000000FF
-#define BF_ENET_MAC1_TX_SECTION_EMPTY_TX_SECTION_EMPTY(v) \
- (((v) << 0) & BM_ENET_MAC1_TX_SECTION_EMPTY_TX_SECTION_EMPTY)
-
-#define HW_ENET_MAC1_TX_ALMOST_EMPTY (0x000041a0)
-
-#define BP_ENET_MAC1_TX_ALMOST_EMPTY_RSRVD0 8
-#define BM_ENET_MAC1_TX_ALMOST_EMPTY_RSRVD0 0xFFFFFF00
-#define BF_ENET_MAC1_TX_ALMOST_EMPTY_RSRVD0(v) \
- (((v) << 8) & BM_ENET_MAC1_TX_ALMOST_EMPTY_RSRVD0)
-#define BP_ENET_MAC1_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY 0
-#define BM_ENET_MAC1_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY 0x000000FF
-#define BF_ENET_MAC1_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY(v) \
- (((v) << 0) & BM_ENET_MAC1_TX_ALMOST_EMPTY_TX_ALMOST_EMPTY)
-
-#define HW_ENET_MAC1_TX_ALMOST_FULL (0x000041a4)
-
-#define BP_ENET_MAC1_TX_ALMOST_FULL_RSRVD0 8
-#define BM_ENET_MAC1_TX_ALMOST_FULL_RSRVD0 0xFFFFFF00
-#define BF_ENET_MAC1_TX_ALMOST_FULL_RSRVD0(v) \
- (((v) << 8) & BM_ENET_MAC1_TX_ALMOST_FULL_RSRVD0)
-#define BP_ENET_MAC1_TX_ALMOST_FULL_TX_ALMOST_FULL 0
-#define BM_ENET_MAC1_TX_ALMOST_FULL_TX_ALMOST_FULL 0x000000FF
-#define BF_ENET_MAC1_TX_ALMOST_FULL_TX_ALMOST_FULL(v) \
- (((v) << 0) & BM_ENET_MAC1_TX_ALMOST_FULL_TX_ALMOST_FULL)
-
-#define HW_ENET_MAC1_TX_IPG_LENGTH (0x000041a8)
-
-#define BP_ENET_MAC1_TX_IPG_LENGTH_RSRVD0 5
-#define BM_ENET_MAC1_TX_IPG_LENGTH_RSRVD0 0xFFFFFFE0
-#define BF_ENET_MAC1_TX_IPG_LENGTH_RSRVD0(v) \
- (((v) << 5) & BM_ENET_MAC1_TX_IPG_LENGTH_RSRVD0)
-#define BP_ENET_MAC1_TX_IPG_LENGTH_TX_IPG_LENGTH 0
-#define BM_ENET_MAC1_TX_IPG_LENGTH_TX_IPG_LENGTH 0x0000001F
-#define BF_ENET_MAC1_TX_IPG_LENGTH_TX_IPG_LENGTH(v) \
- (((v) << 0) & BM_ENET_MAC1_TX_IPG_LENGTH_TX_IPG_LENGTH)
-
-#define HW_ENET_MAC1_TRUNC_FL (0x000041ac)
-
-#define BP_ENET_MAC1_TRUNC_FL_RSRVD0 14
-#define BM_ENET_MAC1_TRUNC_FL_RSRVD0 0xFFFFC000
-#define BF_ENET_MAC1_TRUNC_FL_RSRVD0(v) \
- (((v) << 14) & BM_ENET_MAC1_TRUNC_FL_RSRVD0)
-#define BP_ENET_MAC1_TRUNC_FL_TRUNC_FL 0
-#define BM_ENET_MAC1_TRUNC_FL_TRUNC_FL 0x00003FFF
-#define BF_ENET_MAC1_TRUNC_FL_TRUNC_FL(v) \
- (((v) << 0) & BM_ENET_MAC1_TRUNC_FL_TRUNC_FL)
-
-#define HW_ENET_MAC1_IPACCTXCONF (0x000041bc)
-
-#define BP_ENET_MAC1_IPACCTXCONF_RSRVD0 5
-#define BM_ENET_MAC1_IPACCTXCONF_RSRVD0 0xFFFFFFE0
-#define BF_ENET_MAC1_IPACCTXCONF_RSRVD0(v) \
- (((v) << 5) & BM_ENET_MAC1_IPACCTXCONF_RSRVD0)
-#define BM_ENET_MAC1_IPACCTXCONF_TX_PROTCHK_INS 0x00000010
-#define BM_ENET_MAC1_IPACCTXCONF_TX_IPCHK_INS 0x00000008
-#define BP_ENET_MAC1_IPACCTXCONF_RSRVD1 1
-#define BM_ENET_MAC1_IPACCTXCONF_RSRVD1 0x00000006
-#define BF_ENET_MAC1_IPACCTXCONF_RSRVD1(v) \
- (((v) << 1) & BM_ENET_MAC1_IPACCTXCONF_RSRVD1)
-#define BM_ENET_MAC1_IPACCTXCONF_SHIFT16 0x00000001
-
-#define HW_ENET_MAC1_IPACCRXCONF (0x000041c0)
-
-#define BP_ENET_MAC1_IPACCRXCONF_RSRVD0 8
-#define BM_ENET_MAC1_IPACCRXCONF_RSRVD0 0xFFFFFF00
-#define BF_ENET_MAC1_IPACCRXCONF_RSRVD0(v) \
- (((v) << 8) & BM_ENET_MAC1_IPACCRXCONF_RSRVD0)
-#define BM_ENET_MAC1_IPACCRXCONF_SHIFT16 0x00000080
-#define BM_ENET_MAC1_IPACCRXCONF_RX_LINEERR_DISC 0x00000040
-#define BP_ENET_MAC1_IPACCRXCONF_RSRVD1 3
-#define BM_ENET_MAC1_IPACCRXCONF_RSRVD1 0x00000038
-#define BF_ENET_MAC1_IPACCRXCONF_RSRVD1(v) \
- (((v) << 3) & BM_ENET_MAC1_IPACCRXCONF_RSRVD1)
-#define BM_ENET_MAC1_IPACCRXCONF_RX_PROTERR_DISCARD 0x00000004
-#define BM_ENET_MAC1_IPACCRXCONF_RX_IPERR_DISCARD 0x00000002
-#define BM_ENET_MAC1_IPACCRXCONF_RX_IP_PAD_REMOVE 0x00000001
-
-#define HW_ENET_MAC1_RMON_T_DROP (0x000041fc)
-
-#define BP_ENET_MAC1_RMON_T_DROP_RMON_T_DROP 0
-#define BM_ENET_MAC1_RMON_T_DROP_RMON_T_DROP 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_DROP_RMON_T_DROP(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_PACKETS (0x00004200)
-
-#define BP_ENET_MAC1_RMON_T_PACKETS_RMON_T_PACKETS 0
-#define BM_ENET_MAC1_RMON_T_PACKETS_RMON_T_PACKETS 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_PACKETS_RMON_T_PACKETS(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_BC_PKT (0x00004204)
-
-#define BP_ENET_MAC1_RMON_T_BC_PKT_RMON_T_BC_PKT 0
-#define BM_ENET_MAC1_RMON_T_BC_PKT_RMON_T_BC_PKT 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_BC_PKT_RMON_T_BC_PKT(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_MC_PKT (0x00004208)
-
-#define BP_ENET_MAC1_RMON_T_MC_PKT_RMON_T_MC_PKT 0
-#define BM_ENET_MAC1_RMON_T_MC_PKT_RMON_T_MC_PKT 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_MC_PKT_RMON_T_MC_PKT(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_CRC_ALIGN (0x0000420c)
-
-#define BP_ENET_MAC1_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN 0
-#define BM_ENET_MAC1_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_CRC_ALIGN_RMON_T_CRC_ALIGN(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_UNDERSIZE (0x00004210)
-
-#define BP_ENET_MAC1_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE 0
-#define BM_ENET_MAC1_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_UNDERSIZE_RMON_T_UNDERSIZE(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_OVERSIZE (0x00004214)
-
-#define BP_ENET_MAC1_RMON_T_OVERSIZE_RMON_T_OVERSIZE 0
-#define BM_ENET_MAC1_RMON_T_OVERSIZE_RMON_T_OVERSIZE 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_OVERSIZE_RMON_T_OVERSIZE(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_FRAG (0x00004218)
-
-#define BP_ENET_MAC1_RMON_T_FRAG_RMON_T_FRAG 0
-#define BM_ENET_MAC1_RMON_T_FRAG_RMON_T_FRAG 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_FRAG_RMON_T_FRAG(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_JAB (0x0000421c)
-
-#define BP_ENET_MAC1_RMON_T_JAB_RMON_T_JAB 0
-#define BM_ENET_MAC1_RMON_T_JAB_RMON_T_JAB 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_JAB_RMON_T_JAB(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_COL (0x00004220)
-
-#define BP_ENET_MAC1_RMON_T_COL_RMON_T_COL 0
-#define BM_ENET_MAC1_RMON_T_COL_RMON_T_COL 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_COL_RMON_T_COL(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_P64 (0x00004224)
-
-#define BP_ENET_MAC1_RMON_T_P64_RMON_T_P64 0
-#define BM_ENET_MAC1_RMON_T_P64_RMON_T_P64 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_P64_RMON_T_P64(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_P65TO127N (0x00004228)
-
-#define BP_ENET_MAC1_RMON_T_P65TO127N_RMON_T_P65TO127N 0
-#define BM_ENET_MAC1_RMON_T_P65TO127N_RMON_T_P65TO127N 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_P65TO127N_RMON_T_P65TO127N(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_P128TO255N (0x0000422c)
-
-#define BP_ENET_MAC1_RMON_T_P128TO255N_RMON_T_P128TO255N 0
-#define BM_ENET_MAC1_RMON_T_P128TO255N_RMON_T_P128TO255N 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_P128TO255N_RMON_T_P128TO255N(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_P256TO511 (0x00004230)
-
-#define BP_ENET_MAC1_RMON_T_P256TO511_RMON_T_P256TO511 0
-#define BM_ENET_MAC1_RMON_T_P256TO511_RMON_T_P256TO511 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_P256TO511_RMON_T_P256TO511(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_P512TO1023 (0x00004234)
-
-#define BP_ENET_MAC1_RMON_T_P512TO1023_RMON_T_P512TO1023 0
-#define BM_ENET_MAC1_RMON_T_P512TO1023_RMON_T_P512TO1023 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_P512TO1023_RMON_T_P512TO1023(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_P1024TO2047 (0x00004238)
-
-#define BP_ENET_MAC1_RMON_T_P1024TO2047_RMON_T_P1024TO2047 0
-#define BM_ENET_MAC1_RMON_T_P1024TO2047_RMON_T_P1024TO2047 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_P1024TO2047_RMON_T_P1024TO2047(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_P_GTE2048 (0x0000423c)
-
-#define BP_ENET_MAC1_RMON_T_P_GTE2048_RMON_T_P_GTE2048 0
-#define BM_ENET_MAC1_RMON_T_P_GTE2048_RMON_T_P_GTE2048 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_P_GTE2048_RMON_T_P_GTE2048(v) (v)
-
-#define HW_ENET_MAC1_RMON_T_OCTETS (0x00004240)
-
-#define BP_ENET_MAC1_RMON_T_OCTETS_RMON_T_OCTETS 0
-#define BM_ENET_MAC1_RMON_T_OCTETS_RMON_T_OCTETS 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_T_OCTETS_RMON_T_OCTETS(v) (v)
-
-#define HW_ENET_MAC1_IEEE_T_DROP (0x00004244)
-
-#define BP_ENET_MAC1_IEEE_T_DROP_IEEE_T_DROP 0
-#define BM_ENET_MAC1_IEEE_T_DROP_IEEE_T_DROP 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_T_DROP_IEEE_T_DROP(v) (v)
-
-#define HW_ENET_MAC1_IEEE_T_FRAME_OK (0x00004248)
-
-#define BP_ENET_MAC1_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK 0
-#define BM_ENET_MAC1_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_T_FRAME_OK_IEEE_T_FRAME_OK(v) (v)
-
-#define HW_ENET_MAC1_IEEE_T_1COL (0x0000424c)
-
-#define BP_ENET_MAC1_IEEE_T_1COL_IEEE_T_1COL 0
-#define BM_ENET_MAC1_IEEE_T_1COL_IEEE_T_1COL 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_T_1COL_IEEE_T_1COL(v) (v)
-
-#define HW_ENET_MAC1_IEEE_T_MCOL (0x00004250)
-
-#define BP_ENET_MAC1_IEEE_T_MCOL_IEEE_T_MCOL 0
-#define BM_ENET_MAC1_IEEE_T_MCOL_IEEE_T_MCOL 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_T_MCOL_IEEE_T_MCOL(v) (v)
-
-#define HW_ENET_MAC1_IEEE_T_DEF (0x00004254)
-
-#define BP_ENET_MAC1_IEEE_T_DEF_IEEE_T_DEF 0
-#define BM_ENET_MAC1_IEEE_T_DEF_IEEE_T_DEF 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_T_DEF_IEEE_T_DEF(v) (v)
-
-#define HW_ENET_MAC1_IEEE_T_LCOL (0x00004258)
-
-#define BP_ENET_MAC1_IEEE_T_LCOL_IEEE_T_LCOL 0
-#define BM_ENET_MAC1_IEEE_T_LCOL_IEEE_T_LCOL 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_T_LCOL_IEEE_T_LCOL(v) (v)
-
-#define HW_ENET_MAC1_IEEE_T_EXCOL (0x0000425c)
-
-#define BP_ENET_MAC1_IEEE_T_EXCOL_IEEE_T_EXCOL 0
-#define BM_ENET_MAC1_IEEE_T_EXCOL_IEEE_T_EXCOL 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_T_EXCOL_IEEE_T_EXCOL(v) (v)
-
-#define HW_ENET_MAC1_IEEE_T_MACERR (0x00004260)
-
-#define BP_ENET_MAC1_IEEE_T_MACERR_IEEE_T_MACERR 0
-#define BM_ENET_MAC1_IEEE_T_MACERR_IEEE_T_MACERR 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_T_MACERR_IEEE_T_MACERR(v) (v)
-
-#define HW_ENET_MAC1_IEEE_T_CSERR (0x00004264)
-
-#define BP_ENET_MAC1_IEEE_T_CSERR_IEEE_T_CSERR 0
-#define BM_ENET_MAC1_IEEE_T_CSERR_IEEE_T_CSERR 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_T_CSERR_IEEE_T_CSERR(v) (v)
-
-#define HW_ENET_MAC1_IEEE_T_SQE (0x00004268)
-
-#define BP_ENET_MAC1_IEEE_T_SQE_IEEE_T_SQE 0
-#define BM_ENET_MAC1_IEEE_T_SQE_IEEE_T_SQE 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_T_SQE_IEEE_T_SQE(v) (v)
-
-#define HW_ENET_MAC1_IEEE_T_FDXFC (0x0000426c)
-
-#define BP_ENET_MAC1_IEEE_T_FDXFC_IEEE_T_FDXFC 0
-#define BM_ENET_MAC1_IEEE_T_FDXFC_IEEE_T_FDXFC 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_T_FDXFC_IEEE_T_FDXFC(v) (v)
-
-#define HW_ENET_MAC1_IEEE_T_OCTETS_OK (0x00004270)
-
-#define BP_ENET_MAC1_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK 0
-#define BM_ENET_MAC1_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_T_OCTETS_OK_IEEE_T_OCTETS_OK(v) (v)
-
-#define HW_ENET_MAC1_RMON_R_PACKETS (0x00004280)
-
-#define BP_ENET_MAC1_RMON_R_PACKETS_RMON_R_PACKETS 0
-#define BM_ENET_MAC1_RMON_R_PACKETS_RMON_R_PACKETS 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_R_PACKETS_RMON_R_PACKETS(v) (v)
-
-#define HW_ENET_MAC1_RMON_R_BC_PKT (0x00004284)
-
-#define BP_ENET_MAC1_RMON_R_BC_PKT_RMON_R_BC_PKT 0
-#define BM_ENET_MAC1_RMON_R_BC_PKT_RMON_R_BC_PKT 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_R_BC_PKT_RMON_R_BC_PKT(v) (v)
-
-#define HW_ENET_MAC1_RMON_R_MC_PKT (0x00004288)
-
-#define BP_ENET_MAC1_RMON_R_MC_PKT_RMON_R_MC_PKT 0
-#define BM_ENET_MAC1_RMON_R_MC_PKT_RMON_R_MC_PKT 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_R_MC_PKT_RMON_R_MC_PKT(v) (v)
-
-#define HW_ENET_MAC1_RMON_R_CRC_ALIGN (0x0000428c)
-
-#define BP_ENET_MAC1_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN 0
-#define BM_ENET_MAC1_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_R_CRC_ALIGN_RMON_R_CRC_ALIGN(v) (v)
-
-#define HW_ENET_MAC1_RMON_R_UNDERSIZE (0x00004290)
-
-#define BP_ENET_MAC1_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE 0
-#define BM_ENET_MAC1_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_R_UNDERSIZE_RMON_R_UNDERSIZE(v) (v)
-
-#define HW_ENET_MAC1_RMON_R_OVERSIZE (0x00004294)
-
-#define BP_ENET_MAC1_RMON_R_OVERSIZE_RMON_R_OVERSIZE 0
-#define BM_ENET_MAC1_RMON_R_OVERSIZE_RMON_R_OVERSIZE 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_R_OVERSIZE_RMON_R_OVERSIZE(v) (v)
-
-#define HW_ENET_MAC1_RMON_R_FRAG (0x00004298)
-
-#define BP_ENET_MAC1_RMON_R_FRAG_RMON_R_FRAG 0
-#define BM_ENET_MAC1_RMON_R_FRAG_RMON_R_FRAG 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_R_FRAG_RMON_R_FRAG(v) (v)
-
-#define HW_ENET_MAC1_RMON_R_JAB (0x0000429c)
-
-#define BP_ENET_MAC1_RMON_R_JAB_RMON_R_JAB 0
-#define BM_ENET_MAC1_RMON_R_JAB_RMON_R_JAB 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_R_JAB_RMON_R_JAB(v) (v)
-
-#define HW_ENET_MAC1_RMON_R_P64 (0x000042a4)
-
-#define BP_ENET_MAC1_RMON_R_P64_RMON_R_P64 0
-#define BM_ENET_MAC1_RMON_R_P64_RMON_R_P64 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_R_P64_RMON_R_P64(v) (v)
-
-#define HW_ENET_MAC1_RMON_R_P65TO127 (0x000042a8)
-
-#define BP_ENET_MAC1_RMON_R_P65TO127_RMON_R_P65TO127 0
-#define BM_ENET_MAC1_RMON_R_P65TO127_RMON_R_P65TO127 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_R_P65TO127_RMON_R_P65TO127(v) (v)
-
-#define HW_ENET_MAC1_RMON_R_P128TO255 (0x000042ac)
-
-#define BP_ENET_MAC1_RMON_R_P128TO255_RMON_R_P128TO255 0
-#define BM_ENET_MAC1_RMON_R_P128TO255_RMON_R_P128TO255 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_R_P128TO255_RMON_R_P128TO255(v) (v)
-
-#define HW_ENET_MAC1_RMON_R_P256TO511 (0x000042b0)
-
-#define BP_ENET_MAC1_RMON_R_P256TO511_RMON_R_P256TO511 0
-#define BM_ENET_MAC1_RMON_R_P256TO511_RMON_R_P256TO511 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_R_P256TO511_RMON_R_P256TO511(v) (v)
-
-#define HW_ENET_MAC1_RMON_R_P512TO1023 (0x000042b4)
-
-#define BP_ENET_MAC1_RMON_R_P512TO1023_RMON_R_P512TO1023 0
-#define BM_ENET_MAC1_RMON_R_P512TO1023_RMON_R_P512TO1023 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_R_P512TO1023_RMON_R_P512TO1023(v) (v)
-
-#define HW_ENET_MAC1_RMON_R_P1024TO2047 (0x000042b8)
-
-#define BP_ENET_MAC1_RMON_R_P1024TO2047_RMON_R_P1024TO2047 0
-#define BM_ENET_MAC1_RMON_R_P1024TO2047_RMON_R_P1024TO2047 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_R_P1024TO2047_RMON_R_P1024TO2047(v) (v)
-
-#define HW_ENET_MAC1_RMON_R_P_GTE2048 (0x000042bc)
-
-#define BP_ENET_MAC1_RMON_R_P_GTE2048_RMON_R_P_GTE2048 0
-#define BM_ENET_MAC1_RMON_R_P_GTE2048_RMON_R_P_GTE2048 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_R_P_GTE2048_RMON_R_P_GTE2048(v) (v)
-
-#define HW_ENET_MAC1_RMON_R_OCTETS (0x000042c0)
-
-#define BP_ENET_MAC1_RMON_R_OCTETS_RMON_R_OCTETS 0
-#define BM_ENET_MAC1_RMON_R_OCTETS_RMON_R_OCTETS 0xFFFFFFFF
-#define BF_ENET_MAC1_RMON_R_OCTETS_RMON_R_OCTETS(v) (v)
-
-#define HW_ENET_MAC1_IEEE_R_DROP (0x000042c4)
-
-#define BP_ENET_MAC1_IEEE_R_DROP_IEEE_R_DROP 0
-#define BM_ENET_MAC1_IEEE_R_DROP_IEEE_R_DROP 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_R_DROP_IEEE_R_DROP(v) (v)
-
-#define HW_ENET_MAC1_IEEE_R_FRAME_OK (0x000042c8)
-
-#define BP_ENET_MAC1_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK 0
-#define BM_ENET_MAC1_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_R_FRAME_OK_IEEE_R_FRAME_OK(v) (v)
-
-#define HW_ENET_MAC1_IEEE_R_CRC (0x000042cc)
-
-#define BP_ENET_MAC1_IEEE_R_CRC_IEEE_R_CRC 0
-#define BM_ENET_MAC1_IEEE_R_CRC_IEEE_R_CRC 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_R_CRC_IEEE_R_CRC(v) (v)
-
-#define HW_ENET_MAC1_IEEE_R_ALIGN (0x000042d0)
-
-#define BP_ENET_MAC1_IEEE_R_ALIGN_IEEE_R_ALIGN 0
-#define BM_ENET_MAC1_IEEE_R_ALIGN_IEEE_R_ALIGN 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_R_ALIGN_IEEE_R_ALIGN(v) (v)
-
-#define HW_ENET_MAC1_IEEE_R_MACERR (0x000042d4)
-
-#define BP_ENET_MAC1_IEEE_R_MACERR_IEEE_R_MACERR 0
-#define BM_ENET_MAC1_IEEE_R_MACERR_IEEE_R_MACERR 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_R_MACERR_IEEE_R_MACERR(v) (v)
-
-#define HW_ENET_MAC1_IEEE_R_FDXFC (0x000042d8)
-
-#define BP_ENET_MAC1_IEEE_R_FDXFC_IEEE_R_FDXFC 0
-#define BM_ENET_MAC1_IEEE_R_FDXFC_IEEE_R_FDXFC 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_R_FDXFC_IEEE_R_FDXFC(v) (v)
-
-#define HW_ENET_MAC1_IEEE_R_OCTETS_OK (0x000042dc)
-
-#define BP_ENET_MAC1_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK 0
-#define BM_ENET_MAC1_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK 0xFFFFFFFF
-#define BF_ENET_MAC1_IEEE_R_OCTETS_OK_IEEE_R_OCTETS_OK(v) (v)
-
-#define HW_ENET_MAC1_ATIME_CTRL (0x000043fc)
-
-#define BP_ENET_MAC1_ATIME_CTRL_RSRVD0 14
-#define BM_ENET_MAC1_ATIME_CTRL_RSRVD0 0xFFFFC000
-#define BF_ENET_MAC1_ATIME_CTRL_RSRVD0(v) \
- (((v) << 14) & BM_ENET_MAC1_ATIME_CTRL_RSRVD0)
-#define BM_ENET_MAC1_ATIME_CTRL_FRC_SLAVE 0x00002000
-#define BM_ENET_MAC1_ATIME_CTRL_RSRVD1 0x00001000
-#define BM_ENET_MAC1_ATIME_CTRL_CAPTURE 0x00000800
-#define BM_ENET_MAC1_ATIME_CTRL_RSRVD2 0x00000400
-#define BM_ENET_MAC1_ATIME_CTRL_RESTART 0x00000200
-#define BM_ENET_MAC1_ATIME_CTRL_RSRVD3 0x00000100
-#define BM_ENET_MAC1_ATIME_CTRL_PIN_PERIOD_ENA 0x00000080
-#define BM_ENET_MAC1_ATIME_CTRL_RSRVD4 0x00000040
-#define BM_ENET_MAC1_ATIME_CTRL_EVT_PERIOD_RST 0x00000020
-#define BM_ENET_MAC1_ATIME_CTRL_EVT_PERIOD_ENA 0x00000010
-#define BM_ENET_MAC1_ATIME_CTRL_EVT_OFFSET_RST 0x00000008
-#define BM_ENET_MAC1_ATIME_CTRL_EVT_OFFSET_ENA 0x00000004
-#define BM_ENET_MAC1_ATIME_CTRL_ONE_SHOT 0x00000002
-#define BM_ENET_MAC1_ATIME_CTRL_ENABLE 0x00000001
-
-#define HW_ENET_MAC1_ATIME (0x00004400)
-
-#define BP_ENET_MAC1_ATIME_ATIME 0
-#define BM_ENET_MAC1_ATIME_ATIME 0xFFFFFFFF
-#define BF_ENET_MAC1_ATIME_ATIME(v) (v)
-
-#define HW_ENET_MAC1_ATIME_EVT_OFFSET (0x00004404)
-
-#define BP_ENET_MAC1_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET 0
-#define BM_ENET_MAC1_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET 0xFFFFFFFF
-#define BF_ENET_MAC1_ATIME_EVT_OFFSET_ATIME_EVT_OFFSET(v) (v)
-
-#define HW_ENET_MAC1_ATIME_EVT_PERIOD (0x00004408)
-
-#define BP_ENET_MAC1_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD 0
-#define BM_ENET_MAC1_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD 0xFFFFFFFF
-#define BF_ENET_MAC1_ATIME_EVT_PERIOD_ATIME_EVT_PERIOD(v) (v)
-
-#define HW_ENET_MAC1_ATIME_CORR (0x0000440c)
-
-#define BM_ENET_MAC1_ATIME_CORR_RSRVD0 0x80000000
-#define BP_ENET_MAC1_ATIME_CORR_ATIME_CORR 0
-#define BM_ENET_MAC1_ATIME_CORR_ATIME_CORR 0x7FFFFFFF
-#define BF_ENET_MAC1_ATIME_CORR_ATIME_CORR(v) \
- (((v) << 0) & BM_ENET_MAC1_ATIME_CORR_ATIME_CORR)
-
-#define HW_ENET_MAC1_ATIME_INC (0x00004410)
-
-#define BP_ENET_MAC1_ATIME_INC_RSRVD0 15
-#define BM_ENET_MAC1_ATIME_INC_RSRVD0 0xFFFF8000
-#define BF_ENET_MAC1_ATIME_INC_RSRVD0(v) \
- (((v) << 15) & BM_ENET_MAC1_ATIME_INC_RSRVD0)
-#define BP_ENET_MAC1_ATIME_INC_ATIME_INC_CORR 8
-#define BM_ENET_MAC1_ATIME_INC_ATIME_INC_CORR 0x00007F00
-#define BF_ENET_MAC1_ATIME_INC_ATIME_INC_CORR(v) \
- (((v) << 8) & BM_ENET_MAC1_ATIME_INC_ATIME_INC_CORR)
-#define BM_ENET_MAC1_ATIME_INC_RSRVD1 0x00000080
-#define BP_ENET_MAC1_ATIME_INC_ATIME_INC 0
-#define BM_ENET_MAC1_ATIME_INC_ATIME_INC 0x0000007F
-#define BF_ENET_MAC1_ATIME_INC_ATIME_INC(v) \
- (((v) << 0) & BM_ENET_MAC1_ATIME_INC_ATIME_INC)
-
-#define HW_ENET_MAC1_TS_TIMESTAMP (0x00004414)
-
-#define BP_ENET_MAC1_TS_TIMESTAMP_TS_TIMESTAMP 0
-#define BM_ENET_MAC1_TS_TIMESTAMP_TS_TIMESTAMP 0xFFFFFFFF
-#define BF_ENET_MAC1_TS_TIMESTAMP_TS_TIMESTAMP(v) (v)
-
-#define HW_ENET_MAC1_SMAC_0_0 (0x000044fc)
-
-#define BP_ENET_MAC1_SMAC_0_0_SMAC_0_0 0
-#define BM_ENET_MAC1_SMAC_0_0_SMAC_0_0 0xFFFFFFFF
-#define BF_ENET_MAC1_SMAC_0_0_SMAC_0_0(v) (v)
-
-#define HW_ENET_MAC1_SMAC_0_1 (0x00004500)
-
-#define BP_ENET_MAC1_SMAC_0_1_SMAC_0_1 0
-#define BM_ENET_MAC1_SMAC_0_1_SMAC_0_1 0xFFFFFFFF
-#define BF_ENET_MAC1_SMAC_0_1_SMAC_0_1(v) (v)
-
-#define HW_ENET_MAC1_SMAC_1_0 (0x00004504)
-
-#define BP_ENET_MAC1_SMAC_1_0_SMAC_1_0 0
-#define BM_ENET_MAC1_SMAC_1_0_SMAC_1_0 0xFFFFFFFF
-#define BF_ENET_MAC1_SMAC_1_0_SMAC_1_0(v) (v)
-
-#define HW_ENET_MAC1_SMAC_1_1 (0x00004508)
-
-#define BP_ENET_MAC1_SMAC_1_1_SMAC_1_1 0
-#define BM_ENET_MAC1_SMAC_1_1_SMAC_1_1 0xFFFFFFFF
-#define BF_ENET_MAC1_SMAC_1_1_SMAC_1_1(v) (v)
-
-#define HW_ENET_MAC1_SMAC_2_0 (0x0000450c)
-
-#define BP_ENET_MAC1_SMAC_2_0_SMAC_2_0 0
-#define BM_ENET_MAC1_SMAC_2_0_SMAC_2_0 0xFFFFFFFF
-#define BF_ENET_MAC1_SMAC_2_0_SMAC_2_0(v) (v)
-
-#define HW_ENET_MAC1_SMAC_2_1 (0x00004510)
-
-#define BP_ENET_MAC1_SMAC_2_1_SMAC_2_1 0
-#define BM_ENET_MAC1_SMAC_2_1_SMAC_2_1 0xFFFFFFFF
-#define BF_ENET_MAC1_SMAC_2_1_SMAC_2_1(v) (v)
-
-#define HW_ENET_MAC1_SMAC_3_0 (0x00004514)
-
-#define BP_ENET_MAC1_SMAC_3_0_SMAC_3_0 0
-#define BM_ENET_MAC1_SMAC_3_0_SMAC_3_0 0xFFFFFFFF
-#define BF_ENET_MAC1_SMAC_3_0_SMAC_3_0(v) (v)
-
-#define HW_ENET_MAC1_SMAC_3_1 (0x00004518)
-
-#define BP_ENET_MAC1_SMAC_3_1_SMAC_3_1 0
-#define BM_ENET_MAC1_SMAC_3_1_SMAC_3_1 0xFFFFFFFF
-#define BF_ENET_MAC1_SMAC_3_1_SMAC_3_1(v) (v)
-
-#define HW_ENET_MAC1_COMP_REG_0 (0x000045fc)
-
-#define BP_ENET_MAC1_COMP_REG_0_COMP_REG_0 0
-#define BM_ENET_MAC1_COMP_REG_0_COMP_REG_0 0xFFFFFFFF
-#define BF_ENET_MAC1_COMP_REG_0_COMP_REG_0(v) (v)
-
-#define HW_ENET_MAC1_COMP_REG_1 (0x00004600)
-
-#define BP_ENET_MAC1_COMP_REG_1_COMP_REG_1 0
-#define BM_ENET_MAC1_COMP_REG_1_COMP_REG_1 0xFFFFFFFF
-#define BF_ENET_MAC1_COMP_REG_1_COMP_REG_1(v) (v)
-
-#define HW_ENET_MAC1_COMP_REG_2 (0x00004604)
-
-#define BP_ENET_MAC1_COMP_REG_2_COMP_REG_2 0
-#define BM_ENET_MAC1_COMP_REG_2_COMP_REG_2 0xFFFFFFFF
-#define BF_ENET_MAC1_COMP_REG_2_COMP_REG_2(v) (v)
-
-#define HW_ENET_MAC1_COMP_REG_3 (0x00004608)
-
-#define BP_ENET_MAC1_COMP_REG_3_COMP_REG_3 0
-#define BM_ENET_MAC1_COMP_REG_3_COMP_REG_3 0xFFFFFFFF
-#define BF_ENET_MAC1_COMP_REG_3_COMP_REG_3(v) (v)
-
-#define HW_ENET_MAC1_CAPT_REG_0 (0x0000463c)
-
-#define BP_ENET_MAC1_CAPT_REG_0_CAPT_REG_0 0
-#define BM_ENET_MAC1_CAPT_REG_0_CAPT_REG_0 0xFFFFFFFF
-#define BF_ENET_MAC1_CAPT_REG_0_CAPT_REG_0(v) (v)
-
-#define HW_ENET_MAC1_CAPT_REG_1 (0x00004640)
-
-#define BP_ENET_MAC1_CAPT_REG_1_CAPT_REG_1 0
-#define BM_ENET_MAC1_CAPT_REG_1_CAPT_REG_1 0xFFFFFFFF
-#define BF_ENET_MAC1_CAPT_REG_1_CAPT_REG_1(v) (v)
-
-#define HW_ENET_MAC1_CAPT_REG_2 (0x00004644)
-
-#define BP_ENET_MAC1_CAPT_REG_2_CAPT_REG_2 0
-#define BM_ENET_MAC1_CAPT_REG_2_CAPT_REG_2 0xFFFFFFFF
-#define BF_ENET_MAC1_CAPT_REG_2_CAPT_REG_2(v) (v)
-
-#define HW_ENET_MAC1_CAPT_REG_3 (0x00004648)
-
-#define BP_ENET_MAC1_CAPT_REG_3_CAPT_REG_3 0
-#define BM_ENET_MAC1_CAPT_REG_3_CAPT_REG_3 0xFFFFFFFF
-#define BF_ENET_MAC1_CAPT_REG_3_CAPT_REG_3(v) (v)
-
-#define HW_ENET_MAC1_CCB_INT (0x0000467c)
-
-#define BP_ENET_MAC1_CCB_INT_RSRVD0 20
-#define BM_ENET_MAC1_CCB_INT_RSRVD0 0xFFF00000
-#define BF_ENET_MAC1_CCB_INT_RSRVD0(v) \
- (((v) << 20) & BM_ENET_MAC1_CCB_INT_RSRVD0)
-#define BM_ENET_MAC1_CCB_INT_COMPARE3 0x00080000
-#define BM_ENET_MAC1_CCB_INT_COMPARE2 0x00040000
-#define BM_ENET_MAC1_CCB_INT_COMPARE1 0x00020000
-#define BM_ENET_MAC1_CCB_INT_COMPARE0 0x00010000
-#define BP_ENET_MAC1_CCB_INT_RSRVD1 4
-#define BM_ENET_MAC1_CCB_INT_RSRVD1 0x0000FFF0
-#define BF_ENET_MAC1_CCB_INT_RSRVD1(v) \
- (((v) << 4) & BM_ENET_MAC1_CCB_INT_RSRVD1)
-#define BM_ENET_MAC1_CCB_INT_CAPTURE3 0x00000008
-#define BM_ENET_MAC1_CCB_INT_CAPTURE2 0x00000004
-#define BM_ENET_MAC1_CCB_INT_CAPTURE1 0x00000002
-#define BM_ENET_MAC1_CCB_INT_CAPTURE0 0x00000001
-
-#define HW_ENET_MAC1_CCB_INT_MASK (0x00004680)
-
-#define BP_ENET_MAC1_CCB_INT_MASK_RSRVD0 20
-#define BM_ENET_MAC1_CCB_INT_MASK_RSRVD0 0xFFF00000
-#define BF_ENET_MAC1_CCB_INT_MASK_RSRVD0(v) \
- (((v) << 20) & BM_ENET_MAC1_CCB_INT_MASK_RSRVD0)
-#define BM_ENET_MAC1_CCB_INT_MASK_COMPARE3 0x00080000
-#define BM_ENET_MAC1_CCB_INT_MASK_COMPARE2 0x00040000
-#define BM_ENET_MAC1_CCB_INT_MASK_COMPARE1 0x00020000
-#define BM_ENET_MAC1_CCB_INT_MASK_COMPARE0 0x00010000
-#define BP_ENET_MAC1_CCB_INT_MASK_RSRVD1 4
-#define BM_ENET_MAC1_CCB_INT_MASK_RSRVD1 0x0000FFF0
-#define BF_ENET_MAC1_CCB_INT_MASK_RSRVD1(v) \
- (((v) << 4) & BM_ENET_MAC1_CCB_INT_MASK_RSRVD1)
-#define BM_ENET_MAC1_CCB_INT_MASK_CAPTURE3 0x00000008
-#define BM_ENET_MAC1_CCB_INT_MASK_CAPTURE2 0x00000004
-#define BM_ENET_MAC1_CCB_INT_MASK_CAPTURE1 0x00000002
-#define BM_ENET_MAC1_CCB_INT_MASK_CAPTURE0 0x00000001
-
-#define HW_ENET_SWI_REVISION (0x00007ffc)
-
-#define BP_ENET_SWI_REVISION_CUSTOMER_REVISION 16
-#define BM_ENET_SWI_REVISION_CUSTOMER_REVISION 0xFFFF0000
-#define BF_ENET_SWI_REVISION_CUSTOMER_REVISION(v) \
- (((v) << 16) & BM_ENET_SWI_REVISION_CUSTOMER_REVISION)
-#define BP_ENET_SWI_REVISION_CORE_REVISION 0
-#define BM_ENET_SWI_REVISION_CORE_REVISION 0x0000FFFF
-#define BF_ENET_SWI_REVISION_CORE_REVISION(v) \
- (((v) << 0) & BM_ENET_SWI_REVISION_CORE_REVISION)
-
-#define HW_ENET_SWI_SCRATCH (0x00008000)
-
-#define BP_ENET_SWI_SCRATCH_COMPARE0 0
-#define BM_ENET_SWI_SCRATCH_COMPARE0 0xFFFFFFFF
-#define BF_ENET_SWI_SCRATCH_COMPARE0(v) (v)
-
-#define HW_ENET_SWI_PORT_ENA (0x00008004)
-
-#define BP_ENET_SWI_PORT_ENA_RSRVD1 19
-#define BM_ENET_SWI_PORT_ENA_RSRVD1 0xFFF80000
-#define BF_ENET_SWI_PORT_ENA_RSRVD1(v) \
- (((v) << 19) & BM_ENET_SWI_PORT_ENA_RSRVD1)
-#define BM_ENET_SWI_PORT_ENA_ENA_RECEIVE_2 0x00040000
-#define BM_ENET_SWI_PORT_ENA_ENA_RECEIVE_1 0x00020000
-#define BM_ENET_SWI_PORT_ENA_ENA_RECEIVE_0 0x00010000
-#define BP_ENET_SWI_PORT_ENA_RSRVD0 3
-#define BM_ENET_SWI_PORT_ENA_RSRVD0 0x0000FFF8
-#define BF_ENET_SWI_PORT_ENA_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_PORT_ENA_RSRVD0)
-#define BM_ENET_SWI_PORT_ENA_ENA_TRANSMIT_2 0x00000004
-#define BM_ENET_SWI_PORT_ENA_ENA_TRANSMIT_1 0x00000002
-#define BM_ENET_SWI_PORT_ENA_ENA_TRANSMIT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_VERIFY (0x0000800c)
-
-#define BP_ENET_SWI_VLAN_VERIFY_RSRVD1 19
-#define BM_ENET_SWI_VLAN_VERIFY_RSRVD1 0xFFF80000
-#define BF_ENET_SWI_VLAN_VERIFY_RSRVD1(v) \
- (((v) << 19) & BM_ENET_SWI_VLAN_VERIFY_RSRVD1)
-#define BM_ENET_SWI_VLAN_VERIFY_DISCARD_P2 0x00040000
-#define BM_ENET_SWI_VLAN_VERIFY_DISCARD_P1 0x00020000
-#define BM_ENET_SWI_VLAN_VERIFY_DISCARD_P0 0x00010000
-#define BP_ENET_SWI_VLAN_VERIFY_RSRVD0 3
-#define BM_ENET_SWI_VLAN_VERIFY_RSRVD0 0x0000FFF8
-#define BF_ENET_SWI_VLAN_VERIFY_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_VERIFY_RSRVD0)
-#define BM_ENET_SWI_VLAN_VERIFY_VLAN_VERIFY_2 0x00000004
-#define BM_ENET_SWI_VLAN_VERIFY_VLAN_VERIFY_1 0x00000002
-#define BM_ENET_SWI_VLAN_VERIFY_VLAN_VERIFY_0 0x00000001
-
-#define HW_ENET_SWI_BCAST_DEFAULT_MASK (0x00008010)
-
-#define BP_ENET_SWI_BCAST_DEFAULT_MASK_RSRVD0 3
-#define BM_ENET_SWI_BCAST_DEFAULT_MASK_RSRVD0 0xFFFFFFF8
-#define BF_ENET_SWI_BCAST_DEFAULT_MASK_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_BCAST_DEFAULT_MASK_RSRVD0)
-#define BM_ENET_SWI_BCAST_DEFAULT_MASK_BCAST_DEFAULT_MASK_2 0x00000004
-#define BM_ENET_SWI_BCAST_DEFAULT_MASK_BCAST_DEFAULT_MASK_1 0x00000002
-#define BM_ENET_SWI_BCAST_DEFAULT_MASK_BCAST_DEFAULT_MASK_0 0x00000001
-
-#define HW_ENET_SWI_MCAST_DEFAULT_MASK (0x00008014)
-
-#define BP_ENET_SWI_MCAST_DEFAULT_MASK_RSRVD0 3
-#define BM_ENET_SWI_MCAST_DEFAULT_MASK_RSRVD0 0xFFFFFFF8
-#define BF_ENET_SWI_MCAST_DEFAULT_MASK_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_MCAST_DEFAULT_MASK_RSRVD0)
-#define BM_ENET_SWI_MCAST_DEFAULT_MASK_MCAST_DEFAULT_MASK_2 0x00000004
-#define BM_ENET_SWI_MCAST_DEFAULT_MASK_MCAST_DEFAULT_MASK_1 0x00000002
-#define BM_ENET_SWI_MCAST_DEFAULT_MASK_MCAST_DEFAULT_MASK_0 0x00000001
-
-#define HW_ENET_SWI_INPUT_LEARN_BLOCK (0x00008018)
-
-#define BP_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD1 19
-#define BM_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD1 0xFFF80000
-#define BF_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD1(v) \
- (((v) << 19) & BM_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD1)
-#define BM_ENET_SWI_INPUT_LEARN_BLOCK_LEARNING_DIS_P2 0x00040000
-#define BM_ENET_SWI_INPUT_LEARN_BLOCK_LEARNING_DI_P1 0x00020000
-#define BM_ENET_SWI_INPUT_LEARN_BLOCK_LEARNING_DI_P0 0x00010000
-#define BP_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD0 3
-#define BM_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD0 0x0000FFF8
-#define BF_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_INPUT_LEARN_BLOCK_RSRVD0)
-#define BM_ENET_SWI_INPUT_LEARN_BLOCK_BLOCKING_ENA_P2 0x00000004
-#define BM_ENET_SWI_INPUT_LEARN_BLOCK_BLOCKING_ENA_P1 0x00000002
-#define BM_ENET_SWI_INPUT_LEARN_BLOCK_BLOCKING_ENA_P0 0x00000001
-
-#define HW_ENET_SWI_MGMT_CONFIG (0x0000801c)
-
-#define BP_ENET_SWI_MGMT_CONFIG_RSRVD2 19
-#define BM_ENET_SWI_MGMT_CONFIG_RSRVD2 0xFFF80000
-#define BF_ENET_SWI_MGMT_CONFIG_RSRVD2(v) \
- (((v) << 19) & BM_ENET_SWI_MGMT_CONFIG_RSRVD2)
-#define BP_ENET_SWI_MGMT_CONFIG_PORTMASK 16
-#define BM_ENET_SWI_MGMT_CONFIG_PORTMASK 0x00070000
-#define BF_ENET_SWI_MGMT_CONFIG_PORTMASK(v) \
- (((v) << 16) & BM_ENET_SWI_MGMT_CONFIG_PORTMASK)
-#define BP_ENET_SWI_MGMT_CONFIG_PRIORITY 13
-#define BM_ENET_SWI_MGMT_CONFIG_PRIORITY 0x0000E000
-#define BF_ENET_SWI_MGMT_CONFIG_PRIORITY(v) \
- (((v) << 13) & BM_ENET_SWI_MGMT_CONFIG_PRIORITY)
-#define BP_ENET_SWI_MGMT_CONFIG_RSRVD1 8
-#define BM_ENET_SWI_MGMT_CONFIG_RSRVD1 0x00001F00
-#define BF_ENET_SWI_MGMT_CONFIG_RSRVD1(v) \
- (((v) << 8) & BM_ENET_SWI_MGMT_CONFIG_RSRVD1)
-#define BM_ENET_SWI_MGMT_CONFIG_DISCARD 0x00000080
-#define BM_ENET_SWI_MGMT_CONFIG_ENABLE 0x00000040
-#define BM_ENET_SWI_MGMT_CONFIG_MESSAGE_TRANSMITTED 0x00000020
-#define BM_ENET_SWI_MGMT_CONFIG_RSRVD0 0x00000010
-#define BP_ENET_SWI_MGMT_CONFIG_PORT 0
-#define BM_ENET_SWI_MGMT_CONFIG_PORT 0x0000000F
-#define BF_ENET_SWI_MGMT_CONFIG_PORT(v) \
- (((v) << 0) & BM_ENET_SWI_MGMT_CONFIG_PORT)
-
-#define HW_ENET_SWI_MODE_CONFIG (0x00008020)
-
-#define BM_ENET_SWI_MODE_CONFIG_STATSRESET 0x80000000
-#define BP_ENET_SWI_MODE_CONFIG_RSRVD1 10
-#define BM_ENET_SWI_MODE_CONFIG_RSRVD1 0x7FFFFC00
-#define BF_ENET_SWI_MODE_CONFIG_RSRVD1(v) \
- (((v) << 10) & BM_ENET_SWI_MODE_CONFIG_RSRVD1)
-#define BM_ENET_SWI_MODE_CONFIG_P0BUF_CUT_THROUGH 0x00000200
-#define BM_ENET_SWI_MODE_CONFIG_CRC_TRANSPARENT 0x00000100
-#define BM_ENET_SWI_MODE_CONFIG_STOP_EN 0x00000080
-#define BP_ENET_SWI_MODE_CONFIG_RSRVD0 2
-#define BM_ENET_SWI_MODE_CONFIG_RSRVD0 0x0000007C
-#define BF_ENET_SWI_MODE_CONFIG_RSRVD0(v) \
- (((v) << 2) & BM_ENET_SWI_MODE_CONFIG_RSRVD0)
-#define BM_ENET_SWI_MODE_CONFIG_SWITCH_EN 0x00000002
-#define BM_ENET_SWI_MODE_CONFIG_SWITCH_RESET 0x00000001
-
-#define HW_ENET_SWI_VLAN_IN_MODE (0x00008024)
-
-#define BP_ENET_SWI_VLAN_IN_MODE_RSRVD0 6
-#define BM_ENET_SWI_VLAN_IN_MODE_RSRVD0 0xFFFFFFC0
-#define BF_ENET_SWI_VLAN_IN_MODE_RSRVD0(v) \
- (((v) << 6) & BM_ENET_SWI_VLAN_IN_MODE_RSRVD0)
-#define BP_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_2 4
-#define BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_2 0x00000030
-#define BF_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_2(v) \
- (((v) << 4) & BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_2)
-#define BP_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_1 2
-#define BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_1 0x0000000C
-#define BF_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_1(v) \
- (((v) << 2) & BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_1)
-#define BP_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_0 0
-#define BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_0 0x00000003
-#define BF_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_0(v) \
- (((v) << 0) & BM_ENET_SWI_VLAN_IN_MODE_VLAN_IN_MODE_0)
-
-#define HW_ENET_SWI_VLAN_OUT_MODE (0x00008028)
-
-#define BP_ENET_SWI_VLAN_OUT_MODE_RSRVD0 6
-#define BM_ENET_SWI_VLAN_OUT_MODE_RSRVD0 0xFFFFFFC0
-#define BF_ENET_SWI_VLAN_OUT_MODE_RSRVD0(v) \
- (((v) << 6) & BM_ENET_SWI_VLAN_OUT_MODE_RSRVD0)
-#define BP_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_2 4
-#define BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_2 0x00000030
-#define BF_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_2(v) \
- (((v) << 4) & BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_2)
-#define BP_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_1 2
-#define BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_1 0x0000000C
-#define BF_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_1(v) \
- (((v) << 2) & BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_1)
-#define BP_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_0 0
-#define BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_0 0x00000003
-#define BF_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_0(v) \
- (((v) << 0) & BM_ENET_SWI_VLAN_OUT_MODE_VLAN_OUT_MODE_0)
-
-#define HW_ENET_SWI_VLAN_IN_MODE_ENA (0x0000802c)
-
-#define BP_ENET_SWI_VLAN_IN_MODE_ENA_RSRVD0 3
-#define BM_ENET_SWI_VLAN_IN_MODE_ENA_RSRVD0 0xFFFFFFF8
-#define BF_ENET_SWI_VLAN_IN_MODE_ENA_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_IN_MODE_ENA_RSRVD0)
-#define BM_ENET_SWI_VLAN_IN_MODE_ENA_VLAN_IN_MODE_ENA_2 0x00000004
-#define BM_ENET_SWI_VLAN_IN_MODE_ENA_VLAN_IN_MODE_ENA_1 0x00000002
-#define BM_ENET_SWI_VLAN_IN_MODE_ENA_VLAN_IN_MODE_ENA_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_TAG_ID (0x00008030)
-
-#define BP_ENET_SWI_VLAN_TAG_ID_RSRVD0 16
-#define BM_ENET_SWI_VLAN_TAG_ID_RSRVD0 0xFFFF0000
-#define BF_ENET_SWI_VLAN_TAG_ID_RSRVD0(v) \
- (((v) << 16) & BM_ENET_SWI_VLAN_TAG_ID_RSRVD0)
-#define BP_ENET_SWI_VLAN_TAG_ID_SWI_VLAN_TAG_ID 0
-#define BM_ENET_SWI_VLAN_TAG_ID_SWI_VLAN_TAG_ID 0x0000FFFF
-#define BF_ENET_SWI_VLAN_TAG_ID_SWI_VLAN_TAG_ID(v) \
- (((v) << 0) & BM_ENET_SWI_VLAN_TAG_ID_SWI_VLAN_TAG_ID)
-
-#define HW_ENET_SWI_MIRROR_CONTROL (0x0000803c)
-
-#define BP_ENET_SWI_MIRROR_CONTROL_RSRVD0 11
-#define BM_ENET_SWI_MIRROR_CONTROL_RSRVD0 0xFFFFF800
-#define BF_ENET_SWI_MIRROR_CONTROL_RSRVD0(v) \
- (((v) << 11) & BM_ENET_SWI_MIRROR_CONTROL_RSRVD0)
-#define BM_ENET_SWI_MIRROR_CONTROL_EG_DA_MATCH 0x00000400
-#define BM_ENET_SWI_MIRROR_CONTROL_EG_SA_MATCH 0x00000200
-#define BM_ENET_SWI_MIRROR_CONTROL_ING_DA_MATCH 0x00000100
-#define BM_ENET_SWI_MIRROR_CONTROL_ING_SA_MATCH 0x00000080
-#define BM_ENET_SWI_MIRROR_CONTROL_EG_MAP_ENABLE 0x00000040
-#define BM_ENET_SWI_MIRROR_CONTROL_ING_MAP_ENABLE 0x00000020
-#define BM_ENET_SWI_MIRROR_CONTROL_MIRROR_ENABLE 0x00000010
-#define BP_ENET_SWI_MIRROR_CONTROL_PORTX 0
-#define BM_ENET_SWI_MIRROR_CONTROL_PORTX 0x0000000F
-#define BF_ENET_SWI_MIRROR_CONTROL_PORTX(v) \
- (((v) << 0) & BM_ENET_SWI_MIRROR_CONTROL_PORTX)
-
-#define HW_ENET_SWI_MIRROR_EG_MAP (0x00008040)
-
-#define BP_ENET_SWI_MIRROR_EG_MAP_RSRVD0 3
-#define BM_ENET_SWI_MIRROR_EG_MAP_RSRVD0 0xFFFFFFF8
-#define BF_ENET_SWI_MIRROR_EG_MAP_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_MIRROR_EG_MAP_RSRVD0)
-#define BM_ENET_SWI_MIRROR_EG_MAP_MIRROR_EG_MAP_2 0x00000004
-#define BM_ENET_SWI_MIRROR_EG_MAP_MIRROR_EG_MAP_1 0x00000002
-#define BM_ENET_SWI_MIRROR_EG_MAP_MIRROR_EG_MAP_0 0x00000001
-
-#define HW_ENET_SWI_MIRROR_ING_MAP (0x00008044)
-
-#define BP_ENET_SWI_MIRROR_ING_MAP_RSRVD0 3
-#define BM_ENET_SWI_MIRROR_ING_MAP_RSRVD0 0xFFFFFFF8
-#define BF_ENET_SWI_MIRROR_ING_MAP_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_MIRROR_ING_MAP_RSRVD0)
-#define BM_ENET_SWI_MIRROR_ING_MAP_MIRROR_ING_MAP_2 0x00000004
-#define BM_ENET_SWI_MIRROR_ING_MAP_MIRROR_ING_MAP_1 0x00000002
-#define BM_ENET_SWI_MIRROR_ING_MAP_MIRROR_ING_MAP_0 0x00000001
-
-#define HW_ENET_SWI_MIRROR_ISRC_0 (0x00008048)
-
-#define BP_ENET_SWI_MIRROR_ISRC_0_MIRROR_ISRC_0 0
-#define BM_ENET_SWI_MIRROR_ISRC_0_MIRROR_ISRC_0 0xFFFFFFFF
-#define BF_ENET_SWI_MIRROR_ISRC_0_MIRROR_ISRC_0(v) (v)
-
-#define HW_ENET_SWI_MIRROR_ISRC_1 (0x0000804c)
-
-#define BP_ENET_SWI_MIRROR_ISRC_1_RSRVD0 16
-#define BM_ENET_SWI_MIRROR_ISRC_1_RSRVD0 0xFFFF0000
-#define BF_ENET_SWI_MIRROR_ISRC_1_RSRVD0(v) \
- (((v) << 16) & BM_ENET_SWI_MIRROR_ISRC_1_RSRVD0)
-#define BP_ENET_SWI_MIRROR_ISRC_1_MIRROR_ISRC_1 0
-#define BM_ENET_SWI_MIRROR_ISRC_1_MIRROR_ISRC_1 0x0000FFFF
-#define BF_ENET_SWI_MIRROR_ISRC_1_MIRROR_ISRC_1(v) \
- (((v) << 0) & BM_ENET_SWI_MIRROR_ISRC_1_MIRROR_ISRC_1)
-
-#define HW_ENET_SWI_MIRROR_IDST_0 (0x00008050)
-
-#define BP_ENET_SWI_MIRROR_IDST_0_MIRROR_IDST_0 0
-#define BM_ENET_SWI_MIRROR_IDST_0_MIRROR_IDST_0 0xFFFFFFFF
-#define BF_ENET_SWI_MIRROR_IDST_0_MIRROR_IDST_0(v) (v)
-
-#define HW_ENET_SWI_MIRROR_IDST_1 (0x00008054)
-
-#define BP_ENET_SWI_MIRROR_IDST_1_RSRVD0 16
-#define BM_ENET_SWI_MIRROR_IDST_1_RSRVD0 0xFFFF0000
-#define BF_ENET_SWI_MIRROR_IDST_1_RSRVD0(v) \
- (((v) << 16) & BM_ENET_SWI_MIRROR_IDST_1_RSRVD0)
-#define BP_ENET_SWI_MIRROR_IDST_1_MIRROR_IDST_1 0
-#define BM_ENET_SWI_MIRROR_IDST_1_MIRROR_IDST_1 0x0000FFFF
-#define BF_ENET_SWI_MIRROR_IDST_1_MIRROR_IDST_1(v) \
- (((v) << 0) & BM_ENET_SWI_MIRROR_IDST_1_MIRROR_IDST_1)
-
-#define HW_ENET_SWI_MIRROR_ESRC_0 (0x00008058)
-
-#define BP_ENET_SWI_MIRROR_ESRC_0_MIRROR_ESRC_0 0
-#define BM_ENET_SWI_MIRROR_ESRC_0_MIRROR_ESRC_0 0xFFFFFFFF
-#define BF_ENET_SWI_MIRROR_ESRC_0_MIRROR_ESRC_0(v) (v)
-
-#define HW_ENET_SWI_MIRROR_ESRC_1 (0x0000805c)
-
-#define BP_ENET_SWI_MIRROR_ESRC_1_RSRVD0 16
-#define BM_ENET_SWI_MIRROR_ESRC_1_RSRVD0 0xFFFF0000
-#define BF_ENET_SWI_MIRROR_ESRC_1_RSRVD0(v) \
- (((v) << 16) & BM_ENET_SWI_MIRROR_ESRC_1_RSRVD0)
-#define BP_ENET_SWI_MIRROR_ESRC_1_MIRROR_ESRC_1 0
-#define BM_ENET_SWI_MIRROR_ESRC_1_MIRROR_ESRC_1 0x0000FFFF
-#define BF_ENET_SWI_MIRROR_ESRC_1_MIRROR_ESRC_1(v) \
- (((v) << 0) & BM_ENET_SWI_MIRROR_ESRC_1_MIRROR_ESRC_1)
-
-#define HW_ENET_SWI_MIRROR_EDST_0 (0x00008060)
-
-#define BP_ENET_SWI_MIRROR_EDST_0_MIRROR_ESRC_0 0
-#define BM_ENET_SWI_MIRROR_EDST_0_MIRROR_ESRC_0 0xFFFFFFFF
-#define BF_ENET_SWI_MIRROR_EDST_0_MIRROR_ESRC_0(v) (v)
-
-#define HW_ENET_SWI_MIRROR_EDST_1 (0x00008064)
-
-#define BP_ENET_SWI_MIRROR_EDST_1_RSRVD0 16
-#define BM_ENET_SWI_MIRROR_EDST_1_RSRVD0 0xFFFF0000
-#define BF_ENET_SWI_MIRROR_EDST_1_RSRVD0(v) \
- (((v) << 16) & BM_ENET_SWI_MIRROR_EDST_1_RSRVD0)
-#define BP_ENET_SWI_MIRROR_EDST_1_MIRROR_ESRC_1 0
-#define BM_ENET_SWI_MIRROR_EDST_1_MIRROR_ESRC_1 0x0000FFFF
-#define BF_ENET_SWI_MIRROR_EDST_1_MIRROR_ESRC_1(v) \
- (((v) << 0) & BM_ENET_SWI_MIRROR_EDST_1_MIRROR_ESRC_1)
-
-#define HW_ENET_SWI_MIRROR_CNT (0x00008068)
-
-#define BP_ENET_SWI_MIRROR_CNT_RSRVD0 8
-#define BM_ENET_SWI_MIRROR_CNT_RSRVD0 0xFFFFFF00
-#define BF_ENET_SWI_MIRROR_CNT_RSRVD0(v) \
- (((v) << 8) & BM_ENET_SWI_MIRROR_CNT_RSRVD0)
-#define BP_ENET_SWI_MIRROR_CNT_MIRROR_CNT 0
-#define BM_ENET_SWI_MIRROR_CNT_MIRROR_CNT 0x000000FF
-#define BF_ENET_SWI_MIRROR_CNT_MIRROR_CNT(v) \
- (((v) << 0) & BM_ENET_SWI_MIRROR_CNT_MIRROR_CNT)
-
-#define HW_ENET_SWI_OQMGR_STATUS (0x0000807c)
-
-#define BP_ENET_SWI_OQMGR_STATUS_RSRVD2 24
-#define BM_ENET_SWI_OQMGR_STATUS_RSRVD2 0xFF000000
-#define BF_ENET_SWI_OQMGR_STATUS_RSRVD2(v) \
- (((v) << 24) & BM_ENET_SWI_OQMGR_STATUS_RSRVD2)
-#define BP_ENET_SWI_OQMGR_STATUS_CELLS_AVAILABLE 16
-#define BM_ENET_SWI_OQMGR_STATUS_CELLS_AVAILABLE 0x00FF0000
-#define BF_ENET_SWI_OQMGR_STATUS_CELLS_AVAILABLE(v) \
- (((v) << 16) & BM_ENET_SWI_OQMGR_STATUS_CELLS_AVAILABLE)
-#define BP_ENET_SWI_OQMGR_STATUS_RSRVD1 7
-#define BM_ENET_SWI_OQMGR_STATUS_RSRVD1 0x0000FF80
-#define BF_ENET_SWI_OQMGR_STATUS_RSRVD1(v) \
- (((v) << 7) & BM_ENET_SWI_OQMGR_STATUS_RSRVD1)
-#define BM_ENET_SWI_OQMGR_STATUS_DEQUEUE_GRANT 0x00000040
-#define BP_ENET_SWI_OQMGR_STATUS_RSRVD0 4
-#define BM_ENET_SWI_OQMGR_STATUS_RSRVD0 0x00000030
-#define BF_ENET_SWI_OQMGR_STATUS_RSRVD0(v) \
- (((v) << 4) & BM_ENET_SWI_OQMGR_STATUS_RSRVD0)
-#define BM_ENET_SWI_OQMGR_STATUS_MEM_FULL_LATCH 0x00000008
-#define BM_ENET_SWI_OQMGR_STATUS_MEM_FULL 0x00000004
-#define BM_ENET_SWI_OQMGR_STATUS_NO_CELL_LATCH 0x00000002
-#define BM_ENET_SWI_OQMGR_STATUS_BUSY_INITIALIZING 0x00000001
-
-#define HW_ENET_SWI_QMGR_MINCELLS (0x00008080)
-
-#define BP_ENET_SWI_QMGR_MINCELLS_RSRVD0 8
-#define BM_ENET_SWI_QMGR_MINCELLS_RSRVD0 0xFFFFFF00
-#define BF_ENET_SWI_QMGR_MINCELLS_RSRVD0(v) \
- (((v) << 8) & BM_ENET_SWI_QMGR_MINCELLS_RSRVD0)
-#define BP_ENET_SWI_QMGR_MINCELLS_QMGR_MINCELLS 0
-#define BM_ENET_SWI_QMGR_MINCELLS_QMGR_MINCELLS 0x000000FF
-#define BF_ENET_SWI_QMGR_MINCELLS_QMGR_MINCELLS(v) \
- (((v) << 0) & BM_ENET_SWI_QMGR_MINCELLS_QMGR_MINCELLS)
-
-#define HW_ENET_SWI_QMGR_ST_MINCELLS (0x00008084)
-
-#define BP_ENET_SWI_QMGR_ST_MINCELLS_QMGR_ST_MINCELLS 0
-#define BM_ENET_SWI_QMGR_ST_MINCELLS_QMGR_ST_MINCELLS 0xFFFFFFFF
-#define BF_ENET_SWI_QMGR_ST_MINCELLS_QMGR_ST_MINCELLS(v) (v)
-
-#define HW_ENET_SWI_QMGR_CONGEST_STAT (0x00008088)
-
-#define BP_ENET_SWI_QMGR_CONGEST_STAT_RSRVD0 3
-#define BM_ENET_SWI_QMGR_CONGEST_STAT_RSRVD0 0xFFFFFFF8
-#define BF_ENET_SWI_QMGR_CONGEST_STAT_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_QMGR_CONGEST_STAT_RSRVD0)
-#define BM_ENET_SWI_QMGR_CONGEST_STAT_QMGR_CONGEST_STAT_2 0x00000004
-#define BM_ENET_SWI_QMGR_CONGEST_STAT_QMGR_CONGEST_STAT_1 0x00000002
-#define BM_ENET_SWI_QMGR_CONGEST_STAT_QMGR_CONGEST_STAT_0 0x00000001
-
-#define HW_ENET_SWI_QMGR_IFACE_STAT (0x0000808c)
-
-#define BP_ENET_SWI_QMGR_IFACE_STAT_RSRVD1 19
-#define BM_ENET_SWI_QMGR_IFACE_STAT_RSRVD1 0xFFF80000
-#define BF_ENET_SWI_QMGR_IFACE_STAT_RSRVD1(v) \
- (((v) << 19) & BM_ENET_SWI_QMGR_IFACE_STAT_RSRVD1)
-#define BM_ENET_SWI_QMGR_IFACE_STAT_INPUT_2 0x00040000
-#define BM_ENET_SWI_QMGR_IFACE_STAT_INPUT_1 0x00020000
-#define BM_ENET_SWI_QMGR_IFACE_STAT_INPUT_0 0x00010000
-#define BP_ENET_SWI_QMGR_IFACE_STAT_RSRVD0 3
-#define BM_ENET_SWI_QMGR_IFACE_STAT_RSRVD0 0x0000FFF8
-#define BF_ENET_SWI_QMGR_IFACE_STAT_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_QMGR_IFACE_STAT_RSRVD0)
-#define BM_ENET_SWI_QMGR_IFACE_STAT_OUTPUT_2 0x00000004
-#define BM_ENET_SWI_QMGR_IFACE_STAT_OUTPUT_1 0x00000002
-#define BM_ENET_SWI_QMGR_IFACE_STAT_OUTPUT_0 0x00000001
-
-#define HW_ENET_SWI_QM_WEIGHTS (0x00008090)
-
-#define BP_ENET_SWI_QM_WEIGHTS_RSRVD3 29
-#define BM_ENET_SWI_QM_WEIGHTS_RSRVD3 0xE0000000
-#define BF_ENET_SWI_QM_WEIGHTS_RSRVD3(v) \
- (((v) << 29) & BM_ENET_SWI_QM_WEIGHTS_RSRVD3)
-#define BP_ENET_SWI_QM_WEIGHTS_QUEUE_3 24
-#define BM_ENET_SWI_QM_WEIGHTS_QUEUE_3 0x1F000000
-#define BF_ENET_SWI_QM_WEIGHTS_QUEUE_3(v) \
- (((v) << 24) & BM_ENET_SWI_QM_WEIGHTS_QUEUE_3)
-#define BP_ENET_SWI_QM_WEIGHTS_RSRVD2 21
-#define BM_ENET_SWI_QM_WEIGHTS_RSRVD2 0x00E00000
-#define BF_ENET_SWI_QM_WEIGHTS_RSRVD2(v) \
- (((v) << 21) & BM_ENET_SWI_QM_WEIGHTS_RSRVD2)
-#define BP_ENET_SWI_QM_WEIGHTS_QUEUE_2 16
-#define BM_ENET_SWI_QM_WEIGHTS_QUEUE_2 0x001F0000
-#define BF_ENET_SWI_QM_WEIGHTS_QUEUE_2(v) \
- (((v) << 16) & BM_ENET_SWI_QM_WEIGHTS_QUEUE_2)
-#define BP_ENET_SWI_QM_WEIGHTS_RSRVD1 13
-#define BM_ENET_SWI_QM_WEIGHTS_RSRVD1 0x0000E000
-#define BF_ENET_SWI_QM_WEIGHTS_RSRVD1(v) \
- (((v) << 13) & BM_ENET_SWI_QM_WEIGHTS_RSRVD1)
-#define BP_ENET_SWI_QM_WEIGHTS_QUEUE_1 8
-#define BM_ENET_SWI_QM_WEIGHTS_QUEUE_1 0x00001F00
-#define BF_ENET_SWI_QM_WEIGHTS_QUEUE_1(v) \
- (((v) << 8) & BM_ENET_SWI_QM_WEIGHTS_QUEUE_1)
-#define BP_ENET_SWI_QM_WEIGHTS_RSRVD0 5
-#define BM_ENET_SWI_QM_WEIGHTS_RSRVD0 0x000000E0
-#define BF_ENET_SWI_QM_WEIGHTS_RSRVD0(v) \
- (((v) << 5) & BM_ENET_SWI_QM_WEIGHTS_RSRVD0)
-#define BP_ENET_SWI_QM_WEIGHTS_QUEUE_0 0
-#define BM_ENET_SWI_QM_WEIGHTS_QUEUE_0 0x0000001F
-#define BF_ENET_SWI_QM_WEIGHTS_QUEUE_0(v) \
- (((v) << 0) & BM_ENET_SWI_QM_WEIGHTS_QUEUE_0)
-
-#define HW_ENET_SWI_QMGR_MINCELLSP0 (0x00008098)
-
-#define BP_ENET_SWI_QMGR_MINCELLSP0_RSRVD0 8
-#define BM_ENET_SWI_QMGR_MINCELLSP0_RSRVD0 0xFFFFFF00
-#define BF_ENET_SWI_QMGR_MINCELLSP0_RSRVD0(v) \
- (((v) << 8) & BM_ENET_SWI_QMGR_MINCELLSP0_RSRVD0)
-#define BP_ENET_SWI_QMGR_MINCELLSP0_QMGR_MINCELLSP0 0
-#define BM_ENET_SWI_QMGR_MINCELLSP0_QMGR_MINCELLSP0 0x000000FF
-#define BF_ENET_SWI_QMGR_MINCELLSP0_QMGR_MINCELLSP0(v) \
- (((v) << 0) & BM_ENET_SWI_QMGR_MINCELLSP0_QMGR_MINCELLSP0)
-
-#define HW_ENET_SWI_FORCE_FWD_P0 (0x000080b8)
-
-#define BP_ENET_SWI_FORCE_FWD_P0_RSRVD1 4
-#define BM_ENET_SWI_FORCE_FWD_P0_RSRVD1 0xFFFFFFF0
-#define BF_ENET_SWI_FORCE_FWD_P0_RSRVD1(v) \
- (((v) << 4) & BM_ENET_SWI_FORCE_FWD_P0_RSRVD1)
-#define BP_ENET_SWI_FORCE_FWD_P0_FORCE_DESTINATION 2
-#define BM_ENET_SWI_FORCE_FWD_P0_FORCE_DESTINATION 0x0000000C
-#define BF_ENET_SWI_FORCE_FWD_P0_FORCE_DESTINATION(v) \
- (((v) << 2) & BM_ENET_SWI_FORCE_FWD_P0_FORCE_DESTINATION)
-#define BM_ENET_SWI_FORCE_FWD_P0_RSRVD0 0x00000002
-#define BM_ENET_SWI_FORCE_FWD_P0_FORCE_ENABLE 0x00000001
-
-#define HW_ENET_SWI_PORTSNOOP1 (0x000080bc)
-
-#define BP_ENET_SWI_PORTSNOOP1_DESTINATION_PORT 16
-#define BM_ENET_SWI_PORTSNOOP1_DESTINATION_PORT 0xFFFF0000
-#define BF_ENET_SWI_PORTSNOOP1_DESTINATION_PORT(v) \
- (((v) << 16) & BM_ENET_SWI_PORTSNOOP1_DESTINATION_PORT)
-#define BP_ENET_SWI_PORTSNOOP1_RSRVD0 5
-#define BM_ENET_SWI_PORTSNOOP1_RSRVD0 0x0000FFE0
-#define BF_ENET_SWI_PORTSNOOP1_RSRVD0(v) \
- (((v) << 5) & BM_ENET_SWI_PORTSNOOP1_RSRVD0)
-#define BM_ENET_SWI_PORTSNOOP1_COMPARE_SOURCE 0x00000010
-#define BM_ENET_SWI_PORTSNOOP1_COMPARE_DEST 0x00000008
-#define BP_ENET_SWI_PORTSNOOP1_MODE 1
-#define BM_ENET_SWI_PORTSNOOP1_MODE 0x00000006
-#define BF_ENET_SWI_PORTSNOOP1_MODE(v) \
- (((v) << 1) & BM_ENET_SWI_PORTSNOOP1_MODE)
-#define BM_ENET_SWI_PORTSNOOP1_ENABLE 0x00000001
-
-#define HW_ENET_SWI_PORTSNOOP2 (0x000080c0)
-
-#define BP_ENET_SWI_PORTSNOOP2_DESTINATION_PORT 16
-#define BM_ENET_SWI_PORTSNOOP2_DESTINATION_PORT 0xFFFF0000
-#define BF_ENET_SWI_PORTSNOOP2_DESTINATION_PORT(v) \
- (((v) << 16) & BM_ENET_SWI_PORTSNOOP2_DESTINATION_PORT)
-#define BP_ENET_SWI_PORTSNOOP2_RSRVD0 5
-#define BM_ENET_SWI_PORTSNOOP2_RSRVD0 0x0000FFE0
-#define BF_ENET_SWI_PORTSNOOP2_RSRVD0(v) \
- (((v) << 5) & BM_ENET_SWI_PORTSNOOP2_RSRVD0)
-#define BM_ENET_SWI_PORTSNOOP2_COMPARE_SOURCE 0x00000010
-#define BM_ENET_SWI_PORTSNOOP2_COMPARE_DEST 0x00000008
-#define BP_ENET_SWI_PORTSNOOP2_MODE 1
-#define BM_ENET_SWI_PORTSNOOP2_MODE 0x00000006
-#define BF_ENET_SWI_PORTSNOOP2_MODE(v) \
- (((v) << 1) & BM_ENET_SWI_PORTSNOOP2_MODE)
-#define BM_ENET_SWI_PORTSNOOP2_ENABLE 0x00000001
-
-#define HW_ENET_SWI_PORTSNOOP3 (0x000080c4)
-
-#define BP_ENET_SWI_PORTSNOOP3_DESTINATION_PORT 16
-#define BM_ENET_SWI_PORTSNOOP3_DESTINATION_PORT 0xFFFF0000
-#define BF_ENET_SWI_PORTSNOOP3_DESTINATION_PORT(v) \
- (((v) << 16) & BM_ENET_SWI_PORTSNOOP3_DESTINATION_PORT)
-#define BP_ENET_SWI_PORTSNOOP3_RSRVD0 5
-#define BM_ENET_SWI_PORTSNOOP3_RSRVD0 0x0000FFE0
-#define BF_ENET_SWI_PORTSNOOP3_RSRVD0(v) \
- (((v) << 5) & BM_ENET_SWI_PORTSNOOP3_RSRVD0)
-#define BM_ENET_SWI_PORTSNOOP3_COMPARE_SOURCE 0x00000010
-#define BM_ENET_SWI_PORTSNOOP3_COMPARE_DEST 0x00000008
-#define BP_ENET_SWI_PORTSNOOP3_MODE 1
-#define BM_ENET_SWI_PORTSNOOP3_MODE 0x00000006
-#define BF_ENET_SWI_PORTSNOOP3_MODE(v) \
- (((v) << 1) & BM_ENET_SWI_PORTSNOOP3_MODE)
-#define BM_ENET_SWI_PORTSNOOP3_ENABLE 0x00000001
-
-#define HW_ENET_SWI_PORTSNOOP4 (0x000080c8)
-
-#define BP_ENET_SWI_PORTSNOOP4_DESTINATION_PORT 16
-#define BM_ENET_SWI_PORTSNOOP4_DESTINATION_PORT 0xFFFF0000
-#define BF_ENET_SWI_PORTSNOOP4_DESTINATION_PORT(v) \
- (((v) << 16) & BM_ENET_SWI_PORTSNOOP4_DESTINATION_PORT)
-#define BP_ENET_SWI_PORTSNOOP4_RSRVD0 5
-#define BM_ENET_SWI_PORTSNOOP4_RSRVD0 0x0000FFE0
-#define BF_ENET_SWI_PORTSNOOP4_RSRVD0(v) \
- (((v) << 5) & BM_ENET_SWI_PORTSNOOP4_RSRVD0)
-#define BM_ENET_SWI_PORTSNOOP4_COMPARE_SOURCE 0x00000010
-#define BM_ENET_SWI_PORTSNOOP4_COMPARE_DEST 0x00000008
-#define BP_ENET_SWI_PORTSNOOP4_MODE 1
-#define BM_ENET_SWI_PORTSNOOP4_MODE 0x00000006
-#define BF_ENET_SWI_PORTSNOOP4_MODE(v) \
- (((v) << 1) & BM_ENET_SWI_PORTSNOOP4_MODE)
-#define BM_ENET_SWI_PORTSNOOP4_ENABLE 0x00000001
-
-#define HW_ENET_SWI_PORTSNOOP5 (0x000080cc)
-
-#define BP_ENET_SWI_PORTSNOOP5_DESTINATION_PORT 16
-#define BM_ENET_SWI_PORTSNOOP5_DESTINATION_PORT 0xFFFF0000
-#define BF_ENET_SWI_PORTSNOOP5_DESTINATION_PORT(v) \
- (((v) << 16) & BM_ENET_SWI_PORTSNOOP5_DESTINATION_PORT)
-#define BP_ENET_SWI_PORTSNOOP5_RSRVD0 5
-#define BM_ENET_SWI_PORTSNOOP5_RSRVD0 0x0000FFE0
-#define BF_ENET_SWI_PORTSNOOP5_RSRVD0(v) \
- (((v) << 5) & BM_ENET_SWI_PORTSNOOP5_RSRVD0)
-#define BM_ENET_SWI_PORTSNOOP5_COMPARE_SOURCE 0x00000010
-#define BM_ENET_SWI_PORTSNOOP5_COMPARE_DEST 0x00000008
-#define BP_ENET_SWI_PORTSNOOP5_MODE 1
-#define BM_ENET_SWI_PORTSNOOP5_MODE 0x00000006
-#define BF_ENET_SWI_PORTSNOOP5_MODE(v) \
- (((v) << 1) & BM_ENET_SWI_PORTSNOOP5_MODE)
-#define BM_ENET_SWI_PORTSNOOP5_ENABLE 0x00000001
-
-#define HW_ENET_SWI_PORTSNOOP6 (0x000080d0)
-
-#define BP_ENET_SWI_PORTSNOOP6_DESTINATION_PORT 16
-#define BM_ENET_SWI_PORTSNOOP6_DESTINATION_PORT 0xFFFF0000
-#define BF_ENET_SWI_PORTSNOOP6_DESTINATION_PORT(v) \
- (((v) << 16) & BM_ENET_SWI_PORTSNOOP6_DESTINATION_PORT)
-#define BP_ENET_SWI_PORTSNOOP6_RSRVD0 5
-#define BM_ENET_SWI_PORTSNOOP6_RSRVD0 0x0000FFE0
-#define BF_ENET_SWI_PORTSNOOP6_RSRVD0(v) \
- (((v) << 5) & BM_ENET_SWI_PORTSNOOP6_RSRVD0)
-#define BM_ENET_SWI_PORTSNOOP6_COMPARE_SOURCE 0x00000010
-#define BM_ENET_SWI_PORTSNOOP6_COMPARE_DEST 0x00000008
-#define BP_ENET_SWI_PORTSNOOP6_MODE 1
-#define BM_ENET_SWI_PORTSNOOP6_MODE 0x00000006
-#define BF_ENET_SWI_PORTSNOOP6_MODE(v) \
- (((v) << 1) & BM_ENET_SWI_PORTSNOOP6_MODE)
-#define BM_ENET_SWI_PORTSNOOP6_ENABLE 0x00000001
-
-#define HW_ENET_SWI_PORTSNOOP7 (0x000080d4)
-
-#define BP_ENET_SWI_PORTSNOOP7_DESTINATION_PORT 16
-#define BM_ENET_SWI_PORTSNOOP7_DESTINATION_PORT 0xFFFF0000
-#define BF_ENET_SWI_PORTSNOOP7_DESTINATION_PORT(v) \
- (((v) << 16) & BM_ENET_SWI_PORTSNOOP7_DESTINATION_PORT)
-#define BP_ENET_SWI_PORTSNOOP7_RSRVD0 5
-#define BM_ENET_SWI_PORTSNOOP7_RSRVD0 0x0000FFE0
-#define BF_ENET_SWI_PORTSNOOP7_RSRVD0(v) \
- (((v) << 5) & BM_ENET_SWI_PORTSNOOP7_RSRVD0)
-#define BM_ENET_SWI_PORTSNOOP7_COMPARE_SOURCE 0x00000010
-#define BM_ENET_SWI_PORTSNOOP7_COMPARE_DEST 0x00000008
-#define BP_ENET_SWI_PORTSNOOP7_MODE 1
-#define BM_ENET_SWI_PORTSNOOP7_MODE 0x00000006
-#define BF_ENET_SWI_PORTSNOOP7_MODE(v) \
- (((v) << 1) & BM_ENET_SWI_PORTSNOOP7_MODE)
-#define BM_ENET_SWI_PORTSNOOP7_ENABLE 0x00000001
-
-#define HW_ENET_SWI_PORTSNOOP8 (0x000080d8)
-
-#define BP_ENET_SWI_PORTSNOOP8_DESTINATION_PORT 16
-#define BM_ENET_SWI_PORTSNOOP8_DESTINATION_PORT 0xFFFF0000
-#define BF_ENET_SWI_PORTSNOOP8_DESTINATION_PORT(v) \
- (((v) << 16) & BM_ENET_SWI_PORTSNOOP8_DESTINATION_PORT)
-#define BP_ENET_SWI_PORTSNOOP8_RSRVD0 5
-#define BM_ENET_SWI_PORTSNOOP8_RSRVD0 0x0000FFE0
-#define BF_ENET_SWI_PORTSNOOP8_RSRVD0(v) \
- (((v) << 5) & BM_ENET_SWI_PORTSNOOP8_RSRVD0)
-#define BM_ENET_SWI_PORTSNOOP8_COMPARE_SOURCE 0x00000010
-#define BM_ENET_SWI_PORTSNOOP8_COMPARE_DEST 0x00000008
-#define BP_ENET_SWI_PORTSNOOP8_MODE 1
-#define BM_ENET_SWI_PORTSNOOP8_MODE 0x00000006
-#define BF_ENET_SWI_PORTSNOOP8_MODE(v) \
- (((v) << 1) & BM_ENET_SWI_PORTSNOOP8_MODE)
-#define BM_ENET_SWI_PORTSNOOP8_ENABLE 0x00000001
-
-#define HW_ENET_SWI_IPSNOOP1 (0x000080dc)
-
-#define BP_ENET_SWI_IPSNOOP1_RSRVD1 16
-#define BM_ENET_SWI_IPSNOOP1_RSRVD1 0xFFFF0000
-#define BF_ENET_SWI_IPSNOOP1_RSRVD1(v) \
- (((v) << 16) & BM_ENET_SWI_IPSNOOP1_RSRVD1)
-#define BP_ENET_SWI_IPSNOOP1_PROTOCOL 8
-#define BM_ENET_SWI_IPSNOOP1_PROTOCOL 0x0000FF00
-#define BF_ENET_SWI_IPSNOOP1_PROTOCOL(v) \
- (((v) << 8) & BM_ENET_SWI_IPSNOOP1_PROTOCOL)
-#define BP_ENET_SWI_IPSNOOP1_RSRVD0 3
-#define BM_ENET_SWI_IPSNOOP1_RSRVD0 0x000000F8
-#define BF_ENET_SWI_IPSNOOP1_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_IPSNOOP1_RSRVD0)
-#define BP_ENET_SWI_IPSNOOP1_MODE 1
-#define BM_ENET_SWI_IPSNOOP1_MODE 0x00000006
-#define BF_ENET_SWI_IPSNOOP1_MODE(v) \
- (((v) << 1) & BM_ENET_SWI_IPSNOOP1_MODE)
-#define BM_ENET_SWI_IPSNOOP1_ENABLE 0x00000001
-
-#define HW_ENET_SWI_IPSNOOP2 (0x000080e0)
-
-#define BP_ENET_SWI_IPSNOOP2_RSRVD1 16
-#define BM_ENET_SWI_IPSNOOP2_RSRVD1 0xFFFF0000
-#define BF_ENET_SWI_IPSNOOP2_RSRVD1(v) \
- (((v) << 16) & BM_ENET_SWI_IPSNOOP2_RSRVD1)
-#define BP_ENET_SWI_IPSNOOP2_PROTOCOL 8
-#define BM_ENET_SWI_IPSNOOP2_PROTOCOL 0x0000FF00
-#define BF_ENET_SWI_IPSNOOP2_PROTOCOL(v) \
- (((v) << 8) & BM_ENET_SWI_IPSNOOP2_PROTOCOL)
-#define BP_ENET_SWI_IPSNOOP2_RSRVD0 3
-#define BM_ENET_SWI_IPSNOOP2_RSRVD0 0x000000F8
-#define BF_ENET_SWI_IPSNOOP2_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_IPSNOOP2_RSRVD0)
-#define BP_ENET_SWI_IPSNOOP2_MODE 1
-#define BM_ENET_SWI_IPSNOOP2_MODE 0x00000006
-#define BF_ENET_SWI_IPSNOOP2_MODE(v) \
- (((v) << 1) & BM_ENET_SWI_IPSNOOP2_MODE)
-#define BM_ENET_SWI_IPSNOOP2_ENABLE 0x00000001
-
-#define HW_ENET_SWI_IPSNOOP3 (0x000080e4)
-
-#define BP_ENET_SWI_IPSNOOP3_RSRVD1 16
-#define BM_ENET_SWI_IPSNOOP3_RSRVD1 0xFFFF0000
-#define BF_ENET_SWI_IPSNOOP3_RSRVD1(v) \
- (((v) << 16) & BM_ENET_SWI_IPSNOOP3_RSRVD1)
-#define BP_ENET_SWI_IPSNOOP3_PROTOCOL 8
-#define BM_ENET_SWI_IPSNOOP3_PROTOCOL 0x0000FF00
-#define BF_ENET_SWI_IPSNOOP3_PROTOCOL(v) \
- (((v) << 8) & BM_ENET_SWI_IPSNOOP3_PROTOCOL)
-#define BP_ENET_SWI_IPSNOOP3_RSRVD0 3
-#define BM_ENET_SWI_IPSNOOP3_RSRVD0 0x000000F8
-#define BF_ENET_SWI_IPSNOOP3_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_IPSNOOP3_RSRVD0)
-#define BP_ENET_SWI_IPSNOOP3_MODE 1
-#define BM_ENET_SWI_IPSNOOP3_MODE 0x00000006
-#define BF_ENET_SWI_IPSNOOP3_MODE(v) \
- (((v) << 1) & BM_ENET_SWI_IPSNOOP3_MODE)
-#define BM_ENET_SWI_IPSNOOP3_ENABLE 0x00000001
-
-#define HW_ENET_SWI_IPSNOOP4 (0x000080e8)
-
-#define BP_ENET_SWI_IPSNOOP4_RSRVD1 16
-#define BM_ENET_SWI_IPSNOOP4_RSRVD1 0xFFFF0000
-#define BF_ENET_SWI_IPSNOOP4_RSRVD1(v) \
- (((v) << 16) & BM_ENET_SWI_IPSNOOP4_RSRVD1)
-#define BP_ENET_SWI_IPSNOOP4_PROTOCOL 8
-#define BM_ENET_SWI_IPSNOOP4_PROTOCOL 0x0000FF00
-#define BF_ENET_SWI_IPSNOOP4_PROTOCOL(v) \
- (((v) << 8) & BM_ENET_SWI_IPSNOOP4_PROTOCOL)
-#define BP_ENET_SWI_IPSNOOP4_RSRVD0 3
-#define BM_ENET_SWI_IPSNOOP4_RSRVD0 0x000000F8
-#define BF_ENET_SWI_IPSNOOP4_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_IPSNOOP4_RSRVD0)
-#define BP_ENET_SWI_IPSNOOP4_MODE 1
-#define BM_ENET_SWI_IPSNOOP4_MODE 0x00000006
-#define BF_ENET_SWI_IPSNOOP4_MODE(v) \
- (((v) << 1) & BM_ENET_SWI_IPSNOOP4_MODE)
-#define BM_ENET_SWI_IPSNOOP4_ENABLE 0x00000001
-
-#define HW_ENET_SWI_IPSNOOP5 (0x000080ec)
-
-#define BP_ENET_SWI_IPSNOOP5_RSRVD1 16
-#define BM_ENET_SWI_IPSNOOP5_RSRVD1 0xFFFF0000
-#define BF_ENET_SWI_IPSNOOP5_RSRVD1(v) \
- (((v) << 16) & BM_ENET_SWI_IPSNOOP5_RSRVD1)
-#define BP_ENET_SWI_IPSNOOP5_PROTOCOL 8
-#define BM_ENET_SWI_IPSNOOP5_PROTOCOL 0x0000FF00
-#define BF_ENET_SWI_IPSNOOP5_PROTOCOL(v) \
- (((v) << 8) & BM_ENET_SWI_IPSNOOP5_PROTOCOL)
-#define BP_ENET_SWI_IPSNOOP5_RSRVD0 3
-#define BM_ENET_SWI_IPSNOOP5_RSRVD0 0x000000F8
-#define BF_ENET_SWI_IPSNOOP5_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_IPSNOOP5_RSRVD0)
-#define BP_ENET_SWI_IPSNOOP5_MODE 1
-#define BM_ENET_SWI_IPSNOOP5_MODE 0x00000006
-#define BF_ENET_SWI_IPSNOOP5_MODE(v) \
- (((v) << 1) & BM_ENET_SWI_IPSNOOP5_MODE)
-#define BM_ENET_SWI_IPSNOOP5_ENABLE 0x00000001
-
-#define HW_ENET_SWI_IPSNOOP6 (0x000080f0)
-
-#define BP_ENET_SWI_IPSNOOP6_RSRVD1 16
-#define BM_ENET_SWI_IPSNOOP6_RSRVD1 0xFFFF0000
-#define BF_ENET_SWI_IPSNOOP6_RSRVD1(v) \
- (((v) << 16) & BM_ENET_SWI_IPSNOOP6_RSRVD1)
-#define BP_ENET_SWI_IPSNOOP6_PROTOCOL 8
-#define BM_ENET_SWI_IPSNOOP6_PROTOCOL 0x0000FF00
-#define BF_ENET_SWI_IPSNOOP6_PROTOCOL(v) \
- (((v) << 8) & BM_ENET_SWI_IPSNOOP6_PROTOCOL)
-#define BP_ENET_SWI_IPSNOOP6_RSRVD0 3
-#define BM_ENET_SWI_IPSNOOP6_RSRVD0 0x000000F8
-#define BF_ENET_SWI_IPSNOOP6_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_IPSNOOP6_RSRVD0)
-#define BP_ENET_SWI_IPSNOOP6_MODE 1
-#define BM_ENET_SWI_IPSNOOP6_MODE 0x00000006
-#define BF_ENET_SWI_IPSNOOP6_MODE(v) \
- (((v) << 1) & BM_ENET_SWI_IPSNOOP6_MODE)
-#define BM_ENET_SWI_IPSNOOP6_ENABLE 0x00000001
-
-#define HW_ENET_SWI_IPSNOOP7 (0x000080f4)
-
-#define BP_ENET_SWI_IPSNOOP7_RSRVD1 16
-#define BM_ENET_SWI_IPSNOOP7_RSRVD1 0xFFFF0000
-#define BF_ENET_SWI_IPSNOOP7_RSRVD1(v) \
- (((v) << 16) & BM_ENET_SWI_IPSNOOP7_RSRVD1)
-#define BP_ENET_SWI_IPSNOOP7_PROTOCOL 8
-#define BM_ENET_SWI_IPSNOOP7_PROTOCOL 0x0000FF00
-#define BF_ENET_SWI_IPSNOOP7_PROTOCOL(v) \
- (((v) << 8) & BM_ENET_SWI_IPSNOOP7_PROTOCOL)
-#define BP_ENET_SWI_IPSNOOP7_RSRVD0 3
-#define BM_ENET_SWI_IPSNOOP7_RSRVD0 0x000000F8
-#define BF_ENET_SWI_IPSNOOP7_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_IPSNOOP7_RSRVD0)
-#define BP_ENET_SWI_IPSNOOP7_MODE 1
-#define BM_ENET_SWI_IPSNOOP7_MODE 0x00000006
-#define BF_ENET_SWI_IPSNOOP7_MODE(v) \
- (((v) << 1) & BM_ENET_SWI_IPSNOOP7_MODE)
-#define BM_ENET_SWI_IPSNOOP7_ENABLE 0x00000001
-
-#define HW_ENET_SWI_IPSNOOP8 (0x000080f8)
-
-#define BP_ENET_SWI_IPSNOOP8_RSRVD1 16
-#define BM_ENET_SWI_IPSNOOP8_RSRVD1 0xFFFF0000
-#define BF_ENET_SWI_IPSNOOP8_RSRVD1(v) \
- (((v) << 16) & BM_ENET_SWI_IPSNOOP8_RSRVD1)
-#define BP_ENET_SWI_IPSNOOP8_PROTOCOL 8
-#define BM_ENET_SWI_IPSNOOP8_PROTOCOL 0x0000FF00
-#define BF_ENET_SWI_IPSNOOP8_PROTOCOL(v) \
- (((v) << 8) & BM_ENET_SWI_IPSNOOP8_PROTOCOL)
-#define BP_ENET_SWI_IPSNOOP8_RSRVD0 3
-#define BM_ENET_SWI_IPSNOOP8_RSRVD0 0x000000F8
-#define BF_ENET_SWI_IPSNOOP8_RSRVD0(v) \
- (((v) << 3) & BM_ENET_SWI_IPSNOOP8_RSRVD0)
-#define BP_ENET_SWI_IPSNOOP8_MODE 1
-#define BM_ENET_SWI_IPSNOOP8_MODE 0x00000006
-#define BF_ENET_SWI_IPSNOOP8_MODE(v) \
- (((v) << 1) & BM_ENET_SWI_IPSNOOP8_MODE)
-#define BM_ENET_SWI_IPSNOOP8_ENABLE 0x00000001
-
-#define HW_ENET_SWI_VLAN_PRIORITY0 (0x000080fc)
-
-#define BP_ENET_SWI_VLAN_PRIORITY0_RSRVD0 24
-#define BM_ENET_SWI_VLAN_PRIORITY0_RSRVD0 0xFF000000
-#define BF_ENET_SWI_VLAN_PRIORITY0_RSRVD0(v) \
- (((v) << 24) & BM_ENET_SWI_VLAN_PRIORITY0_RSRVD0)
-#define BP_ENET_SWI_VLAN_PRIORITY0_P7 21
-#define BM_ENET_SWI_VLAN_PRIORITY0_P7 0x00E00000
-#define BF_ENET_SWI_VLAN_PRIORITY0_P7(v) \
- (((v) << 21) & BM_ENET_SWI_VLAN_PRIORITY0_P7)
-#define BP_ENET_SWI_VLAN_PRIORITY0_P6 18
-#define BM_ENET_SWI_VLAN_PRIORITY0_P6 0x001C0000
-#define BF_ENET_SWI_VLAN_PRIORITY0_P6(v) \
- (((v) << 18) & BM_ENET_SWI_VLAN_PRIORITY0_P6)
-#define BP_ENET_SWI_VLAN_PRIORITY0_P5 15
-#define BM_ENET_SWI_VLAN_PRIORITY0_P5 0x00038000
-#define BF_ENET_SWI_VLAN_PRIORITY0_P5(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_PRIORITY0_P5)
-#define BP_ENET_SWI_VLAN_PRIORITY0_P4 12
-#define BM_ENET_SWI_VLAN_PRIORITY0_P4 0x00007000
-#define BF_ENET_SWI_VLAN_PRIORITY0_P4(v) \
- (((v) << 12) & BM_ENET_SWI_VLAN_PRIORITY0_P4)
-#define BP_ENET_SWI_VLAN_PRIORITY0_P3 9
-#define BM_ENET_SWI_VLAN_PRIORITY0_P3 0x00000E00
-#define BF_ENET_SWI_VLAN_PRIORITY0_P3(v) \
- (((v) << 9) & BM_ENET_SWI_VLAN_PRIORITY0_P3)
-#define BP_ENET_SWI_VLAN_PRIORITY0_P2 6
-#define BM_ENET_SWI_VLAN_PRIORITY0_P2 0x000001C0
-#define BF_ENET_SWI_VLAN_PRIORITY0_P2(v) \
- (((v) << 6) & BM_ENET_SWI_VLAN_PRIORITY0_P2)
-#define BP_ENET_SWI_VLAN_PRIORITY0_P1 3
-#define BM_ENET_SWI_VLAN_PRIORITY0_P1 0x00000038
-#define BF_ENET_SWI_VLAN_PRIORITY0_P1(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_PRIORITY0_P1)
-#define BP_ENET_SWI_VLAN_PRIORITY0_P0 0
-#define BM_ENET_SWI_VLAN_PRIORITY0_P0 0x00000007
-#define BF_ENET_SWI_VLAN_PRIORITY0_P0(v) \
- (((v) << 0) & BM_ENET_SWI_VLAN_PRIORITY0_P0)
-
-#define HW_ENET_SWI_VLAN_PRIORITY1 (0x00008100)
-
-#define BP_ENET_SWI_VLAN_PRIORITY1_RSRVD0 24
-#define BM_ENET_SWI_VLAN_PRIORITY1_RSRVD0 0xFF000000
-#define BF_ENET_SWI_VLAN_PRIORITY1_RSRVD0(v) \
- (((v) << 24) & BM_ENET_SWI_VLAN_PRIORITY1_RSRVD0)
-#define BP_ENET_SWI_VLAN_PRIORITY1_P7 21
-#define BM_ENET_SWI_VLAN_PRIORITY1_P7 0x00E00000
-#define BF_ENET_SWI_VLAN_PRIORITY1_P7(v) \
- (((v) << 21) & BM_ENET_SWI_VLAN_PRIORITY1_P7)
-#define BP_ENET_SWI_VLAN_PRIORITY1_P6 18
-#define BM_ENET_SWI_VLAN_PRIORITY1_P6 0x001C0000
-#define BF_ENET_SWI_VLAN_PRIORITY1_P6(v) \
- (((v) << 18) & BM_ENET_SWI_VLAN_PRIORITY1_P6)
-#define BP_ENET_SWI_VLAN_PRIORITY1_P5 15
-#define BM_ENET_SWI_VLAN_PRIORITY1_P5 0x00038000
-#define BF_ENET_SWI_VLAN_PRIORITY1_P5(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_PRIORITY1_P5)
-#define BP_ENET_SWI_VLAN_PRIORITY1_P4 12
-#define BM_ENET_SWI_VLAN_PRIORITY1_P4 0x00007000
-#define BF_ENET_SWI_VLAN_PRIORITY1_P4(v) \
- (((v) << 12) & BM_ENET_SWI_VLAN_PRIORITY1_P4)
-#define BP_ENET_SWI_VLAN_PRIORITY1_P3 9
-#define BM_ENET_SWI_VLAN_PRIORITY1_P3 0x00000E00
-#define BF_ENET_SWI_VLAN_PRIORITY1_P3(v) \
- (((v) << 9) & BM_ENET_SWI_VLAN_PRIORITY1_P3)
-#define BP_ENET_SWI_VLAN_PRIORITY1_P2 6
-#define BM_ENET_SWI_VLAN_PRIORITY1_P2 0x000001C0
-#define BF_ENET_SWI_VLAN_PRIORITY1_P2(v) \
- (((v) << 6) & BM_ENET_SWI_VLAN_PRIORITY1_P2)
-#define BP_ENET_SWI_VLAN_PRIORITY1_P1 3
-#define BM_ENET_SWI_VLAN_PRIORITY1_P1 0x00000038
-#define BF_ENET_SWI_VLAN_PRIORITY1_P1(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_PRIORITY1_P1)
-#define BP_ENET_SWI_VLAN_PRIORITY1_P0 0
-#define BM_ENET_SWI_VLAN_PRIORITY1_P0 0x00000007
-#define BF_ENET_SWI_VLAN_PRIORITY1_P0(v) \
- (((v) << 0) & BM_ENET_SWI_VLAN_PRIORITY1_P0)
-
-#define HW_ENET_SWI_VLAN_PRIORITY2 (0x00008104)
-
-#define BP_ENET_SWI_VLAN_PRIORITY2_RSRVD0 24
-#define BM_ENET_SWI_VLAN_PRIORITY2_RSRVD0 0xFF000000
-#define BF_ENET_SWI_VLAN_PRIORITY2_RSRVD0(v) \
- (((v) << 24) & BM_ENET_SWI_VLAN_PRIORITY2_RSRVD0)
-#define BP_ENET_SWI_VLAN_PRIORITY2_P7 21
-#define BM_ENET_SWI_VLAN_PRIORITY2_P7 0x00E00000
-#define BF_ENET_SWI_VLAN_PRIORITY2_P7(v) \
- (((v) << 21) & BM_ENET_SWI_VLAN_PRIORITY2_P7)
-#define BP_ENET_SWI_VLAN_PRIORITY2_P6 18
-#define BM_ENET_SWI_VLAN_PRIORITY2_P6 0x001C0000
-#define BF_ENET_SWI_VLAN_PRIORITY2_P6(v) \
- (((v) << 18) & BM_ENET_SWI_VLAN_PRIORITY2_P6)
-#define BP_ENET_SWI_VLAN_PRIORITY2_P5 15
-#define BM_ENET_SWI_VLAN_PRIORITY2_P5 0x00038000
-#define BF_ENET_SWI_VLAN_PRIORITY2_P5(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_PRIORITY2_P5)
-#define BP_ENET_SWI_VLAN_PRIORITY2_P4 12
-#define BM_ENET_SWI_VLAN_PRIORITY2_P4 0x00007000
-#define BF_ENET_SWI_VLAN_PRIORITY2_P4(v) \
- (((v) << 12) & BM_ENET_SWI_VLAN_PRIORITY2_P4)
-#define BP_ENET_SWI_VLAN_PRIORITY2_P3 9
-#define BM_ENET_SWI_VLAN_PRIORITY2_P3 0x00000E00
-#define BF_ENET_SWI_VLAN_PRIORITY2_P3(v) \
- (((v) << 9) & BM_ENET_SWI_VLAN_PRIORITY2_P3)
-#define BP_ENET_SWI_VLAN_PRIORITY2_P2 6
-#define BM_ENET_SWI_VLAN_PRIORITY2_P2 0x000001C0
-#define BF_ENET_SWI_VLAN_PRIORITY2_P2(v) \
- (((v) << 6) & BM_ENET_SWI_VLAN_PRIORITY2_P2)
-#define BP_ENET_SWI_VLAN_PRIORITY2_P1 3
-#define BM_ENET_SWI_VLAN_PRIORITY2_P1 0x00000038
-#define BF_ENET_SWI_VLAN_PRIORITY2_P1(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_PRIORITY2_P1)
-#define BP_ENET_SWI_VLAN_PRIORITY2_P0 0
-#define BM_ENET_SWI_VLAN_PRIORITY2_P0 0x00000007
-#define BF_ENET_SWI_VLAN_PRIORITY2_P0(v) \
- (((v) << 0) & BM_ENET_SWI_VLAN_PRIORITY2_P0)
-
-#define HW_ENET_SWI_IP_PRIORITY (0x0000813c)
-
-#define BM_ENET_SWI_IP_PRIORITY_READ 0x80000000
-#define BP_ENET_SWI_IP_PRIORITY_RSRVD0 15
-#define BM_ENET_SWI_IP_PRIORITY_RSRVD0 0x7FFF8000
-#define BF_ENET_SWI_IP_PRIORITY_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_IP_PRIORITY_RSRVD0)
-#define BP_ENET_SWI_IP_PRIORITY_PRIORITY_PORT2 13
-#define BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT2 0x00006000
-#define BF_ENET_SWI_IP_PRIORITY_PRIORITY_PORT2(v) \
- (((v) << 13) & BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT2)
-#define BP_ENET_SWI_IP_PRIORITY_PRIORITY_PORT1 11
-#define BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT1 0x00001800
-#define BF_ENET_SWI_IP_PRIORITY_PRIORITY_PORT1(v) \
- (((v) << 11) & BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT1)
-#define BP_ENET_SWI_IP_PRIORITY_PRIORITY_PORT0 9
-#define BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT0 0x00000600
-#define BF_ENET_SWI_IP_PRIORITY_PRIORITY_PORT0(v) \
- (((v) << 9) & BM_ENET_SWI_IP_PRIORITY_PRIORITY_PORT0)
-#define BM_ENET_SWI_IP_PRIORITY_IPV4_SELECT 0x00000100
-#define BP_ENET_SWI_IP_PRIORITY_ADDRESS 0
-#define BM_ENET_SWI_IP_PRIORITY_ADDRESS 0x000000FF
-#define BF_ENET_SWI_IP_PRIORITY_ADDRESS(v) \
- (((v) << 0) & BM_ENET_SWI_IP_PRIORITY_ADDRESS)
-
-#define HW_ENET_SWI_PRIORITY_CFG0 (0x0000817c)
-
-#define BP_ENET_SWI_PRIORITY_CFG0_RSRVD1 7
-#define BM_ENET_SWI_PRIORITY_CFG0_RSRVD1 0xFFFFFF80
-#define BF_ENET_SWI_PRIORITY_CFG0_RSRVD1(v) \
- (((v) << 7) & BM_ENET_SWI_PRIORITY_CFG0_RSRVD1)
-#define BP_ENET_SWI_PRIORITY_CFG0_DEFAULT_PRIORITY 4
-#define BM_ENET_SWI_PRIORITY_CFG0_DEFAULT_PRIORITY 0x00000070
-#define BF_ENET_SWI_PRIORITY_CFG0_DEFAULT_PRIORITY(v) \
- (((v) << 4) & BM_ENET_SWI_PRIORITY_CFG0_DEFAULT_PRIORITY)
-#define BM_ENET_SWI_PRIORITY_CFG0_RSRVD0 0x00000008
-#define BM_ENET_SWI_PRIORITY_CFG0_MAC_EN 0x00000004
-#define BM_ENET_SWI_PRIORITY_CFG0_IP_EN 0x00000002
-#define BM_ENET_SWI_PRIORITY_CFG0_VLAN_EN 0x00000001
-
-#define HW_ENET_SWI_PRIORITY_CFG1 (0x00008180)
-
-#define BP_ENET_SWI_PRIORITY_CFG1_RSRVD1 7
-#define BM_ENET_SWI_PRIORITY_CFG1_RSRVD1 0xFFFFFF80
-#define BF_ENET_SWI_PRIORITY_CFG1_RSRVD1(v) \
- (((v) << 7) & BM_ENET_SWI_PRIORITY_CFG1_RSRVD1)
-#define BP_ENET_SWI_PRIORITY_CFG1_DEFAULT_PRIORITY 4
-#define BM_ENET_SWI_PRIORITY_CFG1_DEFAULT_PRIORITY 0x00000070
-#define BF_ENET_SWI_PRIORITY_CFG1_DEFAULT_PRIORITY(v) \
- (((v) << 4) & BM_ENET_SWI_PRIORITY_CFG1_DEFAULT_PRIORITY)
-#define BM_ENET_SWI_PRIORITY_CFG1_RSRVD0 0x00000008
-#define BM_ENET_SWI_PRIORITY_CFG1_MAC_EN 0x00000004
-#define BM_ENET_SWI_PRIORITY_CFG1_IP_EN 0x00000002
-#define BM_ENET_SWI_PRIORITY_CFG1_VLAN_EN 0x00000001
-
-#define HW_ENET_SWI_PRIORITY_CFG2 (0x00008184)
-
-#define BP_ENET_SWI_PRIORITY_CFG2_RSRVD1 7
-#define BM_ENET_SWI_PRIORITY_CFG2_RSRVD1 0xFFFFFF80
-#define BF_ENET_SWI_PRIORITY_CFG2_RSRVD1(v) \
- (((v) << 7) & BM_ENET_SWI_PRIORITY_CFG2_RSRVD1)
-#define BP_ENET_SWI_PRIORITY_CFG2_DEFAULT_PRIORITY 4
-#define BM_ENET_SWI_PRIORITY_CFG2_DEFAULT_PRIORITY 0x00000070
-#define BF_ENET_SWI_PRIORITY_CFG2_DEFAULT_PRIORITY(v) \
- (((v) << 4) & BM_ENET_SWI_PRIORITY_CFG2_DEFAULT_PRIORITY)
-#define BM_ENET_SWI_PRIORITY_CFG2_RSRVD0 0x00000008
-#define BM_ENET_SWI_PRIORITY_CFG2_MAC_EN 0x00000004
-#define BM_ENET_SWI_PRIORITY_CFG2_IP_EN 0x00000002
-#define BM_ENET_SWI_PRIORITY_CFG2_VLAN_EN 0x00000001
-
-#define HW_ENET_SWI_SYSTEM_TAGINFO0 (0x000081fc)
-
-#define BP_ENET_SWI_SYSTEM_TAGINFO0_RSRVD0 16
-#define BM_ENET_SWI_SYSTEM_TAGINFO0_RSRVD0 0xFFFF0000
-#define BF_ENET_SWI_SYSTEM_TAGINFO0_RSRVD0(v) \
- (((v) << 16) & BM_ENET_SWI_SYSTEM_TAGINFO0_RSRVD0)
-#define BP_ENET_SWI_SYSTEM_TAGINFO0_SYSTEM_TAGINFO0 0
-#define BM_ENET_SWI_SYSTEM_TAGINFO0_SYSTEM_TAGINFO0 0x0000FFFF
-#define BF_ENET_SWI_SYSTEM_TAGINFO0_SYSTEM_TAGINFO0(v) \
- (((v) << 0) & BM_ENET_SWI_SYSTEM_TAGINFO0_SYSTEM_TAGINFO0)
-
-#define HW_ENET_SWI_SYSTEM_TAGINFO1 (0x00008200)
-
-#define BP_ENET_SWI_SYSTEM_TAGINFO1_RSRVD0 16
-#define BM_ENET_SWI_SYSTEM_TAGINFO1_RSRVD0 0xFFFF0000
-#define BF_ENET_SWI_SYSTEM_TAGINFO1_RSRVD0(v) \
- (((v) << 16) & BM_ENET_SWI_SYSTEM_TAGINFO1_RSRVD0)
-#define BP_ENET_SWI_SYSTEM_TAGINFO1_SYSTEM_TAGINFO0 0
-#define BM_ENET_SWI_SYSTEM_TAGINFO1_SYSTEM_TAGINFO0 0x0000FFFF
-#define BF_ENET_SWI_SYSTEM_TAGINFO1_SYSTEM_TAGINFO0(v) \
- (((v) << 0) & BM_ENET_SWI_SYSTEM_TAGINFO1_SYSTEM_TAGINFO0)
-
-#define HW_ENET_SWI_SYSTEM_TAGINFO2 (0x00008204)
-
-#define BP_ENET_SWI_SYSTEM_TAGINFO2_RSRVD0 16
-#define BM_ENET_SWI_SYSTEM_TAGINFO2_RSRVD0 0xFFFF0000
-#define BF_ENET_SWI_SYSTEM_TAGINFO2_RSRVD0(v) \
- (((v) << 16) & BM_ENET_SWI_SYSTEM_TAGINFO2_RSRVD0)
-#define BP_ENET_SWI_SYSTEM_TAGINFO2_SYSTEM_TAGINFO0 0
-#define BM_ENET_SWI_SYSTEM_TAGINFO2_SYSTEM_TAGINFO0 0x0000FFFF
-#define BF_ENET_SWI_SYSTEM_TAGINFO2_SYSTEM_TAGINFO0(v) \
- (((v) << 0) & BM_ENET_SWI_SYSTEM_TAGINFO2_SYSTEM_TAGINFO0)
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_0 (0x0000827c)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_0_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_0_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_0_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_0_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_0_VLAN_ID_0 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_0_VLAN_ID_0 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_0_VLAN_ID_0(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_0_VLAN_ID_0)
-#define BM_ENET_SWI_VLAN_RES_TABLE_0_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_0_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_0_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_1 (0x00008280)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_1_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_1_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_1_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_1_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_1_VLAN_ID_1 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_1_VLAN_ID_1 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_1_VLAN_ID_1(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_1_VLAN_ID_1)
-#define BM_ENET_SWI_VLAN_RES_TABLE_1_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_1_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_1_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_2 (0x00008284)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_2_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_2_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_2_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_2_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_2_VLAN_ID_2 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_2_VLAN_ID_2 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_2_VLAN_ID_2(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_2_VLAN_ID_2)
-#define BM_ENET_SWI_VLAN_RES_TABLE_2_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_2_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_2_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_3 (0x00008288)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_3_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_3_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_3_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_3_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_3_VLAN_ID_3 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_3_VLAN_ID_3 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_3_VLAN_ID_3(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_3_VLAN_ID_3)
-#define BM_ENET_SWI_VLAN_RES_TABLE_3_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_3_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_3_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_4 (0x0000828c)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_4_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_4_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_4_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_4_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_4_VLAN_ID_4 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_4_VLAN_ID_4 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_4_VLAN_ID_4(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_4_VLAN_ID_4)
-#define BM_ENET_SWI_VLAN_RES_TABLE_4_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_4_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_4_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_5 (0x00008290)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_5_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_5_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_5_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_5_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_5_VLAN_ID_5 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_5_VLAN_ID_5 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_5_VLAN_ID_5(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_5_VLAN_ID_5)
-#define BM_ENET_SWI_VLAN_RES_TABLE_5_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_5_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_5_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_6 (0x00008294)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_6_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_6_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_6_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_6_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_6_VLAN_ID_6 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_6_VLAN_ID_6 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_6_VLAN_ID_6(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_6_VLAN_ID_6)
-#define BM_ENET_SWI_VLAN_RES_TABLE_6_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_6_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_6_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_7 (0x00008298)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_7_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_7_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_7_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_7_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_7_VLAN_ID_7 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_7_VLAN_ID_7 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_7_VLAN_ID_7(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_7_VLAN_ID_7)
-#define BM_ENET_SWI_VLAN_RES_TABLE_7_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_7_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_7_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_8 (0x0000829c)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_8_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_8_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_8_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_8_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_8_VLAN_ID_8 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_8_VLAN_ID_8 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_8_VLAN_ID_8(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_8_VLAN_ID_8)
-#define BM_ENET_SWI_VLAN_RES_TABLE_8_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_8_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_8_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_9 (0x000082a0)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_9_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_9_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_9_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_9_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_9_VLAN_ID_9 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_9_VLAN_ID_9 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_9_VLAN_ID_9(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_9_VLAN_ID_9)
-#define BM_ENET_SWI_VLAN_RES_TABLE_9_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_9_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_9_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_10 (0x000082a4)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_10_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_10_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_10_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_10_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_10_VLAN_ID_10 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_10_VLAN_ID_10 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_10_VLAN_ID_10(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_10_VLAN_ID_10)
-#define BM_ENET_SWI_VLAN_RES_TABLE_10_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_10_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_10_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_11 (0x000082a8)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_11_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_11_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_11_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_11_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_11_VLAN_ID_11 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_11_VLAN_ID_11 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_11_VLAN_ID_11(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_11_VLAN_ID_11)
-#define BM_ENET_SWI_VLAN_RES_TABLE_11_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_11_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_11_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_12 (0x000082ac)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_12_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_12_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_12_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_12_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_12_VLAN_ID_12 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_12_VLAN_ID_12 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_12_VLAN_ID_12(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_12_VLAN_ID_12)
-#define BM_ENET_SWI_VLAN_RES_TABLE_12_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_12_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_12_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_13 (0x000082b0)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_13_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_13_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_13_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_13_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_13_VLAN_ID_13 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_13_VLAN_ID_13 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_13_VLAN_ID_13(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_13_VLAN_ID_13)
-#define BM_ENET_SWI_VLAN_RES_TABLE_13_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_13_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_13_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_14 (0x000082b4)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_14_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_14_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_14_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_14_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_14_VLAN_ID_14 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_14_VLAN_ID_14 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_14_VLAN_ID_14(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_14_VLAN_ID_14)
-#define BM_ENET_SWI_VLAN_RES_TABLE_14_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_14_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_14_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_15 (0x000082b8)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_15_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_15_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_15_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_15_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_15_VLAN_ID_15 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_15_VLAN_ID_15 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_15_VLAN_ID_15(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_15_VLAN_ID_15)
-#define BM_ENET_SWI_VLAN_RES_TABLE_15_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_15_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_15_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_16 (0x000082bc)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_16_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_16_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_16_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_16_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_16_VLAN_ID_16 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_16_VLAN_ID_16 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_16_VLAN_ID_16(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_16_VLAN_ID_16)
-#define BM_ENET_SWI_VLAN_RES_TABLE_16_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_16_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_16_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_17 (0x000082c0)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_17_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_17_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_17_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_17_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_17_VLAN_ID_17 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_17_VLAN_ID_17 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_17_VLAN_ID_17(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_17_VLAN_ID_17)
-#define BM_ENET_SWI_VLAN_RES_TABLE_17_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_17_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_17_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_18 (0x000082c4)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_18_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_18_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_18_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_18_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_18_VLAN_ID_18 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_18_VLAN_ID_18 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_18_VLAN_ID_18(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_18_VLAN_ID_18)
-#define BM_ENET_SWI_VLAN_RES_TABLE_18_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_18_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_18_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_19 (0x000082c8)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_19_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_19_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_19_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_19_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_19_VLAN_ID_19 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_19_VLAN_ID_19 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_19_VLAN_ID_19(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_19_VLAN_ID_19)
-#define BM_ENET_SWI_VLAN_RES_TABLE_19_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_19_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_19_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_20 (0x000082cc)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_20_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_20_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_20_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_20_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_20_VLAN_ID_20 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_20_VLAN_ID_20 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_20_VLAN_ID_20(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_20_VLAN_ID_20)
-#define BM_ENET_SWI_VLAN_RES_TABLE_20_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_20_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_20_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_21 (0x000082d0)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_21_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_21_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_21_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_21_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_21_VLAN_ID_21 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_21_VLAN_ID_21 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_21_VLAN_ID_21(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_21_VLAN_ID_21)
-#define BM_ENET_SWI_VLAN_RES_TABLE_21_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_21_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_21_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_22 (0x000082d4)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_22_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_22_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_22_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_22_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_22_VLAN_ID_22 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_22_VLAN_ID_22 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_22_VLAN_ID_22(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_22_VLAN_ID_22)
-#define BM_ENET_SWI_VLAN_RES_TABLE_22_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_22_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_22_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_23 (0x000082d8)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_23_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_23_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_23_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_23_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_23_VLAN_ID_23 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_23_VLAN_ID_23 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_23_VLAN_ID_23(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_23_VLAN_ID_23)
-#define BM_ENET_SWI_VLAN_RES_TABLE_23_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_23_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_23_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_24 (0x000082dc)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_24_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_24_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_24_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_24_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_24_VLAN_ID_24 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_24_VLAN_ID_24 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_24_VLAN_ID_24(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_24_VLAN_ID_24)
-#define BM_ENET_SWI_VLAN_RES_TABLE_24_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_24_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_24_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_25 (0x000082e0)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_25_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_25_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_25_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_25_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_25_VLAN_ID_25 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_25_VLAN_ID_25 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_25_VLAN_ID_25(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_25_VLAN_ID_25)
-#define BM_ENET_SWI_VLAN_RES_TABLE_25_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_25_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_25_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_26 (0x000082e4)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_26_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_26_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_26_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_26_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_26_VLAN_ID_26 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_26_VLAN_ID_26 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_26_VLAN_ID_26(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_26_VLAN_ID_26)
-#define BM_ENET_SWI_VLAN_RES_TABLE_26_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_26_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_26_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_27 (0x000082e8)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_27_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_27_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_27_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_27_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_27_VLAN_ID_27 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_27_VLAN_ID_27 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_27_VLAN_ID_27(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_27_VLAN_ID_27)
-#define BM_ENET_SWI_VLAN_RES_TABLE_27_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_27_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_27_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_28 (0x000082ec)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_28_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_28_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_28_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_28_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_28_VLAN_ID_28 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_28_VLAN_ID_28 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_28_VLAN_ID_28(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_28_VLAN_ID_28)
-#define BM_ENET_SWI_VLAN_RES_TABLE_28_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_28_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_28_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_29 (0x000082f0)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_29_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_29_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_29_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_29_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_29_VLAN_ID_29 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_29_VLAN_ID_29 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_29_VLAN_ID_29(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_29_VLAN_ID_29)
-#define BM_ENET_SWI_VLAN_RES_TABLE_29_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_29_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_29_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_30 (0x000082f4)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_30_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_30_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_30_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_30_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_30_VLAN_ID_30 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_30_VLAN_ID_30 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_30_VLAN_ID_30(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_30_VLAN_ID_30)
-#define BM_ENET_SWI_VLAN_RES_TABLE_30_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_30_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_30_PORT_0 0x00000001
-
-#define HW_ENET_SWI_VLAN_RES_TABLE_31 (0x000082f8)
-
-#define BP_ENET_SWI_VLAN_RES_TABLE_31_RSRVD0 15
-#define BM_ENET_SWI_VLAN_RES_TABLE_31_RSRVD0 0xFFFF8000
-#define BF_ENET_SWI_VLAN_RES_TABLE_31_RSRVD0(v) \
- (((v) << 15) & BM_ENET_SWI_VLAN_RES_TABLE_31_RSRVD0)
-#define BP_ENET_SWI_VLAN_RES_TABLE_31_VLAN_ID_31 3
-#define BM_ENET_SWI_VLAN_RES_TABLE_31_VLAN_ID_31 0x00007FF8
-#define BF_ENET_SWI_VLAN_RES_TABLE_31_VLAN_ID_31(v) \
- (((v) << 3) & BM_ENET_SWI_VLAN_RES_TABLE_31_VLAN_ID_31)
-#define BM_ENET_SWI_VLAN_RES_TABLE_31_PORT_2 0x00000004
-#define BM_ENET_SWI_VLAN_RES_TABLE_31_PORT_1 0x00000002
-#define BM_ENET_SWI_VLAN_RES_TABLE_31_PORT_0 0x00000001
-
-#define HW_ENET_SWI_TOTAL_DISC (0x000082fc)
-
-#define BP_ENET_SWI_TOTAL_DISC_TOTAL_DISC 0
-#define BM_ENET_SWI_TOTAL_DISC_TOTAL_DISC 0xFFFFFFFF
-#define BF_ENET_SWI_TOTAL_DISC_TOTAL_DISC(v) (v)
-
-#define HW_ENET_SWI_TOTAL_BYT_DISC (0x00008300)
-
-#define BP_ENET_SWI_TOTAL_BYT_DISC_TOTAL_BYT_DISC 0
-#define BM_ENET_SWI_TOTAL_BYT_DISC_TOTAL_BYT_DISC 0xFFFFFFFF
-#define BF_ENET_SWI_TOTAL_BYT_DISC_TOTAL_BYT_DISC(v) (v)
-
-#define HW_ENET_SWI_TOTAL_FRM (0x00008304)
-
-#define BP_ENET_SWI_TOTAL_FRM_TOTAL_FRM 0
-#define BM_ENET_SWI_TOTAL_FRM_TOTAL_FRM 0xFFFFFFFF
-#define BF_ENET_SWI_TOTAL_FRM_TOTAL_FRM(v) (v)
-
-#define HW_ENET_SWI_TOTAL_BYT_FRM (0x00008308)
-
-#define BP_ENET_SWI_TOTAL_BYT_FRM_TOTAL_BYT_FRM 0
-#define BM_ENET_SWI_TOTAL_BYT_FRM_TOTAL_BYT_FRM 0xFFFFFFFF
-#define BF_ENET_SWI_TOTAL_BYT_FRM_TOTAL_BYT_FRM(v) (v)
-
-#define HW_ENET_SWI_ODISC0 (0x0000830c)
-
-#define BP_ENET_SWI_ODISC0_ODISC0 0
-#define BM_ENET_SWI_ODISC0_ODISC0 0xFFFFFFFF
-#define BF_ENET_SWI_ODISC0_ODISC0(v) (v)
-
-#define HW_ENET_SWI_IDISC_VLAN0 (0x00008310)
-
-#define BP_ENET_SWI_IDISC_VLAN0_IDISC_VLAN0 0
-#define BM_ENET_SWI_IDISC_VLAN0_IDISC_VLAN0 0xFFFFFFFF
-#define BF_ENET_SWI_IDISC_VLAN0_IDISC_VLAN0(v) (v)
-
-#define HW_ENET_SWI_IDISC_UNTAGGED0 (0x00008314)
-
-#define BP_ENET_SWI_IDISC_UNTAGGED0_IDISC_UNTAGGED0 0
-#define BM_ENET_SWI_IDISC_UNTAGGED0_IDISC_UNTAGGED0 0xFFFFFFFF
-#define BF_ENET_SWI_IDISC_UNTAGGED0_IDISC_UNTAGGED0(v) (v)
-
-#define HW_ENET_SWI_IDISC_BLOCKED0 (0x00008318)
-
-#define BP_ENET_SWI_IDISC_BLOCKED0_IDISC_BLOCKED0 0
-#define BM_ENET_SWI_IDISC_BLOCKED0_IDISC_BLOCKED0 0xFFFFFFFF
-#define BF_ENET_SWI_IDISC_BLOCKED0_IDISC_BLOCKED0(v) (v)
-
-#define HW_ENET_SWI_ODISC1 (0x0000831c)
-
-#define BP_ENET_SWI_ODISC1_ODISC1 0
-#define BM_ENET_SWI_ODISC1_ODISC1 0xFFFFFFFF
-#define BF_ENET_SWI_ODISC1_ODISC1(v) (v)
-
-#define HW_ENET_SWI_IDISC_VLAN1 (0x00008320)
-
-#define BP_ENET_SWI_IDISC_VLAN1_IDISC_VLAN1 0
-#define BM_ENET_SWI_IDISC_VLAN1_IDISC_VLAN1 0xFFFFFFFF
-#define BF_ENET_SWI_IDISC_VLAN1_IDISC_VLAN1(v) (v)
-
-#define HW_ENET_SWI_IDISC_UNTAGGED1 (0x00008324)
-
-#define BP_ENET_SWI_IDISC_UNTAGGED1_IDISC_UNTAGGED1 0
-#define BM_ENET_SWI_IDISC_UNTAGGED1_IDISC_UNTAGGED1 0xFFFFFFFF
-#define BF_ENET_SWI_IDISC_UNTAGGED1_IDISC_UNTAGGED1(v) (v)
-
-#define HW_ENET_SWI_IDISC_BLOCKED1 (0x00008328)
-
-#define BP_ENET_SWI_IDISC_BLOCKED1_IDISC_BLOCKED1 0
-#define BM_ENET_SWI_IDISC_BLOCKED1_IDISC_BLOCKED1 0xFFFFFFFF
-#define BF_ENET_SWI_IDISC_BLOCKED1_IDISC_BLOCKED1(v) (v)
-
-#define HW_ENET_SWI_ODISC2 (0x0000832c)
-
-#define BP_ENET_SWI_ODISC2_ODISC2 0
-#define BM_ENET_SWI_ODISC2_ODISC2 0xFFFFFFFF
-#define BF_ENET_SWI_ODISC2_ODISC2(v) (v)
-
-#define HW_ENET_SWI_IDISC_VLAN2 (0x00008330)
-
-#define BP_ENET_SWI_IDISC_VLAN2_IDISC_VLAN2 0
-#define BM_ENET_SWI_IDISC_VLAN2_IDISC_VLAN2 0xFFFFFFFF
-#define BF_ENET_SWI_IDISC_VLAN2_IDISC_VLAN2(v) (v)
-
-#define HW_ENET_SWI_IDISC_UNTAGGED2 (0x00008334)
-
-#define BP_ENET_SWI_IDISC_UNTAGGED2_IDISC_UNTAGGED2 0
-#define BM_ENET_SWI_IDISC_UNTAGGED2_IDISC_UNTAGGED2 0xFFFFFFFF
-#define BF_ENET_SWI_IDISC_UNTAGGED2_IDISC_UNTAGGED2(v) (v)
-
-#define HW_ENET_SWI_IDISC_BLOCKED2 (0x00008338)
-
-#define BP_ENET_SWI_IDISC_BLOCKED2_IDISC_BLOCKED2 0
-#define BM_ENET_SWI_IDISC_BLOCKED2_IDISC_BLOCKED2 0xFFFFFFFF
-#define BF_ENET_SWI_IDISC_BLOCKED2_IDISC_BLOCKED2(v) (v)
-
-#define HW_ENET_SWI_EIR (0x000083fc)
-
-#define BP_ENET_SWI_EIR_RSRVD0 10
-#define BM_ENET_SWI_EIR_RSRVD0 0xFFFFFC00
-#define BF_ENET_SWI_EIR_RSRVD0(v) \
- (((v) << 10) & BM_ENET_SWI_EIR_RSRVD0)
-#define BM_ENET_SWI_EIR_LRN 0x00000200
-#define BM_ENET_SWI_EIR_OD2 0x00000100
-#define BM_ENET_SWI_EIR_OD1 0x00000080
-#define BM_ENET_SWI_EIR_OD0 0x00000040
-#define BM_ENET_SWI_EIR_QM 0x00000020
-#define BM_ENET_SWI_EIR_TXF 0x00000010
-#define BM_ENET_SWI_EIR_TXB 0x00000008
-#define BM_ENET_SWI_EIR_RXF 0x00000004
-#define BM_ENET_SWI_EIR_RXB 0x00000002
-#define BM_ENET_SWI_EIR_EBERR 0x00000001
-
-#define HW_ENET_SWI_EIMR (0x00008400)
-
-#define BP_ENET_SWI_EIMR_RSRVD0 10
-#define BM_ENET_SWI_EIMR_RSRVD0 0xFFFFFC00
-#define BF_ENET_SWI_EIMR_RSRVD0(v) \
- (((v) << 10) & BM_ENET_SWI_EIMR_RSRVD0)
-#define BM_ENET_SWI_EIMR_LRN 0x00000200
-#define BM_ENET_SWI_EIMR_OD2 0x00000100
-#define BM_ENET_SWI_EIMR_OD1 0x00000080
-#define BM_ENET_SWI_EIMR_OD0 0x00000040
-#define BM_ENET_SWI_EIMR_QM 0x00000020
-#define BM_ENET_SWI_EIMR_TXF 0x00000010
-#define BM_ENET_SWI_EIMR_TXB 0x00000008
-#define BM_ENET_SWI_EIMR_RXF 0x00000004
-#define BM_ENET_SWI_EIMR_RXB 0x00000002
-#define BM_ENET_SWI_EIMR_EBERR 0x00000001
-
-#define HW_ENET_SWI_ERDSR (0x00008404)
-
-#define BP_ENET_SWI_ERDSR_ERDSR 2
-#define BM_ENET_SWI_ERDSR_ERDSR 0xFFFFFFFC
-#define BF_ENET_SWI_ERDSR_ERDSR(v) \
- (((v) << 2) & BM_ENET_SWI_ERDSR_ERDSR)
-#define BP_ENET_SWI_ERDSR_RSRVD0 0
-#define BM_ENET_SWI_ERDSR_RSRVD0 0x00000003
-#define BF_ENET_SWI_ERDSR_RSRVD0(v) \
- (((v) << 0) & BM_ENET_SWI_ERDSR_RSRVD0)
-
-#define HW_ENET_SWI_ETDSR (0x00008408)
-
-#define BP_ENET_SWI_ETDSR_ETDSR 2
-#define BM_ENET_SWI_ETDSR_ETDSR 0xFFFFFFFC
-#define BF_ENET_SWI_ETDSR_ETDSR(v) \
- (((v) << 2) & BM_ENET_SWI_ETDSR_ETDSR)
-#define BP_ENET_SWI_ETDSR_RSRVD0 0
-#define BM_ENET_SWI_ETDSR_RSRVD0 0x00000003
-#define BF_ENET_SWI_ETDSR_RSRVD0(v) \
- (((v) << 0) & BM_ENET_SWI_ETDSR_RSRVD0)
-
-#define HW_ENET_SWI_EMRBR (0x0000840c)
-
-#define BP_ENET_SWI_EMRBR_RSRVD1 14
-#define BM_ENET_SWI_EMRBR_RSRVD1 0xFFFFC000
-#define BF_ENET_SWI_EMRBR_RSRVD1(v) \
- (((v) << 14) & BM_ENET_SWI_EMRBR_RSRVD1)
-#define BP_ENET_SWI_EMRBR_EMRBR 4
-#define BM_ENET_SWI_EMRBR_EMRBR 0x00003FF0
-#define BF_ENET_SWI_EMRBR_EMRBR(v) \
- (((v) << 4) & BM_ENET_SWI_EMRBR_EMRBR)
-#define BP_ENET_SWI_EMRBR_RSRVD0 0
-#define BM_ENET_SWI_EMRBR_RSRVD0 0x0000000F
-#define BF_ENET_SWI_EMRBR_RSRVD0(v) \
- (((v) << 0) & BM_ENET_SWI_EMRBR_RSRVD0)
-
-#define HW_ENET_SWI_RDAR (0x00008410)
-
-#define BP_ENET_SWI_RDAR_RDAR 0
-#define BM_ENET_SWI_RDAR_RDAR 0xFFFFFFFF
-#define BF_ENET_SWI_RDAR_RDAR(v) (v)
-
-#define HW_ENET_SWI_TDAR (0x00008414)
-
-#define BP_ENET_SWI_TDAR_TDAR 0
-#define BM_ENET_SWI_TDAR_TDAR 0xFFFFFFFF
-#define BF_ENET_SWI_TDAR_TDAR(v) (v)
-
-#define HW_ENET_SWI_LRN_REC_0 (0x000084fc)
-
-#define BP_ENET_SWI_LRN_REC_0_LRN_REC_0 0
-#define BM_ENET_SWI_LRN_REC_0_LRN_REC_0 0xFFFFFFFF
-#define BF_ENET_SWI_LRN_REC_0_LRN_REC_0(v) (v)
-
-#define HW_ENET_SWI_LRN_REC_1 (0x00008500)
-
-#define BP_ENET_SWI_LRN_REC_1_RSRVD0 26
-#define BM_ENET_SWI_LRN_REC_1_RSRVD0 0xFC000000
-#define BF_ENET_SWI_LRN_REC_1_RSRVD0(v) \
- (((v) << 26) & BM_ENET_SWI_LRN_REC_1_RSRVD0)
-#define BP_ENET_SWI_LRN_REC_1_SW_PORT 24
-#define BM_ENET_SWI_LRN_REC_1_SW_PORT 0x03000000
-#define BF_ENET_SWI_LRN_REC_1_SW_PORT(v) \
- (((v) << 24) & BM_ENET_SWI_LRN_REC_1_SW_PORT)
-#define BP_ENET_SWI_LRN_REC_1_HASH 16
-#define BM_ENET_SWI_LRN_REC_1_HASH 0x00FF0000
-#define BF_ENET_SWI_LRN_REC_1_HASH(v) \
- (((v) << 16) & BM_ENET_SWI_LRN_REC_1_HASH)
-#define BP_ENET_SWI_LRN_REC_1_MAC_ADDR1 0
-#define BM_ENET_SWI_LRN_REC_1_MAC_ADDR1 0x0000FFFF
-#define BF_ENET_SWI_LRN_REC_1_MAC_ADDR1(v) \
- (((v) << 0) & BM_ENET_SWI_LRN_REC_1_MAC_ADDR1)
-
-#define HW_ENET_SWI_LRN_STATUS (0x00008504)
-
-#define BP_ENET_SWI_LRN_STATUS_RSRVD0 1
-#define BM_ENET_SWI_LRN_STATUS_RSRVD0 0xFFFFFFFE
-#define BF_ENET_SWI_LRN_STATUS_RSRVD0(v) \
- (((v) << 1) & BM_ENET_SWI_LRN_STATUS_RSRVD0)
-#define BM_ENET_SWI_LRN_STATUS_LRN_STATUS 0x00000001
-
-#define HW_ENET_SWI_LOOKUP_MEMORY_START (0x0000bffc)
-
-#define BP_ENET_SWI_LOOKUP_MEMORY_START_MEMORY_DATA 0
-#define BM_ENET_SWI_LOOKUP_MEMORY_START_MEMORY_DATA 0xFFFFFFFF
-#define BF_ENET_SWI_LOOKUP_MEMORY_START_MEMORY_DATA(v) (v)
-
-#define HW_ENET_SWI_LOOKUP_MEMORY_END (0x0000fff8)
-
-#define BP_ENET_SWI_LOOKUP_MEMORY_END_MEMORY_DATA 0
-#define BM_ENET_SWI_LOOKUP_MEMORY_END_MEMORY_DATA 0xFFFFFFFF
-#define BF_ENET_SWI_LOOKUP_MEMORY_END_MEMORY_DATA(v) (v)
-#endif /* __ARCH_ARM___ENET_H */
+++ /dev/null
-/*
- * Freescale OCOTP Register Definitions
- *
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * This file is created by xml file. Don't Edit it.
- *
- * Xml Revision: 1.21
- * Template revision: 26195
- */
-
-#ifndef __ARCH_ARM___OCOTP_H
-#define __ARCH_ARM___OCOTP_H
-
-
-#define HW_OCOTP_CTRL (0x00000000)
-#define HW_OCOTP_CTRL_SET (0x00000004)
-#define HW_OCOTP_CTRL_CLR (0x00000008)
-#define HW_OCOTP_CTRL_TOG (0x0000000c)
-
-#define BP_OCOTP_CTRL_WR_UNLOCK 16
-#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000
-#define BF_OCOTP_CTRL_WR_UNLOCK(v) \
- (((v) << 16) & BM_OCOTP_CTRL_WR_UNLOCK)
-#define BV_OCOTP_CTRL_WR_UNLOCK__KEY 0x3E77
-#define BP_OCOTP_CTRL_RSRVD2 14
-#define BM_OCOTP_CTRL_RSRVD2 0x0000C000
-#define BF_OCOTP_CTRL_RSRVD2(v) \
- (((v) << 14) & BM_OCOTP_CTRL_RSRVD2)
-#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000
-#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000
-#define BP_OCOTP_CTRL_RSRVD1 10
-#define BM_OCOTP_CTRL_RSRVD1 0x00000C00
-#define BF_OCOTP_CTRL_RSRVD1(v) \
- (((v) << 10) & BM_OCOTP_CTRL_RSRVD1)
-#define BM_OCOTP_CTRL_ERROR 0x00000200
-#define BM_OCOTP_CTRL_BUSY 0x00000100
-#define BP_OCOTP_CTRL_RSRVD0 6
-#define BM_OCOTP_CTRL_RSRVD0 0x000000C0
-#define BF_OCOTP_CTRL_RSRVD0(v) \
- (((v) << 6) & BM_OCOTP_CTRL_RSRVD0)
-#define BP_OCOTP_CTRL_ADDR 0
-#define BM_OCOTP_CTRL_ADDR 0x0000003F
-#define BF_OCOTP_CTRL_ADDR(v) \
- (((v) << 0) & BM_OCOTP_CTRL_ADDR)
-
-#define HW_OCOTP_DATA (0x00000010)
-
-#define BP_OCOTP_DATA_DATA 0
-#define BM_OCOTP_DATA_DATA 0xFFFFFFFF
-#define BF_OCOTP_DATA_DATA(v) (v)
-
-/*
- * multi-register-define name HW_OCOTP_CUSTn
- * base 0x00000020
- * count 4
- * offset 0x10
- */
-#define HW_OCOTP_CUSTn(n) (0x00000020 + (n) * 0x10)
-#define BP_OCOTP_CUSTn_BITS 0
-#define BM_OCOTP_CUSTn_BITS 0xFFFFFFFF
-#define BF_OCOTP_CUSTn_BITS(v) (v)
-
-/*
- * multi-register-define name HW_OCOTP_CRYPTOn
- * base 0x00000060
- * count 4
- * offset 0x10
- */
-#define HW_OCOTP_CRYPTOn(n) (0x00000060 + (n) * 0x10)
-#define BP_OCOTP_CRYPTOn_BITS 0
-#define BM_OCOTP_CRYPTOn_BITS 0xFFFFFFFF
-#define BF_OCOTP_CRYPTOn_BITS(v) (v)
-
-/*
- * multi-register-define name HW_OCOTP_HWCAPn
- * base 0x000000A0
- * count 6
- * offset 0x10
- */
-#define HW_OCOTP_HWCAPn(n) (0x000000a0 + (n) * 0x10)
-#define BP_OCOTP_HWCAPn_BITS 0
-#define BM_OCOTP_HWCAPn_BITS 0xFFFFFFFF
-#define BF_OCOTP_HWCAPn_BITS(v) (v)
-
-#define HW_OCOTP_SWCAP (0x00000100)
-
-#define BP_OCOTP_SWCAP_BITS 0
-#define BM_OCOTP_SWCAP_BITS 0xFFFFFFFF
-#define BF_OCOTP_SWCAP_BITS(v) (v)
-
-#define HW_OCOTP_CUSTCAP (0x00000110)
-
-#define BP_OCOTP_CUSTCAP_RSRVD1 3
-#define BM_OCOTP_CUSTCAP_RSRVD1 0xFFFFFFF8
-#define BF_OCOTP_CUSTCAP_RSRVD1(v) \
- (((v) << 3) & BM_OCOTP_CUSTCAP_RSRVD1)
-#define BM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT 0x00000004
-#define BM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT 0x00000002
-#define BM_OCOTP_CUSTCAP_RSRVD0 0x00000001
-
-#define HW_OCOTP_LOCK (0x00000120)
-
-#define BM_OCOTP_LOCK_ROM7 0x80000000
-#define BM_OCOTP_LOCK_ROM6 0x40000000
-#define BM_OCOTP_LOCK_ROM5 0x20000000
-#define BM_OCOTP_LOCK_ROM4 0x10000000
-#define BM_OCOTP_LOCK_ROM3 0x08000000
-#define BM_OCOTP_LOCK_ROM2 0x04000000
-#define BM_OCOTP_LOCK_ROM1 0x02000000
-#define BM_OCOTP_LOCK_ROM0 0x01000000
-#define BM_OCOTP_LOCK_HWSW_SHADOW_ALT 0x00800000
-#define BM_OCOTP_LOCK_CRYPTODCP_ALT 0x00400000
-#define BM_OCOTP_LOCK_CRYPTOKEY_ALT 0x00200000
-#define BM_OCOTP_LOCK_PIN 0x00100000
-#define BM_OCOTP_LOCK_OPS 0x00080000
-#define BM_OCOTP_LOCK_UN2 0x00040000
-#define BM_OCOTP_LOCK_UN1 0x00020000
-#define BM_OCOTP_LOCK_UN0 0x00010000
-#define BM_OCOTP_LOCK_SRK 0x00008000
-#define BP_OCOTP_LOCK_UNALLOCATED 12
-#define BM_OCOTP_LOCK_UNALLOCATED 0x00007000
-#define BF_OCOTP_LOCK_UNALLOCATED(v) \
- (((v) << 12) & BM_OCOTP_LOCK_UNALLOCATED)
-#define BM_OCOTP_LOCK_SRK_SHADOW 0x00000800
-#define BM_OCOTP_LOCK_ROM_SHADOW 0x00000400
-#define BM_OCOTP_LOCK_CUSTCAP 0x00000200
-#define BM_OCOTP_LOCK_HWSW 0x00000100
-#define BM_OCOTP_LOCK_CUSTCAP_SHADOW 0x00000080
-#define BM_OCOTP_LOCK_HWSW_SHADOW 0x00000040
-#define BM_OCOTP_LOCK_CRYPTODCP 0x00000020
-#define BM_OCOTP_LOCK_CRYPTOKEY 0x00000010
-#define BM_OCOTP_LOCK_CUST3 0x00000008
-#define BM_OCOTP_LOCK_CUST2 0x00000004
-#define BM_OCOTP_LOCK_CUST1 0x00000002
-#define BM_OCOTP_LOCK_CUST0 0x00000001
-
-/*
- * multi-register-define name HW_OCOTP_OPSn
- * base 0x00000130
- * count 4
- * offset 0x10
- */
-#define HW_OCOTP_OPSn(n) (0x00000130 + (n) * 0x10)
-#define BP_OCOTP_OPSn_BITS 0
-#define BM_OCOTP_OPSn_BITS 0xFFFFFFFF
-#define BF_OCOTP_OPSn_BITS(v) (v)
-
-/*
- * multi-register-define name HW_OCOTP_UNn
- * base 0x00000170
- * count 3
- * offset 0x10
- */
-#define HW_OCOTP_UNn(n) (0x00000170 + (n) * 0x10)
-#define BP_OCOTP_UNn_BITS 0
-#define BM_OCOTP_UNn_BITS 0xFFFFFFFF
-#define BF_OCOTP_UNn_BITS(v) (v)
-
-/*
- * multi-register-define name HW_OCOTP_ROMn
- * base 0x000001A0
- * count 8
- * offset 0x10
- */
-#define HW_OCOTP_ROMn(n) (0x000001a0 + (n) * 0x10)
-#define BP_OCOTP_ROMn_BOOT_MODE 24
-#define BM_OCOTP_ROMn_BOOT_MODE 0xFF000000
-#define BF_OCOTP_ROMn_BOOT_MODE(v) \
- (((v) << 24) & BM_OCOTP_ROMn_BOOT_MODE)
-#define BP_OCOTP_ROMn_SD_MMC_MODE 22
-#define BM_OCOTP_ROMn_SD_MMC_MODE 0x00C00000
-#define BF_OCOTP_ROMn_SD_MMC_MODE(v) \
- (((v) << 22) & BM_OCOTP_ROMn_SD_MMC_MODE)
-#define BP_OCOTP_ROMn_SD_POWER_GATE_GPIO 20
-#define BM_OCOTP_ROMn_SD_POWER_GATE_GPIO 0x00300000
-#define BF_OCOTP_ROMn_SD_POWER_GATE_GPIO(v) \
- (((v) << 20) & BM_OCOTP_ROMn_SD_POWER_GATE_GPIO)
-#define BP_OCOTP_ROMn_SD_POWER_UP_DELAY 14
-#define BM_OCOTP_ROMn_SD_POWER_UP_DELAY 0x000FC000
-#define BF_OCOTP_ROMn_SD_POWER_UP_DELAY(v) \
- (((v) << 14) & BM_OCOTP_ROMn_SD_POWER_UP_DELAY)
-#define BP_OCOTP_ROMn_SD_BUS_WIDTH 12
-#define BM_OCOTP_ROMn_SD_BUS_WIDTH 0x00003000
-#define BF_OCOTP_ROMn_SD_BUS_WIDTH(v) \
- (((v) << 12) & BM_OCOTP_ROMn_SD_BUS_WIDTH)
-#define BP_OCOTP_ROMn_SSP_SCK_INDEX 8
-#define BM_OCOTP_ROMn_SSP_SCK_INDEX 0x00000F00
-#define BF_OCOTP_ROMn_SSP_SCK_INDEX(v) \
- (((v) << 8) & BM_OCOTP_ROMn_SSP_SCK_INDEX)
-#define BM_OCOTP_ROMn_EMMC_USE_DDR 0x00000080
-#define BM_OCOTP_ROMn_DISABLE_SPI_NOR_FAST_READ 0x00000040
-#define BM_OCOTP_ROMn_ENABLE_USB_BOOT_SERIAL_NUM 0x00000020
-#define BM_OCOTP_ROMn_ENABLE_UNENCRYPTED_BOOT 0x00000010
-#define BM_OCOTP_ROMn_SD_MBR_BOOT 0x00000008
-#define BM_OCOTP_ROMn_RSRVD2 0x00000004
-#define BM_OCOTP_ROMn_RSRVD1 0x00000002
-#define BM_OCOTP_ROMn_RSRVD0 0x00000001
-
-/*
- * multi-register-define name HW_OCOTP_SRKn
- * base 0x00000220
- * count 8
- * offset 0x10
- */
-#define HW_OCOTP_SRKn(n) (0x00000220 + (n) * 0x10)
-#define BP_OCOTP_SRKn_BITS 0
-#define BM_OCOTP_SRKn_BITS 0xFFFFFFFF
-#define BF_OCOTP_SRKn_BITS(v) (v)
-
-#define HW_OCOTP_VERSION (0x000002a0)
-
-#define BP_OCOTP_VERSION_MAJOR 24
-#define BM_OCOTP_VERSION_MAJOR 0xFF000000
-#define BF_OCOTP_VERSION_MAJOR(v) \
- (((v) << 24) & BM_OCOTP_VERSION_MAJOR)
-#define BP_OCOTP_VERSION_MINOR 16
-#define BM_OCOTP_VERSION_MINOR 0x00FF0000
-#define BF_OCOTP_VERSION_MINOR(v) \
- (((v) << 16) & BM_OCOTP_VERSION_MINOR)
-#define BP_OCOTP_VERSION_STEP 0
-#define BM_OCOTP_VERSION_STEP 0x0000FFFF
-#define BF_OCOTP_VERSION_STEP(v) \
- (((v) << 0) & BM_OCOTP_VERSION_STEP)
-#endif /* __ARCH_ARM___OCOTP_H */
+++ /dev/null
-/*
- * Freescale PINCTRL Register Definitions
- *
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * This file is created by xml file. Don't Edit it.
- *
- * Xml Revision: 1.19
- * Template revision: 26195
- */
-
-#ifndef __ARCH_ARM___PINCTRL_H
-#define __ARCH_ARM___PINCTRL_H
-
-
-#define HW_PINCTRL_CTRL 0x00000000
-#define HW_PINCTRL_CTRL_SET 0x00000004
-#define HW_PINCTRL_CTRL_CLR 0x00000008
-#define HW_PINCTRL_CTRL_TOG 0x0000000c
-
-#define BM_PINCTRL_CTRL_SFTRST 0x80000000
-#define BM_PINCTRL_CTRL_CLKGATE 0x40000000
-#define BP_PINCTRL_CTRL_RSRVD2 25
-#define BM_PINCTRL_CTRL_RSRVD2 0x3E000000
-#define BF_PINCTRL_CTRL_RSRVD2(v) \
- (((v) << 25) & BM_PINCTRL_CTRL_RSRVD2)
-#define BM_PINCTRL_CTRL_PRESENT4 0x01000000
-#define BM_PINCTRL_CTRL_PRESENT3 0x00800000
-#define BM_PINCTRL_CTRL_PRESENT2 0x00400000
-#define BM_PINCTRL_CTRL_PRESENT1 0x00200000
-#define BM_PINCTRL_CTRL_PRESENT0 0x00100000
-#define BP_PINCTRL_CTRL_RSRVD1 5
-#define BM_PINCTRL_CTRL_RSRVD1 0x000FFFE0
-#define BF_PINCTRL_CTRL_RSRVD1(v) \
- (((v) << 5) & BM_PINCTRL_CTRL_RSRVD1)
-#define BM_PINCTRL_CTRL_IRQOUT4 0x00000010
-#define BM_PINCTRL_CTRL_IRQOUT3 0x00000008
-#define BM_PINCTRL_CTRL_IRQOUT2 0x00000004
-#define BM_PINCTRL_CTRL_IRQOUT1 0x00000002
-#define BM_PINCTRL_CTRL_IRQOUT0 0x00000001
-
-#define HW_PINCTRL_MUXSEL0 0x00000100
-#define HW_PINCTRL_MUXSEL0_SET 0x00000104
-#define HW_PINCTRL_MUXSEL0_CLR 0x00000108
-#define HW_PINCTRL_MUXSEL0_TOG 0x0000010c
-
-#define BP_PINCTRL_MUXSEL0_RSRVD0 16
-#define BM_PINCTRL_MUXSEL0_RSRVD0 0xFFFF0000
-#define BF_PINCTRL_MUXSEL0_RSRVD0(v) \
- (((v) << 16) & BM_PINCTRL_MUXSEL0_RSRVD0)
-#define BP_PINCTRL_MUXSEL0_BANK0_PIN07 14
-#define BM_PINCTRL_MUXSEL0_BANK0_PIN07 0x0000C000
-#define BF_PINCTRL_MUXSEL0_BANK0_PIN07(v) \
- (((v) << 14) & BM_PINCTRL_MUXSEL0_BANK0_PIN07)
-#define BP_PINCTRL_MUXSEL0_BANK0_PIN06 12
-#define BM_PINCTRL_MUXSEL0_BANK0_PIN06 0x00003000
-#define BF_PINCTRL_MUXSEL0_BANK0_PIN06(v) \
- (((v) << 12) & BM_PINCTRL_MUXSEL0_BANK0_PIN06)
-#define BP_PINCTRL_MUXSEL0_BANK0_PIN05 10
-#define BM_PINCTRL_MUXSEL0_BANK0_PIN05 0x00000C00
-#define BF_PINCTRL_MUXSEL0_BANK0_PIN05(v) \
- (((v) << 10) & BM_PINCTRL_MUXSEL0_BANK0_PIN05)
-#define BP_PINCTRL_MUXSEL0_BANK0_PIN04 8
-#define BM_PINCTRL_MUXSEL0_BANK0_PIN04 0x00000300
-#define BF_PINCTRL_MUXSEL0_BANK0_PIN04(v) \
- (((v) << 8) & BM_PINCTRL_MUXSEL0_BANK0_PIN04)
-#define BP_PINCTRL_MUXSEL0_BANK0_PIN03 6
-#define BM_PINCTRL_MUXSEL0_BANK0_PIN03 0x000000C0
-#define BF_PINCTRL_MUXSEL0_BANK0_PIN03(v) \
- (((v) << 6) & BM_PINCTRL_MUXSEL0_BANK0_PIN03)
-#define BP_PINCTRL_MUXSEL0_BANK0_PIN02 4
-#define BM_PINCTRL_MUXSEL0_BANK0_PIN02 0x00000030
-#define BF_PINCTRL_MUXSEL0_BANK0_PIN02(v) \
- (((v) << 4) & BM_PINCTRL_MUXSEL0_BANK0_PIN02)
-#define BP_PINCTRL_MUXSEL0_BANK0_PIN01 2
-#define BM_PINCTRL_MUXSEL0_BANK0_PIN01 0x0000000C
-#define BF_PINCTRL_MUXSEL0_BANK0_PIN01(v) \
- (((v) << 2) & BM_PINCTRL_MUXSEL0_BANK0_PIN01)
-#define BP_PINCTRL_MUXSEL0_BANK0_PIN00 0
-#define BM_PINCTRL_MUXSEL0_BANK0_PIN00 0x00000003
-#define BF_PINCTRL_MUXSEL0_BANK0_PIN00(v) \
- (((v) << 0) & BM_PINCTRL_MUXSEL0_BANK0_PIN00)
-
-#define HW_PINCTRL_MUXSEL1 0x00000110
-#define HW_PINCTRL_MUXSEL1_SET 0x00000114
-#define HW_PINCTRL_MUXSEL1_CLR 0x00000118
-#define HW_PINCTRL_MUXSEL1_TOG 0x0000011c
-
-#define BP_PINCTRL_MUXSEL1_RSRVD0 26
-#define BM_PINCTRL_MUXSEL1_RSRVD0 0xFC000000
-#define BF_PINCTRL_MUXSEL1_RSRVD0(v) \
- (((v) << 26) & BM_PINCTRL_MUXSEL1_RSRVD0)
-#define BP_PINCTRL_MUXSEL1_BANK0_PIN28 24
-#define BM_PINCTRL_MUXSEL1_BANK0_PIN28 0x03000000
-#define BF_PINCTRL_MUXSEL1_BANK0_PIN28(v) \
- (((v) << 24) & BM_PINCTRL_MUXSEL1_BANK0_PIN28)
-#define BP_PINCTRL_MUXSEL1_BANK0_PIN27 22
-#define BM_PINCTRL_MUXSEL1_BANK0_PIN27 0x00C00000
-#define BF_PINCTRL_MUXSEL1_BANK0_PIN27(v) \
- (((v) << 22) & BM_PINCTRL_MUXSEL1_BANK0_PIN27)
-#define BP_PINCTRL_MUXSEL1_BANK0_PIN26 20
-#define BM_PINCTRL_MUXSEL1_BANK0_PIN26 0x00300000
-#define BF_PINCTRL_MUXSEL1_BANK0_PIN26(v) \
- (((v) << 20) & BM_PINCTRL_MUXSEL1_BANK0_PIN26)
-#define BP_PINCTRL_MUXSEL1_BANK0_PIN25 18
-#define BM_PINCTRL_MUXSEL1_BANK0_PIN25 0x000C0000
-#define BF_PINCTRL_MUXSEL1_BANK0_PIN25(v) \
- (((v) << 18) & BM_PINCTRL_MUXSEL1_BANK0_PIN25)
-#define BP_PINCTRL_MUXSEL1_BANK0_PIN24 16
-#define BM_PINCTRL_MUXSEL1_BANK0_PIN24 0x00030000
-#define BF_PINCTRL_MUXSEL1_BANK0_PIN24(v) \
- (((v) << 16) & BM_PINCTRL_MUXSEL1_BANK0_PIN24)
-#define BP_PINCTRL_MUXSEL1_BANK0_PIN23 14
-#define BM_PINCTRL_MUXSEL1_BANK0_PIN23 0x0000C000
-#define BF_PINCTRL_MUXSEL1_BANK0_PIN23(v) \
- (((v) << 14) & BM_PINCTRL_MUXSEL1_BANK0_PIN23)
-#define BP_PINCTRL_MUXSEL1_BANK0_PIN22 12
-#define BM_PINCTRL_MUXSEL1_BANK0_PIN22 0x00003000
-#define BF_PINCTRL_MUXSEL1_BANK0_PIN22(v) \
- (((v) << 12) & BM_PINCTRL_MUXSEL1_BANK0_PIN22)
-#define BP_PINCTRL_MUXSEL1_BANK0_PIN21 10
-#define BM_PINCTRL_MUXSEL1_BANK0_PIN21 0x00000C00
-#define BF_PINCTRL_MUXSEL1_BANK0_PIN21(v) \
- (((v) << 10) & BM_PINCTRL_MUXSEL1_BANK0_PIN21)
-#define BP_PINCTRL_MUXSEL1_BANK0_PIN20 8
-#define BM_PINCTRL_MUXSEL1_BANK0_PIN20 0x00000300
-#define BF_PINCTRL_MUXSEL1_BANK0_PIN20(v) \
- (((v) << 8) & BM_PINCTRL_MUXSEL1_BANK0_PIN20)
-#define BP_PINCTRL_MUXSEL1_BANK0_PIN19 6
-#define BM_PINCTRL_MUXSEL1_BANK0_PIN19 0x000000C0
-#define BF_PINCTRL_MUXSEL1_BANK0_PIN19(v) \
- (((v) << 6) & BM_PINCTRL_MUXSEL1_BANK0_PIN19)
-#define BP_PINCTRL_MUXSEL1_BANK0_PIN18 4
-#define BM_PINCTRL_MUXSEL1_BANK0_PIN18 0x00000030
-#define BF_PINCTRL_MUXSEL1_BANK0_PIN18(v) \
- (((v) << 4) & BM_PINCTRL_MUXSEL1_BANK0_PIN18)
-#define BP_PINCTRL_MUXSEL1_BANK0_PIN17 2
-#define BM_PINCTRL_MUXSEL1_BANK0_PIN17 0x0000000C
-#define BF_PINCTRL_MUXSEL1_BANK0_PIN17(v) \
- (((v) << 2) & BM_PINCTRL_MUXSEL1_BANK0_PIN17)
-#define BP_PINCTRL_MUXSEL1_BANK0_PIN16 0
-#define BM_PINCTRL_MUXSEL1_BANK0_PIN16 0x00000003
-#define BF_PINCTRL_MUXSEL1_BANK0_PIN16(v) \
- (((v) << 0) & BM_PINCTRL_MUXSEL1_BANK0_PIN16)
-
-#define HW_PINCTRL_MUXSEL2 0x00000120
-#define HW_PINCTRL_MUXSEL2_SET 0x00000124
-#define HW_PINCTRL_MUXSEL2_CLR 0x00000128
-#define HW_PINCTRL_MUXSEL2_TOG 0x0000012c
-
-#define BP_PINCTRL_MUXSEL2_BANK1_PIN15 30
-#define BM_PINCTRL_MUXSEL2_BANK1_PIN15 0xC0000000
-#define BF_PINCTRL_MUXSEL2_BANK1_PIN15(v) \
- (((v) << 30) & BM_PINCTRL_MUXSEL2_BANK1_PIN15)
-#define BP_PINCTRL_MUXSEL2_BANK1_PIN14 28
-#define BM_PINCTRL_MUXSEL2_BANK1_PIN14 0x30000000
-#define BF_PINCTRL_MUXSEL2_BANK1_PIN14(v) \
- (((v) << 28) & BM_PINCTRL_MUXSEL2_BANK1_PIN14)
-#define BP_PINCTRL_MUXSEL2_BANK1_PIN13 26
-#define BM_PINCTRL_MUXSEL2_BANK1_PIN13 0x0C000000
-#define BF_PINCTRL_MUXSEL2_BANK1_PIN13(v) \
- (((v) << 26) & BM_PINCTRL_MUXSEL2_BANK1_PIN13)
-#define BP_PINCTRL_MUXSEL2_BANK1_PIN12 24
-#define BM_PINCTRL_MUXSEL2_BANK1_PIN12 0x03000000
-#define BF_PINCTRL_MUXSEL2_BANK1_PIN12(v) \
- (((v) << 24) & BM_PINCTRL_MUXSEL2_BANK1_PIN12)
-#define BP_PINCTRL_MUXSEL2_BANK1_PIN11 22
-#define BM_PINCTRL_MUXSEL2_BANK1_PIN11 0x00C00000
-#define BF_PINCTRL_MUXSEL2_BANK1_PIN11(v) \
- (((v) << 22) & BM_PINCTRL_MUXSEL2_BANK1_PIN11)
-#define BP_PINCTRL_MUXSEL2_BANK1_PIN10 20
-#define BM_PINCTRL_MUXSEL2_BANK1_PIN10 0x00300000
-#define BF_PINCTRL_MUXSEL2_BANK1_PIN10(v) \
- (((v) << 20) & BM_PINCTRL_MUXSEL2_BANK1_PIN10)
-#define BP_PINCTRL_MUXSEL2_BANK1_PIN09 18
-#define BM_PINCTRL_MUXSEL2_BANK1_PIN09 0x000C0000
-#define BF_PINCTRL_MUXSEL2_BANK1_PIN09(v) \
- (((v) << 18) & BM_PINCTRL_MUXSEL2_BANK1_PIN09)
-#define BP_PINCTRL_MUXSEL2_BANK1_PIN08 16
-#define BM_PINCTRL_MUXSEL2_BANK1_PIN08 0x00030000
-#define BF_PINCTRL_MUXSEL2_BANK1_PIN08(v) \
- (((v) << 16) & BM_PINCTRL_MUXSEL2_BANK1_PIN08)
-#define BP_PINCTRL_MUXSEL2_BANK1_PIN07 14
-#define BM_PINCTRL_MUXSEL2_BANK1_PIN07 0x0000C000
-#define BF_PINCTRL_MUXSEL2_BANK1_PIN07(v) \
- (((v) << 14) & BM_PINCTRL_MUXSEL2_BANK1_PIN07)
-#define BP_PINCTRL_MUXSEL2_BANK1_PIN06 12
-#define BM_PINCTRL_MUXSEL2_BANK1_PIN06 0x00003000
-#define BF_PINCTRL_MUXSEL2_BANK1_PIN06(v) \
- (((v) << 12) & BM_PINCTRL_MUXSEL2_BANK1_PIN06)
-#define BP_PINCTRL_MUXSEL2_BANK1_PIN05 10
-#define BM_PINCTRL_MUXSEL2_BANK1_PIN05 0x00000C00
-#define BF_PINCTRL_MUXSEL2_BANK1_PIN05(v) \
- (((v) << 10) & BM_PINCTRL_MUXSEL2_BANK1_PIN05)
-#define BP_PINCTRL_MUXSEL2_BANK1_PIN04 8
-#define BM_PINCTRL_MUXSEL2_BANK1_PIN04 0x00000300
-#define BF_PINCTRL_MUXSEL2_BANK1_PIN04(v) \
- (((v) << 8) & BM_PINCTRL_MUXSEL2_BANK1_PIN04)
-#define BP_PINCTRL_MUXSEL2_BANK1_PIN03 6
-#define BM_PINCTRL_MUXSEL2_BANK1_PIN03 0x000000C0
-#define BF_PINCTRL_MUXSEL2_BANK1_PIN03(v) \
- (((v) << 6) & BM_PINCTRL_MUXSEL2_BANK1_PIN03)
-#define BP_PINCTRL_MUXSEL2_BANK1_PIN02 4
-#define BM_PINCTRL_MUXSEL2_BANK1_PIN02 0x00000030
-#define BF_PINCTRL_MUXSEL2_BANK1_PIN02(v) \
- (((v) << 4) & BM_PINCTRL_MUXSEL2_BANK1_PIN02)
-#define BP_PINCTRL_MUXSEL2_BANK1_PIN01 2
-#define BM_PINCTRL_MUXSEL2_BANK1_PIN01 0x0000000C
-#define BF_PINCTRL_MUXSEL2_BANK1_PIN01(v) \
- (((v) << 2) & BM_PINCTRL_MUXSEL2_BANK1_PIN01)
-#define BP_PINCTRL_MUXSEL2_BANK1_PIN00 0
-#define BM_PINCTRL_MUXSEL2_BANK1_PIN00 0x00000003
-#define BF_PINCTRL_MUXSEL2_BANK1_PIN00(v) \
- (((v) << 0) & BM_PINCTRL_MUXSEL2_BANK1_PIN00)
-
-#define HW_PINCTRL_MUXSEL3 0x00000130
-#define HW_PINCTRL_MUXSEL3_SET 0x00000134
-#define HW_PINCTRL_MUXSEL3_CLR 0x00000138
-#define HW_PINCTRL_MUXSEL3_TOG 0x0000013c
-
-#define BP_PINCTRL_MUXSEL3_BANK1_PIN31 30
-#define BM_PINCTRL_MUXSEL3_BANK1_PIN31 0xC0000000
-#define BF_PINCTRL_MUXSEL3_BANK1_PIN31(v) \
- (((v) << 30) & BM_PINCTRL_MUXSEL3_BANK1_PIN31)
-#define BP_PINCTRL_MUXSEL3_BANK1_PIN30 28
-#define BM_PINCTRL_MUXSEL3_BANK1_PIN30 0x30000000
-#define BF_PINCTRL_MUXSEL3_BANK1_PIN30(v) \
- (((v) << 28) & BM_PINCTRL_MUXSEL3_BANK1_PIN30)
-#define BP_PINCTRL_MUXSEL3_BANK1_PIN29 26
-#define BM_PINCTRL_MUXSEL3_BANK1_PIN29 0x0C000000
-#define BF_PINCTRL_MUXSEL3_BANK1_PIN29(v) \
- (((v) << 26) & BM_PINCTRL_MUXSEL3_BANK1_PIN29)
-#define BP_PINCTRL_MUXSEL3_BANK1_PIN28 24
-#define BM_PINCTRL_MUXSEL3_BANK1_PIN28 0x03000000
-#define BF_PINCTRL_MUXSEL3_BANK1_PIN28(v) \
- (((v) << 24) & BM_PINCTRL_MUXSEL3_BANK1_PIN28)
-#define BP_PINCTRL_MUXSEL3_BANK1_PIN27 22
-#define BM_PINCTRL_MUXSEL3_BANK1_PIN27 0x00C00000
-#define BF_PINCTRL_MUXSEL3_BANK1_PIN27(v) \
- (((v) << 22) & BM_PINCTRL_MUXSEL3_BANK1_PIN27)
-#define BP_PINCTRL_MUXSEL3_BANK1_PIN26 20
-#define BM_PINCTRL_MUXSEL3_BANK1_PIN26 0x00300000
-#define BF_PINCTRL_MUXSEL3_BANK1_PIN26(v) \
- (((v) << 20) & BM_PINCTRL_MUXSEL3_BANK1_PIN26)
-#define BP_PINCTRL_MUXSEL3_BANK1_PIN25 18
-#define BM_PINCTRL_MUXSEL3_BANK1_PIN25 0x000C0000
-#define BF_PINCTRL_MUXSEL3_BANK1_PIN25(v) \
- (((v) << 18) & BM_PINCTRL_MUXSEL3_BANK1_PIN25)
-#define BP_PINCTRL_MUXSEL3_BANK1_PIN24 16
-#define BM_PINCTRL_MUXSEL3_BANK1_PIN24 0x00030000
-#define BF_PINCTRL_MUXSEL3_BANK1_PIN24(v) \
- (((v) << 16) & BM_PINCTRL_MUXSEL3_BANK1_PIN24)
-#define BP_PINCTRL_MUXSEL3_BANK1_PIN23 14
-#define BM_PINCTRL_MUXSEL3_BANK1_PIN23 0x0000C000
-#define BF_PINCTRL_MUXSEL3_BANK1_PIN23(v) \
- (((v) << 14) & BM_PINCTRL_MUXSEL3_BANK1_PIN23)
-#define BP_PINCTRL_MUXSEL3_BANK1_PIN22 12
-#define BM_PINCTRL_MUXSEL3_BANK1_PIN22 0x00003000
-#define BF_PINCTRL_MUXSEL3_BANK1_PIN22(v) \
- (((v) << 12) & BM_PINCTRL_MUXSEL3_BANK1_PIN22)
-#define BP_PINCTRL_MUXSEL3_BANK1_PIN21 10
-#define BM_PINCTRL_MUXSEL3_BANK1_PIN21 0x00000C00
-#define BF_PINCTRL_MUXSEL3_BANK1_PIN21(v) \
- (((v) << 10) & BM_PINCTRL_MUXSEL3_BANK1_PIN21)
-#define BP_PINCTRL_MUXSEL3_BANK1_PIN20 8
-#define BM_PINCTRL_MUXSEL3_BANK1_PIN20 0x00000300
-#define BF_PINCTRL_MUXSEL3_BANK1_PIN20(v) \
- (((v) << 8) & BM_PINCTRL_MUXSEL3_BANK1_PIN20)
-#define BP_PINCTRL_MUXSEL3_BANK1_PIN19 6
-#define BM_PINCTRL_MUXSEL3_BANK1_PIN19 0x000000C0
-#define BF_PINCTRL_MUXSEL3_BANK1_PIN19(v) \
- (((v) << 6) & BM_PINCTRL_MUXSEL3_BANK1_PIN19)
-#define BP_PINCTRL_MUXSEL3_BANK1_PIN18 4
-#define BM_PINCTRL_MUXSEL3_BANK1_PIN18 0x00000030
-#define BF_PINCTRL_MUXSEL3_BANK1_PIN18(v) \
- (((v) << 4) & BM_PINCTRL_MUXSEL3_BANK1_PIN18)
-#define BP_PINCTRL_MUXSEL3_BANK1_PIN17 2
-#define BM_PINCTRL_MUXSEL3_BANK1_PIN17 0x0000000C
-#define BF_PINCTRL_MUXSEL3_BANK1_PIN17(v) \
- (((v) << 2) & BM_PINCTRL_MUXSEL3_BANK1_PIN17)
-#define BP_PINCTRL_MUXSEL3_BANK1_PIN16 0
-#define BM_PINCTRL_MUXSEL3_BANK1_PIN16 0x00000003
-#define BF_PINCTRL_MUXSEL3_BANK1_PIN16(v) \
- (((v) << 0) & BM_PINCTRL_MUXSEL3_BANK1_PIN16)
-
-#define HW_PINCTRL_MUXSEL4 0x00000140
-#define HW_PINCTRL_MUXSEL4_SET 0x00000144
-#define HW_PINCTRL_MUXSEL4_CLR 0x00000148
-#define HW_PINCTRL_MUXSEL4_TOG 0x0000014c
-
-#define BP_PINCTRL_MUXSEL4_BANK2_PIN15 30
-#define BM_PINCTRL_MUXSEL4_BANK2_PIN15 0xC0000000
-#define BF_PINCTRL_MUXSEL4_BANK2_PIN15(v) \
- (((v) << 30) & BM_PINCTRL_MUXSEL4_BANK2_PIN15)
-#define BP_PINCTRL_MUXSEL4_BANK2_PIN14 28
-#define BM_PINCTRL_MUXSEL4_BANK2_PIN14 0x30000000
-#define BF_PINCTRL_MUXSEL4_BANK2_PIN14(v) \
- (((v) << 28) & BM_PINCTRL_MUXSEL4_BANK2_PIN14)
-#define BP_PINCTRL_MUXSEL4_BANK2_PIN13 26
-#define BM_PINCTRL_MUXSEL4_BANK2_PIN13 0x0C000000
-#define BF_PINCTRL_MUXSEL4_BANK2_PIN13(v) \
- (((v) << 26) & BM_PINCTRL_MUXSEL4_BANK2_PIN13)
-#define BP_PINCTRL_MUXSEL4_BANK2_PIN12 24
-#define BM_PINCTRL_MUXSEL4_BANK2_PIN12 0x03000000
-#define BF_PINCTRL_MUXSEL4_BANK2_PIN12(v) \
- (((v) << 24) & BM_PINCTRL_MUXSEL4_BANK2_PIN12)
-#define BP_PINCTRL_MUXSEL4_RSRVD0 22
-#define BM_PINCTRL_MUXSEL4_RSRVD0 0x00C00000
-#define BF_PINCTRL_MUXSEL4_RSRVD0(v) \
- (((v) << 22) & BM_PINCTRL_MUXSEL4_RSRVD0)
-#define BP_PINCTRL_MUXSEL4_BANK2_PIN10 20
-#define BM_PINCTRL_MUXSEL4_BANK2_PIN10 0x00300000
-#define BF_PINCTRL_MUXSEL4_BANK2_PIN10(v) \
- (((v) << 20) & BM_PINCTRL_MUXSEL4_BANK2_PIN10)
-#define BP_PINCTRL_MUXSEL4_BANK2_PIN09 18
-#define BM_PINCTRL_MUXSEL4_BANK2_PIN09 0x000C0000
-#define BF_PINCTRL_MUXSEL4_BANK2_PIN09(v) \
- (((v) << 18) & BM_PINCTRL_MUXSEL4_BANK2_PIN09)
-#define BP_PINCTRL_MUXSEL4_BANK2_PIN08 16
-#define BM_PINCTRL_MUXSEL4_BANK2_PIN08 0x00030000
-#define BF_PINCTRL_MUXSEL4_BANK2_PIN08(v) \
- (((v) << 16) & BM_PINCTRL_MUXSEL4_BANK2_PIN08)
-#define BP_PINCTRL_MUXSEL4_BANK2_PIN07 14
-#define BM_PINCTRL_MUXSEL4_BANK2_PIN07 0x0000C000
-#define BF_PINCTRL_MUXSEL4_BANK2_PIN07(v) \
- (((v) << 14) & BM_PINCTRL_MUXSEL4_BANK2_PIN07)
-#define BP_PINCTRL_MUXSEL4_BANK2_PIN06 12
-#define BM_PINCTRL_MUXSEL4_BANK2_PIN06 0x00003000
-#define BF_PINCTRL_MUXSEL4_BANK2_PIN06(v) \
- (((v) << 12) & BM_PINCTRL_MUXSEL4_BANK2_PIN06)
-#define BP_PINCTRL_MUXSEL4_BANK2_PIN05 10
-#define BM_PINCTRL_MUXSEL4_BANK2_PIN05 0x00000C00
-#define BF_PINCTRL_MUXSEL4_BANK2_PIN05(v) \
- (((v) << 10) & BM_PINCTRL_MUXSEL4_BANK2_PIN05)
-#define BP_PINCTRL_MUXSEL4_BANK2_PIN04 8
-#define BM_PINCTRL_MUXSEL4_BANK2_PIN04 0x00000300
-#define BF_PINCTRL_MUXSEL4_BANK2_PIN04(v) \
- (((v) << 8) & BM_PINCTRL_MUXSEL4_BANK2_PIN04)
-#define BP_PINCTRL_MUXSEL4_BANK2_PIN03 6
-#define BM_PINCTRL_MUXSEL4_BANK2_PIN03 0x000000C0
-#define BF_PINCTRL_MUXSEL4_BANK2_PIN03(v) \
- (((v) << 6) & BM_PINCTRL_MUXSEL4_BANK2_PIN03)
-#define BP_PINCTRL_MUXSEL4_BANK2_PIN02 4
-#define BM_PINCTRL_MUXSEL4_BANK2_PIN02 0x00000030
-#define BF_PINCTRL_MUXSEL4_BANK2_PIN02(v) \
- (((v) << 4) & BM_PINCTRL_MUXSEL4_BANK2_PIN02)
-#define BP_PINCTRL_MUXSEL4_BANK2_PIN01 2
-#define BM_PINCTRL_MUXSEL4_BANK2_PIN01 0x0000000C
-#define BF_PINCTRL_MUXSEL4_BANK2_PIN01(v) \
- (((v) << 2) & BM_PINCTRL_MUXSEL4_BANK2_PIN01)
-#define BP_PINCTRL_MUXSEL4_BANK2_PIN00 0
-#define BM_PINCTRL_MUXSEL4_BANK2_PIN00 0x00000003
-#define BF_PINCTRL_MUXSEL4_BANK2_PIN00(v) \
- (((v) << 0) & BM_PINCTRL_MUXSEL4_BANK2_PIN00)
-
-#define HW_PINCTRL_MUXSEL5 0x00000150
-#define HW_PINCTRL_MUXSEL5_SET 0x00000154
-#define HW_PINCTRL_MUXSEL5_CLR 0x00000158
-#define HW_PINCTRL_MUXSEL5_TOG 0x0000015c
-
-#define BP_PINCTRL_MUXSEL5_RSRVD1 24
-#define BM_PINCTRL_MUXSEL5_RSRVD1 0xFF000000
-#define BF_PINCTRL_MUXSEL5_RSRVD1(v) \
- (((v) << 24) & BM_PINCTRL_MUXSEL5_RSRVD1)
-#define BP_PINCTRL_MUXSEL5_BANK2_PIN27 22
-#define BM_PINCTRL_MUXSEL5_BANK2_PIN27 0x00C00000
-#define BF_PINCTRL_MUXSEL5_BANK2_PIN27(v) \
- (((v) << 22) & BM_PINCTRL_MUXSEL5_BANK2_PIN27)
-#define BP_PINCTRL_MUXSEL5_BANK2_PIN26 20
-#define BM_PINCTRL_MUXSEL5_BANK2_PIN26 0x00300000
-#define BF_PINCTRL_MUXSEL5_BANK2_PIN26(v) \
- (((v) << 20) & BM_PINCTRL_MUXSEL5_BANK2_PIN26)
-#define BP_PINCTRL_MUXSEL5_BANK2_PIN25 18
-#define BM_PINCTRL_MUXSEL5_BANK2_PIN25 0x000C0000
-#define BF_PINCTRL_MUXSEL5_BANK2_PIN25(v) \
- (((v) << 18) & BM_PINCTRL_MUXSEL5_BANK2_PIN25)
-#define BP_PINCTRL_MUXSEL5_BANK2_PIN24 16
-#define BM_PINCTRL_MUXSEL5_BANK2_PIN24 0x00030000
-#define BF_PINCTRL_MUXSEL5_BANK2_PIN24(v) \
- (((v) << 16) & BM_PINCTRL_MUXSEL5_BANK2_PIN24)
-#define BP_PINCTRL_MUXSEL5_RSRVD0 12
-#define BM_PINCTRL_MUXSEL5_RSRVD0 0x0000F000
-#define BF_PINCTRL_MUXSEL5_RSRVD0(v) \
- (((v) << 12) & BM_PINCTRL_MUXSEL5_RSRVD0)
-#define BP_PINCTRL_MUXSEL5_BANK2_PIN21 10
-#define BM_PINCTRL_MUXSEL5_BANK2_PIN21 0x00000C00
-#define BF_PINCTRL_MUXSEL5_BANK2_PIN21(v) \
- (((v) << 10) & BM_PINCTRL_MUXSEL5_BANK2_PIN21)
-#define BP_PINCTRL_MUXSEL5_BANK2_PIN20 8
-#define BM_PINCTRL_MUXSEL5_BANK2_PIN20 0x00000300
-#define BF_PINCTRL_MUXSEL5_BANK2_PIN20(v) \
- (((v) << 8) & BM_PINCTRL_MUXSEL5_BANK2_PIN20)
-#define BP_PINCTRL_MUXSEL5_BANK2_PIN19 6
-#define BM_PINCTRL_MUXSEL5_BANK2_PIN19 0x000000C0
-#define BF_PINCTRL_MUXSEL5_BANK2_PIN19(v) \
- (((v) << 6) & BM_PINCTRL_MUXSEL5_BANK2_PIN19)
-#define BP_PINCTRL_MUXSEL5_BANK2_PIN18 4
-#define BM_PINCTRL_MUXSEL5_BANK2_PIN18 0x00000030
-#define BF_PINCTRL_MUXSEL5_BANK2_PIN18(v) \
- (((v) << 4) & BM_PINCTRL_MUXSEL5_BANK2_PIN18)
-#define BP_PINCTRL_MUXSEL5_BANK2_PIN17 2
-#define BM_PINCTRL_MUXSEL5_BANK2_PIN17 0x0000000C
-#define BF_PINCTRL_MUXSEL5_BANK2_PIN17(v) \
- (((v) << 2) & BM_PINCTRL_MUXSEL5_BANK2_PIN17)
-#define BP_PINCTRL_MUXSEL5_BANK2_PIN16 0
-#define BM_PINCTRL_MUXSEL5_BANK2_PIN16 0x00000003
-#define BF_PINCTRL_MUXSEL5_BANK2_PIN16(v) \
- (((v) << 0) & BM_PINCTRL_MUXSEL5_BANK2_PIN16)
-
-#define HW_PINCTRL_MUXSEL6 0x00000160
-#define HW_PINCTRL_MUXSEL6_SET 0x00000164
-#define HW_PINCTRL_MUXSEL6_CLR 0x00000168
-#define HW_PINCTRL_MUXSEL6_TOG 0x0000016c
-
-#define BP_PINCTRL_MUXSEL6_BANK3_PIN15 30
-#define BM_PINCTRL_MUXSEL6_BANK3_PIN15 0xC0000000
-#define BF_PINCTRL_MUXSEL6_BANK3_PIN15(v) \
- (((v) << 30) & BM_PINCTRL_MUXSEL6_BANK3_PIN15)
-#define BP_PINCTRL_MUXSEL6_BANK3_PIN14 28
-#define BM_PINCTRL_MUXSEL6_BANK3_PIN14 0x30000000
-#define BF_PINCTRL_MUXSEL6_BANK3_PIN14(v) \
- (((v) << 28) & BM_PINCTRL_MUXSEL6_BANK3_PIN14)
-#define BP_PINCTRL_MUXSEL6_BANK3_PIN13 26
-#define BM_PINCTRL_MUXSEL6_BANK3_PIN13 0x0C000000
-#define BF_PINCTRL_MUXSEL6_BANK3_PIN13(v) \
- (((v) << 26) & BM_PINCTRL_MUXSEL6_BANK3_PIN13)
-#define BP_PINCTRL_MUXSEL6_BANK3_PIN12 24
-#define BM_PINCTRL_MUXSEL6_BANK3_PIN12 0x03000000
-#define BF_PINCTRL_MUXSEL6_BANK3_PIN12(v) \
- (((v) << 24) & BM_PINCTRL_MUXSEL6_BANK3_PIN12)
-#define BP_PINCTRL_MUXSEL6_BANK3_PIN11 22
-#define BM_PINCTRL_MUXSEL6_BANK3_PIN11 0x00C00000
-#define BF_PINCTRL_MUXSEL6_BANK3_PIN11(v) \
- (((v) << 22) & BM_PINCTRL_MUXSEL6_BANK3_PIN11)
-#define BP_PINCTRL_MUXSEL6_BANK3_PIN10 20
-#define BM_PINCTRL_MUXSEL6_BANK3_PIN10 0x00300000
-#define BF_PINCTRL_MUXSEL6_BANK3_PIN10(v) \
- (((v) << 20) & BM_PINCTRL_MUXSEL6_BANK3_PIN10)
-#define BP_PINCTRL_MUXSEL6_BANK3_PIN09 18
-#define BM_PINCTRL_MUXSEL6_BANK3_PIN09 0x000C0000
-#define BF_PINCTRL_MUXSEL6_BANK3_PIN09(v) \
- (((v) << 18) & BM_PINCTRL_MUXSEL6_BANK3_PIN09)
-#define BP_PINCTRL_MUXSEL6_BANK3_PIN08 16
-#define BM_PINCTRL_MUXSEL6_BANK3_PIN08 0x00030000
-#define BF_PINCTRL_MUXSEL6_BANK3_PIN08(v) \
- (((v) << 16) & BM_PINCTRL_MUXSEL6_BANK3_PIN08)
-#define BP_PINCTRL_MUXSEL6_BANK3_PIN07 14
-#define BM_PINCTRL_MUXSEL6_BANK3_PIN07 0x0000C000
-#define BF_PINCTRL_MUXSEL6_BANK3_PIN07(v) \
- (((v) << 14) & BM_PINCTRL_MUXSEL6_BANK3_PIN07)
-#define BP_PINCTRL_MUXSEL6_BANK3_PIN06 12
-#define BM_PINCTRL_MUXSEL6_BANK3_PIN06 0x00003000
-#define BF_PINCTRL_MUXSEL6_BANK3_PIN06(v) \
- (((v) << 12) & BM_PINCTRL_MUXSEL6_BANK3_PIN06)
-#define BP_PINCTRL_MUXSEL6_BANK3_PIN05 10
-#define BM_PINCTRL_MUXSEL6_BANK3_PIN05 0x00000C00
-#define BF_PINCTRL_MUXSEL6_BANK3_PIN05(v) \
- (((v) << 10) & BM_PINCTRL_MUXSEL6_BANK3_PIN05)
-#define BP_PINCTRL_MUXSEL6_BANK3_PIN04 8
-#define BM_PINCTRL_MUXSEL6_BANK3_PIN04 0x00000300
-#define BF_PINCTRL_MUXSEL6_BANK3_PIN04(v) \
- (((v) << 8) & BM_PINCTRL_MUXSEL6_BANK3_PIN04)
-#define BP_PINCTRL_MUXSEL6_BANK3_PIN03 6
-#define BM_PINCTRL_MUXSEL6_BANK3_PIN03 0x000000C0
-#define BF_PINCTRL_MUXSEL6_BANK3_PIN03(v) \
- (((v) << 6) & BM_PINCTRL_MUXSEL6_BANK3_PIN03)
-#define BP_PINCTRL_MUXSEL6_BANK3_PIN02 4
-#define BM_PINCTRL_MUXSEL6_BANK3_PIN02 0x00000030
-#define BF_PINCTRL_MUXSEL6_BANK3_PIN02(v) \
- (((v) << 4) & BM_PINCTRL_MUXSEL6_BANK3_PIN02)
-#define BP_PINCTRL_MUXSEL6_BANK3_PIN01 2
-#define BM_PINCTRL_MUXSEL6_BANK3_PIN01 0x0000000C
-#define BF_PINCTRL_MUXSEL6_BANK3_PIN01(v) \
- (((v) << 2) & BM_PINCTRL_MUXSEL6_BANK3_PIN01)
-#define BP_PINCTRL_MUXSEL6_BANK3_PIN00 0
-#define BM_PINCTRL_MUXSEL6_BANK3_PIN00 0x00000003
-#define BF_PINCTRL_MUXSEL6_BANK3_PIN00(v) \
- (((v) << 0) & BM_PINCTRL_MUXSEL6_BANK3_PIN00)
-
-#define HW_PINCTRL_MUXSEL7 0x00000170
-#define HW_PINCTRL_MUXSEL7_SET 0x00000174
-#define HW_PINCTRL_MUXSEL7_CLR 0x00000178
-#define HW_PINCTRL_MUXSEL7_TOG 0x0000017c
-
-#define BP_PINCTRL_MUXSEL7_RSRVD1 30
-#define BM_PINCTRL_MUXSEL7_RSRVD1 0xC0000000
-#define BF_PINCTRL_MUXSEL7_RSRVD1(v) \
- (((v) << 30) & BM_PINCTRL_MUXSEL7_RSRVD1)
-#define BP_PINCTRL_MUXSEL7_BANK3_PIN30 28
-#define BM_PINCTRL_MUXSEL7_BANK3_PIN30 0x30000000
-#define BF_PINCTRL_MUXSEL7_BANK3_PIN30(v) \
- (((v) << 28) & BM_PINCTRL_MUXSEL7_BANK3_PIN30)
-#define BP_PINCTRL_MUXSEL7_BANK3_PIN29 26
-#define BM_PINCTRL_MUXSEL7_BANK3_PIN29 0x0C000000
-#define BF_PINCTRL_MUXSEL7_BANK3_PIN29(v) \
- (((v) << 26) & BM_PINCTRL_MUXSEL7_BANK3_PIN29)
-#define BP_PINCTRL_MUXSEL7_BANK3_PIN28 24
-#define BM_PINCTRL_MUXSEL7_BANK3_PIN28 0x03000000
-#define BF_PINCTRL_MUXSEL7_BANK3_PIN28(v) \
- (((v) << 24) & BM_PINCTRL_MUXSEL7_BANK3_PIN28)
-#define BP_PINCTRL_MUXSEL7_BANK3_PIN27 22
-#define BM_PINCTRL_MUXSEL7_BANK3_PIN27 0x00C00000
-#define BF_PINCTRL_MUXSEL7_BANK3_PIN27(v) \
- (((v) << 22) & BM_PINCTRL_MUXSEL7_BANK3_PIN27)
-#define BP_PINCTRL_MUXSEL7_BANK3_PIN26 20
-#define BM_PINCTRL_MUXSEL7_BANK3_PIN26 0x00300000
-#define BF_PINCTRL_MUXSEL7_BANK3_PIN26(v) \
- (((v) << 20) & BM_PINCTRL_MUXSEL7_BANK3_PIN26)
-#define BP_PINCTRL_MUXSEL7_BANK3_PIN25 18
-#define BM_PINCTRL_MUXSEL7_BANK3_PIN25 0x000C0000
-#define BF_PINCTRL_MUXSEL7_BANK3_PIN25(v) \
- (((v) << 18) & BM_PINCTRL_MUXSEL7_BANK3_PIN25)
-#define BP_PINCTRL_MUXSEL7_BANK3_PIN24 16
-#define BM_PINCTRL_MUXSEL7_BANK3_PIN24 0x00030000
-#define BF_PINCTRL_MUXSEL7_BANK3_PIN24(v) \
- (((v) << 16) & BM_PINCTRL_MUXSEL7_BANK3_PIN24)
-#define BP_PINCTRL_MUXSEL7_BANK3_PIN23 14
-#define BM_PINCTRL_MUXSEL7_BANK3_PIN23 0x0000C000
-#define BF_PINCTRL_MUXSEL7_BANK3_PIN23(v) \
- (((v) << 14) & BM_PINCTRL_MUXSEL7_BANK3_PIN23)
-#define BP_PINCTRL_MUXSEL7_BANK3_PIN22 12
-#define BM_PINCTRL_MUXSEL7_BANK3_PIN22 0x00003000
-#define BF_PINCTRL_MUXSEL7_BANK3_PIN22(v) \
- (((v) << 12) & BM_PINCTRL_MUXSEL7_BANK3_PIN22)
-#define BP_PINCTRL_MUXSEL7_BANK3_PIN21 10
-#define BM_PINCTRL_MUXSEL7_BANK3_PIN21 0x00000C00
-#define BF_PINCTRL_MUXSEL7_BANK3_PIN21(v) \
- (((v) << 10) & BM_PINCTRL_MUXSEL7_BANK3_PIN21)
-#define BP_PINCTRL_MUXSEL7_BANK3_PIN20 8
-#define BM_PINCTRL_MUXSEL7_BANK3_PIN20 0x00000300
-#define BF_PINCTRL_MUXSEL7_BANK3_PIN20(v) \
- (((v) << 8) & BM_PINCTRL_MUXSEL7_BANK3_PIN20)
-#define BP_PINCTRL_MUXSEL7_RSRVD0 6
-#define BM_PINCTRL_MUXSEL7_RSRVD0 0x000000C0
-#define BF_PINCTRL_MUXSEL7_RSRVD0(v) \
- (((v) << 6) & BM_PINCTRL_MUXSEL7_RSRVD0)
-#define BP_PINCTRL_MUXSEL7_BANK3_PIN18 4
-#define BM_PINCTRL_MUXSEL7_BANK3_PIN18 0x00000030
-#define BF_PINCTRL_MUXSEL7_BANK3_PIN18(v) \
- (((v) << 4) & BM_PINCTRL_MUXSEL7_BANK3_PIN18)
-#define BP_PINCTRL_MUXSEL7_BANK3_PIN17 2
-#define BM_PINCTRL_MUXSEL7_BANK3_PIN17 0x0000000C
-#define BF_PINCTRL_MUXSEL7_BANK3_PIN17(v) \
- (((v) << 2) & BM_PINCTRL_MUXSEL7_BANK3_PIN17)
-#define BP_PINCTRL_MUXSEL7_BANK3_PIN16 0
-#define BM_PINCTRL_MUXSEL7_BANK3_PIN16 0x00000003
-#define BF_PINCTRL_MUXSEL7_BANK3_PIN16(v) \
- (((v) << 0) & BM_PINCTRL_MUXSEL7_BANK3_PIN16)
-
-#define HW_PINCTRL_MUXSEL8 0x00000180
-#define HW_PINCTRL_MUXSEL8_SET 0x00000184
-#define HW_PINCTRL_MUXSEL8_CLR 0x00000188
-#define HW_PINCTRL_MUXSEL8_TOG 0x0000018c
-
-#define BP_PINCTRL_MUXSEL8_BANK4_PIN15 30
-#define BM_PINCTRL_MUXSEL8_BANK4_PIN15 0xC0000000
-#define BF_PINCTRL_MUXSEL8_BANK4_PIN15(v) \
- (((v) << 30) & BM_PINCTRL_MUXSEL8_BANK4_PIN15)
-#define BP_PINCTRL_MUXSEL8_BANK4_PIN14 28
-#define BM_PINCTRL_MUXSEL8_BANK4_PIN14 0x30000000
-#define BF_PINCTRL_MUXSEL8_BANK4_PIN14(v) \
- (((v) << 28) & BM_PINCTRL_MUXSEL8_BANK4_PIN14)
-#define BP_PINCTRL_MUXSEL8_BANK4_PIN13 26
-#define BM_PINCTRL_MUXSEL8_BANK4_PIN13 0x0C000000
-#define BF_PINCTRL_MUXSEL8_BANK4_PIN13(v) \
- (((v) << 26) & BM_PINCTRL_MUXSEL8_BANK4_PIN13)
-#define BP_PINCTRL_MUXSEL8_BANK4_PIN12 24
-#define BM_PINCTRL_MUXSEL8_BANK4_PIN12 0x03000000
-#define BF_PINCTRL_MUXSEL8_BANK4_PIN12(v) \
- (((v) << 24) & BM_PINCTRL_MUXSEL8_BANK4_PIN12)
-#define BP_PINCTRL_MUXSEL8_BANK4_PIN11 22
-#define BM_PINCTRL_MUXSEL8_BANK4_PIN11 0x00C00000
-#define BF_PINCTRL_MUXSEL8_BANK4_PIN11(v) \
- (((v) << 22) & BM_PINCTRL_MUXSEL8_BANK4_PIN11)
-#define BP_PINCTRL_MUXSEL8_BANK4_PIN10 20
-#define BM_PINCTRL_MUXSEL8_BANK4_PIN10 0x00300000
-#define BF_PINCTRL_MUXSEL8_BANK4_PIN10(v) \
- (((v) << 20) & BM_PINCTRL_MUXSEL8_BANK4_PIN10)
-#define BP_PINCTRL_MUXSEL8_BANK4_PIN09 18
-#define BM_PINCTRL_MUXSEL8_BANK4_PIN09 0x000C0000
-#define BF_PINCTRL_MUXSEL8_BANK4_PIN09(v) \
- (((v) << 18) & BM_PINCTRL_MUXSEL8_BANK4_PIN09)
-#define BP_PINCTRL_MUXSEL8_BANK4_PIN08 16
-#define BM_PINCTRL_MUXSEL8_BANK4_PIN08 0x00030000
-#define BF_PINCTRL_MUXSEL8_BANK4_PIN08(v) \
- (((v) << 16) & BM_PINCTRL_MUXSEL8_BANK4_PIN08)
-#define BP_PINCTRL_MUXSEL8_BANK4_PIN07 14
-#define BM_PINCTRL_MUXSEL8_BANK4_PIN07 0x0000C000
-#define BF_PINCTRL_MUXSEL8_BANK4_PIN07(v) \
- (((v) << 14) & BM_PINCTRL_MUXSEL8_BANK4_PIN07)
-#define BP_PINCTRL_MUXSEL8_BANK4_PIN06 12
-#define BM_PINCTRL_MUXSEL8_BANK4_PIN06 0x00003000
-#define BF_PINCTRL_MUXSEL8_BANK4_PIN06(v) \
- (((v) << 12) & BM_PINCTRL_MUXSEL8_BANK4_PIN06)
-#define BP_PINCTRL_MUXSEL8_BANK4_PIN05 10
-#define BM_PINCTRL_MUXSEL8_BANK4_PIN05 0x00000C00
-#define BF_PINCTRL_MUXSEL8_BANK4_PIN05(v) \
- (((v) << 10) & BM_PINCTRL_MUXSEL8_BANK4_PIN05)
-#define BP_PINCTRL_MUXSEL8_BANK4_PIN04 8
-#define BM_PINCTRL_MUXSEL8_BANK4_PIN04 0x00000300
-#define BF_PINCTRL_MUXSEL8_BANK4_PIN04(v) \
- (((v) << 8) & BM_PINCTRL_MUXSEL8_BANK4_PIN04)
-#define BP_PINCTRL_MUXSEL8_BANK4_PIN03 6
-#define BM_PINCTRL_MUXSEL8_BANK4_PIN03 0x000000C0
-#define BF_PINCTRL_MUXSEL8_BANK4_PIN03(v) \
- (((v) << 6) & BM_PINCTRL_MUXSEL8_BANK4_PIN03)
-#define BP_PINCTRL_MUXSEL8_BANK4_PIN02 4
-#define BM_PINCTRL_MUXSEL8_BANK4_PIN02 0x00000030
-#define BF_PINCTRL_MUXSEL8_BANK4_PIN02(v) \
- (((v) << 4) & BM_PINCTRL_MUXSEL8_BANK4_PIN02)
-#define BP_PINCTRL_MUXSEL8_BANK4_PIN01 2
-#define BM_PINCTRL_MUXSEL8_BANK4_PIN01 0x0000000C
-#define BF_PINCTRL_MUXSEL8_BANK4_PIN01(v) \
- (((v) << 2) & BM_PINCTRL_MUXSEL8_BANK4_PIN01)
-#define BP_PINCTRL_MUXSEL8_BANK4_PIN00 0
-#define BM_PINCTRL_MUXSEL8_BANK4_PIN00 0x00000003
-#define BF_PINCTRL_MUXSEL8_BANK4_PIN00(v) \
- (((v) << 0) & BM_PINCTRL_MUXSEL8_BANK4_PIN00)
-
-#define HW_PINCTRL_MUXSEL9 0x00000190
-#define HW_PINCTRL_MUXSEL9_SET 0x00000194
-#define HW_PINCTRL_MUXSEL9_CLR 0x00000198
-#define HW_PINCTRL_MUXSEL9_TOG 0x0000019c
-
-#define BP_PINCTRL_MUXSEL9_RSRVD1 10
-#define BM_PINCTRL_MUXSEL9_RSRVD1 0xFFFFFC00
-#define BF_PINCTRL_MUXSEL9_RSRVD1(v) \
- (((v) << 10) & BM_PINCTRL_MUXSEL9_RSRVD1)
-#define BP_PINCTRL_MUXSEL9_BANK4_PIN20 8
-#define BM_PINCTRL_MUXSEL9_BANK4_PIN20 0x00000300
-#define BF_PINCTRL_MUXSEL9_BANK4_PIN20(v) \
- (((v) << 8) & BM_PINCTRL_MUXSEL9_BANK4_PIN20)
-#define BP_PINCTRL_MUXSEL9_RSRVD0 2
-#define BM_PINCTRL_MUXSEL9_RSRVD0 0x000000FC
-#define BF_PINCTRL_MUXSEL9_RSRVD0(v) \
- (((v) << 2) & BM_PINCTRL_MUXSEL9_RSRVD0)
-#define BP_PINCTRL_MUXSEL9_BANK4_PIN16 0
-#define BM_PINCTRL_MUXSEL9_BANK4_PIN16 0x00000003
-#define BF_PINCTRL_MUXSEL9_BANK4_PIN16(v) \
- (((v) << 0) & BM_PINCTRL_MUXSEL9_BANK4_PIN16)
-
-#define HW_PINCTRL_MUXSEL10 0x000001a0
-#define HW_PINCTRL_MUXSEL10_SET 0x000001a4
-#define HW_PINCTRL_MUXSEL10_CLR 0x000001a8
-#define HW_PINCTRL_MUXSEL10_TOG 0x000001ac
-
-#define BP_PINCTRL_MUXSEL10_BANK5_PIN15 30
-#define BM_PINCTRL_MUXSEL10_BANK5_PIN15 0xC0000000
-#define BF_PINCTRL_MUXSEL10_BANK5_PIN15(v) \
- (((v) << 30) & BM_PINCTRL_MUXSEL10_BANK5_PIN15)
-#define BP_PINCTRL_MUXSEL10_BANK5_PIN14 28
-#define BM_PINCTRL_MUXSEL10_BANK5_PIN14 0x30000000
-#define BF_PINCTRL_MUXSEL10_BANK5_PIN14(v) \
- (((v) << 28) & BM_PINCTRL_MUXSEL10_BANK5_PIN14)
-#define BP_PINCTRL_MUXSEL10_BANK5_PIN13 26
-#define BM_PINCTRL_MUXSEL10_BANK5_PIN13 0x0C000000
-#define BF_PINCTRL_MUXSEL10_BANK5_PIN13(v) \
- (((v) << 26) & BM_PINCTRL_MUXSEL10_BANK5_PIN13)
-#define BP_PINCTRL_MUXSEL10_BANK5_PIN12 24
-#define BM_PINCTRL_MUXSEL10_BANK5_PIN12 0x03000000
-#define BF_PINCTRL_MUXSEL10_BANK5_PIN12(v) \
- (((v) << 24) & BM_PINCTRL_MUXSEL10_BANK5_PIN12)
-#define BP_PINCTRL_MUXSEL10_BANK5_PIN11 22
-#define BM_PINCTRL_MUXSEL10_BANK5_PIN11 0x00C00000
-#define BF_PINCTRL_MUXSEL10_BANK5_PIN11(v) \
- (((v) << 22) & BM_PINCTRL_MUXSEL10_BANK5_PIN11)
-#define BP_PINCTRL_MUXSEL10_BANK5_PIN10 20
-#define BM_PINCTRL_MUXSEL10_BANK5_PIN10 0x00300000
-#define BF_PINCTRL_MUXSEL10_BANK5_PIN10(v) \
- (((v) << 20) & BM_PINCTRL_MUXSEL10_BANK5_PIN10)
-#define BP_PINCTRL_MUXSEL10_BANK5_PIN09 18
-#define BM_PINCTRL_MUXSEL10_BANK5_PIN09 0x000C0000
-#define BF_PINCTRL_MUXSEL10_BANK5_PIN09(v) \
- (((v) << 18) & BM_PINCTRL_MUXSEL10_BANK5_PIN09)
-#define BP_PINCTRL_MUXSEL10_BANK5_PIN08 16
-#define BM_PINCTRL_MUXSEL10_BANK5_PIN08 0x00030000
-#define BF_PINCTRL_MUXSEL10_BANK5_PIN08(v) \
- (((v) << 16) & BM_PINCTRL_MUXSEL10_BANK5_PIN08)
-#define BP_PINCTRL_MUXSEL10_BANK5_PIN07 14
-#define BM_PINCTRL_MUXSEL10_BANK5_PIN07 0x0000C000
-#define BF_PINCTRL_MUXSEL10_BANK5_PIN07(v) \
- (((v) << 14) & BM_PINCTRL_MUXSEL10_BANK5_PIN07)
-#define BP_PINCTRL_MUXSEL10_BANK5_PIN06 12
-#define BM_PINCTRL_MUXSEL10_BANK5_PIN06 0x00003000
-#define BF_PINCTRL_MUXSEL10_BANK5_PIN06(v) \
- (((v) << 12) & BM_PINCTRL_MUXSEL10_BANK5_PIN06)
-#define BP_PINCTRL_MUXSEL10_BANK5_PIN05 10
-#define BM_PINCTRL_MUXSEL10_BANK5_PIN05 0x00000C00
-#define BF_PINCTRL_MUXSEL10_BANK5_PIN05(v) \
- (((v) << 10) & BM_PINCTRL_MUXSEL10_BANK5_PIN05)
-#define BP_PINCTRL_MUXSEL10_BANK5_PIN04 8
-#define BM_PINCTRL_MUXSEL10_BANK5_PIN04 0x00000300
-#define BF_PINCTRL_MUXSEL10_BANK5_PIN04(v) \
- (((v) << 8) & BM_PINCTRL_MUXSEL10_BANK5_PIN04)
-#define BP_PINCTRL_MUXSEL10_BANK5_PIN03 6
-#define BM_PINCTRL_MUXSEL10_BANK5_PIN03 0x000000C0
-#define BF_PINCTRL_MUXSEL10_BANK5_PIN03(v) \
- (((v) << 6) & BM_PINCTRL_MUXSEL10_BANK5_PIN03)
-#define BP_PINCTRL_MUXSEL10_BANK5_PIN02 4
-#define BM_PINCTRL_MUXSEL10_BANK5_PIN02 0x00000030
-#define BF_PINCTRL_MUXSEL10_BANK5_PIN02(v) \
- (((v) << 4) & BM_PINCTRL_MUXSEL10_BANK5_PIN02)
-#define BP_PINCTRL_MUXSEL10_BANK5_PIN01 2
-#define BM_PINCTRL_MUXSEL10_BANK5_PIN01 0x0000000C
-#define BF_PINCTRL_MUXSEL10_BANK5_PIN01(v) \
- (((v) << 2) & BM_PINCTRL_MUXSEL10_BANK5_PIN01)
-#define BP_PINCTRL_MUXSEL10_BANK5_PIN00 0
-#define BM_PINCTRL_MUXSEL10_BANK5_PIN00 0x00000003
-#define BF_PINCTRL_MUXSEL10_BANK5_PIN00(v) \
- (((v) << 0) & BM_PINCTRL_MUXSEL10_BANK5_PIN00)
-
-#define HW_PINCTRL_MUXSEL11 0x000001b0
-#define HW_PINCTRL_MUXSEL11_SET 0x000001b4
-#define HW_PINCTRL_MUXSEL11_CLR 0x000001b8
-#define HW_PINCTRL_MUXSEL11_TOG 0x000001bc
-
-#define BP_PINCTRL_MUXSEL11_RSRVD1 22
-#define BM_PINCTRL_MUXSEL11_RSRVD1 0xFFC00000
-#define BF_PINCTRL_MUXSEL11_RSRVD1(v) \
- (((v) << 22) & BM_PINCTRL_MUXSEL11_RSRVD1)
-#define BP_PINCTRL_MUXSEL11_BANK5_PIN26 20
-#define BM_PINCTRL_MUXSEL11_BANK5_PIN26 0x00300000
-#define BF_PINCTRL_MUXSEL11_BANK5_PIN26(v) \
- (((v) << 20) & BM_PINCTRL_MUXSEL11_BANK5_PIN26)
-#define BP_PINCTRL_MUXSEL11_RSRVD0 16
-#define BM_PINCTRL_MUXSEL11_RSRVD0 0x000F0000
-#define BF_PINCTRL_MUXSEL11_RSRVD0(v) \
- (((v) << 16) & BM_PINCTRL_MUXSEL11_RSRVD0)
-#define BP_PINCTRL_MUXSEL11_BANK5_PIN23 14
-#define BM_PINCTRL_MUXSEL11_BANK5_PIN23 0x0000C000
-#define BF_PINCTRL_MUXSEL11_BANK5_PIN23(v) \
- (((v) << 14) & BM_PINCTRL_MUXSEL11_BANK5_PIN23)
-#define BP_PINCTRL_MUXSEL11_BANK5_PIN22 12
-#define BM_PINCTRL_MUXSEL11_BANK5_PIN22 0x00003000
-#define BF_PINCTRL_MUXSEL11_BANK5_PIN22(v) \
- (((v) << 12) & BM_PINCTRL_MUXSEL11_BANK5_PIN22)
-#define BP_PINCTRL_MUXSEL11_BANK5_PIN21 10
-#define BM_PINCTRL_MUXSEL11_BANK5_PIN21 0x00000C00
-#define BF_PINCTRL_MUXSEL11_BANK5_PIN21(v) \
- (((v) << 10) & BM_PINCTRL_MUXSEL11_BANK5_PIN21)
-#define BP_PINCTRL_MUXSEL11_BANK5_PIN20 8
-#define BM_PINCTRL_MUXSEL11_BANK5_PIN20 0x00000300
-#define BF_PINCTRL_MUXSEL11_BANK5_PIN20(v) \
- (((v) << 8) & BM_PINCTRL_MUXSEL11_BANK5_PIN20)
-#define BP_PINCTRL_MUXSEL11_BANK5_PIN19 6
-#define BM_PINCTRL_MUXSEL11_BANK5_PIN19 0x000000C0
-#define BF_PINCTRL_MUXSEL11_BANK5_PIN19(v) \
- (((v) << 6) & BM_PINCTRL_MUXSEL11_BANK5_PIN19)
-#define BP_PINCTRL_MUXSEL11_BANK5_PIN18 4
-#define BM_PINCTRL_MUXSEL11_BANK5_PIN18 0x00000030
-#define BF_PINCTRL_MUXSEL11_BANK5_PIN18(v) \
- (((v) << 4) & BM_PINCTRL_MUXSEL11_BANK5_PIN18)
-#define BP_PINCTRL_MUXSEL11_BANK5_PIN17 2
-#define BM_PINCTRL_MUXSEL11_BANK5_PIN17 0x0000000C
-#define BF_PINCTRL_MUXSEL11_BANK5_PIN17(v) \
- (((v) << 2) & BM_PINCTRL_MUXSEL11_BANK5_PIN17)
-#define BP_PINCTRL_MUXSEL11_BANK5_PIN16 0
-#define BM_PINCTRL_MUXSEL11_BANK5_PIN16 0x00000003
-#define BF_PINCTRL_MUXSEL11_BANK5_PIN16(v) \
- (((v) << 0) & BM_PINCTRL_MUXSEL11_BANK5_PIN16)
-
-#define HW_PINCTRL_MUXSEL12 0x000001c0
-#define HW_PINCTRL_MUXSEL12_SET 0x000001c4
-#define HW_PINCTRL_MUXSEL12_CLR 0x000001c8
-#define HW_PINCTRL_MUXSEL12_TOG 0x000001cc
-
-#define BP_PINCTRL_MUXSEL12_RSRVD0 30
-#define BM_PINCTRL_MUXSEL12_RSRVD0 0xC0000000
-#define BF_PINCTRL_MUXSEL12_RSRVD0(v) \
- (((v) << 30) & BM_PINCTRL_MUXSEL12_RSRVD0)
-#define BP_PINCTRL_MUXSEL12_BANK6_PIN14 28
-#define BM_PINCTRL_MUXSEL12_BANK6_PIN14 0x30000000
-#define BF_PINCTRL_MUXSEL12_BANK6_PIN14(v) \
- (((v) << 28) & BM_PINCTRL_MUXSEL12_BANK6_PIN14)
-#define BP_PINCTRL_MUXSEL12_BANK6_PIN13 26
-#define BM_PINCTRL_MUXSEL12_BANK6_PIN13 0x0C000000
-#define BF_PINCTRL_MUXSEL12_BANK6_PIN13(v) \
- (((v) << 26) & BM_PINCTRL_MUXSEL12_BANK6_PIN13)
-#define BP_PINCTRL_MUXSEL12_BANK6_PIN12 24
-#define BM_PINCTRL_MUXSEL12_BANK6_PIN12 0x03000000
-#define BF_PINCTRL_MUXSEL12_BANK6_PIN12(v) \
- (((v) << 24) & BM_PINCTRL_MUXSEL12_BANK6_PIN12)
-#define BP_PINCTRL_MUXSEL12_BANK6_PIN11 22
-#define BM_PINCTRL_MUXSEL12_BANK6_PIN11 0x00C00000
-#define BF_PINCTRL_MUXSEL12_BANK6_PIN11(v) \
- (((v) << 22) & BM_PINCTRL_MUXSEL12_BANK6_PIN11)
-#define BP_PINCTRL_MUXSEL12_BANK6_PIN10 20
-#define BM_PINCTRL_MUXSEL12_BANK6_PIN10 0x00300000
-#define BF_PINCTRL_MUXSEL12_BANK6_PIN10(v) \
- (((v) << 20) & BM_PINCTRL_MUXSEL12_BANK6_PIN10)
-#define BP_PINCTRL_MUXSEL12_BANK6_PIN09 18
-#define BM_PINCTRL_MUXSEL12_BANK6_PIN09 0x000C0000
-#define BF_PINCTRL_MUXSEL12_BANK6_PIN09(v) \
- (((v) << 18) & BM_PINCTRL_MUXSEL12_BANK6_PIN09)
-#define BP_PINCTRL_MUXSEL12_BANK6_PIN08 16
-#define BM_PINCTRL_MUXSEL12_BANK6_PIN08 0x00030000
-#define BF_PINCTRL_MUXSEL12_BANK6_PIN08(v) \
- (((v) << 16) & BM_PINCTRL_MUXSEL12_BANK6_PIN08)
-#define BP_PINCTRL_MUXSEL12_BANK6_PIN07 14
-#define BM_PINCTRL_MUXSEL12_BANK6_PIN07 0x0000C000
-#define BF_PINCTRL_MUXSEL12_BANK6_PIN07(v) \
- (((v) << 14) & BM_PINCTRL_MUXSEL12_BANK6_PIN07)
-#define BP_PINCTRL_MUXSEL12_BANK6_PIN06 12
-#define BM_PINCTRL_MUXSEL12_BANK6_PIN06 0x00003000
-#define BF_PINCTRL_MUXSEL12_BANK6_PIN06(v) \
- (((v) << 12) & BM_PINCTRL_MUXSEL12_BANK6_PIN06)
-#define BP_PINCTRL_MUXSEL12_BANK6_PIN05 10
-#define BM_PINCTRL_MUXSEL12_BANK6_PIN05 0x00000C00
-#define BF_PINCTRL_MUXSEL12_BANK6_PIN05(v) \
- (((v) << 10) & BM_PINCTRL_MUXSEL12_BANK6_PIN05)
-#define BP_PINCTRL_MUXSEL12_BANK6_PIN04 8
-#define BM_PINCTRL_MUXSEL12_BANK6_PIN04 0x00000300
-#define BF_PINCTRL_MUXSEL12_BANK6_PIN04(v) \
- (((v) << 8) & BM_PINCTRL_MUXSEL12_BANK6_PIN04)
-#define BP_PINCTRL_MUXSEL12_BANK6_PIN03 6
-#define BM_PINCTRL_MUXSEL12_BANK6_PIN03 0x000000C0
-#define BF_PINCTRL_MUXSEL12_BANK6_PIN03(v) \
- (((v) << 6) & BM_PINCTRL_MUXSEL12_BANK6_PIN03)
-#define BP_PINCTRL_MUXSEL12_BANK6_PIN02 4
-#define BM_PINCTRL_MUXSEL12_BANK6_PIN02 0x00000030
-#define BF_PINCTRL_MUXSEL12_BANK6_PIN02(v) \
- (((v) << 4) & BM_PINCTRL_MUXSEL12_BANK6_PIN02)
-#define BP_PINCTRL_MUXSEL12_BANK6_PIN01 2
-#define BM_PINCTRL_MUXSEL12_BANK6_PIN01 0x0000000C
-#define BF_PINCTRL_MUXSEL12_BANK6_PIN01(v) \
- (((v) << 2) & BM_PINCTRL_MUXSEL12_BANK6_PIN01)
-#define BP_PINCTRL_MUXSEL12_BANK6_PIN00 0
-#define BM_PINCTRL_MUXSEL12_BANK6_PIN00 0x00000003
-#define BF_PINCTRL_MUXSEL12_BANK6_PIN00(v) \
- (((v) << 0) & BM_PINCTRL_MUXSEL12_BANK6_PIN00)
-
-#define HW_PINCTRL_MUXSEL13 0x000001d0
-#define HW_PINCTRL_MUXSEL13_SET 0x000001d4
-#define HW_PINCTRL_MUXSEL13_CLR 0x000001d8
-#define HW_PINCTRL_MUXSEL13_TOG 0x000001dc
-
-#define BP_PINCTRL_MUXSEL13_RSRVD0 18
-#define BM_PINCTRL_MUXSEL13_RSRVD0 0xFFFC0000
-#define BF_PINCTRL_MUXSEL13_RSRVD0(v) \
- (((v) << 18) & BM_PINCTRL_MUXSEL13_RSRVD0)
-#define BP_PINCTRL_MUXSEL13_BANK6_PIN24 16
-#define BM_PINCTRL_MUXSEL13_BANK6_PIN24 0x00030000
-#define BF_PINCTRL_MUXSEL13_BANK6_PIN24(v) \
- (((v) << 16) & BM_PINCTRL_MUXSEL13_BANK6_PIN24)
-#define BP_PINCTRL_MUXSEL13_BANK6_PIN23 14
-#define BM_PINCTRL_MUXSEL13_BANK6_PIN23 0x0000C000
-#define BF_PINCTRL_MUXSEL13_BANK6_PIN23(v) \
- (((v) << 14) & BM_PINCTRL_MUXSEL13_BANK6_PIN23)
-#define BP_PINCTRL_MUXSEL13_BANK6_PIN22 12
-#define BM_PINCTRL_MUXSEL13_BANK6_PIN22 0x00003000
-#define BF_PINCTRL_MUXSEL13_BANK6_PIN22(v) \
- (((v) << 12) & BM_PINCTRL_MUXSEL13_BANK6_PIN22)
-#define BP_PINCTRL_MUXSEL13_BANK6_PIN21 10
-#define BM_PINCTRL_MUXSEL13_BANK6_PIN21 0x00000C00
-#define BF_PINCTRL_MUXSEL13_BANK6_PIN21(v) \
- (((v) << 10) & BM_PINCTRL_MUXSEL13_BANK6_PIN21)
-#define BP_PINCTRL_MUXSEL13_BANK6_PIN20 8
-#define BM_PINCTRL_MUXSEL13_BANK6_PIN20 0x00000300
-#define BF_PINCTRL_MUXSEL13_BANK6_PIN20(v) \
- (((v) << 8) & BM_PINCTRL_MUXSEL13_BANK6_PIN20)
-#define BP_PINCTRL_MUXSEL13_BANK6_PIN19 6
-#define BM_PINCTRL_MUXSEL13_BANK6_PIN19 0x000000C0
-#define BF_PINCTRL_MUXSEL13_BANK6_PIN19(v) \
- (((v) << 6) & BM_PINCTRL_MUXSEL13_BANK6_PIN19)
-#define BP_PINCTRL_MUXSEL13_BANK6_PIN18 4
-#define BM_PINCTRL_MUXSEL13_BANK6_PIN18 0x00000030
-#define BF_PINCTRL_MUXSEL13_BANK6_PIN18(v) \
- (((v) << 4) & BM_PINCTRL_MUXSEL13_BANK6_PIN18)
-#define BP_PINCTRL_MUXSEL13_BANK6_PIN17 2
-#define BM_PINCTRL_MUXSEL13_BANK6_PIN17 0x0000000C
-#define BF_PINCTRL_MUXSEL13_BANK6_PIN17(v) \
- (((v) << 2) & BM_PINCTRL_MUXSEL13_BANK6_PIN17)
-#define BP_PINCTRL_MUXSEL13_BANK6_PIN16 0
-#define BM_PINCTRL_MUXSEL13_BANK6_PIN16 0x00000003
-#define BF_PINCTRL_MUXSEL13_BANK6_PIN16(v) \
- (((v) << 0) & BM_PINCTRL_MUXSEL13_BANK6_PIN16)
-
-#define HW_PINCTRL_DRIVE0 0x00000300
-#define HW_PINCTRL_DRIVE0_SET 0x00000304
-#define HW_PINCTRL_DRIVE0_CLR 0x00000308
-#define HW_PINCTRL_DRIVE0_TOG 0x0000030c
-
-#define BM_PINCTRL_DRIVE0_RSRVD7 0x80000000
-#define BM_PINCTRL_DRIVE0_BANK0_PIN07_V 0x40000000
-#define BP_PINCTRL_DRIVE0_BANK0_PIN07_MA 28
-#define BM_PINCTRL_DRIVE0_BANK0_PIN07_MA 0x30000000
-#define BF_PINCTRL_DRIVE0_BANK0_PIN07_MA(v) \
- (((v) << 28) & BM_PINCTRL_DRIVE0_BANK0_PIN07_MA)
-#define BM_PINCTRL_DRIVE0_RSRVD6 0x08000000
-#define BM_PINCTRL_DRIVE0_BANK0_PIN06_V 0x04000000
-#define BP_PINCTRL_DRIVE0_BANK0_PIN06_MA 24
-#define BM_PINCTRL_DRIVE0_BANK0_PIN06_MA 0x03000000
-#define BF_PINCTRL_DRIVE0_BANK0_PIN06_MA(v) \
- (((v) << 24) & BM_PINCTRL_DRIVE0_BANK0_PIN06_MA)
-#define BM_PINCTRL_DRIVE0_RSRVD5 0x00800000
-#define BM_PINCTRL_DRIVE0_BANK0_PIN05_V 0x00400000
-#define BP_PINCTRL_DRIVE0_BANK0_PIN05_MA 20
-#define BM_PINCTRL_DRIVE0_BANK0_PIN05_MA 0x00300000
-#define BF_PINCTRL_DRIVE0_BANK0_PIN05_MA(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE0_BANK0_PIN05_MA)
-#define BM_PINCTRL_DRIVE0_RSRVD4 0x00080000
-#define BM_PINCTRL_DRIVE0_BANK0_PIN04_V 0x00040000
-#define BP_PINCTRL_DRIVE0_BANK0_PIN04_MA 16
-#define BM_PINCTRL_DRIVE0_BANK0_PIN04_MA 0x00030000
-#define BF_PINCTRL_DRIVE0_BANK0_PIN04_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE0_BANK0_PIN04_MA)
-#define BM_PINCTRL_DRIVE0_RSRVD3 0x00008000
-#define BM_PINCTRL_DRIVE0_BANK0_PIN03_V 0x00004000
-#define BP_PINCTRL_DRIVE0_BANK0_PIN03_MA 12
-#define BM_PINCTRL_DRIVE0_BANK0_PIN03_MA 0x00003000
-#define BF_PINCTRL_DRIVE0_BANK0_PIN03_MA(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE0_BANK0_PIN03_MA)
-#define BM_PINCTRL_DRIVE0_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE0_BANK0_PIN02_V 0x00000400
-#define BP_PINCTRL_DRIVE0_BANK0_PIN02_MA 8
-#define BM_PINCTRL_DRIVE0_BANK0_PIN02_MA 0x00000300
-#define BF_PINCTRL_DRIVE0_BANK0_PIN02_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE0_BANK0_PIN02_MA)
-#define BM_PINCTRL_DRIVE0_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE0_BANK0_PIN01_V 0x00000040
-#define BP_PINCTRL_DRIVE0_BANK0_PIN01_MA 4
-#define BM_PINCTRL_DRIVE0_BANK0_PIN01_MA 0x00000030
-#define BF_PINCTRL_DRIVE0_BANK0_PIN01_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE0_BANK0_PIN01_MA)
-#define BM_PINCTRL_DRIVE0_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE0_BANK0_PIN00_V 0x00000004
-#define BP_PINCTRL_DRIVE0_BANK0_PIN00_MA 0
-#define BM_PINCTRL_DRIVE0_BANK0_PIN00_MA 0x00000003
-#define BF_PINCTRL_DRIVE0_BANK0_PIN00_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE0_BANK0_PIN00_MA)
-
-#define HW_PINCTRL_DRIVE1 0x00000310
-#define HW_PINCTRL_DRIVE1_SET 0x00000314
-#define HW_PINCTRL_DRIVE1_CLR 0x00000318
-#define HW_PINCTRL_DRIVE1_TOG 0x0000031c
-
-#define BP_PINCTRL_DRIVE1_RSRVD0 0
-#define BM_PINCTRL_DRIVE1_RSRVD0 0xFFFFFFFF
-#define BF_PINCTRL_DRIVE1_RSRVD0(v) (v)
-
-#define HW_PINCTRL_DRIVE2 0x00000320
-#define HW_PINCTRL_DRIVE2_SET 0x00000324
-#define HW_PINCTRL_DRIVE2_CLR 0x00000328
-#define HW_PINCTRL_DRIVE2_TOG 0x0000032c
-
-#define BM_PINCTRL_DRIVE2_RSRVD7 0x80000000
-#define BM_PINCTRL_DRIVE2_BANK0_PIN23_V 0x40000000
-#define BP_PINCTRL_DRIVE2_BANK0_PIN23_MA 28
-#define BM_PINCTRL_DRIVE2_BANK0_PIN23_MA 0x30000000
-#define BF_PINCTRL_DRIVE2_BANK0_PIN23_MA(v) \
- (((v) << 28) & BM_PINCTRL_DRIVE2_BANK0_PIN23_MA)
-#define BM_PINCTRL_DRIVE2_RSRVD6 0x08000000
-#define BM_PINCTRL_DRIVE2_BANK0_PIN22_V 0x04000000
-#define BP_PINCTRL_DRIVE2_BANK0_PIN22_MA 24
-#define BM_PINCTRL_DRIVE2_BANK0_PIN22_MA 0x03000000
-#define BF_PINCTRL_DRIVE2_BANK0_PIN22_MA(v) \
- (((v) << 24) & BM_PINCTRL_DRIVE2_BANK0_PIN22_MA)
-#define BM_PINCTRL_DRIVE2_RSRVD5 0x00800000
-#define BM_PINCTRL_DRIVE2_BANK0_PIN21_V 0x00400000
-#define BP_PINCTRL_DRIVE2_BANK0_PIN21_MA 20
-#define BM_PINCTRL_DRIVE2_BANK0_PIN21_MA 0x00300000
-#define BF_PINCTRL_DRIVE2_BANK0_PIN21_MA(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE2_BANK0_PIN21_MA)
-#define BM_PINCTRL_DRIVE2_RSRVD4 0x00080000
-#define BM_PINCTRL_DRIVE2_BANK0_PIN20_V 0x00040000
-#define BP_PINCTRL_DRIVE2_BANK0_PIN20_MA 16
-#define BM_PINCTRL_DRIVE2_BANK0_PIN20_MA 0x00030000
-#define BF_PINCTRL_DRIVE2_BANK0_PIN20_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE2_BANK0_PIN20_MA)
-#define BM_PINCTRL_DRIVE2_RSRVD3 0x00008000
-#define BM_PINCTRL_DRIVE2_BANK0_PIN19_V 0x00004000
-#define BP_PINCTRL_DRIVE2_BANK0_PIN19_MA 12
-#define BM_PINCTRL_DRIVE2_BANK0_PIN19_MA 0x00003000
-#define BF_PINCTRL_DRIVE2_BANK0_PIN19_MA(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE2_BANK0_PIN19_MA)
-#define BM_PINCTRL_DRIVE2_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE2_BANK0_PIN18_V 0x00000400
-#define BP_PINCTRL_DRIVE2_BANK0_PIN18_MA 8
-#define BM_PINCTRL_DRIVE2_BANK0_PIN18_MA 0x00000300
-#define BF_PINCTRL_DRIVE2_BANK0_PIN18_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE2_BANK0_PIN18_MA)
-#define BM_PINCTRL_DRIVE2_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE2_BANK0_PIN17_V 0x00000040
-#define BP_PINCTRL_DRIVE2_BANK0_PIN17_MA 4
-#define BM_PINCTRL_DRIVE2_BANK0_PIN17_MA 0x00000030
-#define BF_PINCTRL_DRIVE2_BANK0_PIN17_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE2_BANK0_PIN17_MA)
-#define BM_PINCTRL_DRIVE2_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE2_BANK0_PIN16_V 0x00000004
-#define BP_PINCTRL_DRIVE2_BANK0_PIN16_MA 0
-#define BM_PINCTRL_DRIVE2_BANK0_PIN16_MA 0x00000003
-#define BF_PINCTRL_DRIVE2_BANK0_PIN16_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE2_BANK0_PIN16_MA)
-
-#define HW_PINCTRL_DRIVE3 0x00000330
-#define HW_PINCTRL_DRIVE3_SET 0x00000334
-#define HW_PINCTRL_DRIVE3_CLR 0x00000338
-#define HW_PINCTRL_DRIVE3_TOG 0x0000033c
-
-#define BP_PINCTRL_DRIVE3_RSRVD5 20
-#define BM_PINCTRL_DRIVE3_RSRVD5 0xFFF00000
-#define BF_PINCTRL_DRIVE3_RSRVD5(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE3_RSRVD5)
-#define BM_PINCTRL_DRIVE3_RSRVD4 0x00080000
-#define BM_PINCTRL_DRIVE3_BANK0_PIN28_V 0x00040000
-#define BP_PINCTRL_DRIVE3_BANK0_PIN28_MA 16
-#define BM_PINCTRL_DRIVE3_BANK0_PIN28_MA 0x00030000
-#define BF_PINCTRL_DRIVE3_BANK0_PIN28_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE3_BANK0_PIN28_MA)
-#define BM_PINCTRL_DRIVE3_RSRVD3 0x00008000
-#define BM_PINCTRL_DRIVE3_BANK0_PIN27_V 0x00004000
-#define BP_PINCTRL_DRIVE3_BANK0_PIN27_MA 12
-#define BM_PINCTRL_DRIVE3_BANK0_PIN27_MA 0x00003000
-#define BF_PINCTRL_DRIVE3_BANK0_PIN27_MA(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE3_BANK0_PIN27_MA)
-#define BM_PINCTRL_DRIVE3_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE3_BANK0_PIN26_V 0x00000400
-#define BP_PINCTRL_DRIVE3_BANK0_PIN26_MA 8
-#define BM_PINCTRL_DRIVE3_BANK0_PIN26_MA 0x00000300
-#define BF_PINCTRL_DRIVE3_BANK0_PIN26_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE3_BANK0_PIN26_MA)
-#define BM_PINCTRL_DRIVE3_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE3_BANK0_PIN25_V 0x00000040
-#define BP_PINCTRL_DRIVE3_BANK0_PIN25_MA 4
-#define BM_PINCTRL_DRIVE3_BANK0_PIN25_MA 0x00000030
-#define BF_PINCTRL_DRIVE3_BANK0_PIN25_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE3_BANK0_PIN25_MA)
-#define BM_PINCTRL_DRIVE3_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE3_BANK0_PIN24_V 0x00000004
-#define BP_PINCTRL_DRIVE3_BANK0_PIN24_MA 0
-#define BM_PINCTRL_DRIVE3_BANK0_PIN24_MA 0x00000003
-#define BF_PINCTRL_DRIVE3_BANK0_PIN24_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE3_BANK0_PIN24_MA)
-
-#define HW_PINCTRL_DRIVE4 0x00000340
-#define HW_PINCTRL_DRIVE4_SET 0x00000344
-#define HW_PINCTRL_DRIVE4_CLR 0x00000348
-#define HW_PINCTRL_DRIVE4_TOG 0x0000034c
-
-#define BM_PINCTRL_DRIVE4_RSRVD7 0x80000000
-#define BM_PINCTRL_DRIVE4_BANK1_PIN07_V 0x40000000
-#define BP_PINCTRL_DRIVE4_BANK1_PIN07_MA 28
-#define BM_PINCTRL_DRIVE4_BANK1_PIN07_MA 0x30000000
-#define BF_PINCTRL_DRIVE4_BANK1_PIN07_MA(v) \
- (((v) << 28) & BM_PINCTRL_DRIVE4_BANK1_PIN07_MA)
-#define BM_PINCTRL_DRIVE4_RSRVD6 0x08000000
-#define BM_PINCTRL_DRIVE4_BANK1_PIN06_V 0x04000000
-#define BP_PINCTRL_DRIVE4_BANK1_PIN06_MA 24
-#define BM_PINCTRL_DRIVE4_BANK1_PIN06_MA 0x03000000
-#define BF_PINCTRL_DRIVE4_BANK1_PIN06_MA(v) \
- (((v) << 24) & BM_PINCTRL_DRIVE4_BANK1_PIN06_MA)
-#define BM_PINCTRL_DRIVE4_RSRVD5 0x00800000
-#define BM_PINCTRL_DRIVE4_BANK1_PIN05_V 0x00400000
-#define BP_PINCTRL_DRIVE4_BANK1_PIN05_MA 20
-#define BM_PINCTRL_DRIVE4_BANK1_PIN05_MA 0x00300000
-#define BF_PINCTRL_DRIVE4_BANK1_PIN05_MA(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE4_BANK1_PIN05_MA)
-#define BM_PINCTRL_DRIVE4_RSRVD4 0x00080000
-#define BM_PINCTRL_DRIVE4_BANK1_PIN04_V 0x00040000
-#define BP_PINCTRL_DRIVE4_BANK1_PIN04_MA 16
-#define BM_PINCTRL_DRIVE4_BANK1_PIN04_MA 0x00030000
-#define BF_PINCTRL_DRIVE4_BANK1_PIN04_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE4_BANK1_PIN04_MA)
-#define BM_PINCTRL_DRIVE4_RSRVD3 0x00008000
-#define BM_PINCTRL_DRIVE4_BANK1_PIN03_V 0x00004000
-#define BP_PINCTRL_DRIVE4_BANK1_PIN03_MA 12
-#define BM_PINCTRL_DRIVE4_BANK1_PIN03_MA 0x00003000
-#define BF_PINCTRL_DRIVE4_BANK1_PIN03_MA(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE4_BANK1_PIN03_MA)
-#define BM_PINCTRL_DRIVE4_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE4_BANK1_PIN02_V 0x00000400
-#define BP_PINCTRL_DRIVE4_BANK1_PIN02_MA 8
-#define BM_PINCTRL_DRIVE4_BANK1_PIN02_MA 0x00000300
-#define BF_PINCTRL_DRIVE4_BANK1_PIN02_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE4_BANK1_PIN02_MA)
-#define BM_PINCTRL_DRIVE4_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE4_BANK1_PIN01_V 0x00000040
-#define BP_PINCTRL_DRIVE4_BANK1_PIN01_MA 4
-#define BM_PINCTRL_DRIVE4_BANK1_PIN01_MA 0x00000030
-#define BF_PINCTRL_DRIVE4_BANK1_PIN01_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE4_BANK1_PIN01_MA)
-#define BM_PINCTRL_DRIVE4_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE4_BANK1_PIN00_V 0x00000004
-#define BP_PINCTRL_DRIVE4_BANK1_PIN00_MA 0
-#define BM_PINCTRL_DRIVE4_BANK1_PIN00_MA 0x00000003
-#define BF_PINCTRL_DRIVE4_BANK1_PIN00_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE4_BANK1_PIN00_MA)
-
-#define HW_PINCTRL_DRIVE5 0x00000350
-#define HW_PINCTRL_DRIVE5_SET 0x00000354
-#define HW_PINCTRL_DRIVE5_CLR 0x00000358
-#define HW_PINCTRL_DRIVE5_TOG 0x0000035c
-
-#define BM_PINCTRL_DRIVE5_RSRVD7 0x80000000
-#define BM_PINCTRL_DRIVE5_BANK1_PIN15_V 0x40000000
-#define BP_PINCTRL_DRIVE5_BANK1_PIN15_MA 28
-#define BM_PINCTRL_DRIVE5_BANK1_PIN15_MA 0x30000000
-#define BF_PINCTRL_DRIVE5_BANK1_PIN15_MA(v) \
- (((v) << 28) & BM_PINCTRL_DRIVE5_BANK1_PIN15_MA)
-#define BM_PINCTRL_DRIVE5_RSRVD6 0x08000000
-#define BM_PINCTRL_DRIVE5_BANK1_PIN14_V 0x04000000
-#define BP_PINCTRL_DRIVE5_BANK1_PIN14_MA 24
-#define BM_PINCTRL_DRIVE5_BANK1_PIN14_MA 0x03000000
-#define BF_PINCTRL_DRIVE5_BANK1_PIN14_MA(v) \
- (((v) << 24) & BM_PINCTRL_DRIVE5_BANK1_PIN14_MA)
-#define BM_PINCTRL_DRIVE5_RSRVD5 0x00800000
-#define BM_PINCTRL_DRIVE5_BANK1_PIN13_V 0x00400000
-#define BP_PINCTRL_DRIVE5_BANK1_PIN13_MA 20
-#define BM_PINCTRL_DRIVE5_BANK1_PIN13_MA 0x00300000
-#define BF_PINCTRL_DRIVE5_BANK1_PIN13_MA(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE5_BANK1_PIN13_MA)
-#define BM_PINCTRL_DRIVE5_RSRVD4 0x00080000
-#define BM_PINCTRL_DRIVE5_BANK1_PIN12_V 0x00040000
-#define BP_PINCTRL_DRIVE5_BANK1_PIN12_MA 16
-#define BM_PINCTRL_DRIVE5_BANK1_PIN12_MA 0x00030000
-#define BF_PINCTRL_DRIVE5_BANK1_PIN12_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE5_BANK1_PIN12_MA)
-#define BM_PINCTRL_DRIVE5_RSRVD3 0x00008000
-#define BM_PINCTRL_DRIVE5_BANK1_PIN11_V 0x00004000
-#define BP_PINCTRL_DRIVE5_BANK1_PIN11_MA 12
-#define BM_PINCTRL_DRIVE5_BANK1_PIN11_MA 0x00003000
-#define BF_PINCTRL_DRIVE5_BANK1_PIN11_MA(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE5_BANK1_PIN11_MA)
-#define BM_PINCTRL_DRIVE5_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE5_BANK1_PIN10_V 0x00000400
-#define BP_PINCTRL_DRIVE5_BANK1_PIN10_MA 8
-#define BM_PINCTRL_DRIVE5_BANK1_PIN10_MA 0x00000300
-#define BF_PINCTRL_DRIVE5_BANK1_PIN10_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE5_BANK1_PIN10_MA)
-#define BM_PINCTRL_DRIVE5_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE5_BANK1_PIN09_V 0x00000040
-#define BP_PINCTRL_DRIVE5_BANK1_PIN09_MA 4
-#define BM_PINCTRL_DRIVE5_BANK1_PIN09_MA 0x00000030
-#define BF_PINCTRL_DRIVE5_BANK1_PIN09_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE5_BANK1_PIN09_MA)
-#define BM_PINCTRL_DRIVE5_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE5_BANK1_PIN08_V 0x00000004
-#define BP_PINCTRL_DRIVE5_BANK1_PIN08_MA 0
-#define BM_PINCTRL_DRIVE5_BANK1_PIN08_MA 0x00000003
-#define BF_PINCTRL_DRIVE5_BANK1_PIN08_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE5_BANK1_PIN08_MA)
-
-#define HW_PINCTRL_DRIVE6 0x00000360
-#define HW_PINCTRL_DRIVE6_SET 0x00000364
-#define HW_PINCTRL_DRIVE6_CLR 0x00000368
-#define HW_PINCTRL_DRIVE6_TOG 0x0000036c
-
-#define BM_PINCTRL_DRIVE6_RSRVD7 0x80000000
-#define BM_PINCTRL_DRIVE6_BANK1_PIN23_V 0x40000000
-#define BP_PINCTRL_DRIVE6_BANK1_PIN23_MA 28
-#define BM_PINCTRL_DRIVE6_BANK1_PIN23_MA 0x30000000
-#define BF_PINCTRL_DRIVE6_BANK1_PIN23_MA(v) \
- (((v) << 28) & BM_PINCTRL_DRIVE6_BANK1_PIN23_MA)
-#define BM_PINCTRL_DRIVE6_RSRVD6 0x08000000
-#define BM_PINCTRL_DRIVE6_BANK1_PIN22_V 0x04000000
-#define BP_PINCTRL_DRIVE6_BANK1_PIN22_MA 24
-#define BM_PINCTRL_DRIVE6_BANK1_PIN22_MA 0x03000000
-#define BF_PINCTRL_DRIVE6_BANK1_PIN22_MA(v) \
- (((v) << 24) & BM_PINCTRL_DRIVE6_BANK1_PIN22_MA)
-#define BM_PINCTRL_DRIVE6_RSRVD5 0x00800000
-#define BM_PINCTRL_DRIVE6_BANK1_PIN21_V 0x00400000
-#define BP_PINCTRL_DRIVE6_BANK1_PIN21_MA 20
-#define BM_PINCTRL_DRIVE6_BANK1_PIN21_MA 0x00300000
-#define BF_PINCTRL_DRIVE6_BANK1_PIN21_MA(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE6_BANK1_PIN21_MA)
-#define BM_PINCTRL_DRIVE6_RSRVD4 0x00080000
-#define BM_PINCTRL_DRIVE6_BANK1_PIN20_V 0x00040000
-#define BP_PINCTRL_DRIVE6_BANK1_PIN20_MA 16
-#define BM_PINCTRL_DRIVE6_BANK1_PIN20_MA 0x00030000
-#define BF_PINCTRL_DRIVE6_BANK1_PIN20_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE6_BANK1_PIN20_MA)
-#define BM_PINCTRL_DRIVE6_RSRVD3 0x00008000
-#define BM_PINCTRL_DRIVE6_BANK1_PIN19_V 0x00004000
-#define BP_PINCTRL_DRIVE6_BANK1_PIN19_MA 12
-#define BM_PINCTRL_DRIVE6_BANK1_PIN19_MA 0x00003000
-#define BF_PINCTRL_DRIVE6_BANK1_PIN19_MA(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE6_BANK1_PIN19_MA)
-#define BM_PINCTRL_DRIVE6_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE6_BANK1_PIN18_V 0x00000400
-#define BP_PINCTRL_DRIVE6_BANK1_PIN18_MA 8
-#define BM_PINCTRL_DRIVE6_BANK1_PIN18_MA 0x00000300
-#define BF_PINCTRL_DRIVE6_BANK1_PIN18_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE6_BANK1_PIN18_MA)
-#define BM_PINCTRL_DRIVE6_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE6_BANK1_PIN17_V 0x00000040
-#define BP_PINCTRL_DRIVE6_BANK1_PIN17_MA 4
-#define BM_PINCTRL_DRIVE6_BANK1_PIN17_MA 0x00000030
-#define BF_PINCTRL_DRIVE6_BANK1_PIN17_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE6_BANK1_PIN17_MA)
-#define BM_PINCTRL_DRIVE6_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE6_BANK1_PIN16_V 0x00000004
-#define BP_PINCTRL_DRIVE6_BANK1_PIN16_MA 0
-#define BM_PINCTRL_DRIVE6_BANK1_PIN16_MA 0x00000003
-#define BF_PINCTRL_DRIVE6_BANK1_PIN16_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE6_BANK1_PIN16_MA)
-
-#define HW_PINCTRL_DRIVE7 0x00000370
-#define HW_PINCTRL_DRIVE7_SET 0x00000374
-#define HW_PINCTRL_DRIVE7_CLR 0x00000378
-#define HW_PINCTRL_DRIVE7_TOG 0x0000037c
-
-#define BM_PINCTRL_DRIVE7_RSRVD7 0x80000000
-#define BM_PINCTRL_DRIVE7_BANK1_PIN31_V 0x40000000
-#define BP_PINCTRL_DRIVE7_BANK1_PIN31_MA 28
-#define BM_PINCTRL_DRIVE7_BANK1_PIN31_MA 0x30000000
-#define BF_PINCTRL_DRIVE7_BANK1_PIN31_MA(v) \
- (((v) << 28) & BM_PINCTRL_DRIVE7_BANK1_PIN31_MA)
-#define BM_PINCTRL_DRIVE7_RSRVD6 0x08000000
-#define BM_PINCTRL_DRIVE7_BANK1_PIN30_V 0x04000000
-#define BP_PINCTRL_DRIVE7_BANK1_PIN30_MA 24
-#define BM_PINCTRL_DRIVE7_BANK1_PIN30_MA 0x03000000
-#define BF_PINCTRL_DRIVE7_BANK1_PIN30_MA(v) \
- (((v) << 24) & BM_PINCTRL_DRIVE7_BANK1_PIN30_MA)
-#define BM_PINCTRL_DRIVE7_RSRVD5 0x00800000
-#define BM_PINCTRL_DRIVE7_BANK1_PIN29_V 0x00400000
-#define BP_PINCTRL_DRIVE7_BANK1_PIN29_MA 20
-#define BM_PINCTRL_DRIVE7_BANK1_PIN29_MA 0x00300000
-#define BF_PINCTRL_DRIVE7_BANK1_PIN29_MA(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE7_BANK1_PIN29_MA)
-#define BM_PINCTRL_DRIVE7_RSRVD4 0x00080000
-#define BM_PINCTRL_DRIVE7_BANK1_PIN28_V 0x00040000
-#define BP_PINCTRL_DRIVE7_BANK1_PIN28_MA 16
-#define BM_PINCTRL_DRIVE7_BANK1_PIN28_MA 0x00030000
-#define BF_PINCTRL_DRIVE7_BANK1_PIN28_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE7_BANK1_PIN28_MA)
-#define BM_PINCTRL_DRIVE7_RSRVD3 0x00008000
-#define BM_PINCTRL_DRIVE7_BANK1_PIN27_V 0x00004000
-#define BP_PINCTRL_DRIVE7_BANK1_PIN27_MA 12
-#define BM_PINCTRL_DRIVE7_BANK1_PIN27_MA 0x00003000
-#define BF_PINCTRL_DRIVE7_BANK1_PIN27_MA(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE7_BANK1_PIN27_MA)
-#define BM_PINCTRL_DRIVE7_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE7_BANK1_PIN26_V 0x00000400
-#define BP_PINCTRL_DRIVE7_BANK1_PIN26_MA 8
-#define BM_PINCTRL_DRIVE7_BANK1_PIN26_MA 0x00000300
-#define BF_PINCTRL_DRIVE7_BANK1_PIN26_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE7_BANK1_PIN26_MA)
-#define BM_PINCTRL_DRIVE7_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE7_BANK1_PIN25_V 0x00000040
-#define BP_PINCTRL_DRIVE7_BANK1_PIN25_MA 4
-#define BM_PINCTRL_DRIVE7_BANK1_PIN25_MA 0x00000030
-#define BF_PINCTRL_DRIVE7_BANK1_PIN25_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE7_BANK1_PIN25_MA)
-#define BM_PINCTRL_DRIVE7_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE7_BANK1_PIN24_V 0x00000004
-#define BP_PINCTRL_DRIVE7_BANK1_PIN24_MA 0
-#define BM_PINCTRL_DRIVE7_BANK1_PIN24_MA 0x00000003
-#define BF_PINCTRL_DRIVE7_BANK1_PIN24_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE7_BANK1_PIN24_MA)
-
-#define HW_PINCTRL_DRIVE8 0x00000380
-#define HW_PINCTRL_DRIVE8_SET 0x00000384
-#define HW_PINCTRL_DRIVE8_CLR 0x00000388
-#define HW_PINCTRL_DRIVE8_TOG 0x0000038c
-
-#define BM_PINCTRL_DRIVE8_RSRVD7 0x80000000
-#define BM_PINCTRL_DRIVE8_BANK2_PIN07_V 0x40000000
-#define BP_PINCTRL_DRIVE8_BANK2_PIN07_MA 28
-#define BM_PINCTRL_DRIVE8_BANK2_PIN07_MA 0x30000000
-#define BF_PINCTRL_DRIVE8_BANK2_PIN07_MA(v) \
- (((v) << 28) & BM_PINCTRL_DRIVE8_BANK2_PIN07_MA)
-#define BM_PINCTRL_DRIVE8_RSRVD6 0x08000000
-#define BM_PINCTRL_DRIVE8_BANK2_PIN06_V 0x04000000
-#define BP_PINCTRL_DRIVE8_BANK2_PIN06_MA 24
-#define BM_PINCTRL_DRIVE8_BANK2_PIN06_MA 0x03000000
-#define BF_PINCTRL_DRIVE8_BANK2_PIN06_MA(v) \
- (((v) << 24) & BM_PINCTRL_DRIVE8_BANK2_PIN06_MA)
-#define BM_PINCTRL_DRIVE8_RSRVD5 0x00800000
-#define BM_PINCTRL_DRIVE8_BANK2_PIN05_V 0x00400000
-#define BP_PINCTRL_DRIVE8_BANK2_PIN05_MA 20
-#define BM_PINCTRL_DRIVE8_BANK2_PIN05_MA 0x00300000
-#define BF_PINCTRL_DRIVE8_BANK2_PIN05_MA(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE8_BANK2_PIN05_MA)
-#define BM_PINCTRL_DRIVE8_RSRVD4 0x00080000
-#define BM_PINCTRL_DRIVE8_BANK2_PIN04_V 0x00040000
-#define BP_PINCTRL_DRIVE8_BANK2_PIN04_MA 16
-#define BM_PINCTRL_DRIVE8_BANK2_PIN04_MA 0x00030000
-#define BF_PINCTRL_DRIVE8_BANK2_PIN04_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE8_BANK2_PIN04_MA)
-#define BM_PINCTRL_DRIVE8_RSRVD3 0x00008000
-#define BM_PINCTRL_DRIVE8_BANK2_PIN03_V 0x00004000
-#define BP_PINCTRL_DRIVE8_BANK2_PIN03_MA 12
-#define BM_PINCTRL_DRIVE8_BANK2_PIN03_MA 0x00003000
-#define BF_PINCTRL_DRIVE8_BANK2_PIN03_MA(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE8_BANK2_PIN03_MA)
-#define BM_PINCTRL_DRIVE8_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE8_BANK2_PIN02_V 0x00000400
-#define BP_PINCTRL_DRIVE8_BANK2_PIN02_MA 8
-#define BM_PINCTRL_DRIVE8_BANK2_PIN02_MA 0x00000300
-#define BF_PINCTRL_DRIVE8_BANK2_PIN02_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE8_BANK2_PIN02_MA)
-#define BM_PINCTRL_DRIVE8_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE8_BANK2_PIN01_V 0x00000040
-#define BP_PINCTRL_DRIVE8_BANK2_PIN01_MA 4
-#define BM_PINCTRL_DRIVE8_BANK2_PIN01_MA 0x00000030
-#define BF_PINCTRL_DRIVE8_BANK2_PIN01_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE8_BANK2_PIN01_MA)
-#define BM_PINCTRL_DRIVE8_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE8_BANK2_PIN00_V 0x00000004
-#define BP_PINCTRL_DRIVE8_BANK2_PIN00_MA 0
-#define BM_PINCTRL_DRIVE8_BANK2_PIN00_MA 0x00000003
-#define BF_PINCTRL_DRIVE8_BANK2_PIN00_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE8_BANK2_PIN00_MA)
-
-#define HW_PINCTRL_DRIVE9 0x00000390
-#define HW_PINCTRL_DRIVE9_SET 0x00000394
-#define HW_PINCTRL_DRIVE9_CLR 0x00000398
-#define HW_PINCTRL_DRIVE9_TOG 0x0000039c
-
-#define BM_PINCTRL_DRIVE9_RSRVD7 0x80000000
-#define BM_PINCTRL_DRIVE9_BANK2_PIN15_V 0x40000000
-#define BP_PINCTRL_DRIVE9_BANK2_PIN15_MA 28
-#define BM_PINCTRL_DRIVE9_BANK2_PIN15_MA 0x30000000
-#define BF_PINCTRL_DRIVE9_BANK2_PIN15_MA(v) \
- (((v) << 28) & BM_PINCTRL_DRIVE9_BANK2_PIN15_MA)
-#define BM_PINCTRL_DRIVE9_RSRVD6 0x08000000
-#define BM_PINCTRL_DRIVE9_BANK2_PIN14_V 0x04000000
-#define BP_PINCTRL_DRIVE9_BANK2_PIN14_MA 24
-#define BM_PINCTRL_DRIVE9_BANK2_PIN14_MA 0x03000000
-#define BF_PINCTRL_DRIVE9_BANK2_PIN14_MA(v) \
- (((v) << 24) & BM_PINCTRL_DRIVE9_BANK2_PIN14_MA)
-#define BM_PINCTRL_DRIVE9_RSRVD5 0x00800000
-#define BM_PINCTRL_DRIVE9_BANK2_PIN13_V 0x00400000
-#define BP_PINCTRL_DRIVE9_BANK2_PIN13_MA 20
-#define BM_PINCTRL_DRIVE9_BANK2_PIN13_MA 0x00300000
-#define BF_PINCTRL_DRIVE9_BANK2_PIN13_MA(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE9_BANK2_PIN13_MA)
-#define BM_PINCTRL_DRIVE9_RSRVD4 0x00080000
-#define BM_PINCTRL_DRIVE9_BANK2_PIN12_V 0x00040000
-#define BP_PINCTRL_DRIVE9_BANK2_PIN12_MA 16
-#define BM_PINCTRL_DRIVE9_BANK2_PIN12_MA 0x00030000
-#define BF_PINCTRL_DRIVE9_BANK2_PIN12_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE9_BANK2_PIN12_MA)
-#define BP_PINCTRL_DRIVE9_RSRVD3 12
-#define BM_PINCTRL_DRIVE9_RSRVD3 0x0000F000
-#define BF_PINCTRL_DRIVE9_RSRVD3(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE9_RSRVD3)
-#define BM_PINCTRL_DRIVE9_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE9_BANK2_PIN10_V 0x00000400
-#define BP_PINCTRL_DRIVE9_BANK2_PIN10_MA 8
-#define BM_PINCTRL_DRIVE9_BANK2_PIN10_MA 0x00000300
-#define BF_PINCTRL_DRIVE9_BANK2_PIN10_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE9_BANK2_PIN10_MA)
-#define BM_PINCTRL_DRIVE9_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE9_BANK2_PIN09_V 0x00000040
-#define BP_PINCTRL_DRIVE9_BANK2_PIN09_MA 4
-#define BM_PINCTRL_DRIVE9_BANK2_PIN09_MA 0x00000030
-#define BF_PINCTRL_DRIVE9_BANK2_PIN09_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE9_BANK2_PIN09_MA)
-#define BM_PINCTRL_DRIVE9_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE9_BANK2_PIN08_V 0x00000004
-#define BP_PINCTRL_DRIVE9_BANK2_PIN08_MA 0
-#define BM_PINCTRL_DRIVE9_BANK2_PIN08_MA 0x00000003
-#define BF_PINCTRL_DRIVE9_BANK2_PIN08_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE9_BANK2_PIN08_MA)
-
-#define HW_PINCTRL_DRIVE10 0x000003a0
-#define HW_PINCTRL_DRIVE10_SET 0x000003a4
-#define HW_PINCTRL_DRIVE10_CLR 0x000003a8
-#define HW_PINCTRL_DRIVE10_TOG 0x000003ac
-
-#define BP_PINCTRL_DRIVE10_RSRVD6 24
-#define BM_PINCTRL_DRIVE10_RSRVD6 0xFF000000
-#define BF_PINCTRL_DRIVE10_RSRVD6(v) \
- (((v) << 24) & BM_PINCTRL_DRIVE10_RSRVD6)
-#define BM_PINCTRL_DRIVE10_RSRVD5 0x00800000
-#define BM_PINCTRL_DRIVE10_BANK2_PIN21_V 0x00400000
-#define BP_PINCTRL_DRIVE10_BANK2_PIN21_MA 20
-#define BM_PINCTRL_DRIVE10_BANK2_PIN21_MA 0x00300000
-#define BF_PINCTRL_DRIVE10_BANK2_PIN21_MA(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE10_BANK2_PIN21_MA)
-#define BM_PINCTRL_DRIVE10_RSRVD4 0x00080000
-#define BM_PINCTRL_DRIVE10_BANK2_PIN20_V 0x00040000
-#define BP_PINCTRL_DRIVE10_BANK2_PIN20_MA 16
-#define BM_PINCTRL_DRIVE10_BANK2_PIN20_MA 0x00030000
-#define BF_PINCTRL_DRIVE10_BANK2_PIN20_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE10_BANK2_PIN20_MA)
-#define BM_PINCTRL_DRIVE10_RSRVD3 0x00008000
-#define BM_PINCTRL_DRIVE10_BANK2_PIN19_V 0x00004000
-#define BP_PINCTRL_DRIVE10_BANK2_PIN19_MA 12
-#define BM_PINCTRL_DRIVE10_BANK2_PIN19_MA 0x00003000
-#define BF_PINCTRL_DRIVE10_BANK2_PIN19_MA(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE10_BANK2_PIN19_MA)
-#define BM_PINCTRL_DRIVE10_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE10_BANK2_PIN18_V 0x00000400
-#define BP_PINCTRL_DRIVE10_BANK2_PIN18_MA 8
-#define BM_PINCTRL_DRIVE10_BANK2_PIN18_MA 0x00000300
-#define BF_PINCTRL_DRIVE10_BANK2_PIN18_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE10_BANK2_PIN18_MA)
-#define BM_PINCTRL_DRIVE10_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE10_BANK2_PIN17_V 0x00000040
-#define BP_PINCTRL_DRIVE10_BANK2_PIN17_MA 4
-#define BM_PINCTRL_DRIVE10_BANK2_PIN17_MA 0x00000030
-#define BF_PINCTRL_DRIVE10_BANK2_PIN17_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE10_BANK2_PIN17_MA)
-#define BM_PINCTRL_DRIVE10_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE10_BANK2_PIN16_V 0x00000004
-#define BP_PINCTRL_DRIVE10_BANK2_PIN16_MA 0
-#define BM_PINCTRL_DRIVE10_BANK2_PIN16_MA 0x00000003
-#define BF_PINCTRL_DRIVE10_BANK2_PIN16_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE10_BANK2_PIN16_MA)
-
-#define HW_PINCTRL_DRIVE11 0x000003b0
-#define HW_PINCTRL_DRIVE11_SET 0x000003b4
-#define HW_PINCTRL_DRIVE11_CLR 0x000003b8
-#define HW_PINCTRL_DRIVE11_TOG 0x000003bc
-
-#define BP_PINCTRL_DRIVE11_RSRVD4 16
-#define BM_PINCTRL_DRIVE11_RSRVD4 0xFFFF0000
-#define BF_PINCTRL_DRIVE11_RSRVD4(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE11_RSRVD4)
-#define BM_PINCTRL_DRIVE11_RSRVD3 0x00008000
-#define BM_PINCTRL_DRIVE11_BANK2_PIN27_V 0x00004000
-#define BP_PINCTRL_DRIVE11_BANK2_PIN27_MA 12
-#define BM_PINCTRL_DRIVE11_BANK2_PIN27_MA 0x00003000
-#define BF_PINCTRL_DRIVE11_BANK2_PIN27_MA(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE11_BANK2_PIN27_MA)
-#define BM_PINCTRL_DRIVE11_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE11_BANK2_PIN26_V 0x00000400
-#define BP_PINCTRL_DRIVE11_BANK2_PIN26_MA 8
-#define BM_PINCTRL_DRIVE11_BANK2_PIN26_MA 0x00000300
-#define BF_PINCTRL_DRIVE11_BANK2_PIN26_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE11_BANK2_PIN26_MA)
-#define BM_PINCTRL_DRIVE11_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE11_BANK2_PIN25_V 0x00000040
-#define BP_PINCTRL_DRIVE11_BANK2_PIN25_MA 4
-#define BM_PINCTRL_DRIVE11_BANK2_PIN25_MA 0x00000030
-#define BF_PINCTRL_DRIVE11_BANK2_PIN25_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE11_BANK2_PIN25_MA)
-#define BM_PINCTRL_DRIVE11_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE11_BANK2_PIN24_V 0x00000004
-#define BP_PINCTRL_DRIVE11_BANK2_PIN24_MA 0
-#define BM_PINCTRL_DRIVE11_BANK2_PIN24_MA 0x00000003
-#define BF_PINCTRL_DRIVE11_BANK2_PIN24_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE11_BANK2_PIN24_MA)
-
-#define HW_PINCTRL_DRIVE12 0x000003c0
-#define HW_PINCTRL_DRIVE12_SET 0x000003c4
-#define HW_PINCTRL_DRIVE12_CLR 0x000003c8
-#define HW_PINCTRL_DRIVE12_TOG 0x000003cc
-
-#define BM_PINCTRL_DRIVE12_RSRVD7 0x80000000
-#define BM_PINCTRL_DRIVE12_BANK3_PIN07_V 0x40000000
-#define BP_PINCTRL_DRIVE12_BANK3_PIN07_MA 28
-#define BM_PINCTRL_DRIVE12_BANK3_PIN07_MA 0x30000000
-#define BF_PINCTRL_DRIVE12_BANK3_PIN07_MA(v) \
- (((v) << 28) & BM_PINCTRL_DRIVE12_BANK3_PIN07_MA)
-#define BM_PINCTRL_DRIVE12_RSRVD6 0x08000000
-#define BM_PINCTRL_DRIVE12_BANK3_PIN06_V 0x04000000
-#define BP_PINCTRL_DRIVE12_BANK3_PIN06_MA 24
-#define BM_PINCTRL_DRIVE12_BANK3_PIN06_MA 0x03000000
-#define BF_PINCTRL_DRIVE12_BANK3_PIN06_MA(v) \
- (((v) << 24) & BM_PINCTRL_DRIVE12_BANK3_PIN06_MA)
-#define BM_PINCTRL_DRIVE12_RSRVD5 0x00800000
-#define BM_PINCTRL_DRIVE12_BANK3_PIN05_V 0x00400000
-#define BP_PINCTRL_DRIVE12_BANK3_PIN05_MA 20
-#define BM_PINCTRL_DRIVE12_BANK3_PIN05_MA 0x00300000
-#define BF_PINCTRL_DRIVE12_BANK3_PIN05_MA(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE12_BANK3_PIN05_MA)
-#define BM_PINCTRL_DRIVE12_RSRVD4 0x00080000
-#define BM_PINCTRL_DRIVE12_BANK3_PIN04_V 0x00040000
-#define BP_PINCTRL_DRIVE12_BANK3_PIN04_MA 16
-#define BM_PINCTRL_DRIVE12_BANK3_PIN04_MA 0x00030000
-#define BF_PINCTRL_DRIVE12_BANK3_PIN04_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE12_BANK3_PIN04_MA)
-#define BM_PINCTRL_DRIVE12_RSRVD3 0x00008000
-#define BM_PINCTRL_DRIVE12_BANK3_PIN03_V 0x00004000
-#define BP_PINCTRL_DRIVE12_BANK3_PIN03_MA 12
-#define BM_PINCTRL_DRIVE12_BANK3_PIN03_MA 0x00003000
-#define BF_PINCTRL_DRIVE12_BANK3_PIN03_MA(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE12_BANK3_PIN03_MA)
-#define BM_PINCTRL_DRIVE12_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE12_BANK3_PIN02_V 0x00000400
-#define BP_PINCTRL_DRIVE12_BANK3_PIN02_MA 8
-#define BM_PINCTRL_DRIVE12_BANK3_PIN02_MA 0x00000300
-#define BF_PINCTRL_DRIVE12_BANK3_PIN02_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE12_BANK3_PIN02_MA)
-#define BM_PINCTRL_DRIVE12_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE12_BANK3_PIN01_V 0x00000040
-#define BP_PINCTRL_DRIVE12_BANK3_PIN01_MA 4
-#define BM_PINCTRL_DRIVE12_BANK3_PIN01_MA 0x00000030
-#define BF_PINCTRL_DRIVE12_BANK3_PIN01_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE12_BANK3_PIN01_MA)
-#define BM_PINCTRL_DRIVE12_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE12_BANK3_PIN00_V 0x00000004
-#define BP_PINCTRL_DRIVE12_BANK3_PIN00_MA 0
-#define BM_PINCTRL_DRIVE12_BANK3_PIN00_MA 0x00000003
-#define BF_PINCTRL_DRIVE12_BANK3_PIN00_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE12_BANK3_PIN00_MA)
-
-#define HW_PINCTRL_DRIVE13 0x000003d0
-#define HW_PINCTRL_DRIVE13_SET 0x000003d4
-#define HW_PINCTRL_DRIVE13_CLR 0x000003d8
-#define HW_PINCTRL_DRIVE13_TOG 0x000003dc
-
-#define BM_PINCTRL_DRIVE13_RSRVD7 0x80000000
-#define BM_PINCTRL_DRIVE13_BANK3_PIN15_V 0x40000000
-#define BP_PINCTRL_DRIVE13_BANK3_PIN15_MA 28
-#define BM_PINCTRL_DRIVE13_BANK3_PIN15_MA 0x30000000
-#define BF_PINCTRL_DRIVE13_BANK3_PIN15_MA(v) \
- (((v) << 28) & BM_PINCTRL_DRIVE13_BANK3_PIN15_MA)
-#define BM_PINCTRL_DRIVE13_RSRVD6 0x08000000
-#define BM_PINCTRL_DRIVE13_BANK3_PIN14_V 0x04000000
-#define BP_PINCTRL_DRIVE13_BANK3_PIN14_MA 24
-#define BM_PINCTRL_DRIVE13_BANK3_PIN14_MA 0x03000000
-#define BF_PINCTRL_DRIVE13_BANK3_PIN14_MA(v) \
- (((v) << 24) & BM_PINCTRL_DRIVE13_BANK3_PIN14_MA)
-#define BM_PINCTRL_DRIVE13_RSRVD5 0x00800000
-#define BM_PINCTRL_DRIVE13_BANK3_PIN13_V 0x00400000
-#define BP_PINCTRL_DRIVE13_BANK3_PIN13_MA 20
-#define BM_PINCTRL_DRIVE13_BANK3_PIN13_MA 0x00300000
-#define BF_PINCTRL_DRIVE13_BANK3_PIN13_MA(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE13_BANK3_PIN13_MA)
-#define BM_PINCTRL_DRIVE13_RSRVD4 0x00080000
-#define BM_PINCTRL_DRIVE13_BANK3_PIN12_V 0x00040000
-#define BP_PINCTRL_DRIVE13_BANK3_PIN12_MA 16
-#define BM_PINCTRL_DRIVE13_BANK3_PIN12_MA 0x00030000
-#define BF_PINCTRL_DRIVE13_BANK3_PIN12_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE13_BANK3_PIN12_MA)
-#define BM_PINCTRL_DRIVE13_RSRVD3 0x00008000
-#define BM_PINCTRL_DRIVE13_BANK3_PIN11_V 0x00004000
-#define BP_PINCTRL_DRIVE13_BANK3_PIN11_MA 12
-#define BM_PINCTRL_DRIVE13_BANK3_PIN11_MA 0x00003000
-#define BF_PINCTRL_DRIVE13_BANK3_PIN11_MA(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE13_BANK3_PIN11_MA)
-#define BM_PINCTRL_DRIVE13_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE13_BANK3_PIN10_V 0x00000400
-#define BP_PINCTRL_DRIVE13_BANK3_PIN10_MA 8
-#define BM_PINCTRL_DRIVE13_BANK3_PIN10_MA 0x00000300
-#define BF_PINCTRL_DRIVE13_BANK3_PIN10_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE13_BANK3_PIN10_MA)
-#define BM_PINCTRL_DRIVE13_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE13_BANK3_PIN09_V 0x00000040
-#define BP_PINCTRL_DRIVE13_BANK3_PIN09_MA 4
-#define BM_PINCTRL_DRIVE13_BANK3_PIN09_MA 0x00000030
-#define BF_PINCTRL_DRIVE13_BANK3_PIN09_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE13_BANK3_PIN09_MA)
-#define BM_PINCTRL_DRIVE13_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE13_BANK3_PIN08_V 0x00000004
-#define BP_PINCTRL_DRIVE13_BANK3_PIN08_MA 0
-#define BM_PINCTRL_DRIVE13_BANK3_PIN08_MA 0x00000003
-#define BF_PINCTRL_DRIVE13_BANK3_PIN08_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE13_BANK3_PIN08_MA)
-
-#define HW_PINCTRL_DRIVE14 0x000003e0
-#define HW_PINCTRL_DRIVE14_SET 0x000003e4
-#define HW_PINCTRL_DRIVE14_CLR 0x000003e8
-#define HW_PINCTRL_DRIVE14_TOG 0x000003ec
-
-#define BM_PINCTRL_DRIVE14_RSRVD7 0x80000000
-#define BM_PINCTRL_DRIVE14_BANK3_PIN23_V 0x40000000
-#define BP_PINCTRL_DRIVE14_BANK3_PIN23_MA 28
-#define BM_PINCTRL_DRIVE14_BANK3_PIN23_MA 0x30000000
-#define BF_PINCTRL_DRIVE14_BANK3_PIN23_MA(v) \
- (((v) << 28) & BM_PINCTRL_DRIVE14_BANK3_PIN23_MA)
-#define BM_PINCTRL_DRIVE14_RSRVD6 0x08000000
-#define BM_PINCTRL_DRIVE14_BANK3_PIN22_V 0x04000000
-#define BP_PINCTRL_DRIVE14_BANK3_PIN22_MA 24
-#define BM_PINCTRL_DRIVE14_BANK3_PIN22_MA 0x03000000
-#define BF_PINCTRL_DRIVE14_BANK3_PIN22_MA(v) \
- (((v) << 24) & BM_PINCTRL_DRIVE14_BANK3_PIN22_MA)
-#define BM_PINCTRL_DRIVE14_RSRVD5 0x00800000
-#define BM_PINCTRL_DRIVE14_BANK3_PIN21_V 0x00400000
-#define BP_PINCTRL_DRIVE14_BANK3_PIN21_MA 20
-#define BM_PINCTRL_DRIVE14_BANK3_PIN21_MA 0x00300000
-#define BF_PINCTRL_DRIVE14_BANK3_PIN21_MA(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE14_BANK3_PIN21_MA)
-#define BM_PINCTRL_DRIVE14_RSRVD4 0x00080000
-#define BM_PINCTRL_DRIVE14_BANK3_PIN20_V 0x00040000
-#define BP_PINCTRL_DRIVE14_BANK3_PIN20_MA 16
-#define BM_PINCTRL_DRIVE14_BANK3_PIN20_MA 0x00030000
-#define BF_PINCTRL_DRIVE14_BANK3_PIN20_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE14_BANK3_PIN20_MA)
-#define BP_PINCTRL_DRIVE14_RSRVD3 12
-#define BM_PINCTRL_DRIVE14_RSRVD3 0x0000F000
-#define BF_PINCTRL_DRIVE14_RSRVD3(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE14_RSRVD3)
-#define BM_PINCTRL_DRIVE14_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE14_BANK3_PIN18_V 0x00000400
-#define BP_PINCTRL_DRIVE14_BANK3_PIN18_MA 8
-#define BM_PINCTRL_DRIVE14_BANK3_PIN18_MA 0x00000300
-#define BF_PINCTRL_DRIVE14_BANK3_PIN18_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE14_BANK3_PIN18_MA)
-#define BM_PINCTRL_DRIVE14_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE14_BANK3_PIN17_V 0x00000040
-#define BP_PINCTRL_DRIVE14_BANK3_PIN17_MA 4
-#define BM_PINCTRL_DRIVE14_BANK3_PIN17_MA 0x00000030
-#define BF_PINCTRL_DRIVE14_BANK3_PIN17_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE14_BANK3_PIN17_MA)
-#define BM_PINCTRL_DRIVE14_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE14_BANK3_PIN16_V 0x00000004
-#define BP_PINCTRL_DRIVE14_BANK3_PIN16_MA 0
-#define BM_PINCTRL_DRIVE14_BANK3_PIN16_MA 0x00000003
-#define BF_PINCTRL_DRIVE14_BANK3_PIN16_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE14_BANK3_PIN16_MA)
-
-#define HW_PINCTRL_DRIVE15 0x000003f0
-#define HW_PINCTRL_DRIVE15_SET 0x000003f4
-#define HW_PINCTRL_DRIVE15_CLR 0x000003f8
-#define HW_PINCTRL_DRIVE15_TOG 0x000003fc
-
-#define BP_PINCTRL_DRIVE15_RSRVD7 28
-#define BM_PINCTRL_DRIVE15_RSRVD7 0xF0000000
-#define BF_PINCTRL_DRIVE15_RSRVD7(v) \
- (((v) << 28) & BM_PINCTRL_DRIVE15_RSRVD7)
-#define BM_PINCTRL_DRIVE15_RSRVD6 0x08000000
-#define BM_PINCTRL_DRIVE15_BANK3_PIN30_V 0x04000000
-#define BP_PINCTRL_DRIVE15_BANK3_PIN30_MA 24
-#define BM_PINCTRL_DRIVE15_BANK3_PIN30_MA 0x03000000
-#define BF_PINCTRL_DRIVE15_BANK3_PIN30_MA(v) \
- (((v) << 24) & BM_PINCTRL_DRIVE15_BANK3_PIN30_MA)
-#define BM_PINCTRL_DRIVE15_RSRVD5 0x00800000
-#define BM_PINCTRL_DRIVE15_BANK3_PIN29_V 0x00400000
-#define BP_PINCTRL_DRIVE15_BANK3_PIN29_MA 20
-#define BM_PINCTRL_DRIVE15_BANK3_PIN29_MA 0x00300000
-#define BF_PINCTRL_DRIVE15_BANK3_PIN29_MA(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE15_BANK3_PIN29_MA)
-#define BM_PINCTRL_DRIVE15_RSRVD4 0x00080000
-#define BM_PINCTRL_DRIVE15_BANK3_PIN28_V 0x00040000
-#define BP_PINCTRL_DRIVE15_BANK3_PIN28_MA 16
-#define BM_PINCTRL_DRIVE15_BANK3_PIN28_MA 0x00030000
-#define BF_PINCTRL_DRIVE15_BANK3_PIN28_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE15_BANK3_PIN28_MA)
-#define BM_PINCTRL_DRIVE15_RSRVD3 0x00008000
-#define BM_PINCTRL_DRIVE15_BANK3_PIN27_V 0x00004000
-#define BP_PINCTRL_DRIVE15_BANK3_PIN27_MA 12
-#define BM_PINCTRL_DRIVE15_BANK3_PIN27_MA 0x00003000
-#define BF_PINCTRL_DRIVE15_BANK3_PIN27_MA(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE15_BANK3_PIN27_MA)
-#define BM_PINCTRL_DRIVE15_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE15_BANK3_PIN26_V 0x00000400
-#define BP_PINCTRL_DRIVE15_BANK3_PIN26_MA 8
-#define BM_PINCTRL_DRIVE15_BANK3_PIN26_MA 0x00000300
-#define BF_PINCTRL_DRIVE15_BANK3_PIN26_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE15_BANK3_PIN26_MA)
-#define BM_PINCTRL_DRIVE15_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE15_BANK3_PIN25_V 0x00000040
-#define BP_PINCTRL_DRIVE15_BANK3_PIN25_MA 4
-#define BM_PINCTRL_DRIVE15_BANK3_PIN25_MA 0x00000030
-#define BF_PINCTRL_DRIVE15_BANK3_PIN25_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE15_BANK3_PIN25_MA)
-#define BM_PINCTRL_DRIVE15_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE15_BANK3_PIN24_V 0x00000004
-#define BP_PINCTRL_DRIVE15_BANK3_PIN24_MA 0
-#define BM_PINCTRL_DRIVE15_BANK3_PIN24_MA 0x00000003
-#define BF_PINCTRL_DRIVE15_BANK3_PIN24_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE15_BANK3_PIN24_MA)
-
-#define HW_PINCTRL_DRIVE16 0x00000400
-#define HW_PINCTRL_DRIVE16_SET 0x00000404
-#define HW_PINCTRL_DRIVE16_CLR 0x00000408
-#define HW_PINCTRL_DRIVE16_TOG 0x0000040c
-
-#define BM_PINCTRL_DRIVE16_RSRVD7 0x80000000
-#define BM_PINCTRL_DRIVE16_BANK4_PIN07_V 0x40000000
-#define BP_PINCTRL_DRIVE16_BANK4_PIN07_MA 28
-#define BM_PINCTRL_DRIVE16_BANK4_PIN07_MA 0x30000000
-#define BF_PINCTRL_DRIVE16_BANK4_PIN07_MA(v) \
- (((v) << 28) & BM_PINCTRL_DRIVE16_BANK4_PIN07_MA)
-#define BM_PINCTRL_DRIVE16_RSRVD6 0x08000000
-#define BM_PINCTRL_DRIVE16_BANK4_PIN06_V 0x04000000
-#define BP_PINCTRL_DRIVE16_BANK4_PIN06_MA 24
-#define BM_PINCTRL_DRIVE16_BANK4_PIN06_MA 0x03000000
-#define BF_PINCTRL_DRIVE16_BANK4_PIN06_MA(v) \
- (((v) << 24) & BM_PINCTRL_DRIVE16_BANK4_PIN06_MA)
-#define BM_PINCTRL_DRIVE16_RSRVD5 0x00800000
-#define BM_PINCTRL_DRIVE16_BANK4_PIN05_V 0x00400000
-#define BP_PINCTRL_DRIVE16_BANK4_PIN05_MA 20
-#define BM_PINCTRL_DRIVE16_BANK4_PIN05_MA 0x00300000
-#define BF_PINCTRL_DRIVE16_BANK4_PIN05_MA(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE16_BANK4_PIN05_MA)
-#define BM_PINCTRL_DRIVE16_RSRVD4 0x00080000
-#define BM_PINCTRL_DRIVE16_BANK4_PIN04_V 0x00040000
-#define BP_PINCTRL_DRIVE16_BANK4_PIN04_MA 16
-#define BM_PINCTRL_DRIVE16_BANK4_PIN04_MA 0x00030000
-#define BF_PINCTRL_DRIVE16_BANK4_PIN04_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE16_BANK4_PIN04_MA)
-#define BM_PINCTRL_DRIVE16_RSRVD3 0x00008000
-#define BM_PINCTRL_DRIVE16_BANK4_PIN03_V 0x00004000
-#define BP_PINCTRL_DRIVE16_BANK4_PIN03_MA 12
-#define BM_PINCTRL_DRIVE16_BANK4_PIN03_MA 0x00003000
-#define BF_PINCTRL_DRIVE16_BANK4_PIN03_MA(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE16_BANK4_PIN03_MA)
-#define BM_PINCTRL_DRIVE16_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE16_BANK4_PIN02_V 0x00000400
-#define BP_PINCTRL_DRIVE16_BANK4_PIN02_MA 8
-#define BM_PINCTRL_DRIVE16_BANK4_PIN02_MA 0x00000300
-#define BF_PINCTRL_DRIVE16_BANK4_PIN02_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE16_BANK4_PIN02_MA)
-#define BM_PINCTRL_DRIVE16_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE16_BANK4_PIN01_V 0x00000040
-#define BP_PINCTRL_DRIVE16_BANK4_PIN01_MA 4
-#define BM_PINCTRL_DRIVE16_BANK4_PIN01_MA 0x00000030
-#define BF_PINCTRL_DRIVE16_BANK4_PIN01_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE16_BANK4_PIN01_MA)
-#define BM_PINCTRL_DRIVE16_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE16_BANK4_PIN00_V 0x00000004
-#define BP_PINCTRL_DRIVE16_BANK4_PIN00_MA 0
-#define BM_PINCTRL_DRIVE16_BANK4_PIN00_MA 0x00000003
-#define BF_PINCTRL_DRIVE16_BANK4_PIN00_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE16_BANK4_PIN00_MA)
-
-#define HW_PINCTRL_DRIVE17 0x00000410
-#define HW_PINCTRL_DRIVE17_SET 0x00000414
-#define HW_PINCTRL_DRIVE17_CLR 0x00000418
-#define HW_PINCTRL_DRIVE17_TOG 0x0000041c
-
-#define BM_PINCTRL_DRIVE17_RSRVD7 0x80000000
-#define BM_PINCTRL_DRIVE17_BANK4_PIN15_V 0x40000000
-#define BP_PINCTRL_DRIVE17_BANK4_PIN15_MA 28
-#define BM_PINCTRL_DRIVE17_BANK4_PIN15_MA 0x30000000
-#define BF_PINCTRL_DRIVE17_BANK4_PIN15_MA(v) \
- (((v) << 28) & BM_PINCTRL_DRIVE17_BANK4_PIN15_MA)
-#define BM_PINCTRL_DRIVE17_RSRVD6 0x08000000
-#define BM_PINCTRL_DRIVE17_BANK4_PIN14_V 0x04000000
-#define BP_PINCTRL_DRIVE17_BANK4_PIN14_MA 24
-#define BM_PINCTRL_DRIVE17_BANK4_PIN14_MA 0x03000000
-#define BF_PINCTRL_DRIVE17_BANK4_PIN14_MA(v) \
- (((v) << 24) & BM_PINCTRL_DRIVE17_BANK4_PIN14_MA)
-#define BM_PINCTRL_DRIVE17_RSRVD5 0x00800000
-#define BM_PINCTRL_DRIVE17_BANK4_PIN13_V 0x00400000
-#define BP_PINCTRL_DRIVE17_BANK4_PIN13_MA 20
-#define BM_PINCTRL_DRIVE17_BANK4_PIN13_MA 0x00300000
-#define BF_PINCTRL_DRIVE17_BANK4_PIN13_MA(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE17_BANK4_PIN13_MA)
-#define BM_PINCTRL_DRIVE17_RSRVD4 0x00080000
-#define BM_PINCTRL_DRIVE17_BANK4_PIN12_V 0x00040000
-#define BP_PINCTRL_DRIVE17_BANK4_PIN12_MA 16
-#define BM_PINCTRL_DRIVE17_BANK4_PIN12_MA 0x00030000
-#define BF_PINCTRL_DRIVE17_BANK4_PIN12_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE17_BANK4_PIN12_MA)
-#define BM_PINCTRL_DRIVE17_RSRVD3 0x00008000
-#define BM_PINCTRL_DRIVE17_BANK4_PIN11_V 0x00004000
-#define BP_PINCTRL_DRIVE17_BANK4_PIN11_MA 12
-#define BM_PINCTRL_DRIVE17_BANK4_PIN11_MA 0x00003000
-#define BF_PINCTRL_DRIVE17_BANK4_PIN11_MA(v) \
- (((v) << 12) & BM_PINCTRL_DRIVE17_BANK4_PIN11_MA)
-#define BM_PINCTRL_DRIVE17_RSRVD2 0x00000800
-#define BM_PINCTRL_DRIVE17_BANK4_PIN10_V 0x00000400
-#define BP_PINCTRL_DRIVE17_BANK4_PIN10_MA 8
-#define BM_PINCTRL_DRIVE17_BANK4_PIN10_MA 0x00000300
-#define BF_PINCTRL_DRIVE17_BANK4_PIN10_MA(v) \
- (((v) << 8) & BM_PINCTRL_DRIVE17_BANK4_PIN10_MA)
-#define BM_PINCTRL_DRIVE17_RSRVD1 0x00000080
-#define BM_PINCTRL_DRIVE17_BANK4_PIN09_V 0x00000040
-#define BP_PINCTRL_DRIVE17_BANK4_PIN09_MA 4
-#define BM_PINCTRL_DRIVE17_BANK4_PIN09_MA 0x00000030
-#define BF_PINCTRL_DRIVE17_BANK4_PIN09_MA(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE17_BANK4_PIN09_MA)
-#define BM_PINCTRL_DRIVE17_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE17_BANK4_PIN08_V 0x00000004
-#define BP_PINCTRL_DRIVE17_BANK4_PIN08_MA 0
-#define BM_PINCTRL_DRIVE17_BANK4_PIN08_MA 0x00000003
-#define BF_PINCTRL_DRIVE17_BANK4_PIN08_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE17_BANK4_PIN08_MA)
-
-#define HW_PINCTRL_DRIVE18 0x00000420
-#define HW_PINCTRL_DRIVE18_SET 0x00000424
-#define HW_PINCTRL_DRIVE18_CLR 0x00000428
-#define HW_PINCTRL_DRIVE18_TOG 0x0000042c
-
-#define BP_PINCTRL_DRIVE18_RSRVD3 20
-#define BM_PINCTRL_DRIVE18_RSRVD3 0xFFF00000
-#define BF_PINCTRL_DRIVE18_RSRVD3(v) \
- (((v) << 20) & BM_PINCTRL_DRIVE18_RSRVD3)
-#define BM_PINCTRL_DRIVE18_RSRVD2 0x00080000
-#define BM_PINCTRL_DRIVE18_BANK4_PIN20_V 0x00040000
-#define BP_PINCTRL_DRIVE18_BANK4_PIN20_MA 16
-#define BM_PINCTRL_DRIVE18_BANK4_PIN20_MA 0x00030000
-#define BF_PINCTRL_DRIVE18_BANK4_PIN20_MA(v) \
- (((v) << 16) & BM_PINCTRL_DRIVE18_BANK4_PIN20_MA)
-#define BP_PINCTRL_DRIVE18_RSRVD1 4
-#define BM_PINCTRL_DRIVE18_RSRVD1 0x0000FFF0
-#define BF_PINCTRL_DRIVE18_RSRVD1(v) \
- (((v) << 4) & BM_PINCTRL_DRIVE18_RSRVD1)
-#define BM_PINCTRL_DRIVE18_RSRVD0 0x00000008
-#define BM_PINCTRL_DRIVE18_BANK4_PIN16_V 0x00000004
-#define BP_PINCTRL_DRIVE18_BANK4_PIN16_MA 0
-#define BM_PINCTRL_DRIVE18_BANK4_PIN16_MA 0x00000003
-#define BF_PINCTRL_DRIVE18_BANK4_PIN16_MA(v) \
- (((v) << 0) & BM_PINCTRL_DRIVE18_BANK4_PIN16_MA)
-
-#define HW_PINCTRL_DRIVE19 0x00000430
-#define HW_PINCTRL_DRIVE19_SET 0x00000434
-#define HW_PINCTRL_DRIVE19_CLR 0x00000438
-#define HW_PINCTRL_DRIVE19_TOG 0x0000043c
-
-#define BP_PINCTRL_DRIVE19_RSRVD0 0
-#define BM_PINCTRL_DRIVE19_RSRVD0 0xFFFFFFFF
-#define BF_PINCTRL_DRIVE19_RSRVD0(v) (v)
-
-#define HW_PINCTRL_PULL0 0x00000600
-#define HW_PINCTRL_PULL0_SET 0x00000604
-#define HW_PINCTRL_PULL0_CLR 0x00000608
-#define HW_PINCTRL_PULL0_TOG 0x0000060c
-
-#define BP_PINCTRL_PULL0_RSRVD1 29
-#define BM_PINCTRL_PULL0_RSRVD1 0xE0000000
-#define BF_PINCTRL_PULL0_RSRVD1(v) \
- (((v) << 29) & BM_PINCTRL_PULL0_RSRVD1)
-#define BM_PINCTRL_PULL0_BANK0_PIN28 0x10000000
-#define BM_PINCTRL_PULL0_BANK0_PIN27 0x08000000
-#define BM_PINCTRL_PULL0_BANK0_PIN26 0x04000000
-#define BM_PINCTRL_PULL0_BANK0_PIN25 0x02000000
-#define BM_PINCTRL_PULL0_BANK0_PIN24 0x01000000
-#define BM_PINCTRL_PULL0_BANK0_PIN23 0x00800000
-#define BM_PINCTRL_PULL0_BANK0_PIN22 0x00400000
-#define BM_PINCTRL_PULL0_BANK0_PIN21 0x00200000
-#define BM_PINCTRL_PULL0_BANK0_PIN20 0x00100000
-#define BM_PINCTRL_PULL0_BANK0_PIN19 0x00080000
-#define BM_PINCTRL_PULL0_BANK0_PIN18 0x00040000
-#define BM_PINCTRL_PULL0_BANK0_PIN17 0x00020000
-#define BM_PINCTRL_PULL0_BANK0_PIN16 0x00010000
-#define BP_PINCTRL_PULL0_RSRVD0 8
-#define BM_PINCTRL_PULL0_RSRVD0 0x0000FF00
-#define BF_PINCTRL_PULL0_RSRVD0(v) \
- (((v) << 8) & BM_PINCTRL_PULL0_RSRVD0)
-#define BM_PINCTRL_PULL0_BANK0_PIN07 0x00000080
-#define BM_PINCTRL_PULL0_BANK0_PIN06 0x00000040
-#define BM_PINCTRL_PULL0_BANK0_PIN05 0x00000020
-#define BM_PINCTRL_PULL0_BANK0_PIN04 0x00000010
-#define BM_PINCTRL_PULL0_BANK0_PIN03 0x00000008
-#define BM_PINCTRL_PULL0_BANK0_PIN02 0x00000004
-#define BM_PINCTRL_PULL0_BANK0_PIN01 0x00000002
-#define BM_PINCTRL_PULL0_BANK0_PIN00 0x00000001
-
-#define HW_PINCTRL_PULL1 0x00000610
-#define HW_PINCTRL_PULL1_SET 0x00000614
-#define HW_PINCTRL_PULL1_CLR 0x00000618
-#define HW_PINCTRL_PULL1_TOG 0x0000061c
-
-#define BM_PINCTRL_PULL1_BANK1_PIN31 0x80000000
-#define BM_PINCTRL_PULL1_BANK1_PIN30 0x40000000
-#define BM_PINCTRL_PULL1_BANK1_PIN29 0x20000000
-#define BM_PINCTRL_PULL1_BANK1_PIN28 0x10000000
-#define BM_PINCTRL_PULL1_BANK1_PIN27 0x08000000
-#define BM_PINCTRL_PULL1_BANK1_PIN26 0x04000000
-#define BM_PINCTRL_PULL1_BANK1_PIN25 0x02000000
-#define BM_PINCTRL_PULL1_BANK1_PIN24 0x01000000
-#define BM_PINCTRL_PULL1_BANK1_PIN23 0x00800000
-#define BM_PINCTRL_PULL1_BANK1_PIN22 0x00400000
-#define BM_PINCTRL_PULL1_BANK1_PIN21 0x00200000
-#define BM_PINCTRL_PULL1_BANK1_PIN20 0x00100000
-#define BM_PINCTRL_PULL1_BANK1_PIN19 0x00080000
-#define BM_PINCTRL_PULL1_BANK1_PIN18 0x00040000
-#define BM_PINCTRL_PULL1_BANK1_PIN17 0x00020000
-#define BM_PINCTRL_PULL1_BANK1_PIN16 0x00010000
-#define BM_PINCTRL_PULL1_BANK1_PIN15 0x00008000
-#define BM_PINCTRL_PULL1_BANK1_PIN14 0x00004000
-#define BM_PINCTRL_PULL1_BANK1_PIN13 0x00002000
-#define BM_PINCTRL_PULL1_BANK1_PIN12 0x00001000
-#define BM_PINCTRL_PULL1_BANK1_PIN11 0x00000800
-#define BM_PINCTRL_PULL1_BANK1_PIN10 0x00000400
-#define BM_PINCTRL_PULL1_BANK1_PIN09 0x00000200
-#define BM_PINCTRL_PULL1_BANK1_PIN08 0x00000100
-#define BM_PINCTRL_PULL1_BANK1_PIN07 0x00000080
-#define BM_PINCTRL_PULL1_BANK1_PIN06 0x00000040
-#define BM_PINCTRL_PULL1_BANK1_PIN05 0x00000020
-#define BM_PINCTRL_PULL1_BANK1_PIN04 0x00000010
-#define BM_PINCTRL_PULL1_BANK1_PIN03 0x00000008
-#define BM_PINCTRL_PULL1_BANK1_PIN02 0x00000004
-#define BM_PINCTRL_PULL1_BANK1_PIN01 0x00000002
-#define BM_PINCTRL_PULL1_BANK1_PIN00 0x00000001
-
-#define HW_PINCTRL_PULL2 0x00000620
-#define HW_PINCTRL_PULL2_SET 0x00000624
-#define HW_PINCTRL_PULL2_CLR 0x00000628
-#define HW_PINCTRL_PULL2_TOG 0x0000062c
-
-#define BP_PINCTRL_PULL2_RSRVD2 28
-#define BM_PINCTRL_PULL2_RSRVD2 0xF0000000
-#define BF_PINCTRL_PULL2_RSRVD2(v) \
- (((v) << 28) & BM_PINCTRL_PULL2_RSRVD2)
-#define BM_PINCTRL_PULL2_BANK2_PIN27 0x08000000
-#define BM_PINCTRL_PULL2_BANK2_PIN26 0x04000000
-#define BM_PINCTRL_PULL2_BANK2_PIN25 0x02000000
-#define BM_PINCTRL_PULL2_BANK2_PIN24 0x01000000
-#define BP_PINCTRL_PULL2_RSRVD1 22
-#define BM_PINCTRL_PULL2_RSRVD1 0x00C00000
-#define BF_PINCTRL_PULL2_RSRVD1(v) \
- (((v) << 22) & BM_PINCTRL_PULL2_RSRVD1)
-#define BM_PINCTRL_PULL2_BANK2_PIN21 0x00200000
-#define BM_PINCTRL_PULL2_BANK2_PIN20 0x00100000
-#define BM_PINCTRL_PULL2_BANK2_PIN19 0x00080000
-#define BM_PINCTRL_PULL2_BANK2_PIN18 0x00040000
-#define BM_PINCTRL_PULL2_BANK2_PIN17 0x00020000
-#define BM_PINCTRL_PULL2_BANK2_PIN16 0x00010000
-#define BM_PINCTRL_PULL2_BANK2_PIN15 0x00008000
-#define BM_PINCTRL_PULL2_BANK2_PIN14 0x00004000
-#define BM_PINCTRL_PULL2_BANK2_PIN13 0x00002000
-#define BM_PINCTRL_PULL2_BANK2_PIN12 0x00001000
-#define BM_PINCTRL_PULL2_RSRVD0 0x00000800
-#define BM_PINCTRL_PULL2_BANK2_PIN10 0x00000400
-#define BM_PINCTRL_PULL2_BANK2_PIN09 0x00000200
-#define BM_PINCTRL_PULL2_BANK2_PIN08 0x00000100
-#define BM_PINCTRL_PULL2_BANK2_PIN07 0x00000080
-#define BM_PINCTRL_PULL2_BANK2_PIN06 0x00000040
-#define BM_PINCTRL_PULL2_BANK2_PIN05 0x00000020
-#define BM_PINCTRL_PULL2_BANK2_PIN04 0x00000010
-#define BM_PINCTRL_PULL2_BANK2_PIN03 0x00000008
-#define BM_PINCTRL_PULL2_BANK2_PIN02 0x00000004
-#define BM_PINCTRL_PULL2_BANK2_PIN01 0x00000002
-#define BM_PINCTRL_PULL2_BANK2_PIN00 0x00000001
-
-#define HW_PINCTRL_PULL3 0x00000630
-#define HW_PINCTRL_PULL3_SET 0x00000634
-#define HW_PINCTRL_PULL3_CLR 0x00000638
-#define HW_PINCTRL_PULL3_TOG 0x0000063c
-
-#define BM_PINCTRL_PULL3_RSRVD1 0x80000000
-#define BM_PINCTRL_PULL3_BANK3_PIN30 0x40000000
-#define BM_PINCTRL_PULL3_BANK3_PIN29 0x20000000
-#define BM_PINCTRL_PULL3_BANK3_PIN28 0x10000000
-#define BM_PINCTRL_PULL3_BANK3_PIN27 0x08000000
-#define BM_PINCTRL_PULL3_BANK3_PIN26 0x04000000
-#define BM_PINCTRL_PULL3_BANK3_PIN25 0x02000000
-#define BM_PINCTRL_PULL3_BANK3_PIN24 0x01000000
-#define BM_PINCTRL_PULL3_BANK3_PIN23 0x00800000
-#define BM_PINCTRL_PULL3_BANK3_PIN22 0x00400000
-#define BM_PINCTRL_PULL3_BANK3_PIN21 0x00200000
-#define BM_PINCTRL_PULL3_BANK3_PIN20 0x00100000
-#define BM_PINCTRL_PULL3_RSRVD0 0x00080000
-#define BM_PINCTRL_PULL3_BANK3_PIN18 0x00040000
-#define BM_PINCTRL_PULL3_BANK3_PIN17 0x00020000
-#define BM_PINCTRL_PULL3_BANK3_PIN16 0x00010000
-#define BM_PINCTRL_PULL3_BANK3_PIN15 0x00008000
-#define BM_PINCTRL_PULL3_BANK3_PIN14 0x00004000
-#define BM_PINCTRL_PULL3_BANK3_PIN13 0x00002000
-#define BM_PINCTRL_PULL3_BANK3_PIN12 0x00001000
-#define BM_PINCTRL_PULL3_BANK3_PIN11 0x00000800
-#define BM_PINCTRL_PULL3_BANK3_PIN10 0x00000400
-#define BM_PINCTRL_PULL3_BANK3_PIN09 0x00000200
-#define BM_PINCTRL_PULL3_BANK3_PIN08 0x00000100
-#define BM_PINCTRL_PULL3_BANK3_PIN07 0x00000080
-#define BM_PINCTRL_PULL3_BANK3_PIN06 0x00000040
-#define BM_PINCTRL_PULL3_BANK3_PIN05 0x00000020
-#define BM_PINCTRL_PULL3_BANK3_PIN04 0x00000010
-#define BM_PINCTRL_PULL3_BANK3_PIN03 0x00000008
-#define BM_PINCTRL_PULL3_BANK3_PIN02 0x00000004
-#define BM_PINCTRL_PULL3_BANK3_PIN01 0x00000002
-#define BM_PINCTRL_PULL3_BANK3_PIN00 0x00000001
-
-#define HW_PINCTRL_PULL4 0x00000640
-#define HW_PINCTRL_PULL4_SET 0x00000644
-#define HW_PINCTRL_PULL4_CLR 0x00000648
-#define HW_PINCTRL_PULL4_TOG 0x0000064c
-
-#define BP_PINCTRL_PULL4_RSRVD1 21
-#define BM_PINCTRL_PULL4_RSRVD1 0xFFE00000
-#define BF_PINCTRL_PULL4_RSRVD1(v) \
- (((v) << 21) & BM_PINCTRL_PULL4_RSRVD1)
-#define BM_PINCTRL_PULL4_BANK4_PIN20 0x00100000
-#define BP_PINCTRL_PULL4_RSRVD0 17
-#define BM_PINCTRL_PULL4_RSRVD0 0x000E0000
-#define BF_PINCTRL_PULL4_RSRVD0(v) \
- (((v) << 17) & BM_PINCTRL_PULL4_RSRVD0)
-#define BM_PINCTRL_PULL4_BANK4_PIN16 0x00010000
-#define BM_PINCTRL_PULL4_BANK4_PIN15 0x00008000
-#define BM_PINCTRL_PULL4_BANK4_PIN14 0x00004000
-#define BM_PINCTRL_PULL4_BANK4_PIN13 0x00002000
-#define BM_PINCTRL_PULL4_BANK4_PIN12 0x00001000
-#define BM_PINCTRL_PULL4_BANK4_PIN11 0x00000800
-#define BM_PINCTRL_PULL4_BANK4_PIN10 0x00000400
-#define BM_PINCTRL_PULL4_BANK4_PIN09 0x00000200
-#define BM_PINCTRL_PULL4_BANK4_PIN08 0x00000100
-#define BM_PINCTRL_PULL4_BANK4_PIN07 0x00000080
-#define BM_PINCTRL_PULL4_BANK4_PIN06 0x00000040
-#define BM_PINCTRL_PULL4_BANK4_PIN05 0x00000020
-#define BM_PINCTRL_PULL4_BANK4_PIN04 0x00000010
-#define BM_PINCTRL_PULL4_BANK4_PIN03 0x00000008
-#define BM_PINCTRL_PULL4_BANK4_PIN02 0x00000004
-#define BM_PINCTRL_PULL4_BANK4_PIN01 0x00000002
-#define BM_PINCTRL_PULL4_BANK4_PIN00 0x00000001
-
-#define HW_PINCTRL_PULL5 0x00000650
-#define HW_PINCTRL_PULL5_SET 0x00000654
-#define HW_PINCTRL_PULL5_CLR 0x00000658
-#define HW_PINCTRL_PULL5_TOG 0x0000065c
-
-#define BP_PINCTRL_PULL5_RSRVD1 27
-#define BM_PINCTRL_PULL5_RSRVD1 0xF8000000
-#define BF_PINCTRL_PULL5_RSRVD1(v) \
- (((v) << 27) & BM_PINCTRL_PULL5_RSRVD1)
-#define BM_PINCTRL_PULL5_BANK5_PIN26 0x04000000
-#define BP_PINCTRL_PULL5_RSRVD0 24
-#define BM_PINCTRL_PULL5_RSRVD0 0x03000000
-#define BF_PINCTRL_PULL5_RSRVD0(v) \
- (((v) << 24) & BM_PINCTRL_PULL5_RSRVD0)
-#define BM_PINCTRL_PULL5_BANK5_PIN23 0x00800000
-#define BM_PINCTRL_PULL5_BANK5_PIN22 0x00400000
-#define BM_PINCTRL_PULL5_BANK5_PIN21 0x00200000
-#define BM_PINCTRL_PULL5_BANK5_PIN20 0x00100000
-#define BM_PINCTRL_PULL5_BANK5_PIN19 0x00080000
-#define BM_PINCTRL_PULL5_BANK5_PIN18 0x00040000
-#define BM_PINCTRL_PULL5_BANK5_PIN17 0x00020000
-#define BM_PINCTRL_PULL5_BANK5_PIN16 0x00010000
-#define BM_PINCTRL_PULL5_BANK5_PIN15 0x00008000
-#define BM_PINCTRL_PULL5_BANK5_PIN14 0x00004000
-#define BM_PINCTRL_PULL5_BANK5_PIN13 0x00002000
-#define BM_PINCTRL_PULL5_BANK5_PIN12 0x00001000
-#define BM_PINCTRL_PULL5_BANK5_PIN11 0x00000800
-#define BM_PINCTRL_PULL5_BANK5_PIN10 0x00000400
-#define BM_PINCTRL_PULL5_BANK5_PIN09 0x00000200
-#define BM_PINCTRL_PULL5_BANK5_PIN08 0x00000100
-#define BM_PINCTRL_PULL5_BANK5_PIN07 0x00000080
-#define BM_PINCTRL_PULL5_BANK5_PIN06 0x00000040
-#define BM_PINCTRL_PULL5_BANK5_PIN05 0x00000020
-#define BM_PINCTRL_PULL5_BANK5_PIN04 0x00000010
-#define BM_PINCTRL_PULL5_BANK5_PIN03 0x00000008
-#define BM_PINCTRL_PULL5_BANK5_PIN02 0x00000004
-#define BM_PINCTRL_PULL5_BANK5_PIN01 0x00000002
-#define BM_PINCTRL_PULL5_BANK5_PIN00 0x00000001
-
-#define HW_PINCTRL_PULL6 0x00000660
-#define HW_PINCTRL_PULL6_SET 0x00000664
-#define HW_PINCTRL_PULL6_CLR 0x00000668
-#define HW_PINCTRL_PULL6_TOG 0x0000066c
-
-#define BP_PINCTRL_PULL6_RSRVD1 25
-#define BM_PINCTRL_PULL6_RSRVD1 0xFE000000
-#define BF_PINCTRL_PULL6_RSRVD1(v) \
- (((v) << 25) & BM_PINCTRL_PULL6_RSRVD1)
-#define BM_PINCTRL_PULL6_BANK6_PIN24 0x01000000
-#define BM_PINCTRL_PULL6_BANK6_PIN23 0x00800000
-#define BM_PINCTRL_PULL6_BANK6_PIN22 0x00400000
-#define BM_PINCTRL_PULL6_BANK6_PIN21 0x00200000
-#define BM_PINCTRL_PULL6_BANK6_PIN20 0x00100000
-#define BM_PINCTRL_PULL6_BANK6_PIN19 0x00080000
-#define BM_PINCTRL_PULL6_BANK6_PIN18 0x00040000
-#define BM_PINCTRL_PULL6_BANK6_PIN17 0x00020000
-#define BM_PINCTRL_PULL6_BANK6_PIN16 0x00010000
-#define BM_PINCTRL_PULL6_RSRVD0 0x00008000
-#define BM_PINCTRL_PULL6_BANK6_PIN14 0x00004000
-#define BM_PINCTRL_PULL6_BANK6_PIN13 0x00002000
-#define BM_PINCTRL_PULL6_BANK6_PIN12 0x00001000
-#define BM_PINCTRL_PULL6_BANK6_PIN11 0x00000800
-#define BM_PINCTRL_PULL6_BANK6_PIN10 0x00000400
-#define BM_PINCTRL_PULL6_BANK6_PIN09 0x00000200
-#define BM_PINCTRL_PULL6_BANK6_PIN08 0x00000100
-#define BM_PINCTRL_PULL6_BANK6_PIN07 0x00000080
-#define BM_PINCTRL_PULL6_BANK6_PIN06 0x00000040
-#define BM_PINCTRL_PULL6_BANK6_PIN05 0x00000020
-#define BM_PINCTRL_PULL6_BANK6_PIN04 0x00000010
-#define BM_PINCTRL_PULL6_BANK6_PIN03 0x00000008
-#define BM_PINCTRL_PULL6_BANK6_PIN02 0x00000004
-#define BM_PINCTRL_PULL6_BANK6_PIN01 0x00000002
-#define BM_PINCTRL_PULL6_BANK6_PIN00 0x00000001
-
-#define HW_PINCTRL_DOUT0 0x00000700
-#define HW_PINCTRL_DOUT0_SET 0x00000704
-#define HW_PINCTRL_DOUT0_CLR 0x00000708
-#define HW_PINCTRL_DOUT0_TOG 0x0000070c
-
-#define BP_PINCTRL_DOUT0_RSRVD1 29
-#define BM_PINCTRL_DOUT0_RSRVD1 0xE0000000
-#define BF_PINCTRL_DOUT0_RSRVD1(v) \
- (((v) << 29) & BM_PINCTRL_DOUT0_RSRVD1)
-#define BP_PINCTRL_DOUT0_DOUT 0
-#define BM_PINCTRL_DOUT0_DOUT 0x1FFFFFFF
-#define BF_PINCTRL_DOUT0_DOUT(v) \
- (((v) << 0) & BM_PINCTRL_DOUT0_DOUT)
-
-#define HW_PINCTRL_DOUT1 0x00000710
-#define HW_PINCTRL_DOUT1_SET 0x00000714
-#define HW_PINCTRL_DOUT1_CLR 0x00000718
-#define HW_PINCTRL_DOUT1_TOG 0x0000071c
-
-#define BP_PINCTRL_DOUT1_DOUT 0
-#define BM_PINCTRL_DOUT1_DOUT 0xFFFFFFFF
-#define BF_PINCTRL_DOUT1_DOUT(v) (v)
-
-#define HW_PINCTRL_DOUT2 0x00000720
-#define HW_PINCTRL_DOUT2_SET 0x00000724
-#define HW_PINCTRL_DOUT2_CLR 0x00000728
-#define HW_PINCTRL_DOUT2_TOG 0x0000072c
-
-#define BP_PINCTRL_DOUT2_RSRVD1 28
-#define BM_PINCTRL_DOUT2_RSRVD1 0xF0000000
-#define BF_PINCTRL_DOUT2_RSRVD1(v) \
- (((v) << 28) & BM_PINCTRL_DOUT2_RSRVD1)
-#define BP_PINCTRL_DOUT2_DOUT 0
-#define BM_PINCTRL_DOUT2_DOUT 0x0FFFFFFF
-#define BF_PINCTRL_DOUT2_DOUT(v) \
- (((v) << 0) & BM_PINCTRL_DOUT2_DOUT)
-
-#define HW_PINCTRL_DOUT3 0x00000730
-#define HW_PINCTRL_DOUT3_SET 0x00000734
-#define HW_PINCTRL_DOUT3_CLR 0x00000738
-#define HW_PINCTRL_DOUT3_TOG 0x0000073c
-
-#define BM_PINCTRL_DOUT3_RSRVD1 0x80000000
-#define BP_PINCTRL_DOUT3_DOUT 0
-#define BM_PINCTRL_DOUT3_DOUT 0x7FFFFFFF
-#define BF_PINCTRL_DOUT3_DOUT(v) \
- (((v) << 0) & BM_PINCTRL_DOUT3_DOUT)
-
-#define HW_PINCTRL_DOUT4 0x00000740
-#define HW_PINCTRL_DOUT4_SET 0x00000744
-#define HW_PINCTRL_DOUT4_CLR 0x00000748
-#define HW_PINCTRL_DOUT4_TOG 0x0000074c
-
-#define BP_PINCTRL_DOUT4_RSRVD1 21
-#define BM_PINCTRL_DOUT4_RSRVD1 0xFFE00000
-#define BF_PINCTRL_DOUT4_RSRVD1(v) \
- (((v) << 21) & BM_PINCTRL_DOUT4_RSRVD1)
-#define BP_PINCTRL_DOUT4_DOUT 0
-#define BM_PINCTRL_DOUT4_DOUT 0x001FFFFF
-#define BF_PINCTRL_DOUT4_DOUT(v) \
- (((v) << 0) & BM_PINCTRL_DOUT4_DOUT)
-
-#define HW_PINCTRL_DIN0 0x00000900
-#define HW_PINCTRL_DIN0_SET 0x00000904
-#define HW_PINCTRL_DIN0_CLR 0x00000908
-#define HW_PINCTRL_DIN0_TOG 0x0000090c
-
-#define BP_PINCTRL_DIN0_RSRVD1 29
-#define BM_PINCTRL_DIN0_RSRVD1 0xE0000000
-#define BF_PINCTRL_DIN0_RSRVD1(v) \
- (((v) << 29) & BM_PINCTRL_DIN0_RSRVD1)
-#define BP_PINCTRL_DIN0_DIN 0
-#define BM_PINCTRL_DIN0_DIN 0x1FFFFFFF
-#define BF_PINCTRL_DIN0_DIN(v) \
- (((v) << 0) & BM_PINCTRL_DIN0_DIN)
-
-#define HW_PINCTRL_DIN1 0x00000910
-#define HW_PINCTRL_DIN1_SET 0x00000914
-#define HW_PINCTRL_DIN1_CLR 0x00000918
-#define HW_PINCTRL_DIN1_TOG 0x0000091c
-
-#define BP_PINCTRL_DIN1_DIN 0
-#define BM_PINCTRL_DIN1_DIN 0xFFFFFFFF
-#define BF_PINCTRL_DIN1_DIN(v) (v)
-
-#define HW_PINCTRL_DIN2 0x00000920
-#define HW_PINCTRL_DIN2_SET 0x00000924
-#define HW_PINCTRL_DIN2_CLR 0x00000928
-#define HW_PINCTRL_DIN2_TOG 0x0000092c
-
-#define BP_PINCTRL_DIN2_RSRVD1 28
-#define BM_PINCTRL_DIN2_RSRVD1 0xF0000000
-#define BF_PINCTRL_DIN2_RSRVD1(v) \
- (((v) << 28) & BM_PINCTRL_DIN2_RSRVD1)
-#define BP_PINCTRL_DIN2_DIN 0
-#define BM_PINCTRL_DIN2_DIN 0x0FFFFFFF
-#define BF_PINCTRL_DIN2_DIN(v) \
- (((v) << 0) & BM_PINCTRL_DIN2_DIN)
-
-#define HW_PINCTRL_DIN3 0x00000930
-#define HW_PINCTRL_DIN3_SET 0x00000934
-#define HW_PINCTRL_DIN3_CLR 0x00000938
-#define HW_PINCTRL_DIN3_TOG 0x0000093c
-
-#define BM_PINCTRL_DIN3_RSRVD1 0x80000000
-#define BP_PINCTRL_DIN3_DIN 0
-#define BM_PINCTRL_DIN3_DIN 0x7FFFFFFF
-#define BF_PINCTRL_DIN3_DIN(v) \
- (((v) << 0) & BM_PINCTRL_DIN3_DIN)
-
-#define HW_PINCTRL_DIN4 0x00000940
-#define HW_PINCTRL_DIN4_SET 0x00000944
-#define HW_PINCTRL_DIN4_CLR 0x00000948
-#define HW_PINCTRL_DIN4_TOG 0x0000094c
-
-#define BP_PINCTRL_DIN4_RSRVD1 21
-#define BM_PINCTRL_DIN4_RSRVD1 0xFFE00000
-#define BF_PINCTRL_DIN4_RSRVD1(v) \
- (((v) << 21) & BM_PINCTRL_DIN4_RSRVD1)
-#define BP_PINCTRL_DIN4_DIN 0
-#define BM_PINCTRL_DIN4_DIN 0x001FFFFF
-#define BF_PINCTRL_DIN4_DIN(v) \
- (((v) << 0) & BM_PINCTRL_DIN4_DIN)
-
-#define HW_PINCTRL_DOE0 0x00000b00
-#define HW_PINCTRL_DOE0_SET 0x00000b04
-#define HW_PINCTRL_DOE0_CLR 0x00000b08
-#define HW_PINCTRL_DOE0_TOG 0x00000b0c
-
-#define BP_PINCTRL_DOE0_RSRVD1 29
-#define BM_PINCTRL_DOE0_RSRVD1 0xE0000000
-#define BF_PINCTRL_DOE0_RSRVD1(v) \
- (((v) << 29) & BM_PINCTRL_DOE0_RSRVD1)
-#define BP_PINCTRL_DOE0_DOE 0
-#define BM_PINCTRL_DOE0_DOE 0x1FFFFFFF
-#define BF_PINCTRL_DOE0_DOE(v) \
- (((v) << 0) & BM_PINCTRL_DOE0_DOE)
-
-#define HW_PINCTRL_DOE1 0x00000b10
-#define HW_PINCTRL_DOE1_SET 0x00000b14
-#define HW_PINCTRL_DOE1_CLR 0x00000b18
-#define HW_PINCTRL_DOE1_TOG 0x00000b1c
-
-#define BP_PINCTRL_DOE1_DOE 0
-#define BM_PINCTRL_DOE1_DOE 0xFFFFFFFF
-#define BF_PINCTRL_DOE1_DOE(v) (v)
-
-#define HW_PINCTRL_DOE2 0x00000b20
-#define HW_PINCTRL_DOE2_SET 0x00000b24
-#define HW_PINCTRL_DOE2_CLR 0x00000b28
-#define HW_PINCTRL_DOE2_TOG 0x00000b2c
-
-#define BP_PINCTRL_DOE2_RSRVD1 28
-#define BM_PINCTRL_DOE2_RSRVD1 0xF0000000
-#define BF_PINCTRL_DOE2_RSRVD1(v) \
- (((v) << 28) & BM_PINCTRL_DOE2_RSRVD1)
-#define BP_PINCTRL_DOE2_DOE 0
-#define BM_PINCTRL_DOE2_DOE 0x0FFFFFFF
-#define BF_PINCTRL_DOE2_DOE(v) \
- (((v) << 0) & BM_PINCTRL_DOE2_DOE)
-
-#define HW_PINCTRL_DOE3 0x00000b30
-#define HW_PINCTRL_DOE3_SET 0x00000b34
-#define HW_PINCTRL_DOE3_CLR 0x00000b38
-#define HW_PINCTRL_DOE3_TOG 0x00000b3c
-
-#define BM_PINCTRL_DOE3_RSRVD1 0x80000000
-#define BP_PINCTRL_DOE3_DOE 0
-#define BM_PINCTRL_DOE3_DOE 0x7FFFFFFF
-#define BF_PINCTRL_DOE3_DOE(v) \
- (((v) << 0) & BM_PINCTRL_DOE3_DOE)
-
-#define HW_PINCTRL_DOE4 0x00000b40
-#define HW_PINCTRL_DOE4_SET 0x00000b44
-#define HW_PINCTRL_DOE4_CLR 0x00000b48
-#define HW_PINCTRL_DOE4_TOG 0x00000b4c
-
-#define BP_PINCTRL_DOE4_RSRVD1 21
-#define BM_PINCTRL_DOE4_RSRVD1 0xFFE00000
-#define BF_PINCTRL_DOE4_RSRVD1(v) \
- (((v) << 21) & BM_PINCTRL_DOE4_RSRVD1)
-#define BP_PINCTRL_DOE4_DOE 0
-#define BM_PINCTRL_DOE4_DOE 0x001FFFFF
-#define BF_PINCTRL_DOE4_DOE(v) \
- (((v) << 0) & BM_PINCTRL_DOE4_DOE)
-
-#define HW_PINCTRL_PIN2IRQ0 0x00001000
-#define HW_PINCTRL_PIN2IRQ0_SET 0x00001004
-#define HW_PINCTRL_PIN2IRQ0_CLR 0x00001008
-#define HW_PINCTRL_PIN2IRQ0_TOG 0x0000100c
-
-#define BP_PINCTRL_PIN2IRQ0_RSRVD1 29
-#define BM_PINCTRL_PIN2IRQ0_RSRVD1 0xE0000000
-#define BF_PINCTRL_PIN2IRQ0_RSRVD1(v) \
- (((v) << 29) & BM_PINCTRL_PIN2IRQ0_RSRVD1)
-#define BP_PINCTRL_PIN2IRQ0_PIN2IRQ 0
-#define BM_PINCTRL_PIN2IRQ0_PIN2IRQ 0x1FFFFFFF
-#define BF_PINCTRL_PIN2IRQ0_PIN2IRQ(v) \
- (((v) << 0) & BM_PINCTRL_PIN2IRQ0_PIN2IRQ)
-
-#define HW_PINCTRL_PIN2IRQ1 0x00001010
-#define HW_PINCTRL_PIN2IRQ1_SET 0x00001014
-#define HW_PINCTRL_PIN2IRQ1_CLR 0x00001018
-#define HW_PINCTRL_PIN2IRQ1_TOG 0x0000101c
-
-#define BP_PINCTRL_PIN2IRQ1_PIN2IRQ 0
-#define BM_PINCTRL_PIN2IRQ1_PIN2IRQ 0xFFFFFFFF
-#define BF_PINCTRL_PIN2IRQ1_PIN2IRQ(v) (v)
-
-#define HW_PINCTRL_PIN2IRQ2 0x00001020
-#define HW_PINCTRL_PIN2IRQ2_SET 0x00001024
-#define HW_PINCTRL_PIN2IRQ2_CLR 0x00001028
-#define HW_PINCTRL_PIN2IRQ2_TOG 0x0000102c
-
-#define BP_PINCTRL_PIN2IRQ2_RSRVD1 28
-#define BM_PINCTRL_PIN2IRQ2_RSRVD1 0xF0000000
-#define BF_PINCTRL_PIN2IRQ2_RSRVD1(v) \
- (((v) << 28) & BM_PINCTRL_PIN2IRQ2_RSRVD1)
-#define BP_PINCTRL_PIN2IRQ2_PIN2IRQ 0
-#define BM_PINCTRL_PIN2IRQ2_PIN2IRQ 0x0FFFFFFF
-#define BF_PINCTRL_PIN2IRQ2_PIN2IRQ(v) \
- (((v) << 0) & BM_PINCTRL_PIN2IRQ2_PIN2IRQ)
-
-#define HW_PINCTRL_PIN2IRQ3 0x00001030
-#define HW_PINCTRL_PIN2IRQ3_SET 0x00001034
-#define HW_PINCTRL_PIN2IRQ3_CLR 0x00001038
-#define HW_PINCTRL_PIN2IRQ3_TOG 0x0000103c
-
-#define BM_PINCTRL_PIN2IRQ3_RSRVD1 0x80000000
-#define BP_PINCTRL_PIN2IRQ3_PIN2IRQ 0
-#define BM_PINCTRL_PIN2IRQ3_PIN2IRQ 0x7FFFFFFF
-#define BF_PINCTRL_PIN2IRQ3_PIN2IRQ(v) \
- (((v) << 0) & BM_PINCTRL_PIN2IRQ3_PIN2IRQ)
-
-#define HW_PINCTRL_PIN2IRQ4 0x00001040
-#define HW_PINCTRL_PIN2IRQ4_SET 0x00001044
-#define HW_PINCTRL_PIN2IRQ4_CLR 0x00001048
-#define HW_PINCTRL_PIN2IRQ4_TOG 0x0000104c
-
-#define BP_PINCTRL_PIN2IRQ4_RSRVD1 21
-#define BM_PINCTRL_PIN2IRQ4_RSRVD1 0xFFE00000
-#define BF_PINCTRL_PIN2IRQ4_RSRVD1(v) \
- (((v) << 21) & BM_PINCTRL_PIN2IRQ4_RSRVD1)
-#define BP_PINCTRL_PIN2IRQ4_PIN2IRQ 0
-#define BM_PINCTRL_PIN2IRQ4_PIN2IRQ 0x001FFFFF
-#define BF_PINCTRL_PIN2IRQ4_PIN2IRQ(v) \
- (((v) << 0) & BM_PINCTRL_PIN2IRQ4_PIN2IRQ)
-
-#define HW_PINCTRL_IRQEN0 0x00001100
-#define HW_PINCTRL_IRQEN0_SET 0x00001104
-#define HW_PINCTRL_IRQEN0_CLR 0x00001108
-#define HW_PINCTRL_IRQEN0_TOG 0x0000110c
-
-#define BP_PINCTRL_IRQEN0_RSRVD1 29
-#define BM_PINCTRL_IRQEN0_RSRVD1 0xE0000000
-#define BF_PINCTRL_IRQEN0_RSRVD1(v) \
- (((v) << 29) & BM_PINCTRL_IRQEN0_RSRVD1)
-#define BP_PINCTRL_IRQEN0_IRQEN 0
-#define BM_PINCTRL_IRQEN0_IRQEN 0x1FFFFFFF
-#define BF_PINCTRL_IRQEN0_IRQEN(v) \
- (((v) << 0) & BM_PINCTRL_IRQEN0_IRQEN)
-
-#define HW_PINCTRL_IRQEN1 0x00001110
-#define HW_PINCTRL_IRQEN1_SET 0x00001114
-#define HW_PINCTRL_IRQEN1_CLR 0x00001118
-#define HW_PINCTRL_IRQEN1_TOG 0x0000111c
-
-#define BP_PINCTRL_IRQEN1_IRQEN 0
-#define BM_PINCTRL_IRQEN1_IRQEN 0xFFFFFFFF
-#define BF_PINCTRL_IRQEN1_IRQEN(v) (v)
-
-#define HW_PINCTRL_IRQEN2 0x00001120
-#define HW_PINCTRL_IRQEN2_SET 0x00001124
-#define HW_PINCTRL_IRQEN2_CLR 0x00001128
-#define HW_PINCTRL_IRQEN2_TOG 0x0000112c
-
-#define BP_PINCTRL_IRQEN2_RSRVD1 28
-#define BM_PINCTRL_IRQEN2_RSRVD1 0xF0000000
-#define BF_PINCTRL_IRQEN2_RSRVD1(v) \
- (((v) << 28) & BM_PINCTRL_IRQEN2_RSRVD1)
-#define BP_PINCTRL_IRQEN2_IRQEN 0
-#define BM_PINCTRL_IRQEN2_IRQEN 0x0FFFFFFF
-#define BF_PINCTRL_IRQEN2_IRQEN(v) \
- (((v) << 0) & BM_PINCTRL_IRQEN2_IRQEN)
-
-#define HW_PINCTRL_IRQEN3 0x00001130
-#define HW_PINCTRL_IRQEN3_SET 0x00001134
-#define HW_PINCTRL_IRQEN3_CLR 0x00001138
-#define HW_PINCTRL_IRQEN3_TOG 0x0000113c
-
-#define BM_PINCTRL_IRQEN3_RSRVD1 0x80000000
-#define BP_PINCTRL_IRQEN3_IRQEN 0
-#define BM_PINCTRL_IRQEN3_IRQEN 0x7FFFFFFF
-#define BF_PINCTRL_IRQEN3_IRQEN(v) \
- (((v) << 0) & BM_PINCTRL_IRQEN3_IRQEN)
-
-#define HW_PINCTRL_IRQEN4 0x00001140
-#define HW_PINCTRL_IRQEN4_SET 0x00001144
-#define HW_PINCTRL_IRQEN4_CLR 0x00001148
-#define HW_PINCTRL_IRQEN4_TOG 0x0000114c
-
-#define BP_PINCTRL_IRQEN4_RSRVD1 21
-#define BM_PINCTRL_IRQEN4_RSRVD1 0xFFE00000
-#define BF_PINCTRL_IRQEN4_RSRVD1(v) \
- (((v) << 21) & BM_PINCTRL_IRQEN4_RSRVD1)
-#define BP_PINCTRL_IRQEN4_IRQEN 0
-#define BM_PINCTRL_IRQEN4_IRQEN 0x001FFFFF
-#define BF_PINCTRL_IRQEN4_IRQEN(v) \
- (((v) << 0) & BM_PINCTRL_IRQEN4_IRQEN)
-
-#define HW_PINCTRL_IRQLEVEL0 0x00001200
-#define HW_PINCTRL_IRQLEVEL0_SET 0x00001204
-#define HW_PINCTRL_IRQLEVEL0_CLR 0x00001208
-#define HW_PINCTRL_IRQLEVEL0_TOG 0x0000120c
-
-#define BP_PINCTRL_IRQLEVEL0_RSRVD1 29
-#define BM_PINCTRL_IRQLEVEL0_RSRVD1 0xE0000000
-#define BF_PINCTRL_IRQLEVEL0_RSRVD1(v) \
- (((v) << 29) & BM_PINCTRL_IRQLEVEL0_RSRVD1)
-#define BP_PINCTRL_IRQLEVEL0_IRQLEVEL 0
-#define BM_PINCTRL_IRQLEVEL0_IRQLEVEL 0x1FFFFFFF
-#define BF_PINCTRL_IRQLEVEL0_IRQLEVEL(v) \
- (((v) << 0) & BM_PINCTRL_IRQLEVEL0_IRQLEVEL)
-
-#define HW_PINCTRL_IRQLEVEL1 0x00001210
-#define HW_PINCTRL_IRQLEVEL1_SET 0x00001214
-#define HW_PINCTRL_IRQLEVEL1_CLR 0x00001218
-#define HW_PINCTRL_IRQLEVEL1_TOG 0x0000121c
-
-#define BP_PINCTRL_IRQLEVEL1_IRQLEVEL 0
-#define BM_PINCTRL_IRQLEVEL1_IRQLEVEL 0xFFFFFFFF
-#define BF_PINCTRL_IRQLEVEL1_IRQLEVEL(v) (v)
-
-#define HW_PINCTRL_IRQLEVEL2 0x00001220
-#define HW_PINCTRL_IRQLEVEL2_SET 0x00001224
-#define HW_PINCTRL_IRQLEVEL2_CLR 0x00001228
-#define HW_PINCTRL_IRQLEVEL2_TOG 0x0000122c
-
-#define BP_PINCTRL_IRQLEVEL2_RSRVD1 28
-#define BM_PINCTRL_IRQLEVEL2_RSRVD1 0xF0000000
-#define BF_PINCTRL_IRQLEVEL2_RSRVD1(v) \
- (((v) << 28) & BM_PINCTRL_IRQLEVEL2_RSRVD1)
-#define BP_PINCTRL_IRQLEVEL2_IRQLEVEL 0
-#define BM_PINCTRL_IRQLEVEL2_IRQLEVEL 0x0FFFFFFF
-#define BF_PINCTRL_IRQLEVEL2_IRQLEVEL(v) \
- (((v) << 0) & BM_PINCTRL_IRQLEVEL2_IRQLEVEL)
-
-#define HW_PINCTRL_IRQLEVEL3 0x00001230
-#define HW_PINCTRL_IRQLEVEL3_SET 0x00001234
-#define HW_PINCTRL_IRQLEVEL3_CLR 0x00001238
-#define HW_PINCTRL_IRQLEVEL3_TOG 0x0000123c
-
-#define BM_PINCTRL_IRQLEVEL3_RSRVD1 0x80000000
-#define BP_PINCTRL_IRQLEVEL3_IRQLEVEL 0
-#define BM_PINCTRL_IRQLEVEL3_IRQLEVEL 0x7FFFFFFF
-#define BF_PINCTRL_IRQLEVEL3_IRQLEVEL(v) \
- (((v) << 0) & BM_PINCTRL_IRQLEVEL3_IRQLEVEL)
-
-#define HW_PINCTRL_IRQLEVEL4 0x00001240
-#define HW_PINCTRL_IRQLEVEL4_SET 0x00001244
-#define HW_PINCTRL_IRQLEVEL4_CLR 0x00001248
-#define HW_PINCTRL_IRQLEVEL4_TOG 0x0000124c
-
-#define BP_PINCTRL_IRQLEVEL4_RSRVD1 21
-#define BM_PINCTRL_IRQLEVEL4_RSRVD1 0xFFE00000
-#define BF_PINCTRL_IRQLEVEL4_RSRVD1(v) \
- (((v) << 21) & BM_PINCTRL_IRQLEVEL4_RSRVD1)
-#define BP_PINCTRL_IRQLEVEL4_IRQLEVEL 0
-#define BM_PINCTRL_IRQLEVEL4_IRQLEVEL 0x001FFFFF
-#define BF_PINCTRL_IRQLEVEL4_IRQLEVEL(v) \
- (((v) << 0) & BM_PINCTRL_IRQLEVEL4_IRQLEVEL)
-
-#define HW_PINCTRL_IRQPOL0 0x00001300
-#define HW_PINCTRL_IRQPOL0_SET 0x00001304
-#define HW_PINCTRL_IRQPOL0_CLR 0x00001308
-#define HW_PINCTRL_IRQPOL0_TOG 0x0000130c
-
-#define BP_PINCTRL_IRQPOL0_RSRVD1 29
-#define BM_PINCTRL_IRQPOL0_RSRVD1 0xE0000000
-#define BF_PINCTRL_IRQPOL0_RSRVD1(v) \
- (((v) << 29) & BM_PINCTRL_IRQPOL0_RSRVD1)
-#define BP_PINCTRL_IRQPOL0_IRQPOL 0
-#define BM_PINCTRL_IRQPOL0_IRQPOL 0x1FFFFFFF
-#define BF_PINCTRL_IRQPOL0_IRQPOL(v) \
- (((v) << 0) & BM_PINCTRL_IRQPOL0_IRQPOL)
-
-#define HW_PINCTRL_IRQPOL1 0x00001310
-#define HW_PINCTRL_IRQPOL1_SET 0x00001314
-#define HW_PINCTRL_IRQPOL1_CLR 0x00001318
-#define HW_PINCTRL_IRQPOL1_TOG 0x0000131c
-
-#define BP_PINCTRL_IRQPOL1_IRQPOL 0
-#define BM_PINCTRL_IRQPOL1_IRQPOL 0xFFFFFFFF
-#define BF_PINCTRL_IRQPOL1_IRQPOL(v) (v)
-
-#define HW_PINCTRL_IRQPOL2 0x00001320
-#define HW_PINCTRL_IRQPOL2_SET 0x00001324
-#define HW_PINCTRL_IRQPOL2_CLR 0x00001328
-#define HW_PINCTRL_IRQPOL2_TOG 0x0000132c
-
-#define BP_PINCTRL_IRQPOL2_RSRVD1 28
-#define BM_PINCTRL_IRQPOL2_RSRVD1 0xF0000000
-#define BF_PINCTRL_IRQPOL2_RSRVD1(v) \
- (((v) << 28) & BM_PINCTRL_IRQPOL2_RSRVD1)
-#define BP_PINCTRL_IRQPOL2_IRQPOL 0
-#define BM_PINCTRL_IRQPOL2_IRQPOL 0x0FFFFFFF
-#define BF_PINCTRL_IRQPOL2_IRQPOL(v) \
- (((v) << 0) & BM_PINCTRL_IRQPOL2_IRQPOL)
-
-#define HW_PINCTRL_IRQPOL3 0x00001330
-#define HW_PINCTRL_IRQPOL3_SET 0x00001334
-#define HW_PINCTRL_IRQPOL3_CLR 0x00001338
-#define HW_PINCTRL_IRQPOL3_TOG 0x0000133c
-
-#define BM_PINCTRL_IRQPOL3_RSRVD1 0x80000000
-#define BP_PINCTRL_IRQPOL3_IRQPOL 0
-#define BM_PINCTRL_IRQPOL3_IRQPOL 0x7FFFFFFF
-#define BF_PINCTRL_IRQPOL3_IRQPOL(v) \
- (((v) << 0) & BM_PINCTRL_IRQPOL3_IRQPOL)
-
-#define HW_PINCTRL_IRQPOL4 0x00001340
-#define HW_PINCTRL_IRQPOL4_SET 0x00001344
-#define HW_PINCTRL_IRQPOL4_CLR 0x00001348
-#define HW_PINCTRL_IRQPOL4_TOG 0x0000134c
-
-#define BP_PINCTRL_IRQPOL4_RSRVD1 21
-#define BM_PINCTRL_IRQPOL4_RSRVD1 0xFFE00000
-#define BF_PINCTRL_IRQPOL4_RSRVD1(v) \
- (((v) << 21) & BM_PINCTRL_IRQPOL4_RSRVD1)
-#define BP_PINCTRL_IRQPOL4_IRQPOL 0
-#define BM_PINCTRL_IRQPOL4_IRQPOL 0x001FFFFF
-#define BF_PINCTRL_IRQPOL4_IRQPOL(v) \
- (((v) << 0) & BM_PINCTRL_IRQPOL4_IRQPOL)
-
-#define HW_PINCTRL_IRQSTAT0 0x00001400
-#define HW_PINCTRL_IRQSTAT0_SET 0x00001404
-#define HW_PINCTRL_IRQSTAT0_CLR 0x00001408
-#define HW_PINCTRL_IRQSTAT0_TOG 0x0000140c
-
-#define BP_PINCTRL_IRQSTAT0_RSRVD1 29
-#define BM_PINCTRL_IRQSTAT0_RSRVD1 0xE0000000
-#define BF_PINCTRL_IRQSTAT0_RSRVD1(v) \
- (((v) << 29) & BM_PINCTRL_IRQSTAT0_RSRVD1)
-#define BP_PINCTRL_IRQSTAT0_IRQSTAT 0
-#define BM_PINCTRL_IRQSTAT0_IRQSTAT 0x1FFFFFFF
-#define BF_PINCTRL_IRQSTAT0_IRQSTAT(v) \
- (((v) << 0) & BM_PINCTRL_IRQSTAT0_IRQSTAT)
-
-#define HW_PINCTRL_IRQSTAT1 0x00001410
-#define HW_PINCTRL_IRQSTAT1_SET 0x00001414
-#define HW_PINCTRL_IRQSTAT1_CLR 0x00001418
-#define HW_PINCTRL_IRQSTAT1_TOG 0x0000141c
-
-#define BP_PINCTRL_IRQSTAT1_IRQSTAT 0
-#define BM_PINCTRL_IRQSTAT1_IRQSTAT 0xFFFFFFFF
-#define BF_PINCTRL_IRQSTAT1_IRQSTAT(v) (v)
-
-#define HW_PINCTRL_IRQSTAT2 0x00001420
-#define HW_PINCTRL_IRQSTAT2_SET 0x00001424
-#define HW_PINCTRL_IRQSTAT2_CLR 0x00001428
-#define HW_PINCTRL_IRQSTAT2_TOG 0x0000142c
-
-#define BP_PINCTRL_IRQSTAT2_RSRVD1 28
-#define BM_PINCTRL_IRQSTAT2_RSRVD1 0xF0000000
-#define BF_PINCTRL_IRQSTAT2_RSRVD1(v) \
- (((v) << 28) & BM_PINCTRL_IRQSTAT2_RSRVD1)
-#define BP_PINCTRL_IRQSTAT2_IRQSTAT 0
-#define BM_PINCTRL_IRQSTAT2_IRQSTAT 0x0FFFFFFF
-#define BF_PINCTRL_IRQSTAT2_IRQSTAT(v) \
- (((v) << 0) & BM_PINCTRL_IRQSTAT2_IRQSTAT)
-
-#define HW_PINCTRL_IRQSTAT3 0x00001430
-#define HW_PINCTRL_IRQSTAT3_SET 0x00001434
-#define HW_PINCTRL_IRQSTAT3_CLR 0x00001438
-#define HW_PINCTRL_IRQSTAT3_TOG 0x0000143c
-
-#define BM_PINCTRL_IRQSTAT3_RSRVD1 0x80000000
-#define BP_PINCTRL_IRQSTAT3_IRQSTAT 0
-#define BM_PINCTRL_IRQSTAT3_IRQSTAT 0x7FFFFFFF
-#define BF_PINCTRL_IRQSTAT3_IRQSTAT(v) \
- (((v) << 0) & BM_PINCTRL_IRQSTAT3_IRQSTAT)
-
-#define HW_PINCTRL_IRQSTAT4 0x00001440
-#define HW_PINCTRL_IRQSTAT4_SET 0x00001444
-#define HW_PINCTRL_IRQSTAT4_CLR 0x00001448
-#define HW_PINCTRL_IRQSTAT4_TOG 0x0000144c
-
-#define BP_PINCTRL_IRQSTAT4_RSRVD1 21
-#define BM_PINCTRL_IRQSTAT4_RSRVD1 0xFFE00000
-#define BF_PINCTRL_IRQSTAT4_RSRVD1(v) \
- (((v) << 21) & BM_PINCTRL_IRQSTAT4_RSRVD1)
-#define BP_PINCTRL_IRQSTAT4_IRQSTAT 0
-#define BM_PINCTRL_IRQSTAT4_IRQSTAT 0x001FFFFF
-#define BF_PINCTRL_IRQSTAT4_IRQSTAT(v) \
- (((v) << 0) & BM_PINCTRL_IRQSTAT4_IRQSTAT)
-
-#define HW_PINCTRL_EMI_ODT_CTRL 0x00001a40
-#define HW_PINCTRL_EMI_ODT_CTRL_SET 0x00001a44
-#define HW_PINCTRL_EMI_ODT_CTRL_CLR 0x00001a48
-#define HW_PINCTRL_EMI_ODT_CTRL_TOG 0x00001a4c
-
-#define BP_PINCTRL_EMI_ODT_CTRL_RSRVD1 28
-#define BM_PINCTRL_EMI_ODT_CTRL_RSRVD1 0xF0000000
-#define BF_PINCTRL_EMI_ODT_CTRL_RSRVD1(v) \
- (((v) << 28) & BM_PINCTRL_EMI_ODT_CTRL_RSRVD1)
-#define BP_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB 26
-#define BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB 0x0C000000
-#define BF_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB(v) \
- (((v) << 26) & BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB)
-#define BP_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD 24
-#define BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD 0x03000000
-#define BF_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD(v) \
- (((v) << 24) & BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD)
-#define BP_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB 22
-#define BM_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB 0x00C00000
-#define BF_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB(v) \
- (((v) << 22) & BM_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB)
-#define BP_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD 20
-#define BM_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD 0x00300000
-#define BF_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD(v) \
- (((v) << 20) & BM_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD)
-#define BP_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB 18
-#define BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB 0x000C0000
-#define BF_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB(v) \
- (((v) << 18) & BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB)
-#define BP_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD 16
-#define BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD 0x00030000
-#define BF_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD(v) \
- (((v) << 16) & BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD)
-#define BP_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB 14
-#define BM_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB 0x0000C000
-#define BF_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB(v) \
- (((v) << 14) & BM_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB)
-#define BP_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD 12
-#define BM_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD 0x00003000
-#define BF_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD(v) \
- (((v) << 12) & BM_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD)
-#define BP_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB 10
-#define BM_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB 0x00000C00
-#define BF_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB(v) \
- (((v) << 10) & BM_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB)
-#define BP_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD 8
-#define BM_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD 0x00000300
-#define BF_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD(v) \
- (((v) << 8) & BM_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD)
-#define BP_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB 6
-#define BM_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB 0x000000C0
-#define BF_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB(v) \
- (((v) << 6) & BM_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB)
-#define BP_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD 4
-#define BM_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD 0x00000030
-#define BF_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD(v) \
- (((v) << 4) & BM_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD)
-#define BP_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB 2
-#define BM_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB 0x0000000C
-#define BF_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB(v) \
- (((v) << 2) & BM_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB)
-#define BP_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD 0
-#define BM_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD 0x00000003
-#define BF_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD(v) \
- (((v) << 0) & BM_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD)
-
-#define HW_PINCTRL_EMI_DS_CTRL 0x00001b80
-#define HW_PINCTRL_EMI_DS_CTRL_SET 0x00001b84
-#define HW_PINCTRL_EMI_DS_CTRL_CLR 0x00001b88
-#define HW_PINCTRL_EMI_DS_CTRL_TOG 0x00001b8c
-
-#define BP_PINCTRL_EMI_DS_CTRL_RSRVD1 18
-#define BM_PINCTRL_EMI_DS_CTRL_RSRVD1 0xFFFC0000
-#define BF_PINCTRL_EMI_DS_CTRL_RSRVD1(v) \
- (((v) << 18) & BM_PINCTRL_EMI_DS_CTRL_RSRVD1)
-#define BP_PINCTRL_EMI_DS_CTRL_DDR_MODE 16
-#define BM_PINCTRL_EMI_DS_CTRL_DDR_MODE 0x00030000
-#define BF_PINCTRL_EMI_DS_CTRL_DDR_MODE(v) \
- (((v) << 16) & BM_PINCTRL_EMI_DS_CTRL_DDR_MODE)
-#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__mDDR 00
-#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__GPIO 01
-#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__LVDDR2 10
-#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__DDR2 11
-#define BP_PINCTRL_EMI_DS_CTRL_RSRVD0 14
-#define BM_PINCTRL_EMI_DS_CTRL_RSRVD0 0x0000C000
-#define BF_PINCTRL_EMI_DS_CTRL_RSRVD0(v) \
- (((v) << 14) & BM_PINCTRL_EMI_DS_CTRL_RSRVD0)
-#define BP_PINCTRL_EMI_DS_CTRL_ADDRESS_MA 12
-#define BM_PINCTRL_EMI_DS_CTRL_ADDRESS_MA 0x00003000
-#define BF_PINCTRL_EMI_DS_CTRL_ADDRESS_MA(v) \
- (((v) << 12) & BM_PINCTRL_EMI_DS_CTRL_ADDRESS_MA)
-#define BP_PINCTRL_EMI_DS_CTRL_CONTROL_MA 10
-#define BM_PINCTRL_EMI_DS_CTRL_CONTROL_MA 0x00000C00
-#define BF_PINCTRL_EMI_DS_CTRL_CONTROL_MA(v) \
- (((v) << 10) & BM_PINCTRL_EMI_DS_CTRL_CONTROL_MA)
-#define BP_PINCTRL_EMI_DS_CTRL_DUALPAD_MA 8
-#define BM_PINCTRL_EMI_DS_CTRL_DUALPAD_MA 0x00000300
-#define BF_PINCTRL_EMI_DS_CTRL_DUALPAD_MA(v) \
- (((v) << 8) & BM_PINCTRL_EMI_DS_CTRL_DUALPAD_MA)
-#define BP_PINCTRL_EMI_DS_CTRL_SLICE3_MA 6
-#define BM_PINCTRL_EMI_DS_CTRL_SLICE3_MA 0x000000C0
-#define BF_PINCTRL_EMI_DS_CTRL_SLICE3_MA(v) \
- (((v) << 6) & BM_PINCTRL_EMI_DS_CTRL_SLICE3_MA)
-#define BP_PINCTRL_EMI_DS_CTRL_SLICE2_MA 4
-#define BM_PINCTRL_EMI_DS_CTRL_SLICE2_MA 0x00000030
-#define BF_PINCTRL_EMI_DS_CTRL_SLICE2_MA(v) \
- (((v) << 4) & BM_PINCTRL_EMI_DS_CTRL_SLICE2_MA)
-#define BP_PINCTRL_EMI_DS_CTRL_SLICE1_MA 2
-#define BM_PINCTRL_EMI_DS_CTRL_SLICE1_MA 0x0000000C
-#define BF_PINCTRL_EMI_DS_CTRL_SLICE1_MA(v) \
- (((v) << 2) & BM_PINCTRL_EMI_DS_CTRL_SLICE1_MA)
-#define BP_PINCTRL_EMI_DS_CTRL_SLICE0_MA 0
-#define BM_PINCTRL_EMI_DS_CTRL_SLICE0_MA 0x00000003
-#define BF_PINCTRL_EMI_DS_CTRL_SLICE0_MA(v) \
- (((v) << 0) & BM_PINCTRL_EMI_DS_CTRL_SLICE0_MA)
-#endif /* __ARCH_ARM___PINCTRL_H */
+++ /dev/null
-/*
- * Freescale SSP Register Definitions
- *
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * This file is created by xml file. Don't Edit it.
- *
- * Xml Revision: 4.0
- * Template revision: 26195
- */
-
-#ifndef __ARCH_ARM___SSP_H
-#define __ARCH_ARM___SSP_H
-
-
-#define HW_SSP_CTRL0 (0x00000000)
-#define HW_SSP_CTRL0_SET (0x00000004)
-#define HW_SSP_CTRL0_CLR (0x00000008)
-#define HW_SSP_CTRL0_TOG (0x0000000c)
-
-#define BM_SSP_CTRL0_SFTRST 0x80000000
-#define BM_SSP_CTRL0_CLKGATE 0x40000000
-#define BM_SSP_CTRL0_RUN 0x20000000
-#define BM_SSP_CTRL0_SDIO_IRQ_CHECK 0x10000000
-#define BM_SSP_CTRL0_LOCK_CS 0x08000000
-#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
-#define BM_SSP_CTRL0_READ 0x02000000
-#define BM_SSP_CTRL0_DATA_XFER 0x01000000
-#define BP_SSP_CTRL0_BUS_WIDTH 22
-#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
-#define BF_SSP_CTRL0_BUS_WIDTH(v) \
- (((v) << 22) & BM_SSP_CTRL0_BUS_WIDTH)
-#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT 0x0
-#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT 0x1
-#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT 0x2
-#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
-#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
-#define BM_SSP_CTRL0_LONG_RESP 0x00080000
-#define BM_SSP_CTRL0_CHECK_RESP 0x00040000
-#define BM_SSP_CTRL0_GET_RESP 0x00020000
-#define BM_SSP_CTRL0_ENABLE 0x00010000
-#define BP_SSP_CTRL0_RSVD0 0
-#define BM_SSP_CTRL0_RSVD0 0x0000FFFF
-#define BF_SSP_CTRL0_RSVD0(v) \
- (((v) << 0) & BM_SSP_CTRL0_RSVD0)
-
-#define HW_SSP_CMD0 (0x00000010)
-#define HW_SSP_CMD0_SET (0x00000014)
-#define HW_SSP_CMD0_CLR (0x00000018)
-#define HW_SSP_CMD0_TOG (0x0000001c)
-
-#define BP_SSP_CMD0_RSVD0 27
-#define BM_SSP_CMD0_RSVD0 0xF8000000
-#define BF_SSP_CMD0_RSVD0(v) \
- (((v) << 27) & BM_SSP_CMD0_RSVD0)
-#define BM_SSP_CMD0_SOFT_TERMINATE 0x04000000
-#define BM_SSP_CMD0_DBL_DATA_RATE_EN 0x02000000
-#define BM_SSP_CMD0_PRIM_BOOT_OP_EN 0x01000000
-#define BM_SSP_CMD0_BOOT_ACK_EN 0x00800000
-#define BM_SSP_CMD0_SLOW_CLKING_EN 0x00400000
-#define BM_SSP_CMD0_CONT_CLKING_EN 0x00200000
-#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
-#define BP_SSP_CMD0_RSVD1 8
-#define BM_SSP_CMD0_RSVD1 0x000FFF00
-#define BF_SSP_CMD0_RSVD1(v) \
- (((v) << 8) & BM_SSP_CMD0_RSVD1)
-#define BP_SSP_CMD0_CMD 0
-#define BM_SSP_CMD0_CMD 0x000000FF
-#define BF_SSP_CMD0_CMD(v) \
- (((v) << 0) & BM_SSP_CMD0_CMD)
-#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE 0x00
-#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND 0x01
-#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID 0x02
-#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR 0x03
-#define BV_SSP_CMD0_CMD__MMC_SET_DSR 0x04
-#define BV_SSP_CMD0_CMD__MMC_RESERVED_5 0x05
-#define BV_SSP_CMD0_CMD__MMC_SWITCH 0x06
-#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD 0x07
-#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD 0x08
-#define BV_SSP_CMD0_CMD__MMC_SEND_CSD 0x09
-#define BV_SSP_CMD0_CMD__MMC_SEND_CID 0x0A
-#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP 0x0B
-#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION 0x0C
-#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS 0x0D
-#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R 0x0E
-#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE 0x0F
-#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN 0x10
-#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK 0x11
-#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK 0x12
-#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W 0x13
-#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP 0x14
-#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT 0x17
-#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK 0x18
-#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK 0x19
-#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID 0x1A
-#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD 0x1B
-#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT 0x1C
-#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT 0x1D
-#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT 0x1E
-#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START 0x23
-#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END 0x24
-#define BV_SSP_CMD0_CMD__MMC_ERASE 0x26
-#define BV_SSP_CMD0_CMD__MMC_FAST_IO 0x27
-#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE 0x28
-#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK 0x2A
-#define BV_SSP_CMD0_CMD__MMC_APP_CMD 0x37
-#define BV_SSP_CMD0_CMD__MMC_GEN_CMD 0x38
-#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE 0x00
-#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID 0x02
-#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR 0x03
-#define BV_SSP_CMD0_CMD__SD_SET_DSR 0x04
-#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND 0x05
-#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD 0x07
-#define BV_SSP_CMD0_CMD__SD_SEND_CSD 0x09
-#define BV_SSP_CMD0_CMD__SD_SEND_CID 0x0A
-#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION 0x0C
-#define BV_SSP_CMD0_CMD__SD_SEND_STATUS 0x0D
-#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE 0x0F
-#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN 0x10
-#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK 0x11
-#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK 0x12
-#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK 0x18
-#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK 0x19
-#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD 0x1B
-#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT 0x1C
-#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT 0x1D
-#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT 0x1E
-#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START 0x20
-#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END 0x21
-#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START 0x23
-#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END 0x24
-#define BV_SSP_CMD0_CMD__SD_ERASE 0x26
-#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK 0x2A
-#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT 0x34
-#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED 0x35
-#define BV_SSP_CMD0_CMD__SD_APP_CMD 0x37
-#define BV_SSP_CMD0_CMD__SD_GEN_CMD 0x38
-
-#define HW_SSP_CMD1 (0x00000020)
-
-#define BP_SSP_CMD1_CMD_ARG 0
-#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
-#define BF_SSP_CMD1_CMD_ARG(v) (v)
-
-#define HW_SSP_XFER_SIZE (0x00000030)
-
-#define BP_SSP_XFER_SIZE_XFER_COUNT 0
-#define BM_SSP_XFER_SIZE_XFER_COUNT 0xFFFFFFFF
-#define BF_SSP_XFER_SIZE_XFER_COUNT(v) (v)
-
-#define HW_SSP_BLOCK_SIZE (0x00000040)
-
-#define BP_SSP_BLOCK_SIZE_RSVD0 28
-#define BM_SSP_BLOCK_SIZE_RSVD0 0xF0000000
-#define BF_SSP_BLOCK_SIZE_RSVD0(v) \
- (((v) << 28) & BM_SSP_BLOCK_SIZE_RSVD0)
-#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT 4
-#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT 0x0FFFFFF0
-#define BF_SSP_BLOCK_SIZE_BLOCK_COUNT(v) \
- (((v) << 4) & BM_SSP_BLOCK_SIZE_BLOCK_COUNT)
-#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE 0
-#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE 0x0000000F
-#define BF_SSP_BLOCK_SIZE_BLOCK_SIZE(v) \
- (((v) << 0) & BM_SSP_BLOCK_SIZE_BLOCK_SIZE)
-
-#define HW_SSP_COMPREF (0x00000050)
-
-#define BP_SSP_COMPREF_REFERENCE 0
-#define BM_SSP_COMPREF_REFERENCE 0xFFFFFFFF
-#define BF_SSP_COMPREF_REFERENCE(v) (v)
-
-#define HW_SSP_COMPMASK (0x00000060)
-
-#define BP_SSP_COMPMASK_MASK 0
-#define BM_SSP_COMPMASK_MASK 0xFFFFFFFF
-#define BF_SSP_COMPMASK_MASK(v) (v)
-
-#define HW_SSP_TIMING (0x00000070)
-
-#define BP_SSP_TIMING_TIMEOUT 16
-#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
-#define BF_SSP_TIMING_TIMEOUT(v) \
- (((v) << 16) & BM_SSP_TIMING_TIMEOUT)
-#define BP_SSP_TIMING_CLOCK_DIVIDE 8
-#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
-#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \
- (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
-#define BP_SSP_TIMING_CLOCK_RATE 0
-#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
-#define BF_SSP_TIMING_CLOCK_RATE(v) \
- (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
-
-#define HW_SSP_CTRL1 (0x00000080)
-#define HW_SSP_CTRL1_SET (0x00000084)
-#define HW_SSP_CTRL1_CLR (0x00000088)
-#define HW_SSP_CTRL1_TOG (0x0000008c)
-
-#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
-#define BM_SSP_CTRL1_SDIO_IRQ_EN 0x40000000
-#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
-#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
-#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
-#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
-#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
-#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
-#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
-#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
-#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
-#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN 0x00100000
-#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ 0x00080000
-#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 0x00040000
-#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
-#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
-#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
-#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 0x00004000
-#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
-#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN 0x00001000
-#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE 0x00000800
-#define BM_SSP_CTRL1_PHASE 0x00000400
-#define BM_SSP_CTRL1_POLARITY 0x00000200
-#define BM_SSP_CTRL1_SLAVE_MODE 0x00000100
-#define BP_SSP_CTRL1_WORD_LENGTH 4
-#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
-#define BF_SSP_CTRL1_WORD_LENGTH(v) \
- (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
-#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0 0x0
-#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1 0x1
-#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2 0x2
-#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3
-#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7
-#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF
-#define BP_SSP_CTRL1_SSP_MODE 0
-#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
-#define BF_SSP_CTRL1_SSP_MODE(v) \
- (((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
-#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0
-#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1
-#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3
-#define BV_SSP_CTRL1_SSP_MODE__MS 0x4
-
-#define HW_SSP_DATA (0x00000090)
-
-#define BP_SSP_DATA_DATA 0
-#define BM_SSP_DATA_DATA 0xFFFFFFFF
-#define BF_SSP_DATA_DATA(v) (v)
-
-#define HW_SSP_SDRESP0 (0x000000a0)
-
-#define BP_SSP_SDRESP0_RESP0 0
-#define BM_SSP_SDRESP0_RESP0 0xFFFFFFFF
-#define BF_SSP_SDRESP0_RESP0(v) (v)
-
-#define HW_SSP_SDRESP1 (0x000000b0)
-
-#define BP_SSP_SDRESP1_RESP1 0
-#define BM_SSP_SDRESP1_RESP1 0xFFFFFFFF
-#define BF_SSP_SDRESP1_RESP1(v) (v)
-
-#define HW_SSP_SDRESP2 (0x000000c0)
-
-#define BP_SSP_SDRESP2_RESP2 0
-#define BM_SSP_SDRESP2_RESP2 0xFFFFFFFF
-#define BF_SSP_SDRESP2_RESP2(v) (v)
-
-#define HW_SSP_SDRESP3 (0x000000d0)
-
-#define BP_SSP_SDRESP3_RESP3 0
-#define BM_SSP_SDRESP3_RESP3 0xFFFFFFFF
-#define BF_SSP_SDRESP3_RESP3(v) (v)
-
-#define HW_SSP_DDR_CTRL (0x000000e0)
-
-#define BP_SSP_DDR_CTRL_DMA_BURST_TYPE 30
-#define BM_SSP_DDR_CTRL_DMA_BURST_TYPE 0xC0000000
-#define BF_SSP_DDR_CTRL_DMA_BURST_TYPE(v) \
- (((v) << 30) & BM_SSP_DDR_CTRL_DMA_BURST_TYPE)
-#define BP_SSP_DDR_CTRL_RSVD0 2
-#define BM_SSP_DDR_CTRL_RSVD0 0x3FFFFFFC
-#define BF_SSP_DDR_CTRL_RSVD0(v) \
- (((v) << 2) & BM_SSP_DDR_CTRL_RSVD0)
-#define BM_SSP_DDR_CTRL_NIBBLE_POS 0x00000002
-#define BM_SSP_DDR_CTRL_TXCLK_DELAY_TYPE 0x00000001
-
-#define HW_SSP_DLL_CTRL (0x000000f0)
-
-#define BP_SSP_DLL_CTRL_REF_UPDATE_INT 28
-#define BM_SSP_DLL_CTRL_REF_UPDATE_INT 0xF0000000
-#define BF_SSP_DLL_CTRL_REF_UPDATE_INT(v) \
- (((v) << 28) & BM_SSP_DLL_CTRL_REF_UPDATE_INT)
-#define BP_SSP_DLL_CTRL_SLV_UPDATE_INT 20
-#define BM_SSP_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000
-#define BF_SSP_DLL_CTRL_SLV_UPDATE_INT(v) \
- (((v) << 20) & BM_SSP_DLL_CTRL_SLV_UPDATE_INT)
-#define BP_SSP_DLL_CTRL_RSVD1 16
-#define BM_SSP_DLL_CTRL_RSVD1 0x000F0000
-#define BF_SSP_DLL_CTRL_RSVD1(v) \
- (((v) << 16) & BM_SSP_DLL_CTRL_RSVD1)
-#define BP_SSP_DLL_CTRL_SLV_OVERRIDE_VAL 10
-#define BM_SSP_DLL_CTRL_SLV_OVERRIDE_VAL 0x0000FC00
-#define BF_SSP_DLL_CTRL_SLV_OVERRIDE_VAL(v) \
- (((v) << 10) & BM_SSP_DLL_CTRL_SLV_OVERRIDE_VAL)
-#define BM_SSP_DLL_CTRL_SLV_OVERRIDE 0x00000200
-#define BM_SSP_DLL_CTRL_RSVD0 0x00000100
-#define BM_SSP_DLL_CTRL_GATE_UPDATE 0x00000080
-#define BP_SSP_DLL_CTRL_SLV_DLY_TARGET 3
-#define BM_SSP_DLL_CTRL_SLV_DLY_TARGET 0x00000078
-#define BF_SSP_DLL_CTRL_SLV_DLY_TARGET(v) \
- (((v) << 3) & BM_SSP_DLL_CTRL_SLV_DLY_TARGET)
-#define BM_SSP_DLL_CTRL_SLV_FORCE_UPD 0x00000004
-#define BM_SSP_DLL_CTRL_RESET 0x00000002
-#define BM_SSP_DLL_CTRL_ENABLE 0x00000001
-
-#define HW_SSP_STATUS (0x00000100)
-
-#define BM_SSP_STATUS_PRESENT 0x80000000
-#define BM_SSP_STATUS_MS_PRESENT 0x40000000
-#define BM_SSP_STATUS_SD_PRESENT 0x20000000
-#define BM_SSP_STATUS_CARD_DETECT 0x10000000
-#define BP_SSP_STATUS_RSVD3 23
-#define BM_SSP_STATUS_RSVD3 0x0F800000
-#define BF_SSP_STATUS_RSVD3(v) \
- (((v) << 23) & BM_SSP_STATUS_RSVD3)
-#define BM_SSP_STATUS_DMABURST 0x00400000
-#define BM_SSP_STATUS_DMASENSE 0x00200000
-#define BM_SSP_STATUS_DMATERM 0x00100000
-#define BM_SSP_STATUS_DMAREQ 0x00080000
-#define BM_SSP_STATUS_DMAEND 0x00040000
-#define BM_SSP_STATUS_SDIO_IRQ 0x00020000
-#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
-#define BM_SSP_STATUS_RESP_ERR 0x00008000
-#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
-#define BM_SSP_STATUS_DATA_CRC_ERR 0x00002000
-#define BM_SSP_STATUS_TIMEOUT 0x00001000
-#define BM_SSP_STATUS_RECV_TIMEOUT_STAT 0x00000800
-#define BM_SSP_STATUS_CEATA_CCS_ERR 0x00000400
-#define BM_SSP_STATUS_FIFO_OVRFLW 0x00000200
-#define BM_SSP_STATUS_FIFO_FULL 0x00000100
-#define BP_SSP_STATUS_RSVD1 6
-#define BM_SSP_STATUS_RSVD1 0x000000C0
-#define BF_SSP_STATUS_RSVD1(v) \
- (((v) << 6) & BM_SSP_STATUS_RSVD1)
-#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
-#define BM_SSP_STATUS_FIFO_UNDRFLW 0x00000010
-#define BM_SSP_STATUS_CMD_BUSY 0x00000008
-#define BM_SSP_STATUS_DATA_BUSY 0x00000004
-#define BM_SSP_STATUS_RSVD0 0x00000002
-#define BM_SSP_STATUS_BUSY 0x00000001
-
-#define HW_SSP_DLL_STS (0x00000110)
-
-#define BP_SSP_DLL_STS_RSVD0 14
-#define BM_SSP_DLL_STS_RSVD0 0xFFFFC000
-#define BF_SSP_DLL_STS_RSVD0(v) \
- (((v) << 14) & BM_SSP_DLL_STS_RSVD0)
-#define BP_SSP_DLL_STS_REF_SEL 8
-#define BM_SSP_DLL_STS_REF_SEL 0x00003F00
-#define BF_SSP_DLL_STS_REF_SEL(v) \
- (((v) << 8) & BM_SSP_DLL_STS_REF_SEL)
-#define BP_SSP_DLL_STS_SLV_SEL 2
-#define BM_SSP_DLL_STS_SLV_SEL 0x000000FC
-#define BF_SSP_DLL_STS_SLV_SEL(v) \
- (((v) << 2) & BM_SSP_DLL_STS_SLV_SEL)
-#define BM_SSP_DLL_STS_REF_LOCK 0x00000002
-#define BM_SSP_DLL_STS_SLV_LOCK 0x00000001
-
-#define HW_SSP_DEBUG (0x00000120)
-
-#define BP_SSP_DEBUG_DATACRC_ERR 28
-#define BM_SSP_DEBUG_DATACRC_ERR 0xF0000000
-#define BF_SSP_DEBUG_DATACRC_ERR(v) \
- (((v) << 28) & BM_SSP_DEBUG_DATACRC_ERR)
-#define BM_SSP_DEBUG_DATA_STALL 0x08000000
-#define BP_SSP_DEBUG_DAT_SM 24
-#define BM_SSP_DEBUG_DAT_SM 0x07000000
-#define BF_SSP_DEBUG_DAT_SM(v) \
- (((v) << 24) & BM_SSP_DEBUG_DAT_SM)
-#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE 0x0
-#define BV_SSP_DEBUG_DAT_SM__DSM_WORD 0x2
-#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1 0x3
-#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2 0x4
-#define BV_SSP_DEBUG_DAT_SM__DSM_END 0x5
-#define BP_SSP_DEBUG_MSTK_SM 20
-#define BM_SSP_DEBUG_MSTK_SM 0x00F00000
-#define BF_SSP_DEBUG_MSTK_SM(v) \
- (((v) << 20) & BM_SSP_DEBUG_MSTK_SM)
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE 0x0
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON 0x1
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1 0x2
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC 0x3
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2 0x4
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK 0x5
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3 0x6
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW 0x7
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1 0x8
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2 0x9
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0 0xA
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1 0xB
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W 0xC
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R 0xD
-#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE 0xE
-#define BM_SSP_DEBUG_CMD_OE 0x00080000
-#define BP_SSP_DEBUG_DMA_SM 16
-#define BM_SSP_DEBUG_DMA_SM 0x00070000
-#define BF_SSP_DEBUG_DMA_SM(v) \
- (((v) << 16) & BM_SSP_DEBUG_DMA_SM)
-#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE 0x0
-#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ 0x1
-#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK 0x2
-#define BV_SSP_DEBUG_DMA_SM__DMA_STALL 0x3
-#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY 0x4
-#define BV_SSP_DEBUG_DMA_SM__DMA_DONE 0x5
-#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT 0x6
-#define BP_SSP_DEBUG_MMC_SM 12
-#define BM_SSP_DEBUG_MMC_SM 0x0000F000
-#define BF_SSP_DEBUG_MMC_SM(v) \
- (((v) << 12) & BM_SSP_DEBUG_MMC_SM)
-#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE 0x0
-#define BV_SSP_DEBUG_MMC_SM__MMC_CMD 0x1
-#define BV_SSP_DEBUG_MMC_SM__MMC_TRC 0x2
-#define BV_SSP_DEBUG_MMC_SM__MMC_RESP 0x3
-#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX 0x4
-#define BV_SSP_DEBUG_MMC_SM__MMC_TX 0x5
-#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK 0x6
-#define BV_SSP_DEBUG_MMC_SM__MMC_RX 0x7
-#define BV_SSP_DEBUG_MMC_SM__MMC_CCS 0x8
-#define BV_SSP_DEBUG_MMC_SM__MMC_PUP 0x9
-#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT 0xA
-#define BP_SSP_DEBUG_CMD_SM 10
-#define BM_SSP_DEBUG_CMD_SM 0x00000C00
-#define BF_SSP_DEBUG_CMD_SM(v) \
- (((v) << 10) & BM_SSP_DEBUG_CMD_SM)
-#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE 0x0
-#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX 0x1
-#define BV_SSP_DEBUG_CMD_SM__CSM_ARG 0x2
-#define BV_SSP_DEBUG_CMD_SM__CSM_CRC 0x3
-#define BM_SSP_DEBUG_SSP_CMD 0x00000200
-#define BM_SSP_DEBUG_SSP_RESP 0x00000100
-#define BP_SSP_DEBUG_SSP_RXD 0
-#define BM_SSP_DEBUG_SSP_RXD 0x000000FF
-#define BF_SSP_DEBUG_SSP_RXD(v) \
- (((v) << 0) & BM_SSP_DEBUG_SSP_RXD)
-
-#define HW_SSP_VERSION (0x00000130)
-
-#define BP_SSP_VERSION_MAJOR 24
-#define BM_SSP_VERSION_MAJOR 0xFF000000
-#define BF_SSP_VERSION_MAJOR(v) \
- (((v) << 24) & BM_SSP_VERSION_MAJOR)
-#define BP_SSP_VERSION_MINOR 16
-#define BM_SSP_VERSION_MINOR 0x00FF0000
-#define BF_SSP_VERSION_MINOR(v) \
- (((v) << 16) & BM_SSP_VERSION_MINOR)
-#define BP_SSP_VERSION_STEP 0
-#define BM_SSP_VERSION_STEP 0x0000FFFF
-#define BF_SSP_VERSION_STEP(v) \
- (((v) << 0) & BM_SSP_VERSION_STEP)
-#endif /* __ARCH_ARM___SSP_H */
+++ /dev/null
-/*
- * Freescale TIMROT Register Definitions
- *
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * This file is created by xml file. Don't Edit it.
- *
- * Xml Revision: 1.40
- * Template revision: 26195
- */
-
-#ifndef __ARCH_ARM___TIMROT_H
-#define __ARCH_ARM___TIMROT_H
-
-
-#define HW_TIMROT_ROTCTRL (0x00000000)
-#define HW_TIMROT_ROTCTRL_SET (0x00000004)
-#define HW_TIMROT_ROTCTRL_CLR (0x00000008)
-#define HW_TIMROT_ROTCTRL_TOG (0x0000000c)
-
-#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
-#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
-#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000
-#define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000
-#define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x08000000
-#define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x04000000
-#define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x02000000
-#define BP_TIMROT_ROTCTRL_STATE 22
-#define BM_TIMROT_ROTCTRL_STATE 0x01C00000
-#define BF_TIMROT_ROTCTRL_STATE(v) \
- (((v) << 22) & BM_TIMROT_ROTCTRL_STATE)
-#define BP_TIMROT_ROTCTRL_DIVIDER 16
-#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000
-#define BF_TIMROT_ROTCTRL_DIVIDER(v) \
- (((v) << 16) & BM_TIMROT_ROTCTRL_DIVIDER)
-#define BP_TIMROT_ROTCTRL_RSRVD3 13
-#define BM_TIMROT_ROTCTRL_RSRVD3 0x0000E000
-#define BF_TIMROT_ROTCTRL_RSRVD3(v) \
- (((v) << 13) & BM_TIMROT_ROTCTRL_RSRVD3)
-#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000
-#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10
-#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00
-#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) \
- (((v) << 10) & BM_TIMROT_ROTCTRL_OVERSAMPLE)
-#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0
-#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1
-#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2
-#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3
-#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200
-#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100
-#define BP_TIMROT_ROTCTRL_SELECT_B 4
-#define BM_TIMROT_ROTCTRL_SELECT_B 0x000000F0
-#define BF_TIMROT_ROTCTRL_SELECT_B(v) \
- (((v) << 4) & BM_TIMROT_ROTCTRL_SELECT_B)
-#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM5 0x6
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM6 0x7
-#define BV_TIMROT_ROTCTRL_SELECT_B__PWM7 0x8
-#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x9
-#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0xA
-#define BP_TIMROT_ROTCTRL_SELECT_A 0
-#define BM_TIMROT_ROTCTRL_SELECT_A 0x0000000F
-#define BF_TIMROT_ROTCTRL_SELECT_A(v) \
- (((v) << 0) & BM_TIMROT_ROTCTRL_SELECT_A)
-#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM5 0x6
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM6 0x7
-#define BV_TIMROT_ROTCTRL_SELECT_A__PWM7 0x8
-#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x9
-#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0xA
-
-#define HW_TIMROT_ROTCOUNT (0x00000010)
-
-#define BP_TIMROT_ROTCOUNT_RSRVD1 16
-#define BM_TIMROT_ROTCOUNT_RSRVD1 0xFFFF0000
-#define BF_TIMROT_ROTCOUNT_RSRVD1(v) \
- (((v) << 16) & BM_TIMROT_ROTCOUNT_RSRVD1)
-#define BP_TIMROT_ROTCOUNT_UPDOWN 0
-#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF
-#define BF_TIMROT_ROTCOUNT_UPDOWN(v) \
- (((v) << 0) & BM_TIMROT_ROTCOUNT_UPDOWN)
-
-/*
- * multi-register-define name HW_TIMROT_TIMCTRLn
- * base 0x00000020
- * count 3
- * offset 0x40
- */
-#define HW_TIMROT_TIMCTRLn(n) (0x00000020 + (n) * 0x40)
-#define HW_TIMROT_TIMCTRLn_SET(n) (0x00000024 + (n) * 0x40)
-#define HW_TIMROT_TIMCTRLn_CLR(n) (0x00000028 + (n) * 0x40)
-#define HW_TIMROT_TIMCTRLn_TOG(n) (0x0000002c + (n) * 0x40)
-#define BP_TIMROT_TIMCTRLn_RSRVD3 16
-#define BM_TIMROT_TIMCTRLn_RSRVD3 0xFFFF0000
-#define BF_TIMROT_TIMCTRLn_RSRVD3(v) \
- (((v) << 16) & BM_TIMROT_TIMCTRLn_RSRVD3)
-#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
-#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
-#define BP_TIMROT_TIMCTRLn_RSRVD2 12
-#define BM_TIMROT_TIMCTRLn_RSRVD2 0x00003000
-#define BF_TIMROT_TIMCTRLn_RSRVD2(v) \
- (((v) << 12) & BM_TIMROT_TIMCTRLn_RSRVD2)
-#define BM_TIMROT_TIMCTRLn_MATCH_MODE 0x00000800
-#define BP_TIMROT_TIMCTRLn_RSRVD1 9
-#define BM_TIMROT_TIMCTRLn_RSRVD1 0x00000600
-#define BF_TIMROT_TIMCTRLn_RSRVD1(v) \
- (((v) << 9) & BM_TIMROT_TIMCTRLn_RSRVD1)
-#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100
-#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
-#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
-#define BP_TIMROT_TIMCTRLn_PRESCALE 4
-#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
-#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \
- (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE)
-#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0
-#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1
-#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2
-#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3
-#define BP_TIMROT_TIMCTRLn_SELECT 0
-#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
-#define BF_TIMROT_TIMCTRLn_SELECT(v) \
- (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT)
-#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM5 0x6
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM6 0x7
-#define BV_TIMROT_TIMCTRLn_SELECT__PWM7 0x8
-#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x9
-#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0xA
-#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0xB
-#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0xC
-#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xD
-#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xE
-#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xF
-
-/*
- * multi-register-define name HW_TIMROT_RUNNING_COUNTn
- * base 0x00000030
- * count 3
- * offset 0x40
- */
-#define HW_TIMROT_RUNNING_COUNTn(n) (0x00000030 + (n) * 0x40)
-#define BP_TIMROT_RUNNING_COUNTn_RUNNING_COUNT 0
-#define BM_TIMROT_RUNNING_COUNTn_RUNNING_COUNT 0xFFFFFFFF
-#define BF_TIMROT_RUNNING_COUNTn_RUNNING_COUNT(v) (v)
-
-/*
- * multi-register-define name HW_TIMROT_FIXED_COUNTn
- * base 0x00000040
- * count 3
- * offset 0x40
- */
-#define HW_TIMROT_FIXED_COUNTn(n) (0x00000040 + (n) * 0x40)
-#define BP_TIMROT_FIXED_COUNTn_FIXED_COUNT 0
-#define BM_TIMROT_FIXED_COUNTn_FIXED_COUNT 0xFFFFFFFF
-#define BF_TIMROT_FIXED_COUNTn_FIXED_COUNT(v) (v)
-
-/*
- * multi-register-define name HW_TIMROT_MATCH_COUNTn
- * base 0x00000050
- * count 4
- * offset 0x40
- */
-#define HW_TIMROT_MATCH_COUNTn(n) (0x00000050 + (n) * 0x40)
-#define BP_TIMROT_MATCH_COUNTn_MATCH_COUNT 0
-#define BM_TIMROT_MATCH_COUNTn_MATCH_COUNT 0xFFFFFFFF
-#define BF_TIMROT_MATCH_COUNTn_MATCH_COUNT(v) (v)
-
-#define HW_TIMROT_TIMCTRL3 (0x000000e0)
-#define HW_TIMROT_TIMCTRL3_SET (0x000000e4)
-#define HW_TIMROT_TIMCTRL3_CLR (0x000000e8)
-#define HW_TIMROT_TIMCTRL3_TOG (0x000000ec)
-
-#define BP_TIMROT_TIMCTRL3_RSRVD2 20
-#define BM_TIMROT_TIMCTRL3_RSRVD2 0xFFF00000
-#define BF_TIMROT_TIMCTRL3_RSRVD2(v) \
- (((v) << 20) & BM_TIMROT_TIMCTRL3_RSRVD2)
-#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16
-#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0x000F0000
-#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) \
- (((v) << 16) & BM_TIMROT_TIMCTRL3_TEST_SIGNAL)
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM5 0x6
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM6 0x7
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM7 0x8
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x9
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0xA
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0xB
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0xC
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xD
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xE
-#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xF
-#define BM_TIMROT_TIMCTRL3_IRQ 0x00008000
-#define BM_TIMROT_TIMCTRL3_IRQ_EN 0x00004000
-#define BP_TIMROT_TIMCTRL3_RSRVD1 12
-#define BM_TIMROT_TIMCTRL3_RSRVD1 0x00003000
-#define BF_TIMROT_TIMCTRL3_RSRVD1(v) \
- (((v) << 12) & BM_TIMROT_TIMCTRL3_RSRVD1)
-#define BM_TIMROT_TIMCTRL3_MATCH_MODE 0x00000800
-#define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x00000400
-#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x00000200
-#define BM_TIMROT_TIMCTRL3_POLARITY 0x00000100
-#define BM_TIMROT_TIMCTRL3_UPDATE 0x00000080
-#define BM_TIMROT_TIMCTRL3_RELOAD 0x00000040
-#define BP_TIMROT_TIMCTRL3_PRESCALE 4
-#define BM_TIMROT_TIMCTRL3_PRESCALE 0x00000030
-#define BF_TIMROT_TIMCTRL3_PRESCALE(v) \
- (((v) << 4) & BM_TIMROT_TIMCTRL3_PRESCALE)
-#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0
-#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1
-#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2
-#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3
-#define BP_TIMROT_TIMCTRL3_SELECT 0
-#define BM_TIMROT_TIMCTRL3_SELECT 0x0000000F
-#define BF_TIMROT_TIMCTRL3_SELECT(v) \
- (((v) << 0) & BM_TIMROT_TIMCTRL3_SELECT)
-#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM5 0x6
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM6 0x7
-#define BV_TIMROT_TIMCTRL3_SELECT__PWM7 0x8
-#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x9
-#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0xA
-#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0xB
-#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0xC
-#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xD
-#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xE
-#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xF
-
-#define HW_TIMROT_RUNNING_COUNT3 (0x000000f0)
-
-#define BP_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT 0
-#define BM_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT 0xFFFFFFFF
-#define BF_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT(v) (v)
-
-#define HW_TIMROT_FIXED_COUNT3 (0x00000100)
-
-#define BP_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT 0
-#define BM_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT 0xFFFFFFFF
-#define BF_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT(v) (v)
-
-#define HW_TIMROT_VERSION (0x00000120)
-
-#define BP_TIMROT_VERSION_MAJOR 24
-#define BM_TIMROT_VERSION_MAJOR 0xFF000000
-#define BF_TIMROT_VERSION_MAJOR(v) \
- (((v) << 24) & BM_TIMROT_VERSION_MAJOR)
-#define BP_TIMROT_VERSION_MINOR 16
-#define BM_TIMROT_VERSION_MINOR 0x00FF0000
-#define BF_TIMROT_VERSION_MINOR(v) \
- (((v) << 16) & BM_TIMROT_VERSION_MINOR)
-#define BP_TIMROT_VERSION_STEP 0
-#define BM_TIMROT_VERSION_STEP 0x0000FFFF
-#define BF_TIMROT_VERSION_STEP(v) \
- (((v) << 0) & BM_TIMROT_VERSION_STEP)
-#endif /* __ARCH_ARM___TIMROT_H */
+++ /dev/null
-/*
- * Freescale UARTDBG Register Definitions
- *
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * This file is created by xml file. Don't Edit it.
- *
- * Xml Revision: 1.21
- * Template revision: 26195
- */
-
-#ifndef __ARCH_ARM___UARTDBG_H
-#define __ARCH_ARM___UARTDBG_H
-
-
-#define HW_UARTDBGDR (0x00000000)
-
-#define BP_UARTDBGDR_UNAVAILABLE 16
-#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGDR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
-#define BP_UARTDBGDR_RESERVED 12
-#define BM_UARTDBGDR_RESERVED 0x0000F000
-#define BF_UARTDBGDR_RESERVED(v) \
- (((v) << 12) & BM_UARTDBGDR_RESERVED)
-#define BM_UARTDBGDR_OE 0x00000800
-#define BM_UARTDBGDR_BE 0x00000400
-#define BM_UARTDBGDR_PE 0x00000200
-#define BM_UARTDBGDR_FE 0x00000100
-#define BP_UARTDBGDR_DATA 0
-#define BM_UARTDBGDR_DATA 0x000000FF
-#define BF_UARTDBGDR_DATA(v) \
- (((v) << 0) & BM_UARTDBGDR_DATA)
-
-#define HW_UARTDBGRSR_ECR (0x00000004)
-
-#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
-#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
-#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
- (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
-#define BP_UARTDBGRSR_ECR_EC 4
-#define BM_UARTDBGRSR_ECR_EC 0x000000F0
-#define BF_UARTDBGRSR_ECR_EC(v) \
- (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
-#define BM_UARTDBGRSR_ECR_OE 0x00000008
-#define BM_UARTDBGRSR_ECR_BE 0x00000004
-#define BM_UARTDBGRSR_ECR_PE 0x00000002
-#define BM_UARTDBGRSR_ECR_FE 0x00000001
-
-#define HW_UARTDBGFR (0x00000018)
-
-#define BP_UARTDBGFR_UNAVAILABLE 16
-#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGFR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
-#define BP_UARTDBGFR_RESERVED 9
-#define BM_UARTDBGFR_RESERVED 0x0000FE00
-#define BF_UARTDBGFR_RESERVED(v) \
- (((v) << 9) & BM_UARTDBGFR_RESERVED)
-#define BM_UARTDBGFR_RI 0x00000100
-#define BM_UARTDBGFR_TXFE 0x00000080
-#define BM_UARTDBGFR_RXFF 0x00000040
-#define BM_UARTDBGFR_TXFF 0x00000020
-#define BM_UARTDBGFR_RXFE 0x00000010
-#define BM_UARTDBGFR_BUSY 0x00000008
-#define BM_UARTDBGFR_DCD 0x00000004
-#define BM_UARTDBGFR_DSR 0x00000002
-#define BM_UARTDBGFR_CTS 0x00000001
-
-#define HW_UARTDBGILPR (0x00000020)
-
-#define BP_UARTDBGILPR_UNAVAILABLE 8
-#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
-#define BF_UARTDBGILPR_UNAVAILABLE(v) \
- (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
-#define BP_UARTDBGILPR_ILPDVSR 0
-#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
-#define BF_UARTDBGILPR_ILPDVSR(v) \
- (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
-
-#define HW_UARTDBGIBRD (0x00000024)
-
-#define BP_UARTDBGIBRD_UNAVAILABLE 16
-#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
-#define BP_UARTDBGIBRD_BAUD_DIVINT 0
-#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
-#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
- (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
-
-#define HW_UARTDBGFBRD (0x00000028)
-
-#define BP_UARTDBGFBRD_UNAVAILABLE 8
-#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
-#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
- (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
-#define BP_UARTDBGFBRD_RESERVED 6
-#define BM_UARTDBGFBRD_RESERVED 0x000000C0
-#define BF_UARTDBGFBRD_RESERVED(v) \
- (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
-#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
-#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
-#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
- (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
-
-#define HW_UARTDBGLCR_H (0x0000002c)
-
-#define BP_UARTDBGLCR_H_UNAVAILABLE 16
-#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
-#define BP_UARTDBGLCR_H_RESERVED 8
-#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
-#define BF_UARTDBGLCR_H_RESERVED(v) \
- (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
-#define BM_UARTDBGLCR_H_SPS 0x00000080
-#define BP_UARTDBGLCR_H_WLEN 5
-#define BM_UARTDBGLCR_H_WLEN 0x00000060
-#define BF_UARTDBGLCR_H_WLEN(v) \
- (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
-#define BM_UARTDBGLCR_H_FEN 0x00000010
-#define BM_UARTDBGLCR_H_STP2 0x00000008
-#define BM_UARTDBGLCR_H_EPS 0x00000004
-#define BM_UARTDBGLCR_H_PEN 0x00000002
-#define BM_UARTDBGLCR_H_BRK 0x00000001
-
-#define HW_UARTDBGCR (0x00000030)
-
-#define BP_UARTDBGCR_UNAVAILABLE 16
-#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGCR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
-#define BM_UARTDBGCR_CTSEN 0x00008000
-#define BM_UARTDBGCR_RTSEN 0x00004000
-#define BM_UARTDBGCR_OUT2 0x00002000
-#define BM_UARTDBGCR_OUT1 0x00001000
-#define BM_UARTDBGCR_RTS 0x00000800
-#define BM_UARTDBGCR_DTR 0x00000400
-#define BM_UARTDBGCR_RXE 0x00000200
-#define BM_UARTDBGCR_TXE 0x00000100
-#define BM_UARTDBGCR_LBE 0x00000080
-#define BP_UARTDBGCR_RESERVED 3
-#define BM_UARTDBGCR_RESERVED 0x00000078
-#define BF_UARTDBGCR_RESERVED(v) \
- (((v) << 3) & BM_UARTDBGCR_RESERVED)
-#define BM_UARTDBGCR_SIRLP 0x00000004
-#define BM_UARTDBGCR_SIREN 0x00000002
-#define BM_UARTDBGCR_UARTEN 0x00000001
-
-#define HW_UARTDBGIFLS (0x00000034)
-
-#define BP_UARTDBGIFLS_UNAVAILABLE 16
-#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
-#define BP_UARTDBGIFLS_RESERVED 6
-#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
-#define BF_UARTDBGIFLS_RESERVED(v) \
- (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
-#define BP_UARTDBGIFLS_RXIFLSEL 3
-#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
-#define BF_UARTDBGIFLS_RXIFLSEL(v) \
- (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
-#define BV_UARTDBGIFLS_RXIFLSEL__ONE_EIGHT 0x0
-#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
-#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
-#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
-#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
-#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
-#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
-#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
-#define BP_UARTDBGIFLS_TXIFLSEL 0
-#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
-#define BF_UARTDBGIFLS_TXIFLSEL(v) \
- (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
-#define BV_UARTDBGIFLS_TXIFLSEL__ONE_EIGHT 0x0
-#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
-#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
-#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
-#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
-#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
-#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
-#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
-
-#define HW_UARTDBGIMSC (0x00000038)
-
-#define BP_UARTDBGIMSC_UNAVAILABLE 16
-#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
-#define BP_UARTDBGIMSC_RESERVED 11
-#define BM_UARTDBGIMSC_RESERVED 0x0000F800
-#define BF_UARTDBGIMSC_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
-#define BM_UARTDBGIMSC_OEIM 0x00000400
-#define BM_UARTDBGIMSC_BEIM 0x00000200
-#define BM_UARTDBGIMSC_PEIM 0x00000100
-#define BM_UARTDBGIMSC_FEIM 0x00000080
-#define BM_UARTDBGIMSC_RTIM 0x00000040
-#define BM_UARTDBGIMSC_TXIM 0x00000020
-#define BM_UARTDBGIMSC_RXIM 0x00000010
-#define BM_UARTDBGIMSC_DSRMIM 0x00000008
-#define BM_UARTDBGIMSC_DCDMIM 0x00000004
-#define BM_UARTDBGIMSC_CTSMIM 0x00000002
-#define BM_UARTDBGIMSC_RIMIM 0x00000001
-
-#define HW_UARTDBGRIS (0x0000003c)
-
-#define BP_UARTDBGRIS_UNAVAILABLE 16
-#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGRIS_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
-#define BP_UARTDBGRIS_RESERVED 11
-#define BM_UARTDBGRIS_RESERVED 0x0000F800
-#define BF_UARTDBGRIS_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGRIS_RESERVED)
-#define BM_UARTDBGRIS_OERIS 0x00000400
-#define BM_UARTDBGRIS_BERIS 0x00000200
-#define BM_UARTDBGRIS_PERIS 0x00000100
-#define BM_UARTDBGRIS_FERIS 0x00000080
-#define BM_UARTDBGRIS_RTRIS 0x00000040
-#define BM_UARTDBGRIS_TXRIS 0x00000020
-#define BM_UARTDBGRIS_RXRIS 0x00000010
-#define BM_UARTDBGRIS_DSRRMIS 0x00000008
-#define BM_UARTDBGRIS_DCDRMIS 0x00000004
-#define BM_UARTDBGRIS_CTSRMIS 0x00000002
-#define BM_UARTDBGRIS_RIRMIS 0x00000001
-
-#define HW_UARTDBGMIS (0x00000040)
-
-#define BP_UARTDBGMIS_UNAVAILABLE 16
-#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGMIS_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
-#define BP_UARTDBGMIS_RESERVED 11
-#define BM_UARTDBGMIS_RESERVED 0x0000F800
-#define BF_UARTDBGMIS_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGMIS_RESERVED)
-#define BM_UARTDBGMIS_OEMIS 0x00000400
-#define BM_UARTDBGMIS_BEMIS 0x00000200
-#define BM_UARTDBGMIS_PEMIS 0x00000100
-#define BM_UARTDBGMIS_FEMIS 0x00000080
-#define BM_UARTDBGMIS_RTMIS 0x00000040
-#define BM_UARTDBGMIS_TXMIS 0x00000020
-#define BM_UARTDBGMIS_RXMIS 0x00000010
-#define BM_UARTDBGMIS_DSRMMIS 0x00000008
-#define BM_UARTDBGMIS_DCDMMIS 0x00000004
-#define BM_UARTDBGMIS_CTSMMIS 0x00000002
-#define BM_UARTDBGMIS_RIMMIS 0x00000001
-
-#define HW_UARTDBGICR (0x00000044)
-
-#define BP_UARTDBGICR_UNAVAILABLE 16
-#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGICR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
-#define BP_UARTDBGICR_RESERVED 11
-#define BM_UARTDBGICR_RESERVED 0x0000F800
-#define BF_UARTDBGICR_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGICR_RESERVED)
-#define BM_UARTDBGICR_OEIC 0x00000400
-#define BM_UARTDBGICR_BEIC 0x00000200
-#define BM_UARTDBGICR_PEIC 0x00000100
-#define BM_UARTDBGICR_FEIC 0x00000080
-#define BM_UARTDBGICR_RTIC 0x00000040
-#define BM_UARTDBGICR_TXIC 0x00000020
-#define BM_UARTDBGICR_RXIC 0x00000010
-#define BM_UARTDBGICR_DSRMIC 0x00000008
-#define BM_UARTDBGICR_DCDMIC 0x00000004
-#define BM_UARTDBGICR_CTSMIC 0x00000002
-#define BM_UARTDBGICR_RIMIC 0x00000001
-
-#define HW_UARTDBGDMACR (0x00000048)
-
-#define BP_UARTDBGDMACR_UNAVAILABLE 16
-#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
-#define BP_UARTDBGDMACR_RESERVED 3
-#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
-#define BF_UARTDBGDMACR_RESERVED(v) \
- (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
-#define BM_UARTDBGDMACR_DMAONERR 0x00000004
-#define BM_UARTDBGDMACR_TXDMAE 0x00000002
-#define BM_UARTDBGDMACR_RXDMAE 0x00000001
-#endif /* __ARCH_ARM___UARTDBG_H */
+++ /dev/null
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __MACH_MX35_IOMUX_H__
-#define __MACH_MX35_IOMUX_H__
-
-#include <asm/arch/mx35.h>
-
-/*!
- * @file mach-mx35/iomux.h
- *
- * @brief I/O Muxing control definitions and functions
- *
- * @ingroup GPIO_MX35
- */
-
-/*!
- * various IOMUX functions
- */
-typedef enum iomux_pin_config {
- MUX_CONFIG_FUNC = 0, /*!< used as function */
- MUX_CONFIG_ALT1, /*!< used as alternate function 1 */
- MUX_CONFIG_ALT2, /*!< used as alternate function 2 */
- MUX_CONFIG_ALT3, /*!< used as alternate function 3 */
- MUX_CONFIG_ALT4, /*!< used as alternate function 4 */
- MUX_CONFIG_ALT5, /*!< used as alternate function 5 */
- MUX_CONFIG_ALT6, /*!< used as alternate function 6 */
- MUX_CONFIG_ALT7, /*!< used as alternate function 7 */
- MUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
- MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /*!< used as GPIO */
-} iomux_pin_cfg_t;
-
-/*!
- * various IOMUX pad functions
- */
-typedef enum iomux_pad_config {
- PAD_CTL_DRV_3_3V = 0x0 << 13,
- PAD_CTL_DRV_1_8V = 0x1 << 13,
- PAD_CTL_HYS_CMOS = 0x0 << 8,
- PAD_CTL_HYS_SCHMITZ = 0x1 << 8,
- PAD_CTL_PKE_NONE = 0x0 << 7,
- PAD_CTL_PKE_ENABLE = 0x1 << 7,
- PAD_CTL_PUE_KEEPER = 0x0 << 6,
- PAD_CTL_PUE_PUD = 0x1 << 6,
- PAD_CTL_100K_PD = 0x0 << 4,
- PAD_CTL_47K_PU = 0x1 << 4,
- PAD_CTL_100K_PU = 0x2 << 4,
- PAD_CTL_22K_PU = 0x3 << 4,
- PAD_CTL_ODE_CMOS = 0x0 << 3,
- PAD_CTL_ODE_OpenDrain = 0x1 << 3,
- PAD_CTL_DRV_NORMAL = 0x0 << 1,
- PAD_CTL_DRV_HIGH = 0x1 << 1,
- PAD_CTL_DRV_MAX = 0x2 << 1,
- PAD_CTL_SRE_SLOW = 0x0 << 0,
- PAD_CTL_SRE_FAST = 0x1 << 0
-} iomux_pad_config_t;
-
-/*!
- * various IOMUX general purpose functions
- */
-typedef enum iomux_gp_func {
- MUX_SDCTL_CSD0_SEL = 0x1 << 0,
- MUX_SDCTL_CSD1_SEL = 0x1 << 1,
- MUX_TAMPER_DETECT_EN = 0x1 << 2,
-} iomux_gp_func_t;
-
-/*!
- * various IOMUX input select register index
- */
-typedef enum iomux_input_select {
- MUX_IN_AMX_P5_RXCLK = 0,
- MUX_IN_AMX_P5_RXFS,
- MUX_IN_AMX_P6_DA,
- MUX_IN_AMX_P6_DB,
- MUX_IN_AMX_P6_RXCLK,
- MUX_IN_AMX_P6_RXFS,
- MUX_IN_AMX_P6_TXCLK,
- MUX_IN_AMX_P6_TXFS,
- MUX_IN_CAN1_CANRX,
- MUX_IN_CAN2_CANRX,
- MUX_IN_CCM_32K_MUXED,
- MUX_IN_CCM_PMIC_RDY,
- MUX_IN_CSPI1_SS2_B,
- MUX_IN_CSPI1_SS3_B,
- MUX_IN_CSPI2_CLK_IN,
- MUX_IN_CSPI2_DATAREADY_B,
- MUX_IN_CSPI2_MISO,
- MUX_IN_CSPI2_MOSI,
- MUX_IN_CSPI2_SS0_B,
- MUX_IN_CSPI2_SS1_B,
- MUX_IN_CSPI2_SS2_B,
- MUX_IN_CSPI2_SS3_B,
- MUX_IN_EMI_WEIM_DTACK_B,
- MUX_IN_ESDHC1_DAT4_IN,
- MUX_IN_ESDHC1_DAT5_IN,
- MUX_IN_ESDHC1_DAT6_IN,
- MUX_IN_ESDHC1_DAT7_IN,
- MUX_IN_ESDHC3_CARD_CLK_IN,
- MUX_IN_ESDHC3_CMD_IN,
- MUX_IN_ESDHC3_DAT0,
- MUX_IN_ESDHC3_DAT1,
- MUX_IN_ESDHC3_DAT2,
- MUX_IN_ESDHC3_DAT3,
- MUX_IN_GPIO1_IN_0,
- MUX_IN_GPIO1_IN_10,
- MUX_IN_GPIO1_IN_11,
- MUX_IN_GPIO1_IN_1,
- MUX_IN_GPIO1_IN_20,
- MUX_IN_GPIO1_IN_21,
- MUX_IN_GPIO1_IN_22,
- MUX_IN_GPIO1_IN_2,
- MUX_IN_GPIO1_IN_3,
- MUX_IN_GPIO1_IN_4,
- MUX_IN_GPIO1_IN_5,
- MUX_IN_GPIO1_IN_6,
- MUX_IN_GPIO1_IN_7,
- MUX_IN_GPIO1_IN_8,
- MUX_IN_GPIO1_IN_9,
- MUX_IN_GPIO2_IN_0,
- MUX_IN_GPIO2_IN_10,
- MUX_IN_GPIO2_IN_11,
- MUX_IN_GPIO2_IN_12,
- MUX_IN_GPIO2_IN_13,
- MUX_IN_GPIO2_IN_14,
- MUX_IN_GPIO2_IN_15,
- MUX_IN_GPIO2_IN_16,
- MUX_IN_GPIO2_IN_17,
- MUX_IN_GPIO2_IN_18,
- MUX_IN_GPIO2_IN_19,
- MUX_IN_GPIO2_IN_20,
- MUX_IN_GPIO2_IN_21,
- MUX_IN_GPIO2_IN_22,
- MUX_IN_GPIO2_IN_23,
- MUX_IN_GPIO2_IN_24,
- MUX_IN_GPIO2_IN_25,
- MUX_IN_GPIO2_IN_26,
- MUX_IN_GPIO2_IN_27,
- MUX_IN_GPIO2_IN_28,
- MUX_IN_GPIO2_IN_29,
- MUX_IN_GPIO2_IN_2,
- MUX_IN_GPIO2_IN_30,
- MUX_IN_GPIO2_IN_31,
- MUX_IN_GPIO2_IN_3,
- MUX_IN_GPIO2_IN_4,
- MUX_IN_GPIO2_IN_5,
- MUX_IN_GPIO2_IN_6,
- MUX_IN_GPIO2_IN_7,
- MUX_IN_GPIO2_IN_8,
- MUX_IN_GPIO2_IN_9,
- MUX_IN_GPIO3_IN_0,
- MUX_IN_GPIO3_IN_10,
- MUX_IN_GPIO3_IN_11,
- MUX_IN_GPIO3_IN_12,
- MUX_IN_GPIO3_IN_13,
- MUX_IN_GPIO3_IN_14,
- MUX_IN_GPIO3_IN_15,
- MUX_IN_GPIO3_IN_4,
- MUX_IN_GPIO3_IN_5,
- MUX_IN_GPIO3_IN_6,
- MUX_IN_GPIO3_IN_7,
- MUX_IN_GPIO3_IN_8,
- MUX_IN_GPIO3_IN_9,
- MUX_IN_I2C3_SCL_IN,
- MUX_IN_I2C3_SDA_IN,
- MUX_IN_IPU_DISPB_D0_VSYNC,
- MUX_IN_IPU_DISPB_D12_VSYNC,
- MUX_IN_IPU_DISPB_SD_D,
- MUX_IN_IPU_SENSB_DATA_0,
- MUX_IN_IPU_SENSB_DATA_1,
- MUX_IN_IPU_SENSB_DATA_2,
- MUX_IN_IPU_SENSB_DATA_3,
- MUX_IN_IPU_SENSB_DATA_4,
- MUX_IN_IPU_SENSB_DATA_5,
- MUX_IN_IPU_SENSB_DATA_6,
- MUX_IN_IPU_SENSB_DATA_7,
- MUX_IN_KPP_COL_0,
- MUX_IN_KPP_COL_1,
- MUX_IN_KPP_COL_2,
- MUX_IN_KPP_COL_3,
- MUX_IN_KPP_COL_4,
- MUX_IN_KPP_COL_5,
- MUX_IN_KPP_COL_6,
- MUX_IN_KPP_COL_7,
- MUX_IN_KPP_ROW_0,
- MUX_IN_KPP_ROW_1,
- MUX_IN_KPP_ROW_2,
- MUX_IN_KPP_ROW_3,
- MUX_IN_KPP_ROW_4,
- MUX_IN_KPP_ROW_5,
- MUX_IN_KPP_ROW_6,
- MUX_IN_KPP_ROW_7,
- MUX_IN_OWIRE_BATTERY_LINE,
- MUX_IN_SPDIF_HCKT_CLK2,
- MUX_IN_SPDIF_SPDIF_IN1,
- MUX_IN_UART3_UART_RTS_B,
- MUX_IN_UART3_UART_RXD_MUX,
- MUX_IN_USB_OTG_DATA_0,
- MUX_IN_USB_OTG_DATA_1,
- MUX_IN_USB_OTG_DATA_2,
- MUX_IN_USB_OTG_DATA_3,
- MUX_IN_USB_OTG_DATA_4,
- MUX_IN_USB_OTG_DATA_5,
- MUX_IN_USB_OTG_DATA_6,
- MUX_IN_USB_OTG_DATA_7,
- MUX_IN_USB_OTG_DIR,
- MUX_IN_USB_OTG_NXT,
- MUX_IN_USB_UH2_DATA_0,
- MUX_IN_USB_UH2_DATA_1,
- MUX_IN_USB_UH2_DATA_2,
- MUX_IN_USB_UH2_DATA_3,
- MUX_IN_USB_UH2_DATA_4,
- MUX_IN_USB_UH2_DATA_5,
- MUX_IN_USB_UH2_DATA_6,
- MUX_IN_USB_UH2_DATA_7,
- MUX_IN_USB_UH2_DIR,
- MUX_IN_USB_UH2_NXT,
- MUX_IN_USB_UH2_USB_OC,
-} iomux_input_select_t;
-
-/*!
- * various IOMUX input functions
- */
-typedef enum iomux_input_config {
- INPUT_CTL_PATH0 = 0x0,
- INPUT_CTL_PATH1,
- INPUT_CTL_PATH2,
- INPUT_CTL_PATH3,
- INPUT_CTL_PATH4,
- INPUT_CTL_PATH5,
- INPUT_CTL_PATH6,
- INPUT_CTL_PATH7,
-} iomux_input_cfg_t;
-
-/*!
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param cfg an input function as defined in \b #iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
-
-/*!
- * Release ownership for an IO pin
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param cfg an input function as defined in \b #iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
-
-/*!
- * This function enables/disables the general purpose function for a particular
- * signal.
- *
- * @param gp one signal as defined in \b #iomux_gp_func_t
- * @param en \b #true to enable; \b #false to disable
- */
-void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en);
-
-/*!
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @param config the ORed value of elements defined in \b
- * #iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
-
-/*!
- * This function configures input path.
- *
- * @param input index of input select register as defined in \b
- * #iomux_input_select_t
- * @param config the binary value of elements defined in \b
- * #iomux_input_cfg_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __ARM_ARCH_MMU_H
-#define __ARM_ARCH_MMU_H
-
-/*
- * Translation Table Base Bit Masks
- */
-#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
-
-/*
- * Domain Access Control Bit Masks
- */
-#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
-#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
-#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
-
-struct ARM_MMU_FIRST_LEVEL_FAULT {
- unsigned int id:2;
- unsigned int sbz:30;
-};
-
-#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
-
-struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
- unsigned int id:2;
- unsigned int imp:2;
- unsigned int domain:4;
- unsigned int sbz:1;
- unsigned int base_address:23;
-};
-
-#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
-
-struct ARM_MMU_FIRST_LEVEL_SECTION {
- unsigned int id:2;
- unsigned int b:1;
- unsigned int c:1;
- unsigned int imp:1;
- unsigned int domain:4;
- unsigned int sbz0:1;
- unsigned int ap:2;
- unsigned int sbz1:8;
- unsigned int base_address:12;
-};
-
-#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
-
-struct ARM_MMU_FIRST_LEVEL_RESERVED {
- unsigned int id:2;
- unsigned int sbz:30;
-};
-
-#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
-
-#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
- (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
-
-#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
-
-#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
- cacheable, bufferable, perm) \
- { \
- register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
- desc.word = 0; \
- desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
- desc.section.domain = 0; \
- desc.section.c = (cacheable); \
- desc.section.b = (bufferable); \
- desc.section.ap = (perm); \
- desc.section.base_address = (actual_base); \
- *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
- = desc.word; \
- }
-
-#define X_ARM_MMU_SECTION(abase, vbase, size, cache, buff, access) \
- { \
- int i; int j = abase; int k = vbase; \
- for (i = size; i > 0 ; i--, j++, k++) \
- ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
- }
-
-union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
- unsigned long word;
- struct ARM_MMU_FIRST_LEVEL_FAULT fault;
- struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
- struct ARM_MMU_FIRST_LEVEL_SECTION section;
- struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
-};
-
-#define ARM_UNCACHEABLE 0
-#define ARM_CACHEABLE 1
-#define ARM_UNBUFFERABLE 0
-#define ARM_BUFFERABLE 1
-
-#define ARM_ACCESS_PERM_NONE_NONE 0
-#define ARM_ACCESS_PERM_RO_NONE 0
-#define ARM_ACCESS_PERM_RO_RO 0
-#define ARM_ACCESS_PERM_RW_NONE 1
-#define ARM_ACCESS_PERM_RW_RO 2
-#define ARM_ACCESS_PERM_RW_RW 3
-
-/*
- * Initialization for the Domain Access Control Register
- */
-#define ARM_ACCESS_DACR_DEFAULT ( \
- ARM_ACCESS_TYPE_MANAGER(0) | \
- ARM_ACCESS_TYPE_NO_ACCESS(1) | \
- ARM_ACCESS_TYPE_NO_ACCESS(2) | \
- ARM_ACCESS_TYPE_NO_ACCESS(3) | \
- ARM_ACCESS_TYPE_NO_ACCESS(4) | \
- ARM_ACCESS_TYPE_NO_ACCESS(5) | \
- ARM_ACCESS_TYPE_NO_ACCESS(6) | \
- ARM_ACCESS_TYPE_NO_ACCESS(7) | \
- ARM_ACCESS_TYPE_NO_ACCESS(8) | \
- ARM_ACCESS_TYPE_NO_ACCESS(9) | \
- ARM_ACCESS_TYPE_NO_ACCESS(10) | \
- ARM_ACCESS_TYPE_NO_ACCESS(11) | \
- ARM_ACCESS_TYPE_NO_ACCESS(12) | \
- ARM_ACCESS_TYPE_NO_ACCESS(13) | \
- ARM_ACCESS_TYPE_NO_ACCESS(14) | \
- ARM_ACCESS_TYPE_NO_ACCESS(15))
-
-/*
- * Translate the virtual address of ram space to physical address
- * It is dependent on the implementation of mmu_init
- */
-inline unsigned long iomem_to_phys(unsigned long virt)
-{
- if (virt < 0x08000000)
- return (unsigned long)(virt | PHYS_SDRAM_1);
-
- if ((virt & 0xF0000000) == PHYS_SDRAM_1)
- return (unsigned long)(virt & (~0x08000000));
-
- return (unsigned long)virt;
-}
-
-/*
- * Remap the physical address of ram space to uncacheable virtual address space
- * It is dependent on the implementation of hal_mmu_init
- */
-void __iounmap(void *addr)
-{
- return;
-}
-
-void *__ioremap(unsigned long offset, size_t size, unsigned long flags)
-{
- if (1 == flags) {
- /* 0x88000000~0x87FFFFFF is uncacheable meory
- space which is mapped to SDRAM */
- if ((offset & 0xF0000000) == PHYS_SDRAM_1)
- return (void *)(offset | 0x08000000);
- else
- return NULL;
- } else
- return (void *)offset;
-}
-
-#endif
+++ /dev/null
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MX35_H
-#define __ASM_ARCH_MX35_H
-
-#define __REG(x) (*((volatile u32 *)(x)))
-#define __REG16(x) (*((volatile u16 *)(x)))
-#define __REG8(x) (*((volatile u8 *)(x)))
-
-#define L2CC_BASE_ADDR 0x30000000
-
-/*
- * AIPS 1
- */
-#define AIPS1_BASE_ADDR 0x43F00000
-#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
-#define MAX_BASE_ADDR 0x43F04000
-#define EVTMON_BASE_ADDR 0x43F08000
-#define CLKCTL_BASE_ADDR 0x43F0C000
-#define I2C_BASE_ADDR 0x43F80000
-#define I2C3_BASE_ADDR 0x43F84000
-#define ATA_BASE_ADDR 0x43F8C000
-#define UART1_BASE_ADDR 0x43F90000
-#define UART2_BASE_ADDR 0x43F94000
-#define I2C2_BASE_ADDR 0x43F98000
-#define CSPI1_BASE_ADDR 0x43FA4000
-#define IOMUXC_BASE_ADDR 0x43FAC000
-
-/*
- * SPBA
- */
-#define SPBA_BASE_ADDR 0x50000000
-#define UART3_BASE_ADDR 0x5000C000
-#define CSPI2_BASE_ADDR 0x50010000
-#define ATA_DMA_BASE_ADDR 0x50020000
-#define FEC_BASE_ADDR 0x50038000
-#define SPBA_CTRL_BASE_ADDR 0x5003C000
-
-/*
- * AIPS 2
- */
-#define AIPS2_BASE_ADDR 0x53F00000
-#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
-#define CCM_BASE_ADDR 0x53F80000
-#define GPT1_BASE_ADDR 0x53F90000
-#define EPIT1_BASE_ADDR 0x53F94000
-#define EPIT2_BASE_ADDR 0x53F98000
-#define GPIO3_BASE_ADDR 0x53FA4000
-#define MMC_SDHC1_BASE_ADDR 0x53FB4000
-#define MMC_SDHC2_BASE_ADDR 0x53FB8000
-#define MMC_SDHC3_BASE_ADDR 0x53FBC000
-#define IPU_CTRL_BASE_ADDR 0x53FC0000
-#define GPIO3_BASE_ADDR 0x53FA4000
-#define GPIO1_BASE_ADDR 0x53FCC000
-#define GPIO2_BASE_ADDR 0x53FD0000
-#define SDMA_BASE_ADDR 0x53FD4000
-#define RTC_BASE_ADDR 0x53FD8000
-#define WDOG_BASE_ADDR 0x53FDC000
-#define PWM_BASE_ADDR 0x53FE0000
-#define RTIC_BASE_ADDR 0x53FEC000
-#define IIM_BASE_ADDR 0x53FF0000
-
-/*
- * ROMPATCH and AVIC
- */
-#define ROMPATCH_BASE_ADDR 0x60000000
-#define AVIC_BASE_ADDR 0x68000000
-
-/*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
- */
-#define EXT_MEM_CTRL_BASE 0xB8000000
-#define ESDCTL_BASE_ADDR 0xB8001000
-#define WEIM_BASE_ADDR 0xB8002000
-#define WEIM_CTRL_CS0 WEIM_BASE_ADDR
-#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
-#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
-#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
-#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
-#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50)
-#define M3IF_BASE_ADDR 0xB8003000
-#define EMI_BASE_ADDR 0xB8004000
-
-#define NFC_BASE_ADDR 0xBB000000
-
-/*
- * Memory regions and CS
- */
-#define IPU_MEM_BASE_ADDR 0x70000000
-#define CSD0_BASE_ADDR 0x80000000
-#define CSD1_BASE_ADDR 0x90000000
-#define CS0_BASE_ADDR 0xA0000000
-#define CS1_BASE_ADDR 0xA8000000
-#define CS2_BASE_ADDR 0xB0000000
-#define CS3_BASE_ADDR 0xB2000000
-#define CS4_BASE_ADDR 0xB4000000
-#define CS5_BASE_ADDR 0xB6000000
-
-/*
- * IRQ Controller Register Definitions.
- */
-#define AVIC_NIMASK 0x04
-#define AVIC_INTTYPEH 0x18
-#define AVIC_INTTYPEL 0x1C
-
-/* L210 */
-#define L2CC_BASE_ADDR 0x30000000
-#define L2_CACHE_LINE_SIZE 32
-#define L2_CACHE_CTL_REG 0x100
-#define L2_CACHE_AUX_CTL_REG 0x104
-#define L2_CACHE_SYNC_REG 0x730
-#define L2_CACHE_INV_LINE_REG 0x770
-#define L2_CACHE_INV_WAY_REG 0x77C
-#define L2_CACHE_CLEAN_LINE_REG 0x7B0
-#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
-#define L2_CACHE_DBG_CTL_REG 0xF40
-
-/* CCM */
-#define CLKCTL_CCMR 0x00
-#define CLKCTL_PDR0 0x04
-#define CLKCTL_PDR1 0x08
-#define CLKCTL_PDR2 0x0C
-#define CLKCTL_PDR3 0x10
-#define CLKCTL_PDR4 0x14
-#define CLKCTL_RCSR 0x18
-#define CLKCTL_MPCTL 0x1C
-#define CLKCTL_PPCTL 0x20
-#define CLKCTL_ACMR 0x24
-#define CLKCTL_COSR 0x28
-#define CLKCTL_CGR0 0x2C
-#define CLKCTL_CGR1 0x30
-#define CLKCTL_CGR2 0x34
-#define CLKCTL_CGR3 0x38
-
-#define CLKMODE_AUTO 0
-#define CLKMODE_CONSUMER 1
-
-#define PLL_PD(x) (((x) & 0xf) << 26)
-#define PLL_MFD(x) (((x) & 0x3ff) << 16)
-#define PLL_MFI(x) (((x) & 0xf) << 10)
-#define PLL_MFN(x) (((x) & 0x3ff) << 0)
-
-#define CSCR_U(x) (WEIM_CTRL_CS#x + 0)
-#define CSCR_L(x) (WEIM_CTRL_CS#x + 4)
-#define CSCR_A(x) (WEIM_CTRL_CS#x + 8)
-
-#define IIM_SREV 0x24
-#define ROMPATCH_REV 0x40
-
-#define IPU_CONF IPU_CTRL_BASE_ADDR
-
-#define IPU_CONF_PXL_ENDIAN (1<<8)
-#define IPU_CONF_DU_EN (1<<7)
-#define IPU_CONF_DI_EN (1<<6)
-#define IPU_CONF_ADC_EN (1<<5)
-#define IPU_CONF_SDC_EN (1<<4)
-#define IPU_CONF_PF_EN (1<<3)
-#define IPU_CONF_ROT_EN (1<<2)
-#define IPU_CONF_IC_EN (1<<1)
-#define IPU_CONF_SCI_EN (1<<0)
-
-#define GPIO_PORT_NUM 3
-#define GPIO_NUM_PIN 32
-
-#define NFC_BUF_SIZE 0x1000
-#define NFC_BUFSIZE_REG_OFF (0 + 0x00)
-#define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04)
-#define NAND_FLASH_ADD_REG_OFF (0 + 0x06)
-#define NAND_FLASH_CMD_REG_OFF (0 + 0x08)
-#define NFC_CONFIGURATION_REG_OFF (0 + 0x0A)
-#define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C)
-#define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E)
-#define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10)
-#define NF_WR_PROT_REG_OFF (0 + 0x12)
-#define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18)
-#define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A)
-#define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C)
-#define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x20)
-#define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x22)
-#define RAM_BUFFER_ADDRESS_RBA_3 0x3
-#define NFC_BUFSIZE_1KB 0x0
-#define NFC_BUFSIZE_2KB 0x1
-#define NFC_CONFIGURATION_UNLOCKED 0x2
-#define ECC_STATUS_RESULT_NO_ERR 0x0
-#define ECC_STATUS_RESULT_1BIT_ERR 0x1
-#define ECC_STATUS_RESULT_2BIT_ERR 0x2
-#define NF_WR_PROT_UNLOCK 0x4
-#define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7)
-#define NAND_FLASH_CONFIG1_RST (1 << 6)
-#define NAND_FLASH_CONFIG1_BIG (1 << 5)
-#define NAND_FLASH_CONFIG1_INT_MSK (1 << 4)
-#define NAND_FLASH_CONFIG1_ECC_EN (1 << 3)
-#define NAND_FLASH_CONFIG1_SP_EN (1 << 2)
-#define NAND_FLASH_CONFIG2_INT_DONE (1 << 15)
-#define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3)
-#define NAND_FLASH_CONFIG2_FDO_ID (2 << 3)
-#define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3)
-#define NAND_FLASH_CONFIG2_FDI_EN (1 << 2)
-#define NAND_FLASH_CONFIG2_FADD_EN (1 << 1)
-#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
-#define FDO_PAGE_SPARE_VAL 0x8
-#define NAND_BUF_NUM 8
-
-#define CHIP_REV_1_0 0x10
-#define CHIP_REV_2_0 0x20
-
-#define BOARD_REV_1_0 0x0
-#define BOARD_REV_2_0 0x1
-
-#ifndef __ASSEMBLER__
-
-
-enum mxc_clock {
-MXC_ARM_CLK = 0,
-MXC_AHB_CLK,
-MXC_IPG_CLK,
-MXC_IPG_PERCLK,
-MXC_UART_CLK,
-MXC_ESDHC_CLK,
-MXC_USB_CLK,
-};
-
-enum plls {
- MCU_PLL = CCM_BASE_ADDR + CLKCTL_MPCTL,
- PER_PLL = CCM_BASE_ADDR + CLKCTL_PPCTL,
-};
-
-enum mxc_main_clocks {
- CPU_CLK,
- AHB_CLK,
- IPG_CLK,
- IPG_PER_CLK,
- NFC_CLK,
- USB_CLK,
- HSP_CLK,
-};
-
-enum mxc_peri_clocks {
- UART1_BAUD,
- UART2_BAUD,
- UART3_BAUD,
- SSI1_BAUD,
- SSI2_BAUD,
- CSI_BAUD,
- MSHC_CLK,
- ESDHC1_CLK,
- ESDHC2_CLK,
- ESDHC3_CLK,
- SPDIF_CLK,
- SPI1_CLK,
- SPI2_CLK,
-};
-/*!
- * NFMS bit in RCSR register for pagesize of nandflash
- */
-#define NFMS (*((volatile u32 *)(CCM_BASE_ADDR+0x18)))
-#define NFMS_BIT 8
-#define NFMS_NF_DWIDTH 14
-#define NFMS_NF_PG_SZ 8
-
-
-extern unsigned int mxc_get_clock(enum mxc_clock clk);
-extern unsigned int get_board_rev(void);
-extern int is_soc_rev(int rev);
-extern int sdhc_init(void);
-
-#define fixup_before_linux \
- { \
- volatile unsigned long *l2cc_ctl = (unsigned long *)0x30000100;\
- if (is_soc_rev(CHIP_REV_2_0) < 0) \
- *l2cc_ctl = 1;\
- }
-#endif /* __ASSEMBLER__*/
-#endif /* __ASM_ARCH_MX35_H */
+++ /dev/null
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_ARCH_MXC_MX35_PINS_H__
-#define __ASM_ARCH_MXC_MX35_PINS_H__
-
-/*!
- * @file arch-mxc/mx35_pins.h
- *
- * @brief MX35 I/O Pin List
- *
- * @ingroup GPIO_MX35
- */
-
-#ifndef __ASSEMBLY__
-
-/*!
- * @name IOMUX/PAD Bit field definitions
- */
-
-/*! @{ */
-
-/*!
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P | IO_I | RSVD | PAD_I | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 7 contains MUX_I used to identify the register
- * offset (base is IOMUX_module_base ) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The similar field
- * definitions are used for the pad control register.the MX35_PIN_A0 is
- * defined in the enumeration: ( 0x28 << MUX_I) |( 0x368 << PAD_I)
- * So the absolute address is: IOMUX_module_base + 0x28.
- * The pad control register offset is: 0x368.
- */
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I 0
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I 10
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * reserved filed
- */
-#define RSVD_I 21
-
-#define MUX_IO_P 29
-#define MUX_IO_I 24
-#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
- GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
- ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
-#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
-#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
-
-#define NON_GPIO_I 0x7
-#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1)
-#define NON_MUX_I PIN_TO_MUX_MASK
-
-#define _MXC_BUILD_PIN(gp, gi, mi, pi) \
- (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
- ((mi) << MUX_I) | ((pi) << PAD_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \
- _MXC_BUILD_PIN(gp, gi, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
- _MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
-
-/*! @} End IOMUX/PAD Bit field definitions */
-
-/*!
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX35 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-typedef enum iomux_pins {
- MX35_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 4, 0x4, 0x328),
- MX35_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 5, 0x8, 0x32C),
- MX35_PIN_WATCHDOG_RST = _MXC_BUILD_GPIO_PIN(0, 6, 0xC, 0x330),
- MX35_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 0x10, 0x334),
- MX35_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 0x14, 0x338),
- MX35_PIN_GPIO2_0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x18, 0x33C),
- MX35_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1C, 0x340),
- MX35_PIN_CLKO = _MXC_BUILD_GPIO_PIN(0, 8, 0x20, 0x34C),
-
- MX35_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x360),
- MX35_PIN_VSTBY = _MXC_BUILD_GPIO_PIN(0, 7, 0x24, 0x364),
- MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368),
- MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C),
- MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370),
- MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374),
- MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378),
- MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C),
- MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380),
- MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384),
- MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388),
- MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C),
- MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390),
- MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394),
- MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398),
- MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C),
- MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0),
- MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4),
- MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8),
- MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC),
- MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0),
- MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4),
- MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8),
- MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC),
- MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0),
- MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4),
- MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8),
- MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC),
- MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0),
-
- MX35_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x46C),
- MX35_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x470),
- MX35_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x474),
- MX35_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x478),
- MX35_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x47C),
- MX35_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x480),
- MX35_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x484),
- MX35_PIN_CS4 = _MXC_BUILD_GPIO_PIN(0, 20, 0xB0, 0x488),
- MX35_PIN_CS5 = _MXC_BUILD_GPIO_PIN(0, 21, 0xB4, 0x48C),
- MX35_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xB8, 0x490),
-
- MX35_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(0xBC, 0x498),
- MX35_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(0xC0, 0x49C),
- MX35_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(0xC4, 0x4A0),
-
- MX35_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(0, 18, 0xC8, 0x4CC),
- MX35_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(0, 19, 0xCC, 0x4D0),
- MX35_PIN_NFALE = _MXC_BUILD_GPIO_PIN(0, 20, 0xD0, 0x4D4),
- MX35_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(0, 21, 0xD4, 0x4D8),
- MX35_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xD8, 0x4DC),
- MX35_PIN_NFRB = _MXC_BUILD_GPIO_PIN(0, 23, 0xDC, 0x4E0),
-
- MX35_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E4),
- MX35_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E8),
- MX35_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4EC),
- MX35_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F0),
- MX35_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F4),
- MX35_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F8),
- MX35_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4FC),
- MX35_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x500),
- MX35_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x504),
- MX35_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x508),
- MX35_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x50C),
- MX35_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x510),
- MX35_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x514),
- MX35_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x518),
- MX35_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x51C),
- MX35_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x520),
-
- MX35_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 20, 0xE0, 0x524),
- MX35_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(0, 21, 0xE4, 0x528),
- MX35_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(0, 22, 0xE8, 0x52C),
- MX35_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(0, 23, 0xEC, 0x530),
- MX35_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(0, 24, 0xF0, 0x534),
- MX35_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(0, 25, 0xF4, 0x538),
- MX35_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(0, 26, 0xF8, 0x53C),
- MX35_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(0, 27, 0xFC, 0x540),
- MX35_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 28, 0x100, 0x544),
- MX35_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 29, 0x104, 0x548),
- MX35_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 30, 0x108, 0x54C),
- MX35_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 31, 0x10C, 0x550),
-
- MX35_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x110, 0x554),
- MX35_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(1, 25, 0x114, 0x558),
- MX35_PIN_I2C2_CLK = _MXC_BUILD_GPIO_PIN(1, 26, 0x118, 0x55C),
- MX35_PIN_I2C2_DAT = _MXC_BUILD_GPIO_PIN(1, 27, 0x11C, 0x560),
-
- MX35_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(1, 28, 0x120, 0x564),
- MX35_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(1, 29, 0x124, 0x568),
- MX35_PIN_SCK4 = _MXC_BUILD_GPIO_PIN(1, 30, 0x128, 0x56C),
- MX35_PIN_STXFS4 = _MXC_BUILD_GPIO_PIN(1, 31, 0x12C, 0x570),
- MX35_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 0, 0x130, 0x574),
- MX35_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 1, 0x134, 0x578),
- MX35_PIN_SCK5 = _MXC_BUILD_GPIO_PIN(0, 2, 0x138, 0x57C),
- MX35_PIN_STXFS5 = _MXC_BUILD_GPIO_PIN(0, 3, 0x13C, 0x580),
-
- MX35_PIN_SCKR = _MXC_BUILD_GPIO_PIN(0, 4, 0x140, 0x584),
- MX35_PIN_FSR = _MXC_BUILD_GPIO_PIN(0, 5, 0x144, 0x588),
- MX35_PIN_HCKR = _MXC_BUILD_GPIO_PIN(0, 6, 0x148, 0x58C),
- MX35_PIN_SCKT = _MXC_BUILD_GPIO_PIN(0, 7, 0x14C, 0x590),
- MX35_PIN_FST = _MXC_BUILD_GPIO_PIN(0, 8, 0x150, 0x594),
- MX35_PIN_HCKT = _MXC_BUILD_GPIO_PIN(0, 9, 0x154, 0x598),
- MX35_PIN_TX5_RX0 = _MXC_BUILD_GPIO_PIN(0, 10, 0x158, 0x59C),
- MX35_PIN_TX4_RX1 = _MXC_BUILD_GPIO_PIN(0, 11, 0x15C, 0x5A0),
- MX35_PIN_TX3_RX2 = _MXC_BUILD_GPIO_PIN(0, 12, 0x160, 0x5A4),
- MX35_PIN_TX2_RX3 = _MXC_BUILD_GPIO_PIN(0, 13, 0x164, 0x5A8),
- MX35_PIN_TX1 = _MXC_BUILD_GPIO_PIN(0, 14, 0x168, 0x5AC),
- MX35_PIN_TX0 = _MXC_BUILD_GPIO_PIN(0, 15, 0x16C, 0x5B0),
-
- MX35_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 16, 0x170, 0x5B4),
- MX35_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 17, 0x174, 0x5B8),
- MX35_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 18, 0x178, 0x5BC),
- MX35_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 19, 0x17C, 0x5C0),
- MX35_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(2, 4, 0x180, 0x5C4),
- MX35_PIN_CSPI1_SPI_RDY = _MXC_BUILD_GPIO_PIN(2, 5, 0x184, 0x5C8),
-
- MX35_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(2, 6, 0x188, 0x5CC),
- MX35_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(2, 7, 0x18C, 0x5D0),
- MX35_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x190, 0x5D4),
- MX35_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(2, 9, 0x194, 0x5D8),
- MX35_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(2, 10, 0x198, 0x5DC),
- MX35_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(1, 11, 0x19C, 0x5E0),
- MX35_PIN_RTS2 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1A0, 0x5E4),
- MX35_PIN_CTS2 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1A4, 0x5E8),
-
- MX35_PIN_USBOTG_PWR = _MXC_BUILD_GPIO_PIN(2, 14, 0x1A8, 0x60C),
- MX35_PIN_USBOTG_OC = _MXC_BUILD_GPIO_PIN(2, 15, 0x1AC, 0x610),
-
- MX35_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x1B0, 0x614),
- MX35_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 1, 0x1B4, 0x618),
- MX35_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 2, 0x1B8, 0x61C),
- MX35_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1BC, 0x620),
- MX35_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 4, 0x1C0, 0x624),
- MX35_PIN_LD5 = _MXC_BUILD_GPIO_PIN(1, 5, 0x1C4, 0x628),
- MX35_PIN_LD6 = _MXC_BUILD_GPIO_PIN(1, 6, 0x1C8, 0x62C),
- MX35_PIN_LD7 = _MXC_BUILD_GPIO_PIN(1, 7, 0x1CC, 0x630),
- MX35_PIN_LD8 = _MXC_BUILD_GPIO_PIN(1, 8, 0x1D0, 0x634),
- MX35_PIN_LD9 = _MXC_BUILD_GPIO_PIN(1, 9, 0x1D4, 0x638),
- MX35_PIN_LD10 = _MXC_BUILD_GPIO_PIN(1, 10, 0x1D8, 0x63C),
- MX35_PIN_LD11 = _MXC_BUILD_GPIO_PIN(1, 11, 0x1DC, 0x640),
- MX35_PIN_LD12 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1E0, 0x644),
- MX35_PIN_LD13 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1E4, 0x648),
- MX35_PIN_LD14 = _MXC_BUILD_GPIO_PIN(1, 14, 0x1E8, 0x64C),
- MX35_PIN_LD15 = _MXC_BUILD_GPIO_PIN(1, 15, 0x1EC, 0x650),
- MX35_PIN_LD16 = _MXC_BUILD_GPIO_PIN(1, 16, 0x1F0, 0x654),
- MX35_PIN_LD17 = _MXC_BUILD_GPIO_PIN(1, 17, 0x1F4, 0x658),
- MX35_PIN_LD18 = _MXC_BUILD_GPIO_PIN(2, 24, 0x1F8, 0x65C),
- MX35_PIN_LD19 = _MXC_BUILD_GPIO_PIN(2, 25, 0x1FC, 0x660),
- MX35_PIN_LD20 = _MXC_BUILD_GPIO_PIN(2, 26, 0x200, 0x664),
- MX35_PIN_LD21 = _MXC_BUILD_GPIO_PIN(2, 27, 0x204, 0x668),
- MX35_PIN_LD22 = _MXC_BUILD_GPIO_PIN(2, 28, 0x208, 0x66C),
- MX35_PIN_LD23 = _MXC_BUILD_GPIO_PIN(2, 29, 0x20C, 0x670),
-
- MX35_PIN_D3_HSYNC = _MXC_BUILD_GPIO_PIN(2, 30, 0x210, 0x674),
- MX35_PIN_D3_FPSHIFT = _MXC_BUILD_GPIO_PIN(2, 31, 0x214, 0x678),
- MX35_PIN_D3_DRDY = _MXC_BUILD_GPIO_PIN(0, 0, 0x218, 0x67C),
- MX35_PIN_CONTRAST = _MXC_BUILD_GPIO_PIN(0, 1, 0x21C, 0x680),
- MX35_PIN_D3_VSYNC = _MXC_BUILD_GPIO_PIN(0, 2, 0x220, 0x684),
- MX35_PIN_D3_REV = _MXC_BUILD_GPIO_PIN(0, 3, 0x224, 0x688),
- MX35_PIN_D3_CLS = _MXC_BUILD_GPIO_PIN(0, 4, 0x228, 0x68C),
- MX35_PIN_D3_SPL = _MXC_BUILD_GPIO_PIN(0, 5, 0x22C, 0x690),
-
- MX35_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 6, 0x230, 0x694),
- MX35_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 7, 0x234, 0x698),
- MX35_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 8, 0x238, 0x69C),
- MX35_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 9, 0x23C, 0x6A0),
- MX35_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 10, 0x240, 0x6A4),
- MX35_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 11, 0x244, 0x6A8),
- MX35_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(1, 0, 0x248, 0x6AC),
- MX35_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(1, 1, 0x24C, 0x6B0),
- MX35_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(1, 2, 0x250, 0x6B4),
- MX35_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(1, 3, 0x254, 0x6B8),
- MX35_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(1, 4, 0x258, 0x6BC),
- MX35_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(1, 5, 0x25C, 0x6C0),
-
- MX35_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(1, 6, 0x260, 0x6C4),
- MX35_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(1, 7, 0x264, 0x6C8),
- MX35_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(1, 8, 0x268, 0x6CC),
- MX35_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(1, 9, 0x26C, 0x6D0),
- MX35_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(1, 10, 0x270, 0x6D4),
- MX35_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(1, 11, 0x274, 0x6D8),
- MX35_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(1, 12, 0x278, 0x6DC),
- MX35_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 13, 0x27C, 0x6E0),
- MX35_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 14, 0x280, 0x6E4),
- MX35_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 15, 0x284, 0x6E8),
- MX35_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 16, 0x288, 0x6EC),
- MX35_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 17, 0x28C, 0x6F0),
- MX35_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 18, 0x290, 0x6F4),
- MX35_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 19, 0x294, 0x6F8),
- MX35_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 20, 0x298, 0x6FC),
- MX35_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 21, 0x29C, 0x700),
- MX35_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 22, 0x2A0, 0x704),
- MX35_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 23, 0x2A4, 0x708),
- MX35_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 24, 0x2A8, 0x70C),
- MX35_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 25, 0x2AC, 0x710),
- MX35_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 26, 0x2B0, 0x714),
- MX35_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 27, 0x2B4, 0x718),
- MX35_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 28, 0x2B8, 0x71C),
- MX35_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(1, 29, 0x2BC, 0x720),
- MX35_PIN_ATA_BUFF_EN = _MXC_BUILD_GPIO_PIN(1, 30, 0x2C0, 0x724),
- MX35_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(1, 31, 0x2C4, 0x728),
- MX35_PIN_ATA_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 0x2C8, 0x72C),
- MX35_PIN_ATA_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 0x2CC, 0x730),
- MX35_PIN_ATA_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 0x2D0, 0x734),
-
- MX35_PIN_MLB_CLK = _MXC_BUILD_GPIO_PIN(2, 3, 0x2D4, 0x738),
- MX35_PIN_MLB_DAT = _MXC_BUILD_GPIO_PIN(2, 4, 0x2D8, 0x73C),
- MX35_PIN_MLB_SIG = _MXC_BUILD_GPIO_PIN(2, 5, 0x2DC, 0x740),
-
- MX35_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 6, 0x2E0, 0x744),
- MX35_PIN_FEC_RX_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 0x2E4, 0x748),
- MX35_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 8, 0x2E8, 0x74C),
- MX35_PIN_FEC_COL = _MXC_BUILD_GPIO_PIN(2, 9, 0x2EC, 0x750),
- MX35_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x2F0, 0x754),
- MX35_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 11, 0x2F4, 0x758),
- MX35_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 12, 0x2F8, 0x75C),
- MX35_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 13, 0x2FC, 0x760),
- MX35_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 14, 0x300, 0x764),
- MX35_PIN_FEC_TX_ERR = _MXC_BUILD_GPIO_PIN(2, 15, 0x304, 0x768),
- MX35_PIN_FEC_RX_ERR = _MXC_BUILD_GPIO_PIN(2, 16, 0x308, 0x76C),
- MX35_PIN_FEC_CRS = _MXC_BUILD_GPIO_PIN(2, 17, 0x30C, 0x770),
- MX35_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 18, 0x310, 0x774),
- MX35_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 19, 0x314, 0x778),
- MX35_PIN_FEC_RDATA2 = _MXC_BUILD_GPIO_PIN(2, 20, 0x318, 0x77C),
- MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780),
- MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784),
- MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788),
-} iomux_pin_name_t;
-
-#endif
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/*!
- * @file mxc_nd2.h
- *
- * @brief This file contains the NAND Flash Controller register information.
- *
- *
- * @ingroup NAND_MTD
- */
-
-#ifndef __MXC_NAND_H__
-#define __MXC_NAND_H__
-
-#include <asm/arch/mx35.h>
-
-#define IS_2K_PAGE_NAND ((mtd->writesize / info->num_of_intlv) \
- == NAND_PAGESIZE_2KB)
-#define IS_4K_PAGE_NAND ((mtd->writesize / info->num_of_intlv) \
- == NAND_PAGESIZE_4KB)
-#define IS_LARGE_PAGE_NAND ((mtd->writesize / info->num_of_intlv) > 512)
-
-#define GET_NAND_OOB_SIZE (mtd->oobsize / info->num_of_intlv)
-#define GET_NAND_PAGE_SIZE (mtd->writesize / info->num_of_intlv)
-
-#define NAND_PAGESIZE_2KB 2048
-#define NAND_PAGESIZE_4KB 4096
-
-/*
- * main area for bad block marker is in the last data section
- * the spare area for swapped bad block marker is the second
- * byte of last spare section
- */
-#define NAND_SECTIONS (GET_NAND_PAGE_SIZE >> 9)
-#define NAND_OOB_PER_SECTION (((GET_NAND_OOB_SIZE / NAND_SECTIONS) >> 1) << 1)
-#define NAND_CHUNKS (GET_NAND_PAGE_SIZE / (512 + NAND_OOB_PER_SECTION))
-
-#define BAD_BLK_MARKER_MAIN_OFFS \
- (GET_NAND_PAGE_SIZE - NAND_CHUNKS * NAND_OOB_PER_SECTION)
-
-#define BAD_BLK_MARKER_SP_OFFS (NAND_CHUNKS * SPARE_LEN)
-
-#define BAD_BLK_MARKER_OOB_OFFS (NAND_CHUNKS * NAND_OOB_PER_SECTION)
-
-#define BAD_BLK_MARKER_MAIN \
- ((u32)MAIN_AREA0 + BAD_BLK_MARKER_MAIN_OFFS)
-
-#define BAD_BLK_MARKER_SP \
- ((u32)SPARE_AREA0 + BAD_BLK_MARKER_SP_OFFS)
-
-
-/*
- * Addresses for NFC registers
- */
-#define NFC_REG_BASE (NFC_BASE_ADDR + 0x1000)
-#define NFC_BUF_ADDR (NFC_REG_BASE + 0xE04)
-#define NFC_FLASH_ADDR (NFC_REG_BASE + 0xE06)
-#define NFC_FLASH_CMD (NFC_REG_BASE + 0xE08)
-#define NFC_CONFIG (NFC_REG_BASE + 0xE0A)
-#define NFC_ECC_STATUS_RESULT (NFC_REG_BASE + 0xE0C)
-#define NFC_SPAS (NFC_REG_BASE + 0xE10)
-#define NFC_WRPROT (NFC_REG_BASE + 0xE12)
-#define NFC_UNLOCKSTART_BLKADDR (NFC_REG_BASE + 0xE20)
-#define NFC_UNLOCKEND_BLKADDR (NFC_REG_BASE + 0xE22)
-#define NFC_CONFIG1 (NFC_REG_BASE + 0xE1A)
-#define NFC_CONFIG2 (NFC_REG_BASE + 0xE1C)
-
-/*!
- * Addresses for NFC RAM BUFFER Main area 0
- */
-#define MAIN_AREA0 (u16 *)(NFC_BASE_ADDR + 0x000)
-#define MAIN_AREA1 (u16 *)(NFC_BASE_ADDR + 0x200)
-
-/*!
- * Addresses for NFC SPARE BUFFER Spare area 0
- */
-#define SPARE_AREA0 (u16 *)(NFC_BASE_ADDR + 0x1000)
-#define SPARE_LEN 64
-#define SPARE_COUNT 8
-#define SPARE_SIZE (SPARE_LEN * SPARE_COUNT)
-
-
-#define SPAS_SHIFT (0)
-#define SPAS_MASK (0xFF00)
-#define IS_4BIT_ECC \
- ((raw_read(REG_NFC_ECC_MODE) & NFC_ECC_MODE_4) >> 0)
-
-#define NFC_SET_SPAS(v) \
- raw_write(((raw_read(REG_NFC_SPAS) & SPAS_MASK) | \
- ((v<<SPAS_SHIFT))), \
- REG_NFC_SPAS)
-
-#define NFC_SET_ECC_MODE(v) \
-do { \
- if ((v) == NFC_SPAS_218) { \
- raw_write((raw_read(REG_NFC_ECC_MODE) & \
- NFC_ECC_MODE_8), \
- REG_NFC_ECC_MODE); \
- } else { \
- raw_write((raw_read(REG_NFC_ECC_MODE) | \
- NFC_ECC_MODE_4), \
- REG_NFC_ECC_MODE); \
- } \
-} while (0)
-
-#define GET_ECC_STATUS() \
- __raw_readl(REG_NFC_ECC_STATUS_RESULT);
-
-#define NFC_SET_NFMS(v) \
-do { \
- if (((v) & (1 << NFMS_NF_PG_SZ))) { \
- if (IS_2K_PAGE_NAND) { \
- (NFMS |= 0x00000100); \
- (NFMS &= ~0x00000200); \
- NFC_SET_SPAS(NFC_SPAS_64); \
- } else if (IS_4K_PAGE_NAND) { \
- (NFMS &= ~0x00000100); \
- (NFMS |= 0x00000200); \
- GET_NAND_OOB_SIZE == 128 ? \
- NFC_SET_SPAS(NFC_SPAS_128) : \
- NFC_SET_SPAS(NFC_SPAS_218); \
- } else { \
- printk(KERN_ERR "Err for setting page/oob size"); \
- } \
- NFC_SET_ECC_MODE(GET_NAND_OOB_SIZE >> 1); \
- } \
-} while (0)
-
-
-#define WRITE_NFC_IP_REG(val, reg) \
- raw_write((raw_read(REG_NFC_OPS_STAT) & ~NFC_OPS_STAT), \
- REG_NFC_OPS_STAT)
-
-#define GET_NFC_ECC_STATUS() \
- raw_read(REG_NFC_ECC_STATUS_RESULT);
-
-/*!
- * Set INT to 0, Set 1 to specific operation bit, rest to 0 in LAUNCH_NFC Register for
- * Specific operation
- */
-#define NFC_CMD 0x1
-#define NFC_ADDR 0x2
-#define NFC_INPUT 0x4
-#define NFC_OUTPUT 0x8
-#define NFC_ID 0x10
-#define NFC_STATUS 0x20
-
-/* Bit Definitions */
-#define NFC_OPS_STAT (1 << 15)
-#define NFC_SP_EN (1 << 2)
-#define NFC_ECC_EN (1 << 3)
-#define NFC_INT_MSK (1 << 4)
-#define NFC_BIG (1 << 5)
-#define NFC_RST (1 << 6)
-#define NFC_CE (1 << 7)
-#define NFC_ONE_CYCLE (1 << 8)
-#define NFC_BLS_LOCKED 0
-#define NFC_BLS_LOCKED_DEFAULT 1
-#define NFC_BLS_UNLCOKED 2
-#define NFC_WPC_LOCK_TIGHT 1
-#define NFC_WPC_LOCK (1 << 1)
-#define NFC_WPC_UNLOCK (1 << 2)
-#define NFC_FLASH_ADDR_SHIFT 0
-#define NFC_UNLOCK_END_ADDR_SHIFT 0
-
-#define NFC_ECC_MODE_4 (1<<0)
-#define NFC_ECC_MODE_8 (~(1<<0))
-#define NFC_SPAS_16 8
-#define NFC_SPAS_64 32
-#define NFC_SPAS_128 64
-#define NFC_SPAS_218 109
-
-/* NFC Register Mapping */
-#define REG_NFC_OPS_STAT NFC_CONFIG2
-#define REG_NFC_INTRRUPT NFC_CONFIG1
-#define REG_NFC_FLASH_ADDR NFC_FLASH_ADDR
-#define REG_NFC_FLASH_CMD NFC_FLASH_CMD
-#define REG_NFC_OPS NFC_CONFIG2
-#define REG_NFC_SET_RBA NFC_BUF_ADDR
-#define REG_NFC_ECC_EN NFC_CONFIG1
-#define REG_NFC_ECC_STATUS_RESULT NFC_ECC_STATUS_RESULT
-#define REG_NFC_CE NFC_CONFIG1
-#define REG_NFC_SP_EN NFC_CONFIG1
-#define REG_NFC_BLS NFC_CONFIG
-#define REG_NFC_WPC NFC_WRPROT
-#define REG_START_BLKADDR NFC_UNLOCKSTART_BLKADDR
-#define REG_END_BLKADDR NFC_UNLOCKEND_BLKADDR
-#define REG_NFC_RST NFC_CONFIG1
-#define REG_NFC_ECC_MODE NFC_CONFIG1
-#define REG_NFC_SPAS NFC_SPAS
-
-
-/* NFC V1/V2 Specific MACRO functions definitions */
-
-#define raw_write(v, a) __raw_writew(v, a)
-#define raw_read(a) __raw_readw(a)
-
-#define NFC_SET_BLS(val) val
-
-#define UNLOCK_ADDR(start_addr, end_addr) \
-{ \
- raw_write(start_addr, REG_START_BLKADDR); \
- raw_write(end_addr, REG_END_BLKADDR); \
-}
-
-#define NFC_SET_NFC_ACTIVE_CS(val)
-#define NFC_SET_WPC(val) val
-
-/* NULL Definitions */
-#define ACK_OPS
-#define NFC_SET_RBA(val) raw_write(val, REG_NFC_SET_RBA);
-
-#define READ_PAGE() send_read_page(0)
-#define PROG_PAGE() send_prog_page(0)
-#define CHECK_NFC_RB 1
-
-#endif /* __MXC_NAND_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _IMX_SPI_PMIC_H_
-#define _IMX_SPI_PMIC_H_
-
-#include <linux/types.h>
-
-extern struct spi_slave *spi_pmic_probe(void);
-extern void spi_pmic_free(struct spi_slave *slave);
-extern u32 pmic_reg(struct spi_slave *slave,
- u32 reg, u32 val, u32 write);
-
-#endif /* _IMX_SPI_PMIC_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __MACH_MX50_IOMUX_H__
-#define __MACH_MX50_IOMUX_H__
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mx50.h>
-#include <asm/arch/mx50_pins.h>
-
-typedef unsigned int iomux_pin_name_t;
-
-/* various IOMUX output functions */
-typedef enum iomux_config {
- IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */
- IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */
- IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */
- IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */
- IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */
- IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */
- IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */
- IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */
- IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */
- IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
-} iomux_pin_cfg_t;
-
-/* various IOMUX pad functions */
-typedef enum iomux_pad_config {
- PAD_CTL_SRE_SLOW = 0x0 << 0,
- PAD_CTL_SRE_FAST = 0x1 << 0,
- PAD_CTL_DRV_LOW = 0x0 << 1,
- PAD_CTL_DRV_MEDIUM = 0x1 << 1,
- PAD_CTL_DRV_HIGH = 0x2 << 1,
- PAD_CTL_DRV_MAX = 0x3 << 1,
- PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,
- PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,
- PAD_CTL_100K_PD = 0x0 << 4,
- PAD_CTL_47K_PU = 0x1 << 4,
- PAD_CTL_100K_PU = 0x2 << 4,
- PAD_CTL_22K_PU = 0x3 << 4,
- PAD_CTL_PUE_KEEPER = 0x0 << 6,
- PAD_CTL_PUE_PULL = 0x1 << 6,
- PAD_CTL_PKE_NONE = 0x0 << 7,
- PAD_CTL_PKE_ENABLE = 0x1 << 7,
- PAD_CTL_HYS_NONE = 0x0 << 8,
- PAD_CTL_HYS_ENABLE = 0x1 << 8,
- PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,
- PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,
- PAD_CTL_DRV_VOT_LOW = 0x0 << 13,
- PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,
-} iomux_pad_config_t;
-
-/* various IOMUX input select register index */
-typedef enum iomux_input_select {
- MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
- MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
- MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
- MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
- MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
- MUX_IN_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_DATAREADY_B_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS1_B_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS2_B_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS3_B_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_BUSY_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_RXDATA_0_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_RXDATA_1_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_RXDATA_2_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_RXDATA_3_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_RXDATA_4_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_RXDATA_5_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_RXDATA_6_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_RXDATA_7_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_RXDATA_8_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_RXDATA_9_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_RXDATA_10_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_RXDATA_11_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_RXDATA_12_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_RXDATA_13_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_RXDATA_14_SELECT_INPUT,
- MUX_IN_ELCDIF_LCDIF_RXDATA_15_SELECT_INPUT,
- MUX_IN_ELCDIF_VSYNC_I_SELECT_INPUT,
- MUX_IN_ESDHC2_IPP_CARD_DET_SELECT_INPUT,
- MUX_IN_ESDHC2_IPP_WP_ON_SELECT_INPUT,
- MUX_IN_ESDHC4_IPP_CARD_CLK_IN_SELECT_INPUT,
- MUX_IN_ESDHC4_IPP_CMD_IN_SELECT_INPUT,
- MUX_IN_ESDHC4_IPP_DAT0_IN_SELECT_INPUT,
- MUX_IN_ESDHC4_IPP_DAT1_IN_SELECT_INPUT,
- MUX_IN_ESDHC4_IPP_DAT2_IN_SELECT_INPUT,
- MUX_IN_ESDHC4_IPP_DAT3_IN_SELECT_INPUT,
- MUX_IN_ESDHC4_IPP_DAT4_IN_SELECT_INPUT,
- MUX_IN_ESDHC4_IPP_DAT5_IN_SELECT_INPUT,
- MUX_IN_ESDHC4_IPP_DAT6_IN_SELECT_INPUT,
- MUX_IN_ESDHC4_IPP_DAT7_IN_SELECT_INPUT,
- MUX_IN_FEC_FEC_COL_SELECT_INPUT,
- MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
- MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
- MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
- MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
- MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_COL_4_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_COL_5_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
- MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT,
- MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_RDY0_IN_SELECT_INPUT,
- MUX_IN_SDMA_EVENTS_14_SELECT_INPUT,
- MUX_IN_SDMA_EVENTS_15_SELECT_INPUT,
- MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_UART4_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_UART5_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_USBOH1_IPP_IND_OTG_OC_SELECT_INPUT,
- MUX_IN_WEIMV2_IPP_IND_READ_DATA_0_SELECT_INPUT,
- MUX_IN_WEIMV2_IPP_IND_READ_DATA_1_SELECT_INPUT,
- MUX_IN_WEIMV2_IPP_IND_READ_DATA_2_SELECT_INPUT,
- MUX_IN_WEIMV2_IPP_IND_READ_DATA_3_SELECT_INPUT,
- MUX_IN_WEIMV2_IPP_IND_READ_DATA_4_SELECT_INPUT,
- MUX_IN_WEIMV2_IPP_IND_READ_DATA_5_SELECT_INPUT,
- MUX_IN_WEIMV2_IPP_IND_READ_DATA_6_SELECT_INPUT,
- MUX_IN_WEIMV2_IPP_IND_READ_DATA_7_SELECT_INPUT,
- MUX_IN_WEIMV2_IPP_IND_READ_DATA_8_SELECT_INPUT,
- MUX_IN_WEIMV2_IPP_IND_READ_DATA_9_SELECT_INPUT,
- MUX_IN_WEIMV2_IPP_IND_READ_DATA_10_SELECT_INPUT,
- MUX_IN_WEIMV2_IPP_IND_READ_DATA_11_SELECT_INPUT,
- MUX_IN_WEIMV2_IPP_IND_READ_DATA_12_SELECT_INPUT,
- MUX_IN_WEIMV2_IPP_IND_READ_DATA_13_SELECT_INPUT,
- MUX_IN_WEIMV2_IPP_IND_READ_DATA_14_SELECT_INPUT,
- MUX_IN_WEIMV2_IPP_IND_READ_DATA_15_SELECT_INPUT,
- MUX_INPUT_NUM_MUX,
-} iomux_input_select_t;
-
-/* various IOMUX input functions */
-typedef enum iomux_input_config {
- INPUT_CTL_PATH0 = 0x0,
- INPUT_CTL_PATH1,
- INPUT_CTL_PATH2,
- INPUT_CTL_PATH3,
- INPUT_CTL_PATH4,
- INPUT_CTL_PATH5,
- INPUT_CTL_PATH6,
- INPUT_CTL_PATH7,
-} iomux_input_config_t;
-
-struct mxc_iomux_pin_cfg {
- iomux_pin_name_t pin;
- u8 mux_mode;
- u16 pad_cfg;
- u8 in_select;
- u8 in_mode;
-};
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param config config as defined in \b #iomux_pin_ocfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-
-/*
- * Release ownership for an IO pin
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param config config as defined in \b #iomux_pin_ocfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @param config the ORed value of elements defined in
- * \b #iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
-
-/*
- * This function gets the current pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @return current pad value
- */
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
-
-/*
- * This function configures input path.
- *
- * @param input index of input select register as defined in
- * \b #iomux_input_select_t
- * @param config the binary value of elements defined in \b #iomux_input_config_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-
-#endif /* __MACH_MX50_IOMUX_H__ */
+++ /dev/null
-/*
- * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __ARM_ARCH_MMU_H
-#define __ARM_ARCH_MMU_H
-
-#include <linux/types.h>
-
-/*
- * Translation Table Base Bit Masks
- */
-#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
-
-/*
- * Domain Access Control Bit Masks
- */
-#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
-#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
-#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
-
-struct ARM_MMU_FIRST_LEVEL_FAULT {
- unsigned int id:2;
- unsigned int sbz:30;
-};
-
-#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
-
-struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
- unsigned int id:2;
- unsigned int imp:2;
- unsigned int domain:4;
- unsigned int sbz:1;
- unsigned int base_address:23;
-};
-
-#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
-
-struct ARM_MMU_FIRST_LEVEL_SECTION {
- unsigned int id:2;
- unsigned int b:1;
- unsigned int c:1;
- unsigned int imp:1;
- unsigned int domain:4;
- unsigned int sbz0:1;
- unsigned int ap:2;
- unsigned int sbz1:8;
- unsigned int base_address:12;
-};
-
-#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
-
-struct ARM_MMU_FIRST_LEVEL_RESERVED {
- unsigned int id:2;
- unsigned int sbz:30;
-};
-
-#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
-
-#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
- (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
-
-#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
-
-#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
- cacheable, bufferable, perm) \
- { \
- register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
- desc.word = 0; \
- desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
- desc.section.domain = 0; \
- desc.section.c = (cacheable); \
- desc.section.b = (bufferable); \
- desc.section.ap = (perm); \
- desc.section.base_address = (actual_base); \
- *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
- = desc.word; \
- }
-
-#define X_ARM_MMU_SECTION(abase, vbase, size, cache, buff, access) \
- { \
- int i; int j = abase; int k = vbase; \
- for (i = size; i > 0 ; i--, j++, k++) \
- ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
- }
-
-union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
- unsigned long word;
- struct ARM_MMU_FIRST_LEVEL_FAULT fault;
- struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
- struct ARM_MMU_FIRST_LEVEL_SECTION section;
- struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
-};
-
-#define ARM_UNCACHEABLE 0
-#define ARM_CACHEABLE 1
-#define ARM_UNBUFFERABLE 0
-#define ARM_BUFFERABLE 1
-
-#define ARM_ACCESS_PERM_NONE_NONE 0
-#define ARM_ACCESS_PERM_RO_NONE 0
-#define ARM_ACCESS_PERM_RO_RO 0
-#define ARM_ACCESS_PERM_RW_NONE 1
-#define ARM_ACCESS_PERM_RW_RO 2
-#define ARM_ACCESS_PERM_RW_RW 3
-
-/*
- * Initialization for the Domain Access Control Register
- */
-#define ARM_ACCESS_DACR_DEFAULT ( \
- ARM_ACCESS_TYPE_MANAGER(0) | \
- ARM_ACCESS_TYPE_NO_ACCESS(1) | \
- ARM_ACCESS_TYPE_NO_ACCESS(2) | \
- ARM_ACCESS_TYPE_NO_ACCESS(3) | \
- ARM_ACCESS_TYPE_NO_ACCESS(4) | \
- ARM_ACCESS_TYPE_NO_ACCESS(5) | \
- ARM_ACCESS_TYPE_NO_ACCESS(6) | \
- ARM_ACCESS_TYPE_NO_ACCESS(7) | \
- ARM_ACCESS_TYPE_NO_ACCESS(8) | \
- ARM_ACCESS_TYPE_NO_ACCESS(9) | \
- ARM_ACCESS_TYPE_NO_ACCESS(10) | \
- ARM_ACCESS_TYPE_NO_ACCESS(11) | \
- ARM_ACCESS_TYPE_NO_ACCESS(12) | \
- ARM_ACCESS_TYPE_NO_ACCESS(13) | \
- ARM_ACCESS_TYPE_NO_ACCESS(14) | \
- ARM_ACCESS_TYPE_NO_ACCESS(15))
-
-/*
- * Translate the virtual address of ram space to physical address
- * It is dependent on the implementation of mmu_init
- */
-inline void *iomem_to_phys(unsigned long virt)
-{
- if (virt >= 0xB0000000)
- return (void *)((virt - 0xB0000000) + PHYS_SDRAM_1);
-
- return (void *)virt;
-}
-
-/*
- * remap the physical address of ram space to uncacheable virtual address space
- * It is dependent on the implementation of hal_mmu_init
- */
-void *__ioremap(unsigned long offset, size_t size, unsigned long flags)
-{
- if (1 == flags) {
- if (offset >= PHYS_SDRAM_1 &&
- offset < (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
- return (void *)(offset - PHYS_SDRAM_1) + 0xB0000000;
- else
- return NULL;
- } else
- return (void *)offset;
-}
-
-/*
- * Remap the physical address of ram space to uncacheable virtual address space
- * It is dependent on the implementation of hal_mmu_init
- */
-void __iounmap(void *addr)
-{
- return;
-}
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __ASM_ARCH_MXC_MX50_H__
-#define __ASM_ARCH_MXC_MX50_H__
-
-#define __REG(x) (*((volatile u32 *)(x)))
-#define __REG16(x) (*((volatile u16 *)(x)))
-#define __REG8(x) (*((volatile u8 *)(x)))
-
- /*
- * IRAM
- */
-#define IRAM_BASE_ADDR 0xF8000000 /* internal ram */
-#define IRAM_PARTITIONS 16
-#define IRAM_SIZE (IRAM_PARTITIONS*SZ_8K) /* 128KB */
-
-#define TZIC_BASE_ADDR 0x0FFFC000
-#define DATABAHN_BASE_ADDR 0x14000000
-
-#define DEBUG_BASE_ADDR 0x40000000
-#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
-#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
-#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
-#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
-#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
-#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
-#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
-#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
-#define OCOTP_CTRL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01002000)
-#define EPDC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01010000)
-
-/*
- * SPBA global module enabled #0
- */
-#define SPBA0_BASE_ADDR 0x50000000
-
-#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
-#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
-#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
-#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
-#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
-#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
-#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
-
-/*
- * defines for SPBA modules
- */
-#define SPBA_SDHC1 0x04
-#define SPBA_SDHC2 0x08
-#define SPBA_UART3 0x0C
-#define SPBA_CSPI1 0x10
-#define SPBA_SSI2 0x14
-#define SPBA_ESAI 0x18
-#define SPBA_SDHC3 0x20
-#define SPBA_SDHC4 0x24
-#define SPBA_SPDIF 0x28
-#define SPBA_ASRC 0x2C
-#define SPBA_ATA 0x30
-#define SPBA_CTRL 0x3C
-
-/*
- * AIPS 1
- */
-#define AIPS1_BASE_ADDR 0x53F00000
-
-#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
-#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
-#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
-#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
-#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
-#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
-#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
-#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
-#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
-#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
-#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
-#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
-#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
-#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
-#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
-#define USBOH1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C4000)
-#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
-#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
-#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
-#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
-#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
-#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
-#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E8000)
-#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
-#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
-#define MSHC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F4000)
-#define RNGB_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F8000)
-
-/*
- * AIPS 2
- */
-#define AIPS2_BASE_ADDR 0x63F00000
-
-#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
-#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
-#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
-#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
-#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
-#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
-#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
-#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
-#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
-#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
-#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
-#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
-#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
-#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
-#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
-#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
-#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
-#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
-#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
-#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
-#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
-
-/*
- * Some of i.MX50 SoC registers are associated with four addresses
- * used for different operations - read/write, set, clear and toggle bits.
- *
- * Some of registers do not implement such feature and, thus, should be
- * accessed/manipulated via single address in common way.
- */
-#define REG_RD(base, reg) \
- (*(volatile unsigned int *)((base) + (reg)))
-#define REG_WR(base, reg, value) \
- ((*(volatile unsigned int *)((base) + (reg))) = (value))
-#define REG_SET(base, reg, value) \
- ((*(volatile unsigned int *)((base) + (reg ## _SET))) = (value))
-#define REG_CLR(base, reg, value) \
- ((*(volatile unsigned int *)((base) + (reg ## _CLR))) = (value))
-#define REG_TOG(base, reg, value) \
- ((*(volatile unsigned int *)((base) + (reg ## _TOG))) = (value))
-
-#define REG_RD_ADDR(addr) \
- (*(volatile unsigned int *)((addr)))
-#define REG_WR_ADDR(addr, value) \
- ((*(volatile unsigned int *)((addr))) = (value))
-#define REG_SET_ADDR(addr, value) \
- ((*(volatile unsigned int *)((addr) + 0x4)) = (value))
-#define REG_CLR_ADDR(addr, value) \
- ((*(volatile unsigned int *)((addr) + 0x8)) = (value))
-#define REG_TOG_ADDR(addr, value) \
- ((*(volatile unsigned int *)((addr) + 0xc)) = (value))
-
-/*
- * Memory regions and CS
- */
-#define CSD0_BASE_ADDR 0x70000000
-#define CSD1_BASE_ADDR 0xB0000000
-
-/* gpio and gpio based interrupt handling */
-#define GPIO_DR 0x00
-#define GPIO_GDIR 0x04
-#define GPIO_PSR 0x08
-#define GPIO_ICR1 0x0C
-#define GPIO_ICR2 0x10
-#define GPIO_IMR 0x14
-#define GPIO_ISR 0x18
-#define GPIO_INT_LOW_LEV 0x0
-#define GPIO_INT_HIGH_LEV 0x1
-#define GPIO_INT_RISE_EDGE 0x2
-#define GPIO_INT_FALL_EDGE 0x3
-#define GPIO_INT_NONE 0x4
-
-#define CLKCTL_CCR 0x00
-#define CLKCTL_CCDR 0x04
-#define CLKCTL_CSR 0x08
-#define CLKCTL_CCSR 0x0C
-#define CLKCTL_CACRR 0x10
-#define CLKCTL_CBCDR 0x14
-#define CLKCTL_CBCMR 0x18
-#define CLKCTL_CSCMR1 0x1C
-#define CLKCTL_CSCMR2 0x20
-#define CLKCTL_CSCDR1 0x24
-#define CLKCTL_CS1CDR 0x28
-#define CLKCTL_CS2CDR 0x2C
-#define CLKCTL_CDCDR 0x30
-#define CLKCTL_CHSCDR 0x34
-#define CLKCTL_CSCDR2 0x38
-#define CLKCTL_CSCDR3 0x3C
-#define CLKCTL_CSCDR4 0x40
-#define CLKCTL_CWDR 0x44
-#define CLKCTL_CDHIPR 0x48
-#define CLKCTL_CDCR 0x4C
-#define CLKCTL_CTOR 0x50
-#define CLKCTL_CLPCR 0x54
-#define CLKCTL_CISR 0x58
-#define CLKCTL_CIMR 0x5C
-#define CLKCTL_CCOSR 0x60
-#define CLKCTL_CGPR 0x64
-#define CLKCTL_CCGR0 0x68
-#define CLKCTL_CCGR1 0x6C
-#define CLKCTL_CCGR2 0x70
-#define CLKCTL_CCGR3 0x74
-#define CLKCTL_CCGR4 0x78
-#define CLKCTL_CCGR5 0x7C
-#define CLKCTL_CCGR6 0x80
-#define CLKCTL_CCGR7 0x84
-#define CLKCTL_CMEOR 0x88
-
-#define CLKCTL_CSR2 0x8C
-#define CLKCTL_CLKSEQ_BYPASS 0x90
-#define CLKCTL_CLK_SYS 0x94
-#define CLKCTL_CLK_DDR 0x98
-
-#define CHIP_REV_1_0 0x10
-#define PLATFORM_ICGC 0x14
-
-/* Assuming 24MHz input clock with doubler ON */
-/* MFI PDF */
-#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
-#define DP_MFD_850 (48 - 1)
-#define DP_MFN_850 41
-
-#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
-#define DP_MFD_800 (3 - 1)
-#define DP_MFN_800 1
-
-#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
-#define DP_MFD_700 (24 - 1)
-#define DP_MFN_700 7
-
-#define DP_OP_600 ((6 << 4) + ((1 - 1) << 0))
-#define DP_MFD_600 (4 - 1)
-#define DP_MFN_600 1
-
-#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
-#define DP_MFD_665 (96 - 1)
-#define DP_MFN_665 89
-
-#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
-#define DP_MFD_532 (24 - 1)
-#define DP_MFN_532 13
-
-#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
-#define DP_MFD_400 (3 - 1)
-#define DP_MFN_400 1
-
-#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
-#define DP_MFD_216 (4 - 1)
-#define DP_MFN_216 3
-
-#define PLL_DP_CTL 0x00
-#define PLL_DP_CONFIG 0x04
-#define PLL_DP_OP 0x08
-#define PLL_DP_MFD 0x0C
-#define PLL_DP_MFN 0x10
-#define PLL_DP_MFNMINUS 0x14
-#define PLL_DP_MFNPLUS 0x18
-#define PLL_DP_HFS_OP 0x1C
-#define PLL_DP_HFS_MFD 0x20
-#define PLL_DP_HFS_MFN 0x24
-#define PLL_DP_TOGC 0x28
-#define PLL_DP_DESTAT 0x2C
-
-#ifndef __ASSEMBLER__
-
-enum boot_device {
- WEIM_NOR_BOOT,
- ONE_NAND_BOOT,
- PATA_BOOT,
- SATA_BOOT,
- I2C_BOOT,
- SPI_NOR_BOOT,
- SD_BOOT,
- MMC_BOOT,
- NAND_BOOT,
- UNKNOWN_BOOT
-};
-
-enum mxc_clock {
- MXC_ARM_CLK = 0,
- MXC_PER_CLK,
- MXC_AHB_CLK,
- MXC_IPG_CLK,
- MXC_IPG_PERCLK,
- MXC_UART_CLK,
- MXC_CSPI_CLK,
- MXC_AXI_A_CLK,
- MXC_AXI_B_CLK,
- MXC_EMI_SLOW_CLK,
- MXC_DDR_CLK,
- MXC_ESDHC_CLK,
- MXC_ESDHC2_CLK,
- MXC_ESDHC3_CLK,
- MXC_ESDHC4_CLK,
-};
-
-enum mxc_peri_clocks {
- MXC_UART1_BAUD,
- MXC_UART2_BAUD,
- MXC_UART3_BAUD,
- MXC_SSI1_BAUD,
- MXC_SSI2_BAUD,
- MXC_CSI_BAUD,
- MXC_MSTICK1_CLK,
- MXC_MSTICK2_CLK,
- MXC_SPI1_CLK,
- MXC_SPI2_CLK,
-};
-
-extern unsigned int mxc_get_clock(enum mxc_clock clk);
-extern unsigned int get_board_rev(void);
-extern int is_soc_rev(int rev);
-extern enum boot_device get_boot_device(void);
-
-#endif /* __ASSEMBLER__*/
-
-#endif /* __ASM_ARCH_MXC_MX50_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#ifndef __ASM_ARCH_MXC_MX50_PINS_H__
-#define __ASM_ARCH_MXC_MX50_PINS_H__
-
-#ifndef __ASSEMBLY__
-
-/*
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P | IO_I | GPIO_I | PAD_I | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 9 contains MUX_I used to identify the register
- * offset (0-based. base is IOMUX_module_base) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
- * similar field definitions are used for the pad control register.
- * For example, the MX50_PIN_GPIO_19 is defined in the enumeration:
- * ( (0x20 - MUX_I_START) << MUX_I)|( (0x348 - PAD_I_START) << PAD_I)
- * It means the mux control register is at register offset 0x20. The pad control
- * register offset is: 0x348 and also occupy the least significant bits
- * within the register.
- */
-
-/*
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I 0
-/*
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I 10
-/*
- * Starting bit position within each entry of \b iomux_pins to represent which
- * mux mode is for GPIO (0-based)
- */
-#define GPIO_I 21
-
-#define MUX_IO_P 29
-#define MUX_IO_I 24
-
-#define NON_GPIO_PORT 0x7
-#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
-#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
-
-#define NON_MUX_I PIN_TO_MUX_MASK
-#define NON_PAD_I PIN_TO_PAD_MASK
-#define MUX_I_START 0x0020
-#define PAD_I_START 0x2CC
-#define INPUT_CTL_START 0x6C4
-#define MUX_I_END (PAD_I_START - 4)
-
-#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
- (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
- ((mi) << MUX_I) | \
- ((pi - PAD_I_START) << PAD_I) | \
- ((ga) << GPIO_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
- _MXC_BUILD_PIN(gp, gi, ga, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
- _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
-#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
-#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
-
-/*
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX50 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-enum iomux_pins {
- MX50_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 0, 1, 0x20, 0x2CC),
- MX50_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 1, 1, 0x24, 0x2D0),
- MX50_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 2, 1, 0x28, 0x2D4),
- MX50_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 3, 1, 0x2C, 0x2D8),
- MX50_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 4, 1, 0x30, 0x2DC),
- MX50_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x34, 0x2E0),
- MX50_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x38, 0x2E4),
- MX50_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x3C, 0x2E8),
- MX50_PIN_I2C1_SCL = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x40, 0x2EC),
- MX50_PIN_I2C1_SDA = _MXC_BUILD_GPIO_PIN(5, 19, 1, 0x44, 0x2F0),
- MX50_PIN_I2C2_SCL = _MXC_BUILD_GPIO_PIN(5, 20, 1, 0x48, 0x2F4),
- MX50_PIN_I2C2_SDA = _MXC_BUILD_GPIO_PIN(5, 21, 1, 0x4C, 0x2F8),
- MX50_PIN_I2C3_SCL = _MXC_BUILD_GPIO_PIN(5, 22, 1, 0x50, 0x2FC),
- MX50_PIN_I2C3_SDA = _MXC_BUILD_GPIO_PIN(5, 23, 1, 0x54, 0x300),
- MX50_PIN_PWM1 = _MXC_BUILD_GPIO_PIN(5, 24, 1, 0x58, 0x304),
- MX50_PIN_PWM2 = _MXC_BUILD_GPIO_PIN(5, 25, 1, 0x5C, 0x308),
- MX50_PIN_OWIRE = _MXC_BUILD_GPIO_PIN(5, 26, 1, 0x60, 0x30C),
- MX50_PIN_EPITO = _MXC_BUILD_GPIO_PIN(5, 27, 1, 0x64, 0x310),
- MX50_PIN_WDOG = _MXC_BUILD_GPIO_PIN(5, 28, 1, 0x68, 0x314),
- MX50_PIN_SSI_TXFS = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0x6C, 0x318),
- MX50_PIN_SSI_TXC = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0x70, 0x31C),
- MX50_PIN_SSI_TXD = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x74, 0x320),
- MX50_PIN_SSI_RXD = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x78, 0x324),
- MX50_PIN_SSI_RXFS = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x7C, 0x328),
- MX50_PIN_SSI_RXC = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x80, 0x32C),
- MX50_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x84, 0x330),
- MX50_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x88, 0x334),
- MX50_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(5, 8, 1, 0x8C, 0x338),
- MX50_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x90, 0x33C),
- MX50_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x94, 0x340),
- MX50_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x98, 0x344),
- MX50_PIN_UART2_CTS = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x9C, 0x348),
- MX50_PIN_UART2_RTS = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0xA0, 0x34C),
- MX50_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0xA4, 0x350),
- MX50_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0xA8, 0x354),
- MX50_PIN_UART4_TXD = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0xAC, 0x358),
- MX50_PIN_UART4_RXD = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0xB0, 0x35C),
- MX50_PIN_CSPI_SCLK = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0xB4, 0x360),
- MX50_PIN_CSPI_MOSI = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0xB8, 0x364),
- MX50_PIN_CSPI_MISO = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0xBC, 0x368),
- MX50_PIN_CSPI_SS0 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0xC0, 0x36C),
- MX50_PIN_ECSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0xC4, 0x370),
- MX50_PIN_ECSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0xC8, 0x374),
- MX50_PIN_ECSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0xCC, 0x378),
- MX50_PIN_ECSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0xD0, 0x37C),
- MX50_PIN_ECSPI2_SCLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0xD4, 0x380),
- MX50_PIN_ECSPI2_MOSI = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0xD8, 0x384),
- MX50_PIN_ECSPI2_MISO = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0xDC, 0x388),
- MX50_PIN_ECSPI2_SS0 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0xE0, 0x38C),
- MX50_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0xE4, 0x390),
- MX50_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(4, 1, 1, 0xE8, 0x394),
- MX50_PIN_SD1_D0 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0xEC, 0x398),
- MX50_PIN_SD1_D1 = _MXC_BUILD_GPIO_PIN(4, 3, 1, 0xF0, 0x39C),
- MX50_PIN_SD1_D2 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0xF4, 0x3A0),
- MX50_PIN_SD1_D3 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0xF8, 0x3A4),
- MX50_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0xFC, 0x3A8),
- MX50_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x100, 0x3AC),
- MX50_PIN_SD2_D0 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x104, 0x3B0),
- MX50_PIN_SD2_D1 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x108, 0x3B4),
- MX50_PIN_SD2_D2 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0x10C, 0x3B8),
- MX50_PIN_SD2_D3 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0x110, 0x3BC),
- MX50_PIN_SD2_D4 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0x114, 0x3C0),
- MX50_PIN_SD2_D5 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0x118, 0x3C4),
- MX50_PIN_SD2_D6 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0x11C, 0x3C8),
- MX50_PIN_SD2_D7 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0x120, 0x3CC),
- MX50_PIN_SD2_WP = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0x124, 0x3D0),
- MX50_PIN_SD2_CD = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0x128, 0x3D4),
- MX50_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3D8),
- MX50_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3DC),
- MX50_PIN_PMIC_PORT_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3E0),
- MX50_PIN_PMIC_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3E4),
- MX50_PIN_PMIC_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3E8),
- MX50_PIN_PMIC_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3EC),
- MX50_PIN_PMIC_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3F0),
- MX50_PIN_PMIC_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3F4),
- MX50_PIN_PMIC_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3F8),
- MX50_PIN_PMIC_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3FC),
- MX50_PIN_PMIC_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x400),
- MX50_PIN_PMIC_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x404),
- MX50_PIN_PMIC_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x408),
- MX50_PIN_DISP_D0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x12C, 0x40C),
- MX50_PIN_DISP_D1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x130, 0x410),
- MX50_PIN_DISP_D2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x134, 0x414),
- MX50_PIN_DISP_D3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x138, 0x418),
- MX50_PIN_DISP_D4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x13C, 0x41C),
- MX50_PIN_DISP_D5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x140, 0x420),
- MX50_PIN_DISP_D6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x144, 0x424),
- MX50_PIN_DISP_D7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x148, 0x428),
- MX50_PIN_DISP_WR = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x14C, 0x42C),
- MX50_PIN_DISP_RD = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x150, 0x430),
- MX50_PIN_DISP_RS = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x154, 0x434),
- MX50_PIN_DISP_CS = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x158, 0x438),
- MX50_PIN_DISP_BUSY = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x15C, 0x43C),
- MX50_PIN_DISP_RESET = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x160, 0x440),
- MX50_PIN_SD3_CMD = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0x164, 0x444),
- MX50_PIN_SD3_CLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0x168, 0x448),
- MX50_PIN_SD3_D0 = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0x16C, 0x44C),
- MX50_PIN_SD3_D1 = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0x170, 0x450),
- MX50_PIN_SD3_D2 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0x174, 0x454),
- MX50_PIN_SD3_D3 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0x178, 0x458),
- MX50_PIN_SD3_D4 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0x17C, 0x45C),
- MX50_PIN_SD3_D5 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0x180, 0x460),
- MX50_PIN_SD3_D6 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0x184, 0x464),
- MX50_PIN_SD3_D7 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0x188, 0x468),
- MX50_PIN_SD3_WP = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0x18C, 0x46C),
- MX50_PIN_DISP_D8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x190, 0x470),
- MX50_PIN_DISP_D9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x194, 0x474),
- MX50_PIN_DISP_D10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x198, 0x478),
- MX50_PIN_DISP_D11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x19C, 0x47C),
- MX50_PIN_DISP_D12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x1A0, 0x480),
- MX50_PIN_DISP_D13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x1A4, 0x484),
- MX50_PIN_DISP_D14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x1A8, 0x488),
- MX50_PIN_DISP_D15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x1AC, 0x48C),
- MX50_PIN_EPDC_D0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x1B0, 0x54C),
- MX50_PIN_EPDC_D1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1B4, 0x550),
- MX50_PIN_EPDC_D2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1B8, 0x554),
- MX50_PIN_EPDC_D3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1BC, 0x558),
- MX50_PIN_EPDC_D4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1C0, 0x55C),
- MX50_PIN_EPDC_D5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1C4, 0x560),
- MX50_PIN_EPDC_D6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1C8, 0x564),
- MX50_PIN_EPDC_D7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1CC, 0x568),
- MX50_PIN_EPDC_D8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1D0, 0x56C),
- MX50_PIN_EPDC_D9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1D4, 0x570),
- MX50_PIN_EPDC_D10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1D8, 0x574),
- MX50_PIN_EPDC_D11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1DC, 0x578),
- MX50_PIN_EPDC_D12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1E0, 0x57C),
- MX50_PIN_EPDC_D13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1E4, 0x580),
- MX50_PIN_EPDC_D14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1E8, 0x584),
- MX50_PIN_EPDC_D15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1EC, 0x588),
- MX50_PIN_EPDC_GDCLK = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x1F0, 0x58C),
- MX50_PIN_EPDC_GDSP = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x1F4, 0x590),
- MX50_PIN_EPDC_GDOE = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x1F8, 0x594),
- MX50_PIN_EPDC_GDRL = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x1FC, 0x598),
- MX50_PIN_EPDC_SDCLK = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x200, 0x59C),
- MX50_PIN_EPDC_SDOEZ = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x204, 0x5A0),
- MX50_PIN_EPDC_SDOED = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x208, 0x5A4),
- MX50_PIN_EPDC_SDOE = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x20C, 0x5A8),
- MX50_PIN_EPDC_SDLE = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x210, 0x5AC),
- MX50_PIN_EPDC_SDCLKN = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x214, 0x5B0),
- MX50_PIN_EPDC_SDSHR = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x218, 0x5B4),
- MX50_PIN_EPDC_PWRCOM = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x21C, 0x5B8),
- MX50_PIN_EPDC_PWRSTAT = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x220, 0x5BC),
- MX50_PIN_EPDC_PWRCTRL0 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x224, 0x5C0),
- MX50_PIN_EPDC_PWRCTRL1 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x228, 0x5C4),
- MX50_PIN_EPDC_PWRCTRL2 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x22C, 0x5C8),
- MX50_PIN_EPDC_PWRCTRL3 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x230, 0x5CC),
- MX50_PIN_EPDC_VCOM0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x234, 0x5D0),
- MX50_PIN_EPDC_VCOM1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x238, 0x5D4),
- MX50_PIN_EPDC_BDR0 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x23C, 0x5D8),
- MX50_PIN_EPDC_BDR1 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x240, 0x5DC),
- MX50_PIN_EPDC_SDCE0 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x244, 0x5E0),
- MX50_PIN_EPDC_SDCE1 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x248, 0x5E4),
- MX50_PIN_EPDC_SDCE2 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x24C, 0x5E8),
- MX50_PIN_EPDC_SDCE3 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x250, 0x5EC),
- MX50_PIN_EPDC_SDCE4 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x254, 0x5F0),
- MX50_PIN_EPDC_SDCE5 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x258, 0x5F4),
- MX50_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x25C, 0x5F8),
- MX50_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x260, 0x5FC),
- MX50_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x264, 0x600),
- MX50_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x268, 0x604),
- MX50_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x26C, 0x608),
- MX50_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x270, 0x60C),
- MX50_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x274, 0x610),
- MX50_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x278, 0x614),
- MX50_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x27C, 0x618),
- MX50_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x280, 0x61C),
- MX50_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x284, 0x620),
- MX50_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x288, 0x624),
- MX50_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x28C, 0x628),
- MX50_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x290, 0x62C),
- MX50_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x294, 0x630),
- MX50_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x298, 0x634),
- MX50_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x29C, 0x638),
- MX50_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2A0, 0x63C),
- MX50_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2A4, 0x640),
- MX50_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2A8, 0x644),
- MX50_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2AC, 0x648),
- MX50_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2B0, 0x64C),
- MX50_PIN_EIM_BCLK = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x2B4, 0x650),
- MX50_PIN_EIM_RDY = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x2B8, 0x654),
- MX50_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x2BC, 0x658),
- MX50_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x2C0, 0x65C),
- MX50_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x2C4, 0x660),
- MX50_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x2C8, 0x664),
-};
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_MXC_MX50_PINS_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _IMX_SPI_PMIC_H_
-#define _IMX_SPI_PMIC_H_
-
-#include <linux/types.h>
-
-extern struct spi_slave *spi_pmic_probe(void);
-extern void spi_pmic_free(struct spi_slave *slave);
-extern u32 pmic_reg(struct spi_slave *slave,
- u32 reg, u32 val, u32 write);
-
-#endif /* _IMX_SPI_PMIC_H_ */
+++ /dev/null
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __MACH_MX51_IOMUX_H__
-#define __MACH_MX51_IOMUX_H__
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mx51.h>
-#include <asm/arch/mx51_pins.h>
-
-/*!
- * @file iomux.h
- *
- * @brief I/O Muxing control definitions and functions
- *
- * @ingroup GPIO_MX51
- */
-
-typedef unsigned int iomux_pin_name_t;
-
-/*!
- * various IOMUX output functions
- */
-typedef enum iomux_config {
- IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */
- IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */
- IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */
- IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */
- IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */
- IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */
- IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */
- IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */
- IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */
- IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
-} iomux_pin_cfg_t;
-
-/*!
- * various IOMUX pad functions
- */
-typedef enum iomux_pad_config {
- PAD_CTL_SRE_SLOW = 0x0 << 0,
- PAD_CTL_SRE_FAST = 0x1 << 0,
- PAD_CTL_DRV_LOW = 0x0 << 1,
- PAD_CTL_DRV_MEDIUM = 0x1 << 1,
- PAD_CTL_DRV_HIGH = 0x2 << 1,
- PAD_CTL_DRV_MAX = 0x3 << 1,
- PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,
- PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,
- PAD_CTL_100K_PD = 0x0 << 4,
- PAD_CTL_47K_PU = 0x1 << 4,
- PAD_CTL_100K_PU = 0x2 << 4,
- PAD_CTL_22K_PU = 0x3 << 4,
- PAD_CTL_PUE_KEEPER = 0x0 << 6,
- PAD_CTL_PUE_PULL = 0x1 << 6,
- PAD_CTL_PKE_NONE = 0x0 << 7,
- PAD_CTL_PKE_ENABLE = 0x1 << 7,
- PAD_CTL_HYS_NONE = 0x0 << 8,
- PAD_CTL_HYS_ENABLE = 0x1 << 8,
- PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,
- PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,
- PAD_CTL_DRV_VOT_LOW = 0x0 << 13,
- PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,
-} iomux_pad_config_t;
-
-/*!
- * various IOMUX input select register index
- */
-typedef enum iomux_input_select {
- MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
- MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
- MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
- MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
- MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT,
- /* TO2 */
- MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
- MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
- MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
- MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
- MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
- /* TO2 */
- MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
- MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
- MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
- MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
- MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
- MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
- MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
- MUX_IN_FEC_FEC_COL_SELECT_INPUT,
- MUX_IN_FEC_FEC_CRS_SELECT_INPUT,
- MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT,
- MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT,
- MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
- MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
- MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
- MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
- MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
- /* TO2 */
- MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
- MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
- MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
- /* TO2 */
- MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
- /* TO2 */
- MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
- MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
- MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
- MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
- MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
- MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
-
- MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
-
- MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
-
- MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
- MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
- MUX_INPUT_NUM_MUX,
-} iomux_input_select_t;
-
-/*!
- * various IOMUX input functions
- */
-typedef enum iomux_input_config {
- INPUT_CTL_PATH0 = 0x0,
- INPUT_CTL_PATH1,
- INPUT_CTL_PATH2,
- INPUT_CTL_PATH3,
- INPUT_CTL_PATH4,
- INPUT_CTL_PATH5,
- INPUT_CTL_PATH6,
- INPUT_CTL_PATH7,
-} iomux_input_config_t;
-
-/*!
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param config config as defined in \b #iomux_pin_ocfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-
-/*!
- * Release ownership for an IO pin
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param config config as defined in \b #iomux_pin_ocfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-
-/*!
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @param config the ORed value of elements defined in
- * \b #iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
-
-/*!
- * This function gets the current pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @return current pad value
- */
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
-
-/*!
- * This function configures input path.
- *
- * @param input index of input select register as defined in
- * \b #iomux_input_select_t
- * @param config the binary value of elements defined in
- * \b #iomux_input_config_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-
-#endif /* __MACH_MX51_IOMUX_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the MX51-3Stack Freescale board.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _MXC_KEYPAD_H_
-#define _MXC_KEYPAD_H_
-
-#include <config.h>
-
-#define KEY_1 2
-#define KEY_2 3
-#define KEY_3 4
-#define KEY_F1 59
-#define KEY_UP 103
-#define KEY_F2 60
-
-#define KEY_4 5
-#define KEY_5 6
-#define KEY_6 7
-#define KEY_LEFT 105
-#define KEY_SELECT 0x161
-#define KEY_RIGHT 106
-
-#define KEY_7 8
-#define KEY_8 9
-#define KEY_9 10
-#define KEY_F3 61
-#define KEY_DOWN 108
-#define KEY_F4 62
-
-#define KEY_0 11
-#define KEY_OK 0x160
-#define KEY_ESC 1
-#define KEY_ENTER 28
-#define KEY_MENU 139 /* Menu (show menu) */
-#define KEY_BACK 158 /* AC Back */
-
-#if defined(CONFIG_MX51_BBG)
-#define TEST_HOME_KEY_DEPRESS(k, e) (((k) == (KEY_F1)) && (((e) == (KDepress))))
-#define TEST_POWER_KEY_DEPRESS(k, e) (((k) == (KEY_F3)) && (((e) == (KDepress))))
-#elif defined(CONFIG_MX51_3DS)
-#define TEST_HOME_KEY_DEPRESS(k, e) (((k) == (KEY_MENU)) && (((e) == (KDepress))))
-#define TEST_POWER_KEY_DEPRESS(k, e) (((k) == (KEY_F2)) && (((e) == (KDepress))))
-#else
-# error Undefined board type!
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __ARM_ARCH_MMU_H
-#define __ARM_ARCH_MMU_H
-
-#include <linux/types.h>
-
-/*
- * Translation Table Base Bit Masks
- */
-#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
-
-/*
- * Domain Access Control Bit Masks
- */
-#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
-#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
-#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
-
-struct ARM_MMU_FIRST_LEVEL_FAULT {
- unsigned int id:2;
- unsigned int sbz:30;
-};
-
-#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
-
-struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
- unsigned int id:2;
- unsigned int imp:2;
- unsigned int domain:4;
- unsigned int sbz:1;
- unsigned int base_address:23;
-};
-
-#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
-
-struct ARM_MMU_FIRST_LEVEL_SECTION {
- unsigned int id:2;
- unsigned int b:1;
- unsigned int c:1;
- unsigned int imp:1;
- unsigned int domain:4;
- unsigned int sbz0:1;
- unsigned int ap:2;
- unsigned int sbz1:8;
- unsigned int base_address:12;
-};
-
-#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
-
-struct ARM_MMU_FIRST_LEVEL_RESERVED {
- unsigned int id:2;
- unsigned int sbz:30;
-};
-
-#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
-
-#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
- (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
-
-#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
-
-#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
- cacheable, bufferable, perm) \
- { \
- register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
- desc.word = 0; \
- desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
- desc.section.domain = 0; \
- desc.section.c = (cacheable); \
- desc.section.b = (bufferable); \
- desc.section.ap = (perm); \
- desc.section.base_address = (actual_base); \
- *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
- = desc.word; \
- }
-
-#define X_ARM_MMU_SECTION(abase, vbase, size, cache, buff, access) \
- { \
- int i; int j = abase; int k = vbase; \
- for (i = size; i > 0 ; i--, j++, k++) \
- ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
- }
-
-union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
- unsigned long word;
- struct ARM_MMU_FIRST_LEVEL_FAULT fault;
- struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
- struct ARM_MMU_FIRST_LEVEL_SECTION section;
- struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
-};
-
-#define ARM_UNCACHEABLE 0
-#define ARM_CACHEABLE 1
-#define ARM_UNBUFFERABLE 0
-#define ARM_BUFFERABLE 1
-
-#define ARM_ACCESS_PERM_NONE_NONE 0
-#define ARM_ACCESS_PERM_RO_NONE 0
-#define ARM_ACCESS_PERM_RO_RO 0
-#define ARM_ACCESS_PERM_RW_NONE 1
-#define ARM_ACCESS_PERM_RW_RO 2
-#define ARM_ACCESS_PERM_RW_RW 3
-
-/*
- * Initialization for the Domain Access Control Register
- */
-#define ARM_ACCESS_DACR_DEFAULT ( \
- ARM_ACCESS_TYPE_MANAGER(0) | \
- ARM_ACCESS_TYPE_NO_ACCESS(1) | \
- ARM_ACCESS_TYPE_NO_ACCESS(2) | \
- ARM_ACCESS_TYPE_NO_ACCESS(3) | \
- ARM_ACCESS_TYPE_NO_ACCESS(4) | \
- ARM_ACCESS_TYPE_NO_ACCESS(5) | \
- ARM_ACCESS_TYPE_NO_ACCESS(6) | \
- ARM_ACCESS_TYPE_NO_ACCESS(7) | \
- ARM_ACCESS_TYPE_NO_ACCESS(8) | \
- ARM_ACCESS_TYPE_NO_ACCESS(9) | \
- ARM_ACCESS_TYPE_NO_ACCESS(10) | \
- ARM_ACCESS_TYPE_NO_ACCESS(11) | \
- ARM_ACCESS_TYPE_NO_ACCESS(12) | \
- ARM_ACCESS_TYPE_NO_ACCESS(13) | \
- ARM_ACCESS_TYPE_NO_ACCESS(14) | \
- ARM_ACCESS_TYPE_NO_ACCESS(15))
-
-#if defined(CONFIG_MX51_3DS)
-
-/*
- * Translate the virtual address of ram space to physical address
- * It is dependent on the implementation of mmu_init
- */
-inline unsigned long iomem_to_phys(unsigned long virt)
-{
- if (virt < 0x08000000)
- return (unsigned long)(virt | PHYS_SDRAM_1);
-
- if ((virt & 0xF0000000) == PHYS_SDRAM_1)
- return (unsigned long)(virt & (~0x08000000));
-
- return (unsigned long)virt;
-}
-
-/*
- * remap the physical address of ram space to uncacheable virtual address space
- * It is dependent on the implementation of hal_mmu_init
- */
-void *__ioremap(unsigned long offset, size_t size, unsigned long flags)
-{
- if (1 == flags) {
- /* 0x98000000~0x9FFFFFFF is uncacheable meory
- space which is mapped to SDRAM */
- if ((offset & 0xF0000000) == PHYS_SDRAM_1)
- return (void *)(offset |= 0x08000000);
- else
- return NULL;
- } else
- return (void *)offset;
-}
-
-#elif defined(CONFIG_MX51_BBG)
-
-/*
- * Translate the virtual address of ram space to physical address
- * It is dependent on the implementation of mmu_init
- */
-inline unsigned long iomem_to_phys(unsigned long virt)
-{
- if (virt < (PHYS_SDRAM_1_SIZE - 0x100000))
- return (unsigned long)(virt + PHYS_SDRAM_1);
-
- if (virt >= 0xE0000000)
- return (unsigned long)((virt - 0xE0000000) + PHYS_SDRAM_1);
-
- return (unsigned long)virt;
-}
-
-/*
- * Remap the physical address of ram space to uncacheable virtual address space
- * It is dependent on the implementation of hal_mmu_init
- */
-void __iounmap(void *addr)
-{
- return;
-}
-
-void *__ioremap(unsigned long offset, size_t size, unsigned long flags)
-{
- if (1 == flags) {
- /* 0xE0000000~0xFFFFFFFF is uncacheable
- meory space which is mapped to SDRAM */
- if (offset >= PHYS_SDRAM_1 &&
- offset < (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
- return (void *)((offset - PHYS_SDRAM_1) + 0xE0000000);
- else
- return NULL;
- } else
- return (void *)offset;
-}
-
-#else
- #error "No such platforms for MMU!"
-#endif
-
-#endif
+++ /dev/null
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __ASM_ARCH_MXC_MX51_H__
-#define __ASM_ARCH_MXC_MX51_H__
-
-#define __REG(x) (*((volatile u32 *)(x)))
-#define __REG16(x) (*((volatile u16 *)(x)))
-#define __REG8(x) (*((volatile u8 *)(x)))
-/*
- * IRAM
- */
-#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */
-/*
- * Graphics Memory of GPU
- */
-#define GPU_BASE_ADDR 0x20000000
-#define GPU_CTRL_BASE_ADDR 0x30000000
-#define IPU_CTRL_BASE_ADDR 0x40000000
-/*
- * Debug
- */
-#define DEBUG_BASE_ADDR 0x60000000
-#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
-#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
-#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
-#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
-#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
-#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
-#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
-#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
-
-/*
- * SPBA global module enabled #0
- */
-#define SPBA0_BASE_ADDR 0x70000000
-
-#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
-#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
-#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
-#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
-#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
-#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
-#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
-#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
-#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
-#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
-#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
-
-/*
- * AIPS 1
- */
-#define AIPS1_BASE_ADDR 0x73F00000
-
-#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
-#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
-#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
-#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
-#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
-#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
-#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
-#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
-#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
-#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
-#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
-#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
-#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
-#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
-#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
-#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
-#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
-#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
-#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
-#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
-
-/*
- * AIPS 2
- */
-#define AIPS2_BASE_ADDR 0x83F00000
-
-#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
-#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
-#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
-#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
-#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
-#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
-#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
-#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
-#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
-#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
-#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
-#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
-#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
-#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
-#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
-#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
-#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
-#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
-#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
-#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
-#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
-#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
-#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
-#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
-#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
-#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
-#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
-#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
-#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
-#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
-#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
-#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
-
-#define TZIC_BASE_ADDR 0x8FFFC000
-
-/*
- * Memory regions and CS
- */
-#define CSD0_BASE_ADDR 0x90000000
-#define CSD1_BASE_ADDR 0xA0000000
-#define CS0_BASE_ADDR 0xB0000000
-#define CS1_BASE_ADDR 0xB8000000
-#define CS2_BASE_ADDR 0xC0000000
-#define CS3_BASE_ADDR 0xC8000000
-#define CS4_BASE_ADDR 0xCC000000
-#define CS5_BASE_ADDR 0xCE000000
-
-/*
- * NFC
- */
-#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */
-
-/*!
- * defines for SPBA modules
- */
-#define SPBA_SDHC1 0x04
-#define SPBA_SDHC2 0x08
-#define SPBA_UART3 0x0C
-#define SPBA_CSPI1 0x10
-#define SPBA_SSI2 0x14
-#define SPBA_SDHC3 0x20
-#define SPBA_SDHC4 0x24
-#define SPBA_SPDIF 0x28
-#define SPBA_ATA 0x30
-#define SPBA_SLIM 0x34
-#define SPBA_HSI2C 0x38
-#define SPBA_CTRL 0x3C
-
-/*
- * Interrupt numbers
- */
-#define MXC_INT_BASE 0
-#define MXC_INT_RESV0 0
-#define MXC_INT_MMC_SDHC1 1
-#define MXC_INT_MMC_SDHC2 2
-#define MXC_INT_MMC_SDHC3 3
-#define MXC_INT_MMC_SDHC4 4
-#define MXC_INT_RESV5 5
-#define MXC_INT_SDMA 6
-#define MXC_INT_IOMUX 7
-#define MXC_INT_NFC 8
-#define MXC_INT_VPU 9
-#define MXC_INT_IPU_ERR 10
-#define MXC_INT_IPU_SYN 11
-#define MXC_INT_GPU 12
-#define MXC_INT_RESV13 13
-#define MXC_INT_USB_H1 14
-#define MXC_INT_EMI 15
-#define MXC_INT_USB_H2 16
-#define MXC_INT_USB_H3 17
-#define MXC_INT_USB_OTG 18
-#define MXC_INT_SAHARA_H0 19
-#define MXC_INT_SAHARA_H1 20
-#define MXC_INT_SCC_SMN 21
-#define MXC_INT_SCC_STZ 22
-#define MXC_INT_SCC_SCM 23
-#define MXC_INT_SRTC_NTZ 24
-#define MXC_INT_SRTC_TZ 25
-#define MXC_INT_RTIC 26
-#define MXC_INT_CSU 27
-#define MXC_INT_SLIM_B 28
-#define MXC_INT_SSI1 29
-#define MXC_INT_SSI2 30
-#define MXC_INT_UART1 31
-#define MXC_INT_UART2 32
-#define MXC_INT_UART3 33
-#define MXC_INT_RESV34 34
-#define MXC_INT_RESV35 35
-#define MXC_INT_CSPI1 36
-#define MXC_INT_CSPI2 37
-#define MXC_INT_CSPI 38
-#define MXC_INT_GPT 39
-#define MXC_INT_EPIT1 40
-#define MXC_INT_EPIT2 41
-#define MXC_INT_GPIO1_INT7 42
-#define MXC_INT_GPIO1_INT6 43
-#define MXC_INT_GPIO1_INT5 44
-#define MXC_INT_GPIO1_INT4 45
-#define MXC_INT_GPIO1_INT3 46
-#define MXC_INT_GPIO1_INT2 47
-#define MXC_INT_GPIO1_INT1 48
-#define MXC_INT_GPIO1_INT0 49
-#define MXC_INT_GPIO1_LOW 50
-#define MXC_INT_GPIO1_HIGH 51
-#define MXC_INT_GPIO2_LOW 52
-#define MXC_INT_GPIO2_HIGH 53
-#define MXC_INT_GPIO3_LOW 54
-#define MXC_INT_GPIO3_HIGH 55
-#define MXC_INT_GPIO4_LOW 56
-#define MXC_INT_GPIO4_HIGH 57
-#define MXC_INT_WDOG1 58
-#define MXC_INT_WDOG2 59
-#define MXC_INT_KPP 60
-#define MXC_INT_PWM1 61
-#define MXC_INT_I2C1 62
-#define MXC_INT_I2C2 63
-#define MXC_INT_HS_I2C 64
-#define MXC_INT_RESV65 65
-#define MXC_INT_RESV66 66
-#define MXC_INT_SIM_IPB 67
-#define MXC_INT_SIM_DAT 68
-#define MXC_INT_IIM 69
-#define MXC_INT_ATA 70
-#define MXC_INT_CCM1 71
-#define MXC_INT_CCM2 72
-#define MXC_INT_GPC1 73
-#define MXC_INT_GPC2 74
-#define MXC_INT_SRC 75
-#define MXC_INT_NM 76
-#define MXC_INT_PMU 77
-#define MXC_INT_CTI_IRQ 78
-#define MXC_INT_CTI1_TG0 79
-#define MXC_INT_CTI1_TG1 80
-#define MXC_INT_MCG_ERR 81
-#define MXC_INT_MCG_TMR 82
-#define MXC_INT_MCG_FUNC 83
-#define MXC_INT_RESV84 84
-#define MXC_INT_RESV85 85
-#define MXC_INT_RESV86 86
-#define MXC_INT_FEC 87
-#define MXC_INT_OWIRE 88
-#define MXC_INT_CTI1_TG2 89
-#define MXC_INT_SJC 90
-#define MXC_INT_SPDIF 91
-#define MXC_INT_TVE 92
-#define MXC_INT_FIRI 93
-#define MXC_INT_PWM2 94
-#define MXC_INT_SLIM_EXP 95
-#define MXC_INT_SSI3 96
-#define MXC_INT_RESV97 97
-#define MXC_INT_CTI1_TG3 98
-#define MXC_INT_SMC_RX 99
-#define MXC_INT_VPU_IDLE 100
-#define MXC_INT_RESV101 101
-#define MXC_INT_GPU_IDLE 102
-
-#define MXC_MAX_INT_LINES 128
-
-#define MXC_GPIO_INT_BASE (MXC_MAX_INT_LINES)
-
-/*!
- * Number of GPIO port as defined in the IC Spec
- */
-#define GPIO_PORT_NUM 4
-/*!
- * Number of GPIO pins per port
- */
-#define GPIO_NUM_PIN 32
-
-#define MXC_GPIO_SPLIT_IRQ_2
-
-#define IIM_SREV 0x24
-#define ROM_SI_REV 0x48
-
-#define NFC_BUF_SIZE 0x1000
-
-/* WEIM registers */
-#define CSGCR1 0x00
-#define CSGCR2 0x04
-#define CSRCR1 0x08
-#define CSRCR2 0x0C
-#define CSWCR1 0x10
-
-/* M4IF */
-#define M4IF_FBPM0 0x40
-#define M4IF_FIDBP 0x48
-
-/* ESDCTL */
-#define ESDCTL_ESDCTL0 0x00
-#define ESDCTL_ESDCFG0 0x04
-#define ESDCTL_ESDCTL1 0x08
-#define ESDCTL_ESDCFG1 0x0C
-#define ESDCTL_ESDMISC 0x10
-#define ESDCTL_ESDSCR 0x14
-#define ESDCTL_ESDCDLY1 0x20
-#define ESDCTL_ESDCDLY2 0x24
-#define ESDCTL_ESDCDLY3 0x28
-#define ESDCTL_ESDCDLY4 0x2C
-#define ESDCTL_ESDCDLY5 0x30
-#define ESDCTL_ESDCDLYGD 0x34
-
-/* CCM */
-#define CLKCTL_CCR 0x00
-#define CLKCTL_CCDR 0x04
-#define CLKCTL_CSR 0x08
-#define CLKCTL_CCSR 0x0C
-#define CLKCTL_CACRR 0x10
-#define CLKCTL_CBCDR 0x14
-#define CLKCTL_CBCMR 0x18
-#define CLKCTL_CSCMR1 0x1C
-#define CLKCTL_CSCMR2 0x20
-#define CLKCTL_CSCDR1 0x24
-#define CLKCTL_CS1CDR 0x28
-#define CLKCTL_CS2CDR 0x2C
-#define CLKCTL_CDCDR 0x30
-#define CLKCTL_CHSCCDR 0x34
-#define CLKCTL_CSCDR2 0x38
-#define CLKCTL_CSCDR3 0x3C
-#define CLKCTL_CSCDR4 0x40
-#define CLKCTL_CWDR 0x44
-#define CLKCTL_CDHIPR 0x48
-#define CLKCTL_CDCR 0x4C
-#define CLKCTL_CTOR 0x50
-#define CLKCTL_CLPCR 0x54
-#define CLKCTL_CISR 0x58
-#define CLKCTL_CIMR 0x5C
-#define CLKCTL_CCOSR 0x60
-#define CLKCTL_CGPR 0x64
-#define CLKCTL_CCGR0 0x68
-#define CLKCTL_CCGR1 0x6C
-#define CLKCTL_CCGR2 0x70
-#define CLKCTL_CCGR3 0x74
-#define CLKCTL_CCGR4 0x78
-#define CLKCTL_CCGR5 0x7C
-#define CLKCTL_CCGR6 0x80
-#define CLKCTL_CMEOR 0x84
-
-/* DPLL */
-#define PLL_DP_CTL 0x00
-#define PLL_DP_CONFIG 0x04
-#define PLL_DP_OP 0x08
-#define PLL_DP_MFD 0x0C
-#define PLL_DP_MFN 0x10
-#define PLL_DP_MFNMINUS 0x14
-#define PLL_DP_MFNPLUS 0x18
-#define PLL_DP_HFS_OP 0x1C
-#define PLL_DP_HFS_MFD 0x20
-#define PLL_DP_HFS_MFN 0x24
-#define PLL_DP_TOGC 0x28
-#define PLL_DP_DESTAT 0x2C
-
-/* Assuming 24MHz input clock with doubler ON */
-/* MFI PDF */
-#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
-#define DP_MFD_850 (48 - 1)
-#define DP_MFN_850 41
-
-#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
-#define DP_MFD_800 (3 - 1)
-#define DP_MFN_800 1
-
-#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
-#define DP_MFD_700 (24 - 1)
-#define DP_MFN_700 7
-
-#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
-#define DP_MFD_665 (96 - 1)
-#define DP_MFN_665 89
-
-#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
-#define DP_MFD_532 (24 - 1)
-#define DP_MFN_532 13
-
-#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
-#define DP_MFD_400 (3 - 1)
-#define DP_MFN_400 1
-
-#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
-#define DP_MFD_216 (4 - 1)
-#define DP_MFN_216 3
-
-/* IIM */
-#define IIM_STAT_OFF 0x00
-#define IIM_STAT_BUSY (1 << 7)
-#define IIM_STAT_PRGD (1 << 1)
-#define IIM_STAT_SNSD (1 << 0)
-#define IIM_STATM_OFF 0x04
-#define IIM_ERR_OFF 0x08
-#define IIM_ERR_PRGE (1 << 7)
-#define IIM_ERR_WPE (1 << 6)
-#define IIM_ERR_OPE (1 << 5)
-#define IIM_ERR_RPE (1 << 4)
-#define IIM_ERR_WLRE (1 << 3)
-#define IIM_ERR_SNSE (1 << 2)
-#define IIM_ERR_PARITYE (1 << 1)
-#define IIM_EMASK_OFF 0x0C
-#define IIM_FCTL_OFF 0x10
-#define IIM_UA_OFF 0x14
-#define IIM_LA_OFF 0x18
-#define IIM_SDAT_OFF 0x1C
-#define IIM_PREV_OFF 0x20
-#define IIM_SREV_OFF 0x24
-#define IIM_PREG_P_OFF 0x28
-#define IIM_SCS0_OFF 0x2C
-#define IIM_SCS1_P_OFF 0x30
-#define IIM_SCS2_OFF 0x34
-#define IIM_SCS3_P_OFF 0x38
-
-#define IIM_PROD_REV_SH 3
-#define IIM_PROD_REV_LEN 5
-#define IIM_SREV_REV_SH 4
-#define IIM_SREV_REV_LEN 4
-#define PROD_SIGNATURE_MX51 0x1
-
-#define CHIP_REV_1_0 0x10
-#define CHIP_REV_1_1 0x11
-#define CHIP_REV_2_0 0x20
-#define CHIP_REV_2_5 0x25
-#define CHIP_REV_3_0 0x30
-
-#define BOARD_REV_1_0 0x0
-#define BOARD_REV_2_0 0x1
-
-#define BOARD_VER_OFFSET 0x8
-
-#define NAND_FLASH_BOOT 0x10000000
-#define SPI_NOR_FLASH_BOOT 0x80000000
-#define MMC_FLASH_BOOT 0x40000000
-
-#ifndef __ASSEMBLER__
-
-enum boot_device {
- UNKNOWN_BOOT,
- NAND_BOOT,
- SPI_NOR_BOOT,
- MMC_BOOT,
-};
-
-enum mxc_clock {
-MXC_ARM_CLK = 0,
-MXC_AHB_CLK,
-MXC_IPG_CLK,
-MXC_IPG_PERCLK,
-MXC_UART_CLK,
-MXC_CSPI_CLK,
-MXC_FEC_CLK,
-MXC_ESDHC_CLK,
-};
-
-/*
-enum mxc_main_clocks {
- MXC_CPU_CLK,
- MXC_AHB_CLK,
- MXC_IPG_CLK,
- MXC_IPG_PER_CLK,
- MXC_DDR_CLK,
- MXC_NFC_CLK,
- MXC_USB_CLK,
-};
-*/
-
-enum mxc_peri_clocks {
- MXC_UART1_BAUD,
- MXC_UART2_BAUD,
- MXC_UART3_BAUD,
- MXC_SSI1_BAUD,
- MXC_SSI2_BAUD,
- MXC_CSI_BAUD,
- MXC_MSTICK1_CLK,
- MXC_MSTICK2_CLK,
- MXC_SPI1_CLK,
- MXC_SPI2_CLK,
-};
-
-extern unsigned int mxc_get_clock(enum mxc_clock clk);
-extern unsigned int get_board_rev(void);
-extern int is_soc_rev(int rev);
-extern enum boot_device get_boot_device(void);
-
-#endif /* __ASSEMBLER__*/
-
-#endif /* __ASM_ARCH_MXC_MX51_H__ */
+++ /dev/null
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_ARCH_MXC_MX51_PINS_H__
-#define __ASM_ARCH_MXC_MX51_PINS_H__
-
-/*!
- * @file arch-mxc/mx51_pins.h
- *
- * @brief MX51 I/O Pin List
- *
- * @ingroup GPIO_MX51
- */
-
-#ifndef __ASSEMBLY__
-
-/*!
- * @name IOMUX/PAD Bit field definitions
- */
-
-/*! @{ */
-
-/*!
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P | IO_I | GPIO_I | PAD_I | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 9 contains MUX_I used to identify the register
- * offset (0-based. base is IOMUX_module_base) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
- * similar field definitions are used for the pad control register.
- * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
- * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
- * It means the mux control register is at register offset 0x28. The pad control
- * register offset is: 0x250 and also occupy the least significant bits
- * within the register.
- */
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I 0
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I 10
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent which
- * mux mode is for GPIO (0-based)
- */
-#define GPIO_I 21
-
-#define MUX_IO_P 29
-#define MUX_IO_I 24
-#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
- GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
- ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
-#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
-#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
-
-#define NON_GPIO_PORT 0x7
-#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
-#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
-
-#define NON_MUX_I PIN_TO_MUX_MASK
-#define MUX_I_START 0x001C
-#define PAD_I_START 0x3F0
-#define INPUT_CTL_START 0x8C4
-#define INPUT_CTL_START_TO1 0x928
-#define MUX_I_END (PAD_I_START - 4)
-
-#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
- (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
- ((mi) << MUX_I) | \
- ((pi - PAD_I_START) << PAD_I) | \
- ((ga) << GPIO_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
- _MXC_BUILD_PIN(gp, gi, ga, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
- _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
-#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
-#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
-
-/*! @} End IOMUX/PAD Bit field definitions */
-
-/*!
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-enum iomux_pins {
- MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
- MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
- MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
- MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
- MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
- MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
- MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
- MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
- MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
- MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
- MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
- MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
- MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
- MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
- MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
- MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
- MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
- MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
- MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
- MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
- MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
- MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
- MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
- MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
- MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
- MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
- MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
- MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
- MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
- MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
- MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
- MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
- MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
- MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
- MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
- MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
- MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
- MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
- MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
- MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
- MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
- MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
- MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
- MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
- MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
- MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
- MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
- MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
- MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
- MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
- MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
- MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
- MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
- MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
- MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
- MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
- MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
- MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
- MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
- MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
- MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
- MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
- MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
- MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
- MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
- MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
- MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
- MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
- MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514),
- MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
- MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
- MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
- MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
- MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
- MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
- MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
- MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
- MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
- MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
- MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
- MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
- MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
- MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
- MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
- MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
- MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
- MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
- MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
- MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
- MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
- MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
- MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
- MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
- MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
- MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
- MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
- MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
- MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
- MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
- MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
- MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
- MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
- MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
- MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
- MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
- MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
- MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
- MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
- MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
- MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
- MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC),
- MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0),
- MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
- MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
- MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
- MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
- MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
- MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4),
- MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8),
- MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC),
- MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0),
- MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
- MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
- MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
- MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
- MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
- MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
- MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
- MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
- MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
- MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
- MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
- MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
- MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
- MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
- MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
- MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
- MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
- MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
- MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
- MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
- MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
- MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
- MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
- MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
- MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
- MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
- MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
- MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
- MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
- MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
- MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
- MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
- MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
- MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
- MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
- MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
- MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
- MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
- MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
- MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
- MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
- MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
- MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
- MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
- MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
- MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
- MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
- MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
- MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
- MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
- MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
- MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
- MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
- MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
- MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
- MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
- MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
- MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
- MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
- MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
- MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
- MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
- MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
- MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
- MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
- MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
- MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
- MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
- MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
- MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
- MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
- MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
- MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
- MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
- MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
- MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
- MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
- MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
- MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
- MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
- MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
- MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
- MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
- MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
- MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
- MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
- MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
- MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
- MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
- MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
- MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
- MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
- MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
- MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
- MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
- MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
- MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
- MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
- MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
- MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
- MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
- MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
- MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
- MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788),
- MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
- MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
- MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
- MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
- MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
- MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
- MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
- MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
- MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
- MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
- MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
- MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
- MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
- MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
- MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
- MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
- MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
- MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
- MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
- MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
- MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
- MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
- MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
- MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
- MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
- MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
- MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
-};
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */
+++ /dev/null
-/*
- * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/*!
- * @file mxc_nand.h
- *
- * @brief This file contains the NAND Flash Controller register information.
- *
- *
- * @ingroup NAND_MTD
- */
-
-#ifndef __MXC_NAND_H__
-#define __MXC_NAND_H__
-
-#include <asm/arch/mx51.h>
-
-#define IS_2K_PAGE_NAND ((mtd->writesize / info->num_of_intlv) \
- == NAND_PAGESIZE_2KB)
-#define IS_4K_PAGE_NAND ((mtd->writesize / info->num_of_intlv) \
- == NAND_PAGESIZE_4KB)
-#define IS_LARGE_PAGE_NAND ((mtd->writesize / info->num_of_intlv) > 512)
-
-#define GET_NAND_OOB_SIZE (mtd->oobsize / info->num_of_intlv)
-#define GET_NAND_PAGE_SIZE (mtd->writesize / info->num_of_intlv)
-
-/*
- * main area for bad block marker is in the last data section
- * the spare area for swapped bad block marker is the second
- * byte of last spare section
- */
-#define NAND_SECTIONS (GET_NAND_PAGE_SIZE >> 9)
-#define NAND_OOB_PER_SECTION (((GET_NAND_OOB_SIZE / NAND_SECTIONS) >> 1) << 1)
-#define NAND_CHUNKS (GET_NAND_PAGE_SIZE / (512 + NAND_OOB_PER_SECTION))
-
-#define BAD_BLK_MARKER_MAIN_OFFS \
- (GET_NAND_PAGE_SIZE - NAND_CHUNKS * NAND_OOB_PER_SECTION)
-
-#define BAD_BLK_MARKER_SP_OFFS (NAND_CHUNKS * SPARE_LEN)
-
-#define BAD_BLK_MARKER_OOB_OFFS (NAND_CHUNKS * NAND_OOB_PER_SECTION)
-
-#define BAD_BLK_MARKER_MAIN \
- ((u32)MAIN_AREA0 + BAD_BLK_MARKER_MAIN_OFFS)
-
-#define BAD_BLK_MARKER_SP \
- ((u32)SPARE_AREA0 + BAD_BLK_MARKER_SP_OFFS)
-
-#define NAND_PAGESIZE_2KB 2048
-#define NAND_PAGESIZE_4KB 4096
-
-#define NFC_AXI_BASE_ADDR NFC_BASE_ADDR_AXI
-#define NFC_IP_BASE_ADDR NFC_BASE_ADDR
-#define MXC_INT_NANDFC MXC_INT_NFC
-#define CONFIG_MXC_NFC_SP_AUTO
-#define NFC_FLASH_CMD (NFC_AXI_BASE_ADDR + 0x1E00)
-#define NFC_FLASH_ADDR0 (NFC_AXI_BASE_ADDR + 0x1E04)
-#define NFC_FLASH_ADDR8 (NFC_AXI_BASE_ADDR + 0x1E24)
-#define NFC_CONFIG1 (NFC_AXI_BASE_ADDR + 0x1E34)
-#define NFC_ECC_STATUS_RESULT (NFC_AXI_BASE_ADDR + 0x1E38)
-#define NFC_ECC_STATUS_SUM (NFC_AXI_BASE_ADDR + 0x1E3C)
-#define LAUNCH_NFC (NFC_AXI_BASE_ADDR + 0x1E40)
-#define NFC_WRPROT (NFC_IP_BASE_ADDR + 0x00)
-#define NFC_WRPROT_UNLOCK_BLK_ADD0 (NFC_IP_BASE_ADDR + 0x04)
-#define NFC_CONFIG2 (NFC_IP_BASE_ADDR + 0x24)
-#define NFC_CONFIG3 (NFC_IP_BASE_ADDR + 0x28)
-#define NFC_IPC (NFC_IP_BASE_ADDR + 0x2C)
-
-/*!
- * Addresses for NFC RAM BUFFER Main area 0
- */
-#define MAIN_AREA0 ((u16 *)(NFC_AXI_BASE_ADDR + 0x000))
-#define MAIN_AREA1 ((u16 *)(NFC_AXI_BASE_ADDR + 0x200))
-
-/*!
- * Addresses for NFC SPARE BUFFER Spare area 0
- */
-#define SPARE_AREA0 ((u16 *)(NFC_AXI_BASE_ADDR + 0x1000))
-#define SPARE_LEN 64
-#define SPARE_COUNT 8
-#define SPARE_SIZE (SPARE_LEN * SPARE_COUNT)
-
-#define NFC_SPAS_WIDTH 8
-#define NFC_SPAS_SHIFT 16
-
-#define IS_4BIT_ECC \
-( \
- is_soc_rev(CHIP_REV_2_0) >= 0 ? \
- !((raw_read(NFC_CONFIG2) & NFC_ECC_MODE_4) >> 6) : \
- ((raw_read(NFC_CONFIG2) & NFC_ECC_MODE_4) >> 6) \
-)
-
-#define NFC_SET_SPAS(v) \
- raw_write((((raw_read(NFC_CONFIG2) & \
- NFC_FIELD_RESET(NFC_SPAS_WIDTH, NFC_SPAS_SHIFT)) | ((v) << 16))), \
- NFC_CONFIG2)
-
-#define NFC_SET_ECC_MODE(v) \
-do { \
- if (is_soc_rev(CHIP_REV_2_0) >= 0) { \
- if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \
- raw_write(((raw_read(NFC_CONFIG2) & \
- NFC_ECC_MODE_MASK) | \
- NFC_ECC_MODE_4), NFC_CONFIG2); \
- else \
- raw_write(((raw_read(NFC_CONFIG2) & \
- NFC_ECC_MODE_MASK) & \
- NFC_ECC_MODE_8), NFC_CONFIG2); \
- } else { \
- if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \
- raw_write(((raw_read(NFC_CONFIG2) & \
- NFC_ECC_MODE_MASK) & \
- NFC_ECC_MODE_8), NFC_CONFIG2); \
- else \
- raw_write(((raw_read(NFC_CONFIG2) & \
- NFC_ECC_MODE_MASK) | \
- NFC_ECC_MODE_4), NFC_CONFIG2); \
- } \
-} while (0)
-
-#define WRITE_NFC_IP_REG(val, reg) \
- do { \
- raw_write(NFC_IPC_CREQ, NFC_IPC); \
- while (!((raw_read(NFC_IPC) & NFC_IPC_ACK)>>1)) \
- ; \
- raw_write(val, reg); \
- raw_write(0, NFC_IPC); \
- } while (0)
-
-#define GET_NFC_ECC_STATUS() raw_read(REG_NFC_ECC_STATUS_RESULT);
-
-/*!
- * Set 1 to specific operation bit, rest to 0 in LAUNCH_NFC Register for
- * Specific operation
- */
-#define NFC_CMD 0x1
-#define NFC_ADDR 0x2
-#define NFC_INPUT 0x4
-#define NFC_OUTPUT 0x8
-#define NFC_ID 0x10
-#define NFC_STATUS 0x20
-#define NFC_AUTO_PROG 0x40
-#define NFC_AUTO_READ 0x80
-#define NFC_AUTO_ERASE 0x200
-#define NFC_COPY_BACK_0 0x400
-#define NFC_COPY_BACK_1 0x800
-#define NFC_AUTO_STATE 0x1000
-
-/* Bit Definitions for NFC_IPC*/
-#define NFC_OPS_STAT (1 << 31)
-#define NFC_OP_DONE (1 << 30)
-#define NFC_RB (1 << 28)
-#define NFC_PS_WIDTH 2
-#define NFC_PS_SHIFT 0
-#define NFC_PS_512 0
-#define NFC_PS_2K 1
-#define NFC_PS_4K 2
-
-
-#define NFC_ONE_CYCLE (1 << 2)
-#define NFC_INT_MSK (1 << 15)
-#define NFC_AUTO_PROG_DONE_MSK (1 << 14)
-#define NFC_NUM_ADDR_PHASE1_WIDTH 2
-#define NFC_NUM_ADDR_PHASE1_SHIFT 12
-#define NFC_NUM_ADDR_PHASE0_WIDTH 1
-#define NFC_NUM_ADDR_PHASE0_SHIFT 5
-#define NFC_ONE_LESS_PHASE1 0
-#define NFC_TWO_LESS_PHASE1 1
-#define NFC_FLASH_ADDR_SHIFT 0
-#define NFC_UNLOCK_END_ADDR_SHIFT 16
-
-/* Bit definition for NFC_CONFIGRATION_1 */
-#define NFC_SP_EN (1 << 0)
-#define NFC_CE (1 << 1)
-#define NFC_RST (1 << 2)
-#define NFC_ECC_EN (1 << 3)
-
-#define NFC_FIELD_RESET(width, shift) (~(((1 << (width)) - 1) << (shift)))
-
-#define NFC_RBA_SHIFT 4
-#define NFC_RBA_WIDTH 3
-
-#define NFC_ITERATION_SHIFT 8
-#define NFC_ITERATION_WIDTH 4
-#define NFC_ACTIVE_CS_SHIFT 12
-#define NFC_ACTIVE_CS_WIDTH 3
-/* bit definition for CONFIGRATION3 */
-#define NFC_NO_SDMA (1 << 20)
-#define NFC_FMP_SHIFT 16
-#define NFC_FMP_WIDTH 4
-#define NFC_RBB_MODE (1 << 15)
-#define NFC_NUM_OF_DEVICES_SHIFT 12
-#define NFC_NUM_OF_DEVICES_WIDTH 4
-#define NFC_DMA_MODE_SHIFT 11
-#define NFC_DMA_MODE_WIDTH 1
-#define NFC_SBB_SHIFT 8
-#define NFC_SBB_WIDTH 3
-#define NFC_BIG (1 << 7)
-#define NFC_SB2R_SHIFT 4
-#define NFC_SB2R_WIDTH 3
-#define NFC_FW_SHIFT 3
-#define NFC_FW_WIDTH 1
-#define NFC_TOO (1 << 2)
-#define NFC_ADD_OP_SHIFT 0
-#define NFC_ADD_OP_WIDTH 2
-#define NFC_FW_8 1
-#define NFC_FW_16 0
-#define NFC_ST_CMD_SHITF 24
-#define NFC_ST_CMD_WIDTH 8
-
-#define NFC_PPB_32 (0 << 7)
-#define NFC_PPB_64 (1 << 7)
-#define NFC_PPB_128 (2 << 7)
-#define NFC_PPB_256 (3 << 7)
-#define NFC_PPB_RESET (~(3 << 7))
-
-#define NFC_BLS_LOCKED (0 << 6)
-#define NFC_BLS_LOCKED_DEFAULT (1 << 6)
-#define NFC_BLS_UNLCOKED (2 << 6)
-#define NFC_BLS_RESET (~(3 << 16))
-#define NFC_WPC_LOCK_TIGHT 1
-#define NFC_WPC_LOCK (1 << 1)
-#define NFC_WPC_UNLOCK (1 << 2)
-#define NFC_WPC_RESET (~(7))
-#define NFC_ECC_MODE_4 (1 << 6)
-#define NFC_ECC_MODE_8 (~(1 << 6))
-#define NFC_ECC_MODE_MASK (~(1 << 6))
-#define NFC_SPAS_16 8
-#define NFC_SPAS_64 32
-#define NFC_SPAS_128 64
-#define NFC_SPAS_112 56
-#define NFC_SPAS_218 109
-#define NFC_IPC_CREQ (1 << 0)
-#define NFC_IPC_ACK (1 << 1)
-
-#define REG_NFC_OPS_STAT NFC_IPC
-#define REG_NFC_INTRRUPT NFC_CONFIG2
-#define REG_NFC_FLASH_ADDR NFC_FLASH_ADDR0
-#define REG_NFC_FLASH_CMD NFC_FLASH_CMD
-#define REG_NFC_OPS LAUNCH_NFC
-#define REG_NFC_SET_RBA NFC_CONFIG1
-#define REG_NFC_RB NFC_IPC
-#define REG_NFC_ECC_EN NFC_CONFIG2
-#define REG_NFC_ECC_STATUS_RESULT NFC_ECC_STATUS_RESULT
-#define REG_NFC_CE NFC_CONFIG1
-#define REG_NFC_RST NFC_CONFIG1
-#define REG_NFC_PPB NFC_CONFIG2
-#define REG_NFC_SP_EN NFC_CONFIG1
-#define REG_NFC_BLS NFC_WRPROT
-#define REG_UNLOCK_BLK_ADD0 NFC_WRPROT_UNLOCK_BLK_ADD0
-#define REG_UNLOCK_BLK_ADD1 NFC_WRPROT_UNLOCK_BLK_ADD1
-#define REG_UNLOCK_BLK_ADD2 NFC_WRPROT_UNLOCK_BLK_ADD2
-#define REG_UNLOCK_BLK_ADD3 NFC_WRPROT_UNLOCK_BLK_ADD3
-#define REG_NFC_WPC NFC_WRPROT
-#define REG_NFC_ONE_CYCLE NFC_CONFIG2
-
-/* NFC V3 Specific MACRO functions definitions */
-#define raw_write(v, a) __raw_writel(v, a)
-#define raw_read(a) __raw_readl(a)
-
-/* Explcit ack ops status (if any), before issue of any command */
-#define ACK_OPS \
- raw_write((raw_read(REG_NFC_OPS_STAT) & ~NFC_OPS_STAT), \
- REG_NFC_OPS_STAT);
-
-/* Set RBA buffer id*/
-#define NFC_SET_RBA(val) \
- raw_write((raw_read(REG_NFC_SET_RBA) & \
- (NFC_FIELD_RESET(NFC_RBA_WIDTH, NFC_RBA_SHIFT))) | \
- ((val) << NFC_RBA_SHIFT), REG_NFC_SET_RBA);
-
-#define NFC_SET_PS(val) \
- raw_write((raw_read(NFC_CONFIG2) & \
- (NFC_FIELD_RESET(NFC_PS_WIDTH, NFC_PS_SHIFT))) | \
- ((val) << NFC_PS_SHIFT), NFC_CONFIG2);
-
-#define UNLOCK_ADDR(start_addr, end_addr) \
-{ \
- int i = 0; \
- for (; i < NAND_MAX_CHIPS; i++) \
- raw_write(start_addr | \
- (end_addr << NFC_UNLOCK_END_ADDR_SHIFT), \
- REG_UNLOCK_BLK_ADD0 + (i << 2)); \
-}
-
-#define NFC_SET_NFC_ACTIVE_CS(val) \
- raw_write((raw_read(NFC_CONFIG1) & \
- (NFC_FIELD_RESET(NFC_ACTIVE_CS_WIDTH, NFC_ACTIVE_CS_SHIFT))) | \
- ((val) << NFC_ACTIVE_CS_SHIFT), NFC_CONFIG1);
-
-#define NFC_GET_MAXCHIP_SP() 8
-
-#define NFC_SET_BLS(val) ((raw_read(REG_NFC_BLS) & NFC_BLS_RESET) | val)
-#define NFC_SET_WPC(val) ((raw_read(REG_NFC_WPC) & NFC_WPC_RESET) | val)
-#define CHECK_NFC_RB (raw_read(REG_NFC_RB) & NFC_RB)
-
-#define NFC_SET_NFC_NUM_ADDR_PHASE1(val) \
- raw_write((raw_read(NFC_CONFIG2) & \
- (NFC_FIELD_RESET(NFC_NUM_ADDR_PHASE1_WIDTH, \
- NFC_NUM_ADDR_PHASE1_SHIFT))) | \
- ((val) << NFC_NUM_ADDR_PHASE1_SHIFT), NFC_CONFIG2);
-
-#define NFC_SET_NFC_NUM_ADDR_PHASE0(val) \
- raw_write((raw_read(NFC_CONFIG2) & \
- (NFC_FIELD_RESET(NFC_NUM_ADDR_PHASE0_WIDTH, \
- NFC_NUM_ADDR_PHASE0_SHIFT))) | \
- ((val) << NFC_NUM_ADDR_PHASE0_SHIFT), NFC_CONFIG2);
-
-#define NFC_SET_NFC_ITERATION(val) \
- raw_write((raw_read(NFC_CONFIG1) & \
- (NFC_FIELD_RESET(NFC_ITERATION_WIDTH, NFC_ITERATION_SHIFT))) | \
- ((val) << NFC_ITERATION_SHIFT), NFC_CONFIG1);
-
-#define NFC_SET_FW(val) \
- raw_write((raw_read(NFC_CONFIG3) & \
- (NFC_FIELD_RESET(NFC_FW_WIDTH, NFC_FW_SHIFT))) | \
- ((val) << NFC_FW_SHIFT), NFC_CONFIG3);
-
-#define NFC_SET_NUM_OF_DEVICE(val) \
- raw_write((raw_read(NFC_CONFIG3) & \
- (NFC_FIELD_RESET(NFC_NUM_OF_DEVICES_WIDTH, \
- NFC_NUM_OF_DEVICES_SHIFT))) | \
- ((val) << NFC_NUM_OF_DEVICES_SHIFT), NFC_CONFIG3);
-
-#define NFC_SET_ADD_OP_MODE(val) \
- raw_write((raw_read(NFC_CONFIG3) & \
- (NFC_FIELD_RESET(NFC_ADD_OP_WIDTH, NFC_ADD_OP_SHIFT))) | \
- ((val) << NFC_ADD_OP_SHIFT), NFC_CONFIG3);
-
-#define NFC_SET_ADD_CS_MODE(val) \
-{ \
- NFC_SET_ADD_OP_MODE(val); \
- NFC_SET_NUM_OF_DEVICE(this->numchips - 1); \
-}
-
-#define NFC_SET_ST_CMD(val) \
- raw_write((raw_read(NFC_CONFIG2) & \
- (NFC_FIELD_RESET(NFC_ST_CMD_WIDTH, \
- NFC_ST_CMD_SHITF))) | \
- ((val) << NFC_ST_CMD_SHITF), NFC_CONFIG2);
-
-#define NFMS_NF_DWIDTH 0
-#define NFMS_NF_PG_SZ 1
-#define NFC_CMD_1_SHIFT 8
-
-#define NUM_OF_ADDR_CYCLE ((ffs(~(info->page_mask)) - 1) >> 3)
-
-/*should set the fw,ps,spas,ppb*/
-#define NFC_SET_NFMS(v) \
-do { \
- if (!(v)) \
- NFC_SET_FW(NFC_FW_8); \
- if (((v) & (1 << NFMS_NF_DWIDTH))) \
- NFC_SET_FW(NFC_FW_16); \
- if (((v) & (1 << NFMS_NF_PG_SZ))) { \
- if (IS_2K_PAGE_NAND) { \
- NFC_SET_PS(NFC_PS_2K); \
- NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE); \
- NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_TWO_LESS_PHASE1); \
- } else if (IS_4K_PAGE_NAND) { \
- NFC_SET_PS(NFC_PS_4K); \
- NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE); \
- NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_TWO_LESS_PHASE1); \
- } else { \
- NFC_SET_PS(NFC_PS_512); \
- NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE - 1); \
- NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_ONE_LESS_PHASE1); \
- } \
- NFC_SET_ADD_CS_MODE(1); \
- NFC_SET_SPAS(GET_NAND_OOB_SIZE >> 1); \
- NFC_SET_ECC_MODE(GET_NAND_OOB_SIZE >> 1); \
- NFC_SET_ST_CMD(0x70); \
- raw_write(raw_read(NFC_CONFIG3) | NFC_NO_SDMA, NFC_CONFIG3); \
- raw_write(raw_read(NFC_CONFIG3) | NFC_RBB_MODE, NFC_CONFIG3); \
- } \
-} while (0)
-
-#define READ_PAGE() send_read_page(0)
-#define PROG_PAGE() send_prog_page(0)
-
-#endif /* __MXC_NAND_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __MACH_MX53_IOMUX_H__
-#define __MACH_MX53_IOMUX_H__
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mx53.h>
-#include <asm/arch/mx53_pins.h>
-
-/*!
- * @file mach-mx53/iomux.h
- *
- * @brief I/O Muxing control definitions and functions
- *
- * @ingroup GPIO_MX53
- */
-
-typedef unsigned int iomux_pin_name_t;
-
-/*!
- * various IOMUX output functions
- */
-typedef enum iomux_config {
- IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */
- IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */
- IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */
- IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */
- IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */
- IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */
- IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */
- IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */
- IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */
- IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
-} iomux_pin_cfg_t;
-
-/*!
- * various IOMUX pad functions
- */
-typedef enum iomux_pad_config {
- PAD_CTL_SRE_SLOW = 0x0 << 0,
- PAD_CTL_SRE_FAST = 0x1 << 0,
- PAD_CTL_DRV_LOW = 0x0 << 1,
- PAD_CTL_DRV_MEDIUM = 0x1 << 1,
- PAD_CTL_DRV_HIGH = 0x2 << 1,
- PAD_CTL_DRV_MAX = 0x3 << 1,
- PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,
- PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,
- PAD_CTL_100K_PD = 0x0 << 4,
- PAD_CTL_47K_PU = 0x1 << 4,
- PAD_CTL_100K_PU = 0x2 << 4,
- PAD_CTL_22K_PU = 0x3 << 4,
- PAD_CTL_PUE_KEEPER = 0x0 << 6,
- PAD_CTL_PUE_PULL = 0x1 << 6,
- PAD_CTL_PKE_NONE = 0x0 << 7,
- PAD_CTL_PKE_ENABLE = 0x1 << 7,
- PAD_CTL_HYS_NONE = 0x0 << 8,
- PAD_CTL_HYS_ENABLE = 0x1 << 8,
- PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,
- PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,
- PAD_CTL_DRV_VOT_LOW = 0x0 << 13,
- PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,
-} iomux_pad_config_t;
-
-/*!
- * various IOMUX input select register index
- */
-typedef enum iomux_input_select {
- MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
- MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
- MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_I,
- MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_I,
- MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
- MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
- MUX_IN_CAN1_IPP_IND_CANRX_SELECT_INPUT, /*0x760*/
- MUX_IN_CAN2_IPP_IND_CANRX_SELECT_INPUT,
- MUX_IN_CCM_IPP_ASRC_EXT_SELECT_INPUT,
- MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
- MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
- MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
- MUX_IN_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
- MUX_IN_CCM_PLL4_BYPASS_CLK_SELECT_INPUT,
- MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, /*0x780*/
- MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
- MUX_IN_CSPI_IPP_IND_SS_B_4_SELECT_INPUT,
- MUX_IN_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
- MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
- MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
- MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
- MUX_IN_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
- MUX_IN_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT, /*0x7B0*/
- MUX_IN_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT,
- MUX_IN_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
- MUX_IN_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
- MUX_IN_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
- MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
- MUX_IN_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT,
- MUX_IN_ESAI1_IPP_IND_FSR_SELECT_INPUT,
- MUX_IN_ESAI1_IPP_IND_FST_SELECT_INPUT,
- MUX_IN_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
- MUX_IN_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
- MUX_IN_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
- MUX_IN_ESAI1_IPP_IND_SCKT_SELECT_INPUT, /*0x7E0*/
- MUX_IN_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
- MUX_IN_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
- MUX_IN_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
- MUX_IN_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
- MUX_IN_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
- MUX_IN_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
- MUX_IN_ESDHC1_IPP_WP_ON_SELECT_INPUT,
- MUX_IN_FEC_FEC_COL_SELECT_INPUT, /*0x800*/
- MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
- MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
- MUX_IN_FIRI_IPP_IND_RXD_SELECT_INPUT,
- MUX_IN_GPC_PMIC_RDY_SELECT_INPUT,
- MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
- MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
- MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
- MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
- MUX_IN_I2C3_IPP_SCL_IN_SELECT_INPUT,
- MUX_IN_I2C3_IPP_SDA_IN_SELECT_INPUT,
- MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
- MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
- MUX_IN_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
- MUX_IN_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT,
- MUX_IN_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_COL_5_SELECT_INPUT, /*0x840*/
- MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
- MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
- MUX_IN_MLB_MLBCLK_IN_SELECT_INPUT,
- MUX_IN_MLB_MLBDAT_IN_SELECT_INPUT,
- MUX_IN_MLB_MLBSIG_IN_SELECT_INPUT,
- MUX_IN_OWIRE_BATTERY_LINE_IN_SELECT_INPUT,
- MUX_IN_SDMA_EVENTS_14_SELECT_INPUT,
- MUX_IN_SDMA_EVENTS_15_SELECT_INPUT,
- MUX_IN_SPDIF_SPDIF_IN1_SELECT_INPUT, /*0x870*/
- MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_UART4_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_UART5_IPP_UART_RTS_B_SELECT_INPUT,
- MUX_IN_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT,
- MUX_IN_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT,
-} iomux_input_select_t;
-
-/*!
- * various IOMUX input functions
- */
-typedef enum iomux_input_config {
- INPUT_CTL_PATH0 = 0x0,
- INPUT_CTL_PATH1,
- INPUT_CTL_PATH2,
- INPUT_CTL_PATH3,
- INPUT_CTL_PATH4,
- INPUT_CTL_PATH5,
- INPUT_CTL_PATH6,
- INPUT_CTL_PATH7,
-} iomux_input_config_t;
-
-struct mxc_iomux_pin_cfg {
- iomux_pin_name_t pin;
- u8 mux_mode;
- u16 pad_cfg;
- u8 in_select;
- u8 in_mode;
-};
-
-/*!
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param config config as defined in \b #iomux_pin_ocfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-
-/*!
- * Release ownership for an IO pin
- *
- * @param pin a name defined by \b iomux_pin_name_t
- * @param config config as defined in \b #iomux_pin_ocfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-
-/*!
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @param config the ORed value of elements defined in
- * \b #iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
-
-/*!
- * This function gets the current pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in \b #iomux_pin_name_t
- * @return current pad value
- */
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
-
-/*!
- * This function configures input path.
- *
- * @param input index of input select register as defined in
- * \b #iomux_input_select_t
- * @param config the binary value of elements defined in \b #iomux_input_config_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-
-#endif /* __MACH_MX53_IOMUX_H__ */
+++ /dev/null
-/*
- * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __ARM_ARCH_MMU_H
-#define __ARM_ARCH_MMU_H
-
-#include <linux/types.h>
-
-/*
- * Translation Table Base Bit Masks
- */
-#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
-
-/*
- * Domain Access Control Bit Masks
- */
-#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
-#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
-#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
-
-struct ARM_MMU_FIRST_LEVEL_FAULT {
- unsigned int id:2;
- unsigned int sbz:30;
-};
-
-#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
-
-struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
- unsigned int id:2;
- unsigned int imp:2;
- unsigned int domain:4;
- unsigned int sbz:1;
- unsigned int base_address:23;
-};
-
-#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
-
-struct ARM_MMU_FIRST_LEVEL_SECTION {
- unsigned int id:2;
- unsigned int b:1;
- unsigned int c:1;
- unsigned int imp:1;
- unsigned int domain:4;
- unsigned int sbz0:1;
- unsigned int ap:2;
- unsigned int sbz1:8;
- unsigned int base_address:12;
-};
-
-#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
-
-struct ARM_MMU_FIRST_LEVEL_RESERVED {
- unsigned int id:2;
- unsigned int sbz:30;
-};
-
-#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
-
-#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
- (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
-
-#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
-
-#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
- cacheable, bufferable, perm) \
- { \
- register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
- desc.word = 0; \
- desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
- desc.section.domain = 0; \
- desc.section.c = (cacheable); \
- desc.section.b = (bufferable); \
- desc.section.ap = (perm); \
- desc.section.base_address = (actual_base); \
- *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
- = desc.word; \
- }
-
-#define X_ARM_MMU_SECTION(abase, vbase, size, cache, buff, access) \
- { \
- int i; int j = abase; int k = vbase; \
- for (i = size; i > 0 ; i--, j++, k++) \
- ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
- }
-
-union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
- unsigned long word;
- struct ARM_MMU_FIRST_LEVEL_FAULT fault;
- struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
- struct ARM_MMU_FIRST_LEVEL_SECTION section;
- struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
-};
-
-#define ARM_UNCACHEABLE 0
-#define ARM_CACHEABLE 1
-#define ARM_UNBUFFERABLE 0
-#define ARM_BUFFERABLE 1
-
-#define ARM_ACCESS_PERM_NONE_NONE 0
-#define ARM_ACCESS_PERM_RO_NONE 0
-#define ARM_ACCESS_PERM_RO_RO 0
-#define ARM_ACCESS_PERM_RW_NONE 1
-#define ARM_ACCESS_PERM_RW_RO 2
-#define ARM_ACCESS_PERM_RW_RW 3
-
-/*
- * Initialization for the Domain Access Control Register
- */
-#define ARM_ACCESS_DACR_DEFAULT ( \
- ARM_ACCESS_TYPE_MANAGER(0) | \
- ARM_ACCESS_TYPE_NO_ACCESS(1) | \
- ARM_ACCESS_TYPE_NO_ACCESS(2) | \
- ARM_ACCESS_TYPE_NO_ACCESS(3) | \
- ARM_ACCESS_TYPE_NO_ACCESS(4) | \
- ARM_ACCESS_TYPE_NO_ACCESS(5) | \
- ARM_ACCESS_TYPE_NO_ACCESS(6) | \
- ARM_ACCESS_TYPE_NO_ACCESS(7) | \
- ARM_ACCESS_TYPE_NO_ACCESS(8) | \
- ARM_ACCESS_TYPE_NO_ACCESS(9) | \
- ARM_ACCESS_TYPE_NO_ACCESS(10) | \
- ARM_ACCESS_TYPE_NO_ACCESS(11) | \
- ARM_ACCESS_TYPE_NO_ACCESS(12) | \
- ARM_ACCESS_TYPE_NO_ACCESS(13) | \
- ARM_ACCESS_TYPE_NO_ACCESS(14) | \
- ARM_ACCESS_TYPE_NO_ACCESS(15))
-
-/*
- * Translate the virtual address of ram space to physical address
- * It is dependent on the implementation of mmu_init
- */
-inline unsigned long iomem_to_phys(unsigned long virt)
-{
- if (virt >= 0xB0000000)
- return (unsigned long)((virt - 0xB0000000) + PHYS_SDRAM_1);
-
- return (unsigned long)virt;
-}
-
-/*
- * remap the physical address of ram space to uncacheable virtual address space
- * It is dependent on the implementation of hal_mmu_init
- */
-void *__ioremap(unsigned long offset, size_t size, unsigned long flags)
-{
- if (1 == flags) {
- if (offset >= PHYS_SDRAM_1 &&
- offset < (unsigned long)(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
- return (void *)((offset - PHYS_SDRAM_1) + 0xB0000000);
- else
- return NULL;
- } else
- return (void *)offset;
-}
-
-/*
- * Remap the physical address of ram space to uncacheable virtual address space
- * It is dependent on the implementation of hal_mmu_init
- */
-void __iounmap(void *addr)
-{
- return;
-}
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __ASM_ARCH_MXC_MX53_H__
-#define __ASM_ARCH_MXC_MX53_H__
-
-#define __REG(x) (*((volatile u32 *)(x)))
-#define __REG16(x) (*((volatile u16 *)(x)))
-#define __REG8(x) (*((volatile u8 *)(x)))
-
-/*
- * SATA
- */
-#define SATA_BASE_ADDR 0x10000000
-
-/*
- * IRAM
- */
-#define IRAM_BASE_ADDR 0xF8000000 /* internal ram */
-#define IRAM_PARTITIONS 16
-#define IRAM_SIZE (IRAM_PARTITIONS*SZ_8K) /* 128KB */
-
-/*
- * NFC
- */
-#define NFC_BASE_ADDR_AXI 0xF7FF0000 /* NAND flash AXI */
-#define NFC_AXI_SIZE SZ_64K
-
-#define TZIC_BASE_ADDR 0x0FFFC000
-
-#define DEBUG_BASE_ADDR 0x40000000
-#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
-#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
-#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
-#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
-#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
-#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
-#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
-#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
-
-/*
- * SPBA global module enabled #0
- */
-#define SPBA0_BASE_ADDR 0x50000000
-
-#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
-#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
-#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
-#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
-#define ESAI_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
-#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
-#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
-#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
-#define ASRC_BASE_ADDR (SPBA0_BASE_ADDR + 0x0002C000)
-#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
-#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
-
-/*!
- * defines for SPBA modules
- */
-#define SPBA_SDHC1 0x04
-#define SPBA_SDHC2 0x08
-#define SPBA_UART3 0x0C
-#define SPBA_CSPI1 0x10
-#define SPBA_SSI2 0x14
-#define SPBA_ESAI 0x18
-#define SPBA_SDHC3 0x20
-#define SPBA_SDHC4 0x24
-#define SPBA_SPDIF 0x28
-#define SPBA_ASRC 0x2C
-#define SPBA_ATA 0x30
-#define SPBA_CTRL 0x3C
-
-/*
- * AIPS 1
- */
-#define AIPS1_BASE_ADDR 0x53F00000
-
-#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
-#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
-#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
-#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
-#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
-#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
-#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
-#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
-#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
-#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
-#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
-#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
-#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
-#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
-#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
-#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
-#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
-#define CAN1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C8000)
-#define CAN2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000CC000)
-#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
-#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
-#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
-#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
-#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
-#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
-#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E8000)
-#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
-#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
-
-/*
- * AIPS 2
- */
-#define AIPS2_BASE_ADDR 0x63F00000
-
-#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
-#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
-#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
-#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
-#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
-#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
-#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
-#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
-#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
-#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
-#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
-#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
-#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
-#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
-#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
-#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
-#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
-#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
-#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
-#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
-#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
-#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
-#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
-#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
-#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
-#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
-#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
-#define MLB_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
-#define SSI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
-#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
-#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
-#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
-#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
-#define PTP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000FC000)
-
-/*
- * Memory regions and CS
- */
-#define CSD0_BASE_ADDR 0x70000000
-#define CSD1_BASE_ADDR 0xB0000000
-
-/*
- * Interrupt numbers
- */
-#define MXC_INT_BASE 0
-#define MXC_INT_RESV0 0
-#define MXC_INT_MMC_SDHC1 1
-#define MXC_INT_MMC_SDHC2 2
-#define MXC_INT_MMC_SDHC3 3
-#define MXC_INT_MMC_SDHC4 4
-#define MXC_INT_DAP 5
-#define MXC_INT_SDMA 6
-#define MXC_INT_IOMUX 7
-#define MXC_INT_NFC 8
-#define MXC_INT_VPU 9
-#define MXC_INT_IPU_ERR 10
-#define MXC_INT_IPU_SYN 11
-#define MXC_INT_GPU 12
-#define MXC_INT_UART4 13
-#define MXC_INT_USB_H1 14
-#define MXC_INT_EMI 15
-#define MXC_INT_USB_H2 16
-#define MXC_INT_USB_H3 17
-#define MXC_INT_USB_OTG 18
-#define MXC_INT_SAHARA_H0 19
-#define MXC_INT_SAHARA_H1 20
-#define MXC_INT_SCC_SMN 21
-#define MXC_INT_SCC_STZ 22
-#define MXC_INT_SCC_SCM 23
-#define MXC_INT_SRTC_NTZ 24
-#define MXC_INT_SRTC_TZ 25
-#define MXC_INT_RTIC 26
-#define MXC_INT_CSU 27
-#define MXC_INT_SATA 28
-#define MXC_INT_SSI1 29
-#define MXC_INT_SSI2 30
-#define MXC_INT_UART1 31
-#define MXC_INT_UART2 32
-#define MXC_INT_UART3 33
-#define MXC_INT_RTC 34
-#define MXC_INT_PTP 35
-#define MXC_INT_CSPI1 36
-#define MXC_INT_CSPI2 37
-#define MXC_INT_CSPI 38
-#define MXC_INT_GPT 39
-#define MXC_INT_EPIT1 40
-#define MXC_INT_EPIT2 41
-#define MXC_INT_GPIO1_INT7 42
-#define MXC_INT_GPIO1_INT6 43
-#define MXC_INT_GPIO1_INT5 44
-#define MXC_INT_GPIO1_INT4 45
-#define MXC_INT_GPIO1_INT3 46
-#define MXC_INT_GPIO1_INT2 47
-#define MXC_INT_GPIO1_INT1 48
-#define MXC_INT_GPIO1_INT0 49
-#define MXC_INT_GPIO1_LOW 50
-#define MXC_INT_GPIO1_HIGH 51
-#define MXC_INT_GPIO2_LOW 52
-#define MXC_INT_GPIO2_HIGH 53
-#define MXC_INT_GPIO3_LOW 54
-#define MXC_INT_GPIO3_HIGH 55
-#define MXC_INT_GPIO4_LOW 56
-#define MXC_INT_GPIO4_HIGH 57
-#define MXC_INT_WDOG1 58
-#define MXC_INT_WDOG2 59
-#define MXC_INT_KPP 60
-#define MXC_INT_PWM1 61
-#define MXC_INT_I2C1 62
-#define MXC_INT_I2C2 63
-#define MXC_INT_I2C3 64
-#define MXC_INT_MLB 65
-#define MXC_INT_ASRC 66
-#define MXC_INT_SPDIF 67
-#define MXC_INT_RESV1 68
-#define MXC_INT_IIM 69
-#define MXC_INT_ATA 70
-#define MXC_INT_CCM1 71
-#define MXC_INT_CCM2 72
-#define MXC_INT_GPC1 73
-#define MXC_INT_GPC2 74
-#define MXC_INT_SRC 75
-#define MXC_INT_NM 76
-#define MXC_INT_PMU 77
-#define MXC_INT_CTI_IRQ 78
-#define MXC_INT_CTI1_TG0 79
-#define MXC_INT_CTI1_TG1 80
-#define MXC_INT_ESAI 81
-#define MXC_INT_CAN1 82
-#define MXC_INT_CAN2 83
-#define MXC_INT_GPU2_IRQ 84
-#define MXC_INT_GPU2_BUSY 85
-#define MXC_INT_UART5 86
-#define MXC_INT_FEC 87
-#define MXC_INT_OWIRE 88
-#define MXC_INT_CTI1_TG2 89
-#define MXC_INT_SJC 90
-#define MXC_INT_RESV2 91
-#define MXC_INT_TVE 92
-#define MXC_INT_FIRI 93
-#define MXC_INT_PWM2 94
-#define MXC_INT_RESV3 95
-#define MXC_INT_SSI3 96
-#define MXC_INT_RESV4 97
-#define MXC_INT_CTI1_TG3 98
-#define MXC_INT_RESV5 99
-#define MXC_INT_VPU_IDLE 100
-#define MXC_INT_EMI_NFC 101
-#define MXC_INT_GPU_IDLE 102
-#define MXC_INT_GPIO5_LOW 103
-#define MXC_INT_GPIO5_HIGH 104
-#define MXC_INT_GPIO6_LOW 105
-#define MXC_INT_GPIO6_HIGH 106
-#define MXC_INT_GPIO7_LOW 107
-#define MXC_INT_GPIO7_HIGH 108
-
-/* gpio and gpio based interrupt handling */
-#define GPIO_DR 0x00
-#define GPIO_GDIR 0x04
-#define GPIO_PSR 0x08
-#define GPIO_ICR1 0x0C
-#define GPIO_ICR2 0x10
-#define GPIO_IMR 0x14
-#define GPIO_ISR 0x18
-#define GPIO_INT_LOW_LEV 0x0
-#define GPIO_INT_HIGH_LEV 0x1
-#define GPIO_INT_RISE_EDGE 0x2
-#define GPIO_INT_FALL_EDGE 0x3
-#define GPIO_INT_NONE 0x4
-
-#define CLKCTL_CCR 0x00
-#define CLKCTL_CCDR 0x04
-#define CLKCTL_CSR 0x08
-#define CLKCTL_CCSR 0x0C
-#define CLKCTL_CACRR 0x10
-#define CLKCTL_CBCDR 0x14
-#define CLKCTL_CBCMR 0x18
-#define CLKCTL_CSCMR1 0x1C
-#define CLKCTL_CSCMR2 0x20
-#define CLKCTL_CSCDR1 0x24
-#define CLKCTL_CS1CDR 0x28
-#define CLKCTL_CS2CDR 0x2C
-#define CLKCTL_CDCDR 0x30
-#define CLKCTL_CHSCDR 0x34
-#define CLKCTL_CSCDR2 0x38
-#define CLKCTL_CSCDR3 0x3C
-#define CLKCTL_CSCDR4 0x40
-#define CLKCTL_CWDR 0x44
-#define CLKCTL_CDHIPR 0x48
-#define CLKCTL_CDCR 0x4C
-#define CLKCTL_CTOR 0x50
-#define CLKCTL_CLPCR 0x54
-#define CLKCTL_CISR 0x58
-#define CLKCTL_CIMR 0x5C
-#define CLKCTL_CCOSR 0x60
-#define CLKCTL_CGPR 0x64
-#define CLKCTL_CCGR0 0x68
-#define CLKCTL_CCGR1 0x6C
-#define CLKCTL_CCGR2 0x70
-#define CLKCTL_CCGR3 0x74
-#define CLKCTL_CCGR4 0x78
-#define CLKCTL_CCGR5 0x7C
-#define CLKCTL_CCGR6 0x80
-#define CLKCTL_CCGR7 0x84
-#define CLKCTL_CMEOR 0x88
-
-#define CHIP_REV_1_0 0x10
-#define PLATFORM_ICGC 0x14
-
-/* Assuming 24MHz input clock with doubler ON */
-/* MFI PDF */
-#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
-#define DP_MFD_850 (48 - 1)
-#define DP_MFN_850 41
-
-#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
-#define DP_MFD_800 (3 - 1)
-#define DP_MFN_800 1
-
-#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
-#define DP_MFD_700 (24 - 1)
-#define DP_MFN_700 7
-
-#define DP_OP_600 ((6 << 4) + ((1 - 1) << 0))
-#define DP_MFD_600 (4 - 1)
-#define DP_MFN_600 1
-
-#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
-#define DP_MFD_665 (96 - 1)
-#define DP_MFN_665 89
-
-#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
-#define DP_MFD_532 (24 - 1)
-#define DP_MFN_532 13
-
-#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
-#define DP_MFD_400 (3 - 1)
-#define DP_MFN_400 1
-
-#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
-#define DP_MFD_216 (4 - 1)
-#define DP_MFN_216 3
-
-#define PLL_DP_CTL 0x00
-#define PLL_DP_CONFIG 0x04
-#define PLL_DP_OP 0x08
-#define PLL_DP_MFD 0x0C
-#define PLL_DP_MFN 0x10
-#define PLL_DP_MFNMINUS 0x14
-#define PLL_DP_MFNPLUS 0x18
-#define PLL_DP_HFS_OP 0x1C
-#define PLL_DP_HFS_MFD 0x20
-#define PLL_DP_HFS_MFN 0x24
-#define PLL_DP_TOGC 0x28
-#define PLL_DP_DESTAT 0x2C
-
-#ifndef __ASSEMBLER__
-
-enum boot_device {
- WEIM_NOR_BOOT,
- ONE_NAND_BOOT,
- PATA_BOOT,
- SATA_BOOT,
- I2C_BOOT,
- SPI_NOR_BOOT,
- SD_BOOT,
- MMC_BOOT,
- NAND_BOOT,
- UNKNOWN_BOOT
-};
-
-enum mxc_clock {
- MXC_ARM_CLK = 0,
- MXC_PER_CLK,
- MXC_AHB_CLK,
- MXC_IPG_CLK,
- MXC_IPG_PERCLK,
- MXC_UART_CLK,
- MXC_CSPI_CLK,
- MXC_AXI_A_CLK,
- MXC_AXI_B_CLK,
- MXC_EMI_SLOW_CLK,
- MXC_DDR_CLK,
- MXC_ESDHC_CLK,
- MXC_ESDHC2_CLK,
- MXC_ESDHC3_CLK,
- MXC_ESDHC4_CLK,
- MXC_SATA_CLK
-};
-
-enum mxc_peri_clocks {
- MXC_UART1_BAUD,
- MXC_UART2_BAUD,
- MXC_UART3_BAUD,
- MXC_SSI1_BAUD,
- MXC_SSI2_BAUD,
- MXC_CSI_BAUD,
- MXC_MSTICK1_CLK,
- MXC_MSTICK2_CLK,
- MXC_SPI1_CLK,
- MXC_SPI2_CLK,
-};
-
-extern unsigned int mxc_get_clock(enum mxc_clock clk);
-extern unsigned int get_board_rev(void);
-extern int is_soc_rev(int rev);
-extern enum boot_device get_boot_device(void);
-
-#endif /* __ASSEMBLER__*/
-
-#endif /* __ASM_ARCH_MXC_MX53_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#ifndef __ASM_ARCH_MXC_MX53_PINS_H__
-#define __ASM_ARCH_MXC_MX53_PINS_H__
-
-/*!
- * @file arch-mxc/mx53_pins.h
- *
- * @brief MX53 I/O Pin List
- *
- * @ingroup GPIO_MX53
- */
-
-#ifndef __ASSEMBLY__
-
-/*!
- * @name IOMUX/PAD Bit field definitions
- */
-
-/*! @{ */
-
-/*!
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P | IO_I | GPIO_I | PAD_I | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 9 contains MUX_I used to identify the register
- * offset (0-based. base is IOMUX_module_base) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
- * similar field definitions are used for the pad control register.
- * For example, the MX53_PIN_GPIO_19 is defined in the enumeration:
- * ( (0x20 - MUX_I_START) << MUX_I)|( (0x348 - PAD_I_START) << PAD_I)
- * It means the mux control register is at register offset 0x20. The pad control
- * register offset is: 0x348 and also occupy the least significant bits
- * within the register.
- */
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I 0
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I 10
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent which
- * mux mode is for GPIO (0-based)
- */
-#define GPIO_I 21
-
-#define MUX_IO_P 29
-#define MUX_IO_I 24
-
-#define NON_GPIO_PORT 0x7
-#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
-#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
-
-#define NON_MUX_I PIN_TO_MUX_MASK
-#define NON_PAD_I PIN_TO_PAD_MASK
-#define MUX_I_START 0x0020
-#define PAD_I_START 0x348
-#define INPUT_CTL_START 0x730
-#define MUX_I_END (PAD_I_START - 4)
-
-#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
- (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
- ((mi) << MUX_I) | \
- ((pi - PAD_I_START) << PAD_I) | \
- ((ga) << GPIO_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
- _MXC_BUILD_PIN(gp, gi, ga, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
- _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
-#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
-#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
-
-/*! @} End IOMUX/PAD Bit field definitions */
-
-/*!
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX53 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-enum iomux_pins {
- MX53_PIN_GPIO_19 = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348),
- MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C),
- MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350),
- MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354),
- MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358),
- MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C),
- MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360),
- MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364),
- MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368),
- MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C),
- MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370),
- MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374),
- MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378),
- MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C),
- MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380),
- MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384),
- MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388),
- MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C),
- MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390),
- MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394),
- MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398),
- MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C),
- MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0),
- MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4),
- MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8),
- MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC),
- MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0),
- MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4),
- MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8),
- MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC),
- MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0),
- MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4),
- MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8),
- MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC),
- MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0),
- MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4),
- MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8),
- MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC),
- MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0),
- MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4),
- MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8),
- MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC),
- MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0),
- MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4),
- MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8),
- MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC),
- MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400),
- MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404),
- MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408),
- MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C),
- MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410),
- MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414),
- MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418),
- MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C),
- MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420),
- MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424),
- MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428),
- MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C),
- MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430),
- MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434),
- MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438),
- MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C),
- MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440),
- MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444),
- MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448),
- MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C),
- MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450),
- MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454),
- MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458),
- MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C),
- MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460),
- MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464),
- MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468),
- MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C),
- MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470),
- MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474),
- MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478),
- MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C),
- MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480),
- MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484),
- MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488),
- MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C),
- MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490),
- MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494),
- MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498),
- MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C),
- MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0),
- MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4),
- MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8),
- MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC),
- MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0),
- MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4),
- MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8),
- MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC),
- MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0),
- MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4),
- MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8),
- MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC),
- MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0),
- MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4),
- MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8),
- MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC),
- MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0),
- MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4),
- MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8),
- MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC),
- MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0),
- MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4),
- MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8),
- MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC),
- MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500),
- MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504),
- MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508),
- MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C),
- MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510),
- MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514),
- MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518),
- MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C),
- MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520),
- MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524),
- MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528),
- MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C),
- MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530),
- MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534),
- MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538),
- MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C),
- MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I),
- MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I),
- MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I),
- MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I),
- MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I),
- MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I),
- MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I),
- MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I),
- MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I),
- MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I),
- MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540),
- MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544),
- MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548),
- MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C),
- MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550),
- MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554),
- MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558),
- MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C),
- MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560),
- MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564),
- MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568),
- MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C),
- MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570),
- MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574),
- MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578),
- MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C),
- MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580),
- MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584),
- MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588),
- MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C),
- MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590),
- MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594),
- MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598),
- MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C),
- MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0),
- MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4),
- MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8),
- MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC),
- MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0),
- MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4),
- MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8),
- MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC),
- MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0),
- MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4),
- MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8),
- MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC),
- MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0),
- MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4),
- MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8),
- MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC),
- MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0),
- MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4),
- MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8),
- MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC),
- MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0),
- MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4),
- MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8),
- MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC),
- MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600),
- MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604),
- MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608),
- MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C),
- MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610),
- MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614),
- MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618),
- MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C),
- MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620),
- MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624),
- MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628),
- MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C),
- MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630),
- MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634),
- MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638),
- MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C),
- MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640),
- MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644),
- MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648),
- MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C),
- MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650),
- MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654),
- MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658),
- MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C),
- MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660),
- MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664),
- MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668),
- MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C),
- MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670),
- MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674),
- MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678),
- MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C),
- MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680),
- MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684),
- MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688),
- MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C),
- MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690),
- MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694),
- MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698),
- MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C),
- MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0),
- MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4),
- MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8),
- MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC),
- MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0),
- MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4),
- MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8),
- MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC),
- MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0),
- MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4),
- MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8),
- MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC),
- MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0),
- MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4),
- MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8),
- MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC),
- MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0),
- MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4),
- MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8),
- MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC),
- MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0),
- MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4),
- MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC),
- MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708),
- MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C),
- MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710),
- MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714),
- MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718),
- MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C),
- MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720),
- MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724),
- MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728),
- MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C),
-};
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_MXC_MX53_PINS_H__ */
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#ifndef __MX28_EVK_H
-#define __MX28_EVK_H
+#ifndef __CONFIG_H
+#define __CONFIG_H
-#include <asm/arch/mx28.h>
+#include <asm/arch/regs-base.h>
/*
- * SoC configurations
+ * Ka-Ro TX28 board - SoC configuration
*/
#define CONFIG_MX28 /* i.MX28 SoC */
-#define CONFIG_MX28_TO1_2
#define CONFIG_SYS_HZ 1000 /* Ticks per second */
-/* ROM loads UBOOT into DRAM */
-#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_SPL
+#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
+#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mx28"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
/*
* Memory configurations
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-#define CONFIG_STACKSIZE 0x00020000 /* 128 KB stack */
+#define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Reserved for initial data */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start address */
/*
* Boot Linux
*/
+#define xstr(s) str(s)
+#define str(s) #s
+
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTDELAY 3
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"autostart=no\0"
-#define __stringify(s) _stringify(s)
-#define _stringify(s) #s
-
#define MTD_NAME "gpmi-nand"
#define MTDIDS_DEFAULT "nand0=" MTD_NAME
#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":128k@" \
- __stringify(CONFIG_ENV_OFFSET) \
+ xstr(CONFIG_ENV_OFFSET) \
"(env),1m@0x40000(u-boot),4m(linux),16m(rootfs),-(userfs)"
/*
/*
* Serial Driver
*/
-#define CONFIG_UARTDBG_CLK 24000000
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 24000000
+#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
+#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_MTD_DEVICE
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_MXS_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_SYS_MXS_DMA_CHANNEL 4
#define CONFIG_SYS_MAX_FLASH_SECT 1024
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define BOOT_MODE_SD0 0x9
#define BOOT_MODE_SD1 0xa
-#endif /* __MX28_EVK_H */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+ GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
#endif /* CONFIG_ENV_IS_IN_MG_DISK */
#if defined(CONFIG_ENV_IS_IN_MMC)
-# ifndef CONFIG_ENV_OFFSET
-# error "Need to define CONFIG_ENV_OFFSET when using CONFIG_ENV_IS_IN_MMC"
-# endif
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_ENV_OFFSET)
+# ifndef CONFIG_ENV_ADDR
+# define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
# endif
-# ifndef CONFIG_ENV_OFFSET
-# define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
+# ifndef CONFIG_ENV_OFFSET
+# define CONFIG_ENV_OFFSET CONFIG_ENV_ADDR
# endif
# ifdef CONFIG_ENV_OFFSET_REDUND
# define CONFIG_SYS_REDUNDAND_ENVIRONMENT
# endif
-# ifdef CONFIG_ENV_IS_EMBEDDED
-# define ENV_IS_EMBEDDED 1
-# endif
#endif /* CONFIG_ENV_IS_IN_MMC */
/* Embedded env is only supported for some flash types */
*/
#include <common.h>
-#include <arm926ejs.h>
-#if defined(CONFIG_INTEGRATOR) || defined(CONFIG_MX25)
/*
* DSP test
*
projects / karo-tx-uboot.git / commitdiff