/u-boot.ais
/u-boot.dtb
/u-boot.sb
+/u-boot.bd
/u-boot.geany
#
mx6qsabresd i.MX6Q
mx6qsabreauto i.MX6Q
wandboard i.MX6DL/S
+ mx6slevk i.MX6SL
Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
x600 ARM926EJS (spear600 Soc)
+ titanium i.MX6Q
+
pdnb3 xscale/ixp
scpu xscale/ixp
mx23_olinuxino i.MX23
m28evk i.MX28
sc_sps_1 i.MX28
+ m53evk i.MX53
Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
# load other configuration
include $(TOPDIR)/config.mk
+# Targets which don't build the source code
+NON_BUILD_TARGETS = backup clean clobber distclean mkproper tidy unconfig
+
+# Only do the generic board check when actually building, not configuring
+ifeq ($(filter $(NON_BUILD_TARGETS),$(MAKECMDGOALS)),)
+ifeq ($(findstring _config,$(MAKECMDGOALS)),)
+$(CHECK_GENERIC_BOARD)
+endif
+endif
+
# If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use
# that (or fail if absent). Otherwise, search for a linker script in a
# standard location.
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs))
LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
endif
cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.img > \
$(obj)u-boot.ais
-# Specify the target for use in elftosb call
-ELFTOSB_TARGET-$(CONFIG_MX23) = imx23
-ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
- elftosb -zf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
- -o $(obj)u-boot.sb
+ $(MAKE) -C $(SRCTREE)/$(CPUDIR)/$(SOC)/ $(OBJTREE)/u-boot.sb
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
# Both images are created using mkimage (crc etc), so that the ROM
$(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
cat $(obj)spl/u-boot-spl.bin $(obj)u-boot.img > $@
+# PPC4xx needs the SPL at the end of the image, since the reset vector
+# is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target
+# and need to introduce a new build target with the full blown U-Boot
+# at the start padded up to the start of the SPL image. And then concat
+# the SPL image to the end.
+$(obj)u-boot-img-spl-at-end.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
+ tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_UBOOT_PAD_TO) \
+ of=$(obj)u-boot-pad.img 2>/dev/null
+ dd if=$(obj)u-boot.img of=$(obj)u-boot-pad.img \
+ conv=notrunc 2>/dev/null
+ cat $(obj)u-boot-pad.img $(obj)spl/u-boot-spl.bin > $@
+
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
@rm -f $(obj)u-boot.ais
@rm -f $(obj)u-boot.dtb
@rm -f $(obj)u-boot.sb
+ @rm -f $(obj)u-boot.bd
@rm -f $(obj)u-boot.spr
@rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
@rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
CONFIG_CMD_FDOS * Dos diskette Support
CONFIG_CMD_FLASH flinfo, erase, protect
CONFIG_CMD_FPGA FPGA device initialization support
+ CONFIG_CMD_FUSE Device fuse support
CONFIG_CMD_GETTIME * Get time since boot
CONFIG_CMD_GO * the 'go' command (exec code)
CONFIG_CMD_GREPENV * search environment
XXX - this list needs to get updated!
+- Regular expression support:
+ CONFIG_REGEX
+ If this variable is defined, U-Boot is linked against
+ the SLRE (Super Light Regular Expression) library,
+ which adds regex support to some commands, as for
+ example "env grep" and "setexpr".
+
- Device tree:
CONFIG_OF_CONTROL
If this variable is defined, U-Boot will use a device tree
digits and dots. Recommended value: 45 (9..1) for 80
column displays, 15 (3..1) for 40 column displays.
+- CONFIG_FLASH_VERIFY
+ If defined, the content of the flash (destination) is compared
+ against the source after the write operation. An error message
+ will be printed when the contents are not identical.
+ Please note that this option is useless in nearly all cases,
+ since such flash programming errors usually are detected earlier
+ while unprotecting/erasing/programming. Please only enable
+ this option if you really know what you are doing.
+
- CONFIG_SYS_RX_ETH_BUFFER:
Defines the number of Ethernet receive buffers. On some
Ethernet controllers it is recommended to set this value
COBJS += generic.o
COBJS += timer.o
-COBJS += iomux.o
COBJS += mx35_sdram.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+++ /dev/null
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx35_pins.h>
-#include <asm/arch/iomux.h>
-
-/*
- * IOMUX register (base) addresses
- */
-enum iomux_reg_addr {
- IOMUXGPR = IOMUXC_BASE_ADDR, /* General purpose */
- IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4, /* MUX control */
- IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324, /* last MUX control */
- IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328, /* Pad control */
- IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794, /* last Pad control */
- IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC, /* input select */
- IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4, /* last input select */
-};
-
-#define MUX_PIN_NUM_MAX \
- (((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1)
-#define MUX_INPUT_NUM_MUX \
- (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1)
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used.
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
- if (mux_reg != NON_MUX_I) {
- mux_reg += IOMUXGPR;
- writel(cfg, mux_reg);
- }
-}
-
-/*
- * Release ownership for an IO pin
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in iomux_pin_name_t
- * @param config the ORed value of elements defined in iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
- u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin);
-
- writel(config, pad_reg);
-}
-
-/*
- * This function enables/disables the general purpose function for a particular
- * signal.
- *
- * @param gp one signal as defined in iomux_gp_func_t
- * @param en enable/disable
- */
-void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en)
-{
- u32 l;
-
- l = readl(IOMUXGPR);
- if (en)
- l |= gp;
- else
- l &= ~gp;
-
- writel(l, IOMUXGPR);
-}
-
-/*
- * This function configures input path.
- *
- * @param input index of input select register as defined in
- * iomux_input_select_t
- * @param config the binary value of elements defined in
- * iomux_input_config_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
-{
- u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
-
- writel(config, reg);
-}
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/imx25-pinmux.h>
#include <asm/arch/clock.h>
#ifdef CONFIG_FSL_ESDHC
}
#endif
-#ifdef CONFIG_MXC_UART
-void mx25_uart1_init_pins(void)
-{
- struct iomuxc_mux_ctl *muxctl;
- struct iomuxc_pad_ctl *padctl;
- u32 inpadctl;
- u32 outpadctl;
- u32 muxmode0;
-
- muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
- padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
- muxmode0 = MX25_PIN_MUX_MODE(0);
- /*
- * set up input pins with hysteresis and 100K pull-ups
- */
- inpadctl = MX25_PIN_PAD_CTL_HYS
- | MX25_PIN_PAD_CTL_PKE
- | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU;
-
- /*
- * set up output pins with 100K pull-downs
- * FIXME: need to revisit this
- * PUE is ignored if PKE is not set
- * so the right value here is likely
- * 0x0 for no pull up/down
- * or
- * 0xc0 for 100k pull down
- */
- outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-
- /* UART1 */
- /* rxd */
- writel(muxmode0, &muxctl->pad_uart1_rxd);
- writel(inpadctl, &padctl->pad_uart1_rxd);
-
- /* txd */
- writel(muxmode0, &muxctl->pad_uart1_txd);
- writel(outpadctl, &padctl->pad_uart1_txd);
-
- /* rts */
- writel(muxmode0, &muxctl->pad_uart1_rts);
- writel(outpadctl, &padctl->pad_uart1_rts);
-
- /* cts */
- writel(muxmode0, &muxctl->pad_uart1_cts);
- writel(inpadctl, &padctl->pad_uart1_cts);
-}
-#endif /* CONFIG_MXC_UART */
-
#ifdef CONFIG_FEC_MXC
-void mx25_fec_init_pins(void)
-{
- struct iomuxc_mux_ctl *muxctl;
- struct iomuxc_pad_ctl *padctl;
- u32 inpadctl_100kpd;
- u32 inpadctl_22kpu;
- u32 outpadctl;
- u32 muxmode0;
-
- muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
- padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
- muxmode0 = MX25_PIN_MUX_MODE(0);
- inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
- | MX25_PIN_PAD_CTL_PKE
- | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
- inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS
- | MX25_PIN_PAD_CTL_PKE
- | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU;
- /*
- * set up output pins with 100K pull-downs
- * FIXME: need to revisit this
- * PUE is ignored if PKE is not set
- * so the right value here is likely
- * 0x0 for no pull
- * or
- * 0xc0 for 100k pull down
- */
- outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-
- /* FEC_TX_CLK */
- writel(muxmode0, &muxctl->pad_fec_tx_clk);
- writel(inpadctl_100kpd, &padctl->pad_fec_tx_clk);
-
- /* FEC_RX_DV */
- writel(muxmode0, &muxctl->pad_fec_rx_dv);
- writel(inpadctl_100kpd, &padctl->pad_fec_rx_dv);
-
- /* FEC_RDATA0 */
- writel(muxmode0, &muxctl->pad_fec_rdata0);
- writel(inpadctl_100kpd, &padctl->pad_fec_rdata0);
-
- /* FEC_TDATA0 */
- writel(muxmode0, &muxctl->pad_fec_tdata0);
- writel(outpadctl, &padctl->pad_fec_tdata0);
-
- /* FEC_TX_EN */
- writel(muxmode0, &muxctl->pad_fec_tx_en);
- writel(outpadctl, &padctl->pad_fec_tx_en);
-
- /* FEC_MDC */
- writel(muxmode0, &muxctl->pad_fec_mdc);
- writel(outpadctl, &padctl->pad_fec_mdc);
-
- /* FEC_MDIO */
- writel(muxmode0, &muxctl->pad_fec_mdio);
- writel(inpadctl_22kpu, &padctl->pad_fec_mdio);
-
- /* FEC_RDATA1 */
- writel(muxmode0, &muxctl->pad_fec_rdata1);
- writel(inpadctl_100kpd, &padctl->pad_fec_rdata1);
-
- /* FEC_TDATA1 */
- writel(muxmode0, &muxctl->pad_fec_tdata1);
- writel(outpadctl, &padctl->pad_fec_tdata1);
-
-}
-
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
int i;
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+# Specify the target for use in elftosb call
+ELFTOSB_TARGET-$(CONFIG_MX23) = imx23
+ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
+
+$(OBJTREE)/u-boot.bd: $(SRCTREE)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd
+ sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@
+
+$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/u-boot.bd
+ elftosb -zf $(ELFTOSB_TARGET-y) -c $(OBJTREE)/u-boot.bd -o $(OBJTREE)/u-boot.sb
+
#########################################################################
# defines $(obj).depend target
bus, tgtclk, freq);
}
+void mxs_set_lcdclk(uint32_t freq)
+{
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ uint32_t fp, x, k_rest, k_best, x_best, tk;
+ int32_t k_best_l = 999, k_best_t = 0, x_best_l = 0xff, x_best_t = 0xff;
+
+ if (freq == 0)
+ return;
+
+#if defined(CONFIG_MX23)
+ writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr);
+#elif defined(CONFIG_MX28)
+ writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr);
+#endif
+
+ /*
+ * / 18 \ 1 1
+ * freq kHz = | 480000000 Hz * -- | * --- * ------
+ * \ x / k 1000
+ *
+ * 480000000 Hz 18
+ * ------------ * --
+ * freq kHz x
+ * k = -------------------
+ * 1000
+ */
+
+ fp = ((PLL_FREQ_KHZ * 1000) / freq) * 18;
+
+ for (x = 18; x <= 35; x++) {
+ tk = fp / x;
+ if ((tk / 1000 == 0) || (tk / 1000 > 255))
+ continue;
+
+ k_rest = tk % 1000;
+
+ if (k_rest < (k_best_l % 1000)) {
+ k_best_l = tk;
+ x_best_l = x;
+ }
+
+ if (k_rest > (k_best_t % 1000)) {
+ k_best_t = tk;
+ x_best_t = x;
+ }
+ }
+
+ if (1000 - (k_best_t % 1000) > (k_best_l % 1000)) {
+ k_best = k_best_l;
+ x_best = x_best_l;
+ } else {
+ k_best = k_best_t;
+ x_best = x_best_t;
+ }
+
+ k_best /= 1000;
+
+#if defined(CONFIG_MX23)
+ writeb(CLKCTRL_FRAC_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]);
+ writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
+ &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_PIX]);
+ writeb(CLKCTRL_FRAC_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_PIX]);
+
+ writel(CLKCTRL_PIX_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_pix_set);
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_pix,
+ CLKCTRL_PIX_DIV_MASK | CLKCTRL_PIX_CLKGATE,
+ k_best << CLKCTRL_PIX_DIV_OFFSET);
+
+ while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY)
+ ;
+#elif defined(CONFIG_MX28)
+ writeb(CLKCTRL_FRAC_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]);
+ writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
+ &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_PIX]);
+ writeb(CLKCTRL_FRAC_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_frac1_clr[CLKCTRL_FRAC1_PIX]);
+
+ writel(CLKCTRL_DIS_LCDIF_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_lcdif_set);
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_lcdif,
+ CLKCTRL_DIS_LCDIF_DIV_MASK | CLKCTRL_DIS_LCDIF_CLKGATE,
+ k_best << CLKCTRL_DIS_LCDIF_DIV_OFFSET);
+
+ while (readl(&clkctrl_regs->hw_clkctrl_lcdif) & CLKCTRL_DIS_LCDIF_BUSY)
+ ;
+#endif
+}
+
uint32_t mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
#include <asm/arch/gpio.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
DECLARE_GLOBAL_DATA_PTR;
-/* 1 second delay should be plenty of time for block reset. */
-#define RESET_MAX_TIMEOUT 1000000
-
-#define MXS_BLOCK_SFTRST (1 << 31)
-#define MXS_BLOCK_CLKGATE (1 << 30)
-
/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
inline void lowlevel_init(void) {}
#endif
}
-int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
- int timeout)
-{
- while (--timeout) {
- if ((readl(®->reg) & mask) == mask)
- break;
- udelay(1);
- }
-
- return !timeout;
-}
-
-int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
- int timeout)
-{
- while (--timeout) {
- if ((readl(®->reg) & mask) == 0)
- break;
- udelay(1);
- }
-
- return !timeout;
-}
-
-int mxs_reset_block(struct mxs_register_32 *reg)
-{
- /* Clear SFTRST */
- writel(MXS_BLOCK_SFTRST, ®->reg_clr);
-
- if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
- return 1;
-
- /* Clear CLKGATE */
- writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
-
- /* Set SFTRST */
- writel(MXS_BLOCK_SFTRST, ®->reg_set);
-
- /* Wait for CLKGATE being set */
- if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
- return 1;
-
- /* Clear SFTRST */
- writel(MXS_BLOCK_SFTRST, ®->reg_clr);
-
- if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
- return 1;
-
- /* Clear CLKGATE */
- writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
-
- if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
- return 1;
-
- return 0;
-}
-
void mx28_fixup_vt(uint32_t start_addr)
{
uint32_t *vt = (uint32_t *)0x20;
for (;;)
;
}
-
-void hang(void) __attribute__ ((noreturn));
-void hang(void)
-{
- for (;;)
- ;
-}
{
}
+#ifdef CONFIG_MX28
static void initialize_dram_values(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+}
+#else
+static void initialize_dram_values(void)
+{
+ int i;
+
+ mxs_adjust_memory_params(dram_vals);
+
+ /*
+ * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
+ * per FSL bootlets code.
+ *
+ * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
+ * "reserved".
+ * HW_DRAM_CTL8 is setup as the last element.
+ * So skip the initialization of these HW_DRAM_CTL registers.
+ */
+ for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
+ if (i == 8 || i == 27 || i == 28 || i == 35)
+ continue;
+ writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+ }
-#ifdef CONFIG_MX23
/*
* Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
* element to be set
*/
writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
-#endif
}
+#endif
static void mxs_mem_init_clock(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
- writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
- POWER_VDDMEMCTRL_ENABLE_ILIMIT |
- POWER_VDDMEMCTRL_ENABLE_LINREG |
- POWER_VDDMEMCTRL_PULLDOWN_ACTIVE,
- &power_regs->hw_power_vddmemctrl);
+ clrbits_le32(&power_regs->hw_power_vddmemctrl,
+ POWER_VDDMEMCTRL_ENABLE_ILIMIT);
- early_delay(10000);
-
- writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
- POWER_VDDMEMCTRL_ENABLE_LINREG,
- &power_regs->hw_power_vddmemctrl);
}
static void mx23_mem_init(void)
initialize_dram_values();
- /* Set START bit in DRAM_CTL16 */
+ /* Set START bit in DRAM_CTL8 */
setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
early_delay(20000);
/* Adjust EMI port priority. */
- clrsetbits_le32(0x80020000, 0x1f << 16, 0x8);
+ clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
early_delay(20000);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
-
- /* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
- while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
- ;
}
#endif
mxs_init_batt_bo();
mxs_switch_vddd_to_dcdc_source();
+
+#ifdef CONFIG_MX23
+ /* Fire up the VDDMEM LinReg now that we're all set. */
+ writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
+ &power_regs->hw_power_vddmemctrl);
+#endif
}
static void mxs_enable_output_rail_protection(void)
static const struct mxs_vddx_cfg mxs_vddio_cfg = {
.reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
hw_power_vddioctrl),
+#if defined(CONFIG_MX23)
+ .step_mV = 25,
+#else
.step_mV = 50,
+#endif
.lowest_mV = 2800,
.powered_by_linreg = mxs_get_vddio_power_source_off,
.trg_mask = POWER_VDDIOCTRL_TRG_MASK,
.bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
};
+#ifdef CONFIG_MX23
+static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
+ .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
+ hw_power_vddmemctrl),
+ .step_mV = 50,
+ .lowest_mV = 1700,
+ .powered_by_linreg = NULL,
+ .trg_mask = POWER_VDDMEMCTRL_TRG_MASK,
+ .bo_irq = 0,
+ .bo_enirq = 0,
+ .bo_offset_mask = 0,
+ .bo_offset_offset = 0,
+};
+#endif
+
static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
uint32_t new_target, uint32_t new_brownout)
{
cur_target += cfg->lowest_mV;
adjust_up = new_target > cur_target;
- powered_by_linreg = cfg->powered_by_linreg();
+ if (cfg->powered_by_linreg)
+ powered_by_linreg = cfg->powered_by_linreg();
- if (adjust_up) {
+ if (adjust_up && cfg->bo_irq) {
if (powered_by_linreg) {
bo_int = readl(cfg->reg);
clrbits_le32(cfg->reg, cfg->bo_enirq);
cur_target += cfg->lowest_mV;
} while (new_target > cur_target);
- if (adjust_up && powered_by_linreg) {
- writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
- if (bo_int & cfg->bo_enirq)
- setbits_le32(cfg->reg, cfg->bo_enirq);
- }
+ if (cfg->bo_irq) {
+ if (adjust_up && powered_by_linreg) {
+ writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
+ if (bo_int & cfg->bo_enirq)
+ setbits_le32(cfg->reg, cfg->bo_enirq);
+ }
- clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
- new_brownout << cfg->bo_offset_offset);
+ clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
+ new_brownout << cfg->bo_offset_offset);
+ }
}
static void mxs_setup_batt_detect(void)
mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
-
+#ifdef CONFIG_MX23
+ mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
+#endif
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
}
sources {
- u_boot_spl="spl/u-boot-spl.bin";
- u_boot="u-boot.bin";
+ u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
+ u_boot="OBJTREE/u-boot.bin";
}
section (0) {
sources {
- u_boot_spl="spl/u-boot-spl.bin";
- u_boot="u-boot.bin";
+ u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
+ u_boot="OBJTREE/u-boot.bin";
}
section (0) {
#include <asm/arch/spr_misc.h>
#include <asm/arch/spr_syscntl.h>
-inline void hang(void)
-{
- serial_puts("### ERROR ### Please RESET the board ###\n");
- for (;;)
- ;
-}
-
static void ddr_clock_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
LIB = $(obj)lib$(SOC).o
-COBJS = soc.o clock.o iomux.o
+COBJS = soc.o clock.o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
static int config_nfc_clk(u32 nfc_clk)
{
u32 parent_rate = get_emi_slow_clk();
- u32 div = parent_rate / nfc_clk;
+ u32 div;
- if (nfc_clk <= 0)
+ if (nfc_clk == 0)
return -EINVAL;
+ div = parent_rate / nfc_clk;
if (div == 0)
div++;
if (parent_rate / div > NFC_CLK_MAX)
return 0;
}
+void enable_nfc_clk(unsigned char enable)
+{
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+ clrsetbits_le32(&mxc_ccm->CCGR5,
+ MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR5_EMI_ENFC(cg));
+}
+
/* Config main_bus_clock for periphs */
static int config_periph_clk(u32 ref, u32 freq)
{
+++ /dev/null
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/sys_proto.h>
-
-/* IOMUX register (base) addresses */
-enum iomux_reg_addr {
- IOMUXGPR0 = IOMUXC_BASE_ADDR,
- IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
- IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
- IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
- IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
- IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START,
-};
-
-#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
-
-/* Get the iomux register address of this pin */
-static inline u32 get_mux_reg(iomux_pin_name_t pin)
-{
- u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
-#if defined(CONFIG_MX51)
- if (is_soc_rev(CHIP_REV_2_0) < 0) {
- /*
- * Fixup register address:
- * i.MX51 TO1 has offset with the register
- * which is define as TO2.
- */
- if ((pin == MX51_PIN_NANDF_RB5) ||
- (pin == MX51_PIN_NANDF_RB6) ||
- (pin == MX51_PIN_NANDF_RB7))
- ; /* Do nothing */
- else if (mux_reg >= 0x2FC)
- mux_reg += 8;
- else if (mux_reg >= 0x130)
- mux_reg += 0xC;
- }
-#endif
- mux_reg += IOMUXSW_MUX_CTL;
- return mux_reg;
-}
-
-/* Get the pad register address of this pin */
-static inline u32 get_pad_reg(iomux_pin_name_t pin)
-{
- u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
-
-#if defined(CONFIG_MX51)
- if (is_soc_rev(CHIP_REV_2_0) < 0) {
- /*
- * Fixup register address:
- * i.MX51 TO1 has offset with the register
- * which is define as TO2.
- */
- if ((pin == MX51_PIN_NANDF_RB5) ||
- (pin == MX51_PIN_NANDF_RB6) ||
- (pin == MX51_PIN_NANDF_RB7))
- ; /* Do nothing */
- else if (pad_reg == 0x4D0 - PAD_I_START)
- pad_reg += 0x4C;
- else if (pad_reg == 0x860 - PAD_I_START)
- pad_reg += 0x9C;
- else if (pad_reg >= 0x804 - PAD_I_START)
- pad_reg += 0xB0;
- else if (pad_reg >= 0x7FC - PAD_I_START)
- pad_reg += 0xB4;
- else if (pad_reg >= 0x4E4 - PAD_I_START)
- pad_reg += 0xCC;
- else
- pad_reg += 8;
- }
-#endif
- pad_reg += IOMUXSW_PAD_CTL;
- return pad_reg;
-}
-
-/* Get the last iomux register address */
-static inline u32 get_mux_end(void)
-{
-#if defined(CONFIG_MX51)
- if (is_soc_rev(CHIP_REV_2_0) < 0)
- return IOMUXC_BASE_ADDR + (0x3F8 - 4);
- else
- return IOMUXC_BASE_ADDR + (0x3F0 - 4);
-#endif
- return IOMUXSW_MUX_END;
-}
-
-/*
- * This function is used to configure a pin through the IOMUX module.
- * @param pin a pin number as defined in iomux_pin_name_t
- * @param cfg an output function as defined in iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-static void iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- u32 mux_reg = get_mux_reg(pin);
-
- if ((mux_reg > get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
- return ;
- if (cfg == IOMUX_CONFIG_GPIO)
- writel(PIN_TO_ALT_GPIO(pin), mux_reg);
- else
- writel(cfg, mux_reg);
-}
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param pin a name defined by iomux_pin_name_t
- * @param cfg an input function as defined in iomux_pin_cfg_t
- *
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- iomux_config_mux(pin, cfg);
-}
-
-/*
- * Release ownership for an IO pin
- *
- * @param pin a name defined by iomux_pin_name_t
- * @param cfg an input function as defined in iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in iomux_pin_name_t
- * @param config the ORed value of elements defined in iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
- u32 pad_reg = get_pad_reg(pin);
- writel(config, pad_reg);
-}
-
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
-{
- u32 pad_reg = get_pad_reg(pin);
- return readl(pad_reg);
-}
-
-/*
- * This function configures daisy-chain
- *
- * @param input index of input select register
- * @param config the binary value of elements
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
-{
- u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
-
- writel(config, reg);
-}
return system_rev;
}
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+#endif
+
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+ u32 reg;
+
+ reg = __raw_readl(&imx_ccm->CCGR2);
+ if (enable)
+ reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+ else
+ reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+ __raw_writel(reg, &imx_ccm->CCGR2);
+}
+#endif
+
void enable_usboh3_clk(unsigned char enable)
{
u32 reg;
static u32 get_uart_clk(void)
{
u32 reg, uart_podf;
-
+ u32 freq = PLL3_80M;
reg = __raw_readl(&imx_ccm->cscdr1);
+#ifdef CONFIG_MX6SL
+ if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
+ freq = MXC_HCLK;
+#endif
reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
- return PLL3_80M / (uart_podf + 1);
+ return freq / (uart_podf + 1);
}
static u32 get_cspi_clk(void)
return root_freq / (emi_slow_pof + 1);
}
+#ifdef CONFIG_MX6SL
+static u32 get_mmdc_ch0_clk(void)
+{
+ u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
+ u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
+ u32 freq, podf;
+
+ podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
+ >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
+
+ switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
+ MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
+ case 0:
+ freq = decode_pll(PLL_BUS, MXC_HCLK);
+ break;
+ case 1:
+ freq = PLL2_PFD2_FREQ;
+ break;
+ case 2:
+ freq = PLL2_PFD0_FREQ;
+ break;
+ case 3:
+ freq = PLL2_PFD2_DIV_FREQ;
+ }
+
+ return freq / (podf + 1);
+
+}
+#else
static u32 get_mmdc_ch0_clk(void)
{
u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
return get_periph_clk() / (mmdc_ch0_podf + 1);
}
+#endif
static u32 get_usdhc_clk(u32 port)
{
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/dma.h>
#include <stdbool.h>
struct scu_regs {
set_vddsoc(1200); /* Set VDDSOC to 1.2V */
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
+
+#ifdef CONFIG_APBH_DMA
+ /* Start APBH DMA */
+ mxs_dma_init();
+#endif
+
return 0;
}
#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
- struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
- struct fuse_bank *bank = &iim->bank[4];
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[4];
struct fuse_bank4_regs *fuse =
(struct fuse_bank4_regs *)bank->fuse_regs;
#define SLCR_LOCK_MAGIC 0x767B
#define SLCR_UNLOCK_MAGIC 0xDF0D
+#define SLCR_IDCODE_MASK 0x1F000
+#define SLCR_IDCODE_SHIFT 12
+
static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
void zynq_slcr_lock(void)
out:
zynq_slcr_lock();
}
+
+void zynq_slcr_devcfg_disable(void)
+{
+ zynq_slcr_unlock();
+
+ /* Disable AXI interface */
+ writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
+
+ /* Set Level Shifters DT618760 */
+ writel(0xA, &slcr_base->lvl_shftr_en);
+
+ zynq_slcr_lock();
+}
+
+void zynq_slcr_devcfg_enable(void)
+{
+ zynq_slcr_unlock();
+
+ /* Set Level Shifters DT618760 */
+ writel(0xF, &slcr_base->lvl_shftr_en);
+
+ /* Disable AXI interface */
+ writel(0x0, &slcr_base->fpga_rst_ctrl);
+
+ zynq_slcr_lock();
+}
+
+u32 zynq_slcr_get_idcode(void)
+{
+ return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
+ SLCR_IDCODE_SHIFT;
+}
writel(readl(CKEN) | CKEN14_I2C, CKEN);
}
-void reset_cpu(ulong ignored) __attribute__((noreturn));
+void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn));
void reset_cpu(ulong ignored)
{
LIB = $(obj)libimx-common.o
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6))
+COBJS-y = iomux-v3.o
+endif
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
-COBJS-y = iomux-v3.o timer.o cpu.o speed.o
+COBJS-y += timer.o cpu.o speed.o
COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
endif
+ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
+COBJS-y += misc.o
+endif
COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
COBJS-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
COBJS := $(sort $(COBJS-y))
$(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
-I binary -O binary $< $(OBJTREE)/spl/u-boot-spl-pad.imx
- cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.bin > $@
- rm $(OBJTREE)/spl/u-boot-spl-pad.imx
+ $(OBJTREE)/tools/mkimage -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
+ -e $(CONFIG_SYS_TEXT_BASE) -C none -d $(OBJTREE)/u-boot.bin \
+ $(OBJTREE)/u-boot.uim
+ cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.uim > $@
+ rm $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.uim
$(OBJTREE)/u-boot-with-nand-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
(echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \
-I binary -O binary $(OBJTREE)/spl/u-boot-nand-spl.imx \
$(OBJTREE)/spl/u-boot-nand-spl-pad.imx
rm $(OBJTREE)/spl/u-boot-nand-spl.imx
- cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.bin > $@
- rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx
+ $(OBJTREE)/tools/mkimage -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
+ -e $(CONFIG_SYS_TEXT_BASE) -C none -d $(OBJTREE)/u-boot.bin \
+ $(OBJTREE)/u-boot.uim
+ cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.uim > $@
+ rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.uim
#########################################################################
/*
* configures a single pad in the iomuxer
*/
-int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
+void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
{
u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
-
- return 0;
}
-int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
- unsigned count)
+void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+ unsigned count)
{
iomux_v3_cfg_t const *p = pad_list;
int i;
- int ret;
- for (i = 0; i < count; i++) {
- ret = imx_iomux_v3_setup_pad(*p);
- if (ret)
- return ret;
- p++;
- }
- return 0;
+ for (i = 0; i < count; i++)
+ imx_iomux_v3_setup_pad(*p++);
}
--- /dev/null
+/*
+ * Copyright 2013 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/imx-common/regs-common.h>
+
+/* 1 second delay should be plenty of time for block reset. */
+#define RESET_MAX_TIMEOUT 1000000
+
+#define MXS_BLOCK_SFTRST (1 << 31)
+#define MXS_BLOCK_CLKGATE (1 << 30)
+
+int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
+ int timeout)
+{
+ while (--timeout) {
+ if ((readl(®->reg) & mask) == mask)
+ break;
+ udelay(1);
+ }
+
+ return !timeout;
+}
+
+int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
+ int timeout)
+{
+ while (--timeout) {
+ if ((readl(®->reg) & mask) == 0)
+ break;
+ udelay(1);
+ }
+
+ return !timeout;
+}
+
+int mxs_reset_block(struct mxs_register_32 *reg)
+{
+ /* Clear SFTRST */
+ writel(MXS_BLOCK_SFTRST, ®->reg_clr);
+
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+ return 1;
+
+ /* Clear CLKGATE */
+ writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
+
+ /* Set SFTRST */
+ writel(MXS_BLOCK_SFTRST, ®->reg_set);
+
+ /* Wait for CLKGATE being set */
+ if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+ return 1;
+
+ /* Clear SFTRST */
+ writel(MXS_BLOCK_SFTRST, ®->reg_clr);
+
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+ return 1;
+
+ /* Clear CLKGATE */
+ writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
+
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+ return 1;
+
+ return 0;
+}
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
- u32 iim_prog_p;
- u32 res1[0x1f5];
+ u32 iim_prg_p;
+ u32 iim_scs0;
+ u32 iim_scs1;
+ u32 iim_scs2;
+ u32 iim_scs3;
+ u32 res1[0x1f1];
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
};
struct fuse_bank0_regs {
- u32 fuse0_25[0x1a];
+ u32 fuse0_7[8];
+ u32 uid[8];
+ u32 fuse16_25[0xa];
u32 mac_addr[6];
};
+struct fuse_bank1_regs {
+ u32 fuse0_21[0x16];
+ u32 usr5;
+ u32 fuse23_29[7];
+ u32 usr6[2];
+};
+
/* Multi-Layer AHB Crossbar Switch (MAX) registers */
struct max_regs {
u32 mpr0;
#define IMX_CSPI1_BASE (0x43FA4000)
#define IMX_KPP_BASE (0x43FA8000)
#define IMX_IOPADMUX_BASE (0x43FAC000)
+#define IOMUXC_BASE_ADDR IMX_IOPADMUX_BASE
#define IMX_IOPADCTL_BASE (0x43FAC22C)
#define IMX_IOPADGRPCTL_BASE (0x43FAC418)
#define IMX_IOPADINPUTSEL_BASE (0x43FAC460)
#define IMX_PWM1_BASE (0x53FE0000)
#define IMX_RTIC_BASE (0x53FEC000)
#define IMX_IIM_BASE (0x53FF0000)
+#define IIM_BASE_ADDR IMX_IIM_BASE
#define IMX_USB_BASE (0x53FF4000)
#define IMX_USB_PORT_OFFSET 0x200
#define IMX_CSI_BASE (0x53FF8000)
+++ /dev/null
-/*
- * iopin settings are controlled by four different sets of registers
- * iopad mux control
- * individual iopad setup (voltage select, pull/keep, drive strength ...)
- * group iopad setup (same as above but for groups of signals)
- * input select when multiple inputs are possible
- */
-
-/*
- * software pad mux control
- */
-/* SW Input On (Loopback) */
-#define MX25_PIN_MUX_SION (1 << 4)
-/* MUX Mode (0-7) */
-#define MX25_PIN_MUX_MODE(mode) ((mode & 0x7) << 0)
-struct iomuxc_mux_ctl {
- u32 gpr1;
- u32 observe_int_mux;
- u32 pad_a10;
- u32 pad_a13;
- u32 pad_a14;
- u32 pad_a15;
- u32 pad_a16;
- u32 pad_a17;
- u32 pad_a18;
- u32 pad_a19;
- u32 pad_a20;
- u32 pad_a21;
- u32 pad_a22;
- u32 pad_a23;
- u32 pad_a24;
- u32 pad_a25;
- u32 pad_eb0;
- u32 pad_eb1;
- u32 pad_oe;
- u32 pad_cs0;
- u32 pad_cs1;
- u32 pad_cs4;
- u32 pad_cs5;
- u32 pad_nf_ce0;
- u32 pad_ecb;
- u32 pad_lba;
- u32 pad_bclk;
- u32 pad_rw;
- u32 pad_nfwe_b;
- u32 pad_nfre_b;
- u32 pad_nfale;
- u32 pad_nfcle;
- u32 pad_nfwp_b;
- u32 pad_nfrb;
- u32 pad_d15;
- u32 pad_d14;
- u32 pad_d13;
- u32 pad_d12;
- u32 pad_d11;
- u32 pad_d10;
- u32 pad_d9;
- u32 pad_d8;
- u32 pad_d7;
- u32 pad_d6;
- u32 pad_d5;
- u32 pad_d4;
- u32 pad_d3;
- u32 pad_d2;
- u32 pad_d1;
- u32 pad_d0;
- u32 pad_ld0;
- u32 pad_ld1;
- u32 pad_ld2;
- u32 pad_ld3;
- u32 pad_ld4;
- u32 pad_ld5;
- u32 pad_ld6;
- u32 pad_ld7;
- u32 pad_ld8;
- u32 pad_ld9;
- u32 pad_ld10;
- u32 pad_ld11;
- u32 pad_ld12;
- u32 pad_ld13;
- u32 pad_ld14;
- u32 pad_ld15;
- u32 pad_hsync;
- u32 pad_vsync;
- u32 pad_lsclk;
- u32 pad_oe_acd;
- u32 pad_contrast;
- u32 pad_pwm;
- u32 pad_csi_d2;
- u32 pad_csi_d3;
- u32 pad_csi_d4;
- u32 pad_csi_d5;
- u32 pad_csi_d6;
- u32 pad_csi_d7;
- u32 pad_csi_d8;
- u32 pad_csi_d9;
- u32 pad_csi_mclk;
- u32 pad_csi_vsync;
- u32 pad_csi_hsync;
- u32 pad_csi_pixclk;
- u32 pad_i2c1_clk;
- u32 pad_i2c1_dat;
- u32 pad_cspi1_mosi;
- u32 pad_cspi1_miso;
- u32 pad_cspi1_ss0;
- u32 pad_cspi1_ss1;
- u32 pad_cspi1_sclk;
- u32 pad_cspi1_rdy;
- u32 pad_uart1_rxd;
- u32 pad_uart1_txd;
- u32 pad_uart1_rts;
- u32 pad_uart1_cts;
- u32 pad_uart2_rxd;
- u32 pad_uart2_txd;
- u32 pad_uart2_rts;
- u32 pad_uart2_cts;
- u32 pad_sd1_cmd;
- u32 pad_sd1_clk;
- u32 pad_sd1_data0;
- u32 pad_sd1_data1;
- u32 pad_sd1_data2;
- u32 pad_sd1_data3;
- u32 pad_kpp_row0;
- u32 pad_kpp_row1;
- u32 pad_kpp_row2;
- u32 pad_kpp_row3;
- u32 pad_kpp_col0;
- u32 pad_kpp_col1;
- u32 pad_kpp_col2;
- u32 pad_kpp_col3;
- u32 pad_fec_mdc;
- u32 pad_fec_mdio;
- u32 pad_fec_tdata0;
- u32 pad_fec_tdata1;
- u32 pad_fec_tx_en;
- u32 pad_fec_rdata0;
- u32 pad_fec_rdata1;
- u32 pad_fec_rx_dv;
- u32 pad_fec_tx_clk;
- u32 pad_rtck;
- u32 pad_de_b;
- u32 pad_gpio_a;
- u32 pad_gpio_b;
- u32 pad_gpio_c;
- u32 pad_gpio_d;
- u32 pad_gpio_e;
- u32 pad_gpio_f;
- u32 pad_ext_armclk;
- u32 pad_upll_bypclk;
- u32 pad_vstby_req;
- u32 pad_vstby_ack;
- u32 pad_power_fail;
- u32 pad_clko;
- u32 pad_boot_mode0;
- u32 pad_boot_mode1;
-};
-
-/*
- * software pad control
- */
-/* Select 3.3 or 1.8 volts */
-#define MX25_PIN_PAD_CTL_DVS_33 (0 << 13)
-#define MX25_PIN_PAD_CTL_DVS_18 (1 << 13)
-/* Enable hysteresis */
-#define MX25_PIN_PAD_CTL_HYS (1 << 8)
-/* Enable pull/keeper */
-#define MX25_PIN_PAD_CTL_PKE (1 << 7)
-/* 0 - keeper / 1 - pull */
-#define MX25_PIN_PAD_CTL_PUE (1 << 6)
-/* pull up/down strength */
-#define MX25_PIN_PAD_CTL_100K_PD (0 << 4)
-#define MX25_PIN_PAD_CTL_47K_PU (1 << 4)
-#define MX25_PIN_PAD_CTL_100K_PU (2 << 4)
-#define MX25_PIN_PAD_CTL_22K_PU (3 << 4)
-/* open drain control */
-#define MX25_PIN_PAD_CTL_OD (1 << 3)
-/* drive strength */
-#define MX25_PIN_PAD_CTL_DS_NOM (0 << 1)
-#define MX25_PIN_PAD_CTL_DS_HIGH (1 << 1)
-#define MX25_PIN_PAD_CTL_DS_MAX (2 << 1)
-#define MX25_PIN_PAD_CTL_DS_MAX11 (3 << 1)
-/* slew rate */
-#define MX25_PIN_PAD_CTL_SRE_SLOW (0 << 0)
-#define MX25_PIN_PAD_CTL_SRE_FAST (1 << 0)
-struct iomuxc_pad_ctl {
- u32 pad_a13;
- u32 pad_a14;
- u32 pad_a15;
- u32 pad_a17;
- u32 pad_a18;
- u32 pad_a19;
- u32 pad_a20;
- u32 pad_a21;
- u32 pad_a23;
- u32 pad_a24;
- u32 pad_a25;
- u32 pad_eb0;
- u32 pad_eb1;
- u32 pad_oe;
- u32 pad_cs4;
- u32 pad_cs5;
- u32 pad_nf_ce0;
- u32 pad_ecb;
- u32 pad_lba;
- u32 pad_rw;
- u32 pad_nfrb;
- u32 pad_d15;
- u32 pad_d14;
- u32 pad_d13;
- u32 pad_d12;
- u32 pad_d11;
- u32 pad_d10;
- u32 pad_d9;
- u32 pad_d8;
- u32 pad_d7;
- u32 pad_d6;
- u32 pad_d5;
- u32 pad_d4;
- u32 pad_d3;
- u32 pad_d2;
- u32 pad_d1;
- u32 pad_d0;
- u32 pad_ld0;
- u32 pad_ld1;
- u32 pad_ld2;
- u32 pad_ld3;
- u32 pad_ld4;
- u32 pad_ld5;
- u32 pad_ld6;
- u32 pad_ld7;
- u32 pad_ld8;
- u32 pad_ld9;
- u32 pad_ld10;
- u32 pad_ld11;
- u32 pad_ld12;
- u32 pad_ld13;
- u32 pad_ld14;
- u32 pad_ld15;
- u32 pad_hsync;
- u32 pad_vsync;
- u32 pad_lsclk;
- u32 pad_oe_acd;
- u32 pad_contrast;
- u32 pad_pwm;
- u32 pad_csi_d2;
- u32 pad_csi_d3;
- u32 pad_csi_d4;
- u32 pad_csi_d5;
- u32 pad_csi_d6;
- u32 pad_csi_d7;
- u32 pad_csi_d8;
- u32 pad_csi_d9;
- u32 pad_csi_mclk;
- u32 pad_csi_vsync;
- u32 pad_csi_hsync;
- u32 pad_csi_pixclk;
- u32 pad_i2c1_clk;
- u32 pad_i2c1_dat;
- u32 pad_cspi1_mosi;
- u32 pad_cspi1_miso;
- u32 pad_cspi1_ss0;
- u32 pad_cspi1_ss1;
- u32 pad_cspi1_sclk;
- u32 pad_cspi1_rdy;
- u32 pad_uart1_rxd;
- u32 pad_uart1_txd;
- u32 pad_uart1_rts;
- u32 pad_uart1_cts;
- u32 pad_uart2_rxd;
- u32 pad_uart2_txd;
- u32 pad_uart2_rts;
- u32 pad_uart2_cts;
- u32 pad_sd1_cmd;
- u32 pad_sd1_clk;
- u32 pad_sd1_data0;
- u32 pad_sd1_data1;
- u32 pad_sd1_data2;
- u32 pad_sd1_data3;
- u32 pad_kpp_row0;
- u32 pad_kpp_row1;
- u32 pad_kpp_row2;
- u32 pad_kpp_row3;
- u32 pad_kpp_col0;
- u32 pad_kpp_col1;
- u32 pad_kpp_col2;
- u32 pad_kpp_col3;
- u32 pad_fec_mdc;
- u32 pad_fec_mdio;
- u32 pad_fec_tdata0;
- u32 pad_fec_tdata1;
- u32 pad_fec_tx_en;
- u32 pad_fec_rdata0;
- u32 pad_fec_rdata1;
- u32 pad_fec_rx_dv;
- u32 pad_fec_tx_clk;
- u32 pad_rtck;
- u32 pad_tdo;
- u32 pad_de_b;
- u32 pad_gpio_a;
- u32 pad_gpio_b;
- u32 pad_gpio_c;
- u32 pad_gpio_d;
- u32 pad_gpio_e;
- u32 pad_gpio_f;
- u32 pad_vstby_req;
- u32 pad_vstby_ack;
- u32 pad_power_fail;
- u32 pad_clko;
-};
-
-
-/*
- * Pad group drive strength and voltage select
- * Same fields as iomuxc_pad_ctl plus ddr type
- */
-/* Select DDR type */
-#define MX25_PIN_PAD_CTL_DDR_18 (0 << 11)
-#define MX25_PIN_PAD_CTL_DDR_33 (1 << 11)
-#define MX25_PIN_PAD_CTL_DDR_MAX (2 << 11)
-struct iomuxc_pad_grp_ctl {
- u32 grp_dvs_misc;
- u32 grp_dse_fec;
- u32 grp_dvs_jtag;
- u32 grp_dse_nfc;
- u32 grp_dse_csi;
- u32 grp_dse_weim;
- u32 grp_dse_ddr;
- u32 grp_dvs_crm;
- u32 grp_dse_kpp;
- u32 grp_dse_sdhc1;
- u32 grp_dse_lcd;
- u32 grp_dse_uart;
- u32 grp_dvs_nfc;
- u32 grp_dvs_csi;
- u32 grp_dse_cspi1;
- u32 grp_ddrtype;
- u32 grp_dvs_sdhc1;
- u32 grp_dvs_lcd;
-};
-
-/*
- * Pad input select control
- * Select which pad to connect to an input port
- * where multiple pads can function as given input
- */
-#define MX25_PAD_INPUT_SELECT_DAISY(in) ((in & 0x7) << 0)
-struct iomuxc_pad_input_select {
- u32 audmux_p4_input_da_amx;
- u32 audmux_p4_input_db_amx;
- u32 audmux_p4_input_rxclk_amx;
- u32 audmux_p4_input_rxfs_amx;
- u32 audmux_p4_input_txclk_amx;
- u32 audmux_p4_input_txfs_amx;
- u32 audmux_p7_input_da_amx;
- u32 audmux_p7_input_txfs_amx;
- u32 can1_ipp_ind_canrx;
- u32 can2_ipp_ind_canrx;
- u32 csi_ipp_csi_d_0;
- u32 csi_ipp_csi_d_1;
- u32 cspi1_ipp_ind_ss3_b;
- u32 cspi2_ipp_cspi_clk_in;
- u32 cspi2_ipp_ind_dataready_b;
- u32 cspi2_ipp_ind_miso;
- u32 cspi2_ipp_ind_mosi;
- u32 cspi2_ipp_ind_ss0_b;
- u32 cspi2_ipp_ind_ss1_b;
- u32 cspi3_ipp_cspi_clk_in;
- u32 cspi3_ipp_ind_dataready_b;
- u32 cspi3_ipp_ind_miso;
- u32 cspi3_ipp_ind_mosi;
- u32 cspi3_ipp_ind_ss0_b;
- u32 cspi3_ipp_ind_ss1_b;
- u32 cspi3_ipp_ind_ss2_b;
- u32 cspi3_ipp_ind_ss3_b;
- u32 esdhc1_ipp_dat4_in;
- u32 esdhc1_ipp_dat5_in;
- u32 esdhc1_ipp_dat6_in;
- u32 esdhc1_ipp_dat7_in;
- u32 esdhc2_ipp_card_clk_in;
- u32 esdhc2_ipp_cmd_in;
- u32 esdhc2_ipp_dat0_in;
- u32 esdhc2_ipp_dat1_in;
- u32 esdhc2_ipp_dat2_in;
- u32 esdhc2_ipp_dat3_in;
- u32 esdhc2_ipp_dat4_in;
- u32 esdhc2_ipp_dat5_in;
- u32 esdhc2_ipp_dat6_in;
- u32 esdhc2_ipp_dat7_in;
- u32 fec_fec_col;
- u32 fec_fec_crs;
- u32 fec_fec_rdata_2;
- u32 fec_fec_rdata_3;
- u32 fec_fec_rx_clk;
- u32 fec_fec_rx_er;
- u32 i2c2_ipp_scl_in;
- u32 i2c2_ipp_sda_in;
- u32 i2c3_ipp_scl_in;
- u32 i2c3_ipp_sda_in;
- u32 kpp_ipp_ind_col_4;
- u32 kpp_ipp_ind_col_5;
- u32 kpp_ipp_ind_col_6;
- u32 kpp_ipp_ind_col_7;
- u32 kpp_ipp_ind_row_4;
- u32 kpp_ipp_ind_row_5;
- u32 kpp_ipp_ind_row_6;
- u32 kpp_ipp_ind_row_7;
- u32 sim1_pin_sim_rcvd1_in;
- u32 sim1_pin_sim_simpd1;
- u32 sim1_sim_rcvd1_io;
- u32 sim2_pin_sim_rcvd1_in;
- u32 sim2_pin_sim_simpd1;
- u32 sim2_sim_rcvd1_io;
- u32 uart3_ipp_uart_rts_b;
- u32 uart3_ipp_uart_rxd_mux;
- u32 uart4_ipp_uart_rts_b;
- u32 uart4_ipp_uart_rxd_mux;
- u32 uart5_ipp_uart_rts_b;
- u32 uart5_ipp_uart_rxd_mux;
- u32 usb_top_ipp_ind_otg_usb_oc;
- u32 usb_top_ipp_ind_uh2_usb_oc;
-};
--- /dev/null
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on mainline Linux i.MX iomux-mx25.h file:
+ * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
+ *
+ * Based on Linux arch/arm/mach-mx25/mx25_pins.h:
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * and Linux arch/arm/plat-mxc/include/mach/iomux-mx35.h:
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IOMUX_MX25_H__
+#define __IOMUX_MX25_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Pad control groupings */
+#define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP
+#define MX25_KPP_COL_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+/*
+ * The naming convention for the pad modes is MX25_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/* PAD MUX ALT INPSE PATH PADCTRL */
+enum {
+ MX25_PAD_A10__A10 = IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A10__GPIO_4_0 = IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A13__A13 = IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A13__GPIO_4_1 = IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A17__A17 = IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A17__GPIO_2_3 = IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A18__A18 = IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A18__GPIO_2_4 = IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A18__FEC_COL = IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A19__A19 = IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A19__FEC_RX_ER = IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL),
+ MX25_PAD_A19__GPIO_2_5 = IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A20__A20 = IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A20__GPIO_2_6 = IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A20__FEC_RDATA2 = IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A21__A21 = IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A21__GPIO_2_7 = IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A21__FEC_RDATA3 = IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A22__A22 = IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A22__GPIO_2_8 = IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A23__A23 = IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A23__GPIO_2_9 = IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A24__A24 = IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A24__GPIO_2_10 = IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A24__FEC_RX_CLK = IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A25__A25 = IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A25__GPIO_2_11 = IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A25__FEC_CRS = IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL),
+
+ MX25_PAD_EB0__EB0 = IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_EB0__AUD4_TXD = IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL),
+ MX25_PAD_EB0__GPIO_2_12 = IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_EB1__EB1 = IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_EB1__AUD4_RXD = IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL),
+ MX25_PAD_EB1__GPIO_2_13 = IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_OE__OE = IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_OE__AUD4_TXC = IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_OE__GPIO_2_14 = IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CS0__CS0 = IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CS0__GPIO_4_2 = IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CS1__CS1 = IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CS1__NF_CE3 = IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CS1__GPIO_4_3 = IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CS4__CS4 = IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CS4__NF_CE1 = IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CS4__UART5_CTS = IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CS4__GPIO_3_20 = IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CS5__CS5 = IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CS5__NF_CE2 = IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CS5__UART5_RTS = IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL),
+ MX25_PAD_CS5__GPIO_3_21 = IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_NF_CE0__NF_CE0 = IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_NF_CE0__GPIO_3_22 = IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_ECB__ECB = IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_ECB__UART5_TXD_MUX = IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_ECB__GPIO_3_23 = IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LBA__LBA = IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_LBA__UART5_RXD_MUX = IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL),
+ MX25_PAD_LBA__GPIO_3_24 = IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_BCLK__BCLK = IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_BCLK__GPIO_4_4 = IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_RW__RW = IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_RW__AUD4_TXFS = IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL),
+ MX25_PAD_RW__GPIO_3_25 = IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_NFWE_B__NFWE_B = IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_NFWE_B__GPIO_3_26 = IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_NFRE_B__NFRE_B = IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_NFRE_B__GPIO_3_27 = IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_NFALE__NFALE = IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_NFALE__GPIO_3_28 = IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_NFCLE__NFCLE = IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_NFCLE__GPIO_3_29 = IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_NFWP_B__NFWP_B = IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_NFWP_B__GPIO_3_30 = IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE),
+ MX25_PAD_NFRB__GPIO_3_31 = IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D15__D15 = IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D15__LD16 = IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_D15__GPIO_4_5 = IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D14__D14 = IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D14__LD17 = IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_D14__GPIO_4_6 = IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D13__D13 = IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D13__LD18 = IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_D13__GPIO_4_7 = IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D12__D12 = IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D12__GPIO_4_8 = IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D11__D11 = IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D11__GPIO_4_9 = IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D10__D10 = IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D10__GPIO_4_10 = IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D10__USBOTG_OC = IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP),
+
+ MX25_PAD_D9__D9 = IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D9__GPIO_4_11 = IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D9__USBH2_PWR = IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE),
+
+ MX25_PAD_D8__D8 = IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D8__GPIO_4_12 = IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D8__USBH2_OC = IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP),
+
+ MX25_PAD_D7__D7 = IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D7__GPIO_4_13 = IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D6__D6 = IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D6__GPIO_4_14 = IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D5__D5 = IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D5__GPIO_4_15 = IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D4__D4 = IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D4__GPIO_4_16 = IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D3__D3 = IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D3__GPIO_4_17 = IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D2__D2 = IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D2__GPIO_4_18 = IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D1__D1 = IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D1__GPIO_4_19 = IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D0__D0 = IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D0__GPIO_4_20 = IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD0__LD0 = IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD0__CSI_D0 = IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL),
+ MX25_PAD_LD0__GPIO_2_15 = IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD1__LD1 = IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD1__CSI_D1 = IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL),
+ MX25_PAD_LD1__GPIO_2_16 = IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD2__LD2 = IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD2__GPIO_2_17 = IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD3__LD3 = IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD3__GPIO_2_18 = IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD4__LD4 = IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD4__GPIO_2_19 = IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD5__LD5 = IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD5__GPIO_1_19 = IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD6__LD6 = IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD6__GPIO_1_20 = IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD7__LD7 = IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD7__GPIO_1_21 = IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD8__LD8 = IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD8__FEC_TX_ERR = IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD9__LD9 = IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD9__FEC_COL = IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL),
+
+ MX25_PAD_LD10__LD10 = IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD10__FEC_RX_ER = IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL),
+
+ MX25_PAD_LD11__LD11 = IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD11__FEC_RDATA2 = IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL),
+
+ MX25_PAD_LD12__LD12 = IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL),
+
+ MX25_PAD_LD13__LD13 = IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD13__FEC_TDATA2 = IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD14__LD14 = IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD14__FEC_TDATA3 = IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD15__LD15 = IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD15__FEC_RX_CLK = IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL),
+
+ MX25_PAD_HSYNC__HSYNC = IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_HSYNC__GPIO_1_22 = IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_VSYNC__VSYNC = IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_VSYNC__GPIO_1_23 = IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LSCLK__LSCLK = IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_LSCLK__GPIO_1_24 = IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_OE_ACD__OE_ACD = IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_OE_ACD__GPIO_1_25 = IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CONTRAST__CONTRAST = IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CONTRAST__PWM4_PWMO = IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CONTRAST__FEC_CRS = IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL),
+
+ MX25_PAD_PWM__PWM = IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_PWM__GPIO_1_26 = IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP),
+
+ MX25_PAD_CSI_D2__CSI_D2 = IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D2__UART5_RXD_MUX = IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL),
+ MX25_PAD_CSI_D2__GPIO_1_27 = IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D2__CSPI3_MOSI = IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_D3__CSI_D3 = IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D3__GPIO_1_28 = IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D3__CSPI3_MISO = IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_D4__CSI_D4 = IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D4__UART5_RTS = IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL),
+ MX25_PAD_CSI_D4__GPIO_1_29 = IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D4__CSPI3_SCLK = IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_D5__CSI_D5 = IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D5__GPIO_1_30 = IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D5__CSPI3_RDY = IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_HSYNC__GPIO_1_10 = IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_PIXCLK__GPIO_1_11 = IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_I2C1_CLK__GPIO_1_12 = IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x11, 0x528, 1, NO_PAD_CTRL),
+ MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSPI1_SCLK__GPIO_1_18 = IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE),
+ MX25_PAD_CSPI1_RDY__GPIO_2_22 = IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN),
+ MX25_PAD_UART1_RXD__GPIO_4_22 = IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP),
+ MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL),
+ MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP),
+ MX25_PAD_UART1_CTS__CSI_D1 = IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL),
+ MX25_PAD_UART1_CTS__GPIO_4_25 = IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_UART2_RXD__GPIO_4_26 = IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_UART2_TXD__GPIO_4_27 = IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL),
+ MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL),
+ MX25_PAD_UART2_CTS__UART2_CTS = IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_UART2_CTS__GPIO_4_29 = IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+ MX25_PAD_SD1_CMD__FEC_RDATA2 = IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL),
+ MX25_PAD_SD1_CMD__GPIO_2_23 = IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+ MX25_PAD_SD1_CLK__FEC_RDATA3 = IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL),
+ MX25_PAD_SD1_CLK__GPIO_2_24 = IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+ MX25_PAD_SD1_DATA0__GPIO_2_25 = IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+ MX25_PAD_SD1_DATA1__AUD7_RXD = IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL),
+ MX25_PAD_SD1_DATA1__GPIO_2_26 = IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+ MX25_PAD_SD1_DATA2__FEC_RX_CLK = IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL),
+ MX25_PAD_SD1_DATA2__GPIO_2_27 = IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+ MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL),
+ MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+ MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+ MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+ MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL),
+ MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+ MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL),
+ MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_KPP_COL0__KPP_COL0 = IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
+ MX25_PAD_KPP_COL0__UART4_RXD_MUX = IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL),
+ MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
+ MX25_PAD_KPP_COL0__GPIO_3_1 = IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_KPP_COL1__KPP_COL1 = IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
+ MX25_PAD_KPP_COL1__UART4_TXD_MUX = IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
+ MX25_PAD_KPP_COL1__GPIO_3_2 = IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_KPP_COL2__KPP_COL2 = IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
+ MX25_PAD_KPP_COL2__UART4_RTS = IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
+ MX25_PAD_KPP_COL2__GPIO_3_3 = IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_KPP_COL3__KPP_COL3 = IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
+ MX25_PAD_KPP_COL3__UART4_CTS = IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_KPP_COL3__AUD5_TXFS = IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
+ MX25_PAD_KPP_COL3__GPIO_3_4 = IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_FEC_MDC__AUD4_TXD = IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL),
+ MX25_PAD_FEC_MDC__GPIO_3_5 = IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
+ MX25_PAD_FEC_MDIO__AUD4_RXD = IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL),
+ MX25_PAD_FEC_MDIO__GPIO_3_6 = IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_TDATA0__FEC_TDATA0 = IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_FEC_TDATA0__GPIO_3_7 = IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_TDATA1__FEC_TDATA1 = IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_FEC_TDATA1__AUD4_TXFS = IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL),
+ MX25_PAD_FEC_TDATA1__GPIO_3_8 = IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_FEC_TX_EN__GPIO_3_9 = IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_RDATA0__FEC_RDATA0 = IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ MX25_PAD_FEC_RDATA0__GPIO_3_10 = IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_RDATA1__FEC_RDATA1 = IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ MX25_PAD_FEC_RDATA1__GPIO_3_11 = IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ MX25_PAD_FEC_RX_DV__CAN2_RX = IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP),
+ MX25_PAD_FEC_RX_DV__GPIO_3_12 = IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ MX25_PAD_FEC_TX_CLK__GPIO_3_13 = IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_RTCK__RTCK = IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_RTCK__OWIRE = IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_RTCK__GPIO_3_14 = IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_DE_B__DE_B = IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_DE_B__GPIO_2_20 = IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_TDO__TDO = IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_GPIO_A__GPIO_A = IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_GPIO_A__CAN1_TX = IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP),
+ MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE),
+
+ MX25_PAD_GPIO_B__GPIO_B = IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_GPIO_B__CAN1_RX = IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP),
+ MX25_PAD_GPIO_B__USBOTG_OC = IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP),
+
+ MX25_PAD_GPIO_C__GPIO_C = IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP),
+
+ MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_GPIO_E__LD16 = IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP),
+
+ MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_GPIO_F__LD17 = IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x11, 0x524, 2, NO_PAD_CTRL),
+ MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_EXT_ARMCLK__GPIO_3_15 = IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK = IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_UPLL_BYPCLK__GPIO_3_16 = IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_VSTBY_REQ__VSTBY_REQ = IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_POWER_FAIL__AUD7_RXD = IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL),
+ MX25_PAD_POWER_FAIL__GPIO_3_19 = IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CLKO__CLKO = IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CLKO__GPIO_2_21 = IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_BOOT_MODE0__BOOT_MODE0 = IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_BOOT_MODE0__GPIO_4_30 = IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_BOOT_MODE1__BOOT_MODE1 = IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_BOOT_MODE1__GPIO_4_31 = IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CTL_GRP_DVS_MISC = IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_FEC = IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DVS_JTAG = IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_NFC = IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_CSI = IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_WEIM = IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_DDR = IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DVS_CRM = IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_KPP = IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_SDHC1 = IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_LCD = IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_UART = IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DVS_NFC = IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DVS_CSI = IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_CSPI1 = IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DDRTYPE = IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DVS_SDHC1 = IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DVS_LCD = IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX25_H__ */
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
- u32 iim_prog_p;
+ u32 iim_prg_p;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE)
#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE)
+#define IIM_BASE_ADDR IMX_IIM_BASE
#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE)
#define IMX_ESD_BASE (0xD8001000)
u32 test;
};
-/* IIM Control Registers */
+/* IIM control registers */
struct iim_regs {
u32 iim_stat;
u32 iim_statm;
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
- u32 iim_prog_p;
+ u32 iim_prg_p;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
u32 iim_scs3;
+ u32 res[0x1f1];
+ struct fuse_bank {
+ u32 fuse_regs[0x20];
+ u32 fuse_rsvd[0xe0];
+ } bank[3];
+};
+
+struct fuse_bank0_regs {
+ u32 fuse0_5[6];
+ u32 usr;
+ u32 fuse7_15[9];
+};
+
+struct fuse_bank2_regs {
+ u32 fuse0;
+ u32 uid[8];
+ u32 fuse9_15[7];
};
struct iomuxc_regs {
#define CCMR_CKIH (2 << 1)
#define MX31_IIM_BASE_ADDR 0x5001C000
+#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
#define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26)
#define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23)
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
- u32 iim_prog_p;
+ u32 iim_prg_p;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
u32 iim_scs3;
+ u32 res1[0x1f1];
+ struct fuse_bank {
+ u32 fuse_regs[0x20];
+ u32 fuse_rsvd[0xe0];
+ } bank[3];
+};
+
+struct fuse_bank0_regs {
+ u32 fuse0_7[8];
+ u32 uid[8];
+ u32 fuse16_31[0x10];
+};
+
+struct fuse_bank1_regs {
+ u32 fuse0_21[0x16];
+ u32 usr;
+ u32 fuse23_31[9];
};
/* General Purpose Timer (GPT) registers */
--- /dev/null
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on mainline Linux i.MX iomux-mx35.h file:
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IOMUX_MX35_H__
+#define __IOMUX_MX35_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/*
+ * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/* PAD MUX ALT INPSE PATH PADCTRL */
+enum {
+ MX35_PAD_CAPTURE__GPT_CAPIN1 = IOMUX_PAD(0x328, 0x004, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CAPTURE__GPT_CMPOUT2 = IOMUX_PAD(0x328, 0x004, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CAPTURE__CSPI2_SS1 = IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL),
+ MX35_PAD_CAPTURE__EPIT1_EPITO = IOMUX_PAD(0x328, 0x004, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CAPTURE__CCM_CLK32K = IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL),
+ MX35_PAD_CAPTURE__GPIO1_4 = IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL),
+
+ MX35_PAD_COMPARE__GPT_CMPOUT1 = IOMUX_PAD(0x32c, 0x008, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_COMPARE__GPT_CAPIN2 = IOMUX_PAD(0x32c, 0x008, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_COMPARE__GPT_CMPOUT3 = IOMUX_PAD(0x32c, 0x008, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_COMPARE__EPIT2_EPITO = IOMUX_PAD(0x32c, 0x008, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_COMPARE__GPIO1_5 = IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL),
+ MX35_PAD_COMPARE__SDMA_EXTDMA_2 = IOMUX_PAD(0x32c, 0x008, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_WDOG_RST__WDOG_WDOG_B = IOMUX_PAD(0x330, 0x00c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_WDOG_RST__IPU_FLASH_STROBE = IOMUX_PAD(0x330, 0x00c, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_WDOG_RST__GPIO1_6 = IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL),
+
+ MX35_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO1_0__CCM_PMIC_RDY = IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO1_0__OWIRE_LINE = IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 = IOMUX_PAD(0x334, 0x010, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_GPIO1_1__GPIO1_1 = IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO1_1__PWM_PWMO = IOMUX_PAD(0x338, 0x014, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO1_1__CSPI1_SS2 = IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT = IOMUX_PAD(0x338, 0x014, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 = IOMUX_PAD(0x338, 0x014, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_GPIO2_0__GPIO2_0 = IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK = IOMUX_PAD(0x33c, 0x018, 1, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_GPIO3_0__GPIO3_0 = IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK = IOMUX_PAD(0x340, 0x01c, 1, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_RESET_IN_B__CCM_RESET_IN_B = IOMUX_PAD(0x344, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_POR_B__CCM_POR_B = IOMUX_PAD(0x348, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CLKO__CCM_CLKO = IOMUX_PAD(0x34c, 0x020, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CLKO__GPIO1_8 = IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL),
+
+ MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 = IOMUX_PAD(0x350, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 = IOMUX_PAD(0x354, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 = IOMUX_PAD(0x358, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 = IOMUX_PAD(0x35c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 = IOMUX_PAD(0x360, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_VSTBY__CCM_VSTBY = IOMUX_PAD(0x364, 0x024, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_VSTBY__GPIO1_7 = IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A0__EMI_EIM_DA_L_0 = IOMUX_PAD(0x368, 0x028, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A1__EMI_EIM_DA_L_1 = IOMUX_PAD(0x36c, 0x02c, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A2__EMI_EIM_DA_L_2 = IOMUX_PAD(0x370, 0x030, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A3__EMI_EIM_DA_L_3 = IOMUX_PAD(0x374, 0x034, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A4__EMI_EIM_DA_L_4 = IOMUX_PAD(0x378, 0x038, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A5__EMI_EIM_DA_L_5 = IOMUX_PAD(0x37c, 0x03c, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A6__EMI_EIM_DA_L_6 = IOMUX_PAD(0x380, 0x040, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A7__EMI_EIM_DA_L_7 = IOMUX_PAD(0x384, 0x044, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A8__EMI_EIM_DA_H_8 = IOMUX_PAD(0x388, 0x048, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A9__EMI_EIM_DA_H_9 = IOMUX_PAD(0x38c, 0x04c, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A10__EMI_EIM_DA_H_10 = IOMUX_PAD(0x390, 0x050, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_MA10__EMI_MA10 = IOMUX_PAD(0x394, 0x054, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A11__EMI_EIM_DA_H_11 = IOMUX_PAD(0x398, 0x058, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A12__EMI_EIM_DA_H_12 = IOMUX_PAD(0x39c, 0x05c, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A13__EMI_EIM_DA_H_13 = IOMUX_PAD(0x3a0, 0x060, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A14__EMI_EIM_DA_H2_14 = IOMUX_PAD(0x3a4, 0x064, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A15__EMI_EIM_DA_H2_15 = IOMUX_PAD(0x3a8, 0x068, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A16__EMI_EIM_A_16 = IOMUX_PAD(0x3ac, 0x06c, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A17__EMI_EIM_A_17 = IOMUX_PAD(0x3b0, 0x070, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A18__EMI_EIM_A_18 = IOMUX_PAD(0x3b4, 0x074, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A19__EMI_EIM_A_19 = IOMUX_PAD(0x3b8, 0x078, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A20__EMI_EIM_A_20 = IOMUX_PAD(0x3bc, 0x07c, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A21__EMI_EIM_A_21 = IOMUX_PAD(0x3c0, 0x080, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A22__EMI_EIM_A_22 = IOMUX_PAD(0x3c4, 0x084, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A23__EMI_EIM_A_23 = IOMUX_PAD(0x3c8, 0x088, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A24__EMI_EIM_A_24 = IOMUX_PAD(0x3cc, 0x08c, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A25__EMI_EIM_A_25 = IOMUX_PAD(0x3d0, 0x090, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDBA1__EMI_EIM_SDBA1 = IOMUX_PAD(0x3d4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDBA0__EMI_EIM_SDBA0 = IOMUX_PAD(0x3d8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD0__EMI_DRAM_D_0 = IOMUX_PAD(0x3dc, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD1__EMI_DRAM_D_1 = IOMUX_PAD(0x3e0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD2__EMI_DRAM_D_2 = IOMUX_PAD(0x3e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD3__EMI_DRAM_D_3 = IOMUX_PAD(0x3e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD4__EMI_DRAM_D_4 = IOMUX_PAD(0x3ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD5__EMI_DRAM_D_5 = IOMUX_PAD(0x3f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD6__EMI_DRAM_D_6 = IOMUX_PAD(0x3f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD7__EMI_DRAM_D_7 = IOMUX_PAD(0x3f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD8__EMI_DRAM_D_8 = IOMUX_PAD(0x3fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD9__EMI_DRAM_D_9 = IOMUX_PAD(0x400, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD10__EMI_DRAM_D_10 = IOMUX_PAD(0x404, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD11__EMI_DRAM_D_11 = IOMUX_PAD(0x408, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD12__EMI_DRAM_D_12 = IOMUX_PAD(0x40c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD13__EMI_DRAM_D_13 = IOMUX_PAD(0x410, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD14__EMI_DRAM_D_14 = IOMUX_PAD(0x414, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD15__EMI_DRAM_D_15 = IOMUX_PAD(0x418, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD16__EMI_DRAM_D_16 = IOMUX_PAD(0x41c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD17__EMI_DRAM_D_17 = IOMUX_PAD(0x420, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD18__EMI_DRAM_D_18 = IOMUX_PAD(0x424, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD19__EMI_DRAM_D_19 = IOMUX_PAD(0x428, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD20__EMI_DRAM_D_20 = IOMUX_PAD(0x42c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD21__EMI_DRAM_D_21 = IOMUX_PAD(0x430, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD22__EMI_DRAM_D_22 = IOMUX_PAD(0x434, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD23__EMI_DRAM_D_23 = IOMUX_PAD(0x438, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD24__EMI_DRAM_D_24 = IOMUX_PAD(0x43c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD25__EMI_DRAM_D_25 = IOMUX_PAD(0x440, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD26__EMI_DRAM_D_26 = IOMUX_PAD(0x444, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD27__EMI_DRAM_D_27 = IOMUX_PAD(0x448, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD28__EMI_DRAM_D_28 = IOMUX_PAD(0x44c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD29__EMI_DRAM_D_29 = IOMUX_PAD(0x450, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD30__EMI_DRAM_D_30 = IOMUX_PAD(0x454, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD31__EMI_DRAM_D_31 = IOMUX_PAD(0x458, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_DQM0__EMI_DRAM_DQM_0 = IOMUX_PAD(0x45c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_DQM1__EMI_DRAM_DQM_1 = IOMUX_PAD(0x460, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_DQM2__EMI_DRAM_DQM_2 = IOMUX_PAD(0x464, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_DQM3__EMI_DRAM_DQM_3 = IOMUX_PAD(0x468, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_EB0__EMI_EIM_EB0_B = IOMUX_PAD(0x46c, 0x094, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_EB1__EMI_EIM_EB1_B = IOMUX_PAD(0x470, 0x098, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_OE__EMI_EIM_OE = IOMUX_PAD(0x474, 0x09c, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CS0__EMI_EIM_CS0 = IOMUX_PAD(0x478, 0x0a0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CS1__EMI_EIM_CS1 = IOMUX_PAD(0x47c, 0x0a4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CS1__EMI_NANDF_CE3 = IOMUX_PAD(0x47c, 0x0a4, 3, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CS2__EMI_EIM_CS2 = IOMUX_PAD(0x480, 0x0a8, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CS3__EMI_EIM_CS3 = IOMUX_PAD(0x484, 0x0ac, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CS4__EMI_EIM_CS4 = IOMUX_PAD(0x488, 0x0b0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CS4__EMI_DTACK_B = IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL),
+ MX35_PAD_CS4__EMI_NANDF_CE1 = IOMUX_PAD(0x488, 0x0b0, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CS4__GPIO1_20 = IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CS5__EMI_EIM_CS5 = IOMUX_PAD(0x48c, 0x0b4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CS5__CSPI2_SS2 = IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL),
+ MX35_PAD_CS5__CSPI1_SS2 = IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL),
+ MX35_PAD_CS5__EMI_NANDF_CE2 = IOMUX_PAD(0x48c, 0x0b4, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CS5__GPIO1_21 = IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL),
+
+ MX35_PAD_NF_CE0__EMI_NANDF_CE0 = IOMUX_PAD(0x490, 0x0b8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NF_CE0__GPIO1_22 = IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ECB__EMI_EIM_ECB = IOMUX_PAD(0x494, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LBA__EMI_EIM_LBA = IOMUX_PAD(0x498, 0x0bc, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_BCLK__EMI_EIM_BCLK = IOMUX_PAD(0x49c, 0x0c0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_RW__EMI_EIM_RW = IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_RAS__EMI_DRAM_RAS = IOMUX_PAD(0x4a4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CAS__EMI_DRAM_CAS = IOMUX_PAD(0x4a8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDWE__EMI_DRAM_SDWE = IOMUX_PAD(0x4ac, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 = IOMUX_PAD(0x4b0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 = IOMUX_PAD(0x4b4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDCLK__EMI_DRAM_SDCLK = IOMUX_PAD(0x4b8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 = IOMUX_PAD(0x4bc, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 = IOMUX_PAD(0x4c0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 = IOMUX_PAD(0x4c4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 = IOMUX_PAD(0x4c8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_NFWE_B__EMI_NANDF_WE_B = IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 = IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL),
+ MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL),
+ MX35_PAD_NFWE_B__GPIO2_18 = IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL),
+ MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 = IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_NFRE_B__EMI_NANDF_RE_B = IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR = IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL),
+ MX35_PAD_NFRE_B__IPU_DISPB_BCLK = IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFRE_B__GPIO2_19 = IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL),
+ MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 = IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_NFALE__EMI_NANDF_ALE = IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFALE__USB_TOP_USBH2_STP = IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFALE__IPU_DISPB_CS0 = IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFALE__GPIO2_20 = IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL),
+ MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 = IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_NFCLE__EMI_NANDF_CLE = IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFCLE__USB_TOP_USBH2_NXT = IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFCLE__IPU_DISPB_PAR_RS = IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFCLE__GPIO2_21 = IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL),
+ MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 = IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_NFWP_B__EMI_NANDF_WP_B = IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 = IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL),
+ MX35_PAD_NFWP_B__IPU_DISPB_WR = IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFWP_B__GPIO2_22 = IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL = IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_NFRB__EMI_NANDF_RB = IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFRB__IPU_DISPB_RD = IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFRB__GPIO2_23 = IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL),
+ MX35_PAD_NFRB__ARM11P_TOP_TRCLK = IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D15__EMI_EIM_D_15 = IOMUX_PAD(0x4e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D14__EMI_EIM_D_14 = IOMUX_PAD(0x4e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D13__EMI_EIM_D_13 = IOMUX_PAD(0x4ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D12__EMI_EIM_D_12 = IOMUX_PAD(0x4f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D11__EMI_EIM_D_11 = IOMUX_PAD(0x4f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D10__EMI_EIM_D_10 = IOMUX_PAD(0x4f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D9__EMI_EIM_D_9 = IOMUX_PAD(0x4fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D8__EMI_EIM_D_8 = IOMUX_PAD(0x500, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D7__EMI_EIM_D_7 = IOMUX_PAD(0x504, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D6__EMI_EIM_D_6 = IOMUX_PAD(0x508, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D5__EMI_EIM_D_5 = IOMUX_PAD(0x50c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D4__EMI_EIM_D_4 = IOMUX_PAD(0x510, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D3__EMI_EIM_D_3 = IOMUX_PAD(0x514, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D2__EMI_EIM_D_2 = IOMUX_PAD(0x518, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D1__EMI_EIM_D_1 = IOMUX_PAD(0x51c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D0__EMI_EIM_D_0 = IOMUX_PAD(0x520, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_D8__IPU_CSI_D_8 = IOMUX_PAD(0x524, 0x0e0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D8__KPP_COL_0 = IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D8__GPIO1_20 = IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL),
+ MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 = IOMUX_PAD(0x524, 0x0e0, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_D9__IPU_CSI_D_9 = IOMUX_PAD(0x528, 0x0e4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D9__KPP_COL_1 = IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D9__GPIO1_21 = IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL),
+ MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 = IOMUX_PAD(0x528, 0x0e4, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_D10__IPU_CSI_D_10 = IOMUX_PAD(0x52c, 0x0e8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D10__KPP_COL_2 = IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D10__GPIO1_22 = IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL),
+ MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 = IOMUX_PAD(0x52c, 0x0e8, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_D11__IPU_CSI_D_11 = IOMUX_PAD(0x530, 0x0ec, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D11__KPP_COL_3 = IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D11__GPIO1_23 = IOMUX_PAD(0x530, 0x0ec, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_D12__IPU_CSI_D_12 = IOMUX_PAD(0x534, 0x0f0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D12__KPP_ROW_0 = IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D12__GPIO1_24 = IOMUX_PAD(0x534, 0x0f0, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_D13__IPU_CSI_D_13 = IOMUX_PAD(0x538, 0x0f4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D13__KPP_ROW_1 = IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D13__GPIO1_25 = IOMUX_PAD(0x538, 0x0f4, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_D14__IPU_CSI_D_14 = IOMUX_PAD(0x53c, 0x0f8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D14__KPP_ROW_2 = IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D14__GPIO1_26 = IOMUX_PAD(0x53c, 0x0f8, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_D15__IPU_CSI_D_15 = IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D15__KPP_ROW_3 = IOMUX_PAD(0x540, 0x0fc, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D15__GPIO1_27 = IOMUX_PAD(0x540, 0x0fc, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_MCLK__IPU_CSI_MCLK = IOMUX_PAD(0x544, 0x100, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_MCLK__GPIO1_28 = IOMUX_PAD(0x544, 0x100, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC = IOMUX_PAD(0x548, 0x104, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_VSYNC__GPIO1_29 = IOMUX_PAD(0x548, 0x104, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC = IOMUX_PAD(0x54c, 0x108, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_HSYNC__GPIO1_30 = IOMUX_PAD(0x54c, 0x108, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK = IOMUX_PAD(0x550, 0x10c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_PIXCLK__GPIO1_31 = IOMUX_PAD(0x550, 0x10c, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_I2C1_CLK__I2C1_SCL = IOMUX_PAD(0x554, 0x110, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C1_CLK__GPIO2_24 = IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK = IOMUX_PAD(0x554, 0x110, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_I2C1_DAT__I2C1_SDA = IOMUX_PAD(0x558, 0x114, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C1_DAT__GPIO2_25 = IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL),
+
+ MX35_PAD_I2C2_CLK__I2C2_SCL = IOMUX_PAD(0x55c, 0x118, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C2_CLK__CAN1_TXCAN = IOMUX_PAD(0x55c, 0x118, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR = IOMUX_PAD(0x55c, 0x118, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C2_CLK__GPIO2_26 = IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x55c, 0x118, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_I2C2_DAT__I2C2_SDA = IOMUX_PAD(0x560, 0x11c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C2_DAT__CAN1_RXCAN = IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC = IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C2_DAT__GPIO2_27 = IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x560, 0x11c, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_STXD4__AUDMUX_AUD4_TXD = IOMUX_PAD(0x564, 0x120, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_STXD4__GPIO2_28 = IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL),
+ MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 = IOMUX_PAD(0x564, 0x120, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SRXD4__AUDMUX_AUD4_RXD = IOMUX_PAD(0x568, 0x124, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SRXD4__GPIO2_29 = IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL),
+ MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 = IOMUX_PAD(0x568, 0x124, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SCK4__AUDMUX_AUD4_TXC = IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SCK4__GPIO2_30 = IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL),
+ MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 = IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x570, 0x12c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_STXFS4__GPIO2_31 = IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL),
+ MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 = IOMUX_PAD(0x570, 0x12c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_STXD5__AUDMUX_AUD5_TXD = IOMUX_PAD(0x574, 0x130, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x574, 0x130, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_STXD5__CSPI2_MOSI = IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL),
+ MX35_PAD_STXD5__GPIO1_0 = IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL),
+ MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 = IOMUX_PAD(0x574, 0x130, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SRXD5__AUDMUX_AUD5_RXD = IOMUX_PAD(0x578, 0x134, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL),
+ MX35_PAD_SRXD5__CSPI2_MISO = IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL),
+ MX35_PAD_SRXD5__GPIO1_1 = IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL),
+ MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 = IOMUX_PAD(0x578, 0x134, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SCK5__AUDMUX_AUD5_TXC = IOMUX_PAD(0x57c, 0x138, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL),
+ MX35_PAD_SCK5__CSPI2_SCLK = IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL),
+ MX35_PAD_SCK5__GPIO1_2 = IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL),
+ MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 = IOMUX_PAD(0x57c, 0x138, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x580, 0x13c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_STXFS5__CSPI2_RDY = IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL),
+ MX35_PAD_STXFS5__GPIO1_3 = IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL),
+ MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 = IOMUX_PAD(0x580, 0x13c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SCKR__ESAI_SCKR = IOMUX_PAD(0x584, 0x140, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SCKR__GPIO1_4 = IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL),
+ MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 = IOMUX_PAD(0x584, 0x140, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FSR__ESAI_FSR = IOMUX_PAD(0x588, 0x144, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FSR__GPIO1_5 = IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL),
+ MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 = IOMUX_PAD(0x588, 0x144, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_HCKR__ESAI_HCKR = IOMUX_PAD(0x58c, 0x148, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_HCKR__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x58c, 0x148, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_HCKR__CSPI2_SS0 = IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL),
+ MX35_PAD_HCKR__IPU_FLASH_STROBE = IOMUX_PAD(0x58c, 0x148, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_HCKR__GPIO1_6 = IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL),
+ MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 = IOMUX_PAD(0x58c, 0x148, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SCKT__ESAI_SCKT = IOMUX_PAD(0x590, 0x14c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SCKT__GPIO1_7 = IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL),
+ MX35_PAD_SCKT__IPU_CSI_D_0 = IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL),
+ MX35_PAD_SCKT__KPP_ROW_2 = IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL),
+
+ MX35_PAD_FST__ESAI_FST = IOMUX_PAD(0x594, 0x150, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FST__GPIO1_8 = IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL),
+ MX35_PAD_FST__IPU_CSI_D_1 = IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL),
+ MX35_PAD_FST__KPP_ROW_3 = IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL),
+
+ MX35_PAD_HCKT__ESAI_HCKT = IOMUX_PAD(0x598, 0x154, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_HCKT__AUDMUX_AUD5_RXC = IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL),
+ MX35_PAD_HCKT__GPIO1_9 = IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL),
+ MX35_PAD_HCKT__IPU_CSI_D_2 = IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL),
+ MX35_PAD_HCKT__KPP_COL_3 = IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL),
+
+ MX35_PAD_TX5_RX0__ESAI_TX5_RX0 = IOMUX_PAD(0x59c, 0x158, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC = IOMUX_PAD(0x59c, 0x158, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX5_RX0__CSPI2_SS2 = IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL),
+ MX35_PAD_TX5_RX0__CAN2_TXCAN = IOMUX_PAD(0x59c, 0x158, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX5_RX0__UART2_DTR = IOMUX_PAD(0x59c, 0x158, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX5_RX0__GPIO1_10 = IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL),
+ MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 = IOMUX_PAD(0x59c, 0x158, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TX4_RX1__ESAI_TX4_RX1 = IOMUX_PAD(0x5a0, 0x15c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x5a0, 0x15c, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX4_RX1__CSPI2_SS3 = IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL),
+ MX35_PAD_TX4_RX1__CAN2_RXCAN = IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL),
+ MX35_PAD_TX4_RX1__UART2_DSR = IOMUX_PAD(0x5a0, 0x15c, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX4_RX1__GPIO1_11 = IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL),
+ MX35_PAD_TX4_RX1__IPU_CSI_D_3 = IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL),
+ MX35_PAD_TX4_RX1__KPP_ROW_0 = IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL),
+
+ MX35_PAD_TX3_RX2__ESAI_TX3_RX2 = IOMUX_PAD(0x5a4, 0x160, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX3_RX2__I2C3_SCL = IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL),
+ MX35_PAD_TX3_RX2__EMI_NANDF_CE1 = IOMUX_PAD(0x5a4, 0x160, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX3_RX2__GPIO1_12 = IOMUX_PAD(0x5a4, 0x160, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX3_RX2__IPU_CSI_D_4 = IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL),
+ MX35_PAD_TX3_RX2__KPP_ROW_1 = IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL),
+
+ MX35_PAD_TX2_RX3__ESAI_TX2_RX3 = IOMUX_PAD(0x5a8, 0x164, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX2_RX3__I2C3_SDA = IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL),
+ MX35_PAD_TX2_RX3__EMI_NANDF_CE2 = IOMUX_PAD(0x5a8, 0x164, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX2_RX3__GPIO1_13 = IOMUX_PAD(0x5a8, 0x164, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX2_RX3__IPU_CSI_D_5 = IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL),
+ MX35_PAD_TX2_RX3__KPP_COL_0 = IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL),
+
+ MX35_PAD_TX1__ESAI_TX1 = IOMUX_PAD(0x5ac, 0x168, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX1__CCM_PMIC_RDY = IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL),
+ MX35_PAD_TX1__CSPI1_SS2 = IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL),
+ MX35_PAD_TX1__EMI_NANDF_CE3 = IOMUX_PAD(0x5ac, 0x168, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX1__UART2_RI = IOMUX_PAD(0x5ac, 0x168, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX1__GPIO1_14 = IOMUX_PAD(0x5ac, 0x168, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX1__IPU_CSI_D_6 = IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL),
+ MX35_PAD_TX1__KPP_COL_1 = IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL),
+
+ MX35_PAD_TX0__ESAI_TX0 = IOMUX_PAD(0x5b0, 0x16c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL),
+ MX35_PAD_TX0__CSPI1_SS3 = IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL),
+ MX35_PAD_TX0__EMI_DTACK_B = IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL),
+ MX35_PAD_TX0__UART2_DCD = IOMUX_PAD(0x5b0, 0x16c, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX0__GPIO1_15 = IOMUX_PAD(0x5b0, 0x16c, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX0__IPU_CSI_D_7 = IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL),
+ MX35_PAD_TX0__KPP_COL_2 = IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL),
+
+ MX35_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x5b4, 0x170, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_MOSI__GPIO1_16 = IOMUX_PAD(0x5b4, 0x170, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 = IOMUX_PAD(0x5b4, 0x170, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x5b8, 0x174, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_MISO__GPIO1_17 = IOMUX_PAD(0x5b8, 0x174, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 = IOMUX_PAD(0x5b8, 0x174, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x5bc, 0x178, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS0__OWIRE_LINE = IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS0__CSPI2_SS3 = IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS0__GPIO1_18 = IOMUX_PAD(0x5bc, 0x178, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 = IOMUX_PAD(0x5bc, 0x178, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x5c0, 0x17c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS1__PWM_PWMO = IOMUX_PAD(0x5c0, 0x17c, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS1__CCM_CLK32K = IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS1__GPIO1_19 = IOMUX_PAD(0x5c0, 0x17c, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 = IOMUX_PAD(0x5c0, 0x17c, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 = IOMUX_PAD(0x5c0, 0x17c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x5c4, 0x180, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SCLK__GPIO3_4 = IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 = IOMUX_PAD(0x5c4, 0x180, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 = IOMUX_PAD(0x5c4, 0x180, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY = IOMUX_PAD(0x5c8, 0x184, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 = IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 = IOMUX_PAD(0x5c8, 0x184, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 = IOMUX_PAD(0x5c8, 0x184, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_RXD1__UART1_RXD_MUX = IOMUX_PAD(0x5cc, 0x188, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_RXD1__CSPI2_MOSI = IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL),
+ MX35_PAD_RXD1__KPP_COL_4 = IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL),
+ MX35_PAD_RXD1__GPIO3_6 = IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL),
+ MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 = IOMUX_PAD(0x5cc, 0x188, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TXD1__UART1_TXD_MUX = IOMUX_PAD(0x5d0, 0x18c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TXD1__CSPI2_MISO = IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL),
+ MX35_PAD_TXD1__KPP_COL_5 = IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL),
+ MX35_PAD_TXD1__GPIO3_7 = IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL),
+ MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 = IOMUX_PAD(0x5d0, 0x18c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_RTS1__UART1_RTS = IOMUX_PAD(0x5d4, 0x190, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_RTS1__CSPI2_SCLK = IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL),
+ MX35_PAD_RTS1__I2C3_SCL = IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL),
+ MX35_PAD_RTS1__IPU_CSI_D_0 = IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL),
+ MX35_PAD_RTS1__KPP_COL_6 = IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL),
+ MX35_PAD_RTS1__GPIO3_8 = IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL),
+ MX35_PAD_RTS1__EMI_NANDF_CE1 = IOMUX_PAD(0x5d4, 0x190, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 = IOMUX_PAD(0x5d4, 0x190, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CTS1__UART1_CTS = IOMUX_PAD(0x5d8, 0x194, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS1__CSPI2_RDY = IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL),
+ MX35_PAD_CTS1__I2C3_SDA = IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL),
+ MX35_PAD_CTS1__IPU_CSI_D_1 = IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL),
+ MX35_PAD_CTS1__KPP_COL_7 = IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS1__GPIO3_9 = IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS1__EMI_NANDF_CE2 = IOMUX_PAD(0x5d8, 0x194, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 = IOMUX_PAD(0x5d8, 0x194, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_RXD2__UART2_RXD_MUX = IOMUX_PAD(0x5dc, 0x198, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_RXD2__KPP_ROW_4 = IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL),
+ MX35_PAD_RXD2__GPIO3_10 = IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TXD2__UART2_TXD_MUX = IOMUX_PAD(0x5e0, 0x19c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL),
+ MX35_PAD_TXD2__KPP_ROW_5 = IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL),
+ MX35_PAD_TXD2__GPIO3_11 = IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_RTS2__UART2_RTS = IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_RTS2__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL),
+ MX35_PAD_RTS2__CAN2_RXCAN = IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL),
+ MX35_PAD_RTS2__IPU_CSI_D_2 = IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL),
+ MX35_PAD_RTS2__KPP_ROW_6 = IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL),
+ MX35_PAD_RTS2__GPIO3_12 = IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL),
+ MX35_PAD_RTS2__AUDMUX_AUD5_RXC = IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_RTS2__UART3_RXD_MUX = IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CTS2__UART2_CTS = IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS2__CAN2_TXCAN = IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS2__IPU_CSI_D_3 = IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL),
+ MX35_PAD_CTS2__KPP_ROW_7 = IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS2__GPIO3_13 = IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS2__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS2__UART3_TXD_MUX = IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_RTCK__ARM11P_TOP_RTCK = IOMUX_PAD(0x5ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TCK__SJC_TCK = IOMUX_PAD(0x5f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TMS__SJC_TMS = IOMUX_PAD(0x5f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TDI__SJC_TDI = IOMUX_PAD(0x5f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TDO__SJC_TDO = IOMUX_PAD(0x5fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TRSTB__SJC_TRSTB = IOMUX_PAD(0x600, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_DE_B__SJC_DE_B = IOMUX_PAD(0x604, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SJC_MOD__SJC_MOD = IOMUX_PAD(0x608, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR = IOMUX_PAD(0x60c, 0x1a8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR = IOMUX_PAD(0x60c, 0x1a8, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_USBOTG_PWR__GPIO3_14 = IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL),
+
+ MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC = IOMUX_PAD(0x610, 0x1ac, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC = IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL),
+ MX35_PAD_USBOTG_OC__GPIO3_15 = IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD0__IPU_DISPB_DAT_0 = IOMUX_PAD(0x614, 0x1b0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD0__GPIO2_0 = IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL),
+ MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 = IOMUX_PAD(0x614, 0x1b0, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD1__IPU_DISPB_DAT_1 = IOMUX_PAD(0x618, 0x1b4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD1__GPIO2_1 = IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL),
+ MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 = IOMUX_PAD(0x618, 0x1b4, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD2__IPU_DISPB_DAT_2 = IOMUX_PAD(0x61c, 0x1b8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD2__GPIO2_2 = IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 = IOMUX_PAD(0x61c, 0x1b8, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD3__IPU_DISPB_DAT_3 = IOMUX_PAD(0x620, 0x1bc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD3__GPIO2_3 = IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL),
+ MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 = IOMUX_PAD(0x620, 0x1bc, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD4__IPU_DISPB_DAT_4 = IOMUX_PAD(0x624, 0x1c0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD4__GPIO2_4 = IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 = IOMUX_PAD(0x624, 0x1c0, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD5__IPU_DISPB_DAT_5 = IOMUX_PAD(0x628, 0x1c4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD5__GPIO2_5 = IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL),
+ MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 = IOMUX_PAD(0x628, 0x1c4, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD6__IPU_DISPB_DAT_6 = IOMUX_PAD(0x62c, 0x1c8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD6__GPIO2_6 = IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL),
+ MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 = IOMUX_PAD(0x62c, 0x1c8, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD7__IPU_DISPB_DAT_7 = IOMUX_PAD(0x630, 0x1cc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD7__GPIO2_7 = IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL),
+ MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 = IOMUX_PAD(0x630, 0x1cc, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD8__IPU_DISPB_DAT_8 = IOMUX_PAD(0x634, 0x1d0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD8__GPIO2_8 = IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 = IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD9__IPU_DISPB_DAT_9 = IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD9__GPIO2_9 = IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL),
+ MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 = IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD10__IPU_DISPB_DAT_10 = IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD10__GPIO2_10 = IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL),
+ MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 = IOMUX_PAD(0x63c, 0x1d8, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD11__IPU_DISPB_DAT_11 = IOMUX_PAD(0x640, 0x1dc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD11__GPIO2_11 = IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL),
+ MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 = IOMUX_PAD(0x640, 0x1dc, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD11__ARM11P_TOP_TRACE_4 = IOMUX_PAD(0x640, 0x1dc, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD12__IPU_DISPB_DAT_12 = IOMUX_PAD(0x644, 0x1e0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD12__GPIO2_12 = IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL),
+ MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 = IOMUX_PAD(0x644, 0x1e0, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD12__ARM11P_TOP_TRACE_5 = IOMUX_PAD(0x644, 0x1e0, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD13__IPU_DISPB_DAT_13 = IOMUX_PAD(0x648, 0x1e4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD13__GPIO2_13 = IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL),
+ MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 = IOMUX_PAD(0x648, 0x1e4, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD13__ARM11P_TOP_TRACE_6 = IOMUX_PAD(0x648, 0x1e4, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD14__IPU_DISPB_DAT_14 = IOMUX_PAD(0x64c, 0x1e8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD14__GPIO2_14 = IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL),
+ MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x64c, 0x1e8, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD14__ARM11P_TOP_TRACE_7 = IOMUX_PAD(0x64c, 0x1e8, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD15__IPU_DISPB_DAT_15 = IOMUX_PAD(0x650, 0x1ec, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD15__GPIO2_15 = IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL),
+ MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x650, 0x1ec, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD15__ARM11P_TOP_TRACE_8 = IOMUX_PAD(0x650, 0x1ec, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD16__IPU_DISPB_DAT_16 = IOMUX_PAD(0x654, 0x1f0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD16__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL),
+ MX35_PAD_LD16__GPIO2_16 = IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL),
+ MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x654, 0x1f0, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD16__ARM11P_TOP_TRACE_9 = IOMUX_PAD(0x654, 0x1f0, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD17__IPU_DISPB_DAT_17 = IOMUX_PAD(0x658, 0x1f4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD17__IPU_DISPB_CS2 = IOMUX_PAD(0x658, 0x1f4, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD17__GPIO2_17 = IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL),
+ MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x658, 0x1f4, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD17__ARM11P_TOP_TRACE_10 = IOMUX_PAD(0x658, 0x1f4, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD18__IPU_DISPB_DAT_18 = IOMUX_PAD(0x65c, 0x1f8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD18__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL),
+ MX35_PAD_LD18__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL),
+ MX35_PAD_LD18__ESDHC3_CMD = IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL),
+ MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 = IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD18__GPIO3_24 = IOMUX_PAD(0x65c, 0x1f8, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x65c, 0x1f8, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD18__ARM11P_TOP_TRACE_11 = IOMUX_PAD(0x65c, 0x1f8, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD19__IPU_DISPB_DAT_19 = IOMUX_PAD(0x660, 0x1fc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD19__IPU_DISPB_BCLK = IOMUX_PAD(0x660, 0x1fc, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD19__IPU_DISPB_CS1 = IOMUX_PAD(0x660, 0x1fc, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD19__ESDHC3_CLK = IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL),
+ MX35_PAD_LD19__USB_TOP_USBOTG_DIR = IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL),
+ MX35_PAD_LD19__GPIO3_25 = IOMUX_PAD(0x660, 0x1fc, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x660, 0x1fc, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD19__ARM11P_TOP_TRACE_12 = IOMUX_PAD(0x660, 0x1fc, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD20__IPU_DISPB_DAT_20 = IOMUX_PAD(0x664, 0x200, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD20__IPU_DISPB_CS0 = IOMUX_PAD(0x664, 0x200, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD20__IPU_DISPB_SD_CLK = IOMUX_PAD(0x664, 0x200, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD20__ESDHC3_DAT0 = IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL),
+ MX35_PAD_LD20__GPIO3_26 = IOMUX_PAD(0x664, 0x200, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 = IOMUX_PAD(0x664, 0x200, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD20__ARM11P_TOP_TRACE_13 = IOMUX_PAD(0x664, 0x200, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD21__IPU_DISPB_DAT_21 = IOMUX_PAD(0x668, 0x204, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD21__IPU_DISPB_PAR_RS = IOMUX_PAD(0x668, 0x204, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD21__IPU_DISPB_SER_RS = IOMUX_PAD(0x668, 0x204, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD21__ESDHC3_DAT1 = IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL),
+ MX35_PAD_LD21__USB_TOP_USBOTG_STP = IOMUX_PAD(0x668, 0x204, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD21__GPIO3_27 = IOMUX_PAD(0x668, 0x204, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x668, 0x204, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD21__ARM11P_TOP_TRACE_14 = IOMUX_PAD(0x668, 0x204, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD22__IPU_DISPB_DAT_22 = IOMUX_PAD(0x66c, 0x208, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD22__IPU_DISPB_WR = IOMUX_PAD(0x66c, 0x208, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD22__IPU_DISPB_SD_D_I = IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL),
+ MX35_PAD_LD22__ESDHC3_DAT2 = IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL),
+ MX35_PAD_LD22__USB_TOP_USBOTG_NXT = IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL),
+ MX35_PAD_LD22__GPIO3_28 = IOMUX_PAD(0x66c, 0x208, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x66c, 0x208, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD22__ARM11P_TOP_TRCTL = IOMUX_PAD(0x66c, 0x208, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD23__IPU_DISPB_DAT_23 = IOMUX_PAD(0x670, 0x20c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD23__IPU_DISPB_RD = IOMUX_PAD(0x670, 0x20c, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD23__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL),
+ MX35_PAD_LD23__ESDHC3_DAT3 = IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL),
+ MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 = IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD23__GPIO3_29 = IOMUX_PAD(0x670, 0x20c, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x670, 0x20c, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD23__ARM11P_TOP_TRCLK = IOMUX_PAD(0x670, 0x20c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC = IOMUX_PAD(0x674, 0x210, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL),
+ MX35_PAD_D3_HSYNC__GPIO3_30 = IOMUX_PAD(0x674, 0x210, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x674, 0x210, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 = IOMUX_PAD(0x674, 0x210, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK = IOMUX_PAD(0x678, 0x214, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK = IOMUX_PAD(0x678, 0x214, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_FPSHIFT__GPIO3_31 = IOMUX_PAD(0x678, 0x214, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 = IOMUX_PAD(0x678, 0x214, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 = IOMUX_PAD(0x678, 0x214, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY = IOMUX_PAD(0x67c, 0x218, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O = IOMUX_PAD(0x67c, 0x218, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_DRDY__GPIO1_0 = IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL),
+ MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 = IOMUX_PAD(0x67c, 0x218, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 = IOMUX_PAD(0x67c, 0x218, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CONTRAST__IPU_DISPB_CONTR = IOMUX_PAD(0x680, 0x21c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CONTRAST__GPIO1_1 = IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL),
+ MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 = IOMUX_PAD(0x680, 0x21c, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 = IOMUX_PAD(0x680, 0x21c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC = IOMUX_PAD(0x684, 0x220, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 = IOMUX_PAD(0x684, 0x220, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_VSYNC__GPIO1_2 = IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL),
+ MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD = IOMUX_PAD(0x684, 0x220, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 = IOMUX_PAD(0x684, 0x220, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D3_REV__IPU_DISPB_D3_REV = IOMUX_PAD(0x688, 0x224, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_REV__IPU_DISPB_SER_RS = IOMUX_PAD(0x688, 0x224, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_REV__GPIO1_3 = IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL),
+ MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x688, 0x224, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 = IOMUX_PAD(0x688, 0x224, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS = IOMUX_PAD(0x68c, 0x228, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_CLS__IPU_DISPB_CS2 = IOMUX_PAD(0x68c, 0x228, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_CLS__GPIO1_4 = IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL),
+ MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x68c, 0x228, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 = IOMUX_PAD(0x68c, 0x228, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL = IOMUX_PAD(0x690, 0x22c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL),
+ MX35_PAD_D3_SPL__GPIO1_5 = IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL),
+ MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 = IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD1_CMD__ESDHC1_CMD = IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_CMD__MSHC_SCLK = IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL),
+ MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 = IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_CMD__GPIO1_6 = IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL),
+ MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL = IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD1_CLK__ESDHC1_CLK = IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_CLK__MSHC_BS = IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_CLK__IPU_DISPB_BCLK = IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 = IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_CLK__GPIO1_7 = IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL),
+ MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK = IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD1_DATA0__ESDHC1_DAT0 = IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA0__MSHC_DATA_0 = IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 = IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 = IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA0__GPIO1_8 = IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 = IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD1_DATA1__ESDHC1_DAT1 = IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA1__MSHC_DATA_1 = IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS = IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 = IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA1__GPIO1_9 = IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 = IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD1_DATA2__ESDHC1_DAT2 = IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA2__MSHC_DATA_2 = IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA2__IPU_DISPB_WR = IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 = IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA2__GPIO1_10 = IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 = IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD1_DATA3__ESDHC1_DAT3 = IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA3__MSHC_DATA_3 = IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA3__IPU_DISPB_RD = IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 = IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA3__GPIO1_11 = IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 = IOMUX_PAD(0x6a8, 0x244, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD2_CMD__ESDHC2_CMD = IOMUX_PAD(0x6ac, 0x248, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_CMD__I2C3_SCL = IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL),
+ MX35_PAD_SD2_CMD__ESDHC1_DAT4 = IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_CMD__IPU_CSI_D_2 = IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL),
+ MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 = IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_CMD__GPIO2_0 = IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL),
+ MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x6ac, 0x248, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL),
+
+ MX35_PAD_SD2_CLK__ESDHC2_CLK = IOMUX_PAD(0x6b0, 0x24c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_CLK__I2C3_SDA = IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL),
+ MX35_PAD_SD2_CLK__ESDHC1_DAT5 = IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_CLK__IPU_CSI_D_3 = IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL),
+ MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 = IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_CLK__GPIO2_1 = IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL),
+ MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL),
+ MX35_PAD_SD2_CLK__IPU_DISPB_CS2 = IOMUX_PAD(0x6b0, 0x24c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD2_DATA0__ESDHC2_DAT0 = IOMUX_PAD(0x6b4, 0x250, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA0__UART3_RXD_MUX = IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA0__ESDHC1_DAT6 = IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA0__IPU_CSI_D_4 = IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 = IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA0__GPIO2_2 = IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL),
+
+ MX35_PAD_SD2_DATA1__ESDHC2_DAT1 = IOMUX_PAD(0x6b8, 0x254, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA1__UART3_TXD_MUX = IOMUX_PAD(0x6b8, 0x254, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA1__ESDHC1_DAT7 = IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA1__IPU_CSI_D_5 = IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 = IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA1__GPIO2_3 = IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL),
+
+ MX35_PAD_SD2_DATA2__ESDHC2_DAT2 = IOMUX_PAD(0x6bc, 0x258, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA2__UART3_RTS = IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA2__CAN1_RXCAN = IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA2__IPU_CSI_D_6 = IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 = IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA2__GPIO2_4 = IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL),
+
+ MX35_PAD_SD2_DATA3__ESDHC2_DAT3 = IOMUX_PAD(0x6c0, 0x25c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA3__UART3_CTS = IOMUX_PAD(0x6c0, 0x25c, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA3__CAN1_TXCAN = IOMUX_PAD(0x6c0, 0x25c, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA3__IPU_CSI_D_7 = IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 = IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA3__GPIO2_5 = IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_CS0__ATA_CS0 = IOMUX_PAD(0x6c4, 0x260, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS0__CSPI1_SS3 = IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS0__IPU_DISPB_CS1 = IOMUX_PAD(0x6c4, 0x260, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS0__GPIO2_6 = IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS0__IPU_DIAGB_0 = IOMUX_PAD(0x6c4, 0x260, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 = IOMUX_PAD(0x6c4, 0x260, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_CS1__ATA_CS1 = IOMUX_PAD(0x6c8, 0x264, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS1__IPU_DISPB_CS2 = IOMUX_PAD(0x6c8, 0x264, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS1__CSPI2_SS0 = IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS1__GPIO2_7 = IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS1__IPU_DIAGB_1 = IOMUX_PAD(0x6c8, 0x264, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 = IOMUX_PAD(0x6c8, 0x264, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DIOR__ATA_DIOR = IOMUX_PAD(0x6cc, 0x268, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOR__ESDHC3_DAT0 = IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR = IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 = IOMUX_PAD(0x6cc, 0x268, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOR__CSPI2_SS1 = IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOR__GPIO2_8 = IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOR__IPU_DIAGB_2 = IOMUX_PAD(0x6cc, 0x268, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 = IOMUX_PAD(0x6cc, 0x268, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DIOW__ATA_DIOW = IOMUX_PAD(0x6d0, 0x26c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOW__ESDHC3_DAT1 = IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP = IOMUX_PAD(0x6d0, 0x26c, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 = IOMUX_PAD(0x6d0, 0x26c, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOW__CSPI2_MOSI = IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOW__GPIO2_9 = IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOW__IPU_DIAGB_3 = IOMUX_PAD(0x6d0, 0x26c, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 = IOMUX_PAD(0x6d0, 0x26c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DMACK__ATA_DMACK = IOMUX_PAD(0x6d4, 0x270, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMACK__ESDHC3_DAT2 = IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT = IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMACK__CSPI2_MISO = IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMACK__GPIO2_10 = IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMACK__IPU_DIAGB_4 = IOMUX_PAD(0x6d4, 0x270, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 = IOMUX_PAD(0x6d4, 0x270, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_RESET_B__ATA_RESET_B = IOMUX_PAD(0x6d8, 0x274, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 = IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 = IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O = IOMUX_PAD(0x6d8, 0x274, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_RESET_B__CSPI2_RDY = IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_RESET_B__GPIO2_11 = IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 = IOMUX_PAD(0x6d8, 0x274, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 = IOMUX_PAD(0x6d8, 0x274, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_IORDY__ATA_IORDY = IOMUX_PAD(0x6dc, 0x278, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_IORDY__ESDHC3_DAT4 = IOMUX_PAD(0x6dc, 0x278, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 = IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL),
+ MX35_PAD_ATA_IORDY__ESDHC2_DAT4 = IOMUX_PAD(0x6dc, 0x278, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_IORDY__GPIO2_12 = IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_IORDY__IPU_DIAGB_6 = IOMUX_PAD(0x6dc, 0x278, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 = IOMUX_PAD(0x6dc, 0x278, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA0__ATA_DATA_0 = IOMUX_PAD(0x6e0, 0x27c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA0__ESDHC3_DAT5 = IOMUX_PAD(0x6e0, 0x27c, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 = IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA0__ESDHC2_DAT5 = IOMUX_PAD(0x6e0, 0x27c, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA0__GPIO2_13 = IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA0__IPU_DIAGB_7 = IOMUX_PAD(0x6e0, 0x27c, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 = IOMUX_PAD(0x6e0, 0x27c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA1__ATA_DATA_1 = IOMUX_PAD(0x6e4, 0x280, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA1__ESDHC3_DAT6 = IOMUX_PAD(0x6e4, 0x280, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 = IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK = IOMUX_PAD(0x6e4, 0x280, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA1__ESDHC2_DAT6 = IOMUX_PAD(0x6e4, 0x280, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA1__GPIO2_14 = IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA1__IPU_DIAGB_8 = IOMUX_PAD(0x6e4, 0x280, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 = IOMUX_PAD(0x6e4, 0x280, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA2__ATA_DATA_2 = IOMUX_PAD(0x6e8, 0x284, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA2__ESDHC3_DAT7 = IOMUX_PAD(0x6e8, 0x284, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 = IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS = IOMUX_PAD(0x6e8, 0x284, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA2__ESDHC2_DAT7 = IOMUX_PAD(0x6e8, 0x284, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA2__GPIO2_15 = IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA2__IPU_DIAGB_9 = IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 = IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA3__ATA_DATA_3 = IOMUX_PAD(0x6ec, 0x288, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA3__ESDHC3_CLK = IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 = IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA3__CSPI2_SCLK = IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA3__GPIO2_16 = IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA3__IPU_DIAGB_10 = IOMUX_PAD(0x6ec, 0x288, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 = IOMUX_PAD(0x6ec, 0x288, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA4__ATA_DATA_4 = IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA4__ESDHC3_CMD = IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 = IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA4__GPIO2_17 = IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA4__IPU_DIAGB_11 = IOMUX_PAD(0x6f0, 0x28c, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 = IOMUX_PAD(0x6f0, 0x28c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA5__ATA_DATA_5 = IOMUX_PAD(0x6f4, 0x290, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 = IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA5__GPIO2_18 = IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA5__IPU_DIAGB_12 = IOMUX_PAD(0x6f4, 0x290, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 = IOMUX_PAD(0x6f4, 0x290, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA6__ATA_DATA_6 = IOMUX_PAD(0x6f8, 0x294, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA6__CAN1_TXCAN = IOMUX_PAD(0x6f8, 0x294, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA6__UART1_DTR = IOMUX_PAD(0x6f8, 0x294, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD = IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA6__GPIO2_19 = IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA6__IPU_DIAGB_13 = IOMUX_PAD(0x6f8, 0x294, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA7__ATA_DATA_7 = IOMUX_PAD(0x6fc, 0x298, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA7__CAN1_RXCAN = IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA7__UART1_DSR = IOMUX_PAD(0x6fc, 0x298, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD = IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA7__GPIO2_20 = IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA7__IPU_DIAGB_14 = IOMUX_PAD(0x6fc, 0x298, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA8__ATA_DATA_8 = IOMUX_PAD(0x700, 0x29c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA8__UART3_RTS = IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA8__UART1_RI = IOMUX_PAD(0x700, 0x29c, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC = IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA8__GPIO2_21 = IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA8__IPU_DIAGB_15 = IOMUX_PAD(0x700, 0x29c, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA9__ATA_DATA_9 = IOMUX_PAD(0x704, 0x2a0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA9__UART3_CTS = IOMUX_PAD(0x704, 0x2a0, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA9__UART1_DCD = IOMUX_PAD(0x704, 0x2a0, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA9__GPIO2_22 = IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA9__IPU_DIAGB_16 = IOMUX_PAD(0x704, 0x2a0, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA10__ATA_DATA_10 = IOMUX_PAD(0x708, 0x2a4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA10__UART3_RXD_MUX = IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC = IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA10__GPIO2_23 = IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA10__IPU_DIAGB_17 = IOMUX_PAD(0x708, 0x2a4, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA11__ATA_DATA_11 = IOMUX_PAD(0x70c, 0x2a8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA11__UART3_TXD_MUX = IOMUX_PAD(0x70c, 0x2a8, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA11__GPIO2_24 = IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA11__IPU_DIAGB_18 = IOMUX_PAD(0x70c, 0x2a8, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA12__ATA_DATA_12 = IOMUX_PAD(0x710, 0x2ac, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA12__I2C3_SCL = IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA12__GPIO2_25 = IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA12__IPU_DIAGB_19 = IOMUX_PAD(0x710, 0x2ac, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA13__ATA_DATA_13 = IOMUX_PAD(0x714, 0x2b0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA13__I2C3_SDA = IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA13__GPIO2_26 = IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA13__IPU_DIAGB_20 = IOMUX_PAD(0x714, 0x2b0, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA14__ATA_DATA_14 = IOMUX_PAD(0x718, 0x2b4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA14__IPU_CSI_D_0 = IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA14__KPP_ROW_0 = IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA14__GPIO2_27 = IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA14__IPU_DIAGB_21 = IOMUX_PAD(0x718, 0x2b4, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA15__ATA_DATA_15 = IOMUX_PAD(0x71c, 0x2b8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA15__IPU_CSI_D_1 = IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA15__KPP_ROW_1 = IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA15__GPIO2_28 = IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA15__IPU_DIAGB_22 = IOMUX_PAD(0x71c, 0x2b8, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_INTRQ__ATA_INTRQ = IOMUX_PAD(0x720, 0x2bc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 = IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL),
+ MX35_PAD_ATA_INTRQ__KPP_ROW_2 = IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_INTRQ__GPIO2_29 = IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 = IOMUX_PAD(0x720, 0x2bc, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN = IOMUX_PAD(0x724, 0x2c0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 = IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL),
+ MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 = IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_BUFF_EN__GPIO2_30 = IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 = IOMUX_PAD(0x724, 0x2c0, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DMARQ__ATA_DMARQ = IOMUX_PAD(0x728, 0x2c4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 = IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMARQ__KPP_COL_0 = IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMARQ__GPIO2_31 = IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 = IOMUX_PAD(0x728, 0x2c4, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 = IOMUX_PAD(0x728, 0x2c4, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DA0__ATA_DA_0 = IOMUX_PAD(0x72c, 0x2c8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA0__IPU_CSI_D_5 = IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA0__KPP_COL_1 = IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA0__GPIO3_0 = IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA0__IPU_DIAGB_26 = IOMUX_PAD(0x72c, 0x2c8, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 = IOMUX_PAD(0x72c, 0x2c8, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DA1__ATA_DA_1 = IOMUX_PAD(0x730, 0x2cc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA1__IPU_CSI_D_6 = IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA1__KPP_COL_2 = IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA1__GPIO3_1 = IOMUX_PAD(0x730, 0x2cc, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA1__IPU_DIAGB_27 = IOMUX_PAD(0x730, 0x2cc, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 = IOMUX_PAD(0x730, 0x2cc, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DA2__ATA_DA_2 = IOMUX_PAD(0x734, 0x2d0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA2__IPU_CSI_D_7 = IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA2__KPP_COL_3 = IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA2__GPIO3_2 = IOMUX_PAD(0x734, 0x2d0, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA2__IPU_DIAGB_28 = IOMUX_PAD(0x734, 0x2d0, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 = IOMUX_PAD(0x734, 0x2d0, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_MLB_CLK__MLB_MLBCLK = IOMUX_PAD(0x738, 0x2d4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_MLB_CLK__GPIO3_3 = IOMUX_PAD(0x738, 0x2d4, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_MLB_DAT__MLB_MLBDAT = IOMUX_PAD(0x73c, 0x2d8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_MLB_DAT__GPIO3_4 = IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL),
+
+ MX35_PAD_MLB_SIG__MLB_MLBSIG = IOMUX_PAD(0x740, 0x2dc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_MLB_SIG__GPIO3_5 = IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x744, 0x2e0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 = IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX = IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR = IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_CLK__CSPI2_MOSI = IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_CLK__GPIO3_6 = IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 = IOMUX_PAD(0x744, 0x2e0, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_RX_CLK__FEC_RX_CLK = IOMUX_PAD(0x748, 0x2e4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 = IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX = IOMUX_PAD(0x748, 0x2e4, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP = IOMUX_PAD(0x748, 0x2e4, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_CLK__CSPI2_MISO = IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_CLK__GPIO3_7 = IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I = IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 = IOMUX_PAD(0x748, 0x2e4, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x74c, 0x2e8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 = IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_DV__UART3_RTS = IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT = IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_DV__CSPI2_SCLK = IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_DV__GPIO3_8 = IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK = IOMUX_PAD(0x74c, 0x2e8, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 = IOMUX_PAD(0x74c, 0x2e8, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_COL__FEC_COL = IOMUX_PAD(0x750, 0x2ec, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_COL__ESDHC1_DAT7 = IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_COL__UART3_CTS = IOMUX_PAD(0x750, 0x2ec, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 = IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_COL__CSPI2_RDY = IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_COL__GPIO3_9 = IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_COL__IPU_DISPB_SER_RS = IOMUX_PAD(0x750, 0x2ec, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 = IOMUX_PAD(0x750, 0x2ec, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_RDATA0__FEC_RDATA_0 = IOMUX_PAD(0x754, 0x2f0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA0__PWM_PWMO = IOMUX_PAD(0x754, 0x2f0, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA0__UART3_DTR = IOMUX_PAD(0x754, 0x2f0, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 = IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA0__CSPI2_SS0 = IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA0__GPIO3_10 = IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 = IOMUX_PAD(0x754, 0x2f0, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 = IOMUX_PAD(0x754, 0x2f0, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_TDATA0__FEC_TDATA_0 = IOMUX_PAD(0x758, 0x2f4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x758, 0x2f4, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA0__UART3_DSR = IOMUX_PAD(0x758, 0x2f4, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 = IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA0__CSPI2_SS1 = IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA0__GPIO3_11 = IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 = IOMUX_PAD(0x758, 0x2f4, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 = IOMUX_PAD(0x758, 0x2f4, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x75c, 0x2f8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_EN__UART3_RI = IOMUX_PAD(0x75c, 0x2f8, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 = IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_EN__GPIO3_12 = IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS = IOMUX_PAD(0x75c, 0x2f8, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 = IOMUX_PAD(0x75c, 0x2f8, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x760, 0x2fc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDC__CAN2_TXCAN = IOMUX_PAD(0x760, 0x2fc, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDC__UART3_DCD = IOMUX_PAD(0x760, 0x2fc, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 = IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDC__GPIO3_13 = IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDC__IPU_DISPB_WR = IOMUX_PAD(0x760, 0x2fc, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 = IOMUX_PAD(0x760, 0x2fc, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x764, 0x300, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDIO__CAN2_RXCAN = IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 = IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDIO__GPIO3_14 = IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDIO__IPU_DISPB_RD = IOMUX_PAD(0x764, 0x300, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 = IOMUX_PAD(0x764, 0x300, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_TX_ERR__FEC_TX_ERR = IOMUX_PAD(0x768, 0x304, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_ERR__OWIRE_LINE = IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 = IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_ERR__GPIO3_15 = IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 = IOMUX_PAD(0x768, 0x304, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_RX_ERR__FEC_RX_ERR = IOMUX_PAD(0x76c, 0x308, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 = IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 = IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_ERR__KPP_COL_4 = IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_ERR__GPIO3_16 = IOMUX_PAD(0x76c, 0x308, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_CRS__FEC_CRS = IOMUX_PAD(0x770, 0x30c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_CRS__IPU_CSI_D_1 = IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR = IOMUX_PAD(0x770, 0x30c, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_CRS__KPP_COL_5 = IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_CRS__GPIO3_17 = IOMUX_PAD(0x770, 0x30c, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_CRS__IPU_FLASH_STROBE = IOMUX_PAD(0x770, 0x30c, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_RDATA1__FEC_RDATA_1 = IOMUX_PAD(0x774, 0x310, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 = IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC = IOMUX_PAD(0x774, 0x310, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC = IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA1__KPP_COL_6 = IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA1__GPIO3_18 = IOMUX_PAD(0x774, 0x310, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 = IOMUX_PAD(0x774, 0x310, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_TDATA1__FEC_TDATA_1 = IOMUX_PAD(0x778, 0x314, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 = IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA1__KPP_COL_7 = IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA1__GPIO3_19 = IOMUX_PAD(0x778, 0x314, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 = IOMUX_PAD(0x778, 0x314, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_RDATA2__FEC_RDATA_2 = IOMUX_PAD(0x77c, 0x318, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 = IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA2__KPP_ROW_4 = IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA2__GPIO3_20 = IOMUX_PAD(0x77c, 0x318, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_TDATA2__FEC_TDATA_2 = IOMUX_PAD(0x780, 0x31c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 = IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD = IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA2__KPP_ROW_5 = IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA2__GPIO3_21 = IOMUX_PAD(0x780, 0x31c, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_RDATA3__FEC_RDATA_3 = IOMUX_PAD(0x784, 0x320, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 = IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC = IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA3__KPP_ROW_6 = IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA3__GPIO3_22 = IOMUX_PAD(0x784, 0x320, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_TDATA3__FEC_TDATA_3 = IOMUX_PAD(0x788, 0x324, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 = IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA3__KPP_ROW_7 = IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA3__GPIO3_23 = IOMUX_PAD(0x788, 0x324, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK = IOMUX_PAD(0x78c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX35_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __MACH_MX35_IOMUX_H__
-#define __MACH_MX35_IOMUX_H__
-
-#include <asm/arch/imx-regs.h>
-
-/*
- * various IOMUX functions
- */
-typedef enum iomux_pin_config {
- MUX_CONFIG_FUNC = 0, /* used as function */
- MUX_CONFIG_ALT1, /* used as alternate function 1 */
- MUX_CONFIG_ALT2, /* used as alternate function 2 */
- MUX_CONFIG_ALT3, /* used as alternate function 3 */
- MUX_CONFIG_ALT4, /* used as alternate function 4 */
- MUX_CONFIG_ALT5, /* used as alternate function 5 */
- MUX_CONFIG_ALT6, /* used as alternate function 6 */
- MUX_CONFIG_ALT7, /* used as alternate function 7 */
- MUX_CONFIG_SION = 0x1 << 4, /* used as LOOPBACK:MUX SION bit */
- MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /* used as GPIO */
-} iomux_pin_cfg_t;
-
-/*
- * various IOMUX pad functions
- */
-typedef enum iomux_pad_config {
- PAD_CTL_DRV_3_3V = 0x0 << 13,
- PAD_CTL_DRV_1_8V = 0x1 << 13,
- PAD_CTL_HYS_CMOS = 0x0 << 8,
- PAD_CTL_HYS_SCHMITZ = 0x1 << 8,
- PAD_CTL_PKE_NONE = 0x0 << 7,
- PAD_CTL_PKE_ENABLE = 0x1 << 7,
- PAD_CTL_PUE_KEEPER = 0x0 << 6,
- PAD_CTL_PUE_PUD = 0x1 << 6,
- PAD_CTL_100K_PD = 0x0 << 4,
- PAD_CTL_47K_PU = 0x1 << 4,
- PAD_CTL_100K_PU = 0x2 << 4,
- PAD_CTL_22K_PU = 0x3 << 4,
- PAD_CTL_ODE_CMOS = 0x0 << 3,
- PAD_CTL_ODE_OpenDrain = 0x1 << 3,
- PAD_CTL_DRV_NORMAL = 0x0 << 1,
- PAD_CTL_DRV_HIGH = 0x1 << 1,
- PAD_CTL_DRV_MAX = 0x2 << 1,
- PAD_CTL_SRE_SLOW = 0x0 << 0,
- PAD_CTL_SRE_FAST = 0x1 << 0
-} iomux_pad_config_t;
-
-/*
- * various IOMUX general purpose functions
- */
-typedef enum iomux_gp_func {
- MUX_SDCTL_CSD0_SEL = 0x1 << 0,
- MUX_SDCTL_CSD1_SEL = 0x1 << 1,
- MUX_TAMPER_DETECT_EN = 0x1 << 2,
-} iomux_gp_func_t;
-
-/*
- * various IOMUX input select register index
- */
-typedef enum iomux_input_select {
- MUX_IN_AMX_P5_RXCLK = 0,
- MUX_IN_AMX_P5_RXFS,
- MUX_IN_AMX_P6_DA,
- MUX_IN_AMX_P6_DB,
- MUX_IN_AMX_P6_RXCLK,
- MUX_IN_AMX_P6_RXFS,
- MUX_IN_AMX_P6_TXCLK,
- MUX_IN_AMX_P6_TXFS,
- MUX_IN_CAN1_CANRX,
- MUX_IN_CAN2_CANRX,
- MUX_IN_CCM_32K_MUXED,
- MUX_IN_CCM_PMIC_RDY,
- MUX_IN_CSPI1_SS2_B,
- MUX_IN_CSPI1_SS3_B,
- MUX_IN_CSPI2_CLK_IN,
- MUX_IN_CSPI2_DATAREADY_B,
- MUX_IN_CSPI2_MISO,
- MUX_IN_CSPI2_MOSI,
- MUX_IN_CSPI2_SS0_B,
- MUX_IN_CSPI2_SS1_B,
- MUX_IN_CSPI2_SS2_B,
- MUX_IN_CSPI2_SS3_B,
- MUX_IN_EMI_WEIM_DTACK_B,
- MUX_IN_ESDHC1_DAT4_IN,
- MUX_IN_ESDHC1_DAT5_IN,
- MUX_IN_ESDHC1_DAT6_IN,
- MUX_IN_ESDHC1_DAT7_IN,
- MUX_IN_ESDHC3_CARD_CLK_IN,
- MUX_IN_ESDHC3_CMD_IN,
- MUX_IN_ESDHC3_DAT0,
- MUX_IN_ESDHC3_DAT1,
- MUX_IN_ESDHC3_DAT2,
- MUX_IN_ESDHC3_DAT3,
- MUX_IN_GPIO1_IN_0,
- MUX_IN_GPIO1_IN_10,
- MUX_IN_GPIO1_IN_11,
- MUX_IN_GPIO1_IN_1,
- MUX_IN_GPIO1_IN_20,
- MUX_IN_GPIO1_IN_21,
- MUX_IN_GPIO1_IN_22,
- MUX_IN_GPIO1_IN_2,
- MUX_IN_GPIO1_IN_3,
- MUX_IN_GPIO1_IN_4,
- MUX_IN_GPIO1_IN_5,
- MUX_IN_GPIO1_IN_6,
- MUX_IN_GPIO1_IN_7,
- MUX_IN_GPIO1_IN_8,
- MUX_IN_GPIO1_IN_9,
- MUX_IN_GPIO2_IN_0,
- MUX_IN_GPIO2_IN_10,
- MUX_IN_GPIO2_IN_11,
- MUX_IN_GPIO2_IN_12,
- MUX_IN_GPIO2_IN_13,
- MUX_IN_GPIO2_IN_14,
- MUX_IN_GPIO2_IN_15,
- MUX_IN_GPIO2_IN_16,
- MUX_IN_GPIO2_IN_17,
- MUX_IN_GPIO2_IN_18,
- MUX_IN_GPIO2_IN_19,
- MUX_IN_GPIO2_IN_20,
- MUX_IN_GPIO2_IN_21,
- MUX_IN_GPIO2_IN_22,
- MUX_IN_GPIO2_IN_23,
- MUX_IN_GPIO2_IN_24,
- MUX_IN_GPIO2_IN_25,
- MUX_IN_GPIO2_IN_26,
- MUX_IN_GPIO2_IN_27,
- MUX_IN_GPIO2_IN_28,
- MUX_IN_GPIO2_IN_29,
- MUX_IN_GPIO2_IN_2,
- MUX_IN_GPIO2_IN_30,
- MUX_IN_GPIO2_IN_31,
- MUX_IN_GPIO2_IN_3,
- MUX_IN_GPIO2_IN_4,
- MUX_IN_GPIO2_IN_5,
- MUX_IN_GPIO2_IN_6,
- MUX_IN_GPIO2_IN_7,
- MUX_IN_GPIO2_IN_8,
- MUX_IN_GPIO2_IN_9,
- MUX_IN_GPIO3_IN_0,
- MUX_IN_GPIO3_IN_10,
- MUX_IN_GPIO3_IN_11,
- MUX_IN_GPIO3_IN_12,
- MUX_IN_GPIO3_IN_13,
- MUX_IN_GPIO3_IN_14,
- MUX_IN_GPIO3_IN_15,
- MUX_IN_GPIO3_IN_4,
- MUX_IN_GPIO3_IN_5,
- MUX_IN_GPIO3_IN_6,
- MUX_IN_GPIO3_IN_7,
- MUX_IN_GPIO3_IN_8,
- MUX_IN_GPIO3_IN_9,
- MUX_IN_I2C3_SCL_IN,
- MUX_IN_I2C3_SDA_IN,
- MUX_IN_IPU_DISPB_D0_VSYNC,
- MUX_IN_IPU_DISPB_D12_VSYNC,
- MUX_IN_IPU_DISPB_SD_D,
- MUX_IN_IPU_SENSB_DATA_0,
- MUX_IN_IPU_SENSB_DATA_1,
- MUX_IN_IPU_SENSB_DATA_2,
- MUX_IN_IPU_SENSB_DATA_3,
- MUX_IN_IPU_SENSB_DATA_4,
- MUX_IN_IPU_SENSB_DATA_5,
- MUX_IN_IPU_SENSB_DATA_6,
- MUX_IN_IPU_SENSB_DATA_7,
- MUX_IN_KPP_COL_0,
- MUX_IN_KPP_COL_1,
- MUX_IN_KPP_COL_2,
- MUX_IN_KPP_COL_3,
- MUX_IN_KPP_COL_4,
- MUX_IN_KPP_COL_5,
- MUX_IN_KPP_COL_6,
- MUX_IN_KPP_COL_7,
- MUX_IN_KPP_ROW_0,
- MUX_IN_KPP_ROW_1,
- MUX_IN_KPP_ROW_2,
- MUX_IN_KPP_ROW_3,
- MUX_IN_KPP_ROW_4,
- MUX_IN_KPP_ROW_5,
- MUX_IN_KPP_ROW_6,
- MUX_IN_KPP_ROW_7,
- MUX_IN_OWIRE_BATTERY_LINE,
- MUX_IN_SPDIF_HCKT_CLK2,
- MUX_IN_SPDIF_SPDIF_IN1,
- MUX_IN_UART3_UART_RTS_B,
- MUX_IN_UART3_UART_RXD_MUX,
- MUX_IN_USB_OTG_DATA_0,
- MUX_IN_USB_OTG_DATA_1,
- MUX_IN_USB_OTG_DATA_2,
- MUX_IN_USB_OTG_DATA_3,
- MUX_IN_USB_OTG_DATA_4,
- MUX_IN_USB_OTG_DATA_5,
- MUX_IN_USB_OTG_DATA_6,
- MUX_IN_USB_OTG_DATA_7,
- MUX_IN_USB_OTG_DIR,
- MUX_IN_USB_OTG_NXT,
- MUX_IN_USB_UH2_DATA_0,
- MUX_IN_USB_UH2_DATA_1,
- MUX_IN_USB_UH2_DATA_2,
- MUX_IN_USB_UH2_DATA_3,
- MUX_IN_USB_UH2_DATA_4,
- MUX_IN_USB_UH2_DATA_5,
- MUX_IN_USB_UH2_DATA_6,
- MUX_IN_USB_UH2_DATA_7,
- MUX_IN_USB_UH2_DIR,
- MUX_IN_USB_UH2_NXT,
- MUX_IN_USB_UH2_USB_OC,
-} iomux_input_select_t;
-
-/*
- * various IOMUX input functions
- */
-typedef enum iomux_input_config {
- INPUT_CTL_PATH0 = 0x0,
- INPUT_CTL_PATH1,
- INPUT_CTL_PATH2,
- INPUT_CTL_PATH3,
- INPUT_CTL_PATH4,
- INPUT_CTL_PATH5,
- INPUT_CTL_PATH6,
- INPUT_CTL_PATH7,
-} iomux_input_cfg_t;
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param pin a name defined by iomux_pin_name_t
- * @param cfg an input function as defined in iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
-
-/*
- * Release ownership for an IO pin
- *
- * @param pin a name defined by iomux_pin_name_t
- * @param cfg an input function as defined in iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
-
-/*
- * This function enables/disables the general purpose function for a particular
- * signal.
- *
- * @param gp one signal as defined in iomux_gp_func_t
- * @param en 1 to enable; 0 to disable
- */
-void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en);
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in iomux_pin_name_t
- * @param config the ORed value of elements defined in
- * iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
-
-/*
- * This function configures input path.
- *
- * @param input index of input select register as defined in
- * iomux_input_select_t
- * @param config the binary value of elements defined in
- * iomux_input_cfg_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MXC_MX35_PINS_H__
-#define __ASM_ARCH_MXC_MX35_PINS_H__
-
-/*!
- * @file arch-mxc/mx35_pins.h
- *
- * @brief MX35 I/O Pin List
- *
- * @ingroup GPIO_MX35
- */
-
-#ifndef __ASSEMBLY__
-
-/*!
- * @name IOMUX/PAD Bit field definitions
- */
-
-/*! @{ */
-
-/*!
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P | IO_I | RSVD | PAD_I | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 7 contains MUX_I used to identify the register
- * offset (base is IOMUX_module_base ) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The similar field
- * definitions are used for the pad control register.the MX35_PIN_A0 is
- * defined in the enumeration: ( 0x28 << MUX_I) |( 0x368 << PAD_I)
- * So the absolute address is: IOMUX_module_base + 0x28.
- * The pad control register offset is: 0x368.
- */
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I 0
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I 10
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * reserved filed
- */
-#define RSVD_I 21
-
-#define MUX_IO_P 29
-#define MUX_IO_I 24
-#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
- GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
- ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
-#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-
-#define NON_GPIO_I 0x7
-#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1)
-#define NON_MUX_I PIN_TO_MUX_MASK
-
-#define _MXC_BUILD_PIN(gp, gi, mi, pi) \
- (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
- ((mi) << MUX_I) | ((pi) << PAD_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \
- _MXC_BUILD_PIN(gp, gi, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
- _MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
-
-/*! @} End IOMUX/PAD Bit field definitions */
-
-/*!
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX35 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-typedef enum iomux_pins {
- MX35_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 4, 0x4, 0x328),
- MX35_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 5, 0x8, 0x32C),
- MX35_PIN_WATCHDOG_RST = _MXC_BUILD_GPIO_PIN(0, 6, 0xC, 0x330),
- MX35_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 0x10, 0x334),
- MX35_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 0x14, 0x338),
- MX35_PIN_GPIO2_0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x18, 0x33C),
- MX35_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1C, 0x340),
- MX35_PIN_CLKO = _MXC_BUILD_GPIO_PIN(0, 8, 0x20, 0x34C),
-
- MX35_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x360),
- MX35_PIN_VSTBY = _MXC_BUILD_GPIO_PIN(0, 7, 0x24, 0x364),
- MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368),
- MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C),
- MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370),
- MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374),
- MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378),
- MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C),
- MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380),
- MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384),
- MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388),
- MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C),
- MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390),
- MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394),
- MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398),
- MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C),
- MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0),
- MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4),
- MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8),
- MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC),
- MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0),
- MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4),
- MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8),
- MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC),
- MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0),
- MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4),
- MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8),
- MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC),
- MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0),
-
- MX35_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x46C),
- MX35_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x470),
- MX35_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x474),
- MX35_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x478),
- MX35_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x47C),
- MX35_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x480),
- MX35_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x484),
- MX35_PIN_CS4 = _MXC_BUILD_GPIO_PIN(0, 20, 0xB0, 0x488),
- MX35_PIN_CS5 = _MXC_BUILD_GPIO_PIN(0, 21, 0xB4, 0x48C),
- MX35_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xB8, 0x490),
-
- MX35_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(0xBC, 0x498),
- MX35_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(0xC0, 0x49C),
- MX35_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(0xC4, 0x4A0),
-
- MX35_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(0, 18, 0xC8, 0x4CC),
- MX35_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(0, 19, 0xCC, 0x4D0),
- MX35_PIN_NFALE = _MXC_BUILD_GPIO_PIN(0, 20, 0xD0, 0x4D4),
- MX35_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(0, 21, 0xD4, 0x4D8),
- MX35_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xD8, 0x4DC),
- MX35_PIN_NFRB = _MXC_BUILD_GPIO_PIN(0, 23, 0xDC, 0x4E0),
-
- MX35_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E4),
- MX35_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E8),
- MX35_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4EC),
- MX35_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F0),
- MX35_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F4),
- MX35_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F8),
- MX35_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4FC),
- MX35_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x500),
- MX35_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x504),
- MX35_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x508),
- MX35_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x50C),
- MX35_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x510),
- MX35_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x514),
- MX35_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x518),
- MX35_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x51C),
- MX35_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x520),
-
- MX35_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 20, 0xE0, 0x524),
- MX35_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(0, 21, 0xE4, 0x528),
- MX35_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(0, 22, 0xE8, 0x52C),
- MX35_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(0, 23, 0xEC, 0x530),
- MX35_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(0, 24, 0xF0, 0x534),
- MX35_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(0, 25, 0xF4, 0x538),
- MX35_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(0, 26, 0xF8, 0x53C),
- MX35_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(0, 27, 0xFC, 0x540),
- MX35_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 28, 0x100, 0x544),
- MX35_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 29, 0x104, 0x548),
- MX35_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 30, 0x108, 0x54C),
- MX35_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 31, 0x10C, 0x550),
-
- MX35_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x110, 0x554),
- MX35_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(1, 25, 0x114, 0x558),
- MX35_PIN_I2C2_CLK = _MXC_BUILD_GPIO_PIN(1, 26, 0x118, 0x55C),
- MX35_PIN_I2C2_DAT = _MXC_BUILD_GPIO_PIN(1, 27, 0x11C, 0x560),
-
- MX35_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(1, 28, 0x120, 0x564),
- MX35_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(1, 29, 0x124, 0x568),
- MX35_PIN_SCK4 = _MXC_BUILD_GPIO_PIN(1, 30, 0x128, 0x56C),
- MX35_PIN_STXFS4 = _MXC_BUILD_GPIO_PIN(1, 31, 0x12C, 0x570),
- MX35_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 0, 0x130, 0x574),
- MX35_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 1, 0x134, 0x578),
- MX35_PIN_SCK5 = _MXC_BUILD_GPIO_PIN(0, 2, 0x138, 0x57C),
- MX35_PIN_STXFS5 = _MXC_BUILD_GPIO_PIN(0, 3, 0x13C, 0x580),
-
- MX35_PIN_SCKR = _MXC_BUILD_GPIO_PIN(0, 4, 0x140, 0x584),
- MX35_PIN_FSR = _MXC_BUILD_GPIO_PIN(0, 5, 0x144, 0x588),
- MX35_PIN_HCKR = _MXC_BUILD_GPIO_PIN(0, 6, 0x148, 0x58C),
- MX35_PIN_SCKT = _MXC_BUILD_GPIO_PIN(0, 7, 0x14C, 0x590),
- MX35_PIN_FST = _MXC_BUILD_GPIO_PIN(0, 8, 0x150, 0x594),
- MX35_PIN_HCKT = _MXC_BUILD_GPIO_PIN(0, 9, 0x154, 0x598),
- MX35_PIN_TX5_RX0 = _MXC_BUILD_GPIO_PIN(0, 10, 0x158, 0x59C),
- MX35_PIN_TX4_RX1 = _MXC_BUILD_GPIO_PIN(0, 11, 0x15C, 0x5A0),
- MX35_PIN_TX3_RX2 = _MXC_BUILD_GPIO_PIN(0, 12, 0x160, 0x5A4),
- MX35_PIN_TX2_RX3 = _MXC_BUILD_GPIO_PIN(0, 13, 0x164, 0x5A8),
- MX35_PIN_TX1 = _MXC_BUILD_GPIO_PIN(0, 14, 0x168, 0x5AC),
- MX35_PIN_TX0 = _MXC_BUILD_GPIO_PIN(0, 15, 0x16C, 0x5B0),
-
- MX35_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 16, 0x170, 0x5B4),
- MX35_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 17, 0x174, 0x5B8),
- MX35_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 18, 0x178, 0x5BC),
- MX35_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 19, 0x17C, 0x5C0),
- MX35_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(2, 4, 0x180, 0x5C4),
- MX35_PIN_CSPI1_SPI_RDY = _MXC_BUILD_GPIO_PIN(2, 5, 0x184, 0x5C8),
-
- MX35_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(2, 6, 0x188, 0x5CC),
- MX35_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(2, 7, 0x18C, 0x5D0),
- MX35_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x190, 0x5D4),
- MX35_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(2, 9, 0x194, 0x5D8),
- MX35_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(2, 10, 0x198, 0x5DC),
- MX35_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(1, 11, 0x19C, 0x5E0),
- MX35_PIN_RTS2 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1A0, 0x5E4),
- MX35_PIN_CTS2 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1A4, 0x5E8),
-
- MX35_PIN_USBOTG_PWR = _MXC_BUILD_GPIO_PIN(2, 14, 0x1A8, 0x60C),
- MX35_PIN_USBOTG_OC = _MXC_BUILD_GPIO_PIN(2, 15, 0x1AC, 0x610),
-
- MX35_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x1B0, 0x614),
- MX35_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 1, 0x1B4, 0x618),
- MX35_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 2, 0x1B8, 0x61C),
- MX35_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1BC, 0x620),
- MX35_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 4, 0x1C0, 0x624),
- MX35_PIN_LD5 = _MXC_BUILD_GPIO_PIN(1, 5, 0x1C4, 0x628),
- MX35_PIN_LD6 = _MXC_BUILD_GPIO_PIN(1, 6, 0x1C8, 0x62C),
- MX35_PIN_LD7 = _MXC_BUILD_GPIO_PIN(1, 7, 0x1CC, 0x630),
- MX35_PIN_LD8 = _MXC_BUILD_GPIO_PIN(1, 8, 0x1D0, 0x634),
- MX35_PIN_LD9 = _MXC_BUILD_GPIO_PIN(1, 9, 0x1D4, 0x638),
- MX35_PIN_LD10 = _MXC_BUILD_GPIO_PIN(1, 10, 0x1D8, 0x63C),
- MX35_PIN_LD11 = _MXC_BUILD_GPIO_PIN(1, 11, 0x1DC, 0x640),
- MX35_PIN_LD12 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1E0, 0x644),
- MX35_PIN_LD13 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1E4, 0x648),
- MX35_PIN_LD14 = _MXC_BUILD_GPIO_PIN(1, 14, 0x1E8, 0x64C),
- MX35_PIN_LD15 = _MXC_BUILD_GPIO_PIN(1, 15, 0x1EC, 0x650),
- MX35_PIN_LD16 = _MXC_BUILD_GPIO_PIN(1, 16, 0x1F0, 0x654),
- MX35_PIN_LD17 = _MXC_BUILD_GPIO_PIN(1, 17, 0x1F4, 0x658),
- MX35_PIN_LD18 = _MXC_BUILD_GPIO_PIN(2, 24, 0x1F8, 0x65C),
- MX35_PIN_LD19 = _MXC_BUILD_GPIO_PIN(2, 25, 0x1FC, 0x660),
- MX35_PIN_LD20 = _MXC_BUILD_GPIO_PIN(2, 26, 0x200, 0x664),
- MX35_PIN_LD21 = _MXC_BUILD_GPIO_PIN(2, 27, 0x204, 0x668),
- MX35_PIN_LD22 = _MXC_BUILD_GPIO_PIN(2, 28, 0x208, 0x66C),
- MX35_PIN_LD23 = _MXC_BUILD_GPIO_PIN(2, 29, 0x20C, 0x670),
-
- MX35_PIN_D3_HSYNC = _MXC_BUILD_GPIO_PIN(2, 30, 0x210, 0x674),
- MX35_PIN_D3_FPSHIFT = _MXC_BUILD_GPIO_PIN(2, 31, 0x214, 0x678),
- MX35_PIN_D3_DRDY = _MXC_BUILD_GPIO_PIN(0, 0, 0x218, 0x67C),
- MX35_PIN_CONTRAST = _MXC_BUILD_GPIO_PIN(0, 1, 0x21C, 0x680),
- MX35_PIN_D3_VSYNC = _MXC_BUILD_GPIO_PIN(0, 2, 0x220, 0x684),
- MX35_PIN_D3_REV = _MXC_BUILD_GPIO_PIN(0, 3, 0x224, 0x688),
- MX35_PIN_D3_CLS = _MXC_BUILD_GPIO_PIN(0, 4, 0x228, 0x68C),
- MX35_PIN_D3_SPL = _MXC_BUILD_GPIO_PIN(0, 5, 0x22C, 0x690),
-
- MX35_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 6, 0x230, 0x694),
- MX35_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 7, 0x234, 0x698),
- MX35_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 8, 0x238, 0x69C),
- MX35_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 9, 0x23C, 0x6A0),
- MX35_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 10, 0x240, 0x6A4),
- MX35_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 11, 0x244, 0x6A8),
- MX35_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(1, 0, 0x248, 0x6AC),
- MX35_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(1, 1, 0x24C, 0x6B0),
- MX35_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(1, 2, 0x250, 0x6B4),
- MX35_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(1, 3, 0x254, 0x6B8),
- MX35_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(1, 4, 0x258, 0x6BC),
- MX35_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(1, 5, 0x25C, 0x6C0),
-
- MX35_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(1, 6, 0x260, 0x6C4),
- MX35_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(1, 7, 0x264, 0x6C8),
- MX35_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(1, 8, 0x268, 0x6CC),
- MX35_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(1, 9, 0x26C, 0x6D0),
- MX35_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(1, 10, 0x270, 0x6D4),
- MX35_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(1, 11, 0x274, 0x6D8),
- MX35_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(1, 12, 0x278, 0x6DC),
- MX35_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 13, 0x27C, 0x6E0),
- MX35_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 14, 0x280, 0x6E4),
- MX35_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 15, 0x284, 0x6E8),
- MX35_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 16, 0x288, 0x6EC),
- MX35_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 17, 0x28C, 0x6F0),
- MX35_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 18, 0x290, 0x6F4),
- MX35_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 19, 0x294, 0x6F8),
- MX35_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 20, 0x298, 0x6FC),
- MX35_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 21, 0x29C, 0x700),
- MX35_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 22, 0x2A0, 0x704),
- MX35_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 23, 0x2A4, 0x708),
- MX35_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 24, 0x2A8, 0x70C),
- MX35_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 25, 0x2AC, 0x710),
- MX35_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 26, 0x2B0, 0x714),
- MX35_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 27, 0x2B4, 0x718),
- MX35_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 28, 0x2B8, 0x71C),
- MX35_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(1, 29, 0x2BC, 0x720),
- MX35_PIN_ATA_BUFF_EN = _MXC_BUILD_GPIO_PIN(1, 30, 0x2C0, 0x724),
- MX35_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(1, 31, 0x2C4, 0x728),
- MX35_PIN_ATA_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 0x2C8, 0x72C),
- MX35_PIN_ATA_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 0x2CC, 0x730),
- MX35_PIN_ATA_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 0x2D0, 0x734),
-
- MX35_PIN_MLB_CLK = _MXC_BUILD_GPIO_PIN(2, 3, 0x2D4, 0x738),
- MX35_PIN_MLB_DAT = _MXC_BUILD_GPIO_PIN(2, 4, 0x2D8, 0x73C),
- MX35_PIN_MLB_SIG = _MXC_BUILD_GPIO_PIN(2, 5, 0x2DC, 0x740),
-
- MX35_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 6, 0x2E0, 0x744),
- MX35_PIN_FEC_RX_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 0x2E4, 0x748),
- MX35_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 8, 0x2E8, 0x74C),
- MX35_PIN_FEC_COL = _MXC_BUILD_GPIO_PIN(2, 9, 0x2EC, 0x750),
- MX35_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x2F0, 0x754),
- MX35_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 11, 0x2F4, 0x758),
- MX35_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 12, 0x2F8, 0x75C),
- MX35_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 13, 0x2FC, 0x760),
- MX35_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 14, 0x300, 0x764),
- MX35_PIN_FEC_TX_ERR = _MXC_BUILD_GPIO_PIN(2, 15, 0x304, 0x768),
- MX35_PIN_FEC_RX_ERR = _MXC_BUILD_GPIO_PIN(2, 16, 0x308, 0x76C),
- MX35_PIN_FEC_CRS = _MXC_BUILD_GPIO_PIN(2, 17, 0x30C, 0x770),
- MX35_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 18, 0x310, 0x774),
- MX35_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 19, 0x314, 0x778),
- MX35_PIN_FEC_RDATA2 = _MXC_BUILD_GPIO_PIN(2, 20, 0x318, 0x77C),
- MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780),
- MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784),
- MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788),
-} iomux_pin_name_t;
-
-#endif
-#endif
void enable_usboh3_clk(unsigned char enable);
void mxc_set_sata_internal_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
+void enable_nfc_clk(unsigned char enable);
#endif /* __ASM_ARCH_CLOCK_H */
/* M4IF */
#define M4IF_FBPM0 0x40
#define M4IF_FIDBP 0x48
+#define M4IF_GENP_WEIM_MM_MASK 0x00000001
+#define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
/* Assuming 24MHz input clock with doubler ON */
/* MFI PDF */
u32 sdat;
u32 prev;
u32 srev;
- u32 preg_p;
+ u32 prg_p;
u32 scs0;
u32 scs1;
u32 scs2;
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
+#if defined(CONFIG_MX51)
} bank[4];
+#elif defined(CONFIG_MX53)
+ } bank[5];
+#endif
};
struct fuse_bank0_regs {
- u32 fuse0_23[24];
+ u32 fuse0_7[8];
+ u32 uid[8];
+ u32 fuse16_23[8];
+#if defined(CONFIG_MX51)
+ u32 imei[8];
+#elif defined(CONFIG_MX53)
u32 gp[8];
+#endif
};
struct fuse_bank1_regs {
u32 fuse15_31[0x11];
};
+#if defined(CONFIG_MX53)
+struct fuse_bank4_regs {
+ u32 fuse0_4[5];
+ u32 gp[3];
+ u32 fuse8_31[0x18];
+};
+#endif
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */
#include <asm/imx-common/iomux-v3.h>
-#define PAD_CTL_DVS (1 << 13)
-#define PAD_CTL_INPUT_DDR (1 << 9)
-#define PAD_CTL_HYS (1 << 8)
-
-#define PAD_CTL_PKE (1 << 7)
-#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
-#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
-
-#define PAD_CTL_ODE (1 << 3)
-
-#define PAD_CTL_DSE_LOW (0 << 1)
-#define PAD_CTL_DSE_MED (1 << 1)
-#define PAD_CTL_DSE_HIGH (2 << 1)
-#define PAD_CTL_DSE_MAX (3 << 1)
-
-#define PAD_CTL_SRE_FAST (1 << 0)
-#define PAD_CTL_SRE_SLOW (0 << 0)
-
/* Pad control groupings */
-#define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
+#define MX51_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
PAD_CTL_HYS | PAD_CTL_SRE_FAST)
#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
PAD_CTL_HYS)
-#define MX51_USBH1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
- PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
- PAD_CTL_HYS | PAD_CTL_PUE)
+#define MX51_USBH_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
#define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \
PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
-#define MX51_SDHCI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
- PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
+#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
PAD_CTL_SRE_FAST | PAD_CTL_DVS)
#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
-#define __NA_ 0x000
+#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* See also iomux-v3.h
*/
-/* PAD MUX ALT INPSE PATH PADCTRL */
+/* PAD MUX ALT INPSE PATH PADCTRL */
enum {
- MX51_PAD_EIM_D16__USBH2_DATA0 = IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D17__USBH2_DATA1 = IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D18__USBH2_DATA2 = IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D19__USBH2_DATA3 = IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D20__USBH2_DATA4 = IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_D16__USBH2_DATA0 = IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D17__GPIO2_1 = IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_D17__USBH2_DATA1 = IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D18__USBH2_DATA2 = IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D19__USBH2_DATA3 = IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D20__USBH2_DATA4 = IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D21__GPIO2_5 = IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_EIM_D26__UART3_TXD = IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL),
MX51_PAD_EIM_D27__GPIO2_9 = IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_EIM_A24__USBH2_CLK = IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_A25__USBH2_DIR = IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_A16__GPIO2_10 = IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A17__GPIO2_11 = IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A20__GPIO2_14 = IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A22__GPIO2_16 = IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A24__USBH2_CLK = IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_A25__USBH2_DIR = IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
MX51_PAD_EIM_A26__GPIO2_20 = IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_EB2__FEC_MDIO = IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, PAD_CTL_PUS_22K_UP | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_HYS),
+ MX51_PAD_EIM_EB3__FEC_RDATA1 = IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_EB3__GPIO2_23 = IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_EIM_CS0__GPIO2_25 = IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_EIM_CS2__SD1_CD = IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+ MX51_PAD_EIM_CS2__FEC_RDATA2 = IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS2__GPIO2_27 = IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_CS3__FEC_RDATA3 = IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL),
MX51_PAD_EIM_CS3__GPIO2_28 = IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_CS4__FEC_RX_ER = IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2),
MX51_PAD_EIM_CS4__GPIO2_29 = IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_CS5__FEC_CRS = IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2),
+ MX51_PAD_DRAM_RAS__DRAM_RAS = IOMUX_PAD(0x4a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_CAS__DRAM_CAS = IOMUX_PAD(0x4a8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDWE__DRAM_SDWE = IOMUX_PAD(0x4ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0 = IOMUX_PAD(0x4b0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1 = IOMUX_PAD(0x4b4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDCLK__DRAM_SDCLK = IOMUX_PAD(0x4b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDQS0__DRAM_SDQS0 = IOMUX_PAD(0x4bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDQS1__DRAM_SDQS1 = IOMUX_PAD(0x4c0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDQS2__DRAM_SDQS2 = IOMUX_PAD(0x4c4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDQS3__DRAM_SDQS3 = IOMUX_PAD(0x4c8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_CS0__DRAM_CS0 = IOMUX_PAD(0x4cc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_CS1__DRAM_CS1 = IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_DQM0__DRAM_DQM0 = IOMUX_PAD(0x4d4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_DQM1__DRAM_DQM1 = IOMUX_PAD(0x4d8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_DQM2__DRAM_DQM2 = IOMUX_PAD(0x4dc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_DQM3__DRAM_DQM3 = IOMUX_PAD(0x4e0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_WE_B__PATA_DIOW = IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_RE_B__PATA_DIOR = IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_ALE__PATA_BUFFER_EN = IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_WP_B__PATA_DMACK = IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_RB0__PATA_DMARQ = IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_RB1__PATA_IORDY = IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RB2__FEC_COL = IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2),
+ MX51_PAD_NANDF_RB2__GPIO3_10 = IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_RB3__FEC_RX_CLK = IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2),
+ MX51_PAD_NANDF_RB3__GPIO3_11 = IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO_NAND__PATA_INTRQ = IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS2__FEC_TX_ER = IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_NANDF_CS2__PATA_CS_0 = IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS3__FEC_MDC = IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_NANDF_CS3__PATA_CS_1 = IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS4__FEC_TDATA1 = IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_NANDF_CS4__PATA_DA_0 = IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS5__FEC_TDATA2 = IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_NANDF_CS5__PATA_DA_1 = IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS6__FEC_TDATA3 = IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_NANDF_CS6__PATA_DA_2 = IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS7__FEC_TX_EN = IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK = IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4),
+ MX51_PAD_NANDF_D15__GPIO3_25 = IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_NANDF_D15__PATA_DATA15 = IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D14__GPIO3_26 = IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_NANDF_D14__PATA_DATA14 = IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D13__GPIO3_27 = IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_NANDF_D13__PATA_DATA13 = IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_D12__PATA_DATA12 = IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D11__FEC_RX_DV = IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_D11__PATA_DATA11 = IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D10__GPIO3_30 = IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_NANDF_D10__PATA_DATA10 = IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D9__FEC_RDATA0 = IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4),
+ MX51_PAD_NANDF_D9__GPIO3_31 = IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_NANDF_D9__PATA_DATA9 = IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D8__FEC_TDATA0 = IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_NANDF_D8__PATA_DATA8 = IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_D7__PATA_DATA7 = IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_D6__PATA_DATA6 = IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_D2__PATA_DATA2 = IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_D1__PATA_DATA1 = IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_D0__PATA_DATA0 = IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_CSI2_D12__GPIO4_9 = IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSI2_D13__GPIO4_10 = IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
MX51_PAD_CSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_CSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
MX51_PAD_CSPI1_SS0__GPIO4_24 = IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSPI1_SS1__ECSPI1_SS1 = IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
MX51_PAD_CSPI1_SS1__GPIO4_25 = IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSPI1_RDY__ECSPI1_RDY = IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_CSPI1_RDY__GPIO4_26 = IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
MX51_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL),
MX51_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL),
MX51_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL),
MX51_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL),
- MX51_PAD_USBH1_CLK__USBH1_CLK = IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DIR__USBH1_DIR = IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_STP__USBH1_STP = IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+ MX51_PAD_USBH1_CLK__USBH1_CLK = IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DIR__USBH1_DIR = IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
MX51_PAD_USBH1_STP__GPIO1_27 = IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_USBH1_NXT__USBH1_NXT = IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA0__USBH1_DATA0 = IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA1__USBH1_DATA1 = IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA2__USBH1_DATA2 = IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA3__USBH1_DATA3 = IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA4__USBH1_DATA4 = IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA5__USBH1_DATA5 = IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA6__USBH1_DATA6 = IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA7__USBH1_DATA7 = IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+ MX51_PAD_USBH1_STP__USBH1_STP = IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_NXT__USBH1_NXT = IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA0__USBH1_DATA0 = IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA1__USBH1_DATA1 = IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA2__USBH1_DATA2 = IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA3__USBH1_DATA3 = IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA4__USBH1_DATA4 = IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA5__USBH1_DATA5 = IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA6__USBH1_DATA6 = IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA7__USBH1_DATA7 = IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_DI1_PIN11__ECSPI1_SS2 = IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_DI1_PIN12__GPIO3_1 = IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DI1_PIN13__GPIO3_2 = IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DI1_D0_CS__GPIO3_3 = IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DI1_D1_CS__GPIO3_4 = IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DISPB2_SER_DIN__GPIO3_5 = IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DISPB2_SER_DIO__GPIO3_6 = IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DI1_PIN3__DI1_PIN3 = IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DI1_PIN2__DI1_PIN2 = IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK = IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DI_GP4__DI2_PIN15 = IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
MX51_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+ MX51_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO1_0__SD1_CD = IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
MX51_PAD_GPIO1_1__SD1_WP = IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
MX51_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+ MX51_PAD_GPIO1_2__GPIO1_2 = IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_GPIO1_2__PWM1_PWMO = IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_GPIO1_3__GPIO1_3 = IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO1_5__GPIO1_5 = IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO1_6__GPIO1_6 = IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_GPIO1_7__GPIO1_7 = IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO1_7__SD2_WP = IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
MX51_PAD_GPIO1_8__SD2_CD = IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+ MX51_GRP_DDRPKS = IOMUX_PAD(0x820, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_B4 = IOMUX_PAD(0x82c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_PKEDDR = IOMUX_PAD(0x838, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDR_A0 = IOMUX_PAD(0x83c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDR_A1 = IOMUX_PAD(0x848, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDRAPUS = IOMUX_PAD(0x84c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_HYSDDR0 = IOMUX_PAD(0x85c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_HYSDDR1 = IOMUX_PAD(0x864, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_HYSDDR2 = IOMUX_PAD(0x86c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_HYSDDR3 = IOMUX_PAD(0x874, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_SR_B0 = IOMUX_PAD(0x878, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDRAPKS = IOMUX_PAD(0x87c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_SR_B1 = IOMUX_PAD(0x880, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDRPUS = IOMUX_PAD(0x884, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_SR_B2 = IOMUX_PAD(0x88c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_PKEADDR = IOMUX_PAD(0x890, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_SR_B4 = IOMUX_PAD(0x89c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_INMODE1 = IOMUX_PAD(0x8a0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_B0 = IOMUX_PAD(0x8a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_B1 = IOMUX_PAD(0x8ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_B2 = IOMUX_PAD(0x8b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDR_SR_A1 = IOMUX_PAD(0x8bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
};
#endif /* __IOMUX_MX51_H__ */
--- /dev/null
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on Freescale's Linux i.MX iomux-mx53.h file:
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IOMUX_MX53_H__
+#define __IOMUX_MX53_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Pad control groupings */
+#define MX53_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
+
+/*
+ * The naming convention for the pad modes is MX53_PAD_<padname>__<padmode>
+ * If <padname> refers to a GPIO, it is named GPIO_<unit>
+ * If <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/* PAD MUX ALT INPSE PATH PADCTRL */
+enum {
+ MX53_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_19__GPIO4_5 = IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 = IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_19__FEC_TDATA_3 = IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL0__GPIO4_6 = IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL0__UART4_TXD_MUX = IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL0__FEC_RDATA_3 = IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW0__GPIO4_7 = IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW0__UART4_RXD_MUX = IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL),
+ MX53_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW0__FEC_TX_ER = IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL1__GPIO4_8 = IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL1__UART5_TXD_MUX = IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL1__FEC_RX_CLK = IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL1__USBPHY1_TXREADY = IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW1__GPIO4_9 = IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW1__UART5_RXD_MUX = IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL),
+ MX53_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW1__FEC_COL = IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW1__USBPHY1_RXVALID = IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL2__GPIO4_10 = IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL2__FEC_MDIO = IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL2__FEC_RDATA_2 = IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE = IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW2__GPIO4_11 = IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW2__FEC_MDC = IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW2__FEC_TDATA_2 = IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW2__USBPHY1_RXERROR = IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL3__GPIO4_12 = IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL3__USBOH3_H2_DP = IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL3__FEC_CRS = IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK = IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW3__GPIO4_13 = IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW3__USBOH3_H2_DM = IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK = IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW3__CCM_PLL4_BYP = IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 = IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL4__GPIO4_14 = IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL4__IPU_SISG_4 = IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 = IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW4__GPIO4_15 = IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW4__IPU_SISG_5 = IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID = IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK = IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_DISP_CLK__GPIO4_16 = IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR = IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 = IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 = IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID = IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 = IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN15__GPIO4_17 = IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 = IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 = IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN15__USBPHY1_BVALID = IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 = IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN2__GPIO4_18 = IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 = IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION = IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 = IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN3__GPIO4_19 = IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 = IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 = IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN3__USBPHY1_IDDIG = IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 = IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN4__GPIO4_20 = IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN4__ESDHC1_WP = IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 = IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT = IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 = IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT0__GPIO4_21 = IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT0__CSPI_SCLK = IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 = IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 = IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY = IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 = IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT1__GPIO4_22 = IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT1__CSPI_MOSI = IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 = IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL
+ = IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 = IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID = IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 = IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT2__GPIO4_23 = IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT2__CSPI_MISO = IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 = IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 = IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE = IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 = IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT3__GPIO4_24 = IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT3__CSPI_SS0 = IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 = IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 = IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR = IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 = IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT4__GPIO4_25 = IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT4__CSPI_SS1 = IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 = IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 = IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK = IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 = IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT5__GPIO4_26 = IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT5__CSPI_SS2 = IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 = IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 = IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 = IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 = IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT6__GPIO4_27 = IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT6__CSPI_SS3 = IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 = IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 = IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 = IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 = IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT7__GPIO4_28 = IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT7__CSPI_RDY = IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 = IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 = IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID = IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 = IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT8__GPIO4_29 = IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 = IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT8__USBPHY2_AVALID = IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 = IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT9__GPIO4_30 = IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 = IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 = IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 = IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT10__GPIO4_31 = IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP = IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3
+ = IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 = IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 = IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 = IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT11__GPIO5_5 = IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT = IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4
+ = IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 = IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 = IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 = IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT12__GPIO5_6 = IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK = IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5
+ = IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 = IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 = IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 = IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT13__GPIO5_7 = IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0
+ = IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 = IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 = IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 = IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT14__GPIO5_8 = IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1
+ = IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 = IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 = IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 = IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT15__GPIO5_9 = IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2
+ = IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 = IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 = IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 = IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT16__GPIO5_10 = IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3
+ = IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 = IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 = IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 = IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT17__GPIO5_11 = IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4
+ = IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 = IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 = IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT18__GPIO5_12 = IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5
+ = IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 = IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 = IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 = IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT19__GPIO5_13 = IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6
+ = IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 = IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 = IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 = IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT20__GPIO5_14 = IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7
+ = IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 = IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT20__SATA_PHY_TDI = IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 = IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT21__GPIO5_15 = IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 = IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT21__SATA_PHY_TDO = IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 = IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT22__GPIO5_16 = IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 = IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT22__SATA_PHY_TCK = IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 = IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT23__GPIO5_17 = IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 = IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT23__SATA_PHY_TMS = IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK = IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_PIXCLK__GPIO5_18 = IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 = IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC = IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_MCLK__GPIO5_19 = IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK = IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 = IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_MCLK__TPIU_TRCTL = IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN = IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DATA_EN__GPIO5_20 = IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 = IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK = IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC = IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_VSYNC__GPIO5_21 = IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 = IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 = IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 = IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT4__GPIO5_22 = IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP = IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 = IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 = IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 = IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT5__GPIO5_23 = IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT = IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 = IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 = IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 = IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT6__GPIO5_24 = IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK = IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 = IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 = IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 = IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT7__GPIO5_25 = IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR = IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 = IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 = IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 = IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT8__GPIO5_26 = IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC = IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 = IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 = IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 = IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT9__GPIO5_27 = IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR = IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 = IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 = IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 = IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT10__GPIO5_28 = IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT10__UART1_TXD_MUX = IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 = IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 = IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 = IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT11__GPIO5_29 = IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT11__UART1_RXD_MUX = IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 = IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 = IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 = IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT12__GPIO5_30 = IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT12__UART4_TXD_MUX = IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 = IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 = IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 = IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 = IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT13__GPIO5_31 = IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT13__UART4_RXD_MUX = IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 = IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 = IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 = IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 = IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT14__GPIO6_0 = IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT14__UART5_TXD_MUX = IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 = IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 = IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 = IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 = IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT15__GPIO6_1 = IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT15__UART5_RXD_MUX = IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 = IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 = IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 = IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 = IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT16__GPIO6_2 = IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 = IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 = IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 = IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 = IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT17__GPIO6_3 = IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 = IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 = IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 = IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 = IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT18__GPIO6_4 = IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 = IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 = IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 = IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 = IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT19__GPIO6_5 = IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 = IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 = IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK = IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A25__EMI_WEIM_A_25 = IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A25__GPIO5_2 = IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A25__IPU_DI1_PIN12 = IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A25__CSPI_SS1 = IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_A25__IPU_DI0_D1_CS = IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A25__USBPHY1_BISTOK = IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 = IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB2__GPIO2_30 = IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS = IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D16__EMI_WEIM_D_16 = IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D16__GPIO3_16 = IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D16__IPU_DI0_PIN5 = IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK = IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL),
+ MX53_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D17__EMI_WEIM_D_17 = IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D17__GPIO3_17 = IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D17__IPU_DI0_PIN6 = IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN = IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL),
+ MX53_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D18__EMI_WEIM_D_18 = IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D18__GPIO3_18 = IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D18__IPU_DI0_PIN7 = IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO = IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL),
+ MX53_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D18__IPU_DI1_D0_CS = IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D19__EMI_WEIM_D_19 = IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D19__GPIO3_19 = IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D19__IPU_DI0_PIN8 = IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS = IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL),
+ MX53_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D19__USBOH3_USBH2_OC = IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D20__EMI_WEIM_D_20 = IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D20__GPIO3_20 = IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D20__IPU_DI0_PIN16 = IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D20__IPU_SER_DISP0_CS = IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D20__CSPI_SS0 = IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D20__USBOH3_USBH2_PWR = IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D21__EMI_WEIM_D_21 = IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D21__GPIO3_21 = IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D21__IPU_DI0_PIN17 = IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK = IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D21__CSPI_SCLK = IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D22__EMI_WEIM_D_22 = IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D22__GPIO3_22 = IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D22__IPU_DI0_PIN1 = IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN = IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D22__CSPI_MISO = IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D23__EMI_WEIM_D_23 = IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D23__GPIO3_23 = IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D23__IPU_DI0_D0_CS = IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D23__IPU_DI1_PIN2 = IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN = IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D23__IPU_DI1_PIN14 = IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 = IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB3__GPIO2_31 = IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB3__IPU_DI1_PIN3 = IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC = IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB3__IPU_DI1_PIN16 = IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D24__EMI_WEIM_D_24 = IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D24__GPIO3_24 = IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D24__UART3_TXD_MUX = IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D24__CSPI_SS2 = IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D25__EMI_WEIM_D_25 = IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D25__GPIO3_25 = IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D25__UART3_RXD_MUX = IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D25__CSPI_SS3 = IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D26__EMI_WEIM_D_26 = IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D26__GPIO3_26 = IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D26__UART2_TXD_MUX = IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D26__FIRI_RXD = IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D26__IPU_CSI0_D_1 = IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D26__IPU_DI1_PIN11 = IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D26__IPU_SISG_2 = IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 = IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D27__EMI_WEIM_D_27 = IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D27__GPIO3_27 = IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D27__UART2_RXD_MUX = IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D27__FIRI_TXD = IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D27__IPU_CSI0_D_0 = IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D27__IPU_DI1_PIN13 = IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D27__IPU_SISG_3 = IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 = IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D28__EMI_WEIM_D_28 = IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D28__GPIO3_28 = IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO = IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D28__CSPI_MOSI = IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D28__IPU_EXT_TRIG = IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D28__IPU_DI0_PIN13 = IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D29__EMI_WEIM_D_29 = IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D29__GPIO3_29 = IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS = IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D29__CSPI_SS0 = IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL),
+ MX53_PAD_EIM_D29__IPU_DI1_PIN15 = IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D29__IPU_CSI1_VSYNC = IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D29__IPU_DI0_PIN14 = IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D30__EMI_WEIM_D_30 = IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D30__GPIO3_30 = IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D30__IPU_CSI0_D_3 = IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D30__IPU_DI0_PIN11 = IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 = IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D30__USBOH3_USBH2_OC = IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D31__EMI_WEIM_D_31 = IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D31__GPIO3_31 = IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D31__IPU_CSI0_D_2 = IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D31__IPU_DI0_PIN12 = IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 = IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D31__USBOH3_USBH2_PWR = IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A24__EMI_WEIM_A_24 = IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A24__GPIO5_4 = IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 = IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A24__IPU_CSI1_D_19 = IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A24__IPU_SISG_2 = IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A24__USBPHY2_BVALID = IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A23__EMI_WEIM_A_23 = IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A23__GPIO6_6 = IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 = IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A23__IPU_CSI1_D_18 = IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A23__IPU_SISG_3 = IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A23__USBPHY2_ENDSESSION = IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A22__EMI_WEIM_A_22 = IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A22__GPIO2_16 = IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 = IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A22__IPU_CSI1_D_17 = IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A22__SRC_BT_CFG1_7 = IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A21__EMI_WEIM_A_21 = IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A21__GPIO2_17 = IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 = IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A21__IPU_CSI1_D_16 = IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A21__SRC_BT_CFG1_6 = IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A20__EMI_WEIM_A_20 = IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A20__GPIO2_18 = IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 = IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A20__IPU_CSI1_D_15 = IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A20__SRC_BT_CFG1_5 = IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A19__EMI_WEIM_A_19 = IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A19__GPIO2_19 = IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 = IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A19__IPU_CSI1_D_14 = IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A19__SRC_BT_CFG1_4 = IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A18__EMI_WEIM_A_18 = IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A18__GPIO2_20 = IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 = IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A18__IPU_CSI1_D_13 = IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A18__SRC_BT_CFG1_3 = IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A17__EMI_WEIM_A_17 = IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A17__GPIO2_21 = IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 = IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A17__IPU_CSI1_D_12 = IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A17__SRC_BT_CFG1_2 = IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A16__EMI_WEIM_A_16 = IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A16__GPIO2_22 = IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK = IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK = IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A16__SRC_BT_CFG1_1 = IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 = IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_CS0__GPIO2_23 = IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL),
+ MX53_PAD_EIM_CS0__IPU_DI1_PIN5 = IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 = IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_CS1__GPIO2_24 = IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL),
+ MX53_PAD_EIM_CS1__IPU_DI1_PIN6 = IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_OE__EMI_WEIM_OE = IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_OE__GPIO2_25 = IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL),
+ MX53_PAD_EIM_OE__IPU_DI1_PIN7 = IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_OE__USBPHY2_IDDIG = IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_RW__EMI_WEIM_RW = IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_RW__GPIO2_26 = IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL),
+ MX53_PAD_EIM_RW__IPU_DI1_PIN8 = IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT = IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_LBA__EMI_WEIM_LBA = IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_LBA__GPIO2_27 = IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_LBA__IPU_DI1_PIN17 = IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 = IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 = IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB0__GPIO2_28 = IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 = IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB0__IPU_CSI1_D_11 = IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB0__GPC_PMIC_RDY = IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 = IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 = IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB1__GPIO2_29 = IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 = IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB1__IPU_CSI1_D_10 = IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 = IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 = IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA0__GPIO3_0 = IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 = IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA0__IPU_CSI1_D_9 = IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 = IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 = IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA1__GPIO3_1 = IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 = IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA1__IPU_CSI1_D_8 = IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 = IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 = IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA2__GPIO3_2 = IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 = IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA2__IPU_CSI1_D_7 = IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 = IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 = IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA3__GPIO3_3 = IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 = IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA3__IPU_CSI1_D_6 = IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 = IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 = IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA4__GPIO3_4 = IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 = IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA4__IPU_CSI1_D_5 = IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 = IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 = IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA5__GPIO3_5 = IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 = IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA5__IPU_CSI1_D_4 = IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 = IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 = IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA6__GPIO3_6 = IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 = IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA6__IPU_CSI1_D_3 = IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 = IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 = IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA7__GPIO3_7 = IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 = IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA7__IPU_CSI1_D_2 = IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 = IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 = IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA8__GPIO3_8 = IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 = IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA8__IPU_CSI1_D_1 = IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 = IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 = IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA9__GPIO3_9 = IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 = IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA9__IPU_CSI1_D_0 = IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 = IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 = IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA10__GPIO3_10 = IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA10__IPU_DI1_PIN15 = IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN = IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 = IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 = IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA11__GPIO3_11 = IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA11__IPU_DI1_PIN2 = IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC = IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 = IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA12__GPIO3_12 = IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA12__IPU_DI1_PIN3 = IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC = IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 = IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA13__GPIO3_13 = IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA13__IPU_DI1_D0_CS = IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 = IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA14__GPIO3_14 = IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA14__IPU_DI1_D1_CS = IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 = IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA15__GPIO3_15 = IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA15__IPU_DI1_PIN1 = IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA15__IPU_DI1_PIN4 = IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B = IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_WE_B__GPIO6_12 = IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B = IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_RE_B__GPIO6_13 = IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT = IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_WAIT__GPIO5_0 = IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B = IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_TX3_P__GPIO6_22 = IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_TX2_P__GPIO6_24 = IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_CLK_P__GPIO6_26 = IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_TX1_P__GPIO6_28 = IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_TX0_P__GPIO6_30 = IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_TX3_P__GPIO7_22 = IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_CLK_P__GPIO7_24 = IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_TX2_P__GPIO7_26 = IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_TX1_P__GPIO7_28 = IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_TX0_P__GPIO7_30 = IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_10__GPIO4_0 = IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_10__OSC32k_32K_OUT = IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_11__GPIO4_1 = IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_12__GPIO4_2 = IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_13__GPIO4_3 = IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_14__GPIO4_4 = IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CLE__EMI_NANDF_CLE = IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CLE__GPIO6_7 = IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 = IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_ALE__EMI_NANDF_ALE = IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_ALE__GPIO6_8 = IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 = IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B = IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_WP_B__GPIO6_9 = IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 = IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 = IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_RB0__GPIO6_10 = IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 = IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 = IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS0__GPIO6_11 = IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 = IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 = IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS1__GPIO6_14 = IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS1__MLB_MLBCLK = IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 = IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 = IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS2__GPIO6_15 = IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS2__IPU_SISG_0 = IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS2__EMI_WEIM_CRE = IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK = IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS2__MLB_MLBSIG = IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 = IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 = IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS3__GPIO6_16 = IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS3__IPU_SISG_1 = IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 = IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS3__MLB_MLBDAT = IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 = IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDIO__GPIO1_22 = IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDIO__ESAI1_SCKR = IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDIO__FEC_COL = IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 = IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 = IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK = IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_REF_CLK__GPIO1_23 = IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 = IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 = IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER = IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RX_ER__GPIO1_24 = IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RX_ER__FEC_RX_CLK = IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL),
+ MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 = IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV = IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_CRS_DV__GPIO1_25 = IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 = IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD1__GPIO1_26 = IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD1__ESAI1_FST = IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD1__MLB_MLBSIG = IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 = IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 = IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD0__GPIO1_27 = IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD0__ESAI1_HCKT = IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD0__OSC32k_32K_OUT = IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TX_EN__GPIO1_28 = IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 = IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD1__GPIO1_29 = IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD1__MLB_MLBCLK = IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK = IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 = IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD0__GPIO1_30 = IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 = IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDC__GPIO1_31 = IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDC__MLB_MLBDAT = IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG = IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 = IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DIOW__PATA_DIOW = IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DIOW__GPIO6_17 = IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DIOW__UART1_TXD_MUX = IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 = IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DMACK__PATA_DMACK = IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DMACK__GPIO6_18 = IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DMACK__UART1_RXD_MUX = IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 = IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DMARQ__PATA_DMARQ = IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DMARQ__GPIO7_0 = IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DMARQ__UART2_TXD_MUX = IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 = IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 = IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN = IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_BUFFER_EN__GPIO7_1 = IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX = IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 = IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 = IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_INTRQ__PATA_INTRQ = IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_INTRQ__GPIO7_2 = IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_INTRQ__UART2_CTS = IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_INTRQ__CAN1_TXCAN = IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 = IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 = IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DIOR__PATA_DIOR = IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DIOR__GPIO7_3 = IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DIOR__UART2_RTS = IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_DIOR__CAN1_RXCAN = IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL),
+ MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 = IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B = IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_RESET_B__GPIO7_4 = IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_RESET_B__ESDHC3_CMD = IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_RESET_B__UART1_CTS = IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_RESET_B__CAN2_TXCAN = IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 = IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_IORDY__PATA_IORDY = IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_IORDY__GPIO7_5 = IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_IORDY__ESDHC3_CLK = IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_IORDY__UART1_RTS = IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_IORDY__CAN2_RXCAN = IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL),
+ MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 = IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_0__PATA_DA_0 = IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_0__GPIO7_6 = IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_0__ESDHC3_RST = IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_0__OWIRE_LINE = IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 = IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_1__PATA_DA_1 = IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_1__GPIO7_7 = IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_1__ESDHC4_CMD = IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DA_1__UART3_CTS = IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 = IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_2__PATA_DA_2 = IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_2__GPIO7_8 = IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_2__ESDHC4_CLK = IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DA_2__UART3_RTS = IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 = IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_CS_0__PATA_CS_0 = IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_CS_0__GPIO7_9 = IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_CS_0__UART3_TXD_MUX = IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 = IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_CS_1__PATA_CS_1 = IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_CS_1__GPIO7_10 = IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_CS_1__UART3_RXD_MUX = IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 = IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA0__PATA_DATA_0 = IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA0__GPIO2_0 = IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 = IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA0__ESDHC3_DAT4 = IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 = IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 = IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 = IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA1__PATA_DATA_1 = IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA1__GPIO2_1 = IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 = IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA1__ESDHC3_DAT5 = IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 = IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 = IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA2__PATA_DATA_2 = IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA2__GPIO2_2 = IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 = IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA2__ESDHC3_DAT6 = IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 = IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 = IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA3__PATA_DATA_3 = IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA3__GPIO2_3 = IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 = IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA3__ESDHC3_DAT7 = IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 = IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 = IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA4__PATA_DATA_4 = IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA4__GPIO2_4 = IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 = IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA4__ESDHC4_DAT4 = IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 = IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 = IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA5__PATA_DATA_5 = IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA5__GPIO2_5 = IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 = IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA5__ESDHC4_DAT5 = IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 = IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 = IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA6__PATA_DATA_6 = IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA6__GPIO2_6 = IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 = IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA6__ESDHC4_DAT6 = IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 = IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 = IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA7__PATA_DATA_7 = IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA7__GPIO2_7 = IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 = IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA7__ESDHC4_DAT7 = IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 = IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 = IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA8__PATA_DATA_8 = IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA8__GPIO2_8 = IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA8__ESDHC1_DAT4 = IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 = IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA8__ESDHC3_DAT0 = IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 = IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 = IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA9__PATA_DATA_9 = IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA9__GPIO2_9 = IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA9__ESDHC1_DAT5 = IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 = IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA9__ESDHC3_DAT1 = IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 = IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 = IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA10__PATA_DATA_10 = IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA10__GPIO2_10 = IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA10__ESDHC1_DAT6 = IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 = IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA10__ESDHC3_DAT2 = IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 = IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 = IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA11__PATA_DATA_11 = IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA11__GPIO2_11 = IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA11__ESDHC1_DAT7 = IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 = IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA11__ESDHC3_DAT3 = IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 = IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 = IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA12__PATA_DATA_12 = IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA12__GPIO2_12 = IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA12__ESDHC2_DAT4 = IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 = IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA12__ESDHC4_DAT0 = IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 = IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 = IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA13__PATA_DATA_13 = IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA13__GPIO2_13 = IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA13__ESDHC2_DAT5 = IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 = IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA13__ESDHC4_DAT1 = IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 = IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 = IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA14__PATA_DATA_14 = IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA14__GPIO2_14 = IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA14__ESDHC2_DAT6 = IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 = IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA14__ESDHC4_DAT2 = IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 = IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 = IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA15__PATA_DATA_15 = IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA15__GPIO2_15 = IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA15__ESDHC2_DAT7 = IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 = IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA15__ESDHC4_DAT3 = IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 = IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 = IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 = IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD1_DATA0__GPIO1_16 = IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA0__GPT_CAPIN1 = IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA0__CSPI_MISO = IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA0__CCM_PLL3_BYP = IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 = IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD1_DATA1__GPIO1_17 = IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA1__GPT_CAPIN2 = IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA1__CSPI_SS0 = IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA1__CCM_PLL4_BYP = IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL),
+ MX53_PAD_SD1_CMD__ESDHC1_CMD = IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD1_CMD__GPIO1_18 = IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_CMD__CSPI_MOSI = IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL),
+ MX53_PAD_SD1_CMD__CCM_PLL1_BYP = IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 = IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD1_DATA2__GPIO1_19 = IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA2__GPT_CMPOUT2 = IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA2__PWM2_PWMO = IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA2__WDOG1_WDOG_B = IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA2__CSPI_SS1 = IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA2__CCM_PLL2_BYP = IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_CLK__ESDHC1_CLK = IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD1_CLK__GPIO1_20 = IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_CLK__OSC32k_32K_OUT = IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_CLK__CSPI_SCLK = IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL),
+ MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 = IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 = IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD1_DATA3__GPIO1_21 = IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA3__GPT_CMPOUT3 = IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA3__PWM1_PWMO = IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA3__WDOG2_WDOG_B = IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA3__CSPI_SS2 = IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 = IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_CLK__ESDHC2_CLK = IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD2_CLK__GPIO1_10 = IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL),
+ MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_CLK__CSPI_SCLK = IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL),
+ MX53_PAD_SD2_CLK__SCC_RANDOM_V = IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_CMD__ESDHC2_CMD = IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD2_CMD__GPIO1_11 = IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_CMD__CSPI_MOSI = IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL),
+ MX53_PAD_SD2_CMD__SCC_RANDOM = IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA3__ESDHC2_DAT3 = IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD2_DATA3__GPIO1_12 = IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA3__KPP_COL_6 = IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA3__CSPI_SS2 = IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA3__SJC_DONE = IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA2__ESDHC2_DAT2 = IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD2_DATA2__GPIO1_13 = IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA2__KPP_ROW_6 = IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA2__CSPI_SS1 = IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA2__SJC_FAIL = IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA1__ESDHC2_DAT1 = IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD2_DATA1__GPIO1_14 = IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA1__KPP_COL_7 = IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA1__CSPI_SS0 = IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA1__RTIC_SEC_VIO = IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA0__ESDHC2_DAT0 = IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD2_DATA0__GPIO1_15 = IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA0__KPP_ROW_7 = IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA0__CSPI_MISO = IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA0__RTIC_DONE_INT = IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_0__GPIO1_0 = IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL),
+ MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK = IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_0__SRTC_ALARM_DEB = IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_0__CSU_TD = IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_1__GPIO1_1 = IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK = IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_1__ESDHC1_CD = IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_9__GPIO1_9 = IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_9__ESDHC1_WP = IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_9__SCC_FAIL_STATE = IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_3__GPIO1_3 = IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_3__DPLLIP1_TOG_EN = IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 = IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_6__GPIO1_6 = IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 = IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_6__ESDHC2_LCTL = IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_2__GPIO1_2 = IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 = IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_2__ESDHC2_WP = IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_4__GPIO1_4 = IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 = IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_4__ESDHC2_CD = IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_4__SCC_SEC_STATE = IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_5__GPIO1_5 = IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 = IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_5__CCM_PLL1_BYP = IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_7__GPIO1_7 = IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_7__UART2_TXD_MUX = IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_GPIO_7__FIRI_RXD = IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_7__CCM_PLL2_BYP = IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_8__GPIO1_8 = IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL),
+ MX53_PAD_GPIO_8__UART2_RXD_MUX = IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL),
+ MX53_PAD_GPIO_8__FIRI_TXD = IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_8__CCM_PLL3_BYP = IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_16__GPIO7_11 = IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT = IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 = IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_17__GPIO7_12 = IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_17__GPC_PMIC_RDY = IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG = IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_17__IPU_SNOOP2 = IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_18__GPIO7_13 = IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_18__OWIRE_LINE = IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG = IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK = IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_18__ESDHC1_LCTL = IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX53_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __MACH_MX5_IOMUX_H__
-#define __MACH_MX5_IOMUX_H__
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-
-typedef unsigned int iomux_pin_name_t;
-
-/* various IOMUX output functions */
-typedef enum iomux_config {
- IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */
- IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */
- IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */
- IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */
- IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */
- IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */
- IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */
- IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */
- IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */
- IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
-} iomux_pin_cfg_t;
-
-/* various IOMUX pad functions */
-typedef enum iomux_pad_config {
- PAD_CTL_SRE_SLOW = 0x0 << 0, /* Slow slew rate */
- PAD_CTL_SRE_FAST = 0x1 << 0, /* Fast slew rate */
- PAD_CTL_DRV_LOW = 0x0 << 1, /* Low drive strength */
- PAD_CTL_DRV_MEDIUM = 0x1 << 1, /* Medium drive strength */
- PAD_CTL_DRV_HIGH = 0x2 << 1, /* High drive strength */
- PAD_CTL_DRV_MAX = 0x3 << 1, /* Max drive strength */
- PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, /* Opendrain disable */
- PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,/* Opendrain enable */
- PAD_CTL_100K_PD = 0x0 << 4, /* 100Kohm pulldown */
- PAD_CTL_47K_PU = 0x1 << 4, /* 47Kohm pullup */
- PAD_CTL_100K_PU = 0x2 << 4, /* 100Kohm pullup */
- PAD_CTL_22K_PU = 0x3 << 4, /* 22Kohm pullup */
- PAD_CTL_PUE_KEEPER = 0x0 << 6, /* enable pulldown */
- PAD_CTL_PUE_PULL = 0x1 << 6, /* enable pullup */
- PAD_CTL_PKE_NONE = 0x0 << 7, /* Disable pullup/pulldown */
- PAD_CTL_PKE_ENABLE = 0x1 << 7, /* Enable pullup/pulldown */
- PAD_CTL_HYS_NONE = 0x0 << 8, /* Hysteresis disabled */
- PAD_CTL_HYS_ENABLE = 0x1 << 8, /* Hysteresis enabled */
- PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */
- PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */
- PAD_CTL_DRV_VOT_LOW = 0x1 << 13, /* Low voltage mode */
- PAD_CTL_DRV_VOT_HIGH = 0x0 << 13,/* High voltage mode */
-} iomux_pad_config_t;
-
-/* various IOMUX input functions */
-typedef enum iomux_input_config {
- INPUT_CTL_PATH0 = 0x0,
- INPUT_CTL_PATH1,
- INPUT_CTL_PATH2,
- INPUT_CTL_PATH3,
- INPUT_CTL_PATH4,
- INPUT_CTL_PATH5,
- INPUT_CTL_PATH6,
- INPUT_CTL_PATH7,
-} iomux_input_config_t;
-
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-
-#endif /* __MACH_MX5_IOMUX_H__ */
+++ /dev/null
-/*
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__
-#define __ASM_ARCH_MX5_MX5X_PINS_H__
-
-#ifndef __ASSEMBLY__
-
-/*
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P | IO_I | GPIO_I | PAD_I | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 9 contains MUX_I used to identify the register
- * offset (0-based. base is IOMUX_module_base) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
- * similar field definitions are used for the pad control register.
- * The IOMUX controller can be split in two parts. At the begeinning,
- * there is the register definitions for the multiplexing each pin.
- * Then there is a set of registers (PAD_I) to configure each pin
- * (pullup, pulldown, etc).
- * PAD_I defines the offset of the pad register for each pin.
- * GPIO_I defines, if available, the number of gpio that can be
- * connected to that pad
- * IO_I defines the multiplexer mode required to set the pad in gpio mode
- * IO_P defines the gpio structure (gpio1..gpio4) the pad belongs
- *
- * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
- * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
- * It means the mux control register is at register offset 0x28. The pad control
- * register offset is: 0x250 and also occupy the least significant bits
- * within the register.
- */
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I 0
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I 10
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent which
- * mux mode is for GPIO (0-based)
- */
-#define GPIO_I 21
-
-#define MUX_IO_P 29
-#define MUX_IO_I 24
-#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
- GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
- ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
-#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-
-#define NON_GPIO_PORT 0x7
-#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
-#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
-
-#define NON_MUX_I PIN_TO_MUX_MASK
-#define NON_PAD_I PIN_TO_PAD_MASK
-
-#if defined(CONFIG_MX51)
-#define MUX_I_START 0x001C
-#define PAD_I_START 0x3F0
-#define INPUT_CTL_START 0x8C4
-#define MUX_I_END (PAD_I_START - 4)
-#elif defined(CONFIG_MX53)
-#define MUX_I_START 0x0020
-#define PAD_I_START 0x348
-#define INPUT_CTL_START 0x730
-#define MUX_I_END (PAD_I_START - 4)
-#else
-#error "CPU_TYPE not defined"
-#endif
-
-#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
- (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
- ((mi) << MUX_I) | \
- ((pi - PAD_I_START) << PAD_I) | \
- ((ga) << GPIO_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
- _MXC_BUILD_PIN(gp, gi, ga, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
- _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
-#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
-#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
-
-/*
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-enum {
- MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
- MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
- MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
- MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
- MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
- MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
- MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
- MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
- MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
- MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
- MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
- MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
- MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
- MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
- MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
- MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
- MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
- MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
- MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
- MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
- MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
- MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
- MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
- MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
- MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
- MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
- MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
- MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
- MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
- MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
- MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
- MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
- MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
- MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
- MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
- MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
- MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
- MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
- MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
- MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
- MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
- MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
- MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
- MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
- MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
- MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
- MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
- MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
- MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
- MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
- MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
- MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
- MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
- MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
- MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
- MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
- MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
- MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
- MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
- MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
- MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
- MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
- MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
- MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
- MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
- MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
- MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
- MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
- MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514),
- MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
- MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
- MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
- MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
- MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
- MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
- MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
- MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
- MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
- MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
- MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
- MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
- MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
- MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
- MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
- MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
- MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
- MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
- MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
- MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
- MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
- MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
- MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
- MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
- MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
- MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
- MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
- MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
- MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
- MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
- MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
- MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
- MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
- MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
- MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
- MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
- MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
- MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
- MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
- MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
- MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
- MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC),
- MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0),
- MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
- MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
- MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
- MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
- MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
- MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4),
- MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8),
- MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC),
- MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0),
- MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
- MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
- MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
- MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
- MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
- MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
- MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
- MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
- MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
- MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
- MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
- MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
- MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
- MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
- MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
- MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
- MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
- MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
- MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
- MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
- MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
- MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
- MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
- MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
- MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
- MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
- MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
- MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
- MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
- MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
- MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
- MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
- MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
- MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
- MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
- MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
- MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
- MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
- MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
- MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
- MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
- MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
- MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
- MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
- MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
- MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
- MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
- MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
- MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
- MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
- MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
- MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
- MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
- MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
- MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
- MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
- MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
- MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
- MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
- MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
- MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
- MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
- MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
- MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
- MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
- MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
- MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
- MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
- MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
- MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
- MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
- MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
- MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
- MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
- MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
- MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
- MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
- MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
- MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
- MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
- MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
- MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
- MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
- MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
- MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
- MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
- MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
- MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
- MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
- MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
- MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
- MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
- MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
- MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
- MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
- MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
- MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
- MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
- MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
- MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
- MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
- MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
- MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
- MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788),
- MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
- MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
- MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
- MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
- MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
- MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
- MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
- MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
- MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
- MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
- MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
- MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
- MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
- MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
- MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
- MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
- MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
- MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
- MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
- MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
- MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
- MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
- MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
- MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
- MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
- MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
- MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
-
- /* The following are PADS used for drive strength */
-
- MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820),
- MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838),
- MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890),
- MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C),
- MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C),
- MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884),
- MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C),
- MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864),
- MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C),
- MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874),
- MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878),
- MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880),
- MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C),
- MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C),
- MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4),
- MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC),
- MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8),
- MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C),
- MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0),
- MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0),
- MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4),
- MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC),
- MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C),
- MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848),
- MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868),
- MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4),
- MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8),
- MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac),
- MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0),
- MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4),
- MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8),
- MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC),
- MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0),
- MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4),
- MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8),
- MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC),
- MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0),
- MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4),
- MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8),
- MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC),
- MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
-};
-
-enum {
- MX53_PIN_GPIO_19 = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348),
- MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C),
- MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350),
- MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354),
- MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358),
- MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C),
- MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360),
- MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364),
- MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368),
- MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C),
- MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370),
- MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374),
- MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378),
- MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C),
- MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380),
- MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384),
- MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388),
- MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C),
- MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390),
- MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394),
- MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398),
- MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C),
- MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0),
- MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4),
- MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8),
- MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC),
- MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0),
- MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4),
- MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8),
- MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC),
- MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0),
- MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4),
- MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8),
- MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC),
- MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0),
- MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4),
- MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8),
- MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC),
- MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0),
- MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4),
- MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8),
- MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC),
- MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0),
- MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4),
- MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8),
- MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC),
- MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400),
- MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404),
- MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408),
- MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C),
- MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410),
- MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414),
- MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418),
- MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C),
- MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420),
- MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424),
- MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428),
- MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C),
- MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430),
- MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434),
- MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438),
- MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C),
- MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440),
- MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444),
- MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448),
- MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C),
- MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450),
- MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454),
- MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458),
- MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C),
- MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460),
- MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464),
- MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468),
- MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C),
- MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470),
- MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474),
- MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478),
- MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C),
- MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480),
- MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484),
- MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488),
- MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C),
- MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490),
- MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494),
- MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498),
- MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C),
- MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0),
- MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4),
- MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8),
- MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC),
- MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0),
- MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4),
- MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8),
- MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC),
- MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0),
- MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4),
- MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8),
- MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC),
- MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0),
- MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4),
- MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8),
- MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC),
- MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0),
- MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4),
- MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8),
- MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC),
- MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0),
- MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4),
- MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8),
- MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC),
- MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500),
- MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504),
- MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508),
- MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C),
- MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510),
- MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514),
- MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518),
- MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C),
- MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520),
- MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524),
- MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528),
- MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C),
- MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530),
- MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534),
- MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538),
- MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C),
- MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I),
- MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I),
- MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I),
- MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I),
- MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I),
- MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I),
- MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I),
- MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I),
- MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I),
- MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I),
- MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540),
- MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544),
- MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548),
- MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C),
- MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550),
- MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554),
- MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558),
- MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C),
- MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560),
- MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564),
- MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568),
- MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C),
- MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570),
- MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574),
- MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578),
- MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C),
- MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580),
- MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584),
- MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588),
- MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C),
- MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590),
- MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594),
- MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598),
- MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C),
- MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0),
- MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4),
- MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8),
- MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC),
- MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0),
- MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4),
- MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8),
- MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC),
- MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0),
- MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4),
- MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8),
- MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC),
- MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0),
- MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4),
- MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8),
- MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC),
- MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0),
- MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4),
- MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8),
- MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC),
- MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0),
- MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4),
- MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8),
- MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC),
- MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600),
- MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604),
- MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608),
- MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C),
- MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610),
- MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614),
- MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618),
- MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C),
- MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620),
- MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624),
- MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628),
- MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C),
- MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630),
- MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634),
- MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638),
- MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C),
- MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640),
- MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644),
- MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648),
- MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C),
- MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650),
- MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654),
- MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658),
- MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C),
- MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660),
- MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664),
- MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668),
- MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C),
- MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670),
- MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674),
- MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678),
- MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C),
- MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680),
- MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684),
- MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688),
- MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C),
- MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690),
- MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694),
- MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698),
- MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C),
- MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0),
- MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4),
- MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8),
- MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC),
- MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0),
- MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4),
- MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8),
- MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC),
- MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0),
- MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4),
- MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8),
- MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC),
- MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0),
- MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4),
- MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8),
- MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC),
- MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0),
- MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4),
- MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8),
- MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC),
- MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0),
- MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4),
- MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC),
- MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708),
- MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C),
- MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710),
- MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714),
- MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718),
- MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C),
- MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720),
- MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724),
- MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728),
- MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C),
-};
-/* various IOMUX input select register index */
-typedef enum iomux_input_select {
- MX51_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
- MX51_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
- MX51_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
- MX51_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
- MX51_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
- MX51_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
- MX51_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
- MX51_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
- MX51_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
- MX51_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
- MX51_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
- MX51_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
- MX51_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
- MX51_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
- MX51_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
- MX51_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
- MX51_CCM_IPP_DI_CLK_SELECT_INPUT,
- /* TO2 */
- MX51_CCM_IPP_DI1_CLK_SELECT_INPUT,
- MX51_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
- MX51_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
- MX51_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
- MX51_CSPI_IPP_IND_MISO_SELECT_INPUT,
- MX51_CSPI_IPP_IND_MOSI_SELECT_INPUT,
- MX51_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
- MX51_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
- MX51_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
- MX51_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
- /* TO2 */
- MX51_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
- MX51_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
- MX51_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
- MX51_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
- MX51_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
- MX51_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
- MX51_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
- MX51_FEC_FEC_COL_SELECT_INPUT,
- MX51_FEC_FEC_CRS_SELECT_INPUT,
- MX51_FEC_FEC_MDI_SELECT_INPUT,
- MX51_FEC_FEC_RDATA_0_SELECT_INPUT,
- MX51_FEC_FEC_RDATA_1_SELECT_INPUT,
- MX51_FEC_FEC_RDATA_2_SELECT_INPUT,
- MX51_FEC_FEC_RDATA_3_SELECT_INPUT,
- MX51_FEC_FEC_RX_CLK_SELECT_INPUT,
- MX51_FEC_FEC_RX_DV_SELECT_INPUT,
- MX51_FEC_FEC_RX_ER_SELECT_INPUT,
- MX51_FEC_FEC_TX_CLK_SELECT_INPUT,
- MX51_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
- MX51_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
- MX51_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
- MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
- MX51_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
- MX51_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
- MX51_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
- MX51_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
- /* TO2 */
- MX51_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
- MX51_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
- MX51_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
- /* TO2 */
- MX51_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
- /* TO2 */
- MX51_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
- MX51_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
- MX51_I2C1_IPP_SCL_IN_SELECT_INPUT,
- MX51_I2C1_IPP_SDA_IN_SELECT_INPUT,
- MX51_I2C2_IPP_SCL_IN_SELECT_INPUT,
- MX51_I2C2_IPP_SDA_IN_SELECT_INPUT,
- MX51_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
- MX51_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
- MX51_KPP_IPP_IND_COL_6_SELECT_INPUT,
- MX51_KPP_IPP_IND_COL_7_SELECT_INPUT,
- MX51_KPP_IPP_IND_ROW_4_SELECT_INPUT,
- MX51_KPP_IPP_IND_ROW_5_SELECT_INPUT,
- MX51_KPP_IPP_IND_ROW_6_SELECT_INPUT,
- MX51_KPP_IPP_IND_ROW_7_SELECT_INPUT,
- MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
- MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
- MX51_UART2_IPP_UART_RTS_B_SELECT_INPUT,
- MX51_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
- MX51_UART3_IPP_UART_RTS_B_SELECT_INPUT,
- MX51_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
- MX51PUT_NUM_MUX,
- /* MX53 */
- MX53_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
- MX53_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
- MX53_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
- MX53_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
- MX53_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
- MX53_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
- MX53_AUDMUX_P5_INPUT_DA_AMX_SELECT_I,
- MX53_AUDMUX_P5_INPUT_DB_AMX_SELECT_I,
- MX53_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
- MX53_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT,
- MX53_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
- MX53_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
- MX53_CAN1_IPP_IND_CANRX_SELECT_INPUT,
- MX53_CAN2_IPP_IND_CANRX_SELECT_INPUT,
- MX53_CCM_IPP_ASRC_EXT_SELECT_INPUT,
- MX53_CCM_IPP_DI1_CLK_SELECT_INPUT,
- MX53_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
- MX53_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
- MX53_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
- MX53_CCM_PLL4_BYPASS_CLK_SELECT_INPUT,
- MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
- MX53_CSPI_IPP_IND_MISO_SELECT_INPUT,
- MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT,
- MX53_CSPI_IPP_IND_SS_B_0_SELECT_INPUT,
- MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
- MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
- MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
- MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
- MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
- MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
- MX53_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT,
- MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
- MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
- MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT,
- MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
- MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
- MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
- MX53_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT,
- MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_FST_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_SCKT_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
- MX53_ESDHC1_IPP_WP_ON_SELECT_INPUT,
- MX53_FEC_FEC_COL_SELECT_INPUT,
- MX53_FEC_FEC_MDI_SELECT_INPUT,
- MX53_FEC_FEC_RX_CLK_SELECT_INPUT,
- MX53_FIRI_IPP_IND_RXD_SELECT_INPUT,
- MX53_GPC_PMIC_RDY_SELECT_INPUT,
- MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
- MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
- MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
- MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
- MX53_I2C3_IPP_SCL_IN_SELECT_INPUT,
- MX53_I2C3_IPP_SDA_IN_SELECT_INPUT,
- MX53_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
- MX53_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
- MX53_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
- MX53_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT,
- MX53_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT,
- MX53_KPP_IPP_IND_COL_5_SELECT_INPUT,
- MX53_KPP_IPP_IND_COL_6_SELECT_INPUT,
- MX53_KPP_IPP_IND_COL_7_SELECT_INPUT,
- MX53_KPP_IPP_IND_ROW_5_SELECT_INPUT,
- MX53_KPP_IPP_IND_ROW_6_SELECT_INPUT,
- MX53_KPP_IPP_IND_ROW_7_SELECT_INPUT,
- MX53_MLB_MLBCLK_IN_SELECT_INPUT,
- MX53_MLB_MLBDAT_IN_SELECT_INPUT,
- MX53_MLB_MLBSIG_IN_SELECT_INPUT,
- MX53_OWIRE_BATTERY_LINE_IN_SELECT_INPUT,
- MX53_SDMA_EVENTS_14_SELECT_INPUT,
- MX53_SDMA_EVENTS_15_SELECT_INPUT,
- MX53_SPDIF_SPDIF_IN1_SELECT_INPUT,
- MX53_UART1_IPP_UART_RTS_B_SELECT_INPUT,
- MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
- MX53_UART2_IPP_UART_RTS_B_SELECT_INPUT,
- MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
- MX53_UART3_IPP_UART_RTS_B_SELECT_INPUT,
- MX53_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
- MX53_UART4_IPP_UART_RTS_B_SELECT_INPUT,
- MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
- MX53_UART5_IPP_UART_RTS_B_SELECT_INPUT,
- MX53_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
- MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT,
- MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT,
- MX53_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT,
-} iomux_input_select_t;
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __ASM_ARCH_SPL_H__
+#define __ASM_ARCH_SPL_H__
+
+#define BOOT_DEVICE_NONE 0
+#define BOOT_DEVICE_NAND 1
+
+#endif /* __ASM_ARCH_SPL_H__ */
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
+void enable_ocotp_clk(unsigned char enable);
void enable_usboh3_clk(unsigned char enable);
int enable_sata_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+#define CCM_CCOSR 0x020c4060
#define CCM_CCGR0 0x020C4068
#define CCM_CCGR1 0x020C406c
#define CCM_CCGR2 0x020C4070
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
+#ifdef CONFIG_MX6SL
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F
+#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
+#else
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
+#endif
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
/* Define the bits in register CS1CDR */
/* Define the bits in register CS2CDR */
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16)
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
#define MXC_CCM_CCGR_CG_MASK 3
#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
-#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
+#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
-#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
-#define MXC_CCM_CCGR0_APBHDMA HCLK_OFFSET 4
-#define MXC_CCM_CCGR0_AMASK (3<<MXC_CCM_CCGR0_APBHDMA)
+#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
+#define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
+#define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
#define MXC_CCM_CCGR0_ASRC_OFFSET 6
-#define MXC_CCM_CCGR0_ASRC_MASK (3<<MXC_CCM_CCGR0_ASRC_OFFSET)
+#define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
-#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3<<MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
-#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
-#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
#define MXC_CCM_CCGR0_CAN1_OFFSET 14
-#define MXC_CCM_CCGR0_CAN1_MASK (3<<MXC_CCM_CCGR0_CAN1_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
-#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
#define MXC_CCM_CCGR0_CAN2_OFFSET 18
-#define MXC_CCM_CCGR0_CAN2_MASK (3<<MXC_CCM_CCGR0_CAN2_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
-#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
-#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3<<MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
#define MXC_CCM_CCGR0_DCIC1_OFFSET 24
-#define MXC_CCM_CCGR0_DCIC1_MASK (3<<MXC_CCM_CCGR0_DCIC1_OFFSET)
+#define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
#define MXC_CCM_CCGR0_DCIC2_OFFSET 26
-#define MXC_CCM_CCGR0_DCIC2_MASK (3<<MXC_CCM_CCGR0_DCIC2_OFFSET)
+#define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
#define MXC_CCM_CCGR0_DTCP_OFFSET 28
-#define MXC_CCM_CCGR0_DTCP_MASK (3<<MXC_CCM_CCGR0_DTCP_OFFSET)
+#define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
#define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
-#define MXC_CCM_CCGR1_ECSPI1S_MASK (3<<MXC_CCM_CCGR1_ECSPI1S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
#define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
-#define MXC_CCM_CCGR1_ECSPI2S_MASK (3<<MXC_CCM_CCGR1_ECSPI2S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
#define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
-#define MXC_CCM_CCGR1_ECSPI3S_MASK (3<<MXC_CCM_CCGR1_ECSPI3S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
#define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
-#define MXC_CCM_CCGR1_ECSPI4S_MASK (3<<MXC_CCM_CCGR1_ECSPI4S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
-#define MXC_CCM_CCGR1_ECSPI5S_MASK (3<<MXC_CCM_CCGR1_ECSPI5S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
-#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3<<MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
-#define MXC_CCM_CCGR1_EPIT1S_MASK (3<<MXC_CCM_CCGR1_EPIT1S_OFFSET)
+#define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
-#define MXC_CCM_CCGR1_EPIT2S_MASK (3<<MXC_CCM_CCGR1_EPIT2S_OFFSET)
+#define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
#define MXC_CCM_CCGR1_ESAIS_OFFSET 16
-#define MXC_CCM_CCGR1_ESAIS_MASK (3<<MXC_CCM_CCGR1_ESAIS_OFFSET)
+#define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
#define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
-#define MXC_CCM_CCGR1_GPT_BUS_MASK (3<<MXC_CCM_CCGR1_GPT_BUS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
-#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3<<MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
#define MXC_CCM_CCGR1_GPU2D_OFFSET 24
-#define MXC_CCM_CCGR1_GPU2D_MASK (3<<MXC_CCM_CCGR1_GPU2D_OFFSET)
+#define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
#define MXC_CCM_CCGR1_GPU3D_OFFSET 26
-#define MXC_CCM_CCGR1_GPU3D_MASK (3<<MXC_CCM_CCGR1_GPU3D_OFFSET)
+#define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
-#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
-#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
-#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
-#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
-#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
-#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3<<MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
+#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
-#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3<<MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
#define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
-#define MXC_CCM_CCGR2_IPMUX1_MASK (3<<MXC_CCM_CCGR2_IPMUX1_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
#define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
-#define MXC_CCM_CCGR2_IPMUX2_MASK (3<<MXC_CCM_CCGR2_IPMUX2_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
#define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
-#define MXC_CCM_CCGR2_IPMUX3_MASK (3<<MXC_CCM_CCGR2_IPMUX3_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
-#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
-#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
-#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3<<MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
-#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
-#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
-#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
-#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
-#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
-#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
-#define MXC_CCM_CCGR3_LDB_DI0_MASK (3<<MXC_CCM_CCGR3_LDB_DI0_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
-#define MXC_CCM_CCGR3_LDB_DI1_MASK (3<<MXC_CCM_CCGR3_LDB_DI1_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
-#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3<<MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
#define MXC_CCM_CCGR3_MLB_OFFSET 18
-#define MXC_CCM_CCGR3_MLB_MASK (3<<MXC_CCM_CCGR3_MLB_OFFSET)
+#define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
-#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
-#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
-#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
-#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
#define MXC_CCM_CCGR3_OCRAM_OFFSET 28
-#define MXC_CCM_CCGR3_OCRAM_MASK (3<<MXC_CCM_CCGR3_OCRAM_OFFSET)
+#define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
-#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3<<MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
+#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
#define MXC_CCM_CCGR4_PCIE_OFFSET 0
-#define MXC_CCM_CCGR4_PCIE_MASK (3<<MXC_CCM_CCGR4_PCIE_OFFSET)
+#define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
-#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
-#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
-#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
#define MXC_CCM_CCGR4_PWM1_OFFSET 16
-#define MXC_CCM_CCGR4_PWM1_MASK (3<<MXC_CCM_CCGR4_PWM1_OFFSET)
+#define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
#define MXC_CCM_CCGR4_PWM2_OFFSET 18
-#define MXC_CCM_CCGR4_PWM2_MASK (3<<MXC_CCM_CCGR4_PWM2_OFFSET)
+#define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
#define MXC_CCM_CCGR4_PWM3_OFFSET 20
-#define MXC_CCM_CCGR4_PWM3_MASK (3<<MXC_CCM_CCGR4_PWM3_OFFSET)
+#define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
#define MXC_CCM_CCGR4_PWM4_OFFSET 22
-#define MXC_CCM_CCGR4_PWM4_MASK (3<<MXC_CCM_CCGR4_PWM4_OFFSET)
+#define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
-#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
#define MXC_CCM_CCGR5_ROM_OFFSET 0
-#define MXC_CCM_CCGR5_ROM_MASK (3<<MXC_CCM_CCGR5_ROM_OFFSET)
+#define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
#define MXC_CCM_CCGR5_SATA_OFFSET 4
-#define MXC_CCM_CCGR5_SATA_MASK (3<<MXC_CCM_CCGR5_SATA_OFFSET)
+#define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
#define MXC_CCM_CCGR5_SDMA_OFFSET 6
-#define MXC_CCM_CCGR5_SDMA_MASK (3<<MXC_CCM_CCGR5_SDMA_OFFSET)
+#define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
#define MXC_CCM_CCGR5_SPBA_OFFSET 12
-#define MXC_CCM_CCGR5_SPBA_MASK (3<<MXC_CCM_CCGR5_SPBA_OFFSET)
+#define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
#define MXC_CCM_CCGR5_SPDIF_OFFSET 14
-#define MXC_CCM_CCGR5_SPDIF_MASK (3<<MXC_CCM_CCGR5_SPDIF_OFFSET)
+#define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
#define MXC_CCM_CCGR5_SSI1_OFFSET 18
-#define MXC_CCM_CCGR5_SSI1_MASK (3<<MXC_CCM_CCGR5_SSI1_OFFSET)
+#define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
#define MXC_CCM_CCGR5_SSI2_OFFSET 20
-#define MXC_CCM_CCGR5_SSI2_MASK (3<<MXC_CCM_CCGR5_SSI2_OFFSET)
+#define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
#define MXC_CCM_CCGR5_SSI3_OFFSET 22
-#define MXC_CCM_CCGR5_SSI3_MASK (3<<MXC_CCM_CCGR5_SSI3_OFFSET)
+#define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
#define MXC_CCM_CCGR5_UART_OFFSET 24
-#define MXC_CCM_CCGR5_UART_MASK (3<<MXC_CCM_CCGR5_UART_OFFSET)
+#define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
-#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3<<MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
+#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
#define MXC_CCM_CCGR6_USBOH3_OFFSET 0
-#define MXC_CCM_CCGR6_USBOH3_MASK (3<<MXC_CCM_CCGR6_USBOH3_OFFSET)
+#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
#define MXC_CCM_CCGR6_USDHC1_OFFSET 2
-#define MXC_CCM_CCGR6_USDHC1_MASK (3<<MXC_CCM_CCGR6_USDHC1_OFFSET)
+#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
-#define MXC_CCM_CCGR6_USDHC2_MASK (3<<MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
-#define MXC_CCM_CCGR6_USDHC3_MASK (3<<MXC_CCM_CCGR6_USDHC3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
-#define MXC_CCM_CCGR6_USDHC4_MASK (3<<MXC_CCM_CCGR6_USDHC4_OFFSET)
+#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
-#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3<<MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
-#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3<<MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
#define BP_ANADIG_PLL_SYS_RSVD0 20
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x000FFFFF
+
+#ifdef CONFIG_MX6SL
+#define GPU_2D_ARB_BASE_ADDR 0x02200000
+#define GPU_2D_ARB_END_ADDR 0x02203FFF
+#define OPENVG_ARB_BASE_ADDR 0x02204000
+#define OPENVG_ARB_END_ADDR 0x02207FFF
+#else
#define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00103FFF
#define APBH_DMA_ARB_BASE_ADDR 0x00110000
#define GPU_2D_ARB_END_ADDR 0x00137FFF
#define DTCP_ARB_BASE_ADDR 0x00138000
#define DTCP_ARB_END_ADDR 0x0013BFFF
+#endif /* CONFIG_MX6SL */
+
+#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
+#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
/* GPV - PL301 configuration ports */
+#ifdef CONFIG_MX6SL
+#define GPV2_BASE_ADDR 0x00D00000
+#else
#define GPV2_BASE_ADDR 0x00200000
+#endif
+
#define GPV3_BASE_ADDR 0x00300000
#define GPV4_BASE_ADDR 0x00800000
#define IRAM_BASE_ADDR 0x00900000
#define WEIM_ARB_BASE_ADDR 0x08000000
#define WEIM_ARB_END_ADDR 0x0FFFFFFF
+#ifdef CONFIG_MX6SL
+#define MMDC0_ARB_BASE_ADDR 0x80000000
+#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
+#define MMDC1_ARB_BASE_ADDR 0xC0000000
+#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
+#else
#define MMDC0_ARB_BASE_ADDR 0x10000000
#define MMDC0_ARB_END_ADDR 0x7FFFFFFF
#define MMDC1_ARB_BASE_ADDR 0x80000000
#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
+#endif
#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
#define IPU_SOC_OFFSET 0x00200000
#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
+#ifdef CONFIG_MX6SL
+#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
+#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
+#define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
+#define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
+#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
+#else
#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+#endif
+
#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
+#ifdef CONFIG_MX6SL
+#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
+#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#else
#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#endif
#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
+#ifdef CONFIG_MX6SL
+#define USBO2H_PL301_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
+#define USBO2H_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
+#else
#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
+#endif
+
#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
+#ifdef CONFIG_MX6SL
+#define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
+#else
#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
+#endif
+
#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
+#ifdef CONFIG_MX6SL
+#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+#else
#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+#endif
+
#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
#define CHIP_REV_1_0 0x10
#define IRAM_SIZE 0x00040000
-#define IMX_IIM_BASE OCOTP_BASE_ADDR
#define FEC_QUIRK_ENET_MAC
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
u32 gpr10;
};
-/* OCOTP Registers */
-struct ocotp_regs {
- u32 reserved[0x198];
- u32 gp1; /* 0x660 */
-};
-
/* GPR3 bitfields */
#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
#define MXC_CSPICON_POL 4
#define MXC_CSPICON_PHA 0
#define MXC_CSPICON_SSPOL 12
+#ifdef CONFIG_MX6SL
+#define MXC_SPI_BASE_ADDRESSES \
+ ECSPI1_BASE_ADDR, \
+ ECSPI2_BASE_ADDR, \
+ ECSPI3_BASE_ADDR, \
+ ECSPI4_BASE_ADDR
+#else
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \
ECSPI3_BASE_ADDR, \
ECSPI4_BASE_ADDR, \
ECSPI5_BASE_ADDR
+#endif
-struct iim_regs {
+struct ocotp_regs {
u32 ctrl;
u32 ctrl_set;
u32 ctrl_clr;
u32 rsvd1[3];
u32 read_ctrl;
u32 rsvd2[3];
- u32 fuse_data;
+ u32 read_fuse_data;
u32 rsvd3[3];
- u32 sticky;
+ u32 sw_sticky;
u32 rsvd4[3];
u32 scs;
u32 scs_set;
struct fuse_bank {
u32 fuse_regs[0x20];
- } bank[15];
+ } bank[16];
+};
+
+struct fuse_bank0_regs {
+ u32 lock;
+ u32 rsvd0[3];
+ u32 uid_low;
+ u32 rsvd1[3];
+ u32 uid_high;
+ u32 rsvd2[0x17];
};
struct fuse_bank4_regs {
u32 mac_addr_low;
u32 rsvd2[3];
u32 mac_addr_high;
- u32 rsvd3[0x13];
+ u32 rsvd3[0xb];
+ u32 gp1;
+ u32 rsvd4[3];
+ u32 gp2;
+ u32 rsvd5[3];
};
struct aipstz_regs {
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#include "mx6dl_pins.h"
#else
+#if defined(CONFIG_MX6SL)
+#include "mx6sl_pins.h"
+#else
#error "Please select cpu"
+#endif /* CONFIG_MX6SL */
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
#include <asm/imx-common/iomux-v3.h>
-/* Use to set PAD control */
-#define PAD_CTL_HYS (1 << 16)
-#define PAD_CTL_PUS_100K_DOWN (0 << 14)
-#define PAD_CTL_PUS_47K_UP (1 << 14)
-#define PAD_CTL_PUS_100K_UP (2 << 14)
-#define PAD_CTL_PUS_22K_UP (3 << 14)
-
-#define PAD_CTL_PUE (1 << 13)
-#define PAD_CTL_PKE (1 << 12)
-#define PAD_CTL_ODE (1 << 11)
-#define PAD_CTL_SPEED_LOW (1 << 6)
-#define PAD_CTL_SPEED_MED (2 << 6)
-#define PAD_CTL_SPEED_HIGH (3 << 6)
-#define PAD_CTL_DSE_DISABLE (0 << 3)
-#define PAD_CTL_DSE_240ohm (1 << 3)
-#define PAD_CTL_DSE_120ohm (2 << 3)
-#define PAD_CTL_DSE_80ohm (3 << 3)
-#define PAD_CTL_DSE_60ohm (4 << 3)
-#define PAD_CTL_DSE_48ohm (5 << 3)
-#define PAD_CTL_DSE_40ohm (6 << 3)
-#define PAD_CTL_DSE_34ohm (7 << 3)
-#define PAD_CTL_SRE_FAST (1 << 0)
-#define PAD_CTL_SRE_SLOW (0 << 0)
-
-#define IOMUX_CONFIG_SION 0x10
-#define NO_MUX_I 0
-#define NO_PAD_I 0
enum {
MX6_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0),
MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
MX6_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0),
MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, 0),
+ MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
#include <asm/imx-common/iomux-v3.h>
-/* Use to set PAD control */
-#define PAD_CTL_HYS (1 << 16)
-#define PAD_CTL_PUS_100K_DOWN (0 << 14)
-#define PAD_CTL_PUS_47K_UP (1 << 14)
-#define PAD_CTL_PUS_100K_UP (2 << 14)
-#define PAD_CTL_PUS_22K_UP (3 << 14)
-
-#define PAD_CTL_PUE (1 << 13)
-#define PAD_CTL_PKE (1 << 12)
-#define PAD_CTL_ODE (1 << 11)
-#define PAD_CTL_SPEED_LOW (1 << 6)
-#define PAD_CTL_SPEED_MED (2 << 6)
-#define PAD_CTL_SPEED_HIGH (3 << 6)
-#define PAD_CTL_DSE_DISABLE (0 << 3)
-#define PAD_CTL_DSE_240ohm (1 << 3)
-#define PAD_CTL_DSE_120ohm (2 << 3)
-#define PAD_CTL_DSE_80ohm (3 << 3)
-#define PAD_CTL_DSE_60ohm (4 << 3)
-#define PAD_CTL_DSE_48ohm (5 << 3)
-#define PAD_CTL_DSE_40ohm (6 << 3)
-#define PAD_CTL_DSE_34ohm (7 << 3)
-#define PAD_CTL_SRE_FAST (1 << 0)
-#define PAD_CTL_SRE_SLOW (0 << 0)
-
-#define NO_MUX_I 0
-#define NO_PAD_I 0
-
enum {
MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0),
--- /dev/null
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6SL_PINS_H__
+#define __ASM_ARCH_MX6_MX6SL_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+enum {
+ MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
+ MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0),
+ MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0),
+};
+#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
+#include <asm/imx-common/regs-common.h>
+
#define MXC_CPU_MX51 0x51
#define MXC_CPU_MX53 0x53
#define MXC_CPU_MX6SL 0x60
int fecmxc_initialize(bd_t *bis);
u32 get_ahb_clk(void);
u32 get_periph_clk(void);
+
+int mxs_reset_block(struct mxs_register_32 *reg);
+int mxs_wait_mask_set(struct mxs_register_32 *reg,
+ uint32_t mask,
+ unsigned int timeout);
+int mxs_wait_mask_clr(struct mxs_register_32 *reg,
+ uint32_t mask,
+ unsigned int timeout);
#endif
void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
+void mxs_set_lcdclk(uint32_t freq);
/* Compatibility with the FEC Ethernet driver */
#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK)
#ifndef __IMX_REGS_H__
#define __IMX_REGS_H__
-#include <asm/arch/regs-apbh.h>
+#include <asm/imx-common/regs-apbh.h>
#include <asm/arch/regs-base.h>
-#include <asm/arch/regs-bch.h>
+#include <asm/imx-common/regs-bch.h>
#include <asm/arch/regs-digctl.h>
-#include <asm/arch/regs-gpmi.h>
+#include <asm/imx-common/regs-gpmi.h>
#include <asm/arch/regs-i2c.h>
#include <asm/arch/regs-lcdif.h>
#include <asm/arch/regs-lradc.h>
#define PAD_16MA 3
#define PAD_1V8 0
+#if defined(CONFIG_MX28)
#define PAD_3V3 1
+#else
+#define PAD_3V3 0
+#endif
#define PAD_NOPULL 0
#define PAD_PULLUP 1
#ifndef __MX23_REGS_CLKCTRL_H__
#define __MX23_REGS_CLKCTRL_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_clkctrl_regs {
#ifndef __MX28_REGS_CLKCTRL_H__
#define __MX28_REGS_CLKCTRL_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_clkctrl_regs {
#ifndef __MX28_REGS_DIGCTL_H__
#define __MX28_REGS_DIGCTL_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_digctl_regs {
#ifndef __MX28_REGS_I2C_H__
#define __MX28_REGS_I2C_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_i2c_regs {
#ifndef __MX28_REGS_LCDIF_H__
#define __MX28_REGS_LCDIF_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
+#if defined(CONFIG_MX28)
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
- mxs_reg_32(hw_lcdif_transfer_count) /* 0x30 */
- mxs_reg_32(hw_lcdif_cur_buf) /* 0x40 */
- mxs_reg_32(hw_lcdif_next_buf) /* 0x50 */
+#endif
+ mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
+ mxs_reg_32(hw_lcdif_cur_buf) /* 0x30/0x40 */
+ mxs_reg_32(hw_lcdif_next_buf) /* 0x40/0x50 */
+
+#if defined(CONFIG_MX23)
+ uint32_t reserved1[4];
+#endif
+
mxs_reg_32(hw_lcdif_timing) /* 0x60 */
mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */
mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */
mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
- mxs_reg_32(hw_lcdif_data) /* 0x180 */
- mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x190 */
+
+#if defined(CONFIG_MX23)
+ uint32_t reserved2[12];
+#endif
+ mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */
+ mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */
+#if defined(CONFIG_MX28)
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
- mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1b0 */
- mxs_reg_32(hw_lcdif_version) /* 0x1c0 */
- mxs_reg_32(hw_lcdif_debug0) /* 0x1d0 */
- mxs_reg_32(hw_lcdif_debug1) /* 0x1e0 */
+#endif
+ mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
+ mxs_reg_32(hw_lcdif_version) /* 0x1e0/0x1c0 */
+ mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */
+ mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
};
#endif
#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
+#if defined(CONFIG_MX23)
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24)
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24
+#elif defined(CONFIG_MX28)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
+#endif
#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
#ifndef __MX28_REGS_LRADC_H__
#define __MX28_REGS_LRADC_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_lradc_regs {
#ifndef __MX28_REGS_OCOTP_H__
#define __MX28_REGS_OCOTP_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_ocotp_regs {
#ifndef __MX28_REGS_PINCTRL_H__
#define __MX28_REGS_PINCTRL_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_pinctrl_regs {
#ifndef __MX23_REGS_POWER_H__
#define __MX23_REGS_POWER_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_power_regs {
#ifndef __MX28_REGS_POWER_H__
#define __MX28_REGS_POWER_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_power_regs {
#ifndef __MX28_REGS_RTC_H__
#define __MX28_REGS_RTC_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_rtc_regs {
#ifndef __MX28_REGS_SSP_H__
#define __MX28_REGS_SSP_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
#if defined(CONFIG_MX23)
#ifndef __MX28_REGS_TIMROT_H__
#define __MX28_REGS_TIMROT_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_timrot_regs {
#define GPIO_FALLING_EDGE 1
#define GPIO_RISING_EDGE 2
#define GPIO_BOTH_EDGES 3
-extern void set_GPIO_IRQ_edge( int gpio_nr, int edge_mask );
-
-/*
- * Handy routine to set GPIO alternate functions
- */
-extern void set_GPIO_mode( int gpio_mode );
-
-/*
- * return current lclk frequency in units of 10kHz
- */
-extern unsigned int get_lclk_frequency_10khz(void);
#endif
u32 boot_mode; /* 0x25c */
u32 reserved4[116];
u32 trust_zone; /* 0x430 */ /* FIXME */
- u32 reserved5[115];
+ u32 reserved5_1[63];
+ u32 pss_idcode; /* 0x530 */
+ u32 reserved5_2[51];
u32 ddr_urgent; /* 0x600 */
u32 reserved6[6];
u32 ddr_urgent_sel; /* 0x61c */
- u32 reserved7[188];
+ u32 reserved7[56];
+ u32 mio_pin[54]; /* 0x700 - 0x7D4 */
+ u32 reserved8[74];
+ u32 lvl_shftr_en; /* 0x900 */
+ u32 reserved9[3];
u32 ocm_cfg; /* 0x910 */
};
extern void zynq_slcr_unlock(void);
extern void zynq_slcr_cpu_reset(void);
extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
+extern void zynq_slcr_devcfg_disable(void);
+extern void zynq_slcr_devcfg_enable(void);
+extern u32 zynq_slcr_get_idcode(void);
/* Driver extern functions */
extern int zynq_sdhci_init(u32 regbase);
MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS,
};
+#elif defined(CONFIG_MX6)
+enum {
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
+ MXS_MAX_DMA_CHANNELS,
+};
#endif
/*
--- /dev/null
+/*
+ * i.MX image header offset values
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ */
+
+/*
+ * NOTE: This file must be kept in sync with tools/imximage.h because
+ * tools/imximage.c can not cross-include headers from arch/arm/
+ * and vice-versa.
+ */
+
+#ifndef __ASM_IMX_COMMON_IMXIMAGE_CFG__
+#define __ASM_IMX_COMMON_IMXIMAGE_CFG__
+
+/* Standard image header offset for NAND, SATA, SD, SPI flash. */
+#define FLASH_OFFSET_STANDARD 0x400
+/* Specific image header offset for booting from OneNAND. */
+#define FLASH_OFFSET_ONENAND 0x100
+/* Specific image header offset for booting from memory-mapped NOR. */
+#define FLASH_OFFSET_NOR 0x1000
+
+#endif /* __ASM_IMX_COMMON_IMXIMAGE_CFG__ */
#ifndef __MACH_IOMUX_V3_H__
#define __MACH_IOMUX_V3_H__
+#include <common.h>
+
/*
* build IOMUX_PAD structure
*
((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
+#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \
+ MUX_PAD_CTRL(pad))
+
+#define __NA_ 0x000
+#define NO_MUX_I 0
+#define NO_PAD_I 0
+
#define NO_PAD_CTRL (1 << 17)
+
+#ifdef CONFIG_MX6
+
+#define PAD_CTL_HYS (1 << 16)
+
+#define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE)
+#define PAD_CTL_PKE (1 << 12)
+
+#define PAD_CTL_ODE (1 << 11)
+
+#define PAD_CTL_SPEED_LOW (1 << 6)
+#define PAD_CTL_SPEED_MED (2 << 6)
+#define PAD_CTL_SPEED_HIGH (3 << 6)
+
+#define PAD_CTL_DSE_DISABLE (0 << 3)
+#define PAD_CTL_DSE_240ohm (1 << 3)
+#define PAD_CTL_DSE_120ohm (2 << 3)
+#define PAD_CTL_DSE_80ohm (3 << 3)
+#define PAD_CTL_DSE_60ohm (4 << 3)
+#define PAD_CTL_DSE_48ohm (5 << 3)
+#define PAD_CTL_DSE_40ohm (6 << 3)
+#define PAD_CTL_DSE_34ohm (7 << 3)
+
+#else
+
+#define PAD_CTL_DVS (1 << 13)
+#define PAD_CTL_INPUT_DDR (1 << 9)
+#define PAD_CTL_HYS (1 << 8)
+
+#define PAD_CTL_PKE (1 << 7)
+#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
+#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
+
+#define PAD_CTL_ODE (1 << 3)
+
+#define PAD_CTL_DSE_LOW (0 << 1)
+#define PAD_CTL_DSE_MED (1 << 1)
+#define PAD_CTL_DSE_HIGH (2 << 1)
+#define PAD_CTL_DSE_MAX (3 << 1)
+
+#endif
+
+#define PAD_CTL_SRE_SLOW (0 << 0)
+#define PAD_CTL_SRE_FAST (1 << 0)
+
+#define IOMUX_CONFIG_SION 0x10
+
#define GPIO_PIN_MASK 0x1f
#define GPIO_PORT_SHIFT 5
#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
-#define MUX_CONFIG_SION (0x1 << 4)
-
-int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
-int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
+void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count);
#endif /* __MACH_IOMUX_V3_H__*/
#ifndef __REGS_APBH_H__
#define __REGS_APBH_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
mxs_reg_32(hw_apbh_version)
};
-#elif defined(CONFIG_MX28)
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0)
mxs_reg_32(hw_apbh_ctrl1)
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
+#elif defined(CONFIG_MX6)
+#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0004
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0008
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0010
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0020
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0040
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0080
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP 0x0100
#endif
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31)
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
#endif
+#if defined(CONFIG_MX6)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
+#endif
+
#if defined(CONFIG_MX23)
#define APBH_DEVSEL_CH7_MASK (0xf << 28)
#define APBH_DEVSEL_CH7_OFFSET 28
#ifndef __MX28_REGS_BCH_H__
#define __MX28_REGS_BCH_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_bch_regs {
#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
+#if defined(CONFIG_MX6)
+#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
+#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
+#else
#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12)
#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12
+#endif
#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12)
#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
+#if defined(CONFIG_MX6)
+#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
+#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
+#else
#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12)
#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12
+#endif
#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12)
#ifndef __MX28_REGS_GPMI_H__
#define __MX28_REGS_GPMI_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_gpmi_regs {
/* NOTREACHED - no way out of command loop except booting */
}
-
-void hang(void)
-{
- puts("### ERROR ### Please RESET the board ###\n");
- for (;;);
-}
return 0;
}
-void hang(void)
-{
- for (;;) ;
-}
-
static int display_dram_config (void)
{
int i;
for (;;)
main_loop();
}
-
-void hang(void)
-{
-#ifdef CONFIG_STATUS_LED
- status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
- status_led_set(STATUS_LED_CRASH, STATUS_LED_BLINKING);
-#endif
- puts("### ERROR ### Please RESET the board ###\n");
- while (1)
- /* If a JTAG emulator is hooked up, we'll automatically trigger
- * a breakpoint in it. If one isn't, this is just a NOP.
- */
- asm("emuexcpt;");
-}
/* NOTREACHED - no way out of command loop except booting */
}
-
-
-void hang(void)
-{
- puts ("### ERROR ### Please RESET the board ###\n");
- for (;;);
-}
/* Microblaze board initialization function */
void board_init(void);
+/* Watchdog functions */
+extern int hw_watchdog_init(void);
+extern void hw_watchdog_disable(void);
+
#endif /* __ASM_MICROBLAZE_PROCESSOR_H */
serial_init,
console_init_f,
interrupts_init,
+#ifdef CONFIG_XILINX_TB_WATCHDOG
+ hw_watchdog_init,
+#endif
timer_init,
NULL,
};
{
bd_t *bd;
init_fnc_t **init_fnc_ptr;
- gd = (gd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET);
- bd = (bd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
+ gd = (gd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET);
+ bd = (bd_t *)(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET
- GENERATED_BD_INFO_SIZE);
#if defined(CONFIG_CMD_FLASH)
ulong flash_size = 0;
#endif
asm ("nop"); /* FIXME gd is not initialize - wait */
- memset ((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
- memset ((void *)bd, 0, GENERATED_BD_INFO_SIZE);
+ memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
+ memset((void *)bd, 0, GENERATED_BD_INFO_SIZE);
gd->bd = bd;
gd->baudrate = CONFIG_BAUDRATE;
bd->bi_baudrate = CONFIG_BAUDRATE;
* aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off
* as our monitory code is run from SDRAM
*/
- mem_malloc_init (CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
+ mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
serial_initialize();
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
- WATCHDOG_RESET ();
- if ((*init_fnc_ptr) () != 0) {
- hang ();
- }
+ WATCHDOG_RESET();
+ if ((*init_fnc_ptr) () != 0)
+ hang();
}
#ifdef CONFIG_OF_CONTROL
/* For now, put this check after the console is ready */
- if (fdtdec_prepare_fdt()) {
- panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
- "doc/README.fdt-control");
- } else
+ if (fdtdec_prepare_fdt())
+ panic("** No FDT - please see doc/README.fdt-control");
+ else
printf("DTB: 0x%x\n", (u32)gd->fdt_blob);
#endif
- puts ("SDRAM :\n");
- printf ("\t\tIcache:%s\n", icache_status() ? "ON" : "OFF");
- printf ("\t\tDcache:%s\n", dcache_status() ? "ON" : "OFF");
- printf ("\tU-Boot Start:0x%08x\n", CONFIG_SYS_TEXT_BASE);
+ puts("SDRAM :\n");
+ printf("\t\tIcache:%s\n", icache_status() ? "ON" : "OFF");
+ printf("\t\tDcache:%s\n", dcache_status() ? "ON" : "OFF");
+ printf("\tU-Boot Start:0x%08x\n", CONFIG_SYS_TEXT_BASE);
#if defined(CONFIG_CMD_FLASH)
- puts ("Flash: ");
+ puts("Flash: ");
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
flash_size = flash_init();
if (bd->bi_flashstart && flash_size > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
- print_size (flash_size, "");
+ print_size(flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
if (getenv_yesno("flashchecksum") == 1) {
- printf (" CRC: %08X",
- crc32(0, (const u8 *)bd->bi_flashstart,
- flash_size)
+ printf(" CRC: %08X",
+ crc32(0, (const u8 *)bd->bi_flashstart,
+ flash_size)
);
}
- putc ('\n');
+ putc('\n');
# else /* !CONFIG_SYS_FLASH_CHECKSUM */
- print_size (flash_size, "\n");
+ print_size(flash_size, "\n");
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
bd->bi_flashsize = flash_size;
bd->bi_flashoffset = bd->bi_flashstart + flash_size;
} else {
- puts ("Flash init FAILED");
+ puts("Flash init FAILED");
bd->bi_flashstart = 0;
bd->bi_flashsize = 0;
bd->bi_flashoffset = 0;
#endif
/* relocate environment function pointers etc. */
- env_relocate ();
+ env_relocate();
/* Initialize stdio devices */
- stdio_init ();
+ stdio_init();
/* Initialize the jump table for applications */
jumptable_init();
/* main_loop */
for (;;) {
- WATCHDOG_RESET ();
- main_loop ();
+ WATCHDOG_RESET();
+ main_loop();
}
}
-
-void hang (void)
-{
- puts ("### ERROR ### Please RESET the board ###\n");
- for (;;) ;
-}
/* NOTREACHED - no way out of command loop except booting */
}
-
-void hang(void)
-{
- puts("### ERROR ### Please RESET the board ###\n");
- for (;;)
- ;
-}
/* NOTREACHED - no way out of command loop except booting */
}
-
-void hang(void)
-{
- puts("### ERROR ### Please RESET the board ###\n");
- for (;;)
- ;
-}
***********************************************************************/
init_fnc_t *init_sequence[] = {
-
#if defined(CONFIG_BOARD_EARLY_INIT_F)
board_early_init_f, /* Call board-specific init code early.*/
#endif
/***********************************************************************/
-void board_init (void)
+void board_init(void)
{
bd_t *bd;
init_fnc_t **init_fnc_ptr;
/* Pointer is writable since we allocated a register for it. */
gd = &gd_data;
/* compiler optimization barrier needed for GCC >= 3.4 */
- __asm__ __volatile__("": : :"memory");
+ __asm__ __volatile__("" : : : "memory");
gd->bd = &bd_data;
gd->baudrate = CONFIG_BAUDRATE;
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
#endif
#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
- bd->bi_sramstart= CONFIG_SYS_SRAM_BASE;
+ bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
bd->bi_baudrate = CONFIG_BAUDRATE;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
- WATCHDOG_RESET ();
- if ((*init_fnc_ptr) () != 0) {
- hang ();
- }
+ WATCHDOG_RESET();
+ if ((*init_fnc_ptr) () != 0)
+ hang();
}
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
/* The Malloc area is immediately below the monitor copy in RAM */
mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
#ifndef CONFIG_SYS_NO_FLASH
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
bd->bi_flashsize = flash_init();
#endif
mmc_initialize(bd);
#endif
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
env_relocate();
- WATCHDOG_RESET ();
+ WATCHDOG_RESET();
stdio_init();
jumptable_init();
console_init_r();
- WATCHDOG_RESET ();
- interrupt_init ();
+ WATCHDOG_RESET();
+ interrupt_init();
#if defined(CONFIG_BOARD_LATE_INIT)
- board_late_init ();
+ board_late_init();
#endif
#if defined(CONFIG_CMD_NET)
- puts ("Net: ");
- eth_initialize (bd);
+ puts("Net: ");
+ eth_initialize(bd);
#endif
/* main_loop */
for (;;) {
- WATCHDOG_RESET ();
- main_loop ();
+ WATCHDOG_RESET();
+ main_loop();
}
}
-
-
-/***********************************************************************/
-
-void hang (void)
-{
- disable_interrupts ();
- puts("### ERROR ### Please reset board ###\n");
- for (;;);
-}
main_loop();
}
}
-
-
-/***********************************************************************/
-
-void hang(void)
-{
- disable_interrupts();
- puts("### ERROR ### Please reset board ###\n");
-
- for (;;)
- ;
-}
COBJS-y += speed.o
COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
COBJS-$(CONFIG_CMD_IDE) += ide.o
-COBJS-$(CONFIG_IIM) += iim.o
COBJS-$(CONFIG_PCI) += pci.o
# Stub implementations of cache management functions for USB
*/
out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
-#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+#if defined(CONFIG_FSL_IIM) || defined(CONFIG_CMD_FUSE)
setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
#endif
}
+++ /dev/null
-/*
- * Copyright 2008 Silicon Turnkey Express, Inc.
- * Martha Marx <mmarx@silicontkx.com>
- *
- * ADS5121 IIM (Fusebox) Interface
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_CMD_FUSE
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static char cur_bank = '1';
-
-char *iim_err_msg(u32 err)
-{
- static char *IIM_errs[] = {
- "Parity Error in cache",
- "Explicit Sense Cycle Error",
- "Write to Locked Register Error",
- "Read Protect Error",
- "Override Protect Error",
- "Write Protect Error"};
-
- int i;
-
- if (!err)
- return "";
- for (i = 1; i < 8; i++)
- if (err & (1 << i))
- printf("IIM - %s\n", IIM_errs[i-1]);
- return "";
-}
-
-int in_range(int n, int min, int max, char *err, char *usg)
-{
- if (n > max || n < min) {
- printf(err);
- printf("Usage:\n%s\n", usg);
- return 0;
- }
- return 1;
-}
-
-int ads5121_fuse_read(int bank, int fstart, int num)
-{
- iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
- u32 *iim_fb, dummy;
- int f, ctr;
-
- out_be32(&iim->err, in_be32(&iim->err));
- if (bank == 0)
- iim_fb = (u32 *)&(iim->fbac0);
- else
- iim_fb = (u32 *)&(iim->fbac1);
-/* try a read to see if Read Protect is set */
- dummy = in_be32(&iim_fb[0]);
- if (in_be32(&iim->err) & IIM_ERR_RPE) {
- printf("\tRead protect fuse is set\n");
- out_be32(&iim->err, IIM_ERR_RPE);
- return 0;
- }
- printf("Reading Bank %d cache\n", bank);
- for (f = fstart, ctr = 0; num > 0; ctr++, num--, f++) {
- if (ctr % 4 == 0)
- printf("F%2d:", f);
- printf("\t%#04x", (u8)(iim_fb[f]));
- if (ctr % 4 == 3)
- printf("\n");
- }
- if (ctr % 4 != 0)
- printf("\n");
-}
-
-int ads5121_fuse_override(int bank, int f, u8 val)
-{
- iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
- u32 *iim_fb;
- u32 iim_stat;
- int i;
-
- out_be32(&iim->err, in_be32(&iim->err));
- if (bank == 0)
- iim_fb = (u32 *)&(iim->fbac0);
- else
- iim_fb = (u32 *)&(iim->fbac1);
-/* try a read to see if Read Protect is set */
- iim_stat = in_be32(&iim_fb[0]);
- if (in_be32(&iim->err) & IIM_ERR_RPE) {
- printf("Read protect fuse is set on bank %d;"
- "Override protect may also be set\n", bank);
- printf("An attempt will be made to override\n");
- out_be32(&iim->err, IIM_ERR_RPE);
- }
- if (iim_stat & IIM_FBAC_FBOP) {
- printf("Override protect fuse is set on bank %d\n", bank);
- return 1;
- }
- if (f > IIM_FMAX) /* reset the entire bank */
- for (i = 0; i < IIM_FMAX + 1; i++)
- out_be32(&iim_fb[i], 0);
- else
- out_be32(&iim_fb[f], val);
- return 0;
-}
-
-int ads5121_fuse_prog(cmd_tbl_t *cmdtp, int bank, char *fuseno_bitno)
-{
- iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
- int f, i, bitno;
- u32 stat, err;
-
- f = simple_strtol(fuseno_bitno, NULL, 10);
- if (f == 0 && fuseno_bitno[0] != '0')
- f = -1;
- if (!in_range(f, 0, IIM_FMAX,
- "<frow> must be between 0-31\n\n", cmdtp->usage))
- return 1;
- bitno = -1;
- for (i = 0; i < 6; i++) {
- if (fuseno_bitno[i] == '_') {
- bitno = simple_strtol(&(fuseno_bitno[i+1]), NULL, 10);
- if (bitno == 0 && fuseno_bitno[i+1] != '0')
- bitno = -1;
- break;
- }
- }
- if (!in_range(bitno, 0, 7, "Bit number ranges from 0-7\n"
- "Example of <frow_bitno>: \"18_4\" sets bit 4 of row 18\n",
- cmdtp->usage))
- return 1;
- out_be32(&iim->err, in_be32(&iim->err));
- out_be32(&iim->prg_p, IIM_PRG_P_SET);
- out_be32(&iim->ua, IIM_SET_UA(bank, f));
- out_be32(&iim->la, IIM_SET_LA(f, bitno));
-#ifdef DEBUG
- printf("Programming disabled with DEBUG defined \n");
- printf(""Set up to pro
- printf("iim.ua = %x; iim.la = %x\n", iim->ua, iim->la);
-#else
- out_be32(&iim->fctl, IIM_FCTL_PROG_PULSE | IIM_FCTL_PROG);
- do
- udelay(20);
- while ((stat = in_be32(&iim->stat)) & IIM_STAT_BUSY);
- out_be32(&iim->prg_p, 0);
- err = in_be32(&iim->err);
- if (stat & IIM_STAT_PRGD) {
- if (!(err & (IIM_ERR_WPE | IIM_ERR_WPE))) {
- printf("Fuse is successfully set");
- if (err)
- printf(" - however there are other errors");
- printf("\n");
- }
- iim->stat = 0;
- }
- if (err) {
- iim_err_msg(err);
- out_be32(&iim->err, in_be32(&iim->err));
- }
-#endif
-}
-
-int ads5121_fuse_sense(int bank, int fstart, int num)
-{
- iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
- u32 iim_fbac;
- u32 stat, err, err_hold = 0;
- int f, ctr;
-
- out_be32(&iim->err, in_be32(&iim->err));
- if (bank == 0)
- iim_fbac = in_be32(&iim->fbac0);
- else
- iim_fbac = in_be32(&iim->fbac1);
- if (iim_fbac & IIM_FBAC_FBESP) {
- printf("\tSense Protect disallows this operation\n");
- out_be32(&iim->err, IIM_FBAC_FBESP);
- return 1;
- }
- err = in_be32(&iim->err);
- if (err) {
- iim_err_msg(err);
- err_hold |= err;
- }
- if (err & IIM_ERR_RPE)
- printf("\tRead protect fuse is set; "
- "Sense Protect may be set but will be attempted\n");
- if (err)
- out_be32(&iim->err, err);
- printf("Sensing fuse(s) on Bank %d\n", bank);
- for (f = fstart, ctr = 0; num > 0; ctr++, f++, num--) {
- out_be32(&iim->ua, IIM_SET_UA(bank, f));
- out_be32(&iim->la, IIM_SET_LA(f, 0));
- out_be32(&iim->fctl, IIM_FCTL_ESNS_N);
- do
- udelay(20);
- while ((stat = in_be32(&iim->stat)) & IIM_STAT_BUSY);
- err = in_be32(&iim->err);
- if (err & IIM_ERR_SNSE) {
- iim_err_msg(err);
- out_be32(&iim->err, IIM_ERR_SNSE);
- return 1;
- }
- if (stat & IIM_STAT_SNSD) {
- out_be32(&iim->stat, 0);
- if (ctr % 4 == 0)
- printf("F%2d:", f);
- printf("\t%#04x", (u8)iim->sdat);
- if (ctr % 4 == 3)
- printf("\n");
- }
- if (err) {
- err_hold |= err;
- out_be32(&iim->err, err);
- }
- }
- if (ctr % 4 != 0)
- printf("\n");
- if (err_hold)
- iim_err_msg(err_hold);
-
- return 0;
-}
-
-int ads5121_fuse_stat(int bank)
-{
- iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
- u32 iim_fbac;
- u32 err;
-
- out_be32(&iim->err, in_be32(&iim->err));
- if (bank == 0)
- iim_fbac = in_be32(&iim->fbac0);
- else
- iim_fbac = in_be32(&iim->fbac1);
- err = in_be32(&iim->err);
- if (err)
- iim_err_msg(err);
- if (err & IIM_ERR_RPE || iim_fbac & IIM_FBAC_FBRP) {
- if (iim_fbac == 0)
- printf("Since protection settings can't be read - "
- "try sensing fuse row 0;\n");
- return 0;
- }
- if (iim_fbac & IIM_PROTECTION)
- printf("Protection Fuses Bank %d = %#04x:\n", bank, iim_fbac);
- else if (!(err & IIM_ERR_RPE))
- printf("No Protection fuses are set\n");
- if (iim_fbac & IIM_FBAC_FBWP)
- printf("\tWrite Protect fuse is set\n");
- if (iim_fbac & IIM_FBAC_FBOP)
- printf("\tOverride Protect fuse is set\n");
- if (iim_fbac & IIM_FBAC_FBESP)
- printf("\tSense Protect Fuse is set\n");
- out_be32(&iim->err, in_be32(&iim->err));
-
- return 0;
-}
-
-int do_ads5121_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int frow, n, v, bank;
-
- if (cur_bank == '0')
- bank = 0;
- else
- bank = 1;
-
- switch (argc) {
- case 0:
- case 1:
- printf("Usage:\n%s\n", cmdtp->usage);
- return 1;
- case 2:
- if (strncmp(argv[1], "stat", 4) == 0)
- return ads5121_fuse_stat(bank);
- if (strncmp(argv[1], "read", 4) == 0)
- return ads5121_fuse_read(bank, 0, IIM_FMAX + 1);
- if (strncmp(argv[1], "sense", 5) == 0)
- return ads5121_fuse_sense(bank, 0, IIM_FMAX + 1);
- if (strncmp(argv[1], "ovride", 6) == 0)
- return ads5121_fuse_override(bank, IIM_FMAX + 1, 0);
- if (strncmp(argv[1], "bank", 4) == 0) {
- printf("Active Fuse Bank is %c\n", cur_bank);
- return 0;
- }
- printf("Usage:\n%s\n", cmdtp->usage);
- return 1;
- case 3:
- if (strncmp(argv[1], "bank", 4) == 0) {
- if (argv[2][0] == '0')
- cur_bank = '0';
- else if (argv[2][0] == '1')
- cur_bank = '1';
- else {
- printf("Usage:\n%s\n", cmdtp->usage);
- return 1;
- }
-
- printf("Setting Active Fuse Bank to %c\n", cur_bank);
- return 0;
- }
- if (strncmp(argv[1], "prog", 4) == 0)
- return ads5121_fuse_prog(cmdtp, bank, argv[2]);
-
- frow = (int)simple_strtol(argv[2], NULL, 10);
- if (frow == 0 && argv[2][0] != '0')
- frow = -1;
- if (!in_range(frow, 0, IIM_FMAX,
- "<frow> must be between 0-31\n\n", cmdtp->usage))
- return 1;
- if (strncmp(argv[1], "read", 4) == 0)
- return ads5121_fuse_read(bank, frow, 1);
- if (strncmp(argv[1], "ovride", 6) == 0)
- return ads5121_fuse_override(bank, frow, 0);
- if (strncmp(argv[1], "sense", 5) == 0)
- return ads5121_fuse_sense(bank, frow, 1);
- printf("Usage:\n%s\n", cmdtp->usage);
- return 1;
- case 4:
- frow = (int)simple_strtol(argv[2], NULL, 10);
- if (frow == 0 && argv[2][0] != '0')
- frow = -1;
- if (!in_range(frow, 0, IIM_FMAX,
- "<frow> must be between 0-31\n\n", cmdtp->usage))
- return 1;
- if (strncmp(argv[1], "read", 4) == 0) {
- n = (int)simple_strtol(argv[3], NULL, 10);
- if (!in_range(frow + n, frow + 1, IIM_FMAX + 1,
- "<frow>+<n> must be between 1-32\n\n",
- cmdtp->usage))
- return 1;
- return ads5121_fuse_read(bank, frow, n);
- }
- if (strncmp(argv[1], "ovride", 6) == 0) {
- v = (int)simple_strtol(argv[3], NULL, 10);
- return ads5121_fuse_override(bank, frow, v);
- }
- if (strncmp(argv[1], "sense", 5) == 0) {
- n = (int)simple_strtol(argv[3], NULL, 10);
- if (!in_range(frow + n, frow + 1, IIM_FMAX + 1,
- "<frow>+<n> must be between 1-32\n\n",
- cmdtp->usage))
- return 1;
- return ads5121_fuse_sense(bank, frow, n);
- }
- printf("Usage:\n%s\n", cmdtp->usage);
- return 1;
- default: /* at least 5 args */
- printf("Usage:\n%s\n", cmdtp->usage);
- return 1;
- }
-}
-
-U_BOOT_CMD(
- fuse, CONFIG_SYS_MAXARGS, 0, do_ads5121_fuse,
- " - Read, Sense, Override or Program Fuses\n",
- "bank <n> - sets active Fuse Bank to 0 or 1\n"
- " no args shows current active bank\n"
- "fuse stat - print active fuse bank's protection status\n"
- "fuse read [<frow> [<n>]] - print <n> fuse rows starting at <frow>\n"
- " no args to print entire bank's fuses\n"
- "fuse ovride [<frow> [<v>]]- override fuses at <frow> with <v>\n"
- " no <v> defaults to 0 for the row\n"
- " no args resets entire bank to 0\n"
- " NOTE - settings persist until hard reset\n"
- "fuse sense [<frow>] - senses current fuse at <frow>\n"
- " no args for entire bank\n"
- "fuse prog <frow_bit> - program fuse at row <frow>, bit <_bit>\n"
- " <frow> is 0-31, <bit> is 0-7; eg. 13_2 \n"
- " WARNING - this is permanent"
-);
-#endif /* CONFIG_CMD_FUSE */
"print clock configuration",
" clocks"
);
-
-int prt_mpc512x_clks (void)
-{
- do_clocks (NULL, 0, 0, NULL);
- return (0);
-}
#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
puts("Work-around for Erratum PCIe-A003 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
+ puts("Work-around for Erratum USB14 enabled\n");
#endif
return 0;
}
#if defined(CONFIG_WATCHDOG)
-void
-watchdog_reset(void)
-{
- int re_enable = disable_interrupts();
- reset_85xx_watchdog();
- if (re_enable) enable_interrupts();
-}
-
void
reset_85xx_watchdog(void)
{
*/
mtspr(SPRN_TSR, TSR_WIS);
}
+
+void
+watchdog_reset(void)
+{
+ int re_enable = disable_interrupts();
+
+ reset_85xx_watchdog();
+ if (re_enable)
+ enable_interrupts();
+}
#endif /* CONFIG_WATCHDOG */
/*
}
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
+ /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
+ * multi-bit ECC errors which has impact on performance, so software
+ * should disable all ECC reporting from USB1 and USB2.
+ */
+ if (IS_SVR_REV(get_svr(), 1, 0)) {
+ struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
+ (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
+ setbits_be32(&dcfg->ecccr1,
+ (DCSR_DCFG_ECC_DISABLE_USB1 |
+ DCSR_DCFG_ECC_DISABLE_USB2));
+ }
+#endif
+
#ifdef CONFIG_FMAN_ENET
fman_enet_init();
#endif
#ifdef CONFIG_FSL_CORENET
do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+ do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2",
+ "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+ do_fixup_by_compat_u32(blob, "fsl,mpic",
+ "clock-frequency", get_bus_freq(0)/2, 1);
+#else
+ do_fixup_by_compat_u32(blob, "fsl,mpic",
+ "clock-frequency", get_bus_freq(0), 1);
#endif
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
{ 22, 168, FSL_SRDS_BANK_3 },
{ 23, 169, FSL_SRDS_BANK_3 },
#endif
+#if SRDS_MAX_BANK > 3
+ { 24, 175, FSL_SRDS_BANK_4 },
+ { 25, 176, FSL_SRDS_BANK_4 },
+#endif
};
int serdes_get_lane_idx(int lane)
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
- SET_QP_INFO(1, 2, 1, 0),
- SET_QP_INFO(3, 4, 2, 1),
- SET_QP_INFO(5, 6, 3, 2),
- SET_QP_INFO(7, 8, 4, 3),
- SET_QP_INFO(9, 10, 5, 0),
- SET_QP_INFO(11, 12, 1, 1),
- SET_QP_INFO(13, 14, 2, 2),
- SET_QP_INFO(15, 16, 3, 3),
- SET_QP_INFO(17, 18, 4, 0), /* for now sdest to 0 */
- SET_QP_INFO(19, 20, 5, 0), /* for now sdest to 0 */
+ SET_QP_INFO(1, 2, 1, 0),
+ SET_QP_INFO(3, 4, 2, 1),
+ SET_QP_INFO(5, 6, 3, 2),
+ SET_QP_INFO(7, 8, 4, 3),
+ SET_QP_INFO(9, 10, 5, 0),
+ SET_QP_INFO(11, 12, 6, 1),
+ SET_QP_INFO(13, 14, 7, 2),
+ SET_QP_INFO(15, 16, 8, 3),
+ SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */
+ SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */
};
#endif
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
- SET_QP_INFO(1, 2, 1, 0),
- SET_QP_INFO(3, 4, 2, 1),
- SET_QP_INFO(5, 6, 3, 2),
- SET_QP_INFO(7, 8, 4, 3),
- SET_QP_INFO(9, 10, 5, 0),
- SET_QP_INFO(11, 12, 1, 1),
- SET_QP_INFO(13, 14, 2, 2),
- SET_QP_INFO(15, 16, 3, 3),
- SET_QP_INFO(17, 18, 4, 0), /* for now sdest to 0 */
- SET_QP_INFO(19, 20, 5, 0), /* for now sdest to 0 */
+ SET_QP_INFO(1, 2, 1, 0),
+ SET_QP_INFO(3, 4, 2, 1),
+ SET_QP_INFO(5, 6, 3, 2),
+ SET_QP_INFO(7, 8, 4, 3),
+ SET_QP_INFO(9, 10, 5, 0),
+ SET_QP_INFO(1, 12, 6, 1),
+ SET_QP_INFO(13, 14, 7, 2),
+ SET_QP_INFO(15, 16, 8, 3),
+ SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */
+ SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */
};
#endif
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
- SET_QP_INFO(1, 2, 1, 0),
- SET_QP_INFO(3, 4, 2, 1),
- SET_QP_INFO(5, 6, 3, 0),
- SET_QP_INFO(7, 8, 4, 1),
- SET_QP_INFO(9, 10, 5, 0),
- SET_QP_INFO(11, 12, 1, 1),
- SET_QP_INFO(13, 14, 2, 0),
- SET_QP_INFO(15, 16, 3, 1),
- SET_QP_INFO(17, 18, 4, 0),
- SET_QP_INFO(19, 20, 5, 1),
+ SET_QP_INFO(1, 2, 1, 0),
+ SET_QP_INFO(3, 4, 2, 1),
+ SET_QP_INFO(5, 6, 3, 0),
+ SET_QP_INFO(7, 8, 4, 1),
+ SET_QP_INFO(9, 10, 5, 0),
+ SET_QP_INFO(11, 12, 6, 1),
+ SET_QP_INFO(13, 14, 7, 0),
+ SET_QP_INFO(15, 16, 8, 1),
+ SET_QP_INFO(17, 18, 9, 0),
+ SET_QP_INFO(19, 20, 10, 1),
};
#endif
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
-static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
-static ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
-
void setup_portals(void)
{
+ ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
#ifdef CONFIG_FSL_CORENET
int i;
num = get_dpaa_liodn(dev, &liodns[0], id);
ret = fdt_setprop(blob, childoff, "fsl,liodn",
&liodns[0], sizeof(u32) * num);
+ if (!strncmp(name, "pme", 3)) {
+ u32 pme_rev1, pme_rev2;
+ ccsr_pme_t *pme_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
+
+ pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
+ pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
+ ret = fdt_setprop(blob, childoff,
+ "fsl,pme-rev1", &pme_rev1, sizeof(u32));
+ if (ret < 0)
+ return ret;
+ ret = fdt_setprop(blob, childoff,
+ "fsl,pme-rev2", &pme_rev2, sizeof(u32));
+ }
#endif
} else {
return childoff;
int off, err;
unsigned int maj, min;
unsigned int ip_cfg;
+ ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
u32 rev_1 = in_be32(&qman->ip_rev_1);
u32 rev_2 = in_be32(&qman->ip_rev_2);
char compat[64];
int off, err;
unsigned int maj, min;
unsigned int ip_cfg;
+ ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
u32 rev_1 = in_be32(&bman->ip_rev_1);
u32 rev_2 = in_be32(&bman->ip_rev_2);
char compat[64];
COBJS += uic.o
endif
+ifdef CONFIG_SPL_BUILD
+COBJS-y += spl_boot.o
+endif
+
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS-y))
START := $(addprefix $(obj),$(START))
--- /dev/null
+/*
+ * Copyright (C) 2013 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Return selected boot device. On PPC4xx its only NOR flash right now.
+ */
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_NOR;
+}
+
+/*
+ * SPL version of board_init_f()
+ */
+void board_init_f(ulong bootflag)
+{
+ /*
+ * First we need to initialize the SDRAM, so that the real
+ * U-Boot or the OS (Linux) can be loaded
+ */
+ initdram(0);
+
+ /* Clear bss */
+ memset(__bss_start, '\0', __bss_end - __bss_start);
+
+ /*
+ * Init global_data pointer. Has to be done before calling
+ * get_clocks(), as it stores some clock values into gd needed
+ * later on in the serial driver.
+ */
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+ /* Clear initial global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+
+ /*
+ * get_clocks() needs to be called so that the serial driver
+ * works correctly
+ */
+ get_clocks();
+
+ /*
+ * Do rudimental console / serial setup
+ */
+ preloader_console_init();
+
+ /*
+ * Call board_init_r() (SPL framework version) to load and boot
+ * real U-Boot or OS
+ */
+ board_init_r(NULL, 0);
+ /* Does not return!!! */
+}
*
* Use r12 to access the GOT
*/
-#if !defined(CONFIG_NAND_SPL)
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
END_GOT
#endif /* CONFIG_NAND_SPL */
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
+ !defined(CONFIG_SPL_BUILD)
/*
* NAND U-Boot image is started from offset 0
*/
bl _start_440
#endif
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+ /*
+ * This is the entry of the real U-Boot from a board port
+ * that supports SPL booting on the PPC4xx. We only need
+ * to call board_init_f() here. Everything else has already
+ * been done in the SPL u-boot version.
+ */
+ GET_GOT /* initialize GOT access */
+ bl board_init_f /* run 1st part of board init code (in Flash)*/
+ /* NOTREACHED - board_init_f() does not return */
+#endif
+
/*
* 440 Startup -- on reset only the top 4k of the effective
* address space is mapped in by an entry in the instruction
* r3 - 1st arg to board_init(): IMMP pointer
* r4 - 2nd arg to board_init(): boot flag
*/
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
.text
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
.globl _start
_start:
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+ /*
+ * This is the entry of the real U-Boot from a board port
+ * that supports SPL booting on the PPC4xx. We only need
+ * to call board_init_f() here. Everything else has already
+ * been done in the SPL u-boot version.
+ */
+ GET_GOT /* initialize GOT access */
+ bl board_init_f /* run 1st part of board init code (in Flash)*/
+ /* NOTREACHED - board_init_f() does not return */
+#endif
+
/*****************************************************************************/
#if defined(CONFIG_440)
#ifdef CONFIG_NAND_SPL
bl nand_boot_common /* will not return */
#else
+#ifndef CONFIG_SPL_BUILD
GET_GOT
+#endif
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
/*----------------------------------------------------------------------- */
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
/*
* This code finishes saving the registers to the exception frame
* and jumps to the appropriate handler for the exception.
lwbrx r3,r0,r3
blr
+#if !defined(CONFIG_SPL_BUILD)
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
mtlr r4 /* restore link register */
blr
+#endif /* CONFIG_SPL_BUILD */
#if defined(CONFIG_440)
/*----------------------------------------------------------------------------+
--- /dev/null
+/*
+ * Copyright 2012-2013 Stefan Roese <sr@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY
+{
+ sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE
+ flash : ORIGIN = CONFIG_SPL_TEXT_BASE,
+ LENGTH = CONFIG_SYS_SPL_MAX_LEN
+}
+
+OUTPUT_ARCH(powerpc)
+ENTRY(_start)
+SECTIONS
+{
+#ifdef CONFIG_440
+ .bootpg 0xfffff000 :
+ {
+ arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
+
+ /*
+ * PPC440 board need a board specific object with the
+ * TLB definitions. This needs to get included right after
+ * start.o, since the first shadow TLB only covers 4k
+ * of address space.
+ */
+ CONFIG_BOARDDIR/init.o (.bootpg)
+ } > flash
+#endif
+
+ .resetvec 0xFFFFFFFC :
+ {
+ KEEP(*(.resetvec))
+ } > flash
+
+ .text :
+ {
+ __start = .;
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
+ CONFIG_BOARDDIR/init.o (.text)
+ *(.text*)
+ } > flash
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } > flash
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } > flash
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } > sdram
+}
. = ALIGN(256);
__init_end = .;
+#ifndef CONFIG_SPL
#ifdef CONFIG_440
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
{
#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
. |= 0x10;
#endif
+#endif /* CONFIG_SPL */
__bss_start = .;
.bss (NOLOAD) :
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
+#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
+#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_USB14
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_USB138
+#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_ERRATUM_A004699
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#elif defined(CONFIG_BSC9132)
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_A_004934
+#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#elif defined(CONFIG_PPC_B4860)
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_A_004934
+#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#else
/* IF_MODE - Interface Mode Register */
#define IF_MODE_EN_AUTO 0x00008000 /* 1 - Enable automatic speed selection */
+#define IF_MODE_SETSP_100M 0x00000000 /* 00 - 100Mbps RGMII */
+#define IF_MODE_SETSP_10M 0x00002000 /* 01 - 10Mbps RGMII */
+#define IF_MODE_SETSP_1000M 0x00004000 /* 10 - 1000Mbps RGMII */
+#define IF_MODE_SETSP_MASK 0x00006000 /* setsp mask bits */
#define IF_MODE_XGMII 0x00000000 /* 00- XGMII(10) interface mode */
#define IF_MODE_GMII 0x00000002 /* 10- GMII interface mode */
#define IF_MODE_MASK 0x00000003 /* mask for mode interface mode */
#define CONFIG_SYS_MPC512x_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET)
+#define IIM_BASE_ADDR (CONFIG_SYS_IMMR + offsetof(immap_t, iim))
+
#endif /* __IMMAP_512x__ */
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
-#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
+ && !defined(CONFIG_PPC_B4420)
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
+struct dcsr_dcfg_regs {
+ u8 res_0[0x520];
+ u32 ecccr1;
+#define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
+#define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
+ u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
+};
#endif /*__IMMAP_85xx__*/
/* NOTREACHED - no way out of command loop except booting */
}
-void hang(void)
-{
- puts("### ERROR ### Please RESET the board ###\n");
- bootstage_error(BOOTSTAGE_ID_NEED_RESET);
- for (;;)
- ;
-}
-
-
#if 0 /* We could use plain global data, but the resulting code is bigger */
/*
* Pointer to initial global data area
# MA 02111-1307 USA
PLATFORM_CPPFLAGS += -DCONFIG_SANDBOX -D__SANDBOX__ -U_FORTIFY_SOURCE
-PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM
+PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM -DCONFIG_SYS_GENERIC_BOARD
PLATFORM_LIBS += -lrt
+
+# Support generic board on sandbox
+__HAVE_ARCH_GENERIC_BOARD := y
return (void *)(gd->arch.ram_buf + paddr);
}
+phys_addr_t map_to_sysmem(void *ptr)
+{
+ return (u8 *)ptr - gd->arch.ram_buf;
+}
+
void flush_dcache_range(unsigned long start, unsigned long stop)
{
}
/* Execute command if required */
if (state->cmd) {
- run_command(state->cmd, 0);
+ run_command_list(state->cmd, -1, 0);
os_exit(state->exit_type);
}
}
SB_CMDLINE_OPT_SHORT(command, 'c', 1, "Execute U-Boot command");
+static int sb_cmdline_cb_fdt(struct sandbox_state *state, const char *arg)
+{
+ state->fdt_fname = arg;
+ return 0;
+}
+SB_CMDLINE_OPT_SHORT(fdt, 'd', 1, "Specify U-Boot's control FDT");
+
int main(int argc, char *argv[])
{
struct sandbox_state *state;
* MA 02111-1307 USA
*/
+#ifndef __SANDBOX_ASM_IO_H
+#define __SANDBOX_ASM_IO_H
+
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
static inline void unmap_sysmem(const void *vaddr)
{
}
+
+/* Map from a pointer to our RAM buffer */
+phys_addr_t map_to_sysmem(void *ptr);
+
+#endif
/* The complete state of the test system */
struct sandbox_state {
const char *cmd; /* Command to execute */
+ const char *fdt_fname; /* Filename of FDT binary */
enum exit_type_id exit_type; /* How we exited U-Boot */
const char *parse_err; /* Error to report from parsing */
int argc; /* Program arguments */
#ifndef _U_BOOT_H_
#define _U_BOOT_H_ 1
-typedef struct bd_info {
- unsigned long bi_memstart; /* start of DRAM memory */
- phys_size_t bi_memsize; /* size of DRAM memory in bytes */
- unsigned long bi_flashstart; /* start of FLASH memory */
- unsigned long bi_flashsize; /* size of FLASH memory */
- unsigned long bi_flashoffset; /* reserved area for startup monitor */
- unsigned long bi_sramstart; /* start of SRAM memory */
- unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
- unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
- unsigned long bi_intfreq; /* Internal Freq, in MHz */
- unsigned long bi_busfreq; /* Bus Freq, in MHz */
- unsigned int bi_baudrate; /* Console Baudrate */
- unsigned long bi_boot_params; /* where this board expects params */
- struct /* RAM configuration */
- {
- ulong start;
- ulong size;
- } bi_dram[CONFIG_NR_DRAM_BANKS];
-} bd_t;
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_SANDBOX
LIB = $(obj)lib$(ARCH).o
-COBJS-y += board.o
COBJS-y += interrupts.o
SRCS := $(COBJS-y:.o=.c)
+++ /dev/null
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * (C) Copyright 2002-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This file was taken from ARM and changed to remove things we don't
- * need. This is most of it, so have tried to avoid being over-zealous!
- * For example, we want to have an emulation of the 'DRAM' used by
- * U-Boot.
- *
- * has been talk upstream of unifying the architectures w.r.t board.c,
- * so the less change here the better.
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <timestamp.h>
-#include <version.h>
-#include <serial.h>
-
-#include <os.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static gd_t gd_mem;
-
-/************************************************************************
- * Init Utilities *
- ************************************************************************
- * Some of this code should be moved into the core functions,
- * or dropped completely,
- * but let's get it working (again) first...
- */
-
-static int display_banner(void)
-{
- display_options();
-
- return 0;
-}
-
-/**
- * Configure and report on the DRAM configuration, which in our case is
- * fairly simple.
- */
-static int display_dram_config(void)
-{
- ulong size = 0;
- int i;
-
- debug("RAM Configuration:\n");
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-#ifdef DEBUG
- printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
- print_size(gd->bd->bi_dram[i].size, "\n");
-#endif
- size += gd->bd->bi_dram[i].size;
- }
- puts("DRAM: ");
- print_size(size, "\n");
- return 0;
-}
-
-/*
- * Breathe some life into the board...
- *
- * Initialize a serial port as console, and carry out some hardware
- * tests.
- *
- * The first part of initialization is running from Flash memory;
- * its main purpose is to initialize the RAM so that we
- * can relocate the monitor code to RAM.
- */
-
-/*
- * All attempts to come up with a "common" initialization sequence
- * that works for all boards and architectures failed: some of the
- * requirements are just _too_ different. To get rid of the resulting
- * mess of board dependent #ifdef'ed code we now make the whole
- * initialization sequence configurable to the user.
- *
- * The requirements for any new initalization function is simple: it
- * receives a pointer to the "global data" structure as it's only
- * argument, and returns an integer return code, where 0 means
- * "continue" and != 0 means "fatal error, hang the system".
- */
-typedef int (init_fnc_t) (void);
-
-void __dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = 0;
- gd->bd->bi_dram[0].size = gd->ram_size;
-}
-
-void dram_init_banksize(void)
- __attribute__((weak, alias("__dram_init_banksize")));
-
-init_fnc_t *init_sequence[] = {
-#if defined(CONFIG_ARCH_CPU_INIT)
- arch_cpu_init, /* basic arch cpu dependent setup */
-#endif
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
- board_early_init_f,
-#endif
- timer_init, /* initialize timer */
- env_init, /* initialize environment */
- serial_init, /* serial communications setup */
- console_init_f, /* stage 1 init of console */
- sandbox_early_getopt_check, /* process command line flags (err/help) */
- display_banner, /* say that we are here */
-#if defined(CONFIG_DISPLAY_CPUINFO)
- print_cpuinfo, /* display cpu info (and speed) */
-#endif
-#if defined(CONFIG_DISPLAY_BOARDINFO)
- checkboard, /* display board info */
-#endif
- dram_init, /* configure available RAM banks */
- NULL,
-};
-
-void board_init_f(ulong bootflag)
-{
- init_fnc_t **init_fnc_ptr;
- uchar *mem;
- unsigned long addr_sp, addr, size;
-
- gd = &gd_mem;
- assert(gd);
-
- memset((void *)gd, 0, sizeof(gd_t));
-
-#if defined(CONFIG_OF_EMBED)
- /* Get a pointer to the FDT */
- gd->fdt_blob = _binary_dt_dtb_start;
-#elif defined(CONFIG_OF_SEPARATE)
- /* FDT is at end of image */
- gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE);
-#endif
-
- for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
- if ((*init_fnc_ptr)() != 0)
- hang();
- }
-
- size = CONFIG_SYS_SDRAM_SIZE;
- mem = os_malloc(CONFIG_SYS_SDRAM_SIZE);
-
- assert(mem);
- gd->arch.ram_buf = mem;
- addr = (ulong)(mem + size);
-
- /*
- * reserve memory for malloc() arena
- */
- addr_sp = addr - TOTAL_MALLOC_LEN;
- debug("Reserving %dk for malloc() at: %08lx\n",
- TOTAL_MALLOC_LEN >> 10, addr_sp);
- /*
- * (permanently) allocate a Board Info struct
- * and a permanent copy of the "global" data
- */
- addr_sp -= sizeof(bd_t);
- gd->bd = (bd_t *) addr_sp;
- debug("Reserving %zu Bytes for Board Info at: %08lx\n",
- sizeof(bd_t), addr_sp);
-
- /* Ram ist board specific, so move it to board code ... */
- dram_init_banksize();
- display_dram_config(); /* and display it */
-
- /* We don't relocate, so just run the post-relocation code */
- board_init_r(NULL, 0);
-
- /* NOTREACHED - no way out of command loop except booting */
-}
-
-/************************************************************************
- *
- * This is the next part if the initialization sequence: we are now
- * running from RAM and have a "normal" C environment, i. e. global
- * data can be written, BSS has been cleared, the stack size in not
- * that critical any more, etc.
- *
- ************************************************************************
- */
-
-void board_init_r(gd_t *id, ulong dest_addr)
-{
-
- if (id)
- gd = id;
-
- gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
-
- serial_initialize();
-
-#ifdef CONFIG_POST
- post_output_backlog();
-#endif
-
- /* The Malloc area is at the top of simulated DRAM */
- mem_malloc_init((ulong)gd->arch.ram_buf + gd->ram_size -
- TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN);
-
- /* initialize environment */
- env_relocate();
-
- stdio_init(); /* get the devices list going. */
-
- jumptable_init();
-
- console_init_r(); /* fully init console as a device */
-
-#if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
- checkboard();
-#endif
-
-#if defined(CONFIG_ARCH_MISC_INIT)
- /* miscellaneous arch dependent initialisations */
- arch_misc_init();
-#endif
-#if defined(CONFIG_MISC_INIT_R)
- /* miscellaneous platform dependent initialisations */
- misc_init_r();
-#endif
-
- /* set up exceptions */
- interrupt_init();
- /* enable exceptions */
- enable_interrupts();
-
-#ifdef CONFIG_BOARD_LATE_INIT
- board_late_init();
-#endif
-
-#ifdef CONFIG_POST
- post_run(NULL, POST_RAM | post_bootmode_get(0));
-#endif
-
- sandbox_main_loop_init();
-
- /*
- * For now, run the main loop. Later we might let this be done
- * in the main program.
- */
- while (1)
- main_loop();
-
- /* NOTREACHED - no way out of command loop except booting */
-}
-
-void hang(void)
-{
- puts("### ERROR ### Please RESET the board ###\n");
- for (;;)
- ;
-}
main_loop();
}
}
-
-/***********************************************************************/
-
-void hang(void)
-{
- puts("Board ERROR\n");
- for (;;)
- ;
-}
}
-void hang(void)
-{
- puts("### ERROR ### Please RESET the board ###\n");
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
- bootstage_error(BOOTSTAGE_ID_NEED_RESET);
-#endif
- for (;;) ;
-}
-
/************************************************************************/
/* NOTREACHED - no way out of command loop except booting */
}
-
-void hang(void)
-{
- puts("### ERROR ### Please RESET the board ###\n");
- for (;;)
- ;
-}
#include <asm/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
-#include <asm/arch/mx35_pins.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx35.h>
#include <i2c.h>
#include <linux/types.h>
#include <asm/gpio.h>
static void setup_iomux_uart3(void)
{
- mxc_request_iomux(MX35_PIN_RTS2, MUX_CONFIG_ALT7);
- mxc_request_iomux(MX35_PIN_CTS2, MUX_CONFIG_ALT7);
+ static const iomux_v3_cfg_t uart3_pads[] = {
+ MX35_PAD_RTS2__UART3_RXD_MUX,
+ MX35_PAD_CTS2__UART3_TXD_MUX,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
}
+#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
+
static void setup_iomux_i2c(void)
{
- int pad;
-
- mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
-
- pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
- | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
+ static const iomux_v3_cfg_t i2c_pads[] = {
+ NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
- mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
- mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+ NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
+ };
- mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1);
- mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1);
-
- mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad);
- mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad);
+ imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
}
static void setup_iomux_spi(void)
{
- mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+ static const iomux_v3_cfg_t spi_pads[] = {
+ MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
+ MX35_PAD_CSPI1_MISO__CSPI1_MISO,
+ MX35_PAD_CSPI1_SS0__CSPI1_SS0,
+ MX35_PAD_CSPI1_SS1__CSPI1_SS1,
+ MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
}
static void setup_iomux_fec(void)
{
- /* setup pins for FEC */
- mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+ static const iomux_v3_cfg_t fec_pads[] = {
+ MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+ MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX35_PAD_FEC_COL__FEC_COL,
+ MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+ MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+ MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+ MX35_PAD_FEC_MDC__FEC_MDC,
+ MX35_PAD_FEC_MDIO__FEC_MDIO,
+ MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+ MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+ MX35_PAD_FEC_CRS__FEC_CRS,
+ MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+ MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+ MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+ MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+ MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+ MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+ };
+ /* setup pins for FEC */
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
int board_early_init_f(void)
(struct ccm_regs *)IMX_CCM_BASE;
/* setup GPIO3_1 to set HighVCore signal */
- mxc_request_iomux(MX35_PIN_ATA_DA1, MUX_CONFIG_ALT5);
+ imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
gpio_direction_output(65, 1);
/* initialize PLL and clock configuration */
* (C) Copyright 2006
* MicroSys GmbH
*
- * Copyright 2012 Stefan Roese <sr@denx.de>
+ * Copyright 2012-2013 Stefan Roese <sr@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
/* And write new value back to register */
out_be32(&mm->ipbi_ws_ctrl, val);
-#endif
- /*
- * No need to change the pin multiplexing (MPC5XXX_GPS_PORT_CONFIG)
- * as all 3 config versions (failsave level) have the same setup.
- */
+
+ /* Setup pin multiplexing */
+ if (failsavelevel == 2) {
+ /* fpga-version ok */
+#if defined(CONFIG_SYS_GPS_PORT_CONFIG_2)
+ out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_2);
+#endif
+ } else if (failsavelevel == 1) {
+ /* digiboard-version ok - fpga not */
+#if defined(CONFIG_SYS_GPS_PORT_CONFIG_1)
+ out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_1);
+#endif
+ } else {
+ /* full failsave-mode */
+#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
+ out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
+#endif
+ }
+#endif
/*
* Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-#define SPI_PAD_CTRL (PAD_CTL_HYS | \
- PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-#define WEAK_PULLUP (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_SRE_SLOW)
-#define WEAK_PULLDOWN (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_SRE_SLOW)
+#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
--- /dev/null
+#
+# DENX M53EVK
+# Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := m53evk.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * DENX M53 DRAM init values
+ * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION 2
+
+
+/* Boot Offset 0x400, valid for both SD and NAND boot. */
+BOOT_OFFSET FLASH_OFFSET_STANDARD
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */
+DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */
+DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */
+DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */
+
+DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */
+DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */
+DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */
+
+DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */
+DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */
+DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */
+
+DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */
+DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */
+DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */
+
+DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */
+DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */
+DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */
+
+DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */
+DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */
+
+DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */
+DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */
+DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */
+DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */
+
+DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */
+DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */
+
+/* ESDCTL */
+DATA 4 0x63fd9088 0x32383535
+DATA 4 0x63fd9090 0x40383538
+DATA 4 0x63fd907c 0x0136014d
+DATA 4 0x63fd9080 0x01510141
+
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd900c 0x555952e3
+DATA 4 0x63fd9010 0xb68e8b63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x092080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x09208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00001800
+DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901c 0x00000000
--- /dev/null
+/*
+ * DENX M53 module
+ *
+ * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/spl.h>
+#include <asm/errno.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <spl.h>
+#include <fsl_esdhc.h>
+#include <asm/gpio.h>
+#include <usb/ehci-fsl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ u32 size1, size2;
+
+ size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+ gd->ram_size = size1 + size2;
+
+ return 0;
+}
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
+static void setup_iomux_uart(void)
+{
+ static const iomux_v3_cfg_t uart_pads[] = {
+ MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
+ MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX5
+int board_ehci_hcd_init(int port)
+{
+ if (port == 0) {
+ /* USB OTG PWRON */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
+ gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
+
+ /* USB OTG Over Current */
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
+ } else if (port == 1) {
+ /* USB Host PWRON */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
+ gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
+
+ /* USB Host Over Current */
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
+ }
+
+ return 0;
+}
+#endif
+
+static void setup_iomux_fec(void)
+{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ /* MDIO pads */
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+
+ /* FEC 0 pads */
+ NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+
+ /* FEC 1 pads */
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg = {
+ MMC_SDHC1_BASE_ADDR,
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
+ gpio_direction_input(IMX_GPIO_NR(1, 1));
+
+ return !gpio_get_value(IMX_GPIO_NR(1, 1));
+}
+
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ MX53_PAD_EIM_DA13__GPIO3_13,
+
+ MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */
+ };
+
+ esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+
+ /* GPIO 2_31 is SD power */
+ gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+#endif
+
+#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_i2c(void)
+{
+ static const iomux_v3_cfg_t i2c_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
+}
+
+static void setup_iomux_nand(void)
+{
+ static const iomux_v3_cfg_t nand_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
+ PAD_CTL_PUS_100K_UP),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
+ PAD_CTL_PUS_100K_UP),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+}
+
+static void m53_set_clock(void)
+{
+ int ret;
+ const uint32_t ref_clk = MXC_HCLK;
+ const uint32_t dramclk = 400;
+ uint32_t cpuclk;
+
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
+ gpio_direction_input(IMX_GPIO_NR(4, 0));
+
+ /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
+ cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
+
+ ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
+ if (ret)
+ printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
+
+ ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
+ if (ret) {
+ printf("CPU: Switch peripheral clock to %dMHz failed\n",
+ dramclk);
+ }
+
+ ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
+ if (ret)
+ printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
+}
+
+static void m53_set_nand(void)
+{
+ u32 i;
+
+ /* NAND flash is muxed on ATA pins */
+ setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
+
+ /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
+ for (i = 0x4; i < 0x94; i += 0x18) {
+ clrbits_le32(WEIM_BASE_ADDR + i,
+ WEIM_GCR2_MUX16_BYP_GRANT_MASK);
+ }
+
+ mxc_set_clock(0, 33, MXC_NFC_CLK);
+ enable_nfc_clk(1);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_fec();
+ setup_iomux_i2c();
+ setup_iomux_nand();
+
+ m53_set_clock();
+
+ mxc_set_sata_internal_clock();
+
+ /* NAND clock @ 33MHz */
+ m53_set_nand();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: DENX M53EVK\n");
+
+ return 0;
+}
+
+/*
+ * NAND SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+ setup_iomux_nand();
+ m53_set_clock();
+ m53_set_nand();
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_NAND;
+}
+#endif
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
#include <asm/errno.h>
#include <netdev.h>
#include <mmc.h>
return 0;
}
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
static void setup_iomux_uart(void)
{
- /* UART4 RXD */
- mxc_request_iomux(MX53_PIN_CSI0_D13, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D13,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
- PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
- mxc_iomux_set_input(MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
-
- /* UART4 TXD */
- mxc_request_iomux(MX53_PIN_CSI0_D12, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D12,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
- PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ static const iomux_v3_cfg_t uart_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__UART4_RXD_MUX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__UART4_TXD_MUX, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
static void setup_iomux_fec(void)
{
- /*FEC_MDIO*/
- mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
- mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
-
- /*FEC_MDC*/
- mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
-
- /* FEC RXD3 */
- mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6);
- mxc_iomux_set_pad(MX53_PIN_KEY_COL0, PAD_CTL_HYS_ENABLE |
- PAD_CTL_PKE_ENABLE);
-
- /* FEC RXD2 */
- mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6);
- mxc_iomux_set_pad(MX53_PIN_KEY_COL2, PAD_CTL_HYS_ENABLE |
- PAD_CTL_PKE_ENABLE);
-
- /* FEC RXD1 */
- mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, PAD_CTL_HYS_ENABLE |
- PAD_CTL_PKE_ENABLE);
-
- /* FEC RXD0 */
- mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, PAD_CTL_HYS_ENABLE |
- PAD_CTL_PKE_ENABLE);
-
- /* FEC TXD3 */
- mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6);
- mxc_iomux_set_pad(MX53_PIN_GPIO_19, PAD_CTL_DRV_HIGH);
-
- /* FEC TXD2 */
- mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6);
- mxc_iomux_set_pad(MX53_PIN_KEY_ROW2, PAD_CTL_DRV_HIGH);
-
- /* FEC TXD1 */
- mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
-
- /* FEC TXD0 */
- mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
-
- /* FEC TX_EN */
- mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
-
- /* FEC TX_CLK */
- mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, PAD_CTL_HYS_ENABLE |
- PAD_CTL_PKE_ENABLE);
-
- /* FEC RX_ER */
- mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, PAD_CTL_HYS_ENABLE |
- PAD_CTL_PKE_ENABLE);
-
- /* FEC RX_DV */
- mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, PAD_CTL_HYS_ENABLE |
- PAD_CTL_PKE_ENABLE);
-
- /* FEC CRS */
- mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6);
- mxc_iomux_set_pad(MX53_PIN_KEY_COL3, PAD_CTL_HYS_ENABLE |
- PAD_CTL_PKE_ENABLE);
-
- /* FEC COL */
- mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6);
- mxc_iomux_set_pad(MX53_PIN_KEY_ROW1, PAD_CTL_HYS_ENABLE |
- PAD_CTL_PKE_ENABLE);
- mxc_iomux_set_input(MX53_FEC_FEC_COL_SELECT_INPUT, 0x0);
-
- /* FEC RX_CLK */
- mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6);
- mxc_iomux_set_pad(MX53_PIN_KEY_COL1, PAD_CTL_HYS_ENABLE |
- PAD_CTL_PKE_ENABLE);
- mxc_iomux_set_input(MX53_FEC_FEC_RX_CLK_SELECT_INPUT, 0x0);
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
#ifdef CONFIG_FSL_ESDHC
{
int ret;
- ret = !gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
return ret;
}
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+#define SD_CD_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_HYS | PAD_CTL_PKE)
+
int board_mmc_init(bd_t *bis)
{
- mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX53_PIN_GPIO_1,
- PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
- PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
- PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE);
- gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
-
- mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
- PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, SD_CD_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+ gpio_direction_input(IMX_GPIO_NR(1, 1));
esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
return fsl_esdhc_initialize(bis, &esdhc_cfg);
}
#endif
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)
+
static void setup_iomux_spi(void)
{
- /* SCLK */
- mxc_request_iomux(MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_input(MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x1);
- /* MOSI */
- mxc_request_iomux(MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, 0x1);
- /* MISO */
- mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, 0x1);
- /* SSEL 0 */
- mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D11), 1);
+ static const iomux_v3_cfg_t spi_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__ECSPI2_SCLK, SPI_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__ECSPI2_MISO, SPI_PAD_CTRL),
+ /* SSEL 0 */
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__GPIO5_29, SPI_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
+ gpio_direction_output(IMX_GPIO_NR(5, 29), 1);
}
int board_early_init_f(void)
#ifdef CONFIG_SYS_NAND_BASE
/*
* *I*G - NAND
- * entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so we use entry 16 for nand.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_4K, 1),
+ /*
+ * *I*G - SRIO
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for SRIO2.
+ */
+#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
+ /* *I*G* - SRIO1 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_256M, 1),
+#endif
+#ifdef CONFIG_SYS_SRIO2_MEM_PHYS
+ /* *I*G* - SRIO2 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_256M, 1),
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
COBJS-$(CONFIG_FSL_VIA) += cds_via.o
COBJS-$(CONFIG_FMAN_ENET) += fman.o
COBJS-$(CONFIG_FSL_PIXIS) += pixis.o
+ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
+endif
COBJS-$(CONFIG_FSL_QIXIS) += qixis.o
COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
+ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o
+endif
COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o
ifndef CONFIG_RAMBOOT_PBL
COBJS-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o
COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o
COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o
+ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_P1022DS) += ics307_clk.o
+endif
COBJS-$(CONFIG_P2020DS) += ics307_clk.o
COBJS-$(CONFIG_P3041DS) += ics307_clk.o
COBJS-$(CONFIG_P4080DS) += ics307_clk.o
int node;
const char *path;
int len, slot, i;
- u32 *map = NULL;
+ u32 *map = NULL, *piccells = NULL;
+ int off, cells;
node = fdt_path_offset(blob, "/aliases");
if (node >= 0) {
if (node >= 0) {
map = fdt_getprop_w(blob, node, "interrupt-map", &len);
}
+ /* Each item in "interrupt-map" property is translated with
+ * following cells:
+ * PCI #address-cells, PCI #interrupt-cells,
+ * PIC address, PIC #address-cells, PIC #interrupt-cells.
+ */
+ cells = fdt_getprop_u32_default(blob, path, "#address-cells", 1);
+ cells += fdt_getprop_u32_default(blob, path, "#interrupt-cells", 1);
+ off = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*(map+cells)));
+ if (off <= 0)
+ return;
+ cells += 1;
+ piccells = (u32 *)fdt_getprop(blob, off, "#address-cells", NULL);
+ if (piccells == NULL)
+ return;
+ cells += *piccells;
+ piccells = (u32 *)fdt_getprop(blob, off, "#interrupt-cells", NULL);
+ if (piccells == NULL)
+ return;
+ cells += *piccells;
}
}
slot = get_pci_slot();
- for (i=0;i<len;i+=7) {
+ for (i=0;i<len;i+=cells) {
/* We rotate the interrupt pins so that the mapping
* changes depending on the slot the carrier card is in.
*/
map[3] = ((map[3] + slot - 2) % 4) + 1;
- map+=7;
+ map+=cells;
}
}
}
#define ESDHC_BOOT_IMAGE_SIZE 0x48
#define ESDHC_BOOT_IMAGE_ADDR 0x50
-int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr)
+int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
{
u8 *tmp_buf;
u32 blklen, code_offset, code_len, n;
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4 0x020c4060 0x000000fb
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#define MUX_CONFIG_SSP1 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_16MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_SSP1 (MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
const iomux_cfg_t iomux_setup[] = {
/* DUART */
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/imx25-pinmux.h>
-#include <asm/arch/sys_proto.h>
+#include <asm/arch/iomux-mx25.h>
#include <asm/arch/clock.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fsl_pmic.h>
#include <mc34704.h>
-#define FEC_RESET_B IMX_GPIO_NR(2, 3)
-#define FEC_ENABLE_B IMX_GPIO_NR(4, 8)
+#define FEC_RESET_B IMX_GPIO_NR(4, 8)
+#define FEC_ENABLE_B IMX_GPIO_NR(2, 3)
#define CARD_DETECT IMX_GPIO_NR(2, 1)
DECLARE_GLOBAL_DATA_PTR;
};
#endif
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ * 0 for no pull
+ * or:
+ * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define FEC_OUT_PAD_CTRL 0
+
+#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_ODE)
+
static void mx25pdk_fec_init(void)
{
- struct iomuxc_mux_ctl *muxctl;
- struct iomuxc_pad_ctl *padctl;
- u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
- u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
-
- /* FEC pin init is generic */
- mx25_fec_init_pins();
-
- muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
- padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
- /*
- * Set up FEC_RESET_B and FEC_ENABLE_B
- *
- * FEC_RESET_B: gpio2_3 is ALT 5 mode of pin D12
- * FEC_ENABLE_B: gpio4_8 is ALT 5 mode of pin A17
- */
- writel(gpio_mux_mode, &muxctl->pad_d12);
- writel(gpio_mux_mode, &muxctl->pad_a17);
-
- writel(0x0, &padctl->pad_d12);
- writel(0x0, &padctl->pad_a17);
+ static const iomux_v3_cfg_t fec_pads[] = {
+ MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+ NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
+ MX25_PAD_FEC_MDIO__FEC_MDIO,
+ MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+ NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
+
+ NEW_PAD_CTRL(MX25_PAD_D12__GPIO_4_8, 0), /* FEC_RESET_B */
+ NEW_PAD_CTRL(MX25_PAD_A17__GPIO_2_3, 0), /* FEC_ENABLE_B */
+ };
+
+ static const iomux_v3_cfg_t i2c_pads[] = {
+ NEW_PAD_CTRL(MX25_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
/* Assert RESET and ENABLE low */
gpio_direction_output(FEC_RESET_B, 0);
gpio_set_value(FEC_ENABLE_B, 1);
/* Setup I2C pins so that PMIC can turn on PHY supply */
- writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_clk);
- writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_dat);
- writel(0x1E8, &padctl->pad_i2c1_clk);
- writel(0x1E8, &padctl->pad_i2c1_dat);
+ imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
}
int dram_init(void)
return 0;
}
+/*
+ * Set up input pins with hysteresis and 100-k pull-ups
+ */
+#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ * 0 for no pull
+ * or:
+ * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define UART1_OUT_PAD_CTRL 0
+
+static void mx25pdk_uart1_init(void)
+{
+ static const iomux_v3_cfg_t uart1_pads[] = {
+ NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
int board_early_init_f(void)
{
- mx25_uart1_init_pins();
+ mx25pdk_uart1_init();
return 0;
}
#ifdef CONFIG_FSL_ESDHC
int board_mmc_getcd(struct mmc *mmc)
{
- struct iomuxc_mux_ctl *muxctl;
- struct iomuxc_pad_ctl *padctl;
- u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
-
- /*
- * Set up the Card Detect pin.
- *
- * SD1_GPIO_CD: gpio2_1 is ALT 5 mode of pin A15
- *
- */
- muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
- padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-
- writel(gpio_mux_mode, &muxctl->pad_a15);
- writel(0x0, &padctl->pad_a15);
+ /* Set up the Card Detect pin. */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_A15__GPIO_2_1, 0));
gpio_direction_input(CARD_DETECT);
return !gpio_get_value(CARD_DETECT);
int board_mmc_init(bd_t *bis)
{
- struct iomuxc_mux_ctl *muxctl;
- u32 sdhc1_mux_mode = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
-
- muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
- writel(sdhc1_mux_mode, &muxctl->pad_sd1_cmd);
- writel(sdhc1_mux_mode, &muxctl->pad_sd1_clk);
- writel(sdhc1_mux_mode, &muxctl->pad_sd1_data0);
- writel(sdhc1_mux_mode, &muxctl->pad_sd1_data1);
- writel(sdhc1_mux_mode, &muxctl->pad_sd1_data2);
- writel(sdhc1_mux_mode, &muxctl->pad_sd1_data3);
+ static const iomux_v3_cfg_t sdhc1_pads[] = {
+ NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
-#include <asm/arch/mx35_pins.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx35.h>
#include <i2c.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}
+#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
+
static void setup_iomux_i2c(void)
{
- int pad;
+ static const iomux_v3_cfg_t i2c1_pads[] = {
+ NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
+ };
/* setup pins for I2C1 */
- mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
-
- pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
- | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
-
- mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
- mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+ imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
}
static void setup_iomux_spi(void)
{
- mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+ static const iomux_v3_cfg_t spi_pads[] = {
+ MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
+ MX35_PAD_CSPI1_MISO__CSPI1_MISO,
+ MX35_PAD_CSPI1_SS0__CSPI1_SS0,
+ MX35_PAD_CSPI1_SS1__CSPI1_SS1,
+ MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
}
+#define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
+#define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
+
static void setup_iomux_usbotg(void)
{
- int in_pad, out_pad;
+ static const iomux_v3_cfg_t usbotg_pads[] = {
+ NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
+ USBOTG_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
+ USBOTG_IN_PAD_CTRL),
+ };
/* Set up pins for USBOTG. */
- mxc_request_iomux(MX35_PIN_USBOTG_PWR,
- MUX_CONFIG_SION | MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_USBOTG_OC,
- MUX_CONFIG_SION | MUX_CONFIG_FUNC);
-
- in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
- PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
- PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
- out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
- PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
-
- mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad);
- mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad);
+ imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
}
+#define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
+
static void setup_iomux_fec(void)
{
- int pad;
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
+ NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),
+ };
/* setup pins for FEC */
- mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
-
- pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \
- PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW);
-
- mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \
- PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \
- PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \
- PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU);
- mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \
- PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \
- PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \
- PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \
- PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
int board_early_init_f(void)
if (pmic_detect()) {
p = pmic_get("FSL_PMIC");
- mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
- MUX_CONFIG_ALT1);
+ imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);
pmic_reg_read(p, REG_SETTING_0, &pmic_val);
pmic_reg_write(p, REG_SETTING_0,
pmic_reg_read(p, REG_MODE_0, &pmic_val);
pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
- mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
- mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
+ imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);
- gpio_direction_output(IMX_GPIO_NR(2, 5), 1);
+ gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
}
val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
int board_mmc_init(bd_t *bis)
{
+ static const iomux_v3_cfg_t sdhc1_pads[] = {
+ MX35_PAD_SD1_CMD__ESDHC1_CMD,
+ MX35_PAD_SD1_CLK__ESDHC1_CLK,
+ MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+ MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+ MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+ MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
+ };
+
/* configure pins for SDHC1 only */
- mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
+ imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
return fsl_esdhc_initialize(bis, &esdhc_cfg);
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx51.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
return rev;
}
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
+
static void setup_iomux_uart(void)
{
- unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
- PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
-
- mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
- mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
+ static const iomux_v3_cfg_t uart_pads[] = {
+ MX51_PAD_UART1_RXD__UART1_RXD,
+ MX51_PAD_UART1_TXD__UART1_TXD,
+ NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
static void setup_iomux_fec(void)
{
- /*FEC_MDIO*/
- mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
-
- /*FEC_MDC*/
- mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
-
- /* FEC RDATA[3] */
- mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
-
- /* FEC RDATA[2] */
- mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
-
- /* FEC RDATA[1] */
- mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
-
- /* FEC RDATA[0] */
- mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
-
- /* FEC TDATA[3] */
- mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
-
- /* FEC TDATA[2] */
- mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
-
- /* FEC TDATA[1] */
- mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
-
- /* FEC TDATA[0] */
- mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
-
- /* FEC TX_EN */
- mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
-
- /* FEC TX_ER */
- mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
-
- /* FEC TX_CLK */
- mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
-
- /* FEC TX_COL */
- mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
-
- /* FEC RX_CLK */
- mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
-
- /* FEC RX_CRS */
- mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
-
- /* FEC RX_ER */
- mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
-
- /* FEC RX_DV */
- mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ MX51_PAD_NANDF_CS3__FEC_MDC,
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
+ NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
+ MX51_PAD_NANDF_D9__FEC_RDATA0,
+ MX51_PAD_NANDF_CS6__FEC_TDATA3,
+ MX51_PAD_NANDF_CS5__FEC_TDATA2,
+ MX51_PAD_NANDF_CS4__FEC_TDATA1,
+ MX51_PAD_NANDF_D8__FEC_TDATA0,
+ MX51_PAD_NANDF_CS7__FEC_TX_EN,
+ MX51_PAD_NANDF_CS2__FEC_TX_ER,
+ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
+ NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
+ NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
+ MX51_PAD_EIM_CS5__FEC_CRS,
+ MX51_PAD_EIM_CS4__FEC_RX_ER,
+ NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
#ifdef CONFIG_MXC_SPI
static void setup_iomux_spi(void)
{
- /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
- mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
-
- /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
-
- /* de-select SS1 of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
-
- /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
- mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
-
- /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
-
- /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
+ static const iomux_v3_cfg_t spi_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
+ MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
}
#endif
#ifdef CONFIG_USB_EHCI_MX5
-#define MX51EVK_USBH1_HUB_RST IOMUX_TO_GPIO(MX51_PIN_GPIO1_7) /* GPIO1_7 */
-#define MX51EVK_USBH1_STP IOMUX_TO_GPIO(MX51_PIN_USBH1_STP) /* GPIO1_27 */
-#define MX51EVK_USB_CLK_EN_B IOMUX_TO_GPIO(MX51_PIN_EIM_D18) /* GPIO2_1 */
-#define MX51EVK_USB_PHY_RESET IOMUX_TO_GPIO(MX51_PIN_EIM_D21) /* GPIO2_5 */
-
-#define USBH1_PAD (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | \
- PAD_CTL_100K_PU | PAD_CTL_PUE_PULL | \
- PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE)
-#define GPIO_PAD (PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE | \
- PAD_CTL_SRE_FAST)
-#define NO_PAD (1 << 16)
+#define MX51EVK_USBH1_HUB_RST IMX_GPIO_NR(1, 7)
+#define MX51EVK_USBH1_STP IMX_GPIO_NR(1, 27)
+#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 2)
+#define MX51EVK_USB_PHY_RESET IMX_GPIO_NR(2, 5)
static void setup_usb_h1(void)
{
- setup_iomux_usb_h1();
-
- /* GPIO_1_7 for USBH1 hub reset */
- mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_7, NO_PAD);
-
- /* GPIO_2_1 */
- mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_EIM_D17, GPIO_PAD);
-
- /* GPIO_2_5 for USB PHY reset */
- mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_EIM_D21, GPIO_PAD);
+ static const iomux_v3_cfg_t usb_h1_pads[] = {
+ MX51_PAD_USBH1_CLK__USBH1_CLK,
+ MX51_PAD_USBH1_DIR__USBH1_DIR,
+ MX51_PAD_USBH1_STP__USBH1_STP,
+ MX51_PAD_USBH1_NXT__USBH1_NXT,
+ MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+ MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+ MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+ MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+ MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+ MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+ MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+ MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */
+ MX51_PAD_EIM_D17__GPIO2_1,
+ MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */
+ };
+
+ imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
}
int board_ehci_hcd_init(int port)
{
/* Set USBH1_STP to GPIO and toggle it */
- mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27,
+ MX51_USBH_PAD_CTRL));
gpio_direction_output(MX51EVK_USBH1_STP, 0);
gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
gpio_set_value(MX51EVK_USBH1_STP, 1);
/* Set back USBH1_STP to be function */
- mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
+ imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);
/* De-assert USB PHY RESETB */
gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
VVIDEOEN | VAUDIOEN | VSDEN;
pmic_reg_write(p, REG_MODE_1, val);
- mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
+ NO_PAD_CTRL));
gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
udelay(500);
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret;
- mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1);
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
+ NO_PAD_CTRL));
gpio_direction_input(IMX_GPIO_NR(1, 0));
- mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
+ NO_PAD_CTRL));
gpio_direction_input(IMX_GPIO_NR(1, 6));
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
int board_mmc_init(bd_t *bis)
{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
+ };
+
+ static const iomux_v3_cfg_t sd2_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD,
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK,
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0,
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1,
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2,
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3,
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
+ };
+
u32 index;
s32 status = 0;
index++) {
switch (index) {
case 0:
- mxc_request_iomux(MX51_PIN_SD1_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA0,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA1,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA2,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA3,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_GPIO1_0,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
- PAD_CTL_HYS_ENABLE);
- mxc_request_iomux(MX51_PIN_GPIO1_1,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
- PAD_CTL_HYS_ENABLE);
+ imx_iomux_v3_setup_multiple_pads(sd1_pads,
+ ARRAY_SIZE(sd1_pads));
break;
case 1:
- mxc_request_iomux(MX51_PIN_SD2_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD2_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD2_DATA0,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_SD2_DATA1,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_SD2_DATA2,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_SD2_DATA3,
- IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_SD2_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_GPIO1_6,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
- PAD_CTL_HYS_ENABLE);
- mxc_request_iomux(MX51_PIN_GPIO1_5,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
- PAD_CTL_HYS_ENABLE);
+ imx_iomux_v3_setup_multiple_pads(sd2_pads,
+ ARRAY_SIZE(sd2_pads));
break;
default:
printf("Warning: you configured more ESDHC controller"
#include <common.h>
#include <linux/list.h>
#include <asm/gpio.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx51.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
void setup_iomux_lcd(void)
{
/* DI2_PIN15 */
- mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT4);
+ imx_iomux_v3_setup_pad(MX51_PAD_DI_GP4__DI2_PIN15);
- /* Pad settings for MX51_PIN_DI2_DISP_CLK */
- mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, PAD_CTL_HYS_NONE |
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_MAX | PAD_CTL_SRE_SLOW);
+ /* Pad settings for DI2_DISP_CLK */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK,
+ PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW));
/* Turn on 3.3V voltage for LCD */
- mxc_request_iomux(MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT3);
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D12__GPIO4_9,
+ NO_PAD_CTRL));
gpio_direction_output(MX51EVK_LCD_3V3, 1);
/* Turn on 5V voltage for LCD */
- mxc_request_iomux(MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT3);
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D13__GPIO4_10,
+ NO_PAD_CTRL));
gpio_direction_output(MX51EVK_LCD_5V, 1);
/* Turn on GPIO backlight */
- mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
- mxc_iomux_set_input(MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
- INPUT_CTL_PATH1);
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4,
+ NO_PAD_CTRL));
gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1);
}
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
#include <asm/errno.h>
#include <netdev.h>
#include <mmc.h>
#ifdef CONFIG_NAND_MXC
static void setup_iomux_nand(void)
{
+ static const iomux_v3_cfg_t nand_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
+ PAD_CTL_PUS_100K_UP),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
+ PAD_CTL_PUS_100K_UP),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ };
+
u32 i, reg;
- #define M4IF_GENP_WEIM_MM_MASK 0x00000001
- #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
reg &= ~M4IF_GENP_WEIM_MM_MASK;
__raw_writel(reg, WEIM_BASE_ADDR + i);
}
- mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH);
- mxc_request_iomux(MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_NANDF_CS1, PAD_CTL_DRV_HIGH);
- mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PKE_ENABLE |
- PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
- mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH);
- mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH);
- mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PKE_ENABLE |
- PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
- mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH);
- mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH);
- mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_DA0, PAD_CTL_PKE_ENABLE |
- PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
- mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_DA1, PAD_CTL_PKE_ENABLE |
- PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
- mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_DA2, PAD_CTL_PKE_ENABLE |
- PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
- mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_DA3, PAD_CTL_PKE_ENABLE |
- PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
- mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_DA4, PAD_CTL_PKE_ENABLE |
- PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
- mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_DA5, PAD_CTL_PKE_ENABLE |
- PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
- mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_DA6, PAD_CTL_PKE_ENABLE |
- PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
- mxc_request_iomux(MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_DA7, PAD_CTL_PKE_ENABLE |
- PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
}
#else
static void setup_iomux_nand(void)
}
#endif
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
static void setup_iomux_uart(void)
{
- /* UART1 RXD */
- mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX53_PIN_ATA_DMACK,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
- mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
-
- /* UART1 TXD */
- mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX53_PIN_ATA_DIOW,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ static const iomux_v3_cfg_t uart_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret;
- mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
gpio_direction_input(IMX_GPIO_NR(1, 1));
- mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1);
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4);
gpio_direction_input(IMX_GPIO_NR(1, 4));
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
return ret;
}
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
int board_mmc_init(bd_t *bis)
{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_CLK_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ };
+
+ static const iomux_v3_cfg_t sd2_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_CLK_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7, SD_PAD_CTRL),
+ };
+
u32 index;
s32 status = 0;
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
switch (index) {
case 0:
- mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA0,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA1,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA2,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA3,
- IOMUX_CONFIG_ALT0);
-
- mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
- mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
+ imx_iomux_v3_setup_multiple_pads(sd1_pads,
+ ARRAY_SIZE(sd1_pads));
break;
case 1:
- mxc_request_iomux(MX53_PIN_SD2_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX53_PIN_SD2_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX53_PIN_SD2_DATA0,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD2_DATA1,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD2_DATA2,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD2_DATA3,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_ATA_DATA12,
- IOMUX_CONFIG_ALT2);
- mxc_request_iomux(MX53_PIN_ATA_DATA13,
- IOMUX_CONFIG_ALT2);
- mxc_request_iomux(MX53_PIN_ATA_DATA14,
- IOMUX_CONFIG_ALT2);
- mxc_request_iomux(MX53_PIN_ATA_DATA15,
- IOMUX_CONFIG_ALT2);
-
- mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4);
- mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4);
- mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4);
+ imx_iomux_v3_setup_multiple_pads(sd2_pads,
+ ARRAY_SIZE(sd2_pads));
break;
default:
printf("Warning: you configured more ESDHC controller"
static void weim_smc911x_iomux(void)
{
+ static const iomux_v3_cfg_t weim_smc911x_pads[] = {
+ /* Data bus */
+ NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+
+ /* Address lines */
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+
+ /* other EIM signals for ethernet */
+ MX53_PAD_EIM_OE__EMI_WEIM_OE,
+ MX53_PAD_EIM_RW__EMI_WEIM_RW,
+ MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
+ };
+
/* ETHERNET_INT as GPIO2_31 */
- mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
+ imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31);
gpio_direction_input(ETHERNET_INT);
- /* Data bus */
- mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_D25, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_D26, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_D27, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4);
-
- /* Address lines */
- mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4);
-
- mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4);
-
- /* other EIM signals for ethernet */
- mxc_request_iomux(MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_EIM_CS1, IOMUX_CONFIG_ALT0);
+ /* WEIM bus */
+ imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads,
+ ARRAY_SIZE(weim_smc911x_pads));
}
static void weim_cs1_settings(void)
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
#include <asm/errno.h>
#include <asm/imx-common/boot_mode.h>
#include <netdev.h>
return 0;
}
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
static void setup_iomux_uart(void)
{
- /* UART1 RXD */
- mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
- mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
-
- /* UART1 TXD */
- mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ static const iomux_v3_cfg_t uart_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
+#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_HYS | PAD_CTL_ODE)
+
static void setup_i2c(unsigned int port_number)
{
+ static const iomux_v3_cfg_t i2c1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
+ };
+
+ static const iomux_v3_cfg_t i2c2_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL),
+ };
+
switch (port_number) {
case 0:
- /* i2c1 SDA */
- mxc_request_iomux(MX53_PIN_CSI0_D8,
- IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
- mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
- INPUT_CTL_PATH0);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
- PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
- PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
- /* i2c1 SCL */
- mxc_request_iomux(MX53_PIN_CSI0_D9,
- IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
- mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
- INPUT_CTL_PATH0);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
- PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
- PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ imx_iomux_v3_setup_multiple_pads(i2c1_pads,
+ ARRAY_SIZE(i2c1_pads));
break;
case 1:
- /* i2c2 SDA */
- mxc_request_iomux(MX53_PIN_KEY_ROW3,
- IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
- mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
- INPUT_CTL_PATH0);
- mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
- PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
- PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
-
- /* i2c2 SCL */
- mxc_request_iomux(MX53_PIN_KEY_COL3,
- IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
- mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
- INPUT_CTL_PATH0);
- mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
- PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
- PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ imx_iomux_v3_setup_multiple_pads(i2c2_pads,
+ ARRAY_SIZE(i2c2_pads));
break;
default:
printf("Warning: Wrong I2C port number\n");
static void setup_iomux_fec(void)
{
- /*FEC_MDIO*/
- mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
- mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
-
- /*FEC_MDC*/
- mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
-
- /* FEC RXD1 */
- mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* FEC RXD0 */
- mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* FEC TXD1 */
- mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
-
- /* FEC TXD0 */
- mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
-
- /* FEC TX_EN */
- mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
-
- /* FEC TX_CLK */
- mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* FEC RX_ER */
- mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* FEC CRS */
- mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret;
- mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
+ imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
gpio_direction_input(IMX_GPIO_NR(3, 11));
- mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
+ imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
gpio_direction_input(IMX_GPIO_NR(3, 13));
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
return ret;
}
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
int board_mmc_init(bd_t *bis)
{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ MX53_PAD_EIM_DA13__GPIO3_13,
+ };
+
+ static const iomux_v3_cfg_t sd2_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+ SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
+ MX53_PAD_EIM_DA11__GPIO3_11,
+ };
+
u32 index;
s32 status = 0;
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
switch (index) {
case 0:
- mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA0,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA1,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA2,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA3,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_EIM_DA13,
- IOMUX_CONFIG_ALT1);
-
- mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ imx_iomux_v3_setup_multiple_pads(sd1_pads,
+ ARRAY_SIZE(sd1_pads));
break;
case 1:
- mxc_request_iomux(MX53_PIN_ATA_RESET_B,
- IOMUX_CONFIG_ALT2);
- mxc_request_iomux(MX53_PIN_ATA_IORDY,
- IOMUX_CONFIG_ALT2);
- mxc_request_iomux(MX53_PIN_ATA_DATA8,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA9,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA10,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA11,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA0,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA1,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA2,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA3,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_EIM_DA11,
- IOMUX_CONFIG_ALT1);
-
- mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-
+ imx_iomux_v3_setup_multiple_pads(sd2_pads,
+ ARRAY_SIZE(sd2_pads));
break;
default:
printf("Warning: you configured more ESDHC controller"
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
#include <asm/arch/clock.h>
#include <asm/errno.h>
#include <asm/imx-common/mx5_video.h>
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
}
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
static void setup_iomux_uart(void)
{
- /* UART1 RXD */
- mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
- mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
-
- /* UART1 TXD */
- mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ static const iomux_v3_cfg_t uart_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
#ifdef CONFIG_USB_EHCI_MX5
int board_ehci_hcd_init(int port)
{
/* request VBUS power enable pin, GPIO7_8 */
- mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
- gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
+ imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
+ gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
return 0;
}
#endif
static void setup_iomux_fec(void)
{
- /*FEC_MDIO*/
- mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
- mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
-
- /*FEC_MDC*/
- mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
-
- /* FEC RXD1 */
- mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* FEC RXD0 */
- mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* FEC TXD1 */
- mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
-
- /* FEC TXD0 */
- mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
-
- /* FEC TX_EN */
- mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
-
- /* FEC TX_CLK */
- mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* FEC RX_ER */
- mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* FEC CRS */
- mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret;
- mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
+ imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
gpio_direction_input(IMX_GPIO_NR(3, 11));
- mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
+ imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
gpio_direction_input(IMX_GPIO_NR(3, 13));
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
return ret;
}
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
int board_mmc_init(bd_t *bis)
{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ MX53_PAD_EIM_DA13__GPIO3_13,
+ };
+
+ static const iomux_v3_cfg_t sd2_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+ SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
+ MX53_PAD_EIM_DA11__GPIO3_11,
+ };
+
u32 index;
s32 status = 0;
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
switch (index) {
case 0:
- mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA0,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA1,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA2,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA3,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_EIM_DA13,
- IOMUX_CONFIG_ALT1);
-
- mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ imx_iomux_v3_setup_multiple_pads(sd1_pads,
+ ARRAY_SIZE(sd1_pads));
break;
case 1:
- mxc_request_iomux(MX53_PIN_ATA_RESET_B,
- IOMUX_CONFIG_ALT2);
- mxc_request_iomux(MX53_PIN_ATA_IORDY,
- IOMUX_CONFIG_ALT2);
- mxc_request_iomux(MX53_PIN_ATA_DATA8,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA9,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA10,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA11,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA0,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA1,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA2,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_ATA_DATA3,
- IOMUX_CONFIG_ALT4);
- mxc_request_iomux(MX53_PIN_EIM_DA11,
- IOMUX_CONFIG_ALT1);
-
- mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-
+ imx_iomux_v3_setup_multiple_pads(sd2_pads,
+ ARRAY_SIZE(sd2_pads));
break;
default:
printf("Warning: you configured more ESDHC controller"
}
#endif
+#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
static void setup_iomux_i2c(void)
{
- /* I2C1 SDA */
- mxc_request_iomux(MX53_PIN_CSI0_D8,
- IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
- mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
- INPUT_CTL_PATH0);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
- PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
- PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
- PAD_CTL_PUE_PULL |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
- /* I2C1 SCL */
- mxc_request_iomux(MX53_PIN_CSI0_D9,
- IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
- mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
- INPUT_CTL_PATH0);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
- PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
- PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
- PAD_CTL_PUE_PULL |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ static const iomux_v3_cfg_t i2c1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
}
static int power_init(void)
#include <common.h>
#include <linux/list.h>
#include <asm/gpio.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
void setup_iomux_lcd(void)
{
- mxc_request_iomux(MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DI0_PIN15, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DI0_PIN2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DI0_PIN3, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT0, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT1, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT3, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT4, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT5, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT6, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT7, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT10, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT11, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT12, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT13, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT14, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT15, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT16, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT17, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT18, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT19, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT20, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT21, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT22, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_DISP0_DAT23, IOMUX_CONFIG_ALT0);
+ static const iomux_v3_cfg_t lcd_pads[] = {
+ MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
+ MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
+ MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
+ MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
+ MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
+ MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
+ MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
+ MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
+ MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
+ MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
+ MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
+ MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
+ MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
+ MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
+ MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
+ MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
+ MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
+ MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
+ MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
+ MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
+ MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
+ MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
+ MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
+ MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
+ MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
+ MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
+ MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
+ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
/* Turn on GPIO backlight */
- mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT1);
+ imx_iomux_v3_setup_pad(MX53_PAD_EIM_D24__GPIO3_24);
gpio_direction_output(MX53LOCO_LCD_POWER, 1);
/* Turn on display contrast */
- mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
- gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 1);
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
+ gpio_direction_output(IMX_GPIO_NR(1, 1), 1);
}
int board_video_skip(void)
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
#include <asm/errno.h>
#include <netdev.h>
#include <mmc.h>
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
static void setup_iomux_uart(void)
{
- /* UART1 RXD */
- mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
- mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
-
- /* UART1 TXD */
- mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ static const iomux_v3_cfg_t uart_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
static void setup_iomux_fec(void)
{
- /*FEC_MDIO*/
- mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
- mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
-
- /*FEC_MDC*/
- mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
-
- /* FEC RXD1 */
- mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* FEC RXD0 */
- mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* FEC TXD1 */
- mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
-
- /* FEC TXD0 */
- mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
-
- /* FEC TX_EN */
- mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
-
- /* FEC TX_CLK */
- mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* FEC RX_ER */
- mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* FEC CRS */
- mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
#ifdef CONFIG_FSL_ESDHC
int board_mmc_getcd(struct mmc *mmc)
{
- mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
+ imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
gpio_direction_input(IMX_GPIO_NR(3, 13));
return !gpio_get_value(IMX_GPIO_NR(3, 13));
}
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
int board_mmc_init(bd_t *bis)
{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ MX53_PAD_EIM_DA13__GPIO3_13,
+ };
+
u32 index;
s32 status = 0;
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
switch (index) {
case 0:
- mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA0,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA1,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA2,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA3,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_EIM_DA13,
- IOMUX_CONFIG_ALT1);
-
- mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ imx_iomux_v3_setup_multiple_pads(sd1_pads,
+ ARRAY_SIZE(sd1_pads));
break;
default:
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
int dram_init(void)
{
* i.MX6Q ARD RevB: 0x02
*/
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- int reg = readl(&ocotp->gp1);
+ struct fuse_bank *bank = &ocotp->bank[4];
+ struct fuse_bank4_regs *fuse =
+ (struct fuse_bank4_regs *)bank->fuse_regs;
+ int reg = readl(&fuse->gp1);
int ret;
switch (reg >> 8 & 0x0F) {
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-#define SPI_PAD_CTRL (PAD_CTL_HYS | \
- PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
int dram_init(void)
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
int dram_init(void)
{
int board_mmc_init(bd_t *bis)
{
+ s32 status = 0;
int i;
/*
break;
default:
printf("Warning: you configured more USDHC controllers"
- "(%d) than supported by the board\n", i + 1);
- return 0;
- }
+ "(%d) then supported by the board (%d)\n",
+ i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return status;
+ }
- if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
- printf("Warning: failed to initialize mmc dev %d\n", i);
+ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
}
- return 0;
+ return status;
}
#endif
--- /dev/null
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := mx6slevk.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x020c4018 0x00260324
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020e0344 0x00003030
+DATA 4 0x020e0348 0x00003030
+DATA 4 0x020e034c 0x00003030
+DATA 4 0x020e0350 0x00003030
+DATA 4 0x020e030c 0x00000030
+DATA 4 0x020e0310 0x00000030
+DATA 4 0x020e0314 0x00000030
+DATA 4 0x020e0318 0x00000030
+DATA 4 0x020e0300 0x00000030
+DATA 4 0x020e031c 0x00000030
+DATA 4 0x020e0338 0x00000028
+DATA 4 0x020e0320 0x00000030
+DATA 4 0x020e032c 0x00000000
+DATA 4 0x020e033c 0x00000008
+DATA 4 0x020e0340 0x00000008
+DATA 4 0x020e05c4 0x00000030
+DATA 4 0x020e05cc 0x00000030
+DATA 4 0x020e05d4 0x00000030
+DATA 4 0x020e05d8 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05c8 0x00000030
+DATA 4 0x020e05b0 0x00020000
+DATA 4 0x020e05b4 0x00000000
+DATA 4 0x020e05c0 0x00020000
+DATA 4 0x020e05d0 0x00080000
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b085c 0x1b4700c7
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b0890 0x00300000
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b082c 0xf3333333
+DATA 4 0x021b0830 0xf3333333
+DATA 4 0x021b0834 0xf3333333
+DATA 4 0x021b0838 0xf3333333
+DATA 4 0x021b0848 0x4241444a
+DATA 4 0x021b0850 0x3030312b
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x00000000
+DATA 4 0x021b08c0 0x24911492
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b000c 0x33374133
+DATA 4 0x021b0004 0x00020024
+DATA 4 0x021b0010 0x00100A82
+DATA 4 0x021b0014 0x00000093
+DATA 4 0x021b0018 0x00001688
+DATA 4 0x021b002c 0x0f9f26d2
+DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0038 0x00190778
+DATA 4 0x021b0008 0x00000000
+DATA 4 0x021b0040 0x0000004f
+DATA 4 0x021b0000 0xc3110000
+DATA 4 0x021b001c 0x003f8030
+DATA 4 0x021b001c 0xff0a8030
+DATA 4 0x021b001c 0x82018030
+DATA 4 0x021b001c 0x04028030
+DATA 4 0x021b001c 0x02038030
+DATA 4 0x021b001c 0xff0a8038
+DATA 4 0x021b001c 0x82018038
+DATA 4 0x021b001c 0x04028038
+DATA 4 0x021b001c 0x02038038
+DATA 4 0x021b0800 0xa1310003
+DATA 4 0x021b0020 0x00001800
+DATA 4 0x021b0818 0x00000000
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b0004 0x00025564
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
--- /dev/null
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <asm/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1; /* Assume boot SD always present */
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+ puts("Board: MX6SLEVK\n");
+
+ return 0;
+}
int nodeoff = 0;
while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
- "fsl,flexcan-v1.0")) >= 0) {
+ "fsl,p1010-flexcan")) >= 0) {
fdt_del_node(blob, nodeoff);
}
}
LIB = $(obj)lib$(BOARD).o
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-y += spl_minimal.o tlb.o law.o
+
+else
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o
COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
+endif
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);
--- /dev/null
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+void sdram_init(void)
+{
+ volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+
+ __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+ __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+ __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
+ __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
+#endif
+ __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
+
+ __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
+ __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
+ __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
+
+ __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
+ __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+ __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
+
+ __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
+ __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+ __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
+
+ /* Set, but do not enable the memory */
+ __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN,
+ &ddr->sdram_cfg);
+
+ in_be32(&ddr->sdram_cfg);
+ udelay(500);
+
+ /* Let the controller go */
+ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+ in_be32(&ddr->sdram_cfg);
+
+ set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
+}
+
+const static u32 sysclk_tbl[] = {
+ 66666000, 7499900, 83332500, 8999900,
+ 99999000, 11111000, 12499800, 13333200
+};
+
+void board_init_f(ulong bootflag)
+{
+ int px_spd;
+ u32 plat_ratio, sys_clk, bus_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* for FPGA */
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+
+ /* initialize selected port with appropriate baud rate */
+ px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
+ sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ bus_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* Initialize the DDR3 */
+ sdram_init();
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0,
+ CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
+#ifndef CONFIG_SPL_BUILD
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_4K, 1),
-#ifdef CONFIG_SYS_RAMBOOT
- /* *I*G - eSDHC/eSPI/NAND boot */
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+ /* **** - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1),
-
- /* map the second 1G */
+ /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_1G, 1),
#endif
-#
+
+#ifdef CONFIG_SYS_NAND_BASE
+ /* *I*G - NAND */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16K, 1),
+#endif
+
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
#define GPIO_SLIC_PIN 30
#define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
+#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
+#define GPIO_DDR_RST_PORT 1
+#define GPIO_DDR_RST_PIN 8
+#define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
+
+#define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
+#endif
#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
#define PCA_IOPORT_I2C_ADDR 0x23
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* GPIO */
{1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
-#if 0
+#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
{1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
#endif
{0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
+#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
+ /* reset DDR3 */
+ setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
+ udelay(1000);
+ clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
+ udelay(1000);
+ setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
+ /* disable CE_PB8 */
+ clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
+#endif
/* Enable VSC7385 switch */
setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
{
phys_addr_t base;
phys_size_t size;
+ const char *soc_usb_compat = "fsl-usb2-dr";
+ int err, usb1_off, usb2_off;
ft_cpu_setup(blob, bd);
#if defined(CONFIG_HAS_FSL_DR_USB)
fdt_fixup_dr_usb(blob, bd);
#endif
+
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+ /* Delete eLBC node as it is muxed with USB2 controller */
+ if (hwconfig("usb2")) {
+ const char *soc_elbc_compat = "fsl,p1020-elbc";
+ int off = fdt_node_offset_by_compatible(blob, -1,
+ soc_elbc_compat);
+ if (off < 0) {
+ printf("WARNING: could not find compatible node %s: %s.\n",
+ soc_elbc_compat,
+ fdt_strerror(off));
+ return;
+ }
+ err = fdt_del_node(blob, off);
+ if (err < 0) {
+ printf("WARNING: could not remove %s: %s.\n",
+ soc_elbc_compat, fdt_strerror(err));
+ }
+ return;
+ }
+#endif
+
+/* Delete USB2 node as it is muxed with eLBC */
+ usb1_off = fdt_node_offset_by_compatible(blob, -1,
+ soc_usb_compat);
+ if (usb1_off < 0) {
+ printf("WARNING: could not find compatible node %s: %s.\n",
+ soc_usb_compat,
+ fdt_strerror(usb1_off));
+ return;
+ }
+ usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
+ soc_usb_compat);
+ if (usb2_off < 0) {
+ printf("WARNING: could not find compatible node %s: %s.\n",
+ soc_usb_compat,
+ fdt_strerror(usb2_off));
+ return;
+ }
+ err = fdt_del_node(blob, usb2_off);
+ if (err < 0) {
+ printf("WARNING: could not remove %s: %s.\n",
+ soc_usb_compat, fdt_strerror(err));
+ }
+
}
#endif
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#ifndef CONFIG_QE
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+#elif defined(CONFIG_P1021RDB)
+ par_io_t *par_io = (par_io_t *)&(gur->qe_par_io);
#endif
/* initialize selected port with appropriate baud rate */
__raw_writel(0x00200000, &pgpio->gpdat);
udelay(1000);
__raw_writel(0x00000000, &pgpio->gpdir);
+#elif defined(CONFIG_P1021RDB)
+ /* init DDR3 reset signal CE_PB8 */
+ out_be32(&par_io[1].cpdir1, 0x00004000);
+ out_be32(&par_io[1].cpodr, 0x00800000);
+ out_be32(&par_io[1].cppar1, 0x00000000);
+ /* reset DDR3 */
+ out_be32(&par_io[1].cpdat, 0x00800000);
+ udelay(1000);
+ out_be32(&par_io[1].cpdat, 0x00000000);
+ udelay(1000);
+ out_be32(&par_io[1].cpdat, 0x00800000);
+ /* disable the CE_PB8 */
+ out_be32(&par_io[1].cpdir1, 0x00000000);
#endif
#ifndef CONFIG_SYS_INIT_L2_ADDR
--- /dev/null
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := titanium.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Projectiondesign AS
+ * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * sd, nand
+ */
+BOOT_FROM nand
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+
+/* (differential input) */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+/* disable ddr pullups */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+/* (differential input) */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+
+/* Read data DQ Byte0-3 delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/*
+ * MDMISC mirroring interleaved (row/bank/col)
+ */
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
+
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
--- /dev/null
+/*
+ * Copyright (C) 2013 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6q_pins.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/boot_mode.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart4_pads[] = {
+ MX6_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+struct i2c_pads_info i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 | PC,
+ .gp = IMX_GPIO_NR(5, 27)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 | PC,
+ .gp = IMX_GPIO_NR(5, 26)
+ }
+};
+
+struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
+ .gp = IMX_GPIO_NR(7, 11)
+ }
+};
+
+iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const enet_pads1[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* pin 35 - 1 (PHY_AD2) on reset */
+ MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 32 - 1 - (MODE0) all */
+ MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 31 - 1 - (MODE1) all */
+ MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 28 - 1 - (MODE2) all */
+ MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 27 - 1 - (MODE3) all */
+ MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+ MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 42 PHY nRST */
+ MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads2[] = {
+ MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+iomux_v3_cfg_t nfc_pads[] = {
+ MX6_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ imx_iomux_v3_setup_multiple_pads(nfc_pads,
+ ARRAY_SIZE(nfc_pads));
+
+ /* config gpmi and bch clock to 100 MHz */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+ /* enable gpmi and bch clock gating */
+ setbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+
+static void setup_iomux_enet(void)
+{
+ gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+ gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
+ imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+ gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
+
+ /* Need delay 10ms according to KSZ9021 spec */
+ udelay(1000 * 10);
+ gpio_set_value(IMX_GPIO_NR(3, 23), 1);
+
+ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+}
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+ return 0;
+}
+
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ { USDHC3_BASE_ADDR },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
+ gpio_direction_input(IMX_GPIO_NR(7, 0));
+ return !gpio_get_value(IMX_GPIO_NR(7, 0));
+ }
+
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ /*
+ * Only one USDHC controller on titianium
+ */
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* min rx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
+ /* min tx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
+ /* max rx/tx clock delay, min rx/tx control */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+
+ setup_iomux_enet();
+
+ ret = cpu_eth_init(bis);
+ if (ret)
+ printf("FEC MXC: %s:failed\n", __func__);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+ setup_gpmi_nand();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Titanium\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* NAND */
+ { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
+ /* 4 bit bus width */
+ { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
+ { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
+ { NULL, 0 },
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ return 0;
+}
#include <usb.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx51.h>
#include <asm/gpio.h>
#include <usb/ehci-fsl.h>
#include <usb/ulpi.h>
#include "../../../drivers/usb/host/ehci.h"
-/* USB pin configuration */
-#define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
- PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
-
/*
* Configure the USB H1 and USB H2 IOMUX
*/
void setup_iomux_usb(void)
{
- setup_iomux_usb_h1();
-
- if (machine_is_efikasb())
- setup_iomux_usb_h2();
-
- /* USB PHY reset */
- mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE |
- PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
-
- /* USB HUB reset */
- mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE |
- PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
-
- /* WIFI EN (act low) */
- mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0);
- /* WIFI RESET */
- mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0);
- /* BT EN (act low) */
- mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0);
+ static const iomux_v3_cfg_t usb_h1_pads[] = {
+ MX51_PAD_USBH1_CLK__USBH1_CLK,
+ MX51_PAD_USBH1_DIR__USBH1_DIR,
+ MX51_PAD_USBH1_STP__USBH1_STP,
+ MX51_PAD_USBH1_NXT__USBH1_NXT,
+ MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+ MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+ MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+ MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+ MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+ MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+ MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+ MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+ };
+
+ static const iomux_v3_cfg_t usb_pads[] = {
+ MX51_PAD_EIM_D27__GPIO2_9, /* USB PHY reset */
+ MX51_PAD_GPIO1_5__GPIO1_5, /* USB HUB reset */
+ NEW_PAD_CTRL(MX51_PAD_EIM_A22__GPIO2_16, 0), /* WIFI /EN */
+ NEW_PAD_CTRL(MX51_PAD_EIM_A16__GPIO2_10, 0), /* WIFI RESET */
+ NEW_PAD_CTRL(MX51_PAD_EIM_A17__GPIO2_11, 0), /* BT /EN */
+ };
+
+ imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
+
+ if (machine_is_efikasb()) {
+ static const iomux_v3_cfg_t usb_h2_pads[] = {
+ MX51_PAD_EIM_A24__USBH2_CLK,
+ MX51_PAD_EIM_A25__USBH2_DIR,
+ MX51_PAD_EIM_A26__USBH2_STP,
+ MX51_PAD_EIM_A27__USBH2_NXT,
+ MX51_PAD_EIM_D16__USBH2_DATA0,
+ MX51_PAD_EIM_D17__USBH2_DATA1,
+ MX51_PAD_EIM_D18__USBH2_DATA2,
+ MX51_PAD_EIM_D19__USBH2_DATA3,
+ MX51_PAD_EIM_D20__USBH2_DATA4,
+ MX51_PAD_EIM_D21__USBH2_DATA5,
+ MX51_PAD_EIM_D22__USBH2_DATA6,
+ MX51_PAD_EIM_D23__USBH2_DATA7,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(usb_h2_pads,
+ ARRAY_SIZE(usb_h2_pads));
+ }
+
+ imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
}
/*
static void efika_usb_enable_devices(void)
{
/* Enable Bluetooth */
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0);
+ gpio_direction_output(IMX_GPIO_NR(2, 11), 0);
udelay(10000);
- gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1);
+ gpio_set_value(IMX_GPIO_NR(2, 11), 1);
/* Enable WiFi */
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1);
+ gpio_direction_output(IMX_GPIO_NR(2, 16), 1);
udelay(10000);
/* Reset the WiFi chip */
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
+ gpio_direction_output(IMX_GPIO_NR(2, 10), 0);
udelay(10000);
- gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);
+ gpio_set_value(IMX_GPIO_NR(2, 10), 1);
}
/*
static void efika_usb_hub_reset(void)
{
/* HUB reset */
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+ gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
udelay(1000);
- gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0);
+ gpio_set_value(IMX_GPIO_NR(1, 5), 0);
udelay(1000);
- gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+ gpio_set_value(IMX_GPIO_NR(1, 5), 1);
}
/*
static void efika_usb_phy_reset(void)
{
/* SMSC 3317 PHY reset */
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0);
+ gpio_direction_output(IMX_GPIO_NR(2, 9), 0);
udelay(1000);
- gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
+ gpio_set_value(IMX_GPIO_NR(2, 9), 1);
}
static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio,
- uint32_t alt0, uint32_t alt1)
+ iomux_v3_cfg_t stp_pad_gpio,
+ iomux_v3_cfg_t stp_pad_usb)
{
int ret;
struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
struct ulpi_viewport ulpi_vp;
- mxc_request_iomux(stp_gpio, alt0);
- mxc_iomux_set_pad(stp_gpio, PAD_CTL_DRV_HIGH |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- gpio_direction_output(IOMUX_TO_GPIO(stp_gpio), 0);
+ imx_iomux_v3_setup_pad(stp_pad_gpio);
+ gpio_direction_output(stp_gpio, 0);
udelay(1000);
- gpio_set_value(IOMUX_TO_GPIO(stp_gpio), 1);
+ gpio_set_value(stp_gpio, 1);
udelay(1000);
- mxc_request_iomux(stp_gpio, alt1);
- mxc_iomux_set_pad(stp_gpio, USB_PAD_CONFIG);
+ imx_iomux_v3_setup_pad(stp_pad_usb);
udelay(10000);
ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
tmp = (tmp & ~0x3) | 0x01;
writel(tmp, OTG_BASE_ADDR + 0x80c);
} else if (port == 1) {
- efika_ehci_init(ehci, MX51_PIN_USBH1_STP,
- IOMUX_CONFIG_ALT2, IOMUX_CONFIG_ALT0);
+ efika_ehci_init(ehci, IMX_GPIO_NR(1, 27),
+ MX51_PAD_USBH1_STP__GPIO1_27,
+ MX51_PAD_USBH1_STP__USBH1_STP);
} else if ((port == 2) && machine_is_efikasb()) {
- efika_ehci_init(ehci, MX51_PIN_EIM_A26,
- IOMUX_CONFIG_ALT1, IOMUX_CONFIG_ALT2);
+ efika_ehci_init(ehci, IMX_GPIO_NR(2, 20),
+ MX51_PAD_EIM_A26__GPIO2_20,
+ MX51_PAD_EIM_A26__USBH2_STP);
}
if (port)
static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
MX51_PAD_GPIO1_0__SD1_CD,
- MX51_PAD_EIM_CS2__SD1_CD,
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, MX51_ESDHC_PAD_CTRL),
};
#define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0)
return 0;
}
+void reset_cpu(ulong ignore)
+{
+ /* Enable VLIO interface on Hamcop */
+ writeb(0x1, 0x4000);
+
+ /* Reset board (cold reset) */
+ writeb(0xff, 0x4002);
+}
+
int board_init(void)
{
/* We have RAM, disable cache */
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/imx25-pinmux.h>
+#include <asm/arch/iomux-mx25.h>
#include <asm/gpio.h>
-#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
#ifdef CONFIG_FEC_MXC
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ * 0 for no pull
+ * or:
+ * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define FEC_OUT_PAD_CTRL 0
+
#define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7)
#define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9)
void tx25_fec_init(void)
{
- struct iomuxc_mux_ctl *muxctl;
- struct iomuxc_pad_ctl *padctl;
- u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
- u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode;
+ static const iomux_v3_cfg_t fec_pads[] = {
+ MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+ NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
+ MX25_PAD_FEC_MDIO__FEC_MDIO,
+ MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+ NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
+
+ NEW_PAD_CTRL(MX25_PAD_D13__GPIO_4_7, 0), /* FEC_RESET_B */
+ NEW_PAD_CTRL(MX25_PAD_D11__GPIO_4_9, 0), /* FEC_ENABLE_B */
+ };
+
+ static const iomux_v3_cfg_t fec_cfg_pads[] = {
+ MX25_PAD_FEC_RDATA0__GPIO_3_10,
+ MX25_PAD_FEC_RDATA1__GPIO_3_11,
+ MX25_PAD_FEC_RX_DV__GPIO_3_12,
+ };
debug("tx25_fec_init\n");
- /*
- * fec pin init is generic
- */
- mx25_fec_init_pins();
-
- /*
- * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
- *
- * FEC_RESET_B: gpio4[7] is ALT 5 mode of pin D13
- * FEC_ENABLE_B: gpio4[9] is ALT 5 mode of pin D11
- */
- muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
- padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-
- writel(gpio_mux_mode, &muxctl->pad_d13);
- writel(gpio_mux_mode, &muxctl->pad_d11);
-
- writel(0x0, &padctl->pad_d13);
- writel(0x0, &padctl->pad_d11);
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
/* drop PHY power and assert reset (low) */
gpio_direction_output(GPIO_FEC_RESET_B, 0);
* RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode
*/
/*
- * save three current mux modes and set each to gpio mode
+ * set each mux mode to gpio mode
*/
- saved_rdata0_mode = readl(&muxctl->pad_fec_rdata0);
- saved_rdata1_mode = readl(&muxctl->pad_fec_rdata1);
- saved_rx_dv_mode = readl(&muxctl->pad_fec_rx_dv);
-
- writel(gpio_mux_mode, &muxctl->pad_fec_rdata0);
- writel(gpio_mux_mode, &muxctl->pad_fec_rdata1);
- writel(gpio_mux_mode, &muxctl->pad_fec_rx_dv);
+ imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
+ ARRAY_SIZE(fec_cfg_pads));
/*
* set each to 1 and make each an output
/*
* set FEC pins back
*/
- writel(saved_rdata0_mode, &muxctl->pad_fec_rdata0);
- writel(saved_rdata1_mode, &muxctl->pad_fec_rdata1);
- writel(saved_rx_dv_mode, &muxctl->pad_fec_rx_dv);
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
#else
#define tx25_fec_init()
#endif
-int board_init()
-{
#ifdef CONFIG_MXC_UART
- mx25_uart1_init_pins();
+/*
+ * Set up input pins with hysteresis and 100-k pull-ups
+ */
+#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ * 0 for no pull
+ * or:
+ * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define UART1_OUT_PAD_CTRL 0
+
+static void tx25_uart1_init(void)
+{
+ static const iomux_v3_cfg_t uart1_pads[] = {
+ NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+#else
+#define tx25_uart1_init()
#endif
+
+int board_init()
+{
+ tx25_uart1_init();
+
/* board id for linux */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
/*
- * (C) Copyright 2007-2010
+ * (C) Copyright 2007-2013
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
u32 pbcr;
int size_val = 0;
u32 reg;
+#ifndef CONFIG_LCD4_LWMON5
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
unsigned long sdr0_pfc1, sdr0_srst;
+#endif
/*
* FLASH stuff...
CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
&flash_info[cfi_flash_num_flash_banks - 1]);
+#ifndef CONFIG_LCD4_LWMON5
/*
* USB suff...
*/
/* 7. Reassert internal PHY reset: */
mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
udelay(1000);
+#endif
/*
* Clear resets
mtsdr(SDR0_SRST1, 0x00000000);
mtsdr(SDR0_SRST0, 0x00000000);
+#ifndef CONFIG_LCD4_LWMON5
printf("USB: Host(int phy) Device(ext phy)\n");
+#endif
/*
* Clear PLB4A0_ACR[WRP]
reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
mtdcr(PLB4A0_ACR, reg);
+#ifndef CONFIG_LCD4_LWMON5
/*
* Init matrix keyboard
*/
misc_init_r_kbd();
+#endif
return 0;
}
char buf[64];
int i = getenv_f("serial#", buf, sizeof(buf));
- puts("Board: lwmon5");
+ printf("Board: %s", __stringify(CONFIG_HOSTNAME));
if (i > 0) {
puts(", serial# ");
{
gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
}
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * lwmon5 specific implementation of spl_start_uboot()
+ *
+ * RETURN
+ * 0 if booting into OS is selected (default)
+ * 1 if booting into U-Boot is selected
+ */
+int spl_start_uboot(void)
+{
+ char s[8];
+
+ env_init();
+ getenv_f("boot_os", s, sizeof(s));
+ if ((s != NULL) && (strcmp(s, "yes") == 0))
+ return 0;
+
+ return 1;
+}
+
+/*
+ * This function is called from the SPL U-Boot version for
+ * early init stuff, that needs to be done for OS (e.g. Linux)
+ * booting. Doing it later in the real U-Boot would not work
+ * in case that the SPL U-Boot boots Linux directly.
+ */
+void spl_board_init(void)
+{
+ const gdc_regs *regs = board_get_regs();
+
+ /*
+ * Setup PFC registers, mainly for ethernet support
+ * later on in Linux
+ */
+ board_early_init_f();
+
+ /*
+ * Clear resets
+ */
+ mtsdr(SDR0_SRST1, 0x00000000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ /*
+ * Reset Lime controller
+ */
+ gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
+ udelay(500);
+ gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
+
+ out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF);
+ udelay(300);
+ out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR);
+
+ while (regs->index) {
+ out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) +
+ regs->index, regs->value);
+ regs++;
+ }
+
+ board_backlight_brightness(DEFAULT_BRIGHTNESS);
+}
+#endif
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
*
- * (C) Copyright 2007-2008
+ * (C) Copyright 2007-2013
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
************************************************************************/
phys_size_t initdram (int board_type)
{
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_LCD4_LWMON5)
/* CL=4 */
mtsdram(DDR0_02, 0x00000000);
* exceptions are enabled.
*/
set_mcsr(get_mcsr());
+#endif /* CONFIG_SPL_BUILD */
return (CONFIG_SYS_MBYTES_SDRAM << 20);
}
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_16MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_SSP (MXS_PAD_8MA | MXS_PAD_PULLUP)
const iomux_cfg_t iomux_setup[] = {
/* DUART */
int dram_init(void)
{
- gd->ram_size = CONFIG_DRAM_SIZE;
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/imx25-pinmux.h>
-#include <asm/arch/sys_proto.h>
+#include <asm/arch/iomux-mx25.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init()
{
- struct iomuxc_mux_ctl *muxctl;
- struct iomuxc_pad_ctl *padctl;
- struct iomuxc_pad_input_select *inputselect;
- u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
- u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1);
- u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
- u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6);
- u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1);
- u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2);
+ static const iomux_v3_cfg_t sdhc1_pads[] = {
+ NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
+ };
+
+ static const iomux_v3_cfg_t dig_out_pads[] = {
+ MX25_PAD_CSI_D8__GPIO_1_7, /* Ouput 1 Ctrl */
+ MX25_PAD_CSI_D7__GPIO_1_6, /* Ouput 2 Ctrl */
+ NEW_PAD_CTRL(MX25_PAD_CSI_D6__GPIO_1_31, 0), /* Ouput 1 Stat */
+ NEW_PAD_CTRL(MX25_PAD_CSI_D5__GPIO_1_30, 0), /* Ouput 2 Stat */
+ };
+
+ static const iomux_v3_cfg_t led_pads[] = {
+ MX25_PAD_CSI_D9__GPIO_4_21,
+ MX25_PAD_CSI_D4__GPIO_1_29,
+ };
+
+ static const iomux_v3_cfg_t can_pads[] = {
+ NEW_PAD_CTRL(MX25_PAD_GPIO_A__CAN1_TX, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_GPIO_B__CAN1_RX, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_GPIO_C__CAN2_TX, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_GPIO_D__CAN2_RX, NO_PAD_CTRL),
+ };
+
+ static const iomux_v3_cfg_t i2c3_pads[] = {
+ MX25_PAD_CSPI1_SS1__I2C3_DAT,
+ MX25_PAD_GPIO_E__I2C3_CLK,
+ };
icache_enable();
- muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
- padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
- inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE;
-
- /* Setup of core volatage selection pin to run at 1.4V */
- writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */
+ /* Setup of core voltage selection pin to run at 1.4V */
+ imx_iomux_v3_setup_pad(MX25_PAD_EXT_ARMCLK__GPIO_3_15); /* VCORE */
gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
- /* Setup of input daisy chains for SD card pins*/
- writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd);
- writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk);
- writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0);
- writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1);
- writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2);
- writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3);
+ /* Setup of SD card pins*/
+ imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
/* Setup of digital output for USB power and OC */
- writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */
+ imx_iomux_v3_setup_pad(MX25_PAD_CSI_D3__GPIO_1_28); /* USB Power */
gpio_direction_output(IMX_GPIO_NR(1, 28), 1);
- writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */
+ imx_iomux_v3_setup_pad(MX25_PAD_CSI_D2__GPIO_1_27); /* USB OC */
gpio_direction_input(IMX_GPIO_NR(1, 18));
/* Setup of digital output control pins */
- writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */
- writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */
- writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/
- writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/
-
- writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */
- writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */
+ imx_iomux_v3_setup_multiple_pads(dig_out_pads,
+ ARRAY_SIZE(dig_out_pads));
/* Switch both output drivers off */
gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
- /* Setup of key input pin GPIO2[29]*/
- writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0);
- writel(0, &padctl->pad_kpp_row0); /* Key pull up off */
+ /* Setup of key input pin */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_KPP_ROW0__GPIO_2_29, 0));
gpio_direction_input(IMX_GPIO_NR(2, 29));
/* Setup of status LED outputs */
- writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */
- writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */
+ imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
/* Switch both LEDs off */
gpio_direction_output(IMX_GPIO_NR(4, 21), 0);
gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
/* Setup of CAN1 and CAN2 signals */
- writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */
- writel(gpio_mux_mode6, &muxctl->pad_gpio_b); /* CAN1 RX */
- writel(gpio_mux_mode6, &muxctl->pad_gpio_c); /* CAN2 TX */
- writel(gpio_mux_mode6, &muxctl->pad_gpio_d); /* CAN2 RX */
-
- /* Setup of input daisy chains for CAN signals*/
- writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */
- writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */
+ imx_iomux_v3_setup_multiple_pads(can_pads, ARRAY_SIZE(can_pads));
/* Setup of I2C3 signals */
- writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1); /* I2C3 SDA */
- writel(gpio_mux_mode1, &muxctl->pad_gpio_e); /* I2C3 SCL */
-
- /* Setup of input daisy chains for I2C3 signals*/
- writel(input_select1, &inputselect->i2c3_ipp_sda_in); /* I2C3 SDA */
- writel(input_select2, &inputselect->i2c3_ipp_scl_in); /* I2C3 SCL */
+ imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
const char *e;
#ifdef CONFIG_FEC_MXC
- struct iomuxc_mux_ctl *muxctl;
- u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2);
- u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
-
- /*
- * fec pin init is generic
- */
- mx25_fec_init_pins();
-
- /*
- * Set up LAN-RESET and FEC_RX_ERR
- *
- * LAN-RESET: GPIO3[16] is ALT 5 mode of pin U20
- * FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2
- */
- muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
-
- writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk);
- writel(gpio_mux_mode2, &muxctl->pad_uart2_cts);
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ * 0 for no pull
+ * or:
+ * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define FEC_OUT_PAD_CTRL 0
+
+ static const iomux_v3_cfg_t fec_pads[] = {
+ MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+ NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
+ MX25_PAD_FEC_MDIO__FEC_MDIO,
+ MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+ NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
+
+ MX25_PAD_UPLL_BYPCLK__GPIO_3_16, /* LAN-RESET */
+ MX25_PAD_UART2_CTS__FEC_RX_ER, /* FEC_RX_ERR */
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
/* assert PHY reset (low) */
gpio_direction_output(IMX_GPIO_NR(3, 16), 0);
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx51.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
int val;
/* toggle watchdog trigger pin */
- val = gpio_get_value(66);
+ val = gpio_get_value(IMX_GPIO_NR(3, 2));
val = val ? 0 : 1;
- gpio_set_value(66, val);
+ gpio_set_value(IMX_GPIO_NR(3, 2), val);
}
#endif
static void init_drive_strength(void)
{
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
- mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
-
- /* Setting pad options */
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
- PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
- PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ static const iomux_v3_cfg_t ddr_pads[] = {
+ NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0),
+ NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0),
+ NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP),
+ NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS,
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS,
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0),
+ NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0),
+ NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0),
+ NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0),
+ NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0),
+ NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP),
+ NEW_PAD_CTRL(MX51_GRP_INMODE1, 0),
+ NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED),
+ NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED),
+ NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED),
+ NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED),
+
+ NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0,
+ MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1,
+ MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK,
+ MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0,
+ MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1,
+ MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2,
+ MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3,
+ MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
}
int dram_init(void)
static void setup_uart(void)
{
- unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
- PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
- /* console RX on Pin EIM_D25 */
- mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
- /* console TX on Pin EIM_D26 */
- mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
+ static const iomux_v3_cfg_t uart_pads[] = {
+ MX51_PAD_EIM_D25__UART3_RXD, /* console RX */
+ MX51_PAD_EIM_D26__UART3_TXD, /* console TX */
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
#ifdef CONFIG_MXC_SPI
void spi_io_init(void)
{
- /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
- mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
- /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
- /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
- /*
- * SS1 will be used as GPIO because of uninterrupted
- * long SPI transmissions (GPIO4_25)
- */
- mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
- /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7);
- mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
- /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+ static const iomux_v3_cfg_t spi_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS |
+ PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS |
+ PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS |
+ PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
}
static void reset_peripherals(int reset)
{
+#ifdef CONFIG_VISION2_HW_1_0
+ static const iomux_v3_cfg_t fec_cfg_pads[] = {
+ /* RXD1 */
+ NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL),
+ /* RXD2 */
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL),
+ /* RXD3 */
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL),
+ /* RXER */
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL),
+ /* COL */
+ NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL),
+ /* RCLK */
+ NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL),
+ /* RXD0 */
+ NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL),
+ };
+
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
+ NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
+ MX51_PAD_NANDF_D9__FEC_RDATA0,
+ NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
+ MX51_PAD_EIM_CS4__FEC_RX_ER,
+ NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
+ };
+#endif
+
if (reset) {
/* reset_n is on NANDF_D15 */
- gpio_direction_output(89, 0);
+ gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
#ifdef CONFIG_VISION2_HW_1_0
/*
* set FEC Configuration lines
* set levels of FEC config lines
*/
- gpio_direction_output(75, 0);
- gpio_direction_output(74, 1);
- gpio_direction_output(95, 1);
+ gpio_direction_output(IMX_GPIO_NR(3, 11), 0);
+ gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
+ gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
/* set direction of FEC config lines */
- gpio_direction_output(59, 0);
- gpio_direction_output(60, 0);
- gpio_direction_output(61, 0);
- gpio_direction_output(55, 1);
-
- /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
- mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
- /* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
- mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1);
- /* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
- mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1);
- /* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
- mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1);
- /* FEC_COL - sel GPIO (3-10) for configuration -> 1 */
- mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3);
- /* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
- mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3);
- /* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
- mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3);
+ gpio_direction_output(IMX_GPIO_NR(2, 27), 0);
+ gpio_direction_output(IMX_GPIO_NR(2, 28), 0);
+ gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
+ gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
+
+ imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
+ ARRAY_SIZE(fec_cfg_pads));
#endif
- /*
- * activate reset_n pin
- * Select mux mode: ALT3 mux port: NAND D15
- */
- mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D15,
- PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX);
+ /* activate reset_n pin */
+ imx_iomux_v3_setup_pad(
+ NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25,
+ PAD_CTL_DSE_MAX));
} else {
/* set FEC Control lines */
- gpio_direction_input(89);
+ gpio_direction_input(IMX_GPIO_NR(3, 25));
udelay(500);
#ifdef CONFIG_VISION2_HW_1_0
- /* FEC RDATA[3] */
- mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
-
- /* FEC RDATA[2] */
- mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
-
- /* FEC RDATA[1] */
- mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
-
- /* FEC RDATA[0] */
- mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
-
- /* FEC RX_CLK */
- mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
-
- /* FEC RX_ER */
- mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
-
- /* FEC COL */
- mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
+ imx_iomux_v3_setup_multiple_pads(fec_pads,
+ ARRAY_SIZE(fec_pads));
#endif
}
}
static void setup_gpios(void)
{
- unsigned int i;
-
- /* CAM_SUP_DISn, GPIO1_7 */
- mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82);
+ static const iomux_v3_cfg_t gpio_pads_1[] = {
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* CAM_SUP_DISn */
+ NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* DAB Display EN */
+ NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* WDOG_TRIGGER */
+ };
+
+ static const iomux_v3_cfg_t gpio_pads_2[] = {
+ NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* Display2 TxEN */
+ NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* DAB Light EN */
+ NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* AUDIO_MUTE */
+ NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* SPARE_OUT */
+ NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* BEEPER_EN */
+ NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* POWER_OFF */
+ NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* FRAM_WE */
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* EXPANSION_EN */
+ MX51_PAD_GPIO1_2__PWM1_PWMO,
+ };
- /* DAB Display EN, GPIO3_1 */
- mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
- mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82);
+ unsigned int i;
- /* WDOG_TRIGGER, GPIO3_2 */
- mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
- mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82);
+ imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1));
/* Now we need to trigger the watchdog */
WATCHDOG_RESET();
- /* Display2 TxEN, GPIO3_3 */
- mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
- mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82);
-
- /* DAB Light EN, GPIO3_4 */
- mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
- mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82);
-
- /* AUDIO_MUTE, GPIO3_5 */
- mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4);
- mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82);
-
- /* SPARE_OUT, GPIO3_6 */
- mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
- mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82);
-
- /* BEEPER_EN, GPIO3_26 */
- mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82);
-
- /* POWER_OFF, GPIO3_27 */
- mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82);
-
- /* FRAM_WE, GPIO3_30 */
- mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82);
-
- /* EXPANSION_EN, GPIO4_26 */
- mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
-
- /* PWM Output GPIO1_2 */
- mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
+ imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2));
/*
* Set GPIO1_4 to high and output; it is used to reset
* the system on reboot
*/
- gpio_direction_output(4, 1);
+ gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
- gpio_direction_output(7, 0);
- for (i = 65; i < 71; i++)
+ gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
+ for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++)
gpio_direction_output(i, 0);
- gpio_direction_output(94, 0);
+ gpio_direction_output(IMX_GPIO_NR(3, 30), 0);
/* Set POWER_OFF high */
- gpio_direction_output(91, 1);
+ gpio_direction_output(IMX_GPIO_NR(3, 27), 1);
- gpio_direction_output(90, 0);
+ gpio_direction_output(IMX_GPIO_NR(3, 26), 0);
- gpio_direction_output(122, 0);
+ gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
- gpio_direction_output(121, 1);
+ gpio_direction_output(IMX_GPIO_NR(4, 25), 1);
WATCHDOG_RESET();
}
static void setup_fec(void)
{
- /*FEC_MDIO*/
- mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD);
-
- /*FEC_MDC*/
- mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
-
- /* FEC RDATA[3] */
- mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
-
- /* FEC RDATA[2] */
- mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
-
- /* FEC RDATA[1] */
- mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
-
- /* FEC RDATA[0] */
- mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
-
- /* FEC TDATA[3] */
- mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
-
- /* FEC TDATA[2] */
- mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
-
- /* FEC TDATA[1] */
- mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
-
- /* FEC TDATA[0] */
- mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
-
- /* FEC TX_EN */
- mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
-
- /* FEC TX_ER */
- mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
-
- /* FEC TX_CLK */
- mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
-
- /* FEC TX_COL */
- mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
-
- /* FEC RX_CLK */
- mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
-
- /* FEC RX_CRS */
- mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
-
- /* FEC RX_ER */
- mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
-
- /* FEC RX_DV */
- mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ MX51_PAD_NANDF_CS3__FEC_MDC,
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
+ NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
+ MX51_PAD_NANDF_D9__FEC_RDATA0,
+ MX51_PAD_NANDF_CS6__FEC_TDATA3,
+ MX51_PAD_NANDF_CS5__FEC_TDATA2,
+ MX51_PAD_NANDF_CS4__FEC_TDATA1,
+ MX51_PAD_NANDF_D8__FEC_TDATA0,
+ MX51_PAD_NANDF_CS7__FEC_TX_EN,
+ MX51_PAD_NANDF_CS2__FEC_TX_ER,
+ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
+ NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
+ NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
+ MX51_PAD_EIM_CS5__FEC_CRS,
+ MX51_PAD_EIM_CS4__FEC_RX_ER,
+ NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
struct fsl_esdhc_cfg esdhc_cfg[1] = {
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
- *cd = gpio_get_value(0);
+ *cd = gpio_get_value(IMX_GPIO_NR(1, 0));
else
*cd = 0;
#ifdef CONFIG_FSL_ESDHC
int board_mmc_init(bd_t *bis)
{
- mxc_request_iomux(MX51_PIN_SD1_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA0,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA1,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA2,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA3,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_GPIO1_0,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
- PAD_CTL_HYS_ENABLE);
- mxc_request_iomux(MX51_PIN_GPIO1_1,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
- PAD_CTL_HYS_ENABLE);
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
void lcd_enable(void)
{
+ static const iomux_v3_cfg_t lcd_pads[] = {
+ MX51_PAD_DI1_PIN2__DI1_PIN2,
+ MX51_PAD_DI1_PIN3__DI1_PIN3,
+ };
+
int ret;
- mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
+ imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
- gpio_set_value(2, 1);
- mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
+ gpio_set_value(IMX_GPIO_NR(1, 2), 1);
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2,
+ NO_PAD_CTRL));
ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
if (ret)
init_drive_strength();
/* Setup debug led */
- gpio_direction_output(6, 0);
- mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+ gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST));
/* wait a little while to give the pll time to settle */
sdelay(100000);
static void backlight(int on)
{
if (on) {
- gpio_set_value(65, 1);
+ gpio_set_value(IMX_GPIO_NR(3, 1), 1);
udelay(10000);
- gpio_set_value(68, 1);
+ gpio_set_value(IMX_GPIO_NR(3, 4), 1);
} else {
- gpio_set_value(65, 0);
- gpio_set_value(68, 0);
+ gpio_set_value(IMX_GPIO_NR(3, 1), 0);
+ gpio_set_value(IMX_GPIO_NR(3, 4), 0);
}
}
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
#include <asm/io.h>
#include <asm/sizes.h>
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
#define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
int dram_init(void)
MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};
+iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* Carrier MicroSD Card Detect */
+ MX6_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* SOM MicroSD Card Detect */
+ MX6_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const enet_pads[] = {
gpio_set_value(ETH_PHY_RESET, 1);
}
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR},
+ {USDHC1_BASE_ADDR},
};
-int board_mmc_init(bd_t *bis)
+int board_mmc_getcd(struct mmc *mmc)
{
- imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[0].max_bus_width = 4;
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+int board_mmc_init(bd_t *bis)
+{
+ s32 status = 0;
+ u32 index = 0;
+
+ /*
+ * Following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 SOM MicroSD
+ * mmc1 Carrier board MicroSD
+ */
+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ gpio_direction_input(USDHC3_CD_GPIO);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ usdhc_cfg[1].max_bus_width = 4;
+ gpio_direction_input(USDHC1_CD_GPIO);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) then supported by the board (%d)\n",
+ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return status;
+ }
+
+ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ }
+
+ return status;
}
static int mx6_rgmii_rework(struct phy_device *phydev)
return 0;
}
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ return 0;
+}
+
int board_init(void)
{
/* address of boot parameters */
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
-#include <asm/arch/mx35_pins.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx35.h>
#include <i2c.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
static void setup_iomux_fec(void)
{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+ MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX35_PAD_FEC_COL__FEC_COL,
+ MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+ MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+ MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+ MX35_PAD_FEC_MDC__FEC_MDC,
+ MX35_PAD_FEC_MDIO__FEC_MDIO,
+ MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+ MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+ MX35_PAD_FEC_CRS__FEC_CRS,
+ MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+ MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+ MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+ MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+ MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+ MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+ };
+
/* setup pins for FEC */
- mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
int woodburn_init(void)
setup_iomux_fec();
/* setup GPIO1_4 FEC_ENABLE signal */
- mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_ALT5);
+ imx_iomux_v3_setup_pad(MX35_PAD_SCKR__GPIO1_4);
gpio_direction_output(4, 1);
- mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_ALT5);
+ imx_iomux_v3_setup_pad(MX35_PAD_HCKT__GPIO1_9);
gpio_direction_output(9, 1);
return 0;
int board_mmc_init(bd_t *bis)
{
+ static const iomux_v3_cfg_t sdhc1_pads[] = {
+ MX35_PAD_SD1_CMD__ESDHC1_CMD,
+ MX35_PAD_SD1_CLK__ESDHC1_CLK,
+ MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+ MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+ MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+ MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
+ };
+
/* configure pins for SDHC1 only */
- mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
+ imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
/* MMC Card Detect on GPIO1_7 */
- mxc_request_iomux(MX35_PIN_SCKT, MUX_CONFIG_ALT5);
- mxc_iomux_set_input(MUX_IN_GPIO1_IN_7, 0x1);
+ imx_iomux_v3_setup_pad(MX35_PAD_SCKT__GPIO1_7);
gpio_direction_input(GPIO_MMC_CD);
/* MMC Write Protection on GPIO1_8 */
- mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_ALT5);
- mxc_iomux_set_input(MUX_IN_GPIO1_IN_8, 0x1);
+ imx_iomux_v3_setup_pad(MX35_PAD_FST__GPIO1_8);
gpio_direction_input(GPIO_MMC_WP);
esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) =
++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)));
#endif
-#ifdef CONFIG_SYS_RESET_ADDRESS
- puts ("Reseting board\n");
- asm ("bra r0");
+
+#ifdef CONFIG_XILINX_TB_WATCHDOG
+ hw_watchdog_disable();
#endif
+
+ puts ("Reseting board\n");
+ __asm__ __volatile__ (" mts rmsr, r0;" \
+ "bra r0");
+
return 0;
}
#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 0x42000180
#define XILINX_LLTEMAC_BASEADDR1 0x44200000
#define XILINX_LLTEMAC_FIFO_BASEADDR1 0x42100000
+
+/* Watchdog IP is wxi_timebase_wdt_0 */
+#define XILINX_WATCHDOG_BASEADDR 0x50000000
+#define XILINX_WATCHDOG_IRQ 1
#include <common.h>
#include <netdev.h>
+#include <zynqpl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_FPGA
+Xilinx_desc fpga;
+
+/* It can be done differently */
+Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
+Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+#endif
+
int board_init(void)
{
+#ifdef CONFIG_FPGA
+ u32 idcode;
+
+ idcode = zynq_slcr_get_idcode();
+
+ switch (idcode) {
+ case XILINX_ZYNQ_7010:
+ fpga = fpga010;
+ break;
+ case XILINX_ZYNQ_7020:
+ fpga = fpga020;
+ break;
+ case XILINX_ZYNQ_7030:
+ fpga = fpga030;
+ break;
+ case XILINX_ZYNQ_7045:
+ fpga = fpga045;
+ break;
+ }
+#endif
+
icache_enable();
+#ifdef CONFIG_FPGA
+ fpga_init();
+ fpga_add(fpga_xilinx, &fpga);
+#endif
+
return 0;
}
ti814x_evm arm armv7 ti814x ti am33xx
pcm051 arm armv7 pcm051 phytec am33xx pcm051
highbank arm armv7 highbank - highbank
+m53evk arm armv7 m53evk denx mx5 m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg
mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+mx6slevk arm armv7 mx6slevk freescale mx6 mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL
+titanium arm armv7 titanium freescale mx6 titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg
eco5pk arm armv7 eco5pk 8dtech omap3
nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
nitrogen6dl2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048
P1021RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SDCARD
P1021RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SPIFLASH
P1022DS powerpc mpc85xx p1022ds freescale
+P1022DS_NAND powerpc mpc85xx p1022ds freescale - P1022DS:NAND
+P1022DS_36BIT_NAND powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,NAND
P1022DS_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:SPIFLASH
P1022DS_36BIT_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SPIFLASH
P1022DS_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:SDCARD
korat powerpc ppc4xx
korat_perm powerpc ppc4xx korat - - korat:KORAT_PERMANENT
lwmon5 powerpc ppc4xx
+lcd4_lwmon5 powerpc ppc4xx lwmon5 - - lwmon5:LCD4_LWMON5
pcs440ep powerpc ppc4xx
quad100hd powerpc ppc4xx
sbc405 powerpc ppc4xx
COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o
endif
COBJS-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o
+COBJS-$(CONFIG_CMD_FUSE) += cmd_fuse.o
COBJS-$(CONFIG_CMD_GETTIME) += cmd_gettime.o
COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o
COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o
#include <version.h>
#include <environment.h>
#include <fdtdec.h>
+#include <fs.h>
#if defined(CONFIG_CMD_IDE)
#include <ide.h>
#endif
#include <mpc5xxx.h>
#endif
+#include <os.h>
#include <post.h>
#include <spi.h>
#include <watchdog.h>
+#include <asm/errno.h>
#include <asm/io.h>
#ifdef CONFIG_MP
#include <asm/mp.h>
#include <asm/init_helpers.h>
#include <asm/relocate.h>
#endif
+#ifdef CONFIG_SANDBOX
+#include <asm/state.h>
+#endif
#include <linux/compiler.h>
/*
static int display_text_info(void)
{
+#ifndef CONFIG_SANDBOX
ulong bss_start, bss_end;
#ifdef CONFIG_SYS_SYM_OFFSETS
#endif
debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n",
CONFIG_SYS_TEXT_BASE, bss_start, bss_end);
+#endif
#ifdef CONFIG_MODEM_SUPPORT
debug("Modem Support enabled\n");
{
#ifdef CONFIG_SYS_SYM_OFFSETS
gd->mon_len = _bss_end_ofs;
+#elif defined(CONFIG_SANDBOX)
+ gd->mon_len = (ulong)&_end - (ulong)_init;
#else
/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
return 0;
}
+#ifdef CONFIG_OF_HOSTFILE
+
+#define CHECK(x) err = (x); if (err) goto failed;
+
+/* Create an empty device tree blob */
+static int make_empty_fdt(void *fdt)
+{
+ int err;
+
+ CHECK(fdt_create(fdt, 256));
+ CHECK(fdt_finish_reservemap(fdt));
+ CHECK(fdt_begin_node(fdt, ""));
+ CHECK(fdt_end_node(fdt));
+ CHECK(fdt_finish(fdt));
+
+ return 0;
+failed:
+ printf("Unable to create empty FDT: %s\n", fdt_strerror(err));
+ return -EACCES;
+}
+
+static int read_fdt_from_file(void)
+{
+ struct sandbox_state *state = state_get_current();
+ void *blob;
+ int size;
+ int err;
+
+ blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0);
+ if (!state->fdt_fname) {
+ err = make_empty_fdt(blob);
+ if (!err)
+ goto done;
+ return err;
+ }
+ err = fs_set_blk_dev("host", NULL, FS_TYPE_SANDBOX);
+ if (err)
+ return err;
+ size = fs_read(state->fdt_fname, CONFIG_SYS_FDT_LOAD_ADDR, 0, 0);
+ if (size < 0)
+ return -EIO;
+
+done:
+ gd->fdt_blob = blob;
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SANDBOX
+static int setup_ram_buf(void)
+{
+ gd->arch.ram_buf = os_malloc(CONFIG_SYS_SDRAM_SIZE);
+ assert(gd->arch.ram_buf);
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+#endif
+
static int setup_fdt(void)
{
#ifdef CONFIG_OF_EMBED
# else
gd->fdt_blob = (ulong *)&_end;
# endif
+#elif defined(CONFIG_OF_HOSTFILE)
+ if (read_fdt_from_file()) {
+ puts("Failed to read control FDT\n");
+ return -1;
+ }
#endif
/* Allow the early environment to override the fdt address */
gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
static int reserve_board(void)
{
gd->dest_addr_sp -= sizeof(bd_t);
- gd->bd = (bd_t *)gd->dest_addr_sp;
+ gd->bd = (bd_t *)map_sysmem(gd->dest_addr_sp, sizeof(bd_t));
memset(gd->bd, '\0', sizeof(bd_t));
debug("Reserving %zu Bytes for Board Info at: %08lx\n",
sizeof(bd_t), gd->dest_addr_sp);
static int reserve_global_data(void)
{
gd->dest_addr_sp -= sizeof(gd_t);
- gd->new_gd = (gd_t *)gd->dest_addr_sp;
+ gd->new_gd = (gd_t *)map_sysmem(gd->dest_addr_sp, sizeof(gd_t));
debug("Reserving %zu Bytes for Global Data at: %08lx\n",
sizeof(gd_t), gd->dest_addr_sp);
return 0;
gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
gd->dest_addr_sp -= gd->fdt_size;
- gd->new_fdt = (void *)gd->dest_addr_sp;
- debug("Reserving %lu Bytes for FDT at: %p\n",
- gd->fdt_size, gd->new_fdt);
+ gd->new_fdt = map_sysmem(gd->dest_addr_sp, gd->fdt_size);
+ debug("Reserving %lu Bytes for FDT at: %08lx\n",
+ gd->fdt_size, gd->dest_addr_sp);
}
return 0;
memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
debug("Relocation Offset is: %08lx\n", gd->reloc_off);
- debug("Relocating to %08lx, new gd at %p, sp at %08lx\n",
- gd->dest_addr, gd->new_gd, gd->dest_addr_sp);
+ debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
+ gd->dest_addr, (ulong)map_to_sysmem(gd->new_gd),
+ gd->dest_addr_sp);
return 0;
}
* (CPU cache)
*/
board_init_f_r_trampoline(gd->start_addr_sp);
+#elif defined(CONFIG_SANDBOX)
+ board_init_r(gd->new_gd, 0);
#else
relocate_code(gd->dest_addr_sp, gd->new_gd, gd->dest_addr);
#endif
!defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
!defined(CONFIG_MPC86xx) && !defined(CONFIG_X86)
zero_global_data,
+#endif
+#ifdef CONFIG_SANDBOX
+ setup_ram_buf,
#endif
setup_fdt,
setup_mon_len,
init_baud_rate, /* initialze baudrate settings */
serial_init, /* serial communications setup */
console_init_f, /* stage 1 init of console */
-#if defined(CONFIG_X86) && defined(CONFIG_OF_CONTROL)
- prepare_fdt, /* TODO(sjg@chromium.org): remove */
+#ifdef CONFIG_SANDBOX
+ sandbox_early_getopt_check,
+#endif
+#ifdef CONFIG_OF_CONTROL
+ fdtdec_prepare_fdt,
#endif
display_options, /* say that we are here */
display_text_info, /* show debugging info if required */
hang();
}
#endif /* CONFIG_X86 */
-
-void hang(void)
-{
- puts("### ERROR ### Please RESET the board ###\n");
- for (;;);
-}
{
#ifdef CONFIG_SYS_SYM_OFFSETS
monitor_flash_len = _end_ofs;
-#else
+#elif !defined(CONFIG_SANDBOX)
monitor_flash_len = (ulong)&__init_end - gd->dest_addr;
#endif
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
/* The malloc area is immediately below the monitor copy in DRAM */
malloc_start = gd->dest_addr - TOTAL_MALLOC_LEN;
- mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
+ mem_malloc_init((ulong)map_sysmem(malloc_start, TOTAL_MALLOC_LEN),
+ TOTAL_MALLOC_LEN);
return 0;
}
static int run_main_loop(void)
{
+#ifdef CONFIG_SANDBOX
+ sandbox_main_loop_init();
+#endif
/* main_loop() can return to retry autoboot, if so just run it again */
for (;;)
main_loop();
#include <asm/global_data.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <asm/io.h>
#define MAX_LEVEL 32 /* how deeply nested we will go */
#define SCRATCHPAD 1024 /* bytes of scratchpad memory */
*/
DECLARE_GLOBAL_DATA_PTR;
-static int fdt_valid(void);
+static int fdt_valid(struct fdt_header **blobp);
static int fdt_parse_prop(char *const*newval, int count, char *data, int *len);
static int fdt_print(const char *pathp, char *prop, int depth);
static int is_printable_string(const void *data, int len);
void set_working_fdt_addr(void *addr)
{
- working_fdt = addr;
+ void *buf;
+
+ buf = map_sysmem((ulong)addr, 0);
+ working_fdt = buf;
setenv_addr("fdtaddr", addr);
}
*/
if (argv[1][0] == 'a') {
unsigned long addr;
+ int control = 0;
+ struct fdt_header *blob;
/*
* Set the address [and length] of the fdt.
*/
- if (argc == 2) {
- if (!fdt_valid()) {
+ argc -= 2;
+ argv += 2;
+/* Temporary #ifdef - some archs don't have fdt_blob yet */
+#ifdef CONFIG_OF_CONTROL
+ if (argc && !strcmp(*argv, "-c")) {
+ control = 1;
+ argc--;
+ argv++;
+ }
+#endif
+ if (argc == 0) {
+ if (control)
+ blob = (struct fdt_header *)gd->fdt_blob;
+ else
+ blob = working_fdt;
+ if (!blob || !fdt_valid(&blob))
return 1;
- }
- printf("The address of the fdt is %p\n", working_fdt);
+ printf("The address of the fdt is %#08lx\n",
+ control ? (ulong)blob :
+ getenv_hex("fdtaddr", 0));
return 0;
}
- addr = simple_strtoul(argv[2], NULL, 16);
- set_working_fdt_addr((void *)addr);
-
- if (!fdt_valid()) {
+ addr = simple_strtoul(argv[0], NULL, 16);
+ blob = map_sysmem(addr, 0);
+ if (!fdt_valid(&blob))
return 1;
- }
+ if (control)
+ gd->fdt_blob = blob;
+ else
+ set_working_fdt_addr(blob);
- if (argc >= 4) {
+ if (argc >= 2) {
int len;
int err;
/*
* Optional new length
*/
- len = simple_strtoul(argv[3], NULL, 16);
- if (len < fdt_totalsize(working_fdt)) {
+ len = simple_strtoul(argv[1], NULL, 16);
+ if (len < fdt_totalsize(blob)) {
printf ("New length %d < existing length %d, "
"ignoring.\n",
- len, fdt_totalsize(working_fdt));
+ len, fdt_totalsize(blob));
} else {
/*
* Open in place with a new length.
*/
- err = fdt_open_into(working_fdt, working_fdt, len);
+ err = fdt_open_into(blob, blob, len);
if (err != 0) {
printf ("libfdt fdt_open_into(): %s\n",
fdt_strerror(err));
* Set the address and length of the fdt.
*/
working_fdt = (struct fdt_header *)simple_strtoul(argv[2], NULL, 16);
- if (!fdt_valid()) {
+ if (!fdt_valid(&working_fdt))
return 1;
- }
newaddr = (struct fdt_header *)simple_strtoul(argv[3],NULL,16);
/****************************************************************************/
-static int fdt_valid(void)
+/**
+ * fdt_valid() - Check if an FDT is valid. If not, change it to NULL
+ *
+ * @blobp: Pointer to FDT pointer
+ * @return 1 if OK, 0 if bad (in which case *blobp is set to NULL)
+ */
+static int fdt_valid(struct fdt_header **blobp)
{
- int err;
+ const void *blob = *blobp;
+ int err;
- if (working_fdt == NULL) {
+ if (blob == NULL) {
printf ("The address of the fdt is invalid (NULL).\n");
return 0;
}
- err = fdt_check_header(working_fdt);
+ err = fdt_check_header(blob);
if (err == 0)
return 1; /* valid */
* Be more informative on bad version.
*/
if (err == -FDT_ERR_BADVERSION) {
- if (fdt_version(working_fdt) <
+ if (fdt_version(blob) <
FDT_FIRST_SUPPORTED_VERSION) {
printf (" - too old, fdt %d < %d",
- fdt_version(working_fdt),
+ fdt_version(blob),
FDT_FIRST_SUPPORTED_VERSION);
- working_fdt = NULL;
}
- if (fdt_last_comp_version(working_fdt) >
+ if (fdt_last_comp_version(blob) >
FDT_LAST_SUPPORTED_VERSION) {
printf (" - too new, fdt %d > %d",
- fdt_version(working_fdt),
+ fdt_version(blob),
FDT_LAST_SUPPORTED_VERSION);
- working_fdt = NULL;
}
- return 0;
}
printf("\n");
+ *blobp = NULL;
return 0;
}
return 1;
/********************************************************************/
#ifdef CONFIG_SYS_LONGHELP
static char fdt_help_text[] =
- "addr
<addr> [<length>] - Set the fdt location to <addr>\n"
+ "addr
[-c] <addr> [<length>] - Set the [control] fdt location to <addr>\n"
#ifdef CONFIG_OF_BOARD_SETUP
"fdt boardsetup - Do board-specific set up\n"
#endif
*/
#include <common.h>
#include <command.h>
-#if defined(CONFIG_CMD_NET)
-#include <net.h>
-#endif
#include <fpga.h>
#include <malloc.h>
/* Local functions */
-static int fpga_get_op (char *opstr);
+static int fpga_get_op(char *opstr);
/* Local defines */
#define FPGA_NONE -1
#define FPGA_DUMP 3
#define FPGA_LOADMK 4
-/* Convert bitstream data and load into the fpga */
-int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
-{
-#if defined(CONFIG_FPGA_XILINX)
- unsigned int length;
- unsigned int swapsize;
- char buffer[80];
- unsigned char *dataptr;
- unsigned int i;
- int rc;
-
- dataptr = (unsigned char *)fpgadata;
-
- /* skip the first bytes of the bitsteam, their meaning is unknown */
- length = (*dataptr << 8) + *(dataptr+1);
- dataptr+=2;
- dataptr+=length;
-
- /* get design name (identifier, length, string) */
- length = (*dataptr << 8) + *(dataptr+1);
- dataptr+=2;
- if (*dataptr++ != 0x61) {
- debug("%s: Design name identifier not recognized "
- "in bitstream\n",
- __func__);
- return FPGA_FAIL;
- }
-
- length = (*dataptr << 8) + *(dataptr+1);
- dataptr+=2;
- for(i=0;i<length;i++)
- buffer[i] = *dataptr++;
-
- printf(" design filename = \"%s\"\n", buffer);
-
- /* get part number (identifier, length, string) */
- if (*dataptr++ != 0x62) {
- printf("%s: Part number identifier not recognized "
- "in bitstream\n",
- __func__);
- return FPGA_FAIL;
- }
-
- length = (*dataptr << 8) + *(dataptr+1);
- dataptr+=2;
- for(i=0;i<length;i++)
- buffer[i] = *dataptr++;
- printf(" part number = \"%s\"\n", buffer);
-
- /* get date (identifier, length, string) */
- if (*dataptr++ != 0x63) {
- printf("%s: Date identifier not recognized in bitstream\n",
- __func__);
- return FPGA_FAIL;
- }
-
- length = (*dataptr << 8) + *(dataptr+1);
- dataptr+=2;
- for(i=0;i<length;i++)
- buffer[i] = *dataptr++;
- printf(" date = \"%s\"\n", buffer);
-
- /* get time (identifier, length, string) */
- if (*dataptr++ != 0x64) {
- printf("%s: Time identifier not recognized in bitstream\n",
- __func__);
- return FPGA_FAIL;
- }
-
- length = (*dataptr << 8) + *(dataptr+1);
- dataptr+=2;
- for(i=0;i<length;i++)
- buffer[i] = *dataptr++;
- printf(" time = \"%s\"\n", buffer);
-
- /* get fpga data length (identifier, length) */
- if (*dataptr++ != 0x65) {
- printf("%s: Data length identifier not recognized in bitstream\n",
- __func__);
- return FPGA_FAIL;
- }
- swapsize = ((unsigned int) *dataptr <<24) +
- ((unsigned int) *(dataptr+1) <<16) +
- ((unsigned int) *(dataptr+2) <<8 ) +
- ((unsigned int) *(dataptr+3) ) ;
- dataptr+=4;
- printf(" bytes in bitstream = %d\n", swapsize);
-
- rc = fpga_load(dev, dataptr, swapsize);
- return rc;
-#else
- printf("Bitstream support only for Xilinx devices\n");
- return FPGA_FAIL;
-#endif
-}
-
/* ------------------------------------------------------------------------- */
/* command form:
* fpga <op> <device number> <data addr> <datasize>
* If there is no data addr field, the fpgadata environment variable is used.
* The info command requires no data address field.
*/
-int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
int op, dev = FPGA_INVALID_DEVICE;
size_t data_size = 0;
void *fpga_data = NULL;
- char *devstr = getenv ("fpga");
- char *datastr = getenv ("fpgadata");
+ char *devstr = getenv("fpga");
+ char *datastr = getenv("fpgadata");
int rc = FPGA_FAIL;
int wrong_parms = 0;
-#if defined (CONFIG_FIT)
+#if defined(CONFIG_FIT)
const char *fit_uname = NULL;
ulong fit_addr;
#endif
if (devstr)
- dev = (int) simple_strtoul (devstr, NULL, 16);
+ dev = (int) simple_strtoul(devstr, NULL, 16);
if (datastr)
- fpga_data = (void *) simple_strtoul (datastr, NULL, 16);
+ fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
switch (argc) {
case 5: /* fpga <op> <dev> <data> <datasize> */
- data_size = simple_strtoul (argv[4], NULL, 16);
+ data_size = simple_strtoul(argv[4], NULL, 16);
case 4: /* fpga <op> <dev> <data> */
#if defined(CONFIG_FIT)
- if (fit_parse_subimage (argv[3], (ulong)fpga_data,
- &fit_addr, &fit_uname)) {
+ if (fit_parse_subimage(argv[3], (ulong)fpga_data,
+ &fit_addr, &fit_uname)) {
fpga_data = (void *)fit_addr;
- debug("* fpga: subimage '%s' from FIT image "
- "at 0x%08lx\n",
- fit_uname, fit_addr);
+ debug("* fpga: subimage '%s' from FIT image ",
+ fit_uname);
+ debug("at 0x%08lx\n", fit_addr);
} else
#endif
{
- fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
+ fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
debug("* fpga: cmdline image address = 0x%08lx\n",
- (ulong)fpga_data);
+ (ulong)fpga_data);
}
- debug("%s: fpga_data = 0x%x\n", __func__, (uint) fpga_data);
+ debug("%s: fpga_data = 0x%x\n", __func__, (uint)fpga_data);
case 3: /* fpga <op> <dev | data addr> */
- dev = (int) simple_strtoul (argv[2], NULL, 16);
+ dev = (int)simple_strtoul(argv[2], NULL, 16);
debug("%s: device = %d\n", __func__, dev);
/* FIXME - this is a really weak test */
- if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */
+ if ((argc == 3) && (dev > fpga_count())) {
+ /* must be buffer ptr */
debug("%s: Assuming buffer pointer in arg 3\n",
- __func__);
+ __func__);
#if defined(CONFIG_FIT)
- if (fit_parse_subimage (argv[2], (ulong)fpga_data,
- &fit_addr, &fit_uname)) {
+ if (fit_parse_subimage(argv[2], (ulong)fpga_data,
+ &fit_addr, &fit_uname)) {
fpga_data = (void *)fit_addr;
- debug("* fpga: subimage '%s' from FIT image "
- "at 0x%08lx\n",
- fit_uname, fit_addr);
+ debug("* fpga: subimage '%s' from FIT image ",
+ fit_uname);
+ debug("at 0x%08lx\n", fit_addr);
} else
#endif
{
- fpga_data = (void *) dev;
- debug("* fpga: cmdline image address = "
- "0x%08lx\n", (ulong)fpga_data);
+ fpga_data = (void *)dev;
+ debug("* fpga: cmdline image addr = 0x%08lx\n",
+ (ulong)fpga_data);
}
debug("%s: fpga_data = 0x%x\n",
- __func__, (uint) fpga_data);
+ __func__, (uint)fpga_data);
dev = FPGA_INVALID_DEVICE; /* reset device num */
}
case 2: /* fpga <op> */
- op = (int) fpga_get_op (argv[1]);
+ op = (int)fpga_get_op(argv[1]);
break;
default:
- debug("%s: Too many or too few args (%d)\n",
- __func__, argc);
+ debug("%s: Too many or too few args (%d)\n", __func__, argc);
op = FPGA_NONE; /* force usage display */
break;
}
return CMD_RET_USAGE;
case FPGA_INFO:
- rc = fpga_info (dev);
+ rc = fpga_info(dev);
break;
case FPGA_LOAD:
- rc = fpga_load (dev, fpga_data, data_size);
+ rc = fpga_load(dev, fpga_data, data_size);
break;
case FPGA_LOADB:
break;
case FPGA_LOADMK:
- switch (genimg_get_format (fpga_data)) {
+ switch (genimg_get_format(fpga_data)) {
case IMAGE_FORMAT_LEGACY:
{
- image_header_t *hdr = (image_header_t *)fpga_data;
- ulong data;
+ image_header_t *hdr =
+ (image_header_t *)fpga_data;
+ ulong data;
- data = (ulong)image_get_data (hdr);
- data_size = image_get_data_size (hdr);
- rc = fpga_load (dev, (void *)data, data_size);
+ data = (ulong)image_get_data(hdr);
+ data_size = image_get_data_size(hdr);
+ rc = fpga_load(dev, (void *)data, data_size);
}
break;
#if defined(CONFIG_FIT)
const void *fit_data;
if (fit_uname == NULL) {
- puts ("No FIT subimage unit name\n");
+ puts("No FIT subimage unit name\n");
return 1;
}
- if (!fit_check_format (fit_hdr)) {
- puts ("Bad FIT image format\n");
+ if (!fit_check_format(fit_hdr)) {
+ puts("Bad FIT image format\n");
return 1;
}
/* get fpga component image node offset */
- noffset = fit_image_get_node (fit_hdr, fit_uname);
+ noffset = fit_image_get_node(fit_hdr,
+ fit_uname);
if (noffset < 0) {
- printf ("Can't find '%s' FIT subimage\n", fit_uname);
+ printf("Can't find '%s' FIT subimage\n",
+ fit_uname);
return 1;
}
/* verify integrity */
- if (!fit_image_check_hashes (fit_hdr, noffset)) {
- puts ("Bad Data Hash\n");
+ if (!fit_image_check_hashes(fit_hdr, noffset)) {
+ puts("Bad Data Hash\n");
return 1;
}
/* get fpga subimage data address and length */
- if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) {
- puts ("Could not find fpga subimage data\n");
+ if (fit_image_get_data(fit_hdr, noffset,
+ &fit_data, &data_size)) {
+ puts("Fpga subimage data not found\n");
return 1;
}
- rc = fpga_load (dev, fit_data, data_size);
+ rc = fpga_load(dev, fit_data, data_size);
}
break;
#endif
default:
- puts ("** Unknown image type\n");
+ puts("** Unknown image type\n");
rc = FPGA_FAIL;
break;
}
break;
case FPGA_DUMP:
- rc = fpga_dump (dev, fpga_data, data_size);
+ rc = fpga_dump(dev, fpga_data, data_size);
break;
default:
- printf ("Unknown operation\n");
+ printf("Unknown operation\n");
return CMD_RET_USAGE;
}
- return (rc);
+ return rc;
}
/*
* Map op to supported operations. We don't use a table since we
* would just have to relocate it from flash anyway.
*/
-static int fpga_get_op (char *opstr)
+static int fpga_get_op(char *opstr)
{
int op = FPGA_NONE;
- if (!strcmp ("info", opstr)) {
+ if (!strcmp("info", opstr))
op = FPGA_INFO;
- } else if (!strcmp ("loadb", opstr)) {
+ else if (!strcmp("loadb", opstr))
op = FPGA_LOADB;
- } else if (!strcmp ("load", opstr)) {
+ else if (!strcmp("load", opstr))
op = FPGA_LOAD;
- } else if (!strcmp ("loadmk", opstr)) {
+ else if (!strcmp("loadmk", opstr))
op = FPGA_LOADMK;
- } else if (!strcmp ("dump", opstr)) {
+ else if (!strcmp("dump", opstr))
op = FPGA_DUMP;
- }
- if (op == FPGA_NONE) {
- printf ("Unknown fpga operation \"%s\"\n", opstr);
- }
+ if (op == FPGA_NONE)
+ printf("Unknown fpga operation \"%s\"\n", opstr);
+
return op;
}
-U_BOOT_CMD (fpga, 6, 1, do_fpga,
- "loadable FPGA image support",
- "[operation type] [device number] [image address] [image size]\n"
- "fpga operations:\n"
- " dump\t[dev]\t\t\tLoad device to memory buffer\n"
- " info\t[dev]\t\t\tlist known device information\n"
- " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
- " loadb\t[dev] [address] [size]\t"
- "Load device from bitstream buffer (Xilinx only)\n"
- " loadmk [dev] [address]\tLoad device generated with mkimage"
+U_BOOT_CMD(fpga, 6, 1, do_fpga,
+ "loadable FPGA image support",
+ "[operation type] [device number] [image address] [image size]\n"
+ "fpga operations:\n"
+ " dump\t[dev]\t\t\tLoad device to memory buffer\n"
+ " info\t[dev]\t\t\tlist known device information\n"
+ " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
+ " loadb\t[dev] [address] [size]\t"
+ "Load device from bitstream buffer (Xilinx only)\n"
+ " loadmk [dev] [address]\tLoad device generated with mkimage"
#if defined(CONFIG_FIT)
- "\n"
- "\tFor loadmk operating on FIT format uImage address must include\n"
- "\tsubimage unit name in the form of addr:<subimg_uname>"
+ "\n"
+ "\tFor loadmk operating on FIT format uImage address must include\n"
+ "\tsubimage unit name in the form of addr:<subimg_uname>"
#endif
);
--- /dev/null
+/*
+ * (C) Copyright 2009-2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on the mpc512x iim code:
+ * Copyright 2008 Silicon Turnkey Express, Inc.
+ * Martha Marx <mmarx@silicontkx.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fuse.h>
+#include <asm/errno.h>
+
+static int strtou32(const char *str, unsigned int base, u32 *result)
+{
+ char *ep;
+
+ *result = simple_strtoul(str, &ep, base);
+ if (ep == str || *ep != '\0')
+ return -EINVAL;
+
+ return 0;
+}
+
+static int confirm_prog(void)
+{
+ puts("Warning: Programming fuses is an irreversible operation!\n"
+ " This may brick your system.\n"
+ " Use this command only if you are sure of "
+ "what you are doing!\n"
+ "\nReally perform this fuse programming? <y/N>\n");
+
+ if (getc() == 'y') {
+ int c;
+
+ putc('y');
+ c = getc();
+ putc('\n');
+ if (c == '\r')
+ return 1;
+ }
+
+ puts("Fuse programming aborted\n");
+ return 0;
+}
+
+static int do_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ const char *op = argc >= 2 ? argv[1] : NULL;
+ int confirmed = argc >= 3 && !strcmp(argv[2], "-y");
+ u32 bank, word, cnt, val;
+ int ret, i;
+
+ argc -= 2 + confirmed;
+ argv += 2 + confirmed;
+
+ if (argc < 2 || strtou32(argv[0], 0, &bank) ||
+ strtou32(argv[1], 0, &word))
+ return CMD_RET_USAGE;
+
+ if (!strcmp(op, "read")) {
+ if (argc == 2)
+ cnt = 1;
+ else if (argc != 3 || strtou32(argv[2], 0, &cnt))
+ return CMD_RET_USAGE;
+
+ printf("Reading bank %u:\n", bank);
+ for (i = 0; i < cnt; i++, word++) {
+ if (!(i % 4))
+ printf("\nWord 0x%.8x:", word);
+
+ ret = fuse_read(bank, word, &val);
+ if (ret)
+ goto err;
+
+ printf(" %.8x", val);
+ }
+ putc('\n');
+ } else if (!strcmp(op, "sense")) {
+ if (argc == 2)
+ cnt = 1;
+ else if (argc != 3 || strtou32(argv[2], 0, &cnt))
+ return CMD_RET_USAGE;
+
+ printf("Sensing bank %u:\n", bank);
+ for (i = 0; i < cnt; i++, word++) {
+ if (!(i % 4))
+ printf("\nWord 0x%.8x:", word);
+
+ ret = fuse_sense(bank, word, &val);
+ if (ret)
+ goto err;
+
+ printf(" %.8x", val);
+ }
+ putc('\n');
+ } else if (!strcmp(op, "prog")) {
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ for (i = 2; i < argc; i++, word++) {
+ if (strtou32(argv[i], 16, &val))
+ return CMD_RET_USAGE;
+
+ printf("Programming bank %u word 0x%.8x to 0x%.8x...\n",
+ bank, word, val);
+ if (!confirmed && !confirm_prog())
+ return CMD_RET_FAILURE;
+ ret = fuse_prog(bank, word, val);
+ if (ret)
+ goto err;
+ }
+ } else if (!strcmp(op, "override")) {
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ for (i = 2; i < argc; i++, word++) {
+ if (strtou32(argv[i], 16, &val))
+ return CMD_RET_USAGE;
+
+ printf("Overriding bank %u word 0x%.8x with "
+ "0x%.8x...\n", bank, word, val);
+ ret = fuse_override(bank, word, val);
+ if (ret)
+ goto err;
+ }
+ } else {
+ return CMD_RET_USAGE;
+ }
+
+ return 0;
+
+err:
+ puts("ERROR\n");
+ return ret;
+}
+
+U_BOOT_CMD(
+ fuse, CONFIG_SYS_MAXARGS, 0, do_fuse,
+ "Fuse sub-system",
+ "read <bank> <word> [<cnt>] - read 1 or 'cnt' fuse words,\n"
+ " starting at 'word'\n"
+ "fuse sense <bank> <word> [<cnt>] - sense 1 or 'cnt' fuse words,\n"
+ " starting at 'word'\n"
+ "fuse prog [-y] <bank> <word> <hexval> [<hexval>...] - program 1 or\n"
+ " several fuse words, starting at 'word' (PERMANENT)\n"
+ "fuse override <bank> <word> <hexval> [<hexval>...] - override 1 or\n"
+ " several fuse words, starting at 'word'"
+);
ide_dev_desc[i].dev = i;
ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
ide_dev_desc[i].blksz = 0;
+ ide_dev_desc[i].log2blksz =
+ LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
ide_dev_desc[i].lba = 0;
ide_dev_desc[i].block_read = ide_read;
ide_dev_desc[i].block_write = ide_write;
/* assuming HD */
dev_desc->type = DEV_TYPE_HARDDISK;
dev_desc->blksz = ATA_BLOCKSIZE;
+ dev_desc->log2blksz = LOG2(dev_desc->blksz);
dev_desc->lun = 0; /* just to fill something in... */
#if 0 /* only used to test the powersaving mode,
dev_desc->lun = 0;
dev_desc->lba = 0;
dev_desc->blksz = 0;
+ dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz));
dev_desc->type = iobuf[0] & 0x1f;
if ((iobuf[1] & 0x80) == 0x80)
dev_desc->blksz = ((unsigned long) iobuf[4] << 24) +
((unsigned long) iobuf[5] << 16) +
((unsigned long) iobuf[6] << 8) + ((unsigned long) iobuf[7]);
+ dev_desc->log2blksz = LOG2(dev_desc->blksz);
#ifdef CONFIG_LBA48
/* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
dev_desc->lba48 = 0;
/*
- * (C) Copyright 2000-2010
+ * (C) Copyright 2000-2013
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
static int do_env_grep(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
- ENTRY *match;
- unsigned char matched[env_htab.size / 8];
- int rcode = 1, arg = 1, idx;
+ char *res = NULL;
+ int len, grep_how, grep_what;
if (argc < 2)
return CMD_RET_USAGE;
- memset(matched, 0, env_htab.size / 8);
+ grep_how = H_MATCH_SUBSTR; /* default: substring search */
+ grep_what = H_MATCH_BOTH; /* default: grep names and values */
- while (arg <= argc) {
- idx = 0;
- while ((idx = hstrstr_r(argv[arg], idx, &match, &env_htab))) {
- if (!(matched[idx / 8] & (1 << (idx & 7)))) {
- puts(match->key);
- puts("=");
- puts(match->data);
- puts("\n");
+ while (argc > 1 && **(argv + 1) == '-') {
+ char *arg = *++argv;
+
+ --argc;
+ while (*++arg) {
+ switch (*arg) {
+#ifdef CONFIG_REGEX
+ case 'e': /* use regex matching */
+ grep_how = H_MATCH_REGEX;
+ break;
+#endif
+ case 'n': /* grep for name */
+ grep_what = H_MATCH_KEY;
+ break;
+ case 'v': /* grep for value */
+ grep_what = H_MATCH_DATA;
+ break;
+ case 'b': /* grep for both */
+ grep_what = H_MATCH_BOTH;
+ break;
+ case '-':
+ goto DONE;
+ default:
+ return CMD_RET_USAGE;
}
- matched[idx / 8] |= 1 << (idx & 7);
- rcode = 0;
}
- arg++;
}
- return rcode;
+DONE:
+ len = hexport_r(&env_htab, '\n',
+ flag | grep_what | grep_how,
+ &res, 0, argc, argv);
+
+ if (len > 0) {
+ puts(res);
+ free(res);
+ }
+
+ if (len < 2)
+ return 1;
+
+ return 0;
}
#endif
#endif /* CONFIG_SPL_BUILD */
return setenv(varname, str);
}
+ulong getenv_hex(const char *varname, ulong default_val)
+{
+ const char *s;
+ ulong value;
+ char *endp;
+
+ s = getenv(varname);
+ if (s)
+ value = simple_strtoul(s, &endp, 16);
+ if (!s || endp == s)
+ return default_val;
+
+ return value;
+}
+
#ifndef CONFIG_SPL_BUILD
static int do_env_set(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
argv++;
if (sep) { /* export as text file */
- len = hexport_r(&env_htab, sep, 0, &addr, size, argc, argv);
+ len = hexport_r(&env_htab, sep,
+ H_MATCH_KEY | H_MATCH_IDENT,
+ &addr, size, argc, argv);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
else /* export as raw binary data */
res = addr;
- len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, argc, argv);
+ len = hexport_r(&env_htab, '\0',
+ H_MATCH_KEY | H_MATCH_IDENT,
+ &res, ENV_SIZE, argc, argv);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
return 1;
"env flags - print variables that have non-default flags\n"
#endif
#if defined(CONFIG_CMD_GREPENV)
- "env grep string [...] - search environment\n"
+#ifdef CONFIG_REGEX
+ "env grep [-e] [-n | -v | -b] string [...] - search environment\n"
+#else
+ "env grep [-n | -v | -b] string [...] - search environment\n"
+#endif
#endif
#if defined(CONFIG_CMD_IMPORTENV)
"env import [-d] [-t | -b | -c] addr [size] - import environment\n"
U_BOOT_CMD_COMPLETE(
grepenv, CONFIG_SYS_MAXARGS, 0, do_env_grep,
"search environment variables",
- "string ...\n"
- " - list environment name=value pairs matching 'string'",
+#ifdef CONFIG_REGEX
+ "[-e] [-n | -v | -b] string ...\n"
+#else
+ "[-n | -v | -b] string ...\n"
+#endif
+ " - list environment name=value pairs matching 'string'\n"
+#ifdef CONFIG_REGEX
+ " \"-e\": enable regular expressions;\n"
+#endif
+ " \"-n\": search variable names; \"-v\": search values;\n"
+ " \"-b\": search both names and values (default)",
var_complete
);
#endif
return do_ls(cmdtp, flag, argc, argv, FS_TYPE_SANDBOX);
}
+static int do_sandbox_save(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ return do_save(cmdtp, flag, argc, argv, FS_TYPE_SANDBOX, 16);
+}
+
static cmd_tbl_t cmd_sandbox_sub[] = {
- U_BOOT_CMD_MKENT(load, 3, 0, do_sandbox_load, "", ""),
+ U_BOOT_CMD_MKENT(load, 7, 0, do_sandbox_load, "", ""),
U_BOOT_CMD_MKENT(ls, 3, 0, do_sandbox_ls, "", ""),
+ U_BOOT_CMD_MKENT(save, 6, 0, do_sandbox_save, "", ""),
};
static int do_sandbox(cmd_tbl_t *cmdtp, int flag, int argc,
}
U_BOOT_CMD(
- sb, 6, 1, do_sandbox,
+ sb, 8, 1, do_sandbox,
"Miscellaneous sandbox commands",
- "load host <addr> <filename> [<bytes> <offset>] - load a file from host\n"
- "sb ls host <filename> - save a file to host"
+ "load host <dev> <addr> <filename> [<bytes> <offset>] - "
+ "load a file from host\n"
+ "sb ls host <filename> - list files on host\n"
+ "sb save host <dev> <filename> <addr> <bytes> [<offset>] - "
+ "save a file to host\n"
);
sata_dev_desc[i].type = DEV_TYPE_HARDDISK;
sata_dev_desc[i].lba = 0;
sata_dev_desc[i].blksz = 512;
+ sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz);
sata_dev_desc[i].block_read = sata_read;
sata_dev_desc[i].block_write = sata_write;
scsi_dev_desc[i].lun=0xff;
scsi_dev_desc[i].lba=0;
scsi_dev_desc[i].blksz=0;
+ scsi_dev_desc[i].log2blksz =
+ LOG2_INVALID(typeof(scsi_dev_desc[i].log2blksz));
scsi_dev_desc[i].type=DEV_TYPE_UNKNOWN;
scsi_dev_desc[i].vendor[0]=0;
scsi_dev_desc[i].product[0]=0;
}
scsi_dev_desc[scsi_max_devs].lba=capacity;
scsi_dev_desc[scsi_max_devs].blksz=blksz;
+ scsi_dev_desc[scsi_max_devs].log2blksz =
+ LOG2(scsi_dev_desc[scsi_max_devs].blksz);
scsi_dev_desc[scsi_max_devs].type=perq;
init_part(&scsi_dev_desc[scsi_max_devs]);
removable:
/*
* Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2013 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
}
}
+#ifdef CONFIG_REGEX
+
+#include <slre.h>
+
+#define SLRE_BUFSZ 16384
+#define SLRE_PATSZ 4096
+
+/*
+ * memstr - Find the first substring in memory
+ * @s1: The string to be searched
+ * @s2: The string to search for
+ *
+ * Similar to and based on strstr(),
+ * but strings do not need to be NUL terminated.
+ */
+static char *memstr(const char *s1, int l1, const char *s2, int l2)
+{
+ if (!l2)
+ return (char *)s1;
+
+ while (l1 >= l2) {
+ l1--;
+ if (!memcmp(s1, s2, l2))
+ return (char *)s1;
+ s1++;
+ }
+ return NULL;
+}
+
+static char *substitute(char *string, /* string buffer */
+ int *slen, /* current string length */
+ int ssize, /* string bufer size */
+ const char *old,/* old (replaced) string */
+ int olen, /* length of old string */
+ const char *new,/* new (replacement) string */
+ int nlen) /* length of new string */
+{
+ char *p = memstr(string, *slen, old, olen);
+
+ if (p == NULL)
+ return NULL;
+
+ debug("## Match at pos %ld: match len %d, subst len %d\n",
+ (long)(p - string), olen, nlen);
+
+ /* make sure replacement matches */
+ if (*slen + nlen - olen > ssize) {
+ printf("## error: substitution buffer overflow\n");
+ return NULL;
+ }
+
+ /* move tail if needed */
+ if (olen != nlen) {
+ int tail, len;
+
+ len = (olen > nlen) ? olen : nlen;
+
+ tail = ssize - (p + len - string);
+
+ debug("## tail len %d\n", tail);
+
+ memmove(p + nlen, p + olen, tail);
+ }
+
+ /* insert substitue */
+ memcpy(p, new, nlen);
+
+ *slen += nlen - olen;
+
+ return p + nlen;
+}
+
+/*
+ * Perform regex operations on a environment variable
+ *
+ * Returns 0 if OK, 1 in case of errors.
+ */
+static int regex_sub(const char *name,
+ const char *r, const char *s, const char *t,
+ int global)
+{
+ struct slre slre;
+ char data[SLRE_BUFSZ];
+ char *datap = data;
+ const char *value;
+ int res, len, nlen, loop;
+
+ if (name == NULL)
+ return 1;
+
+ if (slre_compile(&slre, r) == 0) {
+ printf("Error compiling regex: %s\n", slre.err_str);
+ return 1;
+ }
+
+ if (t == NULL) {
+ value = getenv(name);
+
+ if (value == NULL) {
+ printf("## Error: variable \"%s\" not defined\n", name);
+ return 1;
+ }
+ t = value;
+ }
+
+ debug("REGEX on %s=%s\n", name, t);
+ debug("REGEX=\"%s\", SUBST=\"%s\", GLOBAL=%d\n",
+ r, s ? s : "<NULL>", global);
+
+ len = strlen(t);
+ if (len + 1 > SLRE_BUFSZ) {
+ printf("## error: subst buffer overflow: have %d, need %d\n",
+ SLRE_BUFSZ, len + 1);
+ return 1;
+ }
+
+ strcpy(data, t);
+
+ if (s == NULL)
+ nlen = 0;
+ else
+ nlen = strlen(s);
+
+ for (loop = 0;; loop++) {
+ struct cap caps[slre.num_caps + 2];
+ char nbuf[SLRE_PATSZ];
+ const char *old;
+ char *np;
+ int i, olen;
+
+ (void) memset(caps, 0, sizeof(caps));
+
+ res = slre_match(&slre, datap, len, caps);
+
+ debug("Result: %d\n", res);
+
+ for (i = 0; i < slre.num_caps; i++) {
+ if (caps[i].len > 0) {
+ debug("Substring %d: [%.*s]\n", i,
+ caps[i].len, caps[i].ptr);
+ }
+ }
+
+ if (res == 0) {
+ if (loop == 0) {
+ printf("%s: No match\n", t);
+ return 1;
+ } else {
+ break;
+ }
+ }
+
+ debug("## MATCH ## %s\n", data);
+
+ if (s == NULL) {
+ printf("%s=%s\n", name, t);
+ return 1;
+ }
+
+ old = caps[0].ptr;
+ olen = caps[0].len;
+
+ if (nlen + 1 >= SLRE_PATSZ) {
+ printf("## error: pattern buffer overflow: have %d, need %d\n",
+ SLRE_BUFSZ, nlen + 1);
+ return 1;
+ }
+ strcpy(nbuf, s);
+
+ debug("## SUBST(1) ## %s\n", nbuf);
+
+ /*
+ * Handle back references
+ *
+ * Support for \0 ... \9, where \0 is the
+ * whole matched pattern (similar to &).
+ *
+ * Implementation is a bit simpleminded as
+ * backrefs are substituted sequentially, one
+ * by one. This will lead to somewhat
+ * unexpected results if the replacement
+ * strings contain any \N strings then then
+ * may get substitued, too. We accept this
+ * restriction for the sake of simplicity.
+ */
+ for (i = 0; i < 10; ++i) {
+ char backref[2] = {
+ '\\',
+ '0',
+ };
+
+ if (caps[i].len == 0)
+ break;
+
+ backref[1] += i;
+
+ debug("## BACKREF %d: replace \"%.*s\" by \"%.*s\" in \"%s\"\n",
+ i,
+ 2, backref,
+ caps[i].len, caps[i].ptr,
+ nbuf);
+
+ for (np = nbuf;;) {
+ char *p = memstr(np, nlen, backref, 2);
+
+ if (p == NULL)
+ break;
+
+ np = substitute(np, &nlen,
+ SLRE_PATSZ,
+ backref, 2,
+ caps[i].ptr, caps[i].len);
+
+ if (np == NULL)
+ return 1;
+ }
+ }
+ debug("## SUBST(2) ## %s\n", nbuf);
+
+ datap = substitute(datap, &len, SLRE_BUFSZ,
+ old, olen,
+ nbuf, nlen);
+
+ if (datap == NULL)
+ return 1;
+
+ debug("## REMAINDER: %s\n", datap);
+
+ debug("## RESULT: %s\n", data);
+
+ if (!global)
+ break;
+ }
+ debug("## FINAL (now setenv()) : %s\n", data);
+
+ printf("%s=%s\n", name, data);
+
+ return setenv(name, data);
+}
+#endif
+
static int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong a, b;
ulong value;
int w;
- /* Validate arguments */
- if (argc != 5 && argc != 3)
- return CMD_RET_USAGE;
- if (argc == 5 && strlen(argv[3]) != 1)
+ /*
+ * We take 3, 5, or 6 arguments:
+ * 3 : setexpr name value
+ * 5 : setexpr name val1 op val2
+ * setexpr name [g]sub r s
+ * 6 : setexpr name [g]sub r s t
+ */
+
+ /* > 6 already tested by max command args */
+ if ((argc < 3) || (argc == 4))
return CMD_RET_USAGE;
w = cmd_get_data_size(argv[0], 4);
a = get_arg(argv[2], w);
+ /* plain assignment: "setexpr name value" */
if (argc == 3) {
setenv_hex(argv[1], a);
-
return 0;
}
+ /* 5 or 6 args (6 args only with [g]sub) */
+#ifdef CONFIG_REGEX
+ /*
+ * rexep handling: "setexpr name [g]sub r s [t]"
+ * with 5 args, "t" will be NULL
+ */
+ if (strcmp(argv[2], "gsub") == 0)
+ return regex_sub(argv[1], argv[3], argv[4], argv[5], 1);
+
+ if (strcmp(argv[2], "sub") == 0)
+ return regex_sub(argv[1], argv[3], argv[4], argv[5], 0);
+#endif
+
+ /* standard operators: "setexpr name val1 op val2" */
+ if (argc != 5)
+ return CMD_RET_USAGE;
+
+ if (strlen(argv[3]) != 1)
+ return CMD_RET_USAGE;
+
b = get_arg(argv[4], w);
switch (argv[3][0]) {
}
U_BOOT_CMD(
- setexpr, 5, 0, do_setexpr,
+ setexpr, 6, 0, do_setexpr,
"set environment variable as the result of eval expression",
"[.b, .w, .l] name [*]value1 <op> [*]value2\n"
" - set environment variable 'name' to the result of the evaluated\n"
- " express specified by <op>. <op> can be &, |, ^, +, -, *, /, %\n"
+ " expression specified by <op>. <op> can be &, |, ^, +, -, *, /, %\n"
" size argument is only meaningful if value1 and/or value2 are\n"
" memory addresses (*)\n"
- "setexpr[.b, .w, .l] name *value\n"
- " - load a memory address into a variable"
+ "setexpr[.b, .w, .l] name [*]value\n"
+ " - load a value into a variable"
+#ifdef CONFIG_REGEX
+ "\n"
+ "setexpr name gsub r s [t]\n"
+ " - For each substring matching the regular expression <r> in the\n"
+ " string <t>, substitute the string <s>. The result is\n"
+ " assigned to <name>. If <t> is not supplied, use the old\n"
+ " value of <name>\n"
+ "setexpr name sub r s [t]\n"
+ " - Just like gsub(), but replace only the first matching substring"
+#endif
);
#include <image.h>
#include <malloc.h>
#include <asm/byteorder.h>
+#include <asm/io.h>
#if defined(CONFIG_8xx)
#include <mpc8xx.h>
#endif
source (ulong addr, const char *fit_uname)
{
ulong len;
- image_header_t *hdr;
+ const image_header_t *hdr;
ulong *data;
int verify;
+ void *buf;
#if defined(CONFIG_FIT)
const void* fit_hdr;
int noffset;
verify = getenv_yesno ("verify");
- switch (genimg_get_format ((void *)addr)) {
+ buf = map_sysmem(addr, 0);
+ switch (genimg_get_format(buf)) {
case IMAGE_FORMAT_LEGACY:
- hdr = (image_header_t *)addr;
+ hdr = buf;
if (!image_check_magic (hdr)) {
puts ("Bad magic number\n");
return 1;
}
- fit_hdr = (const void *)addr;
+ fit_hdr = buf;
if (!fit_check_format (fit_hdr)) {
puts ("Bad FIT image format\n");
return 1;
#include <search.h>
#include <errno.h>
+#if defined(CONFIG_ENV_SIZE_REDUND) && \
+ (CONFIG_ENV_SIZE_REDUND != CONFIG_ENV_SIZE)
+#error CONFIG_ENV_SIZE_REDUND should be the same as CONFIG_ENV_SIZE
+#endif
+
char *env_name_spec = "MMC";
#ifdef ENV_IS_EMBEDDED
#define CONFIG_ENV_OFFSET 0
#endif
-__weak int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr)
+__weak int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
{
*env_addr = CONFIG_ENV_OFFSET;
+#ifdef CONFIG_ENV_OFFSET_REDUND
+ if (copy)
+ *env_addr = CONFIG_ENV_OFFSET_REDUND;
+#endif
return 0;
}
return (n == blk_cnt) ? 0 : -1;
}
+#ifdef CONFIG_ENV_OFFSET_REDUND
+static unsigned char env_flags;
+#endif
+
int saveenv(void)
{
ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1);
char *res;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
u32 offset;
- int ret;
+ int ret, copy = 0;
if (init_mmc_for_env(mmc))
return 1;
- if (mmc_get_env_addr(mmc, &offset)) {
- ret = 1;
- goto fini;
- }
-
res = (char *)&env_new->data;
len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
if (len < 0) {
}
env_new->crc = crc32(0, &env_new->data[0], ENV_SIZE);
- printf("Writing to MMC(%d)... ", CONFIG_SYS_MMC_ENV_DEV);
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+ env_new->flags = ++env_flags; /* increase the serial */
+
+ if (gd->env_valid == 1)
+ copy = 1;
+#endif
+
+ if (mmc_get_env_addr(mmc, copy, &offset)) {
+ ret = 1;
+ goto fini;
+ }
+
+ printf("Writing to %sMMC(%d)... ", copy ? "redundant " : "",
+ CONFIG_SYS_MMC_ENV_DEV);
if (write_env(mmc, CONFIG_ENV_SIZE, offset, (u_char *)env_new)) {
puts("failed\n");
ret = 1;
puts("done\n");
ret = 0;
+#ifdef CONFIG_ENV_OFFSET_REDUND
+ gd->env_valid = gd->env_valid == 2 ? 1 : 2;
+#endif
+
fini:
fini_mmc_for_env(mmc);
return ret;
return (n == blk_cnt) ? 0 : -1;
}
+#ifdef CONFIG_ENV_OFFSET_REDUND
+void env_relocate_spec(void)
+{
+#if !defined(ENV_IS_EMBEDDED)
+ struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+ u32 offset1, offset2;
+ int read1_fail = 0, read2_fail = 0;
+ int crc1_ok = 0, crc2_ok = 0;
+ env_t *ep, *tmp_env1, *tmp_env2;
+ int ret;
+
+ tmp_env1 = (env_t *)malloc(CONFIG_ENV_SIZE);
+ tmp_env2 = (env_t *)malloc(CONFIG_ENV_SIZE);
+ if (tmp_env1 == NULL || tmp_env2 == NULL) {
+ puts("Can't allocate buffers for environment\n");
+ ret = 1;
+ goto err;
+ }
+
+ if (init_mmc_for_env(mmc)) {
+ ret = 1;
+ goto err;
+ }
+
+ if (mmc_get_env_addr(mmc, 0, &offset1) ||
+ mmc_get_env_addr(mmc, 1, &offset2)) {
+ ret = 1;
+ goto fini;
+ }
+
+ read1_fail = read_env(mmc, CONFIG_ENV_SIZE, offset1, tmp_env1);
+ read2_fail = read_env(mmc, CONFIG_ENV_SIZE, offset2, tmp_env2);
+
+ if (read1_fail && read2_fail)
+ puts("*** Error - No Valid Environment Area found\n");
+ else if (read1_fail || read2_fail)
+ puts("*** Warning - some problems detected "
+ "reading environment; recovered successfully\n");
+
+ crc1_ok = !read1_fail &&
+ (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc);
+ crc2_ok = !read2_fail &&
+ (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc);
+
+ if (!crc1_ok && !crc2_ok) {
+ ret = 1;
+ goto fini;
+ } else if (crc1_ok && !crc2_ok) {
+ gd->env_valid = 1;
+ } else if (!crc1_ok && crc2_ok) {
+ gd->env_valid = 2;
+ } else {
+ /* both ok - check serial */
+ if (tmp_env1->flags == 255 && tmp_env2->flags == 0)
+ gd->env_valid = 2;
+ else if (tmp_env2->flags == 255 && tmp_env1->flags == 0)
+ gd->env_valid = 1;
+ else if (tmp_env1->flags > tmp_env2->flags)
+ gd->env_valid = 1;
+ else if (tmp_env2->flags > tmp_env1->flags)
+ gd->env_valid = 2;
+ else /* flags are equal - almost impossible */
+ gd->env_valid = 1;
+ }
+
+ free(env_ptr);
+
+ if (gd->env_valid == 1)
+ ep = tmp_env1;
+ else
+ ep = tmp_env2;
+
+ env_flags = ep->flags;
+ env_import((char *)ep, 0);
+ ret = 0;
+
+fini:
+ fini_mmc_for_env(mmc);
+err:
+ if (ret)
+ set_default_env(NULL);
+
+ free(tmp_env1);
+ free(tmp_env2);
+#endif
+}
+#else /* ! CONFIG_ENV_OFFSET_REDUND */
void env_relocate_spec(void)
{
#if !defined(ENV_IS_EMBEDDED)
goto err;
}
- if (mmc_get_env_addr(mmc, &offset)) {
+ if (mmc_get_env_addr(mmc, 0, &offset)) {
ret = 1;
goto fini;
}
set_default_env(NULL);
#endif
}
+#endif /* CONFIG_ENV_OFFSET_REDUND */
flash_info_t *info_first = addr2info (addr);
flash_info_t *info_last = addr2info (end );
flash_info_t *info;
+ __maybe_unused char *src_orig = src;
+ __maybe_unused char *addr_orig = (char *)addr;
+ __maybe_unused ulong cnt_orig = cnt;
if (cnt == 0) {
return (ERR_OK);
addr += len;
src += len;
}
+
+#if defined(CONFIG_FLASH_VERIFY)
+ if (memcmp(src_orig, addr_orig, cnt_orig)) {
+ printf("\nVerify failed!\n");
+ return ERR_PROG_ERROR;
+ }
+#endif /* CONFIG_SYS_FLASH_VERIFY_AFTER_WRITE */
+
return (ERR_OK);
#endif /* CONFIG_SPD823TS */
}
#include <fdtdec.h>
#endif
-#ifdef CONFIG_OF_LIBFDT
-#include <fdt_support.h>
-#endif /* CONFIG_OF_LIBFDT */
-
#include <post.h>
#include <linux/ctype.h>
#include <menu.h>
bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop");
-#if defined CONFIG_OF_CONTROL
- set_working_fdt_addr((void *)gd->fdt_blob);
-#endif /* CONFIG_OF_CONTROL */
-
#ifdef CONFIG_BOOTCOUNT_LIMIT
bootcount = bootcount_load();
bootcount++;
/* Define board data structure */
static bd_t bdata __attribute__ ((section(".data")));
-inline void hang(void)
-{
- puts("### ERROR ### Please RESET the board ###\n");
- for (;;)
- ;
-}
-
/*
* Default function to determine if u-boot or the OS should
* be started. This implementation always returns 1.
*capacity, *blksz);
dev_desc->lba = *capacity;
dev_desc->blksz = *blksz;
+ dev_desc->log2blksz = LOG2(dev_desc->blksz);
dev_desc->type = perq;
USB_STOR_PRINTF(" address %d\n", dev_desc->target);
USB_STOR_PRINTF("partype: %d\n", dev_desc->part_type);
CPPFLAGS += -DCONFIG_SPL_PAD_TO=$(CONFIG_SPL_PAD_TO)
endif
+ifneq ($(CONFIG_UBOOT_PAD_TO),)
+CPPFLAGS += -DCONFIG_UBOOT_PAD_TO=$(CONFIG_UBOOT_PAD_TO)
+endif
+
ifeq ($(CONFIG_SPL_BUILD),y)
CPPFLAGS += -DCONFIG_SPL_BUILD
endif
# Does this architecture support generic board init?
ifeq ($(__HAVE_ARCH_GENERIC_BOARD),)
ifneq ($(CONFIG_SYS_GENERIC_BOARD),)
-$(error Your architecture does not support generic board. Please undefined \
-CONFIG_SYS_GENERIC_BOARD in your board config file)
+CHECK_GENERIC_BOARD = $(error Your architecture does not support generic board. \
+Please undefined CONFIG_SYS_GENERIC_BOARD in your board config file)
endif
endif
static int test_block_type(unsigned char *buffer)
{
+ int slot;
+ struct dos_partition *p;
+
if((buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) ||
(buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) ) {
return (-1);
} /* no DOS Signature at all */
- if (strncmp((char *)&buffer[DOS_PBR_FSTYPE_OFFSET],"FAT",3)==0 ||
- strncmp((char *)&buffer[DOS_PBR32_FSTYPE_OFFSET],"FAT32",5)==0) {
- return DOS_PBR; /* is PBR */
+ p = (struct dos_partition *)&buffer[DOS_PART_TBL_OFFSET];
+ for (slot = 0; slot < 3; slot++) {
+ if (p->boot_ind != 0 && p->boot_ind != 0x80) {
+ if (!slot &&
+ (strncmp((char *)&buffer[DOS_PBR_FSTYPE_OFFSET],
+ "FAT", 3) == 0 ||
+ strncmp((char *)&buffer[DOS_PBR32_FSTYPE_OFFSET],
+ "FAT32", 5) == 0)) {
+ return DOS_PBR; /* is PBR */
+ } else {
+ return -1;
+ }
+ }
}
return DOS_MBR; /* Is MBR */
}
void print_part_efi(block_dev_desc_t * dev_desc)
{
- ALLOC_CACHE_ALIGN_BUFFER(gpt_header, gpt_head, 1);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
gpt_entry *gpt_pte = NULL;
int i = 0;
char uuid[37];
int get_partition_info_efi(block_dev_desc_t * dev_desc, int part,
disk_partition_t * info)
{
- ALLOC_CACHE_ALIGN_BUFFER(gpt_header, gpt_head, 1);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
gpt_entry *gpt_pte = NULL;
/* "part" argument must be at least 1 */
/* The ending LBA is inclusive, to calculate size, add 1 to it */
info->size = ((u64)le64_to_cpu(gpt_pte[part - 1].ending_lba) + 1)
- info->start;
- info->blksz = GPT_BLOCK_SIZE;
+ info->blksz = dev_desc->blksz;
sprintf((char *)info->name, "%s",
print_efiname(&gpt_pte[part - 1]));
int test_part_efi(block_dev_desc_t * dev_desc)
{
- ALLOC_CACHE_ALIGN_BUFFER(legacy_mbr, legacymbr, 1);
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, dev_desc->blksz);
/* Read legacy MBR from block 0 and validate it */
if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *)legacymbr) != 1)
int write_gpt_table(block_dev_desc_t *dev_desc,
gpt_header *gpt_h, gpt_entry *gpt_e)
{
- const int pte_blk_num = (gpt_h->num_partition_entries
- * sizeof(gpt_entry)) / dev_desc->blksz;
-
+ const int pte_blk_cnt = BLOCK_CNT((gpt_h->num_partition_entries
+ * sizeof(gpt_entry)), dev_desc);
u32 calc_crc32;
u64 val;
if (dev_desc->block_write(dev_desc->dev, 1, 1, gpt_h) != 1)
goto err;
- if (dev_desc->block_write(dev_desc->dev, 2, pte_blk_num, gpt_e)
- != pte_blk_num)
+ if (dev_desc->block_write(dev_desc->dev, 2, pte_blk_cnt, gpt_e)
+ != pte_blk_cnt)
goto err;
/* recalculate the values for the Second GPT Header */
if (dev_desc->block_write(dev_desc->dev,
le32_to_cpu(gpt_h->last_usable_lba + 1),
- pte_blk_num, gpt_e) != pte_blk_num)
+ pte_blk_cnt, gpt_e) != pte_blk_cnt)
goto err;
if (dev_desc->block_write(dev_desc->dev,
{
int ret;
- gpt_header *gpt_h = calloc(1, sizeof(gpt_header));
+ gpt_header *gpt_h = calloc(1, PAD_TO_BLOCKSIZE(sizeof(gpt_header),
+ dev_desc));
+ gpt_entry *gpt_e;
+
if (gpt_h == NULL) {
printf("%s: calloc failed!\n", __func__);
return -1;
}
- gpt_entry *gpt_e = calloc(GPT_ENTRY_NUMBERS, sizeof(gpt_entry));
+ gpt_e = calloc(1, PAD_TO_BLOCKSIZE(GPT_ENTRY_NUMBERS
+ * sizeof(gpt_entry),
+ dev_desc));
if (gpt_e == NULL) {
printf("%s: calloc failed!\n", __func__);
free(gpt_h);
static gpt_entry *alloc_read_gpt_entries(block_dev_desc_t * dev_desc,
gpt_header * pgpt_head)
{
- size_t count = 0;
+ size_t count = 0, blk_cnt;
gpt_entry *pte = NULL;
if (!dev_desc || !pgpt_head) {
/* Allocate memory for PTE, remember to FREE */
if (count != 0) {
- pte = memalign(ARCH_DMA_MINALIGN, count);
+ pte = memalign(ARCH_DMA_MINALIGN,
+ PAD_TO_BLOCKSIZE(count, dev_desc));
}
if (count == 0 || pte == NULL) {
}
/* Read GPT Entries from device */
+ blk_cnt = BLOCK_CNT(count, dev_desc);
if (dev_desc->block_read (dev_desc->dev,
le64_to_cpu(pgpt_head->partition_entry_lba),
- (lbaint_t) (count / GPT_BLOCK_SIZE), pte)
- != (count / GPT_BLOCK_SIZE)) {
+ (lbaint_t) (blk_cnt), pte)
+ != blk_cnt) {
printf("*** ERROR: Can't read GPT Entries ***\n");
free(pte);
iso_val_entry_t *pve = (iso_val_entry_t *)tmpbuf;
iso_init_def_entry_t *pide;
+ if (dev_desc->blksz != CD_SECTSIZE)
+ return -1;
+
/* the first sector (sector 0x10) must be a primary volume desc */
blkaddr=PVD_OFFSET;
if (dev_desc->block_read (dev_desc->dev, PVD_OFFSET, 1, (ulong *) tmpbuf) != 1)
and then flash image.bin onto your board.
-You cannot use both of these options at the same time.
+If CONFIG_OF_HOSTFILE is defined, then it will be read from a file on
+startup. This is only useful for sandbox. Use the -d flag to U-Boot to
+specify the file to read.
+
+You cannot use more than one of these options at the same time.
If you wish to put the fdt at a different address in memory, you can
define the "fdtcontroladdr" environment variable. This is the hex
--- /dev/null
+Driver implementing the fuse API for Freescale's IC Identification Module (IIM)
+
+This IP can be found on the following SoCs:
+ - MPC512x,
+ - i.MX25,
+ - i.MX27,
+ - i.MX31,
+ - i.MX35,
+ - i.MX51,
+ - i.MX53.
+
+The section numbers in this file refer to the i.MX25 Reference Manual.
+
+A fuse word contains 8 fuse bit slots, as explained in 30.4.2.2.1.
+
+A bank contains 256 fuse word slots, as shown by the memory map in 30.3.1.
+
+Some fuse bit or word slots may not have the corresponding fuses actually
+implemented in the fusebox.
+
+See the README files of the SoCs using this driver in order to know the
+conventions used by U-Boot to store some specific data in the fuses, e.g. MAC
+addresses.
+
+Fuse operations:
+
+ Read
+ Read operations are implemented as read accesses to the shadow registers,
+ using "Word y of Bank x" from the register summary in 30.3.2. This is
+ explained in detail in 30.4.5.1.
+
+ Sense
+ Sense operations are implemented as explained in 30.4.5.2.
+
+ Program
+ Program operations are implemented as explained in 30.4.5.3. Following
+ this operation, the shadow registers are reloaded by the hardware (not
+ immediately, but this does not make any difference for a user reading
+ these registers).
+
+ Override
+ Override operations are implemented as write accesses to the shadow
+ registers, as explained in 30.4.5.4.
+
+Configuration:
+
+ CONFIG_FSL_IIM
+ Define this to enable the fsl_iim driver.
--- /dev/null
+Fuse API functions and commands
+
+The fuse API allows to control a fusebox and how it is used by the upper
+hardware layers.
+
+A fuse corresponds to a single non-volatile memory bit that can be programmed
+(i.e. blown, set to 1) only once. The programming operation is irreversible. A
+fuse that has not been programmed reads 0.
+
+Fuses can be used by SoCs to store various permanent configuration and data,
+e.g. boot configuration, security configuration, MAC addresses, etc.
+
+A fuse word is the smallest group of fuses that can be read at once from the
+fusebox control IP registers. This is limited to 32 bits with the current API.
+
+A fuse bank is the smallest group of fuse words having a common ID, as defined
+by each SoC.
+
+Upon startup, the fusebox control IP reads the fuse values and stores them to a
+volatile shadow cache.
+
+See the README files of the drivers implementing this API in order to know the
+SoC- and implementation-specific details.
+
+Functions / commands:
+
+ int fuse_read(u32 bank, u32 word, u32 *val);
+ fuse read <bank> <word> [<cnt>]
+ Read fuse words from the shadow cache.
+
+ int fuse_sense(u32 bank, u32 word, u32 *val);
+ fuse sense <bank> <word> [<cnt>]
+ Sense - i.e. read directly from the fusebox, skipping the shadow cache -
+ fuse words. This operation does not update the shadow cache.
+
+ This is useful to know the true value of fuses if an override has been
+ performed (see below).
+
+ int fuse_prog(u32 bank, u32 word, u32 val);
+ fuse prog [-y] <bank> <word> <hexval> [<hexval>...]
+ Program fuse words. This operation directly affects the fusebox and is
+ irreversible. The shadow cache is updated accordingly or not, depending on
+ each IP.
+
+ Only the bits to be programmed should be set in the input value (i.e. for
+ fuse bits that have already been programmed and hence should be left
+ unchanged by a further programming, it is preferable to clear the
+ corresponding bits in the input value in order not to perform a new
+ hardware programming operation on these fuse bits).
+
+ int fuse_override(u32 bank, u32 word, u32 val);
+ fuse override <bank> <word> <hexval> [<hexval>...]
+ Override fuse words in the shadow cache.
+
+ The fusebox is unaffected, so following this operation, the shadow cache
+ may differ from the fusebox values. Read or sense operations can then be
+ used to get the values from the shadow cache or from the fusebox.
+
+ This is useful to change the behaviors linked to some cached fuse values,
+ either because this is needed only temporarily, or because some of the
+ fuses have already been programmed or are locked (if the SoC allows to
+ override a locked fuse).
+
+Configuration:
+
+ CONFIG_CMD_FUSE
+ Define this to enable the fuse commands.
--- /dev/null
+U-Boot for Freescale i.MX25
+
+This file contains information for the port of U-Boot to the Freescale i.MX25
+SoC.
+
+1. CONVENTIONS FOR FUSE ASSIGNMENTS
+-----------------------------------
+
+1.1 MAC Address: It is stored in the words 26 to 31 of fuse bank 0, using the
+ natural MAC byte order (i.e. MSB first).
--- /dev/null
+U-Boot for Freescale i.MX27
+
+This file contains information for the port of U-Boot to the Freescale i.MX27
+SoC.
+
+1. CONVENTIONS FOR FUSE ASSIGNMENTS
+-----------------------------------
+
+1.1 MAC Address: It is stored in the words 4 to 9 of fuse bank 0, using the
+ reversed MAC byte order (i.e. LSB first).
This option should be enabled for boards having a SYS_ON_OFF_CTL signal
connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
reference designs.
+
+2. CONVENTIONS FOR FUSE ASSIGNMENTS
+-----------------------------------
+
+2.1 MAC Address: It is stored in the words 9 to 14 of fuse bank 1, using the
+ natural MAC byte order (i.e. MSB first).
--- /dev/null
+U-Boot for Freescale i.MX6
+
+This file contains information for the port of U-Boot to the Freescale i.MX6
+SoC.
+
+1. CONVENTIONS FOR FUSE ASSIGNMENTS
+-----------------------------------
+
+1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the
+ 16 msbs in word 3.
This command need appear the fist before
other valid commands in configuration file.
+ BOOT_OFFSET value
+
+ This command is parallel to BOOT_FROM and
+ is preferred over BOOT_FROM.
+
+ value: Offset of the image header, this
+ value shall be set to one of the
+ values found in the file:
+ arch/arm/include/asm/\
+ imx-common/imximage.cfg
+ Example:
+ BOOT_OFFSET FLASH_OFFSET_STANDARD
+
BOOT_FROM nand/spi/sd/onenand/nor/sata
+
+ This command is parallel to BOOT_OFFSET and
+ is to be deprecated in favor of BOOT_OFFSET.
+
Example:
BOOT_FROM spi
+
DATA type address value
type: word=4, halfword=2, byte=1
--- /dev/null
+Driver implementing the fuse API for Freescale's On-Chip OTP Controller (OCOTP)
+on MXC
+
+This IP can be found on the following SoCs:
+ - i.MX6.
+
+Note that this IP is different from albeit similar to the IPs of the same name
+that can be found on the following SoCs:
+ - i.MX23,
+ - i.MX28,
+ - i.MX50.
+
+The section numbers in this file refer to the i.MX6 Reference Manual.
+
+A fuse word contains 32 fuse bit slots, as explained in 46.2.1.
+
+A bank contains 8 fuse word slots, as explained in 46.2.1 and shown by the
+memory map in 46.4.
+
+Some fuse bit or word slots may not have the corresponding fuses actually
+implemented in the fusebox.
+
+See the README files of the SoCs using this driver in order to know the
+conventions used by U-Boot to store some specific data in the fuses, e.g. MAC
+addresses.
+
+Fuse operations:
+
+ Read
+ Read operations are implemented as read accesses to the shadow registers,
+ using "Bankx Wordy" from the memory map in 46.4. This is explained in
+ detail by the first two paragraphs in 46.2.1.2.
+
+ Sense
+ Sense operations are implemented as the direct fusebox read explained by
+ the steps in 46.2.1.2.
+
+ Program
+ Program operations are implemented as explained by the steps in 46.2.1.3.
+ Following this operation, the shadow registers are not reloaded by the
+ hardware.
+
+ Override
+ Override operations are implemented as write accesses to the shadow
+ registers, as explained by the first paragraph in 46.2.1.3.
+
+Configuration:
+
+ CONFIG_MXC_OCOTP
+ Define this to enable the mxc_ocotp driver.
--- /dev/null
+Overview
+=========
+The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
+
+The P1010 is a cost-effective, low-power, highly integrated host processor
+based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
+that addresses the requirements of several routing, gateways, storage, consumer,
+and industrial applications. Applications of interest include the main CPUs and
+I/O processors in network attached storage (NAS), the voice over IP (VoIP)
+router/gateway, and wireless LAN (WLAN) and industrial controllers.
+
+The P1010RDB board features are as follows:
+Memory subsystem:
+ - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
+ - 32 Mbyte NOR flash single-chip memory
+ - 32 Mbyte NAND flash memory
+ - 256 Kbit M24256 I2C EEPROM
+ - 16 Mbyte SPI memory
+ - I2C Board EEPROM 128x8 bit memory
+ - SD/MMC connector to interface with the SD memory card
+Interfaces:
+ - PCIe:
+ - Lane0: x1 mini-PCIe slot
+ - Lane1: x1 PCIe standard slot
+ - SATA:
+ - 1 internal SATA connector to 2.5" 160G SATA2 HDD
+ - 1 eSATA connector to rear panel
+ - 10/100/1000 BaseT Ethernet ports:
+ - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
+ - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
+ - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
+ - USB 2.0 port:
+ - x1 USB2.0 port: via an ULPI PHY to micro-AB connector
+ - x1 USB2.0 poort via an internal PHY to micro-AB connector
+ - FlexCAN ports:
+ - x2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
+ interface;
+ - DUART interface:
+ - DUART interface: supports two UARTs up to 115200 bps for
+ console display
+ - J45 connectors are used for these 2 UART ports.
+ - TDM
+ - 2 FXS ports connected via an external SLIC to the TDM
+ interface. SLIC is controllled via SPI.
+ - 1 FXO port connected via a relay to FXS for switchover to
+ POTS
+Board connectors:
+ - Mini-ITX power supply connector
+ - JTAG/COP for debugging
+IEEE Std. 1588 signals for test and measurement
+Real-time clock on I2C bus
+POR
+ - support critical POR setting changed via switch on board
+PCB
+ - 6-layer routing (4-layer signals, 2-layer power and ground)
+
+
+Serial Port Configuration on P1010RDB
+=====================================
+Configure the serial port of the attached computer with the following values:
+ -Data rate: 115200 bps
+ -Number of data bits: 8
+ -Parity: None
+ -Number of Stop bits: 1
+ -Flow Control: Hardware/None
+
+
+Settings of DIP-switch
+======================
+ SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
+ SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
+ SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
+Note: 1 stands for 'on', 0 stands for 'off'
+
+
+Setting of hwconfig
+===================
+If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
+"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
+setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
+By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
+is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
+instead of to CAN/UART1.
+
+
+Build and burn u-boot to NOR flash
+==================================
+1. Build u-boot.bin image
+ export ARCH=powerpc
+ export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
+ make P1010RDB_NOR
+
+2. Burn u-boot.bin into NOR flash
+ => tftp $loadaddr $uboot
+ => protect off eff80000 +$filesize
+ => erase eff80000 +$filesize
+ => cp.b $loadaddr eff80000 $filesize
+
+3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
+
+
+Alternate NOR bank
+============================
+1. Burn u-boot.bin into alternate NOR bank
+ => tftp $loadaddr $uboot
+ => protect off eef80000 +$filesize
+ => erase eef80000 +$filesize
+ => cp.b $loadaddr eef80000 $filesize
+
+2. Switch to alternate NOR bank
+ => mw.b ffb00009 1
+ => reset
+ or set SW1[8]= ON
+
+SW1[8]= OFF: Upper bank used for booting start
+SW1[8]= ON: Lower bank used for booting start
+CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
+0 - boot from upper 4 sectors
+1 - boot from lower 4 sectors
+
+
+Build and burn u-boot to NAND flash
+===================================
+1. Build u-boot.bin image
+ export ARCH=powerpc
+ export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
+ make P1010RDB_NAND
+
+2. Burn u-boot-nand.bin into NAND flash
+ => tftp $loadaddr $uboot-nand
+ => nand erase 0 $filesize
+ => nand write $loadaddr 0 $filesize
+
+3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
+
+
+
+Build and burn u-boot to SPI flash
+==================================
+1. Build u-boot-spi.bin image
+ make P1010RDB_SPIFLASH_config; make
+ Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
+ Download u-boot.bin to linux and you can find some config files
+ under /usr/share such as config_xx.dat. Do below command:
+ boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
+ u-boot-spi.bin
+ to generate u-boot-spi.bin.
+
+2. Burn u-boot-spi.bin into SPI flash
+ => tftp $loadaddr $uboot-spi
+ => sf erase 0 100000
+ => sf write $loadaddr 0 $filesize
+
+3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
+
+
+
+CPLD POR setting registers
+==========================
+1. Set POR switch selection register (addr 0xFFB00011) to 0.
+2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
+ proper values.
+ If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
+ switch command by I2C.
+3. Send reset command.
+ After reset, the new POR setting will be implemented.
+
+Two examples are given in below:
+Switch from NOR to NAND boot with default frequency:
+ => i2c dev 0
+ => i2c mw 18 1 f9
+ => i2c mw 18 3 f0
+ => mw.b ffb00011 0
+ => mw.b ffb00017 1
+ => reset
+Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
+ => i2c dev 0
+ => i2c mw 18 1 f1
+ => i2c mw 18 3 f0
+ => mw.b ffb00011 0
+ => mw.b ffb00014 2
+ => mw.b ffb00015 5
+ => mw.b ffb00016 3
+ => mw.b ffb00017 f
+ => reset
+
+
+
+Boot Linux from network using TFTP on P1010RDB
+==============================================
+Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
+ => tftp 1000000 uImage
+ => tftp 2000000 p1010rdb.dtb
+ => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
+ => bootm 1000000 3000000 2000000
+
+
+Please contact your local field applications engineer or sales representative
+to obtain related documents, such as P1010-RDB User Guide for details.
--- /dev/null
+ RAMBOOT for MPC85xx Platforms
+ ==============================
+
+RAMBOOT literally means boot from DDR. But since DDR is volatile memory some
+pre-mechanism is required to load the DDR with the bootloader binary.
+- In case of SD and SPI boot this is done by BootROM code inside the chip
+ itself.
+- In case of NAND boot FCM supports loading initial 4K code from NAND flash
+ which can initialize the DDR and get the complete bootloader copied to DDR.
+
+In addition to the above there could be some more methods to initialize the DDR
+and load it manually.
+Two of them are described below.There is also an explanation as to where these
+methods could be handy.
+1. Load the RAM based bootloader onto DDR via JTAG/BDI interface. And then
+ execute the bootloader from DDR.
+ This may be handy in the following cases:
+ - In very early stage of platform bringup where other boot options are not
+ functional because of various reasons.
+ - In case the support to program the flashes on the board is not available.
+
+2. Load the RAM based bootloader onto DDR using already existing bootloader on
+ the board.And then execute the bootloader from DDR.
+ Some usecases where this may be used:
+ - While developing some new feature of u-boot, for example USB driver or
+ SPI driver.
+ Suppose the board already has a working bootloader on it. And you would
+ prefer to keep it intact, at the same time want to test your bootloader.
+ In this case you can get your test bootloader binary into DDR via tftp
+ for example. Then execute the test bootloader.
+ - Suppose a platform already has a propreitery bootloader which does not
+ support for example AMP boot. In this case also RAM boot loader can be
+ utilized.
+
+ So basically when the original bootloader is required to be kept intact
+ RAM based bootloader can offer an updated bootloader on the system.
+
+Both the above Bootloaders are slight variants of SDcard or SPI Flash
+bootloader or for that matter even NAND bootloader.
+All of them define CONFIG_SYS_RAMBOOT.
+The main difference among all of them is the way the pre-environment is getting
+configured and who is doing that.
+- In case of SD card and SPI flash bootloader this is done by On Chip BootROM inside the Si itself.
+- In case of NAND boot SPL/TPL code does it with some support from Si itself.
+- In case of the pure RAM based bootloaders we have to do it by JTAG manually or already existing bootloader.
+
+How to use them:
+1. Using JTAG
+ Boot up in core hold off mode or stop the core after reset using JTAG
+ interface.
+ Preconfigure DDR/L2SRAM through JTAG interface.
+ - setup DDR controller registers.
+ - setup DDR LAWs
+ - setup DDR TLB
+ Load the RAM based boot loader to the proper location in DDR/L2SRAM.
+ set up IAR (Instruction counter properly)
+ Enable the core to execute.
+
+2. Using already existing bootloader.
+ get the rambased boot loader binary into DDR/L2SRAM via tftp.
+ execute the RAM based bootloader.
+ => tftp 11000000 u-boot-ram.bin
+ => go 1107f000
+
+Please note that L2SRAM can also be used instead of DDR if the SOC has
+sufficient size of L2SRAM.
+
+Necessary Code changes Required:
+=====================================
+Please note that below mentioned changes are for 85xx platforms.
+They have been tested on P1020/P2020/P1010 RDB.
+
+The main difference between the above two methods from technical perspective is
+that in 1st case SOC is just out of reset so it is in default configuration.
+(CCSRBAR is at 0xff700000).
+In the 2nd case bootloader has already re-located CCSRBAR to 0xffe00000
+
+1. File name-> boards.cfg
+ There can be added specific Make options for RAMBoot. We can keep different
+ options for the two cases mentioned above.
+ for example
+ P1020RDB_JTAG_RAMBOOT and P1020RDB_GO_RAMBOOT.
+
+2. platform config file
+ for example include/configs/P1_P2_RDB.h
+
+ #ifdef CONFIG_RAMBOOT
+ #define CONFIG_SDCARD
+ #endif
+
+ This will finally use the CONFIG_SYS_RAMBOOT.
+
+3. File name-> arch/powerpc/include/asm/config_mpc85xx.h
+ In the section of the particular SOC, for example P1020,
+
+ #if defined(CONFIG_GO)
+ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xffe00000
+ #else
+ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+ #endif
+
+For JTAG RAMBOOT this is not required because CCSRBAR is at ff700000.
Available for i.mx31/35/5x/6x to service the watchdog. This is not
automatically set because some boards (vision2) still need to define
their own hw_watchdog_reset routine.
+
+CONFIG_XILINX_TB_WATCHDOG
+ Available for Xilinx Axi platforms to service timebase watchdog timer.
---------------------------
-What: Remove CONFIG_CMD_MEMTEST from default list
-When: Release v2013.07
+What: Remove unused CONFIG_SYS_MEMTEST_START/END
+When: Release v2013.10
-Why: The "mtest" command is of little practical use (if any), and
- experience has shown that a large number of board configu-
- rations define useless or even dangerous start and end
- addresses. If not even the board maintainers are able to
- figure out which memory range can be reliably tested, how can
- we expect such from the end users? As this problem comes up
- repeatedly, we rather do not enable this command by default,
- so only people who know what they are doing will be confronted
- with it.
+Why: As the 'mtest' command is no longer default, a number of platforms
+ have not opted to turn the command back on and thus provide unused
+ defines (which are likely to be propogated to new platforms from
+ copy/paste). Remove these defines when unused.
-Who: Wolfgang Denk <wd@denx.de>
+Who: Tom Rini <trini@ti.com>
---------------------------
alias smcnutt Scott McNutt <smcnutt@psyent.com>
alias sonic Sonic Zhang <sonic.adi@gmail.com>
alias stroese Stefan Roese <sr@denx.de>
+alias trini Tom Rini <trini@ti.com>
alias vapier Mike Frysinger <vapier@gentoo.org>
alias wd Wolfgang Denk <wd@denx.de>
alias samsung uboot, prom
alias tegra uboot, sjg, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com>
alias tegra2 tegra
-alias ti uboot, Tom Rini <trini@ti.com>
+alias ti uboot, trini
alias avr32 uboot, abiessmann
/* assuming HD */
sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
sata_dev_desc[devno].blksz = ATA_BLOCKSIZE;
+ sata_dev_desc[devno].log2blksz = LOG2(sata_dev_desc[devno].blksz);
sata_dev_desc[devno].lun = 0; /* just to fill something in... */
}
/* assuming HD */
sata_dev_desc[ap->port_no].type = DEV_TYPE_HARDDISK;
sata_dev_desc[ap->port_no].blksz = ATA_SECT_SIZE;
+ sata_dev_desc[ap->port_no].log2blksz =
+ LOG2(sata_dev_desc[ap->port_no].blksz);
sata_dev_desc[ap->port_no].lun = 0; /* just to fill something in... */
printf("PATA device#%d %s is found on ata port#%d.\n",
systemace_dev.part_type = PART_TYPE_UNKNOWN;
systemace_dev.type = DEV_TYPE_HARDDISK;
systemace_dev.blksz = 512;
+ systemace_dev.log2blksz = LOG2(systemace_dev.blksz);
systemace_dev.removable = 1;
systemace_dev.block_read = systemace_read;
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
+#include <asm/imx-common/regs-apbh.h>
static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
#if defined(CONFIG_MX23)
uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
-#elif defined(CONFIG_MX28)
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
#endif
COBJS-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
COBJS-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
COBJS-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
+COBJS-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
COBJS-$(CONFIG_FPGA_XILINX) += xilinx.o
COBJS-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
ifdef CONFIG_FPGA_ALTERA
*
*/
-/*
- * Generic FPGA support
- */
+/* Generic FPGA support */
#include <common.h> /* core U-Boot definitions */
#include <xilinx.h> /* xilinx specific definitions */
#include <altera.h> /* altera specific definitions */
#include <lattice.h>
-#if 0
-#define FPGA_DEBUG /* define FPGA_DEBUG to get debug messages */
-#endif
-
/* Local definitions */
#ifndef CONFIG_MAX_FPGA_DEVICES
#define CONFIG_MAX_FPGA_DEVICES 5
#endif
-/* Enable/Disable debug console messages */
-#ifdef FPGA_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
/* Local static data */
static int next_desc = FPGA_INVALID_DEVICE;
static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES];
-/* Local static functions */
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum );
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf,
- size_t bsize, char *fn );
-static int fpga_dev_info( int devnum );
-
-
-/* ------------------------------------------------------------------------- */
-
-/* fpga_no_sup
+/*
+ * fpga_no_sup
* 'no support' message function
*/
-static void fpga_no_sup( char *fn, char *msg )
+static void fpga_no_sup(char *fn, char *msg)
{
- if ( fn && msg ) {
- printf( "%s: No support for %s.\n", fn, msg);
- } else if ( msg ) {
- printf( "No support for %s.\n", msg);
- } else {
- printf( "No FPGA suport!\n");
- }
+ if (fn && msg)
+ printf("%s: No support for %s.\n", fn, msg);
+ else if (msg)
+ printf("No support for %s.\n", msg);
+ else
+ printf("No FPGA suport!\n");
}
/* fpga_get_desc
* map a device number to a descriptor
*/
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum )
+static const fpga_desc *const fpga_get_desc(int devnum)
{
- fpga_desc *desc = (fpga_desc * )NULL;
+ fpga_desc *desc = (fpga_desc *)NULL;
- if (( devnum >= 0 ) && (devnum < next_desc )) {
+ if ((devnum >= 0) && (devnum < next_desc)) {
desc = &desc_table[devnum];
- PRINTF( "%s: found fpga descriptor #%d @ 0x%p\n",
- __FUNCTION__, devnum, desc );
+ debug("%s: found fpga descriptor #%d @ 0x%p\n",
+ __func__, devnum, desc);
}
return desc;
}
-
-/* fpga_validate
+/*
+ * fpga_validate
* generic parameter checking code
*/
-static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf,
- size_t bsize, char *fn )
+const fpga_desc *const fpga_validate(int devnum, const void *buf,
+ size_t bsize, char *fn)
{
- fpga_desc * desc = fpga_get_desc( devnum );
+ const fpga_desc *desc = fpga_get_desc(devnum);
- if ( !desc ) {
- printf( "%s: Invalid device number %d\n", fn, devnum );
- }
+ if (!desc)
+ printf("%s: Invalid device number %d\n", fn, devnum);
- if ( !buf ) {
- printf( "%s: Null buffer.\n", fn );
+ if (!buf) {
+ printf("%s: Null buffer.\n", fn);
return (fpga_desc * const)NULL;
}
return desc;
}
-
-/* fpga_dev_info
+/*
+ * fpga_dev_info
* generic multiplexing code
*/
-static int fpga_dev_info( int devnum )
+static int fpga_dev_info(int devnum)
{
- int ret_val = FPGA_FAIL; /* assume failure */
- const fpga_desc * const desc = fpga_get_desc( devnum );
+ int ret_val = FPGA_FAIL; /* assume failure */
+ const fpga_desc * const desc = fpga_get_desc(devnum);
- if ( desc ) {
- PRINTF( "%s: Device Descriptor @ 0x%p\n",
- __FUNCTION__, desc->devdesc );
+ if (desc) {
+ debug("%s: Device Descriptor @ 0x%p\n",
+ __func__, desc->devdesc);
- switch ( desc->devtype ) {
+ switch (desc->devtype) {
case fpga_xilinx:
#if defined(CONFIG_FPGA_XILINX)
- printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc );
- ret_val = xilinx_info( desc->devdesc );
+ printf("Xilinx Device\nDescriptor @ 0x%p\n", desc);
+ ret_val = xilinx_info(desc->devdesc);
#else
- fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
+ fpga_no_sup((char *)__func__, "Xilinx devices");
#endif
break;
case fpga_altera:
#if defined(CONFIG_FPGA_ALTERA)
- printf( "Altera Device\nDescriptor @ 0x%p\n", desc );
- ret_val = altera_info( desc->devdesc );
+ printf("Altera Device\nDescriptor @ 0x%p\n", desc);
+ ret_val = altera_info(desc->devdesc);
#else
- fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
+ fpga_no_sup((char *)__func__, "Altera devices");
#endif
break;
case fpga_lattice:
printf("Lattice Device\nDescriptor @ 0x%p\n", desc);
ret_val = lattice_info(desc->devdesc);
#else
- fpga_no_sup( (char *)__FUNCTION__, "Lattice devices" );
+ fpga_no_sup((char *)__func__, "Lattice devices");
#endif
break;
default:
- printf( "%s: Invalid or unsupported device type %d\n",
- __FUNCTION__, desc->devtype );
+ printf("%s: Invalid or unsupported device type %d\n",
+ __func__, desc->devtype);
}
} else {
- printf( "%s: Invalid device number %d\n",
- __FUNCTION__, devnum );
+ printf("%s: Invalid device number %d\n", __func__, devnum);
}
return ret_val;
}
-
-/* ------------------------------------------------------------------------- */
-/* fgpa_init is usually called from misc_init_r() and MUST be called
+/*
+ * fgpa_init is usually called from misc_init_r() and MUST be called
* before any of the other fpga functions are used.
*/
void fpga_init(void)
{
next_desc = 0;
- memset( desc_table, 0, sizeof(desc_table));
+ memset(desc_table, 0, sizeof(desc_table));
- PRINTF( "%s: CONFIG_FPGA = 0x%x\n", __FUNCTION__, CONFIG_FPGA );
+ debug("%s\n", __func__);
}
-/* fpga_count
+/*
+ * fpga_count
* Basic interface function to get the current number of devices available.
*/
-int fpga_count( void )
+int fpga_count(void)
{
return next_desc;
}
-/* fpga_add
+/*
+ * fpga_add
* Add the device descriptor to the device table.
*/
-int fpga_add( fpga_type devtype, void *desc )
+int fpga_add(fpga_type devtype, void *desc)
{
int devnum = FPGA_INVALID_DEVICE;
- if ( next_desc < 0 ) {
- printf( "%s: FPGA support not initialized!\n", __FUNCTION__ );
- } else if (( devtype > fpga_min_type ) && ( devtype < fpga_undefined )) {
- if ( desc ) {
- if ( next_desc < CONFIG_MAX_FPGA_DEVICES ) {
+ if (next_desc < 0) {
+ printf("%s: FPGA support not initialized!\n", __func__);
+ } else if ((devtype > fpga_min_type) && (devtype < fpga_undefined)) {
+ if (desc) {
+ if (next_desc < CONFIG_MAX_FPGA_DEVICES) {
devnum = next_desc;
desc_table[next_desc].devtype = devtype;
desc_table[next_desc++].devdesc = desc;
} else {
- printf( "%s: Exceeded Max FPGA device count\n", __FUNCTION__ );
+ printf("%s: Exceeded Max FPGA device count\n",
+ __func__);
}
} else {
- printf( "%s: NULL device descriptor\n", __FUNCTION__ );
+ printf("%s: NULL device descriptor\n", __func__);
}
} else {
- printf( "%s: Unsupported FPGA type %d\n", __FUNCTION__, devtype );
+ printf("%s: Unsupported FPGA type %d\n", __func__, devtype);
}
return devnum;
}
/*
- * Generic multiplexing code
+ * Convert bitstream data and load into the fpga
+ */
+int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
+{
+ printf("Bitstream support not implemented for this FPGA device\n");
+ return FPGA_FAIL;
+}
+
+/*
+ * Generic multiplexing code
*/
int fpga_load(int devnum, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume failure */
- fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ );
+ const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
+ (char *)__func__);
- if ( desc ) {
- switch ( desc->devtype ) {
+ if (desc) {
+ switch (desc->devtype) {
case fpga_xilinx:
#if defined(CONFIG_FPGA_XILINX)
- ret_val = xilinx_load( desc->devdesc, buf, bsize );
+ ret_val = xilinx_load(desc->devdesc, buf, bsize);
#else
- fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
+ fpga_no_sup((char *)__func__, "Xilinx devices");
#endif
break;
case fpga_altera:
#if defined(CONFIG_FPGA_ALTERA)
- ret_val = altera_load( desc->devdesc, buf, bsize );
+ ret_val = altera_load(desc->devdesc, buf, bsize);
#else
- fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
+ fpga_no_sup((char *)__func__, "Altera devices");
#endif
break;
case fpga_lattice:
#if defined(CONFIG_FPGA_LATTICE)
ret_val = lattice_load(desc->devdesc, buf, bsize);
#else
- fpga_no_sup( (char *)__FUNCTION__, "Lattice devices" );
+ fpga_no_sup((char *)__func__, "Lattice devices");
#endif
break;
default:
- printf( "%s: Invalid or unsupported device type %d\n",
- __FUNCTION__, desc->devtype );
+ printf("%s: Invalid or unsupported device type %d\n",
+ __func__, desc->devtype);
}
}
return ret_val;
}
-/* fpga_dump
+/*
+ * fpga_dump
* generic multiplexing code
*/
int fpga_dump(int devnum, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume failure */
- fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ );
+ const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
+ (char *)__func__);
- if ( desc ) {
- switch ( desc->devtype ) {
+ if (desc) {
+ switch (desc->devtype) {
case fpga_xilinx:
#if defined(CONFIG_FPGA_XILINX)
- ret_val = xilinx_dump( desc->devdesc, buf, bsize );
+ ret_val = xilinx_dump(desc->devdesc, buf, bsize);
#else
- fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
+ fpga_no_sup((char *)__func__, "Xilinx devices");
#endif
break;
case fpga_altera:
#if defined(CONFIG_FPGA_ALTERA)
- ret_val = altera_dump( desc->devdesc, buf, bsize );
+ ret_val = altera_dump(desc->devdesc, buf, bsize);
#else
- fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
+ fpga_no_sup((char *)__func__, "Altera devices");
#endif
break;
case fpga_lattice:
#if defined(CONFIG_FPGA_LATTICE)
ret_val = lattice_dump(desc->devdesc, buf, bsize);
#else
- fpga_no_sup( (char *)__FUNCTION__, "Lattice devices" );
+ fpga_no_sup((char *)__func__, "Lattice devices");
#endif
break;
default:
- printf( "%s: Invalid or unsupported device type %d\n",
- __FUNCTION__, desc->devtype );
+ printf("%s: Invalid or unsupported device type %d\n",
+ __func__, desc->devtype);
}
}
return ret_val;
}
-
-/* fpga_info
+/*
+ * fpga_info
* front end to fpga_dev_info. If devnum is invalid, report on all
* available devices.
*/
-int fpga_info( int devnum )
+int fpga_info(int devnum)
{
- if ( devnum == FPGA_INVALID_DEVICE ) {
- if ( next_desc > 0 ) {
+ if (devnum == FPGA_INVALID_DEVICE) {
+ if (next_desc > 0) {
int dev;
- for ( dev = 0; dev < next_desc; dev++ ) {
- fpga_dev_info( dev );
- }
+ for (dev = 0; dev < next_desc; dev++)
+ fpga_dev_info(dev);
+
return FPGA_SUCCESS;
} else {
- printf( "%s: No FPGA devices available.\n", __FUNCTION__ );
+ printf("%s: No FPGA devices available.\n", __func__);
return FPGA_FAIL;
}
}
- else return fpga_dev_info( devnum );
-}
-/* ------------------------------------------------------------------------- */
+ return fpga_dev_info(devnum);
+}
/*
+ * (C) Copyright 2012-2013, Xilinx, Michal Simek
+ *
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
* Keith Outwater, keith_outwater@mvis.com
*/
#include <common.h>
+#include <fpga.h>
#include <virtex2.h>
#include <spartan2.h>
#include <spartan3.h>
+#include <zynqpl.h>
#if 0
#define FPGA_DEBUG
/* ------------------------------------------------------------------------- */
+int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
+{
+ unsigned int length;
+ unsigned int swapsize;
+ char buffer[80];
+ unsigned char *dataptr;
+ unsigned int i;
+ const fpga_desc *desc;
+ Xilinx_desc *xdesc;
+
+ dataptr = (unsigned char *)fpgadata;
+ /* Find out fpga_description */
+ desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
+ /* Assign xilinx device description */
+ xdesc = desc->devdesc;
+
+ /* skip the first bytes of the bitsteam, their meaning is unknown */
+ length = (*dataptr << 8) + *(dataptr + 1);
+ dataptr += 2;
+ dataptr += length;
+
+ /* get design name (identifier, length, string) */
+ length = (*dataptr << 8) + *(dataptr + 1);
+ dataptr += 2;
+ if (*dataptr++ != 0x61) {
+ debug("%s: Design name id not recognized in bitstream\n",
+ __func__);
+ return FPGA_FAIL;
+ }
+
+ length = (*dataptr << 8) + *(dataptr + 1);
+ dataptr += 2;
+ for (i = 0; i < length; i++)
+ buffer[i] = *dataptr++;
+
+ printf(" design filename = \"%s\"\n", buffer);
+
+ /* get part number (identifier, length, string) */
+ if (*dataptr++ != 0x62) {
+ printf("%s: Part number id not recognized in bitstream\n",
+ __func__);
+ return FPGA_FAIL;
+ }
+
+ length = (*dataptr << 8) + *(dataptr + 1);
+ dataptr += 2;
+ for (i = 0; i < length; i++)
+ buffer[i] = *dataptr++;
+
+ if (xdesc->name) {
+ i = strncmp(buffer, xdesc->name, strlen(xdesc->name));
+ if (i) {
+ printf("%s: Wrong bitstream ID for this device\n",
+ __func__);
+ printf("%s: Bitstream ID %s, current device ID %d/%s\n",
+ __func__, buffer, devnum, xdesc->name);
+ return FPGA_FAIL;
+ }
+ } else {
+ printf("%s: Please fill correct device ID to Xilinx_desc\n",
+ __func__);
+ }
+ printf(" part number = \"%s\"\n", buffer);
+
+ /* get date (identifier, length, string) */
+ if (*dataptr++ != 0x63) {
+ printf("%s: Date identifier not recognized in bitstream\n",
+ __func__);
+ return FPGA_FAIL;
+ }
+
+ length = (*dataptr << 8) + *(dataptr+1);
+ dataptr += 2;
+ for (i = 0; i < length; i++)
+ buffer[i] = *dataptr++;
+ printf(" date = \"%s\"\n", buffer);
+
+ /* get time (identifier, length, string) */
+ if (*dataptr++ != 0x64) {
+ printf("%s: Time identifier not recognized in bitstream\n",
+ __func__);
+ return FPGA_FAIL;
+ }
+
+ length = (*dataptr << 8) + *(dataptr+1);
+ dataptr += 2;
+ for (i = 0; i < length; i++)
+ buffer[i] = *dataptr++;
+ printf(" time = \"%s\"\n", buffer);
+
+ /* get fpga data length (identifier, length) */
+ if (*dataptr++ != 0x65) {
+ printf("%s: Data length id not recognized in bitstream\n",
+ __func__);
+ return FPGA_FAIL;
+ }
+ swapsize = ((unsigned int) *dataptr << 24) +
+ ((unsigned int) *(dataptr + 1) << 16) +
+ ((unsigned int) *(dataptr + 2) << 8) +
+ ((unsigned int) *(dataptr + 3));
+ dataptr += 4;
+ printf(" bytes in bitstream = %d\n", swapsize);
+
+ return fpga_load(devnum, dataptr, swapsize);
+}
+
int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume a failure */
#else
printf ("%s: No support for Virtex-II devices.\n",
__FUNCTION__);
+#endif
+ break;
+ case xilinx_zynq:
+#if defined(CONFIG_FPGA_ZYNQPL)
+ PRINTF("%s: Launching the Zynq PL Loader...\n",
+ __func__);
+ ret_val = zynq_load(desc, buf, bsize);
+#else
+ printf("%s: No support for Zynq devices.\n",
+ __func__);
#endif
break;
#else
printf ("%s: No support for Virtex-II devices.\n",
__FUNCTION__);
+#endif
+ break;
+ case xilinx_zynq:
+#if defined(CONFIG_FPGA_ZYNQPL)
+ PRINTF("%s: Launching the Zynq PL Reader...\n",
+ __func__);
+ ret_val = zynq_dump(desc, buf, bsize);
+#else
+ printf("%s: No support for Zynq devices.\n",
+ __func__);
#endif
break;
case Xilinx_Virtex2:
printf ("Virtex-II\n");
break;
+ case xilinx_zynq:
+ printf("Zynq PL\n");
+ break;
/* Add new family types here */
default:
printf ("Unknown family type, %d\n", desc->family);
case master_selectmap:
printf ("Master SelectMap Mode\n");
break;
+ case devcfg:
+ printf("Device configuration interface (Zynq)\n");
+ break;
/* Add new interface types here */
default:
printf ("Unsupported interface type, %d\n", desc->iface);
printf ("Device Size: \t%d bytes\n"
"Cookie: \t0x%x (%d)\n",
desc->size, desc->cookie, desc->cookie);
+ if (desc->name)
+ printf("Device name: \t%s\n", desc->name);
if (desc->iface_fns) {
printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
__FUNCTION__);
#endif
break;
+ case xilinx_zynq:
+#if defined(CONFIG_FPGA_ZYNQPL)
+ zynq_info(desc);
+#else
+ /* just in case */
+ printf("%s: No support for Zynq devices.\n",
+ __func__);
+#endif
/* Add new family types here */
default:
/* we don't need a message here - we give one up above */
--- /dev/null
+/*
+ * (C) Copyright 2012-2013, Xilinx, Michal Simek
+ *
+ * (C) Copyright 2012
+ * Joe Hershberger <joe.hershberger@ni.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <zynqpl.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+
+#define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
+#define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
+#define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
+#define DEVCFG_ISR_RX_FIFO_OV 0x00040000
+#define DEVCFG_ISR_DMA_DONE 0x00002000
+#define DEVCFG_ISR_PCFG_DONE 0x00000004
+#define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
+#define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
+#define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
+#define DEVCFG_STATUS_PCFG_INIT 0x00000010
+#define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
+#define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
+
+#ifndef CONFIG_SYS_FPGA_WAIT
+#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
+#endif
+
+#ifndef CONFIG_SYS_FPGA_PROG_TIME
+#define CONFIG_SYS_FPGA_PROG_TIME CONFIG_SYS_HZ /* 1 s */
+#endif
+
+int zynq_info(Xilinx_desc *desc)
+{
+ return FPGA_SUCCESS;
+}
+
+#define DUMMY_WORD 0xffffffff
+
+/* Xilinx binary format header */
+static const u32 bin_format[] = {
+ DUMMY_WORD, /* Dummy words */
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ DUMMY_WORD,
+ 0x000000bb, /* Sync word */
+ 0x11220044, /* Sync word */
+ DUMMY_WORD,
+ DUMMY_WORD,
+ 0xaa995566, /* Sync word */
+};
+
+#define SWAP_NO 1
+#define SWAP_DONE 2
+
+/*
+ * Load the whole word from unaligned buffer
+ * Keep in your mind that it is byte loading on little-endian system
+ */
+static u32 load_word(const void *buf, u32 swap)
+{
+ u32 word = 0;
+ u8 *bitc = (u8 *)buf;
+ int p;
+
+ if (swap == SWAP_NO) {
+ for (p = 0; p < 4; p++) {
+ word <<= 8;
+ word |= bitc[p];
+ }
+ } else {
+ for (p = 3; p >= 0; p--) {
+ word <<= 8;
+ word |= bitc[p];
+ }
+ }
+
+ return word;
+}
+
+static u32 check_header(const void *buf)
+{
+ u32 i, pattern;
+ int swap = SWAP_NO;
+ u32 *test = (u32 *)buf;
+
+ debug("%s: Let's check bitstream header\n", __func__);
+
+ /* Checking that passing bin is not a bitstream */
+ for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
+ pattern = load_word(&test[i], swap);
+
+ /*
+ * Bitstreams in binary format are swapped
+ * compare to regular bistream.
+ * Do not swap dummy word but if swap is done assume
+ * that parsing buffer is binary format
+ */
+ if ((__swab32(pattern) != DUMMY_WORD) &&
+ (__swab32(pattern) == bin_format[i])) {
+ pattern = __swab32(pattern);
+ swap = SWAP_DONE;
+ debug("%s: data swapped - let's swap\n", __func__);
+ }
+
+ debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
+ (u32)&test[i], pattern, bin_format[i]);
+ if (pattern != bin_format[i]) {
+ debug("%s: Bitstream is not recognized\n", __func__);
+ return 0;
+ }
+ }
+ debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
+ (u32)buf, swap == SWAP_NO ? "without" : "with");
+
+ return swap;
+}
+
+static void *check_data(u8 *buf, size_t bsize, u32 *swap)
+{
+ u32 word, p = 0; /* possition */
+
+ /* Because buf doesn't need to be aligned let's read it by chars */
+ for (p = 0; p < bsize; p++) {
+ word = load_word(&buf[p], SWAP_NO);
+ debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
+
+ /* Find the first bitstream dummy word */
+ if (word == DUMMY_WORD) {
+ debug("%s: Found dummy word at position %x/%x\n",
+ __func__, p, (u32)&buf[p]);
+ *swap = check_header(&buf[p]);
+ if (*swap) {
+ /* FIXME add full bitstream checking here */
+ return &buf[p];
+ }
+ }
+ /* Loop can be huge - support CTRL + C */
+ if (ctrlc())
+ return 0;
+ }
+ return 0;
+}
+
+
+int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+{
+ unsigned long ts; /* Timestamp */
+ u32 partialbit = 0;
+ u32 i, control, isr_status, status, swap, diff;
+ u32 *buf_start;
+
+ /* Detect if we are going working with partial or full bitstream */
+ if (bsize != desc->size) {
+ printf("%s: Working with partial bitstream\n", __func__);
+ partialbit = 1;
+ }
+
+ buf_start = check_data((u8 *)buf, bsize, &swap);
+ if (!buf_start)
+ return FPGA_FAIL;
+
+ /* Check if data is postpone from start */
+ diff = (u32)buf_start - (u32)buf;
+ if (diff) {
+ printf("%s: Bitstream is not validated yet (diff %x)\n",
+ __func__, diff);
+ return FPGA_FAIL;
+ }
+
+ if ((u32)buf_start & 0x3) {
+ u32 *new_buf = (u32 *)((u32)buf & ~0x3);
+
+ printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
+ (u32)buf_start, (u32)new_buf, swap);
+
+ for (i = 0; i < (bsize/4); i++)
+ new_buf[i] = load_word(&buf_start[i], swap);
+
+ swap = SWAP_DONE;
+ buf = new_buf;
+ } else if (swap != SWAP_DONE) {
+ /* For bitstream which are aligned */
+ u32 *new_buf = (u32 *)buf;
+
+ printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
+ swap);
+
+ for (i = 0; i < (bsize/4); i++)
+ new_buf[i] = load_word(&buf_start[i], swap);
+
+ swap = SWAP_DONE;
+ }
+
+ if (!partialbit) {
+ zynq_slcr_devcfg_disable();
+
+ /* Setting PCFG_PROG_B signal to high */
+ control = readl(&devcfg_base->ctrl);
+ writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
+ /* Setting PCFG_PROG_B signal to low */
+ writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
+
+ /* Polling the PCAP_INIT status for Reset */
+ ts = get_timer(0);
+ while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ printf("%s: Timeout wait for INIT to clear\n",
+ __func__);
+ return FPGA_FAIL;
+ }
+ }
+
+ /* Setting PCFG_PROG_B signal to high */
+ writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
+
+ /* Polling the PCAP_INIT status for Set */
+ ts = get_timer(0);
+ while (!(readl(&devcfg_base->status) &
+ DEVCFG_STATUS_PCFG_INIT)) {
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ printf("%s: Timeout wait for INIT to set\n",
+ __func__);
+ return FPGA_FAIL;
+ }
+ }
+ }
+
+ isr_status = readl(&devcfg_base->int_sts);
+
+ /* Clear it all, so if Boot ROM comes back, it can proceed */
+ writel(0xFFFFFFFF, &devcfg_base->int_sts);
+
+ if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
+ debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
+
+ /* If RX FIFO overflow, need to flush RX FIFO first */
+ if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
+ writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
+ writel(0xFFFFFFFF, &devcfg_base->int_sts);
+ }
+ return FPGA_FAIL;
+ }
+
+ status = readl(&devcfg_base->status);
+
+ debug("%s: Status = 0x%08X\n", __func__, status);
+
+ if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
+ debug("%s: Error: device busy\n", __func__);
+ return FPGA_FAIL;
+ }
+
+ debug("%s: Device ready\n", __func__);
+
+ if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
+ if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
+ /* Error state, transfer cannot occur */
+ debug("%s: ISR indicates error\n", __func__);
+ return FPGA_FAIL;
+ } else {
+ /* Clear out the status */
+ writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
+ }
+ }
+
+ if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
+ /* Clear the count of completed DMA transfers */
+ writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
+ }
+
+ debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
+ debug("%s: Size = %zu\n", __func__, bsize);
+
+ /* Set up the transfer */
+ writel((u32)buf | 1, &devcfg_base->dma_src_addr);
+ writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);
+ writel(bsize >> 2, &devcfg_base->dma_src_len);
+ writel(0, &devcfg_base->dma_dst_len);
+
+ isr_status = readl(&devcfg_base->int_sts);
+
+ /* Polling the PCAP_INIT status for Set */
+ ts = get_timer(0);
+ while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
+ if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
+ debug("%s: Error: isr = 0x%08X\n", __func__,
+ isr_status);
+ debug("%s: Write count = 0x%08X\n", __func__,
+ readl(&devcfg_base->write_count));
+ debug("%s: Read count = 0x%08X\n", __func__,
+ readl(&devcfg_base->read_count));
+
+ return FPGA_FAIL;
+ }
+ if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
+ printf("%s: Timeout wait for DMA to complete\n",
+ __func__);
+ return FPGA_FAIL;
+ }
+ isr_status = readl(&devcfg_base->int_sts);
+ }
+
+ debug("%s: DMA transfer is done\n", __func__);
+
+ /* Check FPGA configuration completion */
+ ts = get_timer(0);
+ while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ printf("%s: Timeout wait for FPGA to config\n",
+ __func__);
+ return FPGA_FAIL;
+ }
+ isr_status = readl(&devcfg_base->int_sts);
+ }
+
+ debug("%s: FPGA config done\n", __func__);
+
+ /* Clear out the DMA status */
+ writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
+
+ if (!partialbit)
+ zynq_slcr_devcfg_enable();
+
+ return FPGA_SUCCESS;
+}
+
+int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+{
+ return FPGA_FAIL;
+}
COBJS-$(CONFIG_ALI152X) += ali512x.o
COBJS-$(CONFIG_DS4510) += ds4510.o
COBJS-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
+COBJS-$(CONFIG_FSL_IIM) += fsl_iim.o
COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
+COBJS-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
COBJS-$(CONFIG_NS87308) += ns87308.o
COBJS-$(CONFIG_PDSP188x) += pdsp188x.o
COBJS-$(CONFIG_STATUS_LED) += status_led.o
--- /dev/null
+/*
+ * (C) Copyright 2009-2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on the mpc512x iim code:
+ * Copyright 2008 Silicon Turnkey Express, Inc.
+ * Martha Marx <mmarx@silicontkx.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fuse.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#ifndef CONFIG_MPC512X
+#include <asm/arch/imx-regs.h>
+#endif
+
+/* FSL IIM-specific constants */
+#define STAT_BUSY 0x80
+#define STAT_PRGD 0x02
+#define STAT_SNSD 0x01
+
+#define STATM_PRGD_M 0x02
+#define STATM_SNSD_M 0x01
+
+#define ERR_PRGE 0x80
+#define ERR_WPE 0x40
+#define ERR_OPE 0x20
+#define ERR_RPE 0x10
+#define ERR_WLRE 0x08
+#define ERR_SNSE 0x04
+#define ERR_PARITYE 0x02
+
+#define EMASK_PRGE_M 0x80
+#define EMASK_WPE_M 0x40
+#define EMASK_OPE_M 0x20
+#define EMASK_RPE_M 0x10
+#define EMASK_WLRE_M 0x08
+#define EMASK_SNSE_M 0x04
+#define EMASK_PARITYE_M 0x02
+
+#define FCTL_DPC 0x80
+#define FCTL_PRG_LENGTH_MASK 0x70
+#define FCTL_ESNS_N 0x08
+#define FCTL_ESNS_0 0x04
+#define FCTL_ESNS_1 0x02
+#define FCTL_PRG 0x01
+
+#define UA_A_BANK_MASK 0x38
+#define UA_A_ROWH_MASK 0x07
+
+#define LA_A_ROWL_MASK 0xf8
+#define LA_A_BIT_MASK 0x07
+
+#define PREV_PROD_REV_MASK 0xf8
+#define PREV_PROD_VT_MASK 0x07
+
+/* Select the correct accessors depending on endianness */
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define iim_read32 in_le32
+#define iim_write32 out_le32
+#define iim_clrsetbits32 clrsetbits_le32
+#define iim_clrbits32 clrbits_le32
+#define iim_setbits32 setbits_le32
+#elif __BYTE_ORDER == __BIG_ENDIAN
+#define iim_read32 in_be32
+#define iim_write32 out_be32
+#define iim_clrsetbits32 clrsetbits_be32
+#define iim_clrbits32 clrbits_be32
+#define iim_setbits32 setbits_be32
+#else
+#error Endianess is not defined: please fix to continue
+#endif
+
+/* IIM control registers */
+struct fsl_iim {
+ u32 stat;
+ u32 statm;
+ u32 err;
+ u32 emask;
+ u32 fctl;
+ u32 ua;
+ u32 la;
+ u32 sdat;
+ u32 prev;
+ u32 srev;
+ u32 prg_p;
+ u32 scs[0x1f5];
+ struct {
+ u32 word[0x100];
+ } bank[8];
+};
+
+static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert,
+ const char *caller)
+{
+ *regs = (struct fsl_iim *)IIM_BASE_ADDR;
+
+ if (bank >= ARRAY_SIZE((*regs)->bank) ||
+ word >= ARRAY_SIZE((*regs)->bank[0].word) ||
+ !assert) {
+ printf("fsl_iim %s(): Invalid argument\n", caller);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void clear_status(struct fsl_iim *regs)
+{
+ iim_setbits32(®s->stat, 0);
+ iim_setbits32(®s->err, 0);
+}
+
+static void finish_access(struct fsl_iim *regs, u32 *stat, u32 *err)
+{
+ *stat = iim_read32(®s->stat);
+ *err = iim_read32(®s->err);
+ clear_status(regs);
+}
+
+static int prepare_read(struct fsl_iim **regs, u32 bank, u32 word, u32 *val,
+ const char *caller)
+{
+ int ret;
+
+ ret = prepare_access(regs, bank, word, val != NULL, caller);
+ if (ret)
+ return ret;
+
+ clear_status(*regs);
+
+ return 0;
+}
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+ struct fsl_iim *regs;
+ u32 stat, err;
+ int ret;
+
+ ret = prepare_read(®s, bank, word, val, __func__);
+ if (ret)
+ return ret;
+
+ *val = iim_read32(®s->bank[bank].word[word]);
+ finish_access(regs, &stat, &err);
+
+ if (err & ERR_RPE) {
+ puts("fsl_iim fuse_read(): Read protect error\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static void direct_access(struct fsl_iim *regs, u32 bank, u32 word, u32 bit,
+ u32 fctl, u32 *stat, u32 *err)
+{
+ iim_write32(®s->ua, bank << 3 | word >> 5);
+ iim_write32(®s->la, (word << 3 | bit) & 0xff);
+ if (fctl == FCTL_PRG)
+ iim_write32(®s->prg_p, 0xaa);
+ iim_setbits32(®s->fctl, fctl);
+ while (iim_read32(®s->stat) & STAT_BUSY)
+ udelay(20);
+ finish_access(regs, stat, err);
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+ struct fsl_iim *regs;
+ u32 stat, err;
+ int ret;
+
+ ret = prepare_read(®s, bank, word, val, __func__);
+ if (ret)
+ return ret;
+
+ direct_access(regs, bank, word, 0, FCTL_ESNS_N, &stat, &err);
+
+ if (err & ERR_SNSE) {
+ puts("fsl_iim fuse_sense(): Explicit sense cycle error\n");
+ return -EIO;
+ }
+
+ if (!(stat & STAT_SNSD)) {
+ puts("fsl_iim fuse_sense(): Explicit sense cycle did not complete\n");
+ return -EIO;
+ }
+
+ *val = iim_read32(®s->sdat);
+ return 0;
+}
+
+static int prog_bit(struct fsl_iim *regs, u32 bank, u32 word, u32 bit)
+{
+ u32 stat, err;
+
+ clear_status(regs);
+ direct_access(regs, bank, word, bit, FCTL_PRG, &stat, &err);
+ iim_write32(®s->prg_p, 0x00);
+
+ if (err & ERR_PRGE) {
+ puts("fsl_iim fuse_prog(): Program error\n");
+ return -EIO;
+ }
+
+ if (err & ERR_WPE) {
+ puts("fsl_iim fuse_prog(): Write protect error\n");
+ return -EIO;
+ }
+
+ if (!(stat & STAT_PRGD)) {
+ puts("fsl_iim fuse_prog(): Program did not complete\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int prepare_write(struct fsl_iim **regs, u32 bank, u32 word, u32 val,
+ const char *caller)
+{
+ return prepare_access(regs, bank, word, !(val & ~0xff), caller);
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+ struct fsl_iim *regs;
+ u32 bit;
+ int ret;
+
+ ret = prepare_write(®s, bank, word, val, __func__);
+ if (ret)
+ return ret;
+
+ for (bit = 0; val; bit++, val >>= 1)
+ if (val & 0x01) {
+ ret = prog_bit(regs, bank, word, bit);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+ struct fsl_iim *regs;
+ u32 stat, err;
+ int ret;
+
+ ret = prepare_write(®s, bank, word, val, __func__);
+ if (ret)
+ return ret;
+
+ clear_status(regs);
+ iim_write32(®s->bank[bank].word[word], val);
+ finish_access(regs, &stat, &err);
+
+ if (err & ERR_OPE) {
+ puts("fsl_iim fuse_override(): Override protect error\n");
+ return -EIO;
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on Dirk Behme's
+ * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
+ * which is based on Freescale's
+ * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
+ * which is:
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fuse.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+
+#define BO_CTRL_WR_UNLOCK 16
+#define BM_CTRL_WR_UNLOCK 0xffff0000
+#define BV_CTRL_WR_UNLOCK_KEY 0x3e77
+#define BM_CTRL_ERROR 0x00000200
+#define BM_CTRL_BUSY 0x00000100
+#define BO_CTRL_ADDR 0
+#define BM_CTRL_ADDR 0x0000007f
+
+#define BO_TIMING_STROBE_READ 16
+#define BM_TIMING_STROBE_READ 0x003f0000
+#define BV_TIMING_STROBE_READ_NS 37
+#define BO_TIMING_RELAX 12
+#define BM_TIMING_RELAX 0x0000f000
+#define BV_TIMING_RELAX_NS 17
+#define BO_TIMING_STROBE_PROG 0
+#define BM_TIMING_STROBE_PROG 0x00000fff
+#define BV_TIMING_STROBE_PROG_US 10
+
+#define BM_READ_CTRL_READ_FUSE 0x00000001
+
+#define BF(value, field) (((value) << BO_##field) & BM_##field)
+
+#define WRITE_POSTAMBLE_US 2
+
+static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
+{
+ while (readl(®s->ctrl) & BM_CTRL_BUSY)
+ udelay(delay_us);
+}
+
+static void clear_error(struct ocotp_regs *regs)
+{
+ writel(BM_CTRL_ERROR, ®s->ctrl_clr);
+}
+
+static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
+ int assert, const char *caller)
+{
+ *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+
+ if (bank >= ARRAY_SIZE((*regs)->bank) ||
+ word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
+ !assert) {
+ printf("mxc_ocotp %s(): Invalid argument\n", caller);
+ return -EINVAL;
+ }
+
+ enable_ocotp_clk(1);
+
+ wait_busy(*regs, 1);
+ clear_error(*regs);
+
+ return 0;
+}
+
+static int finish_access(struct ocotp_regs *regs, const char *caller)
+{
+ u32 err;
+
+ err = !!(readl(®s->ctrl) & BM_CTRL_ERROR);
+ clear_error(regs);
+
+ enable_ocotp_clk(0);
+
+ if (err) {
+ printf("mxc_ocotp %s(): Access protect error\n", caller);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
+ const char *caller)
+{
+ return prepare_access(regs, bank, word, val != NULL, caller);
+}
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+ struct ocotp_regs *regs;
+ int ret;
+
+ ret = prepare_read(®s, bank, word, val, __func__);
+ if (ret)
+ return ret;
+
+ *val = readl(®s->bank[bank].fuse_regs[word << 2]);
+
+ return finish_access(regs, __func__);
+}
+
+static void set_timing(struct ocotp_regs *regs)
+{
+ u32 ipg_clk;
+ u32 relax, strobe_read, strobe_prog;
+ u32 timing;
+
+ ipg_clk = mxc_get_clock(MXC_IPG_CLK);
+
+ relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
+ strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
+ 1000000000) + 2 * (relax + 1) - 1;
+ strobe_prog = DIV_ROUND(ipg_clk * BV_TIMING_STROBE_PROG_US, 1000000) +
+ 2 * (relax + 1) - 1;
+
+ timing = BF(strobe_read, TIMING_STROBE_READ) |
+ BF(relax, TIMING_RELAX) |
+ BF(strobe_prog, TIMING_STROBE_PROG);
+
+ clrsetbits_le32(®s->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
+ BM_TIMING_STROBE_PROG, timing);
+}
+
+static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
+ int write)
+{
+ u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
+ u32 addr = bank << 3 | word;
+
+ set_timing(regs);
+ clrsetbits_le32(®s->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
+ BF(wr_unlock, CTRL_WR_UNLOCK) |
+ BF(addr, CTRL_ADDR));
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+ struct ocotp_regs *regs;
+ int ret;
+
+ ret = prepare_read(®s, bank, word, val, __func__);
+ if (ret)
+ return ret;
+
+ setup_direct_access(regs, bank, word, false);
+ writel(BM_READ_CTRL_READ_FUSE, ®s->read_ctrl);
+ wait_busy(regs, 1);
+ *val = readl(®s->read_fuse_data);
+
+ return finish_access(regs, __func__);
+}
+
+static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
+ const char *caller)
+{
+ return prepare_access(regs, bank, word, true, caller);
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+ struct ocotp_regs *regs;
+ int ret;
+
+ ret = prepare_write(®s, bank, word, __func__);
+ if (ret)
+ return ret;
+
+ setup_direct_access(regs, bank, word, true);
+ writel(val, ®s->data);
+ wait_busy(regs, BV_TIMING_STROBE_PROG_US);
+ udelay(WRITE_POSTAMBLE_US);
+
+ return finish_access(regs, __func__);
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+ struct ocotp_regs *regs;
+ int ret;
+
+ ret = prepare_write(®s, bank, word, __func__);
+ if (ret)
+ return ret;
+
+ writel(val, ®s->bank[bank].fuse_regs[word << 2]);
+
+ return finish_access(regs, __func__);
+}
data.dest = (char *)ext_csd;
data.blocks = 1;
- data.blocksize = 512;
+ data.blocksize = MMC_MAX_BLOCK_LEN;
data.flags = MMC_DATA_READ;
err = mmc_send_cmd(mmc, &cmd, &data);
static int mmc_change_freq(struct mmc *mmc)
{
- ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, 512);
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
char cardtype;
int err;
uint mult, freq;
u64 cmult, csize, capacity;
struct mmc_cmd cmd;
- ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, 512);
- ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, 512);
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
+ ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
int timeout = 1000;
#ifdef CONFIG_MMC_SPI_CRC_ON
mmc->capacity = (csize + 1) << (cmult + 2);
mmc->capacity *= mmc->read_bl_len;
- if (mmc->read_bl_len > 512)
- mmc->read_bl_len = 512;
+ if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
+ mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
- if (mmc->write_bl_len > 512)
- mmc->write_bl_len = 512;
+ if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
+ mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
/* Select the card, and put it into Transfer Mode */
if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
| ext_csd[EXT_CSD_SEC_CNT + 1] << 8
| ext_csd[EXT_CSD_SEC_CNT + 2] << 16
| ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
- capacity *= 512;
+ capacity *= MMC_MAX_BLOCK_LEN;
if ((capacity >> 20) > 2 * 1024)
mmc->capacity = capacity;
}
* group size from ext_csd directly, or calculate
* the group size from the csd value.
*/
- if (ext_csd[EXT_CSD_ERASE_GROUP_DEF])
+ if (ext_csd[EXT_CSD_ERASE_GROUP_DEF]) {
mmc->erase_grp_size =
- ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 512 * 1024;
- else {
+ ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
+ MMC_MAX_BLOCK_LEN * 1024;
+ } else {
int erase_gsz, erase_gmul;
erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
mmc->block_dev.lun = 0;
mmc->block_dev.type = 0;
mmc->block_dev.blksz = mmc->read_bl_len;
+ mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
#include <bouncebuf.h>
struct mxsmmc_priv {
static void mmc_load_image_raw(struct mmc *mmc)
{
- u32 image_size_sectors, err;
- const struct image_header *header;
+ unsigned long err;
+ u32 image_size_sectors;
+ struct image_header *header;
header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
sizeof(struct image_header));
/* read image header to find the image size & load address */
err = mmc->block_dev.block_read(0,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, 1,
- (void *)header);
+ header);
- if (err <= 0)
+ if (err == 0)
goto end;
spl_parse_image_header(header);
image_size_sectors, (void *)spl_image.load_addr);
end:
- if (err <= 0) {
- printf("spl: mmc blk read err - %d\n", err);
+ if (err == 0) {
+ printf("spl: mmc blk read err - %lu\n", err);
hang();
}
}
#ifdef CONFIG_SPL_FAT_SUPPORT
static void mmc_load_image_fat(struct mmc *mmc)
{
- s32 err;
+ int err;
struct image_header *header;
header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
}
err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME,
- (u8 *)header, sizeof(struct image_header));
+ header, sizeof(struct image_header));
if (err <= 0)
goto end;
endif
COBJS-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
+COBJS-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o
COBJS-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
COBJS-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
COBJS-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o
COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
+COBJS-$(CONFIG_NAND_DOCG4) += docg4.o
else # minimal SPL drivers
--- /dev/null
+/*
+ * drivers/mtd/nand/docg4.c
+ *
+ * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * mtd nand driver for M-Systems DiskOnChip G4
+ *
+ * Tested on the Palm Treo 680. The G4 is also present on Toshiba Portege, Asus
+ * P526, some HTC smartphones (Wizard, Prophet, ...), O2 XDA Zinc, maybe others.
+ * Should work on these as well. Let me know!
+ *
+ * TODO:
+ *
+ * Mechanism for management of password-protected areas
+ *
+ * Hamming ecc when reading oob only
+ *
+ * According to the M-Sys documentation, this device is also available in a
+ * "dual-die" configuration having a 256MB capacity, but no mechanism for
+ * detecting this variant is documented. Currently this driver assumes 128MB
+ * capacity.
+ *
+ * Support for multiple cascaded devices ("floors"). Not sure which gadgets
+ * contain multiple G4s in a cascaded configuration, if any.
+ *
+ */
+
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <asm/errno.h>
+#include <malloc.h>
+#include <nand.h>
+#include <linux/bch.h>
+#include <linux/bitrev.h>
+#include <linux/mtd/docg4.h>
+
+/*
+ * The device has a nop register which M-Sys claims is for the purpose of
+ * inserting precise delays. But beware; at least some operations fail if the
+ * nop writes are replaced with a generic delay!
+ */
+static inline void write_nop(void __iomem *docptr)
+{
+ writew(0, docptr + DOC_NOP);
+}
+
+
+static int poll_status(void __iomem *docptr)
+{
+ /*
+ * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL
+ * register. Operations known to take a long time (e.g., block erase)
+ * should sleep for a while before calling this.
+ */
+
+ uint8_t flash_status;
+
+ /* hardware quirk requires reading twice initially */
+ flash_status = readb(docptr + DOC_FLASHCONTROL);
+
+ do {
+ flash_status = readb(docptr + DOC_FLASHCONTROL);
+ } while (!(flash_status & DOC_CTRL_FLASHREADY));
+
+ return 0;
+}
+
+static void write_addr(void __iomem *docptr, uint32_t docg4_addr)
+{
+ /* write the four address bytes packed in docg4_addr to the device */
+
+ writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
+ docg4_addr >>= 8;
+ writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
+ docg4_addr >>= 8;
+ writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
+ docg4_addr >>= 8;
+ writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
+}
+
+/*
+ * This is a module parameter in the linux kernel version of this driver. It is
+ * hard-coded to 'off' for u-boot. This driver uses oob to mark bad blocks.
+ * This can be problematic when dealing with data not intended for the mtd/nand
+ * subsystem. For example, on boards that boot from the docg4 and use the IPL
+ * to load an spl + u-boot image, the blocks containing the image will be
+ * reported as "bad" because the oob of the first page of each block contains a
+ * magic number that the IPL looks for, which causes the badblock scan to
+ * erroneously add them to the bad block table. To erase such a block, use
+ * u-boot's 'nand scrub'. scrub is safe for the docg4. The device does have a
+ * factory bad block table, but it is read-only, and is used in conjunction with
+ * oob bad block markers that are written by mtd/nand when a block is deemed to
+ * be bad. To read data from "bad" blocks, use 'read.raw'. Unfortunately,
+ * read.raw does not use ecc, which would still work fine on such misidentified
+ * bad blocks. TODO: u-boot nand utilities need the ability to ignore bad
+ * blocks.
+ */
+static const int ignore_badblocks; /* remains false */
+
+struct docg4_priv {
+ int status;
+ struct {
+ unsigned int command;
+ int column;
+ int page;
+ } last_command;
+ uint8_t oob_buf[16];
+ uint8_t ecc_buf[7];
+ int oob_page;
+ struct bch_control *bch;
+};
+/*
+ * Oob bytes 0 - 6 are available to the user.
+ * Byte 7 is hamming ecc for first 7 bytes. Bytes 8 - 14 are hw-generated ecc.
+ * Byte 15 (the last) is used by the driver as a "page written" flag.
+ */
+static struct nand_ecclayout docg4_oobinfo = {
+ .eccbytes = 9,
+ .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
+ .oobavail = 7,
+ .oobfree = { {0, 7} }
+};
+
+static void reset(void __iomem *docptr)
+{
+ /* full device reset */
+
+ writew(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN, docptr + DOC_ASICMODE);
+ writew(~(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN),
+ docptr + DOC_ASICMODECONFIRM);
+ write_nop(docptr);
+
+ writew(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN,
+ docptr + DOC_ASICMODE);
+ writew(~(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN),
+ docptr + DOC_ASICMODECONFIRM);
+
+ writew(DOC_ECCCONF1_ECC_ENABLE, docptr + DOC_ECCCONF1);
+
+ poll_status(docptr);
+}
+
+static void docg4_select_chip(struct mtd_info *mtd, int chip)
+{
+ /*
+ * Select among multiple cascaded chips ("floors"). Multiple floors are
+ * not yet supported, so the only valid non-negative value is 0.
+ */
+ void __iomem *docptr = CONFIG_SYS_NAND_BASE;
+
+ if (chip < 0)
+ return; /* deselected */
+
+ if (chip > 0)
+ printf("multiple floors currently unsupported\n");
+
+ writew(0, docptr + DOC_DEVICESELECT);
+}
+
+static void read_hw_ecc(void __iomem *docptr, uint8_t *ecc_buf)
+{
+ /* read the 7 hw-generated ecc bytes */
+
+ int i;
+ for (i = 0; i < 7; i++) { /* hw quirk; read twice */
+ ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
+ ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
+ }
+}
+
+static int correct_data(struct mtd_info *mtd, uint8_t *buf, int page)
+{
+ /*
+ * Called after a page read when hardware reports bitflips.
+ * Up to four bitflips can be corrected.
+ */
+
+ struct nand_chip *nand = mtd->priv;
+ struct docg4_priv *doc = nand->priv;
+ void __iomem *docptr = CONFIG_SYS_NAND_BASE;
+ int i, numerrs;
+ unsigned int errpos[4];
+ const uint8_t blank_read_hwecc[8] = {
+ 0xcf, 0x72, 0xfc, 0x1b, 0xa9, 0xc7, 0xb9, 0 };
+
+ read_hw_ecc(docptr, doc->ecc_buf); /* read 7 hw-generated ecc bytes */
+
+ /* check if read error is due to a blank page */
+ if (!memcmp(doc->ecc_buf, blank_read_hwecc, 7))
+ return 0; /* yes */
+
+ /* skip additional check of "written flag" if ignore_badblocks */
+ if (!ignore_badblocks) {
+ /*
+ * If the hw ecc bytes are not those of a blank page, there's
+ * still a chance that the page is blank, but was read with
+ * errors. Check the "written flag" in last oob byte, which
+ * is set to zero when a page is written. If more than half
+ * the bits are set, assume a blank page. Unfortunately, the
+ * bit flips(s) are not reported in stats.
+ */
+
+ if (doc->oob_buf[15]) {
+ int bit, numsetbits = 0;
+ unsigned long written_flag = doc->oob_buf[15];
+
+ for (bit = 0; bit < 8; bit++) {
+ if (written_flag & 0x01)
+ numsetbits++;
+ written_flag >>= 1;
+ }
+ if (numsetbits > 4) { /* assume blank */
+ printf("errors in blank page at offset %08x\n",
+ page * DOCG4_PAGE_SIZE);
+ return 0;
+ }
+ }
+ }
+
+ /*
+ * The hardware ecc unit produces oob_ecc ^ calc_ecc. The kernel's bch
+ * algorithm is used to decode this. However the hw operates on page
+ * data in a bit order that is the reverse of that of the bch alg,
+ * requiring that the bits be reversed on the result. Thanks to Ivan
+ * Djelic for his analysis!
+ */
+ for (i = 0; i < 7; i++)
+ doc->ecc_buf[i] = bitrev8(doc->ecc_buf[i]);
+
+ numerrs = decode_bch(doc->bch, NULL, DOCG4_USERDATA_LEN, NULL,
+ doc->ecc_buf, NULL, errpos);
+
+ if (numerrs == -EBADMSG) {
+ printf("uncorrectable errors at offset %08x\n",
+ page * DOCG4_PAGE_SIZE);
+ return -EBADMSG;
+ }
+
+ BUG_ON(numerrs < 0); /* -EINVAL, or anything other than -EBADMSG */
+
+ /* undo last step in BCH alg (modulo mirroring not needed) */
+ for (i = 0; i < numerrs; i++)
+ errpos[i] = (errpos[i] & ~7)|(7-(errpos[i] & 7));
+
+ /* fix the errors */
+ for (i = 0; i < numerrs; i++) {
+ /* ignore if error within oob ecc bytes */
+ if (errpos[i] > DOCG4_USERDATA_LEN * 8)
+ continue;
+
+ /* if error within oob area preceeding ecc bytes... */
+ if (errpos[i] > DOCG4_PAGE_SIZE * 8)
+ __change_bit(errpos[i] - DOCG4_PAGE_SIZE * 8,
+ (unsigned long *)doc->oob_buf);
+
+ else /* error in page data */
+ __change_bit(errpos[i], (unsigned long *)buf);
+ }
+
+ printf("%d error(s) corrected at offset %08x\n",
+ numerrs, page * DOCG4_PAGE_SIZE);
+
+ return numerrs;
+}
+
+static int read_progstatus(struct docg4_priv *doc, void __iomem *docptr)
+{
+ /*
+ * This apparently checks the status of programming. Done after an
+ * erasure, and after page data is written. On error, the status is
+ * saved, to be later retrieved by the nand infrastructure code.
+ */
+
+ /* status is read from the I/O reg */
+ uint16_t status1 = readw(docptr + DOC_IOSPACE_DATA);
+ uint16_t status2 = readw(docptr + DOC_IOSPACE_DATA);
+ uint16_t status3 = readw(docptr + DOCG4_MYSTERY_REG);
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "docg4: %s: %02x %02x %02x\n",
+ __func__, status1, status2, status3);
+
+ if (status1 != DOCG4_PROGSTATUS_GOOD ||
+ status2 != DOCG4_PROGSTATUS_GOOD_2 ||
+ status3 != DOCG4_PROGSTATUS_GOOD_2) {
+ doc->status = NAND_STATUS_FAIL;
+ printf("read_progstatus failed: %02x, %02x, %02x\n",
+ status1, status2, status3);
+ return -EIO;
+ }
+ return 0;
+}
+
+static int pageprog(struct mtd_info *mtd)
+{
+ /*
+ * Final step in writing a page. Writes the contents of its
+ * internal buffer out to the flash array, or some such.
+ */
+
+ struct nand_chip *nand = mtd->priv;
+ struct docg4_priv *doc = nand->priv;
+ void __iomem *docptr = CONFIG_SYS_NAND_BASE;
+ int retval = 0;
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "docg4: %s\n", __func__);
+
+ writew(DOCG4_SEQ_PAGEPROG, docptr + DOC_FLASHSEQUENCE);
+ writew(DOC_CMD_PROG_CYCLE2, docptr + DOC_FLASHCOMMAND);
+ write_nop(docptr);
+ write_nop(docptr);
+
+ /* Just busy-wait; usleep_range() slows things down noticeably. */
+ poll_status(docptr);
+
+ writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
+ writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
+ writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+
+ retval = read_progstatus(doc, docptr);
+ writew(0, docptr + DOC_DATAEND);
+ write_nop(docptr);
+ poll_status(docptr);
+ write_nop(docptr);
+
+ return retval;
+}
+
+static void sequence_reset(void __iomem *docptr)
+{
+ /* common starting sequence for all operations */
+
+ writew(DOC_CTRL_UNKNOWN | DOC_CTRL_CE, docptr + DOC_FLASHCONTROL);
+ writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
+ writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
+ write_nop(docptr);
+ write_nop(docptr);
+ poll_status(docptr);
+ write_nop(docptr);
+}
+
+static void read_page_prologue(void __iomem *docptr, uint32_t docg4_addr)
+{
+ /* first step in reading a page */
+
+ sequence_reset(docptr);
+
+ writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE);
+ writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND);
+ write_nop(docptr);
+
+ write_addr(docptr, docg4_addr);
+
+ write_nop(docptr);
+ writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
+ write_nop(docptr);
+ write_nop(docptr);
+
+ poll_status(docptr);
+}
+
+static void write_page_prologue(void __iomem *docptr, uint32_t docg4_addr)
+{
+ /* first step in writing a page */
+
+ sequence_reset(docptr);
+ writew(DOCG4_SEQ_PAGEWRITE, docptr + DOC_FLASHSEQUENCE);
+ writew(DOCG4_CMD_PAGEWRITE, docptr + DOC_FLASHCOMMAND);
+ write_nop(docptr);
+ write_addr(docptr, docg4_addr);
+ write_nop(docptr);
+ write_nop(docptr);
+ poll_status(docptr);
+}
+
+static uint32_t mtd_to_docg4_address(int page, int column)
+{
+ /*
+ * Convert mtd address to format used by the device, 32 bit packed.
+ *
+ * Some notes on G4 addressing... The M-Sys documentation on this device
+ * claims that pages are 2K in length, and indeed, the format of the
+ * address used by the device reflects that. But within each page are
+ * four 512 byte "sub-pages", each with its own oob data that is
+ * read/written immediately after the 512 bytes of page data. This oob
+ * data contains the ecc bytes for the preceeding 512 bytes.
+ *
+ * Rather than tell the mtd nand infrastructure that page size is 2k,
+ * with four sub-pages each, we engage in a little subterfuge and tell
+ * the infrastructure code that pages are 512 bytes in size. This is
+ * done because during the course of reverse-engineering the device, I
+ * never observed an instance where an entire 2K "page" was read or
+ * written as a unit. Each "sub-page" is always addressed individually,
+ * its data read/written, and ecc handled before the next "sub-page" is
+ * addressed.
+ *
+ * This requires us to convert addresses passed by the mtd nand
+ * infrastructure code to those used by the device.
+ *
+ * The address that is written to the device consists of four bytes: the
+ * first two are the 2k page number, and the second is the index into
+ * the page. The index is in terms of 16-bit half-words and includes
+ * the preceeding oob data, so e.g., the index into the second
+ * "sub-page" is 0x108, and the full device address of the start of mtd
+ * page 0x201 is 0x00800108.
+ */
+ int g4_page = page / 4; /* device's 2K page */
+ int g4_index = (page % 4) * 0x108 + column/2; /* offset into page */
+ return (g4_page << 16) | g4_index; /* pack */
+}
+
+static void docg4_command(struct mtd_info *mtd, unsigned command, int column,
+ int page_addr)
+{
+ /* handle standard nand commands */
+
+ struct nand_chip *nand = mtd->priv;
+ struct docg4_priv *doc = nand->priv;
+ uint32_t g4_addr = mtd_to_docg4_address(page_addr, column);
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "%s %x, page_addr=%x, column=%x\n",
+ __func__, command, page_addr, column);
+
+ /*
+ * Save the command and its arguments. This enables emulation of
+ * standard flash devices, and also some optimizations.
+ */
+ doc->last_command.command = command;
+ doc->last_command.column = column;
+ doc->last_command.page = page_addr;
+
+ switch (command) {
+ case NAND_CMD_RESET:
+ reset(CONFIG_SYS_NAND_BASE);
+ break;
+
+ case NAND_CMD_READ0:
+ read_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
+ break;
+
+ case NAND_CMD_STATUS:
+ /* next call to read_byte() will expect a status */
+ break;
+
+ case NAND_CMD_SEQIN:
+ write_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
+
+ /* hack for deferred write of oob bytes */
+ if (doc->oob_page == page_addr)
+ memcpy(nand->oob_poi, doc->oob_buf, 16);
+ break;
+
+ case NAND_CMD_PAGEPROG:
+ pageprog(mtd);
+ break;
+
+ /* we don't expect these, based on review of nand_base.c */
+ case NAND_CMD_READOOB:
+ case NAND_CMD_READID:
+ case NAND_CMD_ERASE1:
+ case NAND_CMD_ERASE2:
+ printf("docg4_command: unexpected nand command 0x%x\n",
+ command);
+ break;
+ }
+}
+
+static void docg4_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ int i;
+ struct nand_chip *nand = mtd->priv;
+ uint16_t *p = (uint16_t *)buf;
+ len >>= 1;
+
+ for (i = 0; i < len; i++)
+ p[i] = readw(nand->IO_ADDR_R);
+}
+
+static int docg4_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
+ int page, int sndcmd)
+{
+ struct docg4_priv *doc = nand->priv;
+ void __iomem *docptr = CONFIG_SYS_NAND_BASE;
+ uint16_t status;
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: page %x\n", __func__, page);
+
+ /*
+ * Oob bytes are read as part of a normal page read. If the previous
+ * nand command was a read of the page whose oob is now being read, just
+ * copy the oob bytes that we saved in a local buffer and avoid a
+ * separate oob read.
+ */
+ if (doc->last_command.command == NAND_CMD_READ0 &&
+ doc->last_command.page == page) {
+ memcpy(nand->oob_poi, doc->oob_buf, 16);
+ return 0;
+ }
+
+ /*
+ * Separate read of oob data only.
+ */
+ docg4_command(mtd, NAND_CMD_READ0, nand->ecc.size, page);
+
+ writew(DOC_ECCCONF0_READ_MODE | DOCG4_OOB_SIZE, docptr + DOC_ECCCONF0);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+
+ /* the 1st byte from the I/O reg is a status; the rest is oob data */
+ status = readw(docptr + DOC_IOSPACE_DATA);
+ if (status & DOCG4_READ_ERROR) {
+ printf("docg4_read_oob failed: status = 0x%02x\n", status);
+ return -EIO;
+ }
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: status = 0x%x\n", __func__, status);
+
+ docg4_read_buf(mtd, nand->oob_poi, 16);
+
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+ writew(0, docptr + DOC_DATAEND);
+ write_nop(docptr);
+
+ return 0;
+}
+
+static int docg4_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
+ int page)
+{
+ /*
+ * Writing oob-only is not really supported, because MLC nand must write
+ * oob bytes at the same time as page data. Nonetheless, we save the
+ * oob buffer contents here, and then write it along with the page data
+ * if the same page is subsequently written. This allows user space
+ * utilities that write the oob data prior to the page data to work
+ * (e.g., nandwrite). The disdvantage is that, if the intention was to
+ * write oob only, the operation is quietly ignored. Also, oob can get
+ * corrupted if two concurrent processes are running nandwrite.
+ */
+
+ /* note that bytes 7..14 are hw generated hamming/ecc and overwritten */
+ struct docg4_priv *doc = nand->priv;
+ doc->oob_page = page;
+ memcpy(doc->oob_buf, nand->oob_poi, 16);
+ return 0;
+}
+
+static int docg4_block_neverbad(struct mtd_info *mtd, loff_t ofs, int getchip)
+{
+ /* only called when module_param ignore_badblocks is set */
+ return 0;
+}
+
+static void docg4_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+ int i;
+ struct nand_chip *nand = mtd->priv;
+ uint16_t *p = (uint16_t *)buf;
+ len >>= 1;
+
+ for (i = 0; i < len; i++)
+ writew(p[i], nand->IO_ADDR_W);
+}
+
+static void write_page(struct mtd_info *mtd, struct nand_chip *nand,
+ const uint8_t *buf, int use_ecc)
+{
+ void __iomem *docptr = CONFIG_SYS_NAND_BASE;
+ uint8_t ecc_buf[8];
+
+ writew(DOC_ECCCONF0_ECC_ENABLE |
+ DOC_ECCCONF0_UNKNOWN |
+ DOCG4_BCH_SIZE,
+ docptr + DOC_ECCCONF0);
+ write_nop(docptr);
+
+ /* write the page data */
+ docg4_write_buf16(mtd, buf, DOCG4_PAGE_SIZE);
+
+ /* oob bytes 0 through 5 are written to I/O reg */
+ docg4_write_buf16(mtd, nand->oob_poi, 6);
+
+ /* oob byte 6 written to a separate reg */
+ writew(nand->oob_poi[6], docptr + DOCG4_OOB_6_7);
+
+ write_nop(docptr);
+ write_nop(docptr);
+
+ /* write hw-generated ecc bytes to oob */
+ if (likely(use_ecc)) {
+ /* oob byte 7 is hamming code */
+ uint8_t hamming = readb(docptr + DOC_HAMMINGPARITY);
+ hamming = readb(docptr + DOC_HAMMINGPARITY); /* 2nd read */
+ writew(hamming, docptr + DOCG4_OOB_6_7);
+ write_nop(docptr);
+
+ /* read the 7 bch bytes from ecc regs */
+ read_hw_ecc(docptr, ecc_buf);
+ ecc_buf[7] = 0; /* clear the "page written" flag */
+ }
+
+ /* write user-supplied bytes to oob */
+ else {
+ writew(nand->oob_poi[7], docptr + DOCG4_OOB_6_7);
+ write_nop(docptr);
+ memcpy(ecc_buf, &nand->oob_poi[8], 8);
+ }
+
+ docg4_write_buf16(mtd, ecc_buf, 8);
+ write_nop(docptr);
+ write_nop(docptr);
+ writew(0, docptr + DOC_DATAEND);
+ write_nop(docptr);
+}
+
+static void docg4_write_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
+ const uint8_t *buf)
+{
+ return write_page(mtd, nand, buf, 0);
+}
+
+static void docg4_write_page(struct mtd_info *mtd, struct nand_chip *nand,
+ const uint8_t *buf)
+{
+ return write_page(mtd, nand, buf, 1);
+}
+
+static int read_page(struct mtd_info *mtd, struct nand_chip *nand,
+ uint8_t *buf, int page, int use_ecc)
+{
+ struct docg4_priv *doc = nand->priv;
+ void __iomem *docptr = CONFIG_SYS_NAND_BASE;
+ uint16_t status, edc_err, *buf16;
+
+ writew(DOC_ECCCONF0_READ_MODE |
+ DOC_ECCCONF0_ECC_ENABLE |
+ DOC_ECCCONF0_UNKNOWN |
+ DOCG4_BCH_SIZE,
+ docptr + DOC_ECCCONF0);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+
+ /* the 1st byte from the I/O reg is a status; the rest is page data */
+ status = readw(docptr + DOC_IOSPACE_DATA);
+ if (status & DOCG4_READ_ERROR) {
+ printf("docg4_read_page: bad status: 0x%02x\n", status);
+ writew(0, docptr + DOC_DATAEND);
+ return -EIO;
+ }
+
+ docg4_read_buf(mtd, buf, DOCG4_PAGE_SIZE); /* read the page data */
+
+ /* first 14 oob bytes read from I/O reg */
+ docg4_read_buf(mtd, nand->oob_poi, 14);
+
+ /* last 2 read from another reg */
+ buf16 = (uint16_t *)(nand->oob_poi + 14);
+ *buf16 = readw(docptr + DOCG4_MYSTERY_REG);
+
+ /*
+ * Diskonchips read oob immediately after a page read. Mtd
+ * infrastructure issues a separate command for reading oob after the
+ * page is read. So we save the oob bytes in a local buffer and just
+ * copy it if the next command reads oob from the same page.
+ */
+ memcpy(doc->oob_buf, nand->oob_poi, 16);
+
+ write_nop(docptr);
+
+ if (likely(use_ecc)) {
+ /* read the register that tells us if bitflip(s) detected */
+ edc_err = readw(docptr + DOC_ECCCONF1);
+ edc_err = readw(docptr + DOC_ECCCONF1);
+
+ /* If bitflips are reported, attempt to correct with ecc */
+ if (edc_err & DOC_ECCCONF1_BCH_SYNDROM_ERR) {
+ int bits_corrected = correct_data(mtd, buf, page);
+ if (bits_corrected == -EBADMSG)
+ mtd->ecc_stats.failed++;
+ else
+ mtd->ecc_stats.corrected += bits_corrected;
+ }
+ }
+
+ writew(0, docptr + DOC_DATAEND);
+ return 0;
+}
+
+
+static int docg4_read_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
+ uint8_t *buf, int page)
+{
+ return read_page(mtd, nand, buf, page, 0);
+}
+
+static int docg4_read_page(struct mtd_info *mtd, struct nand_chip *nand,
+ uint8_t *buf, int page)
+{
+ return read_page(mtd, nand, buf, page, 1);
+}
+
+static void docg4_erase_block(struct mtd_info *mtd, int page)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct docg4_priv *doc = nand->priv;
+ void __iomem *docptr = CONFIG_SYS_NAND_BASE;
+ uint16_t g4_page;
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: page %04x\n", __func__, page);
+
+ sequence_reset(docptr);
+
+ writew(DOCG4_SEQ_BLOCKERASE, docptr + DOC_FLASHSEQUENCE);
+ writew(DOC_CMD_PROG_BLOCK_ADDR, docptr + DOC_FLASHCOMMAND);
+ write_nop(docptr);
+
+ /* only 2 bytes of address are written to specify erase block */
+ g4_page = (uint16_t)(page / 4); /* to g4's 2k page addressing */
+ writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
+ g4_page >>= 8;
+ writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
+ write_nop(docptr);
+
+ /* start the erasure */
+ writew(DOC_CMD_ERASECYCLE2, docptr + DOC_FLASHCOMMAND);
+ write_nop(docptr);
+ write_nop(docptr);
+
+ poll_status(docptr);
+ writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
+ writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
+ writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+
+ read_progstatus(doc, docptr);
+
+ writew(0, docptr + DOC_DATAEND);
+ write_nop(docptr);
+ poll_status(docptr);
+ write_nop(docptr);
+}
+
+static int read_factory_bbt(struct mtd_info *mtd)
+{
+ /*
+ * The device contains a read-only factory bad block table. Read it and
+ * update the memory-based bbt accordingly.
+ */
+
+ struct nand_chip *nand = mtd->priv;
+ uint32_t g4_addr = mtd_to_docg4_address(DOCG4_FACTORY_BBT_PAGE, 0);
+ uint8_t *buf;
+ int i, block, status;
+
+ buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
+ if (buf == NULL)
+ return -ENOMEM;
+
+ read_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
+ status = docg4_read_page(mtd, nand, buf, DOCG4_FACTORY_BBT_PAGE);
+ if (status)
+ goto exit;
+
+ /*
+ * If no memory-based bbt was created, exit. This will happen if module
+ * parameter ignore_badblocks is set. Then why even call this function?
+ * For an unknown reason, block erase always fails if it's the first
+ * operation after device power-up. The above read ensures it never is.
+ * Ugly, I know.
+ */
+ if (nand->bbt == NULL) /* no memory-based bbt */
+ goto exit;
+
+ /*
+ * Parse factory bbt and update memory-based bbt. Factory bbt format is
+ * simple: one bit per block, block numbers increase left to right (msb
+ * to lsb). Bit clear means bad block.
+ */
+ for (i = block = 0; block < DOCG4_NUMBLOCKS; block += 8, i++) {
+ int bitnum;
+ uint8_t mask;
+ for (bitnum = 0, mask = 0x80;
+ bitnum < 8; bitnum++, mask >>= 1) {
+ if (!(buf[i] & mask)) {
+ int badblock = block + bitnum;
+ nand->bbt[badblock / 4] |=
+ 0x03 << ((badblock % 4) * 2);
+ mtd->ecc_stats.badblocks++;
+ printf("factory-marked bad block: %d\n",
+ badblock);
+ }
+ }
+ }
+ exit:
+ kfree(buf);
+ return status;
+}
+
+static int docg4_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+ /*
+ * Mark a block as bad. Bad blocks are marked in the oob area of the
+ * first page of the block. The default scan_bbt() in the nand
+ * infrastructure code works fine for building the memory-based bbt
+ * during initialization, as does the nand infrastructure function that
+ * checks if a block is bad by reading the bbt. This function replaces
+ * the nand default because writes to oob-only are not supported.
+ */
+
+ int ret, i;
+ uint8_t *buf;
+ struct nand_chip *nand = mtd->priv;
+ struct nand_bbt_descr *bbtd = nand->badblock_pattern;
+ int block = (int)(ofs >> nand->bbt_erase_shift);
+ int page = (int)(ofs >> nand->page_shift);
+ uint32_t g4_addr = mtd_to_docg4_address(page, 0);
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: %08llx\n", __func__, ofs);
+
+ if (unlikely(ofs & (DOCG4_BLOCK_SIZE - 1)))
+ printf("%s: ofs %llx not start of block!\n",
+ __func__, ofs);
+
+ /* allocate blank buffer for page data */
+ buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
+ if (buf == NULL)
+ return -ENOMEM;
+
+ /* update bbt in memory */
+ nand->bbt[block / 4] |= 0x01 << ((block & 0x03) * 2);
+
+ /* write bit-wise negation of pattern to oob buffer */
+ memset(nand->oob_poi, 0xff, mtd->oobsize);
+ for (i = 0; i < bbtd->len; i++)
+ nand->oob_poi[bbtd->offs + i] = ~bbtd->pattern[i];
+
+ /* write first page of block */
+ write_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
+ docg4_write_page(mtd, nand, buf);
+ ret = pageprog(mtd);
+ if (!ret)
+ mtd->ecc_stats.badblocks++;
+
+ kfree(buf);
+
+ return ret;
+}
+
+static uint8_t docg4_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct docg4_priv *doc = nand->priv;
+
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "%s\n", __func__);
+
+ if (doc->last_command.command == NAND_CMD_STATUS) {
+ int status;
+
+ /*
+ * Previous nand command was status request, so nand
+ * infrastructure code expects to read the status here. If an
+ * error occurred in a previous operation, report it.
+ */
+ doc->last_command.command = 0;
+
+ if (doc->status) {
+ status = doc->status;
+ doc->status = 0;
+ }
+
+ /* why is NAND_STATUS_WP inverse logic?? */
+ else
+ status = NAND_STATUS_WP | NAND_STATUS_READY;
+
+ return status;
+ }
+
+ printf("unexpectd call to read_byte()\n");
+
+ return 0;
+}
+
+static int docg4_wait(struct mtd_info *mtd, struct nand_chip *nand)
+{
+ struct docg4_priv *doc = nand->priv;
+ int status = NAND_STATUS_WP; /* inverse logic?? */
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "%s...\n", __func__);
+
+ /* report any previously unreported error */
+ if (doc->status) {
+ status |= doc->status;
+ doc->status = 0;
+ return status;
+ }
+
+ status |= poll_status(CONFIG_SYS_NAND_BASE);
+ return status;
+}
+
+int docg4_nand_init(struct mtd_info *mtd, struct nand_chip *nand, int devnum)
+{
+ uint16_t id1, id2;
+ struct docg4_priv *docg4;
+ int retval;
+
+ docg4 = kzalloc(sizeof(*docg4), GFP_KERNEL);
+ if (!docg4)
+ return -1;
+
+ mtd->priv = nand;
+ nand->priv = docg4;
+
+ /* These must be initialized here because the docg4 is non-standard
+ * and doesn't produce an id that the nand code can use to look up
+ * these values (nand_scan_ident() not called).
+ */
+ mtd->size = DOCG4_CHIP_SIZE;
+ mtd->name = "Msys_Diskonchip_G4";
+ mtd->writesize = DOCG4_PAGE_SIZE;
+ mtd->erasesize = DOCG4_BLOCK_SIZE;
+ mtd->oobsize = DOCG4_OOB_SIZE;
+
+ nand->IO_ADDR_R =
+ (void __iomem *)CONFIG_SYS_NAND_BASE + DOC_IOSPACE_DATA;
+ nand->IO_ADDR_W = nand->IO_ADDR_R;
+ nand->chipsize = DOCG4_CHIP_SIZE;
+ nand->chip_shift = DOCG4_CHIP_SHIFT;
+ nand->bbt_erase_shift = DOCG4_ERASE_SHIFT;
+ nand->phys_erase_shift = DOCG4_ERASE_SHIFT;
+ nand->chip_delay = 20;
+ nand->page_shift = DOCG4_PAGE_SHIFT;
+ nand->pagemask = 0x3ffff;
+ nand->badblockpos = NAND_LARGE_BADBLOCK_POS;
+ nand->badblockbits = 8;
+ nand->ecc.layout = &docg4_oobinfo;
+ nand->ecc.mode = NAND_ECC_HW_SYNDROME;
+ nand->ecc.size = DOCG4_PAGE_SIZE;
+ nand->ecc.prepad = 8;
+ nand->ecc.bytes = 8;
+ nand->options =
+ NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE | NAND_NO_AUTOINCR;
+ nand->controller = &nand->hwcontrol;
+
+ /* methods */
+ nand->cmdfunc = docg4_command;
+ nand->waitfunc = docg4_wait;
+ nand->select_chip = docg4_select_chip;
+ nand->read_byte = docg4_read_byte;
+ nand->block_markbad = docg4_block_markbad;
+ nand->read_buf = docg4_read_buf;
+ nand->write_buf = docg4_write_buf16;
+ nand->scan_bbt = nand_default_bbt;
+ nand->erase_cmd = docg4_erase_block;
+ nand->ecc.read_page = docg4_read_page;
+ nand->ecc.write_page = docg4_write_page;
+ nand->ecc.read_page_raw = docg4_read_page_raw;
+ nand->ecc.write_page_raw = docg4_write_page_raw;
+ nand->ecc.read_oob = docg4_read_oob;
+ nand->ecc.write_oob = docg4_write_oob;
+
+ /*
+ * The way the nand infrastructure code is written, a memory-based bbt
+ * is not created if NAND_SKIP_BBTSCAN is set. With no memory bbt,
+ * nand->block_bad() is used. So when ignoring bad blocks, we skip the
+ * scan and define a dummy block_bad() which always returns 0.
+ */
+ if (ignore_badblocks) {
+ nand->options |= NAND_SKIP_BBTSCAN;
+ nand->block_bad = docg4_block_neverbad;
+ }
+
+ reset(CONFIG_SYS_NAND_BASE);
+
+ /* check for presence of g4 chip by reading id registers */
+ id1 = readw(CONFIG_SYS_NAND_BASE + DOC_CHIPID);
+ id1 = readw(CONFIG_SYS_NAND_BASE + DOCG4_MYSTERY_REG);
+ id2 = readw(CONFIG_SYS_NAND_BASE + DOC_CHIPID_INV);
+ id2 = readw(CONFIG_SYS_NAND_BASE + DOCG4_MYSTERY_REG);
+ if (id1 != DOCG4_IDREG1_VALUE || id2 != DOCG4_IDREG2_VALUE)
+ return -1;
+
+ /* initialize bch algorithm */
+ docg4->bch = init_bch(DOCG4_M, DOCG4_T, DOCG4_PRIMITIVE_POLY);
+ if (docg4->bch == NULL)
+ return -1;
+
+ retval = nand_scan_tail(mtd);
+ if (retval)
+ return -1;
+
+ /*
+ * Scan for bad blocks and create bbt here, then add the factory-marked
+ * bad blocks to the bbt.
+ */
+ nand->scan_bbt(mtd);
+ nand->options |= NAND_BBT_SCANNED;
+ retval = read_factory_bbt(mtd);
+ if (retval)
+ return -1;
+
+ retval = nand_register(devnum);
+ if (retval)
+ return -1;
+
+ return 0;
+}
--- /dev/null
+/*
+ * SPL driver for Diskonchip G4 nand flash
+ *
+ * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ *
+ * This driver basically mimics the load functionality of a typical IPL (initial
+ * program loader) resident in the 2k NOR-like region of the docg4 that is
+ * mapped to the reset vector. It allows the u-boot SPL to continue loading if
+ * the IPL loads a fixed number of flash blocks that is insufficient to contain
+ * the entire u-boot image. In this case, a concatenated spl + u-boot image is
+ * written at the flash offset from which the IPL loads an image, and when the
+ * IPL jumps to the SPL, the SPL resumes loading where the IPL left off. See
+ * the palmtreo680 for an example.
+ *
+ * This driver assumes that the data was written to the flash using the device's
+ * "reliable" mode, and also assumes that each 512 byte page is stored
+ * redundantly in the subsequent page. This storage format is likely to be used
+ * by all boards that boot from the docg4. The format compensates for the lack
+ * of ecc in the IPL.
+ *
+ * Reliable mode reduces the capacity of a block by half, and the redundant
+ * pages reduce it by half again. As a result, the normal 256k capacity of a
+ * block is reduced to 64k for the purposes of the IPL/SPL.
+ */
+
+#include <asm/io.h>
+#include <linux/mtd/docg4.h>
+
+/* forward declarations */
+static inline void write_nop(void __iomem *docptr);
+static int poll_status(void __iomem *docptr);
+static void write_addr(void __iomem *docptr, uint32_t docg4_addr);
+static void address_sequence(unsigned int g4_page, unsigned int g4_index,
+ void __iomem *docptr);
+static int docg4_load_block_reliable(uint32_t flash_offset, void *dest_addr);
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+ void *load_addr = dst;
+ uint32_t flash_offset = offs;
+ const unsigned int block_count =
+ (size + DOCG4_BLOCK_CAPACITY_SPL - 1)
+ / DOCG4_BLOCK_CAPACITY_SPL;
+ int i;
+
+ for (i = 0; i < block_count; i++) {
+ int ret = docg4_load_block_reliable(flash_offset, load_addr);
+ if (ret)
+ return ret;
+ load_addr += DOCG4_BLOCK_CAPACITY_SPL;
+ flash_offset += DOCG4_BLOCK_SIZE;
+ }
+ return 0;
+}
+
+static inline void write_nop(void __iomem *docptr)
+{
+ writew(0, docptr + DOC_NOP);
+}
+
+static int poll_status(void __iomem *docptr)
+{
+ /*
+ * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL
+ * register. Operations known to take a long time (e.g., block erase)
+ * should sleep for a while before calling this.
+ */
+
+ uint8_t flash_status;
+
+ /* hardware quirk requires reading twice initially */
+ flash_status = readb(docptr + DOC_FLASHCONTROL);
+
+ do {
+ flash_status = readb(docptr + DOC_FLASHCONTROL);
+ } while (!(flash_status & DOC_CTRL_FLASHREADY));
+
+ return 0;
+}
+
+static void write_addr(void __iomem *docptr, uint32_t docg4_addr)
+{
+ /* write the four address bytes packed in docg4_addr to the device */
+
+ writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
+ docg4_addr >>= 8;
+ writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
+ docg4_addr >>= 8;
+ writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
+ docg4_addr >>= 8;
+ writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
+}
+
+static void address_sequence(unsigned int g4_page, unsigned int g4_index,
+ void __iomem *docptr)
+{
+ writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE);
+ writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND);
+ write_nop(docptr);
+ write_addr(docptr, ((uint32_t)g4_page << 16) | g4_index);
+ write_nop(docptr);
+}
+
+static int docg4_load_block_reliable(uint32_t flash_offset, void *dest_addr)
+{
+ void __iomem *docptr = (void *)CONFIG_SYS_NAND_BASE;
+ unsigned int g4_page = flash_offset >> 11; /* 2k page */
+ const unsigned int last_g4_page = g4_page + 0x80; /* last in block */
+ int g4_index = 0;
+ uint16_t flash_status;
+ uint16_t *buf;
+ uint16_t discard, magic_high, magic_low;
+
+ /* flash_offset must be aligned to the start of a block */
+ if (flash_offset & 0x3ffff)
+ return -1;
+
+ writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
+ writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
+ write_nop(docptr);
+ write_nop(docptr);
+ poll_status(docptr);
+ write_nop(docptr);
+ writew(0x45, docptr + DOC_FLASHSEQUENCE);
+ writew(0xa3, docptr + DOC_FLASHCOMMAND);
+ write_nop(docptr);
+ writew(0x22, docptr + DOC_FLASHCOMMAND);
+ write_nop(docptr);
+
+ /* read 1st 4 oob bytes of first subpage of block */
+ address_sequence(g4_page, 0x0100, docptr); /* index at oob */
+ write_nop(docptr);
+ flash_status = readw(docptr + DOC_FLASHCONTROL);
+ flash_status = readw(docptr + DOC_FLASHCONTROL);
+ if (flash_status & 0x06) /* sequence or protection errors */
+ return -1;
+ writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
+ write_nop(docptr);
+ write_nop(docptr);
+ poll_status(docptr);
+ writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+
+ /*
+ * Here we read the first four oob bytes of the first page of the block.
+ * The IPL on the palmtreo680 requires that this contain a 32 bit magic
+ * number, or the load aborts. We'll ignore it.
+ */
+ discard = readw(docptr + 0x103c); /* hw quirk; 1st read discarded */
+ magic_low = readw(docptr + 0x103c);
+ magic_high = readw(docptr + DOCG4_MYSTERY_REG);
+ writew(0, docptr + DOC_DATAEND);
+ write_nop(docptr);
+ write_nop(docptr);
+
+ /* load contents of block to memory */
+ buf = (uint16_t *)dest_addr;
+ do {
+ int i;
+
+ address_sequence(g4_page, g4_index, docptr);
+ writew(DOCG4_CMD_READ2,
+ docptr + DOC_FLASHCOMMAND);
+ write_nop(docptr);
+ write_nop(docptr);
+ poll_status(docptr);
+ writew(DOC_ECCCONF0_READ_MODE |
+ DOC_ECCCONF0_ECC_ENABLE |
+ DOCG4_BCH_SIZE,
+ docptr + DOC_ECCCONF0);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+ write_nop(docptr);
+
+ /* read the 512 bytes of page data, 2 bytes at a time */
+ discard = readw(docptr + 0x103c);
+ for (i = 0; i < 256; i++)
+ *buf++ = readw(docptr + 0x103c);
+
+ /* read oob, but discard it */
+ for (i = 0; i < 7; i++)
+ discard = readw(docptr + 0x103c);
+ discard = readw(docptr + DOCG4_OOB_6_7);
+ discard = readw(docptr + DOCG4_OOB_6_7);
+
+ writew(0, docptr + DOC_DATAEND);
+ write_nop(docptr);
+ write_nop(docptr);
+
+ if (!(g4_index & 0x100)) {
+ /* not redundant subpage read; check for ecc error */
+ write_nop(docptr);
+ flash_status = readw(docptr + DOC_ECCCONF1);
+ flash_status = readw(docptr + DOC_ECCCONF1);
+ if (flash_status & 0x80) { /* ecc error */
+ g4_index += 0x108; /* read redundant subpage */
+ buf -= 256; /* back up ram ptr */
+ continue;
+ } else /* no ecc error */
+ g4_index += 0x210; /* skip redundant subpage */
+ } else /* redundant page was just read; skip ecc error check */
+ g4_index += 0x108;
+
+ if (g4_index == 0x420) { /* finished with 2k page */
+ g4_index = 0;
+ g4_page += 2; /* odd-numbered 2k pages skipped */
+ }
+
+ } while (g4_page != last_g4_page); /* while still on same block */
+
+ return 0;
+}
return 0;
}
-static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
+int nand_spl_load_image(uint32_t from, unsigned int size, void *buf)
{
int i;
unsigned int page;
page = from / CONFIG_SYS_NAND_PAGE_SIZE;
i = 0;
+ size = roundup(size, CONFIG_SYS_NAND_PAGE_SIZE);
while (i < size / CONFIG_SYS_NAND_PAGE_SIZE) {
if (nfc_read_page(page, buf) < 0)
return -1;
return 0;
}
+#ifndef CONFIG_SPL_FRAMEWORK
/*
* The main entry for NAND booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
* CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
* be aligned to full pages
*/
- if (!nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
+ if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
/* Copy from NAND successful, start U-boot */
uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
uboot();
hang();
}
}
+#endif
-/*
- * Called in case of an exception.
- */
-void hang(void)
-{
- /* Loop forever */
- while (1) ;
-}
+void nand_init(void) {}
+void nand_deselect(void) {}
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/regs-bch.h>
+#include <asm/imx-common/regs-gpmi.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
+#if defined(CONFIG_MX6)
+#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
+#else
+#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
+#endif
#define MXS_NAND_METADATA_SIZE 10
#define MXS_NAND_COMMAND_BUFFER_SIZE 32
tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
<< BCH_FLASHLAYOUT0_ECC0_OFFSET;
- tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
+ tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
+ >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
writel(tmp, &bch_regs->hw_bch_flash0layout0);
tmp = (mtd->writesize + mtd->oobsize)
<< BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
<< BCH_FLASHLAYOUT1_ECCN_OFFSET;
- tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
+ tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
+ >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
writel(tmp, &bch_regs->hw_bch_flash0layout1);
/* Set *all* chip selects to use layout 0 */
/* Enable automatic speed selection */
if_mode |= IF_MODE_EN_AUTO;
+ if (type == PHY_INTERFACE_MODE_RGMII) {
+ if_mode &= ~IF_MODE_EN_AUTO;
+ if_mode &= ~IF_MODE_SETSP_MASK;
+ switch (speed) {
+ case SPEED_1000:
+ if_mode |= IF_MODE_SETSP_1000M;
+ break;
+ case SPEED_100:
+ if_mode |= IF_MODE_SETSP_100M;
+ break;
+ case SPEED_10:
+ if_mode |= IF_MODE_SETSP_10M;
+ default:
+ break;
+ }
+ }
+
debug(" %s, if_mode = %x\n", __func__, if_mode);
debug(" %s, if_status = %x\n", __func__, if_status);
out_be32(®s->if_mode, if_mode);
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
#define MXS_SPI_MAX_TIMEOUT 1000000
#define MXS_SPI_PORT_OFFSET 0x2000
#ifdef CONFIG_USB_DEV_PULLUP_GPIO
/* Turn on the USB connection by enabling the pullup resistor */
- set_GPIO_mode(CONFIG_USB_DEV_PULLUP_GPIO | GPIO_OUT);
+ writel(readl(GPDR(CONFIG_USB_DEV_PULLUP_GPIO))
+ | GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
+ GPDR(CONFIG_USB_DEV_PULLUP_GPIO));
writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), GPSR(CONFIG_USB_DEV_PULLUP_GPIO));
#else
/* Host port 2 transceiver D+ pull up enable */
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
#include "ehci.h"
/* USB_CTRL_1 */
#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
-/* USB pin configuration */
-#define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
- PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
- PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
-
-#ifdef CONFIG_MX51
-/*
- * Configure the MX51 USB H1 IOMUX
- */
-void setup_iomux_usb_h1(void)
-{
- mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG);
-
- mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG);
-}
-
-/*
- * Configure the MX51 USB H2 IOMUX
- */
-void setup_iomux_usb_h2(void)
-{
- mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG);
-
- mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG);
-}
-#endif
-
int mxc_set_usbcontrol(int port, unsigned int flags)
{
unsigned int v;
COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
COBJS-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
+COBJS-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
#endif
#endif
+#ifdef CONFIG_VIDEO_MXS
+#define VIDEO_FB_16BPP_WORD_SWAP
+#endif
+
/*
* Defines for the MB862xx driver
*/
--- /dev/null
+/*
+ * Freescale i.MX23/i.MX28 LCDIF driver
+ *
+ * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <malloc.h>
+#include <video_fb.h>
+
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+
+#include "videomodes.h"
+
+#define PS2KHZ(ps) (1000000000UL / (ps))
+
+static GraphicDevice panel;
+
+/*
+ * DENX M28EVK:
+ * setenv videomode
+ * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
+ * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
+ */
+
+static void mxs_lcd_init(GraphicDevice *panel,
+ struct ctfb_res_modes *mode, int bpp)
+{
+ struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+ uint32_t word_len = 0, bus_width = 0;
+ uint8_t valid_data = 0;
+
+ /* Kick in the LCDIF clock */
+ mxs_set_lcdclk(PS2KHZ(mode->pixclock));
+
+ /* Restart the LCDIF block */
+ mxs_reset_block(®s->hw_lcdif_ctrl_reg);
+
+ switch (bpp) {
+ case 24:
+ word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
+ bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
+ valid_data = 0x7;
+ break;
+ case 18:
+ word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
+ bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
+ valid_data = 0x7;
+ break;
+ case 16:
+ word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
+ bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
+ valid_data = 0xf;
+ break;
+ case 8:
+ word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
+ bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
+ valid_data = 0xf;
+ break;
+ }
+
+ writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
+ LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
+ ®s->hw_lcdif_ctrl);
+
+ writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
+ ®s->hw_lcdif_ctrl1);
+ writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
+ ®s->hw_lcdif_transfer_count);
+
+ writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
+ LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
+ LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
+ mode->vsync_len, ®s->hw_lcdif_vdctrl0);
+ writel(mode->upper_margin + mode->lower_margin +
+ mode->vsync_len + mode->yres,
+ ®s->hw_lcdif_vdctrl1);
+ writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
+ (mode->left_margin + mode->right_margin +
+ mode->hsync_len + mode->xres),
+ ®s->hw_lcdif_vdctrl2);
+ writel(((mode->left_margin + mode->hsync_len) <<
+ LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
+ (mode->upper_margin + mode->vsync_len),
+ ®s->hw_lcdif_vdctrl3);
+ writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
+ ®s->hw_lcdif_vdctrl4);
+
+ writel(panel->frameAdrs, ®s->hw_lcdif_cur_buf);
+ writel(panel->frameAdrs, ®s->hw_lcdif_next_buf);
+
+ /* Flush FIFO first */
+ writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_set);
+
+ /* Sync signals ON */
+ setbits_le32(®s->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
+
+ /* FIFO cleared */
+ writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr);
+
+ /* RUN! */
+ writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
+}
+
+void *video_hw_init(void)
+{
+ int bpp = -1;
+ char *penv;
+ void *fb;
+ struct ctfb_res_modes mode;
+
+ puts("Video: ");
+
+ /* Suck display configuration from "videomode" variable */
+ penv = getenv("videomode");
+ if (!penv) {
+ printf("MXSFB: 'videomode' variable not set!");
+ return NULL;
+ }
+
+ bpp = video_get_params(&mode, penv);
+
+ /* fill in Graphic device struct */
+ sprintf(panel.modeIdent, "%dx%dx%d",
+ mode.xres, mode.yres, bpp);
+
+ panel.winSizeX = mode.xres;
+ panel.winSizeY = mode.yres;
+ panel.plnSizeX = mode.xres;
+ panel.plnSizeY = mode.yres;
+
+ switch (bpp) {
+ case 24:
+ case 18:
+ panel.gdfBytesPP = 4;
+ panel.gdfIndex = GDF_32BIT_X888RGB;
+ break;
+ case 16:
+ panel.gdfBytesPP = 2;
+ panel.gdfIndex = GDF_16BIT_565RGB;
+ break;
+ case 8:
+ panel.gdfBytesPP = 1;
+ panel.gdfIndex = GDF__8BIT_INDEX;
+ break;
+ default:
+ printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
+ return NULL;
+ }
+
+ panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
+
+ /* Allocate framebuffer */
+ fb = malloc(panel.memSize);
+ if (!fb) {
+ printf("MXSFB: Error allocating framebuffer!\n");
+ return NULL;
+ }
+
+ /* Wipe framebuffer */
+ memset(fb, 0, panel.memSize);
+
+ panel.frameAdrs = (u32)fb;
+
+ printf("%s\n", panel.modeIdent);
+
+ /* Start framebuffer */
+ mxs_lcd_init(&panel, &mode, bpp);
+
+ return (void *)&panel;
+}
};
#endif /* CONFIG_ACX517AKN */
+#ifdef CONFIG_ACX544AKN
+
+# define LCD_BPP LCD_COLOR16
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x003008f9
+# define REG_LCCR3 0x04700007 /* 16bpp */
+
+vidinfo_t panel_info = {
+ .vl_col = 320,
+ .vl_row = 320,
+ .vl_width = 320,
+ .vl_height = 320,
+ .vl_clkp = CONFIG_SYS_LOW,
+ .vl_oep = CONFIG_SYS_LOW,
+ .vl_hsp = CONFIG_SYS_LOW,
+ .vl_vsp = CONFIG_SYS_LOW,
+ .vl_dp = CONFIG_SYS_LOW,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 0,
+ .vl_splt = 0,
+ .vl_clor = 1,
+ .vl_tft = 1,
+ .vl_hpw = 0x05,
+ .vl_blw = 0x13,
+ .vl_elw = 0x08,
+ .vl_vpw = 0x02,
+ .vl_bfw = 0x07,
+ .vl_efw = 0x05,
+};
+#endif /* CONFIG_ACX544AKN */
+
/*----------------------------------------------------------------------*/
#ifdef CONFIG_LQ038J7DH53
#endif /* LCD_MONOCHROME */
/*----------------------------------------------------------------------*/
-void lcd_enable (void)
+__weak void lcd_enable(void)
{
}
endif
COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
COBJS-$(CONFIG_S5P) += s5p_wdt.o
+COBJS-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * Copyright (c) 2011-2013 Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/microblaze_intc.h>
+#include <asm/processor.h>
+#include <watchdog.h>
+
+#define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status Mask */
+#define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state Mask */
+#define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 Mask*/
+#define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 Mask */
+
+struct watchdog_regs {
+ u32 twcsr0; /* 0x0 */
+ u32 twcsr1; /* 0x4 */
+ u32 tbr; /* 0x8 */
+};
+
+static struct watchdog_regs *watchdog_base =
+ (struct watchdog_regs *)CONFIG_WATCHDOG_BASEADDR;
+
+void hw_watchdog_reset(void)
+{
+ u32 reg;
+
+ /* Read the current contents of TCSR0 */
+ reg = readl(&watchdog_base->twcsr0);
+
+ /* Clear the watchdog WDS bit */
+ if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK))
+ writel(reg | XWT_CSR0_WDS_MASK, &watchdog_base->twcsr0);
+}
+
+void hw_watchdog_disable(void)
+{
+ u32 reg;
+
+ /* Read the current contents of TCSR0 */
+ reg = readl(&watchdog_base->twcsr0);
+
+ writel(reg & ~XWT_CSR0_EWDT1_MASK, &watchdog_base->twcsr0);
+ writel(~XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
+
+ puts("Watchdog disabled!\n");
+}
+
+static void hw_watchdog_isr(void *arg)
+{
+ hw_watchdog_reset();
+}
+
+int hw_watchdog_init(void)
+{
+ int ret;
+
+ writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK),
+ &watchdog_base->twcsr0);
+ writel(XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
+
+ ret = install_interrupt_handler(CONFIG_WATCHDOG_IRQ,
+ hw_watchdog_isr, NULL);
+ if (ret)
+ return 1;
+
+ return 0;
+}
__u8 *bufptr = mydata->fatbuf;
__u32 startblock = mydata->fatbufnum * FATBUFBLOCKS;
- fatlength *= mydata->sect_size;
startblock += mydata->fat_sect;
if (getsize > fatlength)
return -1;
}
+static inline int fs_write_unsupported(const char *filename, void *buf,
+ int offset, int len)
+{
+ return -1;
+}
+
static inline void fs_close_unsupported(void)
{
}
disk_partition_t *fs_partition);
int (*ls)(const char *dirname);
int (*read)(const char *filename, void *buf, int offset, int len);
+ int (*write)(const char *filename, void *buf, int offset, int len);
void (*close)(void);
};
.close = sandbox_fs_close,
.ls = sandbox_fs_ls,
.read = fs_read_sandbox,
+ .write = fs_write_sandbox,
},
#endif
{
.close = fs_close_unsupported,
.ls = fs_ls_unsupported,
.read = fs_read_unsupported,
+ .write = fs_write_unsupported,
},
};
info->close += gd->reloc_off;
info->ls += gd->reloc_off;
info->read += gd->reloc_off;
+ info->write += gd->reloc_off;
}
relocated = 1;
}
return ret;
}
+int fs_write(const char *filename, ulong addr, int offset, int len)
+{
+ struct fstype_info *info = fs_get_info(fs_type);
+ void *buf;
+ int ret;
+
+ /*
+ * We don't actually know how many bytes are being read, since len==0
+ * means read the whole file.
+ */
+ buf = map_sysmem(addr, len);
+ ret = info->write(filename, buf, offset, len);
+ unmap_sysmem(buf);
+
+ /* If we requested a specific number of bytes, check we got it */
+ if (ret >= 0 && len && ret != len) {
+ printf("** Unable to write file %s **\n", filename);
+ ret = -1;
+ }
+ fs_close();
+
+ return ret;
+}
+
int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
int fstype, int cmdline_base)
{
return 0;
}
+
+int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int fstype, int cmdline_base)
+{
+ unsigned long addr;
+ const char *filename;
+ unsigned long bytes;
+ unsigned long pos;
+ int len;
+ unsigned long time;
+
+ if (argc < 6 || argc > 7)
+ return CMD_RET_USAGE;
+
+ if (fs_set_blk_dev(argv[1], argv[2], fstype))
+ return 1;
+
+ filename = argv[3];
+ addr = simple_strtoul(argv[4], NULL, cmdline_base);
+ bytes = simple_strtoul(argv[5], NULL, cmdline_base);
+ if (argc >= 7)
+ pos = simple_strtoul(argv[6], NULL, cmdline_base);
+ else
+ pos = 0;
+
+ time = get_timer(0);
+ len = fs_write(filename, addr, pos, bytes);
+ time = get_timer(time);
+ if (len <= 0)
+ return 1;
+
+ printf("%d bytes written in %lu ms", len, time);
+ if (time > 0) {
+ puts(" (");
+ print_size(len / time * 1000, "/s");
+ puts(")");
+ }
+ puts("\n");
+
+ return 0;
+}
return size;
}
+long sandbox_fs_write_at(const char *filename, unsigned long pos,
+ void *buffer, unsigned long towrite)
+{
+ ssize_t size;
+ int fd, ret;
+
+ fd = os_open(filename, OS_O_RDWR | OS_O_CREAT);
+ if (fd < 0)
+ return fd;
+ ret = os_lseek(fd, pos, OS_SEEK_SET);
+ if (ret == -1) {
+ os_close(fd);
+ return ret;
+ }
+ size = os_write(fd, buffer, towrite);
+ os_close(fd);
+
+ return size;
+}
+
int sandbox_fs_ls(const char *dirname)
{
struct os_dirent_node *head, *node;
return len_read;
}
+
+int fs_write_sandbox(const char *filename, void *buf, int offset, int len)
+{
+ int len_written;
+
+ len_written = sandbox_fs_write_at(filename, offset, buf, len);
+ if (len_written == -1) {
+ printf("** Unable to write file %s **\n", filename);
+ return -1;
+ }
+
+ return len_written;
+}
#ifndef _ALTERA_H_
#define _ALTERA_H_
-/* Altera Model definitions
- *********************************************************************/
-#define CONFIG_SYS_ACEX1K CONFIG_SYS_FPGA_DEV( 0x1 )
-#define CONFIG_SYS_CYCLON2 CONFIG_SYS_FPGA_DEV( 0x2 )
-#define CONFIG_SYS_STRATIX_II CONFIG_SYS_FPGA_DEV( 0x4 )
-
-#define CONFIG_SYS_ALTERA_ACEX1K (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_ACEX1K)
-#define CONFIG_SYS_ALTERA_CYCLON2 (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_CYCLON2)
-#define CONFIG_SYS_ALTERA_STRATIX_II (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_STRATIX_II)
-/* Add new models here */
-
-/* Altera Interface definitions
- *********************************************************************/
-#define CONFIG_SYS_ALTERA_IF_PS CONFIG_SYS_FPGA_IF( 0x1 ) /* passive serial */
-#define CONFIG_SYS_ALTERA_IF_FPP CONFIG_SYS_FPGA_IF( 0x2 ) /* fast passive parallel */
-/* Add new interfaces here */
-
typedef enum { /* typedef Altera_iface */
min_altera_iface_type, /* insert all new types after this */
passive_serial, /* serial data and external clock */
extern char __bss_start[], __bss_stop[];
extern char __init_begin[], __init_end[];
extern char _sinittext[], _einittext[];
-extern char _end[];
+extern char _end[], _init[];
extern char __per_cpu_load[], __per_cpu_start[], __per_cpu_end[];
extern char __kprobes_text_start[], __kprobes_text_end[];
extern char __entry_text_start[], __entry_text_end[];
char *getenv (const char *);
int getenv_f (const char *name, char *buf, unsigned len);
ulong getenv_ulong(const char *name, int base, ulong default_val);
+
+/**
+ * getenv_hex() - Return an environment variable as a hex value
+ *
+ * Decode an environment as a hex number (it may or may not have a 0x
+ * prefix). If the environment variable cannot be found, or does not start
+ * with hex digits, the default value is returned.
+ *
+ * @varname: Variable to decode
+ * @default_val: Value to return on error
+ */
+ulong getenv_hex(const char *varname, ulong default_val);
+
/*
* Read an environment variable as a boolean
* Return -1 if variable does not exist (default to true)
#elif defined(CONFIG_MPC5xxx)
int prt_mpc5xxx_clks (void);
#endif
-#if defined(CONFIG_MPC512X)
-int prt_mpc512xxx_clks (void);
-#endif
#if defined(CONFIG_MPC8220)
int prt_mpc8220_clks (void);
#endif
static inline void unmap_sysmem(const void *vaddr)
{
}
+
+static inline phys_addr_t map_to_sysmem(void *ptr)
+{
+ return (phys_addr_t)(uintptr_t)ptr;
+}
# endif
#endif /* __ASSEMBLY__ */
* of a function scoped static buffer. It can not be used to create a cache
* line aligned global buffer.
*/
-#define ALLOC_ALIGN_BUFFER(type, name, size, align) \
- char __##name[ROUND(size * sizeof(type), align) + (align - 1)]; \
+#define PAD_COUNT(s, pad) ((s - 1) / pad + 1)
+#define PAD_SIZE(s, pad) (PAD_COUNT(s, pad) * pad)
+#define ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, pad) \
+ char __##name[ROUND(PAD_SIZE(size * sizeof(type), pad), align) \
+ + (align - 1)]; \
\
type *name = (type *) ALIGN((uintptr_t)__##name, align)
+#define ALLOC_ALIGN_BUFFER(type, name, size, align) \
+ ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, 1)
+#define ALLOC_CACHE_ALIGN_BUFFER_PAD(type, name, size, pad) \
+ ALLOC_ALIGN_BUFFER_PAD(type, name, size, ARCH_DMA_MINALIGN, pad)
#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \
ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
*/
#define DEFINE_ALIGN_BUFFER(type, name, size, align) \
static char __##name[roundup(size * sizeof(type), align)] \
- __attribute__((aligned(align))); \
+ __aligned(align); \
\
static type *name = (type *)__##name
#define DEFINE_CACHE_ALIGN_BUFFER(type, name, size) \
#define CONFIG_CMD_FDOS /* Floppy DOS support */
#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
+#define CONFIG_CMD_FUSE /* Device fuse support */
#define CONFIG_CMD_GETTIME /* Get time since boot */
#define CONFIG_CMD_HASH /* calculate hash / digest */
#define CONFIG_CMD_HWFLOW /* RTS/CTS hw flow control */
#define CONFIG_CMD_LOADB /* loadb */
#define CONFIG_CMD_LOADS /* loads */
#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop */
-#define CONFIG_CMD_MEMTEST /* mtest */
#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_NFS /* NFS support */
/* FPGA - Spartan 2 */
/* experiment
-#define CONFIG_FPGA CONFIG_SYS_SPARTAN3
+#define CONFIG_FPGA
#define CONFIG_FPGA_COUNT 1
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_CHECK_CTRLC
* FPGA
*/
#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2
#undef FPGA_DEBUG
#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA 1
#define CONFIG_FPGA_CYCLON2 1
#define CONFIG_FPGA_COUNT 1
""
#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2
#undef FPGA_DEBUG
#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA CONFIG_SYS_XILINX_SPARTAN2
+#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX 1
#define CONFIG_FPGA_SPARTAN2 1
#define CONFIG_FPGA_COUNT 1
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
+#define CONFIG_NAND_FSL_ELBC
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xfffff000
+#define CONFIG_SPL_MAX_SIZE 4096
+#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
+#define CONFIG_SPL_RELOC_STACK 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
+ SPL code*/
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+
/* DDR Setup */
#define CONFIG_DDR_SPD
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
+/* These are used when DDR doesn't use SPD. */
+#define CONFIG_SYS_SDRAM_SIZE 2048
+#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
+#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
+#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
+#define CONFIG_SYS_DDR_TIMING_3 0x00010000
+#define CONFIG_SYS_DDR_TIMING_0 0x40110104
+#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
+#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
+#define CONFIG_SYS_DDR_MODE_1 0x00441221
+#define CONFIG_SYS_DDR_MODE_2 0x00000000
+#define CONFIG_SYS_DDR_INTERVAL 0x0a280100
+#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
+#define CONFIG_SYS_DDR_CONTROL 0xc7000008
+#define CONFIG_SYS_DDR_CONTROL_2 0x24401041
+#define CONFIG_SYS_DDR_TIMING_4 0x00220001
+#define CONFIG_SYS_DDR_TIMING_5 0x02401400
+#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
+
+
/*
* Memory map
*
* Localbus non-cacheable
* 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
* 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
+ * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
* 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
/*
* Local Bus Definitions
*/
-#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
+#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
+#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
#else
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#endif
#define CONFIG_FLASH_BR_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
+ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
+#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
+#endif
-#define CONFIG_SYS_BR1_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
-
-#define CONFIG_SYS_FLASH_BANKS_LIST \
- {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 1024
+#ifndef CONFIG_SYS_MONITOR_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+#endif
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
+/* Nand Flash */
+#if defined(CONFIG_NAND_FSL_ELBC)
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
+#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
+ | OR_FCM_PGS /* Large Page*/ \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR)
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#else
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+
+#endif /* CONFIG_NAND_FSL_ELBC */
+
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define PIXIS_LBMAP_SWITCH 7
#define PIXIS_LBMAP_MASK 0xF0
#define PIXIS_LBMAP_ALTBANK 0x20
+#define PIXIS_SPD 0x07
+#define PIXIS_SPD_SYSCLK_MASK 0x07
#define PIXIS_ELBC_SPI_MASK 0xc0
#define PIXIS_SPI 0x80
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*
* Environment
*/
-#ifdef CONFIG_SYS_RAMBOOT
#ifdef CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_NAND_U_BOOT)
+#elif defined(CONFIG_NAND)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
-#else
+#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
-#endif
#else
#define CONFIG_ENV_IS_IN_FLASH
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
/*
- * Copyright 2012 Stefan Roese <sr@denx.de>
+ * Copyright 2012-2013 Stefan Roese <sr@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_MII
#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_MAY_FAIL
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_NET_RETRY_COUNT 3
+#define CONFIG_CMD_LINK_LOCAL
+#define CONFIG_NETCONSOLE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_CMD_PING
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS /* needed for UBI */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=fc000000.flash"
+#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \
+ "256k(env)," \
+ "128k(hwinfo)," \
+ "1M(nvramsim)," \
+ "128k(dtb)," \
+ "5M(kernel)," \
+ "128k(sysinfo)," \
+ "7552k(root)," \
+ "4M(app)," \
+ "13568k(data)"
+#define CONFIG_LZO /* needed for UBI */
+#define CONFIG_RBTREE /* needed for UBI */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_FIT
/*
* IPB Bus clocking configuration.
*/
#define CONFIG_SYS_FLASH_BASE 0xfc000000
#define CONFIG_SYS_FLASH_SIZE 0x02000000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_FLASH_VERIFY
/*
* Environment settings
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
/*
* Memory map
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
- CONFIG_SYS_GBL_DATA_SIZE)
+ GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-#define CONFIG_SYS_MALLOC_LEN (1 << 20)
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+#define CONFIG_SYS_MALLOC_LEN (4 << 20)
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
/*
*/
#ifdef CONFIG_A4M2K
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x0005C805
+#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805
#else
/* for failsave-level 0 - full failsave */
#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
/* for failsave-level 1 - only digiboard ok */
-#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C005
+#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065
/* for failsave-level 2 - all ok */
-#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C005
+#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065
#endif
#define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7
/*
* Configuration matrix
- * MSB LSB
+ * MSB LSB
* failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave )
- * failsave 1 0x1005C005 00010000000001011100000000000101 ( digib.-ver ok )
- * failsave 2 0x1005C005 00010000000001011100000000000101 ( all ok )
+ * failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok )
+ * failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok )
* || ||| || | ||| | | | |
* || ||| || | ||| | | | | bit rev name
* ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
* Environment Configuration
*/
-#define CONFIG_BOOTDELAY 0 /* -1 disables auto-boot */
+#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS
#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SYS_AUTOLOAD "n"
+
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
"echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
#undef CONFIG_BOOTARGS
-#define CONFIG_SYS_OS_BASE 0xfc080000
-#define CONFIG_SYS_FDT_BASE 0xfc060000
+#define CONFIG_SYS_OS_BASE 0xfc200000
+#define CONFIG_SYS_FDT_BASE 0xfc1e0000
#define CONFIG_EXTRA_ENV_SETTINGS \
- "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
"netdev=eth0\0" \
"verify=no\0" \
"loadaddr=200000\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
- "mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0" \
+ "mtdargs=setenv bootargs root=/dev/mtdblock7 " \
+ "rootfstype=squashfs,jffs2\0" \
+ "addhost=setenv bootargs ${bootargs} " \
+ "hostname=${hostname}\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} " \
"console=${consoledev},${baudrate}\0" \
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr} - ${fdtaddr}\0" \
- "flash_mtd=run mtdargs addip addtty;" \
- "bootm ${kernel_addr} - ${fdtaddr}\0" \
- "flash_self=run ramargs addip addtty;" \
+ "flash_nfs=run nfsargs addip addtty addhost;" \
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
+ "flash_mtd=run mtdargs addip addtty addhost;" \
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
+ "flash_self=run ramargs addip addtty addhost;" \
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
"tftp ${fdt_addr_r} ${fdtfile};" \
- "run nfsargs addip addtty;" \
+ "run nfsargs addip addtty addhost;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \
"/u-boot-img.bin\0" \
- "update=protect off fc000000 fc03ffff; " \
- "era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0" \
+ "update=protect off fc000000 fc07ffff; " \
+ "era fc000000 fc07ffff;" \
+ "cp.b ${loadaddr} fc000000 ${filesize}\0" \
"upd=run load;run update\0" \
- "bootdelay=3\0" \
- "bootcmd=run net_nfs\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_mtd"
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0x7F
+/*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_FSL_IIM
+
/*
* EEPROM configuration for Atmel AT24C01:
* 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
+#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
/*
* Miscellaneous configurable options
#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE /* include version env variable */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
-#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+#define CONFIG_REGEX /* Enable regular expression support */
/*
* BOOTP options
*/
/*
* IIM - IC Identification Module
*/
-#undef CONFIG_IIM
+#undef CONFIG_FSL_IIM
/*
* EEPROM configuration for Atmel AT24C32A-10TQ-2.7:
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
"bank_intlv=cs0_cs1;" \
+ "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
/* SOC type must be included before imx-regs.h */
#define CONFIG_MX53
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
/* SPI FLASH - not used for environment */
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_CS (IOMUX_TO_GPIO(MX53_PIN_CSI0_D11) \
- << 8) | 0
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 25000000
/*
- * (C) Copyright 2007-2010
+ * (C) Copyright 2007-2013
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
-#ifndef CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_LCD4_LWMON5
+#define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */
+#define CONFIG_HOSTNAME lcd4_lwmon5
+#else
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+#define CONFIG_HOSTNAME lwmon5
#endif
#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
* actual resources get mapped (not physical addresses)
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
-#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
+#define CONFIG_SYS_MONITOR_LEN 0x80000
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
+#ifndef CONFIG_LCD4_LWMON5
#define CONFIG_SYS_USB2D0_BASE 0xe0000100
#define CONFIG_SYS_USB_DEVICE 0xe0000000
#define CONFIG_SYS_USB_HOST 0xe0000400
+#endif
/*
* Initial RAM & stack pointer
* content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
* for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
*/
+#ifndef CONFIG_LCD4_LWMON5
#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#endif
/* unused GPT0 COMP reg */
#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
#define CONFIG_SYS_OCM_SIZE (16 << 10)
#define CONFIG_SYS_MBYTES_SDRAM 256
#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
+#ifndef CONFIG_LCD4_LWMON5
#define CONFIG_DDR_ECC /* enable ECC */
+#endif
+#ifndef CONFIG_LCD4_LWMON5
/* POST support */
#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
CONFIG_SYS_POST_CPU | \
#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+#endif
/*
* I2C
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
+#ifndef CONFIG_LCD4_LWMON5
/*
* USB/EHCI
*/
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
+#endif
/*
* BOOTP options
#define CONFIG_CMD_BMP
#endif
+#ifndef CONFIG_LCD4_LWMON5
#ifdef CONFIG_440EPX
#define CONFIG_CMD_USB
#endif
+#endif
/*
* Miscellaneous configurable options
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
+
+#ifndef CONFIG_LCD4_LWMON5
#ifndef DEBUG
#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
#endif
#define CONFIG_WD_PERIOD 40000 /* in usec */
#define CONFIG_WD_MAX_RATE 66600 /* in ticks */
+#endif
/*
* For booting Linux, the board info and command line data
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
+
+/*
+ * SPL related defines
+ */
+#ifdef CONFIG_LCD4_LWMON5
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NOR_SUPPORT
+#define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */
+#define CONFIG_SYS_SPL_MAX_LEN (64 << 10)
+#define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */
+#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/ppc4xx"
+#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/ppc4xx/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+/* Place BSS for SPL near end of SDRAM */
+#define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20)
+#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
+
+#define CONFIG_SPL_OS_BOOT
+/* Place patched DT blob (fdt) at this address */
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
+
+#define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin"
+
+/* Settings for real U-Boot to be loaded from NOR flash */
+#define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_UBOOT_START 0x01002100
+
+#define CONFIG_SYS_OS_BASE 0xf8000000
+#define CONFIG_SYS_FDT_BASE 0xf87c0000
+#endif
+
#endif /* __CONFIG_H */
/*
* SoC configurations
*/
-#define CONFIG_MX28 /* i.MX28 SoC */
-#define CONFIG_MXS_GPIO /* GPIO control */
-#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+#define CONFIG_MX28 /* i.MX28 SoC */
+#define CONFIG_MXS_GPIO /* GPIO control */
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
/*
* Define M28EVK machine type by hand until it lands in mach-types
*/
-#define MACH_TYPE_M28EVK 3613
+#define MACH_TYPE_M28EVK 3613
-#define CONFIG_MACH_TYPE MACH_TYPE_M28EVK
+#define CONFIG_MACH_TYPE MACH_TYPE_M28EVK
#include <asm/arch/regs-base.h>
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_MISC_INIT
/*
* SPL
*/
-#define CONFIG_SPL
-#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
-#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL
+#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
+#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
/*
* U-Boot Commands
*/
#include <config_cmd_default.h>
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DOS_PARTITION
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_GPIO
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SETEXPR
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_USB
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_USB
+#define CONFIG_VIDEO
+
+#define CONFIG_REGEX /* Enable regular expression support */
/*
* Memory configurations
*/
-#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x40000000 /* Base address */
-#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
-#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
-#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
-#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x40000000 /* Base address */
+#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
+#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
+#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
+#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Point initial SP in SRAM so SPL can use it too. */
#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
* binary. In case there was more of this mess, 0x100 bytes are skipped.
*/
-#define CONFIG_SYS_TEXT_BASE 0x40000100
+#define CONFIG_SYS_TEXT_BASE 0x40000100
/*
* U-Boot general configurations
*/
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "=> "
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
-#define CONFIG_SYS_PBSIZE \
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Print buffer size */
-#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
-#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
-#define CONFIG_AUTO_COMPLETE /* Command auto complete */
-#define CONFIG_CMDLINE_EDITING /* Command history etc */
-#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
/*
* Serial Driver
*/
-#define CONFIG_PL011_SERIAL
-#define CONFIG_PL011_CLOCK 24000000
-#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
-#define CONFIG_CONS_INDEX 0
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 24000000
+#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
/*
* MMC Driver
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MXS_MMC
+#define CONFIG_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXS_MMC
#endif
/*
/*
* NAND
*/
-#define CONFIG_ENV_SIZE (16 * 1024)
+#define CONFIG_ENV_SIZE (16 * 1024)
#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_MXS
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x60000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x60000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
/* Environment is in NAND */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_RANGE (512 * 1024)
-#define CONFIG_ENV_OFFSET 0x300000
-#define CONFIG_ENV_OFFSET_REDUND \
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_RANGE (512 * 1024)
+#define CONFIG_ENV_OFFSET 0x300000
+#define CONFIG_ENV_OFFSET_REDUND \
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define MTDIDS_DEFAULT "nand0=gpmi-nand"
-#define MTDPARTS_DEFAULT \
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=gpmi-nand"
+#define MTDPARTS_DEFAULT \
"mtdparts=gpmi-nand:" \
"3m(bootloader)ro," \
"512k(environment)," \
"8m(ramdisk)," \
"-(filesystem)"
#else
-#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_NOWHERE
#endif
/*
* Ethernet on SOC (FEC)
*/
#ifdef CONFIG_CMD_NET
-#define CONFIG_ETHPRIME "FEC0"
-#define CONFIG_FEC_MXC
-#define CONFIG_MII
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_ETHPRIME "FEC0"
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define CONFIG_FEC_XCV_TYPE RMII
#endif
/*
* I2C
*/
#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MXS
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_I2C_MXS
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
#endif
/*
* EEPROM
*/
#ifdef CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#endif
/*
*/
#ifdef CONFIG_CMD_DATE
/* Use the internal RTC in the MXS chip */
-#define CONFIG_RTC_INTERNAL
+#define CONFIG_RTC_INTERNAL
#ifdef CONFIG_RTC_INTERNAL
-#define CONFIG_RTC_MXS
+#define CONFIG_RTC_MXS
#else
-#define CONFIG_RTC_M41T62
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 2000
+#define CONFIG_RTC_M41T62
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
#endif
#endif
* USB
*/
#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MXS
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MXS
#define CONFIG_EHCI_MXS_PORT0
#define CONFIG_EHCI_MXS_PORT1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
#endif
/*
* SPI
*/
#ifdef CONFIG_CMD_SPI
-#define CONFIG_HARD_SPI
-#define CONFIG_MXS_SPI
-#define CONFIG_SPI_HALF_DUPLEX
-#define CONFIG_DEFAULT_SPI_BUS 2
-#define CONFIG_DEFAULT_SPI_CS 0
-#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
+#define CONFIG_HARD_SPI
+#define CONFIG_MXS_SPI
+#define CONFIG_SPI_HALF_DUPLEX
+#define CONFIG_DEFAULT_SPI_BUS 2
+#define CONFIG_DEFAULT_SPI_CS 0
+#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
/* SPI FLASH */
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SF_DEFAULT_BUS 2
-#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 40000000
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SF_DEFAULT_BUS 2
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED 40000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_ENV_SPI_BUS 2
-#define CONFIG_ENV_SPI_CS 0
-#define CONFIG_ENV_SPI_MAX_HZ 40000000
-#define CONFIG_ENV_SPI_MODE SPI_MODE_0
+#define CONFIG_ENV_SPI_BUS 2
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 40000000
+#define CONFIG_ENV_SPI_MODE SPI_MODE_0
+#endif
#endif
+
+/*
+ * LCD
+ */
+#ifdef CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
#endif
/*
* Boot Linux
*/
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 "
-#define CONFIG_BOOTCOMMAND "run bootcmd_net"
-#define CONFIG_LOADADDR 0x42000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 "
+#define CONFIG_BOOTCOMMAND "run bootcmd_net"
+#define CONFIG_LOADADDR 0x42000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_OF_LIBFDT
/*
* Extra Environments
*/
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CONFIG_EXTRA_ENV_SETTINGS \
"update_nand_full_filename=u-boot.nand\0" \
"update_nand_firmware_filename=u-boot.sb\0" \
"update_sd_firmware_filename=u-boot.sd\0" \
--- /dev/null
+/*
+ * DENX M53 configuration
+ * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __M53EVK_CONFIG_H__
+#define __M53EVK_CONFIG_H__
+
+#define CONFIG_MX53
+#define CONFIG_MXC_GPIO
+#define CONFIG_SYS_HZ 1000
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SATA
+#define CONFIG_CMD_USB
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+#define PHYS_SDRAM_2 CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
+#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START 0x70000000
+#define CONFIG_SYS_MEMTEST_END 0xaff00000
+
+#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_TEXT_BASE 0x71000000
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART2_BASE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 1
+#endif
+
+/*
+ * NAND
+ */
+#define CONFIG_ENV_SIZE (16 * 1024)
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
+#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
+/* Environment is in NAND */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_RANGE (512 * 1024)
+#define CONFIG_ENV_OFFSET 0x100000
+#define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=mxc-nand"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=mxc-nand:" \
+ "1m(bootloader)ro," \
+ "512k(environment)," \
+ "512k(redundant-environment)," \
+ "4m(kernel)," \
+ "128k(fdt)," \
+ "8m(ramdisk)," \
+ "-(filesystem)"
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR 0x0
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#endif
+
+/*
+ * I2C
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif
+
+/*
+ * RTC
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_M41T62
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX5
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MXC_USB_PORT 1
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#endif
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_DWC_AHSATA_PORT_ID 0
+#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "m53evk/uImage"
+#define CONFIG_BOOTARGS "console=ttymxc1,115200"
+#define CONFIG_LOADADDR 0x70800000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_OF_LIBFDT
+
+/*
+ * NAND SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_TEXT_BASE 0x70008000
+#define CONFIG_SPL_PAD_TO 0x8000
+#define CONFIG_SPL_STACK 0x70004000
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+
+#endif /* __M53EVK_CONFIG_H__ */
/*
* IIM - IC Identification Module
*/
-#undef CONFIG_IIM
+#undef CONFIG_FSL_IIM
/*
* EEPROM configuration
# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
#endif
+/* watchdog */
+#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
+# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
+# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
+# define CONFIG_HW_WATCHDOG
+# define CONFIG_XILINX_TB_WATCHDOG
+#endif
+
/*
* memory layout - Example
* CONFIG_SYS_TEXT_BASE = 0x1200_0000; defined in config.mk
"nor0=flash-0\0"\
"mtdparts=mtdparts=flash-0:"\
"256k(u-boot),256k(env),3m(kernel),"\
- "1m(romfs),1m(cramfs),-(jffs2)\0"
+ "1m(romfs),1m(cramfs),-(jffs2)\0"\
+ "nc=setenv stdout nc;"\
+ "setenv stdin nc\0" \
+ "serial=setenv stdout serial;"\
+ "setenv stdin serial\0"
#define CONFIG_CMDLINE_EDITING
+#define CONFIG_NETCONSOLE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
/*
* IIM - IC Identification Module
*/
-#undef CONFIG_IIM
+#undef CONFIG_FSL_IIM
/*
* EEPROM configuration
#define CONFIG_CMD_USB
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
/* Memory configurations */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
/* Environment is in NAND */
+#ifdef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_RANGE (512 * 1024)
-#ifndef CONFIG_ENV_OFFSET
#define CONFIG_ENV_OFFSET 0x300000
-#endif
#define CONFIG_ENV_OFFSET_REDUND \
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+#endif
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 2048
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0x87dc0000
#define CONFIG_SYS_TEXT_BASE 0x87e00000
/*
* Hardware drivers
*/
+#define CONFIG_FSL_IIM
+#define CONFIG_CMD_FUSE
+
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_MXC_GPIO
#define CONFIG_ETHPRIME "FEC0"
-#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
+#define CONFIG_LOADADDR 0x92000000 /* loadaddr env var */
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"uimage=uImage\0" \
+ "fdt_file=imx51-babbage.dtb\0" \
+ "fdt_addr=0x91000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
"mmcdev=0\0" \
"mmcpart=2\0" \
- "mmcroot=/dev/mmcblk0p3 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
+ "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
+ "root=${mmcroot}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
- "bootm\0" \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0" \
"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
- "dhcp ${uimage}; bootm\0" \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${uimage}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo ERROR: Cannot load the DT; " \
+ "exit; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#include <config_cmd_default.h>
#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_SETEXPR
#define CONFIG_BOOTDELAY 3
#define CONFIG_SMC911X_16_BIT
#define CONFIG_SMC911X_BASE CS1_BASE_ADDR
-#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
+#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
#define CONFIG_SYS_TEXT_BASE 0x77800000
+#define CONFIG_DEFAULT_FDT_FILE "imx53-ard.dtb"
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"uimage=uImage\0" \
- "mmcdev=0\0" \
- "mmcpart=2\0" \
- "mmcroot=/dev/mmcblk0p3 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_addr=0x71000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \
+ "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+ "update_sd_firmware_filename=u-boot.imx\0" \
+ "update_sd_firmware=" \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "if mmc dev ${mmcdev}; then " \
+ "if ${get_cmd} ${update_sd_firmware_filename}; then " \
+ "setexpr fw_sz ${filesize} / 0x200; " \
+ "setexpr fw_sz ${fw_sz} + 1; " \
+ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+ "fi; " \
+ "fi\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
- "bootm\0" \
- "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
"run netargs; " \
- "dhcp ${uimage}; bootm\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
"else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
+ "setenv get_cmd tftp; " \
"fi; " \
- "else run netboot; fi"
+ "${get_cmd} ${uimage}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
#define CONFIG_ARP_TIMEOUT 200UL
/* Miscellaneous configurable options */
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_OF_LIBFDT
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
#define CONFIG_OF_LIBFDT
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#ifndef __MX6_COMMON_H
#define __MX6_COMMON_H
+#define CONFIG_ARM_ERRATA_742230
#define CONFIG_ARM_ERRATA_743622
#define CONFIG_ARM_ERRATA_751472
#define CONFIG_CMD_BMODE
#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_SETEXPR
#undef CONFIG_CMD_IMLS
#define CONFIG_BOOTDELAY 1
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "update_sd_firmware=" \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "if mmc dev ${mmcdev}; then " \
+ "if ${get_cmd} ${update_sd_firmware_filename}; then " \
+ "setexpr fw_sz ${filesize} / 0x200; " \
+ "setexpr fw_sz ${fw_sz} + 1; " \
+ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+ "fi; " \
+ "fi\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadbootscript=" \
#define CONFIG_MISC_INIT_R
#define CONFIG_MXC_GPIO
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
--- /dev/null
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SL EVK board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <asm/sizes.h>
+
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MACH_TYPE_MX6SLEVK 4307
+#define CONFIG_MACH_TYPE MACH_TYPE_MX6SLEVK
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x80800000
+#define CONFIG_SYS_TEXT_BASE 0x87800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "uimage=uImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=imx6sl-evk.dtb\0" \
+ "fdt_addr=0x81000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev=0\0" \
+ "mmcpart=2\0" \
+ "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${uimage}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_512M)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE SZ_1G
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET (6 * SZ_64K)
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif /* __CONFIG_H */
#define CONFIG_MISC_INIT_R
#define CONFIG_MXC_GPIO
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
#endif /* (CONFIG_CMD_NET) */
#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
#define CONFIG_ENV_OFFSET 0xE0000
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_CMD_SAVEENV
/* Enhance our eMMC support / experience. */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0x7F
+/*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_FSL_IIM
+
/*
* EEPROM configuration
*/
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
+#undef CONFIG_CMD_FUSE
+
#ifdef CONFIG_VIDEO
#define CONFIG_CMD_BMP
#endif
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_DRAM_SIZE (128 << 20)
-
/* Number of bits in a C 'long' on this architecture */
#define CONFIG_SANDBOX_BITS_PER_LONG 64
#define CONFIG_OF_CONTROL
+#define CONFIG_OF_HOSTFILE
#define CONFIG_OF_LIBFDT
#define CONFIG_LMB
+#define CONFIG_FIT
+#define CONFIG_CMD_FDT
#define CONFIG_FS_FAT
#define CONFIG_FS_EXT4
#define CONFIG_SYS_MEMTEST_START 0x00100000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1000)
#define CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FDT_LOAD_ADDR 0x1000000
/* Size of our emulated memory */
+#define CONFIG_SYS_SDRAM_BASE 0
#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
+#define CONFIG_SYS_TEXT_BASE 0
+#define CONFIG_SYS_MONITOR_BASE 0
+#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
--- /dev/null
+/*
+ * Copyright (C) 2013 Stefan Roese <sr@denx.de>
+ *
+ * Configuration settings for the ProjectionDesign / Barco
+ * Titanium board.
+ *
+ * Based on mx6qsabrelite.h which is:
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_MX6
+#define CONFIG_MX6Q
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MACH_TYPE_TITANIUM 3769
+#define CONFIG_MACH_TYPE MACH_TYPE_TITANIUM
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_USDHC_NUM 1
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 4
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_MXC_USB_PORT 1
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x12000000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (500 << 20))
+
+#define CONFIG_HOSTNAME titanium
+#define CONFIG_UBI_PART ubi
+#define CONFIG_UBIFS_VOLUME rootfs0
+
+#define MTDIDS_DEFAULT "nand0=gpmi-nand"
+#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:16M(uboot),512k(env1)," \
+ "512k(env2),-(ubi)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "kernel_fs=/boot/uImage\0" \
+ "kernel_addr=11000000\0" \
+ "dtb=" __stringify(CONFIG_HOSTNAME) "/" \
+ __stringify(CONFIG_HOSTNAME) ".dtb\0" \
+ "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \
+ "dtb_addr=12800000\0" \
+ "script=boot.scr\0" \
+ "uimage=uImage\0" \
+ "console=ttymxc0\0" \
+ "baudrate=115200\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "uimage=uImage\0" \
+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
+ " ${script}\0" \
+ "bootscript=echo Running bootscript from mmc ...; source\0" \
+ "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot} rootwait rw\0" \
+ "bootmmc=run mmcargs; fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
+ " ${uimage}; bootm\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addcon=setenv bootargs ${bootargs} console=ttymxc0," \
+ "${baudrate}\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "rootpath=/opt/eldk-5.3/armv7a/rootfs-minimal-mtdutils\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \
+ "part=" __stringify(CONFIG_UBI_PART) "\0" \
+ "boot_vol=0\0" \
+ "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
+ "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
+ "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
+ " ${filesize}\0" \
+ "upd_ubifs=run load_ubifs update_ubifs\0" \
+ "init_ubi=nand erase.part ubi;ubi part ${part};" \
+ "ubi create ${vol} c800000\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
+ " addcon addmtd;" \
+ "bootm ${kernel_addr} - ${dtb_addr}\0" \
+ "ubifsargs=set bootargs ubi.mtd=ubi " \
+ "root=ubi:rootfs${boot_vol} rootfstype=ubifs\0" \
+ "ubifs_mount=ubi part ubi;ubifsmount ubi:rootfs${boot_vol}\0" \
+ "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
+ "ubifsload ${dtb_addr} ${dtb_fs};\0" \
+ "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
+ "addmtd;bootm ${kernel_addr} - ${dtb_addr}\0" \
+ "load_kernel=tftp ${kernel_addr} ${kernel}\0" \
+ "load_dtb=tftp ${dtb_addr} ${dtb}\0" \
+ "net_nfs=run load_dtb load_kernel; " \
+ "run nfsargs addip addcon addmtd;" \
+ "bootm ${kernel_addr} - ${dtb_addr}\0" \
+ "delenv=env default -a -f; saveenv; reset\0"
+
+#define CONFIG_BOOTCOMMAND "run nand_ubifs"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "Titanium > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
+
+#define CONFIG_SYS_CBSIZE 256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE (512 << 20)
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+/* Enable NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_TIME
+
+#ifdef CONFIG_CMD_NAND
+
+/* NAND stuff */
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+
+/* Environment in NAND */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (16 << 20)
+#define CONFIG_ENV_SECT_SIZE (128 << 10)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 << 10))
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#else /* CONFIG_CMD_NAND */
+
+/* Environment in MMC */
+#define CONFIG_ENV_SIZE (8 << 10)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif /* CONFIG_CMD_NAND */
+
+/* UBI/UBIFS config options */
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif /* __CONFIG_H */
#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 2048
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_TEXT_BASE 0x810c0000
#define CONFIG_SYS_TEXT_BASE 0x81200000
#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+
#define CONFIG_BOOTDELAY 5
#define CONFIG_SYS_MEMTEST_START 0x10000000
/* MMC Configuration */
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_MMC
"fdt_addr=0x11000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
- "mmcdev=0\0" \
- "mmcpart=2\0" \
+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \
"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+ "update_sd_firmware_filename=u-boot.imx\0" \
+ "update_sd_firmware=" \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "if mmc dev ${mmcdev}; then " \
+ "if ${get_cmd} ${update_sd_firmware_filename}; then " \
+ "setexpr fw_sz ${filesize} / 0x200; " \
+ "setexpr fw_sz ${fw_sz} + 1; " \
+ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+ "fi; " \
+ "fi\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadbootscript=" \
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
#endif
+/* Enable the PL to be downloaded */
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_ZYNQPL
+#define CONFIG_CMD_FPGA
+
#define CONFIG_BOOTP_SERVERIP
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_MAX_FPGA_DEVICES 5
#endif
-/* CONFIG_FPGA bit assignments */
-#define CONFIG_SYS_FPGA_MAN(x) (x)
-#define CONFIG_SYS_FPGA_DEV(x) ((x) << 8 )
-#define CONFIG_SYS_FPGA_IF(x) ((x) << 16 )
-
-/* FPGA Manufacturer bits in CONFIG_FPGA */
-#define CONFIG_SYS_FPGA_XILINX CONFIG_SYS_FPGA_MAN( 0x1 )
-#define CONFIG_SYS_FPGA_ALTERA CONFIG_SYS_FPGA_MAN( 0x2 )
-
-
/* fpga_xxxx function return value definitions */
#define FPGA_SUCCESS 0
#define FPGA_FAIL -1
extern int fpga_add(fpga_type devtype, void *desc);
extern int fpga_count(void);
extern int fpga_load(int devnum, const void *buf, size_t bsize);
+extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size);
extern int fpga_dump(int devnum, const void *buf, size_t bsize);
extern int fpga_info(int devnum);
+extern const fpga_desc *const fpga_validate(int devnum, const void *buf,
+ size_t bsize, char *fn);
#endif /* _FPGA_H_ */
int fstype, int cmdline_base);
int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
int fstype);
+int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int fstype, int cmdline_base);
#endif /* _FS_H */
/*
- * (C) Copyright 2009
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ * (C) Copyright 2009-2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on the mpc512x iim code:
+ * Copyright 2008 Silicon Turnkey Express, Inc.
+ * Martha Marx <mmarx@silicontkx.com>
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
+#ifndef _FUSE_H_
+#define _FUSE_H_
-void mx25_uart1_init_pins(void);
-#if defined CONFIG_FEC_MXC
-extern void mx25_fec_init_pins(void);
-#endif
+/*
+ * Read/Sense/Program/Override interface:
+ * bank: Fuse bank
+ * word: Fuse word within the bank
+ * val: Value to read/write
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int fuse_read(u32 bank, u32 word, u32 *val);
+int fuse_sense(u32 bank, u32 word, u32 *val);
+int fuse_prog(u32 bank, u32 word, u32 val);
+int fuse_override(u32 bank, u32 word, u32 val);
-#endif
+#endif /* _FUSE_H_ */
char *desc; /* description string */
} Lattice_desc; /* end, typedef Altera_desc */
-/* Lattice Model Type */
-#define CONFIG_SYS_XP2 CONFIG_SYS_FPGA_DEV(0x1)
-
/* Board specific implementation specific function types */
typedef void (*Lattice_jtag_init)(void);
typedef void (*Lattice_jtag_set_tdi)(int v);
--- /dev/null
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Based on bitrev from the Linux kernel, by Akinobu Mita
+ */
+
+#ifndef _LINUX_BITREV_H
+#define _LINUX_BITREV_H
+
+#include <linux/types.h>
+
+extern u8 const byte_rev_table[256];
+
+static inline u8 bitrev8(u8 byte)
+{
+ return byte_rev_table[byte];
+}
+
+u16 bitrev16(u16 in);
+u32 bitrev32(u32 in);
+
+#endif /* _LINUX_BITREV_H */
--- /dev/null
+/*
+ * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ */
+
+#ifndef __DOCG4_H__
+#define __DOCG4_H__
+
+#include <common.h>
+#include <linux/mtd/nand.h>
+
+extern int docg4_nand_init(struct mtd_info *mtd,
+ struct nand_chip *nand, int devnum);
+
+/* SPL-related definitions */
+#define DOCG4_IPL_LOAD_BLOCK_COUNT 2 /* number of blocks that IPL loads */
+#define DOCG4_BLOCK_CAPACITY_SPL 0x10000 /* reliable mode; redundant pages */
+
+#define DOC_IOSPACE_DATA 0x0800
+
+/* register offsets */
+#define DOC_CHIPID 0x1000
+#define DOC_DEVICESELECT 0x100a
+#define DOC_ASICMODE 0x100c
+#define DOC_DATAEND 0x101e
+#define DOC_NOP 0x103e
+
+#define DOC_FLASHSEQUENCE 0x1032
+#define DOC_FLASHCOMMAND 0x1034
+#define DOC_FLASHADDRESS 0x1036
+#define DOC_FLASHCONTROL 0x1038
+#define DOC_ECCCONF0 0x1040
+#define DOC_ECCCONF1 0x1042
+#define DOC_HAMMINGPARITY 0x1046
+#define DOC_BCH_SYNDROM(idx) (0x1048 + idx)
+
+#define DOC_ASICMODECONFIRM 0x1072
+#define DOC_CHIPID_INV 0x1074
+#define DOC_POWERMODE 0x107c
+
+#define DOCG4_MYSTERY_REG 0x1050
+
+/* apparently used only to write oob bytes 6 and 7 */
+#define DOCG4_OOB_6_7 0x1052
+
+/* DOC_FLASHSEQUENCE register commands */
+#define DOC_SEQ_RESET 0x00
+#define DOCG4_SEQ_PAGE_READ 0x03
+#define DOCG4_SEQ_FLUSH 0x29
+#define DOCG4_SEQ_PAGEWRITE 0x16
+#define DOCG4_SEQ_PAGEPROG 0x1e
+#define DOCG4_SEQ_BLOCKERASE 0x24
+
+/* DOC_FLASHCOMMAND register commands */
+#define DOCG4_CMD_PAGE_READ 0x00
+#define DOC_CMD_ERASECYCLE2 0xd0
+#define DOCG4_CMD_FLUSH 0x70
+#define DOCG4_CMD_READ2 0x30
+#define DOC_CMD_PROG_BLOCK_ADDR 0x60
+#define DOCG4_CMD_PAGEWRITE 0x80
+#define DOC_CMD_PROG_CYCLE2 0x10
+#define DOC_CMD_RESET 0xff
+
+/* DOC_POWERMODE register bits */
+#define DOC_POWERDOWN_READY 0x80
+
+/* DOC_FLASHCONTROL register bits */
+#define DOC_CTRL_CE 0x10
+#define DOC_CTRL_UNKNOWN 0x40
+#define DOC_CTRL_FLASHREADY 0x01
+
+/* DOC_ECCCONF0 register bits */
+#define DOC_ECCCONF0_READ_MODE 0x8000
+#define DOC_ECCCONF0_UNKNOWN 0x2000
+#define DOC_ECCCONF0_ECC_ENABLE 0x1000
+#define DOC_ECCCONF0_DATA_BYTES_MASK 0x07ff
+
+/* DOC_ECCCONF1 register bits */
+#define DOC_ECCCONF1_BCH_SYNDROM_ERR 0x80
+#define DOC_ECCCONF1_ECC_ENABLE 0x07
+#define DOC_ECCCONF1_PAGE_IS_WRITTEN 0x20
+
+/* DOC_ASICMODE register bits */
+#define DOC_ASICMODE_RESET 0x00
+#define DOC_ASICMODE_NORMAL 0x01
+#define DOC_ASICMODE_POWERDOWN 0x02
+#define DOC_ASICMODE_MDWREN 0x04
+#define DOC_ASICMODE_BDETCT_RESET 0x08
+#define DOC_ASICMODE_RSTIN_RESET 0x10
+#define DOC_ASICMODE_RAM_WE 0x20
+
+/* good status values read after read/write/erase operations */
+#define DOCG4_PROGSTATUS_GOOD 0x51
+#define DOCG4_PROGSTATUS_GOOD_2 0xe0
+
+/*
+ * On read operations (page and oob-only), the first byte read from I/O reg is a
+ * status. On error, it reads 0x73; otherwise, it reads either 0x71 (first read
+ * after reset only) or 0x51, so bit 1 is presumed to be an error indicator.
+ */
+#define DOCG4_READ_ERROR 0x02 /* bit 1 indicates read error */
+
+/* anatomy of the device */
+#define DOCG4_CHIP_SIZE 0x8000000
+#define DOCG4_PAGE_SIZE 0x200
+#define DOCG4_PAGES_PER_BLOCK 0x200
+#define DOCG4_BLOCK_SIZE (DOCG4_PAGES_PER_BLOCK * DOCG4_PAGE_SIZE)
+#define DOCG4_NUMBLOCKS (DOCG4_CHIP_SIZE / DOCG4_BLOCK_SIZE)
+#define DOCG4_OOB_SIZE 0x10
+#define DOCG4_CHIP_SHIFT 27 /* log_2(DOCG4_CHIP_SIZE) */
+#define DOCG4_PAGE_SHIFT 9 /* log_2(DOCG4_PAGE_SIZE) */
+#define DOCG4_ERASE_SHIFT 18 /* log_2(DOCG4_BLOCK_SIZE) */
+
+/* all but the last byte is included in ecc calculation */
+#define DOCG4_BCH_SIZE (DOCG4_PAGE_SIZE + DOCG4_OOB_SIZE - 1)
+
+#define DOCG4_USERDATA_LEN 520 /* 512 byte page plus 8 oob avail to user */
+
+/* expected values from the ID registers */
+#define DOCG4_IDREG1_VALUE 0x0400
+#define DOCG4_IDREG2_VALUE 0xfbff
+
+/* primitive polynomial used to build the Galois field used by hw ecc gen */
+#define DOCG4_PRIMITIVE_POLY 0x4443
+
+#define DOCG4_M 14 /* Galois field is of order 2^14 */
+#define DOCG4_T 4 /* BCH alg corrects up to 4 bit errors */
+
+#define DOCG4_FACTORY_BBT_PAGE 16 /* page where read-only factory bbt lives */
+
+#endif /* __DOCG4_H__ */
#define PART_ACCESS_MASK (0x7)
#define PART_SUPPORT (0x1)
+/* Maximum block size for MMC */
+#define MMC_MAX_BLOCK_LEN 512
+
struct mmc_cid {
unsigned long psn;
unsigned short oid;
#endif
lbaint_t lba; /* number of blocks */
unsigned long blksz; /* block size */
+ int log2blksz; /* for convenience: log2(blksz) */
char vendor [40+1]; /* IDE model, SCSI Vendor */
char product[20+1]; /* IDE Serial no, SCSI product */
char revision[8+1]; /* firmware revision */
void *priv; /* driver private struct pointer */
}block_dev_desc_t;
+#define BLOCK_CNT(size, block_dev_desc) (PAD_COUNT(size, block_dev_desc->blksz))
+#define PAD_TO_BLOCKSIZE(size, block_dev_desc) \
+ (PAD_SIZE(size, block_dev_desc->blksz))
+#define LOG2(x) (((x & 0xaaaaaaaa) ? 1 : 0) + ((x & 0xcccccccc) ? 2 : 0) + \
+ ((x & 0xf0f0f0f0) ? 4 : 0) + ((x & 0xff00ff00) ? 8 : 0) + \
+ ((x & 0xffff0000) ? 16 : 0))
+#define LOG2_INVALID(type) ((type)((sizeof(type)<<3)-1))
+
/* Interface types: */
#define IF_TYPE_UNKNOWN 0
#define IF_TYPE_IDE 1
#define EFI_PMBR_OSTYPE_EFI 0xEF
#define EFI_PMBR_OSTYPE_EFI_GPT 0xEE
-#define GPT_BLOCK_SIZE 512
#define GPT_HEADER_SIGNATURE 0x5452415020494645ULL
#define GPT_HEADER_REVISION_V1 0x00010000
#define GPT_PRIMARY_PARTITION_TABLE_LBA 1ULL
__le32 num_partition_entries;
__le32 sizeof_partition_entry;
__le32 partition_entry_array_crc32;
- u8 reserved2[GPT_BLOCK_SIZE - 92];
} __packed gpt_header;
typedef union _gpt_entry_attributes {
void sandbox_fs_close(void);
int sandbox_fs_ls(const char *dirname);
int fs_read_sandbox(const char *filename, void *buf, int offset, int len);
+int fs_write_sandbox(const char *filename, void *buf, int offset, int len);
#endif
/*
* Based on code from uClibc-0.9.30.3
* Extensions for use within U-Boot
- * Copyright (C) 2010 Wolfgang Denk <wd@denx.de>
+ * Copyright (C) 2010-2013 Wolfgang Denk <wd@denx.de>
*/
#ifndef _SEARCH_H
*/
extern int hmatch_r(const char *__match, int __last_idx, ENTRY ** __retval,
struct hsearch_data *__htab);
-/*
- * Search for an entry whose key or data contains `MATCH'. Otherwise,
- * Same semantics as hsearch_r().
- */
-extern int hstrstr_r(const char *__match, int __last_idx, ENTRY ** __retval,
- struct hsearch_data *__htab);
/* Search and delete entry matching ITEM.key in internal hash table. */
extern int hdelete_r(const char *__key, struct hsearch_data *__htab,
#define H_FORCE (1 << 1) /* overwrite read-only/write-once variables */
#define H_INTERACTIVE (1 << 2) /* indicate that an import is user directed */
#define H_HIDE_DOT (1 << 3) /* don't print env vars that begin with '.' */
+#define H_MATCH_KEY (1 << 4) /* search/grep key = variable names */
+#define H_MATCH_DATA (1 << 5) /* search/grep data = variable values */
+#define H_MATCH_BOTH (H_MATCH_KEY | H_MATCH_DATA) /* search/grep both */
+#define H_MATCH_IDENT (1 << 6) /* search for indentical strings */
+#define H_MATCH_SUBSTR (1 << 7) /* search for substring matches */
+#define H_MATCH_REGEX (1 << 8) /* search for regular expression matches */
+#define H_MATCH_METHOD (H_MATCH_IDENT | H_MATCH_SUBSTR | H_MATCH_REGEX)
#endif /* search.h */
--- /dev/null
+/*
+ * Copyright (c) 2004-2005 Sergey Lyubka <valenok@gmail.com>
+ * All rights reserved
+ *
+ * "THE BEER-WARE LICENSE" (Revision 42):
+ * Sergey Lyubka wrote this file. As long as you retain this notice you
+ * can do whatever you want with this stuff. If we meet some day, and you think
+ * this stuff is worth it, you can buy me a beer in return.
+ */
+
+/*
+ * Downloaded Sat Nov 5 17:42:08 CET 2011 at
+ * http://slre.sourceforge.net/1.0/slre.h
+ */
+
+/*
+ * This is a regular expression library that implements a subset of Perl RE.
+ * Please refer to http://slre.sourceforge.net for detailed description.
+ *
+ * Usage example (parsing HTTP request):
+ *
+ * struct slre slre;
+ * struct cap captures[4 + 1]; // Number of braket pairs + 1
+ * ...
+ *
+ * slre_compile(&slre,"^(GET|POST) (\S+) HTTP/(\S+?)\r\n");
+ *
+ * if (slre_match(&slre, buf, len, captures)) {
+ * printf("Request line length: %d\n", captures[0].len);
+ * printf("Method: %.*s\n", captures[1].len, captures[1].ptr);
+ * printf("URI: %.*s\n", captures[2].len, captures[2].ptr);
+ * }
+ *
+ * Supported syntax:
+ * ^ Match beginning of a buffer
+ * $ Match end of a buffer
+ * () Grouping and substring capturing
+ * [...] Match any character from set
+ * [^...] Match any character but ones from set
+ * \s Match whitespace
+ * \S Match non-whitespace
+ * \d Match decimal digit
+ * \r Match carriage return
+ * \n Match newline
+ * + Match one or more times (greedy)
+ * +? Match one or more times (non-greedy)
+ * * Match zero or more times (greedy)
+ * *? Match zero or more times (non-greedy)
+ * ? Match zero or once
+ * \xDD Match byte with hex value 0xDD
+ * \meta Match one of the meta character: ^$().[*+?\
+ */
+
+#ifndef SLRE_HEADER_DEFINED
+#define SLRE_HEADER_DEFINED
+
+/*
+ * Compiled regular expression
+ */
+struct slre {
+ unsigned char code[256];
+ unsigned char data[256];
+ int code_size;
+ int data_size;
+ int num_caps; /* Number of bracket pairs */
+ int anchored; /* Must match from string start */
+ const char *err_str; /* Error string */
+};
+
+/*
+ * Captured substring
+ */
+struct cap {
+ const char *ptr; /* Pointer to the substring */
+ int len; /* Substring length */
+};
+
+/*
+ * Compile regular expression. If success, 1 is returned.
+ * If error, 0 is returned and slre.err_str points to the error message.
+ */
+int slre_compile(struct slre *, const char *re);
+
+/*
+ * Return 1 if match, 0 if no match.
+ * If `captured_substrings' array is not NULL, then it is filled with the
+ * values of captured substrings. captured_substrings[0] element is always
+ * a full matched substring. The round bracket captures start from
+ * captured_substrings[1].
+ * It is assumed that the size of captured_substrings array is enough to
+ * hold all captures. The caller function must make sure it is! So, the
+ * array_size = number_of_round_bracket_pairs + 1
+ */
+int slre_match(const struct slre *, const char *buf, int buf_len,
+ struct cap *captured_substrings);
+
+#ifdef SLRE_TEST
+void slre_dump(const struct slre *r, FILE *fp);
+#endif /* SLRE_TEST */
+#endif /* SLRE_HEADER_DEFINED */
/* Board-specific initialization */
int board_ehci_hcd_init(int port);
-/* CPU-specific abstracted-out IOMUX init */
-#ifdef CONFIG_MX51
-void setup_iomux_usb_h1(void);
-void setup_iomux_usb_h2(void);
-#endif
-
#endif /* _EHCI_FSL_H */
#ifndef _XILINX_H_
#define _XILINX_H_
-/* Xilinx Model definitions
- *********************************************************************/
-#define CONFIG_SYS_SPARTAN2 CONFIG_SYS_FPGA_DEV( 0x1 )
-#define CONFIG_SYS_VIRTEX_E CONFIG_SYS_FPGA_DEV( 0x2 )
-#define CONFIG_SYS_VIRTEX2 CONFIG_SYS_FPGA_DEV( 0x4 )
-#define CONFIG_SYS_SPARTAN3 CONFIG_SYS_FPGA_DEV( 0x8 )
-#define CONFIG_SYS_XILINX_SPARTAN2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN2)
-#define CONFIG_SYS_XILINX_VIRTEX_E (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX_E)
-#define CONFIG_SYS_XILINX_VIRTEX2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX2)
-#define CONFIG_SYS_XILINX_SPARTAN3 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN3)
-/* XXX - Add new models here */
-
-
-/* Xilinx Interface definitions
- *********************************************************************/
-#define CONFIG_SYS_XILINX_IF_SS CONFIG_SYS_FPGA_IF( 0x1 ) /* slave serial */
-#define CONFIG_SYS_XILINX_IF_MS CONFIG_SYS_FPGA_IF( 0x2 ) /* master serial */
-#define CONFIG_SYS_XILINX_IF_SP CONFIG_SYS_FPGA_IF( 0x4 ) /* slave parallel */
-#define CONFIG_SYS_XILINX_IF_JTAG CONFIG_SYS_FPGA_IF( 0x8 ) /* jtag */
-#define CONFIG_SYS_XILINX_IF_MSM CONFIG_SYS_FPGA_IF( 0x10 ) /* master selectmap */
-#define CONFIG_SYS_XILINX_IF_SSM CONFIG_SYS_FPGA_IF( 0x20 ) /* slave selectmap */
-
/* Xilinx types
*********************************************************************/
typedef enum { /* typedef Xilinx_iface */
jtag_mode, /* jtag/tap serial (not used ) */
master_selectmap, /* master SelectMap (virtex2) */
slave_selectmap, /* slave SelectMap (virtex2) */
+ devcfg, /* devcfg interface (zynq) */
max_xilinx_iface_type /* insert all new types before this */
} Xilinx_iface; /* end, typedef Xilinx_iface */
Xilinx_VirtexE, /* Virtex-E Family */
Xilinx_Virtex2, /* Virtex2 Family */
Xilinx_Spartan3, /* Spartan-III Family */
+ xilinx_zynq, /* Zynq Family */
max_xilinx_type /* insert all new types before this */
} Xilinx_Family; /* end, typedef Xilinx_Family */
size_t size; /* bytes of data part can accept */
void *iface_fns; /* interface function table */
int cookie; /* implementation specific cookie */
+ char *name; /* device name in bitstream */
} Xilinx_desc; /* end, typedef Xilinx_desc */
/* Generic Xilinx Functions
--- /dev/null
+/*
+ * (C) Copyright 2012-2013, Xilinx, Michal Simek
+ *
+ * (C) Copyright 2012
+ * Joe Hershberger <joe.hershberger@ni.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ZYNQPL_H_
+#define _ZYNQPL_H_
+
+#include <xilinx.h>
+
+extern int zynq_load(Xilinx_desc *desc, const void *image, size_t size);
+extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+extern int zynq_info(Xilinx_desc *desc);
+
+#define XILINX_ZYNQ_7010 0x2
+#define XILINX_ZYNQ_7020 0x7
+#define XILINX_ZYNQ_7030 0xc
+#define XILINX_ZYNQ_7045 0x11
+
+/* Device Image Sizes */
+#define XILINX_XC7Z010_SIZE 16669920/8
+#define XILINX_XC7Z020_SIZE 32364512/8
+#define XILINX_XC7Z030_SIZE 47839328/8
+#define XILINX_XC7Z045_SIZE 106571232/8
+
+/* Descriptor Macros */
+#define XILINX_XC7Z010_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" }
+
+#define XILINX_XC7Z020_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" }
+
+#define XILINX_XC7Z030_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, "7z030" }
+
+#define XILINX_XC7Z045_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" }
+
+#endif /* _ZYNQPL_H_ */
COBJS-y += strmhz.o
COBJS-$(CONFIG_TPM) += tpm.o
COBJS-$(CONFIG_RBTREE) += rbtree.o
+COBJS-$(CONFIG_BITREVERSE) += bitrev.o
endif
ifdef CONFIG_SPL_BUILD
COBJS-y += crc32.o
COBJS-y += ctype.o
COBJS-y += div64.o
+COBJS-y += hang.o
COBJS-y += linux_string.o
+COBJS-$(CONFIG_REGEX) += slre.o
COBJS-y += string.o
COBJS-y += time.o
COBJS-$(CONFIG_BOOTP_PXE) += uuid.o
--- /dev/null
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ * Based on bitrev from the Linux kernel, by Akinobu Mita
+ */
+
+
+#include <linux/types.h>
+#include <linux/bitrev.h>
+
+const u8 byte_rev_table[256] = {
+ 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
+ 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
+ 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
+ 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
+ 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
+ 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
+ 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
+ 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
+ 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
+ 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
+ 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
+ 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
+ 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
+ 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
+ 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
+ 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
+ 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
+ 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
+ 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
+ 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
+ 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
+ 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
+ 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
+ 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
+ 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
+ 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
+ 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
+ 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
+ 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
+ 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
+ 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
+ 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
+};
+
+u16 bitrev16(u16 x)
+{
+ return (bitrev8(x & 0xff) << 8) | bitrev8(x >> 8);
+}
+
+/**
+ * bitrev32 - reverse the order of bits in a u32 value
+ * @x: value to be bit-reversed
+ */
+u32 bitrev32(u32 x)
+{
+ return (bitrev16(x & 0xffff) << 16) | bitrev16(x >> 16);
+}
*/
int fdtdec_prepare_fdt(void)
{
- if (((uintptr_t)gd->fdt_blob & 3) || fdt_check_header(gd->fdt_blob)) {
+ if (!gd->fdt_blob || ((uintptr_t)gd->fdt_blob & 3) ||
+ fdt_check_header(gd->fdt_blob)) {
printf("No valid FDT found - please append one to U-Boot "
"binary, use u-boot-dtb.bin or define "
- "CONFIG_OF_EMBED\n");
+ "CONFIG_OF_EMBED. For sandbox, use -d <file.dtb>\n");
return -1;
}
return 0;
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * This file consolidates all the different hang() functions implemented in
+ * u-boot.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <bootstage.h>
+
+/**
+ * hang - stop processing by staying in an endless loop
+ *
+ * The purpose of this function is to stop further execution of code cause
+ * something went completely wrong. To catch this and give some feedback to
+ * the user one needs to catch the bootstage_error (see show_boot_progress())
+ * in the board code.
+ */
+void hang(void)
+{
+#if !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
+ defined(CONFIG_SPL_SERIAL_SUPPORT))
+ puts("### ERROR ### Please RESET the board ###\n");
+#endif
+ bootstage_error(BOOTSTAGE_ID_NEED_RESET);
+ for (;;)
+ ;
+}
* This implementation is based on code from uClibc-0.9.30.3 but was
* modified and extended for use within U-Boot.
*
- * Copyright (C) 2010 Wolfgang Denk <wd@denx.de>
+ * Copyright (C) 2010-2013 Wolfgang Denk <wd@denx.de>
*
* Original license header:
*
#include <env_callback.h>
#include <env_flags.h>
#include <search.h>
+#include <slre.h>
/*
* [Aho,Sethi,Ullman] Compilers: Principles, Techniques and Tools, 1986
* example for functions like hdelete().
*/
-/*
- * hstrstr_r - return index to entry whose key and/or data contains match
- */
-int hstrstr_r(const char *match, int last_idx, ENTRY ** retval,
- struct hsearch_data *htab)
-{
- unsigned int idx;
-
- for (idx = last_idx + 1; idx < htab->size; ++idx) {
- if (htab->table[idx].used <= 0)
- continue;
- if (strstr(htab->table[idx].entry.key, match) ||
- strstr(htab->table[idx].entry.data, match)) {
- *retval = &htab->table[idx].entry;
- return idx;
- }
- }
-
- __set_errno(ESRCH);
- *retval = NULL;
- return 0;
-}
-
int hmatch_r(const char *match, int last_idx, ENTRY ** retval,
struct hsearch_data *htab)
{
return (strcmp(e1->key, e2->key));
}
+static int match_string(int flag, const char *str, const char *pat, void *priv)
+{
+ switch (flag & H_MATCH_METHOD) {
+ case H_MATCH_IDENT:
+ if (strcmp(str, pat) == 0)
+ return 1;
+ break;
+ case H_MATCH_SUBSTR:
+ if (strstr(str, pat))
+ return 1;
+ break;
+#ifdef CONFIG_REGEX
+ case H_MATCH_REGEX:
+ {
+ struct slre *slrep = (struct slre *)priv;
+ struct cap caps[slrep->num_caps + 2];
+
+ if (slre_match(slrep, str, strlen(str), caps))
+ return 1;
+ }
+ break;
+#endif
+ default:
+ printf("## ERROR: unsupported match method: 0x%02x\n",
+ flag & H_MATCH_METHOD);
+ break;
+ }
+ return 0;
+}
+
+static int match_entry(ENTRY *ep, int flag,
+ int argc, char * const argv[])
+{
+ int arg;
+ void *priv = NULL;
+
+ for (arg = 1; arg < argc; ++arg) {
+#ifdef CONFIG_REGEX
+ struct slre slre;
+
+ if (slre_compile(&slre, argv[arg]) == 0) {
+ printf("Error compiling regex: %s\n", slre.err_str);
+ return 0;
+ }
+
+ priv = (void *)&slre;
+#endif
+ if (flag & H_MATCH_KEY) {
+ if (match_string(flag, ep->key, argv[arg], priv))
+ return 1;
+ }
+ if (flag & H_MATCH_DATA) {
+ if (match_string(flag, ep->data, argv[arg], priv))
+ return 1;
+ }
+ }
+ return 0;
+}
+
ssize_t hexport_r(struct hsearch_data *htab, const char sep, int flag,
char **resp, size_t size,
int argc, char * const argv[])
if (htab->table[i].used > 0) {
ENTRY *ep = &htab->table[i].entry;
- int arg, found = 0;
+ int found = match_entry(ep, flag, argc, argv);
- for (arg = 0; arg < argc; ++arg) {
- if (strcmp(argv[arg], ep->key) == 0) {
- found = 1;
- break;
- }
- }
if ((argc > 0) && (found == 0))
continue;
--- /dev/null
+/*
+ * Copyright (c) 2004-2005 Sergey Lyubka <valenok@gmail.com>
+ * All rights reserved
+ *
+ * "THE BEER-WARE LICENSE" (Revision 42):
+ * Sergey Lyubka wrote this file. As long as you retain this notice you
+ * can do whatever you want with this stuff. If we meet some day, and you think
+ * this stuff is worth it, you can buy me a beer in return.
+ */
+
+/*
+ * Downloaded Sat Nov 5 17:43:06 CET 2011 at
+ * http://slre.sourceforge.net/1.0/slre.c
+ */
+
+#ifdef SLRE_TEST
+#include <stdio.h>
+#include <assert.h>
+#include <ctype.h>
+#include <stdlib.h>
+#include <string.h>
+#else
+#include <common.h>
+#include <linux/ctype.h>
+#endif /* SLRE_TEST */
+
+#include <errno.h>
+
+#include <slre.h>
+
+enum {END, BRANCH, ANY, EXACT, ANYOF, ANYBUT, OPEN, CLOSE, BOL, EOL,
+ STAR, PLUS, STARQ, PLUSQ, QUEST, SPACE, NONSPACE, DIGIT};
+
+#ifdef SLRE_TEST
+static struct {
+ const char *name;
+ int narg;
+ const char *flags;
+} opcodes[] = {
+ {"END", 0, ""}, /* End of code block or program */
+ {"BRANCH", 2, "oo"}, /* Alternative operator, "|" */
+ {"ANY", 0, ""}, /* Match any character, "." */
+ {"EXACT", 2, "d"}, /* Match exact string */
+ {"ANYOF", 2, "D"}, /* Match any from set, "[]" */
+ {"ANYBUT", 2, "D"}, /* Match any but from set, "[^]"*/
+ {"OPEN ", 1, "i"}, /* Capture start, "(" */
+ {"CLOSE", 1, "i"}, /* Capture end, ")" */
+ {"BOL", 0, ""}, /* Beginning of string, "^" */
+ {"EOL", 0, ""}, /* End of string, "$" */
+ {"STAR", 1, "o"}, /* Match zero or more times "*" */
+ {"PLUS", 1, "o"}, /* Match one or more times, "+" */
+ {"STARQ", 1, "o"}, /* Non-greedy STAR, "*?" */
+ {"PLUSQ", 1, "o"}, /* Non-greedy PLUS, "+?" */
+ {"QUEST", 1, "o"}, /* Match zero or one time, "?" */
+ {"SPACE", 0, ""}, /* Match whitespace, "\s" */
+ {"NONSPACE", 0, ""}, /* Match non-space, "\S" */
+ {"DIGIT", 0, ""} /* Match digit, "\d" */
+};
+#endif /* SLRE_TEST */
+
+/*
+ * Commands and operands are all unsigned char (1 byte long). All code offsets
+ * are relative to current address, and positive (always point forward). Data
+ * offsets are absolute. Commands with operands:
+ *
+ * BRANCH offset1 offset2
+ * Try to match the code block that follows the BRANCH instruction
+ * (code block ends with END). If no match, try to match code block that
+ * starts at offset1. If either of these match, jump to offset2.
+ *
+ * EXACT data_offset data_length
+ * Try to match exact string. String is recorded in data section from
+ * data_offset, and has length data_length.
+ *
+ * OPEN capture_number
+ * CLOSE capture_number
+ * If the user have passed 'struct cap' array for captures, OPEN
+ * records the beginning of the matched substring (cap->ptr), CLOSE
+ * sets the length (cap->len) for respective capture_number.
+ *
+ * STAR code_offset
+ * PLUS code_offset
+ * QUEST code_offset
+ * *, +, ?, respectively. Try to gobble as much as possible from the
+ * matched buffer, until code block that follows these instructions
+ * matches. When the longest possible string is matched,
+ * jump to code_offset
+ *
+ * STARQ, PLUSQ are non-greedy versions of STAR and PLUS.
+ */
+
+static const char *meta_chars = "|.^$*+?()[\\";
+
+#ifdef SLRE_TEST
+
+static void
+print_character_set(FILE *fp, const unsigned char *p, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (i > 0)
+ (void) fputc(',', fp);
+ if (p[i] == 0) {
+ i++;
+ if (p[i] == 0)
+ (void) fprintf(fp, "\\x%02x", p[i]);
+ else
+ (void) fprintf(fp, "%s", opcodes[p[i]].name);
+ } else if (isprint(p[i])) {
+ (void) fputc(p[i], fp);
+ } else {
+ (void) fprintf(fp, "\\x%02x", p[i]);
+ }
+ }
+}
+
+void
+slre_dump(const struct slre *r, FILE *fp)
+{
+ int i, j, ch, op, pc;
+
+ for (pc = 0; pc < r->code_size; pc++) {
+
+ op = r->code[pc];
+ (void) fprintf(fp, "%3d %s ", pc, opcodes[op].name);
+
+ for (i = 0; opcodes[op].flags[i] != '\0'; i++)
+ switch (opcodes[op].flags[i]) {
+ case 'i':
+ (void) fprintf(fp, "%d ", r->code[pc + 1]);
+ pc++;
+ break;
+ case 'o':
+ (void) fprintf(fp, "%d ",
+ pc + r->code[pc + 1] - i);
+ pc++;
+ break;
+ case 'D':
+ print_character_set(fp, r->data +
+ r->code[pc + 1], r->code[pc + 2]);
+ pc += 2;
+ break;
+ case 'd':
+ (void) fputc('"', fp);
+ for (j = 0; j < r->code[pc + 2]; j++) {
+ ch = r->data[r->code[pc + 1] + j];
+ if (isprint(ch)) {
+ (void) fputc(ch, fp);
+ } else {
+ (void) fprintf(fp,
+ "\\x%02x", ch);
+ }
+ }
+ (void) fputc('"', fp);
+ pc += 2;
+ break;
+ }
+
+ (void) fputc('\n', fp);
+ }
+}
+#endif /* SLRE_TEST */
+
+static void
+set_jump_offset(struct slre *r, int pc, int offset)
+{
+ assert(offset < r->code_size);
+
+ if (r->code_size - offset > 0xff)
+ r->err_str = "Jump offset is too big";
+ else
+ r->code[pc] = (unsigned char) (r->code_size - offset);
+}
+
+static void
+emit(struct slre *r, int code)
+{
+ if (r->code_size >= (int) (sizeof(r->code) / sizeof(r->code[0])))
+ r->err_str = "RE is too long (code overflow)";
+ else
+ r->code[r->code_size++] = (unsigned char) code;
+}
+
+static void
+store_char_in_data(struct slre *r, int ch)
+{
+ if (r->data_size >= (int) sizeof(r->data))
+ r->err_str = "RE is too long (data overflow)";
+ else
+ r->data[r->data_size++] = ch;
+}
+
+static void
+exact(struct slre *r, const char **re)
+{
+ int old_data_size = r->data_size;
+
+ while (**re != '\0' && (strchr(meta_chars, **re)) == NULL)
+ store_char_in_data(r, *(*re)++);
+
+ emit(r, EXACT);
+ emit(r, old_data_size);
+ emit(r, r->data_size - old_data_size);
+}
+
+static int
+get_escape_char(const char **re)
+{
+ int res;
+
+ switch (*(*re)++) {
+ case 'n':
+ res = '\n';
+ break;
+ case 'r':
+ res = '\r';
+ break;
+ case 't':
+ res = '\t';
+ break;
+ case '0':
+ res = 0;
+ break;
+ case 'S':
+ res = NONSPACE << 8;
+ break;
+ case 's':
+ res = SPACE << 8;
+ break;
+ case 'd':
+ res = DIGIT << 8;
+ break;
+ default:
+ res = (*re)[-1];
+ break;
+ }
+
+ return res;
+}
+
+static void
+anyof(struct slre *r, const char **re)
+{
+ int esc, old_data_size = r->data_size, op = ANYOF;
+
+ if (**re == '^') {
+ op = ANYBUT;
+ (*re)++;
+ }
+
+ while (**re != '\0')
+
+ switch (*(*re)++) {
+ case ']':
+ emit(r, op);
+ emit(r, old_data_size);
+ emit(r, r->data_size - old_data_size);
+ return;
+ /* NOTREACHED */
+ break;
+ case '\\':
+ esc = get_escape_char(re);
+ if ((esc & 0xff) == 0) {
+ store_char_in_data(r, 0);
+ store_char_in_data(r, esc >> 8);
+ } else {
+ store_char_in_data(r, esc);
+ }
+ break;
+ default:
+ store_char_in_data(r, (*re)[-1]);
+ break;
+ }
+
+ r->err_str = "No closing ']' bracket";
+}
+
+static void
+relocate(struct slre *r, int begin, int shift)
+{
+ emit(r, END);
+ memmove(r->code + begin + shift, r->code + begin, r->code_size - begin);
+ r->code_size += shift;
+}
+
+static void
+quantifier(struct slre *r, int prev, int op)
+{
+ if (r->code[prev] == EXACT && r->code[prev + 2] > 1) {
+ r->code[prev + 2]--;
+ emit(r, EXACT);
+ emit(r, r->code[prev + 1] + r->code[prev + 2]);
+ emit(r, 1);
+ prev = r->code_size - 3;
+ }
+ relocate(r, prev, 2);
+ r->code[prev] = op;
+ set_jump_offset(r, prev + 1, prev);
+}
+
+static void
+exact_one_char(struct slre *r, int ch)
+{
+ emit(r, EXACT);
+ emit(r, r->data_size);
+ emit(r, 1);
+ store_char_in_data(r, ch);
+}
+
+static void
+fixup_branch(struct slre *r, int fixup)
+{
+ if (fixup > 0) {
+ emit(r, END);
+ set_jump_offset(r, fixup, fixup - 2);
+ }
+}
+
+static void
+compile(struct slre *r, const char **re)
+{
+ int op, esc, branch_start, last_op, fixup, cap_no, level;
+
+ fixup = 0;
+ level = r->num_caps;
+ branch_start = last_op = r->code_size;
+
+ for (;;)
+ switch (*(*re)++) {
+ case '\0':
+ (*re)--;
+ return;
+ /* NOTREACHED */
+ break;
+ case '^':
+ emit(r, BOL);
+ break;
+ case '$':
+ emit(r, EOL);
+ break;
+ case '.':
+ last_op = r->code_size;
+ emit(r, ANY);
+ break;
+ case '[':
+ last_op = r->code_size;
+ anyof(r, re);
+ break;
+ case '\\':
+ last_op = r->code_size;
+ esc = get_escape_char(re);
+ if (esc & 0xff00)
+ emit(r, esc >> 8);
+ else
+ exact_one_char(r, esc);
+ break;
+ case '(':
+ last_op = r->code_size;
+ cap_no = ++r->num_caps;
+ emit(r, OPEN);
+ emit(r, cap_no);
+
+ compile(r, re);
+ if (*(*re)++ != ')') {
+ r->err_str = "No closing bracket";
+ return;
+ }
+
+ emit(r, CLOSE);
+ emit(r, cap_no);
+ break;
+ case ')':
+ (*re)--;
+ fixup_branch(r, fixup);
+ if (level == 0) {
+ r->err_str = "Unbalanced brackets";
+ return;
+ }
+ return;
+ /* NOTREACHED */
+ break;
+ case '+':
+ case '*':
+ op = (*re)[-1] == '*' ? STAR : PLUS;
+ if (**re == '?') {
+ (*re)++;
+ op = op == STAR ? STARQ : PLUSQ;
+ }
+ quantifier(r, last_op, op);
+ break;
+ case '?':
+ quantifier(r, last_op, QUEST);
+ break;
+ case '|':
+ fixup_branch(r, fixup);
+ relocate(r, branch_start, 3);
+ r->code[branch_start] = BRANCH;
+ set_jump_offset(r, branch_start + 1, branch_start);
+ fixup = branch_start + 2;
+ r->code[fixup] = 0xff;
+ break;
+ default:
+ (*re)--;
+ last_op = r->code_size;
+ exact(r, re);
+ break;
+ }
+}
+
+int
+slre_compile(struct slre *r, const char *re)
+{
+ r->err_str = NULL;
+ r->code_size = r->data_size = r->num_caps = r->anchored = 0;
+
+ if (*re == '^')
+ r->anchored++;
+
+ emit(r, OPEN); /* This will capture what matches full RE */
+ emit(r, 0);
+
+ while (*re != '\0')
+ compile(r, &re);
+
+ if (r->code[2] == BRANCH)
+ fixup_branch(r, 4);
+
+ emit(r, CLOSE);
+ emit(r, 0);
+ emit(r, END);
+
+ return (r->err_str == NULL ? 1 : 0);
+}
+
+static int match(const struct slre *, int,
+ const char *, int, int *, struct cap *);
+
+static void
+loop_greedy(const struct slre *r, int pc, const char *s, int len, int *ofs)
+{
+ int saved_offset, matched_offset;
+
+ saved_offset = matched_offset = *ofs;
+
+ while (match(r, pc + 2, s, len, ofs, NULL)) {
+ saved_offset = *ofs;
+ if (match(r, pc + r->code[pc + 1], s, len, ofs, NULL))
+ matched_offset = saved_offset;
+ *ofs = saved_offset;
+ }
+
+ *ofs = matched_offset;
+}
+
+static void
+loop_non_greedy(const struct slre *r, int pc, const char *s, int len, int *ofs)
+{
+ int saved_offset = *ofs;
+
+ while (match(r, pc + 2, s, len, ofs, NULL)) {
+ saved_offset = *ofs;
+ if (match(r, pc + r->code[pc + 1], s, len, ofs, NULL))
+ break;
+ }
+
+ *ofs = saved_offset;
+}
+
+static int
+is_any_of(const unsigned char *p, int len, const char *s, int *ofs)
+{
+ int i, ch;
+
+ ch = s[*ofs];
+
+ for (i = 0; i < len; i++)
+ if (p[i] == ch) {
+ (*ofs)++;
+ return 1;
+ }
+
+ return 0;
+}
+
+static int
+is_any_but(const unsigned char *p, int len, const char *s, int *ofs)
+{
+ int i, ch;
+
+ ch = s[*ofs];
+
+ for (i = 0; i < len; i++) {
+ if (p[i] == ch)
+ return 0;
+ }
+
+ (*ofs)++;
+ return 1;
+}
+
+static int
+match(const struct slre *r, int pc, const char *s, int len,
+ int *ofs, struct cap *caps)
+{
+ int n, saved_offset, res = 1;
+
+ while (res && r->code[pc] != END) {
+
+ assert(pc < r->code_size);
+ assert(pc < (int) (sizeof(r->code) / sizeof(r->code[0])));
+
+ switch (r->code[pc]) {
+ case BRANCH:
+ saved_offset = *ofs;
+ res = match(r, pc + 3, s, len, ofs, caps);
+ if (res == 0) {
+ *ofs = saved_offset;
+ res = match(r, pc + r->code[pc + 1],
+ s, len, ofs, caps);
+ }
+ pc += r->code[pc + 2];
+ break;
+ case EXACT:
+ res = 0;
+ n = r->code[pc + 2]; /* String length */
+ if (n <= len - *ofs && !memcmp(s + *ofs, r->data +
+ r->code[pc + 1], n)) {
+ (*ofs) += n;
+ res = 1;
+ }
+ pc += 3;
+ break;
+ case QUEST:
+ res = 1;
+ saved_offset = *ofs;
+ if (!match(r, pc + 2, s, len, ofs, caps))
+ *ofs = saved_offset;
+ pc += r->code[pc + 1];
+ break;
+ case STAR:
+ res = 1;
+ loop_greedy(r, pc, s, len, ofs);
+ pc += r->code[pc + 1];
+ break;
+ case STARQ:
+ res = 1;
+ loop_non_greedy(r, pc, s, len, ofs);
+ pc += r->code[pc + 1];
+ break;
+ case PLUS:
+ res = match(r, pc + 2, s, len, ofs, caps);
+ if (res == 0)
+ break;
+
+ loop_greedy(r, pc, s, len, ofs);
+ pc += r->code[pc + 1];
+ break;
+ case PLUSQ:
+ res = match(r, pc + 2, s, len, ofs, caps);
+ if (res == 0)
+ break;
+
+ loop_non_greedy(r, pc, s, len, ofs);
+ pc += r->code[pc + 1];
+ break;
+ case SPACE:
+ res = 0;
+ if (*ofs < len && isspace(((unsigned char *)s)[*ofs])) {
+ (*ofs)++;
+ res = 1;
+ }
+ pc++;
+ break;
+ case NONSPACE:
+ res = 0;
+ if (*ofs < len &&
+ !isspace(((unsigned char *)s)[*ofs])) {
+ (*ofs)++;
+ res = 1;
+ }
+ pc++;
+ break;
+ case DIGIT:
+ res = 0;
+ if (*ofs < len && isdigit(((unsigned char *)s)[*ofs])) {
+ (*ofs)++;
+ res = 1;
+ }
+ pc++;
+ break;
+ case ANY:
+ res = 0;
+ if (*ofs < len) {
+ (*ofs)++;
+ res = 1;
+ }
+ pc++;
+ break;
+ case ANYOF:
+ res = 0;
+ if (*ofs < len)
+ res = is_any_of(r->data + r->code[pc + 1],
+ r->code[pc + 2], s, ofs);
+ pc += 3;
+ break;
+ case ANYBUT:
+ res = 0;
+ if (*ofs < len)
+ res = is_any_but(r->data + r->code[pc + 1],
+ r->code[pc + 2], s, ofs);
+ pc += 3;
+ break;
+ case BOL:
+ res = *ofs == 0 ? 1 : 0;
+ pc++;
+ break;
+ case EOL:
+ res = *ofs == len ? 1 : 0;
+ pc++;
+ break;
+ case OPEN:
+ if (caps != NULL)
+ caps[r->code[pc + 1]].ptr = s + *ofs;
+ pc += 2;
+ break;
+ case CLOSE:
+ if (caps != NULL)
+ caps[r->code[pc + 1]].len = (s + *ofs) -
+ caps[r->code[pc + 1]].ptr;
+ pc += 2;
+ break;
+ case END:
+ pc++;
+ break;
+ default:
+ printf("unknown cmd (%d) at %d\n", r->code[pc], pc);
+ assert(0);
+ break;
+ }
+ }
+
+ return res;
+}
+
+int
+slre_match(const struct slre *r, const char *buf, int len,
+ struct cap *caps)
+{
+ int i, ofs = 0, res = 0;
+
+ if (r->anchored) {
+ res = match(r, 0, buf, len, &ofs, caps);
+ } else {
+ for (i = 0; i < len && res == 0; i++) {
+ ofs = i;
+ res = match(r, 0, buf, len, &ofs, caps);
+ }
+ }
+
+ return res;
+}
+
+#ifdef SLRE_TEST
+#define N_CAPS 5
+
+int main(int argc, char *argv[])
+{
+ struct slre slre;
+ struct cap caps[N_CAPS];
+ unsigned char data[1 * 1024 * 1024];
+ FILE *fp;
+ int i, res, len;
+
+ if (argc < 2) {
+ fprintf(stderr, "Usage: %s 'slre' <file>\n", argv[0]);
+ return 1;
+ }
+
+ fp = fopen(argv[2], "rb");
+ if (fp == NULL) {
+ fprintf(stderr, "Error: cannot open %s:%s\n",
+ argv[2], strerror(errno));
+ return 1;
+ }
+
+ if (!slre_compile(&slre, argv[1])) {
+ fprintf(stderr, "Error compiling slre: %s\n", slre.err_str);
+ return 1;
+ }
+
+ slre_dump(&slre, stderr);
+
+ while (fgets(data, sizeof(data), fp) != NULL) {
+ len = strlen(data);
+
+ if ((len > 0) && (data[len-1] == '\n')) {
+ data[len-1] = '\0';
+ --len;
+ }
+
+ printf("Data = \"%s\"\n", data);
+
+ (void) memset(caps, 0, sizeof(caps));
+
+ res = 0;
+
+ res = slre_match(&slre, data, len, caps);
+ printf("Result [%d]: %d\n", i, res);
+
+ for (i = 0; i < N_CAPS; i++) {
+ if (caps[i].len > 0) {
+ printf("Substring %d: len=%d [%.*s]\n", i,
+ caps[i].len,
+ caps[i].len, caps[i].ptr);
+ }
+ }
+ printf("----------------------------------------------------\n");
+ }
+ (void) fclose(fp);
+
+ return 0;
+}
+#endif /* SLRE_TEST */
for (i = 0; i < sizeof(i2c_addr_list); ++i) {
if (i2c_addr_list[i] == 0xff)
continue;
+ if (i2c_ignore_device(i2c_addr_list[i]))
+ continue;
post_log("I2C: addr %02x did not respond\n", i2c_addr_list[i]);
ret = -1;
}
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
+endif
+
ifneq ($(CONFIG_TEGRA),)
LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
endif
+ifneq ($(CONFIG_MX23)$(CONFIG_MX35),)
+LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
+endif
+
# Add GCC lib
ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o
*/
static table_entry_t imximage_cmds[] = {
{CMD_BOOT_FROM, "BOOT_FROM", "boot command", },
+ {CMD_BOOT_OFFSET, "BOOT_OFFSET", "Boot offset", },
{CMD_DATA, "DATA", "Reg Write Data", },
{CMD_IMAGE_VERSION, "IMAGE_VERSION", "image version", },
{-1, "", "", },
if (unlikely(cmd_ver_first != 1))
cmd_ver_first = 0;
break;
+ case CMD_BOOT_OFFSET:
+ imxhdr->flash_offset = get_cfg_value(token, name, lineno);
+ if (unlikely(cmd_ver_first != 1))
+ cmd_ver_first = 0;
+ break;
case CMD_DATA:
value = get_cfg_value(token, name, lineno);
(*set_dcd_val)(imxhdr, name, lineno, fld, value, dcd_len);
/*
* ROM bug alert
- * mx53 only loads 512 byte multiples.
- * The remaining fraction of a block bytes would
- * not be loaded.
+ *
+ * MX53 only loads 512 byte multiples in case of SD boot.
+ * MX53 only loads NAND page multiples in case of NAND boot and
+ * supports up to 4096 byte large pages, thus align to 4096.
+ *
+ * The remaining fraction of a block bytes would not be loaded!
*/
- *header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 512);
+ *header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 4096);
}
int imximage_check_params(struct mkimage_params *params)
#define HEADER_OFFSET 0x400
+/*
+ * NOTE: This file must be kept in sync with arch/arm/include/asm/\
+ * imx-common/imximage.cfg because tools/imximage.c can not
+ * cross-include headers from arch/arm/ and vice-versa.
+ */
#define CMD_DATA_STR "DATA"
#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
#define FLASH_OFFSET_STANDARD 0x400
CMD_INVALID,
CMD_IMAGE_VERSION,
CMD_BOOT_FROM,
+ CMD_BOOT_OFFSET,
CMD_DATA
};
dcd_v2_t dcd_table;
} imx_header_v2_t;
+/* The header must be aligned to 4k on MX53 for NAND boot */
struct imx_header {
union {
imx_header_v1_t hdr_v1;
imx_header_v2_t hdr_v2;
} header;
uint32_t flash_offset;
-};
+} __attribute__((aligned(4096)));
typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
char *name, int lineno,
fsize = lseek(infd, 0, SEEK_END);
lseek(infd, 0, SEEK_SET);
- size = fsize + 512;
+ size = fsize + 4 * 512;
buf = malloc(size);
if (!buf) {
goto err0;
}
- ret = read(infd, (uint8_t *)buf + 512, fsize);
+ ret = read(infd, (uint8_t *)buf + 4 * 512, fsize);
if (ret != fsize) {
ret = -1;
goto err1;
cb->drv_info[0].chip_num = 0x0;
cb->drv_info[0].drive_type = 0x0;
cb->drv_info[0].tag = 0x1;
- cb->drv_info[0].first_sector_number = sd_sector + 1;
- cb->drv_info[0].sector_count = (size - 1) / 512;
+ cb->drv_info[0].first_sector_number = sd_sector + 4;
+ cb->drv_info[0].sector_count = (size - 4) / 512;
wr_size = write(outfd, buf, size);
if (wr_size != size) {
projects / karo-tx-uboot.git / commitdiff